From 376640c2d42b760f50c6c5a0ed909a1d6956e8d3 Mon Sep 17 00:00:00 2001 From: Your Name Date: Sun, 27 Jun 2021 09:18:53 +0200 Subject: [PATCH] initial --- ctdc_enc.v | 129 + endp_dummy.vhd | 83 - endp_handler.vhd | 72 - fifo32dc/fifo32dc.cst | 3 - fifo32dc/fifo32dc.edn | 3089 - fifo32dc/fifo32dc.fdc | 2 - fifo32dc/fifo32dc.lpc | 53 - fifo32dc/fifo32dc.sbx | 264 - fifo32dc/fifo32dc.srp | 40 - fifo32dc/fifo32dc.v | 1076 - fifo32dc/fifo32dc_generate.log | 49 - fifo32dc/fifo32dc_tmpl.v | 7 - fifo32dc/generate_core.tcl | 100 - fifo32dc/generate_ngd.tcl | 74 - fifo32dc/msg_file.log | 33 - fifo32dc/tb_fifo32dc_tmpl.v | 76 - fifo40_dc/fifo40_dc.cst | 3 - fifo40_dc/fifo40_dc.edn | 3245 - fifo40_dc/fifo40_dc.fdc | 2 - fifo40_dc/fifo40_dc.lpc | 53 - fifo40_dc/fifo40_dc.sbx | 264 - fifo40_dc/fifo40_dc.srp | 40 - fifo40_dc/fifo40_dc.v | 1114 - fifo40_dc/fifo40_dc_generate.log | 49 - fifo40_dc/fifo40_dc_tmpl.v | 7 - fifo40_dc/generate_core.tcl | 100 - fifo40_dc/generate_ngd.tcl | 74 - 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impl1/s1_impl1_synplify_tmp8.lpf | 0 impl1/s1_impl1_trce.asd | 23 - impl1/s1_impl1_tw1.html | 743 - impl1/s1_impl1_twr.html | 4240 - impl1/s1_impl1_vho.sdf | 26828 --- impl1/s1_impl1_vho.vho | 174140 --------------- impl1/s1_impl1_vo.sdf | 678 - impl1/s1_impl1_vo.vo | 207 - impl1/scratchproject.prs | 99 - impl1/stdout.log | 105 - impl1/stdout.log.bak | 105 - impl1/stdout.log.bak.1 | 105 - impl1/stdout.log.bak.2 | 105 - impl1/stdout.log.bak.3 | 105 - impl1/stdout.log.bak.4 | 105 - impl1/stdout.log.bak.5 | 105 - impl1/synlog.tcl | 1 - impl1/synlog/distcomp0.tlg.rptmap | 1 - impl1/synlog/distcomp1.tlg.rptmap | 1 - impl1/synlog/incr_compile.rpt.rptmap | 1 - impl1/synlog/linker.rpt.rptmap | 1 - impl1/synlog/report/metrics.db | Bin 40960 -> 0 bytes .../report/s1_impl1_compiler_errors.txt | 2 - .../synlog/report/s1_impl1_compiler_notes.txt | 34 - .../report/s1_impl1_compiler_runstatus.xml | 41 - .../report/s1_impl1_compiler_warnings.txt | 9 - .../s1_impl1_fpga_mapper_area_report.xml | 26 - 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top.v.bkp1 delete mode 100644 top2.v delete mode 100644 trb5_tb.vhd delete mode 100644 unrouted_tdc_out4.5_1.dly diff --git a/ctdc_enc.v b/ctdc_enc.v new file mode 100644 index 0000000..c94be35 --- /dev/null +++ b/ctdc_enc.v @@ -0,0 +1,129 @@ +module ctdc_enc_neg( + clk, + in, + in_valid, + out, + out_valid + ) /* synthesis syn_preserve= 1*/; + +input wire clk; +input wire [7:0]in; +input wire in_valid; +output reg [2:0]out /*synthesis syn_preserve=1*/; +output reg out_valid /*synthesis syn_preserve=1*/; + + + always @ (posedge clk)begin + if(in_valid)begin + case (in) + 8'b11111110 : begin + out <= 3'b000; + out_valid <= 1'b1; + end + 8'b11111100 : begin + out <= 3'b001; + out_valid <= 1'b1; + end + 8'b11111000 : begin + out <= 3'b010; + out_valid <= 1'b1; + end + 8'b11110000 : begin + out <= 3'b011; + out_valid <= 1'b1; + end + 8'b11100000 : begin + out <= 3'b100; + out_valid <= 1'b1; + end + 8'b11000000 : begin + out <= 3'b101; + out_valid <= 1'b1; + end + 8'b10000000 : begin + out <= 3'b110; + out_valid <= 1'b1; + end + 8'b00000000 : begin + out <= 3'b111; + out_valid <= 1'b1; + end + default : begin + out <=3'b000; + out_valid <= 1'b0; + end + endcase + end else begin + out <=3'b000; + out_valid <= 1'b0; + end + end + + +endmodule + +module ctdc_enc_pos( + clk, + in, + in_valid, + out, + out_valid + ) /* synthesis syn_preserve= 1*/; + +input wire clk; +input wire [7:0]in; +input wire in_valid; +output reg [2:0]out /*synthesis syn_preserve=1*/; +output reg out_valid /*synthesis syn_preserve=1*/; + + + always @ (posedge clk)begin + if(in_valid)begin + case (in) + //8'b11111110 : begin + ~8'b11111110 : begin + out <= 3'b000; + out_valid <= 1'b1; + end + ~8'b11111100 : begin + out <= 3'b001; + out_valid <= 1'b1; + end + ~8'b11111000 : begin + out <= 3'b010; + out_valid <= 1'b1; + end + ~8'b11110000 : begin + out <= 3'b011; + out_valid <= 1'b1; + end + ~8'b11100000 : begin + out <= 3'b100; + out_valid <= 1'b1; + end + ~8'b11000000 : begin + out <= 3'b101; + out_valid <= 1'b1; + end + ~8'b10000000 : begin + out <= 3'b110; + out_valid <= 1'b1; + end + ~8'b00000000 : begin + out <= 3'b111; + out_valid <= 1'b1; + end + default : begin + out <=3'b000; + out_valid <= 1'b0; + end + endcase + end else begin + out <=3'b000; + out_valid <= 1'b0; + end + end + + +endmodule + diff --git a/endp_dummy.vhd b/endp_dummy.vhd deleted file mode 100644 index a31ea22..0000000 --- a/endp_dummy.vhd +++ /dev/null @@ -1,83 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_unsigned.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.math_real.uniform; -use IEEE.math_real.floor; - -entity endp_dummy is -port ( - CLK : in std_logic; - RESET : in std_logic; - - TRG_TIMING_TRG_RECEIVED_IN : in std_logic; - - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_INVALID_TRG_IN : in std_logic; - - FEE_TRG_RELEASE_OUT : out std_logic; - FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATAFINISHED_OUT : out std_logic; - FEE_DATA_ALMOST_FULL_IN : in std_logic -); -end endp_dummy; - -architecture Behavioral of endp_dummy is - -begin - -process - variable s1, s2 : positive := 123; - variable x : real; - variable y : integer; - variable t : time; -begin - - FEE_DATA_OUT <= x"0000_0000"; - FEE_DATA_WRITE_OUT <= '0'; - FEE_TRG_RELEASE_OUT <= '0'; - FEE_DATAFINISHED_OUT <= '0'; - - wait until rising_edge(LVL1_TRG_DATA_VALID_IN); - - if (LVL1_INVALID_TRG_IN = '0') then - - uniform(s1, s2, x); - t := (x * 100.0 + 5.0) * (1 ns); - wait for t; - - uniform(s1, s2, x); - y := integer(floor(x * 100.0 + 1.0)); - - for i in 1 to y loop - wait until rising_edge(CLK); - FEE_DATA_OUT <= std_logic_vector(to_unsigned(i, 32)); - FEE_DATA_WRITE_OUT <= '1'; - end loop; - - wait until rising_edge(CLK); - FEE_DATA_OUT <= x"abcd_abcd"; - FEE_DATA_WRITE_OUT <= '1'; - FEE_DATAFINISHED_OUT <= '1'; - wait until rising_edge(CLK); - FEE_DATAFINISHED_OUT <= '0'; - FEE_DATA_WRITE_OUT <= '0'; - FEE_DATA_OUT <= x"0000_0000"; - - wait until rising_edge(CLK); - wait until rising_edge(CLK); - wait until rising_edge(CLK); - FEE_TRG_RELEASE_OUT <= '1'; - wait until rising_edge(CLK); - FEE_TRG_RELEASE_OUT <= '0'; - - - end if; - -end process; - - -end Behavioral; diff --git a/endp_handler.vhd b/endp_handler.vhd deleted file mode 100644 index e0b247e..0000000 --- a/endp_handler.vhd +++ /dev/null @@ -1,72 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_unsigned.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.math_real.uniform; -use IEEE.math_real.floor; - - - -entity endp_handler is -Port ( - CLK : in std_logic; - RESET : in std_logic; - - TRG_TIMING_TRG_RECEIVED_IN : in std_logic; - - LVL1_TRG_DATA_VALID_OUT : out std_logic; - LVL1_INVALID_TRG_OUT : out std_logic; - - FEE_TRG_RELEASE_IN : in std_logic; - FEE_TRG_STATUSBITS_IN : in std_logic_vector(31 downto 0); - FEE_DATA_IN : in std_logic_vector(31 downto 0); - FEE_DATA_WRITE_IN : in std_logic; - FEE_DATAFINISHED_IN : in std_logic; - FEE_DATA_ALMOST_FULL_OUT : out std_logic -); -end endp_handler; - -architecture Behavioral of endp_handler is - -begin - - -process - variable s1, s2 : positive := 123; - variable x : real; - variable y : integer; - variable y_slv : std_logic_vector(7 downto 0); -begin - - LVL1_TRG_DATA_VALID_OUT <= '0'; - LVL1_INVALID_TRG_OUT <= '0'; - - wait until rising_edge(TRG_TIMING_TRG_RECEIVED_IN); - - uniform(s1, s2, x); - y := integer(floor(x * 5.0 + 1.0)); - for i in 0 to y loop - wait until rising_edge(CLK); - end loop; - - - uniform(s1, s2, x); - y := integer(floor(x * 5.0 + 1.0)); - y_slv := std_logic_vector(to_unsigned(y, 8)); - - - wait until rising_edge(CLK); - LVL1_TRG_DATA_VALID_OUT <= '1'; - - if (y_slv(0) = '1') then - LVL1_INVALID_TRG_OUT <= '0'; - else - LVL1_INVALID_TRG_OUT <= '1'; - end if; - - wait until rising_edge(CLK); - -end process; - -end Behavioral; diff --git a/fifo32dc/fifo32dc.cst b/fifo32dc/fifo32dc.cst deleted file mode 100644 index 300db0f..0000000 --- a/fifo32dc/fifo32dc.cst +++ /dev/null @@ -1,3 +0,0 @@ -Date=09/13/2020 -Time=16:38:25 - diff --git a/fifo32dc/fifo32dc.edn b/fifo32dc/fifo32dc.edn deleted file mode 100644 index f97f809..0000000 --- a/fifo32dc/fifo32dc.edn +++ /dev/null @@ -1,3089 +0,0 @@ -(edif fifo32dc - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2020 9 13 16 38 29) - (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446")))) - (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell CCU2C - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A0 - (direction INPUT)) - (port A1 - (direction INPUT)) - (port B0 - (direction INPUT)) - (port B1 - (direction INPUT)) - (port C0 - (direction INPUT)) - (port C1 - (direction INPUT)) - (port D0 - (direction INPUT)) - (port D1 - (direction INPUT)) - (port CIN - (direction INPUT)) - (port S0 - (direction OUTPUT)) - (port S1 - (direction OUTPUT)) - (port COUT - (direction OUTPUT))))) - (cell AND2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell FD1P3BX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port SP - (direction INPUT)) - (port CK - (direction INPUT)) - (port PD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1P3DX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port SP - (direction INPUT)) - (port CK - (direction INPUT)) - (port CD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1S3BX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port CK - (direction INPUT)) - (port PD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1S3DX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port CK - (direction INPUT)) - (port CD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell INV - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell OR2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell ROM16X1A - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port AD3 - (direction INPUT)) - (port AD2 - (direction INPUT)) - (port AD1 - (direction INPUT)) - (port AD0 - (direction INPUT)) - (port DO0 - (direction OUTPUT))))) - (cell VHI - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell VLO - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell XOR2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell PDPW16KD - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port DI35 - (direction INPUT)) - (port DI34 - (direction INPUT)) - (port DI33 - (direction INPUT)) - (port DI32 - (direction INPUT)) - (port DI31 - (direction INPUT)) - (port DI30 - (direction INPUT)) - (port DI29 - (direction INPUT)) - (port DI28 - (direction INPUT)) - (port DI27 - (direction INPUT)) - (port DI26 - (direction INPUT)) - (port DI25 - (direction INPUT)) - (port DI24 - (direction INPUT)) - (port DI23 - (direction INPUT)) - (port DI22 - (direction INPUT)) - (port DI21 - (direction INPUT)) - (port DI20 - (direction INPUT)) - (port DI19 - (direction INPUT)) - (port DI18 - (direction INPUT)) - (port DI17 - (direction INPUT)) - (port DI16 - (direction INPUT)) - (port DI15 - (direction INPUT)) - (port DI14 - (direction INPUT)) - (port DI13 - (direction INPUT)) - (port DI12 - (direction INPUT)) - (port DI11 - (direction INPUT)) - (port DI10 - (direction INPUT)) - (port DI9 - (direction INPUT)) - (port DI8 - (direction INPUT)) - (port DI7 - (direction INPUT)) - (port DI6 - (direction INPUT)) - (port DI5 - (direction INPUT)) - (port DI4 - (direction INPUT)) - (port DI3 - (direction INPUT)) - (port DI2 - (direction INPUT)) - (port DI1 - (direction INPUT)) - (port DI0 - (direction INPUT)) - (port ADW8 - (direction INPUT)) - (port ADW7 - (direction INPUT)) - (port ADW6 - (direction INPUT)) - (port ADW5 - (direction INPUT)) - (port ADW4 - (direction INPUT)) - (port ADW3 - (direction INPUT)) - (port ADW2 - (direction INPUT)) - (port ADW1 - (direction INPUT)) - (port ADW0 - (direction INPUT)) - (port BE3 - (direction INPUT)) - (port BE2 - (direction INPUT)) - (port BE1 - (direction INPUT)) - (port BE0 - (direction INPUT)) - (port CEW - (direction INPUT)) - (port CLKW - (direction INPUT)) - (port CSW2 - (direction INPUT)) - (port CSW1 - (direction INPUT)) - (port CSW0 - (direction INPUT)) - (port ADR13 - (direction INPUT)) - (port ADR12 - (direction INPUT)) - (port ADR11 - (direction INPUT)) - (port ADR10 - (direction INPUT)) - (port ADR9 - (direction INPUT)) - (port ADR8 - (direction INPUT)) - (port ADR7 - (direction INPUT)) - (port ADR6 - (direction INPUT)) - (port ADR5 - (direction INPUT)) - (port ADR4 - (direction INPUT)) - (port ADR3 - (direction INPUT)) - (port ADR2 - (direction INPUT)) - (port ADR1 - (direction INPUT)) - (port ADR0 - (direction INPUT)) - (port CER - (direction INPUT)) - (port OCER - (direction INPUT)) - (port CLKR - (direction INPUT)) - (port CSR2 - (direction INPUT)) - (port CSR1 - (direction INPUT)) - (port CSR0 - (direction INPUT)) - (port RST - (direction INPUT)) - (port DO35 - (direction OUTPUT)) - (port DO34 - (direction OUTPUT)) - (port DO33 - (direction OUTPUT)) - (port DO32 - (direction OUTPUT)) - (port DO31 - (direction OUTPUT)) - (port DO30 - (direction OUTPUT)) - (port DO29 - (direction OUTPUT)) - (port DO28 - (direction OUTPUT)) - (port DO27 - (direction OUTPUT)) - (port DO26 - (direction OUTPUT)) - (port DO25 - (direction OUTPUT)) - (port DO24 - (direction OUTPUT)) - (port DO23 - (direction OUTPUT)) - (port DO22 - (direction OUTPUT)) - (port DO21 - (direction OUTPUT)) - (port DO20 - (direction OUTPUT)) - (port DO19 - (direction OUTPUT)) - (port DO18 - (direction OUTPUT)) - (port DO17 - (direction OUTPUT)) - (port DO16 - (direction OUTPUT)) - (port DO15 - (direction OUTPUT)) - (port DO14 - (direction OUTPUT)) - (port DO13 - (direction OUTPUT)) - (port DO12 - (direction OUTPUT)) - (port DO11 - (direction OUTPUT)) - (port DO10 - (direction OUTPUT)) - (port DO9 - (direction OUTPUT)) - (port DO8 - (direction OUTPUT)) - (port DO7 - (direction OUTPUT)) - (port DO6 - (direction OUTPUT)) - (port DO5 - (direction OUTPUT)) - (port DO4 - (direction OUTPUT)) - (port DO3 - (direction OUTPUT)) - (port DO2 - (direction OUTPUT)) - (port DO1 - (direction OUTPUT)) - (port DO0 - (direction OUTPUT))))) - (cell fifo32dc - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port (array (rename Data "Data(31:0)") 32) - (direction INPUT)) - (port WrClock - (direction INPUT)) - (port RdClock - (direction INPUT)) - (port WrEn - (direction INPUT)) - (port RdEn - (direction INPUT)) - (port Reset - (direction INPUT)) - (port RPReset - (direction INPUT)) - (port (array (rename Q "Q(31:0)") 32) - (direction OUTPUT)) - (port Empty - (direction OUTPUT)) - (port Full - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance AND2_t20 - (viewRef view1 - (cellRef AND2))) - (instance INV_1 - (viewRef view1 - (cellRef INV))) - (instance AND2_t19 - (viewRef view1 - (cellRef AND2))) - (instance INV_0 - (viewRef view1 - (cellRef INV))) - (instance OR2_t18 - (viewRef view1 - (cellRef OR2))) - (instance XOR2_t17 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t16 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t15 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t14 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t13 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t12 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t11 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t10 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t9 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t8 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t7 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t6 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t5 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t4 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t3 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t2 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t1 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t0 - (viewRef view1 - (cellRef XOR2))) - (instance LUT4_23 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_22 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_21 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_20 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_19 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_18 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_17 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_16 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_15 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_14 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_13 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_12 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_11 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_10 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_9 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_8 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_7 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_6 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_5 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_4 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_3 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x0410"))) - (instance LUT4_2 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x1004"))) - (instance LUT4_1 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x0140"))) - (instance LUT4_0 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x4001"))) - (instance pdp_ram_0_0_0 - (viewRef view1 - (cellRef PDPW16KD)) - (property INIT_DATA - (string "STATIC")) - (property ASYNC_RESET_RELEASE - (string "SYNC")) - (property MEM_LPC_FILE - (string "fifo32dc.lpc")) - (property MEM_INIT_FILE - (string "")) - (property CSDECODE_R - (string "0b000")) - (property CSDECODE_W - (string "0b001")) - (property GSR - (string "ENABLED")) - (property RESETMODE - (string "SYNC")) - (property REGMODE - (string "NOREG")) - (property DATA_WIDTH_R - (string "36")) - (property DATA_WIDTH_W - (string "36"))) - (instance FF_101 - (viewRef view1 - (cellRef FD1P3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_100 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_99 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_98 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_97 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_96 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_95 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_94 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_93 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_92 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_91 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_90 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_89 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_88 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_87 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_86 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_85 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_84 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_83 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_82 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_81 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_80 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_79 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_78 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_77 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_76 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_75 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_74 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_73 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_72 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_71 - (viewRef view1 - (cellRef FD1P3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_70 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_69 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_68 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_67 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_66 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_65 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_64 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_63 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_62 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_61 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_60 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_59 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_58 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_57 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_56 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_55 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_54 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_53 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_52 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_51 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_50 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_49 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_48 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_47 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_46 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_45 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_44 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_43 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_42 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_41 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_40 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_39 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_38 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_37 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_36 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_35 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_34 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_33 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_32 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_31 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_30 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_29 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_28 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_27 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_26 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_25 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_24 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_23 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_22 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_21 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_20 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_19 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_18 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_17 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_16 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_15 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_14 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_13 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_12 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_11 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_10 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_9 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_8 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_7 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_6 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_5 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_4 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_3 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_2 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_1 - (viewRef view1 - (cellRef FD1S3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_0 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance w_gctr_cia - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_cia - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance empty_cmp_ci_a - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance empty_cmp_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance a0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance full_cmp_ci_a - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance full_cmp_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance scuba_vhi_inst - (viewRef view1 - (cellRef VHI))) - (instance scuba_vlo_inst - (viewRef view1 - (cellRef VLO))) - (instance a1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (net invout_1 - (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)))) - (net invout_0 - (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)))) - (net w_g2b_xor_cluster_1 - (joined - (portRef AD2 (instanceRef LUT4_14)) - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_16)) - (portRef AD2 (instanceRef LUT4_15)))) - (net r_g2b_xor_cluster_1 - (joined - (portRef AD2 (instanceRef LUT4_4)) - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_6)) - (portRef AD2 (instanceRef LUT4_5)))) - (net w_gdata_0 - (joined - (portRef D (instanceRef FF_91)) - (portRef Z (instanceRef XOR2_t17)))) - (net w_gdata_1 - (joined - (portRef D (instanceRef FF_90)) - (portRef Z (instanceRef XOR2_t16)))) - (net w_gdata_2 - (joined - (portRef D (instanceRef FF_89)) - (portRef Z (instanceRef XOR2_t15)))) - (net w_gdata_3 - (joined - (portRef D (instanceRef FF_88)) - (portRef Z (instanceRef XOR2_t14)))) - (net w_gdata_4 - (joined - (portRef D (instanceRef FF_87)) - (portRef Z (instanceRef XOR2_t13)))) - (net w_gdata_5 - (joined - (portRef D (instanceRef FF_86)) - (portRef Z (instanceRef XOR2_t12)))) - (net w_gdata_6 - (joined - (portRef D (instanceRef FF_85)) - (portRef Z (instanceRef XOR2_t11)))) - (net w_gdata_7 - (joined - (portRef D (instanceRef FF_84)) - (portRef Z (instanceRef XOR2_t10)))) - (net w_gdata_8 - (joined - (portRef D (instanceRef FF_83)) - (portRef Z (instanceRef XOR2_t9)))) - (net wptr_0 - (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_0)))) - (net wptr_1 - (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_0)))) - (net wptr_2 - (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_0)))) - (net wptr_3 - (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_0)))) - (net wptr_4 - (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_0)))) - (net wptr_5 - (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_0)))) - (net wptr_6 - (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_0)))) - (net wptr_7 - (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_0)))) - (net wptr_8 - (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_0)))) - (net wptr_9 - (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_1)) - (portRef AD3 (instanceRef LUT4_0)))) - (net r_gdata_0 - (joined - (portRef D (instanceRef FF_61)) - (portRef Z (instanceRef XOR2_t8)))) - (net r_gdata_1 - (joined - (portRef D (instanceRef FF_60)) - (portRef Z (instanceRef XOR2_t7)))) - (net r_gdata_2 - (joined - (portRef D (instanceRef FF_59)) - (portRef Z (instanceRef XOR2_t6)))) - (net r_gdata_3 - (joined - (portRef D (instanceRef FF_58)) - (portRef Z (instanceRef XOR2_t5)))) - (net r_gdata_4 - (joined - (portRef D (instanceRef FF_57)) - (portRef Z (instanceRef XOR2_t4)))) - (net r_gdata_5 - (joined - (portRef D (instanceRef FF_56)) - (portRef Z (instanceRef XOR2_t3)))) - (net r_gdata_6 - (joined - (portRef D (instanceRef FF_55)) - (portRef Z (instanceRef XOR2_t2)))) - (net r_gdata_7 - (joined - (portRef D (instanceRef FF_54)) - (portRef Z (instanceRef XOR2_t1)))) - (net r_gdata_8 - (joined - (portRef D (instanceRef FF_53)) - (portRef Z (instanceRef XOR2_t0)))) - (net rptr_0 - (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_0)))) - (net rptr_1 - (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_0)))) - (net rptr_2 - (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_0)))) - (net rptr_3 - (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_0)))) - (net rptr_4 - (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_0)))) - (net rptr_5 - (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_0)))) - (net rptr_6 - (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_0)))) - (net rptr_7 - (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_0)))) - (net rptr_8 - (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_0)))) - (net rptr_9 - (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_3)) - (portRef AD3 (instanceRef LUT4_2)))) - (net w_gcount_0 - (joined - (portRef D (instanceRef FF_41)) - (portRef Q (instanceRef FF_91)))) - (net w_gcount_1 - (joined - (portRef D (instanceRef FF_40)) - (portRef Q (instanceRef FF_90)))) - (net w_gcount_2 - (joined - (portRef D (instanceRef FF_39)) - (portRef Q (instanceRef FF_89)))) - (net w_gcount_3 - (joined - (portRef D (instanceRef FF_38)) - (portRef Q (instanceRef FF_88)))) - (net w_gcount_4 - (joined - (portRef D (instanceRef FF_37)) - (portRef Q (instanceRef FF_87)))) - (net w_gcount_5 - (joined - (portRef D (instanceRef FF_36)) - (portRef Q (instanceRef FF_86)))) - (net w_gcount_6 - (joined - (portRef D (instanceRef FF_35)) - (portRef Q (instanceRef FF_85)))) - (net w_gcount_7 - (joined - (portRef D (instanceRef FF_34)) - (portRef Q (instanceRef FF_84)))) - (net w_gcount_8 - (joined - (portRef D (instanceRef FF_33)) - (portRef Q (instanceRef FF_83)))) - (net w_gcount_9 - (joined - (portRef D (instanceRef FF_32)) - (portRef Q (instanceRef FF_82)))) - (net r_gcount_0 - (joined - (portRef D (instanceRef FF_31)) - (portRef Q (instanceRef FF_61)))) - (net r_gcount_1 - (joined - (portRef D (instanceRef FF_30)) - (portRef Q (instanceRef FF_60)))) - (net r_gcount_2 - (joined - (portRef D (instanceRef FF_29)) - (portRef Q (instanceRef FF_59)))) - (net r_gcount_3 - (joined - (portRef D (instanceRef FF_28)) - (portRef Q (instanceRef FF_58)))) - (net r_gcount_4 - (joined - (portRef D (instanceRef FF_27)) - (portRef Q (instanceRef FF_57)))) - (net r_gcount_5 - (joined - (portRef D (instanceRef FF_26)) - (portRef Q (instanceRef FF_56)))) - (net r_gcount_6 - (joined - (portRef D (instanceRef FF_25)) - (portRef Q (instanceRef FF_55)))) - (net r_gcount_7 - (joined - (portRef D (instanceRef FF_24)) - (portRef Q (instanceRef FF_54)))) - (net r_gcount_8 - (joined - (portRef D (instanceRef FF_23)) - (portRef Q (instanceRef FF_53)))) - (net r_gcount_9 - (joined - (portRef D (instanceRef FF_22)) - (portRef Q (instanceRef FF_52)))) - (net w_gcount_r20 - (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)))) - (net w_gcount_r0 - (joined - (portRef D (instanceRef FF_21)) - (portRef Q (instanceRef FF_41)))) - (net w_gcount_r21 - (joined - (portRef Q (instanceRef FF_20)) - (portRef AD1 (instanceRef LUT4_15)) - (portRef AD0 (instanceRef LUT4_14)))) - (net w_gcount_r1 - (joined - (portRef D (instanceRef FF_20)) - (portRef Q (instanceRef FF_40)))) - (net w_gcount_r22 - (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)))) - (net w_gcount_r2 - (joined - (portRef D (instanceRef FF_19)) - (portRef Q (instanceRef FF_39)))) - (net w_gcount_r23 - (joined - (portRef Q (instanceRef FF_18)) - (portRef AD2 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_17)))) - (net w_gcount_r3 - (joined - (portRef D (instanceRef FF_18)) - (portRef Q (instanceRef FF_38)))) - (net w_gcount_r24 - (joined - (portRef Q (instanceRef FF_17)) - (portRef AD1 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_17)))) - (net w_gcount_r4 - (joined - (portRef D (instanceRef FF_17)) - (portRef Q (instanceRef FF_37)))) - (net w_gcount_r25 - (joined - (portRef Q (instanceRef FF_16)) - (portRef AD0 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_17)))) - (net w_gcount_r5 - (joined - (portRef D (instanceRef FF_16)) - (portRef Q (instanceRef FF_36)))) - (net w_gcount_r26 - (joined - (portRef Q (instanceRef FF_15)) - (portRef AD3 (instanceRef LUT4_23)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD1 (instanceRef LUT4_18)))) - (net w_gcount_r6 - (joined - (portRef D (instanceRef FF_15)) - (portRef Q (instanceRef FF_35)))) - (net w_gcount_r27 - (joined - (portRef Q (instanceRef FF_14)) - (portRef AD2 (instanceRef LUT4_23)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_19)))) - (net w_gcount_r7 - (joined - (portRef D (instanceRef FF_14)) - (portRef Q (instanceRef FF_34)))) - (net w_gcount_r28 - (joined - (portRef Q (instanceRef FF_13)) - (portRef AD1 (instanceRef LUT4_23)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD2 (instanceRef LUT4_20)))) - (net w_gcount_r8 - (joined - (portRef D (instanceRef FF_13)) - (portRef Q (instanceRef FF_33)))) - (net w_gcount_r29 - (joined - (portRef Q (instanceRef FF_12)) - (portRef AD0 (instanceRef LUT4_23)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_2)))) - (net w_gcount_r9 - (joined - (portRef D (instanceRef FF_12)) - (portRef Q (instanceRef FF_32)))) - (net r_gcount_w20 - (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)))) - (net r_gcount_w0 - (joined - (portRef D (instanceRef FF_11)) - (portRef Q (instanceRef FF_31)))) - (net r_gcount_w21 - (joined - (portRef Q (instanceRef FF_10)) - (portRef AD1 (instanceRef LUT4_5)) - (portRef AD0 (instanceRef LUT4_4)))) - (net r_gcount_w1 - (joined - (portRef D (instanceRef FF_10)) - (portRef Q (instanceRef FF_30)))) - (net r_gcount_w22 - (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)))) - (net r_gcount_w2 - (joined - (portRef D (instanceRef FF_9)) - (portRef Q (instanceRef FF_29)))) - (net r_gcount_w23 - (joined - (portRef Q (instanceRef FF_8)) - (portRef AD2 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_7)))) - (net r_gcount_w3 - (joined - (portRef D (instanceRef FF_8)) - (portRef Q (instanceRef FF_28)))) - (net r_gcount_w24 - (joined - (portRef Q (instanceRef FF_7)) - (portRef AD1 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_7)))) - (net r_gcount_w4 - (joined - (portRef D (instanceRef FF_7)) - (portRef Q (instanceRef FF_27)))) - (net r_gcount_w25 - (joined - (portRef Q (instanceRef FF_6)) - (portRef AD0 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_7)))) - (net r_gcount_w5 - (joined - (portRef D (instanceRef FF_6)) - (portRef Q (instanceRef FF_26)))) - (net r_gcount_w26 - (joined - (portRef Q (instanceRef FF_5)) - (portRef AD3 (instanceRef LUT4_13)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD1 (instanceRef LUT4_8)))) - (net r_gcount_w6 - (joined - (portRef D (instanceRef FF_5)) - (portRef Q (instanceRef FF_25)))) - (net r_gcount_w27 - (joined - (portRef Q (instanceRef FF_4)) - (portRef AD2 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_9)))) - (net r_gcount_w7 - (joined - (portRef D (instanceRef FF_4)) - (portRef Q (instanceRef FF_24)))) - (net r_gcount_w28 - (joined - (portRef Q (instanceRef FF_3)) - (portRef AD1 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD2 (instanceRef LUT4_10)))) - (net r_gcount_w8 - (joined - (portRef D (instanceRef FF_3)) - (portRef Q (instanceRef FF_23)))) - (net r_gcount_w29 - (joined - (portRef Q (instanceRef FF_2)) - (portRef AD0 (instanceRef LUT4_13)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_0)))) - (net r_gcount_w9 - (joined - (portRef D (instanceRef FF_2)) - (portRef Q (instanceRef FF_22)))) - (net rRst - (joined - (portRef PD (instanceRef FF_1)) - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_71)) - (portRef CD (instanceRef FF_70)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_2)))) - (net iwcount_0 - (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)))) - (net iwcount_1 - (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)))) - (net w_gctr_ci - (joined - (portRef CIN (instanceRef w_gctr_0)) - (portRef COUT (instanceRef w_gctr_cia)))) - (net iwcount_2 - (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)))) - (net iwcount_3 - (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)))) - (net co0 - (joined - (portRef CIN (instanceRef w_gctr_1)) - (portRef COUT (instanceRef w_gctr_0)))) - (net iwcount_4 - (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)))) - (net iwcount_5 - (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)))) - (net co1 - (joined - (portRef CIN (instanceRef w_gctr_2)) - (portRef COUT (instanceRef w_gctr_1)))) - (net iwcount_6 - (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)))) - (net iwcount_7 - (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)))) - (net co2 - (joined - (portRef CIN (instanceRef w_gctr_3)) - (portRef COUT (instanceRef w_gctr_2)))) - (net iwcount_8 - (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)))) - (net iwcount_9 - (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)))) - (net co4 - (joined - (portRef COUT (instanceRef w_gctr_4)))) - (net co3 - (joined - (portRef CIN (instanceRef w_gctr_4)) - (portRef COUT (instanceRef w_gctr_3)))) - (net wcount_9 - (joined - (portRef A1 (instanceRef w_gctr_4)) - (portRef B (instanceRef XOR2_t9)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef Q (instanceRef FF_92)) - (portRef D (instanceRef FF_82)) - (portRef D (instanceRef FF_72)))) - (net ircount_0 - (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)))) - (net ircount_1 - (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)))) - (net r_gctr_ci - (joined - (portRef CIN (instanceRef r_gctr_0)) - (portRef COUT (instanceRef r_gctr_cia)))) - (net ircount_2 - (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)))) - (net ircount_3 - (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)))) - (net co0_1 - (joined - (portRef CIN (instanceRef r_gctr_1)) - (portRef COUT (instanceRef r_gctr_0)))) - (net ircount_4 - (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)))) - (net ircount_5 - (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)))) - (net co1_1 - (joined - (portRef CIN (instanceRef r_gctr_2)) - (portRef COUT (instanceRef r_gctr_1)))) - (net ircount_6 - (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)))) - (net ircount_7 - (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)))) - (net co2_1 - (joined - (portRef CIN (instanceRef r_gctr_3)) - (portRef COUT (instanceRef r_gctr_2)))) - (net ircount_8 - (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)))) - (net ircount_9 - (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)))) - (net co4_1 - (joined - (portRef COUT (instanceRef r_gctr_4)))) - (net co3_1 - (joined - (portRef CIN (instanceRef r_gctr_4)) - (portRef COUT (instanceRef r_gctr_3)))) - (net rcount_9 - (joined - (portRef A1 (instanceRef r_gctr_4)) - (portRef B (instanceRef XOR2_t0)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef Q (instanceRef FF_62)) - (portRef D (instanceRef FF_52)) - (portRef D (instanceRef FF_42)))) - (net rden_i - (joined - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef Z (instanceRef AND2_t19)) - (portRef OCER (instanceRef pdp_ram_0_0_0)) - (portRef CER (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_71)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_42)) - (portRef B1 (instanceRef empty_cmp_ci_a)))) - (net cmp_ci - (joined - (portRef CIN (instanceRef empty_cmp_0)) - (portRef COUT (instanceRef empty_cmp_ci_a)))) - (net wcount_r0 - (joined - (portRef B0 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_14)))) - (net wcount_r1 - (joined - (portRef B1 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_15)))) - (net rcount_0 - (joined - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A (instanceRef XOR2_t8)) - (portRef Q (instanceRef FF_71)) - (portRef D (instanceRef FF_51)) - (portRef A0 (instanceRef r_gctr_0)))) - (net rcount_1 - (joined - (portRef A1 (instanceRef empty_cmp_0)) - (portRef B (instanceRef XOR2_t8)) - (portRef A (instanceRef XOR2_t7)) - (portRef Q (instanceRef FF_70)) - (portRef D (instanceRef FF_50)) - (portRef A1 (instanceRef r_gctr_0)))) - (net co0_2 - (joined - (portRef CIN (instanceRef empty_cmp_1)) - (portRef COUT (instanceRef empty_cmp_0)))) - (net wcount_r2 - (joined - (portRef B0 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_16)))) - (net wcount_r3 - (joined - (portRef B1 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_17)))) - (net rcount_2 - (joined - (portRef A0 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t7)) - (portRef A (instanceRef XOR2_t6)) - (portRef Q (instanceRef FF_69)) - (portRef D (instanceRef FF_49)) - (portRef A0 (instanceRef r_gctr_1)))) - (net rcount_3 - (joined - (portRef A1 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t6)) - (portRef A (instanceRef XOR2_t5)) - (portRef Q (instanceRef FF_68)) - (portRef D (instanceRef FF_48)) - (portRef A1 (instanceRef r_gctr_1)))) - (net co1_2 - (joined - (portRef CIN (instanceRef empty_cmp_2)) - (portRef COUT (instanceRef empty_cmp_1)))) - (net wcount_r4 - (joined - (portRef B0 (instanceRef empty_cmp_2)) - (portRef DO0 (instanceRef LUT4_18)))) - (net wcount_r5 - (joined - (portRef B1 (instanceRef empty_cmp_2)) - (portRef DO0 (instanceRef LUT4_19)))) - (net rcount_4 - (joined - (portRef A0 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t5)) - (portRef A (instanceRef XOR2_t4)) - (portRef Q (instanceRef FF_67)) - (portRef D (instanceRef FF_47)) - (portRef A0 (instanceRef r_gctr_2)))) - (net rcount_5 - (joined - (portRef A1 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t4)) - (portRef A (instanceRef XOR2_t3)) - (portRef Q (instanceRef FF_66)) - (portRef D (instanceRef FF_46)) - (portRef A1 (instanceRef r_gctr_2)))) - (net co2_2 - (joined - (portRef CIN (instanceRef empty_cmp_3)) - (portRef COUT (instanceRef empty_cmp_2)))) - (net w_g2b_xor_cluster_0 - (joined - (portRef B0 (instanceRef empty_cmp_3)) - (portRef DO0 (instanceRef LUT4_23)) - (portRef AD0 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_14)))) - (net wcount_r7 - (joined - (portRef B1 (instanceRef empty_cmp_3)) - (portRef DO0 (instanceRef LUT4_20)) - (portRef AD0 (instanceRef LUT4_18)))) - (net rcount_6 - (joined - (portRef A0 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t3)) - (portRef A (instanceRef XOR2_t2)) - (portRef Q (instanceRef FF_65)) - (portRef D (instanceRef FF_45)) - (portRef A0 (instanceRef r_gctr_3)))) - (net rcount_7 - (joined - (portRef A1 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t2)) - (portRef A (instanceRef XOR2_t1)) - (portRef Q (instanceRef FF_64)) - (portRef D (instanceRef FF_44)) - (portRef A1 (instanceRef r_gctr_3)))) - (net co3_2 - (joined - (portRef CIN (instanceRef empty_cmp_4)) - (portRef COUT (instanceRef empty_cmp_3)))) - (net wcount_r8 - (joined - (portRef B0 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_19)))) - (net empty_cmp_clr - (joined - (portRef B1 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_2)))) - (net rcount_8 - (joined - (portRef A0 (instanceRef empty_cmp_4)) - (portRef B (instanceRef XOR2_t1)) - (portRef A (instanceRef XOR2_t0)) - (portRef Q (instanceRef FF_63)) - (portRef D (instanceRef FF_43)) - (portRef A0 (instanceRef r_gctr_4)))) - (net empty_cmp_set - (joined - (portRef A1 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_3)))) - (net empty_d - (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)))) - (net empty_d_c - (joined - (portRef CIN (instanceRef a0)) - (portRef COUT (instanceRef empty_cmp_4)))) - (net wren_i - (joined - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef Z (instanceRef AND2_t20)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_101)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_72)) - (portRef B1 (instanceRef full_cmp_ci_a)))) - (net cmp_ci_1 - (joined - (portRef CIN (instanceRef full_cmp_0)) - (portRef COUT (instanceRef full_cmp_ci_a)))) - (net rcount_w0 - (joined - (portRef B0 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_4)))) - (net rcount_w1 - (joined - (portRef B1 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_5)))) - (net wcount_0 - (joined - (portRef A0 (instanceRef full_cmp_0)) - (portRef A (instanceRef XOR2_t17)) - (portRef Q (instanceRef FF_101)) - (portRef D (instanceRef FF_81)) - (portRef A0 (instanceRef w_gctr_0)))) - (net wcount_1 - (joined - (portRef A1 (instanceRef full_cmp_0)) - (portRef B (instanceRef XOR2_t17)) - (portRef A (instanceRef XOR2_t16)) - (portRef Q (instanceRef FF_100)) - (portRef D (instanceRef FF_80)) - (portRef A1 (instanceRef w_gctr_0)))) - (net co0_3 - (joined - (portRef CIN (instanceRef full_cmp_1)) - (portRef COUT (instanceRef full_cmp_0)))) - (net rcount_w2 - (joined - (portRef B0 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_6)))) - (net rcount_w3 - (joined - (portRef B1 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_7)))) - (net wcount_2 - (joined - (portRef A0 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t16)) - (portRef A (instanceRef XOR2_t15)) - (portRef Q (instanceRef FF_99)) - (portRef D (instanceRef FF_79)) - (portRef A0 (instanceRef w_gctr_1)))) - (net wcount_3 - (joined - (portRef A1 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t15)) - (portRef A (instanceRef XOR2_t14)) - (portRef Q (instanceRef FF_98)) - (portRef D (instanceRef FF_78)) - (portRef A1 (instanceRef w_gctr_1)))) - (net co1_3 - (joined - (portRef CIN (instanceRef full_cmp_2)) - (portRef COUT (instanceRef full_cmp_1)))) - (net rcount_w4 - (joined - (portRef B0 (instanceRef full_cmp_2)) - (portRef DO0 (instanceRef LUT4_8)))) - (net rcount_w5 - (joined - (portRef B1 (instanceRef full_cmp_2)) - (portRef DO0 (instanceRef LUT4_9)))) - (net wcount_4 - (joined - (portRef A0 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t14)) - (portRef A (instanceRef XOR2_t13)) - (portRef Q (instanceRef FF_97)) - (portRef D (instanceRef FF_77)) - (portRef A0 (instanceRef w_gctr_2)))) - (net wcount_5 - (joined - (portRef A1 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t13)) - (portRef A (instanceRef XOR2_t12)) - (portRef Q (instanceRef FF_96)) - (portRef D (instanceRef FF_76)) - (portRef A1 (instanceRef w_gctr_2)))) - (net co2_3 - (joined - (portRef CIN (instanceRef full_cmp_3)) - (portRef COUT (instanceRef full_cmp_2)))) - (net r_g2b_xor_cluster_0 - (joined - (portRef B0 (instanceRef full_cmp_3)) - (portRef DO0 (instanceRef LUT4_13)) - (portRef AD0 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_4)))) - (net rcount_w7 - (joined - (portRef B1 (instanceRef full_cmp_3)) - (portRef DO0 (instanceRef LUT4_10)) - (portRef AD0 (instanceRef LUT4_8)))) - (net wcount_6 - (joined - (portRef A0 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t12)) - (portRef A (instanceRef XOR2_t11)) - (portRef Q (instanceRef FF_95)) - (portRef D (instanceRef FF_75)) - (portRef A0 (instanceRef w_gctr_3)))) - (net wcount_7 - (joined - (portRef A1 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t11)) - (portRef A (instanceRef XOR2_t10)) - (portRef Q (instanceRef FF_94)) - (portRef D (instanceRef FF_74)) - (portRef A1 (instanceRef w_gctr_3)))) - (net co3_3 - (joined - (portRef CIN (instanceRef full_cmp_4)) - (portRef COUT (instanceRef full_cmp_3)))) - (net rcount_w8 - (joined - (portRef B0 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_9)))) - (net full_cmp_clr - (joined - (portRef B1 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_0)))) - (net wcount_8 - (joined - (portRef A0 (instanceRef full_cmp_4)) - (portRef B (instanceRef XOR2_t10)) - (portRef A (instanceRef XOR2_t9)) - (portRef Q (instanceRef FF_93)) - (portRef D (instanceRef FF_73)) - (portRef A0 (instanceRef w_gctr_4)))) - (net full_cmp_set - (joined - (portRef A1 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_1)))) - (net full_d - (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)))) - (net scuba_vhi - (joined - (portRef Z (instanceRef scuba_vhi_inst)) - (portRef CSW0 (instanceRef pdp_ram_0_0_0)) - (portRef BE3 (instanceRef pdp_ram_0_0_0)) - (portRef BE2 (instanceRef pdp_ram_0_0_0)) - (portRef BE1 (instanceRef pdp_ram_0_0_0)) - (portRef BE0 (instanceRef pdp_ram_0_0_0)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef a1)) - (portRef D0 (instanceRef a1)))) - (net scuba_vlo - (joined - (portRef Z (instanceRef scuba_vlo_inst)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef CSR2 (instanceRef pdp_ram_0_0_0)) - (portRef CSW2 (instanceRef pdp_ram_0_0_0)) - (portRef CSR1 (instanceRef pdp_ram_0_0_0)) - (portRef CSW1 (instanceRef pdp_ram_0_0_0)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef ADR4 (instanceRef pdp_ram_0_0_0)) - (portRef ADR3 (instanceRef pdp_ram_0_0_0)) - (portRef ADR2 (instanceRef pdp_ram_0_0_0)) - (portRef ADR1 (instanceRef pdp_ram_0_0_0)) - (portRef ADR0 (instanceRef pdp_ram_0_0_0)) - (portRef DI35 (instanceRef pdp_ram_0_0_0)) - (portRef DI34 (instanceRef pdp_ram_0_0_0)) - (portRef DI33 (instanceRef pdp_ram_0_0_0)) - (portRef DI32 (instanceRef pdp_ram_0_0_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef A0 (instanceRef a1)))) - (net full_d_c - (joined - (portRef CIN (instanceRef a1)) - (portRef COUT (instanceRef full_cmp_4)))) - (net Full - (joined - (portRef Full) - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)))) - (net Empty - (joined - (portRef Empty) - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)))) - (net dataout31 - (joined - (portRef (member Q 0)) - (portRef DO13 (instanceRef pdp_ram_0_0_0)))) - (net dataout30 - (joined - (portRef (member Q 1)) - (portRef DO12 (instanceRef pdp_ram_0_0_0)))) - (net dataout29 - (joined - (portRef (member Q 2)) - (portRef DO11 (instanceRef pdp_ram_0_0_0)))) - (net dataout28 - (joined - (portRef (member Q 3)) - (portRef DO10 (instanceRef pdp_ram_0_0_0)))) - (net dataout27 - (joined - (portRef (member Q 4)) - (portRef DO9 (instanceRef pdp_ram_0_0_0)))) - (net dataout26 - (joined - (portRef (member Q 5)) - (portRef DO8 (instanceRef pdp_ram_0_0_0)))) - (net dataout25 - (joined - (portRef (member Q 6)) - (portRef DO7 (instanceRef pdp_ram_0_0_0)))) - (net dataout24 - (joined - (portRef (member Q 7)) - (portRef DO6 (instanceRef pdp_ram_0_0_0)))) - (net dataout23 - (joined - (portRef (member Q 8)) - (portRef DO5 (instanceRef pdp_ram_0_0_0)))) - (net dataout22 - (joined - (portRef (member Q 9)) - (portRef DO4 (instanceRef pdp_ram_0_0_0)))) - (net dataout21 - (joined - (portRef (member Q 10)) - (portRef DO3 (instanceRef pdp_ram_0_0_0)))) - (net dataout20 - (joined - (portRef (member Q 11)) - (portRef DO2 (instanceRef pdp_ram_0_0_0)))) - (net dataout19 - (joined - (portRef (member Q 12)) - (portRef DO1 (instanceRef pdp_ram_0_0_0)))) - (net dataout18 - (joined - (portRef (member Q 13)) - (portRef DO0 (instanceRef pdp_ram_0_0_0)))) - (net dataout17 - (joined - (portRef (member Q 14)) - (portRef DO35 (instanceRef pdp_ram_0_0_0)))) - (net dataout16 - (joined - (portRef (member Q 15)) - (portRef DO34 (instanceRef pdp_ram_0_0_0)))) - (net dataout15 - (joined - (portRef (member Q 16)) - (portRef DO33 (instanceRef pdp_ram_0_0_0)))) - (net dataout14 - (joined - (portRef (member Q 17)) - (portRef DO32 (instanceRef pdp_ram_0_0_0)))) - (net dataout13 - (joined - (portRef (member Q 18)) - (portRef DO31 (instanceRef pdp_ram_0_0_0)))) - (net dataout12 - (joined - (portRef (member Q 19)) - (portRef DO30 (instanceRef pdp_ram_0_0_0)))) - (net dataout11 - (joined - (portRef (member Q 20)) - (portRef DO29 (instanceRef pdp_ram_0_0_0)))) - (net dataout10 - (joined - (portRef (member Q 21)) - (portRef DO28 (instanceRef pdp_ram_0_0_0)))) - (net dataout9 - (joined - (portRef (member Q 22)) - (portRef DO27 (instanceRef pdp_ram_0_0_0)))) - (net dataout8 - (joined - (portRef (member Q 23)) - (portRef DO26 (instanceRef pdp_ram_0_0_0)))) - (net dataout7 - (joined - (portRef (member Q 24)) - (portRef DO25 (instanceRef pdp_ram_0_0_0)))) - (net dataout6 - (joined - (portRef (member Q 25)) - (portRef DO24 (instanceRef pdp_ram_0_0_0)))) - (net dataout5 - (joined - (portRef (member Q 26)) - (portRef DO23 (instanceRef pdp_ram_0_0_0)))) - (net dataout4 - (joined - (portRef (member Q 27)) - (portRef DO22 (instanceRef pdp_ram_0_0_0)))) - (net dataout3 - (joined - (portRef (member Q 28)) - (portRef DO21 (instanceRef pdp_ram_0_0_0)))) - (net dataout2 - (joined - (portRef (member Q 29)) - (portRef DO20 (instanceRef pdp_ram_0_0_0)))) - (net dataout1 - (joined - (portRef (member Q 30)) - (portRef DO19 (instanceRef pdp_ram_0_0_0)))) - (net dataout0 - (joined - (portRef (member Q 31)) - (portRef DO18 (instanceRef pdp_ram_0_0_0)))) - (net RPRst - (joined - (portRef RPReset) - (portRef B (instanceRef OR2_t18)))) - (net reset - (joined - (portRef Reset) - (portRef A (instanceRef OR2_t18)) - (portRef RST (instanceRef pdp_ram_0_0_0)) - (portRef PD (instanceRef FF_101)) - (portRef CD (instanceRef FF_100)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_0)))) - (net rden - (joined - (portRef RdEn) - (portRef A (instanceRef AND2_t19)))) - (net wren - (joined - (portRef WrEn) - (portRef A (instanceRef AND2_t20)))) - (net rclk - (joined - (portRef RdClock) - (portRef CLKR (instanceRef pdp_ram_0_0_0)) - (portRef CK (instanceRef FF_71)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_1)))) - (net wclk - (joined - (portRef WrClock) - (portRef CLKW (instanceRef pdp_ram_0_0_0)) - (portRef CK (instanceRef FF_101)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_0)))) - (net datain31 - (joined - (portRef (member Data 0)) - (portRef DI31 (instanceRef pdp_ram_0_0_0)))) - (net datain30 - (joined - (portRef (member Data 1)) - (portRef DI30 (instanceRef pdp_ram_0_0_0)))) - (net datain29 - (joined - (portRef (member Data 2)) - (portRef DI29 (instanceRef pdp_ram_0_0_0)))) - (net datain28 - (joined - (portRef (member Data 3)) - (portRef DI28 (instanceRef pdp_ram_0_0_0)))) - (net datain27 - (joined - (portRef (member Data 4)) - (portRef DI27 (instanceRef pdp_ram_0_0_0)))) - (net datain26 - (joined - (portRef (member Data 5)) - (portRef DI26 (instanceRef pdp_ram_0_0_0)))) - (net datain25 - (joined - (portRef (member Data 6)) - (portRef DI25 (instanceRef pdp_ram_0_0_0)))) - (net datain24 - (joined - (portRef (member Data 7)) - (portRef DI24 (instanceRef pdp_ram_0_0_0)))) - (net datain23 - (joined - (portRef (member Data 8)) - (portRef DI23 (instanceRef pdp_ram_0_0_0)))) - (net datain22 - (joined - (portRef (member Data 9)) - (portRef DI22 (instanceRef pdp_ram_0_0_0)))) - (net datain21 - (joined - (portRef (member Data 10)) - (portRef DI21 (instanceRef pdp_ram_0_0_0)))) - (net datain20 - (joined - (portRef (member Data 11)) - (portRef DI20 (instanceRef pdp_ram_0_0_0)))) - (net datain19 - (joined - (portRef (member Data 12)) - (portRef DI19 (instanceRef pdp_ram_0_0_0)))) - (net datain18 - (joined - (portRef (member Data 13)) - (portRef DI18 (instanceRef pdp_ram_0_0_0)))) - (net datain17 - (joined - (portRef (member Data 14)) - (portRef DI17 (instanceRef pdp_ram_0_0_0)))) - (net datain16 - (joined - (portRef (member Data 15)) - (portRef DI16 (instanceRef pdp_ram_0_0_0)))) - (net datain15 - (joined - (portRef (member Data 16)) - (portRef DI15 (instanceRef pdp_ram_0_0_0)))) - (net datain14 - (joined - (portRef (member Data 17)) - (portRef DI14 (instanceRef pdp_ram_0_0_0)))) - (net datain13 - (joined - (portRef (member Data 18)) - (portRef DI13 (instanceRef pdp_ram_0_0_0)))) - (net datain12 - (joined - (portRef (member Data 19)) - (portRef DI12 (instanceRef pdp_ram_0_0_0)))) - (net datain11 - (joined - (portRef (member Data 20)) - (portRef DI11 (instanceRef pdp_ram_0_0_0)))) - (net datain10 - (joined - (portRef (member Data 21)) - (portRef DI10 (instanceRef pdp_ram_0_0_0)))) - (net datain9 - (joined - (portRef (member Data 22)) - (portRef DI9 (instanceRef pdp_ram_0_0_0)))) - (net datain8 - (joined - (portRef (member Data 23)) - (portRef DI8 (instanceRef pdp_ram_0_0_0)))) - (net datain7 - (joined - (portRef (member Data 24)) - (portRef DI7 (instanceRef pdp_ram_0_0_0)))) - (net datain6 - (joined - (portRef (member Data 25)) - (portRef DI6 (instanceRef pdp_ram_0_0_0)))) - (net datain5 - (joined - (portRef (member Data 26)) - (portRef DI5 (instanceRef pdp_ram_0_0_0)))) - (net datain4 - (joined - (portRef (member Data 27)) - (portRef DI4 (instanceRef pdp_ram_0_0_0)))) - (net datain3 - (joined - (portRef (member Data 28)) - (portRef DI3 (instanceRef pdp_ram_0_0_0)))) - (net datain2 - (joined - (portRef (member Data 29)) - (portRef DI2 (instanceRef pdp_ram_0_0_0)))) - (net datain1 - (joined - (portRef (member Data 30)) - (portRef DI1 (instanceRef pdp_ram_0_0_0)))) - (net datain0 - (joined - (portRef (member Data 31)) - (portRef DI0 (instanceRef pdp_ram_0_0_0)))))))) - (design fifo32dc - (cellRef fifo32dc - (libraryRef ORCLIB))) -) diff --git a/fifo32dc/fifo32dc.fdc b/fifo32dc/fifo32dc.fdc deleted file mode 100644 index 6fbcac9..0000000 --- a/fifo32dc/fifo32dc.fdc +++ /dev/null @@ -1,2 +0,0 @@ -###==== Start Configuration - diff --git a/fifo32dc/fifo32dc.lpc b/fifo32dc/fifo32dc.lpc deleted file mode 100644 index 7709870..0000000 --- a/fifo32dc/fifo32dc.lpc +++ /dev/null @@ -1,53 +0,0 @@ -[Device] -Family=ecp5um5g -PartType=LFE5UM5G-45F -PartName=LFE5UM5G-45F-8BG381C -SpeedGrade=8 -Package=CABGA381 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.8 -ModuleName=fifo32dc -SourceFormat=verilog -ParameterFileVersion=1.0 -Date=09/13/2020 -Time=16:38:25 - -[Parameters] -Verilog=1 -VHDL=0 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=32 -RDepth=512 -RWidth=32 -regout=0 -ClockEn=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -Reset=Sync -Reset1=Sync -RDataCount=0 -WDataCount=0 -EnECC=0 - -[Command] -cmd_line= -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 diff --git a/fifo32dc/fifo32dc.sbx b/fifo32dc/fifo32dc.sbx deleted file mode 100644 index 87557c3..0000000 --- a/fifo32dc/fifo32dc.sbx +++ /dev/null @@ -1,264 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - FIFO_DC - 5.8 - - - Diamond_Simulation - simulation - - ./fifo32dc.v - verilogSource - - - - Diamond_Synthesis - synthesis - - ./fifo32dc.v - verilogSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - - - - - - LFE5UM5G-45F-8BG381C - synplify - 2020-09-13.04:38:29 PM - 2020-09-13.04:38:29 PM - 3.11.2.446 - Verilog - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um5g - - - OperatingCondition - COM - - - Package - CABGA381 - - - PartName - LFE5UM5G-45F-8BG381C - - - PartType - LFE5UM5G-45F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - FIFO_DC - - - CoreRevision - 5.8 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 09/13/2020 - - - ModuleName - fifo32dc - - - ParameterFileVersion - 1.0 - - - SourceFormat - verilog - - - Time - 16:38:25 - - - VendorName - Lattice Semiconductor Corporation - - - - ClockEn - 0 - - - CtrlByRdEn - 0 - - - Depth - 512 - - - Destination - Synplicity - - - EDIF - 1 - - - EmpFlg - 0 - - - EnECC - 0 - - - Expression - BusA(0 to 7) - - - FIFOImp - EBR Based - - - FullFlg - 0 - - - IO - 0 - - - Order - Big Endian [MSB:LSB] - - - PeAssert - 10 - - - PeDeassert - 12 - - - PeMode - Static - Dual Threshold - - - PfAssert - 508 - - - PfDeassert - 506 - - - PfMode - Static - Dual Threshold - - - RDataCount - 0 - - - RDepth - 512 - - - RWidth - 32 - - - Reset - Sync - - - Reset1 - Sync - - - VHDL - 0 - - - Verilog - 1 - - - WDataCount - 0 - - - Width - 32 - - - regout - 0 - - - - cmd_line - -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 - - - - - - - LATTICE - LOCAL - fifo32dc - 1.0 - - - - diff --git a/fifo32dc/fifo32dc.srp b/fifo32dc/fifo32dc.srp deleted file mode 100644 index 80bffa7..0000000 --- a/fifo32dc/fifo32dc.srp +++ /dev/null @@ -1,40 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Sun Sep 13 16:38:29 2020 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc - Circuit name : fifo32dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo32dc.edn - Verilog output : fifo32dc.v - Verilog template : fifo32dc_tmpl.v - Verilog testbench: tb_fifo32dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo32dc.srp - Element Usage : - CCU2C : 26 - AND2 : 2 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1A : 24 - XOR2 : 18 - PDPW16KD : 1 - Estimated Resource Usage: - LUT : 97 - EBR : 1 - Reg : 102 diff --git a/fifo32dc/fifo32dc.v b/fifo32dc/fifo32dc.v deleted file mode 100644 index 29bc35c..0000000 --- a/fifo32dc/fifo32dc.v +++ /dev/null @@ -1,1076 +0,0 @@ -/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */ -/* Module Version: 5.8 */ -/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.fdc */ -/* Sun Sep 13 16:38:29 2020 */ - - -`timescale 1 ns / 1 ps -module fifo32dc (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, - Empty, Full)/* synthesis NGD_DRC_MASK=1 */; - input wire [31:0] Data; - input wire WrClock; - input wire RdClock; - input wire WrEn; - input wire RdEn; - input wire Reset; - input wire RPReset; - output wire [31:0] Q; - output wire Empty; - output wire Full; - - wire invout_1; - wire invout_0; - wire w_g2b_xor_cluster_1; - wire r_g2b_xor_cluster_1; - wire w_gdata_0; - wire w_gdata_1; - wire w_gdata_2; - wire w_gdata_3; - wire w_gdata_4; - wire w_gdata_5; - wire w_gdata_6; - wire w_gdata_7; - wire w_gdata_8; - wire wptr_0; - wire wptr_1; - wire wptr_2; - wire wptr_3; - wire wptr_4; - wire wptr_5; - wire wptr_6; - wire wptr_7; - wire wptr_8; - wire wptr_9; - wire r_gdata_0; - wire r_gdata_1; - wire r_gdata_2; - wire r_gdata_3; - wire r_gdata_4; - wire r_gdata_5; - wire r_gdata_6; - wire r_gdata_7; - wire r_gdata_8; - wire rptr_0; - wire rptr_1; - wire rptr_2; - wire rptr_3; - wire rptr_4; - wire rptr_5; - wire rptr_6; - wire rptr_7; - wire rptr_8; - wire rptr_9; - wire w_gcount_0; - wire w_gcount_1; - wire w_gcount_2; - wire w_gcount_3; - wire w_gcount_4; - wire w_gcount_5; - wire w_gcount_6; - wire w_gcount_7; - wire w_gcount_8; - wire w_gcount_9; - wire r_gcount_0; - wire r_gcount_1; - wire r_gcount_2; - wire r_gcount_3; - wire r_gcount_4; - wire r_gcount_5; - wire r_gcount_6; - wire r_gcount_7; - wire r_gcount_8; - wire r_gcount_9; - wire w_gcount_r20; - wire w_gcount_r0; - wire w_gcount_r21; - wire w_gcount_r1; - wire w_gcount_r22; - wire w_gcount_r2; - wire w_gcount_r23; - wire w_gcount_r3; - wire w_gcount_r24; - wire w_gcount_r4; - wire w_gcount_r25; - wire w_gcount_r5; - wire w_gcount_r26; - wire w_gcount_r6; - wire w_gcount_r27; - wire w_gcount_r7; - wire w_gcount_r28; - wire w_gcount_r8; - wire w_gcount_r29; - wire w_gcount_r9; - wire r_gcount_w20; - wire r_gcount_w0; - wire r_gcount_w21; - wire r_gcount_w1; - wire r_gcount_w22; - wire r_gcount_w2; - wire r_gcount_w23; - wire r_gcount_w3; - wire r_gcount_w24; - wire r_gcount_w4; - wire r_gcount_w25; - wire r_gcount_w5; - wire r_gcount_w26; - wire r_gcount_w6; - wire r_gcount_w27; - wire r_gcount_w7; - wire r_gcount_w28; - wire r_gcount_w8; - wire r_gcount_w29; - wire r_gcount_w9; - wire empty_i; - wire rRst; - wire full_i; - wire iwcount_0; - wire iwcount_1; - wire w_gctr_ci; - wire iwcount_2; - wire iwcount_3; - wire co0; - wire iwcount_4; - wire iwcount_5; - wire co1; - wire iwcount_6; - wire iwcount_7; - wire co2; - wire iwcount_8; - wire iwcount_9; - wire co4; - wire co3; - wire wcount_9; - wire ircount_0; - wire ircount_1; - wire r_gctr_ci; - wire ircount_2; - wire ircount_3; - wire co0_1; - wire ircount_4; - wire ircount_5; - wire co1_1; - wire ircount_6; - wire ircount_7; - wire co2_1; - wire ircount_8; - wire ircount_9; - wire co4_1; - wire co3_1; - wire rcount_9; - wire rden_i; - wire cmp_ci; - wire wcount_r0; - wire wcount_r1; - wire rcount_0; - wire rcount_1; - wire co0_2; - wire wcount_r2; - wire wcount_r3; - wire rcount_2; - wire rcount_3; - wire co1_2; - wire wcount_r4; - wire wcount_r5; - wire rcount_4; - wire rcount_5; - wire co2_2; - wire w_g2b_xor_cluster_0; - wire wcount_r7; - wire rcount_6; - wire rcount_7; - wire co3_2; - wire wcount_r8; - wire empty_cmp_clr; - wire rcount_8; - wire empty_cmp_set; - wire empty_d; - wire empty_d_c; - wire wren_i; - wire cmp_ci_1; - wire rcount_w0; - wire rcount_w1; - wire wcount_0; - wire wcount_1; - wire co0_3; - wire rcount_w2; - wire rcount_w3; - wire wcount_2; - wire wcount_3; - wire co1_3; - wire rcount_w4; - wire rcount_w5; - wire wcount_4; - wire wcount_5; - wire co2_3; - wire r_g2b_xor_cluster_0; - wire rcount_w7; - wire wcount_6; - wire wcount_7; - wire co3_3; - wire rcount_w8; - wire full_cmp_clr; - wire wcount_8; - wire full_cmp_set; - wire full_d; - wire scuba_vhi; - wire scuba_vlo; - wire full_d_c; - - AND2 AND2_t20 (.A(WrEn), .B(invout_1), .Z(wren_i)); - - INV INV_1 (.A(full_i), .Z(invout_1)); - - AND2 AND2_t19 (.A(RdEn), .B(invout_0), .Z(rden_i)); - - INV INV_0 (.A(empty_i), .Z(invout_0)); - - OR2 OR2_t18 (.A(Reset), .B(RPReset), .Z(rRst)); - - XOR2 XOR2_t17 (.A(wcount_0), .B(wcount_1), .Z(w_gdata_0)); - - XOR2 XOR2_t16 (.A(wcount_1), .B(wcount_2), .Z(w_gdata_1)); - - XOR2 XOR2_t15 (.A(wcount_2), .B(wcount_3), .Z(w_gdata_2)); - - XOR2 XOR2_t14 (.A(wcount_3), .B(wcount_4), .Z(w_gdata_3)); - - XOR2 XOR2_t13 (.A(wcount_4), .B(wcount_5), .Z(w_gdata_4)); - - XOR2 XOR2_t12 (.A(wcount_5), .B(wcount_6), .Z(w_gdata_5)); - - XOR2 XOR2_t11 (.A(wcount_6), .B(wcount_7), .Z(w_gdata_6)); - - XOR2 XOR2_t10 (.A(wcount_7), .B(wcount_8), .Z(w_gdata_7)); - - XOR2 XOR2_t9 (.A(wcount_8), .B(wcount_9), .Z(w_gdata_8)); - - XOR2 XOR2_t8 (.A(rcount_0), .B(rcount_1), .Z(r_gdata_0)); - - XOR2 XOR2_t7 (.A(rcount_1), .B(rcount_2), .Z(r_gdata_1)); - - XOR2 XOR2_t6 (.A(rcount_2), .B(rcount_3), .Z(r_gdata_2)); - - XOR2 XOR2_t5 (.A(rcount_3), .B(rcount_4), .Z(r_gdata_3)); - - XOR2 XOR2_t4 (.A(rcount_4), .B(rcount_5), .Z(r_gdata_4)); - - XOR2 XOR2_t3 (.A(rcount_5), .B(rcount_6), .Z(r_gdata_5)); - - XOR2 XOR2_t2 (.A(rcount_6), .B(rcount_7), .Z(r_gdata_6)); - - XOR2 XOR2_t1 (.A(rcount_7), .B(rcount_8), .Z(r_gdata_7)); - - XOR2 XOR2_t0 (.A(rcount_8), .B(rcount_9), .Z(r_gdata_8)); - - defparam LUT4_23.initval = 16'h6996 ; - ROM16X1A LUT4_23 (.AD3(w_gcount_r26), .AD2(w_gcount_r27), .AD1(w_gcount_r28), - .AD0(w_gcount_r29), .DO0(w_g2b_xor_cluster_0)); - - defparam LUT4_22.initval = 16'h6996 ; - ROM16X1A LUT4_22 (.AD3(w_gcount_r22), .AD2(w_gcount_r23), .AD1(w_gcount_r24), - .AD0(w_gcount_r25), .DO0(w_g2b_xor_cluster_1)); - - defparam LUT4_21.initval = 16'h6996 ; - ROM16X1A LUT4_21 (.AD3(w_gcount_r28), .AD2(w_gcount_r29), .AD1(scuba_vlo), - .AD0(scuba_vlo), .DO0(wcount_r8)); - - defparam LUT4_20.initval = 16'h6996 ; - ROM16X1A LUT4_20 (.AD3(w_gcount_r27), .AD2(w_gcount_r28), .AD1(w_gcount_r29), - .AD0(scuba_vlo), .DO0(wcount_r7)); - - defparam LUT4_19.initval = 16'h6996 ; - ROM16X1A LUT4_19 (.AD3(w_gcount_r25), .AD2(w_gcount_r26), .AD1(w_gcount_r27), - .AD0(wcount_r8), .DO0(wcount_r5)); - - defparam LUT4_18.initval = 16'h6996 ; - ROM16X1A LUT4_18 (.AD3(w_gcount_r24), .AD2(w_gcount_r25), .AD1(w_gcount_r26), - .AD0(wcount_r7), .DO0(wcount_r4)); - - defparam LUT4_17.initval = 16'h6996 ; - ROM16X1A LUT4_17 (.AD3(w_gcount_r23), .AD2(w_gcount_r24), .AD1(w_gcount_r25), - .AD0(w_g2b_xor_cluster_0), .DO0(wcount_r3)); - - defparam LUT4_16.initval = 16'h6996 ; - ROM16X1A LUT4_16 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(wcount_r2)); - - defparam LUT4_15.initval = 16'h6996 ; - ROM16X1A LUT4_15 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(w_gcount_r21), .AD0(scuba_vlo), .DO0(wcount_r1)); - - defparam LUT4_14.initval = 16'h6996 ; - ROM16X1A LUT4_14 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(w_gcount_r20), .AD0(w_gcount_r21), .DO0(wcount_r0)); - - defparam LUT4_13.initval = 16'h6996 ; - ROM16X1A LUT4_13 (.AD3(r_gcount_w26), .AD2(r_gcount_w27), .AD1(r_gcount_w28), - .AD0(r_gcount_w29), .DO0(r_g2b_xor_cluster_0)); - - defparam LUT4_12.initval = 16'h6996 ; - ROM16X1A LUT4_12 (.AD3(r_gcount_w22), .AD2(r_gcount_w23), .AD1(r_gcount_w24), - .AD0(r_gcount_w25), .DO0(r_g2b_xor_cluster_1)); - - defparam LUT4_11.initval = 16'h6996 ; - ROM16X1A LUT4_11 (.AD3(r_gcount_w28), .AD2(r_gcount_w29), .AD1(scuba_vlo), - .AD0(scuba_vlo), .DO0(rcount_w8)); - - defparam LUT4_10.initval = 16'h6996 ; - ROM16X1A LUT4_10 (.AD3(r_gcount_w27), .AD2(r_gcount_w28), .AD1(r_gcount_w29), - .AD0(scuba_vlo), .DO0(rcount_w7)); - - defparam LUT4_9.initval = 16'h6996 ; - ROM16X1A LUT4_9 (.AD3(r_gcount_w25), .AD2(r_gcount_w26), .AD1(r_gcount_w27), - .AD0(rcount_w8), .DO0(rcount_w5)); - - defparam LUT4_8.initval = 16'h6996 ; - ROM16X1A LUT4_8 (.AD3(r_gcount_w24), .AD2(r_gcount_w25), .AD1(r_gcount_w26), - .AD0(rcount_w7), .DO0(rcount_w4)); - - defparam LUT4_7.initval = 16'h6996 ; - ROM16X1A LUT4_7 (.AD3(r_gcount_w23), .AD2(r_gcount_w24), .AD1(r_gcount_w25), - .AD0(r_g2b_xor_cluster_0), .DO0(rcount_w3)); - - defparam LUT4_6.initval = 16'h6996 ; - ROM16X1A LUT4_6 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(rcount_w2)); - - defparam LUT4_5.initval = 16'h6996 ; - ROM16X1A LUT4_5 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(r_gcount_w21), .AD0(scuba_vlo), .DO0(rcount_w1)); - - defparam LUT4_4.initval = 16'h6996 ; - ROM16X1A LUT4_4 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(r_gcount_w20), .AD0(r_gcount_w21), .DO0(rcount_w0)); - - defparam LUT4_3.initval = 16'h0410 ; - ROM16X1A LUT4_3 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), - .DO0(empty_cmp_set)); - - defparam LUT4_2.initval = 16'h1004 ; - ROM16X1A LUT4_2 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), - .DO0(empty_cmp_clr)); - - defparam LUT4_1.initval = 16'h0140 ; - ROM16X1A LUT4_1 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), - .DO0(full_cmp_set)); - - defparam LUT4_0.initval = 16'h4001 ; - ROM16X1A LUT4_0 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), - .DO0(full_cmp_clr)); - - defparam pdp_ram_0_0_0.INIT_DATA = "STATIC" ; - defparam pdp_ram_0_0_0.ASYNC_RESET_RELEASE = "SYNC" ; - defparam pdp_ram_0_0_0.CSDECODE_R = "0b000" ; - defparam pdp_ram_0_0_0.CSDECODE_W = "0b001" ; - defparam pdp_ram_0_0_0.GSR = "ENABLED" ; - defparam pdp_ram_0_0_0.RESETMODE = "SYNC" ; - defparam pdp_ram_0_0_0.REGMODE = "NOREG" ; - defparam pdp_ram_0_0_0.DATA_WIDTH_R = 36 ; - defparam pdp_ram_0_0_0.DATA_WIDTH_W = 36 ; - PDPW16KD pdp_ram_0_0_0 (.DI35(scuba_vlo), .DI34(scuba_vlo), .DI33(scuba_vlo), - .DI32(scuba_vlo), .DI31(Data[31]), .DI30(Data[30]), .DI29(Data[29]), - .DI28(Data[28]), .DI27(Data[27]), .DI26(Data[26]), .DI25(Data[25]), - .DI24(Data[24]), .DI23(Data[23]), .DI22(Data[22]), .DI21(Data[21]), - .DI20(Data[20]), .DI19(Data[19]), .DI18(Data[18]), .DI17(Data[17]), - .DI16(Data[16]), .DI15(Data[15]), .DI14(Data[14]), .DI13(Data[13]), - .DI12(Data[12]), .DI11(Data[11]), .DI10(Data[10]), .DI9(Data[9]), - .DI8(Data[8]), .DI7(Data[7]), .DI6(Data[6]), .DI5(Data[5]), .DI4(Data[4]), - .DI3(Data[3]), .DI2(Data[2]), .DI1(Data[1]), .DI0(Data[0]), .ADW8(wptr_8), - .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), .ADW4(wptr_4), .ADW3(wptr_3), - .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), .BE3(scuba_vhi), .BE2(scuba_vhi), - .BE1(scuba_vhi), .BE0(scuba_vhi), .CEW(wren_i), .CLKW(WrClock), - .CSW2(scuba_vlo), .CSW1(scuba_vlo), .CSW0(scuba_vhi), .ADR13(rptr_8), - .ADR12(rptr_7), .ADR11(rptr_6), .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), - .ADR7(rptr_2), .ADR6(rptr_1), .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), - .ADR2(scuba_vlo), .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), - .OCER(rden_i), .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), - .CSR0(scuba_vlo), .RST(Reset), .DO35(Q[17]), .DO34(Q[16]), .DO33(Q[15]), - .DO32(Q[14]), .DO31(Q[13]), .DO30(Q[12]), .DO29(Q[11]), .DO28(Q[10]), - .DO27(Q[9]), .DO26(Q[8]), .DO25(Q[7]), .DO24(Q[6]), .DO23(Q[5]), - .DO22(Q[4]), .DO21(Q[3]), .DO20(Q[2]), .DO19(Q[1]), .DO18(Q[0]), - .DO17(), .DO16(), .DO15(), .DO14(), .DO13(Q[31]), .DO12(Q[30]), - .DO11(Q[29]), .DO10(Q[28]), .DO9(Q[27]), .DO8(Q[26]), .DO7(Q[25]), - .DO6(Q[24]), .DO5(Q[23]), .DO4(Q[22]), .DO3(Q[21]), .DO2(Q[20]), - .DO1(Q[19]), .DO0(Q[18])) - /* synthesis MEM_LPC_FILE="fifo32dc.lpc" */ - /* synthesis MEM_INIT_FILE="" */; - - FD1P3BX FF_101 (.D(iwcount_0), .SP(wren_i), .CK(WrClock), .PD(Reset), - .Q(wcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_100 (.D(iwcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_99 (.D(iwcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_98 (.D(iwcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_97 (.D(iwcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_96 (.D(iwcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_95 (.D(iwcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_94 (.D(iwcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_93 (.D(iwcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_92 (.D(iwcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_91 (.D(w_gdata_0), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_90 (.D(w_gdata_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_89 (.D(w_gdata_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_88 (.D(w_gdata_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_87 (.D(w_gdata_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_86 (.D(w_gdata_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_85 (.D(w_gdata_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_84 (.D(w_gdata_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_83 (.D(w_gdata_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_82 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_81 (.D(wcount_0), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_80 (.D(wcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_79 (.D(wcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_78 (.D(wcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_77 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_76 (.D(wcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_75 (.D(wcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_74 (.D(wcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_73 (.D(wcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_72 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3BX FF_71 (.D(ircount_0), .SP(rden_i), .CK(RdClock), .PD(rRst), - .Q(rcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_70 (.D(ircount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_69 (.D(ircount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_68 (.D(ircount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_67 (.D(ircount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_66 (.D(ircount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_65 (.D(ircount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_64 (.D(ircount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_63 (.D(ircount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_62 (.D(ircount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_61 (.D(r_gdata_0), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_60 (.D(r_gdata_1), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_59 (.D(r_gdata_2), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_58 (.D(r_gdata_3), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_57 (.D(r_gdata_4), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_56 (.D(r_gdata_5), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_55 (.D(r_gdata_6), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_54 (.D(r_gdata_7), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_53 (.D(r_gdata_8), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_52 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(r_gcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_51 (.D(rcount_0), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_50 (.D(rcount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_49 (.D(rcount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_48 (.D(rcount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_47 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_46 (.D(rcount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_45 (.D(rcount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_44 (.D(rcount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_43 (.D(rcount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_42 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_41 (.D(w_gcount_0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r0)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_40 (.D(w_gcount_1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r1)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_39 (.D(w_gcount_2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r2)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_38 (.D(w_gcount_3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r3)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_37 (.D(w_gcount_4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r4)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_36 (.D(w_gcount_5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r5)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_35 (.D(w_gcount_6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r6)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_34 (.D(w_gcount_7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r7)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_33 (.D(w_gcount_8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r8)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_32 (.D(w_gcount_9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_31 (.D(r_gcount_0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w0)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_30 (.D(r_gcount_1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w1)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_29 (.D(r_gcount_2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w2)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_28 (.D(r_gcount_3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w3)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_27 (.D(r_gcount_4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w4)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_26 (.D(r_gcount_5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w5)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_25 (.D(r_gcount_6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w6)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_24 (.D(r_gcount_7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w7)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_23 (.D(r_gcount_8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w8)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_22 (.D(r_gcount_9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_21 (.D(w_gcount_r0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r20)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_20 (.D(w_gcount_r1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r21)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_19 (.D(w_gcount_r2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r22)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_18 (.D(w_gcount_r3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r23)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_17 (.D(w_gcount_r4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r24)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_16 (.D(w_gcount_r5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r25)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_15 (.D(w_gcount_r6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r26)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_14 (.D(w_gcount_r7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r27)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_13 (.D(w_gcount_r8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r28)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_12 (.D(w_gcount_r9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r29)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_11 (.D(r_gcount_w0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w20)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_10 (.D(r_gcount_w1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w21)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_9 (.D(r_gcount_w2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w22)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_8 (.D(r_gcount_w3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w23)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_7 (.D(r_gcount_w4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w24)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_6 (.D(r_gcount_w5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w25)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_5 (.D(r_gcount_w6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w26)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_4 (.D(r_gcount_w7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w27)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_3 (.D(r_gcount_w8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w28)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_2 (.D(r_gcount_w9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w29)) - /* synthesis GSR="ENABLED" */; - - FD1S3BX FF_1 (.D(empty_d), .CK(RdClock), .PD(rRst), .Q(empty_i)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_0 (.D(full_d), .CK(WrClock), .CD(Reset), .Q(full_i)) - /* synthesis GSR="ENABLED" */; - - defparam w_gctr_cia.INJECT1_1 = "NO" ; - defparam w_gctr_cia.INJECT1_0 = "NO" ; - defparam w_gctr_cia.INIT1 = 16'h66AA ; - defparam w_gctr_cia.INIT0 = 16'h66AA ; - CCU2C w_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(w_gctr_ci)); - - defparam w_gctr_0.INJECT1_1 = "NO" ; - defparam w_gctr_0.INJECT1_0 = "NO" ; - defparam w_gctr_0.INIT1 = 16'h66AA ; - defparam w_gctr_0.INIT0 = 16'h66AA ; - CCU2C w_gctr_0 (.A0(wcount_0), .A1(wcount_1), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(w_gctr_ci), .S0(iwcount_0), .S1(iwcount_1), .COUT(co0)); - - defparam w_gctr_1.INJECT1_1 = "NO" ; - defparam w_gctr_1.INJECT1_0 = "NO" ; - defparam w_gctr_1.INIT1 = 16'h66AA ; - defparam w_gctr_1.INIT0 = 16'h66AA ; - CCU2C w_gctr_1 (.A0(wcount_2), .A1(wcount_3), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0), .S0(iwcount_2), .S1(iwcount_3), .COUT(co1)); - - defparam w_gctr_2.INJECT1_1 = "NO" ; - defparam w_gctr_2.INJECT1_0 = "NO" ; - defparam w_gctr_2.INIT1 = 16'h66AA ; - defparam w_gctr_2.INIT0 = 16'h66AA ; - CCU2C w_gctr_2 (.A0(wcount_4), .A1(wcount_5), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1), .S0(iwcount_4), .S1(iwcount_5), .COUT(co2)); - - defparam w_gctr_3.INJECT1_1 = "NO" ; - defparam w_gctr_3.INJECT1_0 = "NO" ; - defparam w_gctr_3.INIT1 = 16'h66AA ; - defparam w_gctr_3.INIT0 = 16'h66AA ; - CCU2C w_gctr_3 (.A0(wcount_6), .A1(wcount_7), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co2), .S0(iwcount_6), .S1(iwcount_7), .COUT(co3)); - - defparam w_gctr_4.INJECT1_1 = "NO" ; - defparam w_gctr_4.INJECT1_0 = "NO" ; - defparam w_gctr_4.INIT1 = 16'h66AA ; - defparam w_gctr_4.INIT0 = 16'h66AA ; - CCU2C w_gctr_4 (.A0(wcount_8), .A1(wcount_9), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co3), .S0(iwcount_8), .S1(iwcount_9), .COUT(co4)); - - defparam r_gctr_cia.INJECT1_1 = "NO" ; - defparam r_gctr_cia.INJECT1_0 = "NO" ; - defparam r_gctr_cia.INIT1 = 16'h66AA ; - defparam r_gctr_cia.INIT0 = 16'h66AA ; - CCU2C r_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(r_gctr_ci)); - - defparam r_gctr_0.INJECT1_1 = "NO" ; - defparam r_gctr_0.INJECT1_0 = "NO" ; - defparam r_gctr_0.INIT1 = 16'h66AA ; - defparam r_gctr_0.INIT0 = 16'h66AA ; - CCU2C r_gctr_0 (.A0(rcount_0), .A1(rcount_1), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(r_gctr_ci), .S0(ircount_0), .S1(ircount_1), .COUT(co0_1)); - - defparam r_gctr_1.INJECT1_1 = "NO" ; - defparam r_gctr_1.INJECT1_0 = "NO" ; - defparam r_gctr_1.INIT1 = 16'h66AA ; - defparam r_gctr_1.INIT0 = 16'h66AA ; - CCU2C r_gctr_1 (.A0(rcount_2), .A1(rcount_3), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_1), .S0(ircount_2), .S1(ircount_3), .COUT(co1_1)); - - defparam r_gctr_2.INJECT1_1 = "NO" ; - defparam r_gctr_2.INJECT1_0 = "NO" ; - defparam r_gctr_2.INIT1 = 16'h66AA ; - defparam r_gctr_2.INIT0 = 16'h66AA ; - CCU2C r_gctr_2 (.A0(rcount_4), .A1(rcount_5), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_1), .S0(ircount_4), .S1(ircount_5), .COUT(co2_1)); - - defparam r_gctr_3.INJECT1_1 = "NO" ; - defparam r_gctr_3.INJECT1_0 = "NO" ; - defparam r_gctr_3.INIT1 = 16'h66AA ; - defparam r_gctr_3.INIT0 = 16'h66AA ; - CCU2C r_gctr_3 (.A0(rcount_6), .A1(rcount_7), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co2_1), .S0(ircount_6), .S1(ircount_7), .COUT(co3_1)); - - defparam r_gctr_4.INJECT1_1 = "NO" ; - defparam r_gctr_4.INJECT1_0 = "NO" ; - defparam r_gctr_4.INIT1 = 16'h66AA ; - defparam r_gctr_4.INIT0 = 16'h66AA ; - CCU2C r_gctr_4 (.A0(rcount_8), .A1(rcount_9), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co3_1), .S0(ircount_8), .S1(ircount_9), .COUT(co4_1)); - - defparam empty_cmp_ci_a.INJECT1_1 = "NO" ; - defparam empty_cmp_ci_a.INJECT1_0 = "NO" ; - defparam empty_cmp_ci_a.INIT1 = 16'h66AA ; - defparam empty_cmp_ci_a.INIT0 = 16'h66AA ; - CCU2C empty_cmp_ci_a (.A0(scuba_vlo), .A1(rden_i), .B0(scuba_vlo), .B1(rden_i), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(cmp_ci)); - - defparam empty_cmp_0.INJECT1_1 = "NO" ; - defparam empty_cmp_0.INJECT1_0 = "NO" ; - defparam empty_cmp_0.INIT1 = 16'h99AA ; - defparam empty_cmp_0.INIT0 = 16'h99AA ; - CCU2C empty_cmp_0 (.A0(rcount_0), .A1(rcount_1), .B0(wcount_r0), .B1(wcount_r1), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(cmp_ci), .S0(), .S1(), .COUT(co0_2)); - - defparam empty_cmp_1.INJECT1_1 = "NO" ; - defparam empty_cmp_1.INJECT1_0 = "NO" ; - defparam empty_cmp_1.INIT1 = 16'h99AA ; - defparam empty_cmp_1.INIT0 = 16'h99AA ; - CCU2C empty_cmp_1 (.A0(rcount_2), .A1(rcount_3), .B0(wcount_r2), .B1(wcount_r3), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_2), .S0(), .S1(), .COUT(co1_2)); - - defparam empty_cmp_2.INJECT1_1 = "NO" ; - defparam empty_cmp_2.INJECT1_0 = "NO" ; - defparam empty_cmp_2.INIT1 = 16'h99AA ; - defparam empty_cmp_2.INIT0 = 16'h99AA ; - CCU2C empty_cmp_2 (.A0(rcount_4), .A1(rcount_5), .B0(wcount_r4), .B1(wcount_r5), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_2), .S0(), .S1(), .COUT(co2_2)); - - defparam empty_cmp_3.INJECT1_1 = "NO" ; - defparam empty_cmp_3.INJECT1_0 = "NO" ; - defparam empty_cmp_3.INIT1 = 16'h99AA ; - defparam empty_cmp_3.INIT0 = 16'h99AA ; - CCU2C empty_cmp_3 (.A0(rcount_6), .A1(rcount_7), .B0(w_g2b_xor_cluster_0), - .B1(wcount_r7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co2_2), .S0(), .S1(), .COUT(co3_2)); - - defparam empty_cmp_4.INJECT1_1 = "NO" ; - defparam empty_cmp_4.INJECT1_0 = "NO" ; - defparam empty_cmp_4.INIT1 = 16'h99AA ; - defparam empty_cmp_4.INIT0 = 16'h99AA ; - CCU2C empty_cmp_4 (.A0(rcount_8), .A1(empty_cmp_set), .B0(wcount_r8), - .B1(empty_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co3_2), .S0(), .S1(), .COUT(empty_d_c)); - - defparam a0.INJECT1_1 = "NO" ; - defparam a0.INJECT1_0 = "NO" ; - defparam a0.INIT1 = 16'h66AA ; - defparam a0.INIT0 = 16'h66AA ; - CCU2C a0 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(empty_d_c), .S0(empty_d), .S1(), .COUT()); - - defparam full_cmp_ci_a.INJECT1_1 = "NO" ; - defparam full_cmp_ci_a.INJECT1_0 = "NO" ; - defparam full_cmp_ci_a.INIT1 = 16'h66AA ; - defparam full_cmp_ci_a.INIT0 = 16'h66AA ; - CCU2C full_cmp_ci_a (.A0(scuba_vlo), .A1(wren_i), .B0(scuba_vlo), .B1(wren_i), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(cmp_ci_1)); - - defparam full_cmp_0.INJECT1_1 = "NO" ; - defparam full_cmp_0.INJECT1_0 = "NO" ; - defparam full_cmp_0.INIT1 = 16'h99AA ; - defparam full_cmp_0.INIT0 = 16'h99AA ; - CCU2C full_cmp_0 (.A0(wcount_0), .A1(wcount_1), .B0(rcount_w0), .B1(rcount_w1), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(cmp_ci_1), .S0(), .S1(), .COUT(co0_3)); - - defparam full_cmp_1.INJECT1_1 = "NO" ; - defparam full_cmp_1.INJECT1_0 = "NO" ; - defparam full_cmp_1.INIT1 = 16'h99AA ; - defparam full_cmp_1.INIT0 = 16'h99AA ; - CCU2C full_cmp_1 (.A0(wcount_2), .A1(wcount_3), .B0(rcount_w2), .B1(rcount_w3), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_3), .S0(), .S1(), .COUT(co1_3)); - - defparam full_cmp_2.INJECT1_1 = "NO" ; - defparam full_cmp_2.INJECT1_0 = "NO" ; - defparam full_cmp_2.INIT1 = 16'h99AA ; - defparam full_cmp_2.INIT0 = 16'h99AA ; - CCU2C full_cmp_2 (.A0(wcount_4), .A1(wcount_5), .B0(rcount_w4), .B1(rcount_w5), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_3), .S0(), .S1(), .COUT(co2_3)); - - defparam full_cmp_3.INJECT1_1 = "NO" ; - defparam full_cmp_3.INJECT1_0 = "NO" ; - defparam full_cmp_3.INIT1 = 16'h99AA ; - defparam full_cmp_3.INIT0 = 16'h99AA ; - CCU2C full_cmp_3 (.A0(wcount_6), .A1(wcount_7), .B0(r_g2b_xor_cluster_0), - .B1(rcount_w7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co2_3), .S0(), .S1(), .COUT(co3_3)); - - defparam full_cmp_4.INJECT1_1 = "NO" ; - defparam full_cmp_4.INJECT1_0 = "NO" ; - defparam full_cmp_4.INIT1 = 16'h99AA ; - defparam full_cmp_4.INIT0 = 16'h99AA ; - CCU2C full_cmp_4 (.A0(wcount_8), .A1(full_cmp_set), .B0(rcount_w8), - .B1(full_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co3_3), .S0(), .S1(), .COUT(full_d_c)); - - VHI scuba_vhi_inst (.Z(scuba_vhi)); - - VLO scuba_vlo_inst (.Z(scuba_vlo)); - - defparam a1.INJECT1_1 = "NO" ; - defparam a1.INJECT1_0 = "NO" ; - defparam a1.INIT1 = 16'h66AA ; - defparam a1.INIT0 = 16'h66AA ; - CCU2C a1 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(full_d_c), .S0(full_d), .S1(), .COUT()); - - assign Empty = empty_i; - assign Full = full_i; - - - // exemplar begin - // exemplar attribute pdp_ram_0_0_0 MEM_LPC_FILE fifo32dc.lpc - // exemplar attribute pdp_ram_0_0_0 MEM_INIT_FILE - // exemplar attribute FF_101 GSR ENABLED - // exemplar attribute FF_100 GSR ENABLED - // exemplar attribute FF_99 GSR ENABLED - // exemplar attribute FF_98 GSR ENABLED - // exemplar attribute FF_97 GSR ENABLED - // exemplar attribute FF_96 GSR ENABLED - // exemplar attribute FF_95 GSR ENABLED - // exemplar attribute FF_94 GSR ENABLED - // exemplar attribute FF_93 GSR ENABLED - // exemplar attribute FF_92 GSR ENABLED - // exemplar attribute FF_91 GSR ENABLED - // exemplar attribute FF_90 GSR ENABLED - // exemplar attribute FF_89 GSR ENABLED - // exemplar attribute FF_88 GSR ENABLED - // exemplar attribute FF_87 GSR ENABLED - // exemplar attribute FF_86 GSR ENABLED - // exemplar attribute FF_85 GSR ENABLED - // exemplar attribute FF_84 GSR ENABLED - // exemplar attribute FF_83 GSR ENABLED - // exemplar attribute FF_82 GSR ENABLED - // exemplar attribute FF_81 GSR ENABLED - // exemplar attribute FF_80 GSR ENABLED - // exemplar attribute FF_79 GSR ENABLED - // exemplar attribute FF_78 GSR ENABLED - // exemplar attribute FF_77 GSR ENABLED - // exemplar attribute FF_76 GSR ENABLED - // exemplar attribute FF_75 GSR ENABLED - // exemplar attribute FF_74 GSR ENABLED - // exemplar attribute FF_73 GSR ENABLED - // exemplar attribute FF_72 GSR ENABLED - // exemplar attribute FF_71 GSR ENABLED - // exemplar attribute FF_70 GSR ENABLED - // exemplar attribute FF_69 GSR ENABLED - // exemplar attribute FF_68 GSR ENABLED - // exemplar attribute FF_67 GSR ENABLED - // exemplar attribute FF_66 GSR ENABLED - // exemplar attribute FF_65 GSR ENABLED - // exemplar attribute FF_64 GSR ENABLED - // exemplar attribute FF_63 GSR ENABLED - // exemplar attribute FF_62 GSR ENABLED - // exemplar attribute FF_61 GSR ENABLED - // exemplar attribute FF_60 GSR ENABLED - // exemplar attribute FF_59 GSR ENABLED - // exemplar attribute FF_58 GSR ENABLED - // exemplar attribute FF_57 GSR ENABLED - // exemplar attribute FF_56 GSR ENABLED - // exemplar attribute FF_55 GSR ENABLED - // exemplar attribute FF_54 GSR ENABLED - // exemplar attribute FF_53 GSR ENABLED - // exemplar attribute FF_52 GSR ENABLED - // exemplar attribute FF_51 GSR ENABLED - // exemplar attribute FF_50 GSR ENABLED - // exemplar attribute FF_49 GSR ENABLED - // exemplar attribute FF_48 GSR ENABLED - // exemplar attribute FF_47 GSR ENABLED - // exemplar attribute FF_46 GSR ENABLED - // exemplar attribute FF_45 GSR ENABLED - // exemplar attribute FF_44 GSR ENABLED - // exemplar attribute FF_43 GSR ENABLED - // exemplar attribute FF_42 GSR ENABLED - // exemplar attribute FF_41 GSR ENABLED - // exemplar attribute FF_40 GSR ENABLED - // exemplar attribute FF_39 GSR ENABLED - // exemplar attribute FF_38 GSR ENABLED - // exemplar attribute FF_37 GSR ENABLED - // exemplar attribute FF_36 GSR ENABLED - // exemplar attribute FF_35 GSR ENABLED - // exemplar attribute FF_34 GSR ENABLED - // exemplar attribute FF_33 GSR ENABLED - // exemplar attribute FF_32 GSR ENABLED - // exemplar attribute FF_31 GSR ENABLED - // exemplar attribute FF_30 GSR ENABLED - // exemplar attribute FF_29 GSR ENABLED - // exemplar attribute FF_28 GSR ENABLED - // exemplar attribute FF_27 GSR ENABLED - // exemplar attribute FF_26 GSR ENABLED - // exemplar attribute FF_25 GSR ENABLED - // exemplar attribute FF_24 GSR ENABLED - // exemplar attribute FF_23 GSR ENABLED - // exemplar attribute FF_22 GSR ENABLED - // exemplar attribute FF_21 GSR ENABLED - // exemplar attribute FF_20 GSR ENABLED - // exemplar attribute FF_19 GSR ENABLED - // exemplar attribute FF_18 GSR ENABLED - // exemplar attribute FF_17 GSR ENABLED - // exemplar attribute FF_16 GSR ENABLED - // exemplar attribute FF_15 GSR ENABLED - // exemplar attribute FF_14 GSR ENABLED - // exemplar attribute FF_13 GSR ENABLED - // exemplar attribute FF_12 GSR ENABLED - // exemplar attribute FF_11 GSR ENABLED - // exemplar attribute FF_10 GSR ENABLED - // exemplar attribute FF_9 GSR ENABLED - // exemplar attribute FF_8 GSR ENABLED - // exemplar attribute FF_7 GSR ENABLED - // exemplar attribute FF_6 GSR ENABLED - // exemplar attribute FF_5 GSR ENABLED - // exemplar attribute FF_4 GSR ENABLED - // exemplar attribute FF_3 GSR ENABLED - // exemplar attribute FF_2 GSR ENABLED - // exemplar attribute FF_1 GSR ENABLED - // exemplar attribute FF_0 GSR ENABLED - // exemplar end - -endmodule diff --git a/fifo32dc/fifo32dc_generate.log b/fifo32dc/fifo32dc_generate.log deleted file mode 100644 index 24573c0..0000000 --- a/fifo32dc/fifo32dc_generate.log +++ /dev/null @@ -1,49 +0,0 @@ -Starting process: - -Configuration data saved - - -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Sun Sep 13 16:38:25 2020 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 - Circuit name : fifo32dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo32dc.edn - Verilog output : fifo32dc.v - Verilog template : fifo32dc_tmpl.v - Verilog testbench: tb_fifo32dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo32dc.srp - Estimated Resource Usage: - LUT : 97 - EBR : 1 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo32dc.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/fifo32dc/fifo32dc_tmpl.v b/fifo32dc/fifo32dc_tmpl.v deleted file mode 100644 index 7f35eff..0000000 --- a/fifo32dc/fifo32dc_tmpl.v +++ /dev/null @@ -1,7 +0,0 @@ -/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */ -/* Module Version: 5.8 */ -/* Sun Sep 13 16:38:29 2020 */ - -/* parameterized module instance */ -fifo32dc __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), - .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( )); diff --git a/fifo32dc/generate_core.tcl b/fifo32dc/generate_core.tcl deleted file mode 100644 index 6cb63b1..0000000 --- a/fifo32dc/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "fifo32dc" -set lang "verilog" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "sa5p00g" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/fifo32dc/generate_ngd.tcl b/fifo32dc/generate_ngd.tcl deleted file mode 100644 index adc592e..0000000 --- a/fifo32dc/generate_ngd.tcl +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "fifo32dc" -set Para(Module) "FIFO_DC" -set Para(libname) ecp5um5g -set Para(arch_name) sa5p00g -set Para(PartType) "LFE5UM5G-45F" - -set Para(tech_syn) ecp5um5g -set Para(tech_cae) ecp5um5g -set Para(Package) "CABGA381" -set Para(SpeedGrade) "8" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/fifo32dc/msg_file.log b/fifo32dc/msg_file.log deleted file mode 100644 index bc796a7..0000000 --- a/fifo32dc/msg_file.log +++ /dev/null @@ -1,33 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Sun Sep 13 16:38:25 2020 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo32dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 32 -rwidth 32 -sync_reset -pe -1 -pf -1 - Circuit name : fifo32dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[31:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo32dc.edn - Verilog output : fifo32dc.v - Verilog template : fifo32dc_tmpl.v - Verilog testbench: tb_fifo32dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo32dc.srp - Estimated Resource Usage: - LUT : 97 - EBR : 1 - Reg : 102 - -END SCUBA Module Synthesis - diff --git a/fifo32dc/tb_fifo32dc_tmpl.v b/fifo32dc/tb_fifo32dc_tmpl.v deleted file mode 100644 index 1c08fc7..0000000 --- a/fifo32dc/tb_fifo32dc_tmpl.v +++ /dev/null @@ -1,76 +0,0 @@ -//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.11.2.446 -`timescale 1 ns / 1 ps -module tb; - reg [31:0] Data = 32'b0; - reg WrClock = 0; - reg RdClock = 0; - reg WrEn = 0; - reg RdEn = 0; - reg Reset = 0; - reg RPReset = 0; - wire [31:0] Q; - wire Empty; - wire Full; - - integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0; - - GSR GSR_INST (.GSR(1'b1)); - PUR PUR_INST (.PUR(1'b1)); - - fifo32dc u1 (.Data(Data), .WrClock(WrClock), .RdClock(RdClock), .WrEn(WrEn), - .RdEn(RdEn), .Reset(Reset), .RPReset(RPReset), .Q(Q), .Empty(Empty), - .Full(Full) - ); - - initial - begin - Data <= 0; - #100; - @(Reset == 1'b0); - for (i1 = 0; i1 < 515; i1 = i1 + 1) begin - @(posedge WrClock); - #1 Data <= Data + 1'b1; - end - end - always - #5.00 WrClock <= ~ WrClock; - - always - #5.00 RdClock <= ~ RdClock; - - initial - begin - WrEn <= 1'b0; - #100; - @(Reset == 1'b0); - for (i4 = 0; i4 < 515; i4 = i4 + 1) begin - @(posedge WrClock); - #1 WrEn <= 1'b1; - end - WrEn <= 1'b0; - end - initial - begin - RdEn <= 1'b0; - @(Reset == 1'b0); - @(WrEn == 1'b1); - @(WrEn == 1'b0); - for (i5 = 0; i5 < 515; i5 = i5 + 1) begin - @(posedge RdClock); - #1 RdEn <= 1'b1; - end - RdEn <= 1'b0; - end - initial - begin - Reset <= 1'b1; - #100; - Reset <= 1'b0; - end - initial - begin - RPReset <= 1'b1; - #100; - RPReset <= 1'b0; - end -endmodule \ No newline at end of file diff --git a/fifo40_dc/fifo40_dc.cst b/fifo40_dc/fifo40_dc.cst deleted file mode 100644 index a32fb04..0000000 --- a/fifo40_dc/fifo40_dc.cst +++ /dev/null @@ -1,3 +0,0 @@ -Date=02/09/2021 -Time=13:19:24 - diff --git a/fifo40_dc/fifo40_dc.edn b/fifo40_dc/fifo40_dc.edn deleted file mode 100644 index 51db303..0000000 --- a/fifo40_dc/fifo40_dc.edn +++ /dev/null @@ -1,3245 +0,0 @@ -(edif fifo40_dc - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2021 2 9 13 19 26) - (program "SCUBA" (version "Diamond (64-bit) 3.11.2.446")))) - (comment "/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell CCU2C - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A0 - (direction INPUT)) - (port A1 - (direction INPUT)) - (port B0 - (direction INPUT)) - (port B1 - (direction INPUT)) - (port C0 - (direction INPUT)) - (port C1 - (direction INPUT)) - (port D0 - (direction INPUT)) - (port D1 - (direction INPUT)) - (port CIN - (direction INPUT)) - (port S0 - (direction OUTPUT)) - (port S1 - (direction OUTPUT)) - (port COUT - (direction OUTPUT))))) - (cell AND2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell FD1P3BX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port SP - (direction INPUT)) - (port CK - (direction INPUT)) - (port PD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1P3DX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port SP - (direction INPUT)) - (port CK - (direction INPUT)) - (port CD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1S3BX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port CK - (direction INPUT)) - (port PD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell FD1S3DX - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port D - (direction INPUT)) - (port CK - (direction INPUT)) - (port CD - (direction INPUT)) - (port Q - (direction OUTPUT))))) - (cell INV - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell OR2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell ROM16X1A - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port AD3 - (direction INPUT)) - (port AD2 - (direction INPUT)) - (port AD1 - (direction INPUT)) - (port AD0 - (direction INPUT)) - (port DO0 - (direction OUTPUT))))) - (cell VHI - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell VLO - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell XOR2 - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port A - (direction INPUT)) - (port B - (direction INPUT)) - (port Z - (direction OUTPUT))))) - (cell PDPW16KD - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port DI35 - (direction INPUT)) - (port DI34 - (direction INPUT)) - (port DI33 - (direction INPUT)) - (port DI32 - (direction INPUT)) - (port DI31 - (direction INPUT)) - (port DI30 - (direction INPUT)) - (port DI29 - (direction INPUT)) - (port DI28 - (direction INPUT)) - (port DI27 - (direction INPUT)) - (port DI26 - (direction INPUT)) - (port DI25 - (direction INPUT)) - (port DI24 - (direction INPUT)) - (port DI23 - (direction INPUT)) - (port DI22 - (direction INPUT)) - (port DI21 - (direction INPUT)) - (port DI20 - (direction INPUT)) - (port DI19 - (direction INPUT)) - (port DI18 - (direction INPUT)) - (port DI17 - (direction INPUT)) - (port DI16 - (direction INPUT)) - (port DI15 - (direction INPUT)) - (port DI14 - (direction INPUT)) - (port DI13 - (direction INPUT)) - (port DI12 - (direction INPUT)) - (port DI11 - (direction INPUT)) - (port DI10 - (direction INPUT)) - (port DI9 - (direction INPUT)) - (port DI8 - (direction INPUT)) - (port DI7 - (direction INPUT)) - (port DI6 - (direction INPUT)) - (port DI5 - (direction INPUT)) - (port DI4 - (direction INPUT)) - (port DI3 - (direction INPUT)) - (port DI2 - (direction INPUT)) - (port DI1 - (direction INPUT)) - (port DI0 - (direction INPUT)) - (port ADW8 - (direction INPUT)) - (port ADW7 - (direction INPUT)) - (port ADW6 - (direction INPUT)) - (port ADW5 - (direction INPUT)) - (port ADW4 - (direction INPUT)) - (port ADW3 - (direction INPUT)) - (port ADW2 - (direction INPUT)) - (port ADW1 - (direction INPUT)) - (port ADW0 - (direction INPUT)) - (port BE3 - (direction INPUT)) - (port BE2 - (direction INPUT)) - (port BE1 - (direction INPUT)) - (port BE0 - (direction INPUT)) - (port CEW - (direction INPUT)) - (port CLKW - (direction INPUT)) - (port CSW2 - (direction INPUT)) - (port CSW1 - (direction INPUT)) - (port CSW0 - (direction INPUT)) - (port ADR13 - (direction INPUT)) - (port ADR12 - (direction INPUT)) - (port ADR11 - (direction INPUT)) - (port ADR10 - (direction INPUT)) - (port ADR9 - (direction INPUT)) - (port ADR8 - (direction INPUT)) - (port ADR7 - (direction INPUT)) - (port ADR6 - (direction INPUT)) - (port ADR5 - (direction INPUT)) - (port ADR4 - (direction INPUT)) - (port ADR3 - (direction INPUT)) - (port ADR2 - (direction INPUT)) - (port ADR1 - (direction INPUT)) - (port ADR0 - (direction INPUT)) - (port CER - (direction INPUT)) - (port OCER - (direction INPUT)) - (port CLKR - (direction INPUT)) - (port CSR2 - (direction INPUT)) - (port CSR1 - (direction INPUT)) - (port CSR0 - (direction INPUT)) - (port RST - (direction INPUT)) - (port DO35 - (direction OUTPUT)) - (port DO34 - (direction OUTPUT)) - (port DO33 - (direction OUTPUT)) - (port DO32 - (direction OUTPUT)) - (port DO31 - (direction OUTPUT)) - (port DO30 - (direction OUTPUT)) - (port DO29 - (direction OUTPUT)) - (port DO28 - (direction OUTPUT)) - (port DO27 - (direction OUTPUT)) - (port DO26 - (direction OUTPUT)) - (port DO25 - (direction OUTPUT)) - (port DO24 - (direction OUTPUT)) - (port DO23 - (direction OUTPUT)) - (port DO22 - (direction OUTPUT)) - (port DO21 - (direction OUTPUT)) - (port DO20 - (direction OUTPUT)) - (port DO19 - (direction OUTPUT)) - (port DO18 - (direction OUTPUT)) - (port DO17 - (direction OUTPUT)) - (port DO16 - (direction OUTPUT)) - (port DO15 - (direction OUTPUT)) - (port DO14 - (direction OUTPUT)) - (port DO13 - (direction OUTPUT)) - (port DO12 - (direction OUTPUT)) - (port DO11 - (direction OUTPUT)) - (port DO10 - (direction OUTPUT)) - (port DO9 - (direction OUTPUT)) - (port DO8 - (direction OUTPUT)) - (port DO7 - (direction OUTPUT)) - (port DO6 - (direction OUTPUT)) - (port DO5 - (direction OUTPUT)) - (port DO4 - (direction OUTPUT)) - (port DO3 - (direction OUTPUT)) - (port DO2 - (direction OUTPUT)) - (port DO1 - (direction OUTPUT)) - (port DO0 - (direction OUTPUT))))) - (cell fifo40_dc - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port (array (rename Data "Data(39:0)") 40) - (direction INPUT)) - (port WrClock - (direction INPUT)) - (port RdClock - (direction INPUT)) - (port WrEn - (direction INPUT)) - (port RdEn - (direction INPUT)) - (port Reset - (direction INPUT)) - (port RPReset - (direction INPUT)) - (port (array (rename Q "Q(39:0)") 40) - (direction OUTPUT)) - (port Empty - (direction OUTPUT)) - (port Full - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance AND2_t20 - (viewRef view1 - (cellRef AND2))) - (instance INV_1 - (viewRef view1 - (cellRef INV))) - (instance AND2_t19 - (viewRef view1 - (cellRef AND2))) - (instance INV_0 - (viewRef view1 - (cellRef INV))) - (instance OR2_t18 - (viewRef view1 - (cellRef OR2))) - (instance XOR2_t17 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t16 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t15 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t14 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t13 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t12 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t11 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t10 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t9 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t8 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t7 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t6 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t5 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t4 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t3 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t2 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t1 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t0 - (viewRef view1 - (cellRef XOR2))) - (instance LUT4_23 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_22 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_21 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_20 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_19 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_18 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_17 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_16 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_15 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_14 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_13 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_12 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_11 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_10 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_9 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_8 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_7 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_6 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_5 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_4 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x6996"))) - (instance LUT4_3 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x0410"))) - (instance LUT4_2 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x1004"))) - (instance LUT4_1 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x0140"))) - (instance LUT4_0 - (viewRef view1 - (cellRef ROM16X1A)) - (property initval - (string "0x4001"))) - (instance pdp_ram_0_0_1 - (viewRef view1 - (cellRef PDPW16KD)) - (property INIT_DATA - (string "STATIC")) - (property ASYNC_RESET_RELEASE - (string "SYNC")) - (property MEM_LPC_FILE - (string "fifo40_dc.lpc")) - (property MEM_INIT_FILE - (string "")) - (property CSDECODE_R - (string "0b000")) - (property CSDECODE_W - (string "0b001")) - (property GSR - (string "ENABLED")) - (property RESETMODE - (string "ASYNC")) - (property REGMODE - (string "NOREG")) - (property DATA_WIDTH_R - (string "36")) - (property DATA_WIDTH_W - (string "36"))) - (instance pdp_ram_0_1_0 - (viewRef view1 - (cellRef PDPW16KD)) - (property INIT_DATA - (string "STATIC")) - (property ASYNC_RESET_RELEASE - (string "SYNC")) - (property MEM_LPC_FILE - (string "fifo40_dc.lpc")) - (property MEM_INIT_FILE - (string "")) - (property CSDECODE_R - (string "0b000")) - (property CSDECODE_W - (string "0b001")) - (property GSR - (string "ENABLED")) - (property RESETMODE - (string "ASYNC")) - (property REGMODE - (string "NOREG")) - (property DATA_WIDTH_R - (string "36")) - (property DATA_WIDTH_W - (string "36"))) - (instance FF_101 - (viewRef view1 - (cellRef FD1P3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_100 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_99 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_98 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_97 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_96 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_95 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_94 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_93 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_92 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_91 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_90 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_89 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_88 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_87 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_86 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_85 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_84 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_83 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_82 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_81 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_80 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_79 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_78 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_77 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_76 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_75 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_74 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_73 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_72 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_71 - (viewRef view1 - (cellRef FD1P3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_70 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_69 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_68 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_67 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_66 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_65 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_64 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_63 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_62 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_61 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_60 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_59 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_58 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_57 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_56 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_55 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_54 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_53 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_52 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_51 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_50 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_49 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_48 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_47 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_46 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_45 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_44 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_43 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_42 - (viewRef view1 - (cellRef FD1P3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_41 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_40 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_39 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_38 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_37 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_36 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_35 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_34 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_33 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_32 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_31 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_30 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_29 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_28 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_27 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_26 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_25 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_24 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_23 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_22 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_21 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_20 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_19 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_18 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_17 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_16 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_15 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_14 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_13 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_12 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_11 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_10 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_9 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_8 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_7 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_6 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_5 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_4 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_3 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_2 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance FF_1 - (viewRef view1 - (cellRef FD1S3BX)) - (property GSR - (string "ENABLED"))) - (instance FF_0 - (viewRef view1 - (cellRef FD1S3DX)) - (property GSR - (string "ENABLED"))) - (instance w_gctr_cia - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance w_gctr_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_cia - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance r_gctr_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance empty_cmp_ci_a - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance empty_cmp_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance empty_cmp_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance a0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance full_cmp_ci_a - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (instance full_cmp_0 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_2 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_3 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance full_cmp_4 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x99AA")) - (property INIT0 - (string "0x99AA"))) - (instance scuba_vhi_inst - (viewRef view1 - (cellRef VHI))) - (instance scuba_vlo_inst - (viewRef view1 - (cellRef VLO))) - (instance a1 - (viewRef view1 - (cellRef CCU2C)) - (property INJECT1_1 - (string "NO")) - (property INJECT1_0 - (string "NO")) - (property INIT1 - (string "0x66AA")) - (property INIT0 - (string "0x66AA"))) - (net invout_1 - (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)))) - (net invout_0 - (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)))) - (net w_g2b_xor_cluster_1 - (joined - (portRef AD2 (instanceRef LUT4_14)) - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_16)) - (portRef AD2 (instanceRef LUT4_15)))) - (net r_g2b_xor_cluster_1 - (joined - (portRef AD2 (instanceRef LUT4_4)) - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_6)) - (portRef AD2 (instanceRef LUT4_5)))) - (net w_gdata_0 - (joined - (portRef D (instanceRef FF_91)) - (portRef Z (instanceRef XOR2_t17)))) - (net w_gdata_1 - (joined - (portRef D (instanceRef FF_90)) - (portRef Z (instanceRef XOR2_t16)))) - (net w_gdata_2 - (joined - (portRef D (instanceRef FF_89)) - (portRef Z (instanceRef XOR2_t15)))) - (net w_gdata_3 - (joined - (portRef D (instanceRef FF_88)) - (portRef Z (instanceRef XOR2_t14)))) - (net w_gdata_4 - (joined - (portRef D (instanceRef FF_87)) - (portRef Z (instanceRef XOR2_t13)))) - (net w_gdata_5 - (joined - (portRef D (instanceRef FF_86)) - (portRef Z (instanceRef XOR2_t12)))) - (net w_gdata_6 - (joined - (portRef D (instanceRef FF_85)) - (portRef Z (instanceRef XOR2_t11)))) - (net w_gdata_7 - (joined - (portRef D (instanceRef FF_84)) - (portRef Z (instanceRef XOR2_t10)))) - (net w_gdata_8 - (joined - (portRef D (instanceRef FF_83)) - (portRef Z (instanceRef XOR2_t9)))) - (net wptr_0 - (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_1)) - (portRef ADW0 (instanceRef pdp_ram_0_1_0)))) - (net wptr_1 - (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_1)) - (portRef ADW1 (instanceRef pdp_ram_0_1_0)))) - (net wptr_2 - (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_1)) - (portRef ADW2 (instanceRef pdp_ram_0_1_0)))) - (net wptr_3 - (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_1)) - (portRef ADW3 (instanceRef pdp_ram_0_1_0)))) - (net wptr_4 - (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_1)) - (portRef ADW4 (instanceRef pdp_ram_0_1_0)))) - (net wptr_5 - (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_1)) - (portRef ADW5 (instanceRef pdp_ram_0_1_0)))) - (net wptr_6 - (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_1)) - (portRef ADW6 (instanceRef pdp_ram_0_1_0)))) - (net wptr_7 - (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_1)) - (portRef ADW7 (instanceRef pdp_ram_0_1_0)))) - (net wptr_8 - (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_1)) - (portRef ADW8 (instanceRef pdp_ram_0_1_0)))) - (net wptr_9 - (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_1)) - (portRef AD3 (instanceRef LUT4_0)))) - (net r_gdata_0 - (joined - (portRef D (instanceRef FF_61)) - (portRef Z (instanceRef XOR2_t8)))) - (net r_gdata_1 - (joined - (portRef D (instanceRef FF_60)) - (portRef Z (instanceRef XOR2_t7)))) - (net r_gdata_2 - (joined - (portRef D (instanceRef FF_59)) - (portRef Z (instanceRef XOR2_t6)))) - (net r_gdata_3 - (joined - (portRef D (instanceRef FF_58)) - (portRef Z (instanceRef XOR2_t5)))) - (net r_gdata_4 - (joined - (portRef D (instanceRef FF_57)) - (portRef Z (instanceRef XOR2_t4)))) - (net r_gdata_5 - (joined - (portRef D (instanceRef FF_56)) - (portRef Z (instanceRef XOR2_t3)))) - (net r_gdata_6 - (joined - (portRef D (instanceRef FF_55)) - (portRef Z (instanceRef XOR2_t2)))) - (net r_gdata_7 - (joined - (portRef D (instanceRef FF_54)) - (portRef Z (instanceRef XOR2_t1)))) - (net r_gdata_8 - (joined - (portRef D (instanceRef FF_53)) - (portRef Z (instanceRef XOR2_t0)))) - (net rptr_0 - (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_1)) - (portRef ADR5 (instanceRef pdp_ram_0_1_0)))) - (net rptr_1 - (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_1)) - (portRef ADR6 (instanceRef pdp_ram_0_1_0)))) - (net rptr_2 - (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_1)) - (portRef ADR7 (instanceRef pdp_ram_0_1_0)))) - (net rptr_3 - (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_1)) - (portRef ADR8 (instanceRef pdp_ram_0_1_0)))) - (net rptr_4 - (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_1)) - (portRef ADR9 (instanceRef pdp_ram_0_1_0)))) - (net rptr_5 - (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_1)) - (portRef ADR10 (instanceRef pdp_ram_0_1_0)))) - (net rptr_6 - (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_1)) - (portRef ADR11 (instanceRef pdp_ram_0_1_0)))) - (net rptr_7 - (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_1)) - (portRef ADR12 (instanceRef pdp_ram_0_1_0)))) - (net rptr_8 - (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_1)) - (portRef ADR13 (instanceRef pdp_ram_0_1_0)))) - (net rptr_9 - (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_3)) - (portRef AD3 (instanceRef LUT4_2)))) - (net w_gcount_0 - (joined - (portRef D (instanceRef FF_41)) - (portRef Q (instanceRef FF_91)))) - (net w_gcount_1 - (joined - (portRef D (instanceRef FF_40)) - (portRef Q (instanceRef FF_90)))) - (net w_gcount_2 - (joined - (portRef D (instanceRef FF_39)) - (portRef Q (instanceRef FF_89)))) - (net w_gcount_3 - (joined - (portRef D (instanceRef FF_38)) - (portRef Q (instanceRef FF_88)))) - (net w_gcount_4 - (joined - (portRef D (instanceRef FF_37)) - (portRef Q (instanceRef FF_87)))) - (net w_gcount_5 - (joined - (portRef D (instanceRef FF_36)) - (portRef Q (instanceRef FF_86)))) - (net w_gcount_6 - (joined - (portRef D (instanceRef FF_35)) - (portRef Q (instanceRef FF_85)))) - (net w_gcount_7 - (joined - (portRef D (instanceRef FF_34)) - (portRef Q (instanceRef FF_84)))) - (net w_gcount_8 - (joined - (portRef D (instanceRef FF_33)) - (portRef Q (instanceRef FF_83)))) - (net w_gcount_9 - (joined - (portRef D (instanceRef FF_32)) - (portRef Q (instanceRef FF_82)))) - (net r_gcount_0 - (joined - (portRef D (instanceRef FF_31)) - (portRef Q (instanceRef FF_61)))) - (net r_gcount_1 - (joined - (portRef D (instanceRef FF_30)) - (portRef Q (instanceRef FF_60)))) - (net r_gcount_2 - (joined - (portRef D (instanceRef FF_29)) - (portRef Q (instanceRef FF_59)))) - (net r_gcount_3 - (joined - (portRef D (instanceRef FF_28)) - (portRef Q (instanceRef FF_58)))) - (net r_gcount_4 - (joined - (portRef D (instanceRef FF_27)) - (portRef Q (instanceRef FF_57)))) - (net r_gcount_5 - (joined - (portRef D (instanceRef FF_26)) - (portRef Q (instanceRef FF_56)))) - (net r_gcount_6 - (joined - (portRef D (instanceRef FF_25)) - (portRef Q (instanceRef FF_55)))) - (net r_gcount_7 - (joined - (portRef D (instanceRef FF_24)) - (portRef Q (instanceRef FF_54)))) - (net r_gcount_8 - (joined - (portRef D (instanceRef FF_23)) - (portRef Q (instanceRef FF_53)))) - (net r_gcount_9 - (joined - (portRef D (instanceRef FF_22)) - (portRef Q (instanceRef FF_52)))) - (net w_gcount_r20 - (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)))) - (net w_gcount_r0 - (joined - (portRef D (instanceRef FF_21)) - (portRef Q (instanceRef FF_41)))) - (net w_gcount_r21 - (joined - (portRef Q (instanceRef FF_20)) - (portRef AD1 (instanceRef LUT4_15)) - (portRef AD0 (instanceRef LUT4_14)))) - (net w_gcount_r1 - (joined - (portRef D (instanceRef FF_20)) - (portRef Q (instanceRef FF_40)))) - (net w_gcount_r22 - (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)))) - (net w_gcount_r2 - (joined - (portRef D (instanceRef FF_19)) - (portRef Q (instanceRef FF_39)))) - (net w_gcount_r23 - (joined - (portRef Q (instanceRef FF_18)) - (portRef AD2 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_17)))) - (net w_gcount_r3 - (joined - (portRef D (instanceRef FF_18)) - (portRef Q (instanceRef FF_38)))) - (net w_gcount_r24 - (joined - (portRef Q (instanceRef FF_17)) - (portRef AD1 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_17)))) - (net w_gcount_r4 - (joined - (portRef D (instanceRef FF_17)) - (portRef Q (instanceRef FF_37)))) - (net w_gcount_r25 - (joined - (portRef Q (instanceRef FF_16)) - (portRef AD0 (instanceRef LUT4_22)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_17)))) - (net w_gcount_r5 - (joined - (portRef D (instanceRef FF_16)) - (portRef Q (instanceRef FF_36)))) - (net w_gcount_r26 - (joined - (portRef Q (instanceRef FF_15)) - (portRef AD3 (instanceRef LUT4_23)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD1 (instanceRef LUT4_18)))) - (net w_gcount_r6 - (joined - (portRef D (instanceRef FF_15)) - (portRef Q (instanceRef FF_35)))) - (net w_gcount_r27 - (joined - (portRef Q (instanceRef FF_14)) - (portRef AD2 (instanceRef LUT4_23)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_19)))) - (net w_gcount_r7 - (joined - (portRef D (instanceRef FF_14)) - (portRef Q (instanceRef FF_34)))) - (net w_gcount_r28 - (joined - (portRef Q (instanceRef FF_13)) - (portRef AD1 (instanceRef LUT4_23)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD2 (instanceRef LUT4_20)))) - (net w_gcount_r8 - (joined - (portRef D (instanceRef FF_13)) - (portRef Q (instanceRef FF_33)))) - (net w_gcount_r29 - (joined - (portRef Q (instanceRef FF_12)) - (portRef AD0 (instanceRef LUT4_23)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_2)))) - (net w_gcount_r9 - (joined - (portRef D (instanceRef FF_12)) - (portRef Q (instanceRef FF_32)))) - (net r_gcount_w20 - (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)))) - (net r_gcount_w0 - (joined - (portRef D (instanceRef FF_11)) - (portRef Q (instanceRef FF_31)))) - (net r_gcount_w21 - (joined - (portRef Q (instanceRef FF_10)) - (portRef AD1 (instanceRef LUT4_5)) - (portRef AD0 (instanceRef LUT4_4)))) - (net r_gcount_w1 - (joined - (portRef D (instanceRef FF_10)) - (portRef Q (instanceRef FF_30)))) - (net r_gcount_w22 - (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)))) - (net r_gcount_w2 - (joined - (portRef D (instanceRef FF_9)) - (portRef Q (instanceRef FF_29)))) - (net r_gcount_w23 - (joined - (portRef Q (instanceRef FF_8)) - (portRef AD2 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_7)))) - (net r_gcount_w3 - (joined - (portRef D (instanceRef FF_8)) - (portRef Q (instanceRef FF_28)))) - (net r_gcount_w24 - (joined - (portRef Q (instanceRef FF_7)) - (portRef AD1 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_7)))) - (net r_gcount_w4 - (joined - (portRef D (instanceRef FF_7)) - (portRef Q (instanceRef FF_27)))) - (net r_gcount_w25 - (joined - (portRef Q (instanceRef FF_6)) - (portRef AD0 (instanceRef LUT4_12)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_7)))) - (net r_gcount_w5 - (joined - (portRef D (instanceRef FF_6)) - (portRef Q (instanceRef FF_26)))) - (net r_gcount_w26 - (joined - (portRef Q (instanceRef FF_5)) - (portRef AD3 (instanceRef LUT4_13)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD1 (instanceRef LUT4_8)))) - (net r_gcount_w6 - (joined - (portRef D (instanceRef FF_5)) - (portRef Q (instanceRef FF_25)))) - (net r_gcount_w27 - (joined - (portRef Q (instanceRef FF_4)) - (portRef AD2 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_9)))) - (net r_gcount_w7 - (joined - (portRef D (instanceRef FF_4)) - (portRef Q (instanceRef FF_24)))) - (net r_gcount_w28 - (joined - (portRef Q (instanceRef FF_3)) - (portRef AD1 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD2 (instanceRef LUT4_10)))) - (net r_gcount_w8 - (joined - (portRef D (instanceRef FF_3)) - (portRef Q (instanceRef FF_23)))) - (net r_gcount_w29 - (joined - (portRef Q (instanceRef FF_2)) - (portRef AD0 (instanceRef LUT4_13)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_0)))) - (net r_gcount_w9 - (joined - (portRef D (instanceRef FF_2)) - (portRef Q (instanceRef FF_22)))) - (net rRst - (joined - (portRef PD (instanceRef FF_1)) - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_71)) - (portRef CD (instanceRef FF_70)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_2)))) - (net iwcount_0 - (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)))) - (net iwcount_1 - (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)))) - (net w_gctr_ci - (joined - (portRef CIN (instanceRef w_gctr_0)) - (portRef COUT (instanceRef w_gctr_cia)))) - (net iwcount_2 - (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)))) - (net iwcount_3 - (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)))) - (net co0 - (joined - (portRef CIN (instanceRef w_gctr_1)) - (portRef COUT (instanceRef w_gctr_0)))) - (net iwcount_4 - (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)))) - (net iwcount_5 - (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)))) - (net co1 - (joined - (portRef CIN (instanceRef w_gctr_2)) - (portRef COUT (instanceRef w_gctr_1)))) - (net iwcount_6 - (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)))) - (net iwcount_7 - (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)))) - (net co2 - (joined - (portRef CIN (instanceRef w_gctr_3)) - (portRef COUT (instanceRef w_gctr_2)))) - (net iwcount_8 - (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)))) - (net iwcount_9 - (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)))) - (net co4 - (joined - (portRef COUT (instanceRef w_gctr_4)))) - (net co3 - (joined - (portRef CIN (instanceRef w_gctr_4)) - (portRef COUT (instanceRef w_gctr_3)))) - (net wcount_9 - (joined - (portRef A1 (instanceRef w_gctr_4)) - (portRef B (instanceRef XOR2_t9)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef Q (instanceRef FF_92)) - (portRef D (instanceRef FF_82)) - (portRef D (instanceRef FF_72)))) - (net ircount_0 - (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)))) - (net ircount_1 - (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)))) - (net r_gctr_ci - (joined - (portRef CIN (instanceRef r_gctr_0)) - (portRef COUT (instanceRef r_gctr_cia)))) - (net ircount_2 - (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)))) - (net ircount_3 - (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)))) - (net co0_1 - (joined - (portRef CIN (instanceRef r_gctr_1)) - (portRef COUT (instanceRef r_gctr_0)))) - (net ircount_4 - (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)))) - (net ircount_5 - (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)))) - (net co1_1 - (joined - (portRef CIN (instanceRef r_gctr_2)) - (portRef COUT (instanceRef r_gctr_1)))) - (net ircount_6 - (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)))) - (net ircount_7 - (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)))) - (net co2_1 - (joined - (portRef CIN (instanceRef r_gctr_3)) - (portRef COUT (instanceRef r_gctr_2)))) - (net ircount_8 - (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)))) - (net ircount_9 - (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)))) - (net co4_1 - (joined - (portRef COUT (instanceRef r_gctr_4)))) - (net co3_1 - (joined - (portRef CIN (instanceRef r_gctr_4)) - (portRef COUT (instanceRef r_gctr_3)))) - (net rcount_9 - (joined - (portRef A1 (instanceRef r_gctr_4)) - (portRef B (instanceRef XOR2_t0)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef Q (instanceRef FF_62)) - (portRef D (instanceRef FF_52)) - (portRef D (instanceRef FF_42)))) - (net rden_i - (joined - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef Z (instanceRef AND2_t19)) - (portRef OCER (instanceRef pdp_ram_0_0_1)) - (portRef CER (instanceRef pdp_ram_0_0_1)) - (portRef OCER (instanceRef pdp_ram_0_1_0)) - (portRef CER (instanceRef pdp_ram_0_1_0)) - (portRef SP (instanceRef FF_71)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_42)) - (portRef B1 (instanceRef empty_cmp_ci_a)))) - (net cmp_ci - (joined - (portRef CIN (instanceRef empty_cmp_0)) - (portRef COUT (instanceRef empty_cmp_ci_a)))) - (net wcount_r0 - (joined - (portRef B0 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_14)))) - (net wcount_r1 - (joined - (portRef B1 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_15)))) - (net rcount_0 - (joined - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A (instanceRef XOR2_t8)) - (portRef Q (instanceRef FF_71)) - (portRef D (instanceRef FF_51)) - (portRef A0 (instanceRef r_gctr_0)))) - (net rcount_1 - (joined - (portRef A1 (instanceRef empty_cmp_0)) - (portRef B (instanceRef XOR2_t8)) - (portRef A (instanceRef XOR2_t7)) - (portRef Q (instanceRef FF_70)) - (portRef D (instanceRef FF_50)) - (portRef A1 (instanceRef r_gctr_0)))) - (net co0_2 - (joined - (portRef CIN (instanceRef empty_cmp_1)) - (portRef COUT (instanceRef empty_cmp_0)))) - (net wcount_r2 - (joined - (portRef B0 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_16)))) - (net wcount_r3 - (joined - (portRef B1 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_17)))) - (net rcount_2 - (joined - (portRef A0 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t7)) - (portRef A (instanceRef XOR2_t6)) - (portRef Q (instanceRef FF_69)) - (portRef D (instanceRef FF_49)) - (portRef A0 (instanceRef r_gctr_1)))) - (net rcount_3 - (joined - (portRef A1 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t6)) - (portRef A (instanceRef XOR2_t5)) - (portRef Q (instanceRef FF_68)) - (portRef D (instanceRef FF_48)) - (portRef A1 (instanceRef r_gctr_1)))) - (net co1_2 - (joined - (portRef CIN (instanceRef empty_cmp_2)) - (portRef COUT (instanceRef empty_cmp_1)))) - (net wcount_r4 - (joined - (portRef B0 (instanceRef empty_cmp_2)) - (portRef DO0 (instanceRef LUT4_18)))) - (net wcount_r5 - (joined - (portRef B1 (instanceRef empty_cmp_2)) - (portRef DO0 (instanceRef LUT4_19)))) - (net rcount_4 - (joined - (portRef A0 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t5)) - (portRef A (instanceRef XOR2_t4)) - (portRef Q (instanceRef FF_67)) - (portRef D (instanceRef FF_47)) - (portRef A0 (instanceRef r_gctr_2)))) - (net rcount_5 - (joined - (portRef A1 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t4)) - (portRef A (instanceRef XOR2_t3)) - (portRef Q (instanceRef FF_66)) - (portRef D (instanceRef FF_46)) - (portRef A1 (instanceRef r_gctr_2)))) - (net co2_2 - (joined - (portRef CIN (instanceRef empty_cmp_3)) - (portRef COUT (instanceRef empty_cmp_2)))) - (net w_g2b_xor_cluster_0 - (joined - (portRef B0 (instanceRef empty_cmp_3)) - (portRef DO0 (instanceRef LUT4_23)) - (portRef AD0 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_14)))) - (net wcount_r7 - (joined - (portRef B1 (instanceRef empty_cmp_3)) - (portRef DO0 (instanceRef LUT4_20)) - (portRef AD0 (instanceRef LUT4_18)))) - (net rcount_6 - (joined - (portRef A0 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t3)) - (portRef A (instanceRef XOR2_t2)) - (portRef Q (instanceRef FF_65)) - (portRef D (instanceRef FF_45)) - (portRef A0 (instanceRef r_gctr_3)))) - (net rcount_7 - (joined - (portRef A1 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t2)) - (portRef A (instanceRef XOR2_t1)) - (portRef Q (instanceRef FF_64)) - (portRef D (instanceRef FF_44)) - (portRef A1 (instanceRef r_gctr_3)))) - (net co3_2 - (joined - (portRef CIN (instanceRef empty_cmp_4)) - (portRef COUT (instanceRef empty_cmp_3)))) - (net wcount_r8 - (joined - (portRef B0 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_19)))) - (net empty_cmp_clr - (joined - (portRef B1 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_2)))) - (net rcount_8 - (joined - (portRef A0 (instanceRef empty_cmp_4)) - (portRef B (instanceRef XOR2_t1)) - (portRef A (instanceRef XOR2_t0)) - (portRef Q (instanceRef FF_63)) - (portRef D (instanceRef FF_43)) - (portRef A0 (instanceRef r_gctr_4)))) - (net empty_cmp_set - (joined - (portRef A1 (instanceRef empty_cmp_4)) - (portRef DO0 (instanceRef LUT4_3)))) - (net empty_d - (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)))) - (net empty_d_c - (joined - (portRef CIN (instanceRef a0)) - (portRef COUT (instanceRef empty_cmp_4)))) - (net wren_i - (joined - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef Z (instanceRef AND2_t20)) - (portRef CEW (instanceRef pdp_ram_0_0_1)) - (portRef CEW (instanceRef pdp_ram_0_1_0)) - (portRef SP (instanceRef FF_101)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_72)) - (portRef B1 (instanceRef full_cmp_ci_a)))) - (net cmp_ci_1 - (joined - (portRef CIN (instanceRef full_cmp_0)) - (portRef COUT (instanceRef full_cmp_ci_a)))) - (net rcount_w0 - (joined - (portRef B0 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_4)))) - (net rcount_w1 - (joined - (portRef B1 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_5)))) - (net wcount_0 - (joined - (portRef A0 (instanceRef full_cmp_0)) - (portRef A (instanceRef XOR2_t17)) - (portRef Q (instanceRef FF_101)) - (portRef D (instanceRef FF_81)) - (portRef A0 (instanceRef w_gctr_0)))) - (net wcount_1 - (joined - (portRef A1 (instanceRef full_cmp_0)) - (portRef B (instanceRef XOR2_t17)) - (portRef A (instanceRef XOR2_t16)) - (portRef Q (instanceRef FF_100)) - (portRef D (instanceRef FF_80)) - (portRef A1 (instanceRef w_gctr_0)))) - (net co0_3 - (joined - (portRef CIN (instanceRef full_cmp_1)) - (portRef COUT (instanceRef full_cmp_0)))) - (net rcount_w2 - (joined - (portRef B0 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_6)))) - (net rcount_w3 - (joined - (portRef B1 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_7)))) - (net wcount_2 - (joined - (portRef A0 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t16)) - (portRef A (instanceRef XOR2_t15)) - (portRef Q (instanceRef FF_99)) - (portRef D (instanceRef FF_79)) - (portRef A0 (instanceRef w_gctr_1)))) - (net wcount_3 - (joined - (portRef A1 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t15)) - (portRef A (instanceRef XOR2_t14)) - (portRef Q (instanceRef FF_98)) - (portRef D (instanceRef FF_78)) - (portRef A1 (instanceRef w_gctr_1)))) - (net co1_3 - (joined - (portRef CIN (instanceRef full_cmp_2)) - (portRef COUT (instanceRef full_cmp_1)))) - (net rcount_w4 - (joined - (portRef B0 (instanceRef full_cmp_2)) - (portRef DO0 (instanceRef LUT4_8)))) - (net rcount_w5 - (joined - (portRef B1 (instanceRef full_cmp_2)) - (portRef DO0 (instanceRef LUT4_9)))) - (net wcount_4 - (joined - (portRef A0 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t14)) - (portRef A (instanceRef XOR2_t13)) - (portRef Q (instanceRef FF_97)) - (portRef D (instanceRef FF_77)) - (portRef A0 (instanceRef w_gctr_2)))) - (net wcount_5 - (joined - (portRef A1 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t13)) - (portRef A (instanceRef XOR2_t12)) - (portRef Q (instanceRef FF_96)) - (portRef D (instanceRef FF_76)) - (portRef A1 (instanceRef w_gctr_2)))) - (net co2_3 - (joined - (portRef CIN (instanceRef full_cmp_3)) - (portRef COUT (instanceRef full_cmp_2)))) - (net r_g2b_xor_cluster_0 - (joined - (portRef B0 (instanceRef full_cmp_3)) - (portRef DO0 (instanceRef LUT4_13)) - (portRef AD0 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_4)))) - (net rcount_w7 - (joined - (portRef B1 (instanceRef full_cmp_3)) - (portRef DO0 (instanceRef LUT4_10)) - (portRef AD0 (instanceRef LUT4_8)))) - (net wcount_6 - (joined - (portRef A0 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t12)) - (portRef A (instanceRef XOR2_t11)) - (portRef Q (instanceRef FF_95)) - (portRef D (instanceRef FF_75)) - (portRef A0 (instanceRef w_gctr_3)))) - (net wcount_7 - (joined - (portRef A1 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t11)) - (portRef A (instanceRef XOR2_t10)) - (portRef Q (instanceRef FF_94)) - (portRef D (instanceRef FF_74)) - (portRef A1 (instanceRef w_gctr_3)))) - (net co3_3 - (joined - (portRef CIN (instanceRef full_cmp_4)) - (portRef COUT (instanceRef full_cmp_3)))) - (net rcount_w8 - (joined - (portRef B0 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_9)))) - (net full_cmp_clr - (joined - (portRef B1 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_0)))) - (net wcount_8 - (joined - (portRef A0 (instanceRef full_cmp_4)) - (portRef B (instanceRef XOR2_t10)) - (portRef A (instanceRef XOR2_t9)) - (portRef Q (instanceRef FF_93)) - (portRef D (instanceRef FF_73)) - (portRef A0 (instanceRef w_gctr_4)))) - (net full_cmp_set - (joined - (portRef A1 (instanceRef full_cmp_4)) - (portRef DO0 (instanceRef LUT4_1)))) - (net full_d - (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)))) - (net scuba_vhi - (joined - (portRef Z (instanceRef scuba_vhi_inst)) - (portRef CSW0 (instanceRef pdp_ram_0_0_1)) - (portRef BE3 (instanceRef pdp_ram_0_0_1)) - (portRef BE2 (instanceRef pdp_ram_0_0_1)) - (portRef BE1 (instanceRef pdp_ram_0_0_1)) - (portRef BE0 (instanceRef pdp_ram_0_0_1)) - (portRef CSW0 (instanceRef pdp_ram_0_1_0)) - (portRef BE3 (instanceRef pdp_ram_0_1_0)) - (portRef BE2 (instanceRef pdp_ram_0_1_0)) - (portRef BE1 (instanceRef pdp_ram_0_1_0)) - (portRef BE0 (instanceRef pdp_ram_0_1_0)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef a1)) - (portRef D0 (instanceRef a1)))) - (net scuba_vlo - (joined - (portRef Z (instanceRef scuba_vlo_inst)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef CSR2 (instanceRef pdp_ram_0_0_1)) - (portRef CSW2 (instanceRef pdp_ram_0_0_1)) - (portRef CSR1 (instanceRef pdp_ram_0_0_1)) - (portRef CSW1 (instanceRef pdp_ram_0_0_1)) - (portRef CSR0 (instanceRef pdp_ram_0_0_1)) - (portRef ADR4 (instanceRef pdp_ram_0_0_1)) - (portRef ADR3 (instanceRef pdp_ram_0_0_1)) - (portRef ADR2 (instanceRef pdp_ram_0_0_1)) - (portRef ADR1 (instanceRef pdp_ram_0_0_1)) - (portRef ADR0 (instanceRef pdp_ram_0_0_1)) - (portRef CSR2 (instanceRef pdp_ram_0_1_0)) - (portRef CSW2 (instanceRef pdp_ram_0_1_0)) - (portRef CSR1 (instanceRef pdp_ram_0_1_0)) - (portRef CSW1 (instanceRef pdp_ram_0_1_0)) - (portRef CSR0 (instanceRef pdp_ram_0_1_0)) - (portRef ADR4 (instanceRef pdp_ram_0_1_0)) - (portRef ADR3 (instanceRef pdp_ram_0_1_0)) - (portRef ADR2 (instanceRef pdp_ram_0_1_0)) - (portRef ADR1 (instanceRef pdp_ram_0_1_0)) - (portRef ADR0 (instanceRef pdp_ram_0_1_0)) - (portRef DI35 (instanceRef pdp_ram_0_1_0)) - (portRef DI17 (instanceRef pdp_ram_0_1_0)) - (portRef DI34 (instanceRef pdp_ram_0_1_0)) - (portRef DI16 (instanceRef pdp_ram_0_1_0)) - (portRef DI33 (instanceRef pdp_ram_0_1_0)) - (portRef DI15 (instanceRef pdp_ram_0_1_0)) - (portRef DI32 (instanceRef pdp_ram_0_1_0)) - (portRef DI14 (instanceRef pdp_ram_0_1_0)) - (portRef DI31 (instanceRef pdp_ram_0_1_0)) - (portRef DI13 (instanceRef pdp_ram_0_1_0)) - (portRef DI30 (instanceRef pdp_ram_0_1_0)) - (portRef DI12 (instanceRef pdp_ram_0_1_0)) - (portRef DI29 (instanceRef pdp_ram_0_1_0)) - (portRef DI11 (instanceRef pdp_ram_0_1_0)) - (portRef DI28 (instanceRef pdp_ram_0_1_0)) - (portRef DI10 (instanceRef pdp_ram_0_1_0)) - (portRef DI27 (instanceRef pdp_ram_0_1_0)) - (portRef DI9 (instanceRef pdp_ram_0_1_0)) - (portRef DI26 (instanceRef pdp_ram_0_1_0)) - (portRef DI8 (instanceRef pdp_ram_0_1_0)) - (portRef DI25 (instanceRef pdp_ram_0_1_0)) - (portRef DI7 (instanceRef pdp_ram_0_1_0)) - (portRef DI24 (instanceRef pdp_ram_0_1_0)) - (portRef DI6 (instanceRef pdp_ram_0_1_0)) - (portRef DI23 (instanceRef pdp_ram_0_1_0)) - (portRef DI5 (instanceRef pdp_ram_0_1_0)) - (portRef DI22 (instanceRef pdp_ram_0_1_0)) - (portRef DI4 (instanceRef pdp_ram_0_1_0)) - (portRef DI21 (instanceRef pdp_ram_0_1_0)) - (portRef DI20 (instanceRef pdp_ram_0_1_0)) - (portRef DI19 (instanceRef pdp_ram_0_1_0)) - (portRef DI18 (instanceRef pdp_ram_0_1_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef A0 (instanceRef a1)))) - (net full_d_c - (joined - (portRef CIN (instanceRef a1)) - (portRef COUT (instanceRef full_cmp_4)))) - (net Full - (joined - (portRef Full) - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)))) - (net Empty - (joined - (portRef Empty) - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)))) - (net dataout39 - (joined - (portRef (member Q 0)) - (portRef DO21 (instanceRef pdp_ram_0_1_0)))) - (net dataout38 - (joined - (portRef (member Q 1)) - (portRef DO20 (instanceRef pdp_ram_0_1_0)))) - (net dataout37 - (joined - (portRef (member Q 2)) - (portRef DO19 (instanceRef pdp_ram_0_1_0)))) - (net dataout36 - (joined - (portRef (member Q 3)) - (portRef DO18 (instanceRef pdp_ram_0_1_0)))) - (net dataout35 - (joined - (portRef (member Q 4)) - (portRef DO17 (instanceRef pdp_ram_0_0_1)))) - (net dataout34 - (joined - (portRef (member Q 5)) - (portRef DO16 (instanceRef pdp_ram_0_0_1)))) - (net dataout33 - (joined - (portRef (member Q 6)) - (portRef DO15 (instanceRef pdp_ram_0_0_1)))) - (net dataout32 - (joined - (portRef (member Q 7)) - (portRef DO14 (instanceRef pdp_ram_0_0_1)))) - (net dataout31 - (joined - (portRef (member Q 8)) - (portRef DO13 (instanceRef pdp_ram_0_0_1)))) - (net dataout30 - (joined - (portRef (member Q 9)) - (portRef DO12 (instanceRef pdp_ram_0_0_1)))) - (net dataout29 - (joined - (portRef (member Q 10)) - (portRef DO11 (instanceRef pdp_ram_0_0_1)))) - (net dataout28 - (joined - (portRef (member Q 11)) - (portRef DO10 (instanceRef pdp_ram_0_0_1)))) - (net dataout27 - (joined - (portRef (member Q 12)) - (portRef DO9 (instanceRef pdp_ram_0_0_1)))) - (net dataout26 - (joined - (portRef (member Q 13)) - (portRef DO8 (instanceRef pdp_ram_0_0_1)))) - (net dataout25 - (joined - (portRef (member Q 14)) - (portRef DO7 (instanceRef pdp_ram_0_0_1)))) - (net dataout24 - (joined - (portRef (member Q 15)) - (portRef DO6 (instanceRef pdp_ram_0_0_1)))) - (net dataout23 - (joined - (portRef (member Q 16)) - (portRef DO5 (instanceRef pdp_ram_0_0_1)))) - (net dataout22 - (joined - (portRef (member Q 17)) - (portRef DO4 (instanceRef pdp_ram_0_0_1)))) - (net dataout21 - (joined - (portRef (member Q 18)) - (portRef DO3 (instanceRef pdp_ram_0_0_1)))) - (net dataout20 - (joined - (portRef (member Q 19)) - (portRef DO2 (instanceRef pdp_ram_0_0_1)))) - (net dataout19 - (joined - (portRef (member Q 20)) - (portRef DO1 (instanceRef pdp_ram_0_0_1)))) - (net dataout18 - (joined - (portRef (member Q 21)) - (portRef DO0 (instanceRef pdp_ram_0_0_1)))) - (net dataout17 - (joined - (portRef (member Q 22)) - (portRef DO35 (instanceRef pdp_ram_0_0_1)))) - (net dataout16 - (joined - (portRef (member Q 23)) - (portRef DO34 (instanceRef pdp_ram_0_0_1)))) - (net dataout15 - (joined - (portRef (member Q 24)) - (portRef DO33 (instanceRef pdp_ram_0_0_1)))) - (net dataout14 - (joined - (portRef (member Q 25)) - (portRef DO32 (instanceRef pdp_ram_0_0_1)))) - (net dataout13 - (joined - (portRef (member Q 26)) - (portRef DO31 (instanceRef pdp_ram_0_0_1)))) - (net dataout12 - (joined - (portRef (member Q 27)) - (portRef DO30 (instanceRef pdp_ram_0_0_1)))) - (net dataout11 - (joined - (portRef (member Q 28)) - (portRef DO29 (instanceRef pdp_ram_0_0_1)))) - (net dataout10 - (joined - (portRef (member Q 29)) - (portRef DO28 (instanceRef pdp_ram_0_0_1)))) - (net dataout9 - (joined - (portRef (member Q 30)) - (portRef DO27 (instanceRef pdp_ram_0_0_1)))) - (net dataout8 - (joined - (portRef (member Q 31)) - (portRef DO26 (instanceRef pdp_ram_0_0_1)))) - (net dataout7 - (joined - (portRef (member Q 32)) - (portRef DO25 (instanceRef pdp_ram_0_0_1)))) - (net dataout6 - (joined - (portRef (member Q 33)) - (portRef DO24 (instanceRef pdp_ram_0_0_1)))) - (net dataout5 - (joined - (portRef (member Q 34)) - (portRef DO23 (instanceRef pdp_ram_0_0_1)))) - (net dataout4 - (joined - (portRef (member Q 35)) - (portRef DO22 (instanceRef pdp_ram_0_0_1)))) - (net dataout3 - (joined - (portRef (member Q 36)) - (portRef DO21 (instanceRef pdp_ram_0_0_1)))) - (net dataout2 - (joined - (portRef (member Q 37)) - (portRef DO20 (instanceRef pdp_ram_0_0_1)))) - (net dataout1 - (joined - (portRef (member Q 38)) - (portRef DO19 (instanceRef pdp_ram_0_0_1)))) - (net dataout0 - (joined - (portRef (member Q 39)) - (portRef DO18 (instanceRef pdp_ram_0_0_1)))) - (net RPRst - (joined - (portRef RPReset) - (portRef B (instanceRef OR2_t18)))) - (net reset - (joined - (portRef Reset) - (portRef A (instanceRef OR2_t18)) - (portRef RST (instanceRef pdp_ram_0_0_1)) - (portRef RST (instanceRef pdp_ram_0_1_0)) - (portRef PD (instanceRef FF_101)) - (portRef CD (instanceRef FF_100)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_0)))) - (net rden - (joined - (portRef RdEn) - (portRef A (instanceRef AND2_t19)))) - (net wren - (joined - (portRef WrEn) - (portRef A (instanceRef AND2_t20)))) - (net rclk - (joined - (portRef RdClock) - (portRef CLKR (instanceRef pdp_ram_0_0_1)) - (portRef CLKR (instanceRef pdp_ram_0_1_0)) - (portRef CK (instanceRef FF_71)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_1)))) - (net wclk - (joined - (portRef WrClock) - (portRef CLKW (instanceRef pdp_ram_0_0_1)) - (portRef CLKW (instanceRef pdp_ram_0_1_0)) - (portRef CK (instanceRef FF_101)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_0)))) - (net datain39 - (joined - (portRef (member Data 0)) - (portRef DI3 (instanceRef pdp_ram_0_1_0)))) - (net datain38 - (joined - (portRef (member Data 1)) - (portRef DI2 (instanceRef pdp_ram_0_1_0)))) - (net datain37 - (joined - (portRef (member Data 2)) - (portRef DI1 (instanceRef pdp_ram_0_1_0)))) - (net datain36 - (joined - (portRef (member Data 3)) - (portRef DI0 (instanceRef pdp_ram_0_1_0)))) - (net datain35 - (joined - (portRef (member Data 4)) - (portRef DI35 (instanceRef pdp_ram_0_0_1)))) - (net datain34 - (joined - (portRef (member Data 5)) - (portRef DI34 (instanceRef pdp_ram_0_0_1)))) - (net datain33 - (joined - (portRef (member Data 6)) - (portRef DI33 (instanceRef pdp_ram_0_0_1)))) - (net datain32 - (joined - (portRef (member Data 7)) - (portRef DI32 (instanceRef pdp_ram_0_0_1)))) - (net datain31 - (joined - (portRef (member Data 8)) - (portRef DI31 (instanceRef pdp_ram_0_0_1)))) - (net datain30 - (joined - (portRef (member Data 9)) - (portRef DI30 (instanceRef pdp_ram_0_0_1)))) - (net datain29 - (joined - (portRef (member Data 10)) - (portRef DI29 (instanceRef pdp_ram_0_0_1)))) - (net datain28 - (joined - (portRef (member Data 11)) - (portRef DI28 (instanceRef pdp_ram_0_0_1)))) - (net datain27 - (joined - (portRef (member Data 12)) - (portRef DI27 (instanceRef pdp_ram_0_0_1)))) - (net datain26 - (joined - (portRef (member Data 13)) - (portRef DI26 (instanceRef pdp_ram_0_0_1)))) - (net datain25 - (joined - (portRef (member Data 14)) - (portRef DI25 (instanceRef pdp_ram_0_0_1)))) - (net datain24 - (joined - (portRef (member Data 15)) - (portRef DI24 (instanceRef pdp_ram_0_0_1)))) - (net datain23 - (joined - (portRef (member Data 16)) - (portRef DI23 (instanceRef pdp_ram_0_0_1)))) - (net datain22 - (joined - (portRef (member Data 17)) - (portRef DI22 (instanceRef pdp_ram_0_0_1)))) - (net datain21 - (joined - (portRef (member Data 18)) - (portRef DI21 (instanceRef pdp_ram_0_0_1)))) - (net datain20 - (joined - (portRef (member Data 19)) - (portRef DI20 (instanceRef pdp_ram_0_0_1)))) - (net datain19 - (joined - (portRef (member Data 20)) - (portRef DI19 (instanceRef pdp_ram_0_0_1)))) - (net datain18 - (joined - (portRef (member Data 21)) - (portRef DI18 (instanceRef pdp_ram_0_0_1)))) - (net datain17 - (joined - (portRef (member Data 22)) - (portRef DI17 (instanceRef pdp_ram_0_0_1)))) - (net datain16 - (joined - (portRef (member Data 23)) - (portRef DI16 (instanceRef pdp_ram_0_0_1)))) - (net datain15 - (joined - (portRef (member Data 24)) - (portRef DI15 (instanceRef pdp_ram_0_0_1)))) - (net datain14 - (joined - (portRef (member Data 25)) - (portRef DI14 (instanceRef pdp_ram_0_0_1)))) - (net datain13 - (joined - (portRef (member Data 26)) - (portRef DI13 (instanceRef pdp_ram_0_0_1)))) - (net datain12 - (joined - (portRef (member Data 27)) - (portRef DI12 (instanceRef pdp_ram_0_0_1)))) - (net datain11 - (joined - (portRef (member Data 28)) - (portRef DI11 (instanceRef pdp_ram_0_0_1)))) - (net datain10 - (joined - (portRef (member Data 29)) - (portRef DI10 (instanceRef pdp_ram_0_0_1)))) - (net datain9 - (joined - (portRef (member Data 30)) - (portRef DI9 (instanceRef pdp_ram_0_0_1)))) - (net datain8 - (joined - (portRef (member Data 31)) - (portRef DI8 (instanceRef pdp_ram_0_0_1)))) - (net datain7 - (joined - (portRef (member Data 32)) - (portRef DI7 (instanceRef pdp_ram_0_0_1)))) - (net datain6 - (joined - (portRef (member Data 33)) - (portRef DI6 (instanceRef pdp_ram_0_0_1)))) - (net datain5 - (joined - (portRef (member Data 34)) - (portRef DI5 (instanceRef pdp_ram_0_0_1)))) - (net datain4 - (joined - (portRef (member Data 35)) - (portRef DI4 (instanceRef pdp_ram_0_0_1)))) - (net datain3 - (joined - (portRef (member Data 36)) - (portRef DI3 (instanceRef pdp_ram_0_0_1)))) - (net datain2 - (joined - (portRef (member Data 37)) - (portRef DI2 (instanceRef pdp_ram_0_0_1)))) - (net datain1 - (joined - (portRef (member Data 38)) - (portRef DI1 (instanceRef pdp_ram_0_0_1)))) - (net datain0 - (joined - (portRef (member Data 39)) - (portRef DI0 (instanceRef pdp_ram_0_0_1)))))))) - (design fifo40_dc - (cellRef fifo40_dc - (libraryRef ORCLIB))) -) diff --git a/fifo40_dc/fifo40_dc.fdc b/fifo40_dc/fifo40_dc.fdc deleted file mode 100644 index 6fbcac9..0000000 --- a/fifo40_dc/fifo40_dc.fdc +++ /dev/null @@ -1,2 +0,0 @@ -###==== Start Configuration - diff --git a/fifo40_dc/fifo40_dc.lpc b/fifo40_dc/fifo40_dc.lpc deleted file mode 100644 index 9deb02c..0000000 --- a/fifo40_dc/fifo40_dc.lpc +++ /dev/null @@ -1,53 +0,0 @@ -[Device] -Family=ecp5um5g -PartType=LFE5UM5G-45F -PartName=LFE5UM5G-45F-8BG381C -SpeedGrade=8 -Package=CABGA381 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.8 -ModuleName=fifo40_dc -SourceFormat=verilog -ParameterFileVersion=1.0 -Date=02/09/2021 -Time=13:19:24 - -[Parameters] -Verilog=1 -VHDL=0 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=512 -Width=40 -RDepth=512 -RWidth=40 -regout=0 -ClockEn=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -Reset=Async -Reset1=Sync -RDataCount=0 -WDataCount=0 -EnECC=0 - -[Command] -cmd_line= -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 diff --git a/fifo40_dc/fifo40_dc.sbx b/fifo40_dc/fifo40_dc.sbx deleted file mode 100644 index ec1e426..0000000 --- a/fifo40_dc/fifo40_dc.sbx +++ /dev/null @@ -1,264 +0,0 @@ - - - - Lattice Semiconductor Corporation - LEGACY - FIFO_DC - 5.8 - - - Diamond_Simulation - simulation - - ./fifo40_dc.v - verilogSource - - - - Diamond_Synthesis - synthesis - - ./fifo40_dc.v - verilogSource - - - - - - Configuration - none - ${sbp_path}/generate_core.tcl - CONFIG - - - - - - - - LFE5UM5G-45F-8BG381C - synplify - 2021-02-09.01:19:26 PM - 2021-02-09.01:19:26 PM - 3.11.2.446 - Verilog - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - - - Family - ecp5um5g - - - OperatingCondition - COM - - - Package - CABGA381 - - - PartName - LFE5UM5G-45F-8BG381C - - - PartType - LFE5UM5G-45F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - FIFO_DC - - - CoreRevision - 5.8 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 02/09/2021 - - - ModuleName - fifo40_dc - - - ParameterFileVersion - 1.0 - - - SourceFormat - verilog - - - Time - 13:19:24 - - - VendorName - Lattice Semiconductor Corporation - - - - ClockEn - 0 - - - CtrlByRdEn - 0 - - - Depth - 512 - - - Destination - Synplicity - - - EDIF - 1 - - - EmpFlg - 0 - - - EnECC - 0 - - - Expression - BusA(0 to 7) - - - FIFOImp - EBR Based - - - FullFlg - 0 - - - IO - 0 - - - Order - Big Endian [MSB:LSB] - - - PeAssert - 10 - - - PeDeassert - 12 - - - PeMode - Static - Dual Threshold - - - PfAssert - 508 - - - PfDeassert - 506 - - - PfMode - Static - Dual Threshold - - - RDataCount - 0 - - - RDepth - 512 - - - RWidth - 40 - - - Reset - Async - - - Reset1 - Sync - - - VHDL - 0 - - - Verilog - 1 - - - WDataCount - 0 - - - Width - 40 - - - regout - 0 - - - - cmd_line - -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 - - - - - - - LATTICE - LOCAL - fifo40_dc - 1.0 - - - - diff --git a/fifo40_dc/fifo40_dc.srp b/fifo40_dc/fifo40_dc.srp deleted file mode 100644 index 15f9727..0000000 --- a/fifo40_dc/fifo40_dc.srp +++ /dev/null @@ -1,40 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Tue Feb 9 13:19:26 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc - Circuit name : fifo40_dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[39:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo40_dc.edn - Verilog output : fifo40_dc.v - Verilog template : fifo40_dc_tmpl.v - Verilog testbench: tb_fifo40_dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo40_dc.srp - Element Usage : - CCU2C : 26 - AND2 : 2 - FD1P3BX : 2 - FD1P3DX : 58 - FD1S3BX : 1 - FD1S3DX : 41 - INV : 2 - OR2 : 1 - ROM16X1A : 24 - XOR2 : 18 - PDPW16KD : 2 - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 diff --git a/fifo40_dc/fifo40_dc.v b/fifo40_dc/fifo40_dc.v deleted file mode 100644 index 77ff46f..0000000 --- a/fifo40_dc/fifo40_dc.v +++ /dev/null @@ -1,1114 +0,0 @@ -/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 */ -/* Module Version: 5.8 */ -/* /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.fdc */ -/* Tue Feb 9 13:19:26 2021 */ - - -`timescale 1 ns / 1 ps -module fifo40_dc (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, - Empty, Full)/* synthesis NGD_DRC_MASK=1 */; - input wire [39:0] Data; - input wire WrClock; - input wire RdClock; - input wire WrEn; - input wire RdEn; - input wire Reset; - input wire RPReset; - output wire [39:0] Q; - output wire Empty; - output wire Full; - - wire invout_1; - wire invout_0; - wire w_g2b_xor_cluster_1; - wire r_g2b_xor_cluster_1; - wire w_gdata_0; - wire w_gdata_1; - wire w_gdata_2; - wire w_gdata_3; - wire w_gdata_4; - wire w_gdata_5; - wire w_gdata_6; - wire w_gdata_7; - wire w_gdata_8; - wire wptr_0; - wire wptr_1; - wire wptr_2; - wire wptr_3; - wire wptr_4; - wire wptr_5; - wire wptr_6; - wire wptr_7; - wire wptr_8; - wire wptr_9; - wire r_gdata_0; - wire r_gdata_1; - wire r_gdata_2; - wire r_gdata_3; - wire r_gdata_4; - wire r_gdata_5; - wire r_gdata_6; - wire r_gdata_7; - wire r_gdata_8; - wire rptr_0; - wire rptr_1; - wire rptr_2; - wire rptr_3; - wire rptr_4; - wire rptr_5; - wire rptr_6; - wire rptr_7; - wire rptr_8; - wire rptr_9; - wire w_gcount_0; - wire w_gcount_1; - wire w_gcount_2; - wire w_gcount_3; - wire w_gcount_4; - wire w_gcount_5; - wire w_gcount_6; - wire w_gcount_7; - wire w_gcount_8; - wire w_gcount_9; - wire r_gcount_0; - wire r_gcount_1; - wire r_gcount_2; - wire r_gcount_3; - wire r_gcount_4; - wire r_gcount_5; - wire r_gcount_6; - wire r_gcount_7; - wire r_gcount_8; - wire r_gcount_9; - wire w_gcount_r20; - wire w_gcount_r0; - wire w_gcount_r21; - wire w_gcount_r1; - wire w_gcount_r22; - wire w_gcount_r2; - wire w_gcount_r23; - wire w_gcount_r3; - wire w_gcount_r24; - wire w_gcount_r4; - wire w_gcount_r25; - wire w_gcount_r5; - wire w_gcount_r26; - wire w_gcount_r6; - wire w_gcount_r27; - wire w_gcount_r7; - wire w_gcount_r28; - wire w_gcount_r8; - wire w_gcount_r29; - wire w_gcount_r9; - wire r_gcount_w20; - wire r_gcount_w0; - wire r_gcount_w21; - wire r_gcount_w1; - wire r_gcount_w22; - wire r_gcount_w2; - wire r_gcount_w23; - wire r_gcount_w3; - wire r_gcount_w24; - wire r_gcount_w4; - wire r_gcount_w25; - wire r_gcount_w5; - wire r_gcount_w26; - wire r_gcount_w6; - wire r_gcount_w27; - wire r_gcount_w7; - wire r_gcount_w28; - wire r_gcount_w8; - wire r_gcount_w29; - wire r_gcount_w9; - wire empty_i; - wire rRst; - wire full_i; - wire iwcount_0; - wire iwcount_1; - wire w_gctr_ci; - wire iwcount_2; - wire iwcount_3; - wire co0; - wire iwcount_4; - wire iwcount_5; - wire co1; - wire iwcount_6; - wire iwcount_7; - wire co2; - wire iwcount_8; - wire iwcount_9; - wire co4; - wire co3; - wire wcount_9; - wire ircount_0; - wire ircount_1; - wire r_gctr_ci; - wire ircount_2; - wire ircount_3; - wire co0_1; - wire ircount_4; - wire ircount_5; - wire co1_1; - wire ircount_6; - wire ircount_7; - wire co2_1; - wire ircount_8; - wire ircount_9; - wire co4_1; - wire co3_1; - wire rcount_9; - wire rden_i; - wire cmp_ci; - wire wcount_r0; - wire wcount_r1; - wire rcount_0; - wire rcount_1; - wire co0_2; - wire wcount_r2; - wire wcount_r3; - wire rcount_2; - wire rcount_3; - wire co1_2; - wire wcount_r4; - wire wcount_r5; - wire rcount_4; - wire rcount_5; - wire co2_2; - wire w_g2b_xor_cluster_0; - wire wcount_r7; - wire rcount_6; - wire rcount_7; - wire co3_2; - wire wcount_r8; - wire empty_cmp_clr; - wire rcount_8; - wire empty_cmp_set; - wire empty_d; - wire empty_d_c; - wire wren_i; - wire cmp_ci_1; - wire rcount_w0; - wire rcount_w1; - wire wcount_0; - wire wcount_1; - wire co0_3; - wire rcount_w2; - wire rcount_w3; - wire wcount_2; - wire wcount_3; - wire co1_3; - wire rcount_w4; - wire rcount_w5; - wire wcount_4; - wire wcount_5; - wire co2_3; - wire r_g2b_xor_cluster_0; - wire rcount_w7; - wire wcount_6; - wire wcount_7; - wire co3_3; - wire rcount_w8; - wire full_cmp_clr; - wire wcount_8; - wire full_cmp_set; - wire full_d; - wire scuba_vhi; - wire scuba_vlo; - wire full_d_c; - - AND2 AND2_t20 (.A(WrEn), .B(invout_1), .Z(wren_i)); - - INV INV_1 (.A(full_i), .Z(invout_1)); - - AND2 AND2_t19 (.A(RdEn), .B(invout_0), .Z(rden_i)); - - INV INV_0 (.A(empty_i), .Z(invout_0)); - - OR2 OR2_t18 (.A(Reset), .B(RPReset), .Z(rRst)); - - XOR2 XOR2_t17 (.A(wcount_0), .B(wcount_1), .Z(w_gdata_0)); - - XOR2 XOR2_t16 (.A(wcount_1), .B(wcount_2), .Z(w_gdata_1)); - - XOR2 XOR2_t15 (.A(wcount_2), .B(wcount_3), .Z(w_gdata_2)); - - XOR2 XOR2_t14 (.A(wcount_3), .B(wcount_4), .Z(w_gdata_3)); - - XOR2 XOR2_t13 (.A(wcount_4), .B(wcount_5), .Z(w_gdata_4)); - - XOR2 XOR2_t12 (.A(wcount_5), .B(wcount_6), .Z(w_gdata_5)); - - XOR2 XOR2_t11 (.A(wcount_6), .B(wcount_7), .Z(w_gdata_6)); - - XOR2 XOR2_t10 (.A(wcount_7), .B(wcount_8), .Z(w_gdata_7)); - - XOR2 XOR2_t9 (.A(wcount_8), .B(wcount_9), .Z(w_gdata_8)); - - XOR2 XOR2_t8 (.A(rcount_0), .B(rcount_1), .Z(r_gdata_0)); - - XOR2 XOR2_t7 (.A(rcount_1), .B(rcount_2), .Z(r_gdata_1)); - - XOR2 XOR2_t6 (.A(rcount_2), .B(rcount_3), .Z(r_gdata_2)); - - XOR2 XOR2_t5 (.A(rcount_3), .B(rcount_4), .Z(r_gdata_3)); - - XOR2 XOR2_t4 (.A(rcount_4), .B(rcount_5), .Z(r_gdata_4)); - - XOR2 XOR2_t3 (.A(rcount_5), .B(rcount_6), .Z(r_gdata_5)); - - XOR2 XOR2_t2 (.A(rcount_6), .B(rcount_7), .Z(r_gdata_6)); - - XOR2 XOR2_t1 (.A(rcount_7), .B(rcount_8), .Z(r_gdata_7)); - - XOR2 XOR2_t0 (.A(rcount_8), .B(rcount_9), .Z(r_gdata_8)); - - defparam LUT4_23.initval = 16'h6996 ; - ROM16X1A LUT4_23 (.AD3(w_gcount_r26), .AD2(w_gcount_r27), .AD1(w_gcount_r28), - .AD0(w_gcount_r29), .DO0(w_g2b_xor_cluster_0)); - - defparam LUT4_22.initval = 16'h6996 ; - ROM16X1A LUT4_22 (.AD3(w_gcount_r22), .AD2(w_gcount_r23), .AD1(w_gcount_r24), - .AD0(w_gcount_r25), .DO0(w_g2b_xor_cluster_1)); - - defparam LUT4_21.initval = 16'h6996 ; - ROM16X1A LUT4_21 (.AD3(w_gcount_r28), .AD2(w_gcount_r29), .AD1(scuba_vlo), - .AD0(scuba_vlo), .DO0(wcount_r8)); - - defparam LUT4_20.initval = 16'h6996 ; - ROM16X1A LUT4_20 (.AD3(w_gcount_r27), .AD2(w_gcount_r28), .AD1(w_gcount_r29), - .AD0(scuba_vlo), .DO0(wcount_r7)); - - defparam LUT4_19.initval = 16'h6996 ; - ROM16X1A LUT4_19 (.AD3(w_gcount_r25), .AD2(w_gcount_r26), .AD1(w_gcount_r27), - .AD0(wcount_r8), .DO0(wcount_r5)); - - defparam LUT4_18.initval = 16'h6996 ; - ROM16X1A LUT4_18 (.AD3(w_gcount_r24), .AD2(w_gcount_r25), .AD1(w_gcount_r26), - .AD0(wcount_r7), .DO0(wcount_r4)); - - defparam LUT4_17.initval = 16'h6996 ; - ROM16X1A LUT4_17 (.AD3(w_gcount_r23), .AD2(w_gcount_r24), .AD1(w_gcount_r25), - .AD0(w_g2b_xor_cluster_0), .DO0(wcount_r3)); - - defparam LUT4_16.initval = 16'h6996 ; - ROM16X1A LUT4_16 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(wcount_r2)); - - defparam LUT4_15.initval = 16'h6996 ; - ROM16X1A LUT4_15 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(w_gcount_r21), .AD0(scuba_vlo), .DO0(wcount_r1)); - - defparam LUT4_14.initval = 16'h6996 ; - ROM16X1A LUT4_14 (.AD3(w_g2b_xor_cluster_0), .AD2(w_g2b_xor_cluster_1), - .AD1(w_gcount_r20), .AD0(w_gcount_r21), .DO0(wcount_r0)); - - defparam LUT4_13.initval = 16'h6996 ; - ROM16X1A LUT4_13 (.AD3(r_gcount_w26), .AD2(r_gcount_w27), .AD1(r_gcount_w28), - .AD0(r_gcount_w29), .DO0(r_g2b_xor_cluster_0)); - - defparam LUT4_12.initval = 16'h6996 ; - ROM16X1A LUT4_12 (.AD3(r_gcount_w22), .AD2(r_gcount_w23), .AD1(r_gcount_w24), - .AD0(r_gcount_w25), .DO0(r_g2b_xor_cluster_1)); - - defparam LUT4_11.initval = 16'h6996 ; - ROM16X1A LUT4_11 (.AD3(r_gcount_w28), .AD2(r_gcount_w29), .AD1(scuba_vlo), - .AD0(scuba_vlo), .DO0(rcount_w8)); - - defparam LUT4_10.initval = 16'h6996 ; - ROM16X1A LUT4_10 (.AD3(r_gcount_w27), .AD2(r_gcount_w28), .AD1(r_gcount_w29), - .AD0(scuba_vlo), .DO0(rcount_w7)); - - defparam LUT4_9.initval = 16'h6996 ; - ROM16X1A LUT4_9 (.AD3(r_gcount_w25), .AD2(r_gcount_w26), .AD1(r_gcount_w27), - .AD0(rcount_w8), .DO0(rcount_w5)); - - defparam LUT4_8.initval = 16'h6996 ; - ROM16X1A LUT4_8 (.AD3(r_gcount_w24), .AD2(r_gcount_w25), .AD1(r_gcount_w26), - .AD0(rcount_w7), .DO0(rcount_w4)); - - defparam LUT4_7.initval = 16'h6996 ; - ROM16X1A LUT4_7 (.AD3(r_gcount_w23), .AD2(r_gcount_w24), .AD1(r_gcount_w25), - .AD0(r_g2b_xor_cluster_0), .DO0(rcount_w3)); - - defparam LUT4_6.initval = 16'h6996 ; - ROM16X1A LUT4_6 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(scuba_vlo), .AD0(scuba_vlo), .DO0(rcount_w2)); - - defparam LUT4_5.initval = 16'h6996 ; - ROM16X1A LUT4_5 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(r_gcount_w21), .AD0(scuba_vlo), .DO0(rcount_w1)); - - defparam LUT4_4.initval = 16'h6996 ; - ROM16X1A LUT4_4 (.AD3(r_g2b_xor_cluster_0), .AD2(r_g2b_xor_cluster_1), - .AD1(r_gcount_w20), .AD0(r_gcount_w21), .DO0(rcount_w0)); - - defparam LUT4_3.initval = 16'h0410 ; - ROM16X1A LUT4_3 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), - .DO0(empty_cmp_set)); - - defparam LUT4_2.initval = 16'h1004 ; - ROM16X1A LUT4_2 (.AD3(rptr_9), .AD2(rcount_9), .AD1(w_gcount_r29), .AD0(scuba_vlo), - .DO0(empty_cmp_clr)); - - defparam LUT4_1.initval = 16'h0140 ; - ROM16X1A LUT4_1 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), - .DO0(full_cmp_set)); - - defparam LUT4_0.initval = 16'h4001 ; - ROM16X1A LUT4_0 (.AD3(wptr_9), .AD2(wcount_9), .AD1(r_gcount_w29), .AD0(scuba_vlo), - .DO0(full_cmp_clr)); - - defparam pdp_ram_0_0_1.INIT_DATA = "STATIC" ; - defparam pdp_ram_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ; - defparam pdp_ram_0_0_1.CSDECODE_R = "0b000" ; - defparam pdp_ram_0_0_1.CSDECODE_W = "0b001" ; - defparam pdp_ram_0_0_1.GSR = "ENABLED" ; - defparam pdp_ram_0_0_1.RESETMODE = "ASYNC" ; - defparam pdp_ram_0_0_1.REGMODE = "NOREG" ; - defparam pdp_ram_0_0_1.DATA_WIDTH_R = 36 ; - defparam pdp_ram_0_0_1.DATA_WIDTH_W = 36 ; - PDPW16KD pdp_ram_0_0_1 (.DI35(Data[35]), .DI34(Data[34]), .DI33(Data[33]), - .DI32(Data[32]), .DI31(Data[31]), .DI30(Data[30]), .DI29(Data[29]), - .DI28(Data[28]), .DI27(Data[27]), .DI26(Data[26]), .DI25(Data[25]), - .DI24(Data[24]), .DI23(Data[23]), .DI22(Data[22]), .DI21(Data[21]), - .DI20(Data[20]), .DI19(Data[19]), .DI18(Data[18]), .DI17(Data[17]), - .DI16(Data[16]), .DI15(Data[15]), .DI14(Data[14]), .DI13(Data[13]), - .DI12(Data[12]), .DI11(Data[11]), .DI10(Data[10]), .DI9(Data[9]), - .DI8(Data[8]), .DI7(Data[7]), .DI6(Data[6]), .DI5(Data[5]), .DI4(Data[4]), - .DI3(Data[3]), .DI2(Data[2]), .DI1(Data[1]), .DI0(Data[0]), .ADW8(wptr_8), - .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), .ADW4(wptr_4), .ADW3(wptr_3), - .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), .BE3(scuba_vhi), .BE2(scuba_vhi), - .BE1(scuba_vhi), .BE0(scuba_vhi), .CEW(wren_i), .CLKW(WrClock), - .CSW2(scuba_vlo), .CSW1(scuba_vlo), .CSW0(scuba_vhi), .ADR13(rptr_8), - .ADR12(rptr_7), .ADR11(rptr_6), .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), - .ADR7(rptr_2), .ADR6(rptr_1), .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), - .ADR2(scuba_vlo), .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), - .OCER(rden_i), .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), - .CSR0(scuba_vlo), .RST(Reset), .DO35(Q[17]), .DO34(Q[16]), .DO33(Q[15]), - .DO32(Q[14]), .DO31(Q[13]), .DO30(Q[12]), .DO29(Q[11]), .DO28(Q[10]), - .DO27(Q[9]), .DO26(Q[8]), .DO25(Q[7]), .DO24(Q[6]), .DO23(Q[5]), - .DO22(Q[4]), .DO21(Q[3]), .DO20(Q[2]), .DO19(Q[1]), .DO18(Q[0]), - .DO17(Q[35]), .DO16(Q[34]), .DO15(Q[33]), .DO14(Q[32]), .DO13(Q[31]), - .DO12(Q[30]), .DO11(Q[29]), .DO10(Q[28]), .DO9(Q[27]), .DO8(Q[26]), - .DO7(Q[25]), .DO6(Q[24]), .DO5(Q[23]), .DO4(Q[22]), .DO3(Q[21]), - .DO2(Q[20]), .DO1(Q[19]), .DO0(Q[18])) - /* synthesis MEM_LPC_FILE="fifo40_dc.lpc" */ - /* synthesis MEM_INIT_FILE="" */; - - defparam pdp_ram_0_1_0.INIT_DATA = "STATIC" ; - defparam pdp_ram_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ; - defparam pdp_ram_0_1_0.CSDECODE_R = "0b000" ; - defparam pdp_ram_0_1_0.CSDECODE_W = "0b001" ; - defparam pdp_ram_0_1_0.GSR = "ENABLED" ; - defparam pdp_ram_0_1_0.RESETMODE = "ASYNC" ; - defparam pdp_ram_0_1_0.REGMODE = "NOREG" ; - defparam pdp_ram_0_1_0.DATA_WIDTH_R = 36 ; - defparam pdp_ram_0_1_0.DATA_WIDTH_W = 36 ; - PDPW16KD pdp_ram_0_1_0 (.DI35(scuba_vlo), .DI34(scuba_vlo), .DI33(scuba_vlo), - .DI32(scuba_vlo), .DI31(scuba_vlo), .DI30(scuba_vlo), .DI29(scuba_vlo), - .DI28(scuba_vlo), .DI27(scuba_vlo), .DI26(scuba_vlo), .DI25(scuba_vlo), - .DI24(scuba_vlo), .DI23(scuba_vlo), .DI22(scuba_vlo), .DI21(scuba_vlo), - .DI20(scuba_vlo), .DI19(scuba_vlo), .DI18(scuba_vlo), .DI17(scuba_vlo), - .DI16(scuba_vlo), .DI15(scuba_vlo), .DI14(scuba_vlo), .DI13(scuba_vlo), - .DI12(scuba_vlo), .DI11(scuba_vlo), .DI10(scuba_vlo), .DI9(scuba_vlo), - .DI8(scuba_vlo), .DI7(scuba_vlo), .DI6(scuba_vlo), .DI5(scuba_vlo), - .DI4(scuba_vlo), .DI3(Data[39]), .DI2(Data[38]), .DI1(Data[37]), - .DI0(Data[36]), .ADW8(wptr_8), .ADW7(wptr_7), .ADW6(wptr_6), .ADW5(wptr_5), - .ADW4(wptr_4), .ADW3(wptr_3), .ADW2(wptr_2), .ADW1(wptr_1), .ADW0(wptr_0), - .BE3(scuba_vhi), .BE2(scuba_vhi), .BE1(scuba_vhi), .BE0(scuba_vhi), - .CEW(wren_i), .CLKW(WrClock), .CSW2(scuba_vlo), .CSW1(scuba_vlo), - .CSW0(scuba_vhi), .ADR13(rptr_8), .ADR12(rptr_7), .ADR11(rptr_6), - .ADR10(rptr_5), .ADR9(rptr_4), .ADR8(rptr_3), .ADR7(rptr_2), .ADR6(rptr_1), - .ADR5(rptr_0), .ADR4(scuba_vlo), .ADR3(scuba_vlo), .ADR2(scuba_vlo), - .ADR1(scuba_vlo), .ADR0(scuba_vlo), .CER(rden_i), .OCER(rden_i), - .CLKR(RdClock), .CSR2(scuba_vlo), .CSR1(scuba_vlo), .CSR0(scuba_vlo), - .RST(Reset), .DO35(), .DO34(), .DO33(), .DO32(), .DO31(), .DO30(), - .DO29(), .DO28(), .DO27(), .DO26(), .DO25(), .DO24(), .DO23(), .DO22(), - .DO21(Q[39]), .DO20(Q[38]), .DO19(Q[37]), .DO18(Q[36]), .DO17(), - .DO16(), .DO15(), .DO14(), .DO13(), .DO12(), .DO11(), .DO10(), .DO9(), - .DO8(), .DO7(), .DO6(), .DO5(), .DO4(), .DO3(), .DO2(), .DO1(), - .DO0()) - /* synthesis MEM_LPC_FILE="fifo40_dc.lpc" */ - /* synthesis MEM_INIT_FILE="" */; - - FD1P3BX FF_101 (.D(iwcount_0), .SP(wren_i), .CK(WrClock), .PD(Reset), - .Q(wcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_100 (.D(iwcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_99 (.D(iwcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_98 (.D(iwcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_97 (.D(iwcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_96 (.D(iwcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_95 (.D(iwcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_94 (.D(iwcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_93 (.D(iwcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_92 (.D(iwcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_91 (.D(w_gdata_0), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_90 (.D(w_gdata_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_89 (.D(w_gdata_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_88 (.D(w_gdata_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_87 (.D(w_gdata_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_86 (.D(w_gdata_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_85 (.D(w_gdata_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_84 (.D(w_gdata_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_83 (.D(w_gdata_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_82 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(w_gcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_81 (.D(wcount_0), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_80 (.D(wcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_79 (.D(wcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_78 (.D(wcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_77 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_76 (.D(wcount_5), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_75 (.D(wcount_6), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_74 (.D(wcount_7), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_73 (.D(wcount_8), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_72 (.D(wcount_9), .SP(wren_i), .CK(WrClock), .CD(Reset), - .Q(wptr_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3BX FF_71 (.D(ircount_0), .SP(rden_i), .CK(RdClock), .PD(rRst), - .Q(rcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_70 (.D(ircount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_69 (.D(ircount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_68 (.D(ircount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_67 (.D(ircount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_66 (.D(ircount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_65 (.D(ircount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_64 (.D(ircount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_63 (.D(ircount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_62 (.D(ircount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(rcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_61 (.D(r_gdata_0), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_60 (.D(r_gdata_1), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_59 (.D(r_gdata_2), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_58 (.D(r_gdata_3), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_57 (.D(r_gdata_4), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_56 (.D(r_gdata_5), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_55 (.D(r_gdata_6), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_54 (.D(r_gdata_7), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_53 (.D(r_gdata_8), .SP(rden_i), .CK(RdClock), .CD(rRst), - .Q(r_gcount_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_52 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(r_gcount_9)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_51 (.D(rcount_0), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_0)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_50 (.D(rcount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_1)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_49 (.D(rcount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_2)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_48 (.D(rcount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_3)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_47 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_4)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_46 (.D(rcount_5), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_5)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_45 (.D(rcount_6), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_6)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_44 (.D(rcount_7), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_7)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_43 (.D(rcount_8), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_8)) - /* synthesis GSR="ENABLED" */; - - FD1P3DX FF_42 (.D(rcount_9), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_41 (.D(w_gcount_0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r0)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_40 (.D(w_gcount_1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r1)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_39 (.D(w_gcount_2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r2)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_38 (.D(w_gcount_3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r3)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_37 (.D(w_gcount_4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r4)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_36 (.D(w_gcount_5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r5)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_35 (.D(w_gcount_6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r6)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_34 (.D(w_gcount_7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r7)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_33 (.D(w_gcount_8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r8)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_32 (.D(w_gcount_9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_31 (.D(r_gcount_0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w0)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_30 (.D(r_gcount_1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w1)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_29 (.D(r_gcount_2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w2)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_28 (.D(r_gcount_3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w3)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_27 (.D(r_gcount_4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w4)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_26 (.D(r_gcount_5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w5)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_25 (.D(r_gcount_6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w6)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_24 (.D(r_gcount_7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w7)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_23 (.D(r_gcount_8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w8)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_22 (.D(r_gcount_9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w9)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_21 (.D(w_gcount_r0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r20)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_20 (.D(w_gcount_r1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r21)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_19 (.D(w_gcount_r2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r22)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_18 (.D(w_gcount_r3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r23)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_17 (.D(w_gcount_r4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r24)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_16 (.D(w_gcount_r5), .CK(RdClock), .CD(Reset), .Q(w_gcount_r25)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_15 (.D(w_gcount_r6), .CK(RdClock), .CD(Reset), .Q(w_gcount_r26)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_14 (.D(w_gcount_r7), .CK(RdClock), .CD(Reset), .Q(w_gcount_r27)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_13 (.D(w_gcount_r8), .CK(RdClock), .CD(Reset), .Q(w_gcount_r28)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_12 (.D(w_gcount_r9), .CK(RdClock), .CD(Reset), .Q(w_gcount_r29)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_11 (.D(r_gcount_w0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w20)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_10 (.D(r_gcount_w1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w21)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_9 (.D(r_gcount_w2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w22)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_8 (.D(r_gcount_w3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w23)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_7 (.D(r_gcount_w4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w24)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_6 (.D(r_gcount_w5), .CK(WrClock), .CD(rRst), .Q(r_gcount_w25)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_5 (.D(r_gcount_w6), .CK(WrClock), .CD(rRst), .Q(r_gcount_w26)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_4 (.D(r_gcount_w7), .CK(WrClock), .CD(rRst), .Q(r_gcount_w27)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_3 (.D(r_gcount_w8), .CK(WrClock), .CD(rRst), .Q(r_gcount_w28)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_2 (.D(r_gcount_w9), .CK(WrClock), .CD(rRst), .Q(r_gcount_w29)) - /* synthesis GSR="ENABLED" */; - - FD1S3BX FF_1 (.D(empty_d), .CK(RdClock), .PD(rRst), .Q(empty_i)) - /* synthesis GSR="ENABLED" */; - - FD1S3DX FF_0 (.D(full_d), .CK(WrClock), .CD(Reset), .Q(full_i)) - /* synthesis GSR="ENABLED" */; - - defparam w_gctr_cia.INJECT1_1 = "NO" ; - defparam w_gctr_cia.INJECT1_0 = "NO" ; - defparam w_gctr_cia.INIT1 = 16'h66AA ; - defparam w_gctr_cia.INIT0 = 16'h66AA ; - CCU2C w_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(w_gctr_ci)); - - defparam w_gctr_0.INJECT1_1 = "NO" ; - defparam w_gctr_0.INJECT1_0 = "NO" ; - defparam w_gctr_0.INIT1 = 16'h66AA ; - defparam w_gctr_0.INIT0 = 16'h66AA ; - CCU2C w_gctr_0 (.A0(wcount_0), .A1(wcount_1), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(w_gctr_ci), .S0(iwcount_0), .S1(iwcount_1), .COUT(co0)); - - defparam w_gctr_1.INJECT1_1 = "NO" ; - defparam w_gctr_1.INJECT1_0 = "NO" ; - defparam w_gctr_1.INIT1 = 16'h66AA ; - defparam w_gctr_1.INIT0 = 16'h66AA ; - CCU2C w_gctr_1 (.A0(wcount_2), .A1(wcount_3), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0), .S0(iwcount_2), .S1(iwcount_3), .COUT(co1)); - - defparam w_gctr_2.INJECT1_1 = "NO" ; - defparam w_gctr_2.INJECT1_0 = "NO" ; - defparam w_gctr_2.INIT1 = 16'h66AA ; - defparam w_gctr_2.INIT0 = 16'h66AA ; - CCU2C w_gctr_2 (.A0(wcount_4), .A1(wcount_5), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1), .S0(iwcount_4), .S1(iwcount_5), .COUT(co2)); - - defparam w_gctr_3.INJECT1_1 = "NO" ; - defparam w_gctr_3.INJECT1_0 = "NO" ; - defparam w_gctr_3.INIT1 = 16'h66AA ; - defparam w_gctr_3.INIT0 = 16'h66AA ; - CCU2C w_gctr_3 (.A0(wcount_6), .A1(wcount_7), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co2), .S0(iwcount_6), .S1(iwcount_7), .COUT(co3)); - - defparam w_gctr_4.INJECT1_1 = "NO" ; - defparam w_gctr_4.INJECT1_0 = "NO" ; - defparam w_gctr_4.INIT1 = 16'h66AA ; - defparam w_gctr_4.INIT0 = 16'h66AA ; - CCU2C w_gctr_4 (.A0(wcount_8), .A1(wcount_9), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co3), .S0(iwcount_8), .S1(iwcount_9), .COUT(co4)); - - defparam r_gctr_cia.INJECT1_1 = "NO" ; - defparam r_gctr_cia.INJECT1_0 = "NO" ; - defparam r_gctr_cia.INIT1 = 16'h66AA ; - defparam r_gctr_cia.INIT0 = 16'h66AA ; - CCU2C r_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(r_gctr_ci)); - - defparam r_gctr_0.INJECT1_1 = "NO" ; - defparam r_gctr_0.INJECT1_0 = "NO" ; - defparam r_gctr_0.INIT1 = 16'h66AA ; - defparam r_gctr_0.INIT0 = 16'h66AA ; - CCU2C r_gctr_0 (.A0(rcount_0), .A1(rcount_1), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(r_gctr_ci), .S0(ircount_0), .S1(ircount_1), .COUT(co0_1)); - - defparam r_gctr_1.INJECT1_1 = "NO" ; - defparam r_gctr_1.INJECT1_0 = "NO" ; - defparam r_gctr_1.INIT1 = 16'h66AA ; - defparam r_gctr_1.INIT0 = 16'h66AA ; - CCU2C r_gctr_1 (.A0(rcount_2), .A1(rcount_3), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_1), .S0(ircount_2), .S1(ircount_3), .COUT(co1_1)); - - defparam r_gctr_2.INJECT1_1 = "NO" ; - defparam r_gctr_2.INJECT1_0 = "NO" ; - defparam r_gctr_2.INIT1 = 16'h66AA ; - defparam r_gctr_2.INIT0 = 16'h66AA ; - CCU2C r_gctr_2 (.A0(rcount_4), .A1(rcount_5), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_1), .S0(ircount_4), .S1(ircount_5), .COUT(co2_1)); - - defparam r_gctr_3.INJECT1_1 = "NO" ; - defparam r_gctr_3.INJECT1_0 = "NO" ; - defparam r_gctr_3.INIT1 = 16'h66AA ; - defparam r_gctr_3.INIT0 = 16'h66AA ; - CCU2C r_gctr_3 (.A0(rcount_6), .A1(rcount_7), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co2_1), .S0(ircount_6), .S1(ircount_7), .COUT(co3_1)); - - defparam r_gctr_4.INJECT1_1 = "NO" ; - defparam r_gctr_4.INJECT1_0 = "NO" ; - defparam r_gctr_4.INIT1 = 16'h66AA ; - defparam r_gctr_4.INIT0 = 16'h66AA ; - CCU2C r_gctr_4 (.A0(rcount_8), .A1(rcount_9), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co3_1), .S0(ircount_8), .S1(ircount_9), .COUT(co4_1)); - - defparam empty_cmp_ci_a.INJECT1_1 = "NO" ; - defparam empty_cmp_ci_a.INJECT1_0 = "NO" ; - defparam empty_cmp_ci_a.INIT1 = 16'h66AA ; - defparam empty_cmp_ci_a.INIT0 = 16'h66AA ; - CCU2C empty_cmp_ci_a (.A0(scuba_vlo), .A1(rden_i), .B0(scuba_vlo), .B1(rden_i), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(cmp_ci)); - - defparam empty_cmp_0.INJECT1_1 = "NO" ; - defparam empty_cmp_0.INJECT1_0 = "NO" ; - defparam empty_cmp_0.INIT1 = 16'h99AA ; - defparam empty_cmp_0.INIT0 = 16'h99AA ; - CCU2C empty_cmp_0 (.A0(rcount_0), .A1(rcount_1), .B0(wcount_r0), .B1(wcount_r1), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(cmp_ci), .S0(), .S1(), .COUT(co0_2)); - - defparam empty_cmp_1.INJECT1_1 = "NO" ; - defparam empty_cmp_1.INJECT1_0 = "NO" ; - defparam empty_cmp_1.INIT1 = 16'h99AA ; - defparam empty_cmp_1.INIT0 = 16'h99AA ; - CCU2C empty_cmp_1 (.A0(rcount_2), .A1(rcount_3), .B0(wcount_r2), .B1(wcount_r3), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_2), .S0(), .S1(), .COUT(co1_2)); - - defparam empty_cmp_2.INJECT1_1 = "NO" ; - defparam empty_cmp_2.INJECT1_0 = "NO" ; - defparam empty_cmp_2.INIT1 = 16'h99AA ; - defparam empty_cmp_2.INIT0 = 16'h99AA ; - CCU2C empty_cmp_2 (.A0(rcount_4), .A1(rcount_5), .B0(wcount_r4), .B1(wcount_r5), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_2), .S0(), .S1(), .COUT(co2_2)); - - defparam empty_cmp_3.INJECT1_1 = "NO" ; - defparam empty_cmp_3.INJECT1_0 = "NO" ; - defparam empty_cmp_3.INIT1 = 16'h99AA ; - defparam empty_cmp_3.INIT0 = 16'h99AA ; - CCU2C empty_cmp_3 (.A0(rcount_6), .A1(rcount_7), .B0(w_g2b_xor_cluster_0), - .B1(wcount_r7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co2_2), .S0(), .S1(), .COUT(co3_2)); - - defparam empty_cmp_4.INJECT1_1 = "NO" ; - defparam empty_cmp_4.INJECT1_0 = "NO" ; - defparam empty_cmp_4.INIT1 = 16'h99AA ; - defparam empty_cmp_4.INIT0 = 16'h99AA ; - CCU2C empty_cmp_4 (.A0(rcount_8), .A1(empty_cmp_set), .B0(wcount_r8), - .B1(empty_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co3_2), .S0(), .S1(), .COUT(empty_d_c)); - - defparam a0.INJECT1_1 = "NO" ; - defparam a0.INJECT1_0 = "NO" ; - defparam a0.INIT1 = 16'h66AA ; - defparam a0.INIT0 = 16'h66AA ; - CCU2C a0 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(empty_d_c), .S0(empty_d), .S1(), .COUT()); - - defparam full_cmp_ci_a.INJECT1_1 = "NO" ; - defparam full_cmp_ci_a.INJECT1_0 = "NO" ; - defparam full_cmp_ci_a.INIT1 = 16'h66AA ; - defparam full_cmp_ci_a.INIT0 = 16'h66AA ; - CCU2C full_cmp_ci_a (.A0(scuba_vlo), .A1(wren_i), .B0(scuba_vlo), .B1(wren_i), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(), .S0(), .S1(), .COUT(cmp_ci_1)); - - defparam full_cmp_0.INJECT1_1 = "NO" ; - defparam full_cmp_0.INJECT1_0 = "NO" ; - defparam full_cmp_0.INIT1 = 16'h99AA ; - defparam full_cmp_0.INIT0 = 16'h99AA ; - CCU2C full_cmp_0 (.A0(wcount_0), .A1(wcount_1), .B0(rcount_w0), .B1(rcount_w1), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(cmp_ci_1), .S0(), .S1(), .COUT(co0_3)); - - defparam full_cmp_1.INJECT1_1 = "NO" ; - defparam full_cmp_1.INJECT1_0 = "NO" ; - defparam full_cmp_1.INIT1 = 16'h99AA ; - defparam full_cmp_1.INIT0 = 16'h99AA ; - CCU2C full_cmp_1 (.A0(wcount_2), .A1(wcount_3), .B0(rcount_w2), .B1(rcount_w3), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co0_3), .S0(), .S1(), .COUT(co1_3)); - - defparam full_cmp_2.INJECT1_1 = "NO" ; - defparam full_cmp_2.INJECT1_0 = "NO" ; - defparam full_cmp_2.INIT1 = 16'h99AA ; - defparam full_cmp_2.INIT0 = 16'h99AA ; - CCU2C full_cmp_2 (.A0(wcount_4), .A1(wcount_5), .B0(rcount_w4), .B1(rcount_w5), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(co1_3), .S0(), .S1(), .COUT(co2_3)); - - defparam full_cmp_3.INJECT1_1 = "NO" ; - defparam full_cmp_3.INJECT1_0 = "NO" ; - defparam full_cmp_3.INIT1 = 16'h99AA ; - defparam full_cmp_3.INIT0 = 16'h99AA ; - CCU2C full_cmp_3 (.A0(wcount_6), .A1(wcount_7), .B0(r_g2b_xor_cluster_0), - .B1(rcount_w7), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co2_3), .S0(), .S1(), .COUT(co3_3)); - - defparam full_cmp_4.INJECT1_1 = "NO" ; - defparam full_cmp_4.INJECT1_0 = "NO" ; - defparam full_cmp_4.INIT1 = 16'h99AA ; - defparam full_cmp_4.INIT0 = 16'h99AA ; - CCU2C full_cmp_4 (.A0(wcount_8), .A1(full_cmp_set), .B0(rcount_w8), - .B1(full_cmp_clr), .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), - .D1(scuba_vhi), .CIN(co3_3), .S0(), .S1(), .COUT(full_d_c)); - - VHI scuba_vhi_inst (.Z(scuba_vhi)); - - VLO scuba_vlo_inst (.Z(scuba_vlo)); - - defparam a1.INJECT1_1 = "NO" ; - defparam a1.INJECT1_0 = "NO" ; - defparam a1.INIT1 = 16'h66AA ; - defparam a1.INIT0 = 16'h66AA ; - CCU2C a1 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo), - .C0(scuba_vhi), .C1(scuba_vhi), .D0(scuba_vhi), .D1(scuba_vhi), - .CIN(full_d_c), .S0(full_d), .S1(), .COUT()); - - assign Empty = empty_i; - assign Full = full_i; - - - // exemplar begin - // exemplar attribute pdp_ram_0_0_1 MEM_LPC_FILE fifo40_dc.lpc - // exemplar attribute pdp_ram_0_0_1 MEM_INIT_FILE - // exemplar attribute pdp_ram_0_1_0 MEM_LPC_FILE fifo40_dc.lpc - // exemplar attribute pdp_ram_0_1_0 MEM_INIT_FILE - // exemplar attribute FF_101 GSR ENABLED - // exemplar attribute FF_100 GSR ENABLED - // exemplar attribute FF_99 GSR ENABLED - // exemplar attribute FF_98 GSR ENABLED - // exemplar attribute FF_97 GSR ENABLED - // exemplar attribute FF_96 GSR ENABLED - // exemplar attribute FF_95 GSR ENABLED - // exemplar attribute FF_94 GSR ENABLED - // exemplar attribute FF_93 GSR ENABLED - // exemplar attribute FF_92 GSR ENABLED - // exemplar attribute FF_91 GSR ENABLED - // exemplar attribute FF_90 GSR ENABLED - // exemplar attribute FF_89 GSR ENABLED - // exemplar attribute FF_88 GSR ENABLED - // exemplar attribute FF_87 GSR ENABLED - // exemplar attribute FF_86 GSR ENABLED - // exemplar attribute FF_85 GSR ENABLED - // exemplar attribute FF_84 GSR ENABLED - // exemplar attribute FF_83 GSR ENABLED - // exemplar attribute FF_82 GSR ENABLED - // exemplar attribute FF_81 GSR ENABLED - // exemplar attribute FF_80 GSR ENABLED - // exemplar attribute FF_79 GSR ENABLED - // exemplar attribute FF_78 GSR ENABLED - // exemplar attribute FF_77 GSR ENABLED - // exemplar attribute FF_76 GSR ENABLED - // exemplar attribute FF_75 GSR ENABLED - // exemplar attribute FF_74 GSR ENABLED - // exemplar attribute FF_73 GSR ENABLED - // exemplar attribute FF_72 GSR ENABLED - // exemplar attribute FF_71 GSR ENABLED - // exemplar attribute FF_70 GSR ENABLED - // exemplar attribute FF_69 GSR ENABLED - // exemplar attribute FF_68 GSR ENABLED - // exemplar attribute FF_67 GSR ENABLED - // exemplar attribute FF_66 GSR ENABLED - // exemplar attribute FF_65 GSR ENABLED - // exemplar attribute FF_64 GSR ENABLED - // exemplar attribute FF_63 GSR ENABLED - // exemplar attribute FF_62 GSR ENABLED - // exemplar attribute FF_61 GSR ENABLED - // exemplar attribute FF_60 GSR ENABLED - // exemplar attribute FF_59 GSR ENABLED - // exemplar attribute FF_58 GSR ENABLED - // exemplar attribute FF_57 GSR ENABLED - // exemplar attribute FF_56 GSR ENABLED - // exemplar attribute FF_55 GSR ENABLED - // exemplar attribute FF_54 GSR ENABLED - // exemplar attribute FF_53 GSR ENABLED - // exemplar attribute FF_52 GSR ENABLED - // exemplar attribute FF_51 GSR ENABLED - // exemplar attribute FF_50 GSR ENABLED - // exemplar attribute FF_49 GSR ENABLED - // exemplar attribute FF_48 GSR ENABLED - // exemplar attribute FF_47 GSR ENABLED - // exemplar attribute FF_46 GSR ENABLED - // exemplar attribute FF_45 GSR ENABLED - // exemplar attribute FF_44 GSR ENABLED - // exemplar attribute FF_43 GSR ENABLED - // exemplar attribute FF_42 GSR ENABLED - // exemplar attribute FF_41 GSR ENABLED - // exemplar attribute FF_40 GSR ENABLED - // exemplar attribute FF_39 GSR ENABLED - // exemplar attribute FF_38 GSR ENABLED - // exemplar attribute FF_37 GSR ENABLED - // exemplar attribute FF_36 GSR ENABLED - // exemplar attribute FF_35 GSR ENABLED - // exemplar attribute FF_34 GSR ENABLED - // exemplar attribute FF_33 GSR ENABLED - // exemplar attribute FF_32 GSR ENABLED - // exemplar attribute FF_31 GSR ENABLED - // exemplar attribute FF_30 GSR ENABLED - // exemplar attribute FF_29 GSR ENABLED - // exemplar attribute FF_28 GSR ENABLED - // exemplar attribute FF_27 GSR ENABLED - // exemplar attribute FF_26 GSR ENABLED - // exemplar attribute FF_25 GSR ENABLED - // exemplar attribute FF_24 GSR ENABLED - // exemplar attribute FF_23 GSR ENABLED - // exemplar attribute FF_22 GSR ENABLED - // exemplar attribute FF_21 GSR ENABLED - // exemplar attribute FF_20 GSR ENABLED - // exemplar attribute FF_19 GSR ENABLED - // exemplar attribute FF_18 GSR ENABLED - // exemplar attribute FF_17 GSR ENABLED - // exemplar attribute FF_16 GSR ENABLED - // exemplar attribute FF_15 GSR ENABLED - // exemplar attribute FF_14 GSR ENABLED - // exemplar attribute FF_13 GSR ENABLED - // exemplar attribute FF_12 GSR ENABLED - // exemplar attribute FF_11 GSR ENABLED - // exemplar attribute FF_10 GSR ENABLED - // exemplar attribute FF_9 GSR ENABLED - // exemplar attribute FF_8 GSR ENABLED - // exemplar attribute FF_7 GSR ENABLED - // exemplar attribute FF_6 GSR ENABLED - // exemplar attribute FF_5 GSR ENABLED - // exemplar attribute FF_4 GSR ENABLED - // exemplar attribute FF_3 GSR ENABLED - // exemplar attribute FF_2 GSR ENABLED - // exemplar attribute FF_1 GSR ENABLED - // exemplar attribute FF_0 GSR ENABLED - // exemplar end - -endmodule diff --git a/fifo40_dc/fifo40_dc_generate.log b/fifo40_dc/fifo40_dc_generate.log deleted file mode 100644 index 23a2972..0000000 --- a/fifo40_dc/fifo40_dc_generate.log +++ /dev/null @@ -1,49 +0,0 @@ -Starting process: - -Configuration data saved - - -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Tue Feb 9 13:19:24 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 - Circuit name : fifo40_dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[39:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo40_dc.edn - Verilog output : fifo40_dc.v - Verilog template : fifo40_dc_tmpl.v - Verilog testbench: tb_fifo40_dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo40_dc.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - -File: fifo40_dc.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/fifo40_dc/fifo40_dc_tmpl.v b/fifo40_dc/fifo40_dc_tmpl.v deleted file mode 100644 index 64ab3eb..0000000 --- a/fifo40_dc/fifo40_dc_tmpl.v +++ /dev/null @@ -1,7 +0,0 @@ -/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.2.446 */ -/* Module Version: 5.8 */ -/* Tue Feb 9 13:19:26 2021 */ - -/* parameterized module instance */ -fifo40_dc __ (.Data( ), .WrClock( ), .RdClock( ), .WrEn( ), .RdEn( ), - .Reset( ), .RPReset( ), .Q( ), .Empty( ), .Full( )); diff --git a/fifo40_dc/generate_core.tcl b/fifo40_dc/generate_core.tcl deleted file mode 100644 index 079d16b..0000000 --- a/fifo40_dc/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "fifo40_dc" -set lang "verilog" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "sa5p00g" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/fifo40_dc/generate_ngd.tcl b/fifo40_dc/generate_ngd.tcl deleted file mode 100644 index 9920deb..0000000 --- a/fifo40_dc/generate_ngd.tcl +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "fifo40_dc" -set Para(Module) "FIFO_DC" -set Para(libname) ecp5um5g -set Para(arch_name) sa5p00g -set Para(PartType) "LFE5UM5G-45F" - -set Para(tech_syn) ecp5um5g -set Para(tech_cae) ecp5um5g -set Para(Package) "CABGA381" -set Para(SpeedGrade) "8" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/fifo40_dc/msg_file.log b/fifo40_dc/msg_file.log deleted file mode 100644 index a9be101..0000000 --- a/fifo40_dc/msg_file.log +++ /dev/null @@ -1,33 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.11.2.446 -Tue Feb 9 13:19:24 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n fifo40_dc -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 512 -width 40 -rwidth 40 -reset_rel SYNC -pe -1 -pf -1 - Circuit name : fifo40_dc - Module type : ebfifo - Module Version : 5.8 - Ports : - Inputs : Data[39:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[39:0], Empty, Full - I/O buffer : not inserted - EDIF output : fifo40_dc.edn - Verilog output : fifo40_dc.v - Verilog template : fifo40_dc_tmpl.v - Verilog testbench: tb_fifo40_dc_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : fifo40_dc.srp - Estimated Resource Usage: - LUT : 97 - EBR : 2 - Reg : 102 - -END SCUBA Module Synthesis - diff --git a/fifo40_dc/tb_fifo40_dc_tmpl.v b/fifo40_dc/tb_fifo40_dc_tmpl.v deleted file mode 100644 index d293983..0000000 --- a/fifo40_dc/tb_fifo40_dc_tmpl.v +++ /dev/null @@ -1,76 +0,0 @@ -//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.11.2.446 -`timescale 1 ns / 1 ps -module tb; - reg [39:0] Data = 40'b0; - reg WrClock = 0; - reg RdClock = 0; - reg WrEn = 0; - reg RdEn = 0; - reg Reset = 0; - reg RPReset = 0; - wire [39:0] Q; - wire Empty; - wire Full; - - integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0; - - GSR GSR_INST (.GSR(1'b1)); - PUR PUR_INST (.PUR(1'b1)); - - fifo40_dc u1 (.Data(Data), .WrClock(WrClock), .RdClock(RdClock), .WrEn(WrEn), - .RdEn(RdEn), .Reset(Reset), .RPReset(RPReset), .Q(Q), .Empty(Empty), - .Full(Full) - ); - - initial - begin - Data <= 0; - #100; - @(Reset == 1'b0); - for (i1 = 0; i1 < 515; i1 = i1 + 1) begin - @(posedge WrClock); - #1 Data <= Data + 1'b1; - end - end - always - #5.00 WrClock <= ~ WrClock; - - always - #5.00 RdClock <= ~ RdClock; - - initial - begin - WrEn <= 1'b0; - #100; - @(Reset == 1'b0); - for (i4 = 0; i4 < 515; i4 = i4 + 1) begin - @(posedge WrClock); - #1 WrEn <= 1'b1; - end - WrEn <= 1'b0; - end - initial - begin - RdEn <= 1'b0; - @(Reset == 1'b0); - @(WrEn == 1'b1); - @(WrEn == 1'b0); - for (i5 = 0; i5 < 515; i5 = i5 + 1) begin - @(posedge RdClock); - #1 RdEn <= 1'b1; - end - RdEn <= 1'b0; - end - initial - begin - Reset <= 1'b1; - #100; - Reset <= 1'b0; - end - initial - begin - RPReset <= 1'b1; - #100; - RPReset <= 1'b0; - end -endmodule \ No newline at end of file diff --git a/fifo_colector.v b/fifo_colector.v deleted file mode 100644 index a9efe4a..0000000 --- a/fifo_colector.v +++ /dev/null @@ -1,95 +0,0 @@ -//`define IGNORE_VERILOG_BLACKBOX_GUTS - -module fifo_colector( wr_clk, - rd_clk, - reset, - in_data, - in_empty, - in_read_enable, - out_data, - out_empty, - out_read_enable, - discard, - //buffer_wr_enable, - raw_enable - ); - parameter CHANNELS = 3; - parameter DATA_WIDTH = 32; - parameter ADDRESS_WIDTH = 8; - /* */ - input wire wr_clk; - input wire rd_clk; - input wire reset; - //input wire [CHANNELS-1:0][DATA_WIDTH-1:0]in_data; - input wire [(CHANNELS*DATA_WIDTH-1):0]in_data; - input wire [CHANNELS-1:0]in_empty; - output reg [CHANNELS-1:0]in_read_enable; - //output wire [$clog2(CHANNELS)+DATA_WIDTH-1:0]out_data; - output wire [ADDRESS_WIDTH+DATA_WIDTH-1:0]out_data; - output wire out_empty; - input wire out_read_enable; - input wire discard; - input wire raw_enable; - - wire fifo_clear; - assign fifo_clear = discard | reset; - reg buffer_wr_enable; - //reg [$clog2(CHANNELS)+DATA_WIDTH-1:0]data_buffer - reg [ADDRESS_WIDTH+DATA_WIDTH-1:0]data_buffer; - reg [$clog2(CHANNELS)-1:0]iterator; -fifo40_dc fifo40_inst ( - .Data( data_buffer), - .WrClock( wr_clk), - .RdClock( rd_clk), - .WrEn( buffer_wr_enable), - .RdEn( out_read_enable), - //.Reset( fifo_clear), - .Reset( 0), - .Q( out_data), - .Empty( out_empty), - .Full( ) - ); - - reg [31:0]test_cnt; - always @(posedge wr_clk)begin - if(reset)begin - test_cnt <= 'b0; - end else begin - test_cnt <= test_cnt +1; - end - end - //assign buffer_wr_enable =in_empty[0]; -/*always @(posedge clk)begin - if(~in_empty[0])begin - data_buffer[DATA_WIDTH+: $clog2(CHANNELS)] <= 0; - data_buffer[0 +: DATA_WIDTH] <=in_data[0]; - //buffer_wr_enable<=1; - in_read_enable[0]<=1; - end else begin - //buffer_wr_enable<=0; - in_read_enable[0]<=0; - end - -end*/ -//fifo0 fifo0_inst (.Data( data[i]), .Clock( pll_clks[0]), .WrEn( decoder_data_valid[i]), .RdEn( fifo_read[i]), .Reset( ), .Q( fifo_out[i]), .Empty( fifo_empty[i]), .Full( ), .AlmostEmpty( ), .AlmostFull( )); - - always @( posedge wr_clk)begin - if(~in_empty[iterator])begin - data_buffer[DATA_WIDTH+: $clog2(CHANNELS)] = iterator; - data_buffer[0 +: DATA_WIDTH] = in_data[(iterator*DATA_WIDTH) +: DATA_WIDTH]; - //data_buffer[0 +: DATA_WIDTH] = in_data[iterator]; - //data_buffer[0 +: DATA_WIDTH] = test_cnt; - in_read_enable[iterator] ='b1; - buffer_wr_enable = 'b1; - end else begin - in_read_enable='b0; - buffer_wr_enable = 'b0; - end - if(iterator= 0.0 - -- Error conditions: - -- Error if X < 0.0 - -- Range: - -- SQRT(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of SQRT is - -- approximately given by: - -- SQRT(X) <= SQRT(REAL'HIGH) - - function CBRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns cube root of X - -- Special values: - -- CBRT(0.0) = 0.0 - -- CBRT(1.0) = 1.0 - -- CBRT(-1.0) = -1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CBRT(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of CBRT is approximately given by: - -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) - - function "**" (X : in INTEGER; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0 - -- 0**Y = 0.0; Y > 0.0 - -- X**1.0 = REAL(X); X >= 0 - -- 1**Y = 1.0 - -- Domain: - -- X > 0 - -- X = 0 for Y > 0.0 - -- X < 0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0 and Y /= 0.0 - -- Error if X = 0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function "**" (X : in REAL; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0.0 - -- 0.0**Y = 0.0; Y > 0.0 - -- X**1.0 = X; X >= 0.0 - -- 1.0**Y = 1.0 - -- Domain: - -- X > 0.0 - -- X = 0.0 for Y > 0.0 - -- X < 0.0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0.0 and Y /= 0.0 - -- Error if X = 0.0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function EXP (X : in REAL ) return REAL; - -- Purpose: - -- Returns e**X; where e = MATH_E - -- Special values: - -- EXP(0.0) = 1.0 - -- EXP(1.0) = MATH_E - -- EXP(-1.0) = MATH_1_OVER_E - -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) - -- Domain: - -- X in REAL such that EXP(X) <= REAL'HIGH - -- Error conditions: - -- Error if X > LOG(REAL'HIGH) - -- Range: - -- EXP(X) >= 0.0 - -- Notes: - -- a) The usable domain of EXP is approximately given by: - -- X <= LOG(REAL'HIGH) - - function LOG (X : in REAL ) return REAL; - -- Purpose: - -- Returns natural logarithm of X - -- Special values: - -- LOG(1.0) = 0.0 - -- LOG(MATH_E) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG is approximately given by: - -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) - - function LOG2 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 2 of X - -- Special values: - -- LOG2(1.0) = 0.0 - -- LOG2(2.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG2(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG2 is approximately given by: - -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) - - function LOG10 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 10 of X - -- Special values: - -- LOG10(1.0) = 0.0 - -- LOG10(10.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG10(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG10 is approximately given by: - -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) - - function LOG (X: in REAL; BASE: in REAL) return REAL; - -- Purpose: - -- Returns logarithm base BASE of X - -- Special values: - -- LOG(1.0, BASE) = 0.0 - -- LOG(BASE, BASE) = 1.0 - -- Domain: - -- X > 0.0 - -- BASE > 0.0 - -- BASE /= 1.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Error if BASE <= 0.0 - -- Error if BASE = 1.0 - -- Range: - -- LOG(X, BASE) is mathematically unbounded - -- Notes: - -- a) When BASE > 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) - -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) - - function SIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns sine of X; X in radians - -- Special values: - -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIN(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function COS ( X : in REAL ) return REAL; - -- Purpose: - -- Returns cosine of X; X in radians - -- Special values: - -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER - -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(COS(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function TAN (X : in REAL ) return REAL; - -- Purpose: - -- Returns tangent of X; X in radians - -- Special values: - -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL and - -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER - -- Error conditions: - -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an - -- INTEGER - -- Range: - -- TAN(X) is mathematically unbounded - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function ARCSIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse sine of X - -- Special values: - -- ARCSIN(0.0) = 0.0 - -- ARCSIN(1.0) = MATH_PI_OVER_2 - -- ARCSIN(-1.0) = -MATH_PI_OVER_2 - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCCOS (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse cosine of X - -- Special values: - -- ARCCOS(1.0) = 0.0 - -- ARCCOS(0.0) = MATH_PI_OVER_2 - -- ARCCOS(-1.0) = MATH_PI - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- 0.0 <= ARCCOS(X) <= MATH_PI - -- Notes: - -- None - - function ARCTAN (Y : in REAL) return REAL; - -- Purpose: - -- Returns the value of the angle in radians of the point - -- (1.0, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0) = 0.0 - -- Domain: - -- Y in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCTAN (Y : in REAL; X : in REAL) return REAL; - -- Purpose: - -- Returns the principal value of the angle in radians of - -- the point (X, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0, X) = 0.0 if X > 0.0 - -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 - -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 - -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 - -- Domain: - -- Y in REAL - -- X in REAL, X /= 0.0 when Y = 0.0 - -- Error conditions: - -- Error if X = 0.0 and Y = 0.0 - -- Range: - -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI - -- Notes: - -- None - - function SINH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic sine of X - -- Special values: - -- SINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- SINH(X) is mathematically unbounded - -- Notes: - -- a) The usable domain of SINH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - - function COSH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic cosine of X - -- Special values: - -- COSH(0.0) = 1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- COSH(X) >= 1.0 - -- Notes: - -- a) The usable domain of COSH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - function TANH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic tangent of X - -- Special values: - -- TANH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(TANH(X)) <= 1.0 - -- Notes: - -- None - - function ARCSINH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic sine of X - -- Special values: - -- ARCSINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ARCSINH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCSINH is approximately given by: - -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) - - function ARCCOSH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic cosine of X - -- Special values: - -- ARCCOSH(1.0) = 0.0 - -- Domain: - -- X >= 1.0 - -- Error conditions: - -- Error if X < 1.0 - -- Range: - -- ARCCOSH(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of ARCCOSH is - -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) - - function ARCTANH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic tangent of X - -- Special values: - -- ARCTANH(0.0) = 0.0 - -- Domain: - -- ABS(X) < 1.0 - -- Error conditions: - -- Error if ABS(X) >= 1.0 - -- Range: - -- ARCTANH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCTANH is approximately given by: - -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) - -end MATH_REAL; - - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. - --- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. - --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package body is a nonnormative implementation of the --- functionality defined in the MATH_REAL package declaration. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076 --- -1993. --- --- Notes: --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to clarify such semantics and provide a --- guideline for implementations to verify their implementation --- of MATH_REAL. Tool developers may choose to implement --- the package body in the most efficient manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package body MATH_REAL is - - -- - -- Local Constants for Use in the Package Body Only - -- - constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 - constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 - constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi - constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic - constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries - constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria - constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic - - -- - -- Local Type Declarations for Cordic Operations - -- - type REAL_VECTOR is array (NATURAL range <>) of REAL; - type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; - subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); - subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); - subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); - subtype QUADRANT is INTEGER range 0 to 3; - type CORDIC_MODE_TYPE is (ROTATION, VECTORING); - - -- - -- Auxiliary Functions for Cordic Algorithms - -- - function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; - NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is - -- Description: - -- Returns power of two for a vector of values - -- Notes: - -- None - -- - variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); - variable TEMP : REAL := INITIAL_VALUE; - variable FLAG : BOOLEAN := TRUE; - begin - for I in 0 to NUMBER_OF_VALUES loop - V(I) := TEMP; - for P in D'RANGE loop - if I = D(P) then - FLAG := FALSE; - exit; - end if; - end loop; - if FLAG then - TEMP := TEMP/2.0; - end if; - FLAG := TRUE; - end loop; - return V; - end POWER_OF_2_SERIES; - - - constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( - NATURAL_VECTOR'(100, 90),1.0, - MAX_ITER); - - constant EPSILON : REAL_VECTOR_N := ( - 7.8539816339744827e-01, - 4.6364760900080606e-01, - 2.4497866312686413e-01, - 1.2435499454676144e-01, - 6.2418809995957351e-02, - 3.1239833430268277e-02, - 1.5623728620476830e-02, - 7.8123410601011116e-03, - 3.9062301319669717e-03, - 1.9531225164788189e-03, - 9.7656218955931937e-04, - 4.8828121119489829e-04, - 2.4414062014936175e-04, - 1.2207031189367021e-04, - 6.1035156174208768e-05, - 3.0517578115526093e-05, - 1.5258789061315760e-05, - 7.6293945311019699e-06, - 3.8146972656064960e-06, - 1.9073486328101870e-06, - 9.5367431640596080e-07, - 4.7683715820308876e-07, - 2.3841857910155801e-07, - 1.1920928955078067e-07, - 5.9604644775390553e-08, - 2.9802322387695303e-08, - 1.4901161193847654e-08, - 7.4505805969238281e-09 - ); - - function CORDIC ( X0 : in REAL; - Y0 : in REAL; - Z0 : in REAL; - N : in NATURAL; -- Precision factor - CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) - -- or vectoring (Y -> 0) - ) return REAL_ARR_3 is - -- Description: - -- Compute cordic values - -- Notes: - -- None - variable X : REAL := X0; - variable Y : REAL := Y0; - variable Z : REAL := Z0; - variable X_TEMP : REAL; - begin - if CORDIC_MODE = ROTATION then - for K in 0 to N loop - X_TEMP := X; - if ( Z >= 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - else - for K in 0 to N loop - X_TEMP := X; - if ( Y < 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - end if; - return REAL_ARR_3'(X, Y, Z); - end CORDIC; - - -- - -- Bodies for Global Mathematical Functions Start Here - -- - function SIGN (X: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- None - begin - if ( X > 0.0 ) then - return 1.0; - elsif ( X < 0.0 ) then - return -1.0; - else - return 0.0; - end if; - end SIGN; - - function CEIL (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is X <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS(X) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD >= X then - return RD; - else - return RD + 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD <= X then - return RD + 1.0; - else - return RD; - end if; - end if; - end CEIL; - - function FLOOR (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is ABS(X) <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS( X ) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD <= X then - return RD; - else - return RD - 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD >= X then - return RD - 1.0; - else - return RD; - end if; - end if; - end FLOOR; - - function ROUND (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X + 0.5) if X > 0 - -- c) Returns CEIL(X - 0.5) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X + 0.5); - elsif X < 0.0 then - return CEIL( X - 0.5); - else - return 0.0; - end if; - end ROUND; - - function TRUNC (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X) if X > 0 - -- c) Returns CEIL(X) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X); - elsif X < 0.0 then - return CEIL( X); - else - return 0.0; - end if; - end TRUNC; - - - - - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - end "MOD"; - - - function REALMAX (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMAX(X,Y) = X when X = Y - -- - begin - if X >= Y then - return X; - else - return Y; - end if; - end REALMAX; - - function REALMIN (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMIN(X,Y) = X when X = Y - -- - begin - if X <= Y then - return X; - else - return Y; - end if; - end REALMIN; - - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) - is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - -- - variable Z, K: INTEGER; - variable TSEED1 : INTEGER := INTEGER'(SEED1); - variable TSEED2 : INTEGER := INTEGER'(SEED2); - begin - -- Check validity of arguments - if SEED1 > 2147483562 then - assert FALSE - report "SEED1 > 2147483562 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - if SEED2 > 2147483398 then - assert FALSE - report "SEED2 > 2147483398 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - -- Compute new seed values and pseudo-random number - K := TSEED1/53668; - TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; - - if TSEED1 < 0 then - TSEED1 := TSEED1 + 2147483563; - end if; - - K := TSEED2/52774; - TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; - - if TSEED2 < 0 then - TSEED2 := TSEED2 + 2147483399; - end if; - - Z := TSEED1 - TSEED2; - if Z < 1 then - Z := Z + 2147483562; - end if; - - -- Get output values - SEED1 := POSITIVE'(TSEED1); - SEED2 := POSITIVE'(TSEED2); - X := REAL(Z)*4.656613e-10; - end UNIFORM; - - - - function SQRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = 0.5*[F(n) + x/F(n)] - -- b) Returns 0.0 on error - -- - - constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor - - variable INIVAL: REAL; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - -- Check validity of argument - if ( X < 0.0 ) then - assert FALSE - report "X < 0.0 in SQRT(X)" - severity ERROR; - return 0.0; - end if; - - -- Get the square root for special cases - if X = 0.0 then - return 0.0; - else - if ( X = 1.0 ) then - return 1.0; - end if; - end if; - - -- Get the square root for general cases - INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise - OLDVAL := INIVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - - -- Check for relative and absolute error and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT) ) loop - OLDVAL := NEWVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - COUNT := COUNT + 1; - end loop; - return NEWVAL; - end SQRT; - - function CBRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; - -- - constant EPS : REAL := BASE_EPS*BASE_EPS; - - variable INIVAL: REAL; - variable XLOCAL : REAL := X; - variable NEGATIVE : BOOLEAN := X < 0.0; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - - -- Compute root for special cases - if X = 0.0 then - return 0.0; - elsif ( X = 1.0 ) then - return 1.0; - else - if X = -1.0 then - return -1.0; - end if; - end if; - - -- Compute root for general cases - if NEGATIVE then - XLOCAL := -X; - end if; - - INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but - -- imprecise - OLDVAL := INIVAL; - NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR - (ABS(NEWVAL - OLDVAL) > EPS ) ) AND - ( COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - COUNT := COUNT + 1; - end loop; - - if NEGATIVE then - NEWVAL := -NEWVAL; - end if; - - return NEWVAL; - end CBRT; - - function "**" (X : in INTEGER; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (REAL(X)); - end if; - - -- Get value for general case - return EXP (Y * LOG (REAL(X))); - end "**"; - - function "**" (X : in REAL; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0.0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0.0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0.0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1.0 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0.0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (X); - end if; - - -- Get value for general case - return EXP (Y * LOG (X)); - end "**"; - - function EXP (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) This function computes the exponential using the following - -- series: - -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 - -- and reduces argument X to take advantage of exp(x+y) = - -- exp(x)*exp(y) - -- - -- b) This implementation limits X to be less than LOG(REAL'HIGH) - -- to avoid overflow. Returns REAL'HIGH when X reaches that - -- limit - -- - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria - - variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument - variable XLOCAL : REAL := ABS(X); -- Use positive value - variable OLDVAL: REAL ; - variable COUNT: INTEGER ; - variable NEWVAL: REAL ; - variable LAST_TERM: REAL ; - variable FACTOR : REAL := 1.0; - - begin - -- Compute value for special cases - if X = 0.0 then - return 1.0; - end if; - - if XLOCAL = 1.0 then - if RECIPROCAL then - return MATH_1_OVER_E; - else - return MATH_E; - end if; - end if; - - if XLOCAL = 2.0 then - if RECIPROCAL then - return 1.0/MATH_E_P2; - else - return MATH_E_P2; - end if; - end if; - - if XLOCAL = 10.0 then - if RECIPROCAL then - return 1.0/MATH_E_P10; - else - return MATH_E_P10; - end if; - end if; - - if XLOCAL > LOG(REAL'HIGH) then - if RECIPROCAL then - return 0.0; - else - assert FALSE - report "X > LOG(REAL'HIGH) in EXP(X)" - severity NOTE; - return REAL'HIGH; - end if; - end if; - - -- Reduce argument to ABS(X) < 1.0 - while XLOCAL > 10.0 loop - XLOCAL := XLOCAL - 10.0; - FACTOR := FACTOR*MATH_E_P10; - end loop; - - while XLOCAL > 1.0 loop - XLOCAL := XLOCAL - 1.0; - FACTOR := FACTOR*MATH_E; - end loop; - - -- Compute value for case 0 < XLOCAL < 1 - OLDVAL := 1.0; - LAST_TERM := XLOCAL; - NEWVAL:= OLDVAL + LAST_TERM; - COUNT := 2; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); - NEWVAL := OLDVAL + LAST_TERM; - COUNT := COUNT + 1; - end loop; - - -- Compute final value using exp(x+y) = exp(x)*exp(y) - NEWVAL := NEWVAL*FACTOR; - - if RECIPROCAL then - NEWVAL := 1.0/NEWVAL; - end if; - - return NEWVAL; - end EXP; - - - -- - -- Auxiliary Functions to Compute LOG - -- - function ILOGB(X: in REAL) return INTEGER IS - -- Description: - -- Returns n such that -1 <= ABS(X)/2^n < 2 - -- Notes: - -- None - - variable N: INTEGER := 0; - variable Y: REAL := ABS(X); - - begin - if(Y = 1.0 or Y = 0.0) then - return 0; - end if; - - if( Y > 1.0) then - while Y >= 2.0 loop - Y := Y/2.0; - N := N+1; - end loop; - return N; - end if; - - -- O < Y < 1 - while Y < 1.0 loop - Y := Y*2.0; - N := N -1; - end loop; - return N; - end ILOGB; - - function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS - -- Description: - -- Returns X*2^n - -- Notes: - -- None - begin - return X*(2.0 ** N); - end LDEXP; - - function LOG (X : in REAL ) return REAL IS - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- - -- Notes: - -- a) Returns REAL'LOW on error - -- - -- Copyright (c) 1992 Regents of the University of California. - -- All rights reserved. - -- - -- Redistribution and use in source and binary forms, with or without - -- modification, are permitted provided that the following conditions - -- are met: - -- 1. Redistributions of source code must retain the above copyright - -- notice, this list of conditions and the following disclaimer. - -- 2. Redistributions in binary form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- 3. All advertising materials mentioning features or use of this - -- software must display the following acknowledgement: - -- This product includes software developed by the University of - -- California, Berkeley and its contributors. - -- 4. Neither the name of the University nor the names of its - -- contributors may be used to endorse or promote products derived - -- from this software without specific prior written permission. - -- - -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR - -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - -- DAMAGE. - -- - -- NOTE: This VHDL version was generated using the C version of the - -- original function by the IEEE VHDL Mathematical Package - -- Working Group (CS/JT) - - constant N: INTEGER := 128; - - -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. - -- Used for generation of extend precision logarithms. - -- The constant 35184372088832 is 2^45, so the divide is exact. - -- It ensures correct reading of logF_head, even for inaccurate - -- decimal-to-binary conversion routines. (Everybody gets the - -- right answer for INTEGERs less than 2^53.) - -- Values for LOG(F) were generated using error < 10^-57 absolute - -- with the bc -l package. - - type REAL_VECTOR is array (NATURAL range <>) of REAL; - - constant A1:REAL := 0.08333333333333178827; - constant A2:REAL := 0.01250000000377174923; - constant A3:REAL := 0.002232139987919447809; - constant A4:REAL := 0.0004348877777076145742; - - constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( - 0.0, - 0.007782140442060381246, - 0.015504186535963526694, - 0.023167059281547608406, - 0.030771658666765233647, - 0.038318864302141264488, - 0.045809536031242714670, - 0.053244514518837604555, - 0.060624621816486978786, - 0.067950661908525944454, - 0.075223421237524235039, - 0.082443669210988446138, - 0.089612158689760690322, - 0.096729626458454731618, - 0.103796793681567578460, - 0.110814366340264314203, - 0.117783035656430001836, - 0.124703478501032805070, - 0.131576357788617315236, - 0.138402322859292326029, - 0.145182009844575077295, - 0.151916042025732167530, - 0.158605030176659056451, - 0.165249572895390883786, - 0.171850256926518341060, - 0.178407657472689606947, - 0.184922338493834104156, - 0.191394852999565046047, - 0.197825743329758552135, - 0.204215541428766300668, - 0.210564769107350002741, - 0.216873938300523150246, - 0.223143551314024080056, - 0.229374101064877322642, - 0.235566071312860003672, - 0.241719936886966024758, - 0.247836163904594286577, - 0.253915209980732470285, - 0.259957524436686071567, - 0.265963548496984003577, - 0.271933715484010463114, - 0.277868451003087102435, - 0.283768173130738432519, - 0.289633292582948342896, - 0.295464212893421063199, - 0.301261330578199704177, - 0.307025035294827830512, - 0.312755710004239517729, - 0.318453731118097493890, - 0.324119468654316733591, - 0.329753286372579168528, - 0.335355541920762334484, - 0.340926586970454081892, - 0.346466767346100823488, - 0.351976423156884266063, - 0.357455888922231679316, - 0.362905493689140712376, - 0.368325561158599157352, - 0.373716409793814818840, - 0.379078352934811846353, - 0.384411698910298582632, - 0.389716751140440464951, - 0.394993808240542421117, - 0.400243164127459749579, - 0.405465108107819105498, - 0.410659924985338875558, - 0.415827895143593195825, - 0.420969294644237379543, - 0.426084395310681429691, - 0.431173464818130014464, - 0.436236766774527495726, - 0.441274560805140936281, - 0.446287102628048160113, - 0.451274644139630254358, - 0.456237433481874177232, - 0.461175715122408291790, - 0.466089729924533457960, - 0.470979715219073113985, - 0.475845904869856894947, - 0.480688529345570714212, - 0.485507815781602403149, - 0.490303988045525329653, - 0.495077266798034543171, - 0.499827869556611403822, - 0.504556010751912253908, - 0.509261901790523552335, - 0.513945751101346104405, - 0.518607764208354637958, - 0.523248143765158602036, - 0.527867089620485785417, - 0.532464798869114019908, - 0.537041465897345915436, - 0.541597282432121573947, - 0.546132437597407260909, - 0.550647117952394182793, - 0.555141507540611200965, - 0.559615787935399566777, - 0.564070138285387656651, - 0.568504735352689749561, - 0.572919753562018740922, - 0.577315365035246941260, - 0.581691739635061821900, - 0.586049045003164792433, - 0.590387446602107957005, - 0.594707107746216934174, - 0.599008189645246602594, - 0.603290851438941899687, - 0.607555250224322662688, - 0.611801541106615331955, - 0.616029877215623855590, - 0.620240409751204424537, - 0.624433288012369303032, - 0.628608659422752680256, - 0.632766669570628437213, - 0.636907462236194987781, - 0.641031179420679109171, - 0.645137961373620782978, - 0.649227946625615004450, - 0.653301272011958644725, - 0.657358072709030238911, - 0.661398482245203922502, - 0.665422632544505177065, - 0.669430653942981734871, - 0.673422675212350441142, - 0.677398823590920073911, - 0.681359224807238206267, - 0.685304003098281100392, - 0.689233281238557538017, - 0.693147180560117703862); - - constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( - 0.0, - -0.00000000000000543229938420049, - 0.00000000000000172745674997061, - -0.00000000000001323017818229233, - -0.00000000000001154527628289872, - -0.00000000000000466529469958300, - 0.00000000000005148849572685810, - -0.00000000000002532168943117445, - -0.00000000000005213620639136504, - -0.00000000000001819506003016881, - 0.00000000000006329065958724544, - 0.00000000000008614512936087814, - -0.00000000000007355770219435028, - 0.00000000000009638067658552277, - 0.00000000000007598636597194141, - 0.00000000000002579999128306990, - -0.00000000000004654729747598444, - -0.00000000000007556920687451336, - 0.00000000000010195735223708472, - -0.00000000000017319034406422306, - -0.00000000000007718001336828098, - 0.00000000000010980754099855238, - -0.00000000000002047235780046195, - -0.00000000000008372091099235912, - 0.00000000000014088127937111135, - 0.00000000000012869017157588257, - 0.00000000000017788850778198106, - 0.00000000000006440856150696891, - 0.00000000000016132822667240822, - -0.00000000000007540916511956188, - -0.00000000000000036507188831790, - 0.00000000000009120937249914984, - 0.00000000000018567570959796010, - -0.00000000000003149265065191483, - -0.00000000000009309459495196889, - 0.00000000000017914338601329117, - -0.00000000000001302979717330866, - 0.00000000000023097385217586939, - 0.00000000000023999540484211737, - 0.00000000000015393776174455408, - -0.00000000000036870428315837678, - 0.00000000000036920375082080089, - -0.00000000000009383417223663699, - 0.00000000000009433398189512690, - 0.00000000000041481318704258568, - -0.00000000000003792316480209314, - 0.00000000000008403156304792424, - -0.00000000000034262934348285429, - 0.00000000000043712191957429145, - -0.00000000000010475750058776541, - -0.00000000000011118671389559323, - 0.00000000000037549577257259853, - 0.00000000000013912841212197565, - 0.00000000000010775743037572640, - 0.00000000000029391859187648000, - -0.00000000000042790509060060774, - 0.00000000000022774076114039555, - 0.00000000000010849569622967912, - -0.00000000000023073801945705758, - 0.00000000000015761203773969435, - 0.00000000000003345710269544082, - -0.00000000000041525158063436123, - 0.00000000000032655698896907146, - -0.00000000000044704265010452446, - 0.00000000000034527647952039772, - -0.00000000000007048962392109746, - 0.00000000000011776978751369214, - -0.00000000000010774341461609578, - 0.00000000000021863343293215910, - 0.00000000000024132639491333131, - 0.00000000000039057462209830700, - -0.00000000000026570679203560751, - 0.00000000000037135141919592021, - -0.00000000000017166921336082431, - -0.00000000000028658285157914353, - -0.00000000000023812542263446809, - 0.00000000000006576659768580062, - -0.00000000000028210143846181267, - 0.00000000000010701931762114254, - 0.00000000000018119346366441110, - 0.00000000000009840465278232627, - -0.00000000000033149150282752542, - -0.00000000000018302857356041668, - -0.00000000000016207400156744949, - 0.00000000000048303314949553201, - -0.00000000000071560553172382115, - 0.00000000000088821239518571855, - -0.00000000000030900580513238244, - -0.00000000000061076551972851496, - 0.00000000000035659969663347830, - 0.00000000000035782396591276383, - -0.00000000000046226087001544578, - 0.00000000000062279762917225156, - 0.00000000000072838947272065741, - 0.00000000000026809646615211673, - -0.00000000000010960825046059278, - 0.00000000000002311949383800537, - -0.00000000000058469058005299247, - -0.00000000000002103748251144494, - -0.00000000000023323182945587408, - -0.00000000000042333694288141916, - -0.00000000000043933937969737844, - 0.00000000000041341647073835565, - 0.00000000000006841763641591466, - 0.00000000000047585534004430641, - 0.00000000000083679678674757695, - -0.00000000000085763734646658640, - 0.00000000000021913281229340092, - -0.00000000000062242842536431148, - -0.00000000000010983594325438430, - 0.00000000000065310431377633651, - -0.00000000000047580199021710769, - -0.00000000000037854251265457040, - 0.00000000000040939233218678664, - 0.00000000000087424383914858291, - 0.00000000000025218188456842882, - -0.00000000000003608131360422557, - -0.00000000000050518555924280902, - 0.00000000000078699403323355317, - -0.00000000000067020876961949060, - 0.00000000000016108575753932458, - 0.00000000000058527188436251509, - -0.00000000000035246757297904791, - -0.00000000000018372084495629058, - 0.00000000000088606689813494916, - 0.00000000000066486268071468700, - 0.00000000000063831615170646519, - 0.00000000000025144230728376072, - -0.00000000000017239444525614834); - - variable M, J:INTEGER; - variable F1, F2, G, Q, U, U2, V: REAL; - variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs - variable ONE: REAL := 1.0; --Made variable so no constant folding occurs - - -- double logb(), ldexp(); - - variable U1:REAL; - - begin - - -- Check validity of argument - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = MATH_E ) then - return 1.0; - end if; - - -- Argument reduction: 1 <= g < 2; x/2^m = g; - -- y = F*(1 + f/F) for |f| <= 2^-8 - - M := ILOGB(X); - G := LDEXP(X, -M); - J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding - F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] - F2 := G - F1; - - -- Approximate expansion for log(1+f2/F1) ~= u + q - G := 1.0/(2.0*F1+F2); - U := 2.0*F2*G; - V := U*U; - Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); - - -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, - -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. - -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. - -- - if ( J /= 0 or M /= 0) then - U1 := U + 513.0; - U1 := U1 - 513.0; - - -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero - -- u1 = u to 24 bits. - -- - else - U1 := U; - --TRUNC(U1); --In c this is u1 = (double) (float) (u1) - end if; - - U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; - -- u1 + u2 = 2f/(2F+f) to extra precision. - - -- log(x) = log(2^m*F1*(1+f2/F1)) = - -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); - -- (exact) + (tiny) - - U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact - U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny - U2 := U2 + LOGF_TAIL(N)*REAL(M); - return (U1 + U2); - end LOG; - - - function LOG2 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG2(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 2.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG2_OF_E*LOG(X) ); - end LOG2; - - - function LOG10 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG10(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 10.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG10_OF_E*LOG(X) ); - end LOG10; - - - function LOG (X: in REAL; BASE: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - if ( BASE <= 0.0 or BASE = 1.0 ) then - assert FALSE - report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = BASE ) then - return 1.0; - end if; - - -- Compute value for general case - return ( LOG(X)/LOG(BASE)); - end LOG; - - - function SIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) SIN(-X) = -SIN(X) - -- b) SIN(X) = X if ABS(X) < EPS - -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS - -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) - -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS - -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in SIN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then - return 0.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 then - if NEGATIVE then - return -1.0; - else - return 1.0; - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - if NEGATIVE then - return 1.0; - else - return -1.0; - end if; - end if; - - if XLOCAL < EPS then - if NEGATIVE then - return -XLOCAL; - else - return XLOCAL; - end if; - else - if XLOCAL < BASE_EPS then - TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_2_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - -- Compute value for general cases - if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then - VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); - end if; - - N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); - case QUADRANT( N mod 4) is - when 0 => - VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); - when 1 => - VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, - ROTATION)(0); - when 2 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); - when 3 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, - ROTATION)(0); - end case; - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end SIN; - - - function COS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) COS(-X) = COS(X) - -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) - -- c) COS(MATH_PI + X) = -COS(X) - -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS - -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in COS(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then - return 1.0; - end if; - - if XLOCAL = MATH_PI then - return -1.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then - return 0.0; - end if; - - TEMP := ABS(XLOCAL); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS(XLOCAL -MATH_2_PI); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS (XLOCAL - MATH_PI); - if TEMP < EPS then - return (-1.0 + 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - -- Compute value for general cases - return SIN(MATH_PI_OVER_2 - XLOCAL); - end COS; - - function TAN (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) TAN(0.0) = 0.0 - -- b) TAN(-X) = -TAN(X) - -- c) Returns REAL'LOW on error if X < 0.0 - -- d) Returns REAL'HIGH on error if X > 0.0 - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X) ; - variable VALUE: REAL; - variable TEMP : REAL; - - begin - -- Make 0.0 <= XLOCAL <= MATH_2_PI - if XLOCAL > MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in TAN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Check validity of argument - if XLOCAL = MATH_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'LOW); - else - return(REAL'HIGH); - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'HIGH); - else - return(REAL'LOW); - end if; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_PI then - return 0.0; - end if; - - -- Compute value for general cases - VALUE := SIN(XLOCAL)/COS(XLOCAL); - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TAN; - - function ARCSIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCSIN(-X) = -ARCSIN(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of arguments - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCSIN(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - elsif XLOCAL = 1.0 then - if NEGATIVE then - return -MATH_PI_OVER_2; - else - return MATH_PI_OVER_2; - end if; - end if; - - -- Compute value for general cases - if XLOCAL < 0.9 then - VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCSIN; - - function ARCCOS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of argument - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCCOS(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - elsif X = 0.0 then - return MATH_PI_OVER_2; - elsif X = -1.0 then - return MATH_PI; - end if; - - -- Compute value for general cases - if XLOCAL > 0.9 then - VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); - end if; - - - if NEGATIVE then - VALUE := MATH_PI - VALUE; - end if; - - return VALUE; - end ARCCOS; - - - function ARCTAN (Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCTAN(-Y) = -ARCTAN(Y) - -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 - -- c) ARCTAN(Y) = Y for |Y| < EPS - - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; - - variable NEGATIVE : BOOLEAN := Y < 0.0; - variable RECIPROCAL : BOOLEAN; - variable YLOCAL : REAL := ABS(Y); - variable VALUE : REAL; - - begin - -- Make argument |Y| <=1.0 - if YLOCAL > 1.0 then - YLOCAL := 1.0/YLOCAL; - RECIPROCAL := TRUE; - else - RECIPROCAL := FALSE; - end if; - - -- Compute value for special cases - if YLOCAL = 0.0 then - if RECIPROCAL then - if NEGATIVE then - return (-MATH_PI_OVER_2); - else - return (MATH_PI_OVER_2); - end if; - else - return 0.0; - end if; - end if; - - if YLOCAL < EPS then - if NEGATIVE then - if RECIPROCAL then - return (-MATH_PI_OVER_2 + YLOCAL); - else - return -YLOCAL; - end if; - else - if RECIPROCAL then - return (MATH_PI_OVER_2 - YLOCAL); - else - return YLOCAL; - end if; - end if; - end if; - - -- Compute value for general cases - VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); - - if RECIPROCAL then - VALUE := MATH_PI_OVER_2 - VALUE; - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function ARCTAN (Y : in REAL; X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable YLOCAL : REAL; - variable VALUE : REAL; - begin - - -- Check validity of arguments - if (Y = 0.0 and X = 0.0 ) then - assert FALSE report - "ARCTAN(0.0, 0.0) is undetermined" - severity ERROR; - return 0.0; - end if; - - -- Compute value for special cases - if Y = 0.0 then - if X > 0.0 then - return 0.0; - else - return MATH_PI; - end if; - end if; - - if X = 0.0 then - if Y > 0.0 then - return MATH_PI_OVER_2; - else - return -MATH_PI_OVER_2; - end if; - end if; - - - -- Compute value for general cases - YLOCAL := ABS(Y/X); - - VALUE := ARCTAN(YLOCAL); - - if X < 0.0 then - VALUE := MATH_PI - VALUE; - end if; - - if Y < 0.0 then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function SINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/2.0 - -- b) SINH(-X) = SINH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)*0.5; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end SINH; - - function COSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) + EXP(-X))/2.0 - -- b) COSH(-X) = COSH(X) - - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 1.0; - end if; - - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP + 1.0/TEMP)*0.5; - - return VALUE; - end COSH; - - function TANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) - -- b) TANH(-X) = -TANH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TANH; - - function ARCSINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X + 1.0)) - - begin - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X + 1.0)) ); - end ARCSINH; - - - - function ARCCOSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 - -- b) Returns X on error - - begin - -- Check validity of arguments - if X < 1.0 then - assert FALSE - report "X < 1.0 in ARCCOSH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X - 1.0))); - end ARCCOSH; - - function ARCTANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 - -- b) Returns X on error - begin - -- Check validity of arguments - if ABS(X) >= 1.0 then - assert FALSE - report "ABS(X) >= 1.0 in ARCTANH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); - end ARCTANH; - -end MATH_REAL; diff --git a/impl1/.recordref b/impl1/.recordref deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/.recordref_modgen b/impl1/.recordref_modgen deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/.vdbs/dbStat.txt b/impl1/.vdbs/dbStat.txt deleted file mode 100644 index e8652b9..0000000 --- a/impl1/.vdbs/dbStat.txt +++ /dev/null @@ -1 +0,0 @@ -top_rtl.vdb diff --git a/impl1/.vdbs/s1_impl1_map.vdb b/impl1/.vdbs/s1_impl1_map.vdb deleted file mode 100644 index 31c91454501236a014b62df9b64b0be92bbd71c1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 44946 zcmeHQTXQ4Fbp~vhVyvlBD%PN{nhXB2#a3PJ$3rxf^7P24mEBpuYl3$UW9so1_eceMvDks`h$SSSy zeWx#Hdirwa^qJ{bzP%q>4+K68$Y0~%|5m_{e!cs3g;rMX?%xXk!8hOj3x%A&Mm#VI zgg$t`tNs%v*3thy7`BC5*{G+J`?31V@%lWI`gbK@vMVn&pB- zOOrEqPnb8 z`tDlBq;e(|RaEsgBO_8yMxcVt6D^N)bp8J7qmHiO^b|VE;wF2F2Sst`E&w&Z$w19- zGEnoI4AlH412wjko^u zqt2=|)LT!2fnev<)lH$F>8K5|wk`{|v7AUWort-b%hDC@v=0B(EllR%3@2z) zf*dF4Qi3ce=wpI#XWa6tluj8`J zRcCaZ`u6gbz#@g#j*Fi%*2T8qfn|_fV@T{6-|9Aap$y9U3yZ7VMqH2;L2GNIMnt$Z z(dJOO57XAiXWA9rsa4bab;lB_$CJCsYU=fRT3^BL&L-ol#@rMVgX8pg()_qFp1DPM zH)ErIXFE~lTVb-?Ea9IVwI;spA}TAnTc2nD+^+B4+l`ww+IX&W_5A7S$+fjEQdsKU zsPEM(mg{7e>kOaIrq^Dll3VLjv$5H(%o_DMv;Weg;tfpJMreymB4M+d2^0YW<=|;&l=J-bR)!0rdvG=N{hdhU7 zY-G+xW^H8NMiy;k*+!NuQiWwD?|9rE+hJ zdXg}yoJnO(DsNInlPa53$)pZUs$fv-o%Z>$Y9USi^|poUTDZQ28(O%5g&SG8o`t)# za2FP?)3scOh3i_lzR4}S&qh5~-A$4_=|sM) z_4*|z@!H-!nNgRC)w1|NRExWWXVZyO>vY1?he5Koq3UkcS5x~TK;Q@g8G7?Fn^Amq7EpTk0xmjNad041|qm@F~f=E=Y4xQ#fX z%tEhrS*B95knP{ssnyx(@sFo^DUn>V2Du^`BEmm8ndv#g$1T7MmE=)H5}J3ANN!Wr zBEC(koReCE>AgjiFzX`Hs7u=Sy1Mk{*Xx=-v(!bTQJ37>>*~_)yk6Jw)icX=A!*c= z+<*DHx-X!bj zb@k3uSn8F@L{AkZS}&uCb;2>*N{{_Xv*&4+swl z_X&3iw+VL;tGYl4Kkhf~)&5rZS#Cfs3s zMCl242_N}aeMDLw;Z=mT;UWdxe?h@`39ugi99ue*lz9f8sI1cM10i4+#$lj|le&UlP7Rtl9~tEY(g(NIM}R?F58e zBhKV)!d=3B!b8FX!Xv^x!k2_E5UXp%6;G}a3Asij|AR&DLh{ZfB zrsvt2#Y;}4v9#~(_+-yguvvd84QJiC|^TM@)R_7{c zOvKSsC!A~1h{aF2`O_1dI~Pgg=2znW?%dVDn!1aLv~D+t+j3jn`ekM55N>NLgIaky zh$YHnESkC{cvk=1OLlbZ<31w+Uy0*B+fMqs&l(L?XApNiaqqNy z=o;uk3G2OxM4idh8(PY=K^*MCM(zmE0MHOnA5a$%ZVux%a!=nX4vqi~01W~40d)bv z_A_l%!+tyM#dr0+_+TH<5YPb72v83YLf`uUmMn^x<&tD=e&_(iih@kXdH5)33hTQ`l` zuyXS0Oxs|(2Gci~p}`CcW@IouX4oX)tuSvPlprQtwddiEL~@gd;@2$YA;XRfD`Q7% z9E`YG2xJf*om#v_L>j7W@A`X-WDttjt=Sud>kY9EP0tjOMqP=N{|@-AfEm9fHfL&Q zJGPgSjG7kf&OW&w=p_lO)l|H?O9`djK5A+Sad}#Ao{wAO*>i77lMPiF>0*KEhyt3`vhhz?O6KPs4ey+&9oJXY_vxr^78muoO;{9h6i9uSXxvqXAyvwa0 zB!2Zzu4#Z}{S!<5UPBx6hL4CfaGUqK`NKyD2=igeZWhRtSUtU@Yf;h;S%tALeVOIH%F z@5KEFjCgZo)lrGuy63A7P@Xzl_1*j1j!VpJJ)49TT0eb$baX0nj&JM92wJAmR9gI8 ziPqI7qO3p?m&Y3T$ykS5YBNz*A{F}QcMn$rS}Kbkw;C6-v**U9t%c^=BZb<|egBQy z#^0&hf|s5>C9aDeAbgm_2Tgnk#RpV;c*O@>eCWLdmkv63(D{RoA#@s{LkXQt=!ilm z)um^rt7`{@t{`+1p$iG!OXzw+w-mUn!j~swZ|amSv>xFR;Q`?x;XdIm;Wpt8;>bZP zUG-L2u~th=l$j_pk!K>yM2-pBS;T6iOdM=eiV_oLCW=htnaDDcV?s8DNHHST_7f=y zK+@YR*wLrfU>i^uP#@3`&;ZZ~P!G^0pbH&^q8aa5L*8S^Aj~1mBFrN!A}k{;0aQDU z(6MEw5wPqu0+yXdz_QZ_Sauo#%T6O;*=YnUJB@&4Zy2!b9RrrVWx%rc3|RK20n6Ss zVAsVrf%eE5|IVQ49rjG+bts|3I+Va+9ZJ}+27?!e zI{I8aPtpe4nljP`0L6aMrDDD4P;3_+ishn1v0HQ~R*MFM7e_k!T>W3t2Hv{r^aFrJ zl;#m;5#|tP5Jmw8FT8bA{BEDC7fu4|;b87+F(@X&a2JOPD57Fua6JyddsN zX*uynQOhwS7BQs}o0%A~s)-T1n;5aoi4of!nMi@$n2{U*sy6+5L*GaF{I@VQFm!MX2dL^G-A3CBjyb;VgeB(W)d-CN+ENz zzu`U*e3t!|M3#vh6B#C=OcdmMPpByq zB__&D6q(2~k!2#sM23kd69wL6Jz%25M45>q6L}_Xc7I)qRbH6;+;@MAxIrpok%$Zv zQ6>s`%5uO&iHR~3MJDo0WSPh@kzpdrL?O$XGErip%tVoiJQGd+lnhDH$q2L_p{OA%zc=QHs$7p*%{n z2y+NC2%`Y4feA8Dbj4+u=uifU4rPewPzHz&Wq9aN28Rx1Xy{M|h7M&|=uifQ4rNH_ zPzHn!B@{-75(uM134_t01i|P~LSS@wvw0++#fBJ>n@|<$A7TPrV(3cvf^erxp)`cM zg!_btga?F2gnNW9311NI^hrO$UBZ3BL&5{Zp)Y+gb+}T~$78dta+#!y)8z;9e}2yo*w$$yt5p9m0EVqKu>s)rY+( zs^~WyWfUG_)KPdqctp5I_>%Ai;ZC2Tpa^#f_X!UP4+xJ4_XuASz98Hgl757{g!_bt zga?F2gnNW9311NI3`jr1UBZ3DH&J9Vv;5CRk>xR{tcb9Tu!QgcVF6(@Th%7fPzGTR zVHRN?VG&^&VF}>@!UDo*9<@T4LzqRFM_5EyMp#04fUtltT12f7<`8BP-oybavx(vW zW!1sB!wbTlF3Q`4yM+6MhlB@&M}&KXF9}}|?(|7N!d=3B!b8FX#6f(E65p`Iw=eO{ zOnhq--{{1*J$r}l@K-TffG%_-VGw$dpS)%UkOBlLe2{_*DfEy66De%*04pjWjOIX% z48k13EW$j(BEmAl62b$71%%NoYK1U|FpDscun6!bayB5}RVv7#LAEbWn>=p@u3ofS zhu3^@y76afID`)1(2Yy#I>P zDDs{?5&ZsZBvsu97wye^t#T&NWqUql8=ot&2za_*JIFXoMZ@<^3Fk|g$}YWfhm_c< z63hcw!hHZsKoDRF83HUpMSvyj2(Sbu={QuNc^~2DwERe`9O+t0t00!}F_24u8DI%P z11v#mfF+C#umrm4I8=aTDD+~ihBt3hNC4u^TLQ{y8u|1eIk|aDK&DyMa%8jopRsB} z1u$~d+ri$PHGex8u)G}%Sl$i>EN=$`mbZfe%iF<#R-MSdGF!-j~{y9-hHVtKk#m9egxY`#HQ-T{II>sH6O!X3(%*X!(Bc*fH0pe zpr4?CA=t)=dXbFp5qr;VUsooQFE4ceny)K23aTZOt@DN)2X@-HQlImi9Upx(Yq%ez zMs3}s=bxA~k=U!t`DDBGo%D`;kbD0@t)9?K{S6VTFSP>sk}CE1qe`1=jrQazvI~QlMY1r3iDWTXNMf?wjbYOSC5TBz%WRf_ZLT$p_S~9w!D8AC^*!q^=yz9^kOiqS;6^q_nzT2EN+*Ggb3<0r`Z39^2Iyq}=xCn);~N`8U^KS9Aq@KUGUXfN!M4>_mvENB?Di{$XC+ym0bEtE_@}Ou5TOoO1i$1zMn+vWm->_rq+5H3A|oL z0t!VHdKn7zUZ&3)*vm+w^)ixZy^JJUFC&T8%SfX2 zGLmS$j3inwBZ=0_NTT&JlC-@ZLlUi*kwoidDB0Re)sv}u99LS^%RB+zorDN#sYE@M zjPG0W8Dh*Gt;PLvf(UcPWlDd2FInHNSZX98=DaK4BRe~MdeUf~9UY!G8z;uhWlMo= zbf*?isVm-zsc)lNG_WK5eM0`Z9P{6mKKs$E+nkI~8k5$Ur370FEF-Q? z3Ym|(3XSt%fQ0(h2LrKlskV76mgbbk4a@WzgMrQI_-tay$z6~bFs_}*X7p4n0r&ceQO)X9JkvF)Tu zowhS+r|nGIX*-j4+Rmh%wlis`?M&KfJA=OU(Q`3@xb1E~xF3^)Xz*&(W49Q173ziy zQtwLA_~MCEg=+32bxRg34yUyQX{9QvRg8YPE=QoEqH+qBN*H@pTtiETkW>>-?cBSU zmf@)!TWXBz!k1*QH_i^9x143ub+D=Nq~@4(H6DA}%yiVc8c$9RpBb6tSc}Pgjn<30 zdv$y^6&GGZR_aOX#I{0PQed-06MMN-W#_&a)aam-^;x`ja(yt!U-dKpQyUPcnFmyty4WhBvh8A-HWMiQ-;kwoidD7ht1z;hpl zXSsO?vu)I6zbDRLr#4yM=ncyrod02La%g2u9cL8Ex}9a1SL7fByvr72@+A-YMtw41dqKom*k)6 zAksDGY4t(PRZR}Uah|r2a#B_FRCrWzs9Mp_>I=zjUzUhFeBskmxQ0dj)n#f~3KsS2 zlyO|@BDoxmJejrlyc&b#dl;(L627-@BXFxZJ$ruT97XJ^CC#F2C&}ni3)_h(Wjhh2 zY$u|W?L?HaorqGl6H&@`LTcF*8}%<$ckgkhHd$_r@GmB(PkmcM;xvt8zLz!1`MR-q z?RDeGN*m9$uAUv9%s%!%u2K$MR4FFnyL21ei>vD@`o4(!``U2kM#fC+E|K+;+E7oAkii1LMSK8_#`n zRr=-ZBmaY!LxHvZc>srd17u#@GbwdWw5Z{x@|NGw2k&=XTHHlCUWql&jwNzS97NMA z*&Ugl#h*NW^u78I|M^k7{-pi5J{pa*F}w1kU+;chmGz(MpKxIHSM6WE^M_wi!19;=k z#@p|F_nm@*^UfPz`|uCm`q~>`{>qzQ{pyE*{>JaU@#PQS z`s&+X{%}i7=wv-t*_Tb)%FagaQN3QMcYpYBbNCx6UF>kJ^ltxgJtIehJlY)mMoJfB zUMoH0>OT67lrB#MTIovnTsrS_+B+hTL0Y|;`gh;`K;4mV zY4t+)32sVw0QQ8>RIfZ`Y4t|Udi72k-0W$U{`T(_Gq2<_zg2i;_>v5yt?xd0^u0%q zKls6;_STb!kGkD=A8)<)nubTk>$_)w!mwR0e`~ zr8o|Po0nRh_kY!E|FqlwW&2Y%uspbVm2NoAtA?9b?JcqO>JL?;yKOG-%{p(-3h|HY zbM}peaEbqVfxo+ut0BvUg#Uyxy-B!1cvVLsMr3_yt9EdzrZMtC9 z|AOCMfcF+<{?P(2FC?%gYQqGiW%{Q@ra$CNp&}~w$CTiA2?y@J^Ub%v(fEqYQ{Q~+ zTaCBhY0x|wSo!-!T`S*N2%`8YGqAPt)Dvrhv3wAo6fUW=KwF=sjpOOLEiTYUTLN1RRe#? ztJQL);D%qyEiQS*Vz8Xc=N1FMSXm5UxMBY42Vvqux3ZT)WuR+Q*K)O7K3HfpR-Wdn zL2hBCuu}DcgTq^H7}ocLe7RE0d3o(_tx%D^D<6C751YF?dt37Q>Yjfd)9+tiwJ(F{ zIH~QO_5Gc_^{wOHo!zbbjqQW9U(A)=QpsPsr_`Uy`(>}-=Uu;aJ6|cf zs(;6;c|~va=Ydz|CMQR;BV&_ebK|e0`@V#9>y-cjDMS|R;Rgb#Z3&-!4R!U3D~xx zDTe82gjNh_12P;aMv3B#${>ZFMkMu4G&^zQ;RIxtv4=z_S%n>FK)#elPB1c_0zkee z$}ddor?tkD1IV$^SgrSD+5kB`n2KvYnNUC-L`G}fu~Y+|B7LHlHVkE2UqJ;XDgr=G z1*T(?t=ct_oIH)xI%RTGVPm(s-q^06>2JE#)j~mj9rE594s_cu%6bAsBS&t?Pnj$Z zlfn(-2zNEnp>Z>BTss}LZAn7AbwjmnFC?$e%nz9#l;riHIAdmhCXTQe3HiBR(oU+@ z505IEZg-=ezYu)++SHeNyFYcBhJ@O@~MC7@n$goBqdkfY@amv|=Fm zeOM$Dc2vZ>#O4N!HHS~f+)?&Bl%-REn!u)_kV{bgi1LYe^s zRu)yB34ULp`h4JE~_RnSI-{$5zVz)J|bjw~c+ox^L82>VJuTAS$MEtLsN2exO zGoYSidtp$vni^htg6|(nr5x#Kd(_h0kxWK$Tcb;PiP_V z{c&XbJh^Ez@d^RtLJ<6cVp*OKwd{bLjm~DLve}ueSyeI&+}bR9k$l%K56CI1vuK{6 zEXosvAu0!lj#e+ntn?FYI6U+>qE}*~12NI0)i-h;{hR>!1#KX`@BT=|&MeuO;!6g8 h#oTn*5%@I&zhR*Gsmxoc37m5?dnT>+?yUUx$6r?`JU##b diff --git a/impl1/.vdbs/top_tech.vdb b/impl1/.vdbs/top_tech.vdb deleted file mode 100644 index ec31f7852055ae9525bcc8f16d68ffda4ef21698..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3630 zcmcIn+fQRf7@s+((CbnPRVoUUy1{ib>^D^hV&hNX-H|@mNW2%dgI)TOh z`W^`F&*9H3iqdDtJdVYinJ+A=y;y+k5w*72bo_jG`+(5N2JuZwre`BJgx1dX&vy?N6qMYJyD-;G_v>g zTwR~fE@X2?eRuCGW}3BDJ(12Nbt56*<`*)6-NNXsZ8SI6s}+df3iR(ozAhN5%S)-M zy4ThVt@Uc5a_C&&tdtsSyPkMbPqS1i9$T^845GMrZott?< z3j~LQ(;*0Q1yntIu%c}D;PJ1*(9Rw0xd=>1LPg1auUn5g@Q+bprLUNJ8(dWZOYg z_U#3e?XWw}nor8TyNJx9evv8qx)2=|fm(@oD}$k-f&S5uA~%3@E;v3F9vrq3v@Fc* z%Pp0{l0uEAXU2pc%+2xz-TefY)nrd!Lwpu)emhMPN(=KZO3&DGXBO@xg z%I(|D1G#RtDq2{(7A}3j1&S}7G4iqW(gMpbrFzTdt<~bHzgeo5w2eZeP-~hM?a!0m4vVe6$%XIo9q&2gG+s>6K0QSlxYBp;(SzR)ws+Y67CYG9Ka#o@W0_Qp<@*RzkMyJFX*1(N)F~AAFuOD*bNxq}eG^gL= zJ8}AtIdMd|aGvkz1d*T<{HcVGH6DuhTHIJdu_E+(Hvsj;a8)!aJb?HjqqA$=03#sk zl}>|+F0^QXXpfB(7+BmyputGmvx^I16TfFE{M%_StS~tmXq*cho#Ed?73=8h7+&yX ze1w{xqPeHVb{I3QDTOSUj>Kc0$X0%{f5Cv38VOfrD>d9nyTjV*t%BCAHQu46e2kzz cL0{_C4h^Ed+(r8%o#&2s(v}}K0sj>L0e-MVoB#j- diff --git a/impl1/_CMD_COMPILER.CML b/impl1/_CMD_COMPILER.CML deleted file mode 100644 index 645d8fa..0000000 --- a/impl1/_CMD_COMPILER.CML +++ /dev/null @@ -1 +0,0 @@ - -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -top top_tf -hdllog /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_compiler.srr -encrypt -mp 4 -prodtype synplify_premier -distcompmode 1 -verification_mode 0 -vhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/hadaq/mmichalek/lattice/simplified/impl1/dm -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd -verilog -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -dmgen /home/hadaq/mmichalek/lattice/simplified/impl1/dm -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -jobname "compiler" \ No newline at end of file diff --git a/impl1/_CMD_HDL_INFO_GEN.CML b/impl1/_CMD_HDL_INFO_GEN.CML deleted file mode 100644 index 6b4413b..0000000 --- a/impl1/_CMD_HDL_INFO_GEN.CML +++ /dev/null @@ -1 +0,0 @@ - -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_hdl_.srs -top top_tf -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/hadaq/mmichalek/lattice/simplified/impl1/dm -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd -lib work /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/syntax.log -fileorder /home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/hdlorder.tcl -jobname "hdl_info_gen" \ No newline at end of file diff --git a/impl1/_cmd._cml b/impl1/_cmd._cml deleted file mode 100644 index bb1545e..0000000 --- a/impl1/_cmd._cml +++ /dev/null @@ -1 +0,0 @@ --distcompmode -link -encrypt -top work.top_tf -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs \ No newline at end of file diff --git a/impl1/automake.err b/impl1/automake.err deleted file mode 100644 index d7d1216..0000000 --- a/impl1/automake.err +++ /dev/null @@ -1 +0,0 @@ -error waiting for process to exit: diff --git a/impl1/automake.log b/impl1/automake.log deleted file mode 100644 index fdbe3b4..0000000 --- a/impl1/automake.log +++ /dev/null @@ -1,2671 +0,0 @@ - -synpwrap -msg -prj "s1_impl1_synplify.tcl" -log "s1_impl1.srf" -Copyright (C) 1992-2019 Lattice Semiconductor Corporation. All rights reserved. -Lattice Diamond Version 3.11.2.446 - -###########################################################[ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Wed Jun 16 09:19:12 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Wed Jun 16 09:19:12 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Wed Jun 16 09:19:17 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Wed Jun 16 09:19:17 2021 - -multi_srs_gen completed -# Wed Jun 16 09:19:17 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Wed Jun 16 09:19:17 2021 - -premap completed with warnings -# Wed Jun 16 09:19:18 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Wed Jun 16 09:19:18 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Wed Jun 16 09:19:18 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Wed Jun 16 09:19:25 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier -Child process exit with 0. - -==contents of s1_impl1.srf -#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018 -#install: /opt/synplicity/O-2018.09-SP1 -#OS: Linux -#Hostname: lxhadeb07 - -# Wed Jun 16 09:19:13 2021 - -#Implementation: impl1 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! -File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -Running optimization stage 1 on fifo_colector ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -Running optimization stage 1 on tdc_channel_fifo_out ....... -Running optimization stage 1 on top_tf ....... - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] - -Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Divided design in to 1 groups -@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog " -Compiling work_top_tf_verilog as a separate process -Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s - -Distributed Compiler Report -*************************** - -DP Name Status Start time End Time Total Real Time Log File ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -work.top_tf.verilog Success 0h:00m:00s 0h:00m:01s 0h:00m:01s /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log -============================================================================================================================================================================== -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB) - -Process took 0h:00m:02s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:17 2021 - -###########################################################] -Premap Report - -# Wed Jun 16 09:19:17 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@A: MF827 |No constraint file specified. -@N: MF284 |Setting synthesis effort to medium for the design -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt -Printing clock summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - -syn_allowed_resources : blockrams=108 set on top level netlist top_tf - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------- -0 - System 200.0 MHz 5.000 system system_clkgroup 0 - -0 - pll0|CLKOS3_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_0 787 - -0 - top_tf|rd_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_4 64 - -0 - pll0|CLKOP_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_1 36 - -0 - pll0|CLKOS2_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_3 36 - -0 - pll0|CLKOS_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_2 36 -=============================================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System 0 - - - - - -pll0|CLKOS3_inferred_clock 787 pll0inst.PLLInst_0.CLKOS3(EHXPLLL) reset_dl[2:1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv) - -top_tf|rd_clk 64 rd_clk(port) fifo_colector_inst.fifo40_inst.FF_1.CK - - - -pll0|CLKOP_inferred_clock 36 pll0inst.PLLInst_0.CLKOP(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv) - -pll0|CLKOS2_inferred_clock 36 pll0inst.PLLInst_0.CLKOS2(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv) - -pll0|CLKOS_inferred_clock 36 pll0inst.PLLInst_0.CLKOS(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv) -============================================================================================================================================================================================================================================================= - -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s) -4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s) -0 instances converted, 895 sequential instances remain driven by gated/generated clocks - -===================================== Non-Gated/Non-Generated Clocks ====================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------ -@KP:ckid0_8 rd_clk Unconstrained_port 64 trb_adapter_inst.FEE_DATA_WRITE_OUT -=========================================================================================================== -======================================================================================== Gated/Generated Clocks ======================================================================================== -Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -@KP:ckid0_1 pll0inst.PLLInst_0.CLKOS3 EHXPLLL 787 reset_dl[2:1] Black box on clock path -@KP:ckid0_3 pll0inst.PLLInst_0.CLKOS2 EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2] Black box on clock path -@KP:ckid0_5 pll0inst.PLLInst_0.CLKOS EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1] Black box on clock path -@KP:ckid0_7 pll0inst.PLLInst_0.CLKOP EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0] Black box on clock path -======================================================================================================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jun 16 09:19:18 2021 - -###########################################################] -Map & Optimize Report - -# Wed Jun 16 09:19:18 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog)) -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:02s -0.86ns 187 / 525 - 2 0h:00m:02s -0.86ns 184 / 525 -@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing. -Timing driven replication report -Added 1 Registers via timing driven replication -Added 0 LUTs via timing driven replication - - 3 0h:00m:04s -0.74ns 186 / 526 - - - 4 0h:00m:04s -0.74ns 186 / 526 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB) - -Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - -@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. -@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. -@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. -@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. -@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Wed Jun 16 09:19:25 2021 -# - - -Top view: top_tf -Requested Frequency: 200.0 MHz -Wire load mode: top -Paths requested: 3 -Constraint File(s): -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: -0.652 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------ -pll0|CLKOP_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_1 -pll0|CLKOS2_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_3 -pll0|CLKOS3_inferred_clock 200.0 MHz 158.6 MHz 5.000 6.305 -0.652 inferred Inferred_clkgroup_0 -pll0|CLKOS_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_2 -top_tf|rd_clk 200.0 MHz 256.6 MHz 5.000 3.897 1.103 inferred Inferred_clkgroup_4 -System 200.0 MHz 527.3 MHz 5.000 1.897 3.103 system system_clkgroup -=================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------ -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------ -System pll0|CLKOS3_inferred_clock | 5.000 3.104 | No paths - | No paths - | No paths - -System top_tf|rd_clk | 5.000 3.104 | No paths - | No paths - | No paths - -pll0|CLKOS3_inferred_clock System | 5.000 3.782 | No paths - | No paths - | 5.000 4.247 -pll0|CLKOS3_inferred_clock pll0|CLKOS3_inferred_clock | 5.000 0.197 | 5.000 2.602 | 2.500 1.172 | 2.500 -0.653 -pll0|CLKOS3_inferred_clock top_tf|rd_clk | Diff grp - | No paths - | No paths - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOP_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS2_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -top_tf|rd_clk System | 5.000 3.807 | No paths - | No paths - | No paths - -top_tf|rd_clk pll0|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -top_tf|rd_clk top_tf|rd_clk | 5.000 1.104 | No paths - | No paths - | No paths - -=============================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: pll0|CLKOP_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS2_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -============================================================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -=============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS3_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast pll0|CLKOS3_inferred_clock FD1S3AX Q valid_fast 0.863 -0.652 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX Q window[2] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX Q window[5] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX Q window[6] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX Q window[7] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX Q window[3] 0.838 0.720 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX Q window[4] 0.838 0.720 -=============================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[7] 2.289 -0.652 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[5] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[6] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX PD window_6[2] 2.183 -0.581 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[3] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[4] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[1] 2.289 -0.475 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -============================================================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.942 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -0.652 - - Number of logic level(s): 7 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.992 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.992 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.599 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.599 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.942 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.942 - -============================================================================================================================================= - - -Path information for path number 2: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - -Path information for path number 3: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B0 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: top_tf|rd_clk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------ -fifo_colector_inst.fifo40_inst.FF_12 top_tf|rd_clk FD1S3DX Q w_gcount_r29 0.883 1.103 -fifo_colector_inst.fifo40_inst.FF_13 top_tf|rd_clk FD1S3DX Q w_gcount_r28 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_14 top_tf|rd_clk FD1S3DX Q w_gcount_r27 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_15 top_tf|rd_clk FD1S3DX Q w_gcount_r26 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_16 top_tf|rd_clk FD1S3DX Q w_gcount_r25 0.863 1.169 -fifo_colector_inst.fifo40_inst.FF_17 top_tf|rd_clk FD1S3DX Q w_gcount_r24 0.838 1.194 -fifo_colector_inst.fifo40_inst.FF_18 top_tf|rd_clk FD1S3DX Q w_gcount_r23 0.798 1.234 -fifo_colector_inst.fifo40_inst.FF_19 top_tf|rd_clk FD1S3DX Q w_gcount_r22 0.753 1.278 -fifo_colector_inst.fifo40_inst.FF_20 top_tf|rd_clk FD1S3DX Q w_gcount_r21 0.798 1.841 -fifo_colector_inst.fifo40_inst.FF_21 top_tf|rd_clk FD1S3DX Q w_gcount_r20 0.753 1.887 -================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_1 top_tf|rd_clk FD1S3BX D empty_d 4.789 1.103 -fifo_colector_inst.fifo40_inst.FF_62 top_tf|rd_clk FD1P3DX D ircount_9 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_63 top_tf|rd_clk FD1P3DX D ircount_8 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_64 top_tf|rd_clk FD1P3DX D ircount_7 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_65 top_tf|rd_clk FD1P3DX D ircount_6 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_66 top_tf|rd_clk FD1P3DX D ircount_5 4.789 2.457 -fifo_colector_inst.fifo40_inst.FF_67 top_tf|rd_clk FD1P3DX D ircount_4 4.789 2.457 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR5 rptr_0 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR6 rptr_1 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR7 rptr_2 3.223 2.470 -========================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r1 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B1 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.640 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.148 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_13 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_13 FD1S3DX Q Out 0.838 0.838 - -w_gcount_r28 Net - - - - 3 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD1 In 0.000 0.838 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.491 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.491 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.014 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.014 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.798 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.798 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.857 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.857 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.916 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.916 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 2.975 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 2.975 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.034 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.034 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.640 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.640 - -============================================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 -Block Rams : 4 of 108 (3%) - - -Details: -AND2: 8 -CCU2C: 121 -EHXPLLL: 1 -FD1P3AX: 69 -FD1P3BX: 8 -FD1P3DX: 232 -FD1P3IX: 50 -FD1S3AX: 321 -FD1S3BX: 4 -FD1S3DX: 164 -FD1S3IX: 41 -FD1S3JX: 10 -GSR: 1 -IB: 11 -IFS1P3DX: 5 -INV: 20 -OB: 173 -OBZ: 2 -OFS1P3DX: 17 -OFS1P3IX: 13 -OR2: 4 -ORCALUT4: 180 -PDPW16KD: 4 -PUR: 1 -ROM16X1A: 96 -VHI: 25 -VLO: 6 -XOR2: 72 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB) - -Process took 0h:00m:07s realtime, 0h:00m:07s cputime -# Wed Jun 16 09:19:25 2021 - -###########################################################] - - -Synthesis exit by 0. - -edif2ngd -l "ECP5UM5G" -d LFE5UM5G-45F -path "/home/hadaq/mmichalek/lattice/simplified/impl1" -path "/home/hadaq/mmichalek/lattice/simplified" "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi" "s1_impl1.ngo" -edif2ngd: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - - - - - - - - - - - - - - - - -Writing the design to s1_impl1.ngo... - -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 45 MB - - -ngdbuild -a "ECP5UM5G" -d LFE5UM5G-45F -p "/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data" -p "/home/hadaq/mmichalek/lattice/simplified/impl1" -p "/home/hadaq/mmichalek/lattice/simplified" "s1_impl1.ngo" "s1_impl1.ngd" -ngdbuild: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Reading 's1_impl1.ngo' ... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'... - - -Running DRC... - -DRC complete with no errors or warnings - -Design Results: - 1658 blocks expanded -Complete the first expansion. -Writing 's1_impl1.ngd' ... -Total CPU Time: 0 secs -Total REAL Time: 0 secs -Peak Memory Usage: 86 MB - - -map -a "ECP5UM5G" -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial "s1_impl1.ngd" -o "s1_impl1_map.ncd" -pr "s1_impl1.prf" -mp "s1_impl1.mrp" -lpf "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf" -lpf "/home/hadaq/mmichalek/lattice/simplified/s1.lpf" -xref_sym -xref_sig -tdm -map: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - Process the file: s1_impl1.ngd - Picdevice="LFE5UM5G-45F" - - Pictype="CABGA381" - - Picspeed=8 - - Remove unused logic - - Do not produce over sized NCDs. - -Part used: LFE5UM5G-45FCABGA381, Performance used: 8. - -Your license expires in 13 days. - -A new map free license can be generated from the Lattice website. A map subscription license can be purchased from your local Lattice sales representative or from the Lattice website. For more information on map software refer to http://www.latticesemi.com/latticediamond . -Loading device for application GENERIC from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. - - - - - - - - - - - - -Package Status: Final Version 1.38. - -Running general design DRC... - -Removing unused logic... - -Optimizing... - -144 CCU2 constant inputs absorbed. - - - - - - -Design Summary: - Number of registers: 934 out of 44457 (2%) - PFU registers: 899 out of 43848 (2%) - PIO registers: 35 out of 609 (6%) - Number of SLICEs: 692 out of 21924 (3%) - SLICEs as Logic/ROM: 692 out of 21924 (3%) - SLICEs as RAM: 0 out of 16443 (0%) - SLICEs as Carry: 121 out of 21924 (1%) - Number of LUT4s: 630 out of 43848 (1%) - Number used as logic LUTs: 388 - Number used as distributed RAM: 0 - Number used as ripple logic: 242 - Number used as shift registers: 0 - Number of PIO sites used: 187 out of 203 (92%) - Number of PIO sites used for single ended IOs: 185 - Number of PIO sites used for differential IOs: 2 (represented by 1 PIO comps in NCD) - Number of block RAMs: 4 out of 108 (4%) - Number of GSRs: 0 out of 1 (0%) - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - DTR used : No - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%) - Number of DCC: 0 out of 60 (0%) - Number of DCS: 0 out of 2 (0%) - Number of PLLs: 1 out of 4 (25%) - Number of DDRDLLs: 0 out of 4 (0%) - Number of CLKDIV: 0 out of 4 (0%) - Number of ECLKSYNC: 0 out of 10 (0%) - Number of ECLKBRIDGECS: 0 out of 2 (0%) - Number of DCUs: 0 out of 2 (0%) - Number of DCU Channels: 0 out of 4 (0%) - Number of EXTREFs: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. - - Number Of Mapped DSP Components: - -------------------------------- - MULT18X18D 0 - MULT9X9D 0 - ALU54B 0 - ALU24B 0 - PRADD18A 0 - PRADD9A 0 - -------------------------------- - Number of Used DSP MULT Sites: 0 out of 144 (0 %) - Number of Used DSP ALU Sites: 0 out of 72 (0 %) - Number of Used DSP PRADD Sites: 0 out of 144 (0 %) - Number of clocks: 6 - Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk ) - Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver: pll0inst/PLLInst_0 ) - Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver: pll0inst/PLLInst_0 ) - Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver: pll0inst/PLLInst_0 ) - Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver: pll0inst/PLLInst_0 ) - Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk ) - Number of Clock Enables: 18 - Net reset_dl[2]: 7 loads, 7 LSLICEs - Net N_248_i: 1 loads, 0 LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 LSLICEs - Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs - Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs - Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs - Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs - Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads, 6 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads, 13 LSLICEs - Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10 loads, 1 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1 LSLICEs - Number of LSRs: 13 - Net reset_dl[2]: 37 loads, 33 LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 loads, 1 LSLICEs - Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs - Net fifo_rden_c: 1 loads, 1 LSLICEs - Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced7_rising_i: 3 loads, 3 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_rising_i: 4 loads, 4 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4 loads, 4 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1 LSLICEs - Net valid_fast_RNI999V: 9 loads, 0 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i: 4 loads, 4 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net reset_dl[2]: 59 loads - Net fifo_colector_inst/iterator[0]: 47 loads - Net fifo_colector_inst/iterator[1]: 23 loads - Net fifo_colector_inst/in_empty_pmux_i: 22 loads - Net un1_hit_i_2_0_a2: 20 loads - Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads - - - - Number of warnings: 13 - Number of errors: 0 - - - -Total CPU Time: 4 secs -Total REAL Time: 5 secs -Peak Memory Usage: 361 MB - -Dumping design to file s1_impl1_map.ncd. - -trce -f "s1_impl1.mt" -o "s1_impl1.tw1" "s1_impl1_map.ncd" "s1_impl1.prf" -trce: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file s1_impl1_map.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:19:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf -Design file: s1_impl1_map.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,8 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 78 Score: 41485 -Cumulative negative slack: 24538 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:19:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf -Design file: s1_impl1_map.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 78 (setup), 0 (hold) -Score: 41485 (setup), 0 (hold) -Cumulative negative slack: 24538 (24538+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 3 secs -Total REAL Time: 4 secs -Peak Memory Usage: 369 MB - - -mpartrce -p "s1_impl1.p2t" -f "s1_impl1.p3t" -tf "s1_impl1.pt" "s1_impl1_map.ncd" "s1_impl1.ncd" - ----- MParTrce Tool ---- -Removing old design directory at request of -rem command line option to this program. -Running par. Please wait . . . - -Lattice Place and Route Report for Design "s1_impl1_map.ncd" -Wed Jun 16 09:19:35 2021 - -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf -Preference file: s1_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file s1_impl1_map.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Your license expires in 13 days. - -A new par free license can be generated from the Lattice website. A par subscription license can be purchased from your local Lattice sales representative or from the Lattice website. For more information on par software refer to http://www.latticesemi.com/latticediamond . -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 187/245 76% used - 187/203 92% bonded - IOLOGIC 35/245 14% used - - SLICE 692/21924 3% used - - EBR 4/108 3% used - PLL 1/4 25% used - - -Number of Signals: 1594 -Number of Connections: 3725 - -Pin Constraint Summary: - 7 out of 186 pins locked (3% locked). - -The following 5 signals are selected to use the primary clock routing resources: - pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0) - pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0) - rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0) - pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - - -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -............. -Finished Placer Phase 0. REAL time: 8 secs - -Starting Placer Phase 1. -................. -Placer score = 788909. -Finished Placer Phase 1. REAL time: 24 secs - -Starting Placer Phase 2. -. -Placer score = 774601 -Finished Placer Phase 2. REAL time: 25 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 12 (8%) - GR_PCLK : 0 out of 12 (0%) - PLL : 1 out of 4 (25%) - DCS : 0 out of 2 (0%) - DCC : 0 out of 60 (0%) - CLKDIV : 0 out of 4 (0%) - -Quadrant TL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - - PRIMARY : 5 out of 16 (31%) - -Quadrant TR Clocks: - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8 - - PRIMARY : 2 out of 16 (12%) - -Quadrant BL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - - PRIMARY : 5 out of 16 (31%) - -Quadrant BR Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - - PRIMARY : 5 out of 16 (31%) - -Edge Clocks: - - No edge clock selected. - - ---------------- End of Clock Report --------------- - - -+ -I/O Usage Summary (final): - 187 out of 245 (76.3%) PIO sites used. - 187 out of 203 (92.1%) bonded PIO sites used. - Number of PIO comps: 186; differential: 1. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+------------+------------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | -+----------+----------------+------------+------------+------------+ -| 0 | 27 / 27 (100%) | 2.5V | - | - | -| 1 | 29 / 33 ( 87%) | 2.5V | - | - | -| 2 | 31 / 32 ( 96%) | 2.5V | - | - | -| 3 | 27 / 33 ( 81%) | 2.5V | - | - | -| 6 | 28 / 33 ( 84%) | 2.5V | - | - | -| 7 | 32 / 32 (100%) | 2.5V | - | - | -| 8 | 13 / 13 (100%) | 2.5V | - | - | -+----------+----------------+------------+------------+------------+ - -Total placer CPU time: 24 secs - -Dumping design to file s1_impl1.dir/5_1.ncd. - -0 connections routed; 3725 unrouted. -Starting router resource preassignment - -Completed router resource preassignment. Real time: 39 secs - -Start NBR router at Wed Jun 16 09:20:14 CEST 2021 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021 - -Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021 -Level 1, iteration 1 -21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; -Estimated worst slack/total negative slack: -2.876ns/-158.654ns; real time: 41 secs -Level 2, iteration 1 -46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-159.217ns; real time: 41 secs -Level 3, iteration 1 -167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; -Estimated worst slack/total negative slack: -2.962ns/-163.305ns; real time: 42 secs -Level 4, iteration 1 -81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-177.384ns; real time: 42 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021 -Level 1, iteration 1 -53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-171.398ns; real time: 43 secs -Level 4, iteration 1 -54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 2 -35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 3 -24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 4 -12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 5 -8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 43 secs -Level 4, iteration 6 -5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 44 secs -Level 4, iteration 7 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 8 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 9 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.896ns; real time: 44 secs - -Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 156 (4.19%) - Estimated worst slack : -2.994ns - Timing score : 209210 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -Total CPU time 46 secs -Total REAL time: 47 secs -Completely routed. -End of route. 3725 routed (100.00%); 0 unrouted. - -Generating "par" statistics. - -Hold time timing score: 9, hold timing errors: 18 - -Timing score: 209210 - -Dumping design to file s1_impl1.dir/5_1.ncd. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -2.994 -PAR_SUMMARY::Timing score> = 209.210 -PAR_SUMMARY::Worst slack> = -1.015 -PAR_SUMMARY::Timing score> = 9.647 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 48 secs -Total REAL time to completion: 48 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Exiting par with exit code 0 -Exiting mpartrce with exit code 0 - -trce -f "s1_impl1.pt" -o "s1_impl1.twr" "s1_impl1.ncd" "s1_impl1.prf" -trce: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application trce from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:20:29 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf -Design file: s1_impl1.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,8 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Setup): ---------------- - -Timing errors: 280 Score: 209210 -Cumulative negative slack: 139580 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:20:29 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf -Design file: s1_impl1.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -Timing summary (Hold): ---------------- - -Timing errors: 18 Score: 9647 -Cumulative negative slack: 9647 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 280 (setup), 18 (hold) -Score: 209210 (setup), 9647 (hold) -Cumulative negative slack: 149227 (139580+9647) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - -Total CPU Time: 3 secs -Total REAL Time: 4 secs -Peak Memory Usage: 370 MB - - -iotiming "s1_impl1.ncd" "s1_impl1.prf" -I/O Timing Report: -: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Loading design for application iotiming from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application iotiming from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Running Performance Grade: 8 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 9 -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Running Performance Grade: 9 -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... - -Loading design for application iotiming from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: M -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Running Performance Grade: M -Computing Setup Time ... -Computing Max Clock to Output Delay ... -Computing Hold Time ... -Computing Min Clock to Output Delay ... -Done. - -ldbanno "s1_impl1.ncd" -n VHDL -o "s1_impl1_vho.vho" -noslice -w -neg -ldbanno: version Diamond (64-bit) 3.11.2.446 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Writing a VHDL netlist using the orca library type based on the s1_impl1 design file. - - -Loading design for application ldbanno from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application ldbanno from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Converting design s1_impl1.ncd into .ldb format. -Loading preferences from s1_impl1.prf. -Writing VHDL netlist to file s1_impl1_vho.vho -Writing SDF timing to file s1_impl1_vho.sdf - -Total CPU Time: 5 secs -Total REAL Time: 6 secs -Peak Memory Usage: 271 MB diff --git a/impl1/backup/s1_impl1.srr b/impl1/backup/s1_impl1.srr deleted file mode 100644 index bdc5717..0000000 --- a/impl1/backup/s1_impl1.srr +++ /dev/null @@ -1,637 +0,0 @@ -#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018 -#install: /opt/synplicity/O-2018.09-SP1 -#OS: Linux -#Hostname: lxhadeb07 - -# Mon Jul 27 07:12:33 2020 - -#Implementation: impl1 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/top.v" (library work) -Verilog syntax check successful! -Selecting top level module top -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top.v":1:7:1:9|Synthesizing module top in library work. -Running optimization stage 1 on top ....... - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon Jul 27 07:12:33 2020 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 66MB peak: 67MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon Jul 27 07:12:33 2020 - -###########################################################] - -Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -@W:: Distributed compilation : All files are passed to distribution points -Divided design in to 1 groups -@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top.verilog " -Compiling work_top_verilog as a separate process -Compilation of node work.top finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s - -Distributed Compiler Report -*************************** - -DP Name Status Start time End Time Total Real Time Log File ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -work.top.verilog Success 0h:00m:00s 0h:00m:01s 0h:00m:01s /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log -=========================================================================================================================================================================== -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 67MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon Jul 27 07:12:35 2020 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Process took 0h:00m:02s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon Jul 27 07:12:35 2020 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 67MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Mon Jul 27 07:12:37 2020 - -###########################################################] -Premap Report - -# Mon Jul 27 07:12:37 2020 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@A: MF827 |No constraint file specified. -@N: MF284 |Setting synthesis effort to medium for the design -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt -Printing clock summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -syn_allowed_resources : blockrams=108 set on top level netlist top - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------- -0 - top|clk 200.0 MHz 5.000 inferred Inferred_clkgroup_0 2 -============================================================================================ - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------ -top|clk 2 clk(port) cnt[1:0].C - - -=================================================================================== - -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top.v":25:0:25:5|Found inferred clock top|clk which controls 2 sequential elements including cnt[1:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 2 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -=========================== Non-Gated/Non-Generated Clocks ============================ -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- -@KP:ckid0_0 clk Unconstrained_port 2 cnt[1:0] -======================================================================================= - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 54MB peak: 141MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Mon Jul 27 07:12:37 2020 - -###########################################################] -Map & Optimize Report - -# Mon Jul 27 07:12:37 2020 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031430 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) - - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) - - -Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:00s 3.78ns 2 / 2 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 141MB) - -Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - -@W: MT420 |Found inferred clock top|clk with period 5.00ns. Please declare a user-defined clock on port clk. - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Mon Jul 27 07:12:39 2020 -# - - -Top view: top -Requested Frequency: 200.0 MHz -Wire load mode: top -Paths requested: 3 -Constraint File(s): -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 3.596 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------- -top|clk 200.0 MHz 712.3 MHz 5.000 1.404 3.596 inferred Inferred_clkgroup_0 -===================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------- -top|clk top|clk | 5.000 3.596 | No paths - | No paths - | No paths - -========================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: top|clk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------ -cnt[0] top|clk FD1S3IX Q CO0 0.838 3.596 -cnt[1] top|clk FD1S3IX Q cnt_c[1] 0.798 3.648 -============================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock --------------------------------------------------------------------------------- -cnt[0] top|clk FD1S3IX D CO0_i 4.789 3.596 -cnt[1] top|clk FD1S3IX D cnt_RNO[1] 4.789 3.608 -================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.193 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 3.596 - - Number of logic level(s): 1 - Starting point: cnt[0] / Q - Ending point: cnt[0] / D - The start point is clocked by top|clk [rising] on pin CK - The end point is clocked by top|clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------- -cnt[0] FD1S3IX Q Out 0.838 0.838 - -CO0 Net - - - - 3 -cnt_RNO[0] INV A In 0.000 0.838 - -cnt_RNO[0] INV Z Out 0.355 1.193 - -CO0_i Net - - - - 1 -cnt[0] FD1S3IX D In 0.000 1.193 - -================================================================================ - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.181 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 3.608 - - Number of logic level(s): 1 - Starting point: cnt[0] / Q - Ending point: cnt[1] / D - The start point is clocked by top|clk [rising] on pin CK - The end point is clocked by top|clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -cnt[0] FD1S3IX Q Out 0.838 0.838 - -CO0 Net - - - - 3 -cnt_RNO[1] ORCALUT4 A In 0.000 0.838 - -cnt_RNO[1] ORCALUT4 Z Out 0.343 1.181 - -cnt_RNO[1] Net - - - - 1 -cnt[1] FD1S3IX D In 0.000 1.181 - -================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.141 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 3.648 - - Number of logic level(s): 1 - Starting point: cnt[1] / Q - Ending point: cnt[1] / D - The start point is clocked by top|clk [rising] on pin CK - The end point is clocked by top|clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -cnt[1] FD1S3IX Q Out 0.798 0.798 - -cnt_c[1] Net - - - - 2 -cnt_RNO[1] ORCALUT4 B In 0.000 0.798 - -cnt_RNO[1] ORCALUT4 Z Out 0.343 1.141 - -cnt_RNO[1] Net - - - - 1 -cnt[1] FD1S3IX D In 0.000 1.141 - -================================================================================= - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - -Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 2 of 43848 (0%) -PIC Latch: 0 -I/O cells: 4 - - -Details: -FD1S3IX: 2 -GSR: 1 -IB: 2 -INV: 1 -OB: 2 -ORCALUT4: 1 -PUR: 1 -VHI: 1 -VLO: 1 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 144MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Mon Jul 27 07:12:39 2020 - -###########################################################] diff --git a/impl1/containment_cfg_verif.txt b/impl1/containment_cfg_verif.txt deleted file mode 100644 index ba51e5d..0000000 --- a/impl1/containment_cfg_verif.txt +++ /dev/null @@ -1,41 +0,0 @@ -top_tf.fifo_colector_inst.fifo40_inst work fifo40_dc 0 1 -top_tf.fifo_colector_inst work fifo_colector 0 1 -top_tf.trb_adapter_inst work trb_adapter 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_neg_inst work output_decoder8 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_inst work output_decoder8 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst work tdc4ddr_short 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst work tdc4ddr_short 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.trig_inv_inst1 work trig_inv 0 1 -top_tf.hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst work hades_tdc_channel_raw_out 0 1 -top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst work output_decoder8 0 1 -top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst work tdc4ddr_short 0 1 -top_tf.hades_tdc_bundle_inst.hades_LVL1_raw_out_inst work hades_LVL1_raw_out 0 1 -top_tf.hades_tdc_bundle_inst work hades_tdc_bundle 0 1 -top_tf.pll0inst work pll0 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1 -top_tf.genblk1\[2\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1 -top_tf.genblk1\[1\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst work fifo32dc 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.dec_neg_inst work output_decoder8 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.dec_inst work output_decoder8 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_neg_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst work tdc4ddr_short 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst3 work trig_inv 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst2 work trig_inv 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst.trig_inv_inst1 work trig_inv 0 1 -top_tf.genblk1\[0\]\.tdc_channel_fifo_out_inst work tdc_channel_fifo_out 0 1 diff --git a/impl1/containment_xmr_verif.txt b/impl1/containment_xmr_verif.txt deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/dm/layer0.xdm b/impl1/dm/layer0.xdm deleted file mode 100644 index 85ff6d9..0000000 --- a/impl1/dm/layer0.xdm +++ /dev/null @@ -1,2437 +0,0 @@ -%%% protect protected_file -@EG -- -]17p0Osk0CksRsPC#MHF=3"4j -"> -!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> -S -SS -S"/ -S1S -SF<1kCsOR"b=/0Fb/M#$bODHH/0$mj-.4jU3gu-14H/DL$/#M/HbEHOC/CxOHk#0LP#3"=RN"Rc"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-" -/>S1S -SF<1kCsOR"b=/0Fb/M#$bODHH/0$mj-.4jU3gu-14H/DLD/PF#o/OHCl_bbHC##3PRE"Nn=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S -SS1S"/ - -SF<1kCsOR"b=/lEFCN/E8/NJlOlHECND N/D0O0HCk/lDb0HDkD/N/s0#sFkOzC/q_)aeHCsDWFosbNbCas_mPu3"=RN""4jR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/ - -SF<1kCsOR"b=/lEFCN/E8/NJlOlHECND N/D0O0HCH/#lHbDV8HC/DbD_MsN8/Flb_DDs8NMFPl3"=RN""4.R"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/ -S -SS -S -SF<1kCsOR"b=/lEFCN/E8/NJlOlHECND N/D0O0HCH/#lHbDV8HC/b0F."3PR"N=4Rn"DP="CDsHFRo"O#DH0R="44cR(RR(4Rd"b#DH0-="4>"/ -"/ -< -S/k1Fs#OC> - - - -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s B.BzBC3PsFHDoD"R=C"PsFHDo -">SWSR/ -SqSSqS -SR"/ - -SRSuS"/ -SqS -SR -SR"/ - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s e3pmPHCsD"FoR"D=PHCsD"Fo>S -SSqS -SR"/ -S -S"/ -"/ - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s e3]QPHCsD"FoR"D=PHCsD"Fo>S -SSqS -SR"/ -S -S"/ -"/ - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s w174d37XPHCsD"FoR"D=PHCsD"Fo>S -SR/ -SqSS -S"/ -SqSS -S"/ -"/ - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s w174d3AXPHCsD"FoR"D=PHCsD"Fo>S -SR/ -SqSS -S"/ -SqS"/ -SqSSqS - - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s wu74d37XPHCsD"FoR"D=PHCsD"Fo>S -SR/ -SqSS -S"/ -SqS -SRS -SS -S -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s wu74d3AXPHCsD"FoR"D=PHCsD"Fo>S -SR/ -SqSS -S"/ -SqS -SRS -SS -S -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s uW7u47ni3sPCHoDF"=RD"sPCHoDF"S> -SRS -S"/ -SqS -SRS -S"/ -SuS"/ - -SR -SR -SR -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S -SRSuS"/ -S -S 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-S -SS -SSRS -S - -S-SC<7V=RM"sIF N3E8_C#0_8OL8kMDPC3CDsHFRo"DP="CDsHF>o" -R/ - -SRS -S"/ -"/ - -SRS -S -SRS -S"/ - -SR"/ - -SC<)V=RM"sIF N3E8_C#0_8OOMENM_CDs_NIF3k0PHCsD"FoR"H=ECN8#8_0OE_ONCMMDN_sIk_F0M_H#>0" -SSS -S)S)SSS -S - -S-SC<7V=RM"sIF ]3 XpuppC3PsFHDoD"R=C"PsFHDo -">SWSR/ -SqSS -SS -SSuS -SRS -S"/ -"/ -"/ -"/ -"/ -S -S -SR"/ - -SRS -S"/ - -SR"/ -SuS -SRSuSS -SSuSS -SSuSSuSSuSSuSSuS -SR"/ -S -SS -SS -S"/ - -SRS -S"/ -"/ -SqSSqS - - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s bjDD3sPCHoDF"=RD"sPCHoDF"S> -SRS -S -SRS -SSqSS -SSqS - - - - -SC<)V=RM"sIF ]3 XpuppC3PsFHDoH"R=p"up#QM0"_j>S -SSRR/ -SSS"/ -SSS"/ -SSS -SqSS -SSRS -SSRS -SSRS -SSRS -SSR"/ -SSSS -SqSS -SSRS -SSR"/ -SSSS -SqSS -SSR -SqS"/ -SSSS -SSRS"/ -SSSS -SSR -SqSS"/ -SSSS -SSRS -SSRS -SSRS -SSR"/ -SSSSS -SSRSSS -SSRS -SqSS -SSRS -SSRS -S -SC<)V=RM"sIF p3emC3PsFHDoH"R=O"#k_LNP_DFH0M#"S> -SWSR/ -S -SS -SSRS/S<)>CV -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s 0_Fb0PV3CDsHFRo"DP="CDsHF>o" -R/ - -SRSqS"/ - -SRSuS -SRSqSS -S - -SC<)V=RM"sIF H3VVOF_FODC03FsPHCsD"FoR"H=VFHV_DOFCFO0sM_H#>0" -SSS -S)S)SS -SSRS/S<)>CV -0" -SSS -S)S)S -SWSS -S -SC<)V=RM"sIF 830OE_ONCMMDH_VVFF_kP03CDsHFRo"Ho="CDML r4\.\\93O08_NOEMDMC_VVHFk_F0M_H#>0" -SSS -SqS -SqSSS -S -SC<)V=RM"sIF 830OE_ONCMMDH_VVFF_kP03CDsHFRo"Ho="CDML r4\4\\93O08_NOEMDMC_VVHFk_F0M_H#>0" -SSS -SqS -SqSSS -S -SC<)V=RM"sIF 830OE_ONCMMDH_VVFF_kP03CDsHFRo"Ho="CDML r4\j\\93O08_NOEMDMC_VVHFk_F0M_H#>0" -SSS -SqS -SqSSS -S - -/p]71k0sOs0kC@> - - - - diff --git a/impl1/dm/layer1.xdm b/impl1/dm/layer1.xdm deleted file mode 100644 index 295373a..0000000 --- a/impl1/dm/layer1.xdm +++ /dev/null @@ -1,148 +0,0 @@ -%%% protect protected_file -@EG -- -]17p0Osk0CksRsPC#MHF=3"4j -"> -!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S> -S -S"/ -S -S"/ -S1S"/ -S -SS -S -SF<1kCsOR"b=/lEFCN/E8/NJlOlHECND N/D0O0HCk/lDb0HDkD/N/s0#sFkOHC/MN0VOPC3ER8"NU=""=RD"8PEDO"RD0H#=4"-"DRbH=#0".R4" -/>S1S -SF<1kCsOR"b=/lEFCN/E8/NJlOlHECND N/D0O0HCk/lDb0HDkD/N/s0#sFkOsC/GCOPsE3P8N"R=j"4"=RD"8PEDO"RD0H#=4"-"DRbH=#0".R4" -/>S1S"/ - - - -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s QVM0N3OCHVM0N_OCND"R=E"P8>D" -SqSSqS -SRSqSS -S -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s vCF8lF3l8_ClND"R=E"P8>D" -S -SS -S"/ -S -SSqS - - - -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s )PGOCss3GCOPs"_NR"D=PDE8"S> -SRR/ - -SR -SR"/ - -SR"/ -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s aHGl0003G0lH0"_NR"D=PDE8"S> -SRR/ - -SR -SR"/ - -SR"/ -/S<7>CV -< -S!R--vkF8D7CRCMVHHF0HM-R->< -S7RCVMI="F3s z0Ns_b0F3skN0F_0b"_NR"D=PDE8"S> -SRR/ -"/ - -SR"/ - -SRSqS - - - - -SC<)V=RM"sIF G3al0H03l0GH_00NH"R=c"z"S> -SWS -SqS -SqS -SqS"/ -SSS -SqS"/ -SSS -SqS -SqS -SqS -SqSS"/ -S -SS -SSRS -SSRS -SSRSS -SSRSSSSS"/ -SSSS -S -SC<)V=RM"sIF F3v83CllCF8l"_NR"H=z>." -SSSR/ -SSS"/ -SSS -SqS"/ -SSS -SqS -SqS -SqS -SqSS"/ -S -SSSS -SSRSS -SSRSSS -SSRS -SSRS -SSRS -SSRS -SSRS -SSRS -SSRS -SSRSS -SSRS -SSRS -SSRS -SSR -SqSS/S<)>CV -/S<7>CV -]sC - -@ diff --git a/impl1/hdla_gen_hierarchy.html b/impl1/hdla_gen_hierarchy.html deleted file mode 100644 index f2d8ced..0000000 --- a/impl1/hdla_gen_hierarchy.html +++ /dev/null @@ -1,1101 +0,0 @@ - 
Setting log file to '/home/hadaq/mmichalek/lattice/simplified/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/standard.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_attr.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc
-INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real
-INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/synattr.vhd
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes
-(VERI-1482) Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/modules2.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top2.v
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(181,22-181,35) (VERI-1116) fifo_data_out is already declared
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(64,46-64,59) (VERI-1967) previous declaration of fifo_data_out is from here
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(181,22-181,35) (VERI-1329) second declaration of fifo_data_out ignored
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(64,46-64,59) (VERI-1310) fifo_data_out is declared here
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_modules.v
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(170,13-170,24) (VERI-1362) decoder_out is already implicitly declared on line 156
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(171,13-171,28) (VERI-1362) decoder_out_neg is already implicitly declared on line 163
-(VERI-1482) Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_colector.v
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(1,24-1,30) (VERI-1128) wr_clk is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(2,9-2,15) (VERI-1128) rd_clk is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(3,9-3,14) (VERI-1128) reset is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(4,9-4,16) (VERI-1128) in_data is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(5,9-5,17) (VERI-1128) in_empty is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(6,9-6,23) (VERI-1128) in_read_enable is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(7,9-7,17) (VERI-1128) out_data is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(8,9-8,18) (VERI-1128) out_empty is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(9,9-9,24) (VERI-1128) out_read_enable is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(10,9-10,16) (VERI-1128) discard is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(12,9-12,19) (VERI-1128) raw_enable is not declared
-ERROR - /home/hadaq/mmichalek/lattice/simplified/hades_colector.v(1,1-21,10) (VERI-1072) module hades_colector ignored due to previous errors
-(VERI-1483) Verilog file /home/hadaq/mmichalek/lattice/simplified/hades_colector.v ignored due to errors
-(VHDL-1481) Analyzing VHDL file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.vhd
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(235,8-235,15) (VHDL-1012) analyzing entity intface
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(278,14-278,23) (VHDL-1010) analyzing architecture intface_a
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(50,8-50,13) (VHDL-1012) analyzing entity modem
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(70,14-70,21) (VHDL-1010) analyzing architecture modem_a
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(50,8-50,14) (VHDL-1012) analyzing entity rxcver
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(76,14-76,22) (VHDL-1010) analyzing architecture rxcver_a
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(50,8-50,14) (VHDL-1012) analyzing entity txmitt
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(74,14-74,22) (VHDL-1010) analyzing architecture txmitt_a
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(50,8-50,16) (VHDL-1012) analyzing entity uart_top
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(85,14-85,24) (VHDL-1010) analyzing architecture uart_top_a
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd
-INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(8,8-8,15) (VHDL-1012) analyzing entity trb5_tb
-INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(12,14-12,24) (VHDL-1010) analyzing architecture behavioral
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(9,8-9,18) (VHDL-1012) analyzing entity endp_dummy
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(28,14-28,24) (VHDL-1010) analyzing architecture behavioral
-(VHDL-1481) Analyzing VHDL file /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(11,8-11,20) (VHDL-1012) analyzing entity endp_handler
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(30,14-30,24) (VHDL-1010) analyzing architecture behavioral
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v(8,8-8,12) (VERI-1018) compiling module pll1
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v(8,1-75,10) (VERI-9000) elaborating module 'pll1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(47,8-47,31) (VERI-1018) compiling module UART_VerilogWrapper_TOP
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(47,1-127,10) (VERI-9000) elaborating module 'UART_VerilogWrapper_TOP'
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(103,6-125,8) (VERI-1231) going to vhdl side to elaborate module uart_top
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd(50,8-50,16) (VHDL-1067) elaborating Uart_top_uniq_0(Uart_top_a)
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd(235,8-235,15) (VHDL-1067) elaborating Intface_uniq_0(Intface_a)
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd(50,8-50,13) (VHDL-1067) elaborating Modem_uniq_0(Modem_a)
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd(50,8-50,14) (VHDL-1067) elaborating Rxcver_uniq_0(Rxcver_a)
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd(50,8-50,14) (VHDL-1067) elaborating Txmitt_uniq_0(Txmitt_a)
-INFO - /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v(103,6-125,8) (VERI-1232) back to verilog to continue elaboration
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v(8,8-8,12) (VERI-1018) compiling module pll8
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v(8,1-80,10) (VERI-9000) elaborating module 'pll8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v(8,8-8,18) (VERI-1018) compiling module pll_random
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v(8,1-85,10) (VERI-9000) elaborating module 'pll_random'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(191,8-191,15) (VERI-1018) compiling module tdc4ddr
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(191,1-234,10) (VERI-9000) elaborating module 'tdc4ddr'
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,8-1,14) (VERI-1018) compiling module top_tf
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,1-228,10) (VERI-9000) elaborating module 'top_tf'
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v(8,1-90,10) (VERI-9000) elaborating module 'pll0_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(2,1-194,10) (VERI-9000) elaborating module 'hades_tdc_bundle_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(230,1-319,11) (VERI-9000) elaborating module 'trb_adapter_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(3,1-95,10) (VERI-9000) elaborating module 'fifo_colector_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_4'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(2,1-106,10) (VERI-9000) elaborating module 'hades_LVL1_raw_out_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(110,1-216,10) (VERI-9000) elaborating module 'hades_tdc_channel_raw_out_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v(8,1-1114,10) (VERI-9000) elaborating module 'fifo40_dc_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_5'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_26'
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(1,1-228,10) (VERI-9000) elaborating module 'top_tf'
-INFO - /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v(8,1-90,10) (VERI-9000) elaborating module 'pll0_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(2,1-194,10) (VERI-9000) elaborating module 'hades_tdc_bundle_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/top2.v(230,1-319,11) (VERI-9000) elaborating module 'trb_adapter_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(3,1-95,10) (VERI-9000) elaborating module 'fifo_colector_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(3,1-158,10) (VERI-9000) elaborating module 'tdc_channel_fifo_out_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_4'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_5'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_6'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_7'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_8'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_9'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_4'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_5'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_6'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_7'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_8'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_9'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_4'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_5'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_6'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_7'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_8'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_9'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(1696,1-1738,10) (VERI-9000) elaborating module 'EHXPLLL_uniq_4'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(2,1-106,10) (VERI-9000) elaborating module 'hades_LVL1_raw_out_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(110,1-216,10) (VERI-9000) elaborating module 'hades_tdc_channel_raw_out_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v(8,1-1114,10) (VERI-9000) elaborating module 'fifo40_dc_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v(8,1-1076,10) (VERI-9000) elaborating module 'fifo32dc_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_59'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_60'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_61'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_62'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_63'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_64'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_65'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_66'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_67'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_68'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_69'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_70'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_71'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_72'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_59'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_60'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_61'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_62'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_63'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_64'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_65'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_66'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_67'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_68'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_69'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_70'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_71'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_72'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_73'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_74'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_75'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_76'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_77'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_78'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_79'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_80'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_81'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_82'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_83'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_84'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_85'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_86'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_87'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_88'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_89'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_90'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_91'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_92'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_93'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_94'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_95'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_96'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_59'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_60'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_61'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_62'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_63'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_64'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_65'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_66'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_67'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_68'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_69'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_70'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_71'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_72'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_73'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_74'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_75'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_76'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_77'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_78'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_79'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_80'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_81'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_82'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_83'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_84'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_85'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_86'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_87'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_88'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_89'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_90'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_91'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_92'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_93'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_94'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_95'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_96'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_97'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_98'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_99'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_100'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_101'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_102'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_103'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_104'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_105'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_106'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_107'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_108'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_109'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_110'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_111'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_112'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_113'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_114'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_115'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_116'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_117'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_118'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_119'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_120'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_121'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_122'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_123'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_124'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_125'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_126'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_127'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_128'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_129'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_130'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_131'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_132'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_133'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_134'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_135'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_136'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_137'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_138'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_139'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_140'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_141'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_142'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_143'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_144'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_145'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_146'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_147'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_148'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_149'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_150'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_151'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_152'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_153'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_154'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_155'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_156'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_157'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_158'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_159'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_160'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_161'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_162'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_163'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_164'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_165'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_166'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_167'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_168'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_169'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_170'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_171'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_172'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_173'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_174'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_175'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_176'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_177'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_178'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_179'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_180'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_181'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_182'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_183'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_184'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_185'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_186'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_187'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_188'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_189'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_190'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_191'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_192'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_193'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_194'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_195'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_196'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_197'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_198'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_199'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_200'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_201'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_202'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_203'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_204'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_205'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_206'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_207'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_208'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_209'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_210'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_211'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_212'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_213'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_214'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_215'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_216'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_217'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_218'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_219'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_220'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_221'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_222'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_223'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_224'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_225'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_226'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_227'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_228'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_229'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_230'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_231'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_232'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_59'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_60'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_61'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_62'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_63'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_64'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_65'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_66'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_67'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_68'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_69'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_70'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_71'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_72'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_73'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_74'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_75'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_76'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_77'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_78'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_79'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_80'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_81'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_82'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_83'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_84'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_85'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_86'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_87'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_88'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_89'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_90'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_91'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_92'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_93'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_94'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_95'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_96'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_97'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_98'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_99'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_100'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_101'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_102'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_103'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_104'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_105'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_106'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_107'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_108'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_109'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_110'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_111'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_112'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_113'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_114'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_115'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_116'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_117'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_118'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_119'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_120'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_121'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_122'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_123'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_124'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_125'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_126'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_127'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_128'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_129'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_130'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_131'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_132'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_133'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_134'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_135'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_136'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_137'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_138'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_139'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_140'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_141'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_142'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_143'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_144'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_145'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_146'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_147'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_148'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_149'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_150'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_151'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_152'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_153'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_154'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_155'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_156'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_157'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_158'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_159'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_160'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_161'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_162'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_163'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_164'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_59'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_60'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_61'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_62'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_63'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_64'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_65'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_66'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_67'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_68'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_69'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_70'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_71'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_72'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_73'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_74'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_75'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_76'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_77'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_78'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_79'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_80'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_81'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_82'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_83'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_84'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_85'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_86'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_87'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_88'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_89'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_90'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_91'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_92'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_93'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_94'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_95'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_96'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_97'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_98'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_99'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_100'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_101'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_102'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_103'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_104'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(757,1-759,10) (VERI-9000) elaborating module 'VHI_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(761,1-763,10) (VERI-9000) elaborating module 'VLO_uniq_5'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(160,1-189,10) (VERI-9000) elaborating module 'tdc4ddr_short_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_1'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_2'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(236,1-337,10) (VERI-9000) elaborating module 'output_decoder8_uniq_3'
-INFO - /home/hadaq/mmichalek/lattice/simplified/modules2.v(341,1-347,10) (VERI-9000) elaborating module 'trig_inv_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(25,1-29,10) (VERI-9000) elaborating module 'AND2_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(367,1-370,10) (VERI-9000) elaborating module 'INV_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(656,1-660,10) (VERI-9000) elaborating module 'OR2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(810,1-814,10) (VERI-9000) elaborating module 'XOR2_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(710,1-717,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(959,1-1047,10) (VERI-9000) elaborating module 'PDPW16KD_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(110,1-117,10) (VERI-9000) elaborating module 'FD1P3BX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_45'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_46'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_47'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_48'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_49'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_50'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_51'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_52'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_53'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_54'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_55'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_56'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_57'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(119,1-126,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_58'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_26'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_27'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_28'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_29'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_30'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_31'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_32'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_33'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_34'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_35'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_36'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_37'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_38'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_39'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_40'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(168,1-174,10) (VERI-9000) elaborating module 'FD1S3DX_uniq_41'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(160,1-166,10) (VERI-9000) elaborating module 'FD1S3BX_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_1'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_2'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_3'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_4'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_5'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_6'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_7'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_8'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_9'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_10'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_11'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_12'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_13'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_14'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_15'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_16'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_17'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_18'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_19'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_20'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_21'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_22'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_23'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_24'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_25'
-INFO - /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v(76,1-91,10) (VERI-9000) elaborating module 'CCU2C_uniq_26'
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(137,11-137,37) (VERI-1330) actual bit length 9 differs from formal bit length 12 for port LVL1_offset
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(51,2-56,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(153,2-158,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v(160,2-165,40) (VERI-1927) port in_synced_lb remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/hades_modules.v(187,22-187,59) (VERI-1330) actual bit length 1 differs from formal bit length 2 for port raw_valid_vect
-WARNING - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(40,1-51,9) (VERI-1927) port RPReset remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(194,9-194,33) (VERI-1330) actual bit length 32 differs from formal bit length 40 for port out_data
-WARNING - /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v(47,7-47,17) (VERI-1330) actual bit length 32 differs from formal bit length 1 for port Reset
-WARNING - /home/hadaq/mmichalek/lattice/simplified/modules2.v(83,2-88,9) (VERI-1927) port in_synced_lb remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/modules2.v(90,2-95,40) (VERI-1927) port in_synced_lb remains unconnected for this instance
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(209,11-209,26) (VERI-1330) actual bit length 20 differs from formal bit length 28 for port coarse
-WARNING - /home/hadaq/mmichalek/lattice/simplified/top2.v(211,11-211,64) (VERI-1330) actual bit length 24 differs from formal bit length 32 for port fifo_data_out
-INFO - /home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd(8,8-8,15) (VHDL-1067) elaborating trb5_tb(Behavioral)
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd(11,8-11,20) (VHDL-1067) elaborating endp_handler_uniq_0(Behavioral)
-INFO - /home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd(9,8-9,18) (VHDL-1067) elaborating endp_dummy_uniq_0(Behavioral)
-Done: design load finished with (12) errors, and (16) warnings
-
-
\ No newline at end of file diff --git a/impl1/impl1_syn.prj b/impl1/impl1_syn.prj deleted file mode 100644 index 9ef85f1..0000000 --- a/impl1/impl1_syn.prj +++ /dev/null @@ -1,87 +0,0 @@ -#-- Synopsys, Inc. -#-- Version O-2018.09-SP1 -#-- Project file /home/hadaq/mmichalek/lattice/simplified/impl1/impl1_syn.prj -#-- Written on Sun Jan 24 23:19:27 2021 - - -#project files -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top.v" -add_file -verilog "../pll0/pll0.v" -add_file -verilog "../pll1/pll1.v" -add_file -verilog "../fifo32dc/fifo32dc.v" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" -add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" -add_file -verilog "../pll8/pll8.v" -add_file -verilog "../pll_random/pll_random.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules.v" - - - -#implementation: "impl1" -impl -add impl1 -type fpga - -# -#implementation attributes - -set_option -vlog_std sysv -set_option -project_relative_includes 1 -set_option -hdl_define -set SBP_SYNTHESIS -set_option -include_path {/home/hadaq/mmichalek/lattice/simplified} - -#device options -set_option -technology ECP5UM5G -set_option -part LFE5UM5G_45F -set_option -package BG381C -set_option -speed_grade -8 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "top" - -# hdl_compiler_options -set_option -distributed_compile 0 - -# mapper_without_write_options -set_option -frequency auto -set_option -srs_instrumentation 1 - -# mapper_options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -# Lattice XP -set_option -maxfan 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 1 -set_option -forcegsr no -set_option -fix_gated_and_generated_clocks 1 -set_option -rw_check_on_ram 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# NFilter -set_option -no_sequential_opt 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 1 -set_option -multi_file_compilation_unit 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./impl1.edi" -impl -active "impl1" diff --git a/impl1/launch_synplify.tcl b/impl1/launch_synplify.tcl deleted file mode 100644 index 9b2387b..0000000 --- a/impl1/launch_synplify.tcl +++ /dev/null @@ -1,66 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file /home/hadaq/mmichalek/lattice/simplified/impl1/launch_synplify.tcl -#-- Written on Sun Jan 24 23:19:20 2021 - -project -close -set filename "/home/hadaq/mmichalek/lattice/simplified/impl1/impl1_syn.prj" -if ([file exists "$filename"]) { - project -load "$filename" - project_file -remove * -} else { - project -new "$filename" -} -set create_new 0 - -#device options -set_option -technology ECP5UM5G -set_option -part LFE5UM5G_45F -set_option -package BG381C -set_option -speed_grade -8 - -if {$create_new == 1} { -#-- add synthesis options - set_option -symbolic_fsm_compiler true - set_option -resource_sharing false - set_option -vlog_std v2001 - set_option -frequency 200 - set_option -maxfan 1000 - set_option -auto_constrain_io 0 - set_option -disable_io_insertion false - set_option -retiming false; set_option -pipe true - set_option -force_gsr auto - set_option -compiler_compatible 0 - set_option -dup false - - set_option -default_enum_encoding default - - set_option -num_critical_paths 3 - - set_option -write_apr_constraint 1 - set_option -fix_gated_and_generated_clocks 1 - set_option -update_models_cp 0 - set_option -resolve_multiple_driver 0 - - - -} -#-- add_file options -set_option -hdl_define -set SBP_SYNTHESIS -set_option -include_path "/home/hadaq/mmichalek/lattice/simplified" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" -add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" -add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" -add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" -add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" -add_file -vhdl -lib "work" "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" -add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules.v" -#-- top module name -set_option -top_module {top} -project -result_file {/home/hadaq/mmichalek/lattice/simplified/impl1/impl1.edi} -project -save "$filename" diff --git a/impl1/message.xml b/impl1/message.xml deleted file mode 100644 index c5b5771..0000000 --- a/impl1/message.xml +++ /dev/null @@ -1,599 +0,0 @@ - - - - - 1100086 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic error in "BLOCK NET "tdc_out*" ;": - tdc_out* - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 10 - - - 1100679 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic error in "LOCATE COMP "reset" SITE "D11" ;": - reset - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 48 - - - 1101611 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic error in "UGROUP "trig_gate0" BBOX 1 1 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO - BLKNAME trig_pad_RNII4FF[0];": - Block "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1" of UGROUP "trig_gate0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO" of UGROUP "trig_gate0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2" of UGROUP "trig_gate0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO" of UGROUP "trig_gate0" not found in design - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 59 - - - 1100675 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic error in "LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;": - trig_gate0 - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 60 - - - 1101611 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic error in "UGROUP "tdc_ch0" BBOX 1 6 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de .... _inst/dec_inst/out_internal[2] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;": - Block "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc_ch0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc_ch0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]" of UGROUP "tdc_ch0" not found in designBlock "genblk1[0].tdc_cha .... out_internal[1]" of UGROUP "tdc_ch0" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]" of UGROUP "tdc_ch0" not found in design - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 95 - - - 1100675 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic error in "LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;": - tdc_ch0 - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 96 - - - 1101611 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic error in "UGROUP "tdc2" BBOX 1 6 - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_ .... st/dec_inst/valid - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": - Block "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc2" not found in designBlock "genblk1[1].td .... ternal[2]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "tdc2" not found in design - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 141 - - - 1100675 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic error in "LOCATE UGROUP "tdc2" SITE "R65C41D" ;": - tdc2 - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 142 - - - 1101611 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic error in "UGROUP "dec3" BBOX 1 6 - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_ .... st/dec_inst/valid - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": - Block "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "dec3" not found in designBlock "genblk1[2].td .... ternal[2]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "dec3" not found in design - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 264 - - - 1100675 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic error in "LOCATE UGROUP "dec3" SITE "R65C49D" ;": - dec3 - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 265 - - - 1101611 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic error in "UGROUP "tdc0_neg" BBOX 1 4 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_ .... enblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7];": - Block "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]" of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]" of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b .... of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]" of UGROUP "tdc0_neg" not found in design - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 289 - - - 1100675 - Warning - /home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic error in "LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;": - tdc0_neg - /home/hadaq/mmichalek/lattice/simplified/s1.lpf - 290 - - - 1104614 - Warning - Semantic error in "PGROUP "lvl1_dec" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_ins .... inst/SLICE_734" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";": - lvl1_dec - - - - - 35002000 - Info - - - 35001781 - Info - - - 35901018 - Info - /home/hadaq/mmichalek/lattice/simplified/top.v(1): - top - /home/hadaq/mmichalek/lattice/simplified/top.v - 1 - - - 35001611 - Warning - - - 1166052 - Warning - logical - GND_net - GND_net - - - 1163101 - Warning - 1 - - - - - 35400250 - Info - 0 - - - - - 35400250 - Info - 0 - - - - - 1121027 - Warning - MEM_INIT_FILE - - - 1121027 - Warning - MEM_INIT_FILE - - - 1121027 - Warning - MEM_INIT_FILE - - - 1121027 - Warning - MEM_INIT_FILE - - - 1121028 - Warning - TDC_WIDTH - - - 1121028 - Warning - COARSE_WIDTH - - - 1121028 - Warning - WINDOW_LENGTH - - - 1121028 - Warning - TDC_WIDTH - - - 1121028 - Warning - COARSE_WIDTH - - - 1121028 - Warning - ADDRESS_WIDTH - - - 1121028 - Warning - COARSE_WIDTH_INTERNAL - - - 1121028 - Warning - HITBUFFER_DEPTH - - - 1121028 - Warning - TDC_WIDTH - - - 1121028 - Warning - COARSE_WIDTH - - - 1121028 - Warning - TRIG_WIDTH - - - 1121028 - Warning - ADDRESS_WIDTH - - - - - 2011000 - Info - - - 2019991 - Warning - CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. - CG921 - /home/hadaq/mmichalek/lattice/simplified/top2.v - 181 - 21 - 181 - 33 - fifo_data_out is already declared in this scope. - - - 2019991 - Warning - CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. - CG1337 - /home/hadaq/mmichalek/lattice/simplified/top2.v - 270 - 9 - 270 - 24 - Net buf_rden_falling is not declared. - - - 2019991 - Warning - CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out - CG1249 - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v - 170 - 12 - 170 - 22 - Redeclaration of implicit signal decoder_out - - - 2019991 - Warning - CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg - CG1249 - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v - 171 - 12 - 171 - 26 - Redeclaration of implicit signal decoder_out_neg - - - 2019991 - Warning - CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. - CG921 - /home/hadaq/mmichalek/lattice/simplified/top2.v - 181 - 21 - 181 - 33 - fifo_data_out is already declared in this scope. - - - 2019991 - Warning - CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. - CG1337 - /home/hadaq/mmichalek/lattice/simplified/top2.v - 270 - 9 - 270 - 24 - Net buf_rden_falling is not declared. - - - 2019991 - Warning - CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out - CG1249 - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v - 170 - 12 - 170 - 22 - Redeclaration of implicit signal decoder_out - - - 2019991 - Warning - CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg - CG1249 - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v - 171 - 12 - 171 - 26 - Redeclaration of implicit signal decoder_out_neg - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. - BN114 - /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v - 407 - 13 - 407 - 25 - Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. - - - 2019991 - Warning - MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - MT529 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 181 - 3 - 181 - 8 - Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - - - 2019991 - Warning - MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - MT529 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 181 - 3 - 181 - 8 - Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - - - 2019991 - Warning - MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - MT529 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 181 - 3 - 181 - 8 - Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - - - 2019991 - Warning - MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - MT529 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 181 - 3 - 181 - 8 - Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - - - 2019991 - Warning - MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - MT529 - /home/hadaq/mmichalek/lattice/simplified/top2.v - 305 - 2 - 305 - 7 - Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - BN132 - /home/hadaq/mmichalek/lattice/simplified/modules2.v - 138 - 1 - 138 - 6 - Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - - - 2019991 - Warning - MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - MT246 - /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v - 60 - 12 - 60 - 20 - Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) - - - 2019993 - Warning - MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. - MT420 - Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. - - - 2019993 - Warning - MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. - MT420 - Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. - - - 2019993 - Warning - MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. - MT420 - Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. - - - 2019993 - Warning - MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. - MT420 - Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. - - - 2019993 - Warning - MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - MT420 - Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - - - \ No newline at end of file diff --git a/impl1/run_options.txt b/impl1/run_options.txt deleted file mode 100644 index f585b1f..0000000 --- a/impl1/run_options.txt +++ /dev/null @@ -1,100 +0,0 @@ -#-- Synopsys, Inc. -#-- Version O-2018.09-SP1 -#-- Project file /home/hadaq/mmichalek/lattice/simplified/impl1/run_options.txt -#-- Written on Wed Jun 16 09:19:13 2021 - - -#project files -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules2.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top2.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd" - - - -#implementation: "impl1" -impl -add impl1 -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -num_critical_paths 3 -set_option -project_relative_includes 1 -set_option -hdl_define -set SBP_SYNTHESIS -set_option -include_path {/home/hadaq/mmichalek/lattice/simplified} - -#device options -set_option -technology ECP5UM5G -set_option -part LFE5UM5G_45F -set_option -package BG381C -set_option -speed_grade -8 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "top_tf" - -# hdl_compiler_options -set_option -distributed_compile 1 - -# mapper_without_write_options -set_option -frequency 200 -set_option -srs_instrumentation 1 - -# mapper_options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -# Lattice XP -set_option -maxfan 1000 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 1 -set_option -forcegsr auto -set_option -fix_gated_and_generated_clocks 1 -set_option -rw_check_on_ram 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# NFilter -set_option -no_sequential_opt 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 0 -set_option -multi_file_compilation_unit 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "./s1_impl1.edi" - -#set log file -set_option log_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf" - -#design plan options -impl -active "impl1" diff --git a/impl1/s1_impl1.alt b/impl1/s1_impl1.alt deleted file mode 100644 index 2d05fcf..0000000 --- a/impl1/s1_impl1.alt +++ /dev/null @@ -1,90 +0,0 @@ -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Wed May 26 19:57:02 2021 * -NOTE DESIGN NAME: top_tf * -NOTE DEVICE NAME: LFE5UM5G-45F-8CABGA381 * -NOTE PIN ASSIGNMENTS * -NOTE PINS fifo_data_out[0] : B8 : out * -NOTE PINS clk : P3 : in * -NOTE PINS release_out : F1 : out * -NOTE PINS finished : J5 : out * -NOTE PINS last_buf_empty : H5 : out * -NOTE PINS discard : E2 : out * -NOTE PINS burst : F2 : out * -NOTE PINS LVL1_TRG_DATA_VALI_IN_rising : G3 : out * -NOTE PINS FEE_TRG_RELEASE_OUT : H2 : out * -NOTE PINS FEE_DATAFINISHED_OUT : G2 : out * -NOTE PINS FEE_DATA_WRITE_OUT : G5 : out * -NOTE PINS FEE_DATA_OUT[31] : C9 : out * -NOTE PINS FEE_DATA_OUT[30] : C6 : out * -NOTE PINS FEE_DATA_OUT[29] : C2 : out * -NOTE PINS FEE_DATA_OUT[28] : C5 : out * -NOTE PINS FEE_DATA_OUT[27] : A7 : out * -NOTE PINS FEE_DATA_OUT[26] : A9 : out * -NOTE PINS FEE_DATA_OUT[25] : F5 : out * -NOTE PINS FEE_DATA_OUT[24] : D11 : out * -NOTE PINS FEE_DATA_OUT[23] : E13 : out * -NOTE PINS FEE_DATA_OUT[22] : H3 : out * -NOTE PINS FEE_DATA_OUT[21] : B12 : out * -NOTE PINS FEE_DATA_OUT[20] : A14 : out * -NOTE PINS FEE_DATA_OUT[19] : A12 : out * -NOTE PINS FEE_DATA_OUT[18] : C3 : out * -NOTE PINS FEE_DATA_OUT[17] : E9 : out * -NOTE PINS FEE_DATA_OUT[16] : C1 : out * -NOTE PINS FEE_DATA_OUT[15] : C10 : out * -NOTE PINS FEE_DATA_OUT[14] : E8 : out * -NOTE PINS FEE_DATA_OUT[13] : A4 : out * -NOTE PINS FEE_DATA_OUT[12] : A2 : out * -NOTE PINS FEE_DATA_OUT[11] : C13 : out * -NOTE PINS FEE_DATA_OUT[10] : D1 : out * -NOTE PINS FEE_DATA_OUT[9] : B3 : out * -NOTE PINS FEE_DATA_OUT[8] : C4 : out * -NOTE PINS FEE_DATA_OUT[7] : D5 : out * -NOTE PINS FEE_DATA_OUT[6] : A10 : out * -NOTE PINS FEE_DATA_OUT[5] : A6 : out * -NOTE PINS FEE_DATA_OUT[4] : D6 : out * -NOTE PINS FEE_DATA_OUT[3] : D7 : out * -NOTE PINS FEE_DATA_OUT[2] : D12 : out * -NOTE PINS FEE_DATA_OUT[1] : D10 : out * -NOTE PINS FEE_DATA_OUT[0] : C8 : out * -NOTE PINS LVL1_INVALID_TRG_IN : G1 : in * -NOTE PINS LVL1_TRG_DATA_VALID_IN : F3 : in * -NOTE PINS fifo_rden : H4 : out * -NOTE PINS fifo_data_out[31] : A11 : out * -NOTE PINS fifo_data_out[30] : C7 : out * -NOTE PINS fifo_data_out[29] : F4 : out * -NOTE PINS fifo_data_out[28] : A5 : out * -NOTE PINS fifo_data_out[27] : A8 : out * -NOTE PINS fifo_data_out[26] : B10 : out * -NOTE PINS fifo_data_out[25] : E5 : out * -NOTE PINS fifo_data_out[24] : E11 : out * -NOTE PINS fifo_data_out[23] : D13 : out * -NOTE PINS fifo_data_out[22] : E1 : out * -NOTE PINS fifo_data_out[21] : C12 : out * -NOTE PINS fifo_data_out[20] : C14 : out * -NOTE PINS fifo_data_out[19] : A13 : out * -NOTE PINS fifo_data_out[18] : D3 : out * -NOTE PINS fifo_data_out[17] : D9 : out * -NOTE PINS fifo_data_out[16] : B1 : out * -NOTE PINS fifo_data_out[15] : B9 : out * -NOTE PINS fifo_data_out[14] : D8 : out * -NOTE PINS fifo_data_out[13] : B5 : out * -NOTE PINS fifo_data_out[12] : B2 : out * -NOTE PINS fifo_data_out[11] : B13 : out * -NOTE PINS fifo_data_out[10] : D2 : out * -NOTE PINS fifo_data_out[9] : B4 : out * -NOTE PINS fifo_data_out[8] : A3 : out * -NOTE PINS fifo_data_out[7] : E4 : out * -NOTE PINS fifo_data_out[6] : C11 : out * -NOTE PINS fifo_data_out[5] : B6 : out * -NOTE PINS fifo_data_out[4] : E6 : out * -NOTE PINS fifo_data_out[3] : E7 : out * -NOTE PINS fifo_data_out[2] : E12 : out * -NOTE PINS fifo_data_out[1] : E10 : out * -NOTE PINS trig[2] : T19 : in * -NOTE PINS trig[1] : T3 : in * -NOTE PINS trig[0] : R2 : in * -NOTE PINS reset_dc : E3 : in * -NOTE PINS rd_clk : B11 : in * -NOTE CONFIGURATION MODE: JTAG * -NOTE COMPRESSION: off * diff --git a/impl1/s1_impl1.arearep b/impl1/s1_impl1.arearep deleted file mode 100644 index 276b7e0..0000000 --- a/impl1/s1_impl1.arearep +++ /dev/null @@ -1,12 +0,0 @@ ----------------------------------------------------------------------- -Report for cell top.TECH -Register bits: 2 of 44457 (0.004%) -I/O cells: 4 - Cell usage: - cell count Res Usage(%) - FD1S3IX 2 100.0 - GSR 1 100.0 - IB 2 100.0 - LUT4 2 100.0 - OB 2 100.0 - TOTAL 9 diff --git a/impl1/s1_impl1.areasrr b/impl1/s1_impl1.areasrr deleted file mode 100644 index 422ad73..0000000 --- a/impl1/s1_impl1.areasrr +++ /dev/null @@ -1,490 +0,0 @@ ----------------------------------------------------------------------- -Report for cell top_tf.verilog - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 - Cell usage: - cell count Res Usage(%) - AND2 8 100.0 - CCU2C 121 100.0 - EHXPLLL 1 100.0 - FD1P3AX 69 100.0 - FD1P3BX 8 100.0 - FD1P3DX 232 100.0 - FD1P3IX 50 100.0 - FD1S3AX 321 100.0 - FD1S3BX 4 100.0 - FD1S3DX 164 100.0 - FD1S3IX 41 100.0 - FD1S3JX 10 100.0 - GSR 1 100.0 - IB 11 100.0 - IFS1P3DX 5 100.0 - INV 20 100.0 - OB 173 100.0 - OBZ 2 100.0 - OFS1P3DX 17 100.0 - OFS1P3IX 13 100.0 - OR2 4 100.0 - ORCALUT4 180 100.0 - PDPW16KD 4 100.0 - PUR 1 100.0 - ROM16X1A 96 100.0 - VHI 25 100.0 - VLO 6 100.0 - XOR2 72 100.0 -SUB MODULES - fifo32dc 1 100.0 - fifo32dc_0 1 100.0 - fifo32dc_1 1 100.0 - fifo40_dc 1 100.0 - fifo_colector 1 100.0 - hades_LVL1_raw_out 1 100.0 - hades_tdc_bundle 1 100.0 - hades_tdc_channel_raw_out 1 100.0 - output_decoder8_0 1 100.0 - output_decoder8_0_0 1 100.0 - output_decoder8_0_1 1 100.0 - output_decoder8_2 1 100.0 - output_decoder8_2_0 1 100.0 - output_decoder8_2_1 1 100.0 - pll0 1 100.0 - tdc4ddr_short 1 100.0 - tdc4ddr_short_0 1 100.0 - tdc4ddr_short_1 1 100.0 - tdc4ddr_short_2 1 100.0 - tdc4ddr_short_3 1 100.0 - tdc4ddr_short_4 1 100.0 - tdc_channel_fifo_out 1 100.0 - tdc_channel_fifo_out_2 1 100.0 - tdc_channel_fifo_out_3 1 100.0 - trb_adapter 1 100.0 - trig_inv 1 100.0 - - TOTAL 1685 ----------------------------------------------------------------------- -Report for cell tdc_channel_fifo_out_3.netlist - Original Cell name tdc_channel_fifo_out - Instance path: genblk1[2].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3AX 49 15.3 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - FD1S3IX 3 7.3 - INV 2 10.0 - OR2 1 25.0 - ORCALUT4 5 2.8 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 4 16.0 - VLO 1 16.7 - XOR2 18 25.0 -SUB MODULES - fifo32dc_1 1 100.0 - output_decoder8_2_1 1 100.0 - tdc4ddr_short_4 1 100.0 - - TOTAL 241 ----------------------------------------------------------------------- -Report for cell fifo32dc_1.netlist - Original Cell name fifo32dc - Instance path: genblk1[2].tdc_channel_fifo_out_inst.fifo32dc_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - INV 2 10.0 - OR2 1 25.0 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 1 4.0 - VLO 1 16.7 - XOR2 18 25.0 - - TOTAL 178 ----------------------------------------------------------------------- -Report for cell output_decoder8_2_1.netlist - Original Cell name output_decoder8_2 - Instance path: genblk1[2].tdc_channel_fifo_out_inst.dec_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 25 7.8 - FD1S3IX 1 2.4 - ORCALUT4 4 2.2 - VHI 1 4.0 - - TOTAL 31 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short_4.netlist - Original Cell name tdc4ddr_short - Instance path: genblk1[2].tdc_channel_fifo_out_inst.tdc_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - VHI 1 4.0 - - TOTAL 25 ----------------------------------------------------------------------- -Report for cell tdc_channel_fifo_out_2.netlist - Original Cell name tdc_channel_fifo_out - Instance path: genblk1[1].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3AX 49 15.3 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - FD1S3IX 3 7.3 - INV 2 10.0 - OR2 1 25.0 - ORCALUT4 5 2.8 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 4 16.0 - VLO 1 16.7 - XOR2 18 25.0 -SUB MODULES - fifo32dc_0 1 100.0 - output_decoder8_2_0 1 100.0 - tdc4ddr_short_3 1 100.0 - - TOTAL 241 ----------------------------------------------------------------------- -Report for cell fifo32dc_0.netlist - Original Cell name fifo32dc - Instance path: genblk1[1].tdc_channel_fifo_out_inst.fifo32dc_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - INV 2 10.0 - OR2 1 25.0 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 1 4.0 - VLO 1 16.7 - XOR2 18 25.0 - - TOTAL 178 ----------------------------------------------------------------------- -Report for cell output_decoder8_2_0.netlist - Original Cell name output_decoder8_2 - Instance path: genblk1[1].tdc_channel_fifo_out_inst.dec_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 25 7.8 - FD1S3IX 1 2.4 - ORCALUT4 4 2.2 - VHI 1 4.0 - - TOTAL 31 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short_3.netlist - Original Cell name tdc4ddr_short - Instance path: genblk1[1].tdc_channel_fifo_out_inst.tdc_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - VHI 1 4.0 - - TOTAL 25 ----------------------------------------------------------------------- -Report for cell tdc_channel_fifo_out.netlist - Original Cell name tdc_channel_fifo_out - Instance path: genblk1[0].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3AX 49 15.3 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - FD1S3IX 3 7.3 - INV 2 10.0 - OR2 1 25.0 - ORCALUT4 5 2.8 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 4 16.0 - VLO 1 16.7 - XOR2 18 25.0 -SUB MODULES - fifo32dc 1 100.0 - output_decoder8_2 1 100.0 - tdc4ddr_short_2 1 100.0 - - TOTAL 241 ----------------------------------------------------------------------- -Report for cell fifo32dc.netlist - Original Cell name fifo32dc - Instance path: genblk1[0].tdc_channel_fifo_out_inst.fifo32dc_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - INV 2 10.0 - OR2 1 25.0 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 1 4.0 - VLO 1 16.7 - XOR2 18 25.0 - - TOTAL 178 ----------------------------------------------------------------------- -Report for cell output_decoder8_2.netlist - Original Cell name output_decoder8 - Instance path: genblk1[0].tdc_channel_fifo_out_inst.dec_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 25 7.8 - FD1S3IX 1 2.4 - ORCALUT4 4 2.2 - VHI 1 4.0 - - TOTAL 31 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short_2.netlist - Original Cell name tdc4ddr_short - Instance path: genblk1[0].tdc_channel_fifo_out_inst.tdc_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - VHI 1 4.0 - - TOTAL 25 ----------------------------------------------------------------------- -Report for cell fifo_colector.netlist - Instance path: fifo_colector_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3AX 10 14.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1P3IX 24 48.0 - FD1S3AX 3 0.9 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - FD1S3IX 3 7.3 - INV 2 10.0 - OR2 1 25.0 - ORCALUT4 48 26.7 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 2 8.0 - VLO 1 16.7 - XOR2 18 25.0 -SUB MODULES - fifo40_dc 1 100.0 - - TOTAL 268 ----------------------------------------------------------------------- -Report for cell fifo40_dc.netlist - Instance path: fifo_colector_inst.fifo40_inst - Cell usage: - cell count Res Usage(%) - AND2 2 25.0 - CCU2C 26 21.5 - FD1P3BX 2 25.0 - FD1P3DX 58 25.0 - FD1S3BX 1 25.0 - FD1S3DX 41 25.0 - INV 2 10.0 - OR2 1 25.0 - PDPW16KD 1 25.0 - ROM16X1A 24 25.0 - VHI 1 4.0 - VLO 1 16.7 - XOR2 18 25.0 - - TOTAL 178 ----------------------------------------------------------------------- -Report for cell trb_adapter.netlist - Instance path: trb_adapter_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 6 1.9 - FD1S3IX 1 2.4 - ORCALUT4 4 2.2 - VHI 1 4.0 - - TOTAL 12 ----------------------------------------------------------------------- -Report for cell hades_tdc_bundle.netlist - Instance path: hades_tdc_bundle_inst - Cell usage: - cell count Res Usage(%) - CCU2C 17 14.0 - FD1P3AX 59 85.5 - FD1P3IX 26 52.0 - FD1S3AX 164 51.1 - FD1S3IX 28 68.3 - FD1S3JX 10 100.0 - INV 6 30.0 - ORCALUT4 113 62.8 - VHI 9 36.0 -SUB MODULES - hades_LVL1_raw_out 1 100.0 - hades_tdc_channel_raw_out 1 100.0 - output_decoder8_0 1 100.0 - output_decoder8_0_0 1 100.0 - output_decoder8_0_1 1 100.0 - tdc4ddr_short 1 100.0 - tdc4ddr_short_0 1 100.0 - tdc4ddr_short_1 1 100.0 - trig_inv 1 100.0 - - TOTAL 441 ----------------------------------------------------------------------- -Report for cell hades_tdc_channel_raw_out.netlist - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst - Cell usage: - cell count Res Usage(%) - CCU2C 8 6.6 - FD1P3AX 26 37.7 - FD1P3IX 24 48.0 - FD1S3AX 104 32.4 - FD1S3IX 3 7.3 - FD1S3JX 6 60.0 - INV 1 5.0 - ORCALUT4 34 18.9 - VHI 5 20.0 -SUB MODULES - output_decoder8_0_0 1 100.0 - output_decoder8_0_1 1 100.0 - tdc4ddr_short_0 1 100.0 - tdc4ddr_short_1 1 100.0 - trig_inv 1 100.0 - - TOTAL 216 ----------------------------------------------------------------------- -Report for cell output_decoder8_0_1.netlist - Original Cell name output_decoder8_0 - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_neg_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 28 8.7 - FD1S3IX 1 2.4 - FD1S3JX 3 30.0 - ORCALUT4 13 7.2 - VHI 1 4.0 - - TOTAL 46 ----------------------------------------------------------------------- -Report for cell output_decoder8_0_0.netlist - Original Cell name output_decoder8_0 - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.dec_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 28 8.7 - FD1S3IX 1 2.4 - FD1S3JX 3 30.0 - ORCALUT4 14 7.8 - VHI 1 4.0 - - TOTAL 47 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short_1.netlist - Original Cell name tdc4ddr_short - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - VHI 1 4.0 - - TOTAL 25 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short_0.netlist - Original Cell name tdc4ddr_short - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - VHI 1 4.0 - - TOTAL 25 ----------------------------------------------------------------------- -Report for cell trig_inv.netlist - Instance path: hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.trig_inv_inst1 - Cell usage: - cell count Res Usage(%) - INV 1 5.0 - - TOTAL 1 ----------------------------------------------------------------------- -Report for cell hades_LVL1_raw_out.netlist - Instance path: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst - Cell usage: - cell count Res Usage(%) - CCU2C 5 4.1 - FD1P3IX 2 4.0 - FD1S3AX 60 18.7 - FD1S3IX 8 19.5 - FD1S3JX 4 40.0 - INV 4 20.0 - ORCALUT4 44 24.4 - VHI 3 12.0 -SUB MODULES - output_decoder8_0 1 100.0 - tdc4ddr_short 1 100.0 - - TOTAL 132 ----------------------------------------------------------------------- -Report for cell output_decoder8_0.netlist - Original Cell name output_decoder8 - Instance path: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 29 9.0 - FD1S3IX 1 2.4 - FD1S3JX 3 30.0 - INV 1 5.0 - ORCALUT4 15 8.3 - VHI 1 4.0 - - TOTAL 50 ----------------------------------------------------------------------- -Report for cell tdc4ddr_short.netlist - Original Cell name tdc4ddr_short - Instance path: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst - Cell usage: - cell count Res Usage(%) - FD1S3AX 24 7.5 - INV 3 15.0 - VHI 1 4.0 - - TOTAL 28 ----------------------------------------------------------------------- -Report for cell pll0.netlist - Instance path: pll0inst - Cell usage: - cell count Res Usage(%) - EHXPLLL 1 100.0 - VLO 1 16.7 - - TOTAL 2 diff --git a/impl1/s1_impl1.bgn b/impl1/s1_impl1.bgn deleted file mode 100644 index e325a9a..0000000 --- a/impl1/s1_impl1.bgn +++ /dev/null @@ -1,80 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.11.2.446 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed May 26 19:56:50 2021 - - -Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s /home/hadaq/mmichalek/lattice/simplified/s1.sec -k /home/hadaq/mmichalek/lattice/simplified/s1.bek -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf - -Loading design for application Bitgen from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application Bitgen from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from s1_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| CfgMode | Disable** | -+---------------------------------+---------------------------------+ -| DONE_EX | OFF** | -+---------------------------------+---------------------------------+ -| DONE_OD | ON** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.4** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| CONFIG_MODE | JTAG** | -+---------------------------------+---------------------------------+ -| WAKE_UP | 21** | -+---------------------------------+---------------------------------+ -| INBUF | OFF** | -+---------------------------------+---------------------------------+ -| ES | No** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | OFF** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ -| DisableUES | FALSE** | -+---------------------------------+---------------------------------+ -| SLAVE_PARALLEL_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| DONE_PULL | ON** | -+---------------------------------+---------------------------------+ -| CONFIG_IOVOLTAGE | 2.5** | -+---------------------------------+---------------------------------+ -| TRANSFR | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 10.27. - -Saving bit stream in "s1_impl1.bit". -Total CPU Time: 11 secs -Total REAL Time: 12 secs -Peak Memory Usage: 576 MB diff --git a/impl1/s1_impl1.bit b/impl1/s1_impl1.bit deleted file mode 100644 index 7ef1eed7d89f5868fc493c85feae3eedcf4e1e90..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1032627 zcmeF43A`OemH(^ndoSDskee8sO9ma8&-My1S~Y@9VBURbADOe{=eiyj!>H zRQ>vV>r{1j-MW46V@I!EyLQdVr-sL#`rX|GH-FsVA>J=PaJJ`kdEJvwPx+h z@;$j@hd=Z1L&L@A9(?d&OWA$*-S_E_z@Pgb#~Aww{9iXaJbX`hjo|;0@PGZq3;zKx zEp1odb6-nJAhYLAB<6rNVRQhIqR|ON!bliv2+(j<0|=K*7;&6xtO#QbAY8VBF^F+R z?5)0hJ6$*0(~~8YHk13jB}mK(TEa*ewFD?Yw0N+Ygb_EbN^3_LwRo_Zgb_l-7l-7~w&b!mzg|jP~r5l7vx#VV@+7_U!VK!IqiyDN~NaIz`cFjZQ5{ z7*!h9X~JlYPAy0nRT|c5!f1_7El3zu8rEsTXpK%SNElTb)@j0MjZQ5{7*!h9X~JlY zPAy0nRT|c5!f1_7El3zu8rEsTXpK%SNElTb)@j0MjZQ5{7*!h9X~JlYPAy0nRT|c5 z!f1_7El3zu8rEsTXpK%SNElTb)@j0MjZQ5{7*!h9X~JlYPAy0nRT|c5!f1_7El3zu z8rEsTXpK%SNElTb)@j0MjZQ5{7*!h9X~JlYPAy0nRT|c5!f1_7El3zu8rEsTXpK%S z*d|8$5{^pVKHX-UvFQ>Ux95W_c^W-<5J^gFrUVGJnU<6`Q^BaUbCOA7gi%X?0z``k zn@Je4q_lQ~QHuwgNf@!Dw04A1iwB!Y7_p?Zc7#!j2b)P4v81$igi(tJn@Je4q_lQ~ zQHuwgNf@!Dw04A1iwB!Y7_p?Zc7#!j2b)P4v81$igi(tJn@Je4q_lQ~QHuwgNf@!D zw04A1iwB!Y7_p?Zc7#!j2b)P4v81$igi(tJn@Je4q_lQ~QHuwgNf@!Dw04A1iwB$8 zCPrEzjcpaZU7Kw-Z7Zbp2wdb6Mi&$*K%7t{jD%57fQBnQA7n0JM1sjL3Yh@n(#Ll|ojVGIZ(hElB! zVXQ@jF(8Z>O0_nGu@(`=fG}bx)!GooT0|HF!ib?%YeN`o5n&7nBZg9~4PmTBgfZwe z#_mohb=NaY(7Lhdbm+T5gsG)%jNJ|W?s|raBR4i}N28mg#?(TdVJOww5XM?W7z4tH zp;T)_7;6z>3_6RER!C!-zuu;^0m2l|f_e@OEiOIjfv{>KZb+%N_{(p6AYiP;(9}Q) z{iapbmnX4$MhFYSh=5dYLKy2AAuIr6cPCxC>lvbD9hp!+a{{t$jNJ|W?t11V&`_1M z9gV1ia$-cD5k@Tm3J@(GY$jpElG54{MlBv}CSk;q(%KP5EgozpVZ@Ts+7U)A9&9FI z#FEn55k@T@Y$jpElG54{MlBv}CSdIDbW(Rc!!~boJL+f68A1(hW9)9|ch@r~frhH2 z?Px?DloKQJj4)~mP=ILhU^59LmXy|xFlzB2Giil15>$;DMPm&hTsC3EajLN*j5UC8 z*@O|tsm6*h)&Rm~6Gj}T8mqQ3c6ZXHyPnmAki+b@qtW4^*HqPM&$=7>-Sw;{UL9t4 zI`kcKs;P=F)&Rm~6Gj}T8Y{wB0|=K*7;&6xtO#QbAY3+K#Br*zB8)YFaM^?r$En7O zFxCLVWfMjmry485SOW-`O&D>UYOLDE*xl)*?s`@eLJqUrjz))vUQ<=4J?n1hch|F; zcy*ZF>Ckt`sirEzSOW-`O&D>UYODxj4Io@LVZ?E&v1$_|t&py13}kkjZPxmC29XRL zm=Q(?5ZnJ!sgr|7RYC!R!c=EO80!e3@(CjfQ=L(#F?M&-rMsTh1+2ULPKUlbOm#K2 zjj_9--(An@V#r;7+tKLm$m?n%&*})F@(CjfQ=JiEtRsZVCyXdebw-4-ju0xJFrqNk z84<=hLa2Pgh{9B7L>TJ`q4EhM3R9gCVXPyB$|sB{Om#+`#@OBIr0#lF7qIT~J01G& zFxA!6HpcFTes?{qiy?RUZAYWKBd@E8JgXyw$|sB{Om#+tv5pWbpD>~@)fsgbBdw6G zYkFLMX9I+mW8(s#&WZx0ju0xJFrqNk84<=hLa2Pgh{9B7)M<>}opkB0XLSMVF2B>E z?+#O4O>JZBZs>Q{v$_~^m)~|Yx;yf^n#i*{La2Pgh{9B7L>TJ`q4EhM3R9gCVXPyB z$|sB{Om#+tv5pWbpD>~@)fo}SIzp&?!id6DXG9q52%+)`BMMWUQKvC>cRH!Np4A1c zyZlavzB^2HHMNbgyP@A*&+1~xU4Glq=~@)fsgfW2=)cBvuz| z_4)Vy;=Xz#R~DTPeOHj`>j8`u`t_LVEFkn-#aMSd?((UhIblf{38R((1&9_8Hj^-7 zNonl}qZSV~lQ3dQY3&H377sR)Fk(q*?Fge54>pr9Vo7Q32%{DcHj^-7Nonl}qZSV~ z6EJpnI;p#!VVk$P9rd&3455a$`&oBGzq_6}2{cqC)TvRJ>Wm0u9U)XcVMJl7Ga`(2 zgi!f}5rwJFs7;KtLb|RsaQSVv87*4IwMm^7wOJh@R6b!uVX8ACjCF)i`GgULsm_Qn z))7MG1IAV-T}TYoELtO4A+5!O&1`!Fq0q;+Otl@YkgjH9kkfYP8ys3gQ}V1Kz_d7F zB#c@D6d+nW*i6ERC8f0^j9NU{Ou~pIrL`lBT0GcH!iXiMwIhsLJlIUah$W@9BaB)+ z*i6ERC8f0kj5I5!C4|bPSveG@I-^c^YU*co&0n8S{j8o5!lKjt4B@{c6T;{OBw-|s zS^^XxT0Gdy&SIn$(%2Bt+jTZT)aBTLo`HkhOHXKIt9KvV-tJ;(> zRy zFdD$BHYJSJYz%S;qXDdHQ^Huy#vlhUwmRuTVg`*lq;|2qOYgy$NBgXN0gIj0i~eCY{Ad&ycQfe2hhB14Mm> zGzLU78^YL(Usjqh5=Jcn3J@(GY$jpElG56B8e?~7c)IJEHd>u#b~^N(lG0WN7`q#d z-Ste{rcN`dpEpr9Vo7Q32%{DcHj^-7Nonl}qZSV~lQ3dQY3&H3 z77sR)Fk(q*?Fge54>pr9Vo7Q32%{DcHWM&*ckZgYo?)A}xgGVh<_w_*>SsjEbN^3_LwRo_Z zgb_l-7pr9 zVo7Q32%{DcHnYts8$)PyjMV>hUN*D>FmH-8a z77sR)Fk(q*?Fge54>pr9Vo7Q32%{DcHj^-7Nonl}qZSV~lQ3dQY3&H377sR)Fk(q* z?Fge54>pr9Vo7Q32%{DcHj^-7Nonl}qZSV~lQ3dQY3&H377sR)Fk(q*?Fge54>pr9 zVo7Q32%{DcHj^-7Nonl}qZSV~lQ3dQY3&H377sR)Fk(q*?Fge54>pr9Vo7Q3+QdjJ zq_s_f&TO;I)J4na1GF|I&#cj@1qq`{!#YhEt@baRBF=x>rMHm~v%Zn1moJE5aVQc^|FG?7577bE_u>rii zC}GT5G)NJ~2JrHtgfVB)AVnA(z{`sg#+*fi6k%)tFE2_Ma~2I!gs}m zXVD-<7#qOLixS41MS~P!YydAWN*Hq%4N`=$0ld5@Va!=HND;;c@baRBF=x>r)h0$- zA>E*%l%j368JjM#Kylbl^3s#;^HXtIt%R|Rit)bb!f1S;#s$bTV`OCo2xA!)<9&qD z7+F~X!dOPdcpqUjMpjmUFqTm<-bWaXk(Cu7jAc}e_Yp>8WMu^iV;L3WeT2~%Sy=(X zSVqNoA7L~`R#t#8mQgX@M;MKfl@%b2WmJs!5k_NVWd#Uh85QGwgwYsTSpmXWM#Xp^ zVKhcoR)8>;Q8C^}7>$vY6(EddRE+l#Mq^}U1qfpq72|z`(HL1-0m4{D#dsfKG)7id zfH0O(G2TZQjggfVXcHr?kS=Qh^L=f$*|e>YHpgOGf-ssAE43$#rC3aN5=K*ErS^oe z6pQIj!e~mY)SfVwVlmxG7)^Ku zro>9^31cZ1)18FTlvt@fVJyXBx|1-P5-YVQjHOsicM?WZVx{(ku@sBxPQqwPtkj+` zmSQp8Nf=FumD&@=QY@xB38N{oQhUN!ip6v%VKgOHYEKwTv6${8jHbj&?FnNk7So-C z(Ue%JJz*@xV!D$sni4CuZxbV}kS=WklB#frS zO6>__DHhY6gwd2(sXbvV#bUaXFq#r8wI__FSWI^kMpI&?_Jpw%i|J0nXiBWqo-meT zG2KZRO^KD-6UI_3raK9vDX~&}!dQyMbSGgnC01%r7)!C3?j($+#7gZ6V<{HXorKYp zSgAc>EX88FlQ5bRE43$#rC1Di(h6xqU=`*RjTKy?QZo+8BtHPQv zR)8_vO&HC1Rag_o3NU8738NXW3Twhx0mf`MVKn1aVNDn-z?khOjApzltO;WU7_;4k z(TrDxHDRm(W441vU#;d}bFjjyu+f5kFcvV;v z#tJZIy9uKiuL^6zSOLatH(@m6RbfpSE5MlTCX8mhDy#`(1sJp4gwc#wg*9QU0AseB zFq-kIuqKQZV9a(CMl)U&)@@>>719-rV7R-@Hlt@q8#YdbIki~@7_;4k(TrDxHDRm( zW441vU#;d}bFjjyu+f5kFcvV;v#tJZIy9uKi zuL^6zSOLatH(@m6RbfpSE5MlTZV}^v-LlJlW=Cgl-KrR)XB&2knEQiQPqyu4_e7`wYnv{larTh454a+5~=ysI=xwHhF;&Jp*w zJc**QNoZtc+Z>2n4GZ0XV#b}}o z7Xh_a)X!=WVGIZ(hElB!VXQ@jF(8Z>O0_nGu@(`=fG}bx)!GooT0|HF!ib?%YtvPX zv_iVJ>2U^K4G_BX#I=8|6$MBwB7{MAS50)+v+gbv?XG97E@Yt4M~r+3lQvH=-EFg0 zLthn(5KY|7l-7l-7l-7 zl-7l-7Zxj95|{J9>t+298M< zMWYF=N?XEMiN+*@Fq+V+v?Yv{XbdvC`=sSoJ?n3I(gWZLum*8uY1(F|ZZ$yYvCfte zF;c9}0HFuzj=;BkOKoNeu2_sP7I|2{BaD{dip2hN*4#3+E^2`ZZ!bljk1SmkXc(9p-5lc#A z*Xp9>R>f!mtftvbvZ$Y#(5kd0jFo6iG6zG=_Typ=@gUf#>HK1JlBW_Wj-yb1}oR=H`V?9YcAa824QxJPXZ_)U?EN zj}>C3B`xeb+o`)dTyf9RmTqGpCNYa%HMPhC0OP!^Q{8sG=RG@!&~M>B_t|?1G1qRC z)F%UEq9oJxuFbb+p1H2LtUh_?*~0xh`}Vgo&w9s|9gEw2zxsJ5Ht>1zksb3cS7c)I z+&WQO+k#U>fV9xh=3bnM4ObcFuUGeX`>AN|9$cvc!eZg6jyK(iq6H&}QBB zEM-8Q8W{_vW_hRfeBxxR&wdrQdy2_I-@9jwt^Xo%h+N2W+TX8hFKh2SO=dFpPyM2HZD?};V~|5R6tp;9~%|4GXDLvEP!oyj@Sx} zS)sSBo{p2}T(g6;vVO{GnP*m|4GYPBwyR-58}l<}O^0VTM`~I|Vr+G`V15f%#Cso^ zwb^`ACKmR85CPIE#ul!KY4+P98cK@DYyEZuq~u6k?*h-dJCizXp7|XhpY`_XxCZHB z=%>9Y^{iWMHf^ErdVng{mk(Edn=4U0b4dNHh~Mg6r%#?Kkq(cI`&hNPQK8>FT=X;l zv)@cErfjv%jCfcY%bP*V@iGszWC8f1% z8)N4u%CxlIWVZR_lLy431pF_nVe8KnlP+#zKvPSf{pi!JiLq`!MI#%oTDX*Jd+m1` zK<$1g-U3EBHPP;MqozB$%F55w-MvU{H9$Ix(N)B0>Y)|V8aM`7@}9cYNtYHz{rt-T zzQ0S&Y0F8M7DoNx?iK^Y|#gaBqvoq@2V!3}Toj_8KPr zr#~mh==~Ft+s+r)`aukC`St87@$96z$)h6uPPm`?vmB$}hc`kb$!KifGm|*Bu$7^2 zQP#MK6oY;yqtREGoc`Y>q3>U8LE>35I{Fg(#{R;yrHR<1xtcGr5A7+$lr}SNd1QgT z?i>*dkp*qcPVN=O!aZ$jL6*7a4Mj0zF*~zSj9yPO?-*;>vux6(g=qYX{3b#RV$f#O z;@RXdWbn`9wn~0Ws~wD~EBqA0J@a{Ce9f0d=x3K!J}-**eY6w{y#%u_p=ZEQVD(EojMomu_a?0!?8G2lLW{*5e z5$lD1JN2utQN+@L-=AxWXWQnFd-iP4Q>VwXNq8v3(CaDY`R~d+<1OX+<}=vuN=3|H zXrwjE8~F6Cucbms?ZHpQ=hUfKl)m`+J9vcn#3HTVt7q)wy+!EnketuPe4adaK2HP) zgkmx;5&B`sYu$c{@C*jx8T@><%9~j5-~S~%^QMtkoQHn;L7mSTrT))0PK#%`x870` z;{XCA`R7fFvELn$Vf6pGAY=J6q+9Upsf#kt#sfA;{&~ds+7qWE8oTS6$EK21%YK%2 zGQSt8G8*Rv@yaCnLwO*s6aCMBKa0jzJ)56;w&Qx&{wVeRWp>dspBJfvBVMA4o#!_| zUiCXw3pahS zD&B3>Gv^X{h0tc%>~{-i>P@#u&(=fS5BHwT55#%uE$Y`E66c&t8A{H>eo%&hg&NCT7JbQNc9%|@&7CZ3IMT}nCY^rBr-k`2i z@AzoDo~6g%Qh;P)Gx?AY|3cUB^7>wPjEa$q<$2Ci`EWHGl$c+!gVv~?c@~4vPidtM z=GQZcao%-XH}5_9_AA$WY_yZ#D?FQsPn;NsPb?zmaUm<*`{hE6$9-FEHo=ZzD+0gE zv1g0RZ^lA!7Z&$=+`c_O!z>1nzdPfJO-V}Yp1^Bv!YYO$&-IhJqeP&w$nCcVz4~=0C-|S&*vE}I$$L9BVTSo zy;t2TJPX)?{+`8nlR5wC=3^m^SmaYceL zxmij=KlT_P?|P3AOV;o#@w!6#@N|WA+n!}3NIMuwtUhe`>owZcIWytm&Bz zvTqSzxChUmpFyXN8q`)(^mktpp0Q{ZMB@%|O@Sua2j$Py zOpp2X;u8y4L>wiT1x|e_R5p0jvxR3cDKXCaUZ*BLAlfXw;DKeZVc}?8z6sXsDm+W8 z^%;%qrq>9uL?(hMN0-hN>Kc4ataO3he6roEXUBd)c$OT*Dz9QUT%C)-Y1;3Z`gwQf zVg^0P^5@xS-knXlfJEZi27g-Yx5E*! z*rV756S-J|(Wltr&*oyo;CjCS^0MzuQ#208w)*w#A+N|igBy6bvG5omJN{S|gXP~o z#h&q#JV4SZK#!hwCR{|Lk*fvGMJ5 zqVb)!r7rvU`&{vGEna!lpFEs}K4j85KlA9^v$0^q%$XPa(_)WOXL!crt$xtE3oT9=!-Yt@h>GfbD!jF2+9_@j7k0`$|R3mrtTz zb?!>+^Y%JzVsHWC_c=VDNLME%Y#@5Al_Zp3VJ+2syW3Ky_THlJ1 z0NFoQa~-E|Q@+sQy;DOpCbJUU2N2uM>lEPI#lpN)Y~KEk$rY+wJEP#4-({ln{=FED zUPFIm1X<#>&3+^vUCP^xuL5LI0khLL3!Wt~CUZ%Bubw^mW<_iwhLxgDeNijxvqOI^ zq7ghBix&l-2~`8P>E|4wh)u*Wzv;IALT%4GTfqnqkoJg?vG<*?cm`tNoWJc9@lA0) zLCiyc+oV6S1I23FbT)eNg0K72V(*s2RpMDVu_^MW_5wLkmUL?HZ&mC~?Sx|r(HI7k z9*5$e{i7h}x1U`rz9~MQVq6f1-YBv^$@#`$8(bFn_3V|)GK`sLJ{ME6H-A^Q*(40a zi@l2d`9Xu_Z+=0=7rseggibvc@8z{q|6sWg1La;EUFOrXe-qz}fw5x=jKRCa{?vji z-ky6FGIp3pEjD=f-*YjTkcJDxKPoL|$vb zvwXLoR6z_be)rth)EY1HatgT|JdKOC&s?@!-81o6XW0;e^$jNfuzTQ`0d}EwthD0 zHyS@De*cW0!+@c$Q(02)-9Ig0^e!epi}CK+fiu-;^o+67VtD{|EgH$QoPcer?GYqD z&UT}5+b|!y@?&t8`rJ?*h|gO&K462;S?wbgotQluC)pirfKlJ$q~q0xD4xOUwRq%U zoW6bUzo=qq)sZj7zxE8}OB)QTopL--o_W^=z=X*Yg-4 ze^j4*5?ncqxjV@po^ZVVRhdbJsw4R4592-JH^sRV@U$BK;%z(qETzq|$4JM1)CTOv zwW^rM&qnyuWh3>wOi7#haVx2{@Ms*5I!V=qxvTDq`J0bRnLS-yLf>kDwCb6^dG8eC zT_+bhwcmIwgg*ae32&eJfFBEAGF_fA7#qXT-?N%#{z~!8b2JXVcF>4e=r2YFZ~V`K z*krFa=?~+t4=afIbBotp7_L0G*#k!`^x9}&ncv|6$?t4^N8_76RhX6Y+GK1*Eb^*0 zd*60F%biKu44ez|U2ap~pSI9vtH6^PZoN@zd&s8?o`p)5>tvt3GJRHiT5-~5pa=iF zY}botNb}m;?bP0UNih_01E;AZ8z?aiGfNGZ15+{ITG=jIqe2RfO*EqH%X%%2jkxo`u| zVy|MsjK`}OS9ld;mtCTYc|M;NpC;-g?jUMB^YE8~w$|%MKNu!OW)b(EsRLq}WD9%uk!WQ$Eo=@yu^O z`^~|kpS6JT%vW|;EDQDYTT}kx9%}C0AfqvklF;`!q4Zx%GBNlKIVJS{IQZA2GckBb zLMk@yM~K(@-Y@1Dy?dsNApS84XgGI2I(qniq7VTRMkl3eZ zpG<$6ol7iF{`nO9!!w0vT*c$)!K=SOdIs|n@Xc+$&)fF-{KwYDV>Z6+IB!Z&@iC7P z82PVu_541%^tDhL=`^{iE~j6e%*HWG~y zioLDT#UEA%V$bWY*bl_49CWhK_l?Zc_E4hHw^;bSf|zY<;L2^eG#3Mm5w4V_)uu=1 zV!R5k6J<}7lP<~CPGot^xMF|*r5gGy+!I&K&gvl-s$y~E^&<5@f02uYcE^h^b=$LY zu_#?ak1uR$`HICtY&KjGd!BLpxm*gBy0yymXie--|EBOP3H{J(KRYcFVzc=`>~~Yo zXCbtiSHV+m6rS;cvFG5Bo6kD)wyU7dlpXRf5X*dQk2eV^8rbw^;qUEbB#H z)q09&u~#Li{N>7UNhiooo2CFc z-*1CK?RU!p~A(T~^@Prr zUh4O$ea|HOPAea+?0?@c#Rg#@A7<`H^yK{U53zC$GI~sI z-rw;M=@|oe{CFe|RatEdp2cFfpI2p~43wmpOgK~>uxC6>Vho{T{y*8m?A77RfPLX( zQp{n!6;7I-8L4U8?Xt~Uowi*RE1fzTIVdM@FM5^q%t?LP zN|b2icA?g|X=d?pMonw0DL>*_jdjE9X%h>THiNYL?eTIRBssrC?iG|8l{GxdUQfwq zfLS3%#q*gMq;X$J?dts?K# z!7{C(i_C9Gj4o=csU!DHiTj!|*4gm=Gx_O6WL*og;I234V#p%)X7~O=hz0hQU`t*W zNwKXlwvese9e)>{I=`W|t*f?Nektes76uOGWiJz+1z~>6#uM|5EJd4sc@PzTWV`YGB4W))m z7_>ja^wxa&nlfA9No=M3c0b%N`NlY7gTx45xEIfm_T0I zgcuZ(8Zu!}6T*q=bCA%Y$>HPI1aospn z&(zLkk_y9*iBW&9AAv%xPdQD7eqq0tH!?ux%CRc+BE&1b;%(Bi*qex`So!E!?DF?2 zF(&`)qZUt#b&_6kNt|VU8EQv8$+*Z z|MmS`EXtROj(ZV3NBoXO5{>J;Xvj*x^k335xCV*kelLkL#1BypgY}A-AB=wx7pX0r zJlV>Nvq_gBtb_85vA^*VQfz&kueCg)ZdEd zqz;1{yst?;x|ex2u>wvj%jH3MN&NP$nV6T_M=F(fo-mCHbHwpTw%fNS9G`jC8$aCp zQ#5{jh`=}oE2LTI)|HXk{&8R?HZQn34lapDvfaM@z}GUd{y3jTg?}EmF9^>D6S4PB z{b@06+xHxa{IM#}_>c&Y9-PO#-oOvoS#qkqg*JQTvxR4D!eeNpRevX6N9n!SRA@loVq-rOo{<<3u-$TuEe8mMzU?vN%6;rha-vLGQHCpPZ1wEl=VIPN|6^OH zMT{+ueYe?-|0y~(d{XCIY>!7sG5^C=J~r;){j(VMM6rBrIKh|phQ{HHFVJUidZ&!W z!@LK`x8EnkCKh@RkkbzmV#(O(6C-1X{6vV2T>=;*d=pq${x1JCHw=CEvvcy#sr_H@ zJV$owF_@aT({Gy{ET`Ich`mSS$Heo9+y2BN@;ibscCc8JI^@6X<~j6F6koy_F7@AL z`#*JBPB9C(XMRKfw+CmQ!RP}@tKh}k7R-@PKJliJS1fPf`7RjveQv=EUm!6qjD0Hc zx-U`Jr23wk_}9Hf=+6L*etjF9ae}}I(@DN3%D$K1dG;YdR)M0oZT3FmQzpjd#@=MI zim#K?w&S61E%pg> z;CU40z&>$~7(qPZ6ICk#B6j(EogUBp`IFZyG4d;7-`jy-&H`jUzqAVd%AFv-;yge2 ziC-nC{RuD6J9X?^?M31nKd{=?JI1}mFX0pe#Lq~1jrd3l#M;Dor_yA8Jp0zK^8iuA z{3K;RE4EqWMeT8m#iUCMBgowgq}Y1!#*aq=)9cnqF&M7oc;!d*+c)K6;sCt80>-p% zzFyz=_MJIWERIq!zP@qbMfbvmxmbG3G~_yd#QuB!6tP8KyyBJq?ej{2Bwa1>%#Yp` zJCc|KvVbwIg%8BO+icm7bFo#aSnR-u@+vN0l!?u2!LwP9%f#TiF~zuB`BAypyHfmc zSKDpYYJjvSHt#z4F4IZDaiM!{fH`2|{da zEKIH&XZO6xJyt9^Ob6l^`k6N^cAmK4VaaM+e?q+GzucN(940HIVUI`8E`PXaGttNV z+y{ae1NIv673Y2u7a{EQwGCK!itwz>HuL3=TCbeDQg`}FPmfsf2HuZva<%|EHEfX| zm8{lHOmynx%$e@>^&_*pUzmvv#=JU}RDRMwi+<)`EB`De^(;yxCp-z?Ag=X2)nBMq z?Pp<{5flnmcxZnEi&!0^edE6VGagm76ek)%4i)<@4`Y@TI+;#Xfq5 z2#~;kH0ECp0Jl=l{9W+8Q9kr%tc5mvmcY0JTP2?%t#4=R+#fwjh_%~hVb*5;rfu&Q zzsA=_KU=?hhH?H<|DNrB`E<0|yal{dht`pXDfku|<)6JB|Il^BP?WG>?=8b2Yv%T$<7@+3A_g#IwN1zd|$?>vbe^@A+*hrzliIm>W4 zPh#JHpA=i4dgW25o?_aoN7>|`mn(YF{|c6_;5m@7L=^?xhZelLjgTGfl6d~f5_ zH{=Y@f;d<6(`M{k@j3M{*pwf6@bx_HFty)XvGsCnEVS9JE;VFbH$6^9 zqvDOHHoJ|)B=`miz?haEx!?&K)LB{diEk+vt1QqYBR|Ec5vZn{)IL(SN-P?&bMiKN zevUDeHG1-F%YD-%CLQy2kt*8^R!A#iejai=|1kpN#N;-qmMoQ)@0=yhe1{NIgTnVk z>I8d=;=vxV^2S;6+*O%p&T7RbP``7E%&N@PVQ`;_}Z?* zGci+;)EPIgc}fif_G|fbjm4?BwGp=!^*V7#7FW~fN@@}I-2Br z8>jMt*!%ripS}7adFY4o(1UGxTJCI~IPp3m=G`;KcD+xCsqN(H_fh}l3%OX1&Xd?L ze`*hC!4d{0+bH;FHA!*HdFNnMu- zbwWC?SB=bkZ{t)xg1~xxS(~S6+m{|SO>HI}^FGxM--h%qcH6rI#$q&vxw5;|#v3v* zs8SVB)2`HlCn~ewJ_HH}Du2C5E*9e1el81wtG}9KEF6W0H~lSgRlDj<;6VzieCNYN zH16PkYcG!`eMLquU? zlW)FBh+&F0T>pE$_!ttS)zn5#NDusv`r$o~%`hgW4o~YllUe=?io}lTqsqv-?>;^ z5!+XRFDXMGU&P*0iWQzF8pH$pDyvKGB_^cj1(UgzpHZLv;QwSl+n|c&X@{v}#M8#bC6cqZ+`U@jEUHCtJ-P`-6gK|AwXhjE89=* zagsP%bm|c?FKzaVicgse1FJy%^za2HW^}lqTSBFMV2H3||;)*avp}g6z~= z6B+Rb>UO^U@)J^Qr25>mR1~tCUb=3)PKtd!sT8iQVB0WpSn`_uarV%|YsB)kVyBLC zDTk>?iD%mu#aQG}Lsqrw2!V0$O>!rEJ^eE&PGy&axFtCV-9c z)o$whxGuOwJZqv?oRwP|yK$ya%ZtTRd*_TT4AY#%rv|TE}`Z-^j+Y-9CDA zR`r;;;8BmjS6YUCZ(TNKq@H;h^{-wmLcbUhUfS%YF(H<$kdA?1Zz*HTLmy+~E>BIw zf_OJEg*0RfSg^^kxmgIRE8_zzsTx_>E(RBOgq;$9%!5EC?0pd_^;cLo0 zn?J{)h^Xp<^veMOD+EZe*hhS@Kc;I7M#b2YNF0vC*Y~EMSd5B|uW+a#t9rxfX`78; zyx2>C9Dj3}7z@4pI#c+xQnAR3XFI0P+#GGQIUkgu9VXsh)gd2F#X=Yx zqjWFF7{6{(nz&2MI5ZWD)Wwv8VEuX@0rD-eqD+qZ+>u}fi`+RRYnu1(qRqyXRneXv zx%}(Baxv))eAC}cG+roX3yK)wx>!2zF7e6q>Iy~>W!;r8&rX{qFv<~x&7KX*kBavh zZoJ$3%3Lh3Q5lFQ^1Y2ypFcYli}?$j}c4!MK;$#v$uDn@Crc%L%I%2q)*iT_>>K(`rTtcw~N_3H?s@*mh3oy|?3 zfti|c^(oN%|Mq|$8&PqMFnVBzzO&`@H~xyE5fN>5CJ*pv^gK2?8|VwoC?D`y*lYPT znqnPO->v&SqMv!jIQ6Jp?0JBPz6*rB4#Mb!GTiP%U#8%2+PZ{-=f_8P;|ljn4LRvb@ij$W5d zv)?*8=)5*ZkQsXpOZpl5Pz?>+^o%B53>&Aye7f4q*?RH{zZg4BJU+eB!ePdAVRYz1 zMOBJtu1@|HO0av|?KE6f(?RDbZH6vmZK#M*r?#f}z&M}L2tolem4GsWOwDw?hs2x^ zC5(hoOMn7IiwB!Y7_p?Zc7#!j2b)P4v81$iEn*z7Tg20`wTI*+vsE!#cjctb2qR&v zA<*J*MbTK(7T9cRGb|~s9bwes!DbRhEGexWVbtQmW)em$DXm>sG4|Od?cFlb1&=ny z@R?nWMhXyo3}`Le43O?V;Iq4*Q@7e?!4{t@q(}Qfo1x!b&sq)rR->_1&$=5R-EFg0 z17vc6_?^Lg9CNjRKCe-vE@^LtbPzrKqUl}V=;vt+9OcVrOs{96Io-dudGc(vpOKiG zV4(nU!m;}pBPX0{DmmdhT_1=EV@(L?v%BBV^!_`_C5%o$b{ga87m=M1%PR>YnSP4= z;V!w$UxK$;?5}!W^Q5f)pFY|3^On%qO^F-Gs5o!}1+rv;hhC-w{SjaK&PTvB<;n9bvQtS1d*ti##mf5k^aJ#bSi9 z$iwm-VYCESEJhfMJS^W4MoVzTVx7g<-Bp0Jtfm;kmhUJ)EWwQw>+A^9YCmf=8e0`> z6(fm_^iI3C-TfW-?s`U{Zx`#MrRaP%O2q0tVYI?FT8J=?60v$u7_G3479xzJM6BKu zMk{Qig$Uy)5v%uv(F)sWA;LIH#Ogg^w8A!8h%k;4v3lQGjPaEneFRm&uI{L3-F;9~ ztB-YVRjj*hMxI%nP^K2@>?wvOq^CBv%^nI68){R^5XLD;Y<3Vv8){R^5XLD;Y<3Vv z8){R^5XLD;Y<9GWk)9!K(?BI1 zNtf;}rtEHjbhpjA8~W5{Hs|H3WjcGNZZ-5tY-(iL?4fA1p*E!qVVr`*W(Q%kp*E!q zVVr`*W(Q%kp*E!qVVr`*W(Q%kp~hJLcpr9Vo7Q32%{DcHj^-7Nonk8g|r5aNft$;39U+7!dQvMB%?Kq{HN@D^e6$7 zwyCmht<45-1SidE@Ao{ryG*oI&uD#PRnIZo-&#L|!)i4^T3vED*m7ojBS@>BwJN4Q zVF1%`c+Fxs1%`c+Fxs1%`c+Fxs5P~2`gw2;Ww3-h-}{=QyJ7HgP@ zu6k2@VyM-&cFUnlFdXy9`L0kmXT2Vi%MT9XRj2KF_HiWSj5ypTpVkp(x5XM?W z7z4tHp;T)_7;6z>3D4L{N=x6!ikyy^6L5eUofR`5~j5!PIRI7`YTNR_vsjY*e zSdjWzk%#3w!e|MuSd1_hd04(9jF#Yv#Ry}OhvhrMXbG-Zj4&2?SiU2Smf(uTx{8rj zNEh4L`dwE8gzh}8L!wxa0;I^p@*QEc1XnE9CdO9R5x4qTOsk#^wwy_ypB1Cn>K%o? z6}FK=-CiNB{HF7W-%j2Jp{(ZVo4t4HT#SDLA4_R3iM;wZ&o=X{5%VqoW+v9icheE1 zyPma*v56R+Je$zV%bJFMUeY{8ZD!7_tVEk_*6QUqiIp|C`92B|b7mza2xAEp^Ie3| zoLNbU`whmvI5?RQJFu@4(lF+!Fa3SWwZ3)LvgWG9%V$gx8wgveDib0H``U|zWs-Q+ zxl_bMzWdkvO@KIe?f&gq)WF}9=1_n%z$c0t2MD#9K&QSMV^j;9rb$c?Yw%lW19sT& zOh=Gd=$gI`*sb@spOG_lq0*kBu@a3*hB3w_Q>lmSWE%P=u8i0kdp1(u=q-sE;i@t= z#~4>tRlk4HMHG#K5@8f1lvnd;R0^9WNz9a3sXbvV#bUaXFq#r8wZC6uoKbqn$enxj z%}$;T#QN;g9a|G)tVPdAERVJZ0YVrFV@{wnW!9<3S)*vYc6S=Ccq_Dwv9#flJ6l~x z-0G@{Rz16auSuQJWa;JJ8_ha3GVsdHOs^Z83|GNbI~#iT|H~BM{W}`VTOPUBG(eEm zmYUHsq)V|F?`*TpT0O;(m~kwW7N7tr#bUaXFq#r8wI__FSWI^kMpI&?_Jpw%i|J0n zXiBWqo-meTG2PiUjFALD&ybcVnk2dwAUO;2EN9UmMHm~v%Zn1moJE5aVQc_T6m9jf z&aH~kle|P5H+-dj)(~J?oG=nbEddG;EgozpVZ@Ts+7U)A9&9FI#FEn55k@T@Y$jpE zlG51GGo&?eOtL5%O=wlx62?k2CK-g$gjS_3VXQ=BkkRTo;#OCbwdxr?QqdshG^TBK z>Q)1!)zI(M3hB5IE_>3GPYOKHZwMnA72dGT;i}aU#IM-MH%$f$UugJM6?_XZHX_EZ zo>?L$A3bPNbBXP!*#A686{~x|R9(IlEPpQIMGI9iY3wC2ofkZHnCkK+km<+hx1UKz zvjh!SqeQIU-;XhtM>N{Y>mSqJ2tuKsH4C*_MSR|m`&q>iV|RDbvzU8-`7T~ZkVJ#) zB%9}(!8nsizh8biJy%ZfX!6?0&`*GnXHDWlmL-f5MUw zVx$$)O&Urm+hUv1jfKL!Ns`*E2|ZbsFiI3n5}n1^-DRS!dN!R4hML4RqAZ0z0#dEX zv<66Adw6(*smssCnAZ=*)k7O+pHx4A59%BnU9hOuRYOJ{g>r>AdBMVN z}IDQ_piu~W`afek8bBj__30w(1&@pVG4Xow-{bj@6x?H zJxRehWqE9Bga3P6Vmc1L3K5oh)+-4ReC39g(>D-1ipI*`cw?ZnSrA8hFqPF5id7!- z_!A3ag+kVE;);^@+*c5bD$KIo2A)j~e8$#(wIHU~LgrQ;(ny;jtJ9lRwpp;%xo5pN zhJz_{@1oP3i%o!Mt4hTlw#>O0n~343fXV{omY2B~8|N6ywguO@7pn@8{vg(pVRpxJ=V<%Q3A$IZ5=i9R6ulncqhdUR`x>!l0xpWG7RD&l&0+Fj98c?*dm??84G8@5`JzRu7^K7;y3m;L4ZV%nz}vzv$D+$ zR{n=mE8=^Gaq_n^8Xtax6q8?ZOS&d6mU{;2q@v8TXa!GzMK}}uo1}Ez&+Xw%*RBVbJYR7JgRds;eIq6U= zrPo$J3%P558 zQfa4wGxdf%OcjF_`^i0|eE@v=X(y2=Vz#^a3f#4l5#U8{_aQbOXR5`Q zmt5;oOte!3BS?v7m$|&)$*$jEAdZ8w=zs3&f@dN3yL=o?h{Va?sy~@CmDlb zYBXY1GUecf>MQq76%%>Juh~g+b-Yt~r=I`Yf>>B15Nq@2ryPU$z#bcx1jzO8 zFNkUDs?C&_0~N#7rQ;68)OJ$S;wZoKOow8bXTf&3J}47=;=>$@r2@gy7*xx|?)#)e zG0|qrK&dQ1p7c_OVwpGnJ)x0=uxKy-`suUWiv|4Bs!Z%#e{(O!wu4fc*jNA4xmfU& z7*vVr)0pLULM5Nw|xm0)D-F>iJ+#@J?7it+kG3Syy(cuKks<9HU0 zn_wg^!+7TY1+gjh7k1Q%@$35mm+8R;PoZS`<|nT$h(#qP`L0^A#1v%Ge|fb?-|Y3JV(%$lq!t{R@}}0a6bKBUXUzWga8FKS|7zZrq48)X! z*Cyc_wPf0sv2VV}Kx_swK#nNCZVVp&76UPc5~~c5!IpO!iD~J{%s!u&Ea}&eS?oa! zK2ny#Y9jVAA*~9iX+O(E#gO0QiBRg@{R=M`W&H)QNt2VOS_LZI<2^3lw(jV|v+VQ8 z(XM^Q(|w4g&P2ISY3kZpUc?fea8&FXvyZe!i!vA!IND7g$_YXaYZS35cKpMhV=U1%zk{N3pk=VG&$#`0>Q z*w0?+zRmiRxigYyvTOJ6BRq@q(umX`7|4hphH8OVy$2zt7N}1T*fudX4vLi)6- zPM-6gnH^Knv%Oy9-m_pMkBe*txJu&lAFUVTSMCN|pN0KJshGf-m456!^+!QeK z!M?<^%iVt)G7E|lu`~a}hi6HfO$BoPUe3k9Gu~DuEq%f#+>50bJSAdB&uJzm<4q=# zWhXp9z&kistJ@EMWhEA>b&RAzwxXZy-7rApc$9mVUCQxj1P9e^@(kymZOYm#UZo20 z^h?LA#73)8-)BCS^s`+*?pzGWRYNV+W)3I4kJ@6N?~aoU@c z;Ec*KUpvk-I&C$w{a z?p$nq1z#|fZIMXu*S8$xTnsvO+N&ezY=!TZy?VBDG44Zgm`e7*pLky%Vp)WQAfN`z z*fBoDN>_d}cBO}}JwSLQBS-|ErR!0^L%#j)bIv{Ev)>ydUU|s>DBDAx?_7+nOJ;Z! z5s{p;#JQN#%Y;hyy5Kp^#qtU1a765@_qi8am&_KVO;#AL3SYP%IS|XYJF?QnAW++! zr@8lRg)+NYIN%H1W1O|%D?3F65%K1Z+njs0(^EF7W0X*W*E1gBTx@oK**jM#5_$5+ zcRLpwz%|GuC>)lnWU0d%&Vx*;FuDKBPo9PR8{A(O^n>klBM{;Li`&hAa*y$tP09V) z)N98(4s$NHBMZ{Yf}&gSZnr-=7kh9&sA#j_|BG|6!P0p46sM9MySvBO555fxV9T~M zoIVgOQ5XbCfF!p}`JFt^di^tpB2TP{zm6wGiPp}55rZ7XRF=c#mrs4 zjz?pO*hil2+_PB=_!9auvB$r_x!53zD?EG8%bkloc;=?fa6&7=_$v3eO#Si9vvBkS z)=NE1ZcfAx6#-H_Wk1RNJjkFI_ZRh3j77136u+PdN7Q&50LDdwGO^7&I1dnhV*&9I z#0y5->``78pYTyCiN+$vpFhaGXY-S2To;34QS9v>a4(jA0$<|UMNe=pHW*9p&)|`X zaq?+G9&y2y&c%ASy{>p>k!tUAKW!_YRuf5;Eb#@GPpe7m?6GAND^Fk1wHz z;VK*%8-uz3@aGwb!Q8a6eevtg#d^2q^-ttUNUd}~5QkZt_2PmOyg6%wbI;N#xltkh z-baAsagmH7q13&{{o)f@_mqU6wcm1(ia{`xqDL-u-)5sHXeqYc{dX*cCsU*G+Hd~< z?U|%DCE+JPrpTl_Jcz*sNX0eC&MTd_S&#KMm%H|Zk2x0uA$}KAvi02G#mr~3he=O{ z$>))B(Hjxy}P*$Yzv}AcK`2u86~m&te9@ zEq(`H;%$%^My20xhS2xtO?)o7!gI`<^$kss8=jADoL7?ve_MJN~b8F@dq5le}rcv)t1Q-QVW+NA9U} zPoIx$vsge0MM561Ol0AgRnFf<+?f9f;Xgd6>BsKd3}hC`Q)i-*{dwE%hGLN@E$NJU zCf{ccg-{|b_2##s#Nc8Ay>YP>rPep?juI;^Td`BRJSD${(9bp9ck02Mu()z37dz6! zv~3z8Q7$4Z> z`1ja@-|gD7Ia~=wtdi|D&cEk5&gVa%(ZW%+9-9}r_KXjN6#?>o_tzj}qb|w!KX|%x z&!WY$_L0OK_aD}!3Zv(1K6|#};m$o9aYw!#uv>Ojj{j}R*}xx@V$o-&zqpYzZU`VrI&4OY@-_qxBjYUY`)8Omx7VJH7TW&74cT}NY_ z#$j1B?(t@XSUlwzt9S7A3xFal6T4zZgjjXeQ*(liVHCgxPw_D%sojioU5mxTh*w?a z*{$DoF4p4M2w&~Lp~|!6t{<}!#Cxo$5}W@N=NP$Ed7GW)`o@BXKHtg$#DiEWQznM$ z)akL}{=y0`xUnerY`N=iL$-QZ0G>rvo_Xlh>356D+Uzvv*C27P(zD?;&ifhnsr=ct zPx^#ovE&mo&@03EcK2VsJRnh;D%NMudyR9?pqs(TY^oSzx42)!GZVg>TaNJ=cR2U# znOm#G9^?M2DsbUg<=F?Fdo~N6d^}#-W^3Jh#sj3h&F*yh%K^}vVFNMv4t)AJ-E@!m zd-KiCG4^M0y|U1M%VPIpiF3n}JBxcScP$nUk{Q6vvoJ%L++lB8=vs^~{Hq8M_hVx? zJ9(&i*(2{?eXVoP3ZXABCNwwwz`5AW0e@oYyyBf_^6pQsb1s%mO=OXwyaX>@=3H#& zZ2DV~$&!<}Pno6`tlpEZkt;smFtHAHcE3V8y=5vpn5%AcjxlXBh{-A2OTOh?EZPSy zuGnzK6s`V4+Id832~RxASsFVMwCx7U05=y+5md+&Ox zonPv_E{4jJXdLH#4*q4^p)1^C%jK#*Ai>6xn7n;c)tf!H4Vb61umUsL3s<=a6n ze@hFh9l}ouMQ}P}&jGRi_;5CK=|yp-xA{)@7{|C+hOy9QN16O+Ms|R@7v5%UD`R^N z_u8~a2$EZr09pT1_nrld;JRSAcMQ*(9R`!ip&jP<3mu7PF?8v9v*UU3xd3yA&HKUo zWSe!1W6vN!_-P~LYcP0~qlV|SS?T)XmhHTa_Og?2whpSu(4&d6iI>s0-O2d8L zx)1KgqWR!iay7@DWuM!}u^0r%Mt&tQT)J+^1^{zu?%Wc`C(mK(8GJwB%E=Si_`Hb= zlmI#1{Vfv@_c#fV_|a)PP9QS2<{@q|LbY6g|Gju#l8)d_wmt2!?!}U-L2^o`zVLby z6X0uKfgWreBTTrD#mT$$&$-SQ=E(p_E_jkoE%Z+Kl5LxXq6(SFE=%ExY7#u#VQPTv zZThX_SZGwf0zm%rRvAXs>{xK_=*civi@2T@`zvJ9`1`)Xj3q#&o zJQ@cJuFkdCKOX5;3~tzm58ue5!Ti^K`?<^6t`jkcWs$>{UFTX1eEJ}KpgRmMm`(7_*s$Tk9<^a4a^?f)_>MD)=g27%YQp{$(+f+ng&Li!pZb;e+VwZ1AB) zbH2vd7OoV*tPLh&Vzo|A1sTxOuGH_$&Nh(wQ&|h<>Sc^oc_(k zw!6o;a$*}O!7as-akf%OCUTGXhGWlotzpa`#RLCX(pW1p$Jk2uYrk19d(d*2_pns% z=q1iQi=f$(ErK{qQ`w$--9PjP>W_Ma_$1e#z;iLKmvwEn1Gpzb{}jjb zjchDlGS-J%iY4d8{KjHzW5{|pz|h6FFMq&soAKdleePLdxH|Eb?!};g35+Wfj|9dg zPw*h7wi#CwV%Nm(#R6Wt82h&?Vjm4Xh-IFwgaAo8weak}UEk*NlNn!DlX%8e70`nFR`(0dhsh&?K@3Ly;Ss9XJ+9aA6x(cGaub@u zWbA2oxW`x+8-Zfha*TQDXJQ2D!O*oS%*9^p`Y9TKabi0Uko2>d3AI!I&h@gI8A%+1 zqsTCy@(>^P ze~!iY$z^@gX6w%dm0+WkV(h#f+>4F#MM>O0em6afMN;lde|Im&!g=d1+bvi(Zv)7L zir881S8k?lHb2-loD;yW4NAWl+sXBHBX6@w{#pM7tSw+{DFme4CinG#k?jFr<~uJw z7sf`$;!uh`&%=iZ{C;A?lCjCnfHCY#DaO_hoqGm-D-#$`ZU%F;ANAae1)K8v)iitB zL!FBaddmi5Y%yGbaLr}8F#CY}P7QNA{2x;~SSEPzxO2}|1jq4t7nqj-jfvy9P@>J) zJ?tJ_e6$m!0f9K=>>i=p~Z*j2zd!^)(*Epx)m4ts`#1+l#LC zBbF!yBYIcQbSaijvB2Lz+$O;(JCu^IeyU3`SuKn6WGItcAMH{s;RbWWxo0dLAyd8Q zf5yESNG8+7jGfDZc z`{^Q=7*nyuF`PW-X9{p*C`J>uZhxm@>meS7aK#u*&P#{=;A+J)x6cPjJqtNHerW|4 zs1e(oraAS63!Hiej&Gjr)0_3w!7gLIUHkh4?!EmK^>U00% z)-!Nt2&)R9&G@}i4F43*p5XM8!NjxOmc~Q)7lIfch?P$L9;X*PDaJ`QJV<&5{Y*Yv zbcxd|;@}d9{b4YRhkkO)*;@y1HzxN^;O1Me^3Z16l1>e0(sgWb%Wl~v0*F1=ZGfzY z>)`oI-!q&@hAVblZ{6hMj}ei{c6PgHnX{V@(E%7?)Cb>Y#=~_RVP~=(?fAwbPC_3# z^^i+_8{W>_8~&u*L(g^DW=Wkx7<{={vIX(tBt(-pUwoH)F&>aY46d$nv2Q#6CIWcC zm82M46XaswU*g^~{;3Ff2FuD~&{o8*^Dxz3Y%{p!1<7RF(ftEtAT)+c&xa?rvtR@K zfj*Zg!JnHv1PE`ltuh(`sSw-!Qul3^oK_Ms7*BY-2(cqwe{{@i2aLCKjIb4=@sCcg zh?Dwxo2Aj1yj7y{mG5(pk++%X)CJER_p@2h%&WZ9IyR`YI&P2h&N{fYBb*I^adUTA~qw~zLG`bx4;|t z?aM6--?UZeUOMI!<4!E*;SOI6OKxKJVV{Y^v28-^YUeA;*dPuc5v}c1^v7xDY zdtQ@Gg7o6vp4$?^6(~E5^?+EFKeQ>LGu=Vj3o(ckLJ4iX|>2kL>_|g0YCd55=?n*Es%o zBngF>pJkGcHjLJBxrqOPrBDaD^=!ZvrOyOeoP3VE7^WQaj&|kK+={UnMh`BKZG%ND zl%BnOp<6MI5xz09GhZkN!9N&Z9_8OwdDvInim`YFJe~$(GFr?VEn50IwjdVc)gK*y zmnnpbv$&5yEQTAI{96B*SGe^o>1XgAE$$r1!rvq+`5VR_>G(qgs2x7|NiM$^_TUbK z9R?FHi4y#I!Rc;2Tf$c{F!4mG^{vGF@_1XVp?@izQ3L`CKIGH40;nX&4r1y@|Dgp7twGYA?GG&90;7!?710?N~XL2*G5QSk9p+;9PLS6t`+ zJyqR(d&`}h?$h`GBcHCx^sTDyKHomyI<;3<&(nw!NynG+M(p}j_2uWYgF!LBf98;< zZXoTvZGD&@CSq=}hH3pg+>CJxlp`Ox8#pvO^0n5Hbp-BGOE5ts6+^2iU=Eq?!k2 z5sj{|n0V+ccCeZoOS2$bpYvLFu$6{gJDWBw5Ml}|q}v@SJ>5=aZi9?rP`o9hV9Thu{7uGZ-nfv!jn*Uj>cA+}Z7X)Carv zsk~qgF!sJ>pJ8zZRtv#Z?i5EJ?}I(m$qT0BN`vZX?WF4SYQM?dKZ96fzIUU})DHRU zRm>@qyqdWHv(#iAJmh4zBb5h-k)QB_k=%{r_P9`0j4QC@u+rs&U2qgTm?Z=aX+D+uSuz`Fx z^KLcu2Tu4W_*mfPYr~mlU~%e z0`eI|PY)>hCScGaQGOh5{9yq!D&Yhdn1+VCoO#&R)ne0+2QZJy0gQ_I`T|NSO8nC6 zFRw0!Mk7e5kdiaZgDy(6(#$WWLYiIK&90dqBVH+nD`M>yRc`rR&;94v!8C7B%r(U3 z5Q##}o?Qr-A*PRWu0SI-qS?>(F9OUrKcyFp({qn`=ED|DDWUUO4+?xCpj5~jZ^!oO z%nl0+fEO?s^6z^NJ6H$mm!K)93KSpsZ4YpQ8PdUPh+-{`PEczV4Ia@mAZDmghWkwc zlXa?W?2%p(5=yf>SjY8^Pm%)Q5PzMf5@SLY=#~I z?w%iWrkQHpP)P{QsMvRnhp2Py8_2+0Si#5=Y#0c@$UwgB!ayD;YMy}%{E-uktZ`t4 zRGI-+NPva%*>Hs$4C_!a%orF2ap==%7SQtq65g>`=G8AD;0o)Yi^|m1Ds{_zZNi$p zY%?c~syoq%#DZqj$?eDL6WW%?K@{9cm#~7t1P6M?X(W|iRiPEq6-qO&FnQ=ZoM6Tl zAk>WSs&v9ek=qf(2H8HPKV{9-SW^xHG0-m1Za*J-J6+lDX^4Hap@_sy_sGu#?TzLO&17NVYN>wBpgn;gB1*G ztXwIoW6rcog_K(1W!&r=$mOi>#o&c3qq=ee+kPANn#yWNOktA5bfBMd=Y5n_vo;cH z3Ttk&=x_{Su5)S3ec8!~g}dzeoM481^;zPY^Z8vS+wV|q|R z9Lf9k$Qn>LJR-~i4`7ad@pWwN#{P>{vx=6w-lbm$wn1)09dUTguUNsnqGA}5QF3Vl zJyS%~Z5vp@JRL?{^0=m2mnx2t6oNbXa859_VHo;ILQ*?NSJU{?kA}kM@_1L2jgs8e z1CU<@dzMNyylCOM@4SdrGbkihh*=0n6{-_(3ISD;2=S!H@`7QDt3ed~vWmT$Y|-B@ zoq$9k{+o5|3Q9;aL;Qvv5>dHNv({%+d5TfwYhhzw>`tiPLea1%BmX-*Km z7$_)={`JC@NW7|}G`r$*&NM@*K^b{v&D|hLJQ{LusRyWKbCQ#@u=K)?%@X$viDZ3KS6PY zohHy3{6>doAM$*UB$ls$kiK!pQ&HU zxyDyR%bygm^}cS2L21*5f$pOxf$u8$Y#iX?tLmFK~jXntI4II-DJ-S%$>K6lip> zJr9pS?#ryrZ*-#tI)k!z^p5M>(450+A)-+)J{009KV#KQ;`ss4-bH)qc2uDlHGb?- z{KEa2cV>{POMsDqfJT>I_vta_&+$xuuP1S8rdp#|Nm*?dW3WasTaB3hmw1PhB*=nh zGsdB)VoaOflkKfczu(i$`9D_8FhB;=M?rNC8axhaGnHl-8i5C+1z+R@Qz8KdqZq5a z+ZG)&!hnjfMn&+_3BiX2UqO``qtYH6x)lr+>=1riv!MbTImd`pgGAowqY635+(j z6@$i<;~*qz%cWX!4(}^iXPJbUg)Yd~)k8tx0k&a6DP!6gAXFi)dLAc@Vx1CN>85De}5+AvuQXd9lDoEpj53*{e6+wBd zzjUcuTQE)?EoP=z!Hy)c78E&DVsCxdd%@XwoJKqPHLPG-s5(08h-A|oQs~>PqjE|< z4(94Q!e)d$9$)@wcFkZQ$}R{Q9(=}ph`eym`ZGIN6=E$hqQv6>9UV`z4_Da1gpeJM zHK2$DFq9kffR9_w4n|`w!a|NiZi7njQ0^mlRZ%OXwRk$#ZRI78Vb@HcwIj?9sO5?Z zjfDi7o%>CGFj9vM5{`@o2BMBa+{fC@^@P%o1`9>Ndmrm;F3EP#lv^pJQpcR49?iH9 zd>k{44yYTSt)0Dgr7#VZ!D^V5F94J+6N zN#8$nP!_A@*cXy!13?D=#J^d=h{uj`NS|8ejSv8Pa!ApOWi==9g1L~3k0jN`XB_w> zS)(zvA8HzMA7&j%r7VrDDCNb9MnLE^Q@{Yb_#?cUq52v$#7gWkLH%j1*#&pIq!+%> zv6B_dg-8c#^`Tcm^_hfn4kl!@+t9}f25m-{kIUM)SU!s?dJ;>sHIoYMVBXdhwqn4J ztaCL-n#aNG5)$?WT&6X<`Nf=?89O9)wUrnIp~CPIM@*vlps5S(-p4xU2?U8ma%@Xh zDKF2XLv0^G1A)ph@3|=<9n@hxC3@DhND0Gbz(c7|?nc%$^GD)nRE}CZgrt{=DzNKV zmqIC#S~D^Y1o0tJ8oSc&=*w6Qgm@#Jlx8pz7f3X)s@?Tx^MbibAqBRXFfi9&2it#H zI+&zqaqwT_zw$Wbq5GpAN_!Q9UvkiFnb=!3QoS_WBcO5BpCVwAu6O8=$?foHgf&uv zL6R~MKh0hq$!CUwaB-C6bMar|zw$Wbq1&P!%a6gY*hmM!Eceokz(O?sl5;r8*aNRh zDFbOENR?(`1Nl4a)G;YWFq%dU7BcsE?cEG)o7J6%%rZO5nXm3uAkaFT@3nkBm2Ew&}9D-WAD;)5P8cR&sj9{i%Hh~p}8?13P{2|PCn96Eo9518&;bn|qIt!Xo zREJdtuwA(tN(E~RR=k-LOwl!nJ|OVOZ=pjd+8tFWAXwvk?E$3;6)2|Yw+;qRN%mrry_AZv99?D*p=6v={R;6d)@3zXDA8CoKj9$=tKap!-+CIS z=|dF~C-N5d`Jr@LucTLwJQ}~j9%b{arVlV7HqYYFKRHUN zC9V|?{b*-g$Vek>o&H=`OdH;s8V6mbSs&~W*1Z6cV4zXhE;2P-rLt}kA1vsU9@A8nRZ~m@!RU9YVARJF$G)8r3{uJR$!%6gq#!w8 zw~+%F!Aw9&+6c|Hj4D=!s3aV%AgDoSKg$RPk+gRx29hi?OKOf#?^D;>_~V ztm$PijeW;u^TabO{PGgjX`sXbYO-AsVgGRmY)4 zOq!w~Ug`1pNQ)6n?|lZaRqjB~4q#4zMu7R9!B=kL1T(0W1F#j_B#y{s8VpC}COJQE z1toxizb+(DY5TkR?=(f%$@&1i~(Muf4R9Y;fr4u@#`!8|9JF-r|^WMpJ& zN!k#N?Q&1@!oBBpoM562A^`^LlO$bKN0l{>s(`RLUwf#D0c?5+ut9McJV2!NC$Po| z4feIaacX8v^tuFw=9{IoA#AMi)mY*cUuOlAGiYxZ@`!dCtyQR!H1oj5@8Sd#&L!LM z_BO%vTuC(2zDB0l;DH^+xy{PH_63z;YD{&Dfyzd(=XTsgW1SsdefBxdHK{c;15g}- zK;wKA%4qC#Y$Y0>>sjMR+8Jqt?P33UqR}=lRoh5+XkH)D|(t!W_l63(>+ z)ViWHn*@jU@En@@*wpB5_`Q<&KF&4>3}j!UOH`&-2@C9@g)Heq)s>^PV&a~Eai$rH zUSpinOrQsIbw{-yX*PthR1fSak7Wb{dt&@n$CxGP-SA;(r9lvmk|tY zZ`gGblzZdj7-{UBGR#?k$sxSgvBT-?7gGnwp=Ev>ReW@s5ex=M8er~SDPkJ7 zM1*C|s%UHy&pAB;yYC&Qxng@6?fqJ_9rOedNl6K3>~$TZW~OR>Yr$k7%7;x8#Dw-e z`9?-C1D$r^La-|^-soEE`X|?67N|?Nj)nLE=LnCd34XjpQe6z;4bfrCd(O(U4n{rz zqV3_mgrH8H^lnBPA(6^r-F&06pB!Se2d`d!l^0COr-QbBfdwyh*Tub#m}+W?*L`YY zvMM@UVNosP;Z5@HOlhHIK*bgQP;Mc6VW(v(y|nvn5o^DF;s6$LSGBRG8I9`eKg{F; z$VG8n*KDu-SiyvEc%+eMBSJV7f?F|A9GFH39s5T(!Bi%rosY3yDYCS&500UHw&p{e zV3;@aGW9HAKx1vHueNuPssHdMPB7#!V@eD|v&rj)(`la8Erw0hGLGi*+sx~(YVFhJ zINk!DgJuH*)fo(f*E98foRufaj^J+wJwbXmKu~GoX*SfuNuxNA(rn{)K%RhQAeLiG z(Q)AT2_D$be!vMvX$IxC!ytQvTwZksQKPA01C?l}^KM2$Z^@chN@XK8^d~U%z5;^> zo@PJb-K_>~ZZFwjAb0@{N81=DKe-E;H%UO6!5Z-$C;-fgc>)`sn(+#*n|NPUQEApE zh0e&Q7~OK&lo4d=6aJgmK#*p{WV@U}@gc>GLtQj!dguataKPGuVuHx*rpT z(vVN_z}lJ9Yy~*%!!YAS50%9(?HSf5ulK;dcRnYLXm=QL**0D3OF1HYv4?csK%W14 zPB3HQghTLArmdi{r($-C>28-M5nz+bz4RxnU?i7@Y83z$W%nGl1z^$xt38_+4BJg% zY-gr#0;4ari5<1^X}=T(;FEsD3r4LrsHMiFNlSE}V4t4*8f)`g%LSPJ(_lW75dS54 zHPhPYG=rAf2>&{^_;rKgy92Y)`()`&C%SXGaMcxc-UUd@nZibhx?4SK^ML)Q4dRjgoh z9sL+=nXL8A^%^@ixme3HVXp~jG+5Wl8Iz;J!5rjRMUEX)8SNCKN6unfXAHt9_aDcz zYBm9(HRBsIu#sU&t9jZ{{J&d6VKWlWNd#g1tas!T1EVb%a_ONLr{Ff%M|l3iI&5o9 zp&?~T{C9-4O{~};G0vl~30Ay;brU-X#0UYl_B34KY^sX>&S6^f<-4aofiuk@wV%4{ z?kUwdVcsmoI=MmKT6O0&++81M1zS02jgA_|;E}@)?DEn5PgssU>^g+hVE0|l3g(!u zFvq8AUDGvj^ZBBRw)YhJXr6nJwerO1k#ZxeX))f2t9FD}eic2)yR>(l7Di+0k^aUp zQ88x77gVIHA3>bKIm?8CcTx$4Np3(kv;FBM5A093v!RMlI*KC!%fTSQYE``U>gS-@vIEtxNLTiC9rA zj&U&`87L+`_yJz9CnGN_@rE!>r$ai_9P!65-@_YX6IL61Q+c(6jcO$?niF@P%INZL|b6N}F|e~c4M zl~u@Bnn@}gk3wH<(${Pc&Xt=aRK3VlL-X4hM>*+|NBUs9&f(O|n8#~pounCIVAv7F z){L`!up?O;sj4@IPyf+a5{!jPW0d+6zG_eAZC#D@jtT;Ua?nW_Rv$EjirO8pos&k< zkA(~}LEm<}Y={7+K@JV^~G+dV^*z z%#z$1=7BPuok^iKxx(>sw}!%YMsMXzGh=(lEYzaay)zZL=~kL+!aF&Rhqn4zoM7Tu z6jw)#OUIZVGGv!cbDm>{*H94RPTo0BS~gkRCY4>FD6v)1C4J4tzrd-PF;7eAiN;x^ z*@^CE!fului{fb3JvWW1DM&Y@Ys}Rwdi|KdP=$KdcpIx`5N(SWLNk?S-BqeKQ7HRv zAJ!p2RWQz=w#4+vIx!?>0fP+ggZ+}Vbw#8(WBA6bA;&PA(B@LM6G7|ho6O&=t2&fs z02=~~M4I8VsJ>$2MBWCEtU4~hkg02~1enq+0Q<#rI87g~Rsg_|{l?r0{YWj00@5Il zkM{igdBLCx83<@J*28a$bvM=x=gN(L6@9x-}U=0|T5Ez=E@4QltgIdOSe`K8$_oWhr z)XEZV_-~;%s@>|BaHg49U)RhUu`9+3SBx6YtOvIJm8@WECmf9Jpo&4_4dU~OQ?SN* zrv5W;34%0I4x#6Kuq?G=?n&l7*@|x$~x-Tb~N*>b8kT_JA(O~%4 zY7a_?Q@Ojjy5z;K_vATf8pUzlKn~%2dn8Z+9)dtQg1@>OypNMcC0Ef%K5&S?!MbLv zId}3xb5X%9bl5(~shP5ig`hCg`zTH@g+tj3tBJj$qkpEpaAG~@yScD^+>CDUl$}R#nUx)H1Ewfzqe(Ox9^gRWi*W*@h)j z$QHAtXg!~OfOAbM?J%Saq-XdXpiv=-U|*owiWhRyNCrZ-S2Hdbunv5>+!oz8QH*lt zYl;DrSbqgmY`3d5tg`XIekvHjbmdh;^Yj2IL?19}vWlSzU$bBGPKuKXJrk<)=};dR z+gA6SMPqZyeUo)Zb3e^`j2#p9D7qA+oH6Ht*{A-Mkw)Fl>5(=}A1T&r4Pq1Zo^kA% zpf&sJQ`y0=xV(l;J?kY^jkf&M&N_w_jD(Wuufy+gz0?G;ZS>Xf3uhnmpPXPqLMDOv ziAO=|7;1O_NvvQbl)#j5eI(5^mKggpCz!9059Sg!)>e98J6R{i4U!7cWFR=IOpezD ze6Y7XmQypGW+*`j6i1hiZGmRu%#2_pM>)s)^?#}ukE;z&BG{`6MJy$zuOHK8^Q`$y z0n%8RPCWI7c!0>BUpU=8h&X^?(SJaN2P+*%T z@##Oj`r{x3cM$8Ki*XJ_?u+`>bEz(-46J}vv^ z%gHi*w|XTj7>UJT6>4f11+i}?S3&=p!~3{yIOt5|77GEvQL1;ffvs$vW+T?~$Qc;zBR403K~VDE5pJ)!-fo*Z;w-g?Gy#6?$GkK`BTb|77`j*C8_0M0OZ|G9i2)a_ zamO!*#oK?#shM#n$WmaF@YsU(knZW8_cgnYbqgx83k@~_9|p0m#*#{GuxduxI4}@kpauwK>KE|7PyLNB zSj}2VBQ9Nmf&BLaoSGTapfAu29^|v0zMurz{CQ3==;eWFYaFID^IQLD@H~+fj5-#9 zX13VSOF?7h2K5x;F^6)3>3oKcg`eT7^v$~9wbHNs7c1DjPos39lYw2~=WCU~K)UW? z1k+3N0~%{nG;|iKVm|eBMlf4kOKGP1XAX2kt!eD6Rj$>WA6LbxoK3l!E{Lfqhx!br zfi-2DYUc6FM+q5&o181k&|8N{jLKnV(1A}lZRnI)hCiEo1?NCn&8Qm)pfJH|o-~h0 z?1S+xT5Ox)y$o%G>M=LL?PHHR(!BOaTdh3aUm%r+?p|MI)huPE)q?pnbzzb zTiG;oJ%zM2LOk->#JHrO&^(^|dp0oANuubjQU45{YIOvmt5N>62M{Z&Tn}F0A zm1dSZ+%fAQi1hQp9ypc_jA$eyrx}a3Dd4CDb5%@R`v!8}Ic#9S(ME^_!nh08^&Wa0 z#Te7pAO(f-BHnrGDXGNj1ARsS1sFC*^I|{q2TsjY^BbgLXu|POM{H}vE3J&*v98x2 zPza`|cu1;9G!0Yzit0~U=VG*G$XIPkGZ*iQZ?eU)ZC*{ib%vG3ey9W*F+t}DvFD*! z)Vs50t`$4Ark8DD1*0|P^ql}Tl4?#JLLe|s{E>SDFBr-U6iz|8wOJULVxmZLU8ixs za1WvCt$rn59iXVxp;K8`+v?1#XmgRN4_hfoPkZt(4K}-+HO;7~hm%^kc((WJ{p_6H zWkh3ghM-B{>PyUZ)Z_N$)eN;4$|onV5qvu)z!pDZeM<{+6^)*Jllb(^o}x}OcLfZ4 zm*o1*belNMhZ5qtuk)svk{mHP#|qFM=wk+h zH5$St&9)%9kb)ueeC+d?!2&h32WzJB=ea$3$F6*_!7nunq#ru;I9|EDsBa2IvvRL#XVwgI(NJ_9ynADaJ&n=HnL3So ze@cUe^0}vTwjZU_)P)igx)V;7AZxCTNac?GC$DB?=%7)Jwr{3Quf+8_lM|ZzK4vg1 z_TGCI%l?#ss5PR5t=(#`%fv+^G&`d*i`A0~3>egb_rV6e(SlJAJns*{Ol*BAEd}P_ z=p#Y$R&T8w7Z_Fx31ezn01O=pK+{Nt?|R00(+ql$HYQR_xa%;YI^%)e&f6jultRc`$Y;;Q%o*)9aY;Q>e~`KI)HK@EhnK?HFeJpKG{~df z6SlF_XtZrdHHHxhLv&&=6<;d#u*8$^X9rUy2pI_M@(9%i@zCt&@-C~PG^=gAR%td# zIU27;)-&}ZSv!M@FWUZjAk@3NgA_Mb#|S&5jVy-Jc0eNyPyTf^C9Uic%FryRS*b zq&mHdYmryIUxw|4Xxhwgbt_i2W>-GMtQqpzHdTTUjU$_}lR@1YfBITxFwFI+eWQWl z;KN;tK0lw`{b*(|DnXQHem)Cj>i0d59c)GW^z}Ag6_i$0ObXLFaH2M-6cm?!i5;xg z=hQ|-w{fQwo7@9I=B<9F{uJkog?|3pQ5*0{j^4`DI%flvt2yS3tIs^@9qgK67qr@( zXgderJ;N*hvlHK!epmNm*0&**0(d*C2jz)%h+{trOOq_)MpJ6d&gGnj)FSEVpahx2 zuf%`h`bF7SxNB;)8@5Xr%Or3vv|Lox0~E%h7yeS;6kXPK(bZ*2x82z)uE2T_lvd=P z$UOuInN<_pu3@kCb@=L^n8U=yCATXqaaj+uHG(v>hansu;jE)Y%T+n3!T$I)W-v7M zg*X8QqNl2#Fzz6&qz2o@-28@A(n<=mC{OP>S5ccA=9_$jDq;y|wR za9+(w=1S5{P5*50_8fO88sCZJf3r>)vqH!Y)dr~w_(jFV0d6hp1gn+_Tckat@vcwD zH3z~%9I_X3FXWy?AfX%Z-;y{8vKRPA)sOfxcV`e5U#Ys7tlNTx(Uq!IokI-%$o=ve z{01Vb)K;8?kyO`Rb9>d8qxnK|ulW-*m_un)bMWSNrzMeivNDVx?d1P5gFz?QA-;mG zrv3qf4f|ju%H8`)b})PvthbNw%-g9XS%D1hf!(+lGuS%Ro>NDd14C^S&T-_w8Xqvy zMk#tXF@tFu{UZu3aOl%`-FfU_Akh1xCY)j4s$NDTCV#}=l!Jj_PZz?Yy+TGhjXQnK z9(gCbW@rmjJ|i&K1&#F;(qClVK!&)2J`xoTT34>vXt&+cH5#mtzNCO&%uVN+4ng8u zrH<&o$Xz>4j{tYfbp_B!-CP1wGlQK*yPsx%;BPk~wX9)DX=Y(`e;%Kv@xeOpVb@HI z?*x)cGcuE{n7~jZ;``M6rM`YmT%{S!GIfY9U$f&Gi4z41+Z&g#Scci{0xwds0@J5 zqWWoe8-Fhb8(j6zj`nPmcol83y0dfO+UWsGv#L0X_pM_RiqEJ#byQUFH3YHF=(@A| z+&fp?PVqvV-px)UZO#spAokW7LUy6SDixOaegW?c8rVJBg^i5jjdWPY`24iS5-&S} zT{D=5gCQ$?Z;dc8{}~v_3%|+?W{Oq#1TZ==SkWs!)7CY;;#p_!>1FCy@*7Ca*e+>^ z3xH?lizUJR0A{yvaE77nVm;U#V}4qjFm(%3`k<^A*;uag+wyK=#{P zR$N=0ExYPvkqK zZXn%id9>Lz>!2XPw;|i6{3_-q{<0D3jG?$PF(!gV%hEhVZW$yUh4J+YyJirJwFP)Z zz##y9NHoywyI2Lt>@X;S<~N#-ReMy34r=3Tz<{) zI?SlpXBaavLPE1mo6z4??ql2qF%qmzt{V^?D1xbG>9+>@#ae}B|DJo!Q;Bt?fVsO> zq?s@+1BI7zuYM~#ji{+lcE!qJIphw|X!NqcKwkJZb}+34l54ea$uH?Z&fe>z{9ss) zZENWmY8U39sCX-+zx6I|Fh}9gL85yB=NDF(3c8FNjO0`4;o@kKx9)ld6d2l-td0tP zv$R9sb?LtQl#d8a#E3z~}IfH$pbGuJA+ES=c>s4|Z#W zW|)hi*GYBR=mvO~>HR?z$3bLfk3)CTA}?cN`lfTB+yu(~y8GfC?3yVs8fL@`>7I!= z8gQb69Sk($_0Efj0p=Hut_HKt$ALIXb4or9L;{Luz5(STAA=lZdyp9?J`+XatjFBeZs3R6=;?|Be?7 zqE)7zMqdU!-Kcx39s=Yv5R~;)c|tP>SYgc$eIvVOXm@u&Jt{$DRI?`)(QcGz$EDHu zsvdsLbkie6vu%3iCR>^*-l*C{EkiYR#GQF!5t>Z_BTX~?5)P|os_jkI7&ra%^o)fu z>Fc{zdcLFwU$oS&fk!yFMABs`n!QtZbB!J90=g)lQKG!qpWL7QW)sY$p&O~o|L&ituPvpKqo$C>W*nA?w4Aqg7qI>Iv$mj_8n zncbHre&%0juZv3kn0~30Ia77LusZSh~?l2F*nvd-QR=fH(e2NYu~^O zhMtQd_Yxjb&QMkWaEyQ z(;@HptpE0CbRyB&15#CDvdwm#tDV8wh@hbf1%~$|nVbVTRm&MYMojcf#uDew*L#|| zOkgPRH(>UKdbm|F8kPDkz3(@@F~j3%SBp&$HMS2SMy3AqO}ggRJRYl))Y4ZF8Fq90^VCQvOpjP|PCUuP z-+#+YBgliJjo0wwIur<8*Eg8Klw@m8z(DX#EhhjX&tJ|}U~E+kDoiqc1MBAF%^h@r zzrwDWxj~HE(xIet-H2vmH?eD`8&ok+*V)r7rArUMwrfX_uFzTFJ1?wp2M~4l>%9x0aT9ic7;BdaYwRe3 zM%C6Qg@6}!_S4ukTY<6>dCfqg#o9a<6i|XdA7i?k_I;J`hTJ=jVb=^3{i}xOPoxqg z<{o%0FBrtH7?8EIsRXIT`tM@7UJ7LhC-xLsgQn=*C^`<@*|BZs4E7@liK&V!9ot*;3*iFxX>aT>nF7d1>Z`A0d~&IxKoO&i4*u zo5)zfbgnnlo=bf6W_yxmeKufw)Yy!cxLc1F@O9u}ja4}&?e6-UN{Mu36F>VcDq!Obr{;DNcJC&=!l_FFrR>#x4pacg}sK`%VmqcIkrF-W9AGpxwo zZ(7h7Y@uV_-L!@kjAU2Gja!Y`s&Pfl+FS=B-!|VGqtSUn%Je%rj@p6`dq&;$%xw@z zw@uig!0yU8M%_L91JY(^_4;wuA`Y89V2z!+4HA8Ve4(10ueIZg5@-{k84`B4>T!^8 zRBpeE&h$uS6q}?*t7_xQUCJ88p>w%00s&I{Y$+_yt0TlCwds2yh99KUgs5!XR2e-M z(qu&9mLs)hk;r@jYxMYjXQ%1($F0#`^8ydd&4&=&Z3^>o7`Bx`M96dc9_*S4?07Of z0vo9drpCrokcwX8n8?pIJrY3S}^?G3Gw-UVa(_ z2;=y`t31E^Yk^=#(P7Qd zW@r|?{O*bVuX~HojMnB+`yl2HdrA>t0CDg?TIdUL!;^}jQEOxylzT&IcF6gKXol`f ztOrB*YrflhFvEYXPZN;$h@KgCp~4c4X#PFpz+yDRms@0y98gns!J|vB1c{cm+X$0?oWKarTw~o=VmYzgVMw&}}v^>T!%NnjG_IhI41q=61LqZ>nS;>+Fo_8TH-dKJVV-7@ z*t~)202TN(OGX9#pMJ-}=#NI{458E?8^$ux+oP&|xR5vNP@i>6(K92X>1J==g$8rH zot#rKTH31&M2W5od)BiQSTsM>PiOaGK75r}6TScE-eeu8;bR~PgFJ@BORQ1%NL|G+ z8wipGnXKkasR}zl{Or+1n11)L9H2}s103afP&dDM(~P#pRt6FSd$;a+;!Wh}L*xt9 zW(Cyhj%zmfL``Gt8S-JFl_Q7rV$q18y{;?-4A!CkB3NQiZ(KjFarCOihP*V3Tf(x> z6``3@i>yED?yxji{2`)OEjmQjNH!9^@jVX~p&2kR37-J7_1INP^ELWViwqg+>k{#s zF6t^qGpDBZTaLp0MYr{tH6v>rP8!HfehCtNhMXat$r9E$reBw3)(j;G;l)k-g1_iA zo6o6B{C2ZuOj5@p;{N&_4TiZxMu%5NdM=vkcATixcYeJHYgB3G>}#!wD)5?TE3jx} z{*W;{l41rA9k0P;et@t9EKM?IMBEV8KS6^{g)hzTuZk{nnQg^tSqCd)<^1k`oF*T3!tB46lk|#lmO-U`*JDgRz&odz>D-sz>nnWWOXq5h&~s z^*xKvWtaaM2+c^%lETD=e>|Qio zgl5<&GHuTDzUzws!(NI?BijutCVt~jibrDe20BsX8{bG&*4{QNRJJfW3~r)}CgTz> zSmn{^#?RylSB+bAgC{EF=u3)7vpogMM%W?>k+6Fb|EdXyUm=lR_#Y{(g!s+1TC)M1 z;&WAFUNs9=I}w@tF4th@TqHVY00tsSvzR+dc$&rH^93t(I~FoHQ89O%qrqZDX7r*( zhwzm!W%{Vo!tOiI&|r@XN9Om_?xnDfSXNu^cbW17ge26u=JB0$Va2TR(Kjm1cv%!R ztfWjaklVhhX^b_xLQk2++iUNviS1I1hi|Tm%YLuHWH>s%-?-B@=B2qlD(N?eYcOT3 z(NnoX(#E!OVr5juz`2E_*~a-ARWUJlpB@L{HV~Tlkyx}7MRWC*9dw4%VOwBht1u!4 zg72AsTBjK&5;gN_gJrQyM#bLw_F}AY7F)C@s{efs^1z(vL*xxjOp{tMp@-?$(wWn& zCT_lzM8?4O)+4Ejc#+H1jIAiHDu>04`~x$J#^fTpTwta#)zvkb5b@?>`e%5-$ddR{ zR}>G+Y8;A@bYOEBEtr{-l}E&Ae1)DwNDd?90#=iC6LI?xPx3kz1G$99Z^o`2_y$gV zc)}R?kP@5SZf}v7 zHJ4Rt+I==@hQC;Y=gadt&C+hk9*2&Fs>~c2kzuXYV54p%I%mL=sRGQWYcO8Z?%e@z)Y~{UIvv z^=J`ew>0%ul@mRcBSa1T<1pPHb6=*hD|*qX0O!VQu0LZT11)i&d1Z$U5bL0@t8LnVJ?1InjMP4*!J) zyAZ2Yo#rGpaTQ7=V{d@P6qxz~z`&s#ij`wch+Oy*8@p&&*eueGX5V$UY0c<^JbX@# zq_(MjQo};4zfxd*R9v~?6M6iu-8WG)@fQ-J(JcSz~uk0_>>&DF95=u=hjCTDfhH*I?(&#LRS2s>Cl=Oif+#h**3tmenX4 zhhisk1!0XCbg2pY7jlQ7l{pBkjYD?zXt)y$n7hCronb3)(1u|TVz0KcJ^4j z1lfvxcodDCV7A?-4J7uAue?u#-8>UJktc{RTuCuJ+*6fNDL=!g0c}+5HNPR!9$tSs54e-`~_=h}RDlzaUH4AiM9woicj&n?LA- z#Y@fTb&Ct3CQhr2_r;6_0(JM~eLOI?9+%&T zd^VPnX6K`SMw&@pFim3|?+thRG%m}p5J_<8Kn8;GqrGnw(}av zzUEF}Gd3g$@-lT?vm-wQu$`CeFmI+WjdQu0(LdH6uR4Wz$sMHGm^J9ytGS?{*=l*> z`lIosdp9DpV@}gJjjpGRoXHb_>DT0(_+?DS$7z;nv@-e_&yHfJvj){zM|{1I_{lB0 z1240RO}}pfpQgr`bnN64s9E5sg2jrR$`Qm0mq9l%kShMK3e766wPAj8EQj>?t|OlMgFG)TZr9u#m79;_ZM5n z&Swsq@fmSQ`j{Hw8GzxKrjuE6;zl!V?S!HVUr;MGE6S)GY zVho4s>!|zC^GGuoh_J+5^i-bEoLILKnc9uYIOsKjW-@vvPY9afb~Sc|Mpoc%?V}Q8 z5JeTEF{;sTCpqkViQddV0B7>ZcPgy}a7c_@SvzM5dj#Ha`FL0{yJJhh z(Eq6Ws32=R0K2Ml4%IA`=^}cGI}O**&+kA3K zQCxk)A8%v^n?#06fQ|JQq*+aTcqU$k{QMdXb_KI$_`c>v3C*6gzo(hQn`RTza1&sc zY|>y;%$mXAoCMe?rXi8f_^nZmyTlr)pMALo8|T)nCN8Xr&C%@fkDE2voXeYLsiyx| zd=7+YypUP5shY~vZbY>eg*6KdGhrYrPcO(otSgfx$g$cQE7CySuPqbxbJ?7#x{1%db_YuQ|x&U{fwvC zScS0-LN>R}9E)LzJ6zpfVx!UhsY#Gn6#DD{=Y ziZdsd_}I<1c>8oLO5EVRi4c1?Cw|$Y!_FKnT8_C}-=j6#1kK#oxg5bZ2WlmT`6{=P z>5naQ?q;<{)c~n2i#=`?^VC9M*mgE`OeS`9(?N?2z>Sys=i;SOL!QRn20@EnY&;|W zY!_p^k({HB1s`fBDKHCTtegfS9BE-w?%2bB22HtwTs%t)@rM`J!Q6sS1F_%q$3cet zbW4=g!L`kJ=x(wO8s15`3p@i!oX8eoG`ww%wCbG0bd|-e3 z^oAF4o%B~o&(8P~^I0R^t*o)9PYCJD^nNRQQK^r192O|)sGMNP%Mj+G(R+>?-?8T8 zFKV!x1B}2Ed#vVyWEb@0n|p7PGJeaM_&^@IOvdDp7~QN+GJs9Y3_!De67&5(S1VnH z40*l(7&*Z-jgF{coX;2O|9@&NI19N?i{NJ~|qX;nUTY%1B z+*LpEATJmtf-!Lk8HjY_XlGHWFI7JCPUTB81t#$+p&p~diG#i9-a^1YV zU>IigT;TB|7WM0C2C%bb;>Jhdok5~;YREsu0){^N+2{BYgWtD#>xd_K!BVYJeCZ_x zrCCqX^hM>p1%cHnGN8}*9OS?DfRyv&SbmY45^{d~NUa(6$V{G0T)l{hG_b?2^=NDb zn6H^E!J19Bv@{FT=rk*+nd@rCyAzl7VbDdD`cBvysl~2b;0ZcFNssidRX;%szph!m zZT!Hlz#6B*H|6%HRG#8NY>1{bb5kn2&|UyZg@PEF`e1dix@JduuNT4er|UP>&)4Ic z^Mzt?^W_2Mi!`uCeMjY$048GbPNqHZ@z6Hk3ms~kv8j}nV^`Q^E z8k3NBI~L|)psaF}J3Qy=v)L2Om+ruLdMaD|VDS6tZ)h6lOk++4u{k{(EJ;ndgp{>t z@CdUqYE353B`#i6gc}qH!EOJ6Hb~6nqcO;SF{u>%Ew%O0h{cyNQ_g0Ha=d%&Y9(>^ z$KMalUglZ{xFh}>enGxWT--#2zS*^eb$RmYKhVse>$LUvcZu2L>BYymxCJ8}qHA69 z-oMd{z>_s&+`w7}PFJfY4dly5fkwST+K0+TqaLvWjoRbO)W3Hj%`mNoIY{1V$mCQm z@P3N%Mj`PRtdLG>AAP*WA^&cOj5}M{W0cP@)Q%#?iJ#684zihJ4#?>Jw&=Qvz`!y6 zMNj4or6hgD+kGvkmb8BxnNY9p@bOq6E7s~up7M+BoxQwl?gd7rn1q&8_xBzu~AM* z+@BhOx--=ctb#Sp*81j{@>u|qX5H)VQl^jPYdo1+gUR#}o~NEcU_)3Z^;qfXEBp0N z#-mCEq{&cQQoyZG_cJx8X240K@$er7V96)R6O-0u+HXSuCiBQn+}m2s(#qOk8j^X5 z##l;bJG`$b8jaNnYTq_e6j%z4A#3C{kg*i79WzB~mXc-z^op~psZ$4C60|oRfh~d) z*Z!_J14%9mxtk5m+NWa*=qH#Yfa>6vR>6R z-#h51nK6|WAbg(&!)QRwNYZ$}ni)icC)B!1Yo><$PO!p@u%|S>qWzZz6aPibc?SB(Q}02oEeoWAduzV|*|qOY){e-b`TE-$H5T zCQmOq#!oXFWn%*F!iPM~#_~5(>0ujbX8#^5$_#m_F}I3EGuH>(&^;o79d$$MO@uT0 zW_i*q088zo@2_4j>KT_uoF$#;b1XXK;toH}oZ3gR#xW|w-f=heJmDO*j8ywsj^;`? zCdc^Wk3F#1iTpt$UY`l^_;m^l?{D)qzol(<#2?t$@7JDYXf|-T;L{b-TIs|EUc3i^ zxoT}*{9KlBFoxvifryOfpF;Tz)$~yQOihCQ-QDJD=CFfs*x7G>6*Q9@u&$Sf#=3CR znXL!3@278qX2RY>VsdSB{A7l(pUgoNMzNf`)iBylQJ zM8&%c;u6+qZ}P{8akg;xH@!c|GA_;h2VR}>Zh)}WJT-0ZxJc(Vx*pb%Vj#l3kJ2ni z)kYE)cg~`fpzEXetTVitIvTzEkkjarnpmCo{KsMW8eF2e&`8wo&!MbJE3WJhFy}M> zNmL{L06(OEPk-W4&@8Hx4zbV0q=EQx{t9V{h_p2IuUp(NGFeZ`9e2V&)SwH_rRBqv zTbhWfIfsz2xcP5Y{j-{JFIE_EYPK;^3c!eZ2{Dr{x@Q5MWs)@fwa%oVl% zB#nPL)B|%F)6B$nKWQ|*;|m37Mqp_)wNKT-(jF#Cdb1%&N(1Zg7cE0h+WBV1N3W~F zK%y}!^txWH*>+UbY3EaJX(DO?&0godi7@Gienv3MIpQVBhw7rv;9Re27BGT|N=+ug z9(WqSW_tkUj&OqYUpSEjdn&C5!REnqiV@67752yf)CMxk0_H*rIT%PvKC&nn^s5i~k%>J^WCLq_3U2%kXPnS(jHi;~&kVrx=}Tahv`H}nx`<{s8299ja);|zPS&3b~H1iK8Y04Wn*101eI z!xy01r>iM#HRErfQPN^c9<4kn$YaTDCcb(bG=uF+0!ulchi^0x4oM>El=F;ay68>^Fi7tEvh5!}BkR@A{* zWjiQr;{tzsRY72BmE(hRI#WwLMOsZBf4C;Y*g`9%@;CqG83?3|Bny}(WhX9!b)*=` z85h?z>v0n|WsX1zIGeb6!(XTbp*^IjPtB069R*>C730Zry^G$l@SNrPzJh-Dx+1Ju zN=dy~T=l@NC62GS${W7_z;}~oPD*Nqugc_4(s%;)C{xY>Wb$+-6uK$(>G!ni*2tRA z(z*}(s#O#E3?mpyhy^mWS|JS@huCOz+9t3j2qL3yMYRwbq1m{MA|dpJn+pLmgdSCl z;{8Frs=}XU5=%^?NCN2q3+GbtMxu0G38GhWTaObSgedZw3VL}LzJ zqPH%PW*^Wq@D+>|u!2?6p8T<2RcU5mxf~}Ly&RBqFZw=#;r%T|qno@SQw)%XQf?fq zDb3onW^7=VwOMVzpJW>4P*qdx=d-8pH*R-!#J`B;a4I-qfO zjICnn#qV{{T#xtxA9McNwK>{xrY5ADa{D32>3k+r&Sj5+W|fqJ zqK4KLsXgap7ahM7^019pN?!Xl-isj`W&Dm@;k4l$2%PlSe!ID(M{ZtlY1L!YN|yzm zBqE~u0GO)Cw95~~1S_Rk>dCYlnu_Z^DaAa5I8p6#$P8xmq;J1>%3;1{Db~}J7O{(5 z)lM^H|7`38g7^3(fP~StAxv zyyYv(KvGs6>|W?XS1g!je|%RV*4UtRwR7gN6AL|NhInH_K0ak_5>`#9fwHm6xSK)h z0=HoE4`VV--X+h`G|nz?W0q+3UW`n+^LD&hN1w8@(oUva-(=M3sWkp}RRP^x3|@Xh zILYT)k4bS1dm2XaROXlkWj$t;z}9UNZf4oZ8!H%+OB*k^_i+SvSexS{@5vftR3R)) z-p_Ss&=}7uIpscMQVx9Ea+7C1h$V;UZKsTjC$DWfW`nSX(=LAXkC4x359zd%8RLwz zgqTQ6w4bz*X6i4a=#<->lsFpcAI0_$Led`6sTX96Olx`**bSd0Yjo2LH5(A!wOok) zw7Yv%K1(~3BW^Tp3k}HIbBr|OcZM3gkI8+*1I2&|X~vKcJe&qM8CMl31dJ6_(+0rz zywWoeH~Ao$V_+S_BE{zJ#bzYzn$c6H%&&@He1u96Cxzh5deMyza#d31yRIw9KrBh1 zQFrEdNwbuvh+ekH5DE!5Wgg)Zmnj2Ds=P??k;|nRmT9l0&!R=FoD;b`Utop6`)4U4 zu6btx)+iSkmYO=1z@C!w7}=v1oFe-j=3)$a1Zx#zbPg@Yr{$ARd#qmMl{}FrM)u0I zd1~=V6j$6O2&SS@$)q^v1^i$F?|IIrV2OitQ!edP_Biz=f|T2j$BR?^G#@e3Q_}x`;7~Vfarsf5kTRCxC#f^gr zag!QO;srBon_6s1_tK66Xq>W*JJSqg2dxL8JvW`?gJg{{2JA11nUuS)R}CI!8Y|e- zIgQ5}n%~Ow88t(xzazDcy-XFvyfg~goxb*ar?+58rcj(U%D~LvL|XHE>#O+l88uQT zMattpWhcO<$J(TuRgaYW3ad53$UrQckZ&lc=udt zkEa&IH*Hm#?ICl>PTaasS^LK~6BxD)a}u{?jxemD^m{*rS1*-w($8m#t!y@?Q(79v zfgj)pGj@Qiv}VD{=y}4Wm1LQeQa54c$w4lOQGx)H2Tf$(2Pr+NxB6K&DosXjil{QVg%a_mMCnQXiC{A?t4C` zX6OXkZb-kbkRRSFe#HqElAUIbC*4vISjwv^V$av`fvE!4c0BcHRIVz$fd0AYcYI(p zk<`$A^k7afAF7H5o9_?(9`pAiz);+#f$hRbD!)rJMWAebN)ceTv3)v4g~NZVz?_s* zIifJ=lBV1rw<$0;hvbx7fs~eJ?|pG0G{!f(*AKJ`iz)dXOg}Bl?S-BvzXMn`WnBNI zA1VS2YNfoTC3f6Y5Lg;r^B9_7pFR^R&62I`WuF1q=CsGi6IT@-Qz`fVbXg%Zrk9P~ zm_#UmMzK$dVq#u_rJczWhvF(NpPlgXLTIE-_!1e-{?spv0BdRG2^!N1Vr?LK(kJa+ zl=>-EjD4Knfls?9b6iUc;xtpllk4ItvkD8`*ir+T_R=giF7QMw(cpJ2&D04~)EWH8 zPcJ|-17Iqj#Xvvr6aYrA->POoV3oRV`|^&0zyh3*MHEvI2lUAh6q?^(EJU;PMykN; zMf|R6OjTDW#r^=Vs_?tz?el5f+$Y{s1Xve#PD*hHUs?p%GDBYCCeiNxM-gB(;|_f5 zB;l@FTLf4FMn@DioaBfUYy2U0IV{4ho=#Z?c;~tzz|5-Xbdx%Kt`IPzT9t`rBli7% zY$2MtqP8Nb*}ZQn0!%n5GZwaZ`VmEdnHy4anJw-=sR%G@dhNvHk~H30#5)$4Z5i2; zVvPr5Q`VNbqDqhy0}z(Z1Q;^4kV&)+uPy=%I2bTUp#AFDg22+6 za#wt~ATY5bp_n-IpGASCv_k%G!XFHN#OTTUZA~d5sVyx2f5CK)Tl^RSSC-(3J2QwTfg$|AtptN2=a(w%@$xbV9b zZt5h^E3YpCtZLknvXDU>w4oTVRMRhJmZ?h|(>t0>ooDFjk>rV7F)PsqnN3RA{E8xI z?AQ<++tI-7w-y0b?Mqz%d(F3s09!GfY9PORs0gt3YFApb;GR2+09#p2O|u8EcM`v| zZ<5_9QV)Jd5n$E6)CI844+t!+b&~RAO-EIak~1k6zv00mz*gATcFe}ns^Zx{F9K}k z_?@fVIG7NhKA;G&svJ*i8Qk~lBEanQCG=B2E&{ANm#WzTrxyX%xqK=upWUQtYHriF zg-muUgg8X?V$xbCNn>h0#>U3*DOdkV_0Q7Iq+Hx|RMnK#fn@P`>dBO54`(oH5vM)> z^A0aWvo@Lbwe;)0UIf_6TI%AHmroS|Hl4m_=tZjMnMQEark8SIXL_35cphoS?X2bF zDbH`b>Fy%Hsy9ugfQhdaGKqi%u$5%<+gPWjM^ZX&`IwcdxBu?`B51TGHl=7L4k%>M z#az*EI!Wa&z}t`oxMPx~Fi`GLRSf%pLE3<{Xn$aPA)3vnv1JbwGAVAQwXKBsBbLy& z%oR08oT|VQ0*hJsqgR$`mYU?diHsHSjwor|4P(umPR(cB{S5y>Ub#Fa&A7ng^~?il zt0o?nU_O2RZ=p2$ApUPEn17P{H`N-sL40{7n9oG6-;%~$^!Yb0RT?evxxG?KeP3fZ0Ty&(s^oo`|FnI%wS6mWa-k_Qfn;1 z@)p7R{#F*mWtx>~)|i3P8XNP|X!3lSW=#^+__C75#{4vSwxqF1q8eXT(%6`v zCeM~MHc3?D%Ssv>^V8(nlEx;9YJ6D>X)ISrH%^MC&$ckl%8o_TsnYnuGR+$E)8yHb z#wLkseA$wvv8BsITe?1x(e8ka6udw(GxHB2u^$`#V-yeu~M;am`hHY7_?dri4L zUkWQJQ6-Hjq;N+)oby>@E=tWB^V8(nlEx;9YJ6EqV`F}rJX_M(BvFkoTdFh~;_}w* zHPKSAa=fvzMK^tRshWOiAWfS<;|ogzY0OWPXGK#zyQkeXgXjX{s7sSkl;tou<#Vkj8R_bknKQ_`(*ZS=q5@oD@x; zEz_)Nsv2Eb(%6Wdrq3-|8kg=m;-#xuOBXFyw?DnyL%Qj5V&My0S%Q?yv6JcGCZl#6 z^Y@zzGJT7n*GKW+^Tv!|PE<})p=ZA;BUn??V;2=>`X&LbiK4xwZz*UN)k%j6qp<`_ zV}K>DOtX^4h76Pj(vY5JPnI+`%T&YbN*Wu|)9lHT#%7sncwI?jLwcG$S<=`nQw^^x zX>3SOvnNX$n`Nrub*-dPZY!5#H%yEsPqr}4%D1$dOq1PR*1|Mv>7wP9f|ZlvyEC&U z&$rMT%QR~;O?G!#nP$6VsHyWMjZM+CyNgO1cgIju=Sv!!qG@**l{D^-p{CB4G&V)k z?k*~6+#N$roo^wHYbiqp2&(G;4~c-Cb1DxI2cLI=^ITT)OLs zm#${z3hAcu?CvgFx(2dzSGDt*zT=rkwSk#@@7@Ad+Xh=84@Z$F|HTCM|C?q}ed?h? zD$jt%zB&;3e*Qm9G)BdyhYHaw9jfeDEX2zqx$RFXr;c|+5l*|p7Q%Kz7a|;XPk*4KG0aE0e^}Azgigk3{9Q?7h@Gt7vTV%C zT;#rz#t0o*10{`FnTy<4(iov5YhX#!*yxS1tc0cC_qY3Ym0;=AEGD+3aWQNycx^E> zN)Io1pHGLM_5CGm`U_H=`9zGpK+gQz%eH<%#$r4&a&iCrN*W`CWD6|mWkj9p7>)cYX^6maCrk8S03$3wCvlRZbM3rflg|);zC5;J6vP6_L zW??OHPf25fk}MIRu^a--LR|EoV#cnb7(obNfxmE1na@}#UaB;fdq}gGN7>ddY1|D1 zOSJ?kO@B8D-|XonYamN^Bi*H|SxdK|TDp6bwbVeCE{!d<#uBXA8msYjOSV2M4Wx0x zH+!};kY<@`cwI?jLwcG$S<=`nQw^^xX>3SOvnN60(jC`tmW15bl`Z1j6q10FMiv^& zc4J-|%RQv?G8nqQtf@m}WcQXdX6G(+XGvp-jO^Z$#_ZgM?p&%gwsg^QOTo%%$dLKw z@h(-4J1THc5g{zcJ4xVmNbUQ$nGs^%+6it&Q{ad(lO$Yo&|ebO=H38 zgv6Jcg~-V6Z6S^23hC_06uGm7X;!xNBg|(HlxdcoyU?8_jUh6!dzUPYEnOzs(rL)0 zt658FT)JTG{YSL!ZOC#VL-xWqeCLuah?j0YD>VxnaCU!b`q{Y)-C5EYA|t!Eq%k{p zp*u?&Lu6$4mNaJPE_7!}V~C9G-jc@b+=cEeX$+B(-CNR_ox9MTC5<66vU^J!vvU`^ zv!pRZMs{yWV|MOBca}7U$jIt#>7wP9f|ZlvS#2VAUzyKhgk%erG-l&1c2`MbjF4=> zlE!Sj#qKI;j1iJ8Skjn{x7b}JjWI&91xp&U@fN#lsnS@kkd7sE*5Fb#kh15Q)gof| zl?DykG8 z(i-zy$dWdY{PZ*{0W@Z}M!Q)Q@4Dr0Ez8Cf$`(uG$@i2rrqH<9s2nB8;`i@4_08cl z3+_*Pg6@%OnZ|SqP8zWj(csv-!eG&J?4cYqF8*1fU_r)7dII)5k0XL>ga}SHet`b> zWTeq)EI0M+vtN}FELGZWBBM0!=Hez!%SPAqo%b--tdU|%yUWy2bJmmG*4XgjO0b6X zG<$MM)95tILhkEYI9i|zX|bO8v!BNY`h!#u6;d0BBs~;wkU$EH(AzugVA(e&S~Rf4eVZL7YXi zhevVMEOp`Q%6t}PBeTDxF*9}H8%r9)Y-IL>#+Ee;jEnBhSP*AXuQZS>tcmzWIhVID zl{8zrn#B{kH2pXunZkwAxOAfR!mr;mdlj=x$hxGEw;mbu zJ@nV?U@=j<55hn)x30{PW`UJE4KNQnsaON7iR}sD4#8eIP~s^0ho)&C(R`OH|_5FSvJjFAS~N$9pglw z`U64+v^UF&bVtW232Kzr<7m*^GGJ}?K3i`DF18?)8ai^WkY zb`9-{y_OTzoHcaDK(^MEgQp0_KAL@^5C1S5SUUl1YZk@3?)tWDX|~uNu7bNbV^i)l z+-J&(8St|4V>qQJR*o=l8Q0%4^**(l(Ib?w$K+wi;>SAIF)@;$Am(7?pbr+9k1e%X-i=RqMyKLNz;E<4S7q8if6HQq_eOmqmYK zo(z)AR;U@bPB6ztfCYDI?m(=c?+VrI{>Pb`;ruM~0IbVbwrt~HJTUGZ3r<{_wuYLq zPCv8O@!qqq%1LjCq~Z+v4e3NF&9TiGc^Rx|CdMfD^Q+8( zn9xJl1@C=T1FWd7J7<6a5(x#Ysv8K@jHj44#RW~(p(l|$K4F?sQd2GEoL4o^9a}Om zFlnJHAE#J7=zlNj#*jtkhijRd6-60^T-|SE?cl&l@UvO$&{tVGUa9LosG*swPnDq` ze2xi5nuUU$Vct464cEO|3L)|Gpj8{0nt8}BRAC25L6S#CJup2?Niw4soofxoj9zdT zh6V%XrCB{QdO;+W1`HM%$%=L~(P)MenofUQ*Nnqflvpl0W+sa}`<%E;GxFxTU|D(2 z6w8cNGqDp1g;#%GSF^;7=yfJBTcZ}6bk~u(VExodl}|G>CM}N&bIy=TO2OUEUCL#o zcqUk8^pstw#sZ_kUiCx~Uq&>q%3Q&*E11!!a)R>7vPS(BKI%o>q~rBC~4TjereoHtOgcnH=oG6(k2_BvqNUXc)Z`_L-Zb5}i|!C{~Ssjwr> z8YY{Ha`YziHl!AlHCje;6T@&}BtE*Rju|uZ`zKhPT3?NZY~A$iIg)fi?s(yn*9^{b z_^VR6m8>60=$UQ?nz7PQ?gCykx@A_DP6IFmNVa=bDw8R=fG@kTNckK!kiSY=X!=>z zBx%}F?1^hva5R%XY84Ir-EIz8$%x*A&o(3XjQx{bpONsgMNJR1bjQ1FYb~T8v*?=2 zM*O&mW5%ft{Zc#iGOMC=)9)P3tm%qoj9iTv-_HSaNpzH59vchBv2H6AI5N23tV=}N zK9}TFawD&E0we$+jokjC23TRqn_7scK`eiIZZMcRn~2XTz%)ffCl?Ar;mS5KN;AkH zvi|+@XfT)&5Py1@)Pfyh{bWZEU<%9_>jWmkTia3d3ZFeYHp&($hXvD&QFbzuz$uV5 zpDnoM?Qk#yqay@jA}gx@{)yA!VEv_5)Zh%ntqA(usv|yv%bKFuq?|b7+loTJE%46L zr)Ms4&9cokDT%>D_XO${#3*ceS~+w6Ej_0iCqQx{{F7`jnZg)0y!M%PSgI_|PHvx! z(rIsAdDl!TzINY$LO&k8WFkDzoo8OxHzrF-v!j=AfNk1YL$esbfF=WmO0^=zj_hE9 zMJXYXG6}OYpRrj@k^cM)zoIcfDuYPGKX6SAFt_Lg#B#jzGkbJ)k73bxk)kK(PhE5A zBQ-S3V)ak4N09!ai#4Vbm^95dk)k`gYZ=+x!W`Hkw4h%Q?<=l0;Vb!JlyZV8wd&KArzbBFi8$ePL=ec z-_)|7E8c)+I&x9n#l&&#V04URg;^ZE-#@}JV@8C3!URZ!1DbS@gV9r?LLCQFl!5vQ z?LBWbv(c554V?S_B*5&F*~MgCA<>XxPSKs&_WnBGYL?BvC@JGJ1=$W)=%NU9iayEa z6lLI`gx)53{ToCc*CV7EN3-G%4d}^DBh?Jc zxQbhN>++MA+*1?AE~&<6t>c~g`Vjs%S6{vMJ|wAVtd^wvaSxB$XzW)rT^^aGQ97%~ zqokVV>je)SIw*pqLUdU1OZBZ|3{*+Xrai=JLP~(j2$-Px%yj~nscjScgxV)sBvg)K znWY(pi<)GhPLyJhPSMGT;WKkdIJKmW1*VjW^AhHj0|3)2z$C9fCp$`t#s*aEDCj{D z#E7S{(dBCKP>+$=C$w%4X{NC0Mmd-Wb;wM#MDH}o^k77j8mbxWOJq=POvmZ#vcZ~( zW1@i<5IYGYBwj5N7Bex7Vdl*OSlIHrA%-H^SpcbH9UBJpmBh4=@E7BNyY zIk11}5Awn^8;03h)INz#GsBkAttM$5lr;)sZ`egXi?B7ZxtNqsqZ2}%Xp145))hJ^ zZcPw_TNiIZLKM+G49$?p6#a4=fd!EiZM6-9K)X3A)V4dpNPr;+2)jhIfbN(ef{4k< uJwcBgYJDY2987}_EO9Orj*E<8siMTDg;64=*5=7HeXC5#=;#_SRPrB$Z3r^} diff --git a/impl1/s1_impl1.dir/5_1.dly b/impl1/s1_impl1.dir/5_1.dly deleted file mode 100644 index cd0d94a..0000000 --- a/impl1/s1_impl1.dir/5_1.dly +++ /dev/null @@ -1,8546 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:19:35 2021 - -File: s1_impl1.dir/5_1.dly - - The 20 worst nets by delay are: ---------------------------------- -| Max Delay | Netname | ---------------------------------- - 4.3 fifo_rden_c - 3.7 trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - 3.4 reset_dl[2] - 3.3 FEE_DATA_OUT_c[16] - 3.3 hades_dbg2_coarse_c[7] - 3.2 FEE_DATA_OUT_c[18] - 3.2 FEE_DATA_OUT_c[5] - 3.1 FEE_DATA_OUT_c[7] - 3.1 FEE_DATA_OUT_c[6] - 3.0 FEE_DATA_OUT_c[20] - 3.0 hades_dbg2_coarse_c[4] - 2.9 FEE_DATA_OUT_c[17] - 2.9 FEE_DATA_OUT_c[28] - 2.9 FEE_DATA_OUT_c[1] - 2.9 hades_dbg2_coarse_c[5] - 2.9 FEE_DATA_OUT_c[4] - 2.9 FEE_DATA_OUT_c[2] - 2.8 FEE_DATA_OUT_c[13] - 2.8 FEE_DATA_OUT_c[22] - 2.8 FEE_DATA_OUT_c[25] ---------------------------------- - -------------------------------------------------------------------------------- - Net Delays -------------------------------------------------------------------------------- - -ANB0 - hades_tdc_bundle_inst/hit_out_i_RNO[0].Q0 - 0.2 hades_tdc_bundle_inst/hit_out_i_RNO[0].D0 - 0.5 hades_tdc_bundle_inst/hit_out_i_RNO[0].B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C1 - 0.9 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].M0 - 0.3 hades_tdc_bundle_inst/buf_finished5_0_a2_0.D0 - 1.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.C0 - 0.3 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D0 - 1.5 hades_hit_out_i_pad[0].PADDO - -ANB1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q0 - 0.6 hades_tdc_bundle_inst/hit_out_i_RNO[0].D1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.D1 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].C0 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A1 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.C0 - 0.3 hades_tdc_bundle_inst/buf_finished5_0_a2_0.D1 - 1.3 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.A0 - 0.5 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C1 - 0.5 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.C1 - 1.3 hades_hit_out_i_pad[1].PADDO - -ANB2 - hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].Q0 - 0.9 hades_tdc_bundle_inst/hit_out_i_RNO[0].C1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B1 - 0.6 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B0 - 0.6 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B1 - 1.2 hades_tdc_bundle_inst/buf_finished5_0_a2_0.A0 - 0.9 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.B0 - 1.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B0 - 1.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B1 - 1.5 hades_hit_out_i_pad[2].PADDO - -ANB3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q1 - 0.7 hades_tdc_bundle_inst/hit_out_i_RNO[0].A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.A1 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A0 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.B0 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.B1 - 0.8 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.D0 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A1 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A1 - 1.7 hades_hit_out_i_pad[3].PADDO - -FEE_DATAFINISHED_OUT_c - trb_adapter_inst_FEE_DATAFINISHED_OUTio.IOLDO - 0.0 FEE_DATAFINISHED_OUT_pad.IOLDO - -FEE_DATA_OUT_c[0] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA0 - 2.5 fifo_data_out_pad[0].PADDO - 2.8 FEE_DATA_OUT_pad[0].PADDO - -FEE_DATA_OUT_c[10] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA10 - 2.1 FEE_DATA_OUT_pad[10].PADDO - 2.1 fifo_data_out_pad[10].PADDO - -FEE_DATA_OUT_c[11] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA11 - 2.5 FEE_DATA_OUT_pad[11].PADDO - 2.5 fifo_data_out_pad[11].PADDO - -FEE_DATA_OUT_c[12] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA12 - 2.4 FEE_DATA_OUT_pad[12].PADDO - 2.6 fifo_data_out_pad[12].PADDO - -FEE_DATA_OUT_c[13] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA13 - 2.8 FEE_DATA_OUT_pad[13].PADDO - 2.8 fifo_data_out_pad[13].PADDO - -FEE_DATA_OUT_c[14] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA14 - 2.6 FEE_DATA_OUT_pad[14].PADDO - 2.8 fifo_data_out_pad[14].PADDO - -FEE_DATA_OUT_c[15] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA15 - 2.5 FEE_DATA_OUT_pad[15].PADDO - 2.1 fifo_data_out_pad[15].PADDO - -FEE_DATA_OUT_c[16] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA16 - 3.2 FEE_DATA_OUT_pad[16].PADDO - 3.3 fifo_data_out_pad[16].PADDO - -FEE_DATA_OUT_c[17] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA17 - 2.8 FEE_DATA_OUT_pad[17].PADDO - 2.9 fifo_data_out_pad[17].PADDO - -FEE_DATA_OUT_c[18] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB0 - 2.8 FEE_DATA_OUT_pad[18].PADDO - 3.2 fifo_data_out_pad[18].PADDO - -FEE_DATA_OUT_c[19] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB1 - 2.2 FEE_DATA_OUT_pad[19].PADDO - 2.2 fifo_data_out_pad[19].PADDO - -FEE_DATA_OUT_c[1] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA1 - 2.9 FEE_DATA_OUT_pad[1].PADDO - 2.9 fifo_data_out_pad[1].PADDO - -FEE_DATA_OUT_c[20] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB2 - 2.8 FEE_DATA_OUT_pad[20].PADDO - 3.0 fifo_data_out_pad[20].PADDO - -FEE_DATA_OUT_c[21] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB3 - 2.4 FEE_DATA_OUT_pad[21].PADDO - 2.3 fifo_data_out_pad[21].PADDO - -FEE_DATA_OUT_c[22] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB4 - 2.7 FEE_DATA_OUT_pad[22].PADDO - 2.8 fifo_data_out_pad[22].PADDO - -FEE_DATA_OUT_c[23] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB5 - 2.4 FEE_DATA_OUT_pad[23].PADDO - 2.4 fifo_data_out_pad[23].PADDO - -FEE_DATA_OUT_c[24] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB6 - 2.4 FEE_DATA_OUT_pad[24].PADDO - 2.7 fifo_data_out_pad[24].PADDO - -FEE_DATA_OUT_c[25] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB7 - 2.8 FEE_DATA_OUT_pad[25].PADDO - 2.8 fifo_data_out_pad[25].PADDO - -FEE_DATA_OUT_c[26] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB8 - 2.7 FEE_DATA_OUT_pad[26].PADDO - 2.8 fifo_data_out_pad[26].PADDO - -FEE_DATA_OUT_c[27] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB9 - 2.8 FEE_DATA_OUT_pad[27].PADDO - 2.8 fifo_data_out_pad[27].PADDO - -FEE_DATA_OUT_c[28] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB10 - 2.8 FEE_DATA_OUT_pad[28].PADDO - 2.9 fifo_data_out_pad[28].PADDO - -FEE_DATA_OUT_c[29] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB11 - 2.7 FEE_DATA_OUT_pad[29].PADDO - 2.7 fifo_data_out_pad[29].PADDO - -FEE_DATA_OUT_c[2] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA2 - 2.9 FEE_DATA_OUT_pad[2].PADDO - 2.9 fifo_data_out_pad[2].PADDO - -FEE_DATA_OUT_c[30] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB12 - 2.6 FEE_DATA_OUT_pad[30].PADDO - 2.6 fifo_data_out_pad[30].PADDO - -FEE_DATA_OUT_c[31] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB13 - 2.6 FEE_DATA_OUT_pad[31].PADDO - 2.8 fifo_data_out_pad[31].PADDO - -FEE_DATA_OUT_c[3] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA3 - 2.5 FEE_DATA_OUT_pad[3].PADDO - 2.5 fifo_data_out_pad[3].PADDO - -FEE_DATA_OUT_c[4] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA4 - 2.9 FEE_DATA_OUT_pad[4].PADDO - 2.9 fifo_data_out_pad[4].PADDO - -FEE_DATA_OUT_c[5] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA5 - 3.0 FEE_DATA_OUT_pad[5].PADDO - 3.2 fifo_data_out_pad[5].PADDO - -FEE_DATA_OUT_c[6] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA6 - 2.9 FEE_DATA_OUT_pad[6].PADDO - 3.1 fifo_data_out_pad[6].PADDO - -FEE_DATA_OUT_c[7] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA7 - 2.9 FEE_DATA_OUT_pad[7].PADDO - 3.1 fifo_data_out_pad[7].PADDO - -FEE_DATA_OUT_c[8] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA8 - 2.5 FEE_DATA_OUT_pad[8].PADDO - 2.5 fifo_data_out_pad[8].PADDO - -FEE_DATA_OUT_c[9] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA9 - 2.4 FEE_DATA_OUT_pad[9].PADDO - 2.6 fifo_data_out_pad[9].PADDO - -FEE_DATA_WRITE_OUT_c - trb_adapter_inst_FEE_DATA_WRITE_OUTio.IOLDO - 0.0 FEE_DATA_WRITE_OUT_pad.IOLDO - -FEE_TRG_RELEASE_OUT_c - trb_adapter_inst_FEE_TRG_RELEASE_OUTio.IOLDO - 0.0 FEE_TRG_RELEASE_OUT_pad.IOLDO - -LVL1_INVALID_TRG_IN_c - LVL1_INVALID_TRG_IN_pad.PADDI - 0.0 trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].DI - -LVL1_TRG_DATA_VALID_IN_c - LVL1_TRG_DATA_VALID_IN_pad.PADDI - 0.0 trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].DI - -LVL1_TRG_DATA_VALI_IN_rising_c - trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F0 - 0.6 LVL1_TRG_DATA_VALI_IN_rising_pad.PADDO - -N_248_i - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.OFX0 - 0.4 hades_tdc_bundle_inst_buf_out_validio.CE - -burst_c - trb_adapter_inst/burst.F1 - 0.4 trb_adapter_inst/burst.B0 - 0.4 burst_pad.PADDO - -clk_c - clk_pad.PADDI - 0.1 pll0inst/PLLInst_0.CLKI - -discard_c - trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].Q0 - 0.8 trb_adapter_inst/burst.C1 - 0.4 discard_pad.PADDO - -fifo_colector_inst/buffer_wr_enable - fifo_colector_inst/in_empty_pmux_0_RNIDRET.Q0 - 0.9 fifo_colector_inst/fifo40_inst/AND2_t20.B0 - -fifo_colector_inst/data_buffer[0] - fifo_colector_inst/data_buffer_3[0].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA0 - -fifo_colector_inst/data_buffer[10] - fifo_colector_inst/data_buffer_3_0[11].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA10 - -fifo_colector_inst/data_buffer[11] - fifo_colector_inst/data_buffer_3_0[11].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA11 - -fifo_colector_inst/data_buffer[12] - fifo_colector_inst/data_buffer_3_0[13].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA12 - -fifo_colector_inst/data_buffer[13] - fifo_colector_inst/data_buffer_3_0[13].Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA13 - -fifo_colector_inst/data_buffer[14] - fifo_colector_inst/data_buffer_3_0[15].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA14 - -fifo_colector_inst/data_buffer[15] - fifo_colector_inst/data_buffer_3_0[15].Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA15 - -fifo_colector_inst/data_buffer[16] - fifo_colector_inst/data_buffer_3_0[17].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA16 - -fifo_colector_inst/data_buffer[17] - fifo_colector_inst/data_buffer_3_0[17].Q1 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA17 - -fifo_colector_inst/data_buffer[18] - fifo_colector_inst/data_buffer_3_0[19].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB0 - -fifo_colector_inst/data_buffer[19] - fifo_colector_inst/data_buffer_3_0[19].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB1 - -fifo_colector_inst/data_buffer[1] - fifo_colector_inst/data_buffer_3[1].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA1 - -fifo_colector_inst/data_buffer[20] - fifo_colector_inst/data_buffer_3_0[21].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB2 - -fifo_colector_inst/data_buffer[21] - fifo_colector_inst/data_buffer_3_0[21].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB3 - -fifo_colector_inst/data_buffer[22] - fifo_colector_inst/data_buffer_3_0[23].Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB4 - -fifo_colector_inst/data_buffer[23] - fifo_colector_inst/data_buffer_3_0[23].Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB5 - -fifo_colector_inst/data_buffer[24] - fifo_colector_inst/data_buffer_3_0[25].Q0 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB6 - -fifo_colector_inst/data_buffer[25] - fifo_colector_inst/data_buffer_3_0[25].Q1 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB7 - -fifo_colector_inst/data_buffer[26] - fifo_colector_inst/data_buffer_3_0[27].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB8 - -fifo_colector_inst/data_buffer[27] - fifo_colector_inst/data_buffer_3_0[27].Q1 - 1.0 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB9 - -fifo_colector_inst/data_buffer[28] - fifo_colector_inst/data_buffer_3_0[29].Q0 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB10 - -fifo_colector_inst/data_buffer[29] - fifo_colector_inst/data_buffer_3_0[29].Q1 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB11 - -fifo_colector_inst/data_buffer[2] - fifo_colector_inst/data_buffer_3[2].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA2 - -fifo_colector_inst/data_buffer[30] - fifo_colector_inst/data_buffer_3_0[31].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB12 - -fifo_colector_inst/data_buffer[31] - fifo_colector_inst/data_buffer_3_0[31].Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB13 - -fifo_colector_inst/data_buffer[32] - fifo_colector_inst/data_buffer[33].Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB14 - -fifo_colector_inst/data_buffer[33] - fifo_colector_inst/data_buffer[33].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB15 - -fifo_colector_inst/data_buffer[3] - fifo_colector_inst/data_buffer_3[3].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA3 - -fifo_colector_inst/data_buffer[4] - fifo_colector_inst/data_buffer_3[4].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA4 - -fifo_colector_inst/data_buffer[5] - fifo_colector_inst/data_buffer_3[5].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA5 - -fifo_colector_inst/data_buffer[6] - fifo_colector_inst/data_buffer_3[6].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA6 - -fifo_colector_inst/data_buffer[7] - fifo_colector_inst/data_buffer_3[7].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA7 - -fifo_colector_inst/data_buffer[8] - fifo_colector_inst/data_buffer_3_0[9].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA8 - -fifo_colector_inst/data_buffer[9] - fifo_colector_inst/data_buffer_3_0[9].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA9 - -fifo_colector_inst/data_buffer_3[0] - fifo_colector_inst/data_buffer_3[0].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[0].DI0 - -fifo_colector_inst/data_buffer_3[10] - fifo_colector_inst/data_buffer_3_0[11].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[11].DI0 - -fifo_colector_inst/data_buffer_3[11] - fifo_colector_inst/data_buffer_3_0[11].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[11].DI1 - -fifo_colector_inst/data_buffer_3[12] - fifo_colector_inst/data_buffer_3_0[13].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[13].DI0 - -fifo_colector_inst/data_buffer_3[13] - fifo_colector_inst/data_buffer_3_0[13].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[13].DI1 - -fifo_colector_inst/data_buffer_3[14] - fifo_colector_inst/data_buffer_3_0[15].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[15].DI0 - -fifo_colector_inst/data_buffer_3[15] - fifo_colector_inst/data_buffer_3_0[15].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[15].DI1 - -fifo_colector_inst/data_buffer_3[16] - fifo_colector_inst/data_buffer_3_0[17].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[17].DI0 - -fifo_colector_inst/data_buffer_3[17] - fifo_colector_inst/data_buffer_3_0[17].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[17].DI1 - -fifo_colector_inst/data_buffer_3[18] - fifo_colector_inst/data_buffer_3_0[19].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[19].DI0 - -fifo_colector_inst/data_buffer_3[19] - fifo_colector_inst/data_buffer_3_0[19].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[19].DI1 - -fifo_colector_inst/data_buffer_3[1] - fifo_colector_inst/data_buffer_3[1].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[1].DI0 - -fifo_colector_inst/data_buffer_3[20] - fifo_colector_inst/data_buffer_3_0[21].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[21].DI0 - -fifo_colector_inst/data_buffer_3[21] - fifo_colector_inst/data_buffer_3_0[21].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[21].DI1 - -fifo_colector_inst/data_buffer_3[22] - fifo_colector_inst/data_buffer_3_0[23].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[23].DI0 - -fifo_colector_inst/data_buffer_3[23] - fifo_colector_inst/data_buffer_3_0[23].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[23].DI1 - -fifo_colector_inst/data_buffer_3[24] - fifo_colector_inst/data_buffer_3_0[25].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[25].DI0 - -fifo_colector_inst/data_buffer_3[25] - fifo_colector_inst/data_buffer_3_0[25].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[25].DI1 - -fifo_colector_inst/data_buffer_3[26] - fifo_colector_inst/data_buffer_3_0[27].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[27].DI0 - -fifo_colector_inst/data_buffer_3[27] - fifo_colector_inst/data_buffer_3_0[27].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[27].DI1 - -fifo_colector_inst/data_buffer_3[28] - fifo_colector_inst/data_buffer_3_0[29].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[29].DI0 - -fifo_colector_inst/data_buffer_3[29] - fifo_colector_inst/data_buffer_3_0[29].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[29].DI1 - -fifo_colector_inst/data_buffer_3[2] - fifo_colector_inst/data_buffer_3[2].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[2].DI0 - -fifo_colector_inst/data_buffer_3[30] - fifo_colector_inst/data_buffer_3_0[31].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[31].DI0 - -fifo_colector_inst/data_buffer_3[31] - fifo_colector_inst/data_buffer_3_0[31].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[31].DI1 - -fifo_colector_inst/data_buffer_3[3] - fifo_colector_inst/data_buffer_3[3].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[3].DI0 - -fifo_colector_inst/data_buffer_3[4] - fifo_colector_inst/data_buffer_3[4].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[4].DI0 - -fifo_colector_inst/data_buffer_3[5] - fifo_colector_inst/data_buffer_3[5].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[5].DI0 - -fifo_colector_inst/data_buffer_3[6] - fifo_colector_inst/data_buffer_3[6].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[6].DI0 - -fifo_colector_inst/data_buffer_3[7] - fifo_colector_inst/data_buffer_3[7].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[7].DI0 - -fifo_colector_inst/data_buffer_3[8] - fifo_colector_inst/data_buffer_3_0[9].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[9].DI0 - -fifo_colector_inst/data_buffer_3[9] - fifo_colector_inst/data_buffer_3_0[9].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[9].DI1 - -fifo_colector_inst/fb_0 - fifo_colector_inst/in_read_enable_1_.fb.F0 - 0.0 fifo_colector_inst/in_read_enable_1_.fb.DI0 - -fifo_colector_inst/fb_0_0 - fifo_colector_inst/in_read_enable_2_.fb.F0 - 0.0 fifo_colector_inst/in_read_enable_2_.fb.DI0 - -fifo_colector_inst/fb_0_1 - fifo_colector_inst/in_read_enable_1_.fb.F1 - 0.0 fifo_colector_inst/in_read_enable_1_.fb.DI1 - -fifo_colector_inst/fifo40_inst/Full - fifo_colector_inst/fifo40_inst/FF_0.Q0 - 0.4 fifo_colector_inst/fifo40_inst/AND2_t20.C0 - -fifo_colector_inst/fifo40_inst/cmp_ci - fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_0.FCI - -fifo_colector_inst/fifo40_inst/cmp_ci_1 - fifo_colector_inst/fifo40_inst/full_cmp_ci_a.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_0.FCI - -fifo_colector_inst/fifo40_inst/co0 - fifo_colector_inst/fifo40_inst/FF_100.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_98.FCI - -fifo_colector_inst/fifo40_inst/co0_1 - fifo_colector_inst/fifo40_inst/FF_70.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_68.FCI - -fifo_colector_inst/fifo40_inst/co0_2 - fifo_colector_inst/fifo40_inst/empty_cmp_0.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_1.FCI - -fifo_colector_inst/fifo40_inst/co0_3 - fifo_colector_inst/fifo40_inst/full_cmp_0.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_1.FCI - -fifo_colector_inst/fifo40_inst/co1 - fifo_colector_inst/fifo40_inst/FF_98.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_96.FCI - -fifo_colector_inst/fifo40_inst/co1_1 - fifo_colector_inst/fifo40_inst/FF_68.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_66.FCI - -fifo_colector_inst/fifo40_inst/co1_2 - fifo_colector_inst/fifo40_inst/empty_cmp_1.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_2.FCI - -fifo_colector_inst/fifo40_inst/co1_3 - fifo_colector_inst/fifo40_inst/full_cmp_1.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_2.FCI - -fifo_colector_inst/fifo40_inst/co2 - fifo_colector_inst/fifo40_inst/FF_96.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_94.FCI - -fifo_colector_inst/fifo40_inst/co2_1 - fifo_colector_inst/fifo40_inst/FF_66.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_64.FCI - -fifo_colector_inst/fifo40_inst/co2_2 - fifo_colector_inst/fifo40_inst/empty_cmp_2.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_3.FCI - -fifo_colector_inst/fifo40_inst/co2_3 - fifo_colector_inst/fifo40_inst/full_cmp_2.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_3.FCI - -fifo_colector_inst/fifo40_inst/co3 - fifo_colector_inst/fifo40_inst/FF_94.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_92.FCI - -fifo_colector_inst/fifo40_inst/co3_1 - fifo_colector_inst/fifo40_inst/FF_64.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_62.FCI - -fifo_colector_inst/fifo40_inst/co3_2 - fifo_colector_inst/fifo40_inst/empty_cmp_3.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_4.FCI - -fifo_colector_inst/fifo40_inst/co3_3 - fifo_colector_inst/fifo40_inst/full_cmp_3.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_4.FCI - -fifo_colector_inst/fifo40_inst/empty_cmp_clr - fifo_colector_inst/fifo40_inst/LUT4_2.F1 - 0.4 fifo_colector_inst/fifo40_inst/empty_cmp_4.A1 - -fifo_colector_inst/fifo40_inst/empty_cmp_set - fifo_colector_inst/fifo40_inst/LUT4_2.F0 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_4.B1 - -fifo_colector_inst/fifo40_inst/empty_d - fifo_colector_inst/fifo40_inst/FF_1.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_1.DI0 - -fifo_colector_inst/fifo40_inst/empty_d_c - fifo_colector_inst/fifo40_inst/empty_cmp_4.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_1.FCI - -fifo_colector_inst/fifo40_inst/full_cmp_clr - fifo_colector_inst/fifo40_inst/LUT4_1.F0 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_4.B1 - -fifo_colector_inst/fifo40_inst/full_cmp_set - fifo_colector_inst/fifo40_inst/LUT4_1.F1 - 0.4 fifo_colector_inst/fifo40_inst/full_cmp_4.A1 - -fifo_colector_inst/fifo40_inst/full_d - fifo_colector_inst/fifo40_inst/FF_0.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_0.DI0 - -fifo_colector_inst/fifo40_inst/full_d_c - fifo_colector_inst/fifo40_inst/full_cmp_4.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_0.FCI - -fifo_colector_inst/fifo40_inst/ircount_0 - fifo_colector_inst/fifo40_inst/FF_70.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_70.DI0 - -fifo_colector_inst/fifo40_inst/ircount_1 - fifo_colector_inst/fifo40_inst/FF_70.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_70.DI1 - -fifo_colector_inst/fifo40_inst/ircount_2 - fifo_colector_inst/fifo40_inst/FF_68.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_68.DI0 - -fifo_colector_inst/fifo40_inst/ircount_3 - fifo_colector_inst/fifo40_inst/FF_68.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_68.DI1 - -fifo_colector_inst/fifo40_inst/ircount_4 - fifo_colector_inst/fifo40_inst/FF_66.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_66.DI0 - -fifo_colector_inst/fifo40_inst/ircount_5 - fifo_colector_inst/fifo40_inst/FF_66.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_66.DI1 - -fifo_colector_inst/fifo40_inst/ircount_6 - fifo_colector_inst/fifo40_inst/FF_64.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_64.DI0 - -fifo_colector_inst/fifo40_inst/ircount_7 - fifo_colector_inst/fifo40_inst/FF_64.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_64.DI1 - -fifo_colector_inst/fifo40_inst/ircount_8 - fifo_colector_inst/fifo40_inst/FF_62.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_62.DI0 - -fifo_colector_inst/fifo40_inst/ircount_9 - fifo_colector_inst/fifo40_inst/FF_62.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_62.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_0 - fifo_colector_inst/fifo40_inst/FF_100.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_100.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_1 - fifo_colector_inst/fifo40_inst/FF_100.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_100.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_2 - fifo_colector_inst/fifo40_inst/FF_98.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_98.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_3 - fifo_colector_inst/fifo40_inst/FF_98.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_98.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_4 - fifo_colector_inst/fifo40_inst/FF_96.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_96.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_5 - fifo_colector_inst/fifo40_inst/FF_96.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_96.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_6 - fifo_colector_inst/fifo40_inst/FF_94.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_94.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_7 - fifo_colector_inst/fifo40_inst/FF_94.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_94.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_8 - fifo_colector_inst/fifo40_inst/FF_92.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_92.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_9 - fifo_colector_inst/fifo40_inst/FF_92.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_92.DI1 - -fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - fifo_colector_inst/fifo40_inst/LUT4_4.F0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_4.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_5.D1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.B0 - -fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - fifo_colector_inst/fifo40_inst/LUT4_5.F0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.M0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_4.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_5.C1 - -fifo_colector_inst/fifo40_inst/r_gcount_0 - fifo_colector_inst/fifo40_inst/XOR2_t7.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_30.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_1 - fifo_colector_inst/fifo40_inst/XOR2_t7.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_30.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_2 - fifo_colector_inst/fifo40_inst/XOR2_t5.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_28.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_3 - fifo_colector_inst/fifo40_inst/XOR2_t5.Q1 - 0.5 fifo_colector_inst/fifo40_inst/FF_28.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_4 - fifo_colector_inst/fifo40_inst/XOR2_t3.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_26.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_5 - fifo_colector_inst/fifo40_inst/XOR2_t3.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_26.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_6 - fifo_colector_inst/fifo40_inst/XOR2_t1.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_24.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_7 - fifo_colector_inst/fifo40_inst/XOR2_t1.Q1 - 0.5 fifo_colector_inst/fifo40_inst/FF_24.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_8 - fifo_colector_inst/fifo40_inst/XOR2_t0.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_22.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_9 - fifo_colector_inst/fifo40_inst/XOR2_t0.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_22.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w0 - fifo_colector_inst/fifo40_inst/FF_30.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_10.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w1 - fifo_colector_inst/fifo40_inst/FF_30.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_10.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w2 - fifo_colector_inst/fifo40_inst/FF_28.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_8.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w20 - fifo_colector_inst/fifo40_inst/FF_10.Q0 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_4.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w21 - fifo_colector_inst/fifo40_inst/FF_10.Q1 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_4.A1 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_5.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w22 - fifo_colector_inst/fifo40_inst/FF_8.Q0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_5.B0 - -fifo_colector_inst/fifo40_inst/r_gcount_w23 - fifo_colector_inst/fifo40_inst/FF_8.Q1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_5.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_11.D0 - -fifo_colector_inst/fifo40_inst/r_gcount_w24 - fifo_colector_inst/fifo40_inst/FF_6.Q0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_5.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_8.C1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_11.C0 - -fifo_colector_inst/fifo40_inst/r_gcount_w25 - fifo_colector_inst/fifo40_inst/FF_6.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.M0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_5.A0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_8.A1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.A0 - -fifo_colector_inst/fifo40_inst/r_gcount_w26 - fifo_colector_inst/fifo40_inst/FF_4.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.D1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_9.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_9.D1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_4.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_8.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w27 - fifo_colector_inst/fifo40_inst/FF_4.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.C1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.C0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_9.A1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_4.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_8.C0 - -fifo_colector_inst/fifo40_inst/r_gcount_w28 - fifo_colector_inst/fifo40_inst/FF_2.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_6.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_6.A1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_9.A0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_4.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_8.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_11.D1 - -fifo_colector_inst/fifo40_inst/r_gcount_w29 - fifo_colector_inst/fifo40_inst/FF_2.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_4.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_8.B0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_1.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_1.A1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w3 - fifo_colector_inst/fifo40_inst/FF_28.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_8.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w4 - fifo_colector_inst/fifo40_inst/FF_26.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_6.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w5 - fifo_colector_inst/fifo40_inst/FF_26.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_6.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w6 - fifo_colector_inst/fifo40_inst/FF_24.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_4.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w7 - fifo_colector_inst/fifo40_inst/FF_24.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_4.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w8 - fifo_colector_inst/fifo40_inst/FF_22.Q0 - 0.8 fifo_colector_inst/fifo40_inst/FF_2.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w9 - fifo_colector_inst/fifo40_inst/FF_22.Q1 - 0.8 fifo_colector_inst/fifo40_inst/FF_2.M1 - -fifo_colector_inst/fifo40_inst/r_gctr_ci - fifo_colector_inst/fifo40_inst/r_gctr_cia.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_70.FCI - -fifo_colector_inst/fifo40_inst/r_gdata_0 - fifo_colector_inst/fifo40_inst/XOR2_t7.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t7.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_1 - fifo_colector_inst/fifo40_inst/XOR2_t7.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t7.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_2 - fifo_colector_inst/fifo40_inst/XOR2_t5.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t5.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_3 - fifo_colector_inst/fifo40_inst/XOR2_t5.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t5.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_4 - fifo_colector_inst/fifo40_inst/XOR2_t3.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t3.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_5 - fifo_colector_inst/fifo40_inst/XOR2_t3.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t3.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_6 - fifo_colector_inst/fifo40_inst/XOR2_t1.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t1.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_7 - fifo_colector_inst/fifo40_inst/XOR2_t1.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t1.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_8 - fifo_colector_inst/fifo40_inst/XOR2_t0.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t0.DI0 - -fifo_colector_inst/fifo40_inst/rcount_0 - fifo_colector_inst/fifo40_inst/FF_70.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_70.A0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_0.B0 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.D0 - 1.5 fifo_colector_inst/fifo40_inst/FF_50.M0 - -fifo_colector_inst/fifo40_inst/rcount_1 - fifo_colector_inst/fifo40_inst/FF_70.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_70.B1 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_0.B1 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.C0 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.C1 - 1.3 fifo_colector_inst/fifo40_inst/FF_50.M1 - -fifo_colector_inst/fifo40_inst/rcount_2 - fifo_colector_inst/fifo40_inst/FF_68.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_68.B0 - 1.1 fifo_colector_inst/fifo40_inst/empty_cmp_1.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t7.A1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t5.B0 - 0.8 fifo_colector_inst/fifo40_inst/FF_48.M0 - -fifo_colector_inst/fifo40_inst/rcount_3 - fifo_colector_inst/fifo40_inst/FF_68.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_68.A1 - 1.0 fifo_colector_inst/fifo40_inst/empty_cmp_1.B1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t5.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t5.A1 - 1.4 fifo_colector_inst/fifo40_inst/FF_48.M1 - -fifo_colector_inst/fifo40_inst/rcount_4 - fifo_colector_inst/fifo40_inst/FF_66.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_66.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_2.A0 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t5.D1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t3.D0 - 0.5 fifo_colector_inst/fifo40_inst/FF_46.M0 - -fifo_colector_inst/fifo40_inst/rcount_5 - fifo_colector_inst/fifo40_inst/FF_66.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_66.A1 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_2.A1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t3.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t3.A1 - 0.8 fifo_colector_inst/fifo40_inst/FF_46.M1 - -fifo_colector_inst/fifo40_inst/rcount_6 - fifo_colector_inst/fifo40_inst/FF_64.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_64.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_3.B0 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t3.C1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t1.C0 - 0.6 fifo_colector_inst/fifo40_inst/FF_44.M0 - -fifo_colector_inst/fifo40_inst/rcount_7 - fifo_colector_inst/fifo40_inst/FF_64.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_64.B1 - 1.1 fifo_colector_inst/fifo40_inst/empty_cmp_3.B1 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t1.D0 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t1.D1 - 0.5 fifo_colector_inst/fifo40_inst/FF_44.M1 - -fifo_colector_inst/fifo40_inst/rcount_8 - fifo_colector_inst/fifo40_inst/FF_62.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_62.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_4.B0 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t1.C1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t0.B0 - 0.9 fifo_colector_inst/fifo40_inst/FF_42.M0 - -fifo_colector_inst/fifo40_inst/rcount_9 - fifo_colector_inst/fifo40_inst/FF_62.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_62.B1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t0.D0 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t0.M1 - 0.7 fifo_colector_inst/fifo40_inst/FF_42.M1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_2.D0 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_2.D1 - -fifo_colector_inst/fifo40_inst/rcount_w0 - fifo_colector_inst/fifo40_inst/LUT4_4.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_0.B0 - -fifo_colector_inst/fifo40_inst/rcount_w1 - fifo_colector_inst/fifo40_inst/LUT4_5.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_0.A1 - -fifo_colector_inst/fifo40_inst/rcount_w2 - fifo_colector_inst/fifo40_inst/LUT4_6.OFX0 - 0.6 fifo_colector_inst/fifo40_inst/full_cmp_1.B0 - -fifo_colector_inst/fifo40_inst/rcount_w3 - fifo_colector_inst/fifo40_inst/LUT4_11.F0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_1.A1 - -fifo_colector_inst/fifo40_inst/rcount_w4 - fifo_colector_inst/fifo40_inst/LUT4_8.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_2.A0 - -fifo_colector_inst/fifo40_inst/rcount_w5 - fifo_colector_inst/fifo40_inst/LUT4_9.OFX0 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_2.B1 - -fifo_colector_inst/fifo40_inst/rcount_w7 - fifo_colector_inst/fifo40_inst/LUT4_8.F0 - 0.8 fifo_colector_inst/fifo40_inst/full_cmp_3.B1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_8.D1 - -fifo_colector_inst/fifo40_inst/rcount_w8 - fifo_colector_inst/fifo40_inst/LUT4_11.F1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_4.A0 - -fifo_colector_inst/fifo40_inst/rden_i - fifo_colector_inst/fifo40_inst/AND2_t19.F0 - 0.5 fifo_colector_inst/fifo40_inst/FF_70.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_68.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_66.CE - 0.4 fifo_colector_inst/fifo40_inst/FF_64.CE - 0.4 fifo_colector_inst/fifo40_inst/FF_62.CE - 1.4 fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.A1 - 1.4 fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.B1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t7.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t5.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t3.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t1.CE - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t0.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_50.CE - 1.3 fifo_colector_inst/fifo40_inst/FF_48.CE - 1.1 fifo_colector_inst/fifo40_inst/FF_46.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_44.CE - 1.0 fifo_colector_inst/fifo40_inst/FF_42.CE - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CEB - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.OCEB - -fifo_colector_inst/fifo40_inst/rptr_0 - fifo_colector_inst/fifo40_inst/FF_50.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB5 - -fifo_colector_inst/fifo40_inst/rptr_1 - fifo_colector_inst/fifo40_inst/FF_50.Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB6 - -fifo_colector_inst/fifo40_inst/rptr_2 - fifo_colector_inst/fifo40_inst/FF_48.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB7 - -fifo_colector_inst/fifo40_inst/rptr_3 - fifo_colector_inst/fifo40_inst/FF_48.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB8 - -fifo_colector_inst/fifo40_inst/rptr_4 - fifo_colector_inst/fifo40_inst/FF_46.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB9 - -fifo_colector_inst/fifo40_inst/rptr_5 - fifo_colector_inst/fifo40_inst/FF_46.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB10 - -fifo_colector_inst/fifo40_inst/rptr_6 - fifo_colector_inst/fifo40_inst/FF_44.Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB11 - -fifo_colector_inst/fifo40_inst/rptr_7 - fifo_colector_inst/fifo40_inst/FF_44.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB12 - -fifo_colector_inst/fifo40_inst/rptr_8 - fifo_colector_inst/fifo40_inst/FF_42.Q0 - 1.1 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB13 - -fifo_colector_inst/fifo40_inst/rptr_9 - fifo_colector_inst/fifo40_inst/FF_42.Q1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_2.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_2.C1 - -fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - fifo_colector_inst/fifo40_inst/LUT4_14.F0 - 0.7 fifo_colector_inst/fifo40_inst/empty_cmp_3.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_14.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_15.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_17.D0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_17.C1 - -fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - fifo_colector_inst/fifo40_inst/LUT4_15.F0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_14.B1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_15.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_17.C0 - -fifo_colector_inst/fifo40_inst/w_gcount_0 - fifo_colector_inst/fifo40_inst/XOR2_t16.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_40.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_1 - fifo_colector_inst/fifo40_inst/XOR2_t16.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_40.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_2 - fifo_colector_inst/fifo40_inst/XOR2_t14.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_38.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_3 - fifo_colector_inst/fifo40_inst/XOR2_t14.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_38.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_4 - fifo_colector_inst/fifo40_inst/XOR2_t12.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_36.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_5 - fifo_colector_inst/fifo40_inst/XOR2_t12.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_36.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_6 - fifo_colector_inst/fifo40_inst/XOR2_t10.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_34.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_7 - fifo_colector_inst/fifo40_inst/XOR2_t10.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_34.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_8 - fifo_colector_inst/fifo40_inst/XOR2_t9.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_32.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_9 - fifo_colector_inst/fifo40_inst/XOR2_t9.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_32.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r0 - fifo_colector_inst/fifo40_inst/FF_40.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_20.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r1 - fifo_colector_inst/fifo40_inst/FF_40.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_20.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r2 - fifo_colector_inst/fifo40_inst/FF_38.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_18.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r20 - fifo_colector_inst/fifo40_inst/FF_20.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_14.C1 - -fifo_colector_inst/fifo40_inst/w_gcount_r21 - fifo_colector_inst/fifo40_inst/FF_20.Q1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_14.A1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_15.B1 - -fifo_colector_inst/fifo40_inst/w_gcount_r22 - fifo_colector_inst/fifo40_inst/FF_18.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_15.D0 - -fifo_colector_inst/fifo40_inst/w_gcount_r23 - fifo_colector_inst/fifo40_inst/FF_18.Q1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_15.B0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_17.B1 - -fifo_colector_inst/fifo40_inst/w_gcount_r24 - fifo_colector_inst/fifo40_inst/FF_16.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_15.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_18.B1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_17.D1 - -fifo_colector_inst/fifo40_inst/w_gcount_r25 - fifo_colector_inst/fifo40_inst/FF_16.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_15.C0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_19.A1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_18.A1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_17.A1 - -fifo_colector_inst/fifo40_inst/w_gcount_r26 - fifo_colector_inst/fifo40_inst/FF_14.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_14.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_19.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_18.C1 - -fifo_colector_inst/fifo40_inst/w_gcount_r27 - fifo_colector_inst/fifo40_inst/FF_14.Q1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_14.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_19.C1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_18.B0 - -fifo_colector_inst/fifo40_inst/w_gcount_r28 - fifo_colector_inst/fifo40_inst/FF_12.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_14.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_19.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_18.D0 - -fifo_colector_inst/fifo40_inst/w_gcount_r29 - fifo_colector_inst/fifo40_inst/FF_12.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_14.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_19.B0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_18.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_2.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_2.A1 - -fifo_colector_inst/fifo40_inst/w_gcount_r3 - fifo_colector_inst/fifo40_inst/FF_38.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_18.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r4 - fifo_colector_inst/fifo40_inst/FF_36.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_16.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r5 - fifo_colector_inst/fifo40_inst/FF_36.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_16.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r6 - fifo_colector_inst/fifo40_inst/FF_34.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_14.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r7 - fifo_colector_inst/fifo40_inst/FF_34.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_14.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r8 - fifo_colector_inst/fifo40_inst/FF_32.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_12.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r9 - fifo_colector_inst/fifo40_inst/FF_32.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_12.M1 - -fifo_colector_inst/fifo40_inst/w_gctr_ci - fifo_colector_inst/fifo40_inst/w_gctr_cia.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_100.FCI - -fifo_colector_inst/fifo40_inst/w_gdata_0 - fifo_colector_inst/fifo40_inst/XOR2_t16.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t16.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_1 - fifo_colector_inst/fifo40_inst/XOR2_t16.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t16.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_2 - fifo_colector_inst/fifo40_inst/XOR2_t14.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t14.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_3 - fifo_colector_inst/fifo40_inst/XOR2_t14.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t14.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_4 - fifo_colector_inst/fifo40_inst/XOR2_t12.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t12.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_5 - fifo_colector_inst/fifo40_inst/XOR2_t12.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t12.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_6 - fifo_colector_inst/fifo40_inst/XOR2_t10.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t10.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_7 - fifo_colector_inst/fifo40_inst/XOR2_t10.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t10.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_8 - fifo_colector_inst/fifo40_inst/XOR2_t9.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t9.DI0 - -fifo_colector_inst/fifo40_inst/wcount_0 - fifo_colector_inst/fifo40_inst/FF_100.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_100.B0 - 1.0 fifo_colector_inst/fifo40_inst/full_cmp_0.A0 - 0.3 fifo_colector_inst/fifo40_inst/XOR2_t16.D0 - 0.6 fifo_colector_inst/fifo40_inst/FF_80.M0 - -fifo_colector_inst/fifo40_inst/wcount_1 - fifo_colector_inst/fifo40_inst/FF_100.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_100.B1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_0.B1 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t16.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t16.B1 - 0.6 fifo_colector_inst/fifo40_inst/FF_80.M1 - -fifo_colector_inst/fifo40_inst/wcount_2 - fifo_colector_inst/fifo40_inst/FF_98.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_98.A0 - 0.9 fifo_colector_inst/fifo40_inst/full_cmp_1.A0 - 0.4 fifo_colector_inst/fifo40_inst/XOR2_t16.C1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t14.C0 - 1.2 fifo_colector_inst/fifo40_inst/FF_78.M0 - -fifo_colector_inst/fifo40_inst/wcount_3 - fifo_colector_inst/fifo40_inst/FF_98.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_98.A1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_1.B1 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.D0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.D1 - 0.9 fifo_colector_inst/fifo40_inst/FF_78.M1 - -fifo_colector_inst/fifo40_inst/wcount_4 - fifo_colector_inst/fifo40_inst/FF_96.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_96.B0 - 1.2 fifo_colector_inst/fifo40_inst/full_cmp_2.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.C1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t12.A0 - 0.6 fifo_colector_inst/fifo40_inst/FF_76.M0 - -fifo_colector_inst/fifo40_inst/wcount_5 - fifo_colector_inst/fifo40_inst/FF_96.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_96.A1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_2.A1 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t12.C0 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t12.C1 - 0.6 fifo_colector_inst/fifo40_inst/FF_76.M1 - -fifo_colector_inst/fifo40_inst/wcount_6 - fifo_colector_inst/fifo40_inst/FF_94.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_94.B0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.B0 - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t12.D1 - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t10.D0 - 0.9 fifo_colector_inst/fifo40_inst/FF_74.M0 - -fifo_colector_inst/fifo40_inst/wcount_7 - fifo_colector_inst/fifo40_inst/FF_94.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_94.B1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.A1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t10.B0 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t10.B1 - 0.6 fifo_colector_inst/fifo40_inst/FF_74.M1 - -fifo_colector_inst/fifo40_inst/wcount_8 - fifo_colector_inst/fifo40_inst/FF_92.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_92.B0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_4.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t10.D1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.C0 - 0.6 fifo_colector_inst/fifo40_inst/FF_72.M0 - -fifo_colector_inst/fifo40_inst/wcount_9 - fifo_colector_inst/fifo40_inst/FF_92.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_92.B1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.D0 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.M1 - 0.6 fifo_colector_inst/fifo40_inst/FF_72.M1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_1.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_1.C1 - -fifo_colector_inst/fifo40_inst/wcount_r0 - fifo_colector_inst/fifo40_inst/LUT4_14.F1 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_0.A0 - -fifo_colector_inst/fifo40_inst/wcount_r1 - fifo_colector_inst/fifo40_inst/LUT4_15.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_0.A1 - -fifo_colector_inst/fifo40_inst/wcount_r2 - fifo_colector_inst/fifo40_inst/LUT4_17.F0 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_1.B0 - -fifo_colector_inst/fifo40_inst/wcount_r3 - fifo_colector_inst/fifo40_inst/LUT4_17.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_1.A1 - -fifo_colector_inst/fifo40_inst/wcount_r4 - fifo_colector_inst/fifo40_inst/LUT4_18.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_2.B0 - -fifo_colector_inst/fifo40_inst/wcount_r5 - fifo_colector_inst/fifo40_inst/LUT4_19.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_2.B1 - -fifo_colector_inst/fifo40_inst/wcount_r7 - fifo_colector_inst/fifo40_inst/LUT4_18.F0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_3.A1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_18.D1 - -fifo_colector_inst/fifo40_inst/wcount_r8 - fifo_colector_inst/fifo40_inst/LUT4_19.F0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_4.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_19.D1 - -fifo_colector_inst/fifo40_inst/wptr_0 - fifo_colector_inst/fifo40_inst/FF_80.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA5 - -fifo_colector_inst/fifo40_inst/wptr_1 - fifo_colector_inst/fifo40_inst/FF_80.Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA6 - -fifo_colector_inst/fifo40_inst/wptr_2 - fifo_colector_inst/fifo40_inst/FF_78.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA7 - -fifo_colector_inst/fifo40_inst/wptr_3 - fifo_colector_inst/fifo40_inst/FF_78.Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA8 - -fifo_colector_inst/fifo40_inst/wptr_4 - fifo_colector_inst/fifo40_inst/FF_76.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA9 - -fifo_colector_inst/fifo40_inst/wptr_5 - fifo_colector_inst/fifo40_inst/FF_76.Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA10 - -fifo_colector_inst/fifo40_inst/wptr_6 - fifo_colector_inst/fifo40_inst/FF_74.Q0 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA11 - -fifo_colector_inst/fifo40_inst/wptr_7 - fifo_colector_inst/fifo40_inst/FF_74.Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA12 - -fifo_colector_inst/fifo40_inst/wptr_8 - fifo_colector_inst/fifo40_inst/FF_72.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA13 - -fifo_colector_inst/fifo40_inst/wptr_9 - fifo_colector_inst/fifo40_inst/FF_72.Q1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_1.B0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_1.B1 - -fifo_colector_inst/fifo40_inst/wren_i - fifo_colector_inst/fifo40_inst/AND2_t20.F0 - 0.6 fifo_colector_inst/fifo40_inst/FF_100.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_98.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_96.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_94.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_92.CE - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_ci_a.A1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_ci_a.B1 - 0.3 fifo_colector_inst/fifo40_inst/XOR2_t16.CE - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.CE - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t12.CE - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t10.CE - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t9.CE - 0.3 fifo_colector_inst/fifo40_inst/FF_80.CE - 0.8 fifo_colector_inst/fifo40_inst/FF_78.CE - 0.8 fifo_colector_inst/fifo40_inst/FF_76.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_74.CE - 0.3 fifo_colector_inst/fifo40_inst/FF_72.CE - 1.0 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CEA - -fifo_colector_inst/in_empty_pmux - fifo_colector_inst/in_empty_pmux_0.F0 - 0.2 fifo_colector_inst/in_read_enable_1_.fb.LSR - 0.2 fifo_colector_inst/in_read_enable_2_.fb.LSR - -fifo_colector_inst/in_empty_pmux_0 - fifo_colector_inst/in_empty_pmux_0.F1 - 0.4 fifo_colector_inst/in_empty_pmux_0.A0 - -fifo_colector_inst/in_empty_pmux_i - fifo_colector_inst/in_empty_pmux_0_RNIDRET.OFX0 - 0.0 fifo_colector_inst/in_empty_pmux_0_RNIDRET.DI0 - 1.2 fifo_colector_inst/data_buffer_3[0].CE - 1.2 fifo_colector_inst/data_buffer_3[1].CE - 0.7 fifo_colector_inst/data_buffer_3[2].CE - 0.7 fifo_colector_inst/data_buffer_3[3].CE - 1.4 fifo_colector_inst/data_buffer_3[4].CE - 1.3 fifo_colector_inst/data_buffer_3[5].CE - 1.3 fifo_colector_inst/data_buffer_3[6].CE - 0.4 fifo_colector_inst/data_buffer_3[7].CE - 0.4 fifo_colector_inst/data_buffer_3_0[9].CE - 1.2 fifo_colector_inst/data_buffer_3_0[11].CE - 1.1 fifo_colector_inst/data_buffer_3_0[13].CE - 0.7 fifo_colector_inst/data_buffer_3_0[15].CE - 1.4 fifo_colector_inst/data_buffer_3_0[17].CE - 1.4 fifo_colector_inst/data_buffer_3_0[19].CE - 1.1 fifo_colector_inst/data_buffer_3_0[21].CE - 0.9 fifo_colector_inst/data_buffer_3_0[23].CE - 1.0 fifo_colector_inst/data_buffer_3_0[25].CE - 0.8 fifo_colector_inst/data_buffer_3_0[27].CE - 0.9 fifo_colector_inst/data_buffer_3_0[29].CE - 1.2 fifo_colector_inst/data_buffer_3_0[31].CE - 1.4 fifo_colector_inst/data_buffer[33].CE - -fifo_colector_inst/iterator[0] - fifo_colector_inst/un5_in_read_enable.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.C0 - 0.9 fifo_colector_inst/data_buffer_3[0].D0 - 0.9 fifo_colector_inst/data_buffer_3[0].D1 - 0.6 fifo_colector_inst/data_buffer_3[1].D0 - 0.6 fifo_colector_inst/data_buffer_3[1].D1 - 0.6 fifo_colector_inst/data_buffer_3[2].D0 - 0.6 fifo_colector_inst/data_buffer_3[2].D1 - 0.6 fifo_colector_inst/data_buffer_3[3].D0 - 0.6 fifo_colector_inst/data_buffer_3[3].D1 - 0.5 fifo_colector_inst/data_buffer_3[4].C0 - 0.5 fifo_colector_inst/data_buffer_3[4].C1 - 0.5 fifo_colector_inst/data_buffer_3[5].D0 - 0.5 fifo_colector_inst/data_buffer_3[5].D1 - 0.5 fifo_colector_inst/data_buffer_3[6].C0 - 0.5 fifo_colector_inst/data_buffer_3[6].C1 - 1.3 fifo_colector_inst/data_buffer_3[7].B0 - 1.3 fifo_colector_inst/data_buffer_3[7].B1 - 1.0 fifo_colector_inst/data_buffer_3_0[9].D0 - 1.0 fifo_colector_inst/data_buffer_3_0[9].D1 - 0.9 fifo_colector_inst/data_buffer_3_0[11].D0 - 0.9 fifo_colector_inst/data_buffer_3_0[11].D1 - 1.4 fifo_colector_inst/data_buffer_3_0[13].A0 - 1.1 fifo_colector_inst/data_buffer_3_0[13].D1 - 0.6 fifo_colector_inst/data_buffer_3_0[15].D0 - 0.6 fifo_colector_inst/data_buffer_3_0[15].D1 - 1.3 fifo_colector_inst/data_buffer_3_0[17].B0 - 0.9 fifo_colector_inst/data_buffer_3_0[17].D1 - 1.3 fifo_colector_inst/data_buffer_3_0[19].A0 - 0.9 fifo_colector_inst/data_buffer_3_0[19].D1 - 1.1 fifo_colector_inst/data_buffer_3_0[21].D0 - 1.1 fifo_colector_inst/data_buffer_3_0[21].D1 - 0.9 fifo_colector_inst/data_buffer_3_0[23].D0 - 0.9 fifo_colector_inst/data_buffer_3_0[23].D1 - 0.7 fifo_colector_inst/data_buffer_3_0[25].C0 - 0.8 fifo_colector_inst/data_buffer_3_0[25].D1 - 0.6 fifo_colector_inst/data_buffer_3_0[27].B0 - 0.6 fifo_colector_inst/data_buffer_3_0[27].D1 - 1.0 fifo_colector_inst/data_buffer_3_0[29].B0 - 1.0 fifo_colector_inst/data_buffer_3_0[29].B1 - 0.8 fifo_colector_inst/data_buffer_3_0[31].C0 - 1.0 fifo_colector_inst/data_buffer_3_0[31].B1 - 1.0 fifo_colector_inst/data_buffer[33].M0 - 0.3 fifo_colector_inst/un5_in_read_enable.C0 - 0.6 fifo_colector_inst/un5_in_read_enable.M1 - 0.7 fifo_colector_inst/in_read_enable_1_.fb.C0 - 0.7 fifo_colector_inst/in_read_enable_1_.fb.C1 - 0.6 fifo_colector_inst/in_empty_pmux_0.D1 - -fifo_colector_inst/iterator[1] - fifo_colector_inst/un5_in_read_enable.Q1 - 1.0 fifo_colector_inst/in_empty_pmux_0_RNIDRET.M0 - 0.9 fifo_colector_inst/data_buffer_3[0].A0 - 0.9 fifo_colector_inst/data_buffer_3[0].A1 - 0.9 fifo_colector_inst/data_buffer_3[1].A0 - 0.9 fifo_colector_inst/data_buffer_3[1].A1 - 0.6 fifo_colector_inst/data_buffer_3[2].A0 - 0.6 fifo_colector_inst/data_buffer_3[2].A1 - 0.6 fifo_colector_inst/data_buffer_3[3].A0 - 0.6 fifo_colector_inst/data_buffer_3[3].A1 - 0.6 fifo_colector_inst/data_buffer_3[4].A0 - 0.6 fifo_colector_inst/data_buffer_3[4].A1 - 0.6 fifo_colector_inst/data_buffer_3[5].A0 - 0.6 fifo_colector_inst/data_buffer_3[5].A1 - 0.6 fifo_colector_inst/data_buffer_3[6].A0 - 0.6 fifo_colector_inst/data_buffer_3[6].A1 - 1.1 fifo_colector_inst/data_buffer_3[7].A0 - 1.1 fifo_colector_inst/data_buffer_3[7].A1 - 1.3 fifo_colector_inst/data_buffer[33].M1 - 0.5 fifo_colector_inst/un5_in_read_enable.B0 - 0.8 fifo_colector_inst/in_read_enable_1_.fb.A0 - 0.8 fifo_colector_inst/in_read_enable_2_.fb.A0 - 0.8 fifo_colector_inst/in_empty_pmux_0.B0 - 0.8 fifo_colector_inst/iterator_RNI7U5I[1].D0 - -fifo_colector_inst/iterator_RNI7U5I[1] - fifo_colector_inst/iterator_RNI7U5I[1].F0 - 1.2 fifo_colector_inst/data_buffer_3_0[9].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[11].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[13].LSR - 1.3 fifo_colector_inst/data_buffer_3_0[15].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[17].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[19].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[21].LSR - 1.3 fifo_colector_inst/data_buffer_3_0[23].LSR - 0.7 fifo_colector_inst/data_buffer_3_0[25].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[27].LSR - 0.7 fifo_colector_inst/data_buffer_3_0[29].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[31].LSR - -fifo_colector_inst/un5_in_read_enable - fifo_colector_inst/un5_in_read_enable.F0 - 0.0 fifo_colector_inst/un5_in_read_enable.DI0 - -fifo_empty1_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.A0 - 0.9 fifo_colector_inst/in_empty_pmux_0.C1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - 2.6 fifo_empty1_pad.PADDO - -fifo_empty[1] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.D0 - 0.9 fifo_colector_inst/in_empty_pmux_0.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - -fifo_empty[2] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 1.3 fifo_colector_inst/in_empty_pmux_0_RNIDRET.B1 - 1.4 fifo_colector_inst/in_empty_pmux_0.D0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - 1.3 fifo_colector_inst/iterator_RNI7U5I[1].A0 - -fifo_rden_c - trb_adapter_inst/burst.Q0 - 0.1 trb_adapter_inst/burst.D0 - 3.3 trb_adapter_inst/buf_rden_prev.M0 - 2.6 fifo_colector_inst/fifo40_inst/AND2_t19.C0 - 3.3 trb_adapter_inst/release_out.LSR - 3.4 trb_adapter_inst_FEE_DATA_WRITE_OUTio.TXDATA0 - 4.3 fifo_rden_pad.PADDO - -fifo_read[0] - fifo_colector_inst/in_read_enable_1_.fb.Q0 - 0.1 fifo_colector_inst/in_read_enable_1_.fb.D0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.B0 - -fifo_read[1] - fifo_colector_inst/in_read_enable_1_.fb.Q1 - 0.4 fifo_colector_inst/in_read_enable_1_.fb.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0 - -fifo_read[2] - fifo_colector_inst/in_read_enable_2_.fb.Q0 - 0.1 fifo_colector_inst/in_read_enable_2_.fb.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0 - -finished_c - trb_adapter_inst/release_out.Q0 - 0.5 trb_adapter_inst/finished_prev.M0 - 0.6 trb_adapter_inst/release_out.A0 - 1.0 finished_pad.PADDO - 0.5 trb_adapter_inst_FEE_DATAFINISHED_OUTio.TXDATA0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.A0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 1.6 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fb_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - 1.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 1.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0 - 1.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 1.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 1.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[0] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 1.1 fifo_colector_inst/data_buffer_3[0].B0 - 1.1 fifo_colector_inst/data_buffer_3[0].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[10] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.9 fifo_colector_inst/data_buffer_3_0[11].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[11] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 1.2 fifo_colector_inst/data_buffer_3_0[11].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[12] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 0.7 fifo_colector_inst/data_buffer_3_0[13].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[13] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.8 fifo_colector_inst/data_buffer_3_0[13].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[14] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 0.9 fifo_colector_inst/data_buffer_3_0[15].A0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[15] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.7 fifo_colector_inst/data_buffer_3_0[15].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[16] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 0.6 fifo_colector_inst/data_buffer_3_0[17].D0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[17] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 0.8 fifo_colector_inst/data_buffer_3_0[17].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[18] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.7 fifo_colector_inst/data_buffer_3_0[19].D0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[19] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 1.1 fifo_colector_inst/data_buffer_3_0[19].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[1] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.0 fifo_colector_inst/data_buffer_3[1].B0 - 1.0 fifo_colector_inst/data_buffer_3[1].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[20] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.9 fifo_colector_inst/data_buffer_3_0[21].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[21] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 1.0 fifo_colector_inst/data_buffer_3_0[21].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[22] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.8 fifo_colector_inst/data_buffer_3_0[23].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[23] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.9 fifo_colector_inst/data_buffer_3_0[23].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[2] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 1.0 fifo_colector_inst/data_buffer_3[2].C0 - 1.0 fifo_colector_inst/data_buffer_3[2].C1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[3] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 0.8 fifo_colector_inst/data_buffer_3[3].C0 - 0.8 fifo_colector_inst/data_buffer_3[3].C1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[4] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.9 fifo_colector_inst/data_buffer_3[4].D0 - 0.9 fifo_colector_inst/data_buffer_3[4].D1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[5] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 1.1 fifo_colector_inst/data_buffer_3[5].B0 - 1.1 fifo_colector_inst/data_buffer_3[5].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[6] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 0.9 fifo_colector_inst/data_buffer_3[6].B0 - 0.9 fifo_colector_inst/data_buffer_3[6].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[7] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 0.8 fifo_colector_inst/data_buffer_3[7].D0 - 0.8 fifo_colector_inst/data_buffer_3[7].D1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[8] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 1.0 fifo_colector_inst/data_buffer_3_0[9].B0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[9] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3_0[9].C1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.2 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.A0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fb_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.A0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[0] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 0.9 fifo_colector_inst/data_buffer_3_0[25].A0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[10] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.9 fifo_colector_inst/data_buffer_3[2].B0 - 0.9 fifo_colector_inst/data_buffer_3[2].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[11] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 0.7 fifo_colector_inst/data_buffer_3[3].B0 - 0.7 fifo_colector_inst/data_buffer_3[3].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[12] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 0.6 fifo_colector_inst/data_buffer_3[4].B0 - 0.6 fifo_colector_inst/data_buffer_3[4].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[13] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.5 fifo_colector_inst/data_buffer_3[5].C0 - 0.5 fifo_colector_inst/data_buffer_3[5].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[14] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 0.4 fifo_colector_inst/data_buffer_3[6].D0 - 0.4 fifo_colector_inst/data_buffer_3[6].D1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[15] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.9 fifo_colector_inst/data_buffer_3[7].C0 - 0.9 fifo_colector_inst/data_buffer_3[7].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[16] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 0.7 fifo_colector_inst/data_buffer_3_0[9].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[17] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 1.1 fifo_colector_inst/data_buffer_3_0[9].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[18] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.8 fifo_colector_inst/data_buffer_3_0[11].B0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[19] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 0.9 fifo_colector_inst/data_buffer_3_0[11].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[1] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.0 fifo_colector_inst/data_buffer_3_0[25].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[20] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.8 fifo_colector_inst/data_buffer_3_0[13].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[21] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 0.8 fifo_colector_inst/data_buffer_3_0[13].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[22] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.6 fifo_colector_inst/data_buffer_3_0[15].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[23] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.8 fifo_colector_inst/data_buffer_3_0[15].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[2] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 0.5 fifo_colector_inst/data_buffer_3_0[27].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[3] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 0.7 fifo_colector_inst/data_buffer_3_0[27].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[4] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.7 fifo_colector_inst/data_buffer_3_0[29].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[5] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 0.8 fifo_colector_inst/data_buffer_3_0[29].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[6] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 0.6 fifo_colector_inst/data_buffer_3_0[31].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[7] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 0.7 fifo_colector_inst/data_buffer_3_0[31].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[8] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 0.9 fifo_colector_inst/data_buffer_3[0].C0 - 0.9 fifo_colector_inst/data_buffer_3[0].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[9] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3[1].C0 - 0.9 fifo_colector_inst/data_buffer_3[1].C1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.2 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fb_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 1.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.2 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[0] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 0.9 fifo_colector_inst/data_buffer_3_0[17].C0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[10] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.8 fifo_colector_inst/data_buffer_3_0[27].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[11] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 0.7 fifo_colector_inst/data_buffer_3_0[27].C1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[12] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 1.0 fifo_colector_inst/data_buffer_3_0[29].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[13] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.8 fifo_colector_inst/data_buffer_3_0[29].D1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[14] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 1.1 fifo_colector_inst/data_buffer_3_0[31].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[15] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.8 fifo_colector_inst/data_buffer_3_0[31].D1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[16] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 1.0 fifo_colector_inst/data_buffer_3[0].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[17] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 1.0 fifo_colector_inst/data_buffer_3[1].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[18] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.8 fifo_colector_inst/data_buffer_3[2].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[19] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 0.8 fifo_colector_inst/data_buffer_3[3].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[1] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.1 fifo_colector_inst/data_buffer_3_0[17].C1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[20] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.8 fifo_colector_inst/data_buffer_3[4].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[21] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 0.9 fifo_colector_inst/data_buffer_3[5].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[22] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.9 fifo_colector_inst/data_buffer_3[6].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[23] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.9 fifo_colector_inst/data_buffer_3[7].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[2] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 1.0 fifo_colector_inst/data_buffer_3_0[19].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[3] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 1.0 fifo_colector_inst/data_buffer_3_0[19].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[4] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.9 fifo_colector_inst/data_buffer_3_0[21].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[5] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 1.1 fifo_colector_inst/data_buffer_3_0[21].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[6] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 1.0 fifo_colector_inst/data_buffer_3_0[23].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[7] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 1.0 fifo_colector_inst/data_buffer_3_0[23].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[8] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 1.0 fifo_colector_inst/data_buffer_3_0[25].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[9] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3_0[25].C1 - -hades_buf_drop_c[1] - hades_tdc_bundle_inst_buf_drop_1io[1].IOLDO - 0.0 hades_buf_drop_pad[1].IOLDO - -hades_buf_finished_c - hades_tdc_bundle_inst/buf_finished5_0_a2_0.Q0 - 0.9 hades_tdc_bundle_inst/buf_release.M0 - 1.2 hades_buf_finished_pad.PADDO - -hades_buf_out_valid_c - hades_tdc_bundle_inst_buf_out_validio.IOLDO - 0.0 hades_buf_out_valid_pad.IOLDO - -hades_buf_release_c - hades_tdc_bundle_inst/buf_release.Q0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[0].D0 - 1.2 hades_tdc_bundle_inst/hit_valid_1_RNO[0].B1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].D0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].D1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].C1 - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[3].C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[3].B1 - 1.3 hades_buf_release_pad.PADDO - -hades_dbg2_coarse_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.C1 - 0.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.C1 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].A0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].A1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B1 - 1.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D1 - 1.8 hades_dbg2_coarse_pad[0].PADDO - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].TXDATA0 - -hades_dbg2_coarse_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.D1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.B1 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].D0 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B1 - 1.8 hades_dbg2_coarse_pad[1].PADDO - 1.5 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].TXDATA0 - -hades_dbg2_coarse_c[2] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q0 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].C0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].B1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A1 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C1 - 2.7 hades_dbg2_coarse_pad[2].PADDO - 2.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].TXDATA0 - -hades_dbg2_coarse_c[3] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].C1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A0 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.A0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.C0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A1 - 2.0 hades_dbg2_coarse_pad[3].PADDO - 1.8 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].TXDATA0 - -hades_dbg2_coarse_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q0 - 0.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.C1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.D1 - 1.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M1 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.D1 - 3.0 hades_dbg2_coarse_pad[4].PADDO - 1.9 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].TXDATA0 - -hades_dbg2_coarse_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.A1 - 2.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M0 - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.B1 - 2.9 hades_dbg2_coarse_pad[5].PADDO - 2.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].TXDATA0 - -hades_dbg2_coarse_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C1 - 2.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M1 - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.C0 - 2.5 hades_dbg2_coarse_pad[6].PADDO - -hades_dbg2_coarse_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D1 - 1.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M0 - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.A0 - 3.3 hades_dbg2_coarse_pad[7].PADDO - -hades_dbg2_coarse_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.Q0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.C1 - 1.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M1 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M1 - 2.4 hades_dbg2_coarse_pad[8].PADDO - -hades_dbg2_out_c[0] - hades_tdc_bundle_inst_hitbuffer_1_io[0].IOLDO - 0.0 hades_dbg2_out_pad[0].IOLDO - -hades_dbg2_out_c[10] - hades_tdc_bundle_inst/hitbuffer_1_[10].Q0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[7].M0 - 1.7 hades_dbg2_out_pad[10].PADDO - -hades_dbg2_out_c[11] - hades_tdc_bundle_inst/hitbuffer_1_[10].Q1 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[7].M1 - 1.9 hades_dbg2_out_pad[11].PADDO - -hades_dbg2_out_c[12] - hades_tdc_bundle_inst/hitbuffer_1_[11].Q0 - 1.0 hades_tdc_bundle_inst/drop_cmp_buf_1[8].M0 - 1.7 hades_dbg2_out_pad[12].PADDO - -hades_dbg2_out_c[16] - hades_tdc_bundle_inst_hitbuffer_1_io[12].IOLDO - 0.0 hades_dbg2_out_pad[16].IOLDO - -hades_dbg2_out_c[17] - hades_tdc_bundle_inst_hitbuffer_1_io[13].IOLDO - 0.0 hades_dbg2_out_pad[17].IOLDO - -hades_dbg2_out_c[18] - hades_tdc_bundle_inst_hitbuffer_1_io[14].IOLDO - 0.0 hades_dbg2_out_pad[18].IOLDO - -hades_dbg2_out_c[1] - hades_tdc_bundle_inst_hitbuffer_1_io[1].IOLDO - 0.0 hades_dbg2_out_pad[1].IOLDO - -hades_dbg2_out_c[20] - hades_tdc_bundle_inst_hitbuffer_1_io[15].IOLDO - 0.0 hades_dbg2_out_pad[20].IOLDO - -hades_dbg2_out_c[21] - hades_tdc_bundle_inst_hitbuffer_1_io[16].IOLDO - 0.0 hades_dbg2_out_pad[21].IOLDO - -hades_dbg2_out_c[22] - hades_tdc_bundle_inst_hitbuffer_1_io[17].IOLDO - 0.0 hades_dbg2_out_pad[22].IOLDO - -hades_dbg2_out_c[23] - hades_tdc_bundle_inst_hitbuffer_1_io[18].IOLDO - 0.0 hades_dbg2_out_pad[23].IOLDO - -hades_dbg2_out_c[24] - hades_tdc_bundle_inst_hitbuffer_1_io[19].IOLDO - 0.0 hades_dbg2_out_pad[24].IOLDO - -hades_dbg2_out_c[25] - hades_tdc_bundle_inst_hitbuffer_1_io[20].IOLDO - 0.0 hades_dbg2_out_pad[25].IOLDO - -hades_dbg2_out_c[26] - hades_tdc_bundle_inst_hitbuffer_1_io[21].IOLDO - 0.0 hades_dbg2_out_pad[26].IOLDO - -hades_dbg2_out_c[27] - hades_tdc_bundle_inst_hitbuffer_1_io[22].IOLDO - 0.0 hades_dbg2_out_pad[27].IOLDO - -hades_dbg2_out_c[28] - hades_tdc_bundle_inst_hitbuffer_1_io[23].IOLDO - 0.0 hades_dbg2_out_pad[28].IOLDO - -hades_dbg2_out_c[2] - hades_tdc_bundle_inst_hitbuffer_1_io[2].IOLDO - 0.0 hades_dbg2_out_pad[2].IOLDO - -hades_dbg2_out_c[4] - hades_tdc_bundle_inst/hitbuffer_1_[4].Q0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[1].M0 - 1.8 hades_dbg2_out_pad[4].PADDO - -hades_dbg2_out_c[5] - hades_tdc_bundle_inst/hitbuffer_1_[4].Q1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[1].M1 - 1.4 hades_dbg2_out_pad[5].PADDO - -hades_dbg2_out_c[6] - hades_tdc_bundle_inst/hitbuffer_1_[6].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[3].M0 - 1.5 hades_dbg2_out_pad[6].PADDO - -hades_dbg2_out_c[7] - hades_tdc_bundle_inst/hitbuffer_1_[6].Q1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[3].M1 - 1.4 hades_dbg2_out_pad[7].PADDO - -hades_dbg2_out_c[8] - hades_tdc_bundle_inst/hitbuffer_1_[8].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[5].M0 - 1.5 hades_dbg2_out_pad[8].PADDO - -hades_dbg2_out_c[9] - hades_tdc_bundle_inst/hitbuffer_1_[8].Q1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[5].M1 - 1.5 hades_dbg2_out_pad[9].PADDO - -hades_discard_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.Q0 - 1.5 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].D0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].M0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A1 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.B0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].B0 - 1.3 hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].A0 - 2.1 hades_discard_pad.PADDO - -hades_drop_cmp_buf_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.D1 - 1.1 hades_drop_cmp_buf_pad[0].PADDO - -hades_drop_cmp_buf_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q1 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.A1 - 1.3 hades_drop_cmp_buf_pad[1].PADDO - -hades_drop_cmp_buf_c[2] - hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C0 - 1.5 hades_drop_cmp_buf_pad[2].PADDO - -hades_drop_cmp_buf_c[3] - hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q1 - 1.0 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A0 - 1.5 hades_drop_cmp_buf_pad[3].PADDO - -hades_drop_cmp_buf_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q0 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A1 - 1.4 hades_drop_cmp_buf_pad[4].PADDO - -hades_drop_cmp_buf_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q1 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C1 - 1.4 hades_drop_cmp_buf_pad[5].PADDO - -hades_drop_cmp_buf_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B0 - 1.2 hades_drop_cmp_buf_pad[6].PADDO - -hades_drop_cmp_buf_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q1 - 0.8 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.A0 - 1.6 hades_drop_cmp_buf_pad[7].PADDO - -hades_drop_cmp_buf_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_1[8].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D1 - 1.4 hades_drop_cmp_buf_pad[8].PADDO - -hades_drop_cmp_buf_coarse_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.C1 - 1.5 hades_drop_cmp_buf_coarse_pad[0].PADDO - -hades_drop_cmp_buf_coarse_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.B1 - 1.9 hades_drop_cmp_buf_coarse_pad[1].PADDO - -hades_drop_cmp_buf_coarse_c[2] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B0 - 1.5 hades_drop_cmp_buf_coarse_pad[2].PADDO - -hades_drop_cmp_buf_coarse_c[3] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D0 - 2.0 hades_drop_cmp_buf_coarse_pad[3].PADDO - -hades_drop_cmp_buf_coarse_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B1 - 1.8 hades_drop_cmp_buf_coarse_pad[4].PADDO - -hades_drop_cmp_buf_coarse_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D1 - 1.9 hades_drop_cmp_buf_coarse_pad[5].PADDO - -hades_drop_cmp_buf_coarse_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C0 - 1.7 hades_drop_cmp_buf_coarse_pad[6].PADDO - -hades_drop_cmp_buf_coarse_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q1 - 0.4 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D0 - 1.6 hades_drop_cmp_buf_coarse_pad[7].PADDO - -hades_drop_cmp_buf_coarse_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B1 - 1.9 hades_drop_cmp_buf_coarse_pad[8].PADDO - -hades_drop_cmp_buf_coarse_c[9] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C1 - 2.0 hades_drop_cmp_buf_coarse_pad[9].PADDO - -hades_drop_cmp_buf_valid_c - hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.Q0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].B0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].B1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D1 - 1.3 hades_drop_cmp_buf_valid_pad.PADDO - -hades_hit_valid_c[0] - hades_tdc_bundle_inst/hit_valid_1_RNO[0].Q0 - 0.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].C0 - 0.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].D1 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C0 - 1.2 hades_hit_valid_pad[0].PADDO - -hades_hit_valid_c[1] - hades_tdc_bundle_inst/hit_valid_1_RNO[1].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.D0 - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[1].M0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.C0 - 1.1 hades_hit_valid_pad[1].PADDO - -hades_hit_valid_c[2] - hades_tdc_bundle_inst/hit_valid_1_RNO[2].Q0 - 0.2 hades_tdc_bundle_inst/hit_valid_1_RNO[2].D0 - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[2].A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.B0 - 1.2 hades_hit_valid_pad[2].PADDO - -hades_hit_valid_c[3] - hades_tdc_bundle_inst/hit_valid_1_RNO[3].Q0 - 0.2 hades_tdc_bundle_inst/hit_valid_1_RNO[3].D0 - 0.4 hades_tdc_bundle_inst/hit_valid_1_RNO[3].C1 - 0.9 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A0 - 0.9 hades_hit_valid_pad[3].PADDO - -hades_invalid_dl_c[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].INFF - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M0 - 0.6 hades_invalid_dl_pad[0].PADDO - -hades_invalid_dl_c[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M1 - 1.2 hades_invalid_dl_pad[1].PADDO - -hades_invalid_dl_c[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q1 - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].M0 - 1.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.D0 - 0.9 hades_invalid_dl_pad[2].PADDO - -hades_invalid_dl_c[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].Q0 - 1.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.B0 - 1.2 hades_invalid_dl_pad[3].PADDO - -hades_lvl1_c - hades_lvl1_pad.PADDI - 0.9 hades_lvl1_pad_RNINMH5.D0 - 0.0 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].DI - -hades_lvl1_c_i - hades_lvl1_pad_RNINMH5.F0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -hades_lvl1_invalid_c - hades_lvl1_invalid_pad.PADDI - 0.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].DI - -hades_offset_c[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].IOLDO - 0.0 hades_offset_pad[0].IOLDO - -hades_offset_c[1] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].IOLDO - 0.0 hades_offset_pad[1].IOLDO - -hades_offset_c[2] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].IOLDO - 0.0 hades_offset_pad[2].IOLDO - -hades_offset_c[3] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].IOLDO - 0.0 hades_offset_pad[3].IOLDO - -hades_offset_c[4] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].IOLDO - 0.0 hades_offset_pad[4].IOLDO - -hades_offset_c[5] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].IOLDO - 0.0 hades_offset_pad[5].IOLDO - -hades_offset_c[6] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].IOLDO - 0.0 hades_offset_pad[6].IOLDO - -hades_offset_c[7] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].IOLDO - 0.0 hades_offset_pad[7].IOLDO - -hades_offset_c[8] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].IOLDO - 0.0 hades_offset_pad[8].IOLDO - -hades_offset_valid_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.Q0 - 2.7 hades_offset_valid_pad.PADDO - 2.5 hades_tdc_bundle_inst_referenced_out_validio.TXDATA0 - -hades_raw_out_valid_c - hades_tdc_bundle_inst_referenced_out_validio.IOLDO - 0.0 hades_raw_out_valid_pad.IOLDO - -hades_tdc_bundle_inst.buf_out12 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F0 - 0.8 hades_tdc_bundle_inst_buf_out_validio.TXDATA0 - -hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F1 - 1.0 hades_tdc_bundle_inst_buf_drop_1io[1].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.OFX0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CE - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.D0 - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CE - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CE - 1.5 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CE - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q0 - 1.0 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q1 - 1.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].Q0 - 1.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].INFF - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].M0 - -hades_tdc_bundle_inst.hades_raw_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q0 - 1.0 hades_tdc_bundle_inst_hitbuffer_1_io[0].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[12] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q1 - 0.5 hades_tdc_bundle_inst_hitbuffer_1_io[12].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[13] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q0 - 0.9 hades_tdc_bundle_inst_hitbuffer_1_io[13].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[14] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q1 - 0.9 hades_tdc_bundle_inst_hitbuffer_1_io[14].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[15] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q0 - 1.2 hades_tdc_bundle_inst_hitbuffer_1_io[15].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[16] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q1 - 1.1 hades_tdc_bundle_inst_hitbuffer_1_io[16].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[17] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q0 - 1.0 hades_tdc_bundle_inst_hitbuffer_1_io[17].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[18] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q1 - 1.1 hades_tdc_bundle_inst_hitbuffer_1_io[18].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[19] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q0 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[19].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q1 - 0.8 hades_tdc_bundle_inst_hitbuffer_1_io[1].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[20] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q1 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[20].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[21] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q0 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[21].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[22] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q1 - 0.7 hades_tdc_bundle_inst_hitbuffer_1_io[22].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[23] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].Q0 - 0.8 hades_tdc_bundle_inst_hitbuffer_1_io[23].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q0 - 0.5 hades_tdc_bundle_inst_hitbuffer_1_io[2].TXDATA0 - -hades_tdc_bundle_inst/N_243_i - hades_tdc_bundle_inst/hit_valid_1_RNO[1].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].DI0 - -hades_tdc_bundle_inst/N_244_i - hades_tdc_bundle_inst/hit_valid_1_RNO[3].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[3].DI0 - -hades_tdc_bundle_inst/N_245_i - hades_tdc_bundle_inst/hit_valid_1_RNO[2].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[2].DI0 - -hades_tdc_bundle_inst/N_246_i - hades_tdc_bundle_inst/hit_valid_1_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[0].DI0 - -hades_tdc_bundle_inst/N_247_i - hades_tdc_bundle_inst/hit_out_i_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hit_out_i_RNO[0].DI0 - -hades_tdc_bundle_inst/N_44 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F1 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].A0 - -hades_tdc_bundle_inst/N_45 - hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F0 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.D1 - -hades_tdc_bundle_inst/N_46_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.DI0 - -hades_tdc_bundle_inst/N_50_i_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.DI1 - -hades_tdc_bundle_inst/N_59_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.DI0 - -hades_tdc_bundle_inst/N_66 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F1 - 0.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.D0 - -hades_tdc_bundle_inst/N_80 - hades_tdc_bundle_inst/buf_finished5_0_a2_0.F1 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A0 - -hades_tdc_bundle_inst/N_90 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F1 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.B0 - -hades_tdc_bundle_inst/SUM1_0_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.DI1 - -hades_tdc_bundle_inst/buf_finished5 - hades_tdc_bundle_inst/buf_finished5_0_a2_0.F0 - 0.0 hades_tdc_bundle_inst/buf_finished5_0_a2_0.DI0 - -hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.F0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[1].CE - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[3].CE - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[5].CE - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[7].CE - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_1[8].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CE - 1.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CE - 1.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CE - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.DI1 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].F0 - 0.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].DI0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].F1 - 0.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].DI1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.DI0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.DI1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.DI0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.DI1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.DI0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.OFX0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.DI0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.F0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.B1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.F1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.B0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.B1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.B0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.B1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.B1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.B0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.B1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.B1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.F1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A1 - -hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].F1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.F1 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].Q1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].Q1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].M1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].F0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.A1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.D1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.M0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.F0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.M0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].B1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].A1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].F0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.A0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.F1 - 0.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CE - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].Q1 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].M0 - 1.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.OFX0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].D1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.F0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.F0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.A1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].C1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.C1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.F1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.D1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.C0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.B1 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.B1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].B1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.D0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.C0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.A0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.M0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.M0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.M0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.A1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].Q1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.A0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.D1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.D1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].Q1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].B1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.B1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].A1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.OFX0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].LSR - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].LSR - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.DI0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].LSR - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.DI0 - -hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.DI0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].M0 - -hades_tdc_bundle_inst/hades_raw_out[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q1 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[10].M1 - -hades_tdc_bundle_inst/hades_raw_out[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].Q0 - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[11].M0 - -hades_tdc_bundle_inst/hades_raw_out[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[4].M0 - -hades_tdc_bundle_inst/hades_raw_out[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q1 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[4].M1 - -hades_tdc_bundle_inst/hades_raw_out[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[6].M0 - -hades_tdc_bundle_inst/hades_raw_out[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q1 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[6].M1 - -hades_tdc_bundle_inst/hades_raw_out[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q0 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[8].M0 - -hades_tdc_bundle_inst/hades_raw_out[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q1 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[8].M1 - -hades_tdc_bundle_inst/hades_raw_out[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[10].M0 - -hades_tdc_bundle_inst/hades_raw_out_valid - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.Q0 - 1.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].B0 - 1.2 hades_tdc_bundle_inst/hit_valid_1_RNO[2].D1 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[3].D1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CE - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CE - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.F0 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CE - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CE - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CE - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CE - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CE - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CE - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].Q1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.A1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].Q0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.B1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].M0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].Q0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].Q1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].M0 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].Q0 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].Q1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.A0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].Q1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.A1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].M0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.C0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].Q1 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].M0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.A0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.D0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.B0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.C1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.M0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.F0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].M1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.LSR - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.LSR - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.C1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.C0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.B1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.B0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.A1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.D1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.D0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.A1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].Q1 - 0.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.F0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.F1 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.DI1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.F1 - 0.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.B0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.B1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_o5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.D0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.D0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_cry - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_14 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_19 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.F0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_cry - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.B0 - -hades_tdc_bundle_inst/hit_i[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q0 - 0.9 hades_tdc_bundle_inst/hit_valid_1_RNO[0].A0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[2].B1 - 0.7 hades_tdc_bundle_inst/hit_valid_1_RNO[3].A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.D1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B1 - -hades_tdc_bundle_inst/hit_i[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[0].M0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].M0 - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[3].M0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C1 - -hades_tdc_bundle_inst/hit_out_i_6[2] - hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].OFX0 - 0.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].DI0 - -hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].F0 - 0.4 hades_tdc_bundle_inst/hit_out_i_RNO[0].M0 - -hades_tdc_bundle_inst/hit_valid25 - hades_tdc_bundle_inst/hit_valid25_0_I_27_0.F0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.B0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].C0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].C1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C1 - -hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_27_0.FCI - -hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - hades_tdc_bundle_inst/hit_valid25_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCI - -hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCI - -hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F0 - 0.1 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D0 - -hades_trig_c - hades_trig_pad.PADDI - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1 - 1.1 hades_trig_pad_RNIE1B4.A0 - -hades_trig_c_i - hades_trig_pad_RNIE1B4.F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -hades_window_end_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.Q0 - 1.2 hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].C0 - 2.5 hades_window_end_pad.PADDO - -last_buf_empty_c - fifo_colector_inst/fifo40_inst/FF_1.Q0 - 2.6 trb_adapter_inst/burst.C0 - 1.0 fifo_colector_inst/fifo40_inst/AND2_t19.D0 - 2.7 last_buf_empty_pad.PADDO - -pll0inst/GND - pll0inst/GND.F0 - 0.5 pll0inst/PLLInst_0.STDBY - -pll_clks[0] - pll0inst/PLLInst_0.CLKOP - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK - 1.7 pll0inst/PLLInst_0.CLKFB - -pll_clks[1] - pll0inst/PLLInst_0.CLKOS - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK - -pll_clks[2] - pll0inst/PLLInst_0.CLKOS2 - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK - -pll_clks[3] - pll0inst/PLLInst_0.CLKOS3 - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_100.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_98.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_96.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_94.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_92.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_0.CLK - 1.7 hades_tdc_bundle_inst/hit_out_i_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.CLK - 1.7 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].CLK - 1.7 fifo_colector_inst/in_empty_pmux_0_RNIDRET.CLK - 1.7 fifo_colector_inst/data_buffer_3[0].CLK - 1.7 fifo_colector_inst/data_buffer_3[1].CLK - 1.7 fifo_colector_inst/data_buffer_3[2].CLK - 1.7 fifo_colector_inst/data_buffer_3[3].CLK - 1.7 fifo_colector_inst/data_buffer_3[4].CLK - 1.7 fifo_colector_inst/data_buffer_3[5].CLK - 1.7 fifo_colector_inst/data_buffer_3[6].CLK - 1.7 fifo_colector_inst/data_buffer_3[7].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[9].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[11].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[13].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[15].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[17].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[19].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[21].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[23].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[25].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[27].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[29].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[31].CLK - 1.7 fifo_colector_inst/data_buffer[33].CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_30.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_28.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_26.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_24.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_22.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_10.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_8.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_6.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_4.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_2.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t16.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t14.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t12.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t10.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t9.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_80.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_78.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_76.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_74.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_72.CLK - 1.7 fifo_colector_inst/un5_in_read_enable.CLK - 1.7 fifo_colector_inst/in_read_enable_1_.fb.CLK - 1.7 fifo_colector_inst/in_read_enable_2_.fb.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/buf_finished5_0_a2_0.CLK - 1.7 hades_tdc_bundle_inst/buf_release.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.CLK - 1.7 hades_tdc_bundle_inst/coarse_RNI6RPP[2].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[4].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[6].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[8].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[10].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[11].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[1].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[3].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[5].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[7].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[8].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[1].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[2].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[23].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[22].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[21].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[20].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[19].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[18].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[17].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[16].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[15].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[14].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[13].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[12].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[2].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[1].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[0].CLK - 1.7 hades_tdc_bundle_inst_buf_drop_1io[1].CLK - 1.7 hades_tdc_bundle_inst_buf_out_validio.CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].CLK - 1.7 hades_tdc_bundle_inst_referenced_out_validio.CLK - 1.7 reset_dl_0io[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKA - -rd_clk_c - rd_clk_pad.PADDI - 1.7 fifo_colector_inst/fifo40_inst/FF_70.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_68.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_66.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_64.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_62.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_1.CLK - 1.7 trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t7.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t5.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t3.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t1.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t0.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_50.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_48.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_46.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_44.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_42.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_40.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_38.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_36.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_34.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_32.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_20.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_18.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_16.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_14.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_12.CLK - 1.7 trb_adapter_inst/burst.CLK - 1.7 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].CLK - 1.7 trb_adapter_inst/buf_rden_prev.CLK - 1.7 trb_adapter_inst/finished_prev.CLK - 1.7 trb_adapter_inst/release_out.CLK - 1.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.CLK - 1.8 trb_adapter_inst_FEE_DATAFINISHED_OUTio.CLK - 1.8 trb_adapter_inst_FEE_DATA_WRITE_OUTio.CLK - 1.8 trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].CLK - 1.8 trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].CLK - 1.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKB - -release_out_c - trb_adapter_inst/release_out.F0 - 0.7 release_out_pad.PADDO - 0.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.TXDATA0 - -reset_dc_c - reset_dc_pad.PADDI - 0.0 reset_dl_0io[1].DI - -reset_dl[1] - reset_dl_0io[1].INFF - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.M0 - -reset_dl[2] - hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.Q0 - 0.8 hades_tdc_bundle_inst/hit_out_i_RNO[0].LSR - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.LSR - 1.4 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].LSR - 2.1 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 2.4 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 3.4 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 0.5 hades_tdc_bundle_inst/buf_finished5_0_a2_0.LSR - 0.9 hades_tdc_bundle_inst/buf_release.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.LSR - 2.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].LSR - 2.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.LSR - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.LSR - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CE - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[0].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[1].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[2].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[3].CE - 1.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.LSR - 1.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].LSR - 2.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].LSR - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].LSR - 2.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A0 - 2.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A1 - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.M0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C1 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C0 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].LSR - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].LSR - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].LSR - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].LSR - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].LSR - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.LSR - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CE - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CE - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.LSR - 1.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.M0 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.A0 - 3.2 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.A0 - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.C0 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.B0 - 2.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.A0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].C0 - 0.2 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.D0 - 1.4 hades_tdc_bundle_inst_buf_drop_1io[1].LSR - 1.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.LSR - 1.8 trb_adapter_inst_FEE_DATAFINISHED_OUTio.LSR - 1.9 trb_adapter_inst_FEE_DATA_WRITE_OUTio.LSR - -trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].INFF - 0.6 trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].M0 - -trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].INFF - 3.7 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M0 - -trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q0 - 0.5 trb_adapter_inst/burst.B1 - 0.3 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M1 - 0.5 trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B0 - -trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q1 - 0.5 trb_adapter_inst/burst.A1 - 0.3 trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D0 - -trb_adapter_inst/buf_rden4 - trb_adapter_inst/burst.F0 - 0.0 trb_adapter_inst/burst.DI0 - -trb_adapter_inst/buf_rden_prev - trb_adapter_inst/buf_rden_prev.Q0 - 0.3 trb_adapter_inst/release_out.M0 - -trb_adapter_inst/finished_prev - trb_adapter_inst/finished_prev.Q0 - 0.5 trb_adapter_inst/release_out.B0 - -trig_c[0] - trig_pad[0].PADDI - 0.4 trig_pad_RNII4FF[0].D0 - -trig_c[1] - trig_pad[1].PADDI - 1.5 trig_pad_RNIJ5FF[1].D0 - -trig_c[2] - trig_pad[2].PADDI - 1.7 trig_pad_RNIK6FF[2].D0 - -trig_c_i[0] - trig_pad_RNII4FF[0].F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -trig_c_i[1] - trig_pad_RNIJ5FF[1].F0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -trig_c_i[2] - trig_pad_RNIK6FF[2].F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -un1_hit_i_2_0_a2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F0 - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[4].CE - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[6].CE - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[8].CE - 1.3 hades_tdc_bundle_inst/hitbuffer_1_[10].CE - 1.0 hades_tdc_bundle_inst/hitbuffer_1_[11].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[23].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[22].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[21].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[20].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[19].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[18].CE - 1.4 hades_tdc_bundle_inst_hitbuffer_1_io[17].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[16].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[15].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[14].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[13].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[12].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[2].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[1].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[0].CE - -valid_fast_RNI999V - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.F0 - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].LSR diff --git a/impl1/s1_impl1.dir/5_1.ncd b/impl1/s1_impl1.dir/5_1.ncd deleted file mode 100644 index eb6d8aae862a7e9b50dfe2c3969662b19f0737f2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1332184 zcmeEP2b@*K^}hSwTR;#&uwY+f12y{I_T5P0vIUVQELdWamjxCjBH)58g=`X&m>y#+ zv7~Cc>Am;fV|wrZ^xljAZ_eC%&&-**%iYJq%QN$SzYq4FIdkr`Z~DwV{P5rXuBr8H zkBN#=ao6@8)m@vTM}G3||1?ESJ4ZTpl*^YyD~1L;*01bX`oQ*%p{T!a$BOc&k#ucSB%PG1P$XU3 z6iL@MMN-=~B1yqMLPoNcvg|lVOi6OABPJuqIAV(X(TTO0^%f8JH>sLw9!s+pXrDx?guzxiu(*lOs|~oh$-&V95Kbc z*%4FROOBZ0?l7dC;;tED#GT%#OM_AIbWq$K-gHph9Zq&o+?_~vP~4qJc2L}%NOn+2 zoJe+1+?_~vP~4qJc2L}%YM_JSuA^hbolHB0yOZMXM6#3O?i7bkin~)BIw|f>apAU!{9E8yOVxh6nCdMbWz-$l!!FnC9Rv{ z?xa*V#obA%Zi>6p;85^%#mK?a?TxM%4JidfSBr*}LZNF#LrQ_rm7*b~Fz7nbkW%u? zDp9vIItvY5N_?GzhLn<1XP_aaxas_xnRaw2V6qOgq<)@ag#Mf8%0=W8%Ki7O4W7>nC>NT5ZWnVx|3i?$%5`97*YzD?jjgc z3YhL87*YzD?jRUa$_d>+Fr<_dx@qS~(92|j)YZOj3E6ndIse~vH}5n1$f1ur?F>vzcsUA@bKu4{M6 z2`YKAM0ZmLO9S1M6SC-ad+Q4lN=o!lMJ*Gohbl;!U_IXYqQ_fb^myxw9*Tran;vg{ z(G%Af&FKhiRo}|Nc+fY0^OnuqtD8o4ja0W^x$EM#N^kk$kb|N@Gs^f} zsjJ7U*;dV*(1X}Rb?R=}M)9g{+Uk#*9@^$rrhLn*Oc|F~nR0Hv4)ca9H&-`}ZQqd* zV#>IDs+4c}R4LmsRn1%@V&=*<-64u|ZPSKJS|{L7D;0*Ex)g+*x+X986b6%*d(t&| zxhGwdmwVDRdATQDlb3taHF@dLHFKDfELRTe9$>zli02-38TW+1k)CtP ztxdU{TbmLiw>IT;Zf(lz+}f1exwVPW6KR_{PQlKV<9hHkkzF&-^`L4&oR8?2R5xC} zql!+-#T9Q)SP!=*p-;`tB=jloC!tTdKM8$G$Vuo^37CXFm4Qj1-Thgj=&EYR_dVX^9-l$wm-WwH<$$O)0nY=eDER**} zWhR$5v*^&vauppt=bGyUW(m@BvXl2l1!?l$YAa8A&NtWF%*3N4&rCc+QxA)BX-+&s zHf>T0<+3?(@7}aIaWB!-oVd4PYEIlrnVJ*VW2WZB#n#lEIFIzy9?eZqA|0@6Y|AAV zwdB>gx6DjA=L{U-U>Jk0QM>k0KTAJc^Voc@(K&=TW3`okx+1b(W%$%oLaGWY!~r zEIURr>tR41MJm&I6p3(o6!T`BUY5>dF>l7{rHnil^Jbi0@W`@gWL$2_>8^d2MI#G! zuRf1r-YnD$DtRpC%|gBGlE-4+EYyoLc`WA5LcN5OWzopO+|8Npm1kKrvQT%&^C;%c zLcK(kWzmRC?iN?CBpso<^kXAeSM_xKRihhsU7U^{jX3Ewrb*~i)pxMAzkT!Oouj*W ze!&Rv#0|d@0KG<)VbIj0u2~K}O8XpoQ~~DDBl6_Xqq;ta9#JQU9+lq=z4@zmjE;@$ z+OqAEmj3PAHf`CpW&1X@lW=DL>Xj=8*Y+>#TR{tE2b{NT6?Ly@A+We{>t(i>(sbI` zrfT9cGx4AofDZSp#4T*?T0~Z6u`Zc67BkdZ92GpNXl9~Xb{QMpIy$m*RH|wI=t8E{ zHgDOsW#^@%o1`A);o(}(UISd%<^+;5(y!d=C{u3wl`D=iWvO4e>?l*d8p^y5=m|6N z-mmP2nKF8^OBvzM-cA|hxGZoo8$ovBS0T%@weqGdJ2#Gu$!yaLhVe9oSTJKp?Nn5HyKsiK zQ||TNt_*EA1u4ffwA-CFx}9+7fpvyuC*SqpIz!vZ zcfF|S*RDAEt_Rr}+D^W=O_1*uC*Sp8JHxh)C_2Arf_olkIv2!LRJ(db`<%3(HQX>(xfT zWhc+|a-(0_$#T8k=vQ`fTrW8KmECMH+i(#jGJX^Ysf+;yY+N~ zKgdpQ>+Oy42!euaEITfAvQV!(W~n=wsQ18UsXN)ICn2)bos865D6`a^tke?{S?W$^ z>P?qf>TVWM-e;-DnZ&ic?sR%{-^oxtOOa*T$x=O6adcc*oE6B0754?y#82SEeFwEt zM`galsVMYL(QFS+Nz=0#*&dv-ruUa-dvHpdp54gy;FLGLD>d7LQ{wb&N4AH!%yFsE zqYH1TaI!#8d}JGUN~oRy$@btB3%xNm+k+b|&4poKmUJW$e+PQ#kd(jXnBv%BVisu}6P#QRRZ9N1ncdoclJgGxl8!O!W={iD;*!L=*~7_-EIqB+Ly$^b3fOLTw>9Yy zvu<{mrxNEj>t;8QN&CgR+0|wx&Q;dcqjg_C#gzoBQkEX(QJge(Rc5Iko_SSej_R?QS5>xGdSK>Nby7gjzW5R|CM>6bo_z7C z%G_+D+&q9($2N^_v$>?lU$e+{^zt3MuC0)J%0nu;My|<#=uy^TE6!h0sjgeQR4=BU z-?w7fKy}$F`&D{~HJ?MZkwHJL+ZRh?x%Rat2DfXW*HS!neJPOoZQXw$5uSQ%LyryKKj*o%) z;vx&R9z1!i%CZ!1*z{R-!b;`RXEkZN({$GZCa&)z50t#BGB@=g$*U@J zQ?K57Rb_5w*Zs+4W|{)==1fnzI?azB7kL99GgfcP^s35?)$6!kRhhAR40Na`tg`9R zgCC!!%vL?>@oCCj)x#a1rp#15&hcr=Jk?XQRCX*i6_>4-b>Jg1kQ)Z|h z%J?*8e(FVCpQaN|;wdlxUa)rAxz)!S6$oTpwDtYT58Pg99E#D)#f0qG~$U z4z3vN8}=Ebv^?5vmeAT%$F}Umx}pdHwUW&nt{mIBOSn)MXS%u2lUAwOLkOo)(Ibe1 zwvO!FrFJ@3sj;=+qz4N#tfjz|#Ck+9D_%}i$DV{|>R-*&qde8i63&zn@dBn=HMbWq z`8Cu^#M2y})%9d5jXh9~OyEHliEhf8IG|gv+NwJoY>(1(o{ooduEy(UB0iKW@v#A8 zl|Gq{OS33@%+V_A3B6G7u_>zweZJJAC~FCQVH@@Lu4`t0)z#5$dMQ<9-@1#=8|`WBP&Jp*f;gTDUuZ^J=je>aEj=mtGP4rnyh#0F{8(l9wGW1vQk8k{(L^NQbdpJd_J$?0Mf8}+=OZ(?S!F~IaD1k+%1D+a zJy!8p(nAxULsp9DfrrmWR*LA6h0jM;isVeBhe8H64 z$m-s|&qr46t!MOoK5Q;?XzhGW`&yJ2PG3tjm#G!eTC&{EQkL7{XStoBEYAqN-pQ0k zm-X#Z$#OeySe}sz6ig=-L=%}>5iKOkGg3jckF1}O3ZivneY;SzJR=qK+_0N!qGe3W z0tLrO1>G#VVt+4P@11eqDO$ud?0VwXqn}X{M03b?GSWaahOD1a66m!~WJN=mS`qCa z%QH%XXa!k6qa=tnko7Z4f@lF*KZ6gV{Yy(ihI!HYrRGKB$MTG15KSNJXC#AY_*g$H zoEe2dw0dkOqcCKc5lvodMznY=&qxN*-m!j0GKkiW^)r$|v~{eXQ5r-`mzIVMb0xko#0+$2ZfbGBz;0j<2*a_?ct^}?Et_H3F zt_2|Te08a(32c8Bz9e4)tOyF6-vw`OT&joG( zo(J3rJRi6TxEVm4nr{VO0Ne)L4%`9U3A_+^5%6N*CBRF8mjOtZ=DUHH1FryH3A_q; zHSikXwZJ{V>wwn-Zvfs1ya{+S@D|{$z}tYg1MdLd3A_tc27Gw>JSufX4czXSgO{t5gG_&4w$;JzrD76DB_0Vo0`pc#O}wCTVM-~eDIFbg;k zm<=2R%mL;C2Ltnf`M@E-p}=9l;lKjm2;fNIDBx(|7~ojoIG_bM9(Vw70&pU55^yqb z3a}7Z1e^+-2AmE&5I6%k6DR`}pcQBX+JO$B6X*iEfgYe2co1+Fuo!qS@DSi^pbuCA z^aBIHATR_h1kZ+yUGPybyR1@M7R4z)OLb0e1m+11|?&0lX4;74T}{ zHNb0udw|yguLs@$yb*X4@MhpGz*~X00dEK10lX7<7w~T2J-~Z`_W|z*J^*|W_z>`6 z;3L3CfsX+n2R;FO68IGGY2Y)!XMxWFp9j7Gd=dB(@MYj$;48pafv*8y2fhJ(6ZjVJ zZQwh=cY*H#-v@pG{1EsN@MGX7z)yjn0sja59QXzBOW;?)uYunHzXg5={2urN@JHZJ zz@LG?0DlGk2K*iP2k=keU%JRt@04aXDcslt+260d%-L4L*_+A zpae7n%7hBR4B!A@CNK*)5SR@d1k3^E0tW;0fcd~7z@fllz~R6G;0WMI;3(i|;27Xo z;5eWKI39QaZ~|~5a1wAba0;*xSOlC3oCcf@JPrY)F{JmpY1nDUI0>_xV4WV3{f5M^ZSf%5S3&p5ZQN3|OXDndvlGd1 zuv5TruwQOC*a0;h?0}UN6|ACC7_mb!d-IiBxB5dqGj+1Pu-rDyay!^8w?oZxH_-MQ z3nTWM(&n&|w>iWc3J6u<4Zs_LH=zze{pB`?Du}u{ROLt&I#m``!ByoMRZxT~C_=Ru zp<0Yk6-B5Pqq6~2ixH~DNSQ^o7@=B>P%TEN79&)P(K6s%U^%b?SP85GRs-h&Yk;-D zFt83-51bEN09*)M1UwYD7b&A=tVrN9>8QNU%u zR^W1A8?YVN0bBu$0XuNyb5?V@EYK?z&*h0fY+l*dmr$A-~+%1fo}re0=^A= z2ly`VJ>dJm4}c#6KLUOX`~=1HAYcwK7dRMb2ReXGpbJ<63`DXyY#)b+e%u^NSsCsu zOPU8;N=-|TrAVS~OO*JnSW;3%5RI3R2q8B_iQiUBN{Wc4p-3Xc-Vh~z+bk(5dPMdc z62G=ZyE)|4Q8uYL6e2sdlIFpdD!+jHaq=Wt!n&r-0#Lzua)J!)`d(0ZW=g4vuaP`Ppd> z*@>GgJK!w0!_9I#*eth0&2l%;_8WC`$RSIc!*br{5OsHxs`Cy9763<}4q1xqa7Kry z=oxm>OO5iHsY5-MzbS;3Y zK0;L=p{kEi)kmo6BUJU#IDo1?dLn?TKDrJ-RUe_MkDdyks*h0BN2ux}RP_<6`Uq8h zgsMJ5RUbVUxB++`a3k=1;3nW^ME9-0+km$N?*QHjybE|Y@E+j30IKRHRMkx%08mvo zeF*q4@Dbpnz{h}(1D^ms3499pH1HYVv%u$o&jVioz6g8?_%d)W@D<>zz}JAU1K$A9 z6f~hJXhKuagr=YgO+gcyf~M~SXbPIp6f~hJX!`%oN^WQ8UGe-w&931|kU z0n>pQzyZKaU>0y7FdH}sm;=lO4hH4{^MONvLxIE4q#;d9NYfJ1w1hM*AxDME& z-;nsVE!xeY9cgL~g~(2=q-n9G)QY#z;uZrr{Vm-B5OOXfLI-tb!k+zOz^iBRK2 zsBt3HI1y@`2sKWG8Ye=H6QRb5eh2&>_yh1q;7`Dx0o0-qYS9R_XoOlcLMVL97HvW;+JsuP3AJbwYSAXtqD`npn^223p%!gI zE!u=yv}rDIFfb384;%uZ#%n??+H^Ru05}3T5;zJt8aM_x7B~)Q0geYA0Gt4v2%H3* z44eWi1Qr3O0?z`T4Lk?95qLgu6L2$d3xG63(4%I=r+EebptGCp*hfmZ;p1YQNa8h8z$?A-&r4tPEA2H=grn}9b1 zZvoy4ybX9e@DAXez`KBV1MdOe3%n0_KkxzIgTRLXG(i!Xpy;E($AFImpFl)U15O7X z2%G_&381(&RR9#+rZ%7*=m0u_E}$Fe0eXQ40cQb=fd>N*0nP^cfF(dbFaQh!L%>qt z9AFu6F0dRx0ynJ$RspMl^MEzLT3{Gh2doFq2QC0E1TF#|3S10440t&32%ri)5*PtC z02_f#z$ma8xCFQq*aAEXxD40|Tn=mlwgWqWD}XUzC$I~+61WPu8n_0y7I-x97~rwM zJQcVecpC6@;2FR((bOYPO30JaAAmmse**pt`~~K}I# zqzt7YVp-B`+EQxjdn`o~bz7puFUpo-krcaJQKuzJ{Gv=szbKkggc56r62Bx6;@=K#;+b?w!Sd{p6(~!CetVrfW8XDaMq3EU| zbrV=Cd9Ryb)JS?&hfexvRtaLD3M+NtH#4Oed4v~@IT%)ko#P?<)b z0zM7g3w#s!7VvH0JHU5=9{@iDegym&t6!*Ci>O$Os91}rSc|Awi>O$Os91}rSc|Aw zi>O$Os91}rSc^M=D}XUzC$I}Z#ag@yK*d@_#acwgT13TKM8#TsEP#r&h>Ep{inTZn zpkgheVlAR#Euu0lqB1R_GA*JqEuu0lqB1Q$3wSp09N@XY4Z!n&8-eEoHvu;Tw*a>S zF92=>ZU^oF?gU;4ya;$P@Dkvqz{`NUP~pA-cq4$cDt!j{EGpL`Fb$Xv90{BRoC=%< zoCPcfHULPo=n!?uEZu(E+EFc6msMN4sw(q7i3sZ7vGEa8W9>URPa3adf07i3@Gn9T zAq3IqfX@S80KN!(3HUNX{5s(E076|vsEcm`-VD42cq{NW;O)RWfOi7#0^SY02Qixk z90<$?4g%%?bAf|_dBA+&5a3YYFyL@t0dNF>R45$<91R=;919!=v;fBg4**U8P6Uuz zrIUeEfQ7&!0I63(>Xl9h9tfNPoCzSMN)@0LSO+{7cotH&0KjH5Y&OGYbjX$4D)D_! z)e0pu{)PP0@R~ z$R!lq5(;iJ{4~Q)GjyAw+l<23Tm>EpjNk>7-SHXN?&`*|Ymp7AK-@cyf9U6G=-i%2 zqiv5iz;Re-8}n2ars3FG)tSQX^JVp*1M$gm9Z2jvkqWwyu!38`NE36@d#2kpE`jr*X=^9lqILI?rRXZ>`s&28QhM7v{3)*ZKiW_b5sdiR3BiPsj zlodANGI!V5hU&C|Sw2N|x?ZLZ-~ZPP)^@JYdDH{p{~kzK8K3OC`CvM$4?a1%b; zRi0+}6mG(2#{@owoAB8=fluKke0ELXQ@G8uas{Qg+xF|Y_t@@M>I=V?oA5VZzPCb@ z<|K9%M5&l#Sh!gFwjG5}*R&`$u7W5Xwt3;(b`(Bc)1vse3Zj(Q=7n$DQTTLCi(=#| zh|*%47rt#r;nOuO3X7{CN{nq@__iH|PseoYp2}LQC^43K>DzV`KHYbV(&8$J5@VYe zzHLY0(={zhi>n|?jBQ@{wjG5}*R&`tu7W5rwt3;(b`(Bc)1tJv3Zlf==7n$DQTTLB zx9zE{wTTjAnU}t8#|eE-R8rbRNtu4(>b0%aUEOHpZXL%z^oxaEcwiw-mtZs_MP*AA zd+qcIJ1n8H*U{sOyg_NV^x~JaSwgbs2D!r<6xAo>sKxf&$aQ#v>d{h*>?Z}YGj!ELz zj!Yu8<3rx<$dJg6Nz8XoTuZ#SOhEi7F5kH}n-Z^c6Ss6*u%1H}u_Z=)2v}ce$bOazo$c zrhS(i`Yt#0U2f>R+|YN~p~qZG2PU%d1+bA#zVY>}Etm`#!MeB{KC^>p^$$=Jb?OdZ z6&xPx$F~-mq8W*%rFe)P8q5luv3UbDZW+fv^phGDN8@1Ih77xO7BP_aTlZ*R^lfHr z8cokjsp$$j!_;&eCQfb#?f~utFhkz-BH+cqOMsUGF9YrZ?glUw*o3LTCQJo3VJff* zQ-Mvd0bUE-17I4j3DbB@Zvfs1ya{+S@D@zSdOg>!$rhr9<8dNLICTxjciqO zn^yiDWV>5#&E#f@;wDX1a+}9>*~2+O-Ct1E91B$?-KlC(AyTy{i(;>;I&_4pLS&(` zNBwvq@&-lKRIC@jL{*(EBzta)&y6wo2MLQ;OC14j!(z8QNA~(p?kLMUGE$YYHBI?Hrkz0VMA1}1* z=qvMWZj`7WFFd-Tr+&PxMg4doaubpI@wOKAOFTM`>XCkPO@)gq z)a7N@8ERWgyfZ@gSQlXbJ$4`zun1f@8aM{P4urySKnrj@@Bje21qvquCjln|rvM9q zMZl>5b|4h61EKIh06P#0X97slg5ujz$u$Kyh@zG(^)lY*rV4eY3P+4n$b}-}h|eUO zy)K_3PI}rFRfIDXZHrloxJtpcs5);xi%_&JW+}Ewi>lM-vj|1oVwR$lj;gchvj|1o zVwR$lj;fRCvj|1oVwR$lj;eF&v*@H_mZFo6s#EK;=%k}iJTjv^%Ho*niPWJHit*x9 zPsEwVEIvIE6B@<%^h7?>xW=a^!zc12GkhYYQ#~0zk$&d5SJhZF?k(W20$RudYPtd% zp91Q|0-CA<8puK~@F3tUU@`Du;32@-Kp(IK=m!RXL0|}23Y-IAd|NmdSPrZJumPd; zNsN1;XO4Rdt>X~T&lvZ*Qevs2OH6a5#1=f{lB4Sh zFLXWOh13&XNIl_&)DvDvMR<)7qzJR&BEoIBh_D+jBK(Gnh=buG;$gUmxEL-XKHhP! zkrU3i*KkY5y@n|60;&#K`?xN9*0`62s{cjfULisg>3Z$-2~`Ke_DthmA@T-A^;=ob z827SJg|9>PWQ52Y6xEq!z1W^==vheiJVEvbrR;iD)rzoYzm+<)?mKDRYkQ<|uMpYE zq-@c+S7_OhCoMNhH0~81-O$sx*VdwOuMm~3XseN@8eXuHlGtHa5gxyG91U36n~1o_fFhp( zJ_~#f_&o3h;ETYQfG-300$%~X3VaRtI`9qPo4~h#Zv)=}z6*R0_&)Fh;D^AEfFA=t z0e*^cFKU-&jF+u(@2AHpC@dw0J5pk)BPFIeQc7<}N~!BeDJ>l-rJOCr=#pwPN9qYL zbUopP)DvDvJ>iAa6JAI?;e}L$*BC*HFdHr++=hz?yWt|jZ@7p!7%n0nhKq=c;UePW zANO)jxZ_@SOUJz|GRD1ywDiToE)+x-s{R*^dxfZMX~kYUeL~fNuszebSBO;KkVUaQ z)o*o#s`+Q33LlMog~%He)tP0z_$8`i%|f#039>gRb|R2hPw4EoDlJ;?wcknOURy-t zULmrRN!g-tuh6n1Pg-u2XxuA2x}m3WudPMnULmqmLXAAtxR;fb#16ZX*hNiA?2s#o z9dISFvqDMiU@M86<}~i*08wVyp;jUq_u5)C?iC_C;N;N`If?9`lgJJ`iR{3W$PRrn z*0W!lNZt3+xYrIajeA*?__YI=NZl~fxR<@FFw(e}MTuWKGKtiV4|%sELn1pSiC>$Z ziPX(GTJPlmkwrTuG2iWiNqTmuN#q8Z#=Z6nXxwXyXxuAAcEMNXY1}Kc?C6u0oj)Y9 zqeLP%^fd0Z&C|G7h}=Y^aj&gK<6a?hGmpl-Ldy+3jeCWb8+sb|+FCU36(TqEH14&v zXxuAAZs=*;E419u)3{e?xuK_VFKcCtdz;2lJ<`uN?qyeV+^c)63viGat0+aRq7-qA zv$z^K4_E`N1%`ojzrBgi_K9PRvXg0nn zv2DxFOGh{9y`sh)9EX^$>Yk2~RyxT4$?=%w(SfE0gzPd)xx}B5w;T@MxP4@7=cqa< z-aRnbNjYWsJ9^XD_8oLRxiS#zwpK^3*>KH9)#CFT4$zL$Kq6MPf}uT;UDc$sT_b>< zYtK86vfgk`?5jG$BUVH=#1p+%wb=aHi8NJ{!k_zyZTuT?eCmS5z}88=Zp;cj-3Ia3jAW z^DV!^&G9RWgymPbIetY!vHS|R*;}^h*d|xLaCKlh(Hs3vWRRWaZr{9l=V+3KbSTBB zVh%K2t;)xon7^0mC~QG3;t*BwwZJ{VdjTxr6|sa@`~dJl084m9Ea4Tggjf71@G$^O zctuRI7qNs_#1dZd(*P#;i=PEB!C(A5@CD$Dz?Xn819)TcE5KKQuK`~NFu`BM1b-0| z{6$Rg7rz5wg1`A>09$997Xpg_45^wiq-w^Hsu}HJGlo>rG>n<3cobhfPLWAuD%+(@ zC9WZx8Q)H&ixrgADe9yw(a%V#BaDwz(HcRn9fiTE6--tak4RpE1>+QH{Q6@t%! znC)@Uw`ceqM2e&_Z_SE%tBARA_|C`)V-un)6}cAcD!Z<(N={d*($bZxgmk4U6@?T_ z9yG+}5~jicsVHNy)DvFldcq5-C%lk)!V9S8!jRa zhKq=Y;UeNE0QaV=w;}E1T$QI#ac+gH*Spmu=+c98*PRYR0Q@ z6nFv~A}Q&SD7kYK)f|43XyE$LWiekPYp4IXz+7>CVJc?rEAJ1y}6>W=@bsj}AM-b0y z`4w%8L^F?~nC*yXwfu^sc+2o`{KV4m^4?d?NQU!zc12)sx{9DV^%c@QL)B z8IOM{9gJ>fDpySK$yIqa_h%2#PP#M3;#skePWftf5bsC~DY_f4PQ*fc zUTnWy-FXErTpZbSt$|2)5?4Yv5a7f-S^b@hrW-}_s3^VMYvdC~q3<>>2 zEVR=;E+q$d^-?(n(<7&FdgSz4kDT7?k&8}g`rfQQsh+Q4LuuDjAKPPxBh@VDw$V#Q z=u%vDhsU*Q)@EtfxqV14)|;K&O&cH4H=O2}CUk*hf3_nPvMfg`Gg*!z;cc@b^=(Iy z1-7He2is9(hV3YF#C8cfY)Ty^g(#cY zRiqJRQ{tLtlbYx8Ws|LFWs^DKfGGm}PRH&%tmc;50Zhb~Flk;wN4k_sMlzM>& z0cQb=fd>N*0nP?M;?feJ9~b}zfgxZia1O8xzzMk0a$p6p5?BSS2F?Spc3Z;QZ3%0) zrK^Cefom|Ca4c{f&;lF}oDW<8TnJ!2*W5)|Y8{7we#XGnm8x>(N>zb!rK%*kQdNXp zsVY0JR23Q_#qdz|qFt%VYFFwBFD!V%3#li(kb1%ksVBUUitrjkKoMrcMTFaM5n(r6 zMEDIC5eLIX#KUkAaWPy(d@@FpG;lSNexiY^q2>-;4abaE(ZJPEvu%i^oM7OZX+osA zci?Jxb_TA7+kxtKD6}WZd3&xW)}y3?izRTe1TL1q#S$h0OBVx}2rQ|RjETS!_EwZ0 z35)>PTT#N^iqa-v6xa-00$d7UFkgBUa2c=_xE$C9YzNTuD_sGM0XuXPPl0K#h36YIvQl3*z%x+A4@bfi>n9VwMrM@r?@ky2T8 zq*P9ADcDGybEKZ|Le~>sNIl_&)DvDvJ>iAa6JAI~cn!vhFdHr++=hz?yWt|jZ@7p! z7%n0nhKq=c;UeObL0(-?aE4^4X^yj+&2f=HwxdX+i7EiLf0X*nfNy@Qx?MHotZ2VW zq`JSRV9#z%!EWhK>w%{MPY0d>JQH{!@FL*Fz)OIa0xtvZ0`89XG>=w#EZ(Vq6VIdh z6vYgOo=3}2wC7eRr9H0}a}9bP&1cb>|Dm+@SQN7odLGSZ(V71tHhV0J`4v5n=CcSz zJJwVScq}^UNR@(L(YBbS=%gc6CLW7UI%X+4=}483$D)&tLh(R#CyvujFF9rN$-yi|KNCC_{Y>yE zI_XFS+^=Y-W0s4ozno6;G-s z;;egH9(y7ty8q?Tli?HfSo&TWK2bZRdNO>X&PnxT_(V;T>dEj4mZo|#e1dzao(!L0 zRH`S#CwP+T$?#G7ae+zoWcWmxPW5E?L`hBcWcWn+n}v@iVFwQ;&E#j3=xa*yD^xSo zmYFSjlI)XdT^UPNQW{%x=EhUvquVy=Evj(6H}x}A-t!4n#y~))bW20BuPU#+7$7z1N_oWg~>Blox9EG{67dtkp zcF)ib+=>;E=_}T+YuC497sla2zgXCV2Nq5v%}$TZ)-x=&kCQq4V_0M%Ta+?ok!6O( z%|44PWQ$U!EJ~S*%dM$F?N{ls%pE7_mG&|chNo^P(rQiZPoQPoe|$Xe_M%T>VG5FR ztyN9yuNzoOXXLm{AL>&_=!^n>m``P-)zZ-^+}Z{qXLy|Kn74F<;_zOqi9wO8sRHBJ z?Dh%mx9jZiy<8mQ(Tcuz(?=ip-CEK2YKpj1-qgFLP~6sIMBLF-5tl-7*GKGKMVvJ` z;w+05Ri?3!BhIo|vFuS)5toV-ai&G=TSZ(7DdJK{TPmfHZta&sak-}van|IBv&@J% z3pwH}Ga}AHt*9c-GOb7vXP(EtRm7!`A})pE(*dzfRkJ#pc7+mas{C;@RX81?DjO{1 zBw|?{c2zc5$VtSqSkZnrClM>oL4S4h@*TUb)nDbi5|(cn$3OHFj>;N49_#(KCO)pH zHm-`5lnFNLt4MPlCmS$Kb{Z}8oOsW9yRIiycA-s+AW_Hr=t8Uk4 zitZhUJN+^j8PG%+b9P6W6MJ}t>Re*49p)IT2yi|{q@FP`mtj%uh*K81Cy*7w%WZqd z_(Mqc6qgK()VD~^5FjGUsxjw~BHT|odLnjOnm&7zVsIDCac*U#j7n=n+1S6Ap%^Ej zp*T?z8ftq=LPPafYYRUg98)I;^cQM5KF4J1$`8rLm9E{@jD;$ZBnfO;tmtEqQe^fS zijL5yDQ@Z3q*RJrK^P_-p-)p>fW{`d4l_(TLS<44#o2OiPxf-VVra3lMjt{*c00M% z$c(;K1Nh7wby@i32hdH~SC5TisVr(5$3OIomBmr^L-ae+UAr+&jNyU#5>83$C2iyJ zJ0kNXteo`{u2amHa0#$pGU|N^D`&jK7@U}a3pye)Jby zXoyu=x=yabO)zpZ>`YL1m8~!won5a}3$QLtB0FeH+6ULjjRdoG=|fz**RNb_wFzld zxsXg05!Q+qtTvDA+@(^ar>Ez9tCF@u)ppK#Lli2bE}h^#hSq!?_T)Vs18cgFS%$() zR>O_ z#Zc$iRihhssX)u%9PU$;N{3MGOJ6ZiiRm$;Z?;G@r2pya;{fnw1+fUBB{*6K#maLX zc%MaRQF_AO(7eZF_C4V+L9RvN_E;^$3ga`n2zDa zLURvxX-{7+yFzmhcGaA*kq{GvS7`3Ru9~yXXIE(M!LFJ!&u3R??!m5_v(IN&XzszT zS~JLJS7`3RuBdS)$Ty+62fL!Go4~Hn+=E@gq6zE@%_BX0^HmOUoom)jPOXq>OT5!- zOXwVt5iUXNLtQn={47g?$UaL#CCieauFsNC$+9HK>a!$NvMdRD`YZ{REK7orK1)I+ z%aWj=&yrBdvLs07vm{iqED4(VED4n?OQHb#ED4pQ72j}4YjP`$qMj&qhr~skwWLOd z9Z}{yc7#TT9Z}*uc7#TT9Z}vqc7#TT9Z}jmc7#TT9Z}Xic7#TT9Z}Lec7#TT9Z}9a zc7#TT9Z||Wc7#S!AFC3UbZ^_lyXG0C5IPr2cdrfc9><1o_t|I_6~43~-MuyhqZ}K; zeW8x4+G(}n%59srj?$*+Dkgrh8m=$m*|Pm&eXySUjNUg3hBdISrElm zS`f}Y3!?Z*3&PoFK@>h|K{)#?h@vMg2xp%KQShV%;e1NI{*^to<9n?rtMawNIp1rA zC*NyD@s_U@&iP&|JjJh7yDw?VMU4wZKE$t0RHU=dg2)GHK{)#?h}4l5g!4)Mj81}F zt)Lq%y!c)!(nh{iIL8zEeA^pM9E-%8uS3R4GWq;gL<+f9go59Sh_Y)%DEO_2XuDQ~ zLY!>LHJK<;*3{|jxCYj@Xj)Ej8(?fua!X^}2BbPNJ-s$WYB@H9yVr(DE60X#_u3FC z<=7DJh7G;6=3%E{gLEcH54IuV>(~(P-f)QcIyQv6*M^9%V?(&dHWaOs#cyY^E4E?k zSY^!MeX_DHOQ^wnzJ!^_-!V(n8&rz=7tUgqSV~qnCaAJft6OkX*;sUlCs=q_z7zSm znp>=4`Hz#&yf4zR5GS9hW7&w~6}zkQDEdEhbP%+HbnMZN&V&c8_R^_>YYl`j;|4-h#daWsW37P@X52uCy4((gaI7^D z!c1J@(KeE#2PP}~xWY4atO{@OYw=^tX zepq6*dcoRd>-@2v=jvE5J}L9XY*f59jZG3)XK8G1`chL=k}xVrx3l9=sZ zx_bPJZk_NiTs{6pk4*R%t{(rQGbQ{BSC4hUi+ z4#K~1_4pS}hwv|4J^n=r6aIy(>t8N{*#4!f$G<3H!oP6!_!lKi_!q7o|DuEm|H9Sd zUz9N6U$}bwixMXM3s;YSQNo0O;p*`(N|^93Ts{6p2^0Q>tH-}6VZy&~rG|_SyvNO) z-2XMls(!`7g6mrpFWa|pbbX7$W&0M6u5VGaY~RAs^(_jP?OQmyzD2RJeG5m|wZs})oi3x`8wPj9|Q$?9aB?sPId zKCqYH9W5N`_894g2N{IJ{CZX>&h&@EcYTB#kU6v;p1RU>62P)N%W$+DW|M=yO+xg) z^`Ri;WcfJM-FGiH9vy6{INd9s1(B=Lf^ha&kbNj&K|1>^h?+!N5Y9deqBfBhgtO0r zs8OT^;q0>@Y87cgIQuM!nnhX=&OQsGc99l@v(JL4VWb7&?6V+h8EHW{`z(k;CoKqP zj|JJU5*DPh&w?m)(t>dISrCOzS`f}Y3!>0T3&PoFK@>V^K{)#?h(aeV2xp%KQRt)v z;q0>@3Z1kdoP8EVp_3Mbv(JJkbkc%w_MDLtoh@-jO1OIbixMaN3s;YSQQm}q;p*`( zN}KR6Ts{6pSrh(+tH-}6X~Ms7_4pU%O!ybB9{-}03ID>?<6o39;a|AUN~R6valh%x zK?+%0n9C0*vT_y4AnfN57@ATg^EjJAn zZ^q};aP_+V`_!i{8Qr#F>t*UT&ok5#-Ns8twrv~TinZ3w+i5CR&CZ>vp4wXBOi#lr zmh}(fLWcYBi|8R*+t%6N-q}Z@B3`k4zJYz6$d#nOSd-|jNhCvwWGI#tmkzJh#-=YXFR!dzf1!Sw*1uwT`q11znEpL&#qiqnp|pDF z!q{T-(1odZ8dTEIDxLUc%`5o@%`3~Peo3W}%9dhOM0|A!N*4^Qj{T`Wlh<6(mx`O! z-=@4(`y_cATZzTWN-Ujr!2rJ<4;(B!w5H+0LtFYV9dBb#>WO`+C-$bE*q?gWlJ!Gz zvf^FlL#z4FmOjwCtS9zG@3P$3U-Q6uYx`Cvuj=O6V%~5GTLMfhF|*VzdaaP%kP(rKmZY9!-m8L$gEAY_<#asMJQRDG;THq};1^b$} zs2^2fNqJl0=ZfNSD?hiY=UZ#$bzEnfyzY;A9YuF#u~5-*Uy`p6KTSUM*Hn>j29s}k z1CsB6K)$+=uZ_t@y^DJ8R}Zm&*ZvQ#K9rxA%wHTQ$y{`q|q< zxotb70o%620&n*VZ{_UmYHrJ@Z99*jscm~<&Aje*d7aGO>Jev{K+0M~MOSqJ)A{fQ zr1KGh&UK;l8m2GNc`ZK^onKTloqJq5hxy=qdm=#RqnOS|HXxmk4s@;yorjseMCWz< zOmu#6&2+{`$|y$3gfNDlVL~|nOwzH;=VKa>&&LHm*M-mPnZLy6^ZA+h{F2)FEH*(Y zKKqB!Q?m)`eljC`JoC7v0eSp@z~j2`_yXoF@%Tc1CLX`Eb{^ZCp4!XSlyD!f!{pk~ zTl026O4Wwm#(P4b#(trOoCtnd?M2_-azsVn--J!gOt7C!Jw3_nY){V=?X7KmGMyO6 zR2MScRXdsN4L?MteL4M_MW$qGvgC+ydg^y!AX8n)^vc@FWN$DbG9@FND7t}X$~}0yJ*Q}5@8Zr?;zQ47qgrm$W#|Hy{2|DiA@QL zOi34QU+e)6Jc!#IT}*G_DEivbav`-^qEm2S2SI#1x#jP2&Zj1SuTDND^PHcO-3lTe+!ws`Y zx}BTg9^!ME&&wK+&&va!>%wQu-X*fCl5wB!EuV_F% zuL^vw3!l$s{t}-to0ssL`24Ke`E2hXQhd&s6`q=lOY1f(%&R<8IV*e~^Lcdx@)`Hl zhdmQ@*fX(&`AdB6=V#*cvuo$Gy%~!5ye|jR_mf%SVdnAL2IMg=rVl)>1CKEqpR~io zV@y0I&&1>B)Xrmj?^Ao5(Jp5l6A5=flvg@83*pZ9K#l!C4LKM5+}ex2z43^OzP|~Z znvDus$JY7IyKoV4e0CQfObBGE1DS59nN02Wt{)7rR|l(YHr9>d0^@YQ`tGr%k~}xA)wRgxiVYcI2UfOm!jC zO|_Fr>@ZPeN=7*Mn~R7qZooGS!7lx7SRj4zZ4}$drsn0-5T12ls|Rrn->nj@rp2*6|gYc!bl~ z7ZGo4z?tGrfkFF)L2{<}Nn)n>&V*6r$zDXQ?6SWev#Z%LAY5!spq{U$u{+co07mpLf>IXM0}* z@p)fP^WV?-yq)>HtpWMGBk;K{e4fMnB|gvPXX5j&+WBm6)=+%zOtzBi_IYYM-v0%B zp2|xs#+c7nG$5aM20qt?&j&MqiO=)+nfQEV?R>U(pb($^1L>(b0bI9BEb?4c9_7AV z>PqJEt_I}sRe{HK;qiRtE%EpeekLAYRXdOE?KFzVZArTvW`%2-6}~!V>UI1z3#8G!q;-^c1;7eZjTPc-7mzIv%-tGHKW$;RDPz`?V6g2-Dz*h zAz~-9!ckPWF(UUVr*aPWvCO{5G$8vP7uZ)9_MOITBlexn&&0lKYiFOmhlkh~=5TY5 z6(7%h-razF9uIu33!fjz{3Sl0!Oz6!N7v40cLz~>GFA+8xO@Ciz!RCzPiR0sV<%d; zzGpvN-y?g+XEJ|@&t-llK0l^*KD(Qt+V|zKw{CN|c`g>uKZpBd=J9n6$m6F39@nK^ zt}t(j$F2NKJbrBLJht~fVWYe`hwDFc6)qz7T+{W`K#l!E4LNiBxY~=py-kRUe$s@6 zJ0K=;2gLQE=+~v_@2O!U`)J`UQ-v^N?89nTaLql1e zvT*&0^G%><1~S!!Oi!$tOkMU~3nCMbM{ZEJa`yJ)a+{X5gGG0a#fn~#eOI8dHwCGQM^y0sk{y}^;s<+azVt6h60soc7t>*+P>=!D?3Et~!FZyE7 zfhziT7cDtAHZ|u=vbtz|cWU^aPfVug1~S!!Oi!+zOk%-bktyk-*&BEQne=v^X6ktA zzo+TWCtocex5~{!7pC7dou+%FtP^*Nn^#s+o#vIEN$48_nd(BOr_@d+d)2*7kts|< z*YM?q=Y^tQm!kjF+Kaxu>aL1@SF#Z_YdjK`9zC`GjiKn*rRZN@d(pR7-KpsN$0Jj7 zR4{8i!c)d!JQ9ybo*&3m7cxDqb~4%P_(Y~;JQ78XeaY`l4LDPLb70VZVUV0D#&uU% zTWDUjblCvS6hD3Qmd)F%8@F#A-MDM}Sar*`ox9FdqV}@>dw9jN{=sUOy%nIXVr&Hn zS2xsjb;An+0rm?4#Qbn+eZB&3FV|Cn-HtgW{9GjNwzmloiMh{rKf99Qh0L@&8<1%)3QVgD)BeoNqW<7t_?eh?K|ZF5 zT?49rm`qUbi`{K?<1QcXoXYD|Uc%gcaRYMqrGdM3;qG6VtHj;E@iTGv!hGBn+aAE( z^kXgdO6}B4GyWHFcPg*Ty^Fc~vIgYt-GRGx;qKp=tHj-Z@H27uqI}#HyDSuU_vJA4 zesZnCE10t{Z$QqzGH|vooc$+rlsNk@ekRU7G#_WhW{wVgRhn0{m-FUz?b8A`@8wOS9$M`E!VMUgm}OARwTy1gqbPnyZ)aWkn7b5+z~uGcYl?`c5pzCLib z9^5S%A5l>~&XVzQ2IB6+^Kn<~eNo&Ev$MG`$9*Gn_YDom-8Tj9)`h#qhf|2Vhle}+?)nG5 zQ?s&iKbf6~8j@X%@h?9&+qUe5d8SeWV za3c5vfj0YvHsXqdXeLkm(nRnj`Di3INwis49QeCgVdB>_KKWoM_WPyS%ZcAh^A&Tk zpFkCJe>ZDtHskt@$XJ`iU=AOHApAWmI~ z^Qc_Jsg%W%x?)Z;^Sdv$j%PJFe2-!HNI~4>d?YZZF3hGZPVUL%j|S${g*jVuGDj@aE9Th4oWPtqEz^H2FsClexjZLx#5%oVPBPAE^ow#o z-hi{np9pl>FLaT!$Onj7@5il_?PdQ8K2u=qZqc6( zq%RWErw5Ij9XiV8w$q34fkFC^U~g}q`f}hB`g~yeAwl0A50n3-Af;mC-RORS$BNUduEx8xxjJNG^N9pUA~y8_nYa z%?LDOZeT`q09Hh2MF&Q+ql2P3(Og^zF)x}Q9TFWH9TpuPEr^bYj*O0qj*gCrj*X6s zTB75l2Sg`CCq^elCr7753!`(q(5f!9x`zo= z1Fh^007R=~;Ik-F-9y~K5UItTeMzhCa=9y}Rabc^(CWVXqLS(^t4mZq7id)%TD@+s zXk~9WAX+7>KT$Nn$Y>;tj3)k$=jQ_*>OzOt?-d>FZ3L~I{jKTu48zDsZyfk<*z^2_ zK(4xw>kWHDu8O_WfXKxoBXuw{LMKkGmF~+foG~)O7%6n&%r4v)1Fh;pt2gcyt?X?G zL@OQ{DO#zK(Y~gYF)}K5g^>}85s!?%6lhf!TD@tnXl3tFAXFQ+`6g+kU9N zlWsqBFY14|{rGwyQeBAj)7pq+ul_3{btgO4B6ACj>@oF}lOB^ALG}k%J zz)IL-uiX=SlA-k?><>%ULDYfFY5Q#BWp`_PMR&0*_Joa>Xm!37cvBbNyk){xr`2AT zC*CAu^F>%Y)C==^U*%NrW~Fz6mw8j}?%>k^9^Uk-12_MB^Ss{<+`m?(F{K2)={=pVCRfUP^mFi}(-j(H+i4MA<#{Uj|EGAAP^|{3| zgwb~!?Vu+WydusY#fzO646KeT%@Y2Mqt|>vUn-`*O?kYSO!9a^O?i#Q>d#m@?ScWm zwG9u($D1!0XywJ%3kKTKhv|4Tds0vAOFgkS^~C@1@-*<%E?BEdo_2}Q+7wYjnpZ7dHc-aCmF8RdSzQ;{jPKMY z?&`ZS%{wNhr@e?@sbD`RPr#{tG5Vqby*p;_598eKq37=YQ~OTqKXu{m0sKF3>cS;w z_bpnKG8B*fM9~USl(|{~SBbDZlec%&^-vY@|9(`!=TPzcUQAW|`9uE1(+>hw)lQy3 zRaAkIplXS!sHj@{4nNb)p7_QP3KLP8sCorIw<+rGoS3@yz5|?5O=tY{T!>=s)b&bz z4eOFqclXH_bs^}yyHB;WOX}IM{>a;~{y4BTur+B*1zTmq`a)(SHLUm$t;N={U1J-n zBb!Ec>>3@jPLH?RTNv8g`@2(SM$rbN1*FETx3_nAU~zd;olkUZdvWPP(gE!ozGzi{ zzCI`Q)bw|~(?6+s`)Qy?phgBY#N`Uj7kTdDi6(^VGjFr>e}Q{}dl}pl%~I)~+ze5( zbOt|DC-TGzxG8p9bYPL#oQqL2G3p@1RL#ZQZ8UYsTnxI5Y7(ZOregX}#k@>kG8eND zT#cRam)4*^KxZEI?Rkm@voP@-%~UY<=U&GCA}}^EHXmb~PiBS^W6$JgVr+2&#)@qn zU~ErdtY@Nz`m*sv%`d%-{Z(LWU~Eptp27?z#+Lb+7+acvvGx{~Hrzki&HZ0qWS^=t zyuLOT6ELcc)yo}ARKM41V`FD(ZD~P7HM@F_HTN>e)V8s|_A>T2fw6(HIT^c<8A^<; z@G~*Cc>>1T+hT~Zys0cOHf~zu#k#nS{jHa=zYB~FjLpedwc{*a{2<1*@-s1ZS~g?b z>TA&O%g|IiLtzePF+nHW}dLmz;0vz=w)crb0~NrY5FvDWz}|R?F5TlUQrwS^C0IA{mM$MV!;o$C>JWRXQzh zg@bEIhG<_OT$8PEFH@8#{2+cN3eVwZqVU`aC@i)~VL`|^#b!<~PtB%dFNNLSa(u>A zorsAWXzEC-2D*N&aMQGe!nj0U1w-{wW-x`P2MUK)IA<$-7E_ccyqKSf!Uyv+QFz`2 z6c+oY(2+K7(M>2kb+cDBP*_iHDVm=)P+tnqOelN+Q}{rp@T@@LK;fJeelSy%DEtt9 zCJN8zXQJ>S6Hr)eq*4?%H!JJ0u)5|!O+oMd1hkjJ6OV;KVRWRGPQ597P(tC^OyRjq z;W>fAfx2#LvV`J|X{^+OmraDsi$b`a2Foln13Lh0H94MTV!b40^qVQ6FCJGh>M{TnHT)n*UctA#)6KAm-JLg8bW!YxeU;{t^Pg>zE) z9HuByco{zvg^%H9qVTa3P+08FQmrtLg;g7@&IYOlrF}?YwdPAaRrey=TRU_|T3w)_ zoa($T{D6eQ$1{abWD1`UC>$u9lfvgRMTx@8`I#tu96u9CY(rCZZE4)ib^0R8$N=M}+tl0geZjEBX>JKv&tk z4zWQA^GlscV;V(|GnlmZld|at7rhfcdow5d5a!T>1BU{KGB_mWWJ|_v5yYYHob8#j zBdD!2+0@rKoatlEoER>zXU;4MoC%!C$rPK$IeW8-jUC39v);7s65PR^|6wNv8EdHFcg>27vN z?|^6=&a7t6tO}e7oXN?VHG(s1b8<%PH&A`E#+w6J!<;!Ua3*jjCufEQXV&H9jJprO zm}_pB!&$>jnzey6fiyWubD|*4NjXX5ZUjib)6_sG8rL&v)&xB~!Pfpi8j95sY*r_rh9}x%{2$?}hdEvyT?eS9a zGyJSh>=gga&+2qt@jp3RId><5^{ozl<;4HYaoCZBu#aTIZe+r42!suU%}LnLG9lHH zZSiybOoY9UpXoSkl#{Sx8${W<(n+6D!Z#V?1F`$2g{33wNefH2Ptfr`bsW}rF1FG; z)Ux-7V?AeLark#MA?zk5>?KUt&4I9iusI3)c_t(g_6z(>XJXYwF7XvlMA$+;!gh&0 z7>cmTI1*O?()}>eKJF6J`Spab_3aXGNeFu>6ZSGD?4tr<17UL#_KQqNBJ7v=nFwnf zdMCn`auQZ-00CjsL+xq|tFH^5x-PN*!UXnXB8FtCt6^2Cims)!<%P z^?tw1+@uYR&HPMUotBfEVxtM>m(tst8fQb}4(8DIz@fmQ3=YW)CmzV0Ar769lQUwU zi8=_}c!%f5m@`)d&IHcnC(HOj?CyO=XO17`wfa&o33IMbSw zGh&yC;tcOHX%x;}#hke^a3*jjCuiCOXWDaeMr<-sa}ABxH@k*8b9LZM;7m@=bO_FL z=H!gK$0YrjSL4h9JeoOkZQxAcOis@93C=9Z$r*Q>M+1&$9?P70OyEr5Ois@93(gGW ztIrI3ynZTKx zoLMS3b52gqi2VkNGsy;_#^KBpnKMraoC%!C$(dz>Gw0^yjMxW&?<5-YW({*V>pCXQ zlLBc1X>yWgx**MroTL#O0YI8`Cu##-IPnxF&65LZ0%>xR<^VyOnK?-#b^<8U@Q9{i zTAJ&bG*1nr38cwMnpuK02j(P=*b1OX!&?CwhBQxS(mXAYCXgm4X=V%3Fohpz_TBliaBu)q3kQ{J*ZcIs{X-Ne@ z9UgpMpk$zAPD(zMDX0$oG(Vi56(yU`pP-Etn-@BbFPUjls*~r_(LSoHBKH28h#So| z5?^ROr?Plq|7pfWOp1=X`!pX1;@ zC;YsTo6MWJ$-F7>Gw?HmpW;rY(m$AwbRf^TgNgX5+CJmPh~}njzV?WX6N;~9BbppK zSA3m51$^CN^0f@UmKQHn?34{<8F#lV9bVfzuxz+*$%?^&mi`sXSFXRX7yq^N530Xv zV4>M@y~W!~-WpgKSeU^=c`Wu{%ra^v3zv*;+pzVr%Eje}pRsGx#_GmPN49Mn-C8B` zZNGAt?!0aq-DveP29T%$Ue8I*w{h_m>F zWvkAY>_MB^TY-(Z9qSvuXjOm9%8Fvx%1X=1GW}8ZwP`7v(vBt#18?Ux?Y6+Cz@~g` zD!$leQ}HFWvB_R)?(FWb82il|kWF_oo9+l~3T(>Brk4sfy{tAi*=x|9o&A-Lq;nWW z4alY!F`Hf(*c8~5lTCLCHr-tto9xAD#U^8&tpVBe5@yqj1DgVya7th)W#-zX`9AP$tmD(=D~JN$iDCZBsIC;=^Clu}!vlN;bAX&9hOK_Oi!EPH@0P z{WWk}-y$475ywm>*gZSJR>1t*+0(6mI9T!~VrAS9PLG?sIS@1uG$%n{DG2)P+6ZcI zujuILZ#9Numm72{H)0%bBNV|)XYK5O=zToh3|&)ZtD z72P;C*;=+YPT<&NTZh?@scr81gw`}PW_y1^%bWyRo}AD++c=?B-|vFHEjgC;*0>!* zllBhoXuds=GLSNZl;T)c;pcWcR`>-!t7BP3<69l-yP(DPy&$o@Uqg|&-6XL-`>Zb_ z*jFU(I~x}fB=-{ZpFKr~D{+1j{ZKmKYd5#GQLVVtboNJ1*Wyw~6o?cFKVola(1O%hMlr9e4IoZJtz zm)9KBMB)!6B>o_i_#;f>4+jzl66YlGZ<(Y-;@|Nzk+_GSiNw9Nlel7UifPB^@Qjui zBSKsxRHPdare<>YNycnc(u1b%w0p)|k(keS4^1$$8=vgn18viz-JYJbIj#Fq=I_Uu zzaI8jnYxW*&Vi@F?&oCy#~&kJjx4kL;~BY9`0nYSSp~(Px=Q zp9wq)Jj%(V^@2y|?*)(SO*X1MGVbqh6drw^dGxu!qrjt_Ji0*e=)%3=k-Zm&<};Gz z!N&Qt-xrxjUkE%3Jj%(Viv*7zx)(fh_sSSo_B2X+^kwGJmjaIhk8<*8RPbo?Uhv4> zuJZrvod;ms#?^o!iIlVVo=Th{TW&&-)NIvSA|;!(hE2(qT_s*V`xk_mFA*rRVtj=n`45l5OF?LZtoCI&|+Xam-JeYpar zaP%F?(LKZwaiq!7<%px5^>dW1j+-!WT=zZ6(RYa>;z*ODD-cJsF*s7=8KD1Wu2YWd zjOknZ0}0ai2_ynZ6Qq6w(!*nbqy{wPdLS=G1~eE0(vKuaKO~R{Bu$VWfk0Xr10*$~ zfm0SbfK+*(h0D&|Z10*%10pb~CXt_Zk{X~NFV*-gl(gdl1Kq|%n z3B@$9Y)Jzx($6GFKP8X|Bu$Wp5JKbDa4wBw)1Z4U8?a+^bZQVfXIa1IW! z7}7F`TR6t7@p@y@j)N@mpudWb%t78CmiYGq;@?S#|0p5;13^p>YeM`}2`Pv8XL6fE ze6rl;5T6nQVl|e8Lo8zL{Sdcuj2EV!o&s@!71!g11oj8Se-aQsAR+#Xg!s<{F+r>e z@y{is9O7TdZ4U9Na+^bZTKy2`)Ib)tZrJ6A*eL+Q5N74L;zJx%0Hnw)adHZP{8jS% zcggSHh+pD2gkM|$$~96)pg> zN^-=xS{;KUHC~2uB;#dF355Q)*SXG`=3%jC*xl2zYNBlMDyB=;WY*ZwMZno=EsU)3HqwP5?{%xwYrr`w zH9ox2J!5)!qdW%M5sVjyaS7xRR{F(PqTaMKL&1 z!&MkZS@Xtq&=8CDj$`39Y2t{+b;9D;;OJt+(W7HxO)^Vc;WA~`ykI3kWTIog6a+FCzHd3R1bF;XfFS!F&yGH+aWnB?eC z;)poXXgUT*uH(n$h^Jf2ah)mY*3CyqkPau12qaCA&O{)!#Q@25j|z}jy0tV& z#(;E`1nEcui9pf>=_~}&*)c#;BN}+!0y#r62Bc#oNJkS$1d=95OA$!t!~jVRY2YBq zB_v}&I!=OgEP+HIX@Ybv0_nUMAgM78JV(R8InoIdq~i%B0!b63^ASkxS|IUhP$ipJ z!x*3fm8_k^auh{+Q<^6@#ZPaV3+Qh=*iq!^O_@I4(m2z%t}UvYabI5_1nu-MEsbq( z8ynkgPOwfN{AqJya@fnt_=cf!1-c$bH#BZOk#pzzS-f@JlL$dVP!GY>UsMEBf73#6 zZhBi~$LyZD3tbjFRTjH?3buivd8bM%b_yXx2Pga{!`gx-P>`oFpm>QcjpxD}EEIe)pb>bfZ4AebojXWG`;;7M4=+zF8U z(^o7_3=ED872BMQALc`d@Fdvqo(<=4y$J&oo5l)lJguj1)NbQBJ$<8@NY4Tfq-X8~ zRyeeIsif&_qKRnIr0HXbrcc&KlNvO&>%weYifF)JP&u zlN{a|NYnX}rt^pLAw)D0`9NKW zbXTwL=Z&%=8A5~*(M053^&wKdWZ!KRA~qpHh-f16Hi3wJ@dYd^X4_?3W@l%1R<`fh zzN@lp@0^n+Gd-i`%XFi4_|8J!XGIKLhtJEE!yM5=^n}oZs#-U{U9OPuZg}sgk0!JZ zpD*Nng?J65sY}w-Ni-2nnl!x=(c}%^=4YGGI(%0l*K2f)SdXNsn`k1MG-*OHV$EJc z&HQLWtM^@nd`3=&475#slBQmwiD=TK>AlD{y|2EJ9$NEf^CqJsE*~aodMMFEG-=Xw zH=^l{_0fbP1%Rfk(KJ0=($r5h5lxyjy$R9e#TU$Pq=(`QpdOXk^QM)OrbiG>M3W{> zD2uxJt@YU^6pFy+O-6em1|>}cL=(}ZNz>bqZSrao%*!_Qpr{2H>E(>3sVHeG5KTmr zCQYwIG`*@W+th;s9DpXtL^n9fQl3?bpKdYdDp-@cak?N`Ptt z`hEoH%j*MF4X^0z^#N*G24pOa5;BBL2r{UCNb@VS5Mhz$xh!hX(4z)UD%Shc~GPUjSxcTV9IeRvBMukh)x-8UTB zOvNqk15Hxg7Ak?&eF7S&z^@&*n%D61J!7sNgMI7dKyxiYNl=DBnUZ!Z(*#|H{w=pz z2z%3iNJ~7x%rY-U&J6HkTjD7J z@dgR;CJFIIf|wxIgSgp}kn&_Q-|(43{7Csehj>j4h}Gy62%7|sEmj$_#d0h$yLieS zP%jL`1r_4LeuQ|lfcQ}o;)^B37ZJn+u_na63{ehoi-eX#JR-L_#G~~?+^Yt~Kqi3< zijkI>&54nBJBTCVNRy+T zh@&fFaD-xIz`5^BJvGJ8uv2n$IdMcBX>#;9#L+b|I6~nnj3e{Lb+eMAD~KcFNRy+- zBaW_(!BIfOh)g#%#U5QLIod@W5l5OFU57ZjJ_bhtK^x|Av|DoYSmKB{(&T6#;^>CD zIm%^F+ysp4vgY|2<|IdZh$G@ilcO6EM>oabs4AWz*DE>N=ZhBN(YZ>1kl0w~<;yfC zK4^5F9qJ(B<0=W#UIK|g(gbNO0%=_gkg5V2{FN7t0qJoPq^k)e0!b63G6HEL21o%B z4bo$03`mccAYDTs5lEUKO(Kxi#{db1G-M#j%fO-CbrPg&2_ynZ6Qm6Yq^TGnRmU`B z4YWx6BuLj2NCc85NE;DIn__^3f*LZuLOK6~wF7Px8H+b?GHq4@= z!-*FF`I8E1)1T!w&v)KzxgY_(>AtClbU2u_nZS zk&v?Vs;0lnZ4U8rxy>Q&hyk%0&H>dw)Y<_}ycpNQ)($`gK=xP7A-6fi4~YRWiY2jO4P4Aim%(M4p_-lrRRdVl+_bu7lgn>eYBuxpL9Ubv#4T_AE);Gl@2$Erd2yuA}K+k|thOAS1UqZFUU0 zPxQ4 z;%G|@j!{e4*s%1;i0?q{-1%#L>1G9HGb-@G}_5(TgQVFCvbJBTbHG z5l6dXa8w;!V&J&$rIMqU5J$w3CP!ByjvgC>BQ?H*l{56MDw#5_d%5K3WyBG2q{-24 z#L=D@994%{|pO^~t(q+AS;)PM#Kk~B!hfb@C^((4E$0!b63 zJOZgR21r#A4MtWOxLbns1_Fsd(gdjsfz%xXBsHXgStQ%Qavg7yAia@5B9Jse>Omm& z#sH~0romSl)R>{&TO>$tCXfguO_2H!NDtKlX=0>Q7^>v5Y8XSV%U3c=b|Y?FM&X>V zzNknd9O!_ILfL>g)3>f|I3k$|ijWpY*7Pqejcst-5Zi4d6XntM8~fl-8@w7X4zZV& z@eM=eN@1w2M*HEna_(F|ONxCFR+r;#gdicPhhXXtDuSs8v=E$|-d5Q$yJzk~m&KgQ zVpo@uAw}~j!-x1>NUqlU>k?JhMbYk365&a(;XS)QBfJR%6Pv~gZKF1GGK|`7b@VIw zfTZdDL=(}ZNz*qGP50DClNv8CzXp&5*NgUCKsQskBjO+0$)gJQn~mPaY0;Y za`CbHxTuZ}$jO|AE9#kF%zG6k)>Pxuga{#`iO9F=L!^53-6Oqr>he-93ecq^n*5?QjLPQghj|)Vy7hk}#VzynjWp;LE zXJz}2?Yk5Isas2tBClPt&L53JLFB z=Xt#5M^p7We2+9Z2GaCpNz<2zCZb7`CX@out%$v;ikpDo^ z^nIdh$c;%-h*g*Z+$eOSO`Xw(O!uA zBu)1cO+=F>P47cAy}v%1P%H$SHyQ1P_=%+H$3zp+q)F2U5KSMfk0ulg0k)|}&?IZj zr>wNK#A>w;vJSQmu@1Ekvkte8u#U8jvW~Wnv5vKlvyQh;uuim2vQD;6u}-y4vrf0p zu+FsFth21Mt)G+thg^CT;eAe+kDt6y+WHS}Fg9eFlZ5!M65_uQ#00S>#K%iWIm9Q(Z4PloZgYq)sUPBQH7JHb z>;-K4ox9Ann{EKaw*)wM2fb;qsAns?iOQ*PL`zY)E=~;lD|K{~`JP zJMl~WhVa`WdF0dK6XiDNcZ=NS{BDiGs~UF0eOSWin$zCxUy`eT5?91k2v@jL!qt)^ z&eh{$aHIy@FphkMb4}^-_8-a7zlkH_NRy*$5J!)X!I2tj!#z3X*&|;sgZ~mo#E~XP z*CLLti@}i^WW${)Vr|lxaa~K3XOCK7C1#yFR&8GAPBNQ^#hzhzPYX0HvH0X`$(qa> z)}PVYYAuYc@ix+hA@6mov(D)pl^P%3=$yip!AQD(DDd5n9pG@k)FyVJY}q)dkrhF9E(9CC z-#t~#`rpZU8%yA7@*Y2d*X@hJks1q=x4|hXiz65^u4{n> zOy&Y%@d(Yt5!oZDDX$FC`JqAeC z5e<16(O?Wn$4ZcnA&>|pO^_}{AYB#%BsHXgO_6*p@QeZJcnQ*R1QLOy3DOP((qm$P zq{cKbkbLz$i~;FH3DOA!5`m-%(&Y%GoiRW{K@HvDY!E}c|Gl*1mXqC##g>yencR_a zs)Y0uf|MW)ffN@2X+@AOk=s1u>7jC)XDmJ}2E-_$f;l>b$MAoz07%Q}0^-vo#Aix~ z&mf2iVoit-l92K++=JydhqzyEbBG@v17Z};!7QHVixA_RMR`~3xKqoDdrw0 zKng3Nicj_WJ}ZhT*Y<}Os{lw#yX1GdaZgYN% zF?dA*GmKaB0?$@Rt~!V-vWp>h5hsdXAvxk)&BowJjhA7GqMjScoP>f4Bu5V+j))^o zj&>oAu8hGE3YTF;)y+$A%SetcB#ww9O^zOmINBY9BQ;tkpY_ed%&|vV$&pPQ5l5OF z?Li#P#o!19%YZ%doRa2nl$RXkh$G@ilcT+eqpM|(U7zHrmpCGhG&y=A z;^;{+I8uW)__$64ZJ5K+!z4!!C60(AO^$9w9NktoNBInjn_x*fB5uMQjvg*K>L-qf zBTbHOM;tvl21h8K0SbWRWjup1$!#koNRJ?p2qaCAh7d@@F+frS8geWz#z2q;B}fAV z5`m-%(kcYf>KGuQhz16d9N8ITk%|(e0)a#zX@XQjAU!e$NNPv}vq+r=TBKnK(hz|} zAZdcM27xpZ10)pFz(A5~vBp@W)e@vt1QLOy3DPJ6X-o?wUI(#~&!}MxIdCs{Hpt)K zxKZg%bH0kDYchR(t26!WgB=B)-jwO%8BLkKb!}0}OikG z_|xVzw_-0V;~R#`6{u<&Ri_k+la@GluAjwgEc8f1kPy^EF!gH{!PIZH5S*LdR@pJT zXYN9mMO$UD3(Q!rG-Iap<{Fh&Y=jUZg!B+<`nifw)3547NR1`}ggR~W5E_>VjS)hG zkS0R+A%uQfA3|y%5kttl&fhKTBtmNmAwozKq3!N7)J&EunuvRKIG*WTB2?G_amBqT^~(q5D}v(BUhRXq-jdhw1H?Mnlx$pF{0^b_0gn85;2-=qixeB zNz+E6iD=TK>HCPLAJs>b8cxJ*lhHJ7mNY$zXd;?4Y5F#z={xn&q{b8hP5E9q(%Y)e zn_&Ib?H9R@ExJZ`hx8U%gQrHB(e)eW(G${Z51C=@Aul3Mh?5Xbnj{yQCaAaii~6`w zLxlL4E%{trOk5Bbnq1sl9~V_I2c6mEbMa{6g1FG+;(PURQ58s#@0DrbNgYR3hzsIE zlZ$WE$3;MNfaKzedgd4NUWJJ@)wqNZAw)D0`DJ~GRIUDZW@HSS0f=lNLEZG}{$TmWR5Ya^BTbFH_p4n4j2{Bvu&Q9-~QSxGP z>Uz7KD`dS=Qp>sWBv^zE6?c9N(u#OgUgE@Y`V9yz2MCF z1i3H?bl-uA;C{sSu>#*KCBAzkzPkxu!dDaDmr6W2zAuv79N(wOZI18Lqw!S(DYBh_ zue83bfi0V9ra8cku)c2!w!TGfeLYwe>kAAQ7~R4+7gh?Vj?F6)E&5P;uYh?@!hE%a z`6_~$VAh2B#S&Hy^RwkPhxr+Do5TFfXqeUL4?dI@(SpnPFq+}ays#+%`XK9I>k#Wu z>oDtZ>j>*e>nQ7J>lo`;>p1Ip>jdjW>m=)B>lEu$>on_h>kR8mtIaygI@?-monxJA zooAhIwOh{#fEhfmFpw@TAM_8PF~S4R_*#<7i;6Ai{P!9G?c-c%)e!f`6SM?v2(;KQ z`y2@+hxQe6n?w7oXh_xgldN6H+G4@EYxU^h!vZX#BQ6-`!lAXXj|&59aF0!{@xFYU@Up9^5VaU@Xs z+bs;f06FWo5D)}J2oN}oc>rMHc_&DrF~ zS+;J3x9zz;)I@j*bBebQvNbPOq~BZh0w)~X-@*60FMJ^<^YOMxNJFB%0;=~zXvq_W zyX^_wM&U5XClQ@QX9%6h-IjW{YOYdWklW1NmilZky>8Y1yc%9&_ZG5QvA|`JyX`hP z)Vr0~A$CI8!S1%3BrDwAc5^f7@1 zNxPC*ciS@v2m&Gm2;^?Fj)?@Ivue#>29z5#33-+@7SAL$h>Z|7@Pz$pWGo&R&5F9_ z&x}QnffM#SB`bFjE5wQ>E7u@a9v{sLTJyId)4{+=$a5qs&n8xg6-`#IMXX#G%?euc zXRH`#SMHLmJeOD@Ry0|;9Vcet)qW2Ll>?UBOr$vQMIUKg~x~bmzKshM23k5#Gmoh z&gM0|chL(2d3+J^NIZt{h+T58lKk-)nyaGuLvaClNW+o*v4UefA&wU_YD84%v;F)z z)i8_8_YDeD$O1&6y3ydW4k(SnN@S`z*9~HDo;LEuflR)Hm?S1cn8Y^ng^0;F$Zc*T zcSbXc;t`-?t(St$N{%@ifYnG~Rx-Ygd{s50oJ&R}+NFkWKqYwF>&nI$b!MN;sy2qvJA>>hWJ7U8 z8LM7ORALZ)Wgw!jB18#MO+;UyBAWW4+~#IH(4{(lt7@CKsbo`;3*y zh-Y3E?EBPOgb+&)`pNJ9#fR4gj`m(p$PscO$YIm;9b}q5IX?uaXSOLdE4tKRm0sux zBu&(9K5$};^4PlF$Qozit}w&~bGD!;aDja^#(?jQa=>>tQAJegQDwbLrOJ9wOsdof z7#@Z%B48}bfR@5Hu!Bc)dsVxW3JE2VghjHXMw;ZZ1>acCAeP=H zS$Zq6L@a5tgfb;lH%V&zO^W5-NS4%y5MZfGEG`>mm)CW1*5 zrY9koZjA+#8soqWll0OV#L{~uOYb3;h$T&yZbK~H9*ZS4*nv%$jI>Mdmn^-HSR$4* zS$Z;J=_#>TQUfFyOVTdQsEe|YVd;k6X$0EUc7bPjtX-xpDv8n;V&}c&A$A`iU|_s3NK~ zsrm|{>Z>uSQo|jcSn zqKc@}r0Nrhs+egO-D(H~n^^glZ4JcgGZL#$6IO(kCRQl1)|zKxE%pNTplAq&l?)#@ z5UbBgtUgOv5muU5eFj;pkPf)c$gs8>ut$xHfH9z*mC>&TV)X@y)#nK-!b%gX&mpWn zA8%^aqlQR88BjYX*L4lV>Pr%+1j8zCG*(}cSbdqWBCIsA z`VhkE!!fZ!5f;o^8NC+#HHp<%2`j=%6RVFPtUekOD->b@b1Pp_FarmH-;h{+ov^!s_EOu|gphV68fZ%Ys#KXSHUVq0Ve;gSwpD?Tf;7dk(cjDd_fg=&ev#=C(TF zuf3A9?eM141Z7!=s6E!#2X!qbh9>*re@>;$VH-N3L{%b-sHPNB*CHU67fNG(%W@l{ ze3Ju=8x(z;SSFT3SVqkkta}m5z8Yn$0rLQUVgP+Agd!CzdOV8s@b+> z`xMUizQK-tMW@7jHNqi1ROS!vJiDme6A1Em2xJ0T6Xb6qkWndV>%B2SMzJN#NXseZ zUDep_8|Yx96&P%8dJt;iPKjD9~5=pPW!1hgj5-;esY3CKK$VEUu&kuE0sjN>LcE0Vg4byO8Iunb76>jpX?2py#~+Cg z;zN^c9jURi0G)@h9Sg_|W9z7cu#$iZ<}# zzl~@{|7SvlP|-x?UolasiYD+S=Nk}N{TD)oP|-x?FELT6juw!kE(1{cE1^QDXrl7_ zn5a~R0Qh<%8i2~*2o*v_6O~`h4;3d(r_)Bu`K+zA^Z}a^#`zDq-1v7whL8zC2Ic9b zP${I;JWC-7gwWc3Zy{&P0a;SrVE-geh?5Xb&@yA{6ZM%Ew7S^i%a&dS3;oSd9n5NA zWw3zq2fXS5)H*0at%Jek&c6j&7tGnkDkDJUFgO6-f~sJdzNO=1PED|of_tfVuX$Dx`WH81xE$EOiBsY7zwN3t*w8RYjb_@RvGtR8|ZVNBH%gl3peglnj z0gN*YqM@P~kjwCu#<}{f{brm~Dc3lsTBLDq^^9{WO)wM8Auwa({B;R0huPN)mK$eZ zO9*b9=h+fM7-w}+JZFP(_K&<_Lzux|KL7Izzt&+_ANm3 zr4EsBA53r)+?sHI6~XOmpU&a_hDpK@q0j&ZlbBi>1=CRyrXvX^f=Lsm>kv%W$ASq32|%2UFBHun%XEx{>1cw9 zVA6zXAA;$ISTLcyet^lBEij|bnKCeCa;HfdSOknaLz?Hr$eSav^}p1yL<|uVLJSVN zxiJVv1zQ(7RR-B zq8#&`KqL`Knk2mtk@TWCB<0jV6^KIfg3t^i>10XLNkkHnq)F0?5lJtJMG^`bfw5su z<|`Oulunf>okA!PN}4FW6ruF8SSYCh8d-*tTyHW4rPC!!rx8kok|s(oM<~4_7D^}% zqPx&zpiw$gl5_@v1%wizq>0k=5K7OFg;G^K zMK&YiW&IBKMisnxW{|@jO4by4F&lWnob7If3)mRwfC6;;)7_rojAD1YO}G-Snz+6m z;rg_?aGjpnrWCQrR|RkQ!raYkU!2NITbLub2rfOitZgb>)^uawQsX(;R87Vh8VFaH zgsYR_BDgf+nn7@FZwy>jAs$_Foy$PDdL&%k1Q)@j3D>0vuFDz&7YfJdF8HG34TP&t z!qrP~5nP&Z?LcrnrZI3;MQHdEA`OJ=VG^!~5?lnACS02lTo*M4E)=u@b1tKYg%6i- z^%GnKmnK{nBe)*j7`RXvM|Z)iYHe8tTCSB6u164D1eYdU6$IBM4S}n(DzL-X&(lD- z1|?hr1Q)@j3D*_`*Ve|sRTb*tE8=M&Ttx|2f#4#zG~t>+a7{J_E)@I$b1so=Y2>hQ zSi&_#a1mUZaIHshZDSz zyogt39jTpq`zbKkjp;~zSGB?3HwgH4fKA>vAi%bhM)TT0n%5D{M6)K%S4es}&3olG zr@7o1nyVsVyyRACoLT#6HUN*`g8F6EG-m|EY#a`i@Ag5HdG-=I&U>#4xCY+-GScNh ztS1O-!desS%O%Df>p8j2v0hU**0VF0Dp`A-Y8(!<)bPgLM!KywaQ1kkwe6f$ z1ehjZD-d80X&hi`Yz~`)84cJa60iyZMu2Gob^!wH!o~rn#^%xDXCnFQ=o0*nCD1nfKn*!hhEtSXYj>;$C8NWgXwU<8;ZVC@L7 zWeo$YyDE~y>>A8FC195mU<8;ZV9OC;9gPF5Dw4yO<;QXrS|D+NW%#kQf%sv@@2Czl zh9tfLNZ;!yDtUbaPEsG+3wc1SMYb;;2wrB?J?regbxxMhqNV%Iigdp#IMX)VtJIYe z?_Gp9;T?i^O5&VhjP=WH9tpWhZu8LNGv#)U9e-Bi@UMz9@yb)MBwq{ihFW-z!IFk# z8N4q5f5DbpafWgFXRp_gN$Cb53&uMO{p2+sCGy(VsFTfK#FcymjO+%Xi8wW zPy&y2mB54WpHu>SNC}V<2vGt!=l9_fa;^kc%WbX%mNpLhs@Ru+)S@)l{MLp*Uo*7` z;D-!;mRbb;zr0r>qkrl6*#6D`oeM;JFQH9nYoh%yi84pKD7QJUB~TeX-BUj*a)@|*l=3Wn1qYNHr^Px)My)k%a>Agg>P8v&Q1F! ziv5{-?G~Hv+VJs-GC%Ra#HO)A+h}HV{l>o0Oj|(p89wT4UgJ8;Qf$U-sUy+H5kW*y z2tjO)XIbg7Riz@Ij;^bl7@Xjz${%$6cI%s6k)S;c3srWO{*=Fd(@biY)`@Scv{x=>OhW-!<>PfI;!&)8$zm` zw4pMB!Q(lbkLT=p5A0x_VV|@^*AqcRPzXWT4!suHp}QMHlo|vBMEMdCOd;wNFKrA_YM2WU<#XSeLevu^ zQMV9LM3g2`&p|{zzcECqkt0Bq*##7yB;k4@!9{Rs!u5It*BcuHml~k~aCuRgMy8(L zCgHl3;3Bv*;d&K<>otvm3&lymSWwQc3~VO(WC_>p1Q)@j3D=7eTrX=3TqsTghJ{AM z^;8MhQwT1COB1f=A-G;pH(V&BqAP=}SFay1Q#={ZkW@XLs3NK~sd_r1>RFAW3YjgS zN*2>Hg{o&ss-8(y5mlO0-G-=oO5>>t$iZ%Bp_} zVMEx2V1v^aU)LB+sv-k@6^E0G$x8_n!bB63S2P9_6eR%}RI(OQQZacMVM3T_V)DYq zV1mLPAQV>4Xp)M_%Lx<0L=%(eHU<+E#{faCvQd!%RaRa>#1Ju>#Jr&~#Gn`jNMMrV zF9V2qB@si!XcF_v#t?(z4`3)}6fv(NVu%<`VqVf1Vo*Q-ToS?iG_2)=HiAZEt~o%1f*?^i@8{I@mhII@CJMI@~(KI?_7II@&tM zI@UVQI^H_LI?+1GI@vnKI@LPOI^83SSw}T$%yw<_PQ9=?3Ru*X+|c> zqBkYHtc-6MDpv|aL5(S)SJ7KUi}W}1bTb?7L+WiZ^X#oeAQ2csU`l41vBs3C@5^o0 zM=$jrxy|}0r|0B$j&1J^Cf3JWwcMR_G|GC_%4Q1a>+!D7T z+_p##Ik#Vu+nn2b?-}?LtqFEGKMAt*duRYxfSK zhNual26gL8Pf1D`HR+9^l%U1eLZ`1?SW*{X-$f)42_Yn))ams4&?g_QrNWb+{QR|d z)00n6zUGrZQP&J6ht^HI3prc3<=70S1?DhKeE!1x5%GNy53QcT6qoNSh`CEUo6Rii zXdhf&T-G+v$;W%DCm(zs(!9&7W_WL;;G4Q7LcDKSI!kHgev^ z61bZD5ZjWUVq5ZKY)gKQU2AatuzUC5TKBd;%6sy2>Ehb*z^J%X zK}xW7syyWV63czO(_^bjMLzlXygH0Z{ir^qsuopqzN))j)c|C~(+{(FHk}__J}}>B z|Go6=Tl{&aXTQ#8|I6svzvt4K*{wS-w>M`mzF=;8TV>m2TV`ixc2>6U*uG2p!Pr(V z3vc_qVmWnvG@mWxy|991U{9EboB6j}!LBsIru?!Rsdk3aAg76$6Y!4tUc(!%nPF}- z@mhR<9nbeO7rFDAe?Xjv?G?bniG5cQpW+tG`2y~Be3x6 z?;|ZhT7ZvY>a>7OXR2DD>7*E1Kwa+zhg{w>gQNw7;t*QJQwZ_3!23xHkQRug1x`a+ z;FK6zKwaz3LFTQOL`Yg-0kyyfNDGh_h@}OVAuVur3@xCplXEQ~y-YMCa3&E8Fc$bA zX#vs#v9!Q>NDG`Jw17Qtzd+vgWAZRKtDMgj^4{trQ#LGKrU^U(tvq5TzOOmZF941J z2$z9*d6B!B{jcE-cR%pxy%rx}$MgO0VfQuvfH)7^>-h!5hxk>*r^JT5j_)!|1@JE; z&gWi+@Aj_9zSaCa;~yd|Kw2P<7HB?9)dJ1w7+Szxst{TLyn|l)gfrw|{=p@#e{g}c z0Q1Xn*Bzq`Ty4JB@CGo)31@G(uf+$v{lKgHntwo?hc8@-a9Z&pc{WD5|6_c^cNwOb z_?Hpqb1%bpdsk%NYW`Z_!=wdB3&hd_2O}-8B!(7n7ixT3AR}i4&PbqzN6n@|6D*t- zU_1hHTnqSLGwz)IfTZ^tFysfZSK%9r|^~M6Oa)Chy`;?>UoZ ze?OdC?Dt;s!@cvc1LnI@_z}_qqy=JWffJAxI5LJ7P=m7AN}&>c;zV~j>x2uY1%OZB znz`aQh5py@hPxlQ^Cwr3H>fTHt7*1v2yZ3#c(@uu_=w`30P40n3dRAT8i21W(s+ zZBmaG_!wyc(gLxxz(0@{cp!!rP{ZcHJDBq#v}vV~4MW&4fz2=gb@>u@JA0X4;4kMp zBltLJ0n!4ow7_4H7Wi`vEr4PNGfGCS6OG=?y@QR(jSpNSaHjb%&UU>zO-_R580r4Tn72v-NquqCI@1?Wfod)KxR2LTnqe{Ck$-cwR2|M+%7j|pY6(Ll$?P)iWAHha$W^>Hu`6tz-As7 zz~TcIh5&v72_?Dk*5|3g68S%0TmXn<4)XrI0;sIqK z&>_|T8gO&>1Ag9XK#m{eGUtEIKOoKnqjovcPZsf?CgO?sSj7Jd5r4lJ=||=YPS2=m zf}LtOU>Ae~cFPa|XX&q*rwFoC!T2V>Qk^EaZ=hq}V8^~K#aQEyC3DqdNw11ap`+L_&@njQW!TRX zF+@xpV$yf1#H9Z(niw_e%FZEVn7_3NkZIH!%Sbgc;A3T$ht0JL%Y0?X!68#*#mU*2 zu!FzfQDpDS>f@GWTPb!zr^r+D8eS{>i=uw`7lQKhkb&pd5s0XDcJf3u|;gfV(V)vT+APkNzoXi`xcau>>RZGWaTSZJrHHHL^>fvw#%ZwPZJlzC<+M0!ZlI$u zXe{Vp#M%?8^DOSss5ut=j^OGZ;)=M6#nriptMdg{kuey7e!(s^5QCRPlXEPQ_PnrT zLB&;3*I4j-g01foTf|lzwwlu_Tg^wrU`vg*;A{nt1sjt<6k@ZuZ{70?f)V4qaVLB& zzu*r9SKlYDh^ts!wIZ$#kHM81X2H11O0L*gklC%q*{l$*xNA@u3u^lXe(I`TmOo|mKuM-N{wcv z&z+40nFphBY=w*k`FzS73(kwHUka}7C$5OASX})HarMs_T&b}aym+S^3yP%Th4l+^ zryxwJl(C?;U+~w0t6vdU#8oV={(`vrTm4*htFad_!SeT#4;i^}-vW;AlRImT+fPB61VO!K%g4p9Dt_5J$vO9FAJP zk2w07CP!)%1m{Rb7l|>RQ;?z&Q4k^CIdzPugr3)8=r4kyKNCa5P%MUifEfCzCPQkp zLr#r$aN_eCIiBkdt~SAKk&?N~QZ;Ih<^Cr4`77~5{KVqthlrnhHThAa8n_LT(L&B_ z$SI4oaM3~l4_^~f_~8RNov4O?2!{Sn3=u=I82S-n=srz`)CdN~P^W)B zAclUY$&ebEz!~z7=N#``<7`ooPXP=O4^B|VbK3sx2L(g_C5DKhSPcCVG4$&IhTMY6 zJ!<3uEVlZiyTv?+`Lmf{JAOswH35DERvXr-MGh~ZBCN0W1N7u!Wn-aJ2fTo4%eB{u z(lF{=li~J~I3kYXaFj+>Akr5^R$A^+Ll?4Lg{-fbUgHZrtPDU2swuO6kaB4V+}f<{ za>pPbrj>=12Id`ppbuYpXqEe;*h^PcG_P~_HLnwUhQ*#?cTdZziLz6(dC8j08hdp8 zMrW(FFtWzmNEe2@*R3NHWp5(|&F$PXriV9ryIbK9uNE{r#=Tg2R9+xGn(>ZL6$!;V`}e!&;QQSrK=x60H+$*sZJjF0tHXx;TCkDz zz87rdyp1JrHTfa7B|pWsm*>$R77b zbBkq_v%L_yAeW0o(5bWN+KA<%AU6Xr)DE^tF->e2@WvY2Xqct6z$!&pky(mkmQr6- zu}a+&jFlMSsZk5O0f2vI^Y5n7qsBL|N-18aC(9ZQ zBEos-!Bqe+fC_(kRz?cn#oNs=e?o1ubEx3r5aNQkh{HwG3YCkdhs59l#VvG0l~(^` z$f?unWJffj16m+y%=SRfP8hy1hn?bYVCIMI;r*QWF||oMT#$Ackw&D&BJBc1+J%C& z`PUQbQKK93d8mOWqZ>p$p~iW}14;9{zp+h&_Z*uh4ysMsk%F`%h%_QC4r$G(3r+JW zF-TM6A7BAWR-23*>%kb$8SGV$^_+Lu>_}&tzER_Z7|#i6R@4~VKi zMusx;A;*bShi1{wU zc#m5y7K7((A`=EnPAm=r4lFq9PV9AU4o?>xo<=ZYem>8akly zkXbjl0zhM%unepgLw1v;_1)2!32GpsYM zHtQ_wY-_1?j&-heo^`&}ZmkQlf`Adro^n_diBzK61jCKBrg7hOyVTSQyIm@HJDYeT z-s13<+O6`I3bA6YsBTmbGCOmz`c#8fP%4n<6PnZ)z1Th^UXqbqVfg?zp`Txns) zek@eUn@`Pa?AI%p>LI3xsW?nEwW~}uog?g29ZabK6;KBw-zCR>(nsM`!dRHGpW>rX z8hzCAQ9M*I)kjPbQ?Zyj12J_<HE;U#=Qk@ zcaVoy0|~7k9$`^;kOwX54#G)|?hew#GKk%7A*`ZC>Ni?IvZdl&c3KI!?Y2>51$43U zr7KH38|867BM48{2*iQ020AON(c$-t&>?h0pCq-hjt>>qSf{B)3l$WY-fgS#6J5DN zXGX^D2}&C0?+c`aB?oI!GC-8jh;LpaK1|711SOHnO=5(n20}n&p1)9&fa8B@gg00X zAeid{jqsr942|$~MtHwNBfLLq0U12PQ)4Q4pHjaMP)xv*F~TcWqeCM+cl1H%1fhd% z*B`V{sT$#_Q4(F95GCPXeR3#iTo>%X5#FHg2yciep%Gr35nl5L1tpQi)x`);4R-(^ zUaqSej{l_*-f%U5Fv43!BRm@6c@3LYM}#j*mN_DtzlTP6f7Jpqc!Y-{C%RDmX~%Xo zF1sVpcCntMTHcA()#%U&k4AVAy-3jrulWaBs8o&c)K~}@;n_+ogrLM3W5hXOji!;J&d4pbRU{;NFVD155vo_(qTVU5V>kqGm#Ulv|!Xge9*72HHps)q# z=@AgNz~bguMCt-ri-PW$Y7JpQSj54iIkRfs^YH)!^s390IvFv{eOa8PlCb zOZ1sSx8P|R1bT|K$3|7RdO`r9tg0!Sg*Pxv+J+En8$zw!Q0ak*O=AV^AnCP%xUM5y z30FN_tw*T1TBl1e=h@Gq3Rg8&06IJ^zQ;^E7_?js5+4*$$TY>GX@yK%D;oz6iX(uM zS=DyVv2u;5?vn|!b5KGU8oNNkf#{9KUhB=MCI}^(QN@{2S%Zy339b2O{C$=b6c=}NN#Uh?yT3DYHg~X6E1{HEL`r1iHjOh!8^%To1Ek>HC;pi5kRp3`ff~s z)EI|sFLXDmwl|F%v)vXjX5)QdS-dL@){+vJba6G9;G=jn`6$Roq3NTz5BVtGF+Wh< zq>P*zO2POHh(%|9L*{ai?{GgWh)!zKkYm9x%xm+10}d23tHW6 z6et}5ps*(8?E}mAaazFppjpT95<-RsfpG?bsc+VYOjSHYE+8Jgah+I}1t9~4?in`V z^WNt)3eyON*h0V%FtLES&mCUn)o=#Z0b)U8y!Qqnz^fw6uWCI`nu@g^yR{l8nCon# zxem>B^yWJ0*Q2@4p~3b@K&OU7fP*{RQ$193dKE2cz?|mHAn14yo>mmmbTu9{qoEm% z{){I5<|}vZ%=n||@@k|(SFg-0vaFMf5gSwp_R2mk=85X7ABQ$i?N`AnosBu{b zr&K@j`-)nR{H65B(<2|}k+)6~kG#6@4l3CWi2h2#Gk+O9^YqNedFIpa7tg%9dfo*+ z+wAIrcoLrZ9rVo8Gau`j|A2Vr)dg?%%=aeqnSTsD^YqNedgebUo_Vy0+~c2a1`WOk zv z@xk@OP;Y4M`jHVfY3v^x9~)XxESEM6_4llp7#W%>4@?gAPmGLDttgBPjIQk;A6v0{ z)5PRZd1#_E(LXlORvefd7+t@yZ|y*_IL=PR{zCbp4dtQXzVYGVw(%l+8@j-5C{D0f z?gt=4_i!uCjxIUI!R#`&s9h6uX3bIKPPVdP!-l zT!f$HZn4YCE%u&wktOa|a*rG>tu4tT*_L;t)AHT24qbXKe3^6Cmc~j&*2{W>bkt_p zc8Zq+o!&CHrLt=;zVouZn`J%S`LXS?9qY>GFD!Th>ng-0{0#3c2T{@yg_;wL|^v83}v#y=UBgtoll0@Bp>Bj}B}( z51ZbD4oO(-P{35n?52oWJO z?S&G|AD zmCNHjxm=q(xx5w0++Ely$WKS+nNuFHZgXHq-YPn!{SyzuF#dLSsQ$5){ zEqSteIg-t9f@Gu8((Usxn=YHDd$M^(@?`T0B%9v`$VPRL^>iLM*gVq{&9jmxnpYyx z{4PK=ijQo>Hh!#phbNFblP8c@A%XlpKp={9Y{d2|n3`(zpX~|cImr{qtC2wd5FilM zD`p!%Yk96Gkh_v6kk=rA{4qcviaQKcmRz$mGkW5AoIwX)k1qeiSfZ4_`e7(pM$cvLF5MNR*i}gzXIY1z)=gWAF^%74W zFHN32-hcr4OMpC7k5@Khx(RuiCyRjJ4=$lt5wq0S2Z{h`g2 z2aNMwdAv4x@_0Uy$3Lp&p-c*4$SZ1jnmS8|QKc)7*C$UNFdkR<_-C~|)Hz|+_(?hp zVqAILojiHG5Xs|T)$&lLgpJ|MWzmB-tY zCy$pRc|2Gx4|O`2H9jH*g4bMmyfb<70Ox_9k5VrhM~x%3Cl&Hq-@)A5@NbsAQ;D$%X^b2murw*nvqDtn}mrT-te~dDyK*kSdLdmr&mT9uwz% z_IlENonqhJyAu0;&IWw6=nPh^CGf@NS6JfyAm^|{CMU!Xadxn`eFwY0Ssd*BYG+5f zI5aY_$$ialm-D(6PU3x&R{qW1@6rmN@ZMPh8}b_;G%`L=9FuR3j&EQBaL#yG5yVrN zERD+p(uLuX0r!rzju(sNjc!@nR`^Zcy=*P{-dR$1et>h%LmbK3-bLKE-P3?v@RO-J zTXR|YESjk&KJ4jJhNKbs4^n?j|LRmB&$@~0yX3jf4!k5zMMQgaTC%LhhROCjnETWpKJ~wJ@FON z6DH^hCB6gJ-WD|*W&!*YU-k6F*OI3vZbo{-?cq4>`7!MXJ>i$l0i-9sPI|%wJ)y)K zjpTflh|QdLe8bZd-%OsKxCQBn!|-?_6Qw77vN?eC#J5OK7@#L?CH`&Dm+fqN_}jNV zg>g^v6b4j@R2&tDBZXn3@Hb!aGBefpcRXo)H+j-{B9g`t)zS!GuFm;na{#ID?~(d8 zL4Bj}x6VaPhFO5=;P*W}@q^^)38*2fXze4hp6HGm=J{lE0O^SzlAbU@PpIKxroFH@|ESAU$y(=?N3`gcANX+3g$Knm!-=v8OS9l01z8 zRnV1@#nD(}sNqIkzAysQTcEPY|!uVVAgaJKD6f#al z!cZsXw()9@yYHkX~0dNjsMdV%fFH*7HAuzFmgH)i!vD> z$z>OH#<2j4l>hdG@t@=g<2gteXH*FzB9_4?ngeL<;lH%@V8YsizvC=uiA5doFMyVK zP-ux(D|uQ18cQiE`%I)IA_LofqB(H1L~9di2?Ml*;=P2p_C=liG+s-zHhWs4C3#xn zE~F*ekd}xJYnP%qfV4!4v_x{X#MZsrE7QAoUAbAA2$s8iTEg&&U~Agb7p=+D7jsBo zoaN{XPb|tru-xUFZI~{WC7xIgN}gEuBC(u}#G)?G=6r6GMQ|uCfK5Hv6UHIQ6UJ3Y z7)z^!5jsDg^o!=spi;X~{VNK?wGDj?^FjmBY9u` z-Xf^(#;=mL9^r}O$mEIRN+gbRtHhxUaG)xjT!1iB97lQLI68Uacq|gfc~#<21~x#) zqPi3pfR1B4aU7dGaqLFoIKN69iWM0&zSVW>ah^DiPo6mTAaS%i;+WpCXWN$D)4be% z)7sLwwRX~9_{>Z-b%G~|6O$*1T}Tki96?;RW3Ix@II`ikZMv2^$&<#($&<$ANE*wr zG*lCAd_-pJDV{V=O`bG%B58DBX{Z+5-!{ukO?8?ljnk7SjVq8eR$yr;27JWMOAo)9 z(m2DD#+k{J#w?P?L!>mIheBnCYBwf*b8<6<(dG%`tmFyfQY4HEurL&}F}b)d)CHJn zob3r?Y4U_|84|{YSQv`cfbp$#SDA^%Ii57mO`bG%AZcW1X>|Fev02HV9?9kw)jhNT_A}>+BA+}_Y(k>wMxqF{or+*ywop+-YNu|! zNFx3j=<&@0ke~x}y&*-NWJHr|L>a+^Q@KpelMjRneC`Rk0bVie5!kMAa?L`UG*Ar>Kgk&fR{&9Ehso;iM`OuPW5KJ=w)wuwQ^t#Ungb zu`+q8;$oyK9;&E{sOH^%!5oOHVt`ad;#Gx`OgxfZTz~%psER>PRTPq^Djtng#lsX; z5!JujFPH;SRTN28BwkghQGnUSjmca9RWanLis9s`iV9K{{ferHXyHBS7tDdEDprxI zNW7{*F{+DO`FjCW#cEGgl#-_^E+`=HfC}zmAm-ef` z5`{{A{9h;pG`N1audlB#GBCQfe|)TMLwRVpZ+v*Ttu$6HvhbVI7#z_yT3TCjw)kGl zI^0V0Gw`cet&?T;wzHAuCxybItz#bItLwy4io5l)l!|W!*as9>8#K7RlP;rIxcE9s>X$%fv|FrSXl*&V^D&z1EtGdKb z2Y*>S6n~wWcZH<~;lCFzC8I|)LSt7f*%ZC2*)WjilT>~+Gdu3bMe!qjK~*!bAc ziekC6VW_`n#l*sDEN)d}@U-y(?C4nwT6a4^5ON`o{*^m>z^*&F%C!7!RJ_ z+nJUV$Y zfXR+x(}s6$*)vyR6%uByxN`0q9}VS2?k}+bG{7RMD~U^zCyBL46054K6PEM7(Y2W{ zfJfOC!Pex7U>u2H_13++_xLSB+59TDkVEVWU^;mM08go+jY=aMM(oODc~yl?>na-t zMoN{^SY`K)Jv(Ooqa2XSqK3CGfNp|{9IjlpCr>V;NG^{Y9vb3eDG!Yd4NMGGVAkR@ z6_cGg=>=E>J+%N6QK)g|isQ26iDLwbV@-fK!Y87B;T#~16L!#yG>NNm?6G8ud$=@K znpizltX30?I=@-~H31dITs3id^3()`7AV$qBuE}ndO}L)0MQdWNlzqMPgJJLrOE2S zgz;W&s3q)biP_|7iAN$WF)Fl#ltzS(@X6)?(Gj~yMa#ciG}Zcm;ppt`W4q8_En zLYa0?b}eq-k_C{(lRa5HC3&*wMzYwf%0iiTPj(q^E}rVi;%Ui~MGun2MXD^+X?Lgb zvUs{Di)SQH7Esn$(NPzxvQVepxlWnpXy!2LnVu}3l{{JWAz3_Hm4!0x9_j2gT^4tE zvbZyOvUn(xMMaf`I_y9xOH^4X({A9x^fB#oJz3n9JX!Q3 zS!_{dp-j66?M~BW@jOo!&rhB#9*$(ORh5M@?FKik=}Sp3@MQ7AW1r)7T6x0qy6zYUK?+fNO(-HMLPZY0Do+yTqC?2DT zLYZ%u?QYZOcyI7Tad+}Wu?mUeazzx%bQ?xcrkm|IdZKt!@~chuZMjsHi58uxRd#_F;eMW~zMV|Oy=i=$gacHi!?`;O$X+m6`X6?_{* z@l|fBx%j@5@ZHb&Zr`zems5YsDUs~dLk8<$`bhL$9{%r69{%Se{IBF<*gZWn>sOpT zou&)nJ)RKWn>-<$hlKE0E`;eVb6Z$(Mx6L-cbh&Tc%LVX_a{#ntwaX!J$RF}#@!{mj;vgi8IV1~pIn>|Bz)ZjDM?7JCGJy$YKAAjW9EyZ-H4=up zD4NYkcb=JQ>QkODKAk*a9EODPI3x^pSu|&Skl$xKVSF}u!Z;iW;~FFkbzwB?tD$cu z8K3in@%iKl;|L^-$0K1VOQVCvXRds~lf@U4CyOJIEUrbeP}W8vGv4$m-kEOom3FGU@6UH$}82gYgl=(Nb z5HWqq_YF@N-%Oq`jzz+_0SQBye?u0q>B9JyCyZ|=PZ-A`Vcdv>q0Ya}Pj|e>6UKLv zCye8fFm6J^Q0Lz{<3sho>j~p~$rHv2NEkOGVJP!&NO&~eGxdE>7(Ym!Fiu3mxCIFV z&A&6IPcwe#3FAk}6UIqM7*9aLQ0Cu2hUr7wdp%*?mpoydjD+z-Bn)K&4&~5HA5Hz( z6UI-HCyY~&FrI{jp-jLb8Q63+^;1t6KTDo4PDR4FRTT!#1~%P(|J;+sFOnyV(~vA~ zQ)QvdzabsibT01qWbw=7$>MY*i`!LMDAVteF5`<0{mPTYuahT>GmtEvtja=}eM3U9 z>Bjpvo-BTwJXxHHWbqVL7V6~NHa_?9cb+VMpFCN#Az3_Cm4!0*hLm8_?ZqEFS^P11 zvN#LL;%TZZ)TwvQc;ER0o-F>9JXxHLWbt%W7Rt;Ul7dYi)Bf3$#b1&qi={{w&roHd zOuQj0*mT?dS5FpyOP(ywL9%$}-0mHhZdP&V@&ykrVhY>ez5Di$%K79!%biYeqNj+2Y29XP5eKqp{hgODxJR-Ot&jyQeGLc3$oW)Spc03NKLHlnB6mX zA=}Dj;cdQk<@A-6-CM4xWZ3`l8*U8^mf8O*h6ou*qy$BRRKYl~~A?5;J% zHu0jbudgss94f$@m8t&B)=b7;v1+2+Uo1@w42}#HS4@?Pe0PTbXRjC?8m)}1EmVd} zBSZb-%UrPY%589-sZ77U0{+*|3^Uu+s2|9Jlmban!kMOJidLqeFd}CU~O-ZdK?JwtIxl zk2pTy95z2m3huOXmJ&Jt!CT>$=22&TR_*b=~5iY{cby#6h`;gL=h5d45o!RNQ-6vLn8d5Z!prkxJl+ z-1}X!ov$5ujC;FFw)3q6k8$sI$&UEa?#(XQ5#PtX*CpF|NCL0r-s+O=JR^a}xOci_ zJC8` z$O=igyas+}Aqf}Pz+;3YTv`K<5t7J;OCl>Ikqwsw|LGu!@L!%2l5k-T`ZhTsiCnlO zazYZha7pBZBythoM@S+UE{U9wLc(Ab1AeGhNk#;2@-IZF@@ zosJOLs4VnXcRE5~L$>f^93imrT=+3U2<3=tIXJMfQTTZT4&{hz2^`AdH@Q>bP!4}c zI|UA9=ROBX!g(l)rSM0zOW;tBI7Z-54u6ch1P1jmF+pvTcla7?%edK|3;$ArtE#{mJ32^WGZrc(H?>UBVXvxG~b z*8u^J2^T}J0|FcqE{9%6E5R}0g6MTffMX)Qvyeo@V7pgHB4V)JDGM`g5OqgL=Yi0Z-+C-7N-chVa^OY@`&13 zsd>|#xpm}KYTop0&6}RBdDF8sZ@M$17T+}Jrq}$j&U9LwBIu?&lj+DKYTk5bA{}{- znoqhjiH-t^9zk4IHE(*&i#U_t zsEasL-^e3sKIzW1H}V`cpLBQ58#Rn_=e&`J@H-MY7<1>mk!RsI-aAW>HLYnI+$nF= zW!x!m5syBk_U(7(yU}N=jI}<``nJpBkbJV_|$!F$5nD-@crfwNZqG)9El;P z=3Li(YRCN*a%%oS)_rQnYZh{9u7T@5wc~6HIW-5M?o&HHy5Lh!akou9r@op|6D7u} zx}o8xjuPWk-OTV)M~QK&Ze;kWqr^DH)o$JQI#P^v)5yQIqx?dikh*E)r*?E-$f@h5 zk)PU8eIci=n?`1XfrZgUyhq9`+UBtQ_!$pOv%S@UwFE z8huvB)7S8`a+n)_R?cz#XAPpESmH*n!6zN(=5B@WY27<(S3=`hH`|cG&z{o2Z#d2$ z{dt@$>XCYogfbtAqRS2g-4gDmWblktIr{>dP{KH_9tUFn|;>Lx^-jO!Eqlestr z*&P;fJHLlE5+`ScLjS3?qn}#N(>%@=2^4=e^iP&`PZoUFoK+J2v)PeEIV&pjI9nuA zP9Wnv&KAj(vr;pUvqeIc<511xY>`wsD?sx&n~PPjVVUPw%eo>BJ{jj-|C?naB+7z> z7^C&fVORq(82u{QBuyD%?(BwTljOQ7n*o&JEGzIPx;L7# zNrLW<6ZHa*7-f_A{P}`+$|j*~k|1g*n}kn(gKmuzE0cni$MB$dCt8Lb6UE>%&AM}nvhQawhd<9FyNd|sn$|iAY(Xg5(&OPI|Rot_n zP)xp#Bn}9=?UYTz%lmk@l(I=!IUVnIP&SEjJ1Cn(rG=ZBDD^_wBWRuMI-1EsMneVyhkxeq+ zQ%9vClsVU4#L9e69hHVq=K7%SQ%9vC{6Bl|9&c4uwU4iT$oqv%&AcUMhUSgCx7U=* zQ7PmgXlP0&MO2hT1tc>wLo+L1B~!C96}wp~`j)9F`TD9AWSN*yTA6_vnIYZGioJf% zGoCTlnrolUJ{SG`KHooBpO5arGshfrj4{W&t~uA4X#Gf^MYp8Gv$^TUU3pJsa^<96FC_oJbDN}FrTcW7I-^qX3KN$`jB(ah4tn(Nw;S9<~B*U!df<`hTA0F3hUKvlJ2Fo zY*5wPB;5+@)oqe)rS0!o1|^$xJ@#s=YqQV+ax&Ip5s~nw@KFD zCTVhPI<6$FzfH3KHc5-mB@eb26ujQj;tGtd`^dBIk0B4X^%i-w57O{vKv!vO^+X{2iN~?k|tfJCQR^7i)&$; z29amoZDRf3CRzWtNxJ;qF}>|w|F=oHyd<@5d;M*aG3);}N%PQH|F=ojeF;E=M_0?=~gJ4kgz*_olspQcdCXU86=cyi9YtCcq!QyaSbDrv< zwdOq4Q)>-N#`U*J8v90h#2nk|*sxx$1xLdo+hnZ2O;R~XyZ&#JRNSFubi_}yR=NH* zNyTC7ZDw^VDt^}ACTVb3w|%<)W@q@cS)Xp>b}%$+wCit^RGq&5Hc6!uTYsCR zS)*Bho22=T{q?s=nnjEL0%x%>YRXbw7d2(6E{oRncQ~r&;(KvCq1U%bdMmp(w@G>{ zyEnH{y45v=hT9~)72WC@Lc?v6-imH@4WZ#SNpD5Bx`xnjo20j*TV6xx zbF1m?ZIWJSZK7LMW5aEd-imHjjSaU+dMmnBH8$KP>8 z;x{5DB1B=_<*NiQV-zjK?UTc!JSo80VkdZj*E?tT(qwx);`>M!Vc5fwb3h zo21{Sr%pe0X6MwIGp0?QJ@Z`54QI`^ODMwziB4~h47OV$S^KDo{I7H3&|#x-X4P+w zWG^1oF{b^XIHfosh=UF~Xkz=M_G6fO$jC{@j~~7F=t*PRN8_KJlMfkm@}NP3_da6M z#6!l6oiuXPxb`u7PaZqQ;6e5b-utNbqdLb;7~OgJ*m3QLP+O>W%G7;loIUlR(UT?* zI%F{9O&*Lt27;d<_A_yiegsY=IC0W3`2VPOvX5#XZ2uo({~wC~^L#Fnc?1_f{MfaA zD1e`=*3VG=fO9~Gzwq(~S|pEb9LDOO8;+U4jcolRt7$3I@P@?BDB98=N6WPr(~QF| zYl1^-@rJ!Q9fda`Ji;z1=~OO0d_Q=QGj$BnLbExO6^6fI;eR}!Ig`yr$fU(zb0+Iw z$<%cjSL)>V1v-Z4?0s`dHnr#9)o5j%-xyf`w?4G_(KJlf-_97K5NhTf{fRx^Vpw-W z(_hXb&$>@fYSKxbb=QRElH^(UJsC|A$+PY|0qg(P$5{WfJgwHjliR6Pg5QntTzCUPwJX7 z+0@9G);(yAu&I$Tt$WlOVY`RMwC-U`hg16DZzHZVfJW#xCI1k&@id#z>Y(nJvFmo? z`r8@nuBr96Ga64I+Zt&7?Tq!eGuGeEC~sBR5K|obX;@h6%>Me@8U9yJ8irPRr`ziY zgU!XQ4!7!a2rW5m0B_0B?Gf6+HlDVW(d|jz^|v!B$4<4bZspSTw=*gZTYo#F;*Mdq zP-qoD>u+aN&%Jls53awR(crLd`}Fm)(*ku==%$MYp51 z7QZ2)+1x~b=CUP6x3ic1yPdu4Z#xhzOR-j4Ofs9QYSWk2EZPr<3&2gKbbmhG|Gs5N zY3BKEEAIfkj0+jfG&w+T<65$q?^~LDKy`NBv>@|-Ybo8kUw_@QwUqANe?a%{KcIR& zpqcyE-_B@O&;S45&e*-1*Zn=ciP0lDJ-BtzBRSeDT-U7=Yfe3qqfOcElJ9iISx4-& zT6^k|7`;YZhZyVfdL*XR@p|2o=#dz07Oq1ZYr8!X)9To~Za?%$Ov@wk*28uuriZs0 zdL*Wmi*1&Z#rb?3`+EOPU#vS1FUJ_GV|#m_gQA zC-~X0bWbl##5p4J?%Je_Kjoy^Cv~1Y=hRcDoqK{GTW&7FW;oqR@S~N@6y`A`D)F{% zlxTU_bL?PKqgxrR^{|;(w=#ybINdx}yL{csXmMT-{;;`Rw=!CtyTsR0d*strr!Da{ z)gH-cb;c53TkVmIRtJ{xHP#-O#!ep*@Q9p)LD#oo4UOqeELpx(A_8=E?HWQl^qtHU9z+q96M}a>XN0^XxL#R zQI{;OhQE%c!8xQwQ;WM--L3wc{nehVh86rEyInP5+_&?h3$aDM|F-F``$x_?hU$Qg3&{ao|Mu<(tiw1|Iyh#p4Y4n z(a#uV9nusX+6_24hv7=G+u@fh@k3Z&+1C4t^=P?t<9@ROaW85K!kAzdlAK@xB z!UtKIliJ7eK3CAZ;$`%hu@i%wbWHn%pvQG!Q@H&I{&U>8$s^y>&Z}$qmu`}^k2nA0 z-=Zd!6mN?;h#O;B)|TEB+sG@^?}laC%-edm-5uXOu18s)_68I();5QlaM&zn18^KZ zDo)!r3el`(BUg5vTqeo6Casgp2J?;GGHr?CO;491tpg7>ZFx3hv(AUwcT8Aki8dA* z&$_j;?qx&DnY3=5tV0pgx;3&cs@WJEDAen@Ns;FBqDbv}H(@iMZyZ5yWj5h5ue&g`hjp=;<2N^9-c;7b zY2M#p(lKL39ltIX^ZjN?Lt7W4)j&VA!6pp$hTYmtytl4er=xwGD@1xVFqK{r(2T*V zq?H5U zWwo*695Xtv-@h!Y?Knf2=)C^duVl6D=L!>@*Z=WAR@>jo%${0Jt@I9a4eO#k@7B{pYXxSl((dRf^Fj16$!SfrL5Bxph+dj+2UWqb$Kg1J{fsaU3PIS)n!-Z z{bXtz+92h9GL^TRu*)|~^n1JHU6#t*U06ll-dVQu^Jwc|Px7Kti7ia)XgK;u)X}nU zC43`?u0!~UJ{O%OKx`~*ANu~!moB7K0o7be&w$5MHx z3EQzf;X6OiJJ8w&Jf2`5&hx_-WwnFz1iL_dXT6kQ7v}lu6%B3cqj~<^v3b7s)r9XN z@l~*okuS@3d^q8|SlA9@6YS&6n`ISjp0J7?mpGQnyHvVV`iM`+_Z93i*ZG2^+)pZA z)~49y%-f*zrzEe!_i4vcAACmg>S;T_f>?uX|E;!F@fBjUeh$h_>+LG>RpiZ=pDWmB zrAr0FxX-pw=_jvuU4EGO;0vmcJ${{FUz869PED{cNxvP^yf>&_*5@XCUsf3vc{fVl z9-Rr_P2#JRakFF3C465OR%svKaQ#xgTZN6fI?4M@$F@x{^f#=J3g35yRpRs><*nFz zuVZQK-Y2Y5Z{L%=ioN%H{idnGfu*zv!4eG%}ZZcMO; z^7?1D&FiNfn_&N^yr&d8eoS z3+6m5WA@A>?_$T&{$+{eRrr1^zB#LsypOTJ!X#r>g8fACcjxg5_EYu673^{GRr=?j z3A-bm3p^pLGEOfQRvEXRR2dcQ=dANQzxmNbm!}vT4P)Li$y=1#v0Qm8@_r$#qTert zEf}4Yfi(onxIgWOo)KRK`<2SA#M-ZAM`axRjq|1P_pGqWT;;dID)v4ntTN{PPFQ75 zgYksper2w*((|Ts5X=|o)8*-y{CnwK@!t!=D)sh$^vmC9I{&K>`#GAev8 zN?yhHSTlX9hPq7izU0_5NqziT^N5PP)sk1q`?7SY^v`RAtw>|&FTz$nl$7yT=Q|?7 z{^q_)=S_bXUuE2SRc))%Z>$wIe&#$LAJjJRyt^iR8)n(T;7!|a4RdPD_39tr zDB;`K#;r=9Q`^M)x=Mdl!6}&!8v9{=eG;1_-}V%Y1^v3Ls;6^)ds4J zbnQ~xL%LM>_7wI&GJmPPQ&`%E)%KFSO1ZwqspQ>9e3g3JSMt*SsH}*l=1u#*8up*K-m36nuY`ORJ4Ohr)FswiTo0z>LJjLJ!_rto-^_YT z`|;XAvNv5b)ee>}72jhG#=PnJympxJ)zi63ZH)SZ3U;LU(s@n|8yW03D%eq3HV<=? zO208a%jO)|z=!QZ>=o40`Acm=mVNfvhCb|Q$-DUSq|IRej(IC(OmZxlztoPAyereb z6Kf;tQjv$v9LlTkO?E7q>(!2vysOea`*_K#VDGcM)w(=Edl{AbJ<DXO+zpzR?cdCpE_5m*=jhB-Y2kBb8cCzH9dl|K`oU}X_sfnj&uyIohe_XbEz6O%@BW;J(=1E-KSe8@p6`YRVibp%1Fof z+Sy)4G7qa^eaL;O6-OlU&Xv3hHcMDV-fYLxzIcwxsQC0el~M5@HvhPnR_P-?B&_25 z^MzIVoDa*VmHz$$l~L*IKBBx8z6*s_V&kLIIbCzsuzyeAr*o;=#~e%MX0?l@ONH;_ z!YXw+Pgtdl%hdKOeZ;5L1}oT=;;ZySSBtNL;Uxz5Uv~X*QkU0oepTI*sa-`ys^Bayzu}Xy^p=1?7V*`*cbEqD#ZRh7bn=4981f+LD-|) zCwyP#`VH?Oh9=mJd3_%Ib>4*uhV}jhh|7-K6YOTJ=U&OOC-+OR1;Uozm0(!=lJALR z{agEr^QGl}HP1J^w1Mwy@?zO(l`^oWK>yv7+KW8}V)v$YU{ArY)PHCjlvnYy z@7?cvT4KlT=D*rDsm^x@8<4EeYYQDq*3-2+^ZH{)Wwi?5U3q;P)*zL6)Boi8wp%w~ z-{#sN%T9kj(d9dewPWr}u)AePr9Qr!*LNP6W$FG)?H*z2-c9Y^yuRi2SvK&wMBaUQ zeXqN-Y~*zb_C3sHbV)N73#eT^&yqLTpZPVBX}eykJhk z_EEvGUqZf0oMOL(d=*`=U-H>)8{!oEB_=P8)5n}IZPPyyR*7fqmvFzc5*thNwZB{4 z5YNlx=Xq&eJ}tg^X@Bq==S#6?W!v<$F0p^W{$PCC&ar<$T~0{-hy4R$mDs?%k?~yV zOR#@HzK*m$Z2thU`$`f+zgHht=}%t}R_RawAgt1dtx{iC@zo#Y`wI4=wbg1L`zN)T zbWgDMlCX+xf0nN*`mGjL(eGu&X{B7etF-pfnb`Z6y#Dkv4fXq1m0R)i-z2Y6N7z5u z?dB}2l=}~1mGJ}bO*wv4^8Qn?c1EfT_8zE9CGWqa%k;G0_&45}Vy;-p`ybg>DPyhT zufkWCyb6X_6_l6eZNp1c`YPpXt4UskuT6ZZpWFILUIlwYUe7jbC}RVcm)O>}q4TBK zM)}$`nCn!^-B?&fzfF|4f^90kQAxknwwZKJ_qf|Omo62)Eo4W9Z%fHbW3sKkrDY6I-V=XVwzsyo%ia^mCfFY0OZ%p_y`|rTy%N4b;+xW*V8bLY zZL4huxV&V{Yx^(BOZ(HdL(~tY{e9cJ)OS|O#hjJvigbUs?X$iQaz&!cHQHlL_b1yh zC*=Gf9pl?DUn5qDXMbmt_SwbxhGg#3_G=v5n3CtOemW`lSz=kX+pGk8PJG{3lVB@^ z-S$#~JumE=s}t-6VapCouvNq`9xY0+7sa>svIKic*v}44u$P7X{NM!pi?CNx|NV^^ z=14P3zJBOSi0yt(f}!6aw(Fb(LmxrEEIlN_Hp9OET|6|BV5r9fhBsilO5XKT629H? z{M;8C_;wfH4aX;Z1BIR2Kf(4CcHU+QwwJKkTO`;%dH&wx8_L)(&u9I$0UMm>#~$5) z4bAHvAIa;xeaPZpRsNG?ywCsUMnm{ z+1$#NPa{3jC{6T|{^FBQt9%6pc}uQvKJ#emUyg2<{<|F0 z3(E`t2A?q1+q?~+^B|^?Pj+19cJS9QPp2IP2AaCkUg=!QAzxsOjjMLSmMV@6T=Ol- z+xf>lcBO4r{_=_RNF&C)-<+hhh2Aciz7YKYUmNh35A!lT(!$SA+>BR?h}Y%&kP9^Y zv<&S<$GIG{^hhiDmhUOP<#_#Kc@w?@gS_R~rlGv$W(Vk$FEGS7b$R4Xr7n-)_0%#9 zJ$4k#^;0@9OH;W~@p-hdu=n$5gS1yi%Op?fz%0!%(6pC)VOz>q zVB~|n#^<(G_!{i}8v4f2y7_lomjOOf%X@+5D#W1-94mz28PjW#EKL~m4u2Kf&(~tB8QZ1w!C|*>+gV%E2j`AidZd+k&p1it&U{H2 zWuNtu$~`MElsl7{rHPNR@#0f>?e|^GE$|wN<*r@~`Wd|nTw{Gsq(@qr_n)hAR1N)B z{Q_anLE*KqLq`!EvvgpVR?WNmfif@4WnR95Tx(-8XiHbQfiVtPN6+CkZq(6p2ZMf? z?1K$o_zmg-qz@m)R4^W2WtzN9WIu_}erBlCB9%;r4`64zXM|=fF zKIm+Gu5*RYv8W^ZS@S>Y%K04ah;niEF4+J0bGUl*v1 zwNbxmT{=en7zganBMu%xpS~7(*^ftFrK=wgEd0Fmrqa(#Z(5RKF4TB{qM4)Zgax0Q+5Ovc0BT?(vC+k4`8h6sHy5h z>C9WkOW46VVc5a>4fW%kCgNV{z$`85S8bvG?y}taWYCB|9bFZl(wUcOjzJD>V;Nyb zT1H@Om*iu+EU=_q21ehLk3KChs~h<~u!v{IL&PNgyk-i0#ozE1)8*#^qu(Ike2VyB ze^v3RW2}$2EoYm+tBI-NV?VIRuNlw$b5=A`+eW)XKgJVnqhG={rPF^UMqT&l zlpT9?N?vM5V9Y~%DKG3zPwNP&zP6bN%RF zlwrPid8y6=lQIt34171?DDib=-ceZnGw-OY9kX;`kXvA+w{^a4oA5bCJ6Hzwj54Sz z%b*=0PwBFwz`)1;o_x`-k&j~(WdugO7(>)K;)OPmPid|n`G}EkY^ig>7Z~{1ACNEF zekw08>cH5benlKuj7h)1tPg=5*1z}|mBx735$&9PO0;wKT`xb&yye)VbYPYyJB&u# zH@=e`Gda#Dto{ug)j1ZgW^cl_)Cp+AXh-#%E(d)#UkmZqF-wm$Va$6ZUhgmZd|n^F ztFT31N0|7Eg};tjdZbnJQs>A^olien zI-jn&quF#iFV~#R%Qa`@RXW#OCB|~O=A_(Mb8?L0nv-KxvA(o)m0Muoy94c=XGbc}i!WSYlB}oI{46IUi!VoDW4AN(W|Xr5%e92efyQ#{qr*z^k&O zz`QP5ew0BSSO)crGL$a;3JiR#5AucYQ@#QN--6NNTQIt-y@AnQ)*J1KdZSJELucB1 z|EtQYblDqN`bH)|}7vSd!s*1+g4!InQf3dM|-2r zl&7@PFYNCxf4bE9@)x9wuDgg&>EN?8$4H|;FurG+@HrNK;eKZHCEO#W9o+8>ot3Wr z)4-@J{X#p!FR2}YF^;*WWBkSXjsD}BPHAp0_*QsZSmAvv`Bokwz5)Z^N*{YxKIC~5 zz5=5>=0&+Hj_Ar4*dvTn^amEFdy20Tr;gEA+~1&1u|B8%+-G1Jv8SMP>Fk)zPdUfL z=Oyan-)d#poQ!i!&P$HE(J@O0hWSKbF+b(pCg!J1AHTEmj^EkyTDtNU82K>QV;M28 zlMc@3^FJ$ZSMeR?b6}MxK4JE50&~JFJLu_{BY}QFb0Z${*L_SE}4 z(*ak=Oh5cGXQW4(V_45#ySwQCGgZr5*7OH?>2U z>X&OA)^E)D5sNklrp__nRl4jcFw;S{soanwzQC+5F%DW?`kW!PP2;8Xr);Y?n|oJn zQ@LfG^F6S1wm!$^jOcTG?r43IrSm;;I-k4>@yzlgo~a+}i24=vVd=mujb0YbxF=u4 zz2rn%$;WvF`C`tH+8Y?-o@)rE#r%)uaUHW(!(LuixG|pL2USQOV z{-DnCi)>;)5NRwUbf!I_Gt*ff^G3Om9%;-=n*9LzqCX%XV<*zcN4+?|rp}sYgLWT9 z8u_RT&k9jSoX?>g+Qc#n+dMteA}`N4uq~>u1C3bWI+blz>(w$n(jqVGjd{ZdOsDP4 z8$O8iNQ=BTpr2$~v>B$eO)+n@tw@hF<~2Eg_cHKnnClQ}#LSnFXMXnfTk*4F%)`27 zxl!jVm;Q(}D+7G&L&#V3Ypy@}qJLpK;&}`9QE~o&eHiDq?89PRt912E1x7ya$78Kl z;q$(oWpEwJwixSBwpFeh*;ZqXsC2c}IH$#UdE#cplJrxoE!#)2#$P^+HKsGx0;5ma z_UO}SgK3NlQ$KF+v7uk=3sAq8vDTn|IwL3jx&Ba^%7uQIW1 z8R^iez#=c_#gUhDU*_f9QG2hNXX)&h ze32e$k(XJ<^DUuc(ve zr*_8Ae1)@v#k@VzsdLQbjb0_&G(VMXloM%D#;3NE?pNMI1T<{B66-A5#$Ur=2h$^s zSlC8?hi&vZZPN8*%bG=cq(xqqOWmVf>c#SCTa+8=k;c46-{^e!HO%Ei8Zqj6)y}em zzlJ4t1V%fk3-t_Ls4LTHNAN{@q){I7TE783y5;~~w4LenOYqSzloM&>Gdt0zn-8pS*O^}WDALFm{$pPo z{$pRf40Cw)#r)+H>5)c^dT}q1I%`i*Hif+f20rf7kx%<|;-k)#5g2vhoPl=7oPp_F z6EJVA4I(|#s7u(vw6KHe9AB6>#+gWuv@|cr=E%!&m$q|E4j)8%q%kk$a6Dxh8dpKP z4v`jo94E;a<0bjRR|N)noL7-A=2t0SV6^w2t5v7kt5UskKZmcn;eb&-6>A zF)wxIS?tL#V{dQ_5!uVVK-#N4!7`op24?!7BwgYReb^ppA&+~8l&8JJs=UBL7wQ@3 z!l^6MX-DuydZe)o($tH5pKAj?NRKp@!MvOkp88R=4}9K*57XHmnK#;H zq(@rtalTHzn75~81Qz5&%t zQ8x99GE)5t4EC~JkT2Q?`HC1v8XxMyHqE+}6is z$-H52q(>UdKwg{6bIup@anAcV7v-E#=L$3@WO}5fc{vx2yqxDS59e!t~5Qo%{R+#&WZBFt*_gb9P>?GH_lPpSl3{9{xIJ>A)1J+H6Aow9o`Hop3*4t@pz*mV9n zX6e8zE#ZTojZeOEInL)8%lO~^z#!w%FP3>9-ClVgm2IA`yn!+Ar@xMKDEK_f{GrNw z6V?S+;d-7v`{9_S^SlbvgfTDbw?6L!Mg7+2eGv48z~I~SE)<{Afmxbico&mp@7^8n zNby;xj=O|ia6GU41DnNP$1I)iQcH~W_LDvH`YS)fCqC{rzWOV_=4VELy~1C|EFGAo zm3&L@65mpl>vF_bV94{t-Qs&9%1GoD82FaLS1fm_`$c-WJYm)rpmV+<&c(aV`G#j& z8U9HV*{gK$S(-4~ix{#P_ZYG`MhxkbCW;|XSDboW73Fr|ec{sokvzsOeBhr*am>;c zyY2&(fwrp8rihR2>|U0Oc65)oU()wpD873y?8;YQN70Lt90oc?Gkxwdprx@|17KR3m>9iWBu3mJw2itkv>u@>FhcSb8 zL>Z60gZ;Fy$A%&g*!p;}_r*fo=(s32u(u6TD&Wc-JKTmDxIR9*U{j9U6D{o+tcgu5e zW_GINZF!NMSN2cuIA-biM1ZB0<>D-HeXsv6&Jx%6!dNi!I(_zIB+=Hp&R!vkdxPpKnrLrK^n8_q1*PpG*Db z!=8IEuhVCqlvn9I|6Gi#HebTH>Ysip%b*X;Mvb+~1I*<4e6k`hFvzAn^7)wTda2wP zr=!nadQ;IK*k|+HfArZ(=XuNmt9$!c`@0_%WB1zMJ!NCJe{#y~@bui%WLvZ? zw%KS~Y}515hp|o1yH0#cSDSXsYXy`>tg;W_>33Bu{+Shp??$S&lI_rlY@N zY)tpQiLo&q?^l#&W!SuQJmymR)Rkk&oOS$N!sye0{HHb&aBrCjF;4} zL+w0Qy2=fVWek5sWyJkjmccu`N;7%Z4{^P~b&9VCZN0rZSHRjO~bXft?U@qdq5j z%*%0_pY4e;S?QXC1Qz-+)}xLX@2n%Xg{UK?t1T25_*h5ei~30U0;7JMZ*VRWzUO#F z|MAm&;VY$UEDMZnls;g85caY^*n@KmOOw4(M^AsJEaT~iRE9p6CO)O(vt^bhjQXLi zns2?W+8hpT)%@q}($nR?z-R~i4cZa?Mrwy+Hb3Rw$Zj7l{G9KG*x{asKFMafcsejk za||^19>^Da50WFkh@tQS<3Ie&{RQgB_7VCiUF|5a$jfmg@^WlC1HR|@aYmGFMGo_Fof4=VDm{rM55 zvwv>R@_KsiX_6P^GM1uT#uI(TSPQ=>U9lEel*=*C^V)a>U)gx%ez7qR2wkW%X z^B4+U*5H%eQEzK7*3&QgT%XESIxtIf3^ePPeBslSFEHxD`k*camgwS`&706?ucZvX z3u@)z9;uZv3T+O10G^Itljp_$x5P-zd%rElqx* zUX(|jLtd(LV5Xmcb}(#Xe*t+G!-1K9VF&BC(Anz7eSfulKpo&K`B`;T^|LVf4f4#V z%IiLNpE^eUXa_%MS?HYT7e0u3V>=1oGuBw=jJ42N>5BUTBOi1&KG(0p7Z~{Hd-8=Y zDPQQq{+WFQ`><%|X&)9CeZ_v<`crR%Y2TFgV?6ac@rTmy#2UOlh1#}mgYUQQfqe4eg&am?Bb z_PwoKpQD>>%(KleKBx9{l^Yn#Mc%cn1J7&yWytX)1QaJcs_kxdu_iFy4d><8o2bO#|Gi&mGu}APBCQUznay0nVerd;qM8Etz$y<9_ z@Yx+Plb4?t@^BXGU*h}Op(P*Ayc^%5f0cZ{*jIc%Ke*&8^xL=Od;UoAy>dm#SJcOm z!Ix!wzMp*9hn^XHw#SWfnU?UKBEH?vX~K6($%i)NpFb`6iuxTCe6ZI(r-~RnB>3!% zzwG^+VfiClWVHuz&Ox6^6^6Zx+P!Phjx0^sVe`dzfPFeu7~`3IN;AxCx)h%(roGqW zKgEIV`Ffi2UT}ou=@YBMqFkjJW_fNjKV!e}c*ATAz<#2qm3&ivpmNXcU-Ds$GQKI; zSA{M{&$T$fdJ5xm=!dnWr{TRq)x^ z?PU*5;qam;4Q=0fbkNGq2 zfavqIRe4Gi_BHg4~n2-zV)pd4|#T{5qre?uqq$V zp*Hey9HtM>!kmP5Ig)YRreN?creH8Mr=iF6Z zqyH$cu|9}-y%l9}kF&8Z>F3ElH;cMt-e%=CV@uq}v1-$OoPS#8wi(G~+UKG!oa<8yn6WhevKg@x`Z zR_JNq@;smRAM#5lVj0dwP5V#iWC*Y$McEOvAvH<35pBjPr(3APvd!K_6 zHs%GLue}dz;@ZZ{8#I20C798`4oWbi^ZKvQCTs7qyd`aVR$aw7gVOvmW=Od5N{_>tqtQ5&pW=bSxt z#+jYdPa(GHkb?)0IC$u=gNF|~ciOCJvpY|jal#PJyf+z_)!Oj;UkIh!@TDvCvIC|Z zZR-P|8D5m&Fj#HCQ{yI0bcdh;Q%Y!|L(i1ZowoS`x0lejxo3fW zz88}szpMR;;i*~o2pc#(;k#G+MFU?*u>16`Y~&3I_C38rtdw!T_(pG+@Zmci+)J#K zu}Ih+D-yo=6H}8$M)cGII&juqd*Z*Ygqs@KHD(#;rKykN&bbt%w)3SyqXW`1??6$~t^i@8RZd zR6xaFl1WN!J65gf&g%<@wE1q_Jr5V2Y`fAo&&HPe7Jpmj>IA!n?#0H|j}z<$-`M(P zDee|Q)9)&r+4faM`MhUGMJ=>_!z*TWnem%~#^+^5ZwdpxIwmsq+YDO;-{MlY)S}k&h5H=FYCi(a#Sp<_NV8D|?+*Gbu3e?J+}q1E+gl~Z*ml0bF{7iq7B>4gW=DPY^MxHwM;G2z-e_A= zN%rXNqFWbVML)O0^n)Gh>bvsofhh^FB@3G=P_h? z5Leb47g)k~9%ctD*W}HMUR&5rpOjy2LhtDHTNfQYx%lSI5Z}C6C7gEscB9|;o;?88}h+YXKyo!3|Ii=$YN3lp8!S)Vi2w>u3x%$}}%Cm$t@c}~VL zR{27h>IU-m&T88~>U>7$^&buccAqfO@U!{5%C`bnA9nhsFwtIDUT+o5>n+M%jWYIe z{Y1kDc$Kv0UnNg8;>F^oTJCRe%W7NiB}{Z)XIcFpEOqJspmd42@^bTCQO`RrGCrsC z{CsR7?|7{+(Ru!}-vC3qWsC>?&Z~gom=&L(FJ4(&;tTp#lyTh~9dr8Y z@b{u~ga!Q-yu$eI--HEy#~oSiKF5NN_#$V>zV8dj`>gT?9kEF?u!v#W7WSeqs~veV zx$<1Jey^>U*tKPKad5y;G5Xb$;=M8+{&9e7BT*bcft}L7S z2VtV|m-Ie{_I9*k*0$JYZX1WKoi_;+o!5^6pXYTtufGLt_GE3fIgK%SQ}p|HDX-G= z`Zfm@Iy(&v?ffwBuS6^FNVP4uQ$E~g z@l0Vs$9Th7i@XOym+$^jd_fO;3&s?Szbp%S%-{0-SC@(}=osf1Yej#sHDc&<B2TI^=y%6+9%C5WH`*TJ^q*OFgnaKb;&czh{gvVqjW|VpkMOt`jX1@)KElWN z3fAsrByGP#uR@A8!~US-Lh(rlmGK_PWF1l7dk~|VI|vJ1emWah-hHePt^Q^7nc}Np zlMM5=oYyx+eH`?-FwuE^gPXE!sN^}F*SB~-Ua$MOB^q*7^63KI?awlCp)HeTiVcd$?K z>hFb##$E=>=e`8x#TUT_5JH11EqVs$_u8f{z>z<&k z&avkrKKTfJ_p+?E_jAHTtM7I{TR%SHW%=*m{}x~PdD6_Rw)3vSL_?P?i#fH^D*tV_ zi;sG}4M(vMf7o9!%*Up@{)3@e_MLvhMBCguyXRr$jXviWXeUQqCrosn{}k;n`dHEG zuR2zXFJc@=SF(#dHbkQxAs**FD?av_qbF&nZM6C|n^%oK(=qS=)VB(YKGrbo0@^V% z?~ASfZbv&m5dDVt+3M3BQ+wkY19rmRqxfsO*c@u)FVVjY#2$sl1)o<5^ZAwQul<+Q zj*iu?i~E53jYoJ>Kc6Ss8e_m$wKlc+X)S9*>HUwH+&Okq=je{{laA@c>y29N^pj4R zHmh^?DN{R7o^#eIGp2P;KWouqW7Y1?qg-;e%-%9^0zK38jZFJ?6MEBabOIIcD9ATpIiV&LK?R=u6Eb@)-95U>H&gq~w zxv#W{TlBE#&Y2yDA6KzyPuf&$?`LmNQQ}1&Y*pN;?nUOHSsq|noX^tpd^omkzxxGY zqFp6xzGc0`*&g0g!My3Ig@W|&{@gRK);wla`~LuF)0!7QI35Rw*SzS+MTJ!OjPqs; zMpIMMva-jQWe>seGQ1Jl{rm|d$BePg9{KtW1-gWPcf5c+DH|F*6*sgiZSy1%x1B<9|U3AxYR|SUD6&%9ZAMajb3#UafT=m)GA{7bY4Q zK2vn7uZctp`=-(v_IE}Bon~ltS+O)Gyo^j@2yf)sKJ@C}iPde+Y zX)`)coqp;}_5;=z@5g@)9fD-`%=^vlJZ=MqDtV!+VXiat z(jUw#zr42K#=0o0wJW%>?kO|ZS1V75n- zWs$c7{nqWP#22(x=RQp^n};HlJ&*C(+M|?b)%jKBHN8-tg^HJJ81ypC^$R%`J}%EN zlxLWiYk6U(<#l_F54swk>rCtx=s=9W@a}8sFZYLp+TjW*w4@rgW7%Kcyu53FxkdTL zK0<2uqN^%G>Z>JJgw&#vD?;kiC0B&hzyi{k8H(WdNhtIc`90`K*!%qAw!(roAAY)u zb&S9#EsqrzwE1;lmCy3--UQpCN!~?GFslpH3%gI`v3m5pA=@x7!*oC%tJ@^+LdZ7E z%dot#$@02wmKXXPpV{%+VqgT!so@F)$ILVap6J@GY+oF{D0-T~V+P9|SrG$wm0azv z=HikoV&J-xD`KF%>_grtp%#o!AO4oyF9=%+{pqF8;pUFWUtJ@^+LdZ7E z%dot#)AG8#mNy)3`t>a?hMe5_p_%7)PMtAl*6eBLc5>EOJ5u4X0amxHzfMH?*ka+8 zp|UvcJutFp!^Xv7`G#_WgDpI&d&@p$EL`Ex)kQ31(P*p)Bx4nS^Jm?OPSem^u5N-bdBQ zW9~jpd_kK_53J^8nm(w7gY!+qfe@dS1bx)E%MK!Fv&VJ;u#@ZQhM^Vl ziFC8q`6Asg<9lsB;NDqnoO}R36h25s`0zo$GKkRG^D%>;!0&fpun)mOPkM9N!v_7{ zU*-8%c2(Y>%^-N6PtazZVSO{MVVL3oT05#}PS%xi4EbR(OvRMt=GA3~$H5G3e8H{7 z%%kW72NqCfFFCC3h`lVw3OZy^sf z^GH+A%iajG&5Kq>U%cp}#Q~66D>vKP*ulfrTP7D9*x6P-#NXE?KE#=2$K&|qf(gpm*dL; z?s)li;d_diN*V%pJdflCkt0)-bpYB_~+_4UAx0x zV3hR4cjHgOen)l$-LWCo=8p;sn)WPuQdrO`j@WCk%|==r-eVBpzaj`;DZ@J~ySof; zjLCdx*&VOo_elKS>zLDAQQkjOSkR{V-OfjgK${hYy#_06Ae&fP5skFH4CO7osAHSf z&n@jp#(S~_N4a)Rcf1ppvHQdmG)HiKxZ0#yrH7w=X{M;l&(qY+1jYYoLA?{IYC+7!O#~15Xso#Vl!m z3x0{@705BbwR5`Tt%zJ?`{{o%b~*! zv1;o;RXvMp`-~I}deR=Kwx}Yfty&g}FKDYG!}?-~SBF`FH?q+kQe{@h30!E%L{ zR>uj*@hGf#*|l?;jp+_w;|6V2@L*}h1E8%s4C{jx=SFqR)ytmaWC&I~wdtCyF4?tg zSa@N_zg)8X%%az53us;uYHde|YuU__E1=6tF1%yqwV7ovm0TwZT7FL9r?&G1J)bP0 z11g(x8|vTm+Mp1hZ7U~ny1fLU@a_)mnx82wXrA183eM*f^w@J@-Z@>dWiM5+5g*F) z$EOJk`k%C}-ExW8M-!dQPQoiN$y7Db|om2gu_t36jn<%g8fIO=-guQSp@Bs#iFDL+6zjq2->Slt_a#!ORfmo3(H-F2*<68jM-M^5nKH& z*%9G5HVH?k5Bn0r@gngBZLYqsE4J*_DmDU#&mQ-%4cc6NrT8k?+$Naom+~#Ux+~wZ z3xt_$$gyg4c~PEWUM?}_v5-pgQnq1U2JNIx7G`c+*luCwKCm*NtCe9ozqat%ALi8F zr|{Vbs|bw&7GQF2B2{I%qY@F~00cwr+&pb)l3 ze)JdlJ?O*!7qRl9u%OLf(Or1D`Sq_=zTtmBtXv~3Xsf3ynqYIfV#_aYf_dy&{eZUm zNipOx%=21#kZm#GWrPlfxh|o<#f94uc3NDRy{|0>?1jw!M58|7n*fn5*-*e&|eKOJ-Wu*cA5`U?x%{FPU+BQcLy z`gvhNn-6^`h`hreL0sG{zM!p6u5W@}+!b3MG39bB7SeVL+F~HZkjF63Yvn<<#ekO) zIvD1OL8MVm|d@TiS)Mj9_-SR2dl!?689RQ%m$tXaEkvWF^u z`9wO;e-};8X{$B&Xz-0djXr*q@&-+hEnn3Yiy3I}9f&_y6lDZ$-gaF=4m}_8LI-Oi zu8ZZt49{u^zkOQOCCdog9(uoO2&dW0y3?qRa;_CGVyrs84R@bb zR!7hyFpGNpcz2)E=8C^}#bOo}dHF(N>00pxJ!WFrD+XHLakG7?g#Qzd~ok>xMNY-5W>x?%h^Www48v%Hi$Aq2s(qO{wyB^Jpvm8 zkNap5wE1+k_)=`yUxh`w`NjDx)R1mIFuvE;8Q4zO2jl}R016-6(>2uoU5vJ|6JiG6 z1B3DT)u;aE20K0cUohCGutA$a|4xhpZN?eaH$xhRn!%7>JE>?oZLGl2XuY==Lrt-A znN)UeG1Qc+4a>+*c#CoYvWYa8Jjlfv?ldkvQDkLIi7`yhEY@Hu}V#jL`~xU!?I6Olal6! z(eLI63z{2Hzq&|R(40;@`#-{hHVeHI3EHeR>@`?B6y>1j?$St;`SrG{$Cc%Nex)Ao zLNXd;Op}8i@-D>Vp0Xn7VK2b4$Atw=YgXPOENEIL>@`?s!_#S{Wn3~MMwjoI#%S19 zo_SAgTMqpX=CJN&q9(6*+ni>1tIO(H7PQ&pd4o3F4C{++<$ke^R;SB6&OoNA z4_bC;IRlBIsoa+>hNfD%RlAYwU>~&XPzb?($Fj{Gb9(d~3?&PN1#SJ(235X8@sX9K zzAq9q?fym0`Orski`M!e&l~CVi}?ED7awxWDbve3k0JcQvh8l;(Oh1Sh$)Fh$Ad_I z9v-+?8VAi@C)#e%R-?O!FKDY>!}?-HS-ZCEJ) zK+q#_-s^GS$OwAK4yd93YvUz z^ss^rtmgdyhQ1j5gP!sQ*x}I`^r;u&js69m*J+j!wiSHD?sq=dl|CqR_H^@0!nY85 z$>U{S>Tj6&sxPr~_Uv;zEplcka{75~BXZK$d{NuUy_A5GGv(fGGwk?=?X)vt)tS;Z zXnNs$UOPe4b8+}IXsey}(wj^-3{x~dL7Vj{hCGH@-adF_+6T{`eZE~o#^+U0Q0;?d zUqO>$TY9)@D;3w|y}CG&{1fExlT1M~j=u9#Gb9U|7R7t@plOM)*JR1m8RycHv$|T6 zoX`nNmKU8v^xbC3E3gE27vqFZ&{G~MPv`_~+Ao)NL7OFp^}&+4>bosY_bYq24OAU3 zuPJ*tLh#v|vJ0xs67+m|_%xuEYl`ly_Hhj_Yx);Z@uE3792_s2%M1s%F+9?bv@6SbFW`_I{ zhRlK?OQm4YW2d4GEq0}yHsyDBj7EVrLk#P&A-G4~dCEz%PdeeiDUh|%A<~{_YUZgL z>hp?Ov_Ytb`lH2Wc)$5s_EwDlTYPxT*pci8`4r$M01h53utYyYlnYKi1@C8xa)HgK zK)+0MxIm%zps>@&j2$(i5u6S1fJP8%jS980?UhPT*I^wGHmrS882`x27FUKXCAKAc zGqdj#33icV*rVgayjyeCNZSpiLL}hfj*p-(4`&6`$}CTZ4Sn zEy-pT4Z8MG?TRE#q6pNDM~)d8aT@zuTq85k4#r=Ni$J5{TU_pefm1+yB7Gn_?WoA0 zxA{w1kwH^NI4bCn+owKkE{$b7t$QdYixG`G0;QEa;uSQZ~n+LvG)VWv^O0 zudA^$yVmRuFg7~Tim@|Qb73so;+E&Tu{+2J)-2Px<@29gg#|tEkMP}T!h+rl1#R*L zVL^x7z8gCX0&8bXaX)c=#bHO!`QpjKGfB)@?K|Q*gIg@V0K>iq%r#vEPJ-WvRB-)cZfaG zhvSA9c>V5MR){p@nV^FY*bR)>3ZYt!4j$yLnx# zZPG%A&{}q1_ITZzwP>O|E}UAs#f5IIXNYtj%vj~qgP?cA<)r^$GlNgiv}_aae1qmM z<@ViLb}+c~T38#4o)^1zz6a3Sm=)UYA@b7NmtVy1!}#5Un)sv%!;jUi_h6Ae>R(y5 zqwmrOJscZ$Tf1dJ@Agg9Z7z91zvKAQ13{YyP*&eOaPG9T>;qsmeAJQ4zO8Xk3o}n1 z#9x`*tgq>`{L3$nZkI-OgNX;|*Gw-VM4dq|ln@TGaQ*u72TN!JhZ0#Rm3zA@ZZ4OQ z0hMoIYX~WdU-^?lR_$zMOvKmD5!Z@ICD*wsF@&#OkqWf8D4yNiDAuj*~i}k z!w@0I3**kg%O4ESCm7^dZ6xwmV$hdY#mBvN=B3^I<->AUOcEb|`LGPql$T7iRYElK3Hq>0%5sAa zU!;74|55S`hO*C}t%5t~G#T$B6tqzuqjhGBhJAD&yR4?kKCWM?4A z(2cLXtU8e0g8>uk!%@Zha3d)qUgQ~tJRcBd%A-TIO#)vZM*5x~!C#bKD!!mM-57I} zzY7a`+qa>>t%L==-H*#PW6)7npT;qBz+e&Q|2tNhA3lFjDe;mG4N8LO4m?toZFdiuZ-=q{d;kf67H8=S|@ zJ3K*i?HEg|phIrojU9>-F!XjYwtUTDLoSWQI<(r_ zk#5VWU4#X_+v%93UMei;kkNO;Y|Z%b(y$q-#UyZa*#`sF3 zDRqt;Hoy(@bpEM>HE$6X^uRx&W+8)5(7Vkp7t%q8+`b#jUI;t6MJ!(8ENFUw zW%b?H8nw8*MN@bHYs*nx)|O&MrgxM#T}&$ovVPmwmXSW}TGY2sR)QY5 z0QG&BtPOg%&!E27xCfjLxqY{meNOGtuGW_K#tLh(wj9-EZE4o-4r}*>wSSRz)T)1f zx0Zb%o=6`y1J=G>SkT-nh?j9e@Ai50Tic2+=#blYYi(`$iPGA$FgNB~|MHS$VJ+5{ zqsq0VkF{cE`3MN~=6tLU&`Vq0`r0zm4?yqx2!caT>wq_kay89o=$r!R*4y`vw zsaEyM3Nx0?=X8v24=_7Ssj32KeisxNCyW#6#WzS#{_-Klo4Bfs1jBe?n2#Hr)Gx+> zsp=4)VUS~3B5yf{0p{f|A5M^2o_sBg3m{@#42CYm7F`tH79YzX#xnTJhdQslOl9zw z56iIGjyb%)WqW*Byg3~`6k6t4zXsbW?j8BTuw|qhumKC3O2|DVOd}-dO^TM^EwK7Q@(~{O53W8prbtz4PE$ku=q?= z(B|9Yl{aYfvt!}YF~38Me^q=zAM{kYhz~m2rlBwm-Vj^po!=3_f5A*f+Vd7}R3~-~2;kI*QYw*~jwyxnr@> z`%-b;D3+NVw>STgmX=%CiVCb4TX)37Kv}3yna(xy4tog;dQ&V;wq7Jmbe{ilN$ep9 zjq@hp+sS+#bd<%s$wosrHrsKGP4LG)+K>(Z6*hkqHhY_~KUGfyc9_-NX6&!ps?V0u z(qji4FHsiR66stf?|?Y~pP)B=SJ;P7>KmQsFQV@Cf-ea-8Nq$n>YW5^jZA_vPKqSW%{<5x@-?oe1hKeWZ36z zMKtVu6EN#XgU<6mV|nKBCbN{3*-!`#F)I^ZW(W!8)nM?KT#H-9I} zB45vK9%AkJ>aI3l1)GOa7N1MpfOWKIOkvF?8_!)2v}cCKjxR|F|SuiN?5t z*ChLWj9Acl{(HpCJANokG;Cgw)U(l17WsN^^H8(-b6st|7B&y3EIyaAaboeXN%MNX z)@@!&UbZo^Miyd`4x13$8*fY`X#Dx83Fx;^5+)kANG4#-d7UuPY{Pl}7whYSj1nD<%lNgBhyv zx=B`3LBpgvY7Z+PGtX$u63&L&?-3?C&wqkjphp%R^rt1eUVan2Qlrs9|A*>$z=CFHyWyvWiN@`Q-<56LZyq=um-JkIhpXEq8MZ^UxQMEc)UwuUxiP%!|JGk1X2F1HCDNb;FBg9+CXYs zz(%+G8)4SP{zhHs#ufoVBVcjr`aiQ|ifD-5iK2yxj^c>**p%UBO1WcOn1bH4Jcbvh zBp=1xki~f0i{A7xVP*>G?a=$J{If98>_PMVHv@JTD<~VYn@^XWX=>h=Jox_Cm^D~}-tJ$R%)C{YX!W4m z-b5^D^`_fxFO0qEcH7e=7AH(}s6ed8=Iw8_S8l)-<}HAE+^)1I%)7Om?xyBpEVdfM z+MiF*Zvh?ViDr%Q%?P=I&hz^oheciRqOspM2a4dbcm5d%(cKC+N4lj6qJ4=U}dRS=sv1eiF+e8nwBP za-#G6-=8T*G|_qfcZ9N*UP03siVkB)M{&e@Zj2@=_|xx=#(eMpW9?hO?VPT)*V?J1 zArcxXan~GFLrEeu%~6*K4JFkaN0oGoh)7+6NR<}VP)U^t*_0fYL={y@R25B9x1+M7 zswknTlBg;@M31UN_WIv3g!T?F!*02uR{0R%nZSWU;7?*C(eiCsvi0T8DQ+?|LHfa3~);{u@Z z)*hgTAQv|R{4D{d7-SaLap=Y(1}QZNFb3*=3M3ll_#>EOEP0&9IUksAckJHNQ8hN8KSG08-xlAQQ~aU=S=i`b)o=e% z%x#w~W|S58Ls8_jp2SV-RsB>Zc#*EOIz6qe$fd+vyTqK&Bym2SV=PLXzZOv0#GgE^ z%s&&VbFk&By61YXj=9;wHwpyolsACtFx)@wJZ`Ob%vF)d7wLR#qVsg34SmFUs%P{U z@o3~9URE^o=}lGT+y9#UuwC@v9bi1@Xf^H3SZ&^RZr;kMc90<0wYu+G<+{%5bLovql3g-X)iTZn6KU6#SG1 z`W{4i7;5{Wp>P;@dSozg=cROmXuKvw4g)obw{eL%!^uGNiK=9v`Ni>Mp!p@zWT5#a z;l#=>3ETT?==_eG)4SxA(q>ly93mN=%`#iKIcyepUP?Fcd)Mv-X+Tpww(zwMnT`AxBbL+NIp zMZQ-dtJ$YyhHbwZM!|bi9!fUL>AZS-wpqmKbgHYy=aU&^(M4U+xl>&=9_dd&ZTA+? zu27laMY_R8T2ms2&6>p9Wt)}6`PDhDnoQ#S6UzL?z4dGU{m*2e`I`ml<$?uiGZ?2! zt>CKsTXmI<0~Gsd5}I0`!BdB;E>e-m7wLR#`X*vWUZSl-u6Lg5;cue7VoMX)Q_yC| zyLdkF_$c*-i=8K$k5YB^U9{QN8u|Fq^tbNxvZDF!t{&5h79Qp-d2cW9vXbAs+j(lw z`#b03R};*R0|)c59_I7dt-ds;LkUvC!L#J-b1> zIxGoyUP@P5SM1m%9?)pV`JJm|$N6`^lO5+@w@gNRW7-KwtVQWTK(gaYvhOYJcrw7f zxP~2H5_XKcfsb?pe|J4^B%&t0&?VaRyU6p^@ouc=4SE~)9zIYsKc$yG&=$1W)wT8Q z+7W~P&J)dJD)Qx`>9^lp;rT?fzE#4;cmbHqjsu(8GdqrU4HM)yn++Vs15V=^-Y(cN z*Pzt}*^awGCi(E59satq;h1`k(avdbJ1`PK_>nBy9p!PxFE+=A=*3R=?}H-dQily`KnB?5EdI z;@u3Mx_JkoH+921FQtEFf7nT^7)4u$45-h?cXVD4I}y$JQ@&iZ+G1(tGuwE?>l2S} zn`^9y-sBH?42b^pw(##Kds)$}kMRI6@%EpNe6~f5m^oT9MdRW%$>w;|$McdVdjkf)d?4xBVn|_3k{)hkC-`j5%&^8V0!krg?0g&ki+jvcg z9I=K;yknzn=XaiyZ4XVZwj$duB3~JD{_K6S?feF0vh5ABkH*@Bm-&FdV*o2p8(=XPA4ZIo7Q`wQ-VY4v_ine20D?FcQ+R!^8i`rm* zeKu9J+20n?2AvROHTw*im2UP~MR=rir8OmT_+FEEV54nMN$>V0+kPNFqLpnIUR8!% zn7dfTtLC!pB0i422?IX`K%WBmeH^^$7%_p_HtxKXZr~rN=kYt5`u3S<)9=lmuZ|Zs zruz8HiF&VCG>=Xzo)s;bSflD2^CkG+tGo@-%&)I`i8h-w{|Ov)T9Drq8#t71He2N5 zcrg2v%p9A*WIV&x1)Jrw>gt`@W)Z)cE{Y9bvf!jT+wk?QNXN2U8@`0b4PP(g-J*1* zb;V{);$5=MO5$R}R}vQ+zMHunl^eb?(83?n0{JW=f5$w1o3S{q_lW?-dFu_7cnSB| z12+5U88(YMFQxMxZ0!Mywhq~`KHu2?$-YuF{kMFjXqMG)+bJJ;E5f&lM?d<)B5y-9 z{ixP{qA9!fY?Y6%1?Yu6(af*7T(oc-UdX_GVKachrn+g{YD2OzpJWy$*8*$nf^82& z@#-%cZM)bjmZfyES8TTZ9t0SJF8Cou0VG00sASM0WKz1)niBcU)`|Q=pMQ;P+a$8> zpJB;Wd?!&`YAfGs438MWu6zWM8kU~=P$Fl&m4Lxnk9S^5S6Z_o`LkxzDOVUCX9KO^F%9uvoNgZ2cgdD zry5b@4?CuwU)?x)8;s|CVWclRTJNrop2wXR7fwu9TC*a1&zsD@Y?S$_G<~O@pOTk5 zuz6l4@>95DIaAm3;RILWZuuhpSUiW+Qd#uz=jCZmv}wc2HZgQH4hEy;>c3@V+_xBk zahP9bO#5%0EE7B{iVQ%JSSHxY8?&^nym9BHbftAo8z%GJjWXwj0=`CP?Jp=MlQ{HX zBE#1CKCyy(inRcf2u0@IM2>VmCf9pzqWP;5dM`~hH%@Ll$jgdWz0Jb4@iGK;R(EJb zn}gk?p-zHbgNtByIG!~s*flL6$TbZ`u&Z>XH7l}@7nAv(MwxTCn>3U^#jJBTCNk`r z??Au3kN2qcWS`Iw?!1(~`vuU@Z=5HZpES{LD2wJ+DL*jIOSI~37OrW?HVr?W(Q~sCiA_GGLOk~$v3_I zXP(Y;N#W7>aT|V1WyQ`Wv5EZ5(<&0YNaq9gr{T1DiRMEi{YaE(LSr4xLNjd)Me*uq z8j-c8#bMIMw9e<36|H~)kymU>Q9x50(;OP_#*1{NH7l}f!({$dqs&L<`9<1zzSH?- z#gPyXAAVV}Lx{(oeBMRo-9(P`(ReiWbWD??c~nBbvm)BGVP(58zu2bE&KcS1h&B+; zmt%u0My8#N4bO^nY%^(WaN6V8@G=ff=}POGHcaM4jWQQw<4kY=#z}c>#Qb6+V{C9U zM`MFx-8e}_LgYw4=5V~{{cGom9{X4PD*VmP6V1iQb&LRUiB`SM!nN_TCn~Idwh?VH zUZkN;#*4wlc;RM=#*1kIG zv#S)DcV0>#ivuc8$67@+$H=oYJfCPn^Rmr(G>0|}l~#Y<2(4HQ2-?_ed@*$zw5K5Y zj5VN*4QROYQu^4R16nN2L~{WkXD!;GS=lC_O*-9?*#h&vgp99zGmvS&Dg`peLQvBF zNauk}`&B4%C|-E^v!Sr5vz-fND-*m(=lsGnfSqv4u_v84=%~SCKfAWa)Jlm5xy0;Y zNqlVzW0J&Ar4t2}4PBtc_a;{QSjw3r!pBys-|$?kZ^}NtPat5YT#Mwxfb@^S1De%0 zsYvi5o$<}1;Z;N%dKdyP)x+;&=$E}kGvD$vJ)d~IYqLl+>(v27(JV`uc%?Ru!P{1U zcOD-kkY@gSj&q)9mR)?W^CYWjQ8Gt5d1XGzN}kKygl1)ow&uRS(HL({aa>aEW1Yuw z?YBY{96)UULILA37q1<6UP?EJ#%n_4Fh-MjuuIIjM#fnDHWyhO3i-FWk}>9AFok7$?uOO`^-PuoxUvfQud!f#T|z7{rimr6#EIg zx;!K(@LY+n!rqG)iF}bh`ZKV_^PDHz^xIaSj|T@IJi>XRS#SGG^*sKHrs@;TyABbG z=01)dh>Dh+tWomwz>R*iPP8d3WGQ(|_HtR2ZUz$h$YVNrWxnOWX*L^pg^7LT*t%fH zLm*G}!A3jYG5cBB@xh(@*=0LIycH1TlmgnpF7h(mc`4ms8?OnG!_S(;do$Raz&OC~N-B^hlF4HD~(oJ)3G>{OL@ydA*3xP~3W51Sp!A4j@@$2yRg%8c%n ze=1M(f5MK__lbfw+ZbJ6mIo0ZWN+XSZMN}7C%l-qm2c4BFb4X1KGA%c;jIsxC)y4e zzV1BHHU@-^jtQ8|j)jeO3|Y;NLuQi;GMLSVERxlDCUX-;A%AQ;S`TGA?uqv4XRgTp zm@EvfWek;G4De~f;&el32> z^XTZ-_eLbs#!`Tf0NV?He3Iu{c6W|vHwsYfr>jvfp8W_sb+hbl6^VS2&KU7wytBhg zv~|eS&Qm=+B>3Ro&J)cCl=8>o(YLBT(Q2QimCx+uz4|uz@o)Wbr)Z8N{cxvf8$XMp zENvFDnlVUb+APw&Z#|#dGy9BoCBOGB^L4>yhoX4(zZ-4#rtEuV0qq~*dlBCASy%gY zF0!eiJ)q&vOX*5$O62gpCh_MRZ8m@KHrecJ$%R&AvyUZK`tD@mdu6kQ@0HCi=`_aW zmvi}4t8@ab#1qD{Z@pOJ37@L9??_~VFixfOs*^#1>gZ~E=& zJke%%vDi>q9x&852SuB`OJ>?9WHtMg%(Tx~yztITa+xiLe3IXIUG=H96Z&wrPkj4< z8yM~Vvri=pTQcpV8hxr~MLKqGmv*?w+^1+Cr82>bbftC0K273(&-N*a^XG^wlK80X zQ{e{*V)5|2;F2+}&W8xU?ml(NBl!UL$>DkT%06|I0L6aV2K8c}cj>>JXZ~a_6^VS2 z&OIva5s0=9IjTM%4-PJhHNEQQA(96#@_eGr4p!Im_`5p~e%pDX`Er8V6)icLQ|*oU zG;I5DFDsgDEP2Fvl7&BCDt|1R-(uAFB}H@NO5eH^O}vYTM}0IDU^nAZA4IzA%JT`Q z*?ZuXT;#cYUGUKy&(+^Fj)8&MN6Vr{H~MHB0|NmAYFqkd0S#f1L5uK6>85hyH6e2N zXp{I0jbk8xq&kg(DfzIW#z6k4a8(9hgc@Q!l?tZs`HsjwI^tskzde9rr(IvWHrpBz zV*qzvN;mLR>UsR(jYTn$iRMnbeuP`J+0K~yvOFZH@4brNb8aMuE*qA8dBn#C{#qoz1n{xnOMuHT|9g=D zAL-wC9P|5&&J(TtF4!#NtLoB5n=ST$WdWV+0h`)x zg$3eZq4t0c8p0=o7GadqmDZfimIn)mB#~{e49lzKyQYvSZJ)I^hD=!F8~XwVHn*Oc z?&6tP69O9Uyp*oAW<_>wn9R!>Wgeckw~{uN=P9>1=DB=0M0#-zZ7dIwaW|18ouBO1 zvqaGb!}2vTbWe|QV4KZ*W)$3`7*RLfq`kIIrW?BeScOgFX~kEm1WO6ywB zo6L_k%A6;h>NtEI?^SedaVRQ|6`07FB>3|~nk2Sb%B(8lJ+E{g9Mr=;(fk>r$LD%J z(OdpFKgbrXdYgr7V`B)~sSayIo1JUYP$$mS;KI2M$9MhYTulpbs-~fEu1Z&0vm*Q0 zFqwbbD06Y1ScHd|7>bZBZKHHDhCC~ZU`3`e#2K3*8)s~P_MX#~)~v{`A(Q#B zMwyE-bgZ{uZbZghVj^P<@yA9rhA0*{A}KQOyp+E8_6VSCj;K^b?~eubgXk$8*`1m1jlIk3%GUeu&JS3uuEq&pR)rQ)K5gH~o3fo6L_l%6wjqsm4e9+vJ$4=z0G5 z%Rv*@5P2IF36Ue6ZwKiBhiHR={9Wq#JyE>6ZzGC}bNr;9U(gsoS8*bR-W!Zn5k2;2wb~8;aGq%HmFtwTXv1subxFUr{CPU#or+L+1gtK< z@LN6GjdSi>dCCgBo)aZ@K#Bi$nQ3=(-%=6hDV-lboO_z{MDv3$b9Qu|XbxHFSG4Nw zqJD>7OCrSA`2-ZIpAqW77PJ~+gA zq8T_zzoJ!d7x7wXzC7doCbk5y-}KDgdHjCccL^32A0!IAo)gK3VNvwIE;Ba@7Otlv z!Haah=d<)a=ZWThKH>phqIrHm?pd_z?IK?GcJmIxIEMN^#7R1 zcJ^=~HXOMV$2%{j^G%wiE1V~q_xTGlk2KFT%0G)XyjEYA#;=8(&t<%4x_`d$;H=;8 zxbrE;FZ9QY)9;N3qsKA*&I_BQU*Y&=#K1c*rE_2Vx;E#DKK6iG?HY^;UZPb;7jSTFL9M2%?;Ir0eKH>6FE-s6SL(5~O^VzM&plHsKI%^|Zb#zfj77xA9 zh;8qzBVj8Rn}z*7vo~ZFi3TzmIh7EUKO6M~s;N%{hSi zo6=FnF$fh@|I~=%-mD|xXnc9aaNG+VICE2nV{G8SotM&i-sN#r$4fM0Qf)YkHf&b5 zOFFXn<)w@bd$n8d2uX|i?Rb0)9*fa(`!?*)bD{)(nnm;5&i~1*D&jblzT-*2Hq&{c z2M*3#wW3u=7xiYb%AXst6?2)e6&s%=HjII-x6E^y$%PG1>yFs?RQisW0o$~|7W58B zX1$449bLp`ammXW8+W9zy;J;Re08E5*z(55PoC4aN^}m4_O$#76>%KgN@4mw7oZO~ zo8S`7xKi(miB=t5#5NSoR9|Vtme0#2Y{kQzh(Qb+)=J!rsKd5Au;I>2=_7ub&!LOn z=NIskw|hR(j4PiEKP1}lT76v_gBF9V$au%QE|*lZpFF{ZZ!gYFg`L{wOBHxVVNHzr zniu72-%CZDr*wYocWL++(bS*LGl^CmUDPG5rn<5bTaWBJg{?RXQ)24@Y@^q}HX^X$ z&P(b0VB9U;*LkApFSWrc+OS#KF6qtUl2sDJ~IBY+klY*w}jYFOArWb)K;8-LTHHURVX$?*_JFowp3J ziebZ@m(oYzaosO|=RDE$GfTH}o@mn_{1GqFhS%zA0`G*APd($TR_Lu#eJx?FAWCG^ zxcGy#RcCesZgcfVVi2qvw?_11%(E zD11QW9K2|-0x#DLPshkwPQ|zMPs2MvccjymEth#0znwn@-Exf=T(w;~saYuw=`4Zs z;0BUp7v1_M-gk~*O!Sx+@MABdiKbE!z0bM%XMIFdDR19cpKl8|X#epT{F;=}_;Hvg zRaP`a#gmg&+p%mt@15cGy#L!8U&Xt~c}}Aa=gPgh5h zhaL?1X{?Sza;Ynss|kZUe(FglxxM{0+gpD$2*0s%RJJ#=(Dur+8tu)q!s(63n`D%C zbwlnv(Yb$cwtFn>I?DcQ9KJ(s6mea#lJR#xFDSGGSpboPD%|DVm2?^tCL} zT-C3fC)#NqN;oO-#lp?9{OYz)?(Yv65%!Gq;Jt9bh*4~g7kIop zuhPM&^4si{KL2q<>!>lUBSs%O=094;j5@GdZ9>HHlWn2&W)?04S#@Y39GasLtG?E` zaH|egI>l{Dia~_+_bi24{B0pcw`k?rkC5WGN^e>UTaf%umLghw=b%Cg7}xRhp}emb zQiQ>=kKQ>5QoxYjDYj(ZK1yXMS*3FHKJXL>-RO;(#!F?C)?`20vg56cK+=|`1{ZG# zIx#il|6b{os|js#@tVwjRh9*Qmp#<}y`nb}U>WbyqBje(Z~vasAvu`z%``;{H zh_b9wh{qQxA@Z_bor|}OinH`4yK4O8K`zI;Sq`;%ZXrj{Xy*qXA;-B&Z(5GQF2_H! z9BT8!LJl6Bhw-;>RLD^n|FRDuM+N;=qa1GF?Hj6$^Jw4?&&X-ys*KW_GQ07Uhd74! zG6u<8n%o8UpHOrrI>vZs6rEYv{$i|6 zJiS>#Chyj29__;{huZv0AxH0M=bev`<1b2YT8=?3M=i?{Z7w;kkfV>cv*gsypV2b_)lmJPEgeeo<0&!kuUvQX_N!F#Y!Z45cjtMq0?!I0w=+_F)YBidZK zdm%?ZZ)fE`oy)NjJ8YC^H_8a_DORLXH@6?1xtor1CuKtL$4`Tvn{uS7n^H_rKL@FJaGAY2>Pm(wZ`L z&MT(V{uzVhEp2PFkf#&dGHkz8IwfmjUh(CdkGL(fDA8=4d2t1Y?(EFGj1Tkj^mP)Y z^~}>JoPrWP^7%4bePQpRI8u@pWLKqq0WHY*IASGMJp2rY7G$FNC|Td}7EO=2@+!*c z-jlQ~$c$$@7^hDdcU){>TIT*wWw1u9ck} zH(`A1q*JDxvFo9&Lx%3wIti7v#BU;D9aTNDQknYgTE}Gr(h}cT!@wHTxWxCYmC83a zsCCSY?W3t%GB2vJGA^sqm9~~Pon)PKO6!!fP8mPpxIJ4>pEPCCDHC1p_`Ms*-7>3E zx%{eH$ECM6%01vqW4_{IU{A=2sar$dpFzg$2{m{@o7}BsM=z@OrQIMTE}#Z zZC;|M{0sF(JS$pltt;kljyq}6aZuG66HY&69QQU_im%X0O*`eC_pf1Q#LnOHG5Pck zB3fRirJbOqjkA`xoLmkqc@fX2bUg9zxOklNL?5$Ht>c%!ah~X7K3S`+_vPRP%?-FQ ze{r5@-sd4w<|TUUY&@yy>pamDuuG^XHKHZw+V|e%<0hQmYMqDLd&Jw~80b}Y5OzzK z7cV|dgKxv`RY!iEFnOfnkXv-47p5S1aCo7MZeHi)@HDvdQaaBlK7N|>MDqhjuUzds z(ez;Y6#>zzmpN6I4?$E`G#?&(c&pbZnvS94KIe&cl;o|OlQ{0AqXvyVYBz5BwiKV; zJ*-l>pl7Y){I+a>>|ITcF+#bf|IV+WEZ=wX}1YC3k=ijL!&Qtp24{IG~uXdhj z4yI`lLyJ}&>xwBklfV_f+(Pe15b%B_E{-&MvI*&pQ+>$Nb0Ycc1+Jh^`X(Gk*obJ# zeKFQDyhNKroZvjs-W++&=xUJZs`x0cbTubG$daz^%@0IMUE#sSw6}l>aX&BX=X<>y z&c~gX(oa1Bx_Zueq9<=t>o^w+XI`RJ$GT$5x^i6cizTJ53S81vYkqzZfuZRNxTcOP za0PwRH=wIBV@>=*1qKv=pD>#he6>(lPbSJcj<${Bg(3gYy`Q3CnY` z_i7zyJmPY}H6p8uI8W*LI77$TIK0nG^w{46=U&bejYC4oCPk~>=5^&*cTF)?mB4^? z<}Mklbai6dif>_$+y)sR%kVA6QeoU*Lh?5p0>!)(v6UAIUZfL>=3&vw&z!2qX16I` zRjvLv#NEfDg_ignD811b)X35N zZnp3vypfsh*__MK{4P{B4Jv&v%Q~}NMVzPfV}4VN=AiLm>g2UVBWTK_IcQTe>TP~B zJJxvXooXg9j^^7E)}+(-@`@=&^UOZ!y9{+|zKsF_!Uq90XtU0N&J%4Au=&QTDr-b|D+HCx$rgYTnx4^#6VX`iI}AHJF_ z=c})RbvR~~1M_H(*n*41nY$nvYS!d*`RABbMO=QR&)OtUPNJ2cgJLZ{m)*E9KFTq~ zJNZ-}1%_mo7J(2`2HfhLn_U4ll2f)dPo|%wv7N*(L=Ik z(=z6!%YTUEn43&%hlG}K=cV)?4$t$IXyzC6l6RTPMmi16^Q{~7JeVE+ux!z?hF$Yu zp5=mHntitR-pp=xh3bbCst|)-)>rQ#-|ABc+o>#N0!m@ zVOWMd0`J)QigW6jC~n zVFf*LT#5~<5eQ6e%bqhPNY9B9ST#@lyvt9QF}2NyKkvMhJ`NM#F&4{IDx&cdDjjE_ z+jxm)$bae|ohMrLHm5reb&Kx<2KfZls@)`TE~>LoF|(4`sSm~6HQF4qd80-*c4wF5T=*2 z?u4m-)?JC|Wweahy$)0Vz=XR=7U|f`?3jWL7G9zmv`SB+4U?5^X59H~zfbn>*oLLo z{$Ag#C(d}7NXp%Wz~niR44Kc54P5$d?k0E-(Z-+M=1S=-^pt#(Zr@;TeQv75&noaoL1jj z>5e~pGI{D5zTMbkzpS($`lNQk*sL_n3H0Wrvkawi`a1zp4JWOMw>!XTnAGSby@>Oa z&WUWw1I`o8iA;k_wCY$(r3sA9W<82;7+g}R%)OB!HiBvNh@P`jnYYCnVBiT2On5}4 z{|KI6U_@VX3q0bT4p1~_wNoP!5p4jizID=;O>I5)&)T}QQdu~t9w27{Yz|L6FT27p zN6(28w`PFcO`3R~in!oP|1PGnV-ckB5{=&n?KtM!&J#VQqt-G0e&>l+z3Zq!o6~xX z%m8P)IhJ#`0A85=Vyt>-juWwK%3XWS-6qI|0T6dyO6N|#=5Eo-zm9_2B-P`9Ecj)v znNo22cuZ0!yx*y2DELA+FbPg)e8T%G;({yvyVy287S9TKi5`dG>X_S{Cz_itlkRYy zXw|!p0By$VabN~G3qB0qed0@bYzbg3YbG3p=R^s3_laA&Kqg2n0OHO|>E}KPFd?|; zalgzw(W+w|!Pr#QJ{F|Yvc*}1j=@ba_Q0JvuW#GRMY zIWH;R70r3++>Je-Xai$q*UIaq9fhf<4B}*!9y|{j+B&FpH~UHLmV**T+e$!OcIH{Mzy z;zVT!9f;=GsmC8b;q(c|4LZsr`7b3T)r(>hE+SkwLQX=ZTQ9uc3D2X%^+=8gm-7qV zx)*VomCi|4?pn0+uY;Kx4y^9SpLAjzga{m?8*vm-Euc}T(g~J0UIvbv>T%EsdXc~p z>EA_4lz!zs zwT|Pqcb@1=-iEI`-+7`{$GT#x*O6lz(}=Cm5#a(`siP7bbi`el5*z#6iv+evzvvBM z>+3wxms|;K*9W$siOuzP#_5wLwqlg{p{Nb8+{2QOKk?A=a~~96+czJlxgac~TXJF5 z3*ncsWIdr^eZNv!fM>@gOIDa?s_OK}Rj_6RsPl96KZxp!T|5yU z?mIZoEEJo6X3@Cwn!7)xlivYK?`qrm&S<&jBvMlE#$tT)yge-OK2CuF@>a9y}bEJu&esKEM)!}(?!gLw6 zPkc2mH^Z7IuFi2uI8e`t5<8&8CkfciV0?(%%6;$=Jd_9<~X zG3MF+l}fj^+UlqGsCDfA+=wq7JbKJvue4J6SFPjnezlH6t_NE@1lZFqs^?WJp6}2( zIbRjVX8E=&czfGNQaes~yx@(%Yhy=1!lw$}fu6692LUYK;YB`mTv=AbxoiWWfDNX@ zin5Fkxe->@_e5>=s&gGp}Wv+Ui%{!egdU z1#dvDqxaQo@OJdFqjxRx4fL{K9$4^pb>2~r7Cg9R)>p^dGwQp&$T!@}9(qUSRS+-Y zY-z_Wd)GR?IJed@>wjt;hi>P*Sszfx(tq$Q9r-M+zU;JPa@lDods(*=&*$l|2}{du z96Cp~)7ZwLww#VK+sU3fsn2AtR1Vu6YpADTJD7e?_zLrZeiSqu9KN`0cjHC6(#TWU zKD!}bY^?R!i*_mdWG>K=t~Byk5A(4N-i=qZA)b{%-EPO8udcpmchy6VV*%EGl4Swx zkoDN8k2aL9G}frHb3dQU&V}=4AJ{|@&R*$CV_DX7!eJUKb%<9z`D>$)n0o)9Dt5=QZ_`==BS@0}fX~s)sYb$fv+A5AijYlu*>9y6K z7WJWx3;KB*7xZgvLp+w5)?eecvA$_8v&nMA!5BYFF>W9Ae6KvsG3;aN=uyG5bnq3jJFmg9smel9V`+lW$#Fs{o zI2dn)AG+_Cn4>z#OPzKq*P4@#Bd^Eq!-woKeCXh=EW170I-)V!Dz>x~41BxuXzL|J zQ<$T*rDeh9x5Fpm&P(a@=NHjd(8}MnC7nNbIWps5RD(UL6N)9B0-a*-F``D#2|L2P zt|grX>+ieI_GMX4zX8$Z`1=i7MYQs-D~|eQx8pdf5l68NqCl+J-7axF4>_^hQ{v#V z+vXnJc`5ydZ3`Sh69@Bm4TnEeADeM-O$vRKTcsE{Ho-R9mFGkBKR~{9mOaTKOxL6vdlRJ!3}@Q&o!MUqXmCdW_dusk~R~xB;Rbx>XVQA%J6WRtD^R z$B6k3DFgOyk*_FQ#iWiOXFxEL>#OePK}}s?e}Lz!;~fVoq>L@-bW@y~j`x?ukW&sP`3Z|(WUj?8#lKIN0y(T^0o9lUH^!2TJZ z9P4;F%2G#v$7k^+6V^Z>vt~Gae@J zfe3yd!i$oBfV+zz{`0TV-eh+yo70s>p33$?zpE^RZU(;$x_RfNbfuBUdYDezRzAs~ zG%L&c4wD^|vqpVL9i;`V}mtWD`k zGhQmY3JXn@GoXen9ycbdN>=!i9zEqmCe-Z$P*#rbA&1 z`D{VKAfCZ_3fK*&;}DNBGdQQr3eHQJ6`WHB^H-o51g>_Us4Y{aGvH0ZR?y17u0dlx4nGk# zF5_TSa}~Vv_`LP2K<i^qjECevtik>Jp_thtdcdZ4QXVh|+mVcKrR8ts+|a*A+*7 z5brp~H{vMH;LM7Nq){J+V=Qp=smDP**xZ9VFQxM_dBPDiak$>PVpqFCib~6bjN<~# zMDzrOU4g|%F`aD1drlE@1z^*f}kN^9qEsK&;rYueQW4ZW-9`Wnb;B590TAUR}UGGI(XsJu1qU zJLl@Ra#1inR?X#3{13gePAKcU%=6Xl#6Rv6NZqdcQ$9)61?RGzYgaOQzZ8IzlbpVhHvKZ+`@N+=eD$)MSWZX*t4Pt_sjZx34m!G;q0+XU_A%GjYVj` z^N|=r2t)A==@f=4U1@A3mHiURTECzS$}&`ES%vI7N4nBj)@X#imJfI1g$znF9%Vt@ zCX3oA>SG!&$ujMljAI)1H;Kbs0q(q%t~Byi-R*s_;K5wh_SS*Jo>Ae>OX*4@kM%Ho zw}-`nqijQ=J-P|n|PFkO91yuSr#qN_g-GMPChRSY_*Qh9*%qu!K3{(@)=!Q{fDLC!H&@PK_fJV z9(Ip*od(amq2=qCcqu~lYvl*YL%8ry^72?Lc^YHX??i0({`q0qI&;si zfI94&im)7CI`KNliRHtqv3%IndA5Am)RzpEzdO&K0sP&U4~fTT0OWDsU-^v2k^#?G zs-Ls6nKn7=c_Am5MH!P5tdCqi3|ZIZ!*0We3?9Dw=hiLEs}EN#qH3Ag80Hnv02GEa zhTRtCy#)V-IZb=Dc31`Bw)x!%yOqx4b}7sYTKU&C?5UM2W|M<3;Kc^8pVay&v-o?!1)F(;^DHMJxZh;;7e$<2bPqNAV0mAzcKg;t(<4+iO$|)00YPIi*u~+ScCjS~T zSm#djZ_N!JhH6``^^RU2!+H;dGI!N#H|8HWYWbo?H?_8N(%IR>YD;g>w|InKo7X?* z5^GS-HP-8z{rCLQg;qNRQM+lo@oBk^F@K9ju*xw-X?zm-silm=q-PmWf9H#uAJ!kBm;t4 zsJ-ApR^x@t)*rx5p6v-CtMSlB#*4lpkNr!Y`dRJqXU)~FVS@bRT@*Nk(|CcG^|60h zpZBwze{+L?b6LxEJ_tTu41)X%X365u%rB^GT+B=_sHZ`&Vg3q%2Eq2pN?SAt-p_Su z5KPG|nRnkbdMcj?Rd9eF3{yS0Fz=uTd>>uh$McD{?tj0Y*B|D1$y?47Z7P{kpU=9w zZzHd5W+yz1TV9guQ#~<+!hA%tzIoewzB=B9&SQET>Y-|R=Vd&!XS`_F>OmRu<`rdG zxACG4=9>-da^0a(!9T=Qf@2(0RO)EVK{IqYb&aJfE&}b_Y(mPejR!&RG zOspB%vB)s`W-lVv!0e=CE44gR%T_K-b(Owm;RGMk$yVTN%vRuQ=I&%&QlYOQZGAYf z6P}GJ=u!D-Q$swT*%WB&>slkPZAK@&)9Txx51Z4|d7?M@7j)Lgd7`)caWVA;ZTh@0 z+MxZQZnKqWgK|*@<4G3q<^hx0N?;Rq<3%3`6M3@(o7yw`v38rYpTWnrerqy*nB%0W zQ}8KHe-Ub~n-NB^O*3#gv+qa&Xyr3Lx6UryL|8-HdfAzL-CrpAGI&7~{FSrnd35@-#yd|mJ4Ay^^$Z-G6(!mf@os(D9iPQS_PX;#TRwCF zFV)S?PHj-3NH>K>KFLa6l9~C?p5?Q4n^RQ$ko90p0+p6|NkdhvvHAOd^YSk{D}pF~ zDYZrF$d0^4m zzDs%H4wq=_v2f$cXQq9g=Tm()&9^yEG|Q@8)yJRr(=;R6H2Hy-RePqPXjkpoP>Oa{ z#?j2HBd zC*@zK7CqoPsOSjKC)&DaN+v_Es3rNQ@6zZfmX8_=Z>7nyf~cOC7shNhB>z~K zXhseu;j*-ph(M)1+XyL|gw%Y~;1Y&{DefU*xm?jUnjyy4F|Nl&-YgC8%UKdc< zTI-hNB{)0Mp%zx5z^8446yT;gv@n4H;e}BNetS_SAlkfMs9QY7l=7aU4d4de0iq3T z!MhUmnD?~$y3hd@SKOM_ILbZU+=q)-;43@X`NP_kIcCsDps2{X52H*Q?h9RJ(L3Nr z>Av&t&J*2#lUi*`41Uqw@k#NEdU!t3eLfE*oaa2zI8qtBF5tBp`KKAL6uwtBTcOR< zg3Q*myBD zQ=Dh-K%k)K#NdOWw_$4JCA$B2vs)3}`;*y5MH`w3>O>nd<8=XjOZ{Fdk1lzJHKo5Gr zSlKS<*E(Q+)-R!<1FkH_-;Qp%ZFwh4Ak$x}}`qxJN`+~03mkbopj7NNZ~xoKJqmqTzKg7%$n&Oy8A9j4c6H~+$g7R_LL z?rF{wZK~STd7@2i#%l&#Kr>_u6SA}!@KAPPhDpfT5At2*21IM&@iKfH9B%(pl zrj|e^+Eiq`CQ$IV7fnTH`U9#v90(s!eaa{Ixy$oL>Opv=rq% z*qaxt*qcAb>sqj5T068H>#T)arDaRIxb=d0u0Mcx{1-03`%wXb&@ch{KDIHK&GQPyPc znsHnF{c|^NEK!qjKaqESWy!^JRk4casC;ue{U-hrw+V$#IjvZKCH}upN1xZw^*1W?FS^1kc(KjXS+d$r}{BC~LAJ-Apg! zll;cBd|uyz?YykZ;=F~sI&Y!%OYj~Jo?+{nne7S8EqA(^^?;e78~R)gNX5RRY^v~% zVin#|HdT09v5E%_GP7OMW^ppJof4}OHsyjqARLZT@FSWF33o~OeJrDEwfAp;O+`OB zjRO&T)M|GOr)EV*A0mh(Px;I)#yQVv&$nO~^0EvJBHfMRn?pgHJ_mZfI-cRkZM=IK za2«)U^8}7c>;BDyn%nmUXn4Oip?Sp6T4D!+Kp*^!H^&feV%XlWAFnL+W=DdYF zId7r$OV@0Qkz30z8f~fwon%18qf4<0YmosJxx^}F?_&bZknE>4FAvSr>n7|^^aYI@ zky)RMp^Ml~72O^0@W@X&4c+Z7KPB4xYr&AHFX}P9n{LA{K$}itT2i|4Fwo5QtZvxl zZiS5+9Xc6W-$u6wV0#hnI_>$W@+{aMKy7(8nu zFd^M+%JOBL#*1)*^)0|wD(myU^7a-Eb>2e5)|{QKvGZr~>|Jhd>%sD9515GOznT}z zaI&1M%h^pOA?V0t1koNXuTfQ%^CUCz3O)c}zb{af_Z*Sx+yuFdP02WQ< zsh;(}41?R3JWNJGZ~CYvtx82SV<=5pq8%ekh71SeP6en9lPh?V54?r9JJ027PALk? zsn?cYCT&!=#ScQlS1p*FgK|hiQz;*0sq3%LQM1PI@VqZ4ZQPuviVYpDH-V-QF3i7y zJU2@|NbZ}xD z&q)KpA5f`qtyUWi4;`M|X?S!j41G^QH1cz>-{gIe@?q6}%{9*Zm(jl1nj5Ce#ob(* z8cl9a(SJ9AM@JI%dAjpFU)TD|b_MVCzTyKa^;L1oPJMM-9{Vs<^K|T0c)HrCqGOB( zxa0AF>UGcObac#Z1-RP+obj3ivc{CepuXi-X*k);0x1`aPg7FMLEdQT1djoS+}BKu)U<_jwpjKg($5zNLzTXX!D-u5zAvysMCpCbFcS_kUYsIAI!P&pM5K zBjGJ0ICeV9j`Vyk1A6ddo`Z+Afg%L&^$96j|7M<#mx#po&90l`ciw9Ulkw|$p@KHRHj z*)E{4b=u{Ne+77WKoqK4#LdmWdP&c%*vr|r(Hb@Ed&t{ z0RIfI8#7;~`9SNogPbSYI$&?-iFT>TQ{ApwZ=(yHVzI`OtXc*Zi0|tkZXrBm1hDYl z)GgYj^}I+v3uP9%%%XcWV02rVy-A$;(~ubdwZe;U(KO*gWlj{8sL?RXp`LheV_nsD2&$y6gCOomr-DT zu_4u(%@zxGYbwWib%U=JlHD`aP);WFpLeLq0?GQIxCp`jzm!&nQN>qpFVypD*Ip_oM^`_=mR@xCK?gT z4~yu+BQDS|UPW1XaL%SBgLAyaydp;4nR!LKn&T9rm)}$?uA4))yCX3w|X)@0o z?jjxXJOrE_2mpP%L^RCxN|^3h4$f(x;eARFjr>%lO$nlLr`n9y47gB{A^Y!yEG_)s zYgAE=uuJDM|2;^8m}UMwVL(Bze+E=!D?F$uXj74ezo8<~rXu4tkAn8xGRHx1Zr&c% zVh)?WU0N?23&t>ga+<-ao8hV36tE6U%Y?+*`w*Hguj-B-5zH8#SS@Ed>!Rn9mrATv zsrt%BUV#e&fw0QG=qt|SqsZydoHbue^fTaWInndZOJ&$^((!X7lnM1 z-*|?j8JjrujMH1qA|7^&pzDPe`E+H*R>>lg%3jTDaVd6nT8rxpj~7NI4*^wwMP~pC7U)46(vpWV#o~ zxplmdxol(ceO^|wdT%?=>Onent$ZdIWFT)z$Rb&dXEHZq6Uj?0&0cD_575OMB#THY zdmwGuB-V3zL0X)wT)Y7)!Naaa&pIm6^i01#+ugQzk86KRC^xU-|{|Ka#nUy+FB?g;`IU?+}V<|P~vW=EX+*wCV$T7szq~!?N2f* z718VjkCGiQX@YZJSHOkeTGj~e;_SBst_Xlja2EqyJHTBKfP>!T4*<8^d7`(vS367q z5VV0qAk0g&fivD(gTq_yt;dZ!W86{0#-gGgCp#hp<<)=pP3gB!PMh3hy@gL`ynR=i zSi9kr-BUd)l?~6{f7HIiOc<;<#r!^)g9fe1{UN#N9J^B9%gN<}m{;OnM{dNL&b=Cq zov{C?{o(*zW}X4&=e&4kLahBHR%HvO3Ki}j$G-!d_cA;e>00g2n`il) zRzG@uC9ex5*h)_r$^ptKsEC)6hu<{qcSG-*+h6 z;$_ZVd9fZISgSpAAroBq4QGS_;e-=;o{pvExwYCWFe37t#{KkK?ZaDxXLPOh#@Eoq zMCUoJddX`REXQ-pV~t>kr>QN0?G3ORr{&h_ay&$-4O#>22LZOX3+(9*?3Jm`Bgj{< zaq!01YPHv+1Dvkap2f;b9pJQsl|^w>(V}?Y@B`M@YzNSFwfru30A8RqZQt3b?M=`D zd$KKFrM6)md?548T}*JHdLtY+7XtG(ZCiS+_TF^VZ|+jGYj)c?o{yT{b`Cn==t`yk z4CgtmddX`REIo3|wO$g)nW4)U4>MlaOz zL?f{68#TKFfDNLPvn%YFhYH&9@9hnM>>Z|rRPP0{9h~RsKyxUN{hRZg1{$cpSIv1& zyBgC}1C{o?M)fjZvuN$q)sq?R=V2>X!zPC{s&QwcRn+2!tjxH72ZcW264Q|TbPKdt z&GAxtcjSBJW#>7K=kMUXfTb9F%4zff?BXqRN1|ce*mCG~ljn2Vd!P^YJDTqS`k|Jm z8hc>xMtu)v517kggFX0P^uXS@pNAgkMUG3g;W^O*Q9$V*e-K0Y3(SWfDG9p!_b_bV zb)M7g3An}>wob!V+M)Nbc&F7C%QkBR^eZiY$UQLJ7bJ_9%MpKwa+B(%{o*?XWb$je==%dW^vvMr#s(=f8H9Wjy;@!HZ^%eKg@t%7xR zW^IkSjzGa}GHaV)6?N_6tm3gqMXbEPUj4M^TD)GWtGZLLre)S=oK?tG9q22(g%ffv z3{0+z78eB>p8@0Yp*a^PakB2rEO>f`h6SK1y#_EoGc4zV5n1(FR11ILB6>|7G18_e z_F;rU^f}9}s8lxE2^Gf#&L;rv*LwTy*D^C`@Ro%tmTgh+P@Zxwv*-uXe4YZjRJ`*t z9_le|Sbff;>5|90@-4=^YCPPQmrMwgcV1j^vaI(kIWF_^p)TKY&Mx91 z*zvw~9^>xzZPdBsxqQ!H?qs{X^RhM|t9LIs5xw0DhhzOqUhd022%jIeK1Dr2voD0B zoBET^pef$--@pMg3S7?}-FWSzI5vjrXP_y8R1tF<2yx_~~4@m!q8LwD+SNtVPCm zt8baFzW>~=)CSxZ+JC&&^ND8PK6#h(M6>T*m$_efKE`!~{xI76#qD_wp6tHJr}3eF zehYG|KBr+{ocxBmp&iDFQmNfHoOz^7X z!G?LMZ0}Fztt!#hmf4Wk!>51NuJM|1_ot_I>GC|`4e)q$_TBXp9(>7$SeNb>b{I3h z@_Ot#`!YfZBY^|5O^lB_kFo3Q%RF9P{5$6{j$QmaMt!LKo!}Xb80g>geCKqn_WW=z z&pe;gYKy#PJHXbe&o*|zlKPm39e}lJ+Edb@LWa1rmw1Rf`v)!@M@#R%(E+hmWr#cb z2esO(XW@O?@t)7=TJ4YbqazkO&uJ{x&W4qK;5?_v!;H}`9_i?m2!pIsVwCpA+}(Vq z3`W_O=W?g~n`^pljok`%3f8atnHOVw76&RX?wbPi=}ZVsy%n7j>sL>w1>_EJ8a%86 zHhj~|It{D11y(V|c}`p|TvyI`TMFmgC9EYulp1jh*K-tOVNc zJ&U|%!P@%u`3x4q6Trg!jWml_2o~$tyjj}a1@XKnvj|Qw_L5AflLPFwkDZIgOYW6R9=@od(!VuxUBW^En-0PbRNfu=HRpFEoP99}i4mv8LT`P+HTPi;kW- z5qF%KD$(}o6KHpEi9MZm477i9p3~rUR4N~fLF=?5>(ht%nnh;o*B3Lg9bDKo*Dh2e z*01~J^=qNW#p|IEe08~Y>HS6^LzrwvYw3O<_MUJ@JP>;i+z~ftR({O$IqjP>+KlDq zOm}SLn0>s#e9fYz&uRHnBij7Luc?& zE7y0P)393nEj>Do;rlimvrYS=RWHjni`LeqFJ-hl`nq(+rj64y)}{M(x-OluDGFh# z@*@l(mF8)!OCx=gKh|njM6f3MlWt=51D|)fV$L z(*wt8T{^{k04~4f3PgffHLNPm?`{Vc@Jufjp`Qv?u?R(k!(1~qO$)RNrW!_47Zr=p z?VVNDg@Mgn#n=2QV&zX!RN=H(eOs|`#KRl1t{jwFtRlYS!g0ZCnFZ~z`gxCK)@E^P zCIhNMdKR30cg_U|Lsr=$yf<0p8W-Mxta7~!BjUoT=m{G#2;;ae-H+PBWxOAdH###b zh|j2VR{=I}M_{D99y}~er*Gkyrz=1wFBYcL;eo6ycry?oxHiZ`4}6|#@SfmZJl4bB zDeG&Cg=CurrKkt>T{+0>yOLoY(UTg*pa>Rs+_a52U)=zSh#QSXLatXiiRJOmFpWxgF%b2F_?mSi?8d$yxxx*Hn4lJQ7!vbAdcdnzZ><8g{ ze!CINWx&F9s9iH)U~r6EZk*1&=~=1i3j0WuzZYbeu6q3w@;?bI7dy{s#H-jr=)b~w zPNV9dvTEl!t>(yEd%X-XAMu?=ELQ?c+9(s2oz^(8=c|lfR|XcW8WNVbF^0ZhschcE zc}@f0{7R+o9nN#QR(s-yz;cuGoDO{GAJ%91b_#sPTWfqitn$w@nhWenx3>T2bZEYE zDdrf&wjIMWOJ-+z(exaYxj)1)8sWgDc;L6K^PKi6^}|KZoGhC7c_SqH)* zZ;rgRhT#%pfA+oJc}@qE7*hu8rhsC+wT5E9v(z*HUR2TwT;0CO)xnq1plc%< zT^)^1uI@t@(cB)E;eUGpu5Om|oW}V1FSzX;o#!;6uxjTyt>(yEYbf@Mvpv7js13|YP`V0zok*w#8x7JYhFsGe= z{VHkYzW^nkz*Z`=5H(`4TpQK-SV2#l`0;?>X&BQ@y6|q_~x)}95C)W#h zWXid}KzBbLnw*MJkHZK=>@>W?8OVRP^PEN+rknRyM?RxbAENS()=qc_I?vLvT5(AW zUTg5I>{|DX2k)o2lFOc%kDeLE>Uo{#yX?1A`K;VGV%?hirU$bk zUgd~FWMlmi{pB>=9408utxltFEh!{)boeRaH;%-9c`!)3Wtp3iu<2G7c_ zeLr|;bXsFS+|PbUvC;Qvf%W|$R?!b-Ga*$=%iF~9z=>{*;fzTcqcz+A@* z%$9C$ni4o>FB4L&BW91GPH)8g8)8mD)HJVsiz~7>73;R_O-sxezlJkraHoM8PqXAr zop#Jy+~!#7cvob6TVM;Hy}m`syDfNDcJ1}-!B#vT=vGW1za{1rZ6U~Ii(77*=XJ4m zUE{USu=n4h1a%uzz0R(9<%dsKEt zqn@86=ClC4kRt~VO7a&YD`MsEtzX0Xyw3O3W20qBx&ht5qs(;F=o#(WgBX8}&c%b*qMlgROm_1n; zFM-LQlhAn#(<*{b0}wO5)3w?IU&B(|9HD6J0DTEyUSgf1Yqj5D1@(H2Xs5CJfF|Dz zD{(qNTVNtOKpU?B{gJz`yVn1p>ZEvsb~lLA?PIAEDqA3mzyrYc;)Q0iP6O+aHGczE zS#d|eyY$ZvjmwC3sNc&3&(guOH1e7dxsVudnpb&{$9oB5*XzV{>8onBZADJ`RG$bUx1M zK>u8QK7MHBnLf^Q8e!pXQ0|YM=d{`?^Wl*KjOX#2$;)*2Yk=EA3yh|q`6yv=Ja!R} z_xVqGS6iW#a%!@HYY!7Hs|ox&vH(q=R36WaP8-0Kcl9 z$4~D)eWUZ7cH4e(f%9nFPcBfsWj@&C8L-c3~qwT94Z+erSHjQ+%S<45SV+8G)%|^SD%XlVV6GkCB=48;V zd$!{(ArthotY3ZufGiBHWg|Oxw9ERzj<<(OPt4GkVJ7!7&hvEeVB^cyoZZ)UZU{T3 z#4YiFgmx^6x5$oG66f!|R1j{lzlz@;NJg6%&DEWvryovXa+Ny(^u13U!a2#VPw;=R z*-scUd=0Y%zx)Xm@qC`{{`28;ok#!qF!nR7Lk_FY$5%L?KF@hhd)a4aE_53C;27kio%XV-Pi1%%<#BT; zu;ZY+e;syg@eKTN&}Kt62G-!+OIb3H`R8wwd8GM8VSOS(wArz(ri2N14F6?@&FzyP z<2E~vRhP+t_RMCZUCCuUldlP*kdNkyw%fz5=Qo0aeB- z*4)lRD#LD3I(YQa50Te|$YIBnxaHg&Ye?d&vyYaO7~TL!PeB$74Nu z$H!^ZXZ4o(V7q@tKAZ3|P1{&DmiaP|$6@q7k7%cPGJ34`YojXRd`H!NXo zqWxR6*Sz68ewUVX_kD0wN>{5H6e1?J0))UZlk?l zpWZ8}NaEL$`%U(qf7U1&caB^VD?9wE?0rP`+Zz!8z|b#T4{&&3ronD@iNS9}WQ6DQ z^Z@@_J&#{dc+e&?*qzZRdpF{MHqYmD*n3@l{)yBFhcREK&ECU*@)N2|H(taB;_>S? zzgp#GMQ?z$-_14Wi8h{p1CY&fm#N$O z*=Dy!oA5jB{c{{m7KTUrs5O1Gvf_RgrnnA=OYz!AsZ8)9U1?phSxVgUy==3RIDg2X zB8d-AQAGM|a{gJbWT3?d7YF*m*M<38yXjTgBeIX)I6$$VFdy?(dH*B=Xn=p_2nWwQ zFQs#BrT02Tn=U7NzLM8|xbsw&KUCuT8t{ifb5FtdH4qa7t@c@3`8K;U?`w$e_i4!9 z!`l$u4{^nOTZiHu&YCel{ zj`swXZW}b(@xbhRWfh~>^t}*^s)X|U;DO50H@#a7+US6WJ1?axtt)m+iCZpcwB!8U zie$%A()L8MG-WAWkUXob(7rc@kkIlZfwBzjo?mU2h$8fqG$GrFq?!1(4;HT8{ zx=%;UjJcYZXxg*K%)XaEnq^g=@@@7j*k{<7XxiG+6<(j{P5uS@G{22^hl4g7irAoz zce|HOynFLIvi9Y%iLg)FY506$GCK}zN;f->eAXW7Hk*w$B!lrxmM-{XJX)-D>y_=8 z{)NU_Y#@_Gf84NvtgN_09ZUc0U0~22QJLUHy3)F0$CS9```L~qaj}6ciHi+n?1oss z=1=w}qrET3%sYFo#l>=Pc(4X!f7~}fv7fF5(2D`y_LPwoI$k_LMIv9M+rGe~&J%4N z@?3pB?&mK0yYocTkKPq_BATD;OW!XHTJ5v6(v5eo*Qc`d!P-9-ZFY5EeY@Plm}~J2 z##zuDGjoPSeL?rbd@vt_YPS_+xc7TvC$hfIrV5a}!wu@_8TX)LPc)6o>uV0KX=o7YY{}=h6WWbaFpxAfwDVwKG3G{2_KTi$@k|RtLqoXp zQo7Qb8V4{c*AQjy)~8WJ`Bl-Rp;dVbFEz9QM8XuV&#GEat_ls|&P(b19EZOZi&GIn z^Rpe&nrMEkR&N-IR=v%_H4VZ2S6a@=Xm^5aw6b&Z7$OVP+~V6iA47}JLHcyS{f!|r zkGA-Bl?h&?n}(3qtjMk*%G_M7F}{}9z*t?aiE)qJ0_n+_fr(m7}`rX zVF4!Z#*1_Y^qNdWD}S>vtmipVw4B$7VrCv2>iIiAVrOZ!{FU` zk#0S2yyk|p_dI3pwsE7(GtxFi>iHY<*eH8`2E^l*|F1$k_WX^}^SJX;I>T0dz*)5Q zyya^ShV{H{E}oxJa6=F_Up%r(OVWl%R?3Pm{cM1#?!*uoF!)%C2IP;YaymtB{*jfu zl5OFBqEY7j(5j00ij%;yVV&AMKU%cW##v-~k7bzjy@CTP=!mF>bfunn9GGqQpHnSh1) z*MibgU}mH5=f~?7wxY=0h-R^h<3+I+!Yk3Jc;}^brFBgkwoSH4qs;m1BUOZ0d@+0B zdJW^iM4sT^HIT?V|0lDmNQk_|A?^4J{4fceFfY-{-z*ICK(^&@Q6q}{BWbDU+Zuhp z!8i>tup#Zgk`_JR7CnzUFQr@08?QNI@o``qJN+7E&Ywa_J--i0$=W(}uk^bpz(eqJOG~eX)pT$F&piLWAwmE2~4O=+R$jGqRwJ$RkF_6~3oy0(% z6-5vzCGT& zc&>_s$dSI|NmyhbVRinT|wCZRI+N9H6X}0*=EFr7l`8c1qOfSyLkcCGP(;EU0 zWyKwb4lnvTMF#yJ%&RiNvvj4A*TmQ;ByRbEOHAXD#5wFR79~C+KZnH}%}A*2#I)_7 zK6G+UK9o4XpD4|KI@@QTK)_DnS+bje^sCO}L#Ww!xX6c4v!9N9mhK0){C$7Xf&Pg4 zd_0Ia`x56l?fKfysptLeC$-w8+c?i@d_@?&dQ}hSIqeUyB#Y|i;l)e0XFfcf4Z1gm zzL)g}1f&_9w80}LEuzCr^Cojn_m0f@+RpKOE^`x_l`&!rRl4Vi18U zf>Y-K!;2PY@unXfFb;N}r-MgBHC_`UhcQy(mWy3tuD4~3ITA|}=SN8u8DsvnpJa@u zC6i68BA4v*`8=DI_Q}?70r;;tP_xhH!#-25A8}}9`W3Lx?V+OA2^M*2 zg9tFZjPpEQY2-B_a@eQsrCgHjQxX@4RwQw8Xywzc%b9rt9%m#e_Wxt;Tj0E^ zs{IFM3`vp9Cq7a$B(M2bAVf4%#7AmMhNkAVi2#8VQ63tZDH;J0nvWSJpUh;M4+gK| zBN<<4I%8_+mC?-5z-wMLKr^pbne+dy^6f*MU#s(8`tT z*_JfxHO?sV8ZN8ky}ciNb`5!?8B;IcmOP26mm^M6PV!uSxhe27%Rij{%-KGEumNwh z`f+M(JB%_%ahM;YT>Uty*KirN>oSX@G|nK8*h)Bs`?2ns>{#^UeR#itxbnS*Ig z4hhcI8=__!JB%`?%~Yl3UM9Q}BAXwJ#62%7`f+j?#U)M-qnIBz_R8;(_Hd`26miyB zv!a&!adOZ*IgB#rMt~o&&JO3i`oR;s| zUaAU)j~T80WIn-qyk6rxX&d$ArvE~$0p*W0p3y!TtL`I(rp z3&awahbVFoaL!H%G;BU7G*cDJ!4n@>UI~%Sk4561R~G#^zDAl$JT49bx*sP|)tz?d zNGqI`9P@TRo*OxC>c`k&;&-JRa~9 zS`JS$4+vWQSmRjKlLM$X-Oje8aZq(%Kj7yyd(C9gFnytir++G5b>v zqs+b<dkg*-v^Ks?^K9tklpmKi0kFhVWyTI5~{s5+{dIa3@B#%&vO3=(O>@ z`X1X+?B>34fO`)rdTDYPWorW^db%DheuCd~X;-n$Qj0NiC`JCfT-NGy-zCp!Rfy&g zQBMx_aW4V!(`c#J+?Q>gC$ZHJfRJX)TryhfInCJ0`;1Q0uUtOAo*Y#1{ROAxj_~D@ zwc*cc*=D>-aYP^TJ`Nr%AaIccPWm6`X^vVuJkYvxdWQDo^p2a0-v*x^us4_;G*Q zC*1@V7KTi56WFWb7v|t5FldCGIfr{2gKOnp)}2_c_eU0lAG^fKCa_DKYy$7aSl*Cq zvboa^h}?R6Zp+UZ6Z;wi*l_NU4RUJ(5B53JLw zkdrFw$vLQt-Y3s#IS1wQfYaWW)bx6CV_?ph%InGZ*{*^?4fV_r8*npRd0Ose!YiTWDSq%n?-_luD06&VrAI&OKY7Bq&O{M( zNJ8aCiho)~lG=vl-o)x@ITxUQlS7^`zPgveSY956-eMhy_B}5xq8Oep#B$A#tG*Cx zz~+J6Ot@-=i7YV28H{n{vD`#fUUxJvGS}{2lsUfYl50MB{x#M7fe__ZhQl>SwqkPSF^MdM!K^TNVbPUET7eZFxoXnq8= ztr;f8YCP53nC7+I%Y;`>WZoy$t^Y3-WgZv@{B~gf>CMAL^YUVU*?>t!mYatH({I?Z zoIdZH(Bkv52`!puy>c*A^P(<%5K-TkftR}IZm4MfpzwLu{OIaF--!83HWwOXHD%GJ zaWr8x+WLXz6q&qoB2)7sb8Y{k%tPaVpKCt3Ew+h?C+LPk}K)b!zoFS>CMt1WE{XUJ z4dglf+1qe4M|~a}=tc`Pxkg!NY7Ge`J%3$9_Hv8^x5oMn$ALk^o{SuLZQ4~t0Z**4 zp3vl1{=D4F%8JZ!ATrnPS(N#O7zb{R$s3FV6Zr**grQntjmZ?b8Nc%9<@!05Bgu1G zHLvx$F%EQ5dtIQAh3FEjKjJJ_4_})W&SH60{9={p%Wz#?9d7Gc{K}t~ds+81FEZEu zTT$j%i1)yll-1qr2V)#)1Oi*oVe$NxTVnAnV$FWgo2bNjxg6^A1+ddzzk4ur<+xW7 zMx5ixVLV!JAce6TM8+`W*&EOT<57cwU-|R$J#NC<{&e!3_WGq@(WTi}0ta@f z4I2$Ntm0$Vua(Px_$q4eC_WIq#0U>K@_bK9- z6+zc=^e@;*am<38LpH$C-*Dhp{=8hCJXm7boEE$Ip;)ICo3};9mG9tmpJjh%fmw zkw*Jh-#1UrpZz1zyBWiQ+BEG6pJ<0kt?ePmxSp@(s4Vu_3~h7ph_m%J~B} zAzm++smfpW>9p7Hrrk908C=AXEC3uwazEYtN)f*c9D_H&G1qY5SN^w)Ast=P0}w``=T#a9Cx<^+*=Y4SV)%qR+PE~eP5iQ-!-pC^#?m`y0Nm+yWr z{O<+woEBT%ATuidoEB`QQ|yQ@nr{p#VoM$Xq4}M zMT{+{n(SCF-|(|*N}SM!lrr2&?2@6V$O4HNt{fv zJpkFU6>t=b|hs zE?_~>biC;t;5G5vh!(%1%(7+KJkgsNPs_2nd_!_}OljbiyA&9oYD=YIzx{j+I*se; zb){anY&jSgs2x_s+ZwiXyvZ0$@wP%1WNugeLS!+yCL3NIM_vxR*CcqA2Hw+g7HJ9F zl16>8@3D40rTx0X>lR+kX$}ay*cp;7pha(oeRs8;pV=Gaon8~ao1(?zluvdWTV{I` z@>q^D9Izi>MCr6`7R~N94$V~#EaF%fc5@u_BkxQ$y%wzl4(t{!dMLp$-*C(~99qu% z_I_?lz6o}N!~1}YM!Ow3wE%*672XWf3+fBP^4svi2Z=40n@qQ5FD8<_hyw?Kn*~F%DePDR; zD}P@8MQri^>?rb_-uhX@zst#UTAn8Nyu@k0ZYjLuCY?QPM*UdyQhP{_wZ@*OZMZYv zViuMjR(Q3z#ViZDhC8uTL+Z%SB)*tErJMLDZ`Vr}B$NcK%Sj-(`rr zsOAC&q4)O5kDl~AoAb%Kcv-!EIUcj{dvT7oW-}8&1ihOpPZv~HnL=-eoq(nHvYykT z^)klPE+ zli7UTeU6g#g!kUg)P+7VD+dG{q#NIr23;q)sGl?+^7@kM;&!!j~*pN95Y#0EQg11 z$c#j|_L@XEoCjCl=GBF3HzC_M7lBJjp=*mHLJIHkr->9YCPcDde2NrU0kOQa6uJsH zGNkYxKS`vJw`G18hWcD0h2>Y;JNAWT1h;1*1)Zv`kGCPO_7S{6WNwss{w!_0tfU?> zXliP|5eQt`)YY()s0a$KX8eo2T%;{wO<7gtZhv&hvMcQ~C-tn|jQ1&?HOD+_j(FDp zt=reD%N-lyxhSd2At@1~&iNFVn`16FM;AdQR5fPuK+17k$l-maPPaSdn7e7>bV+oW zBTff7=jw<3O35*Za*PZ)yw4ve&i^I4#_ZH}66c@$W5@yLpL>D04(cMJ&YtIO$P)+u zS+6K_=a)8KR?6+hOdd=O-wF&SZ-vYCr#y2CE@ym^8v|Tju8jMSnRK>={BMUKd+?$S zJ0!{+V7xsxG^*G2a#36lC?e2N^`czJ0#22zfbLk{b+ zaoa?WJ=ss=7pu$BxUH9$mSYg*I5p((KCepTkQ4uZ$7;EeJ!m%5#7CBHC zInh-&dmHk$`Y{f!?G|Oi^)_Bs(x!un;d_C>R-t9wa+U4rF{4o%S+0_0mrd_dWf<&&DC;TVp_S~2v=|UZem)Eqh8m` z%Zf62-+G;b669EXbRvgrgb43D z)#X@xw3nBbV-V$-9CqhN8I!f#k)=23*u^* zRoqMYa4(j3NtF8Yri?oaEqd7(d9eu56&W@L+T)!X`6BK0d>voorqr6;m*dAQf|flx zeoTvdbV7^y+FutLgVqI^@^pJ)%DB;EZFj*A(aC+2R-_@=yb+rF*A>c9qDksC=!E#=g?6%Bj8}im2Y;BPftveVzl^}Ss z9Uwez2W*s2j2$nGx3wf12i*rUhip{WJP1*hkGJIXof0}##v*=jU8G)W#ZI{XN{-a7v)~u z^C~FfZe0BRqTJKJIqKUK15fXmJYUN?r~e2tjzE*?#xq*wR-RuHzfGw3HK`Z$XTOzo zPFl{kPQwX1&$SribYJVMtC-InedffmFx9kiQ_dQFCi{+!06 z-<=PiOP#xr_T>|D=5fR;a} zKQlJAjhvP!_4H)cb6TU6_3QQI8tbt3mOs*bqMdt-PIG^7ZL`#J+O;9Pt_6g#XCe@u zy6P^V=@-J_J zL3Ay7PJ8{X%AW@b!(g8Pk*FpDFM&iK1qK;G5}}qAW*OE*i(61E_nGkL^!95ZuMKdg zHK;9PJ*RnT;gzw0?snHEZ*p}TTo8AK+y* zFkMET(>M{yAYRs(jv7>7P#Cl_r+UX%(v7o*x|y-jm~LE0_D%? zep>^>!{j-ww(#*R6Ax&$i}JdLfn#IPY3QLgdC%)+*f1VYIX3#TlPY6_HFb+Q9~&a0 zj17@Xe&r9_&RYK2_hM`~?e)9rS78HUn8TSAuKP~*+p)j;m>KWFFdb@2Yfrv{!lpjl^dm{-n6^Ob6QQRyfP*otR_uf z7V9QWhMJqSIMmdn7rC#B_+yijwHN4q)t2>PvanO?wqzD+*zZH*TnC3C{}ky)f1$uHxW!;t`E9d zvgEYamwH{3KSn7r*rUy2J`q^*+er9wTiu;U%AECdzDP+{BxsC_G~yzf0|t$w0G;R9 zh;&-bV-sBk?{0ww6G`9#t)@zOXrnxB+co$MvP0B-_S(hNeBrsO4Kd%18%%y?z6`%R zpjamfGY9VLsl{&;>Af7!B*L91JwYC6U7^{CblR^W^}2>BOiEn#%yeqfnfc_G+waa| z;C&*0F-VODUWg?AFcZHrGBx)M8gBwMShziDw4~$t;>2h*qr%rWHEFr>aKm2yoK};j zJhV}sw(XiqXy*OY%=T77F>@ax8ox4fv@OAcna|xSM(HLZmDj{C0`GX7{ZSr9>A72Z z6XR()PKzyqj*cgfw4QG4Jp0e&;nX8&wAE_}uWOjX%*166Xp5Nz1S~cEgB(|G<_GfI z&^c>){wj@h=*YxejmHu(g)5Kf~JRzA8KvkE#rsU;5U_Hs|G0u zuXk=g*5kD)3;XDr+QMt7y5!+<_nMD$)#Z8`o=?}@7eoKzUmwFQMkX$zw4VD6FW)b` zeERSN!*Ii(yslw@>G$(_X)v{LJd@e3a-PbA%+P7jKnEogSNE)Ao%@{cAM!n)vOPb?UKK|ZDZ8s#uCg-sqRcTD~AF_B|RY?5NaIK_tn zI%gi8V1g|ali9?}@!U-3R2}R1u%FR*ZYEF7omNcRw#+zTUT5zR6FY6nlqH?@kgnp0 zSHj$eru$W49L!>KS-^(KPT%keI)U12Ai^+@Y^;yfPUoH1zKIkMGf8B9!U zl1I=TQxf(a(}qhZLys6Q37f}w#e}mns)n5nla}Ly=AT52C#~m<^MnoOj6oYFZCeHt zXK{N+me>g=FeS>4A06XKW;aYi zor@kvKn%>36J9BT*>HK|HSzm0z`RN!RS+y|6u&NSqI}@L0*uoKyoeEEkS@k<2&aN23LV@QOgz-}jxw7#6QbK+g(;pL>D8K}pv7habD>a5f2ya0$fUiLB5 zpkM&gXlB-8P24@+5}-6FP!Ne`0+7+n%Mpzq2N(nl0Z1D4?n6}5G3c~kqsw4)y6N?! z0CNn%q}GyXEz`|~g>fWc#9DIGs$#mi(3^-rUJd|X1(-JBIL*bdTSgYcVi}!oE|hv* zvW(6%y=DZMZ!&IG12d~IjwBWe7+DKcfSF}rW{E&izWMjv^=fKJN~-+G>Y){S5fmW+;AABn?^?=+j!sb6OVWOdeivLyafk(e zF#Yt?$4wbGcA(+7rHCU*2oSslN0s5CI8FnO8!K^)hpV%R;jnU*y?=rObia$>VKd2d zTCmAAx`&Nf+V29}VH`baT$2HXWGBUztfVIZo7`V@8_C=*aqIKi{BX#dk^yD&aBK>l$$(751wiZzw)P}FLTKg9z2<% zlc(21J-r@&*0L?c|E7yep0W3C$e>Aa^cA#d zg{of_q3K$Z#c2S=ul#wr1&)J|EXbZg;#a~#9#zG!SQEvF zp+3%K3KV~06XNjlz2JZDS5ABVuKHEwI46!ria3&SemI4yVh_c!62-Sbb{pp+mn5B< zI;ozc9IrtN97cQnuHvYSyS%ONSl}3rUSW@PdF-3jP*R)~!A$ns{Gwc}$+;YXCO-tYvySH>t^}C!GnA^AYP$0Xc(?g`!7n38?!ZQ@Ot8U zJbW@aPn>#wGs~{I46K{;`|>%fH9ud}^H|nu93MwkoONM-WTodAyViiX);O{n;ybB5 zXFv$t_Gz9O*K*c^xYk@YTpVAJsHM1YInafwAY0Tq-3R!M|LwFygQHJX@FJRjWo~|=o zev`Si*hkCF#-c} z_ItR`IpmRMy@n4e>#3@-j1w32wt79=`>o*Fu6%ku|Ab=&Zz`{+*TEjKMhI)mYa7q{ z5MJX{@*0!2jq{8*FS*`eYioF=Z39j|Ngs|)c#DrDZ?R(Qp8LqoL+$_2eR_e$dsnVm zjxNq9#=+aez8)Hv<)^iBUx`nT=B)UNW9~kC$F+NlA4V(G}#<}{1;^>|a$SL32kBUApt{6gYjG4)O zAbGctPkixF@7xD2&m%$Z1G~kw%m*5`%4^kp&hU#fqIdy9b?yU71Hbry`2}h4ME|?7 zE!!Yo`~t5+e4RYftk<|z72f4lcrz-mclB}TSC7=-i$Y3UzxT0T1@A`kRIVFQPy8a~ z-Df;&EA`}4-Rc+CuktQ8p2V=C+Y>~TyeqsSwTS8J>m2`cMdcQ*{$LLOQ87mEt$O6%STo*D{Jgg zTsZ8RPriKho0;uR{5}|FBMlY27*UqAsl~DsuXp92puRn+D$-Q_;thD0HDN|J9%)9= z+-!)b@|`wSZI49t$c{98SidYc)muGP{hp?J?W23Dm#%8pQ}wl=-!WAst3+3QlF|6^ zi0`ZWBMUk_CgURe#{!LXmR$nyODFY$(}B5Ol0}E>C1!a)t*uI!2my!05`eTRVLXAT62_YnY>Lw{xSN4f zUO6BeOmPDRPnHic4TA`l$rP8bnBwiWc_K3`hM1!cRyxEMy#dK#hI~GgWMwwZ(lVQ< zSuP(9i#drj&D=7K^_-^~F`l=*5Su5rU(I@?5#3IQ+gMa3jbVmpnI|$zTOTHi45yZ1 zCZF}e{>%c(D`NqhrDXAnkmjG1(}@N1eoK5dtLAWBL_ zhF)xDAf07bEREM@lg3)$N7xJS9A9bbuQ|!dn=MZ#uN&B8=B}#^Z0-aP=U>ChkwkG2ejeee#^d!8i<(m;bm@6HZGrnDim2|#?W8501zlX~4iCev8m zCV@s7S=_ZM-bBO^e1WHcph2K1BOFs;GG`J2hxVEH|r_3-iA$i zWw7Dpk&~yNHLZTiAeq(bK0|nty}XTKjP18Y@m8OF3QOMV<5O6${7F1E#zhXtMINHe zq%o$>MZi6hJkrG0a&RS2rw`)^-j;)j*Xyy|rWdVOMhB(=RY0$>uRw$EE&4FV-*9%{ z)Ligf)IdskT37J{Uq0pw-Z?r3P0rUsgt$rH3q&EB2x${-8t$|=jb zO>=O$b>ofvxpfbZ>BNGIno|4$-tBMXC!J-w0=}L?lO~Xs!^u;#!3AUpl2-3sp=sF9u)|A{TuKNw6X8CL)aih?__Y8z?bpqG*~ID4OOG1$iYQ!5NY)3KiNRvOP_5ll-TrYc=#<#ia(uu(^B>$;*oSkLt$y!PkF zYd2Yx_oneoW^Ma|wN<>`b7alQH=`p<^68GeN$du@*DeXSa@I59R_?V=hr2s#Rk*u5 za^mjp$VWv(chQ$4lHo-;lK!ZRZi3(M!A1XSJf+PoXOgGxGZXd1MN^kDUh6Z(daX+; zulLkxaQQa!NJH)7$}d;edj^T+lBwj8wt7buc}rJS;XQ5F6W3cpSIK1&-ZRECnMH=B zPtygKT3h9}=~gQ2CEyy;hTtn2e{`y5~~57}}gJ)eF%6oMkT{w0AB^DT zE)`)Z4}?k7bC+5kj^{4*M840J$Hoykt7c2;n1TT7nh0^E5h}#q_pu&n^PeZk^Lh`% zW0#ojNVA@Yp9rv+J`HI|(s_Rqql`7%q(cG9l z-B%($PV>br=pLJ3Uq!~cq*)il z&8TD8Y1^q0N<1PY^UipKIy$BzpJXCGtJ&NXrd^=L4`KK}7*A>NWRQ(6@;tD!O_n`_ zRpOFUS&ua26vKPoqUHE70vzS3J6Vr(mM#CezueVnwr#WP$#vRJb=)QkTft!-a9<$;~k|QVJi3RV);< zL`@$m;Z$G5UZhQXq)l12a#e>p$N(#^9JmdpxPg$OZmWDK z_7p(yhov9qQ(T_zTpt0{r?@1yaZQ|>r#q>OEd3bQeHYg~o~RYg^@iqp<7qi~V%k%S zJWo(~9efcA$%qdz($?0mhwDi4pmWlzNx!FBzuHF`E!ym(i`T7l|LBQmBuQKAyx8&k zCcUxkg?y&*8awhAY&8z^+Wv`ronB+P2+ z86HsMNzT+fNzH?CVs5)_z{a?UxRIHgw2fdht@Hl)7yrgK@>Qh`tgUG!0=7*xJtn+X zm{CW1cg;8iimux>%!mlA7|u&K=8vY&w7;9Hz&EN{7qY+|JzXPhYr4B=NL|z2g*r$E zo|;P@X}EG{q+F!w%I)v6o(ze03=eT-^15Mgoqe|pyk_v$KH;{G_QgD_^{^&rTl+vm z^I_c+C>`l6dl(v6(vLjS3~TPn64svl$dJ95AbZh}DX$yIbaLB1koka|kq5IHn=;xb z=1D{avKc_O0LW$ex;ySdDezW19sw(wvO)SsH=;o@Z&b-`iHBSnc<+{U|9 z5bUx)p;O87(1ENuH3K9)&clOn6;!DGzn2xgG%tVT8=NwtS8E{#IO*hfYF#r=2Exinq zybejeL=>cf>W46kITdN5XtRwGHPOpNL0%aX5ydccUHeahkj>G9d6#xYd`VncJ7-zP zW--&j^Oqn^X^r)AjkEe6E3T`5ud&v`_ylkMjM4nqJez?Yarx$(BTw8)n!6zQ#o?eA z|3Ti8OVMqA>%M>R7JlHJSzB#`wzy8mW|h3fPi5J2myky~%kF50&aWkpG(7Hdc+>gh zkwzcde`P)8N!EnEyzL#oMfU!&@svi}3*!zvX92rmA-Zx@<^MOZmhzaO`f8kZAeqzjmFcqCD8MO zYVs+wspF=huex0#E(qd!X#Ma=Iu2)dP1hGfH*2DJ4G}Ic^jzXk~}@iexxC3 zCQp&zw1RjkPcW1~a$XYQUXKVj41p7=L>l3Qg@0*;d&5{C=XU{XoYfH#?w?lcl$_Pm z?{G(^oU@Xp!sm#Sg5V<97xV}x(Y?dws1BW@P%gYvyfbU7ZIG_*f~7_ad8EC56`ozM zqMk)5%3y6RVmj}^lOsBk#*Q-fCLgoZmNewJ&6guyZoC&wX2F4!liE&r9~;kP(d%Fl zAj`RSYs+gJPnSVud?JrhyG4`|E5ai>4vZ+}R*X+o=T>|_<|#WJ$;PwFX3Kf@`yhPr$XUBM|bs z1H@w4?nNLsM=Wz7NkT1?7$U3!xf#DmdfILVOx8QdF$J0#&Q7>&**9Cp;9a?4cy0OkAS{TAlm0$DtfuFI+9 zk(QIt_|DF+$s;YZq~Iy?wphQx^}dYj&9mz%&9+%;4%ygnb0M|}XVx~1?o+Vhh)BuI4DWmW%tpw_I#MdAMI;^~guRW}`e*l_nr-+g1< zEW39cUf=Klg}Y`93_jPKz=Af*kzQaLeajPTrEz-ix-9$T8MY;jwz!5XiZpqB=5`0{ zKs2t~qX;%0@yWq%0kA&SD!@(#*fTZ&`>}zw2jf@{uzvwq+sYyhus;G=3}zXTqz&v{ z**ySkpaeAiOOas_doLnV1+otf z*&b5c%Yp12Aj3c5kp{A}fov*yqz&1J!YhkRPe1Jy$dE^>AC4-T>??vyqL==qBXkrR zVM1K>6)B-qeQOPw@mP)#dI(0Z<%*<%?3+M_NmJUAri1pi2}zt4uhQe>h{>xwT8S@p zUn!zJrD(@Ng4Q#oigII+iWKBFV~% z`$ilty~`hrA*_xe!5V6;yMwhqt~Cq|hXo7&tE}W&*wGMH+oagyaaP* zTnhnTSZ&t_Yn8Ef2^JRL+HgUze19SlRdOd>Yu&`CC6g{#tCj~#A~RU4p9z+Xe5o}m zSiaX0%F!_QXE^Kh5r?Z)MTh3};x4P6h7Pcoy~-zMrwS_z4jg1wtdIowOvnMo9&fJzirq#5tMBBD7_dg~^#-nxm=hbAYYwdKK+DU8Yu-l|dLts0f|Awx_0Fdax@)8_#M64kHO zQ(a;hjm2)!%jA(pTh&h$p6Qu(z;4kA$N)8sbQ(`CVyXT1rEE(YnczKG-)uu3X~?27 zk;m)c6$4ku2Vlq}4Q#3(^1R>0_agW;TRo+*SH2=}kY-!AM+ML9=GS}Rxh#9lCREb6 z9`@N^Jc@mg=JnhU((AeZrS)9*uG5F$AHGFFntE=VWZ0ndwn?;`^U~|Jn-8Tt_o1|p z=a=w$(#P{l*oVtPz42beN=t*}Uc^e^7d^WVrM%V8@OmlFeX^nt8(S`moSE@GDAI;^ zYJzvF;ZfK(O4S?sU)`Ox*Kb}Lv>7u3`w4`_HDGmN?mYX_&c2WH1bH}cEW48oH-FVXpaA`x=}Ann(cdS$^5M%%iUGMe-z~eBEhml8`x#AWYkjny- z=u$VN2yAM_IzVN_dhXDH)z))s5f)_~u=Ws2C&>EtHDr5`$8tkvDTg9M*uUY>m~Khi z3a78MEsIRobNdA{giA5Q>Nr-N`zO|OhgMzBtsaS$DE87;-5AKWKyDLsR2wCJsYWkb;;Wz5OC$$ z@pRqyHL}um-$BMo7E@p6{pfVvcd)UNbstnBmv7o7)_u;3SFO}M1G%tLSUfJ)SI_cV zDeF1bYDyMnu#7ZZ^ma59gMroBBUqA8fweZNB@^+^G7(2DiQrOeQm`aKfVFyLu*8YL zS{MsP9Y!Z}-FK*13xCS{w(!u@nKcJU5!xf@tiw|G-V4y%Tja@e{IVFNErKVDLE(7< zEcIjoraVhn<#>QB1_jUxn-7$S>nYE2I7yJ@^^GF`Vw)tTp75le^Q2yrnWV{*XW=b+ zn{5|qTmlVVYY*~Tdl)wGG#5o5YptI2Avmb;q~0X9U26*nxt_#VsyyoH7*w5;r(^H| zj6qd;!hURX9|%o;=dfDRkRpGZAU(*?E4wB^PGdJ7zc1 z)J2X%%Z+C`@V2t}`P&%wOPcjo+n$ftlY>rg%{Td!M%>sw+LDG&Rky6?JUK$*izw2p z=Zm}wp81RG<&K+hP|L89rhIN+%7qN_7adzN+6+B(AcpKCk6Y`N}TbD2G*L~9E zYk3KF`!(^B#(D>!oh3;?NOky$S zbDP~rQ>QLp+ONMjPWrulH2d{2llvNU;PQzML_YPo{_K}DcoIB~=en2IMSU`h^+?+c zYU5mIP>g*YCkL`#1@8gjC3A{=R_;?@+kWc6{bjA#yFQ;tJ#X0jM~97!lbrK-pTG0i z{3g67_Aj&_G&40a0o; zHflPLC6Ba=AiRyor$-EWf4_+Dr@%K*t|fntZ&b`=mM18_pBlckQrBtVLyoZNwd9e; zmyq`Wrpe@yM&^XE{jW9Tk>+}+6HDZ>hz{>*T`M0wPv7@zVY$xl|2M;bo-J>YwSJkoe70DI!jBh3w#Yy|7c zCSEqeMG)S`@@Hpjr!z4@<;>U#lWKD z%4y)cA$X(>pT&B`hxtx6Iy2>MJU;!{RPQlGe7^!dS)1zLe7Sf{%??-R=Zh=w{mL-e z+^AT84}91P>1RGmTI^R-v(=SyQK!Xz!6PmBq&wCl?IH+o+qxY2f=6@SR5&zS>sWzx4v#47tWzQ|ZAxk6NKYPRKQZ1I@IC>$ZLy_vxuH`UTc)Q+ zJInrhH+iJ>OYixeNqp%YH2(b|G*iJd&1g9^ zLrHl(wlQAUG{Yf3vZxt^?BRLHzDTrQQ?t{SG31@KXB^e+ZCVhY@hJXR86;SW#o{C7XFBlvk!Tsv+PwYEVr6S9%<}!>`+s)t&KX;;wO-5Pu8p8ZAqS%Z|Tw} zygiMlZ8zGF7(l*N)D|Xy;rRqGlh;lIq_bK=Tj>b%IRTo;W6B?)q3=LjyOKv5dCdQV zwnmXh8i!q>)veAak2E#2LrWE&#Zl4B4p+ORtf#yd<7wNC){K7FsQ2+j&0y*no=+W^ z&(^F$zt=}P=d309TRLibQyPsuKASvZJn^GPFv5NV#9ttfw2Ux(XM72Hq_gaw$fmaI zM;>W>FZs7<+e#j38Fi4#+E(zcXFV;y-lb1?ON^&&H(Fczm9*a9E@}%CQJl8BgxB72 zene_#-5ilR)t1jqizuPSqealxZHcy&rf+R?0PBfwZF2x()(mLN*4(6_t^3jTKGq{m zZS8n-6`rjvMO!;!8WmgbnDTBmp0?d+ZRs}`dygt=>pEy_KM_Oz5OJixoi+y{KNW34)L#xk0E#}t7^EFYS`QoA5nuOJ~wOHb@`nlyhVUFOfDsV4lj8-=x2nFtVQN% zLH0PT6!%=; z<{}7h;{h@wJ-G<*_X2RBTulBP;ER!^Vn)j?h;@~Mvb=#b0IrU_fpnIAcoX(PF;=B5 zX@LGNqS%Gxkp}4RAQD|h9%%#pB6$k>MFXw8jR(zS^OPd!M+9`9ZO)O^kEk}Rx(Pd1 zw|&GwKSG{@2JbFp8K1$XkN_l&WC?e3Ke2>|v@Evd(yT|?yA$5VgJCZC-6EJj2$(z> zbTEkpQ!vQ(6~H12L>d4-2QZV!BMmTz#0~*z17ns^FtCj3u8Wpo`gUp&%pV0zp1Ix0(@Qo4v~w=p94%XhSXZm8$g>E72u`-_;_Roq_NINPUYDFX#-=~ zfr7!TulnrTtUr(m(P>36FA11DBf_derk3OhCV%E%$I(j!Q^t z+o`OICV#=HyZ@!ga>HT8>)_okzsA#Y@U%>LB}7gnuKg3uAsTjx@5|4iC`)>OKT_>) zFz%%9TrwHkPm3_VmSV4qPptTt02L{2FDzLJr2jNjK(h`rpdej0+jv^eTQPn+N^XhB znLb7Teq}xJ<~Ex$NwZ$N+-*F&ePx46Pr7S-l_y?NMCc@ko|pqgkI?l6x+`N#^h;PcgEvm=5p4=$gSKz=jYFwSNLZuKp~*`Q{)109hSN3pJsoS6TH6@ z!+8>bo?0aeVPJY{73;N6tin5xHW2<7I!GkG4PIEPsYGIcD;2b3;Schdu%4J zCjsxVndXb@tPkLjC&mSb%dEb*&U`Vc*M2#GOLj(y;t_3*n{2{in_LaQf_<=_cy<&_ZG{8J>ZeIfi)#1o0*C}#e^ z!#NQwkD^}Nt2pENu?+@q5wY7=M*M_9gtcl-{#L-6Ee)vl3h+2~k%C{f#+w*;EeG#H ziJ8_`Y4AiL=Tz3a<9_(v0`f>RF22!Bp2WpBn%Q>Mnhn}M1b;uz+A7U@Z7YkscH6$B z{8=XF&7c2}^++QDK0C$_Y5H;Miyh~n5AkEeA$}}AD={^#*M2_hdB1|aZ6$e>uY^;$ zA4~FI7q@p2Yhxqd8APfKEATe`cRr}S6Noe{t%ac4IkUg+A7U@{^~B48}Eh6dQHf}{N;3{ zv6=E2%okg+9%(G@PR6o(5_zQI+h0b#{^XH1-?kh=jeH6E72h_z>f4jex08C3LrA?e zhiH4-cyCJ|B^V*Y`!fL*LH+&yTo@#LhBMIU#LFX^co*lsc}dCFmB?=j4PTR9WnYnvR1zxF*^0_ zy8#|{Ou?@<+pJdGcsb+j^Vd)z5@(;k#uValRe&q<+Q~Ow3rCG1dc2`(#Jd4rJd-ySofy3FBH1yafp79}VzWp5Q zsgZ4->M(5T+n571ZYTBHK19EwaqCywwv9HP%GV9w9s+sl;&?~y+sW75+*4M4O5A=J z=DQ5)zCVFxPSRni8q29Z@=AzozAX~hzFhR}2l8|E3IYmyDLxZhMJ~8rR zXUzzAci&zY`7t)CbR8uz-~oWg4oZb@Tc}^Xj`dhh@GteKe!pA0yX&(Q*ya z%zHhSOWwP(jo0%&cpdWEa7#<%^M3Du&-=TANL#%VSEIwVn}^9sn>QQ>$O=Q>a#P9r}C9>0FTGA+fx@uc53!V|Hy4t432m#ETlgx#uVc* ztD^i=ly4s}R*dmB#?x}}kWQ@_BfJtKo6m~GwXcNFy2QgG9=pWTBWFGa@ei9>ZB-mJ zdDeF|wb~wU2CI3WtX1bkJhu5*!9y|fhVT_0qY+P5o#Ramyq3cs{s+ToE_tL)A=4}C z$#a{3!I35LJJOi*5x@OG2GWSf$Y=9-tTg)7{@K>+NzUQ90cqCrw|3<`zHbwKvz{7$x;cg6Wx3nM`jvP*mHP931ylQr z&${r%vG(Jt})NTl80lV{uAx#NXtHO@+2nCAX|Uc~4v&4v;e4hAU9mn$|8d#yT; zwpn$a)zfkVZ+i)B1Ajg)@olAXbMP$i9%Nh6^gF+v^JKql#cr%en)TY>ufnsx^eUh$=xIliG7ldVPQ$!uCg)AswhWT@r_}H_PV#BT38OA#O>FGS3+d-W0AOa zW%#j6oNNrc#P3EH@lDff@_Jr(+T>l0Z&2)x4a8v}MdHPpMr;eDuozU+GB_0$(pPx6oSh4mdDm<|+231fSl9fp4DPA~dr zvRCZZuCiCG{<#dIz#o0DSfN>Z#C>5e$FKOOrc5P7KCgbfywy+NYF7Jvh>X5vY1+O` zq(Z_HjU8T0g;*7tVm+eD8HtuLU9b&#EC=sWxsLG4iOe^r>iwbdMVWVuWC)%m4>`5Q zr$GFWii*4=M8?jLi!9IXv|jH`Ok^#`iCrWakDWvwX>3sJi_HhS8A4hfZbqQDiJvr| zOKH{9aOL2tg$APU+W#z~9T1bZTj-eLEM!X?mhK>a+9%)$U8?egF9+0}MVWVrG4%H=JAW#& z{YzpDS@NyuFka-D^{4)a;+_8;sp?HkWG&CK*+|?U{~>v#vuynK7+3SjBb{YauqgG& zM>@-XJO~y(n)OJd5A92MUgb)EO`OA zTcfS|7;3*6(6E8-Zva^Z8zJ)C z4XiQWtYHz2<-9%fD2_wQJS4Yj9>wsKEsjMmkVl$Z-2P;^KJh)?ETq>f2Ujhmi}=3< z+BYz!v7AnC-w6v#yK1-ZSQTmMW>~H*p~$+De%0HM$8zuxGCE!rUOACzA>AsOT$DMv zf%o6+Kb@P*LMrmz5P8c=k!5ZYn2Rqlk+mFS<*SH>`;bSPJpa&)@b3H=Q4gEJK88pW zF0a=exVrK_y9hVAr{i#wpq|2g0C2b404^L<;aX5Q z>D?WYw81SKz$Z?jadiQFPM}37x(17$bRSGua!;+wJ{YT_{E^rPleZkm0ZFzY43>kZ zWx^|Ap+w@^Rg_qQvP+!ogSo`X0ZA<8^tB7KVrvWuoFsvZ?~JG6uuu@zy55mv+2*Yx z#irLan3{akOM>IN-rmHJYPq~;4;w}{L`fTZ+ic}^@Z2&EZTrDT(pX(S8xOOP=A7}K z9YB*gd6TVtbx>N-z1OaW;W%O5ZRnoB(7aei6vCH(h@nSr5eB z3-{x`k#&CFfXd*8?_Bc-_^~~YqJG@h{J5{x({h6MLy2qypOCnXCqQKuB@KHY03VZl z7(CMEV-Hl}EhI0$-f!Zj#uZ9qT-<}_U_NF&()8oEEF}~_ehWsV?5yXq$T+&nW`5FH zcJ*=aT?uxOk2JCQho!`iCW^O&qquMDZpzf~ zZDjc3u<0R8VTqVk4q>t?e0v1UoD9*9dT&D&upB&rUG@;B`L;-0`(NSPE^%@Q(6I&CMf*%6#M+JD+Vf!MD|qRlaWcvF_?k4?jK#{YxxQ4r>ZaVtJLrnyd;_j)o~Ml~ic3KHHet zv>ZH%AXux?y{mA8YJxU+ViH!<*9jy&XE_^chmBy9>=Q(5n_pW$%w@#K-l9FIL3f0CLs z`p~{A+g|<v2~8+a`zct60&HprQO1mE79^+>}%5zF72O&)1n??QQ4 zi9FKur?ngOarxij@4sX{(imsAA=kKwJksd*k$6`lY0B5Ufc2cW@ICmk%#_F#NVDH& z8v_+QU)Lh2z0`va;CR)y7m(+Ds2|%}yxH0+Z#U|XeRRXOb=Ua3@a?Z-9M!{C$w5zH z?F?3xgPyF4@`F*nJyjsXQ4V^tjq$V`JS`Jm36agWb#MM3;oB~8a?sNyP7Zn=MuD38 z6dif*csL4ok|biZ>>X*!O0rf@idb%Wxq=^t>mCZgwhk5BtcEYkRaQ?j@LJA$w|>x5 z?%lpL*Az0nvfje|W8Fv^{(2F3Hd&J9LC^ewsk7sODeu?o$pd>Yu4f;lu{-<_Hsnq- zp3;yRvbWecV>#LtodLFOnuUUxx}d$^XUJO?{#dX{)|#eW){F??oNO zb)ap?^R{e5oi)mt{>R!Qmq&Ze@ zJ=WS@ggoY0wrx4M3U5GVTlqGD?-i1U&m)iUy+YE&;qO{jgU$y}f}~>;Ki-8ructmc zz=0z-br%m2Gg-lzt+M2u&_BFB=CJ(w= z+*a_|2fyX`%6;&K$Uo&O3oYMfIeo(S!Nn)!MFFai_f1K99r)sJkiTC>9%;l>xmj;( zMAGO3vA1;u>p4$;{e}r?)@wN?>MfcFJ$yOVlBCUNZ49W-Vho6UP4g<-%AUK&ZPM%` z$16sDpZfNFa9)Qzzn=Q>G1QgIM@-}qTM0*T-yR0J>waAH?PPDk7QAcmWz`Q6EUxDvf|l_V zPc*vtGH*kk93p7JYLR8aD<^Vt-|YON%;Vw^!SmMtCXo=;nRtS391jsxh`fn6F_AB! z$l`E*=!Uexko#XHVd(AXfoNX)W)a0Xap=Z1-%$O)z~XawV4%g$6RCC^3`T>&fF)W0 zfo0`IrshTFx}OwfJ|hkcxaK#DX*kvV89Xphq4~{Bk}PKCdFHFMBx?W%qeWly5&8WdftSJ}(Q<+P8}+5}$X?SMhm;0iVAW zYf|@l6$?JEFwEy!ZXzqMoU_p9MdrGn7G+L+-ZfwJc@-Hxf6K=kXdXVVBAd^%98;pC zzxRl+`y~_->$h4r2+Cu<6N&^TN6vtPiWl`KBi^bTLetY{yL^O4Enlh9a|^ z!?fu`;dMvzB6Hn^MVaFh&o%$aqaA6oltdf(=!!fb;3CVJ97&esG>9h;EXNZmkKscY zDzei&<-vO8U}&@%0u;4tiYQ)=IPaQYUp>w@y$l%e`=(uSDL95|e!Xel*32yTGO1Ti zWcs|wTz64X=J*D6uKDCW78XU+uP`L!V1I??5q(tiAK>bM!E$K(zo7ZI$s>(=ePTI7 z+N_~%%Ry6X=*G;tKqfgk#=)XDVjOsyzD@OUu;>jmfnzOdr^sTBmThQ_mTiou<+KKQ zS<7+S>Aw+R?Zy&m zemKJqe94D1G9RSYSO-xsJ{CPhkyVqJ57dA*AFv!_<2$g1j7E$X z(tOU-4;0IDp7Kc?UPJ1YgQnKdh3*G|Y&qn_*jV~;j16Hyv#ono9~(CrVbjIW&x_b*g^e6ra`r35HVd*~gj8VbYuN1U7t4VS z_ww)TFlP?7)<+vC7H~8B@d1Nlkw(w ziznX|FUFgEIM>IU$~E8c`u?hx!90Qx$E|1`q6oO5NgXLK^>rmja`!S@6 zqxAAI;)_g$b-yU$NETy`qd5604#dEpAO=?8*vxR)-s z5_9aw-g+SGk>=SRkDYS1M`9)4svM`M>4h?M=>TU4vZ~%xS|3F zVxr=(n8|Dxt zdo#uxCNzC=Bw1D^IakY@OdVUqyI}*_UXYl`Cge$K*)kN#`;URmVj^j;FZD{;EpTXF z@~a|_cVlchj$%wy#6T^J@d_M>iHgH~jpbad-)iGh7VEbP-aaw5NE^1YF)^@dUUGS0 z!?HG#jxdS^$2EP4Y>>*3z3cVmZdvSAl0s@<vhXUnr~cD#F5y@ zaU{88l3%sJMv`w-;OJ{OJa^P`*kU;TwGans*zK{vMjCC!ZZ@_^8{V?{WY|sfjVlB1 zf8xrBiOHwJYp|&$MrcaTteD+c6UE;{i`$4p##YlLZ(=+x=ksWOmQS8XlQXHTFZH@* zH_bP$D&pvfvE?|Da|bC78G56E<2MP8sfJ^!@wA)|n)yBahjx(-FvFqsx`jh?i-y2~ zO!Ebdf^;1HnL7|mcaJ&B{Es!!VrKZCY&b04-J1{x%dtW6Px$IR_vMwP`i#f$Ow0_I>JZ;E$M!)tMz<-qn7 z&M6Hb4$`Q1ZLG0L8#Zm*Eo_=^TpieCV*t{oYwTC(V5u$5Cs`Bm9(kd!LuIUpEoC@T z_g>Dpv1Bh|len>DFZ$&FfsHiZxTc6BSx-BTqKy>CEXau*umT5cq&Un*Ea$wn#MWRk zZ!N+2l9=cFAfydjSsRU;boR6v_2SWW3j!B1HkpaiTP?yuK3MHm3#+1hIm&mY;w8b8 zTPalm9>*LHZ1S5%(y*)qc%eNxhn$ z?N8zgFXUxxt8MV?4B~p*pQM`8n43?Iv$Uik7+U7b>0e>}$05Npy5|v}&v{Pwy#Dmy8Qt^I|Mh2=YMgc(KxoJ5 zE+IHvNA45kQRnUy!YdKWPM?0}nH(m+j$v{vr=;|iWnjssc(qrSNsMma22GGv`1`*k zMzcuf^0lYn^He!BAVA-8_19ZFIj|>Mb{lM zA|KpCjCbo1BaV{pDVC=Za;S3u}5{`I(G1K5xA5Ty283Kr0^cENu(HRz5M1=q`(*#wRUJ8SV{_A z3*8h_SdTAln@F)goZ@RR-oGVM_{@*qU)mN@AZos3(OMj7#Q<+3`oYTlS&WuuI@}7& zYS_lhO6yTqK??(cOPjhHau7vO#nqI5otKxCLe?m`+c$?S2Vg(wiVfWUK;u=Bg>}6g zvh=9=zjXV0b-CY$cqU4P+M@<7UQOUU7UrmlaG^;5<5wSTz2 z{&vIlDaWlLhxJ+E{9i}fv1@hbm;S~1W!uo5Uot0gezp-EVcPr;IzP+EV;e6kt;@m0 z@Vmg^@}};8u*p-!E=us{<*=T_K0{*}QKe#|ZY*{I%+G zH1F%>rS&n0a@-Sgc%O?BIgme!11x+jk;5Xq=%E==UL3ahE|CLu@o(Y7-iADJ@*5CP zSVkV((8+Jm`vRqOIhYvk3k)W2g>NB86AVpNd`tQ8EtZRHCFHPmn685Aejl=Uzo~yA z)zZGI_?PmbE0&j(WsD9uj{S#2lp{HfwOyQ;_8Z2#G%>9WIhp#}F81=WqF~7B6#Q7o zVSTpOByt?Ze%d#$E=N0DO5|zR_o$aJkIXA7#}grk_xaOAj-#!gUwn!jKlSp``WQqx zo(eg<&rcFLj=`MJ4*h>Fk;8_Z>fsZ}u@m%>i5y&Nv|($3ZOD7--*IbXu9uO=Hh9cJ z%Y;`-mxGDn>A>LfroM$+Vk%D+-%>t&i{&Nd;F69b?%5Eu=XZ4SMOwdj@l>t!0~2aZ{7yoPEsUo$&AU3unOFA% z51A@?y74k)+~~2V^4s0EHz(I^#p?NPJUO2n)f1L%vcxCp^G%lB<5{6z6o8G<;$~dr z%f?e0kL>&nTNam+M;f=EF2WYZbL5d`!vEgxm2GwVL&hM0lXj`d(`EkdXe)a^+IFLS zbL_Y=^%KvUI&Gih>IV-QRIf|Rj_`)3v(A>OS?BaMaiC0C1GCO^cPShwv#MF=;@Yfp z+J`DvXUo=7*V~ZCa`3cFcwLiq;#u`mXPh-=+}NS@QzlNGc-DBzZJ!oGR^RjLtn;Qf zs>(fm%{NDVTe_4#ZkKnqY>TQtf;>A*6De?-ayyTg%sLlN4}7Gv&f9*UbxvBywxqMp zJJ)8NXY)19M&o+gm(=ST=5t4%IdLpZHErCKvqsC_MqTpKUN_SR`LL<^W0oD#nst7d zoT1a`4++GeAHYhza}?PjH%V1*LKG~|Iv@B(AS0c1E;}^qyy!~SBMshuS?8~tji+?h zxnd5qwVpiES+>=`Wu49MDbMIE+v0?*^G|;xk93ypa$MHAb^&>$v+Qd>3?At$JNV+P z^ZmcF9%8I5{f#~~mAK@^Fh_F-}$?gI|9^~>_n?@=oK*kxbo z-W%ihZ@9?GEt79l)dtLi?6`- zTF4`f=Mn#c0BHO7q#4-OFJnCkSnHR$CWW`LreeSvd*-PFPhgR8}j;#BgHPIkrD}q%rV+mUVugZfZ2z zBCt*PsOy;Wz-GAYLp-uiAs{etC%h84JQ5!iGb586tH~ig{#D8=!+HFxS?6!}$U3La zAdfWVJ@+8;G$%4abrkXv-BaQL$M@%Qzl1G|2r|B5# z8m6!nalIa4TR>pEOgletxvd69*v7OY{xrQIpn6WAjZyp^T!dj(O)$N|n;3j8=UjiT znNQ~ZbEP+^W_knbrMz=xuTXLfl%I?4HJ?&m*WlBngVm(TYm(ihcZQp~NpFmyW;oTP zcfzFCZ(!0JDc7_cDJ#pf&if$u^skUdnjvt~-Q-C)oOCzZZi3v$b3mnum)GkW&M-5v z+WTx}c6Kw*%(3=#n?8`=)yY{;#4CtWGtY!*r@+j|5dvwL^j~5|@<GmHTX2&5H+8@_%k)%1-a*{ zHl*X7W0YE=qUO5*=6i7i^X+W1?ri4Ma+vR1FrP&p(x|rybg<5Jq_pWn+jb38n3TBe zsrb~SS&l0=>7Dr`nX{JX2N!C%fTlmlJU;zYbv=Ka*n_HIit^B=epP4m%qu$lp`IKRpQQ}WT9 zI`C`x=uJPDs@{b1vpnm(`ZbgtPaf&4^Tr>NTWZ*D!^diR=H9b{%k1RoDB? ztV5F$#S(YXAVzoj8=?y=SYlyO5D^d+ENBo>(I{d8ja?)Lu|$oA*gK+PBZ}A%r6fUY zV2oX3?+O|V>dyOr=X~e9duM0!n>Cr=Z<)h)%RB9!bMJlky|G8|#mpiExQ+5_X48e) zd^Cez2rt93k;}&D1QFcxD`|{eER`mHNU=zp`Fx6}<%TU}JvHeu!<)j~+Q>KK-CSq>{df*Jd} z6q7XS!J4Rv#uJ)C zE{$Aw%;VVDI5jOEu$X*_`%P%_Cd63It)aaq5|gc=y(e-NcKBFgvI;wVET@o1&Lt+( z#UtmUKkZkr|3*%(V4{}@xSW5>g0stcL{&&Sv7A_>-2hv~avo7dIggORfauI}$oV>C z8%K;Z$^#3p+2fXg%?*u-VJD%d2JX#)7)0W!(idW;k0=PHxQR=_NWOoJd(FV-WS7SI1a z#Bez;Ax@Dd z|34y5O+Iw|*hy0+b33o?jbYoRh_2q1uoDz7u^C*9c_Rd!CGY?7f>@z+vs#wimpV!UgZM5 zTQ*u)6D=?q9Ogm`Bj`bOVzVEXLm1TC|9LV_8bV|CGupB-X%j}<{wQHIowU6S=jeeE8M0xZAqKNMqxyHZ5*% zQy$X5I;F*(|H*o!)8c*b_B|}+l16&M4osGwlxBDzwoKaoC`D*qYC9_^0+~|Q>n$nb znKG-gCU>Dr6oEYmRm3wCMs}u$-NqYDgZ3sSH<||Rje3_NSGf|EHes~wj}k_cRNHVu zFPEoPV;7Yek0dqW%wW|hpbzVXVk9YdQ3>c1&h#c^oaIbX2k6S$X(lNTh?1lvAhHi> z`=f->?9?_K^UGm4PlJOE?-|CM3v*7ejEybUOpCu80AWrhUOgW}rl3#Yyx=+K{`mtNkG=?PMwq467wyDU$YXq|a7yF9}T#L=_u3sKVA;3 z+Q%P#lpUC$9EDuD9MMWcL<3WCYO@)X$^n;`{WxD~2w#%g*u><}a_*pKa$t4ha{S0t zr1mJ4Lq|^`ALPIsRJa?yRhS71B+4Be!b2p-@U2k18oXQlQ~eJ1CMJiLQ;s1Q5R*Fr zLoPr)vB%&aZ;w*Hq8w|L%Ms$Z1_sD6Y-r1J^aL*-m&!40DCHP7)a1}|`c)+1?fwTsabIrXsNqj3G1*1G{nO%3JZz$YTGqtmoAo4S4j<->6O&9h z409B6ZWZ{FqQL0h z9L@PHps*%d>=6Q^x)B1Sx{=Pky&N;am%|*Lw5j#S&Cy#(RFtEAxg1fVLZ(rlE#C@L zIp&~vNJv!b=15d*Lib=fXS5#RWkxFjp7o{P|B`TZ{#RH#$RWcY+KdyfObKO7l?O)F zMDfEx4smY@jBG+VSe_Qo9u(|B8uhgPkC&s=uP8_7aycTu^2k>1S1QL`@bYNzE9DEC zP&v%6SPnVhe{K)bCdYr_SEX|30>98D$RW`l)2=w-3M4t9JmIn?w_ZHq>aa(`WfR&% zwq}N%oEC5X8^XlL#7JA1_@5Il$*He95QBPvdt#6 z5zDzYbva~hDsr&?|7s7)QC%)aWDlPYmfJ(+fIZ|kk=sMZKI|cK_~M7?f?~Pf*dmOM2?SRn9oJaV;F0q#q*FO+B6xC@u9g11s6EAdVVKz%F7 zI+51!oYkA7z)oS{u5uyyoXKi2be7aglA32iExh7Dpz2Wp!gEHSzg-GVBUCdo)cT!4 zQD5hfiB%tmTEEAGLQqo-O=qp9>7mxSJQyEC@*vjVN?ARReZ{rTClt$g0sBgGq5BI3 zDisLcB2W0l4KET1SBzx5n6=`*+%KZ;aTH!;jB5=P1Gw$*Jr92$64SSptV7#;u@12} z@sxeBK)n<>@lcNvOib8q;+qbb=|>NRDyBqmP^2qsTCG)*VA5^o0+o@q_TSWo&3^{4~E zTwduf&ACDS8kCI|B_@wYiLPi;$HbO`$+u(dPwJ&PVqy=uhK_c_u@An(HKZDJPa020Jeee2xhHFMnl8L2U|w$x+IHpUbV@o+zdAZeIx;954LKmA z^X&DC80;IY;B`q$y&$ji_v$Jk%nwn;a4urCrJZ?+-`HP_h!#fk2HKkeT4my zS6p}3H2sb{wnmd@w>Bff-9A^E z*Y$eN-{<+>s*yg>J==aw=h9)uewDSfZuL;8!scw+8`Ec z@-QssulPOd39rTP$zO(TLjIO)4ksPq^@Nss0V|Fsf5n63TC7JJIFd((jb?vExMGb3 zY|>IM!lM417wJ#<)1+lQfBtv;UuITFm|l;x+nT)4&0)v&@b^o@lupxsx5cZ}>WPs? zLYWDk*C$3A|Htbv*1SiIG_I+9me%{|GX#=dyf8koGVWiPw~dp86VXEg+JH z-PER~*Z68C-cE-}hy-HN!XE;}eZ)u$f1+<<-XCpWiam@v9cK|EjYk`cp+C~Fx%va^ zxon@^7-S<2-K$+nud(bs;Fds1^L3e@An}VF^194Vo}|31e?!c9dFmY`{p+khrKO(B z)pAOGOZNngK2t8+vGU6h1Z<5yjV_b#5EB%S`a%aF$UK5`}b*lLB9(dcog)N;1O z;7$lVY$cVwJWXGNxxYraV5IS?1HIj*WXC_JKGrbWpmZ#|}r$MMaiIGmz zzubrC^&cQc8jrOuNz)%z6C;gRj$RT3C5>z7wWMAJL7BIrCq2QSSfnLEcZZ-lmZjge z@{iZW_lC^`MIut|>~8h6JWU_pCr!WAmk~LQ_sx6(;mvtT%k#UiD6}irAT7TQ4MDFY zM%n~DU$6>-@>EsyIOSPlQF!??1G81cpA!{F_hDjQ^{2IsB!^DLxASvOoY|7*(vz8 zFf9UfX>S4`oT;E%F75{bt|vws0(=I4-;5Y(`H`E*DoRtRF72gW1)+E<%ATkbp|IXx zCHb%gp$>#ldX`oC&4LGoT7}bZE|g4mJ7JSRt#Y7LMxR;^m%~_ep-5v9upg{4pY=#H zKD(<)d~T2F9Q&1e6@=pHD0|LKgaR`nRL#h8OC18C8l+G8L_*1Gan&^t>INyWiz6bc zP=^p>IfOa@LhV6}G=#$cJ6=kRv^-A_YwK8X+WVDy6@=0|Np0;(D-jAa0~M-;@pA-( z>L-25CkqrZ*3jl*2xa3(G};+UTNUaEsqEzt>fkVbNT=yV$jrW6Bb}x8`SQl*&`u!CwDk#>K zD(Ep%*~=07kBvgV(rNnCUBGM#LK+su*z$--+Ju4hhUXN;A9~>!0#elSZ;*hiwN0lAr=8k&o@tp2#8uPLY9MmPmJXd z0snWOCoN+GA|RJZThbJvRr#i#(|~`6iJdIAPi@%>7l;VW=K-vYM!ybL(CMmYoD0Yr z%faGrF_gbDc9q7ftZ;6_EkoL-rqiTeB`a_u@O8NeEm#3F?g3>pZWTc`0LBF?s0deC zgo5L!Wwe}Q;X9kQ$XNJpC}!OMfMslvPMRXLw?wKl?)fH`&eki5#i_uzK`g}2=P-w8 zX@YjSh}C>9z{+TJUC1!PMwVeNr&uh<&knqmB;7U8ISsMi!`jcX6KPpHg$WL6iq)!Y zQqRf2cjaO|Up{886|u6}Ko+^6gXbaEtY%^%B56Lk*2L0sh=Q4OCYI80xDIH$1M87C z5j4V8vJ6vyI5V4I<4F=iOOfkl5h2U{nFvxDm;9u3%w(&fo5>o>A%d*(Z9Yv}94=%J z(k4P{vPV6WdUSx+MQCBn+%6(yS>2{DDlf*&%Fj#3OlL%JwZiQtf|lb&u^-DgAx0X} zYC=ZGnvG#S(r`FLJ)eA%Hc>U|RkD_*dQ5k7GIxyh` z?>X=^!@9U4QhmwN6_TE$jlRY^F&XT7scEw@L!d_3fh5wJyQh zB|}D;!J0I@mLYPt;@Xe^xxDFD%Af=K{7NPJ^CB*47bvkYlS&^=@s(k8(P(zb#P zdTXw47oDrc_KQT_H2gkdwkd+eW@Af9M(+8@uXy>Mh_2PvHwkQTuslugfuvtA6waK+ zTJ3=lp-EGMF1k-rNdn%MZWFx7C1_z=2dmA-Y_(}NP-(IGw{*i&2|8mAriQcCCd<=w zF6LHW-%ANdLxMXXfz10L6=}1>IYvJp9BITjtmL);~e8RMZyCzkw4qd&~oJGCYw_SQt-u0y#5W6H+?){%`_ z=D_qq^S4Ml23N$KwYttQx%x>a0b-BV({gZoEcBfcBW>KCBv>VVYyNK6F>oul6R?fm zQry7;u`x>$ZFoi2Mg3VJ?&!J+c~13h3q+Rlb(X%9B(Jml_Ez}*&G4ev*dJ*~1^an? zB2B3}wBVBxmh%wSoQ+}484XHFMClMT ztRico@GhQ+&LYNg5f$#c4>8g(YG1hToy15(ECf`a3X!H*txHavAVeoLU91+86V{=P z_1QW!77N)a9Z@P)mYpyIlgP+&@l}X*hKZ%L_$tIQKPL^bdO)o8S&y_?t2G&`4`&TO z4c58@dllG=Z)w(mwP|Bmo0?dxj7AR!v2%C?I2RUdjV&zLARCX zoy~}m=5D{QDCI7I-_Gc)8Lc&f$^5<$y+OhSd#NO4Dv#9=ESnr;OEL)b5(F#a8=Da# zm_`t61hSD~S`MFo4^ha5Flmevh%+GEce5nn+lFC<7zAhN^{#WOS(who^(5(+*&DQ5EjBq z8j^>Y0_u(`4@TRF6f(y36Xk%qqtNKfB&mH^N=%QKm#FMI%Do(sXAi`C__Wj`jr}d; zi8jiy)82>Ft7HrOM1vkfFKo(m3}&(d>k(r{c0h@r|_a!*4c<8<3Q!cBu?nuyYJMCt&@mi1oAe!@NI;#$EHQ zCz$jn)@W!;Ob)9`f7B{5Ih0xZDJ7}}KkAae8Zk8#DI2eguuToyl$i7<^`t+qCzwog zsM^rB`Z>0(elEf!^y3YTG)NS=mtS5S|zKJ?@jJAOsxR$pi4NPS$y{@dewwOqaH0#wJRf;{0d1-e| zO&GpPL*A>BWV4T1k2El~OKDr$uN0GO?Q9{OG_ULSa2?2oov4uJS`2HR zutRDVV_metkd4h~BHBiNR-Sq$^q)(O@J z^$K^E3s$=3Q69182^*poqg1e$AQ&cZC2Jmc#cDFga=B%gBpc?4k;cUEX}H}aVx-{# z7?Yij6Rb7X(KXLqK?v-S%R!QsHeayj345KHb)>Ewdo10|=!68Wl6NO_EQfW@4&#Y5 zEU{zQ*CY+W{vP%!7>K1#4lO2J4_`Ycn$sB*T>Btv<~pbHCfdB-3(A z;ZZ@Pkf^Zi?;$FXHYr-|WBqWE!aYF>>#Asj(`=^F!t+)k#*|2lh_BMxx{Bp^j_RFYAJTjluFV8WE6@M5nP5`r zbf`5$O4n6?2{yY0i?b^*##;z@SXV_S-qmJaSypr*;>n=ye2z(>>nbl#)7KI4)<2OP zlTOo@U&Q@`^@x#{(@+>^%ZQPN&Ax@EFd3C}LE5A}N3crL9_s6_%_%J|n7=$pHmQXP zCWQ6ZDDaBaZu|i2XoIF@ON?Y+Lh+-i`z6W7?}EYT@!S0g#eKnL<@uG`1!4W=(BiQE zx)g%_4Nn>!8LoI4VjXykpQ6Q9jX<@NLamvEqSa7>04Z0DA4JAHM7m!!F*KA!hrZ(V zmqb@A6Ji#?nfmSTojBbO6HuxYDqKMIM18M76`yKqr zNle6z)_P`-7;}5LUDxjruHm%XO0E%Ov{Aq|#DcA1XQ_pWh0z@j!2;(cVx;kq)72Od zT?BI)*W4P5JWM_WBMrU6R<(p0Rycgp!7Dz`xwrV$6Nb`=ig5Uw4%)h@I#6yF+%H^OKhN z>b7(mzNS7W{UwR(x6RqEQ}}_=?uVjNzlNSIu9uc}=C~el8v64G-d?9vFs>RGnd2Cfrfb0s<>GJO+ae_`9&HzN%5Ypoaaav!n2r$_bX8TNgI zJwhAZ^+v$*I}y7(vQd8LBzg4oBzMoJQ9Z091)KX}gdsv|y-5M9LcRN&;Fae@*uW&2 z_f<1&*Ce?Dk8PFIn~>z6T9c+{KN+<}R=pT+04%8oAG#kA8`FY4hBmsBBb>-*Btpfv zU%^4Q#&ABBSQn(1rZqk=46|}C6IAHpNvtQ|ibeG@OzO!sFwo??te#=c%f^oeUN&A1 zUci@5DU3fa_cG~EY4EJ|@U58j<7I-4+%idetN<@aO?46?@aeJx=&`~dzZJ7`F9Vi8 zVRf2LTN@65h1F_mh4(X5O_|~$}w#REMt2@~0p}clH+t#WM zyqs+_4E5^9vYzP2uTgg}>pAB96|sTh{1u_g>LIY>aq`W!EC;4##6$*QiJD#SVm0r{Owo3>TsRkT0NwTqF|%s+uKUHv<;ZI{T#PRyzS>m z)y0z}ILJ5KvK*L}2}ZwKe?I-H#oy{puq>*Fgrx!e(iZ9&Cj7}YmUKiPm$BXw>{|~MY+Ly@Ov{0388O$(=h%05y?l

8#h+Y!qKN!=&E# zR`2`r{`xA$SaSRRj3sx!A@vwb?s|i<1mDCEOHi({B*PGM?mme1@Lg8Vuw?Z^Np22o z{pe^UB3(X#9xsW?5)r=Tq(h>p2S1b3xDUy zj+pTG0PN*uf<8Ku^_T!l>v@@=cQ0l=CdJZvUIsM(1Y*Xd{X9`>J&of>ypWXvOw-FD z$HL!v@|1cyE^`l7c^NTT@^$$?PpDbFq}^>8TUsVql3dmfzY>0T$ghH3`a_cZYk9~) zfbtukrS&|w07}ziss;0$AuR<%+ZPxs)?ZwX^?;q5x0SpupZK~Gqnh`(m5rJB8awE? zEaeaWsvqyq{Y$_Y6Pw~wA{+FLPl+7RZ5akV3YO%$+?p1bBmTG^i6yzlY2jK?J--&9 zH0|3}+PWSADTcNe`Sk_EMOLKgVQILQV$kD_c#&Qg{A`0itYG>6aLn z7g%*%k>nmboS4(?X962(n9;dkz~}BDmeJVQTzDw4#A*57H^PJ#%=&XW2b=xtIP1@8 z<-HU$xfS#_Im%svCDTPlKvnu!PrE_8?z+n!Lx%5~1JrKxo`d$@x_;}ewW!OU1NOqo zW5mFrdk+~re83)3BUjH>#~my0?mzNS!8-KWzP|tVeHylJs7GgGcNwtHfUzS+?K5`# zn0h^B+`-PR!ZG|lR>$A&G9r7tsA}&dH+6SRZ|{&r+z9k2pDM)Ybf4yEvXPWwq@Iqc zFEYK{+3onEVCZ9CsqK9!mZakpvz}OQeH=JifD!9u()PUd74tp-dEdBSb_y2imN7`< z2F1D1*6z|@pf|q{nQA-1lEmrJeK8BToS4(6w@Z=((Oy1I-_<5b&OlxH7@aE|46K7f zPUjB9H5@ZKHw{bHIh(Ma(Tc5kC}5xk%k73`Fg{M}_slN>20AyjG08o$fSA#_Gmc7f z_wP*1XxEv5UYT z9jdt%5WChHaIJd18k}gav}u07H2vLaC9d^bqGz8Gqse;G$Xx3TGyh7(*vAa-D`01z z?>!M)Iy+4#UT4_(0Xz3dYdb?Ry6ws|oihM|MH9BuY5LpC;97RKf^?d8|2r_ajqpc0 zEiRj!VMeFL6kdZy{jdx?29$^t5SV z9*0wYPmFZhv;cdNr~i@IzS4@(a*U@mbR5^ojjiy>9mP@6s(!q`TSf5JA)mY z{dX|CY7LF5MyAEKo2SLiN5uxNIw>vo#=B)p(d4IkX+{*x6*Qvg$Uz^~Qrr8|dd1%O zMIOP}6S3W9rNus50n;*K-S8r4!Pp0{!M?G!tjkPdbeit|9!xTZ^+=~_ug`#KKy(^Q z9q?=JVRTx&W=X(Ez2YR@G9boV3~v37|Yok(=ZIx(8qvPu)vdFDp< zX*cWxQz!Nnupw={Ct^=vY1c5yFeC(gFx5?x;a^%?g}m=Hz3UTCI8LYO8%KM>3G}u| z4qF|gjT5IYK0aVhf3QoyjLz+Zq0>9C;!)9x8p#8v@f;(KM1nbiVMZg7{E0iQRr)z-~Ve7=Bh}4BSEc zQyRaG_9;et4Y8vTP3oU(8KZtm+wS@W+O8r-IxW`X9rVBGN{n<`q`n1f?jHKkPlq1m z?lBYY(I74GsT$4^I;>M16RIW?9g3NBnAny?ikapfowXZ{5X17`SHOm@vhIGHtbTjxrUh2osNKsCu`fp>ApuJqU=n}=|izmvz3}NNt}M< zGGK@d@-aHs70Jq@g3-C78Uto@Zqdwu8J*wgqYQI8f1F&GQOoK4y|ozG@91Tn&OiQd zM31G!jMmW(UC1Y^_uwgL`z$e|^Yfnw(ZgtM3*F+=+!gdW<_??mihZb^)^yom<4QL$E(dQNv5og_V;5e(7GXfc0}TZuU>=I?O^F{9NL zdhDZ^)9MP2i7S9sS8z;R0koRmFsIf0j)_}HJ#mHZFdsfn=f$ku?Vi(=WZ2V~7g=&4EqC&hWRm9CK#S`fca-!;HxgQ0=QzwY zxx8RnA5qVeibmIbBitxn9=!-z>BqYI)5Bo!!e`PbtXNetT>%t z(l<%2?Lf@v{9kWLk_BAYI-URPUx4}CgS6{W8hbza$KS#hscs-(enVR8!3Ov=cNu-! zzC&HP%iIc=*+yF6Q#Dk~hd1NC6gx-NaYUP*kI|AnlUvQKFKRdJ<7w|JU`bn9=!tuFNo}^EY3LglNOY==>As0yDiBonMY<*M5!2kvPro_ap3mnEFJl ztRS=0GdjNvyZkR*P0Z;0(jtx--bBpk{F0Y2RcEAiS|bW{D<5x@U-VPlf%u-7(ORFc zO2>844`^)*TjA5(wfY|fumiSe^7xLU(OqyYPPT#XE@n=WYi7qzRCO%Tt8R$e3H5X-l0QA0j=CqAP899sE1~&j-+z}CK zD{1RA&OsufjL`Xm)BNVh4s<8fx%>#dZsPQzaHGr7r+l1#1a9P*(VE;0b6OLfW0L4V zYoc>Z5*=twZiYFniOw-ebW%?e-OT%x6{j`P&AgtNBs$QV=w_ZzOcEVvjWW=qe7syS z=o_Er?!nz!>|Zx`kNe;r+0&v`Lui-DV`5LJnnd*2u`ybbt#Cp^{o^6Iw)J5v?8##S zb}W*+_|CCoiHUz4c#~oK1nflI?2&qt_Y}f)oA@#&RCLJz3XSDjqBxG&D#6Li*{V7{Ut1m#0T2Fii<@v|IOOhkhKQdbD!3Ov= z_Ze=({<7R>9ul9)_F;F!PY`X~e4$)*OxpBO`{roL`sg9EtNK6sSeHv>_9gtJO&{Wy z%CI44JrPUa(514KDOT(}k;`ZHp&0!Ue)*?+kRo~$Bb}x@ydE&pY4N@DGR)|-coAkK zwl`~ZTI~OufRV;VAkNXg^BH*|P0Tmn1e=K^uYCLF8)?O|%{O4W`6l1K`9_-ceDh5( z*?h|{2%BYvE4f+L5=Q-G{7KuU@6X0kS$)Cjw28Wvdd+-+Zz<`pb-6D*CcdERMXRd8 z9Jg1@i6ceTM52GbGe%2%;W6Hfuen|)D;#s|h)4FSR+P=hOHx0Dz zpq)0-F!(ZPjRDgvPRp)ZhOL%*&3%Czti8*9;jiKgeY9)%!XVmU$yc$}tBxl6-jEnA z@dcc#)pOdN$)n_fB_DZT0ecVmQ_9{OLQL$w@dLsdqfuqUwli8;Nz4%h|6 zjL!8qEyJA7oeW!AJ*RUkejYHR^L279_UCl|tla}I&_@E^!5UNkB*3smq?*s5(^dkQJ}ICAN9hc|MHF6|l?ac~8V}hpBk=pA4H9u&c1n!5zcmmG>&f+d)s_W#X?Q0*oL=I!%u}7o**> z2I(|i7qbe#Q%5>2K7^6(8G>|L9KT+`NTu~)pF8ND_fz~^E z#Y+&)q#o|_6)*d~WlVH?Ra#n)`WCF2cj)$edwaRBtx43dxS^N*)I!yGj?a&Fjs2j? zb~`^A7^5ZL;WzXilPg;v+j(CB`(ztpp9~}>apIFL4cjKd9?$v!Xr70>bk`!piM~?L zX}*{8h_1xs9hFCPW!bfBg?iVnMeLL71NO=FSPmYKnDsI-r?=h2G2|Pg<<1T3C5h8= z=f*LkHJ=#fwB{DaB)5Rp+~U}0J1eI7#4x8dw>T!b1+?aocQF^m$7#(Y?`~=sat3IP z6QB4_N{nqO^_qEy?!LGGt~_?&K3(=Z7FCCcRnqj%?PEWvI+y4_X2hsx5p^-YPj?qN z)IPTMz5@1-GrT8avhndk!LTy|cK3X1yR~5E9at61JvrYDaat_cuDiBXYYHtEbj)e7 zpkqd>1r2jrt?8Ip6SP{>F|j6SwV+{6=dalfWmhRLPUn|g<2QRSYapFp)DPbJ9P1gK zUxxGfbC5~!aT*rJQO5bivbH!v{`aqlEh4S;S6)s``T?zNp<8^Kd4g`fx3^bK$8iF; z=?3V~Lz}8`Vu2*r_tp=O&j*&PU$EeBY~D((|!AEf4ccDwCt4btMiFK%dV-cVzO%rTIZN6 z;r;kHt+C;Y0mNj!30mXC7uy?#m;hSi#F|}Oz+MronRnHBWLwt>WgZSy8Ect>t~9O+fe zG$YuiJ+nSg(Y&J_t>5MxX&Y$q1RI;`2|~BS_@);HT6XWY`cT>;JK#^~ixHW(LS~YW z)3Vy|J9kFsx~!WWNOL;3(;u?~X-;d5@xx~lV?b++aqP3571Ow4nA4gu9FvRzT0O!J zt~ssWc5uyU@tE937pWLdi^t^n20`^6p~YiFxAO6FxjUHq#TCSi)_SlDKFz#{TklDE zw!sa)0sXWSc+uD-_dYhsnjKd>C&_)#w>j$jU+P7EgAX%0d~)w^%j1gdi`WMPh_NSP zMf8m0ia9IOwx54P%=!Rk`y@Xg#@rm%ETrL0SK~e>XM!0m_k7(uoIVuZ;@;u(`7<-` zNSu~f0h@S~_e4zQ+GDyJ zc2vNoF1NOto6TcB!tNJxupbH`joq)m28=Xzzhr)*QQv9oe#tz>Fw)rl+9P13)24rQ z0CpgGA)PioiY(F=@eT4CjWx^Q>_nu|hS_>T%dtjV_>1f)o6%gm*lwDxW3Zdnv=EPX z4E_hNL0Ylm8lBZU&F|YWN`x2GE8c!JuKOOI4tj{#W2@5QDQ~olEqpL7p0T#IRa#Fl z7N;&R?N9nu71%Wn#J5~y&!fXN_P(TLOs+9{LAb`~1-!->U12oyN^a!aj|{}w5VsHq za5;lGrkM#Zmzf^>U)40pO=*m&cNlP| zhP2j$Zt-d63H+6@4)&`Tu`A&2UU(O5mF8pEZdnfxcu%Y+cE?+S)E72=AYiq#tnFU}^S;v*6AM|#D(3XyI~>Eo0;8`x zBVbN{y)s}%=Z0^QVNT~}!4AAe;&kqZrvqkmexK_z%xNAhxLWv2oX$UiIenYo5i?rt zwb4n$#CD+7c92^>-bPnT{1HR$s({wj65msl(b|@8TWW51?!;r_l}Ep^-EoI*K)6G9 zKw3QShUWL;s?JJ_6VGXmme~Cvv&~(?Hu{*!J9O-e*u+zau_t2F#_(<&%ZOc%1Nw4g zo_#1rpF*6O+XFhBK#VjFxMCdpUMuM|-3<}b?y?z8%;p7(VP1fzDAM$Ze(aC5JW-Kh zMyJIqR))KAq!r8V#sSm2aq@jTd`@&gn%{mmPB6I}cNvZg`%(Bm-^{ylEn(C}=ug^S zctLhI&S<>QM)fH5n%kY{nmd-;9e3lxdx@*|=bUii*YU`%I+N&vZ(}sE-Aoo=T`hQU`FTbFl)4HIGsOh$AB4~pN;uI!_LZ!)A@&R-BB+RGdlm5dSHu) z8J(Bkg_`y%F{5?&Y$f!7kJEb2@Cn`RLY%)PNkHqF!zZ3+Jvn~}T4O(S%eL$rhtHDa zdi6`}%aX=HvLv}_G3yzPJ=i3DxBaN7XT^Orpw8jO`O}ajP=QChf zpU#BeX#7wb7~;%e^%fc(i%l^8B(=d?DL&9W7%%O}}|1wtCfRj0BrK9-}2Y^2odD z3mA|1u#acGFURmktNXntViJ4s3RI0fD3cHT8FPZ4Wqknhz7c!=53%POsTOFtGw*T6 zX}L4+Cp(;8jyZ{AM(28*m|;%mP8OfpU9OQhom(NkWth?Vx>XtGbpEVe0%o+vnKmD2 ze@<(hX|s};#2L`}C42Y^I-?OsAm>EZGa4}kn9i*vz9{WFlZwtm{(*JT?)zWKSN4jMYD0CqMA9;^G6? zYVlzKTX3-VL=3)AyzOqo4i4DjVb=Bl!Mtzi0{yocN6hJNdDx`8U`gWi38Mq%w4B`V zdPeKX4PRTxi4M?ua>Fq>(IJ?e+;GfjJ-K0+(|U@-F*(Hnnm%!vvgb7Y;|yZzAISdl zm;>j^8Lb%S%EUk`#uI57Ett)56cZXJ2Yrr{(c(vl&AhIaYdy|!SP!(;gI(}x?nm5W z#ilH@Ub239UHquOc8vl&PIB$x&G+A{PDygt9n%~wi8HU8t)JA6a@U@~9eDOd?7CBl zu_t2l7IFvP$^^{Kt|w-F0P?=^t8VZk-@_nH-|EE}tbQi6_>(>Ll+of(jyWy<oQcHpnYJsaPF zH#&FK^sobOwChau=h)mm!w$UBIny`lReCe+*a_n&O*v-r*pqt8eXs&v0V9sn0e?4O zsd_5jAoOMSPT~BXdt-+Ff@(yjBorcO!XRV$)WZnBji4s7PV{s`232`#gcnTDYo9_1#BaLqU zAlEO)YQdMZjqCN?p%lC032aR0wjz$RD9!%5ZOnQl7#DL{f3s1gZeeMEipf9Gb>+YQ z>QLuJG2@T4n~81N#xR|{f<{r@Y&TS>SGUkG<3;pQJBR9Z9Z*NaTvvj1D-i2uvMIK) zVWtDYdhS4s`m5leC(%9CIdQv6oU<+d_C^=jM{DSmIj2Iv zLyLzY?eimhGN@H|Q3ho`w$4Crm_a=UW(}hSenTfP^cEg7-BJ2Phuv`5#ddkqxnOm8 z{|+z4dTfKX&`ZOZQcV11i;szsPSg9~$NpOpq}jHc`D_WcPHEeP2#nnyBt{y?`uD=` zd3;HXG=Irp$Bl@|FB$B(k;~Hp_I_!9Qh&2|L%q%3W!t)oh*3`Ptd=6Cx_aMqW&Nq| z;QeS)ubauCSWm-L-b%hBzk>nGCIuum@f@tdvLA0cF7uqsv}>2goy~$XiQ9=~5fkf< z!}l7DjE4=&4y2UOj#|d#@%aEOFGpfP%5y%LJ>y+aM?uwF>rhd(7F$>{kZ#XSLvSHJ4_gBZ(D>On5&g z+|C$jyftZ&ybfEKa2g(lcu{jHG19=aYr!fod)UNdC!ai4HED|q;rC#?x$O%0?_t64 z0__XvPt7&yRg>f=a6!5{uYyU%xFDaXqeM_2*@!x1O!?S z0Xg>B&Wh>5AH$s1LqLwnAt2EC#}G+=UZboyouBtXnx?-bX0&4W{4rpl^GmUbf9o(} zM(3B|^+U4;5i>eJ{{hs~2!oqzr1OvLCbrRfiR-2B0k|$E*79+>7Mq~Y97oLQ^}fK5 zgTU+L~x!Erv zoSaQE66{gxYf-<+p!{isde&zRGib;z^}@D%*5el$0Ylx=>?hInmFy?mx8K3*;ZTdw&bzesdTlTV+TtZakS2_l`kZ&Lt{E7x1LfDN?%L}MsdsjQy1LAhdDuY#mU+R%}_T=;~-%J9Kf zSeGl{DQU<(0__WBZ`D%nk*X*^7vH-%ds5fi7-r@AI}j*q?Z8&1Zb6JRp03*uhPB~D8hv8e`BKcW_p9L)8}S;Xv4`?24CA@PNaI%$ zWVl1q!V779zl?|Hml~!t`CP4S1OJ^jKni$4>fv01(Q1k91@V65htKgVI}3=BcDV&Z zf7?L@v{7%cwv@>gF14Ho>WaKnaK@8-f8%)WZ;YVDW&F&8+BYv*LgtU;ON(pghQW6f z8E6<7)&@tjR^4WqUu2{9XXQ};Y?~tKLLqonTpb4T^&)9LI_XDG<2qN+16=1ez(lyr_&Jfuc&9v!g6ADo3THZyUK`( z(HaK2&O*I9tX$;%(rhaRN2CF-8dZ#E#lWj#%5&?DD}k<``C!~>s)=~ zvc!~k^@T0GWNnJU{?IS}-}gYnl!jNsgL^$kj5KEoTU%I?Sp%Me(JzLR~Ls} z64LmUfprlg?`40a%^Y*eF%O%n<~gQjtEXzloB3rn;MY|(V;4fbxu^8kdNpIhloa+V zSM!W=FP#-4iK{tmY-MU5oN2y9%`>3pc2M&n6qhu-v@^WagOHX(^*x~aZ&;5sRbP)R zB_1xSmmg|XRg59Vek@RYOiTmB$5eBjd3cQRq?VasmZ^Cb+p=#{vt2{gJlNE%{Z&?T z??cA^cGB_K@0fDJ2I~TNusC7ukzoSzYet*eNZan`&t&uM{BOuc z&oBkgBcG`Q+?$1o3|bm&0)1(!<0rZ5@eq#$9n3d(%Z0Jow+po!Rfvm z5kwcVEorN_w6s65tG}?!X`K+O?QFsfS^}`0sLN;x#wE6UhLSta!hg>p#GGff-Mz$| zXT_EpruLfU{wP+ukJzCW8c)MUqeR{-teOV%lczKrg`g6u?G#){#tL1zPNm0R0v{jjdMZ}b8AG? zAx{hgvQ=_6V3ubitt8c+1Jz#>sa|QQ{&lGSOjDK85Mw@OFBXVM0~6Kj%)-lw)eUIY z7WL|uM=Jdp>S3mmwUzP##JsJlZ@FRGw)N_hNn2qw)mH@?CkW&RZsXf*uD;E~oYUPj z+(46%Cc%Y`@qGb0`MF_ABM;)gzT;1tI_L@4mbNkGcb`;mo0|@-p31w>XxWkv8G#iK!szn&ZF-bTOkAfea; z5|UzSwMbz7;F22skGEE;5<(shuIP~q$#>N>ueUm(Zo z7G1Fpz^+E$TZxf|E8zdWs3naZ7RlVhKy2*-7pX$Z%}TFJ5I4IGP+ z*o!|2p~`V|>&iI}2Tfuf*Byoyl35=%j+N$|>*u|Q$^7f*y^Q18#FXRN#<60RI1YPE z;=~0!@hnVBa-U14`?U`-97f;7Eo}dURw|lGmcX3VU#{kY~rQf=~H=X_#=ASm-NA_BUAQ zGfF`kqu`(LsT+uqHVfJ8RV}o=SxB);90v>Oq7XlGV{VmMs47fH+(OI3LM}E(6_|!g zW#&*Ci{WCDY=`hF1BNu034NvzlWBdQDNytLu+v7`%(jg6)I`h7M2b}s&di~b9g<0w zEq6~XH%HjHjLlJt8|167WUa*}u?~BsZNNwXfn+*h`j|P8DFst=V1G}CxMCGJKHkl7 zQg59(97?8{51oY#zw9_! zSnnt6QdB)ohWY4{iBOZxM@i#o*!}QYog6#Ovjx77$8ut|Z~{?XjQQ%>u^SLTd{IN1 z$F_XjmSD3=`%J20 z={pn#cy?wnOwcnZ(yF7D#45w>AM!mP5mOq z5V#bxw#vhu#JHkh-!dam|FOLc^%eA|zGD5UuWV($qIzk)Utr>w6mY&-qI~QZlR}ht zCx}9UL($fs$B<~B&!Mnwk@-awqTDaSeuv-wQNKX3Jj+zO8}&{a@!%NP_61_3aqQxf z5C=%pSA2}dm~T*cTeXwzE|y>(fAo506D+zkCdJrtV%iVJvf9?#vTwue8iLhfLr86F z{V9gc62+`PwKrmo+S_86+8Y}!8XE@4bt~Ju*?L`5-~^hzfH~tt^!6#V9PRjGQYaUw zK0o9MsRgJuGW#*cMr7mZgnC93`i@i%FM;Bx(8+Malm_+(D8z-1FyB698yFe01KzE7 znr(fjCaZ^~e6PKDjk}e`3BxPHW+Z90tv=s)0T0#Z15>#JR{IRGj2GpVSjIE3o|_YE z)q*3+?Yh=GBC|$vU79}E9_olrUiw&?k=-fJyXvDv?qey;BC`}7b{KuzmY2Y#ro$ST zn~6)S3(hbXoI#A`IBoYWG(U|PX-F%Yu(TLsz9$%C_~j72hGRF%wv_cpn&H_Oq7sT_ zBZoY(Ew5*qx9ci~Nv;kDyM|yru|Fvod8s@^I6FM4x2{=_q%~w+=hg^k@G{j$Nzhdv zZZu`84_ocNm!+!5uFi8)gX&2`&DfIcE;7R$q)p9tmSet~T~co_>#16hQB*C~Rx#Ww zQY@<1b4ydzmeRKMs?xTo(5x?&9G+nwO z^zyOr;qNpSjq}ihVDyVvk2DxOGo&-pCXhLY8WYQJHKt;f1!yNGPM^n%G6#+sab9kE-lA= zlI8Vod?09yG$V!gC)%mSBulj8ZB=7SO=EhEN*c46po_1Gnca0{i(JtH{&03%(>_a= zzG74jU;%$W?CT47(#%L3X$p6m8mK||7oQQ1YubC)g0+(4{-|2OGg&q=^AeuGac#7x z>Iwd~aHGkCSoxkR8>15hZQoNRO(uO$)v>!Di_)*s5b&08Ly9yW)A&s|8cCY{Ro?~y zOaaxm0fQN1tZo=FUbmG>(L6gTm{F1{+_G-$h(Y`5KCxW$Q2J%J=z#{?-D6!8uYe97 zCV!;U^oCvFj^ZZZnKa$8+h$e|U)`|um$@CWR`RUb=-9xs8#3BKb&d9`kk@QeY?5&-0O{6gAgT10qEYvbsn?td&w| z_&+{KA1rbAPmnG_3pc@Msfhv*f0fLM^$eUrw+} zQUputQf^8nNaB{97Um>w$#Cn{?}@9~ra=%SgUoD7!$jA^Y}=AS(!{oy7_cqSwS;Zo zLL*I6)-Gl}HQQn{n_`uOGZU#~CuWjmi_~bJ)=kuU~(T9G`ki_TFtdR40m!l*U_xUxeg0XT?gPg zD&JS&6e}{$dIGIn0hf={%AsNvILw~bGqvI&dLP4LZe*33SHecVPs^e)j7X|83#|#) z$F!{aAH+!0eQRuN>J$uPQ=$&B3Je};PvWZkzL;^BjDYh%U-7+ufe^eK>YE?y_p10t zqVPNW;)4xXy08sdW;rk|6RZMzF?T)5o#a{PE}R2aNVp3px)UF7(JU7$5P8F^ zUvfX8noqMegKz1n0@{Mxk&p^gCNYFQv4`BFPwc@cg0Y+_u->Ktk`Cp7rAj)mwB9{8 zW4ieUG1Ba};i*#W;X~n#Hlj)M)e9gyb=R&*!RH1<-tlSRh_+{yayGDK?Y$Hst~ z1Lp*0FAe7eRK5L;Wm!guIkX(#_+Nu!71%Q;Q||tc+{qH(oh*77-MI^Ab~7i7p0IT% zdpyK>hhEB-FPYzcnLQ^~;&+`Oz&;RkM+&8W_oeyWm&90Zf{rQ0?)f`>%%(P^&BtD1 zy%Oy4QtaXVFrCrZji>aK=F{UFEN4A=8hnH0<~z-JktwVn*dR^*YHE!?d^L;#CS%ok z23Au`%0olYh1DaCO~q3%LA{f0NrM;gr$#eB; z)|-v5hKF%oHEFYuGcG`nFsNiHi2KwMSg;&bQz$Ib&;bUOle~7)8 zfW5cj8ZQQx8|Il9^9<8+VEAu?Vinl4F`(T2vV07Lv*6hncrGk(d<@JAQPmwj-1ko$ ziuQ?o41{NNlb@IXG6v3v0IxM01K-#f_{QpKxe01vbU=5|%i)X<xfDOQ0!^KIp>ce!telZ=^fj|_3veS6~oxg)8wW@G4Qv*784_Feqz_~w&H8< zPo#NWf76$@ePS)lad%~Zr14XOzy?@V=t?s{3(^y8_JU|Wt2D1sGs*Z9BQK>5`ntTzKQWg>`AVt3M&pIN8m2r~a1{6B{bY3%sIRe64YEaVAVGfbDq@~4>Di0>nditB7YSe!2NR@@L2d)@Xx(* zEyR>~LscNK)Y673tD+n#^9@z;LD^7c8>)ciz_d)T3hbGGDtFri|8(x64OQnZ+EDfV z>F5TAJLA+4XXkLm+89j@9wJm14utv9YZbID1b732?n0qt-CKv)D|@VUGfYq|r{DP= ztN5Mlv8wO`OY7b78T@o#Vx$=>{efwTf!*N~51)wZj%7X4xGt{mdDh#ikFQ`o(!6d> z7h>L@i3~Y^SYV5V$gxOhB%1J2CN2?L&5yI>Yr21XYCr~pZcR5 z6`aC-7Wz&KZHgzTndn{+PAy%0^YFYVv zr<}j=v`%s-uhp|{ncpgVpQ0EGHGg(S*z1X)E{l_%ZH+xG=jNyfK3TN)Tu7E#uQJQ3 z(LU(2fESJD@hyL@(de9!YjorC$)B>k21daA)ejn}MzQYFJ%EkLGRw(conn>Qqehj# zcgy(;FWt^G+9~+0MFM5-OI#LHaewq*HQI^n_3T9USkCE>znoX5Kk{;3)|YyfSyqke zrdOZ9F~*4S(Rf8z76Q`M=CYQ3wDAfwK{y_OZ8r&M!b0ORZ$pgbUM5&&_NYHeLtzkRY8si3E+<9Fj=TxRbG`<$NdocFTy#?;UIhF<8HK zEUQKvP`A)f&hebEKyi&e)3T2?VkY(6g<$y$vZ5M&#x(j2F_xP~6>F_VmB07P`J0s; zs>(FFYw%Hvt?C=Iz#g_*N;JBwX>?a(Ps`KvHP~&t1;j|BUQc-mH8IkrWo=to4ApW! zv@i4zQeZx+ywwE1^(pGm|KPVZ&>mvzfJ4cOYI&$>d8lDpZdz8XGJEt}`}|g-$&*A zMKSmuUTfg?!Iz`?t;ArN-^T0>+}@iQds?2RvMAb7{0)9fnk)~5rd!W4bd?l7E@wFk za?bLA5aeQ(5#(e7S;F!FV|jqE;^p}66r6xGFlc$8)~ldpf4{0uc|Q#tBR%QsMb`;K zO`v^o{I#L^Q1hzzPH{x?7GV#xyoD3do^1@Xaxbf>QG5HVa<>DyYlE(wyXeKq&Rz84 zWSsZVr^ut@f|ttBPt(7Ki%>{>s%$f^F6{0WjMrt_`9706~8xn8Xb{>5lb? zzH;>vt7qjZ=>DZxyH7BS7N^FCG+t7GiH1L_Nt&;L^yAL*8p!G$5CndT!x}e9OQ&%U zpaXb8j1!DBd0LJ2dKqRx#p^wZ8TKb1vL0!dN3e*$>%rf>f`C`0p@)4Shx(Wq8*-|# zRbDT58?deDYBiz>jSyi7dWy9saJkR+M*G5N!DmO~`eL8cLlPE9eD==fN!Y96z~$P0 ztQVO0?4905*bC)e)>@xc?sf`3>)eGi$BA>dFzmAWTS&qKi`hGY=ZEdt%a|f+qVw~% zUXRb$tWN<{C(|IvIxZ-agq*LD8350Rgz_$1;^iw<*4AhhejzdTlcukqh!;AZA(+!? z`tnTpM0aAO@tUBE;X5;kk%p4RcWxlYez4zrCEinEzC#*&w(sHn7nsb+HAtIp&o6EJ z;*R0?JZZ|vBmY6RHhcJaZHyzOA!|qM?M`8Tq%pQu1&p-oOzN4VKp*N{su!0D-^T^n z)ZgcuZyV2&uu1(usl|74Mx z6~kJ^(BU1*y{xtVuG|eM_xJF$MCR`+f+xGbM^8(*b4N$a9EzTMaet4_(sVVUL{RwK zPq0(r=k-PB)!&%Ef5UoSu7a*8#i|~MUx-Bbkj6`)4hTL*nwUSLA(%Xlp}uWC;q^Yg z5&m?f^oH@EwE3s`b_sSJ>v?}t*6W(kw%0X0U(@R)Vsh4|*GssE_5~L1U5Jr}A7g6X z)$#yo^JCM2%dQTfI&l8+Eq-irsLxI}pEaHp!_-P*NUI(Zaz93{OA4!kAMXnX6q|h? z;rdi`kMEM zIjzF)K+OATcMR-WO^h_!;l8dvkV6{RM2z-l)E#^E$xx3pmUrmOpGPMxe2SE%*VS>f zEiuv<3;ojcYx6PEE~C`*@-%(%5RAR4#7OfRHFMdY%c)MI@;d)+7q(TOoh$l-&uUxe zl^A($<(#@>B~p}0tzhD-sHkFC126Zo z*7~t>w`;i{w+)L^=MKN+$m@sqT*bbBK3 z+VxcQGnChLx&!90^jW+gQfc_<0l@BMf245@1gJGl#7Mi`?9b&?W2?N*KfaH{*fTkF zEMYyUk;8aaY=L3Qb1QweAFf@%Z$#$tEr0v*Cuo|chS&>8e#E3{Zh7pLABkzgFx;dq zz7MAu^1~-hbG;2QFZZ(6`mAy{IQXn{H$B8&=WcO`z1X7C*GYz#$!8849=}g!Qd@Q5 zeH00l`uW>X_6;HSu4@8_pvZHZ$lB^)!Q{PaQq`MSJuB~qFz!EH;j{|BxU}Aer@)W5 zA?CFF5)Ic@{8bvE<%uu;LSo=S{m#&3UB_*p~g6e_DTn)nUCUe%z`T!uotc#zEoBa-Y34 z#98->`Q>p|efCnQ@h4y%DNQ~q#(Wb4-}3QtFKeyODtAN5efGi-XPvuO!qFM`+30ao zchK+_kj!Vpn}af+on01ZRnQ9|NGAw-fQV#vpKU%nTd+{Bg1%CUsb5)+cDl`J$h~Sq zteK3K?=3X85!<2(J_oG3<#N)Pe;yn#()2NZk$VZYoV^G}QA>a)uYQ~p{RXW{Ef;ore$v94A7M88)A zNPjGC=i~r7u`sY&fPvy^fa4Se}t@PP#QMK?@na>uZ zJz)2W7WRO}XN&8=RM^_^Jzy0B6HygICZzayxtCRB4=(}J`xKb&C50UWd)T;ru06IB z$A_tl@8w?FeCpy=@r@bXst1J;+eymW5M#NQ306US**nUVzpu;rJ2FgOE|(pAusl6X zII_F%fR6-wQv-WTx=B@UV(e)-Hp4E!#+Xe8Nz10c)NdWjs?mDXE!Zz<%4Ey~%16h$#FF!!5tJqVCv7C{LKT2DfJ>Fka{=O~eFZ>K` z0*lJMyf}cH-zs|}!CsfZp4@zr&1E(*_Ou+Qoel{btE5GvQeWy-W?3~Vlice0309dsYFYXFuAIN{TGr%B zUaN)kV=4)v!<(morQM8`|EKL*z^yE*_O~~30Pm)zf)@}KFp--`ilhg;L@H>Cmw=93 zPI6E|P@wYnPg65W(=sdXmYJFwninudBPD+`HNPZGJ$RTR0;RfcIg#Us|<7FGE^td%c4fE-)2_WYQ(D5is# zPltFK%29-V@S)nG*y~aw&~%<%@bhDGc0taMi4pLe*_uUG8`TYi&n1Z^9)*o&kMqSf z)W!8}RNmba-|3H)i3okI7v!g@MP#N^JYs7Wk2b3E{kvAa^iF1Rnaq}`KRq7k4-cs( zC!l)xP8UxOu*kE3%wpncy8SLke`5N39sRKYI~&2QEoMmbVvXCfT(S{cX1S7g&8lh3 z4+CrGLuxh4-iGqU!DaPrS$+gUe5^kXr7e%v5M$|k8P#CAwY*|$7LP5j^0n5=m)?tw zEq_r>?4T__3*v3rrsXvp0(Oy!r|H)6;`L!H+VVrt@>`?jpC(4yT3Pe1Sq*Jv7-P|S zOwvLYSLn^|V^hp4&@4b-tF>>kA{|wB7k3HqbcOOY&tsUTdzxTt7LTp0@>Oc(8<%3< z%dM{L;fM9CTG3=2l7E1|yBl^SXv7YxlEws{j#UNb7{4e<8fnV^pNNb&rsy1MMIN6f zXBRn}oO6-KqguqV-TP)DV{%rJR~x43{Dp(9O2qzwNqVc2iL88UXytgqf3{4n4Mmb! zPM`k}r`oe4{9gVx+;hFdd>NZF*?lcIzSG zaYH%jakDHf;Gxocw)!h%;{a_?)Ar;<4$RH|ETj6l4b0DNK$)2ir||-u#>K=)o9|P; zcFR0OWbRZeb9!?)%Dh=k+pElfhs+2dt7P8HWZukV)^r}S_46Ha$hPNv@b!}koqVKC z56#? zSifaQHgBh(dt8^sjLD}xjF?vZk)MAQ-S)W7vrrGFL$|~5h6Mbr^e<`Xb|Q3JK#Vl? z*yB3E+O5YhFgJ9m)gwE{>3ZCp#!=o!_{1bWtV$1f5V5~KZl-)pXW;Oe5p>K9akL+CExdyLFSPyP<2+O%9}4rK$T43OaP>)JLWp zIr&ca$Q>x3+TYHeh1gPz_mMkb%;10b`6e;ac-QE!=r{d#>9l;WlJR7GN>jI?I}6rs z-Sz@=L$_MpdZ#(wb^BCJzo~A$`KWr8Zl5yUK1KPKZbjYR{ugxnB{9;_=bzB+Wn!d} zccJtZG18`+mbV7o;x6MnjRn?Ey2%b0R)wpwZN@9)<|6`)?7L>{H*PaN@NU`^y8~xc z<+~=cP(G&P-KU4L{P*4f{s_o@BZyjl77K{X0Hs)2%(eB=wud z5gR7mWCsZ2t^4vc-sGu#m~OsZVfI2!B%g#Fn^Hd6Hk0iNW-(0DdB51-3X%K8eGcGp zc0Z>hN89ChBUpyyZFe7OY_U>L5G?IL) z#PlF1>U|42K1-R!wq>hC#z&v?i7}mM;j;{2emeCYtJTk?C=f>7nT+JM1m$(I0wz1A3fAj5P9M9C#m* zHr=$mcI&1w!zYq%vQWOQ+J|8xkp|D#LR}~eIg#VqY9H1YYawPaK1~ndu~&*>OZYC) zjWpi48-sSyb*R&rqt1Z7%g9F>zOEwMTEs|G-@Y3N)^2?@j@Z0b-^|y!zS%k|*B8F7 zf;cAkb$zjpQhgB{iEd1Xj(>o@R}&)*9lrp54k)@pn4+aeCxnbW2HLzH`cKC4;(d`2(~4Ja9&RbRMHb> zn;dy`)953bMvWbF#F0%$j6SGTT7x)KW)4K=hHa7{R_V~`nIMO;qM>u^3o;awy9hs2 z4QP!uYT(g5)##=FC9CmpEAby6QR81c9n!DK#HP&DaG*!3(MsR*OIeNblF%>E0bk8( zw8=(v+Y=9?$o#RVbR0TBUcJ}@o2tx1?8g1DphK|7G-Awy$4fO$ur;=ixXOlYle8{b zZW>2e&2>yeC3?%#+fk#0P0=K`PxT&&V<9+d+4|S4mBtzN&#aZyB%RmOQSaKDWRsdm zuOy09TbY)LaulnooLXO$$}~@JM-xn$If!-cnCkTMU(4z|+RA+ABkFw3)7w?&VAk0? z)oJC2sac)J;7A9|z4gmkoobk@D@?`Ty|E%VUh3p&mex6*huG#{MO3{ir3vbJJgq&3 zNqKil^15ufi5zQn*D(>*11nMe`%jT#O@jfyRzO#|OR5w$SveK1`thuhWSdy97qUh& zS4mz^Z%?H&2R5n4u-E9z$YbUAJuItp0?X_>p?;lx;n$?@zL-MRtSAgn>$FFrrA{yZ z(X38cn>5CNec1m(^*WQR?b<2n*dLEGj$MAoRY4TYyI;QDVYFua@iW)x0+uq6aCvn>Az9{P+`3Z!chFuc&rmxeF-T##)w(@)InbkRkW%d|Zzs??edV0I+9K<^JOL}_ww`X-u zwK9MG5p`m7Q1tBa>vq*Sn04CSBhk~!-*#|TXEUeK?gwUdWRD%I7~2 z!q4|4W_0GXbaXxTq-I^DgU z)1U4O3{#x^b9&Ifu?u}VF{k@(jGa;4F+r$cv>ex6X|lw6%?>5E%X}l`yYms2=d{?@ zuXH6^6i&O%<$3=P=Sl8d&b&sKI)9-kE&8cqPM0R!4(zMMj4s`dPZ^FGUEW|q#GEcq z!E^t{=XCkpd(ifawLGWGXX72MJNF}IblL1*K(}{u1m&nD0L(wCZN zH_e;f)I4L-DdO#NWH|-y4Q09m101 z@EHuTjqs7i*6Hrp-adyIX<$2IJ5?Qv)7(1X)pVy_1j$=Rsg_flXHPnH=Irr98VvX{iqBv$?x z?|g550h|A4GB0V=@muh1R|m6tb3Xqq%PQ>L+PwY{Z_ejGckY-R+GxwC*te_86RfR# zikW<_+xu6h4;!TMn80xuou{xo($X&IziVr;mDki_t9n(-A|F^coJowdv>(bmq7G*L z>-s)}6{6=Q4ZHkw%3Fn5Ua#ZzU0`4sfnqPDS?{VL)!5%KO~3VfVx-CEHsp0YgH`9> ze@s5olx3A{&!Ubh%-X=~{nOSsRC71^NXw)7kk7(i((;<2Uo3JOwyQSGysG;WkE;y3D&>`5v6Z|oAIF|yQ9ki6B8&V@ZMAAI!>o@uzF|M=qR6MV zjlA?x30n!7>7)|2>RRKou^?@_YKX`pe}(VkW~G5TD?Q3tNp_cgR(dSXvW3q|{bIl# zr=UY)q#vQ?^r*wvC`BdXawy|EgZ;JbR;et92Bfll3c4b3Idn(j@+s(tNmPdxq*tuY zVo&wBB$ee*_9TT*L7Szr9O{?KI>&mmPn;tPhxSdETE9VmpHCYO9h{_x^@+8#K9=Ni z==H?)O^G z=^dJsq_@wG-LrmlDC@`X(55Q~rM7n{s}Y}KWz^*1pF>$cUdXaS_9lr#<5CZOm$n*4 zr5YW|xIDVZ-X!tpA~O?%dSt&O=mAInRJ=n6L}Q8p$3v;TPPLJK8}xikS~o=(>VE`-!GDnH1f*K`cO3{PmuVnI?`w_c$#nRdDRncR)_CaVwB(V>LM)Fp&lIzjJ#gOen`x9 zYaNI-e3}?(>KklUuEIuCm-naRpoe)`(ipEY3*AA!D(nhkUaz+40d=tc#JsKKDBFh5 z5hE?fD$$0o5hKmEcbT0}`Xkuv?Xt*`g>7vOlk-)YtLxC2_)ub=_n9-2ETlzW@lWK- zF)yzQYg3*)z2v%)#%2WEpzB5&_AJrG4y?oZ1oJv_K94wZOrBv7JMg>@y@RM`Bgceh z9jgwmgXxUvHjD9bd6Jnl?Zsuu`?qos%kwsP=2Y~PtvyMz{Z{R3e41`pA7VaM<%tP@ zdX2R7Ir`GZTNP$w#`{hC92;300iGf9TfeydCi+6D18w?4*8}td!xkj0$0fvi zSRYB=9=951wxPDT8L@56{%D_unVm`-tm-4O$Y0i>*uIACOHAxZqE?ABd^M!l!G_sb zmAtK(2N@@&@>*Xv%xqHnzZEkqBPH@F20q1%k7GsZNbO9YX_&RM+WY;K#r+G%fMKyb z^#5>T?wf?Kg8tPQ%KBIBb2Md3Iy(bYN(qRa<_9G%Yil_%ZV2ljeMxg5j%yZ0_Sf4f7z_ zs`Q#bjQp-jL47ByPdU-L!ywl^#7LVAR~etkbCt=e*hjPy#d#u%Q^?MjwA1maoqRLw zhab^S$0N%{$Z|-kd*u&V_e%3FOa}(Jh<%higHTA9r;!U#b?>(xwHGE;^wnse zZBWm7NuE_bD9@@M#F$Qbh}Ds2&Wxc==)2j?lcuIk=q^tu*(9`=Q2e3PRszie^g+G0 z5>}23-xJgk_<`p!*)VdtFB93M9Kq_yR%KIQ>0&?J4m*h!mA&|3O}6sY^i55B8s@+9 z_zdep5h_Q)e5ON$iAaCdFr`J*49oeB&-lb7v~0t~Y^Ol=ossu0Vx-}i5rq5p7HQU!hTJ`W5T&pnGjrcRMPa#&yM2V)OBM)olDpMc`5Y90}CX8c9)$w!1hV`8Zc z@H|q2r+b=UYm|+<{C`TaeGTfP394lSsFQsi*~pAcTO`>uK!9w_L)n-P3=UWxKWc|; zgC~Nk%L_@iGoTtqYmfW$b`uazyPi3d8E2yVh`CY@2{wAboSBCh)1}=$#+l!FRoVWWWIKzp^*A7JH-I8rk2~}!U5qm>XFXrtgAbd!@aDmK7hY#^^K?7Ta3(RBors=>W z5dNrep<1?2t8CftI-m%7vnLN^0BNXPCy*g4(%(;#X($cJn1_-v9hijP?UQUTl`Q)) z1eYwEs$H@=Q?*Klse1WLNM=*D){d!KC9|oT=_Z+CYa9oII4S%+8QZyNbD0#f_d5kb zch8$uW59wdBu9LOKt)9m)O$VlFf~{FJ&I#FbxGq}uOrwid^Gu_OhG6SucxFD+ zXw@&oUr}eFiKgkE);`fVC1fv1%1$yye%@-nxm@$=sk7qmcx16w(^VE)O;=gBQZ%Lm zlU12wYi>2p2-%}+E?U-VE?S*dQ!UVH4@^as2&;U7)rwYA(X7>&ZlWo+X3;nyWY2HS z=Z%~^Dg-2J%6e{1uCho}xcrjj)@02o({ zm{!rAgJ{^U?fwMC(CUMU7EClvH_;SZvuKMfw{^H(L|u zAtRJ|Ok7PD(IicJgJHKvuk`qQ|eIp5(U4OzohRUr)pl(cUD|< z-T+x_9j?1GpQ7{NtNETz=kbv*=~qwggLO9Onmun|qUDdHyJ$6!qf@ki4eX`cL9_<8 zkcu|QL>okm=_Z0P(9@P0H5JYL8q-a*_W89ToDH^0qJ09P# zUw1iX~Hswa1Jpbk9@$6?j7JqBp6z(*`0*A^D0(?#n^O@NiNDDE4F z0sw92l0A1SAV8~FJX|HKk+r)1xL{B}ysmI;om zUx#ZTui`J3;lKEu%EM#qTLNpw^^GkJW4fmSY%9?2ha7dtpr#`~e^8TLT4_3}@sQE` zH;o?CH1$MoTX(xG%GjwTgbU%ymz*#>^B;q!^%Xo}Li&UU_{ zaQe(=iqcqou9tsKKYI(XCx{tc8iZ$g#$p+Ze@>Ua`Nf18U3&4C2{XDp4EH-MuhZr4 zNWCo2>GB=lFG>SGp>;Sde~Xu7oS|in*1zB7=x|#9j`~dE0}TwH_q#f#bosUuaTQ=M zVn&zm-W4zAz%S#U)7~$D+8W4!k2Vml3@)XCVECvlz%mzP4;Z--r?Z98V$wt3<;!Rh zxBNJ{4eU9HfMV$jTJZN0So+Tl`z)~Y&4|u7jOpdOcgmC_P37p~y`1u$2jhaAehw;} zCZCmO|^^1F^MkP6rn?0I}AZ ziNBYlwXQa)NmEPxN^crZ0-v;`nTNKBVYl3zX}lM;b3Vy~bZV@8Z8fG(89j#1M0`u` zP%cjn<@lof2=XrKy&qY2_=$jY>mL{O*Dc|ugRCqi2 zj4uCn(-5xLbxq-P`Jo9RT&teBa9SJXdXq&O3p7pQ0G4NRm47`ygtN_bjMh$oO!Ck3 zaO%;#ljqDnXQ za!SjLq=BAW;u;-#!qUQHuu9l{v zTAuQ6{|7y~8TpJZFZo*tSHDcmXjSvOLsEI56+^lBH@o@7=1HeCH_e=5{keba&$ud> zleF5qC|({YQF*Rar^ceVbGbwg)puhH+8&n{a}ZNqg$UpaDoOG32r0!&Bli0j8OO6M zVsBuBR$_bS7u3u73*L3O@j3E2{ldZ&pF90$#O!{n(P=MNay#Es6Ogx+TV+=2MzZojRpy@|+n{Pi$sTJ+0-`rn!?&Y?(TEXw$%^(M^MgHBFiQ6_nd8 zTaJD?gcGM1#qyrnjqz!Q?UvmbFNr+P>*<26v2O5mvuz-(@d_#Y22?mS_Gam(P+5)7 z2D>ka^K$7Iq4EYUEBCxA9t@Ar!gMekn>1q&E=s*_i%@}s!YZd$0SAt0=kXE5NQcmj zL!=-4iWun-jy<&~ZF4#?(kL1?KYQu=%+o{Y`F};J$FAff9V)M`7xNko;jtR+sp|?) zH|(nFynlPYDD8HMVinS83!LHDod*w%_Vyv4mVK2sP=+lujP;uQ-bBJzzprFb;|nlx z=UuOlb7u*`-hKhiuq^eKK#Pmgj-}dzJ!B1`5%<1(J}WhX_iEwwJj9spX@XI*ToO9B z>Cp{DQJ#)7Vd>&fSum(5?b9z#;+?wV!{44oX|EZ%XDBvdy(-_+kPpjCldrO13n{=0 zQa+Y&nwLau>2*bE?*|P#jpebN5c>ZvT7c1^^4|8*Qj89jyS@hT4HET3FR1SbeIYv6P{_Up`Gdi^1^F*{fqeClolsecS zQzsukm@awzAdMo|zcTd)Eby#{iem2k)F0P|&~Q#sEPFBbNBR9w`4%*+_SA*0M?63N zA_SWATh%Qz;289>7rh|r`>i2Tf|o?>>UrXkfoU2smV-7MSroJOCq_Di^{{C$tGi-G zhe|-5yr=JUsI-0$^=la5bO`wEnBobYK+DBStz@zJCp7hxLh(4i#w&&JIrVugqB9mu+Wm#^EIdDPA)tYiFY@BAC)c7464wm|%})@%=Sf+2bxF{T zEbHv6B2?@G6)^OuC;n~&eXVQYh@q$}Og_OLU+fwuY}pc5Ibo0Q>pCk&lUZV>y@c3_ zpA&6eYhsvqqz+R%@h#fG_0BK^&7$R^`3bwLi))_BJNqhET`|)$RNmPMF3H+}bf~QQ zYEirmQTo=$8Tb+bGu``hftgl%QM=Bqt$CNhhD!dir4MTGU*Tw{5k?Hn}kW@^4K7hH;i?VMq6ng z5Ocl*zgQIa2g8&`V9>oNZqZ@pG}<0I+}@3Rq=BKI@1k3=bYhD(sO9s%^m;%0Xi?mR zdSp5!4VmFqPWu}%($H&_Oh&s#SH^%vQM`AJqZLx`A0~E77 zA*_#>?$NIiBOSuVyQWxGIR_ zkZ;k7TE0ab<5qU4EPVyj`n}{Mt!0#Y>Jry!Ee}mr&G#fiv<-Fqg$il3HWmz9xE|js zP!7`0gKxHaNt3Ua`AFvR&SM>d^}?Jbt0(7!?vMepX!ns%+G7#ICt&!SVJi%?HekCE z^Y&BhZNs$vKEfEW0Bzw0f7fNv0@Xxdfs3-h(JgRJ{G?ZM3mgzHBS#CoF}`aO&F#LJ zF+y)d+luD)P&Duey&Q`#wzO7I*=ThOxrk9~T=;CLJdELd+gs!#jaCrLLLe+wS%tk^ zi!FMi4t5_gv3RLt>353a#q)@fhBaYH^9i~FqqW{r&l}0d^iX-~o3N~j#7LWE*#aZy z+h$(k+h!j4uobfHa$=;Jx7Pr}#6suLvbM1D)Y=9Rb3U{O(BVqB)Uwe|cULGJHPi%>MJ zr;`D?b9*egK!;wBF0jh9E`VumBwd{~>qKi->pE%Ho*xkF`2qRR45gl@X*1w2F_r_Y z7Xpq>#-}teG0Vs5V6V5yD_!$+HMVprOz<1TNW%ojzyzC#k%qZ{0&Dx5iILWNqkPWy z)P68aGa1sM@)zu`Z1NN4B@KPW#HxOB&%$YH$N%qZJng(N0G-)vE=ynB-3GP9?24q=yZdwpsrrlJvV!519 zzC5{t(9)gb!lQI0)@auh#f8~|=qfCQ&y^*0siGVnBl4A+-9; z1pPxGyr4QILY+Dh+POJFoeA}7Nl+J-_4uF&6`1eEEF_*;crO0V#NQK%!IWfOCG#Nu zCJbvR#Vqa?lPi|)?7c(2t6};V?(5w{>?{O}bLV^iD2DBl5LO&Pu|8m6DqASUM#Cw6 z@8c8S#Y4$={i_LE&_e7c&J<^4fSf17K#DJ7{#WM1(KGQMu(M;CSXG(@?#}~!UbOk66`rbvpUTACd2kX@y z#PL+Dt+bD{Z?I)`6P`1)Z4T1dvif7fNMp+iePDb>BhY@QC~o*W>mVIk?>il_>;uF| z6YJMEVg337!$rEMUouQ-lvfGi$Fqo$rtIHesF=wL`QCyozaT~$@?8n+Z0046I(93H z@4iHgG_g_pCv4RIsP{K`eV`99(v-zsV^F#98iTguie<*9vJ$&^sA5sROAkf8?-L^( zD(9h%=c8|=?Ma8qSASO&XKh4`bf}zu50;Rii6G8NQ=y3uT~z~NZa70qS)mQV)rObKKoGu&4V8$(7%1&CZCiOG1!yH z;_WAC-Qrjfnt3;3teo+|nYMa)LJOaa9V-v*9NYc~VzeEp3vYcPI@3159@Jx()yJf~ zr)Wd1zcxO__G(iePM_a>5wUxerY!e#u7jP`CNE^Uc0XcL$MuI&mbRGGi<1rb$M%Tr zf_?&KK2z5k#VsEa!&(D$sH_+p_c4rypF9NN!Up7HIx+XLp7*7n6~zM>n^Fg9mbavL z%DbdD^Df<)nA_xezb%THUm-?1RDSpp)_x`*=}@_Jeo>rvH~C1zXTxt?xUXOz5hcb? zWmBe2nlYpK#3o-X>p`@s%~P6YG#}3oXc7#_2g#NhIH)#b(uqTcHVtahwk#MDAjT|j z9V!LJ->A*98*&PwkwzU<^Nqxqk?DE)H82&vRetVl)Iq>B4;5lMj!SFWx={#srBC_F zj491ihxr#|)uv2s)`K=zhSn#p!OzcK5d)m^Cn?v+OVaJ=@>YiR$S`RLk$#Hb=(+r zFDII!l$q{vL?cYU#aBkexm_Qqy(BJQc=ix2DdxHz{;r4?SlMoUVf8Fhx~GTA`a43~ zhlr5|pYjW~wwleHio>5&3Ih%WHQ*zav|lHfp$HGtY`i9IQoR!@e?*hF?3H$rT*Wsd zRCE)OJTv~nTQ&ZVVM?3mZ&qUm!Wc%NV#!N7RIbEvmwo<3j5OBfiy*=E#7M()K7se; z4wi%PR$~_e~U2vw_Pk!nsM!%0tzo=QpppyDW zF0N}KBe57MmZJF>aA}W^T2Gc{O8v?k!8N?dRW*(`N{@SXh79v`~KB!PbIwq>p z!$dNLN^eoR{HNA9ld3U^Lfb*eTp|3_nzjLdLe0}dWsAMz&oLSuDm`9{KM`d#_%RHa zcWsqS{ddwJOfLFs2}QbV6#MOxT8I2l{mEtICFnTpv6!AZfsA|z7@YG+8^%oMkiPZo?E^Ywa)n5^A)+``iA?oO-B{*FxlnqZ+io``KM1?>GC?ba0l2PclS#>FlQlo3N1KF_+r3_`WM6D>$hho#f%yte zhfVGdn=~a!Q%U=oHdVOyt5lMC*H+2gCh_nKZF2qEzPvGBGK)dNV>Oq|*qPW5EU=Pk z#0pL(NC|32K4v!g81-bjrwP_^`KxSFPcUE(J$G+4dv%O+L|F2sx1h z!KM8=G;I#LpqV*o>-?rVAPME-`T@quynAjnuqrt8SG|s*(+MOhar^ zG!j3Vlq_NEUL+nhJSoYb$2gHZzFNsq!#xXyXL_jgIv9g&5;4-DvNcx5dt0B9hT?C< z;K*o{2j4krxa3`1#gmWy_DFuygVuvT!f#5DxexT7s`}7I4+bWF z6MAY$r0Hg(igjFe+<_Q0(I)JTlL8xu)>ZK0+0QGNKLO};2vaj*8)s;JXB?7up!})*-tUPEx49N^vj7FBjp{cis($uu^O=}U&gODE4p@lF;vzJFTk&o%t^QRG0FLs() zNQRASBIbFeWgD@VLGdMT$6J_I!)bQYTB}JvTpg_@n`Y4u;)T_|dZXPi+N-SQe#&ao ztfhz6H-CyYI+1xvvn@L|rKVAwtcH4RM!n#Gqt&FDHCoM__ysRo&9Uh_-~X~J8ds%H zHf~5SMlN5cs$pJ>1{skVlG0FAjEC`r(NwrQxBRxrsG>xWlRW(+@lEa4} zX*0NEtN8-T_j*a25zZl>8X-Q*shi5MQOBAQT6x0PxXN3DdDSrSIYA9m^;lPi$+;Gv zhuj};5-J-%SMAO=2XqN6uXe5_XQ*s4D;j2H&!X~MdZ>J2G1};OVx$oV?ty-= zIFU5+Y8k@UaXpik)oa;}HMuy4Ms`XWaRg7= zt?}9T&D-qPYDMxRNX8z8Oj)EurR&$wMmrEAjWo1Jukj5d4Y^0*3f zC(1l#zs*`+72invsGzobrrBzSjcPVqwY+MpSRRW_dmWm$ljXIgI_3A~ka|1buXL>X zutI?&w{7h=bF6N^2c-229V;yzo12@=Yh%9$P}Y$Lu+5ondrV`A>3-8#_6_+uu2ZsA z>SgEub6f2bKaWRSZK*ZPtO2N5}){7i^W?>o1G(A&dYn@ zThWiSl7^P>D;`vk2KIOxTWv90wer-aUo@LGSrl7sn90m?yd_l@j#Dh{bl7VfblfIr z=lV(q&R#`3-!!zY7*y@2x1ca}!cKA`$Ai(%wH+kv6ieX#kEe&$mw$nFlM#jfBF%Q| z*gjFc0D^jLm3%Uk5NYd$ol~N1Mx##V8llz{oVuMS2VC};B4sQ#qn@l4wch~yu;7$5 zUJBnl&Ra&aJt6QoFNW5)VCSBfw8bqP zOC}fiux051Flif0t*oO8v%EPratis>Pfs!1&#*?=uljS#tG3^2nAM@S|153C+dyL! zoLtZtWu4l-J_A#1U2FT9k9XUz4W8BZ5j?NJTIzFD0kEdQZ$1WqS3*r&C{VaI)k2-Isu-KQ!N5`-t+J0u}Zu{9x;I^M}x!X^H zjJbUdLWI~W7G%RgX*36#!b4rsY$6Y_nJ2Wqy(^j$A)hoaX)|etG7(b~tAmX^x;n3# z?AujXrQ7#V#|MfTZBvk~8=1$<-0~`Rv|&~UWiT^0S=7uCcI#wmQ-PW}Okd5Me02K= zgVgP7y&X3bx_y0SsOX+de=~mf%R|;J0by$=-zBnjqkL8y*$c@RqYus9Jh8v9dKR`N z(?jd>o@uHj4L;=;zK-jZOrLu7pkAF|`l1A+&394U&Sxgmccad{H^z;a7c+;}C-+LD zoHRV~mti6gk&m>Qt9dxbKEy{OH&@aYY0P9^HJh1cHioH*!0V}rtW&QyY@*bjR6jy813C6?BQPX_S)&AFRQG zJ4+`P^J+TFBj38T8aByxX*9UiWD|jW7#ICBkG7uaCH94h;K_Y66HywLj|tiX9@3_( zc@fncJ3}m5%ImmZ7~unbKM{8jeF3vRe9L_@ZsRA_vTQM)4&iI|fsGT%w?btb;o_lW zgfk0uXL@LT@5j&+%_BpGG(0o*824UCj5PKg5y*IZkVbjONx8zeu5{<_(GIn`XD05t zClj~NF?SnI=jfeKC=*GdZ=uKacuo$H2APtux|T_i_u=SI%R>1>r~TE z)ahF2bZi@)8ciqmlcfVYDfW}mrqep@CoVj8Oge3dSVtBf*|@_ROZ<91?mBDx8z*w~ zPUB9d0vUJAVtkq&TAw)wI*lVn8q?B1jJubKk><3tZu^cwX75@(voYp+*7P0q#28xv z|L9{(^~4xcJ=u4b9$NqOWb8YmO{aC*cZ?ozA<}&&&R}Y+lZ`Q%EhnKnvrWrv9>5uc z)+c*Jd(?Rio0gV^eZq7`MeYli_muGlKFo6+`xuxO!<+{=x9wc3Q#Qt2r<#o{YL96B z$zE-AI>2-~z;x1dU_(@Zx+*__b1Y%c-&`IT?aJ87!#@>}CHJRryspTDH zgNvN}OfBp=T31(zSrFyXJ|1ePnP zGgrgoskio|f@2ofDwy?Frl6b)U-c85xBUSHR|U~qs-X22)1e?vGBu7e1(mkhYzJaG zo9$oyhtnC=kb#OY3HP7NK{m&$up=eY*l5_P}wX%vsSJ2zWbI@@Sq zuNo)k?kc5m7)F)8p9;#{4YRFuzA2im(cqK0&y*%@3ToaCk4v5O8lFrF;=+PVdbxs_ z2gS438JFZl4(yQmxRl92#wD|;f|edy|A=PvaY>rHi9Rl6XHmu_%aFVsR#0cV274Jn z%yw_~U_LHg!E9Wb*-BqyTvj%|H;qdb4&zc4l_8WzEF zCGT1(z2+0~1Dj@I+AoR$Y>ZAA9`Yd*UcKHi@|V+YyMF;aBJMcKb|rMQ%=p_Mg?!yG zrSX$dtD-M6n%gO(;Qur)`FL0xwkeo6|IbXaZI_o7jyEKYL&pH# zZ*tqXn$d1O+ju>GjL!FIWDKmjD%yt8q4i()Bzq@q&GCAsIxha|*jH?=RFbEYPM z%c(7MoAuWbzk=c$zC(pDR7<$S{oHodk8NN-U*24pH#RC%@~aI)qHC0la@%3vh&UwT zg^p|o7NcLh8>_(Ii_@DKq(kKi9D_NGJ9tKi%1xgyiXFeiyrl7@{WpMNK_lgn#z{^X zSf;_EOv{oK8N{ycIET1TmLy89dIk(ZopG?Fsc8 zu2ZP|VHV2cZlcj>N7&E2vCK=_+m@K#!Wd#VFRVPl=8f>yC7<5Lz~@Oh6x)H_zZ05wPU2b_DxbOo zEx0N{IO8SDg1)KvqKD}T;l!J6hxYbaRc|nyK;8SEklI5o2#a+A#X}i+E=#JMLc3|F7 z)<@ocyI}D&c{s}>9V$CtRup>83bK$!A8B6+-&%RUs>tx9L3&d_e?_+#mR!0=f(vTr z!4QwMJrL9BKA1~aY^{~jo1hz^~9-h}k$Vf7~^!KdRTOXe}9HJu7hhga`F52-To3u*PmPkTBT zGgbK~3_qv6na;~MP^OmG(}m75Zhgy6QcFvQbtN{vIm5gSGR&T4)k~2re}itTQI5{N zPJ4Z9msOLI4!%|JS}o#M5z~=&8EW~aHz&U7%`O+Qu#)9Tz0OD4+TQZY!gU(H$w_QI z4caEG$KEv4@#aml!IgfJ(VU)`c;~$}fht%tRsM(d5`D6W2`I#I_K_ zF}c*zjK#O`kq(t{aP?E3B1Rf7j*dwf=}=h)N~9#36}3emJzCtt_h~wQf0bzKhw== zDb_LBt1fR1oG2CJJ=C^3yd5o}j8mf8Zkr^l?xNySTU>jRjbT%PR=SC2F+NS_9?N8O zvy6S&Z<+i*q4oaX;_scrNMjA%H+H+xjG8CIcZkVI)I51JGp$VoTiYh_OJ3u(AsX<& zvNwcijUh2@Rcwe77I4xKB=98-`vyT{I8vU`)w~R+siUt+UIFaL4 z2<1Z^Vzz8aRa>?+K268LV0ggE2N5HU{@WjzMN*_0!FePl5nS`}RG;Oot@^Ql`3dN| zNonuj)$xRO?B5TQ(s}=`hCuKq(;iS|*f$?i>G2;Lrs?QYEDgsaG}Qi8nhG8R_aK-k zc+8fwB%k(|KO^wPS8M3exh>sDvJvV z8f1CuL4$mvYQf@r>sz3V%^IY+80lEhKntsh+kJ~pjqZS?p?6nR?C!B_ZS2k-L%jD6 zhK|SXVpxdX)#wMES;C9d=8V#Q!q zzP7k6Mt9{i*aaw%7+6p>fNk7#SS)1>+M*_ z(9k&P;!%2Y&e70j#ra43NvtNDbhG(q`m9jd9{-=aHJNnP&^YN@It*=7wD)$}7Dj^) z?dlUOX<%Y}nzv&*CgY=?qic;X&9l+cZjKwX<*%{5rw>SwTU!5Qq7EGp_w|bnsifLB zCg_cqqzRfduO>|%O2d%rOp|fEMXn~rRin~okT+NJsWBW-2kT#r$*D^(k2DlI4u)oP ziyGg}W_(r$(_L|vr}gzWXL(Pq=H(0Oy7he22|ryUgA5*`>(Kcm)-^P%cm4O6Sd zi~O=hUDn0O;Q3j+nd`3F zN5-7ws(oZ+uG%6{9Yb@_rwG)h{fup28-K#zuJ+J4JrIAi5Npm`u1i&7R2$m8amEL`#fN6 zp)}6e!kgQ=&}j7Saj*-sDW)6Nk9n&wtP{j;9s3Yp6f7WaB~4py8PbLi`wd?2he~r} z-1|k&Mo7P?{hB?JHe1eYboza?$LS`E%HPj0lbJdhmW`nnd{tw!iF_UFdwO}En;sKw zxs1i9%$0e3yPj2AyK6~KEI?+VD^FsZiQcjRQ8~|7%+fK_!rm>uHQL%+`8uXgvSsQt zHrcW$fF8(aF1O`_VwhTXTfQq@P;y)Do#I=Eh9@q!UlWz>;k{+ww%p1Zp)cT z`Xc41!9IEuF!FzlYm&>)RZMX#jtNOQQfU;b-<6qe6* z63;FbvlANb;fXk0xD_RPt&h3vc%8gbRRCarq!hnm-%rEvFv_6h3>Yxv?@^5 z4QP}RR9riEzI86*7coAj!w9hj;=78Z!FL>FGQJ#Zxs`bxQ@>;L25B2u7V|oveCu=r zCv5}EVrVtop){&Iu5P*2jL+&-Zky)&+Om_1cwl-OVSXM(KQ+INs9`ZZXZ6MH|#{8?8#B~4?msD$HCXz=yQSTbAjoj={#`cJ8|-c zs(t<^h)jZyC`Y_xHvde7pO z^D4bBGQAl#>XmfS`=Qn7JBxuxn?CCxM5JAEse_-lEu(?(U+LdmzU6bctmrPO9%q;t z;WPQAX(s+Yg4VU=iGB>jIAa#$({#S~)_eysIWX6J2i{wK3w_3AtI^0SAJlXzTNi!C z5O{p8j@eYq>j+GammwjQ@_KFJzE>sTv`^+w?5_6JfU z3}7RS&wkuoX2MC(C<{w$+7nY9|1@%Jfxl2t!cLi<5SCaLVob+1x}Az*oGsx)R0{jq&g!t}_N4oCJ`h-)TIny;|i$0>c09S3&xB~<%%Z?q}ganH>wv;UVA#y+{2d9E;K zS(#62$F*@H2Ug`iu65~%am_5+o0iUd!bk7O9+rE;NAHMhv~Xn8#uForsrPmn%fv`? zs_H;!AGrB(+{DE%%itde zbIS+#y9_RCKf{!^Jsx~BP`(`Fw9Ri+y^&Y;z;X;XL>1G#9n-nyFqr&;*TANMBGt6i zf3l&5_$u!|*EySgGo8_YdNtd}v&hT3hq3#kQSfq4ACfApK>XNu{ zE=PVZv?a^{$2{Q{w_NQclJ zi@`aED`qs>U{1W*XEZQrGX{j!7#3nup4Ynz%KPl*#7KwAj(>!F&BRFCfm7ADV?HMP z-KH6}#^Xt+i7{I$@D3G!22ys_QW}5Y337q)nj(#8jaLrbItts!%^uNU^n2NFtQ@OODv! zo^s*|_Tz`+x%qZ-(ycF}w6Tq8lUpFf;bV`DpIv-YSmL>{5+nZsZ+FaAnKdjOd#q5-w1rzm>PSmU>(;@4yEHF`j?t#H%}d8y3MZDZFpQ>m*x2((e3H_ zy5S?DY{ZTEvgskR!lyBdVVcghL(~m^FzTkhZ(Zxg4W3hzZo9!s4#oZUVM#Z6h6Mq| znCEJABPWtqKpzc+Xm?}m34}4|SMeiE=ld83Z>yO8pyR>YI=^5Y*R9$nsoT6--9{vv z6m_B7VdLuShJ*FR8`ZiUHqNuC9+u8irBOH7sq1#wxc`Q3+~ogC(oIfbpx^TGW(PCs zj5l&3$H+L|)al81ljh(!@^tEEHmRp)VUxzcZgi_2Z`AFyTHUhoHp~RA9dD|ee6-&; zjyKAR@us?248e5TWYq0>^3PI#A1`=UpKl{k2mUeMy+nyc!Rp4TkUwGZX=)@{9vvd#+zj^ z-87vm@TePNFxPEejkju>|tvZhV#w^s0 z=?wl|HwpelH}d~C`i;7sU8`HxZ=x=AtJ80)8~ROt@haC%`i)skH%*6b@HtU8rK#J0 zr{DO2>71k+B6W#2@_yT!6LD?787DVMO*f4*WPX#m+vhjgBpr)$6dPf_Hr|J@k$$TaK#w^s0>73tOH<{l=H}bC=-Kys|>SkLfWo(_e zZdtzpQbB9hIBW&ejJ-^S4WC)^6GL=$;ta@R1Xq zO>we7@FNpe)x^oc!)w39;>GX|X#NM0iH;8ZiVju7+zhGa_4-k*UgMJ;imK3S!YOV0i+YVmGRDgI^F%hvIpGw~Vwk4WFGjuK7hSIjrwE_v zHM`~bCVZp-uzsLi-7xNN!{^IuP|LEoWm?A5Ub48D@Rf9)aeI#IiE|RP1EHMD2iEGu z)r$h>8F#eeGcIiN>xj&1^u|dLevbzKTwMG;3u4=Y8?q@h;VUjT`NSbjoa2Hg41DUO zCVWLP4%pQu!D{k}QAl3tpNZIPlzO!e@M+tSk9koqrB8XK4((gkVY2d9xsHOnmGb0Q zxsEFHSGkVDbxy&ay%rc^xb+5L&|RjO(fBCvNqpTh<0Wk}Ssj+Q^{t!0*MsGe<`*w} zvq8Uj;mrn}TwFIfMe3NfOO!=^oqF5>l!Y|(6(?tH<+8BNSg&JpVdNM%7152fw_|mA za)QbD^qcE3M_3)Eo0lhbP`-{0)@tXujElM}r=A+bGi zLd-(_WuhPdJx=sKSY@J@!AgGN>zH2ElRWjhqE@fW3HdOtbwa8aoRCcN?u0~6aYCXO zor|Y)l8<`9F}Yq(98Hc-e1*rNWHF3{pEUP zlcAg#fRMFzNWEmigG~jqLzPqB?qL?SLrdo*AN9f{?|O}Yuj6`E+aVX__Dq)qo0v|- zx+Wf-CPSZLYJwNzL=NcXr+d`5&!inPDDiaKp#?8`v;n~jecd__UZ~ekQ-8T$=^$Pi z$JcbQ)C8N<>u|`84X|7<1e=yc`^(blH=q|N|5?&YrtCu@WfpA8Q5^&c zb?lIwNM4E@@OeIWiXAeGVwTQLOV>*-fQVi)*RFdzq+U1F>Xj`HJUXfAFSfw5(Ba`~ zy<~BqF#+Z}=xXWQXpVZp*SKEmqQ9!g*T9KV^UsrB62VD-W&Y5Ex>|ooPUJw~=zd;f z9r#1lOM^&Hr(W*o<@pKm^W+yPl1E<~KVR(+sn<=ldS(7l&c4D9>nwUyFZe^*9QS!y ze{M+#h=2TXrFJInyYMo|^H+7JxsLjpJM|@rTT!{blJ~z(u{V zm~*{4Fuvr$ZhRD;BoB6vS8vf^_YOPZC<&fio--WJ9B&q9toQF^*!R`(G4qyCvYE1%I2AIi=?lNf1WpAeM{Q`*%OjDvpaIo>#sZ2@34<#a!eN;6=ANqF!jex9s@z})d2UdQwO!=35?gv5 z#sM|~S!cqQBK}tCE@FACFN87cquZtvBMq5$mv*b>+Xu1UOp}?kb?*xDIW`c!(#s=l zeDGAFuk)#CG!v_;_gP{tpUQ$*C(paXagb#PVx;YGkC~qy^udT?n^p6bVcwpXbf`Qu z1O3DGwb7w+{u7bU=ukO%QNl>0j}Tv)*&EHFH5a22kndq)q(kd{TNK5Wun*{AG|T(diNvIi#Y^gAQpZxp0JNtEZ9H0EYQH{fnDsgB z&M>n-+KCTIt(R`)KEuqely8M$YLoTci^ksTFX3FXG2F`!P#fG!=ADZc7SfVESaebd z`z;373Gv*mW;_^BQ}Q_CssPPlINpbWqdl2k$=$DRelNk^x`At9MHxuVfv7<##X^!^r1~V+U_lfd-ITQzpJHP zynPg-|H5G_b+-M;r(^LN^Iz8}MyYOg>4=Hl%x!ep5;k<4@!ibwC|3xh;iP@qAq|-^ z4(1(S%{Tm~7`uj%4q@OwisH-T$wwNx$uxBWG3Qf^V>eV`OUYMN@2hn%_y}!NZA;2G zw~3gSw>@N;If@u*^IvSMU|8j~ZzW$vI#e#$rzlQ-M)MjCzw>pJrxTdd=9kzXk#87$ zzvm^*n=XdwO_!6O39a|`M|uCNbr_9t58t4!0RCagr;(12;Po)}DRuLHI|A|M?8k_a z4&if0p$zK}(y*(mQ-657Y>2%j`+1K*I)v?C!J$(6T%*yKoe=h%#5zc`fBg}$m#{Y~ zy8UT;d>_XACVq}IZ}tqik=U~<@zV@9@@7wehE{sZr~e(HRdgF_zDn$FZWH=f9RurC zTYQArJhua}&sPmId!fx5W_C(jJjjzO}`#jMd zCI=kd;j$=Kgx-kWwu}xJcX;sSRqhbSa>N~;a!?z0xQBJ)`A}{HD0wp6;h%{~v$q_~ zX16CgX|B!Y4x5!v&u@>y*-kmXZNELPzmm~%k)7XWNJgn{aOpI!n%7)$;3`|f#?CiB zhJq%Sxx;fQpSq=UA+wm94J*nY!tgUN)NFbt4L!v5y}`Uy*s^L&!n)`-mA1U*(yHoR zUPqR@Yq7a(tEh(#r6a2A-5aiOw&_ON+=JzHnYTx% zLNc09qmQ{(>(FP?$KZFV<>_qy%}vrg6Yq9qb+oo3bhCPmhKojsJ9Dg-XEegPyW;d| zG+o+UJ0HS4_%TF;rPJt2jRy8;Q5;H_W^`zM;Cu3&o^_CBd1L2O59)5e7Q^!R%Q3hH zt9KeW7Sv|v9$`+!>_BY-V~dVP%cE`IO>CaomD>Aq!_59T1`M;Yp!N=TtqX6nUB#9e zW_HhUVVI7Owc4(dYeTlqmFq(IVW+*ILqmE-M4iu_r82B~YvvGk`Wl*q!@eR{SLR*grI3&5q4M6=FnL?Wkq(uowuQ-$ zRz9P7C1oC5iPT|vL!YH78X?UFvtdBj_%s`g*jhE1m_XiWnHi+lN}?HD94|!_Gi*jl zGn-u;2xTJ~N5Q*YrMbdt(t37utyN zA=knhY2&&YlOIo$)!4LEiBEovP5AtWzO+2lAz%ISI{HFO!TPG}$a~0@z;BD}U#YM4G59TF}P~+cd7xfBG!~S5KZX2Fgp7Qq}bR-RX!PM?Q zNJknN?A2{3$Gp5M?ComZet2HejWld%Ueb*;Ftsn{^?utLJ7u5itxk8kpKT%VRpRI2JUI@#&aZD^Hux9piO9*YHKI=P>W- zrB#f-{Fc0X+%(}94U|$|A(M9ywu9t$OI~|-D7=Sy9`hbd=S9dd6PZ^oMUI(BY>$2k z+XH((^4mQF|3ZwkwXBv`SL@x0+8GY&)h(UV&}jqG4o#l`I(3m1Q3%WCwOOq(bkJM0 z>Ox<}ZzVpd!eAv8!acZH!h94^o?zSKNp7YNID>q$u{z)kM8>-n#m0XkMq02C7Q@xZ zMgeKr{0!mN-w|7KMhJK8P#>2@jq9|+4VPA*WX~6rlXtTSjU`6j5M)5FsY#>G<}alxi;}ZC2Ny7sIwk*w=0eVB zbS*~H#!o4q(cIVSgqcUWUiP{gPO6W|e$d7$OI?Nkqi)uZVGWa0bI2X^)d=I$j}(+V zfXeRMYwga7zi+_gZZfUKf1l58?sGmdrejG4tww#07-`Id7|nfp5hIP?+1VJa_%Jcj z81-)zMZf!qkwzU_mtb{UqD|MUuHCLqx{6}x%RWihPIz`+x_+k{+jM`HWA~(e>XbiXDGNKGJ;DZYKt3`oP^zL%4qJJ6!ncD)Jw7DW5EwN;Nyd zX?vHZ=iUn6aXU6HiAo-!rY{8k(;sRNbI{A^0e=BbXCwGxjnMj0X{LwDfM+plBI=WY zOFC4hAn(+}iIEPKyZ?|b{gV!1^IhXbd!s`b26uSstD4tnTVou{@+@!VrAx6)T}+I0 zsQhJj%%szak+vCC4lH-hPo)YvFMT0#bBZehkwpU0ro_2TLu+o-kG_3SVyuh%9kd_%sXdhc?FimDKTF1vVtQ(9rUDsdM8ccR%!wu%vcut@&H>(D-8RYmb4CaN@P77~k zJ1xA`Fij7Y75`flr~Qo>X&TXu`w$Z&x)B%7U;1WIJkXmMY2?L>d^?+%kvW@1=4_Y_z0SbkSdV#0L$8yI z;?5<+NYfGA^*k|g1a~1i5nE$heSDtB+!O36OtUqtK4;7|jOrdUcN*`|Y|Hu62A|Bf4>DGj&~* zj6>Q4-em6lIIc=pP{F06Vl!2F&iP2b0-p1?s+W%XrK3EHVVVx(cml?;DKXM8`U`Oc z1%pdHqS7!JOx+I*B}ST4?h-RfnSPhxMKT$%OGgRc$LZQWgZZ=?%t^^$R-=5hL>8*Y zP26;3tmHOybDCB*py15R#_{M~r{9~|ICF0{J~Ym>n-H7r6yr6c5u0I}v6#!~5cI>@ znVQ#V^F(lm(umR-D6g{O2SqW7!LiY3Sj2GCt|1?3^Exb#Ugu1dfrd5tI3?p;j_xsQ z9Us@&Zdlr!U4K<;SQn)6=Y};pwOu|XUjR9-hW@{%yxQ5L*>+1u8>Z=@@-|jNb{4_t zP+5i5kez)p8iNRiv-oc2C5`e%z?inP@|33jtmET!ZJ%N7H4$Yuq$iU~Zdhr-Pdl8M;d(d&~=_yX{xy9AHDRhqY_>3O-gv*rJqiVeK#eI z#Juldu~#GB@L!JBHl9KyE}UYDX*&Ap9`v29oJbS9fH91wUvNXHTsj|pcL(#5reZ8_ z9rPV{*iK1md*7vJzf1P1r_Qj`zMF-eCtcmAE`~7U9Lgg=K66GSfqm(eUdvb z|AX6HyWG%bo6E)&*^v#4!9F8ZLfz)-bFJqysWlzjTt6y`9T6I#4~)jqjf1cq){7Wv z!-iy-ZGH8*Ry^}fj+dpk4I%7Kj5JPYt{=kt*E26^oY3qO!s?$8BP~1B zA*>ukj5Kz)?+W2Xcmc5o(z3-F!k>2#tZpl`XNxnANj33?^e~&A=Yxrl+Ab{$yq~kT z_%rL4FVpg);v-ce>mzKj=vU~?RB}rX75Q5E8Cbe_7}9u<{14dsKa?10zR%qoF^BNU zz46|!dbxtt)w*rp>poGpYtq>DzE3}sQ(nnFTt25w-*;op+V}6GW=Plv5xew(wEffi zRU?GuHuo`|k8%4JwLHeXdsw{G@#~c#Ja$%n zOl;us1(sK7mr1a?E%P7Q1Gl{GF}qIKnZ%g|8O@`5$5=j|J54{#SMoC-OHx4SLtHcS z=fK@W^x(r1Y=a{xXk4Po=+A+V+yU>`{-r4P`6V&ZxO%ZSW?>E%qeJCNEO({~8%%^W zZa-~N6jS&q$Y^Zld>^xQZ{;(ZYjgV%zF2RsgJGJ-vpmv}56;-+_q8Q!zZ^HJ(gX*xawy@UbP zj~HoU+q{>sZQhelNN^+nB1Ss2w(b(b!d(nVf$y6Q*u7;RDQsRhGIP)z*Y{ zQ?c8%$&<=p7n{5xx`gtZG{t`}X=B1Ri;^ALo<}xnte&)WvFD>EOy}3l9{(mLUpIUF zTTHVkwzRyYVVY>E&2Lpcqxqe8L(E4qOco>F+c0qE{GgSXc+d}8X|Ao9k3Pa&+qQ!4 zo^?wX=H*_f-1f}E^YR;_4UXBauHOn|rw!WL7_ETM_3wHe|A8G-$bTe+CUj z2JPS3MA_$xctke+yk)##o2{xhR3Wu}@kV-O4!nwg)zaIvSXJw7+AWPw(=lj&jW1Ix ziIK)Z(|@LcOd99LU&5fpmogckq%lx2$n2cA(MUu2ekFyp4P=^}$%R|IkayZ>)=SzB zbI~#IVAn}J%*EBbmt%ub%d6V~ZOu^k+PYnr2BVu{TH%*p=b(D>l#ek(Ec4|Kvj3{N zgf&m$a=C=GPo6?em<}_F^k@l)uitm^UKcfGIYjGBR%GeH#t- zbTUIdOE{c!$0(#rLol7;h+o2%&;*yTH5_r%lrZIF#CQ^#*hf>NX%_QFusqLu2|S^n zmn4mOqI(g~OOnPs@dL~g7|$XLY0M43!94L8G18&3>#68an>$Ezo-jRho|renn?v%} z?Uc5rsT+sgu1}^Zjf{CBTS}B)rHTE#UmMfxMhVFtD!ZK@*AqHVeBVN(pIcbNbj%5Z z;SEpLyhig-h^;a7P{?P-!rL7sa|roJ3l_rfe(RXfFwIH`-#?ldY4MaHe0PZPDNS?z z{@a4pZJGbbT=_A=p0gFNxsuJ6O)SxCE>4F`+=A1+D>qkZL^-xA@t|+Ps=4A;lO7>% zRAnq3Ch|T`mfc5;G_l5SC#(_XuOY<_#7LvOAEAHSls68`7(bvwI#g~R89#U!9m0B- z#|YkN9)h=Dgx3S{_(k~8|7UT(&1epj7M;AErnwTU+bM0#b+GP6bxSYBl-yj?N~gSn z=6X|~Hs*@3LI#$DAJbv3yTM#9Rm^A{PeWL<_jANZ%fb(X_GMzE zVTL%(82S<;P3)HQ5_ZdZnCx-F@u#;~dH>Jam%v+DRqem$@-aH#m>HsgnVBQP1#w1H zAccF)DMGs;pk4t{M$Iun{cs3}L`gx-w3PhB)b1rkBs4`FK~qyhMN<d+qT(KZIXnvRVxjkAGK_q^sIm>t({+_P8kZd^h1V zD3$zhf8pp`Avio4PWOF}ojjf51hH^0r=*R%pXs=7sRh4-C6v(CHOHzBd z0t-vW3#pBr+Q<0IH!@U#r}KT@q5^kn?^#qFeV)zXRRG4Og#aiM_Rn`6kn)A=D#$F3zLnaweH&I(_zI2j^BX);8E{B_^(E z&P=Z}Vbk!0jdC}b<*`0IBLqIii#1`sO`1`gKU?IOJnP{nP)S=lE6>yE`KSKnb?CDc zONo)j{o&ov>LaRPD~Wk|2i}BsVFVoc+YV!<^Gq6@^Tfm-X|&aJ(Jaezc@KrWKMBN0 zhcN7-EIa!EVx(bC-_5e=&l7WAc7k?Kw(>}`4H|DP&pWa{%VyHG2huEW4s;{!T!x{G z31)KSf5p(@&xnx5vn1PMqKavfbY0STisWl(gQJO&=Idnko`AkicE)h7YuF{-n78lY zsXWpgwoczg%hMt3^j$b?o%StaGHjiOPj@WZKb{>k8XoSsEW3IZ(>?SAdca-PF&W-w zvrTn)n~ferdtEDUj`pJ+VA>}%@57%5eWDHYZv1)EnRnWUig5w;R_J4Q>_?bB4!lWh z$Bs;y4XNF&wEOFwcL{R5rdZSGcbK9UDTX|;B>;vRwiuDD-rVb`H z)%uKLM;oTPtma;Iy}grtrguZQS8<8AgS%mIxQj0F=J;SogzicHZywp49^xAwvJ9wR zCY{WUE^+6$P#<05kV^ko7i)|zF+Ipsb0KS-c44fs=DE; zF-y;MtPef*s%Vi$hw%M3;WZ{R9cc&)uQu(%a_rD4*w&awj5J;ic?`XGI5E<&0m8(-cM9iS)TB&2CL;meo z5=J_-{Ch+2hp1b;B4RjeyefNc3xG#u{r@FuwZvUS)m_@5svJ z^15r+@@qR<+lwD>KszG}n6rywe7&W!vq4M_-Qx4UdL^QfYc3ki{rnKGRnzHcIt`D; zv(ALgl_<1Nmi_z?#jHL=K3M0OHHR4K5Dq;BzV3cvq|L9LS&r?q8vYOMBDPB!J2gY$ z>);avBTe7bxP%zx3}Fmpz0vvtY4c5p5F~H0-s$fX^E&#zlIkFh5&kBO^sh3VV|&BS zY>O_C4q>xx;uf9JIE;N;+>SGvn0>5Xv6HbCEvMc693g2QP&R$UbkEPly4Nt}B_|#7 z<_i)=8hsj(o*xk=9rA;b?Sxw9C5>kl5KW%2DKXNpjqAij%P_rkJMuxrjAj%zc~@c* zrA^+|q9%?#8o3E3zs;oIHJa(>?x1-YT`gh%bzQQ}ExNL{SHFRUc=aWwOZ6M?o8K^9 zYTrN8`o7v#wZ5;LmYtTd?{`GsmuViXX8MgW^2x@KsZ$D{?Hx~^rl!zDGr}CEza9ga z2(3x+k@x+y+Zp?QTFr`m|D;$}&2sjxMgLpu`W5{cKTkrRJcJl&>$?zM`junyc&w)*jsA+U zb8;7^BaMe0|DI)I`V%9~{(Q>r#Jt|q9?!D#RuLo3{ycq673_6lUT@##R4-}v=czV! zIMxsTX2AZ;OB(%o@3_fiH2UrjvCU8aWi+vqKG3|1orJhoE*$uoZqlxU@^pVf{O0|S zbjasGUh8W{^GOuPLqRc+3djcehqoA_#1g4jeXi*X4$11 zDrPkM?hR)VlYV@|S?s%apr?q=W$Zm=ckd>|r0-6}7%i7cyq%@*PJf+!ce?3Fu{DO7 zF17ETWPMlds#@RGo!(AQvhQM)iGBChG;Vv}t&MYt%=>OyX^9=RFl&)j%h_1)n~?_T zPjN^b4R}g|Vn-dG7INfRR-X_yxuUG2Vla}1(vFHL;idos{h;Zs>A3={I3(z zAVxamcl-$HY!D-j_ju+5vq6k>$ghC0`hZG0SlenHR(8mn8sk82G?zjAtc@&*;9N~E zOBs%l##Ri1h2E#LJks1$il>+12)BQVOVHn*QI@Xdv!}2;{eogfbIYdtO~ho&ru$8y zWf|n^{vt8bc>NSZRXC6sXS((EavKPba4#i@2A=MHQ|WyVDpL$L;7e(!xW0 zw7%d+JlHP``0ht$#-)yu`;i3IJi{*h*@Q^p9m8i6y>v~d`-=IIhD~H0ESnC(*Nz+;d}6!>A4oHukG!7lV0iQiO)QVJb#ha< z=RFi7>ZE@&9cefmIKdMjpEx1Xc&igp^T>CIk;c27=uAEWl19g$i@aNDI-}9a-%TSR zY3umbR-X6l-^CF>CyjSNFN!0+(Kr$D0QTfDl7T;?u@jAYyU`&U4SkH0rL6CwV=|FDNuj7(HUtnGG0OvUaoCXKOIff5iQzlixdZ4`Cbs1d^?}2`wCl8 zC%=c^TQL8BMpARTsj-XaF-(8=-vs-L_(w_Y?AvqyQ{eu?IK|Kh7>7tp#(+Nxv||h{ zWCu>S+XfuuV*AT7vfCzye$WE(&=2X5Ke`FJ2gg*SL%!q^jL{6hjJCJ>=wGdzkUzIL zbtBT&JUdGBcsU_|{xU48ok@%|^ZFYHl2_h1&|SU(Os8)H4z_m#tzP-PaYu^TXmv1; zi!OPqt7X)L@uxM69Cw<&+G&rs;%g+QwZN=I19*SV) z0{Xc?8mp=QLJ&Hh<&n0aQLGcPIX3cqtPb2xj5O2Dxw8s(4Kb0u5ks!-#~3f-tEN0c zU*&S>iUFQo)fEHFtJs}}SsfZwyi9Dm@h5dmF@G4_PuhF{>z(TDta>nPxbRoqNE2H1 znV{;A&Z_&nDZ0OC!fm7bi;I!z?ewxoXWN3aBVaw8>luwTHH?0?7H+gzz`JZ=ZOwPB zH5E(zuZKskd`(#;N;fOj_|Yi~XA9zr>(Ug2!FhUrm|B8Ft71H4G;H-CwESSEBaL)o zCrd4_($o{NR!dZT<&Q7wrt496zRTRB<^6_@)#ZrdQADzcG=#A#`gKgI8 z@&mqskjoN*KM+FNJSzpKmxX85!9uZC3mG55ZbbXFOSeF>v1mhR?3B?-Kp%p4jegDr zWXceFm7s}n)C6fndB2GfozWqG1|^T4qv?#MfQ`En(_vy)3P|kB3%Ezas1cJ!G)x+I zn!VPUE_>)*qdmd;QHKtw6At8`3>t#{=+FV$#DYOQHBe3KzYA8Ky>*OOGVkfwp546- zMl2aDq;qUuIbuB>HyWY`sC=B8nNi3mFfaIYWl?Fw+K4Uv5ISk|056oM+iBbQNu)rU zpJa(EcZe&;^hX`izn-?dN(0+HVd_!vIJZ7AqIFbnnuM;?Pe#)$XpZ+;(@D&zrR4?9 z$@ES%^p|yLZn^(1VkAb24zIfAMvUB}p~dO9MD1`Y7kp%x(%d8Qy%yOo znS3#4es)Dc_fQ0reG`Ahh%~LpBa<@BMoceHezT<5;bncyZKRB%9sUz7O_dC779E9~)%I}~5w|n;i93?f ztP0lQtEB1hSv0G{R;HhTOC}mOJQv1=Q;%bH9bV{DrIkj@zw+MIErw1EE}!ca_H z{5%+Gvp#EimIEt29F{wfc}X+xg_DU%-U}x)@AS3mkhKQ?#2jg}+@qPd3{wqxeOO@K zAJ%s)(~&mKzh9oWFGe`~oLnG{TMd6t>m8)c!uMg`GHiQdYLPg_qE=eO_A$)zszt)8 z)FO>%#f~=2WK)a8u9+^P8P95wuyCE%Ydf!xMT!IL*^3^qg?8Dt-~qRbu|hP$A!z_} ziz}R_bn_}~v&}PGNxm)X%;r%?wjF*R2Zv^%B563N^Pwtq4KXj$A?$_!H`zKOX;b}( z@^o@F(9?N&LpzB{F&$|$FDs9EP}iw2FV2gNW;)*x@pQ8BHM*YVkv4M}LQGXZ#MEq< zs&s^@)Oc3)Vbev`SI4~C#o%~!Sw{J*uF{15{|vc<8}{tmFmi&()-HVyR`rUp^_2R; zcq^fzV8>M-Z%>gWDE(ddO%}O!o!* zaV3k2$KR3vt7nl>OM045V>w}Gb%90c9)f+k4i;DY?_VX0MJ?Z-n$UQedP;#mnel+X zsZ*-+Hx=urY{hgDL%O=( zGhJP6Dz6T)k;vrO!-&djF9KgX;BO1lk#=4U)5ZbzKJs=nY#Wi8>FQP)roRKz-^#K3 z5p5g@UPU&RgEt_K!iP(5B1Srdr*^^Dv8)c#;91*;=~zw(fA|z1RDFpUX_Tw-5c4{o zLJU3db7G|NErE-0l^r|^FQi#V-R~`(@({w(r?5}|Au-ZOe;L|a-JsLVd(cgiE;*V? z_p?sJ?88qXxBDdakeWO2J`5URXj2^W)JVn7?kU(0j91$ea*Mu2cXi&zN(0k8OvfU@ z@4G1a24bY4i~nTVAmowqNVARY3t!saM{LA4W;?Y;R+IE!lvGx;z3(lEtJxVg9>q#) zQ|wqX$pmQ|XDJctnnHjL$iDXF1;_z4MRQd;g!ezg7g?TQI?^HhbvaCPCNa_>yo%|~ zu5*Zy22*zkQ&xwS_uz>zFPM`yo6@LP%)f0FtSd2=<3bW+9+$F!Vb@btsClb4xm`Z0 zFt6RlpLpWL(UTf_n%`?^)X1u%y?(tRBCCUN4)i`)?OR31cMoeUeAcK2M-I-Kh_L9r z*!*qm*x>9V;wO^YY>(5YIJLPreMqT|T`ie2B&D*CWKU?5pq;Rpcs!z{kRba;T=8%OOlfk3OUf%G9O1r1*OcBz`6}F*ZK5iS0uL7$X(8&Mki=#@PmEF$JN`~$ z6q6Wb0)O+-jIR?T9l~UIKzniAXku$@FF<}@^P*y!nlq@hS>-jg)u3MwPhInPr6mH1D(5NZBh`OAc@{3ZF@?ZAkYb~}*# zo&7j5;qUCnLpW(dR=VMCVx&VjD$h#uZB!v00^5=4oR`BfBH4+@KpJm=Ac>!XB#qNm zzeyNrKCa^FXfSXI|&d%+d1Z}%x9#x{;>IB~>8 zvFCQL#!#>3*Bn^u(s1K}-f`PS=caxUH8=K(`>7F1p9+s&@vW2!#cP1|d4#gfDUpo5 zbr_UZ{3H!Zq!DL42QAp(KpMqdpJm@al6gsU06Gq>DLuvW{&Ii$#27Ksu#)5AC$x+X z;m3QWbCRUl;`V{$5c8g&c$uKIrR&8yyj~f^>MXAEyttQ;O?iOnNP`y)jx(<%M%py} z7BMO3I83{x*<3c!eq%3cztQSd>C@#`li~QL-_yv9O!&^Mg;~LRFj|42$cs5js7srTXOH z^th%L=L<99np(-G3w;hqWjS zQNmEs%g{9mx|5Bw`I#|en@vM_@rM|4%kE2MdsDw`+z`&*HQBxBeE26Ud$_n%*z=2c zfgg9EtR!Nu?*z}b%zq=sa$r~RG(UKr7-=X{?B=kwuz~PC3(RoA#=SS?#S}oPF>#nVc(vY zGeYm8RmLZYzEW0ex;5+2e6Jl zrVquAHO%y;{Smx~e|BEjM-8*SDs|MOUkZP2yOM6&OHAkegSO*tit;O)JI-*9O%raN;=CoZivs3zoFfaE zPjWgIFq`E}X25rV>E;}nu;b+l31(>%7)EP(XS5?WrEN-g#)iZuwO33- zeyM{p5tHeHV3diNgyVuyCSv3tP8Tz4zf4J*-+(?Bh6s7}d(h`@!%Gk6uoLN}hjVbI zKrSm7X6>QVhIkPZ(+1GM5WK8;i1m`z0U$a~3;>`x4Y_s`rju#XwVQ-+;kM|UD~XZj zlxWcv<>^kEg>)|wBh4w1r*n*Lq3Mi&UaT-V^kM~M(-&IK{D!8}FBP7BY;{bg5*K!3 zz22si;Mk8pml$cb^D$^Iu_0;aV{q13zOQ`@oUFI=F*u7ZmrIV}^vr0svt!cc$NZ8! z8>T!9CNIex@r0JAJRjY$Iwm|Hzg*Lq{=o|(HnRhx!OMdQBMn|wCyX?wVwP8@Kj$9G zdM7_kUWBj7Pvh$Tb#dF!XikaF*pTV?yJ77VOFFs;^`6Fbe^(lHz*g*g6h`xTfZ5Gf z-c`5+-OTcCJW4T{2CH3R3SU}i&Y5%wr)>!v`X|$oMsUApR$5>fY4m;V+mdemrcR?q zkL0qs9J?Anc@qB5q|p;j9Wl07EtZlRrNFe5UwRVf#oEgz zjNg~ydwA>#dhopY9?v5c`0qS)-F%N=t(2ni)P{*?o;q^$sJ;yo8YecMdJ;vjFOg@O-KYP;k|yW&9LE^R(ouOHVLe)5QhMg)gMbHlG{cm39xBUgx|o=h-GrmE!oOo>^;&t#!!)bc>(FKh`Sg9V zY|gDLk2F5{@UtwteE~7j{LF)Y%S}G{Am4H$@8#)!{J&YY1Z9h2N#oT0kF)IYkBN~E z`3$)8B`*^rjVm~RmU4-ahEZrc3f4-aU^w80Ed?#)j1X2DO}g-5tEU)W6s}y$LV|=V zbuYx}pTD4}{Xs5Y!LgW$YgCRef@l`I6{}bs&N8tWVZ!r-{Q5VuZ2mH0q;cyW1KV$J zAVwNzs164RNXn0vTDZFMGr{ew6?A*8I z8se%;oOe%+$3NpFdup7_MrdZ7QO9|Azc{~*&=GNV9w){h$5g(TM|RN~7=lj5Fexog zn)@n#Jx%slPC!hq@p`}VbW5RWTa^o>@x1??@%d$=+2VYD*?%`J*k%Uv7&eu4czN=- z|A2(`AHZ}23h5%&P@Znl!Pp$JForZ&`Fhf)=_+5(wv?^U5zH&AfDto!DLdy3jot>Z zzyS^51)Xbv)hm`YV5(uppIVz?bwz9@)74oU=)9z#%}WaP_Bp~Z<4?-NQ`%bZe}B@t za>X$Yo5dlMM?teiG-#Y2(2?a>c=hxWed*qi-_OZp5u^2PN3z0@0T9;r| zd-Q+Xc&fGUyW?dLh@Oe~A}hYMbkrkpwXKazV|J8j%v$eHbdY*IIsP7lY;zUk%01SF zn9tJb?;-#7AF&JY3Ng~~oPW+ra~BgM4bOQXu%EL$(kQPJR@bpkC4H832**Nszu$lu zY1=ta?_9NA*10MjZDd?ei=^`C#i^ zNqjf!W%1^C8=0}=O_(n9Aa|1i3YP~KJv`pAsf1^ZFCt8vtAud*l3vb zp};r;F*-;&3ra3)jnxk9g*&|5~3H8xEn|@N9=y?3! zRK0^X;RBgh^+hJc^Ww{{#I(2xUjftDyonfp_usyR9AzC;kA!7#h3;LP{mY}{E#0RJ zWZ8;gY1}cNtAbt*KKBN{Cn}%%ZrBRMD{>5Q#W3Stf5!*pF$Mqa`@~4|Bc;FnBlF4! zOMm;v5Wd?DQSArBNMr5%Y<$6$w@)Fh7_6MWeX1Mk#TdqVs~YEj@3h(^9WkNy zCK35BN1^+~CTSx}Z@aIv(^_(zFy21PmhVUYbVnPVmidVBcU^1G*8H9r*4;q^do7E* z?4*JHF72|D#?7|nnC8F7yrlKLw9@Z6mz4L?K--S`GD%mpUH*Hg9W{1%&*Lpnc`UWg zAMoVIzcCFgJmL38zGSx`y+rCBohgyy&&aW-GOdr_E!e@c5aaJ5mxtZ2TR@C-$j3jB zWwUIMCLQvzeejSBf*a{Pr169#)=lm~a4i^VKESqM2f8aS7>FnqW(y90erISs51D92xs%PQqI#N2)AwLgYV7{(_IBjlE z)t)f9sP13NCQY}p;AoathS7YjY`%2ittu~F+_TzZhDFS)Zr0tl)hq6-c@d>-wse9m z*v}=mdIdY$Fy*C{TB4~k_;|e1RMUHFqBMDQaY1?^vdmN)V5(SCn6nERl&``p*x9oX zl zRMAumUoLmMd^XOOYq01e18LLKakd=oG98qUPxq9wk>ruiB0bich%W0OY`e&J|xLCW44p6%Eqk z`R_0>#JSC~u_flFG(Ii*j$ov*YF!u$mzO@(|#9+W~qNud!@sDw*VWx<2` z0_*6sJmbzKc~D)6+Y&M*KO2pAX`2sxEE>^Oj+QE3syCmBn<;qnXa@II}DIM?Yeusg9=Ct6<<&)aL2V z#XvaUTrX+nExP08(bgBNUUlVg+Zs(5+;%fGpi@WVS^LaVrfaf#6?@$<<4@ZI*M%kT z0&4@dkzv|aU#cJJ`|a6NmHp_DIN^%@sNnM96Q!}VA02|f-O-O+>C%tj^0gnSJNDnv zcSgYwu*4;KNu%$akA_}Fj5P9U8G^M^xa7(ypgk*u?jQS1!IgWT85Wlzd~MJHtyD&zJK7>%UV%8hD@8e8f`xF2sW1b&m+uw`&VLaMa6VYOPG#j z!zJtm>;0S#jJ;@_2SE1 z>dRG*Rw|R$t4|qcn0fjf*{!#K^0RKecc*o|qV#U0rO+!Vbo+w!UY&$?>urcJMw|o|p7@bP77T(- zg-FB=`t2C##7HDv!jJAaJ@I3=QrV60!j7tGH zX{Kv>yF8s5(<9}W4&=itF%M3>UNvk4P%>tcHX}ETWt*W|9g?mI!35ikdDY0@W;*AO zJTTn?<3-CGXyvKAt+WFgzP{s|J(mpsk&vIbJ7$P4q(I$5p*d5N+ipvynG!jmm^pCC z(g?!foT+4R&QwdMzr*l9g5lpqj5PPs?Y-$-_R?>>-OG@4trRX9IR(VAE9u!_yCl*e zs4K4TxRIxCC`2Pq)5qww)94k=H)VA5WfiFEH>he)N~~(ffTn7nM~uJYbil)D!H0Cn z)nu*vlV-~_4`E(UC#~j#9BE5ub3jjb*&mbNCe7s!pAyOPhn!>}pRB{vT?&8iu86dm zyYV7Xg;`KbD6<3%x~Q%uvfQo}S~eabfb6Sa#ebji*4)#Sq5e9wt~TTi}R zjFT@{#>teglBh+a4Nm+f^aj@)EgCEH!tAXB?m$_H64(4rTyClnJ+q{svwp)H$E{Y9tZCnzu=dajDuv|0^-PM%!-Q2}GhzM?fzj<}*o1;K1jdyAhF&JH(#Sg_ znJ{S+Sj+oT0(0dAo7EnEf&IaogZ;vC5rRTl*}UTTGzyu(Od0Y)IN0gSMH1v+alB`t zApAY#-@~%u#>n&(u$zgI=H%h3nZ#uBa24K&Wx0ZVDSzcoW-#8o482IwNxXU4eI~G$ z_oW2pOzD**@Ix@3f8*WL?kUbd%q<$evam1Lp3E>Mz8E_mC)LqUg+UScO3a6ug&2Rw z+VvD1N9|3FbjXJe!hNi*iIEQZh@V67VZ=yN>zBdgr4G^hWplkQ!M;=@FyOXJc`)^o zH^PpoUwb1oB&`=4VMjE=l#!b@)?Mmprje+TJzCq_EtqY$Ur!DORRo|Y@=zLdZmhjBmLotq0>=<6=< z=Sl14+*Dxn^}R7^_P(x+eQp9HFcVYd?+`eLz-JI64S~0Xz#9-F9rA`1$(xflfwjE# z6IdQ9#x6X!5ZmKSlS}#n2kK%cm$7>`dT!zPs7)qhpq}0x^A3f4MFbr^1s zdseQ$mqN>ji^`oeM&?1!!W1ipVM`fWKI)tFH|SnT>RFUq`#t1c_D@clbjT0*OVTOn zkPo~<^hilbqdYCQ^^)rN+x|OA(m$I{cSt&QNekmIJu!8P+fS>ufKGFArW|4X)yCoY zYrjLM2sh6)OC=rh0T4JXc}JX$IGZhEbjZJjP|Y#Yj3uWZ z(0ZNf=-M8)1>JgIq4iEH=+vb;B=u8DrPezQI{ok$NvA3me6KddAu5&q4(t6^(kbbX z*TQF?eL1BkZBl98*7ZppF5B;#q=MfN4HTu40cAjWpR|~PDUoB3B-P&FT>2!ln6C8q zkne|K(zSluXdeR~9d47_fbjW+}l=>uTle86mG9HZ` z+OTIoXd%nqiPGwd>9JUpDWw}azSNr5Rf{)_7L>3A^LE<6BF&|m;;Ld3RvL8~3Tf9@ zH)R}S9L%zJ$#EM*w6c^2j+@gf@$oQk+H#Bg+i3~e<2zU z%b>FP#}FfJ=@3LnI$f7KlEO9@F+^O_04#6)j59Vs#R*EeD7FVrQ2s4x@mGOogbN3p zpS0S4RpDJ_;jph8BcCDax?*I{t2(JL)x^#`^eUXq08lOWGPj^R`mhaXoRy zwV{`kisQG|A9a%o95-E@EOZ%|zZgOkWcwfTBC^R9t!cO8?^wf5k))o*F#SE`7h{q1 z-ouEIMmkL|SgYlbQ?6>af3K8dc6@9&+HGNPqA15~@bX*8@dM*oX>9FcvDeR?khZoT z$aHFu15KBTeK|R3Z672_rlV}}8R^yQC`n=45PemXTe@F z%w+@C2Y1$J4yj(bv!>V)2|I3UV&2Z$=D1TO>5enms4sgrL-n?Pokb>0`jV>LF~CE) zCyt&ldQ{KhT)kZrdw&TpM97Lj;p3+zOeo*@0DNIUZq$cYx6u9a{c!31%8LBO#5vT85-+rI6S<8aZ~1-5NI`|5GVs`bwn8EkaH& zyjf0brjWNn$S2E%oW9VrP$2#uT3);mLelz-hLCWwHc2#^Lh>#0uS7_$&9x*U|77!v z+tZ4yK(ism;-pFXan3}r?X&SSm|vhv%ZMtgP17(TV-~~ocdSnRFus0mw5OMJtrV!- zG$~N16sWLRC37eds9>5!fo{Ri(AovB8S^600MBBW{?6q#d(JzTU*)OU+%O<+)o>a(dgmgk#FW*YqWEa$dss{nWtHe7%J4gnoz}r)iI- zRBncaj4Lqb#b{Pc^&B%6i^nlJNmYbg+o||$YZcnq1>4h5t~VGOXZjN7o9UzP^UdHR~X4UDJG$WABYbx4xO_NJEYviHzlW zUwJ;IBW>kTUgxjn^V^c&BOO}8%9NKhFm1=mdR>lUI>XB3C4a5#k>!3=7gaG|@+p%V z@FFxp!Ns^uSGX81OWlq}!@`WY7&hQyGbWCv_Iqgg2j;`pBaOBO*L1BEsNBU+pf;5P z6@92t;!(69RNYZAm0|aZOhRRKj0=2Ic zs4#T9>njZ1=F?Q5TfsbHj-o&qy6JDQG$SJ&e}_OA-J(EBQ=qSKnARi;Nh8Qgr=SAi9qLuLmkWfr!?Kt_`a1;rzk)zYQ=n;Iom0@o_mWK`u{czc(H35= z*oS02UPkVUK4d9F%ST5ilha`WAu+R1ApTCL;2IJKao%(~g=t@1AEH1TB@MYig+AmF zMMWQ?KnQ<7!UV|skO(B9B?gD*6sU8hKsTm6Jli_19ET{- zjXV}sCJ=V9R3JKqyfYkz3WV@B3Z%3N^wl{9-IgnDngo&{7UNKHqgi(9Bx0@ba+VT5 zgCUFEH4Kt%IcAZT_un}Vd88oY5Mp;r|0Oh3J`Pc!%_{{eggzdqS9m!JgxOVw{@|gH z4y>46>A=d+$A0HH6a~UKqx`X>FBsP_G(lMZP0)YwRpaz=$QmrT=$8?u#Wk+@(D9jZ zajXU_l2T*;^yz}Es}$)H;OEtlWIi#{Sk3wf>#E`@kd8Fc-2qw7EXU;aqd^-HBMqju z!OGgS@^nl8idCbwhAGYRdcR7{>;2`ovh3I%#7N_D&dcB_Yz2ul9{0nf#lB`~{PRt& z_;T$<>E+tvc4m3m!sKD;#VOLPx8CF}woCu_nAb6B zi@iT4MmmK1G3_6E7%|dptNJU6N&EJGmFn_#5jpGewwSyi>-Fji*XB&;awxX5VJ5HW zq5euYCDy@qV|m_w)R!Am;-&sfmghQ`I{LpyjPkCZ|6Y5^88x*_Cjo0@$@W@s+%qjW zPv(+c@526|*$`8P@Wzg?wSMH8G+xWD#|rB`#7J`$*T0q{tGIoz;wYnEFiVyTb0ioz)`cNNQu@20pLC{?_hLcg*Mt&FgHI4n`DRJB`T%O6)VOn>*^1Y19j zCrxNPsR0M8brG}OYjnyQrmY@aXK%X57Lg)MPEpIg0J zwsTL6zdQSawXWfG{@d<#HXNoHrIoz&*El(?8G6Hg5U=xT^P)2keK{^8#_#hmEK5Wy?`x8%ENyJDr~t^xF`&JUWD*HC0%4 zVRJ5OBN=;}jqsv#pAatkaee=T53UpT<=iWB_FTjs`BexPuQ2Rl z%d2@p*ciKQ4?IPTbO`%D5W-)~jgiK~=`g6jU^tX|Nz1Sj!UtyWr16;gFSG31-(ot_ zAw2k_)b~i6-gFDp^Mr5>-27l{gh?HwLzpr)^+(d|x4s)m*+c$U><3;^qj`-E`OIw- zMmpqu4^J5B(DGWR5N5upd5sP&590CkpDrgxTHY*1JB}bmITST zkq&|FsOhXdV3O!YP3$s8!zA&v`S1Rt>5PU+;;Hoeo*+gVUmf}bbYQzyq-lP4btf<0 zE(?F0WgD#~MjG9>2cng8h>?a#!bKj|ix_EkRqt-<67h`}F=uZpF=sJxafz)t5U|!q zB2js}H&ajmza!&%;WR*;-E1BwDGn7s1?iu#XKs83Wk;0ak%ElQ7_n81RTP)Mn;BHW z>epvtP)cn2ED4*QCQH0u2GQ;NZbN>+&OYOd9eh zQBl(?%4q%shUDf2o`)EJ2d2LX)_>?hz3`_a9yk-X*a`pr7$5S)#@xP}Mh}u9(3VeF zbl)jHW1*?=CiA}Ov5U+<%d>k5CVqypkg7*vI_XehI(alx&0mrxipLP@HZRs#gA*B2 zR)L8&Ukmx3N8vfR@(RzJdoBnI=P~HkOg>^`zbR&ULgZTnW9RbnB=5eMw#nF4EU$-Ijbq=%Gk9A=|B{Y0G=Sr!UN2<| zp&xcCPvDqtG}3>Xl`b&nMmmH;_s&W`4lIu}%NxHtF_wdGCPVSRgmFl{q*2FyS*iJ5 zOQ$p(9*zy(elRi8Y?t{<%CXJB^V|!Fkq-IqUjz1i#f-*n5WM&~cQ<0BLw;}{d?xN{ zVx)2I9$my<#WdRW$2!2 zY9cfwF4UB~vuzZ+WQ}*WrkJtDJKO9^=X z(eR>_yQ^TciFqAr4DhUC^krBrF|W7pgK!3xmo)3xx1l`m-nfI~-((~W{{9ZRtq#&5 z)ZzmWzk7yxNwd89P384|7tbDSJ&hP?w6iz^Lkq&vy63B5NG16FaRy`|byt1=7&!U@s z@rt-~EN?&6LoL&dH`%Bg!>s)zZx5_FX{R)K1)JYQ%-c`(Kbu%L)0<*<8>Y5_PAS7_ z$9vf+Hw5h?V0r^QcFKL?>o~Df7S7#DMiD5zp%XjhK5@k}LIdO27W--8(4cqSzOlyG zb?;8S*}HC2bQW=(O#Y+I*F$*e#EP!#{!9k@4KPk#6UWK$65arpkG(M$)%Zb^c3u08 z81ulq@u1Q!PZJ}JmVipSnJE{s9(~L69&mP6>hlj`q?vc$F;y@d*StJQ-{a1duE(9s z+hc2Dp6*6n3{z5u3t z==ZXce85ifl4g11*TzuqnDI;}^^O^D>8xI_qu=LgEG7-t*AHFtBjzOyH!=j>?+s$4 zF?QqF!$NZzq=9AVA|siOG|IarEB)r*R-V#qzxn1iy^d30J@Z~>I@0*~^ml<_3tHqQ z9m1Q#!OMfhNQdw)-fHy++DT*brMAR$t|PG*cMsG9+C`#HYZv)_-+|yydYHATVq*+5 zdr_CM5A%+Oj`xMUJ+@|Ew-+g|M_>fwo=xqv5xVX1TZ!|{NvQ?VbyB{fhJ=H^i zh0!NPr;+?y%}=fQZ;pJm**fId2w6Mc-Vt)a1}GQ)o(K89ZW#L0_^nvb_^lMnm*YUH z#NaH6*t`2NEZ}dJSIgm$+_f_?8J@d#MtRatZ!S-VSyAlIq%EDrcjU`34_mB`eIA2< zFh4>XdW1fEY*$`y-#4<-u5F2tX1aYxSHWz!@_OarXnAB>+KMzj@;D(&A9++7zC*&H zi|7v zdNDson!f(770fGr_pTLegZT^#tn3gZ+?aO*(~%DOtI(hM2ctv2sxJBmqeD)6VBVrW z+!v_+w?`X@e{fxjO;}9d-E=NG+;<53~X zw`d=(ri;SrVl zMRI4R9#g1C;Qo9kOxJ=&*jmsCO2OZ49Z50rmN?<3fk%;*Hdz)~=^LGC4aR@5iOnyJ zuC2|sS@yEz3#8-JS^=^*D0 zBIfkKp8~r@(qT2z=o{f|r$77`?Cc<7PRrjJx&WVLPJb{L^MdhA z=d`z(4i4y?n_uY4k#w!H$3A!pA9>q-9PLp)Bqc{325c3#W#hM{23A@llOhY|0|%LN zm)*+&2oB^J!T<{n_&awmiM57bx>CYO7L+>gD{=U|Sn5+jYg+n^f`E5|N|i4V5;n{)_A zVK2%*E=@XwlQ4(y&!v&(Dy{QJnQ(Irv2wh*rZo6NcRg^X@uxIZU%Ov9FMs$niaN}q)3@wmM=YfBj`&s_t?bQnx-3rrqt^3+?F#qm-bBM;463V5V-O(WyKZ##F{lm`#pQ4&LlF~5 zy9;l12uhj9F#X+s6Rb7-8n>S%qjql7i`Vf2?25P~6^;7B1i4Y46U{Xm^`&v98V~fX zjH}7nCKO292!ZPI&ms63CZy6KJl+Y)xwIU63}gLa8dQWp+KlELrYmCg796o09=6-# z9j23mb$h(ShOD)j3wgk3fG8=B21+wsz41~kZ+~$MP?nUpe+|?1Ur9`j6*D0p5nuCWjj9rOfN~sE@95O0UIBw-%^m0bM;lLvNV9aG%{ z*C9As0X+5{A;#Z^u4~Pam4bWH_R zw`sIY-QBbxr>;L(%^}hR6G>?VB`3q5m57n1$@!P-i&!1z4BB@subd(64?iauY5L`8 zhVaX7hJ6mOylAdI2e2s}6B8M_#wB7pHJeS%Y_#6iG%w6S@7%O&N#+2DD3hStmgKtx zg0JqgYo+gEQqJaT+a})n?CN=l$!xB+EilN^XIH^m!>@6RO-?ahF$d$ePn#4!L-*3@ z`Wzb-9nB#mM`adLw^dvy&)~5|RU%TKHk{76NHVn(_Qk{W9LRK}Y2kg2CFbewKNPXp zyTnLS^r4{=tJ{j0^prlwI`hO-^?^<4c~$jW5o6xgG$mB8cW&E-3f1@NoIHW6zE`Cu z&~`%1|43J~4dyc1cB0;1Xi=RsY&>TuFjgBwiCIFOiW96KaM3H_y{r56n*H&l~^5mg*2O< z=3V5>6I0cH%%=3bs`?FxF>lqTT<5p-{0yz$59oMz)O?#-oV|i+pVoEo&_iLm`mcoZ zq4GXwBa>(s$e{0tLDk3+2RV<%%>C`x~|Nq;pl{>~?9M~@>W&(n?`XA)?-^^;&|L$7|iWY``% zIzEEm1B-yuI{CfivIT<6ZtPOsWuN>Wejko3&nR2!mK(cx9>er^VCd70T?8Ym<4-(M zo?+p^RautmbOKpvgU;!!d>9+D&30Mo{tMP#Z)<}UxCgN6S@F5mEv#~p=R;KfL;QVQ zFqAS=*Ws)*V#{CFbvP@F*u&TW!`hsu2k7PC^xBjxoBX<@a~kV)m_Nwe?_=Gj%Pe9}54;VSPQ(#58hzurzz&jhSW7edU&|9_bZO|fBIb1I)*mO# z=+YD0W~D)xsNxk8=pRV8nCXlz zSvvxx;>!*zYZvN-?N%{D(YzltEgV(`H2Qs<0DU=jp*Ed)$n*U3%Z`w4EENYHA#K9n z&5-E|Vxymt0=yu_^qA=RmwQRXP-faK5?*FGt>t#c|GFERVFj87t)yV|{pI zx(AM9ZbyuC$iJ~iI{8aFv^+Zs={T1#IZybMm3B+6~(nL+|<1Zt33B17JnoS?gC8& zv|zv?Qn~!I_}@&llxJ-wt`KMB^lcGD9Dw8wUr z*_qxVgLA0cy|CX9@1zwDN67UYtisigi|aC(2Pv8zKH(I^)#p+W(pbNEC>jzXQy1spkc;aGlzqp$l=kA3!s7&=N59Q87!<(lh&E?ahZW7L&#w|5S zbqrQ31S5@GagcuKPl%DGiPR&eD@%7B+Tc7(r!>8dgAYFXx3U-TBP?XXOgWhSnXiv zvVdXNPB|Y@z#erz3)o7-=;m};pwA)1`l$B-jXL@qZy2Ic)wc45zV!!0)%Or1&1ILk z#(5F)zQi(WA7wgOmT^p{xv-uhR%^U?d6cod4#iBiV!Ga|s??!!tiScxj^F9l8A`G$HYNGOM{3Dw&qTJD-+~j4RCUxtS6hbh_XeUd32ptgfe z#&w8v+C(_4AkJYXj$&VhII5k^l6Fj-;(CcMpIx7{)0QlWIJGV8Za%@3t|w~?OP@oEy6ywWfI3?fZFt! zYRw(igl$tFD;nkI5C==Ty?;$MNkbfr;{6duiLsHU#(d*aG$tFDYKT@IX|GQ5eib6B z#=cf5V&RQx*VyPJVo_ryumo{>f0yErM$qy~VJ}r_iZfuer9&SZFq+~JTR(9uBF6)= z@^I-M`V?{duTv0-*Wf^8_CB;JnqJ&%DeR*7Ud!n*oQ?5XdUe59v{@d?9gcEupctfW zjdT3n&T%QWPL_H@unuWcvgRBJf+G!0g{PwbFXZnwW~FXdN29V8K1+!lXCTK9 ztcjEk`6JC)wi0{4umYn)z69$Wn|(rzbjY8dk3*D;h>_;uzHL?zlY@TS;2o8B56{2? zG1AVKVAbU#T6s=QqVX6{NeH5D14~e5Df;Zm<8T724;@e^#mhg5z6JaA&;f&qU_C_`<((mGJOz! z{<#i*WGhvF{|fl&Bm8_b@nd!OIkCWx1jOHmzJ6Tb#~i)z(dR_)a|ix53O`7@7t&7k zJjDL=H|)KA?7tCX9-MX1-vq0!>roTNpVlyP+-dT%Zo|m&BPL87-LNOmigdscJh8Mk zFraI3x(#v9)I!uG5CYMu_odyG64tE*TmE`nB=g+}<_@8Lcbq4@ggoM)E3$hr30wZU z7ekDBfNA=2Y%u!qsR%ZuZAjyg@!6PXEF?x+4<%>wzC#QLltJqO7SK@i`ScF*>B(1bVi4; z;VxPBFzYosgwnlPw#-5u(s;Atfh>E@_#+KolqZ(w=|0#b%l>kRVmaxMzjdX7$d3Rj5tR z2z0ulQf-AVEW6s$2j6f4LL2+9e=1X3XNsX}#}3K6S3+$+BBo8$U}|enj3un{l8A}g zp8dCBtC*MNU_`+R-on#}kq-H5FpX!`y*nN9kNyF*ZN+q?O+~EN@?g}$KGiZ)CFzjQ zc`(c5n4pY!q(gqlN5Gnikq#|?pBpiwL(4++z(=tXfxIn?&qt4WxjIG}C0&I&bn&9o zRY@H;uopF_3u&cauoai5XIg4rzMa1}J9^)GdY!V2j>R586 zmqbihefU-XO))DcDG&kW{-KQ8`DXTd8(V&PfU8p!<({qEPRic z^pu6~v3D#&^GhAlI~IM!-r<<^4q)0N3^SU&!^+d%f%3FREbgl18O`4D@T-DVs6+S7 zJN>Lu9qERAR7djaH7(j;r47HePIW-scW;6^4pLUsfxxd*9qM1LgkD~frqf;4HLxl; zy3&Tdn3v_CcT6wz4yDl}zL#asT+ei*L;mqE#WIPJM!n0RmcGPDn~KPbl@szm{XENF z_<-q1qnA9KWiKr!MjAclQ(&B58jT)zMUVxw4k$Fnwe zjO{EXcu7o$?@sFb0sPI%Loa(6S7=|m4SBC6MjDO@O|oovVx-YKFx38mA+C9m7-?X*IbrvYj0T2x0cJr>(gvilDgOqx6(ig8fQ=OM2{bS;cn2vPFFTDd{2*wm?X3`-)0kNNMqAe<(9k^D(b0cLOS6(H^K*vU+0GWCdg9!zUeR7w9AiA-RQHB z--n6#THVOTPv%ECXaoPkvFK>|@m>(+xbIc!h$RtwqC0iO--xlCkpFxyOze*#Mmpq= zA0ERuqoKFn(CIl$N19zL4m{{uao`afMccC+%xp22$# zVmi>ot~FPJyrpY5VcvzOr@RYK5BWnMKyUvfMmpqw>;=79`;o>hT-!p@RqBl!@i$cJ z?U2;BTyN=9b2V#1-tLYHy=_KbRBwksZ?JLyc&qAdr0H!W)3w93U2%UbiP$zcS}M<{ z@HZ<@%YoiDhTaY)MjGw?L+I^~#7IML--h0X5hES)4_{5A5oz|f<;IKW#p*-MOB(uU zmJ=K-kF>^dr7lP-`bA6!T4TCWm!pUwrUM=Fubm7xY5s*YF?W-K&H6OtTWpftB;y+Fo}q1lnZlQkot2-& zO-E%}xVtf~pT~zqZj7ngY{|G~<8PKlMVlMPBEv;}@rhK0?)<2T?iJyaUkT_4BGBDZKdqq!Q_ZLRWt z{~Ge{&GJa|RgI0!FUYGJ8^bSb@R0mvI?|!#X&iXA8-GS4Dtam_wdFL?Xhub!T&j7s z4L-TlBBeuE9%V9(n{0~RXc&3s(+oFqrIB*1+ctY~rSp+wo3e@sMRhx(Xq&#YcyV>x z>~;h)U5ZTmCQiHI6MMQGd9h*oJ1|)vRE%5|ZIj+_0-0$C+jM4*j|b37a8QWZO1s@3 zw*@qnEPS4o1~R|ietopf8q3(NV6I!x$Z98)nd{e#VQB>nZCIHob?al8Fn^W_c9vpl zrnTpJNyIRx!Xl_)=P738=*mQ?%R?sP zXw0eL+Ux-tqpgw2U&P?@OK#T86Y{^W#>*ZS4U$$jjMgpVIY+2d>Vn8t+$(8@HI7M$ z)8*GN|6inZq+$M7fWMnHuhBY3!(uTptY*lG&!Dc1N+k7Tbj~ zG2MSNb$mDy1$B5dnfhI5C{gm$MN=0L#?-y-I!qm})4z+js@t~8m6~(+ww}i@{T&#r zr8``#4-Q3B=hKdpk{fnr(%TUwXC=KI5ux-}TYSmkns_^+&E~YczNeMhb-@jH!@2<0 z3j8Gpwc)osPt+6L=(!@X&nOOtKR*ZrNf+^~Q{ zGPuu5+r(xN665#r_-k$$4*?>r=gIKTf5%__O|VKgtdBBxnv!hOnJKtoXXV!9h8?Q% zTG6I)ORCLgw5VQ_%52j@Rh0rh_X&&v=5y6Hd;P?73CGk2+S`6p%9e;O2&nfuGwF7AJnX>!P zh$}AYGdm!1lF(KD!-loIOLOY`1qU8q$=SZ5lUQP88i!0Tq5!B=7#P1j{$f}e&+cr$ z`)`u2dXtsy9q|Y~dh!%D;&YKtiCI4FhY@XDJQNVam^l?(T2f@e*tF{sNO6p^24o)qOEyig8tXIWR)$<-j=pEJ!m0Sm3?z ztZOYJY-wyuOH71#xUu5m-TOSJp3KE`3$NzXlfPMB&0`|pSB`zq38B1Uq!AlEfWE7~ z*J(~6wt0YgWeTy)0~~9*-CYHnT~`o zZ8}OipYVw6$|L>~8~a_!?!{O-&4YBBz8o9$8XjorL5y?= z-~SgD)ITIf8fW~W-=>blNQW?Hmn^$yH8IktSL+w7O1JYCvg!6;Q~QYEx1)x%XPQl+ z5X-y71HCm%@J#l1D|%38a=`q^bQ#Jy(J*kcyo(n^?15voS6NBKa0XEpbOL{~yjl(< z#{!uxuo;b84nyL?sL`lH>tbH!!BaQ?iEGkE<8khv!s0oa8m$M7d{mP|N1$% zc2l(EyW>)KnI&%pYn%d0PQy($WgoNTeXRY(lJ2JNn!HzP9AmCub0UKP0U5?s-47Y({D0xGY_P^E-n!oO^KFo zDS7>OSSVV^FM*MkuNc5WXE7aVoU6Ve&10P2=wwfaC)AA|g#|soEavp3v)q!i%xU>c zOC~1tjQ!n`6Ma#gTXL2;?Q*NU((AT_Y;c>DZGEhpu@j;Q_tSo$rEo^p547BsVv=~E zCGAA}#Tz})avlz}bcJu$1sz)J)VpZiQ_UL17h@k<#uwj*wmhDm?ay*x-6y1nv`Ax& zJsg{ytC)^-2t#2*wyS0|%i~`67g@5lMW?@|wvbahmxH_X(V1+jHS}3=R$a3gcgJ8a zYgsZD!8MH3{AdltvdcFjcEz3azsyDKwh!rl`5Q6j3E{}`@U>hmG8*q5VJ^39d!{38 z*3H!&`yJm;K`TG;8Pkyt;imsh7Ec-&q7{ocj3(y3R(=;>JGY%%sM8@_zm;34(;-kE z)~n+JVsf=mo) zKVdFOhZmo>hYvn+8?3_3<%!KCA0)6In&B9iCXR$OpG*Qyl)j^Jf)epc_&Ht zMV8ESaeq&8i$J$yb1a?ciI#kI8W|VigK(IitmRKS8>gBd$((5Yz&-^icSqtF-q z(M+d*^fg$m^**N?Fl6}ynNA=7GmMrPz2%?NF1K66a%{<|)v6rpW3_r>u*2&~d$Umz z{KNFw$*&58E-`&+!LQy`o%8;s})XP>cv<(SY|V#BPqK1SHzeH z7=D|+v>cO%Pv>n*j5Kt3YL+c|nHXu#rx%!Y%Y1slt1ORoe32#d^yEjWEksDPMe~ff zl$D)9hL;x}2*NCM%YS{LC8NKN!zj%gBw6;gHne2s67I8Xmw~io|4mwwc_8H^Ncp~` za+)KGN2oHoJSV*ct+qUrryKoiL<0{IBMnQw&1V-*+uXSe)9Kt9^ZozG99w%|qIb9i zQNuBkF3X&jzxKq0VnT0^?I(L;BGTQkEA+bqHEZUy%N;E_cmqqi^|53#z3@NQ&lctn*cvK~RsxPHnVXOJ9 z50;90emg;Ga60G%$}2A-CJ!jDyaY3CISeEd(_UD{0PA%M46bL3bwP(Tq;*zFR zxL}9me>)0?o*RGR38oxt7^0r3J-rxW;w={J;Kf)v&4YBBz8o8bv2$)GVx;ll^f$0F zbS*K`^ia3!TCdaeR?#QJTe(kOu!H3NB1`6(UAR|o9}yfrc|rRMpS&VH*jICZmR)yB zg(VlFiv{gr$p^r~L z)AHB-w9_~I5kC1*sUyprcDbW<%h)2;t#Yi7b?b574sTO?&|nGPROZpsuP*GWDG2*6 z#uu{O@5VeGA-OEz*hlQuI3<{nKH)(Ef2ZLR`y!*_DdSI*Q8`;TRvJ}$_OAx2`0+Cp zM%B5%DZ;S&?VVGk#(Y)WBXdbQ{ALTt{+me2JY1gg5J#4$=HaW4!|>OQg|r!!Eg3i_ z?$Hg1w7R-zK;jCJi<14>f(vI!H4TeX1KVi9~UL zm@yjb_44wii0_{GDeE8|@(IZ27-_sPH8f$Q<%KEK`!CIFbZC)FNz35DA+OOmp@RAE z#}Q9Ruanr|af$3@hVqlLy!p~okr(-;SxJX{ z_M1s1q|qb3kyJujdqm04VxdQX4lRGfe3_2RY5t|-avE}+>oXLmL(5w@C&(F!)4}9c z{)~T9lgd$5ODgSeMLr=g_o3# zO^gLCKg!t#<@{XPVd`r=7csd(Iqv|&u2szP;C?YmxBFm5%eU2&BP4C=q{F0YFErJu z?{^-creo55Fw&};ct;Fs0xd5crgWq^4lTpHAL`U`Xc=x*E;=X6euHsOFw!^``PVGF z={jN${Ugh6Sy&yDd&sxFYk8ICcr_34x0s-MlFLnX>mI|nIQep=>K;uKVOQPkbVTBD zZSc}&-PWnPN6~ECL3KYPi*lb}vt2zGF*$U+`I(08s+i@0>V5##AyO1kNJDi`p(lPu zjI@nm6N%|~HW3>}=r!(GNn3Nw)^uJ+{^1Gei5S~ZhtW_mCgA^s`UE4bjy3ydJ7RFG zpc!g>{0cD%H9mfYYW?V7#Z<)~9SqfB>d|&bVx)PHu=65f(gvLu5!?Js#i%-4iCL~Z zSM7CNjVtW<;BJzRb?GumT#YNd-o7;C<2qG1(T%if%a3w)hU(5HHV!+F;zXH?*tFqv zqWsPBY95SrzfEc)jS~|8m()qxRI;WluQvG;ZxEB_f8q^Zb#gVyRVO?kE8|~udZdZD z(-Tab-sR6>yuxf))JZzz%yBl-3*IOU3eb*F}kI9o-6Am zn~)t<6>f%ox*M8$iel>E-g(_~5fcZuda+@zTVBnBroJgTGtxX(<=dcgtZLZ?47B57 zC>%~)47GsV^LB;9w9Bo5bjUwJmH$L>Wmvas(VSo!RQenvQDv*wmyvQ%&-0$b`{jM~}d}AtRBr6QTo& z{5oOYc1_6dnuycnX&*4&qe?s45lUNw@t9@dbhTf>Sr{i)@iIWybY#=745ZJ)mi$8Wi zh3$ubUX)=T)@YWu#no%2L#uCLZQ$*4 z@4Z>+P;(iiL;kxzWu>z*sg*V$9rBs`rVp!=4tZZJsrkp&Nkbn8rw^->4mowj@_=@738pP=H{LMY+IH()XWo^;#+G&K zx>tb=VqzsSP#TOsI;cOgg*2sP5Qs>O8jU7u6`EKk{{YirWGl#6COTsK9>34|p68zP zwznGl&wcuRpXYqeIrrRi?>+b2bL|v%yU%%?Eu0vRwQ}VgxxCE74Tqfl%&Cbo`PY(% z3CWjFuSllx=%`hb^~4%oc-uP9(~Ps-RQ@Y$-EjIm#zyQ%A+5Gley)@JV5rg_{>YF0 z?lUMguloFKWkTT^U0KJmp8WP>o@aIY9mxDk%#T}Bi*NT~v`z9uEj>TM#Cc4fm$m9R zev`{28MNP1#QgaWd?tC0s8jp%?|jx?fk@siV+JuM2u}>(4Pd*iY(&KA!4Ztk_S?Qo!rO)p4$@mib`qTF(yZ>dGueR~&ItnV>((NTIL z;w&O~gX3&t8o!csHqLgH&Bo2je$-XA)zb6m-|QM3_~M=N3cz~1R#^@mrko6k#qILEHd>Wa)0V&`blr}S1DRwtw`EU z_SWuB{`1xg_B(@6?Y3MfjfCk?Cm#e?r zuYExuH07foT~yE!sEug_b%T;29l|j`rVj=)xIXGkOtZci^+F$L7`!iNasD3F?DTzZI%% zpz4q9ci~|R=xs(x8UnWmMsHW4Ctx>tc3Tu3``RKligavfDK`D#am2ILW>m=DSZFVF z-_+LXOO7EC*N0_WqUc9>?zN!gH$s(R>C}?bA08u~t~R5D&Zarke}{dMFZj|7uKpE{ zJ@C^XEP{Uu>itW=oj*Ke9Gumzwu|!cU=c&EjDu=c^t;i7Z^Amr>%x7TeHYYrs4GL& zbxF=29tC*tOzdopN=5SxilZKVnV_R6zbAxbmq{W}yF%5Y#b40a_6bI9jY>uHp~M3o zorOElwYx${HfAEV?V%c?Yj+V>+w0M_y&9E@-oQa398|8xW1NVDUDqE{;)_hBZgZ%H z?7Duk>$Z4y-4=~XXLHo#QP0MZr|j*2emSJX7bF#^`$E;T#b4Oi9#*#48kNrGvrdeD1E063;S~xm!auWY5XCEZB3dL#M4#>1?+1 zlb(G}*!U#%6Cou&E2%)O=;b|I{DqC}2`#tS8kNrG6Qw6T`!!)3bLtZn?7vAWP(Ku^ zo-O{u#ug_(9^PVWR63iFKc4bzc~lPe#9u;6{8y$j@rO_i*%LDI2lm7%&z?A?QR!@s z-($!^+nTKR3HIdakP@F^Dw9*88nP!(lRY`(*^^ipL~3htDxJ-~W}T~dgfMJqf)@^Rk}PFlj#p1TLfMU^{Y#P=?@Rw_wtfK zZH-C+vrFmm;A@Q8g4^H)7fNfO&MpO}KRhmaFl~)W0kc2Z>cP@4pnVOQaBpVuI9=M; z&}^vseQXy*x9w}_qCjMSLvv@_q1hBLJCki5EGumQT$&FN*{caIoek9xT$(4Wbisp5 z_Ed|s&ZdCblWh0ks|Y@n2@%;kf(PFS)ew9rL-63+9z6KAMx}t+jqLDXImMyGV>gG0 zY%P-*yEarq@Yu}+k2QMmSffUzfZ2!OojcceW-*pCgt3zajcXOuyO(NQ^oPg2zH!mk zs1z_ekewbZ7ZfP*Xh&GKY@T@^y*^aK5|4JU#G|-<(8e{|qEQ}fKi0Vm|5t4!vkJFW zpN1dq;tJodxHCoFU$_UKk_gtK#vT``voD$d9baY2(R(Vrt~TY%k5x)&xo6H-N*||J zm=+E!@d~9iOg@yJ=Dp;O70GOn=p(Mswh$-`Zix#|QoFEIuv!$ab@pjlsF^pdpDT>j z%JLctVqIzIcjk{wkHztRNYDCpx|;#<69x<98R91urhd#TpK&#;q@UcXH>|{0T_293 zbqA=?w$pF)OSm#E2R6#_x#X*D&W5&A^2u2KPEENQ`|m-_X+)(*}AoU73pc78ACtS!u+YGjNji9 zMcdyYmo|qccJL9m9j4f^LYtHL@$ldZH@PW)R6bxwp~|J-RU9EtVUz=t8@7)mV>gja zS)J`LRk`$INjb6ODTI{XOU>Ewv$c4rK0?je@gvK<=Ir>EdQ(0)L_cT8RlA{~%fO%7 znWx{MXliHre(p7AXO`{rn%a-!VfjHj7XnjKoPDIql=t9#C4XuUKPE+|rZ%es+EU|V zu7d4VMDDk~g1?RxZ(B@x^<5PejOR|(y_FS=LkCUOIb+*^prcN+wyem4kyJD#@uO|Z zzu9QYYdWaWHfGs(OnGg+)tqfi->lbYW4<|7rcpoIm~Z|IWUI_r+Q!VjWXj#&qo#IM zr)ubOon3vsuQ;_?OvL_=inBMAIZQ;?6V*2`D2df&7E~M_Hh=Sj7_9E|EtA92&KW`X m`--D&$`76M6-OI>T^PRRvFmL3p;a`opL4e2{!0O-rv3x%l&h=& diff --git a/impl1/s1_impl1.ngd b/impl1/s1_impl1.ngd deleted file mode 100644 index 517dcbc66cfa89a4307d5aa8d200e005bfbafaca..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 884272 zcmbqc2Y3|K+TOmXsMx!%9W0pLgk~kAKqMp~2`EP04N1T#Bryrig4nxa@46Q31$$TQ zV#VIg*t=pwz4v@3TlACXOAgise8Zl+ki1E9Yji`oijg2+q z8p|7}(e=;Ea9vq7wWgwqF2Bp+vZAr7ytyjdTr;VvskwYoLnyTBDEdz*JZ?%&ZDn?9 zRbx|4eO)L#=*2|^Yjb(y_^RfLNtK~+YVDO4yXhso+23R~ya;}IW5oo7F(i}>qxjtN zCI5|bn3M+k2gOGf3B#p;C=z5O%Fd7~MA7rm%_oIIL*|C#d*x8Vj5)JrW!q-=WJ|J5 zY0BV%d9o&Ec63djby&Kk^q}G0bNaK>=ggSV(c95Z*P(FaP!=B2*`J-;I;*oin{G*y zIedGHl;Pgid09x(Wt576JeiVny3*PH_O@)>A+23q9ka4CI%jk+;d&xmV z#|$I-AtgoW+0n$S2QNG?JF~67H`~_PN|9&NWFNYe?2&n$UG3fTved4tGBAX7Lt|Y{ z#gwuN)FHHL7?9Y!9&&&{cY;T8ISQ8rbPQeYEYRMLu52eR3n-%5rJzNbyA)9BwySo- zr4d3$S37LO3JQe1YeA90WdSXv%Mx5#9Z*ZPg11|NNB>%tUTWbr*44L^pq|4W)-0$c zRwKm(HQCKlC{y+2BPv=l@Q{%pS(IPu0Fc})A|46%W;1Zhi~zS_LK24CO-OsGRS3ff zt6?NJX_?)`<=H)UtPCV{Z!4oD+jscvIrCfF=kx%wa?yGB0oRDz;F5i;h1kLwD+g1LOr(0O z)xr%@ZdGyqhJs_{pcnCvvso|#$5~aJ;RO z(L}2O!R~97Al6!|f!M1i35gyEPq%`iTM)@an+0wr*(@l!&gKWv)!8_xK!c5g_!?{+ zf>%uj$1&N1nKhVVcp%Uzc2h43-O;p(wE`YtvUx1wNvg5LX-8cfUFr+3>@U(Wf0W?P9vBt4mF4^4kEh7feu~`-UW_BjU=dC576#91}PLCkOma~cs*tJ4UdtxN5hgnGJzNSCXo+j*$_4g?`$?O(ce)<8^qjKxV4ancDo5#XtN8^Q0;aT+Nr}XL|tdt zO{nP%yO0R04uNT~*a>!aQM6sHv&h^Danx?k(zb-h!c2e&+)+>X>x4g%k*whlLV^wh z6cIjWwD!>^^9Zueg0rN>O52w)W5!GcL1Dy8`zf}#Zb3f$50m2&8lvN5L@@q zsvc+~bGk-Q-m<+Nt?k*4uGZNotj^LOMcZ+pUl-ny8qwgIq zhsdv}P_NuIrAfH%ljG>H{c_hVC1_Q@Tq-8xd2+Fs+2_cW1d5>M%EcIwbL0?930gH* z?wW!UuIG8+(9fs;6uF_wVp^H6@I%l&D~r2Gqb>_fAIh6Iy7d#cZ=-Pgw#biw?+}jg z#l&QPB$(cJkbDDoR7r6jI^d6 z9}b!4$07MzwFnM*vhe5_+zpTQ#Y7&DMd3w#q6LrhyhSeyCjH$oBYNg3hwDQ2dM|Q$4x;LXpWnM1jP+_OMoI+aJ#P}(tNUdi$5+e6u0`~ zX4vm-{(|PS+}nL|+3l^qs2M&GzRg#-XR(4GGLa#JiQp4{ovYvA?^|4-wnTdl6_ckJz%_ z>&GLu!T0&`i0$hAeu&tCK98b{+%1*pYd9|(cf)frL6$e|5Bj1a+UzJ~K+00HkGU-B0Wzvz?Z z{r}4W6yhfI?f?qjn!gZ0z;_rgtn@JhTF<**3{V2!?!6qKgbd%2yb_=YAqY|g-;lf% zM1dQUR|CY9;r{VzfFjboUs(~L3~>+odJqNQAFc=z6?duEf|S91>a`$ca36U+h=QB^ zjUZ8RlfM~6fhK<=NKoA5@A)c1+)}>fkIOUfJN_c!dxN+Aae0z_8!;3)L(_NEl#jRk zdFDINci_3$4zxwwRle(wi<8xNeT9(b`|$VkzCz&j>VuRoF0YvH`{VLW#4zCZN^cq@P|BZ)uC9re^Ps`mSh_S87=4U~4~x@G7u1 zTojwqX{`!}xAEhXwll=^G#w4{c^+xcK}ez(&?#Vf>Zw!IIRY3>Hw`|-)8 z?*O0P8<_)24#<{Jjdp<3;#B%AQFti4Mx{NWli(czb4RgsgA4$T0M=OnE`2B;xY%SG@G&qHL!iz{Ow}L3C|+*jesD z5N4Nx0T=R|lw@a@aWT8dz36e!+rZ)QE^y->WCn$Y*{*QI6}F|s;2_@NCdJGNT4uOL zO7@Old39zpVu;e~w&Cz@kTBNSCElHFp9M1{TraDHfD-VPX-9JpgVf2W%hIthsb!ea zXkz=9&Pn7Zg$F`L=7mZqqY^4jIsM8l+tc0G+21+0gLjbnYn$Ql?kbL143DDqO`4fa zY(&Wol`}#PX7Ju`IGol(?i^qb3$Ro!B@l1X60Q{EtE4&VH?&!RT2DNB#9#m{sJt1e(Yt?i;4Rpdf6tuUW#5bQgmx?22Rx5~x` zHgRNiHT{Mu9Ijvp>zu8Z7bdeRmtSZ_nbj@~W%8;u!49EDI@q9X73pt_( z#^Z2;9YWAGIU5@jV~vd^obGF*iByaOFT!b}MU8~}7KCJ=?L=Qcf~_rRE$OFM+6jUp z&Ms!Q_IG5vI_UT4;bsV;Y;DVSiU8`s6os|V66H?>EygtRi^wOzVvx8^CTUg+imbD7 z5MRC3B3h%~Dia-LGFWRGL2+>nFzJUXSntVKgGMGJ0ulLSm?!o%A2aP^sAT7ZlWIsJ%=S~I8&E*&TPrxc^KcJ9a;gVt=SgRpql#n@Sctbh;=0DtNIuNDs9qgeFBOepYGM$O~9tIMpo0a5$@Jh0X z8l-jq18XccZ6!vTjhe7I5>q?1HqDu-EN?E)PA#vksm#{YW!q z)zpb{&>(tQtm#e#D@qjPA(9j%D%BH2#Kp|cOJhU7LguP#>S~%MR8^WCtH+z4-LJ8R zJ{w_l!v%;Zf^LkRI!zrdql}kn#TPH4`WG+4;a*Uwz3uHdoZHb=Us2n`^J)p&z}fV= zN?H*0-d?z)iNTD3Y;$0XS}MRv>rXkY*l^EwSx1t!&t=6uTYui^0p|yOE-NOGIW7;F zB` z-pS_kkcBQYFAvAKobXJ04A^Gw(0LYtXj;&57TGxHG{@RF=rG6HIOrC~SvmL^1eriu zU9Y$~0K?(qLABetFB}iP84A{?6Tmbr=w~NbIijze2$J0$ce@iowcEM>oRo6ex$RGK z^SRwmcJsN-Pj>UUy-xwZ!CGyK`xKCkn&A0aID9I2riokaR2z$X!)Z1aH~DEc7Psr^ zFojVj^)F-TKHVneA#piOvEFw6@Jcv*Auhw>Oo;YL*r$k3040tvKLHe8oCk?~m$kR| zX8R85?xh1pivLU&+wJI4XBvF>_h~R#&oX3g82#uhsAH&!^XoPQo^80cgaV&u8$K;| zI6FhaM=x3oe$o~?SXpjq+7$4{5O)`em`2`di zI=_G-nhOdjDsw>rMVi;kg+ifq%{GGRVh9S&R?^wc`=*QRX4?5TRg{bSk8=RUOef;- z?V>yxqXnbbBwh?_#Iz!!3t=jhr#lw(OHwur^|{1Or|`sH>k1oHw}HEcQJQdhrBzS; zfLvZ_m9}N+){BgngJ(oatbx@_$Y8|Trtb}}0*j2ZI$G&TCbk2t9yoKX!*1|XWT&hY z_y{2Hw36*I*kZln^8u*%bymYXSn_!bWga@p)!-z1+v!sThjG=e&XXam8$`vf0Vg6% zRINcP3Jg8S%kpG0ik^o)b&bt}K6q`)%0U;t&c;E@F0paY>u<1H;P_gr2ws+04Hyd7 zTP5?*L9e$`Q0p756a;sJm4P90qt$>wZn8=c>rG&opTh#>W>8EEyxeT#@M$VpZvoH9 z7UH|bMnizNf?~Qtt!}k(Q1RPr9Ms}A8wc6C-DaU*Vur(a*ktq?FPUsC`Zz{7ywuJ@ z^_JRMWVzE$LRIdxk@$%BE*p#9K@W%Tva?W|yX`EhPGmzZL|vbTh}f_WK(uBLK4&)T zus)t*E=`ds)@yz!jQl(bmXW!ZG;iPT2hFtcqIId2#_PvDHcJ|nx!Z0+UhYYS3a+wg zTKVs+civF05CtkXE%*GQB5ubt$Eyu^A=)CvYlIB(1BHg5D~c7I%nC+s}V$rE-S$MPg>X29sNPeEx~FtnbwS zpHDgMY<024Y3Onn8y`gqhnKtf_zp)n{DPZL);GaM?ZsL(k7t}$LA4msCtfmbvyTWAfcXoJTTw#)g4Ri3T4jX#GYYr`1 z{SAjLgSx!v5NFV1UUL``-s=uEYW2EnZ#N?F zckCvV{G!tz+U9Mi5vhIGVPu=#;XJhCdk!8PzGJtcBJbIyNZ|)|7IN^hU^ViI;fHn{ z0laTFAsHVCiP0sIiVy83MESO1a(veaPCv3cMFl=KOb$A*kKn4Xnjr=a^nwWm{t8ya z`goU~)#7PEc6J&Mtx@nd;DmeHd$PT)vkAigD(lnuv|%{>Il#4yMN@2YUx3Xlr-fhJ z=UdK!6anj-WS(y|kT)@G?DLZpnH+k)HT@*-2Ke6eQ;C9aPQL(92#;sqFY;t7GfL#} zP>~c_BV{ zQwrXw4SQ&_-`>&I-QLkVn%W4m?;(rY+K#N>vBG9Wi()W-qk!1kw{j3e;@f;kmJECV zDjfbnt`jdSe5L{s{||Dv7(U;#&RK1G(}1ua6&PIp#4cSrLVf{){UDtvh?kBEgMq$@ zMU0j3n{a4R9+Z+MKrAce7$M&oh`c;b`OhixtQepa6W_W2T7-iregOv&O3K1O=XXnf z^Kito0g@Y8OCwiEg85nBG<`xT9R4&R1<=dCYYMRr|t+l#~j(tsJb+8px=Ojnga0{t*B5OcsFCP2c$Y2+pPd6fKns#~= z%pZYH(|35oku^;}1v|}Vk+mdznwTO(+PfVk#!{sEP|1BB?`Kups$aXkSlH`l(-)Be1#@lPa?uf6h{y&YvOm;wBjZYtH_~)aqA-B%lo2(;&DPL`#h61Wo8dazJ!1x5+#FGOei_-s25?Jl2-D`> zcvYXD!gkLf2OGnPO3=SI75^5_#LHw{v+84rL!{mjGfR-TO*Fo=@ZbnWGZG#wo7znr zugxTKu_bH~y$)&p`^GeT(V9zdxJ9(sv~O?&mo_Bp{3vqlOyDKPQzl(r3E-6fi08=ZhTnD5~t+kznqA$(ilQFHeh*$yb_ z3p436kL+CT2O)E;FwOuO0x@Crj5JBaJva*?q)NI5=%5v znk6C~JKHSiPrKPHNNYN0RUu^=n*|9fh00Pxu6CKAb>fm zfGpg@Asm&>auxQ3-BMk&;uwbwZM|pC&O@MkIc(@9dpWd7|K1KB8g6d~54~WV-Nvsu zMJjS3Yk*>Huh8s9oCQWI9ZcSSR63YAA&gWxn7nnWaxih18mV?Ld8VHNW0+o$7JDYT zQ^yTJWM7!EHsc|SSf6>1Rjz?<|CldLy2EEoM*%W0t%Kup5@p5!Wy(x8%WfygloY1` zrAi8>My8@u2v*g|RA{zZLnY??9{Mu_R6Xj^m5o)+$cscMCZdUk((;*O9&i(75^j)M z1F;k~hYFb_aV6%-NfHINOLc~#;0ac+Bh*+0D@Rlhwxe+|2Fl%b(QhY90Pd0Xn%fh) zPlLpc(b(X2l*LG!Ea9U$8YO&;!bS-nGiH;UF9unYTOc;j%@PHVtNoy`4-DjJ3Y#gX z2yd!H%;Rq=SoREyd3ryIg2&K;=y93;8G)5NYNa2s> zaA)tFtM8!>a*0GHTikX$2#U05d7y#wT0Q5gDRLB$kMl6HLp}BHA*QwQT?PAVGuWj{k zMDTQ_8s!k7!$C+>+4Z7d9qe$;5cknGDS|;d-GP+R{<)h@yM)KKTu8L1UKa!9NZK8s zD2`*)>@pD}Cw_)hgg!FXC4#lxWku98TvjB38)~Mk05NeM;)2izXS#f$3WqwaA|Z!4 zU5L5y{(J~|YHjc6<3A}ieNI>VtPXK^iJOP^Ui!;mY4L(dj0e_@N3%SyzH;4G`N91rhgWaP)_etHGaFx_Oq*!>w zk9)JGXC4ysA+@5Synd-jVDp?35h^I~lgHCBVCrR{Esg<6Tnqol!7xal!}v26dwhzZ z{xlmOgd7Wn?t;r$1Oqpbn0ly~V{>HU)a$bmp4df>6IPxtEl$ND%6WN~h{+UzkQobX zReBtDEa#^PjyMCNQN`Bo@R>}?}kQhELxrsEPbRl9J$uFcg)H+_-A8UxWRWU z^cmuCPA)`W^{+df@->iC?;mJoNuaM&S(secgEAA3729^}`-@;S<+3 z`hXUWU&Sjt=3fC1M;`Vl9|D{|74G*RDbD8G&Bu!Hj8kAfZ;766VcVh=A8Bey^WiPN zIvCy8LM`M{9NQd`3z;Ve#$t=j!JDwl4+n;e!xPtHHe7$1XM{-aqp4yZ^zvHxS2~eL z^S=3*8y@pd=b2zx%CCF=^;F~$-~M@!KknN-|B5K`xNrCTp~A>A-+cb{QRE5V@$fH` zB5!J;BJFLo7SD>e`FGFRej6ysFYtSr^@{Tu=M6FWz1XKbRxN8(>J|uspi^(1S!1>A-p9L*+#O%ueJZP0cYr zC=~fvO~RZpa86$7#Q2_1I*1F8=u?!4vnRKDJK0d zb>Q!fgd^WWYmZsnM12Zj)SgCs7Bcds3_vwMlK}XYbma4#+ZFv8UIL)77tVJ-U&sX5 zg?=Uj$o_>Eas|t0F<(gpe2nsyM8PNUU&<87{?{@9H>{sZ0F2*nWJRDB-$(>}==CiC zM?U!Nm9OE-2_UuK0&unx*}r!S#9iGFITF}C@h_+&-vN+z6ntzY@}uU~@v{7#1mK?c zg9PA(_NScN6|bm21CWM*FL6g!N_66>%ugB#9hKr0^G8Ue9_i0>l1J#IFprI&l`y_b z6Zs{lQsXy$kzbT*{;qrESEU@k{EPgmlw(64`Aw9B#gjxd>1v44oJrnz9ectG=f zG$Dtu`X_Tz6)joOq+CUdb##ziMca?)Ai0Vb?C5H86>STmtIHu;@1ko;A+gQ)OOD}5 zV03jYrJ!}c<|hFjFeNm@q+pc&VZxk6uBO9r4%tSfVc zW?xSRpvSH&bA{fpz61~rw}HeL_mb!aG7a~U^<^4vpABUQPcIwE5Z=uE=_;pXG;U6? zKtwlnf!M4@H*tGI*ICca7Jro|x{(awZnKFSK?85>HlwjN&4rx37EQI8+l+?V!e!vw<6z**u`d1y-Pge7ZcUkiUAD-jD>Y&m3Y~sK zQaC8iw&5W{bjuup`mOn_xwGicQsD)^=yuTPYb~2G%hT(2b(1EbpKlM9Z7CL$?DiI! zo;eB%Sd0~arIVaCUSqdVkW7$)9^3tzOx#}YO;&cx#$bKD&=B@AFjrEaorXEW!)At ze082cciwQ1|7VUM{gqWqt=jaDuSADygzGtV;X`>+*$pmaMI$Y{K`#T5loEwfv~~%k z%A$G7O2dJY!ZT^w(+khURVnf!iIGnzqtz;uSG=mcLd#pF@zA;xkEvulgl-7UH9@XI z#ww*M@gX11$OI1pw^ohRIcI#}kz7a;6Jh!Ysqt{m$=(-)m{<}Dy~XHD6H|n`sw{%% zhL{Mso4}LeL(3GHh;87(oD?@F$C>#8ZaatPJukOqHdUY$-h&6uL#)Z-0kAm0M_X0^ z(Ys**5lhCT6k&Ru3Ya;iO@dSg^CqTNiK3s>rV3h1wt3EffFQ%K4bz*l(xSD6#WQK0 z62+LV%NKmxv|=i&SBb?;)}Vwr%k^+B$t5b>0L+yvF<0?#bfS|}ay7!947J2F##JM9 zD$hJ_8s%y+RW*6Zd1N$$;VxWctQo%bVN*z`IR{UHRuvo%oGEZ1@y?UbRLCVDr+X@t zF5gJ@G#MgBLPbg<662UFyPpi_JG%X3PPwb^FGIw%bnn=ZJI2DSw0}wpV~fr$cc2vK z)EtmkN;$7BQmOcB=h!kI0NmMd`gAvNcb-6JYH1AUBd|pZV}su^1xb0PAbCZTc3o zFgBKLpjaA%>usz(2LrS;MgbhkT{b7fIU}tpiITI?D%Btp)1?|@p-qN}Zhpt2kSs)_ zzf8|dVY8dJr<6GN<#x56cMcs=Jx>xHQYo*QGo&hBv2RyE`htDyqL8GzW+%Tzsx~|M zjC?^Y=?}ENQnF`TeAq}>e)$OZFqIo(@UH(5F9ME9Iz7tB(nHc{Cp_rWuPq4uL|EIl zfe3onbQAR1;!v+*aK>^dijjFiO>h@_n3o5fyUg+;-~?v2M-luCF52bg0^R=*PXZXT zJPP4a*X2dP!^UX0S0POBa3KzrdOTc+CBMhZ2cOa%?&X6|Ru1>_!6zTRUJM?9ygd>{UBdva89f1=m-`5^K$u?5A6 zys2B@BSIdsNBD4vk$Yruhhkzs$_J6h;1NEEeE4*9@esvxm4!Y$^3YxA!y`s;(ypr@jnT);>Gi$sFPE^xcn65WPg77>BlMl{PLFn6n}pC z9`aOwet9FE*Fv6oK-WD3{ybC4GsKxiX}pU)Gf&=D7sqb49i%bld48Z`&noJVpGlqp zf1c6tF5s-9G@fD4E?OwhuV)wa#yg_LMZNK+=jvR@vk@@8T~maEndoYb{CK8;~PthQl~H_?0oaf{|n z6u%L~qS`d*s_OZR@2)S^DX~ZAJZI zf5@xpExxF{N4QlhRzAG)dVZTPDwgQj+IjM7%&606X88Sf+Qy(c-mtncFg}XG$bURX zO4%ffIq0;!0&KIq0dqS%7-i#wV#d$g#M@H0Ybqbzt-XC6`tQkjo4pjCWU+`PSEr_# zdxtMB?@8{^{J7;UiS-m%vgjKT@RsCGUlB0%u3{1JdUqEb4p#0sMBy}aQVqoON|Sk@ zcW04uQLMIZk&$S6yBqPz8yYMBy(ml$V`02o4Pz<0C#O_neZEJn#x~$ywHiCa`_wST zzbn1}bW9Es)C5Hc{O-R%|W0;mMUEs_bD%GN(wfJyc>VXo5P#Pmvf$ec-eW`+Ye9kuc=NoTDyVD zkj%X}u*V~l>O zg858rK!Ng~pN)Q?Di=RmjlQ8oQK5HKp7Hl3qwlIvESK-99G7D6{GJNMpQDVvr*e$H zi5Y!gsYRMUP-+p?he|D4;X|bsyXN;*C_c>={Yd2*zr&4wtU}@VBb8(Pwm15*3dLvD zqMFJv{u*FZQ)-c_Pn23D<8y^p9Gwj)wBio^Q-ziv_kE%S(IG!oIOY$HMn6-cNY!U5 z&j7zrNX1U)a}~6dCS|b+Ct6+4qSWF2cC9zmap=LA=)Lkc<6=MmRkY0$U;Tl^#PcmnP2%~8& zmW0mjl4h+~5;8YL(_L(kTt$<2Y>-@qvQ~pi5(i|fK_oD2G)|X>EA#4Dj z*2LjWSc;Pi+yFue$R%#5P;!y$$wACuu?-boc?Q}@F3fPS8!41L^KGmEd2ZTR;g$p1 zR1We)9@|vzmY1j4R#3WIlK)ap^ec@(clOem-OCQ*w~S+(Jb zk`OqXn|sM|10CBuPjXd|IO>XR;pKxL;cVgM12?|0l$Q_Oi^fu3K5)w$+X@Wh4AopR z>5~YQPJ*{i5iH3AxA2yE0-d$QM7y;Nz>K&}N}>=yc#dr&6JeR#Rwlv}w5?2m31&N) z0;|yuG5~i}u^nW-N-@K4FGFwx7u!+l4S-aF1Z*jjp!{8A08jbbNu7~os7!({CdGzI zB}l+9sRqd$Ce@%dcamz5nw_K?tVKIZHC$1dhL_7-Wg6W6#fD2Yh+tBh&DTQYzD6vpujv zj_9XQuPh6>MmOE;>FCQj32GcV$I4O?6ie8^O9VLQ47v@}y}po_pvF;hEGlS5Z|#?kY@b26QAI2;?9l4$w9a^NSa&^Qu~jgZ6ULG4#Lsb}CkvyVzCab7*r zYMd9ik$I(_*QZfxoY$VwYX7CYu#8qaDCKo!FSUmZhq#B@LxxAeo*o`>+8x`&gTS@i z)1wHk=3X8I&U2%)h{8L$_;UrZYA23Oa0Y`bHcst3jic?@SeaIApwpb8-PHtku(t=! zZLqgG1pc^KY#$E~+{|Ou9{2-av2wKs{=!$R+`|Jm(moypZi8_iMQ|%tco29rRicQL z{vL(C#}V@_HNzNyj!ld{8S|5aScM0H(_EEOdf+5hc{resF!1bHiQahKDKOH&`i!__l4l%%Qj$njlqS;TrgE zY{=a*8FK~tMw7wj5;P$%gLw`5dXXH`7oo3GGT2;&YNRkPLp6DslGmXx7Re#K%+FIY z*j$PB&C6hJ%TJfdA>HvOIT>s&RAW*Sn45E=4B<~i4``%u4H<&;BA*8C98qS8lTtF2 zcPf+eGKjY-ALrzdUgSrFx{EZrN~|s=gRyTK_#iKbbjRi4RE0q_@UA9P8QpT=ov||5*y+UT^D-E{cHk{d4(Ta)bCC=-=ck6e3`Q3k zcq1i;bjPnPlfgzeicQQrV9VNzTdBz@2adHDsULW1krWZd#v1bu)Z!O60Zl12j+@IS z4?S)#vd~*^nRWmAE0VmonF@||h!kSrA8N<;^C0k1(B!<@0}rMtY64z~i8ZTBz%M{! z%^rH(_e}B7!qEI~IPUDe&jvV+VNn z=OH}J!#~fFEea3x!7A>Fv1w`oH^KoZ!T78T;0pQi~qk zs??(4Ta{XLtLaKDI>mIAmY*WV=4v5%I`~0h>|m(XBa1g%eK}7K?Cdv{2XsTyoa6Z?T0s_^WaC;o5X;d2N&yFw!y||(BGDf9SMR|&%@#1 zlnUlmZN5^?qj|ojQu7vZfl|#ot0R?a9*9RlEtyX-PL6_9f?gt%4ozXd?o8O)1KX!*tf5#THMx@dFo7wmUH7Dsr3))^7(V_z{ zRDkB!BV!A-kTh5fts~@Wd_f_0v_gl$ezZb|p?-`4!xVCi!Y2muBDt>c{&Q@RT+IW0 z;6IB(vTB;gOR;0U{PW;jpz@DH6rKu>^h6CgT$VL+<9h-;=+iLTqqk#LM{8dP-rIkCMd!>(*c`~F(aOpBgd9p7+MPWrey?Kl4wAByk|pcflarV6wgtBV%vVE z3gt!YY)#=9v-@HN$X{lP9h4$z!dR$Ev%Drz2f$zcZcps@0^JE%ok%1>90R4Rres(C)YNT%jF?;;5Gk7HqUqURVNDqFUQFlX}^Q_8^ODG6$xnOvA7 zRMqcOWx=V1b-h-dLvBao1O0LQz{zjX82Q;NO#*rxy9+l+NsifN_PvqSi6XW zlFe4sk*8aop6v0Uez(~?747txzi)?Ev+$x4%-?qhD~0EXJA-NX1>ZY@Y0x`w4JN@L zxILHzX4u;xI0m~uDJ;93MDgVBJ8iaOFu+Z?6 zme{=k%R!6Y9Z-Yi;;w+Pp?}^RP=l^>UqB7I&RqfPLz3t6p&*?aKP!$cPX*FI@}f;r zQfytuUs{a4oVONJRD)^lQjH|$%uLgoeNIK+dOqbr;Tyo^c`pX~+6!Jj()eC#>;*Wn zPO$b!M(DHqOQ2Z;w$JVe_~n!*1%W4s-#82q`^*xLciL2T~? zEC&p$mM9u5%=n~uA_nZN$l|cCEm2tb^nD4X3B>SHKXk0#>_k$z# ziTmAu;M3X9%5s2s_ydrYT^Doj2MAHcNOSN0(921h-vs>-UaV`2b%+o}kNqR3 zC;LK%zV{J4S>v%&5c0=XFE~QA7A79{u7npO9y-h&?szuqNho7E(>hxnTi#eZxwqFo#5Vy&+*Q8~R;M)g)o%idxZ`~rFg)(z-vum*r;zUg zmc)-|z7JRu_tzf+ints75G*`?nm*vvD3^2^c|Rg5a|)$t*FHURb$^6I6-PX;{K?CW zSQLKp@{$&um2hL7KyA@vM`nlf8Qss$((H3F2mQ0NI6H^C*)O)@imq)u2!4TIGsL1A z9s|DyD~EgY@4?F9KRq2=6->lmX^0I3i;g?MaR>?U%?6ztI1yh3qn_ouaOG{>E8Tfj`-?YFcCU-Z2aN?PZjBNfYBW+9qGq+&}0w+JIXb5L>k{wrYXT2 zCGk=_l*u;n5pH}ZyS)^4bg`Z7_A;Fx`#2vmD$8}FUP;Z4==mBtmxZ&NPNIP%5E<)M%$heJHp<}?w$GYb9Fw1)Z#~2 z?XCT-ccY zZn+?uk>LZ*@o_dDz14lXjU`^@j#uhN$|l!6WBgPqJ`DP`%&hRdRRNpG9@sovj??Tm zRHh0%(MAQY+&WcYTXM}Cv1%C|zk-TaJLtTd8V@>Uz#21gC&6rKT8^%!z@;UQI}E+U z5wCfw;r3%Q>vv zI1^zV#1&&McZ5kA8AYyygUs$}@e{jvofP8Mtk03k5=#qIRH-J|E#A_4?i)3-i&heY z740;z*J1}-Z-ExDg%@LDfS)Yh@`&%J0P*?j_+$l$ufWBd6d=8D6K~Fiq(#DMvqFdN zH$|bNmoef~6gn)+Qx!UTAtOFjp~DC3;`=Lv_-0*vf0dH3164w#W|~5nL9F|!lt|n( z6^INRpaN0N$tn=@&H-9T+8%fZDSn^|M1l@dxW#)o@q<)K!setxvLeO4y+;A!=qcWl zmn!-1kHlMY3J|G1SOp@r2Wtu?QkzvNk=nyk3MEo|cwPY_wY@4OQroLgq6hVh5YO(-mg&dp~M^o$ma+RT1eWO{Drsp+>`=EbIwrc7du~&fpO$lqZN+%v$XMrD#x6Rg(@wld65d`sE$>6<_0`grR78(r_yq& z7Aa89)Nv}uj2IaxmPm{28UThf6|m%2gY3uN(2+#dBC zS$sqyetycW<)MF$M8~tuc@hBg`M@R(Zdc~FAU0a*291xI#m|?x#56y!;bOPS{O;HW zC2r985JS9PbA#d&m-vEb{DPDOMv3dKkOBJM|AM>(#3VbgyG%ys&JE?2RNBQUnGW~B z_@GGqVyRoe_+(f75~Uj73yNQE7Zkv_O4RvIsA*1IDdvTex(x6@XhE|>hk%dBCpn? z`gye+-xG*mt(5aeP~+FCajyO~`H*W~(Z2-Co#R?H&gr>E?Vry}5{EH3I zjS_@E+!?u>(p{?%^Q?B%deNfyi>X{ z6>^u0jnKfD9x0;F?CVNUdO{{nprvqrxc&%OmRLnd{4Is}qjHRVJqlkE70P`~suE8EmpOFC!}0k2 z5Ls%7Fv!>Aa$hLL;mJrPB6z}~G9QpX;SiZm$e)xb$kCH-zNp8204(9+j`SG^8PB)L z{ItZ(L*l7a$d*I&65>DQ;KR)A`84>JGI8trxPxrIgzzlLmIh(~?w@f3qHjLyb|vci zoJ;{%&q)+yUhd%YgK_YeJNOJBMK8z{m^EH>10tpuB(A`Bn?>%PmjNjHB}oZneuvHc znKsN|_`a3?X;b|jp?BagCL?6Bt!*XQG2CQt!HuQKkcF36Sr~?h;$_$@t!2J5@JdPo zK=F!9ft0=K21LqUmAE4Q3b$FL>}45%qE|>tAoFVuK0nF^|1}5SSU=*gyA@)(dtIhL z<=&7eV0QCGo!@lx(FAYG_yFDoKPqq4HjKA-S!pBiR}Bez58ALBqBWuK@Y!?bx6(ga zQHl59BO)P|Wjp6)JBjf=T*(-QD{$aN6)MibK7bQ@JbD+V9y)*e{5G74eE=_BB%IxT z2v4e_F!Oy_%nMF1f5?#+ucDCOAG9JQ)a=J%o{;4qi+MuV{7LPJe-9e}MNPoR=He?o za7+XEKuUb2S13dR=jS4hP}t8!{Gcg*@!;UR{a2LZF>j^C7VcLMH|P?7z>T~y#qs@5 z9u5%aZ)yjekKa7>=(xXo=+Ti@dEjXIRUZD)eg076;z0Lz4+0;j{;7_De@`9%)58Pb z-~8p_fsbyB|E=_p&Z0a1t#rU2 zbBzDT14lFe?cpE8>c1X(H1mHw^ysGl^U$Lk{ZFmu2_z9wJK%@SiI9f}+@~kP9v*PJ zo(OpmaDJZ%dlZ3=mWX%|(9sf6k0NmUo``yQz+G-)CwOq&D^dd{Hid9-`z(5`n%}HW z#B@WJz9~VIULuZb`%J^1M@S@c5`cPjA|X@2RZ^y)ex69m6x4kZt4kF8JETNhf?&&+ z7$gIzt0e}>3ZXuhSWTv&&XrhQqTs0`v4%v#^KN1dnFjMwVz3P1##>E>;Or$aSXK`A zh&5#hxAdBBZ^pJo-vK4ol8JF{kyuMDCUjk()LF<6=X!1U!8P?2*vTCUL`>lxQnKKSbydb)@)~=43 z-27V$q_eNBwYR;DI~)B6iQP(LPXfu}HOxc`@b*ivJQ9)kFQ zITc5Tq^AHe^!fo=%4#zLATL|PZuq6^ZE|#Ns~D<)9G$pYEaF>+ZbcY;4 zQCU=^+fgIXrb8Wv=A2e!YA0}`*271Pu$`S;k&9hGw$`p4}Wy=9( zo!vmSS+T~IxVV_HO27?Uvsj9qUn1>dW4=pE*oZa*wqtRJ_YC+BJ0dKV@X>me5 zCx*e3BTjs}H&F(O1IWNvnM8qCY!V|R3cQq)7$H&MHKD{vC>+(mtTIv}z{@&`Q4lzT zLRv@36v$Mm1i%Y3iP17w2x_!Mf%jAsV`K`n-WZtzIourzNB!6?6ChK2K;Wn!-r`B@ zDN*3Fa)~`<3Z!Z;8GvZ_khwy`?j-|I@x9^7Q4KNu?+u9yL0sj~IBG(NcZ7_UAovDn zVjs;dNux#ffx=M=>|-T@5*}scQUqxkC-GIndya9?I7;CoghT~2uDWp7uF#|qqN|ib zJcO#`5V~b`PUeuuSCt$>t*Ye?(GcV1Dzxi(xeA?Rf?S1qO^~b5uWRHgG;V_oYT?%t z62pMGG7nX)Mu;o(JU{IVksCsl_m!)V-idM*`sGBq3hAwpLr7Gu+#$x(Bsql4Pm()C zmFwgxWWEk6SDt`0$q=!loD6?Xk=R>KhRT^jaktY5l?&p#;zp^8_ohuyxys^QYO_?u ze;YT^0L&%ht?QH=L9RIXt?xv$6yvux5>qtNxm@!0c&c2+M*{Vbxr*c0YZChdbGhWL z##E_{zm${MFGn($%M2%FKe>)K{`<>ye3vjyj&Us0F%ZJMg3XM0cJrSJQG@9)&E{ z){Rki0ch5yY$@eGM8ogZC5{7X+a2N^>BRh$LzFFT;jj25`hnO>6}#ZWB>?BF7l1VY z^2PnOH}3{`upSP;Q3j{6FXaY!4EISC+$jA39EFR4I44DjqY%#d9GQgEI#+^-G0`JK zxRP^IAy)umw9k_vT$_0^Z=8SyG7U#PU#8*wA1y)BtT|GKa0ERl$B`T!91A28{vt}^ z2uK{6=J%BnM@bMdM30hq69e=}nTA{RXc@xEStvu0g817&Y`vU!^2fmJs3kY_5qSa} zbxCvm7s?PG#>dDI_O=L!y>#q57NuNftg^?u&9LTOWURXbA*PITfz1<0?E#;G> zi&a`UzE~y2%g2dJ6jFZ8K5;%!>s-T6<`Q{@D9x$8JWnD?YB|&k6w(Z%m#C!NESIXZ z+%A`@w4D3PR49jhnaVRa%@rz?&*ZL9dFK3HuF$4A<||bwccv>9p7|yH#8oOS=jtkz zma~ypp?XH=uI^24K3Df|({Yd0fPKZi zRtaq#;%|XL_ixxn+;0KJB7CRC!tHvW)qp+5z4=g~LfBp0Z!w5x#t&FDVt;U-mBT&m z0jq^u>_MxF+v-6phg<0(D~A*Qkd?zN^DsE5AYPD8JPw?$5b2}(ztNE&O9^`^r~EMk z;b(Y{n;1MS)2}kjT&6QK%zVPczhNobN;?IntjOS8x6~>i#digxABXmtqCzE4! zOn)-@d>+>#KEZw=MHa3|FMq9uKSz{!3f7qZAZlJOJt}RTKC6QYTMj@}kldfVh^~Y? zy?__;!eahyY0^9b8=Mt#h0pmcfV%>nzlxK1F-2T691MdOO^TUmR#R)>HA&GL;MiLO z+3GIc*Wx-mz~Re)$Ik{_$9X)wRqL-1QWmtw;BC^h1&@~b9l{7 z=SL2&N%-XE4HsPu_%~d1ewQury4%jv_?vD&yiC07=8F@mN8AD){cpMjJafF|=JTw> z)1j?h#q9i^n=kIt-!}nz(4Ed?(??Jm-ZhOz4-ymhd-;&wYnV*T_hFHZd|Cm5JaP>TI=>8f$jwGa z|JZGY?~mP1&_xH_Y;@62Tx_vMz3sB|Xc=&uxkqbm@7$v`37<;+)I}FP`coHO^ytsr zeD2Yoxb58GK6Crw#qJ9?pF8f`u!mcX_w*BA@inG8ZFDyoFV<{OraYfNz8;yTs} z=v#wYQ9q@bSEla@WWv9*;Shgswcy&|vj;4TKMD)~H~?k*C=`569+K;7Au7J9xxBfi zg5cjkkL_RIn926jNOMJdULbt|XL{ikI%nuO%9|wya`yW9D~YG)(D0?lX)E+2t>DiVoSErYM=d3a z9zUAH8M_gwVW*H05bE?snZ-S{dUcFcQPrv9gBKNIu($WZahy=njbnEkdr9P@b=7da%RTK6##(DUcJ(W=p8^* zQUqjahc^yKk;y_-Vw_NQE6CUKmry|?Pl|xZo6&kG|D82gST*P$mPQo;h(7arM~;}r zG=Mtj)6X00EtLS4wteN_gxi#yWJ@{5XtqZ7`U=fZ(KIP~yNRQZH<++77gDn|lF{r& zoE=dNb#X3~s{H0(NRvJh8)Mj*muQ||mM_41?oqnXhr&w|C4{35xW|OT&s;Ku3^6nc z`ei8mblGAuYy*R#V+Y7rDE!n<8lkJ{C`&BpbHC;Y)q{h>LLXrDn}4pf;lk&V@K~~P zZ>16oDlw;p!tYk*Y%0BzKmB=+#cU2ss?y~E;?@|^SKeCWrki{_r<{}q_Ni{aOW{;(Qwu<&cXz`$nx zcgr>KRTcsE_^T{9cJY5$uCYD&)56Dg{!a_e&&~d_5b(#K6MtD5aQQDQ13vy^VPKo| zZ!3Wf76R|`|6^sqB?uF+o1=?g=wi^5Q<|z8v*ool<;dILz!Otzv3vb*ivGRz)C%kZ z|Hi*JnL43{Hi$!V^jm=Anx{2Xg~H=5)@X$N+FaE*siv;H7OFfkBTZ8#(J!Ouf4DzP z4k1!#LDRH4xcVOmiDojdlcRryVa`_7m5-|>f5~-)&5(Cz_~zz+DQ3c&&d$d!bsf#L zpcou*CD+U8HY%2E%v%qhsVy@$dA={UNzmqw8>WRaLgKytzD!Jv=@O z$!|#{Cj-2vmTc8i>MELR>g!0cJsBf!HPqB)$4zOfE1!gvY?&isbTZW`Lme@>F)m|` zRpTesR|4Kdziz5(7M5{$FCs>wv5G8IdNf7zd@b>byQxM3R(n_gQCN~2b=1c05$&G+=EO^~9xfw16iU!y`XI@fwO>PcUkdciofQow1jYM(_ z6UBq|7V3NGy`blG zQnt3fVq&(ks8*pkC?^v`g^gz_fpTD6F0m{zbfS2d7jC*qhLxTbRdPc`Pql`I8tTRohW(LW=@X~IqJqLGoL=&%{G;@|L6rrSp& z4CgP&3WG-f9&3>FpvM|m znW$|!aH>Q`FR&aquFFPq0ONpDw3)I|e7z5FzAhEGc|C%!D{=--$LLhP*t?P*r*g>} zps~7o(Xp#=MXiI%RBH5ZDwn=KPqL~ndl;&(!&F}bEM7OhGF#bLk)2fDL=*PBeez_y zr>?4=1}t&*&Cz9SQq`nvZ9_%2x`tQP2{1-#r`D#k&5h&5YBZJB{K_mX1oWFwp3^33 zL<+k};PiI(b#~1Z&p(p23L<;shaSn=9QlfR`JzxK7A5g_g#*WLLMf0YI1s6~69{VrCW5qM=y^C@O*U#C4DOpv zN(QB2fYkC5MD?mq$`Srh?bM1%^-cJ}MY3NbL#(E*rkPqLTY^cpg-uxWvbaG=PR)VB z*BQPp;F#u`3ourI<^qa2Xnf%kv+tAw8Aa_^xI{4f70CEqQF8wRjLRtn7{BmI?r*t9 zSj&>w&1i1&tDW0n_z-+poVK3sn^Jw|VshPIQ$KD>HF4W?u4w*JRC_!G z3u@~2t*U5FbC;eDOQfc*nF|ajTQ$1o0#L73pzBj{^zZ3F!o(C?uqHYorQjVn4N{bH`~U_aEW#n zy3{Nis}zHEww;Bf&a#;@$XAz5m_fd}>@4J~+s;Dt-F6oGPmi62toGPh$m-#C7P5M{ zorO&F+F7V$ubqXg_Ssp;SD&4QO!V7X$OP}l&CY~Zdy{i*tTftjuFY2(`I={EAz$bTI(LROElvyiW2>?~wrk)4H1oB~t0y0L2Vl&ZRl zX;~Z*&<#7SXS7Lt9^e`^J99eJX)UEcKFKb~8W~EaZ+2wyp#*Nang1XzUh zp#acf4HJX*VK~7_o({v{@paTms(wk)zn6{Yz^l()NxSVaIGr(;kxTLfFJQ}lHI>a1 zLg9lq%aLir>ZWuwM#iZ}iSKuEwA# z&d3o{;-&!@m=dgsuruWtF1dkB0JB(aB;o~A+QU~D-?Hu zK^%?1E;KO&cA<$Ol#5IZpH<+VvRc&CS;PVm_L+KZr7$Upaz)*vWjEhmY zy2K=+u9uou2JgKOz#cU*WaV)KLmS*@T%>tPebl@}#vU_u2>LM-L&lbw z7~Cu~u@YQ9VS@B1<%&hLT3ug_jmeXs@q+_LFT#OH@=2(qDBrCQoUlxR>v#JvY6fn7 zERp3rKAn?d_)%Z-abVoHS+`$fO|#Lpp8`~P(qTgSiP2M<0;cK=9J@>o>d`)J*V0ge zQ@rGtd?sg88W1|;GjbKW!?SV~I>2*s2%Ya)xkGf6`{XKq4)L5^#sh}8ZH1&6;iC^d zFPHIDv0PCc>b6|2BHt)3^iFh!w=HiLj)wG_c?|AD#WPYMucl;6lP z{{2((n|#O-6?+xW2ESE+@cOOXt9a=6og5U;KfhLZ<&1r&0Qp(x_X@ZCpz?c#k{j>` z1;|IVKPuev)7c*tNRE!`IFo&f1o3|QUP*3{|&cM+oO583qP$C9}rQWEQ3<^s%NbA332xaL1SbGm} zC#vmzI6J^0C&`ge4!wjXf{39gMZmzJixN>0D?_hhq=S?QhzN+$iv>lD%0+D4s3@R< zLEto6Y=EdRHpGUZ2zI}B?J_f|_x}FRmq!mXYpuQZdiPqp@0oGfGb-bpOi5_1&ru;` z8ZatmNW#Y^j!GGl@D9^anK+qy9(tpIqe3Q~)H*mSW#Ujv?a1@m(tO0bU`Jl2G}N3p zDre&G6GsjQsmp94J%R0TP}0nNdIsB(pFKVAd_CFu{E>D?l^gRd}$b#4EsyPIB zIaSG#1);2#Ljf;_syP(UL+p+k*#+8iS60uS1^@1!qk0Yvyv9_^A;1f=Mvg3aIThv* z;3a(_2_*O0)a5uD6FsGIyoHYu9fgq$taiNW)udGZ|JYUR*C{MtDbaHrPJu7LCFkb+dye6;DPLrK$E)ZWz1l!%XC9d$D%qJf*EUZzz1 zlh=-V8B@{Z!cjkCD&AB!%#@11@W@d=6N|q;$tGA81z=9DPeZW<>vrxeL#4CEXarju#x&?22o^|pmKO$m)#E=niUnN!C_ z=~`$c>}Z)TPh(U^%M9`$w@MeM;i;olx;TwA9T#ViCo?;x(Zx|=N1Jp-G*WXkN~aUK zbp|q-e{lvn233yMUR!F>)7q8ek_>dxe@O;CRBV@~%kyF5rRnmty5jINAqZ`lsiwJ{0Qc z=uJyUE%C9wi41g!r%yPIr#=zt=om@kQPXs+w=V-->I-SOQ&pHJ`%p%n?*GrxOC3O<@t8arkQ^%+HplTHXpEb&8C`BN%DZP}b6i(uRnC3o&&uXy=Fh5}5371+ zV~b&Gk8Es_IBV8?L{*fH&0kyPD9WarzY)tZL9^k!d!Jr7TF`SS8l1lA+IYX-kLX_O zxYHPQc8-9R)T>IbwdMBpqLdlgyySXiP0iiXJ8NoQHodc^=05L}H8md&_sf==8{R)_ zVj2neO;5{TChE8<1A~vV2BhobBb)*03HaFd*a91VDJ7@A-+HVly_r+rEOzuy*T|QN zkIl=-kPY2je_D1JmcOXR0syI()|g3&-r6D+%uewl!qc66NzB&(*uvsU4v&I9TRli_vQ&G!&~@j$R?bp z!Rxh(}ZM&VDzU08;;phiVp8Prt3DIoKG|Fk~e(nIz@`n>1)Rn$)W41l0g&Dsgh2U zs%a_#&6uW120aq$n65Z97o4GP=vqmUT{9(vPqb%C4!8I&#UW)g6^HVlr8tCTmg10= za}vR47AOvx$|oqKjf!L;iS6n&h_3G;DTZeiDgTA)21kS)i!{l> z;b6xi#lf*)|JBqeRO&?sWgYjERK;HX$;!p@no4c4F6adMUP&j+AxY={zgON6swGm0 zKrNAU!gQac^XR!xGUzzJW2xeh*iywIwD+qULbyWS@TG*HOv3|nnYtk(A5b@Bzym4` zL0PFdWadi6p?n@x95UxY#i7DqE^oN^!cvS^jj-ZSrVmLDDSJpUsF)sBNhr^U6^Bgw zm*NoWRqBSWl@#Uwh+>fDM-+#O<59_>>wgIbJrmB45f2+o0;$9sL42H2*~M`yap2go z8l?PNC~O`>3O2D9<@*?jm8$k4<&T4Et5|g1jby@d(D@Bxs@p`)oXV?|4Qts5mm&|LS3ZLDW`8NVp<|Df?w~)2xW%eyxT}Qcjjc=!S&IhG%r# z2=(}E*O<{$ri>mnY~-XnN8&Y&j;BddFxwC7!&_ibpR*)ERRrZ(3&jw7+CtvWsaLlOONtFW-^-xdiotMyhvBd_O8YC99_^QHzo zZkuYs3zWuAz6rp97wL|dR>10$wYnnHQwNR>hSYWKh8ekUum}wk#=mHiknANRSs>kx zmn}?@_yr?zzy$M>g_z`#mn{tSP6@{=7Nv%r8x^rXZ2FIJBTe2&dZ;|`R97ErmH$Ho zDiVGd)r>olpl^c^C~ok3QP;h#q9eq( zvZ(ihS50}E-R?v~=nqGL*9UrJ{vk>?w zVjJXb4w8WQcDkYb3D~>phR|=4=-% zk~5euC%>-lh_yq>QL*iioEyo4_Y{Zvr}q?x4BaU?gQ@4+sW@clF2x~xiq#EiE0$t| zsiaF3hb%2o9LlFuad>}Qs#uh3nZe?BibdH{m7rqagV}P$;X|a|#ESLcecB#*P4?^| zDbPvRK1nB4dqHOtdr)cY1=;>J#z~HSf=K-RxJ-|%DR<&czj)g(y+(56EuF9?4ABEf zpC)?em@!jFPg5e_leP-JS(o{IIJoTijBf4i+o`ya zWQ}}8p^l#{iWJY4%Q8L8Q?yrQn)!36j*m&1yMweU)#ig-M@m-YKl;?`c$L#Z(vfPA z;bkRtD3dMJyCG;@~RWOVeF*xip`F&HzAsuWxSqm4-#?nMifhQv7Fv&4P&6x3H z?&Po8R(f97z<0E#O8toxm2R0bUVOinI3#2$u@sxW!zM>OuRq0@kNoielhXQkmDz@XYkdZHG}vjT|?8^5oHz@P=3*=1#)5u7#~Ma-8^zYwZa+2zDZFG!L|zZ7bX@)4dP6R125ssDp= zBhgn%wTPJ97WvF%GB1?e*K`^1&Fb8_2esMXaD{EHW%~^mM&F-Qf>cpdbvu`*o{+2Yi+Xw+(<=iV zKhtdm`4+&&>dlpoA9awCL)#AYfSBWZlEQ5VA3dt%_<^{h(<1ABBrfvr(3Ye4iMYtW z?PZrySN{`n>9!M}wkL4QY`$3{-v9smi=6n-6ju6R2yRbO#)QG=qk%<27q`B)9fmg}|;pbHvh2HA6z8rCW~ zB9WNgFcp+vNT@Pig(%|TJl*EWHzPXE>$t1PGq6GHFb&-BlhFIH~R_ zSw`BFtVIVS9kTen79A*Bp#(JG%(qi|AqR_jI9VJib4Gq53>s4$h@!}^Kq*rz1Id}j zRnQ?KjFXjBDiG>a>2aHcVya}M*RV*`d$P0=(NmOhuL~fR^sH<`f#?u&^}Rxl1CoIw z%MF>-F}SIb4`!{1NJ{RYV&o=s<>`# z3lUi=Ms<|#u~g6ueyT+&QErwtJHK{B(0Y++BD#c)W)RkqBI!YaIR8}_>B-xoUCyuT zHAy1u%~Gu!N#$`&^(;w}8zTU&Z>Hg04Uq9f4Jc6)-uSCfR@E=RK}s4bxJD$8mW7um z?(2~Z?o~kZHc%8cxD83VlH$T!M57e>CXLFtC&eylCmt293<*y3dQ*tf`yz=~CLtBj z(3pfPau@Pj;-Xd=K88pW65%u+3m5;b;~u|@@5Wm(x`}IBL06m2;pR7teH*b2sz7f> zLa(pkVvHs)MyZRjiZxbI#;J=jiZxDMj8qpBmCOW#qAn&V)+BW?Ua{^lE);9Bx|pO` zlhws|#R@7)P*Ltu7k4VwUFzaa#hR)vrYP1_bumS;rm2fQiZxSFW*8K8F+;Itsf+1~ zHQTsQtU2mpmSW9O7tEx>yR< zB$9a&l%I86tii=8x_BGH9$escT>PUL^seIyw9-iV*l2&a0)GqHFDGMD`xS0OG&7dp z)W;gG*JYSv=zOQx_+gD|`AwqOKVpq)2duP*G-zm4CuXJH&uMiNR@xGs$;^hG zK2B?pq;H8vat%XV2!BX!F{d?3(swVXHTK%%kIU(lwn>t{M>wr%NQ!ZNt2nJ$)Jl6q zqqG-#t+eGj(OM+w`xlqHC}fp;nA2J&>3dkGw5{-0{K&qrMzq#R`X17Wc1cJ`;hN+) ztxb}?6&lH13Xb@Z+=IAdjoNyww3VFJE@Y)WsF7UzWPMz&1OAF1>07Ch9Dh|gClc)e zPV4CB1pMJNo#Z+t=?iK^>kN+gk=!zkXjdfJcfU@wu6`kfYslTl<+=r}w52-9b;n=v z<8ruTjr>XamTI6i{EttHaeX0@OQG%LX?yssayvBA*8?2!qdeZj9c$DxBuQM~4o)l5 zthD!V#~SrgBrf-^&S?=vBz-YX>+MgXX(ZPh9PuN$ts2q#!~_M`pl#x`zW6JCMBAd1 zTr%y=474p;y4-6zsl}$x*iDa@vxYATt@uldBbpIZ}_^q^E8mECHek8Y3 zBidCVLBTa>7Q7`S7KIXL?b4= zvD7~IZr11;-O79tcd4cKgqDGpE=MncC&jOa?sGhQAVmqi_!&$DNPeVSk5rQuQVxv< zg>3R?N0|h5q6MN>+FXrjgS}ST3{JZ)V5LpfN$&cPl{SUbZb;HMRU^3};D{gctxR=? zH5!_v?@ov& zzmO98?$$_de9%gp!)X)rBpU8mqe)5n?&5NH_^ooYxZLCyfek*Mnr_D;zH%%wG*%7PU6fQT%q7Okd zOtV$QKnX)Id;$R%i*>#VnKVXv;hhcFLXn;2KNgl_q)K8hk8Q0PV0G8~vGGaDxB8>3 z?oizA(dn*7nALqCggegb30@cQcoo{}46(W$V>bMlO({cLND2i}s%-cxSF31Tal_p@ zDK}^uVXYBkTYE+oP1Mtx5r&M2W`~F!m7}u2iY;_pEYWC*6&HOqdiOXkMyrcOI);*3 z@=&o}-qJNtRe|L{apgZPJnL?q59O?lFzuCB)rc z&ilwK)A75H{o?LTE_pB_({bLR7{B933fS($I`dQtiZeQF_YoWOu%P_T#qLkN%u^*Q zKY+3Ovk>#xd^Y@;VQx#^$6&G`N~1aLtQ3?-1~}~(kCNj61TCRx90sR-QpuB0=k`!jwo5WwO>+c`2!+ ziNvk{PLKkkQMgtLd2N-1<&~yHl;tp3T5d}+`0I9q8X;jNmj6;f8f;ev->*MELx%fN-wSJp#91GmQfXELKvE3hqS(Q@>332!7ICC$HQN||3mY<+veG(8v3&bDSejj8lKaZ0}#e73Y z%2xIS>6J7AvDKAP2JJ-429aLW2X|8U;~1yoLQLv2U@cg2{dG{3&+@lRwj&MKZ{OwNbgBL4_b%urBJd{v1sK7&Iy-$I82@ zYJN!*nj5}^uBN(|Xj!rD&`hjaF03C-xtU_!$?|u2Q?c&!usV-KCDyHtVysGYU54&f zZ-mud7n6S7+Bn1t`ti~?{o1HZWBEHhWF}&k3QUCV>Mw7dK?7_Cjgl!sH~(~)L9e7q ztQ$dV93omatn8_XYP;Cu5$WLZS_Z!!oa_A&id-yzcid=bMLiq7NMlu21SQtt_jtKq zg$={+<}pk*Fr!|#zD#FGB#0Jt|Mb!uveuP+3_2uJXlb=3&Y+2C*^uO|Gmum|=v7Gc z3`lNo{Q`p`H_I;%uofOKu2qYXzt7KV)bNYXQ?aeK2&*v(%@2>Jtt`Z91cWneY^xoZ z5xv5`trd{2IusGgJlXuTm>OnKD2P&Ji+V9qD`}=*mrkDDp0#KKrd?A^o@0V1AbiNCCd@d{3BqDdRVBHG_y$F zXi^v#!7wkPn7l|R7?881i6Xh=YCl7cM57j&Uiz$>tFd~nD%|7v=AV)10+#==Wys9C zkNm?vR(BezX`u#{TQ9b;y3ZpRc;mJ8Vx3oL85*r))(U+|oYn2_hgM54H2f^apimH{ zO3b23t)!XApIvpEOH}fUb;ab!c_nWhlQe<6QB{p?y(CVwtikZMSCt06N;^voY}nrN zMJTDl@{f2@VxWk+r5>6zd-!5MtI{r^s{4!9X1wUtI3IHf+lpRGF!!TTVXq3P)_sHU zw?`0F4D<^!sFgIcB%W^8=vxs3F9sEpmjn&fke5<&p^mb?q*Z_+N1{;-*teKf;4Rr8 z2>5u$BfSbVp0k`rL>`uZR8NKfs>TZ1L>2t`C=3iFMIaPyPFQ-eqOIUz$SL8!3GOFR~67}KkzWLS7rHM`OR6Qr~==h$1YRIw|2xl(X0ZUg4RB*bHG{!x}fT)v5IOB z8$F7>t8cy&kRAu$uEJ86%~p-&e;Y{|tL1;^Wv*%w>9qXsZLHcE6$iUtj$0bP-LFJh zL)}9bnVxTX27UT>UO|*fS~*cB-xG-%L=%5i+xDtr{PuEOCE!?FU4c>JD^a3l!^$qz zZ50GWd}gXEAA3wRh9;!Rp8~y_)v3;PY}hCaMo%NhNM4*6pbrx zl@}xBipJHqsvKj;LefMgEkE~AMnvNQjs<(!#$z;Efxdyq`YeC}^u0{-s{wdzo0GpI zQ7xALr(afWQUX&kp;-!HqEd!bJ0xtv; zEU&4qSb24|kGntDpE*4~RyZca>|jA-H5>E2r7^q95VX6rEko!1#hlgsV8vM;Vos{h zYpU%%ed9dlEcCF#QOLP5x3Q+qd~f@i-K{A>yHk7W>yvjdCw2mTZ%0{PbAy%FMElCW zp(}INg&iY8;%j`&Ss!-1<7IgjO~EQ!gK0Z&V$KGz;)^x?7dYgX78?#3@rVcIh!QF(pg?@GgVdX(%7zQhbybOhTRrRlG4u%;QY0USo4=yuPb=M;Pt9mhKEBN-^ z2+ON!u=1+t-LBvIJae`Nu9%0}dl@WySAE>7?hfW`16;8XEHv}-=rzuE`;a*=)xkZ#gWx(~GAE^vh zUPXP)YYr!Kb_A~XqOj0VXz!}A#9J3KXJ;St?ewy|x@M|s`kql8-(^m;PQIOC1gViK zucr3OqecCgvm0>jva!4dCaX}p!Rz^!IlBYbt{_;Z!a{v-Yu_s7^aIx}o#oNEMZ|et zb*)mx(L>3$VggF{CnCcX+FJIMt0gZ}76hmdI;{sc@>dPWb5K%sC{%3NM1fi+PQ` z2`(z}Fjhmip$)j%k2@r5#qVxGk(MC9y!`Ig81t2CjJ4)>wDw{&dFq_{kajp zu7IS6f<{T+ok^0}dOg38HJuZp$WxNDGD+H2h1!o}O=l-4e5GU_yeG>u??Skie@oV8 zk3BlM4{O>7i0b-C(r!buok^1Q{cQbt*0eVe6?&9pGcAKoTZPY@t60-s(CJY+`G+@= z8nltzcFKoGP}2??MGUv+%q0AY=$Q_NS7+>$+u2I*kR^Hx4ux||^EizTp80xv9 zLJ%z@xAA}PzJYh-(5RSv%Hl+K4!x2l#_ZIo?|wH#G(gO>xM({!(WjPk>3t6A1J>(Se0fHXI_xBC9n5bx)j+83e@LzlAtNk@fE1(Ky{oIRlhYCa?#I1knQOxgQJA zt>$|fbV#NIfN=;k5iJV_a#w5a?uZ!Vb z<~8lt4|iz`MU9yA-au;D-RI|{E{VkH=Sallrr71Rgk7;40lGCItTe(7gEr@VenGV0 z`sZL}jH}?GVy9vXofLM^D-%epC>&@fT2`zWNC>Yndm+ZOe8QB`YyYady8;xUxR>Jp zNTwHU>r$5i`OvjbT0Ddn2&QMk_MP2A^xP-8Um%!SQIyc58vVzSsDur zlbtKVX}CWBd$32~YT%Phi`N=@Bu#n^g#+zG%Zjy@iM6`In$c^0s;zwlikdLz18B#R zz4oBS2ksJUi=fqO7X@hKPBvJ)hLOJWK}`@XUW*NR;AerZMNl#&5{&>zC`NKwv0`?kTF48dx$4^HTkVUWs2OuU982}uD&WCX zNn*vQ)Y3u@1aBLeVD%d2R?bz*SV|_Qy4&ne$`;ZXUr4WE##KC!C&-EfGcM(|?s_gH zOR8xJnA4m&AAuRk@%NaIPv0bx>%&$gHw0<^mV%_QmpLEv38KYMFI*Te6MnirESVBX zlLRZiAxO0BNX(klEhmx--|4U(iZCyFEX^mYQSO*hN+h@HRwTC};7(dN($p#A&%!{3C(tYy92kewUGFlTUR6W6Lxp<79Xjze94xx~A&FPaZW6pMl zqKjZcnorikCzyImpWKn;lgaQ&EJQX~kYKLvT$}EbPLrme7f9~VMGA!kGx*}kF`{Kf zQe@VXZaICD_jS#QP=smW(`i0=20n=;6q4CV^<++v)&r2zisVwAIiE@QNon4|Uj>rc zVUa>1K_6EV`qtOWd#| zBzwy*|4|@$GA>dmpESmJdQFsQS&`H>kyOozWL_vX6pGrwgfyRETfw(0sF18n^2xt} za(h77Wgx-Inp5l+Bq6D~@W&ekl65kLLeeb8ivR7)iKLDhT~+m5K6(9}GdDofrOdf8 z%_mXviLQ{m;DMUZQ37i7_)} zSeVU)fmtVp&e zsIL)r8PSDhR_7Z&L9`&bV$x~Mp$N%#k7PX4lMR-7f;D&N zI})BHy8ei+#l{dt*SB$zLe+S5K*c8#M9Ye#p;=FA=8Ue1D@*T&qRW_bTbfTW4yF}< zi6jxTA~_YIzJ`7lB$$jjRfA?h@^P>4st6>Bm`I_JpaUvC6(L$yBn?a?xz}fwesH`L ziY|u3zDlN%()}oCm)aL`k+Aan@6NjNYDWl|CZY) z4b12&%o$xr>hIhL?H!r(y)>Wff=@0{(N)5%HNM1-8ox^yb{X{q8!*mYK5493Pd2=^ z<7JKnIwVup6Ldh(M6|3vsb~5m_v*{{BbM!lqE0X&%_qh13ATTPPfDCtpOiS^lidMf zmw^QPMb6@=AX=g;>TR)DAaQymQzAhJ1WiQCiln~jlNvdF(joD~15nhNIZM)fQU;%3 zw@M&ixXe z1`0FF?ET6UFlVoZ5-!2n zI$w!Lo+febLl21EOUGuNcuh6Fdnrzflmy|IH-gXuzo_#q&YQRjK~zex1qwxq##K3Q z36VNQTg|WNPW&*I7Mai{5HcbvEM|5mKM_KwjM%A&7`zxqaPVd!17X!&=gW}>+qUoP zat5hPEa?cl3Des;VY(dsNvWm~UJhPqT<-3av_V;v`K2i(D{Qo{0IgQMzy^hasPNtz zBejYq@M3efM3d(ixEoe=HLoFDsA zVNMSSC<5j*za<~QPK%_J2VCJF{FFPOBPt%O6E@w2%>_C^`w$%5k(U) zu`*LKEd?glIFN;ulQ6OHTk;s!M}c_mj`VoND=!R~`jNxeLhMTBJd6g6uVotXiZyB4 z8JFIC5L^4V+7!$gUcNOh<8^eHw#J1WDi~;Ez2w1!ASz&P9kh_5ZPv+GBVh0hucBp- z*O75nGCE9hJYG9#w71Bgx#=VuM>Af3F&(+@gE#$1gNpKL&|L8lHFB&jRy>3w!*JwI zuX5InL0V&{>@3d0fU{(*E{F;f7Bx!35k(_R)*sDXvtz;rSILb*lIJmra}BAd-yFZ0 z&Z?n5|1(5;Fz3-&YD`Y@@MAvGSvSS3F*y!#XU616%^H)xL9!%77Fb|nWwt~-vq

  • 1m%h* zU|tqxB{%ydO~Ry>_iT)49Ojo16`|~GYKw|jCmD5c{F+gNk*0__zd?22bx>8Jl3(Gv zZOR8F=XKgaPJu-v;ym=E81pU@w0FxzYz(Eb5%>~YEN;n1k7I9>>5vdQ@X}{uh&4h{NOxtWN+sD zK{Yi-W4bzSt)HtkYyIpWv$`&UvMAM{$BK|@I+i>WB>T)3h|1s@B5|6)OJxuVE1C#Z3g0LEk|slSG-y9X zi6-zGod-LehWDh2_v`m6UyL+;ne((qR!zgB>l4;dz|SGk_;9mIp3w=DYJ83Z;oE-7 z+!C|Y@2^h?qVgzt@8^)BaaB&T{25)*vU{|q&Pt9O2WipJRSsljoQ}!A0^p=97_!_dZk=X$COo z@4nP?%zt{AuiUH7G5;mjMC?5^=y(1Ngyms%j`^Pm^X);dO?2>FHk}pT9+RgEU3Qer zo?yzU<_>!sHe{{}luT!NXdvYg!@L$+#ko5wGgqY`tK9;p7G1hx;T-e7y)}CXVFj6pqgcx(`iq?}_O^y3%rGgnpEvEP$&j(MuP>{I5dj*{CSN;${; z^r+7^Fjt`$ECB0m8r5BI)8^X}=Bk-sz5`myIp%Yt-m1u4wPRq#k;3^L#Q-js99h0PvW&s<*MdOytUz0AD2 z>T5>yKgC>4fa?QW$~orOcSVjdS5qCVV9GgW=dVMLGgtE{SbEAi=FQ%n<;>LrxIPS| zoMXOv@urE))e^WqjHR4ozHLU`>CAO8aDC*1g=QIc)fOy$Wh8T5;sYy^a*p}WKBpgH zu1jsq_pvAC9P`ZXPa+)J0@uf(lyl4ny8e3-bF~Amj}s~9m={gk{Va2J0Iq{t$~op? z!4oT)>+%p-@sxASI|AELhMfY;cgUY|j=9~0U9Fg_3veBZrkrCg@7XuZTwQ_du$Qsr zUR591qR370G4NM+8!Nm50eip6TI_u&RPZQsT^VPEUHptKix{b9Mk+5}Gn=`3L|9>G z8&a99dm>}zZim96C@bt3Ln>3@f{4~@6JxI4nCt)>TWGTG@lN$@dyBdH23X-`P`K1o z81n9)arz17>hEQR?V)h7g%z1tzkC~W4M?!Uc6e$4vli60tKp)yM5J@fP$7tnE%K@}vJA)M)H&uc z6E;m^O{Yf*o07aYlVsj~rQaQeq?ZcFkc?!|S!vD%-*#qAry&md29)H&Op+Bpm~@54 znof<8tCZw@nR2hNzE#CTko1wimE@94I_>`~3r=QDr$i`dl;nMxB-y|*H{AkB4@I7m zT#_kw+o2ktpI}Yz3Q_n<$w~(eop~4Qsyyvu5=U3FrdTsU%S@7X8_R>A)rn_QlFb>h z?+!>J_k52bsb`S1J=Oilde*c1 z>2aQ%XO{1o?4jj^tC;IfjF)~VAQ&(4-rN<8i*EK69m+~JiN#@YX1Qcjg1T9`G+Oee zhq_t%@$r%v44{{W3PH3i<~^zF&9XPZT4aNKac4pcB zeTDf*KajcZib{y;%(81LDig*Ba;+8fHuD@?$u^xv3zW5Gtrhklksw+?)qVCvT>(m+ ze3L~(V-9Gd1X%#^0f;&alKZ6ZH%IPqL($dDH4Vj;?5yc<2u3p!$w7fcoD?iMs9T+N zh$Oj1rn6`;q3EvjeF}?)LK`qx9N8*0ugpn~%nf zWP=%hG{$t@?H5D~lAdj@4GARw1SC@;!N?Puh?W%zhO#RDa-UhAIBg~QBmfhXPmCg- z2cKX}E0B~{PH>-ySSfYHE%8^Hk7(R0t;DQDv^5wKyXM8nOoW&je=i>Cc|XSmjgo1` zAM{F^#EQa!cA{m)TFbd*$28-7) zs&|FLf@ne4xXE!{psVJSOo;?zeP|+DRwQmS{&JsLKGtRX2q+rNT=#fWTa85?K8uh@ z>WL;^daWMX38RTGtq&jWlU5pD!z9GDh?|+@wH-^e7X+?)ifQp$y+krr6b`iK#M(z; zr6)3TozvL=+D*ry={lH|NcGyih&xP+B-Z9$tJf~H(Y#35WrQ^5QLcM+L9}=+y7K+C z0$p>jWJ<5W_oWvSDZAG&yHa&6_nGC}M(y!I(e=!=B$$e1sm7;j63Hb&E0Q(=nyZlw zmiWWm&b3q$El9R*DZ+LM+P~6Ef+B@#$!jK9X`2Aivc_L;vnJ&}vplft5E@F|029)D zvJ5`K^id+YOtc!JG)pf>#Krw&g9QoZo33TLAX<<__02d*Oh_(ENT&1&W}(nTw5&*a znn=21B_jLNCzC#^MBV!k=31WSlLz1vOlc*O?nyqm5^O8LQ~ZeP-FV>++YO=th{3=935E6HK!ulD?WXy88KP zo=ras5-;k>gSsGEka+q{!cILQ>8nYmM1t9RX+J;FvLY!m>q)nqKH2SmyEzmMWv+0V zPacL(J_sr#gQ8X>fiTVek+4x>tJZ?-#21O-PBEbqmX&_9r>_|+X zbk=i4*WS|yzJ{WkU_zQtR>3D91{9K^J}Z)&JhUD`HduVp0`+8-E{GN+wb#Ck^S6X# zs82E_60B;J-sB-#RwTVlpLEUXla+mrkWX%Au1C^*@)&&bkxwDfl6*28KKUp@Hdv5g zO~v(?CWsa!?vHN$O(4-ye1esh(&0IM^1q*1?%>`w5?S8@6ViOL8b0~hqmYbG^2r4F zWIr!W3lgmJxK`_FNZLI55K4)BGTtYd(kJMEN+)nF*?dATB#<@!znocKy6VIrXvb2+ z6KOtK1D{}(N!Iu&Nj>9K8}&89E~95`i>cijO&Uwd(EVe!@X^MP-WN!wcqLOJK?hVi zl}K5mi(ZnTkmNqI+&Z$l^)+OJ#V74h?Q0Yo9(X#u*s3&-FL#`UXd|+q>6y45TPpA3h8TjO&rjR_E)Cxc5 zr@n@4upsFWWv*v5L9`&5&}v0hf#gxelt|D4l|JUD1X+<7v$g+rW_fdyIn$wN7)(g> z$#d|@!MH-QHmSxxjT-+xdDDsn>v*o`bV0Nr`E|hDQ3A1~8j_7o>?;J4=Y5hX zeS!|Cbc2UzS&^9Y&i`^|c}AjmCln2b328pr0G}L+DkRaQ8vm+|`Wj)EfusuxWP>h< z7N2a~QVAy{sqKn-B~v0n2UPkhk#Zn0YkclA%aIdruY{rz%=JQ=PhNsg4to`nElD+g zYk>M1vcXbMy84*wB~1`5NJjWRIxCQD2}-6!f)1#3D=&|%KB;RW$$e&dRw7&q?br`^ zDa|LZV7&>;<+2ryC9G}NjyUx-!Y;!n-EGW;wimyo+1Hp+>|TK+mXJ(|1RYT6jyTb> zB57#WliX*PXV<)<1{95Au8nCviE4axUm__>@<};-@^Of4u=oVq0j{Vfh!&q59J2Y} z0!dj=G9?mpK&9mYqGd(Wz(kV!%yMkq2cDOB6lPG_Yb#3?~`BxZEwKC}Ggu6^yHXbf|`nYL!JCCv9u zq)(3M*68{)Mtu$0VDSkyTU=Yhf@tx{Vf*S60?83wGNn(@0hN9lBU)A@^-Q1SUVZ7i zAwCd_#xmDdwPsl?#EP?j%%(XquCo%Y> zeN6e}Y?4oYflm%ey9^}#z04K!q#-#ozct>CL`cs1l98YTD*c5g$cm)C8C|*0EPr3) z2C`=YOi1&|d+-VN{bY3gndFnd;FH5%VV8jf8-=d-!qQmNC+vcec>>9wloxqQ`UD+N z>0dlS79{`m%<}PBW2ZqS_M&$xPr#hL8gePii}IaHaR$)!o|o@bibFl6fBN}Or8t;T z)(^G5+zUOhO`ZOrjZUZ#M0udZh3!r#QnbxF640h6)F~RR;aYzHD^Gu569^d*&yHmF zO1X~loY9P9OQV(zdk|@`&0Xx5t6$2*GLMhe>ZEaHRe&Pym#1CIss#A%t5{Sn!zwiG zzDm3!aJQG6V!?|gJ18XkV6!YVEEz$qq6xg%)`fCK6KmFkQC8-%^xF|C7p!BKjYyCj z;mvqv`Lu4pe0FJ?SjpJ=^;I(&_D=Y&7I5@x0#E$yrP!=1%$K^!cX6oO{Ket3e~A7i}EmKXYnD8L;vy$qVgfuI*?S+ zHtTd{{wSogS555Tl}(M4G%(rDO^&9YKWpqYLiIoO7o3Awkhwk#q(CXF5#i^mB$ROx z%SrRHBJ9UC_fRetDA*K5B0*G8u8*;@aR%-G1O*%83>lF=at~{ney-JeD!cFG`x-&? zF6KHIOpU@?h$f0V;gwn*5qD$_D=Wm^2eL?6*JL39dpeUjF=Gzth{ z0%k+q+PJ_%0wx=m+9;3@V+!VnA?iWM0*f~ZQlo$%DwqVRp{{6~am9~Yl{J)!)xIA! zIJIL^PQparQubkpXav*lFe)266G>@Ytf#VXoZxGPG*g-Dv$V$L5L{=v^DI0&i%)%IiUlvZ^^ivp6<#WXgAqj&c&Q8y%ESsUxwTPD%1OL8`dC@lAkny6 zFHVnM>#1z_(ET*6pT=CeYEz8Pzm;a~8e1kri^{DjI|N`T0+DA~JW9Qbu)}CIsWZe= zHu#yHA+@9}6N<)F(aAojQ?#rt4DWT~QIg}pT4w;($ZTQGKCz+&L~)GnD>bUYm|u)) zd;mrrfQZ*tajTCy`l$P(Tr55!fA};(R6e4zZxvTGf@1yUY%E>W33l|6Jdepd-FQ;q zOlpUhZ^5+9y})C~$M2fa6TG!Cx*Ta{GS_!$?aFImYXH8gTLbXbps0hqeJfkw zwfb;h!aUTL6ppWj$vzV=h2yKbqHV?%KWJL^YEaS4=5v8p(qugw8f0br5=7&8ou&_S zK0o);@pbPZ%`E2nQBUnI%H!1RD<2++h+!Ewt88nGAKR1d=<6CGl+~}if}c+72=ffQ z)V!C+1yRK;`S(CX(YRtd4+!OoCh!ur*ELC#cyXo&84-=}vgHwqS$^{R0}NXD#mBll zc^#G>XDcFkU0yzqG;^5ilrB$RH)i%8nmVazAEZ|<{qc3?Is<^8;Z>@~yo$v>kJOkj z347M(Z2Se~_G)G-w?44vn`fEpJc{hIP|AC1pTB%0%J(;nBQEiy#n+WWdx2ip+Y8G8 zzf-D&Jo4@O6GM!)(UkYke!i)!J9GUN;?JDguQhWXr0u%3c{AqvJIZ{YYm5!lZ8qk% zL9iRTmmy|mgSEh|N4qjN1F+BIjD6!(b}-$$smt?ac*A~}RXK~po*pw*75#!Su}7G@ zQiS=A`cvM`J7Yx!Ue9Z@WH zEb{4#um8f_o*1k03-X$8vSxS>RZG-j?rN9>`>1S8h1crdeocokcXgDF4pvo@b%FN0 zvt$8t7s5w+kU5^>Xv@aMdog!Co%y~9Fm~LlSWJ)Hzy3%Gb2mt^D(8^be3LajvN6={OXfy@PH%#+ z-)QDFSYH@^=QwkFQ8r)1n7x{r*9H3DGk&Yj+)aS;OAOA}a45~-bYC##{mJhhzp6cR zU+Ccv(A%#!)d%#}n|i`4E&R|CvEj$?y@M<-7aqLU^9g^sFanoEu_VA|N7T_!%WH`9 z?i%;^9{zG+M1qo>5ooV*WfP~MnNmd*_k9Oz83r7D*kd|;82oxXOgVYt<{H4 z{&HbdQYASjlb!ZoB41z5UoMQOSCV&Ul4MUToqH#LxiI2QNzTe7Y5TXfKFD7#40kHY zFHFgABI;0X1^x7;dsvf0acY9-hn|Cd;WbLhl(f&-G~sd9bY_I=w37TXlO*1M*t`R4 zIs;$C^2C&6d8XWL8|FOF1d@J=NGT~osOc;pb2n4@h#Jy#7V@qYQF6QiXgV8T@o)xJ zF1)2`dKYN6kdj-b169-6A?ErsB4{>N@e8loJgs<}Y{@gflIP31>rWxo-OP=lt?QJI zYjg#?4{>+bczZ6EzRKQ3Q*_2B7p=--VQRG@jS@AMzR&?6ksw+YR+n^t7ANx21we;n z%B3%~{m?`-#CfLEysYA_5d+C;bWYh1&gd!|y5uwzp;zmZ=97LJA2~=QFTy8gJ^9oIBpzXx zLPA3gcRx)KEl74fJn~BsT`vYCQzAjdD*Kd3*^!{BQa*Vqr%x(q*{66fHrapaPGqB=aa*bOH_6D7#%lanTr7jyb# z_4a%6py(dvzADWpSEHVM9#=@d$Iu3&G>PPg2o2201`85~w(Dw55G_cq`ElK~e3V!A zeM~Zi78>4_{SYBqb|hwWJ(<%d>${vE14S6`T%G2VK{_8sN}rtZTaldg(m0ZAupoh9 z?m@aBT9CAzvh;d^fsSM(fDTPW z%ZlWb>5~_8A{l*A?fp=6FLU3J=93$(ZC81L&k|kb7kH=+kqs6k)No+z%!wAC{4~RH z3y&`7kWA?lR4iyBT6QF+PhQT6q)PqyB~Y{kCZze~CTrVOUQ@IBq?VujMK+`$xk(p9 z3z8FC4o??8si{e(L;@$4*YXoB8CUx#xH9@o>={h989-r1hhh$15n9o5I(Xt|`Vj_7$&xNFx zzt0O$v=kKftH+r8c3luHNPe0e{YN0_7?Vti z1klSnMTnLiiDvkuERqXJ$;PfXL(%=rJuJ;9!{HN}%kptoxgRwib6JVRkH~8kBO5F} z!Q|IHToXhKk{bedd`F{v1|5t7P?8B&pHSO1MiWGfPewfY0;c#_{wTkec!W

    H+2+pXQT^h#)M=$a*ru&(~pO zJsIhxr5Ccnf&{BL?unWpT97=|Y#5pXtmBlA@JpujNhA1Vq?c$}k<`)+pM07#x{CJR z`xz9igb8UrxdRdOMNA=?5VIng7$KBog9QnekKA|Yf@nd~sY8GCSA=9jOfn@BKrf#d zAzD@>UJH_(K52i^v=vbFAahSn^GOgsp~WlFcFhR##VhHPnE_g_qMrpx6BK<=6GRJ= z!I1&uXw`z1&j?DUM1obX@|nCmvLb10M%QOKk-Xi(Uj^F3Fd@w+Q{a;?BMQlU)DtYj zNhAwUPrmdCyNtFAYi{l-x-`~oyZ#un@N0o&enK)O5}o*}sX{65s<`FZ@vWHq9zQ>CnY@>=ug24NGWSAC zm0;q5efMIhr@f5D5o1|96!|%?(g5bZ7Y%5;5KG?6IB~W~8|GeunE6^`_Jul%)s442 zG<+kPvMVwB;1!QD_x)%LPGAxA8?T{W_fC5BGBZ#Zt-{<7#Gw#7AlKayG_r8?3ko@t{6E89M6UeKJKV>gt^{qF~VD2ZwNQIW?DPF!$A<8lSOMbgZ zg^$ME#oTLc{0wLEUdFkvPk+kXPy3kf2T#h@!^F3a9bxWg5N#+}U1wtihAL6^UAE2vy9;trRnB2>F z0qW6+CU1H?*zDOGnEQnU1mh{MSGjv&M~%5(iqV-{)Fjkl>}4$S8Y}7uJ@tZ-c1vA_ z`~@QjToOg?Ww??r#IU@IByaf9!~fwg7=gPD$w&stO3%){t0RBG2nt$BF3coZvD@*x z8uJ&7z*r@DU#8qEJk`DPTl@thsH94ANhY0k*WSz5@E44rLMX}mGD)(Bd{v&|FBm~k zDaj?7a<@I@URsmCU<5u>l3$oQzlo^wtYDw(DCK(@Xo5%*&1aUqjIoJY_ldoXcRX;PzT z0Qg?ULqSOsEmhMX!g#4y$r*bYXaxoB|FV}+cgDhEq{7zg+Zc*rFU+!+ftPnsdoIU7 ztHYKx+VUr&)M`W8+TWrBaBtHE(b7wOy7+}PybCB_9hOYlOQG$DCZc8QrT+K5jOKNR zybncauD1tMk;F9K$4Dg4qM<`)By1>u&QF~T*}IV5nX%zk|~j(VwLZs{IerL zQ>A>8doLq=y4mkg^aOL4run2?vm*J}XZ6WJ5BZC1NI_CAi54U~I{gb{H1f&EK9NHC z1WqhJ$jc+EPfnUX$-M(`$$KqZLHm=;U7qHXy@((T*`!ZCk6PDgk77NL!ZHa7#(3_% zx*%GRym+oY);TcBEB`zynbId1-jyE>6D>Ou(Art*BBa?pNvYT^a;kq z&_uNCNKBvP-j%s=+_g_a(OTyIAk8Nq!6)AZ6q551E0SMBH25YPEcFD2xj)hb(SoGt z*{y>FlJgPClt?gyFaI?}w5&)@nMiW)WvrSp^%p358YZOqy~D70$f_uxUx-5-56x zxj#ws$)~6%-^FBf?eV}T#v1LOs_@D8K4F(pPcW%-f2s?j1(Xt|`q8UEPy_fOIhDD!45k`1N(|n@CC*MaDlE(0f zv6r!@Nt~vy^s^wr%n z$J}3}`Q$73X@Y1$(zwIQqXJ1QT{5Ll0DaHJF`{Kd z^1tt8ygA^Z525JaFd@w+-&otOJ?(wg=<491Iz%>DkWkz8jV_25By&D1z)?eruJ%63 zlt@sq_H^(NEgO>meJ|sy$=j)(tY_}yX+AlT)OKAFwfdxMnEWN|GHN^_IiU%n1xbm0 zCe~;vx~_;yrbGfK?&%sPT2>^r%o?A22cX@Q#hak$d6klf~%Oz9J>H|@FI zOSG&={^uQlx$Y5_q38vekmi%0QSLu#3d!i0Wwm+FmnGy+By`YI`S&?`x(Uo%t;P~QY2cYOh=1!#flG9Lx zMbgu0J~^AzcFjzxC)gc89U>bnKA{?aRu@DIl9Sp&v?vr^Gl@s|B$8)rpy@=*ilnJo zPjc^N%v)FG5h!|@xqnIX$@!$VYeC5BlMwk!L&{Vn=OxjCWc1?pC?$%n1tF0_Awf9q z3GoEkkgx$dE!6S%-}l5`2Az0iJ@seC>BFIFBXj>2kvkW5W~au3x&H|AsV+Uppbp8` z)_Sa4e2BUK#K@!@nEdY{u8}f2^gxmOl|$d(`nf z(nMK-&BvN;@Z!k?KLu)Us6l-}1%&&6C>}D!Qw983zwO+_=mWQI zyNDH3Ot8YnAy#3Tmjv@-IE#a)Q74&#lcL|8?cIkJI1p$Zd`Vk0dZgCm#hY0{ew?pc zh#i#zmtX9tT*R|>`^PTj{&jS=xiLn~LV+}oDGm14| zfA!6O-OUQBBH76>v)9)RR&D+G_K|B@L3IEP#F@Q0*Iz?tzMpL=p9dJyZ(k8BsObd@ zEAMFGmDlR(Cnr6yh85IGuquO~zA4vH*9JkIKRgZ_>mlnzAmw8L!-Id-VFmR=V8xid zo@rGb?S_?u;;f)yfK|B$kG@wlGQ-!IKivLd2Ug&P9jAOLp9dH=s&g+^&;(_53J)pO zF%;shVwIcO_OXIyFzU32C4U~E&boeOte|-utWe750q$M5Wicyg5dkZKRE9!)9^l&G zLX8!)3^LytE#>n7_a8jEmla$LTxa4bp9i>d>78I*5@5cw{*=!HG^;k`94ojKxXwnI zy_cC+SN-h5k4ssBFTs4jcvC(P@O|*p9;~2U46HC-^lucDy_?o~jQ=fG&;hv4*-}0a zuwikF4_U$Gz;!N&RAyeC_5DNg&$5C}z;#Yf`8+_gADe!|3b5DYJ0F0BW?o&jn|A&B zGAron0V|gBd4Th^x3**j-GS>@U&`kJ+9v+)#tN6ee%YCMNyH3U2nW8izuxa(7;1Z_$AgYuVj( z8*1!rUgrDLD?blVa65|hPXt&KE;%g1e1D;R@bbIiko+qsKMzna0+N5}@~!^`BO&=W zf~6Uk9Hrwf#wy>>@5Xppjh~SF{W|40Ho|KB=x3}2zZ<8s8vn#>_%U0}Y+H2?A8-5x zYhD;5AVM_TR^7zQ2Yv=gAC-n788Nn&(6!6$ze;z^c&!_2UPGfIRgw!cNmg7jQ3LJAXscMvcCbEYvgTw9QIP{);uQ8>B8qO5%YxSkbIBKwTcusN||^MEfpAeXgRl z(20hoykH!zxIH3Rnpc92VvMD53ESvXFA(Ib0gJ zAS0sL@&AAQBtz`i*Zzdu>#Sfo%7^1rbAkgup~3&jFDDTN55)LDM|_guz#!tO4YdQ; zqTxO1g&u)SSckC?R0yJF_}X*j<%h|$3>p>l4V~Z=_!;y{ni!nZpb6TE22W;sh>H*N z)K@3QYc|&7+lYlZ{+S zS(~#9vImI-(E{qZc%!E|DCm$(2>^bBCi-OsFwsZni?Tm_cD+`mGSa_+oKYvZj|>10 z2dw~xVQAXc@QRk8Atq&=0^s4GAX)%Sn!Dqm05B{rnGyg7st2?L(Xs%*Y(h<0|J!#K zcJ%u73>3Y|3jPIuCnH&fh{C9s=AH=QaU$A;4F|?YXxK|OSddipvw~IJFf=Zd4F6!t z+J21dSAk?)Or((0BN{wI6Vb9F$u}l?_S|2`=sTv}aVWxc;1NVbQoSj73_kf;m;@wu z!FKpWyp#UGl#sRFOw|Z8S;SieQEzJK3@QZCf@@#mv0DVLyCRY)bn<#LB_wImYbcxp zQ#GPx#ahe6T8PP4_W1KPyO?HqTUY^Bom0H_grCndq}T3_TH|kSm?j!zgT-r@m=rwW z7eouXEB`;zz6DOI@&A9GWho~&6Zrco(Q?sNVX#Rzdz6AoM&ct_Ba2RdA($x&+~ac=ktEQpXWK} zJmnXpi)KnWoChE5mE6CY6 z)*xF(tS7swomef_DUI^W5D2FhuUY9>Uyt(BJc)IDM92C9`lLIvN1<;rP8n%E6laNf zuX9OKM&5gSy4Mj{$45j9+3R@^eZiDAiM2t5ZHxxVmJw?mSJzV%*89vVbX{Y41|iT& zmS?HGwKGGO0#7oo=9S6llkN=pYM4%3DF>~GBC)(uQy8@#`r^J@iUhjJ3c5tnD8x3t z8m0yrkzA)#`@g;^asGje;t2FEQb?wcwHY=)mzJuPgmfgO0XmsROC5>d&+=y2!l)s6 z@bJ^O2_z*FyXt>u1lY#X05!;nJ`H)~w8Zrcz9!kNv?N}9X@O>llMk<1Y@ zq+oO7n-My}ryMj*upp54hAE61k{esrI9VW>W64UXNwWk)B(h~j;`XlUzbWxWzu_++ z(ECWCk|uMY$pIV-V)ui&exaB(B$7oQT69259Z3s|<;{UJ88svY$DjVWK(f#;DBv?+_xH3YvjGA2IBB}nH5+|L1;2;9UkwPU+=0g*#%}7l?NYUg& zX!56@a?p^R=Vy8IZDG`q{M+vM?E=XMepxAzV2Nkrhh)l(LBl>Abu)vhJz!XLe$slss5W1@2tDzD+KxoDOA$rJ!pcJRG~@28`XMOA|IL@ zNKy`(CRlpSd(Rd|O_Mea?zvJR@kV8()TD*Q5Q%IVk<@d>$^Y?9i8`PCayoblCBsk5)4@yZS*a0Q##L1Qs z37V+hm0#`LwX@wdryvlP@8gv;Swos66_UpKI7#?}w6CEYG)=IuowvpoMh!`etw(Pa zNE(~6QX;_)2$9H^5lLNFlj^@I(RknMw;~WOmEcz5G)>k*6D+IC-qj*Sla|orPuW)- zO|TB1x7MV@QjS&@k3DICK+?jNl@bYdK#7)dvSmb4M?+HWp7Dz}Ki+~s>sj6>n0QiG z3qCdYRRD=3kfKQ;G^yY{T+;-X4e~xUD6teI%bz{*QGq02%1Vg@JD@~ikZhTexV@|T zZ%Pa(Sb7`+eTo#UbR-+1{Gx?K(pEpJPqYirzJ_wpklbXjybV$)t#>_q@eTO`Nn6=M zjT7vE5Q(B>L{i^HQc&$UIdgDtS{KE|vCk`MlE7sO+Zpj!S^9`?AEA8><)9(KMVY*W zA&eT5d%t*~SRlE|l9f^u?0^#OBV@~n1dF|D#MiF2cTF4p{2K^_tBr|Dnrw>lOF~kU z4t^cUO&;3UP!1ZBPBE6ZDJqN_lBZ|icC$dz!7nQ%66}ByH<2kb5?s1fNUC3-Svzvo zM+k)Ths~8V*#b>)1xq5iEk%>g(Bz1u-x=|^p}7pXigMeGTQH zA-UaTd0Q)MGG?;bS0L%5DrN7&4hWGbN=8j^bAduq{Wm2(9^9@80+l0$N}6nkCR?4} z)!)>|$$%j3YbXZ|39f(UZI240HclScG_A2f(qFbva~F0%i2*@skP*r0E|TiMDZwh5 z^+KRcEN@38O?E*OTz!?}WU#Fx84{;`4dtLA>E>a1yAO5O z33fn&h zYk9l<{PMQAx|SG@(Qz~?ucswG!QSz=AmRXxb3LuQO(BF)T~F(YjqLU-+fo}1=t?=l zDch?i{pJ23ro5hpt610&)#RXA*58zPAW&}_+H7HY-v{L$U!|CcTKvWrfiMvTia$(w z{V?%DoL{mRi^_@rfeT!+7pWxv2-6BRrJ~`*k{tpHqr!_NBZO5pfwz~%5M0>^FUz~j z&#(z;lX&ZU7&b&U!ux-HQ)2Ff16$#WOGkS#+wwy+2j8HR7eT`O4HP6pA}bXvk7QjcjS41KVGve0%D{9(OkxR7pAPc`%)3p7O-Mfp6HC~M z-{NHBveq!^5?qY~7GuBr#j2+JjRozS5)bShoRb0 zFsSg3NN_GB-VeFRl!_)R)-MykJ2+O_Bp1n=bZkqx4QpzNWg*d6;U!*1B&1E^C8<9& z$;R=vvlZT)OXX3Li}z3WGWbI4%pqul3%2`_fI0*h19fInEQIjn5+6aeLvhtr7Xdx) ze8W$}M8}~slftMp#99ZMD%(<<{&IgxL)St9)zHjCyhUNE<6ZTv%5Qwvzff>XanE^h z{f6Zo2&GH+mLbFvP~NnJSdM%*Bw+vxaFiEC2 zEoI|@={_+8S2odAu^fj@NSl-nvlli*HZdaYN}tZqVK)BymKku}%JTjUr^EaV$x|;B zFh7NU?uh&}!hy+&=PfGPlIZf`Hch*ffu<%wqK?27k+U^H`ZTF*0wzKFG@@(*CXLd! zlug3Kgp3W5AMc^H+!6VQl{O;v4>A03(4^DdZ7lC_r5R{5@X{C*csBtrq33BOHUS}_ z7qWhaI#<@Vko;JPQqk~|teZ_?)Mee2R5l)%%epC|Y_6=IDL;v~x5dia2FQ=g+NyHz z)j!1W$VdHOfGgIc|F)&9&K?uTl7ZhX1#_DrrXik9;tN0l1!9}!!%+G=CUSG8R@#GX ziwL6vM$^wWL)myJKK*{vx1riLyT-3 z?}@I4)qaTK)}KcmKpUHRYsJ&%(egoYaZt*|C~u$S8j5+P{0fwg;qrjM+djnaq?E(& zF`(a1ndo?FdLI-QMuiviBf=`1z)SPR6^>2dC2Z|O(of<&6}HFxWCLDL#ehKN-Nhfa zGyLkzZ+$b|b~EqEMmo$3a8C3agcL9z5jTEHn2+lBxs^Yh;CIAHm;lkn{YCeM%zHXm-yUZAwp zyp3#D=)v`dX*?-^lArgczDMe+V`nyG-X>8vM$&FiPUhq+W!^JQe#UuRBhv$5O{1(4 zt~I5;&FSuL6Okf@aiIrQhOM&C$+ypIfB7QjZGk+PnRXNQmEA_2%e-gB_!3s?tDRQO z=vsq$&!$$1wA-oQ9@hO{<~;|ka6+H@=BQ?$?U>HI=b}|kFzu~RgWI1nl6lWdqAHg5 zaf_h`XDwsi!Z<5D&YyM%`Mfp9HD%rlaLT<40ez-}%WGa+cSU{Xy^vZ()9wYo>R^pu znfGF}+Uh}uZmW=a+GjflF>f0WD?A=mUEQkN?7dS~pUJ#!!Qt`fH>cRnwhZ&GAI_e_ zyq8+2veRyV-xIubFY{g==1a4wFJd}3blt1Wdj(qMhSF|i-#ewp%gh@Dhd8)Meb3WV z9b5dtyjR(175Cs*%{!WQthxFCzwsMggj{nxnQr_Z`PcK8@f*LPo8xJz8Xd^ce^pax73Z_$JOX|(SCkI zHs%5H#7xR|yD?qQoZRAlf3RkC!ZeR5&u^>pWQPjw4YFpnv7bAQ9C^(3Rc+lvp2mkIdT>5irYmJnA;E^4lyvsfq=@^4l@{{t=K1 zTIF~6Y3hVG(5r=TnuXCw7`3I!Ccl<^z~^Dakd}r5=eSPWTiwx(0f{B%Z$X; zr201-{e1Qf3lQih=Dj;z6K`+KwzTt^XCvS8dkk&Swfr8ci=d^B1bZtq5=IS)H~h>P z>TMK5R!St;YatTZG9uaOcY4=Ev%22(+t9~4BGAvw+ozHyeZ!QkM3Sg5H6)2cLE1f1 z4w@!N%-grJCa?KtuH;A%L$r{6lyWDch%%QPvqr{ctY|(Wlj24^lU47S4~5-P)N`n%WEdd zmJ!K57fJPRHo9w5{}2NG#=QM2X)=Jab&%vIw0F;x8!QKz!Rf`Z458` z4;Lpop406Ieq>vopAan+k`_Q>#K@KziQBuXf7{gN=sn93Xdm-FSV@yG#tAc(CUrwP zl6nC;&ZD1(1c`aWVPVveT-atD4#{wgUS2mOE9HpC(PDYM0NFAk+3#vn{hN*EPVCYg zf%Y@+z)G47f+j4Xkc`Iu1m_1Lhw{-l6#qI-IcP|5tm++<6h;k6>*1jjX>Z5MM^has zC6V9=7Lmx78HuY&^>3RxY977-fs)Moa3xKKK$D!HLh@`tNAjFOC@BXG367t=L&CzS zAt}G&hvx*6XF2~a53~NA$U?d_qj`T`xsx z42h&uM*Jhvs38d(t-FifH6bQiC{1V~;-x6rG9z&{ss0^J-HzrJBG3Wm#mRK)(TaCi z%G@|GGCe40VFOh~eSM^m2}yS_#s zoEAJ@Nt5A8enur{;TeAI-81Dgahh|SpK{Q87f!*v?u9vL?mF0fEr%=enFr=nKx2NlTpy*xTqTO@8D>q zbyCe;3o&0MuiXbe#f8WI}uW0S(DA^G^an=cl< z>q`YwBEi5a|0+ZcGHQYa40YU9{r4t1^_e^dfeth8)0H%NCS~s0nbbAel_0(7mxkmS zl`Kgqj#e&M^TLfnlbs5tL;?}ZcO@uFMkICI5x>oV8#Qp>;k%GnL=3R`}}FIp%~f-zS97nw36Y2s>9{r4umnDEm+1UkyRFILjzC1{cx zmq<1-jCcphrkoI=q#QIPSab8f6c$EJlb`LW|8gXVAuFXOfR0FH%c#j2t|rxgZ=%!J z3%Vc>=KGf`Y4VCbcWpWWBi`vMnVvAek)TX-J~Wj_wee6vQZN z_gEMrZaO7Owv0#?SMTD>7OTk@+q@+vE39d-+-q&MpqzV_*`eUL z4$NC>vHa(;8h(*Y&1Rs#){HPV%}=G7NtBW-x0C5KyU9#GHDU|%zJclGMVt&h$G1Jl z!wPGejP10j*_%O>5}t~VpoMwgim<{Hf}V-RS6ykOB;d!FpQ*jfodmEl7 zMm-g`@VZ!>6`q7cf)2d25baJ1qaF8L1kaOfPsNSAv>2WzhY*E(E`jICakS%gOM|R1 zFW{-@#Os!!U7m$@ytD$IUc*yyGcT=#Cyt{kuH~h7;pt7HU4SsW7iWbyDyyJtjLf?V z?Qn8k(UI51;b{at71#5+)$lZ8h{@|dfTz#T*jt>=4}&P-I>A(4T8nlC9>zZ6oP7+> zf-qxqc-=a97TAof<#nIH^AxP!&*r7|aaLG6iFVxcGqkG%=HK9@4e+d!U~CO9eGX47 z+p^iblz=A|Y}tnvVJHu>!g_wRD9uaz z;dy4jQ*j+{mxSk;mZ#z_UiW*P6*e_c$4h^pUDJrC!sMO@;n_5azQpVPgl998u}z$_ zL-54uC;OC_4hLCb^B`kia0ZW{UGo@Yn|a;e@ND77h~srf;n^aJI$rt*o-I9$ZQ-8B z;wXhtqPl$iSJ=`VlI51y@~EO!|%6$Dw~c^;O#(jp9}pxt?4PsQ29ZvJWTJkMsiXP8u~4bMP` zDB@-MVlK6X&d?^Zn)*qvN;Da*eYJJ?slj5V?)98bj)vAwr zeEyBl>{9GEaZD!P*;liUeaQcP4$HsE&kBL9=9%yl_o>!wVDI?y8Q|)eL{*fr@3;<~ z;;is;DE$*Jg*+&M-|s9B;@=uU2}=LS>u!VR6(PnPWS)xc*3Iw!JCfz!4(EjdD5ete zR4fjE^YhaX^Ns||kD(jy_B#YW5!lpnK$ z_W`b1U<$K=s#+Fqa_kQDj=sP(6Kps-dn%SC7ao7fFD$=bnB|ux(aLmMEl%F(pM_3( ze~{&uB487@YH4!PufeNWet+O9LBKQJswK(i#tvD-@*f1Q*AcLZo5s@cCkMZ|n&m$P zT+?HWVfIoPz7rl2EZfEM2gX_cYuJ|4aXb}E!sfo~?_>E7M_K+<+;VZQ>G81qAr>@` zvmA^8l!n@@@X7$oIh&Ur^`m65oU?f8F_RSr4b<^=!_Y2>8v$DIy5aB)BIa4VZUj89 zGFeVbUK$BcjG3I4-17;W6}AuJb(Op{3hl17Jr#ZV#5Nk9*M(5xliri?ye{skxSiLH zfhYE)75DJEu_j8Er=kz9dm8O-Fgz8#dEGPcydi=*UV0XuHzZNVJ)eW;jVAW`yfn^6 zDdDNOo0rC;T?b@#AcEt-Q`MSz*XzY#XmDLAy`_b-Yvt&s&42=N-*bmMi4Y?P9oiXvWm z2kp87-#0w#CGhMDd|&g@Qh0U)zOQ-K%i-A#_{w={g~&mnK2%bHG?^a&=*hC5VZV8a*I<)JVWHmnIQP#urPTZUO9xr_g&pQ*W#wv?EKZ9ql zAnJH&gN;&*H}LFju^J!o(pH-l_AyxQyB4+Ej&^+_ zEO#j{?SN;WB=GUlPI%s9vfOgs&W7hb36?8V*=@4IzQDJddwz>{eSvQS_uK=|d;Ki; zb6)x$p7%ysjW{p;0MC9Nmb;F(`_V=z%yK{BrJvBQAMm};J%5JheIb@BnD_;r_r+PR zVD~q8-XCDOE4b%A6D5n~iY@F%y9W%GyPDVi4$lW7tj2G=bO4?Y0N*}d`U9T*P4Hq7 z69;XS5-blNFa2$@!iPN2 zhp@x=kU6d;Q2_H z)%cmmJQ<#kfcc+zDG#2HVu>zhQxva_5|+6Z@^%K=Jr-cK7Vwe}o{w25aZjAp77jB! z_%TmI#_HJ4y;}7#Dr?fN$Wy1+iZ`~f=8c1NKu4}Q=5EotPO1mb039hio>j&49c+YGmo-1#qTRaktY4LY*1B9Z>L(XH)YN1fzJp1%JcN9V&>&G|Nc*Sg3taApAD+=Jb72&=secE zF8I7Z=)|mQ>nC+zGN(H{J#^5eJR4RO^Thj-i9@V;oiH7_2~Qj+T2=Ir6K-y|ekW^Q z+or=m71LMM)@#)@=K@jf5FJCRnBNAgh*@*c;`%qR=BLH!Kvcyns48ZS2Hq)tcn0Wb zR(bmDDq`kF0}lZEsTLg)E6;+eJdf|xx8d{fH0Zcmcw%`ZRz=L?x{Pb{5o>-*gbvPC z%(_*@%vn6E!(7(9AW28~%Clirh*;Z^cVToCm~@(;JR4Qz=`q*8Fq$>@CFop3dEyMf z!bwu;8MjeP@!yLuUB ztcC`wwU(C_Mrd`4)%w&%oiP|^VhxihQJv8ZXLF5AR%|(0-ie|>zde&M4zV(># zn30Cn=!*Fm6RpI$9LO8T6xQBhteW{1)_dY8MHSZjO-5^I_-R zma++~KLA(nuwye3#QP)K-V;|gfpu@38TX@>^as|WEOdQ&oi`7@^_ej|kdC#FpRZC2 ztVWNBC<$Hr$AsoW*MZQLG#9!)YyqoGS9KEa9AN0`c1%|h2Z-c3dj?sR565lY880Qz9xF0u9{Jm}E^>rJ*mC$Qe^ zK?yxtU@Z;+t4(QWx)Rm_rZ6h3gsZQEL0~0ZH`&UMhv)tJW-@V}1lC{RN2dl7Yqu

    PA^!QSQYsic-(R8f+pkxzU zVJ!llMo^ijRFv-*=s4CQBPhl)Pov0((iw3|L(`RX=;vt2r#n996iG)Jm~bJuXbhW4 zSTU}#31t&l_jwpLL^j@syJyjdpMCb5ZxF5#GyWG#!&;P|p!rl`#ql$rsRY(K5rIx% zt!s&yN?@&r(wV$_X;{Av0z*ROE3lGY4?0>4T?tp6i1HIyF<%wcwUkX@-H&+nxQ%1I zBMV&@O#bIeU~SBd=Mw2y>jt#(T4Vq@jb4HEyd*UDNaBkM4Z(`QdOk{L%G8`bjPY7j zR}!H5FxdILXpiNe|@q+@Lx*0HvW@#`qaP1BWd1uT`X(DirVsuxf;7i*i4V>1zi_N7H_ z!^$SG{(*SyVq_Cov*^Q<%%?gdToYzYFw(KM^$2u4v7$mCZ>r{|BCM}zy0$lTtXHGd z3`rucdn`e?+LDdWr2^~02=ua)&BYo_IyMvj9BX?+*#y=<5$|el<5+uUfwgVU_a7nL z8O(SkkdE~#plhbaYf-x(zj`J6@QopU^-4@0MIFNY>Xq2%6x|e~t5+g5rw<>34p&(! zUxD>-5ZVNlO<+9&{5OUin@L#zM%xZyWfNGBqU}vFvT>~4v*^Pm_6si{+?mXn97@O9 z0lK!tnB<8SwFmN+VbzCkP4a7O5^HCJUt^P4Z>LgRq~>7#2N*h#P1E&QoFS~Tajf~M zFS<49*i4k^5?)bfL)kdi{2a8so!dCpJG0QW(YP*8BV1EvObw@Fy$$Hx@p=<ZdP&(TZ zsik1;PBu+f!qwSQHi4CJ(UP_B6Z0_j>)r`v6IgTM*N59U*4wkdy7aS4a}l;VGfHCV zSbLlN3a{+LJ%GGNF0c+jsg)s8Q&{s!hu&}&7=*5bp$C~b zeu0(7<^!^^4DY4>-#?)I1lAg`4d6C`HH$v{KKyt>pc7b!CsDHHv47DB zlv*W4Y6`2D=FP!=m9Nm1>lIfvft7GQo^Wg?lH>E$a2Zf;B>x1&8^LWH>-Aam;mbZ6 zS&DFHG2<;G9qaIjK3<0axjQ#K72x+X$UZzKBv=u;jz#GlB#F4GbJOsMFe+VXZW`iO zHjb6guTKRWn~5Ntr!gUA6S|%lVMSxPjbrVag|1D56P`r4vzakJkd77W7~0%40?5yC z=B9B89qaQ+9V?E&3eOFS)Er$2*HgC2m+P8;QXJYul+DFDF5%crh4uNQvI(qth&P_w zIMyy%==#tZ+vXr#D`qSRrDJ_wqT`7bjREp=ow*4|9))Mc)!Z~Oq+^|gQft3RO=0D@ zo{y+}1y(P#8DlG(i}jU&V>1=ji6LbZSo6WtByQtayH%m9#;%3c{VkjK$$} ztgoc#Iv&WKbM>Nm7Qc&1_Tl+)ejkiHmWX-iJ{Xaj!b)opMX%T@Uol>HkTwxz6XSI& z@Xxaxn~CJ|eejzfS2lsQAjrhxp*(-B0_#3A6|3EG`$~j6ml;c==~(AOA9w#c(blmp z3F=svnmX2HD4iD;sik0@?`Y#9=dBuq?UqpNmAu2 zu+p)_+fii`SXakc(fgKTGYRWy@LLsEHi5NvkQJ>alhCzS6}tXxregi(uVb$u+iJCC9F#w{4UmyBcidSl4D(G zDVxBG#e$+wxQ%pWzgnJKuq@mMNhD4D(btrJ;IKeg?p0OyDoa20M_*OdPyNwb{qcbE zx!^+$hI^`QFWK2;S~mawu6RDV3As<09!;5?+N9#(%0 zQdJMDKL)9)!Rn9eRMjKOGSsoCKZdHRN7WxgRMlh7AF67Y`r}bmHB9|6L{$w}mf^}W zLjCc$sv4pGcwALIq5c@Ds-94Pj8s(-^~YdUHCkClITrQDC{^{O`Xi#Mo>CUWWHryB z{?ox^xfA_(3jwCHT8m(*^^*LfW?lH)NIv!O2Y;vc|4`MRe5NAKej9&G!ymuXA1js5 zJvOUZVB>M#$uM8t1|=M-q+Gt}_3Xgz9uEsJ<3qn3iqz#Xh#o>3CjP*VK>e79)q1%K z+ly7$o~gn%)~+0ncAe?l7+Xc#r>d}xslrBwBI*K=2S3W0c4O(=c)2P+vvS+#s_=V> z{L*-tP(|Ab)Hcm8T1DFztMaSDHm-`cFI3?-z6#q5RkR&Pe)3|O2S4I!d=-ArlP%5f zdAqVLTt(YwtFS#oZPR#px(dJlRpnQO?SECYja1?H0oiaM3#EWy=87Xb!yzQAOZI^Rfvy`@rxvhD~BY%|hGMl!W zYFko;jSfN5{TA9J^YslQqxVi8Pmgza$3r1s^1v4u4DrkGXOD*M$q;OBuCMK&zEpkZ2&n&;|iI{Hrymzn+TQZN4B9R+1fe!knLfcY?t}r!hd8N zWRvZ3hYIdzk}b%6=pWc>UTc%>s)RC<-$N$ZuC{dB0Gn*rhIL!SB-`~t-Sz~x-I$W! z6E^wXz6-mMYc?=fz>Ew0;!+vInjL~v>6)kUQXJ=JH7xn4X3<8QKWQPp<7oVC@H08_prUaU zr4xdb3-i>FZ-LAoVo^Y0WFjOzgjW=gN}Kzr@TbFme3d`Tfvw0&u^r3{4BJvcnxmFK zKZh-n4Qy2T%Bh;zQ7Ja=#Svp>HfCOfm> z<6qT4J|sF1x_uKNzl>}=Z)VBHr+q%_i0xc}tt8UeFpk;$PI-~K@i(|}`i75%G&X!W zVV#ZLasCV=^3&LO6qiAd*_3n&8we|HE*sZQd}{$`16xs*4jb5(v`IGJjTLWBHcpZ`J0s;W6Puu% zQ`so`#*j9bjmuwt5)Z~;E!%gzLN59s^$lNcR0R6LbiS5qWL$CM1mJH-wANzW{DtWMZr{jDXl(erNsW!-8d3f%GLqK% z29`b$Pyyk)DcYwXthBj(!)!kOJHbX?LRGr+hBv8#2sT!D7`8~ZjBMbPYU>wrCVJPHo-|!U}vVojM-;J>1{219XvVl|m?AZA5UHT$3Ys-8E(R4O^7JpJo zuu)vYud{Kgp|f#XKxd;a*vL>O{X{qizZt^+P%vr-yYm+M(TbGH2B{yz_(1SBEE^GE$1`1_?;Y zNEte~`DDRHeT7_OAVy05Xp0rMv&oi`4J=}1H&RZ!aPbL9<}&6xJ(V6omJU{3mTze6>x1GqUkgwteH)vtK)m1TSa4#zs0Djr{bs3&lpe6gK=(osA|j zosFBp;`IT_Ph(?Ig!vlzg;8gtodbBDO+;b+;-Vg7zY%Qsqq2e4H=4v$5W&V6P1;Gj=xlT$HZ00dV`GVj`I-cU zQD@`o%53bJ^=7GH<4lEIW20$81rcnFHCb^NGG%7tp`n+*gQe&g|-k8ot zKa_5Wh@72SbR{;?LK?Ncfw00+JKlJ4@*DYrjk6STmkn%7HjwkiGZ-oTxGf_a6SHOG z`P8&*~_2N5$(Va!lH8eJStphq60~7oSYb34pjrZaV0TmE; z4|}Hq=k^WXtZ^8Jbi8q{p{R0a(bfSKMD&ekF;WI5$d-|fSF)WqhShlSQe@qp`C7-) z*zlbj$8keYvC%K6vk?gBY!rrcHijkn6XwWIVzosEmbIvbZnbvB+i=nVrRXJ_8PA*1g?vZeKn zVG(I_+1MD~+(58#u|lq~aYB4>w=JsU4)J5mCVUNIGHT*rKu2GZGR7o_z~#l|>G?;DrJbT%$e=xn@B zY*->^hYc)W`q~8*5O<`ElaAUx<;czr9|<-tQ^++oE>EZ+f{g|SD}KFtHYR7=H=gW! zK_9SjJ@Z`=N@wG8lh!vC8?U6Wab-ehBbe0Lm>uA+O+wPzyzw^r#^t60;^P@U{VDUY%~n9;@JVRWgaQn_KgJvCHEog8<_8^a5@{o2(51_Hm0Yr z(LSlOaSeJyE$oYVe#NW({IyZYPh(>t`bIE9NvG~prd!hHvT^ddEAA0&v{%SAHm)&L z5Wxn{k+4OwWn|;kY}vT~>_%ZEcq8*&6HRC1YT(C;n4CpBM)i?$ouRXFJ$i%7#`++C zZ5Hy=*jOBAK5;=Xm5q*30s@=M#;2$5xj?XSokFg$q0WHRSzF@-D_$R@Aeq_7cBH)h z<{8f*nGVc%eJq`g>*BP&DcSIyZR>2@7|_@#-jvYU*o@KzCgrEGf#plzb#Y;oA?X|z zVWrJwW83-~KEcL~0afW7ePLTFi0B(lFmG(;wv24x@^p4*^vOX-jw0)un6E=3jg8`X zjMg_*-}nR=-DA;?A&m{+&0(F5?MeRHG$gIDLCcr%m;&O?8=oj}E*k^q4(cP==oqTR z2DYVw2sX~ZNZFnwTShjn%a)DR>#k~utUEH_&B-)2d~{}x^zLQ$QK z9}NE5IOM0Xf#pjCq+jYt*=$Oi%f_{l7S9VdZc)g!krIlkAcBoEF;ado$d-|f*Rq{A zuKoG-AxQ9M=DXEMXCvgN^-aab_K42LZBd<#&M}>h{lrF0GB}d9Wuu(I~r+&!XEy39k*Uo)K zNw9%l#PhQbqn$4*a#n2QzhE(67gHEj-cD6X^7J*oGNo){Z08~=cf z0!mMtH|P~;zM_aQ>TDc}OPkBaOQU5 zcPt#Z|IW$C`c`Zun$AWKi@&u^uwfm7{%+ssW$0{}7#j{7B{{@~P5HUAX#NC0^YyTV zQDXyPrOjpI>UimCqHpw4$Tc?1fC?hmSQlj2BH1#sF+JP9G0NX~9J0QR`OH{48@;_>y4bZiQT9 zqjyLJ5p1lFvyz%7*)pC;P zPD)|pfvC<#|CGMb9Hn|PXNQeR7%BJpDe07vQgTvdHtJk9OWf(?dq5%A*ytZtK?EC{ z&^MZMTShiYvYj`6?${lQu`bLvAdt>RfAo!;a z&Wa81#~$VzVksaF8we|HZr^CrsEfQO@KJ?aW8<-a3c}f-cgvQv3zIG5yit~I-?(>* zeGS+sX1>Q_>1;d-{HKKENbz;>>ufw8(AgLs(%HC@*oaVm?$MX`lL+%Y8W%=w4~wwU z=CZNwno&)~NO@c#*Vq^yQb7b8ui32R%Ieveku4j4)t-A9vhL1&!xQOj;Ndj-4uc#i z0gukc$dJy)6Tt7z8`lsUNs+VDH$Fq(c-&S%oW4=Q@urTH9)s_wA=ntHkZWu_!I5KV z$t#bq`&r2~+?KI#SXqyhg}pk1jULSRL^7R?Cx9RKut+v8N?~JESZ8B&RA=Kxun{uT z*!Vn-O^}U{i;(nXl9G#*&Fve1?!+1_zk)DIA=lU#9aTX@->^(pa%1&u%*wWJe0?~t z0TS%Vd`}wbY>f8vZ*536+NH4ZR8(hUOiX8^6S0vHIXiu$Jji^b{R)WNH`NW#iWAb-opBJgtzsY+zfmfgCAi7%81? zvSl18v$AEQ;o^%-}=+GErd z!G`-<3$bQS>l-f^Du`fXCPqq6n`{}`cq7}saYD`uk0a~5u$5>!8{;kdW{&C`-BQ?i z(a_nL5YXA6bKl#dl%K}Nwm9>Rw}eq=qg!P*zU~m7F4%ZcA=moGgn$Yn*qCLr5^-{z znT>4w#zXI0FCgo?nQuZYosAdc{Ou63Z}d!I1<2}{sMJy;QODYvoR&C zu~9NAqO&pDq;KYkoSnY07JUP2j`#t&=x%hpfw0o%va!0+*e3-WQxtNS4Qxv`ko%Og zF^i5i$(E6gH?!>wz>jeA9#cduejs7=`}tvSGz^HcApY8{>!#oAT2}3YISsP#CqoQ8FqiZEoLa zf7zf>f(=U{cl(B~B%y+ck#dgBO2(OF%gDxC+4haZuw%QC^}Wnj8cJuQ1gPrZDhZ$R zO2($JQI^ozn1MQX-gpu1E(wX8oxXwPOCQ!5@Jksf2rF$a8y9>z9ADs}S+qW%=cC-osBo+w7#iE$}1^s z%nRsj%n#{o;H(ngOr!j?c>~LrzBl8-sI&1(Wi}38^TArd#yo{wV`F|u1rdGYe2f%a zFu^Y)8*{T|k%gYwhZ!1ARJ z>T{#c#+1rz{BTY4!-9>NLawo~AgqE2HZCw(2~I@t%gDy;Y}vSX`y0KHb${ktkW6P| zfk!_UeLaPZMPZ$d#ZjG&c__7xikzL1LdT*D$d)#XzFwJ)dBe_HEZA72kZWu#mXXy+ z@p)LuJZ{U##(bBJe$_rXKEKhSYmwjp=6lDGY^d+!`WE}?86@g5gRf?mDIUeR)l7@AT#SoqRGGjHJ z`dU-;}y2RpN(n3c3&1M4YlQu&LN;3uP zkp8_}3as<|s?x=}JRxmz@AxKyEV0Oz5$oI8Vtu9coc2iOA?915Wh;XsKs~SkGa}fjwy7*

    oEbWz6bRPjt){KYL)@vLUl0|Hj@T!jB+^z?-)ceCO2MfmGTP&$1v{yL4n zxD6_v$9QqrMIT#FN5Wn)UKK>?^i?W@;*utuPILd$ilkXiUqB@8B;j=8TcAsta5~YR ziA$PrI?%iqT+&$hXm{rSEh4D=_qo8hkuy^o-c_q3l#okuB6PB zlzE_hO#)|tvX7Wme5n8>2TR1974&5-z8ptUP7GhZBnqsZ^BG#tc~vJ(@nyOEvP>lk z@#u!m7vjq_s=frZIEwb5OeM-|CJ&0Hk>q8P(jJs4#Iq7#?xVKepe9_Pydo(ta|(>$ zRjCL(tLY2F7h?*ChLW;GM-f+5QeLMoHNpIvq`XXD=#Kg*Y90Dy=j+CoyClWSDL5az z5Zd+Vguh1VuByxD5eXc+srfA{IObyQl1a$qALeSza@MF6c{p5rszduM*6w7;DutyX zi5G@{R?^wY|&XHRC#$b^ICQ5h?6MFz}l!h!ZJ5&#E5OC{CzqJJVxD?2ekhDJ)J+ZhtDmj!(2aR= zah-R47~#o{ott2J0sQqMcWoa2YLCO4FYv$I`0D~(na2i?y#4>V*0^+G3+AbhqIChr z6e-_TxjyXc*8Mu>X`r&a7~ZGwmDI{rIXSSf#r$7Tlw^5p!zj{Bfs+DFzu7y5c^XDo z-kN}`QnzY78rxX$G8~cbW_hb1P`7GL41BZeqAn=XSl$~kS7k-g6gVM}_xTOaGf$%c z%Ug-IOyjsJC&YfN9fI8&#aZ5R2s~u9H6rkiwqIwS#vzvXIs_iF+Il#^+#TnjNN0Jk zg&8Z*&9*j%@2T7HIp#Sh%<`7O8f|Pv$y3LkUBo<1TrBU^Bxy zW307R>+SH3lbXZ4=ek+mi)afySi16^@Sa0IzK9}?>_Y0oOC|*I~u1H8FN<=Gya_r)7}kEeNp8eo`RIyiUD+zqH^A9|MgFN%{g_*-zQ4xEi|Z*cG-a0UpGI>~H!rp4T?%zt5o93(lLI>~IXCBOd*%-=pnUN$+MWY%BN^|2G+ zgq6Z9ErWPV?gMgzf#u}5>jUh9^l7d#D4m4*~4v%XX7IW@n#u_5yp!k&#o zQs&{HgUsx@g?Ii9PS~?iT*_?VBs1&6*}FbtelP6VC?GlO>kcwAwXN@EGQUTsVODZB zaN?|a`nDGif-^*8wcvDB-W_w0S>wj|dRVCd_G}oDGMhNb%=l^C-~TXw8`!f!QgWW> zgot$=hDplb2KEGEe5e<f>uxlO-$YX-jL`{NE)Bq{k>hxlV{TS^zXkG@^VeuY)E1L zYjns9i@I3mU85V%Wmsl!RV)y#19`UR&@ati@dK8O-!sp^04*CK04vQsDnu^Ba~E1N zipPY@>S57^Rib!$u&k#_t3+_a^zzvYtuawa5RGcIxI|S++o1EW=KtWg^d|>sDT;=O znbyO!(3HOb+)HzveII%Lf>RFy%MZ+RbHu=chcAmDfO!Tb1eVo0{#w=y^Wa4><7ED_ zbMY4zvf_07GJlK~vh?A|M0Fs82tl-6H25U)++;F4NtA_e>(m|=$B=8#gk)MGLpsqA z>`ph9F}LaR8bxMrV_oljW4Z72BP)RQN9GxCL72&wtE3 zLq${=>CIiJ_M$r_y%{{9087lfApiMbN_w-n;@OSNGc3;XX}vXDGnPk;J*3^x`PXU8 z^KUq5F4eM%rf63loX`VBI?JDf0j)}UQ>XCo^~^Io%<>^W5!X`LiM^ z=}qq3*XN@s!SWx2!0A?75pCay)#otJ2$ki}fWTvlsiCg*pET?YijofL&9YgA|1i%z zh^dn?#=f@IQqGM34Y}F92(S}?{H0a&g;sa@$CMQnJ-rzTA!nsG(GKqfnCE^t^CL7}CB3;LcjvVzLah&xJbWdaru1e&%}qm@ zXB5QmMe=~@LoR$L1%9ab;UM!o06jjy>Q=XEJsJx&3%XGhWqEr7De29Zw>@=&dBO_I z+l{uWq&Hg!d^ZC{F_!lp1e(U7^k!^#c8GZ%46?jk5O~OHYeZng?x{$n9!#*j9S~S0 zy;%|NaxwFaR#{#d98o2`x$xK@=p&<(EUy&SXrr6BHYT<9A3wl6VwDl*< zGtR~GwxO-oR;{hCZogtlPHR@yiE|O zSOOmjT(EpVhG4l=SADn)Nc7=MmuAfVQfnH%EJx4?+=ey$yj?(wpCB51Pe1 zE^lLD6eML#PSsqnScy<$ea(wAn7?(H z5J^tw^ya{j6>XWnl}=`noQ-t{nfZI0-&X^iF#98Jlhdj7hF=wL(3xL}lY=B@Qzw}X z<{eDT0cU``Y;routnXU?(4WlTQl(IloX+V@{XrSuGJlH%#hc`8$EpP#S;{=msrA~g9=-o|aKfIWlY%o{dNZ%>6(gCynMOm3lv!VO@O#d~FJvJN zYv!hLNyRJo-$^EZV(9}G&F4V+|VE$wx~6y|RNdxm3@v%V9e%#5+4hk_IK z3@eh;Ilb9F{ph94e@>LfYQdQHH9sIcU8PH##F z?P$*YjbP9Fb;;Sn3A^h8z2UXsggx&MNzVQ%28i|SwXvrwjo2GrRvcf7+q&I6WRA`kbnlsZItT9nZ5M_FU#U-jr+6JAzSs&7W zk!t---#`d84gOmi!NAb-=ujH8Ld1Lb2q>;uvxbnz7`^5*gBohAHd+nBELL z^P3k~e`TI^iBzoX<6;Fbu+~f1vF66?So5OfQ=z4q-oWaf^>IP8VV$R+#?qUx)=S7j z3u~?+#YhqF2-hEQsHvnjyxr$COF1HU*id1YPT_^k$O(&*{ul>K5tE zK-JW+zq)Q}X$6Wj)&gDBczRP7u%|a=nmxVQ0U>9lH**fQC}f@;5tf$>W8teC^6BZ# zZkKBW^Xx>epOHL#rIcu{ujUt`peFK42(wo0(-=H$j?l8+c4uMtD zn;K^Z)L@?XT`ccdASJ!Ipma)I6h&FyQTV7zdNZPKu!MQ`C@k*?tWhPs+1z9glH@%x zmUlRilHR<(!@GrfJ_xcr9RjPQH#45N_BRwISl*Yhl=SBOZk-x1&t8?~9YR}G(wp2} zYnw68hXI!NIRv&=P0PO>zNzzp_fQmPd7nXGmGoxq)Y^TRClO+K2O+SLtyc2Hz)w4) zNN0JU2H<6@=#jwWt_5Yx^HG@PeS)@H=w@4!W5240u?e&fxb{O}mGmYu%;iQAaD5Dc zRnnV{<0c{xEC;S~xDv|%nfgwQ-4Nb77DY*xw-1{pSIf32hxu^ylz%Z#MTF%=!z^=v z?s75D$03&coiSpX4{R=p5t|DimNt92JaQ>k#`zIyi#RcmvU5~(hslX1r<2V3zpOgv4d!?26bX{kIeU4x=PMV2(@o(dIU6}4%4=2m)*|N5 zgFQbCNKWVMW&DU&E@A#$*mJKcIi0hYPlt?r51cCX4$0Zvsr9>Ur*ro5Ng$5=p)TyXM-iOqvX|3!Ut7xjbzsl;qf%ylC(GwtIjJMo zwsk@@>`0l1gANgreW-N}JQA!Or?E@Qbk1JdxA`i`{Iy`u_jJkWoV`5Nu`eEW)q*|W z3rSAr?B%|GBfew)9N2SLTyUn#UZS=A+rb&6@m$Ju&R(t`Hf1C8XUAw#ketrhOV1Ix zE0{kE_T1@~oX*)x>tn-Ja4O8RBO*EbtLXRbYeZ^oX*+H$)V#;i0q|Uk(>=x=u6oP z7Dxt740Qel0UGRxhLOsa(d=*=e720HOp~;iRLJ8QO<6$FX6rTB-ey6TKMFS!`|`iA)s{aJLas99XLi>shAqEWuVHib8FMg?l!ixb-6099)hVfiECRi2sX+EtS#u4mrX2!`JR zETf+a#-^WZEdOpigPn}};`m?I_3FjFu7`OFV1wbw{85gDh*TRn%F1y6)W%F>hNG-HEndvx;VD z<7UrJGH*KwyaNLNV-t7IfV-RgArt%l-ulHH}C-Zhh z(Lid;D!Nd;W$C92n70!I4uHVXR#8CzZoyr3nfEdj^$)TPzb*x4T%faVZ?CSczk;A+imYl`+&^V>1o_JzQ%5IE7Q)m49dbED6h zw;zhS1ksjNYqoO3=uRt`_j(BIOl?_3UDYp^$6&({iaJ5yYD?fOZAk0DFy8hQRTbz|Q)rS(mEJI|xMq2wZ6u%~HP6S2kkaTObfUGwTscU?+9* z=cNdn!6<4UWLYb$T90XeHD7uS^WFx57oe?&t)k2HtM`8of8CCvb`ZG25;#+7J!mOL z_aRZ1-xdNNv1)bFOE%XS%e;4>$OnPTt)j=2jH!K5bSDIQ<7mqgc$wNXbR%3j6h$7i zwcIM2sm*L&d5U@Og1`a@9A_1EP_u>{4KnXA6rB%&uUJJ>74L0(o?zbL5ZD?5AF_%r z)d#%+`@H;P&XS=Q@T(F|q5(rO`E^_=yE{z}-G^~*Qiz|;%?eqyx~Z!>7j|df$*5He8Y-5Cj|A$J-U*ab zP-_u1yuqr~UA?3@w1j!5qE-$xtgTJ3f3?96&oJ*S)XD;`mQoE@<)qkakry!P&ql3h!YsQd zEmOR6T`a$5BxPS|{Pb4;VcvN`aVmI#PK-~4Y4fPcL-fAt3)6qVxb&o(KSXD3Og(Ut zr)0+nOt?|VNT%*3ZkmL>Uhh*eIw}DpN)>TWLEqi@fz`}AUl)6%hcq(+9u7RzB7Y9^ zERymDLbp1y3Lu$yw9PnA7Uw+ zlU?(FtiimC&{i?_+;qiM(e@E7cUZA^Fav%NsE7OK2+&4XbR`ep7tgKg|0w+WH0>o^RE9C;91`yLvIN zhPK`fxGLjGQ{d+Cq_N{VFz+j9>llhYvy^`;dHt#GnB12n=rD(?vMg-XN`4urg)wj` z+B%waReo$0#ltoBthkzam!YjK5cq{9uq6CQoAEy|?`vr52m~Im)Oa_!ZQpC>Fz@SV zYZC;1Y6&b!*7@f0xy-x5MSH)l%1^AKZOKUYG9UAql)zA$ zX^o;}S@F-WFmDWP9fH99R;^9p3%*-}@%Bx$wH{8Xvd`Q{%U;a9Z=tQvA#j&fYg@Sf z?)Ne8uSZ*NLEu`eXl88U-aAW}_idH7pkZE1jnZ(v0Tcl5psjTQS7j`0YWP^}zRvZr z8sCVv4np7otEe=Y)$8b;%!{;|UlV!5YU{DU+}fp0n0GVU`V<0jzDaH-zZ;(Y@N*}a zcS}^aC%^8gS=~*_g%EL z9~$noYHdnBu>U-SO&o2lf4ol$HaBk^Ka7qc1@+?08DCdEaTb(X-{vG}@e%b52)w1r*f${Cix@v)Xo+F=shjkf5H%bKv+ z)||lJ;({T}`##$GFzKqCW7UcT+@ZmHnRgG`dJO{S2FzMB0^g2Xyo-7FD&pMRI!oZ= zv0sb7$F%n$+FBNHRX$-87+W^=`Y)L`fwn$?z%@xz;OxNLyGB08ydR;hSE0sStJc)m z9fbujZ#ml91A%zPENwV5FnemJEat5U(R~`U6)=mY1okdogyrJLXlpkFz8N-)9uMq) zjg}w#(bg*vIL}rq_VKCnKVaSiXbUk|xz?&RE6`_bvmVU*DcX7&0(V+PTar_^p4rK~ z2P5M6-9f9T6o)^*tw)%7KSNtD#n4vFRAXvj^Tk~ zwzlDsUmFX^oI zcR=9zW>NOv+VzK;S2FMM0Lv{&u$E3zM70!&E61fZx%bBpQ3PDu zqb#SDRm7C1CtTKzdA|j&t!@;V0<-^7?w|C~cofB0?j{IqZPjuqJ!U-yHNFe7T#TeS zwaudJf3$v`JE6mV4_xa}tA!=-Pvz?5*iTUeTyI8MPIIg1FYRcHvD29M2jE)kMlDO= zpV}YVdI&T>~l;CWWjUrM`$8}Db{A44p6MFK^Zz%$Cg!H+`2pMYywkmWS86={7A z5B?iPz@;Ujh9&U0wxmyH8|M8PxO$-0xmM91%9_T9kD(~Raxceb<++x?(@L=QUuY|- zvfRtC&)3wdbz1x9^X*SF?=Qf0iNbQ4S+!0nIo+FJ4e$$aU5K`tS+!0otA;+moq2x+ zE+2}rty;fp{bx4SQKYln)>!tuqPVb-{4LD#3Urp?QTbmwt9MO;W%lHMoq&)ZLoR%n zYc$KLtI4MZIgJ(he4%B-PS4~q|M3tBCRS{M=G1fIZ1KweJ4Z7=VjbE^&RoSo=6N6d z{q0WXKMa|_#3g4PCz;Ln_g;t7VqZe$F9FG!>%@8Pklu;!ng5F@8C!DZIkn#G?%IzZ zVg7@V`Ex>Y)^Xx&`uLzN!%>OoI9@8Xe6DOIq^V`%} z$^36Y<}uTr*-o6b`~#Z)#r!eI{5m3K<~X&U^VQMru>2axM81I!_2L{Snc2l{kg5Au zxoJX^oVA=dv$8MldlB=mfXpM(p4p3ahyI>!3FNVx74Ng}jmU!Z+tE)1KT*bI*d+z7gKfzCPVC73P86Ivdb>eK? zf9}=g{4@tv){^tpu!GD-t`oQ3&rfq;f^XF1HBMLeiA!#F?8nJL@Zc)fUTJ$+^slvtHfK$8i<1okq)N$%*vkY;V@x zv|XFeui9dHE;&~?$*eOp`CC4}YK!H+oKFTETCcUIIPXJ# z)fVZC&`AEz`X7(MowYY|#=D?a=a?W>>nH3nV4&Z0ekx7`G zPBJqeS)cJ3KZ}k`MRGpn#98ym!d|)jEIKkF$+%`f($>3c-^1CP4-jJNgAZ659G8-+4>}$&Jo?!b#a(?Kx5`0QgUL4;B3ohe|_(zF@E<1 znZ3#BBr~gM>0?;2c%f%mRC2!W#F<%ZSGxj!wI16=lJhMm&YJUX+xt7eT9550$+_2w zvqr%6Z=9Peh|qSI~Gpid>6W!lOw%G?AQ5on$tcc-!0={8buw zC}VOu$*ezCc>y^>dxakQNX}+XobDN2Z^7xp3!?N;Npd!FYCW%FXs^Tkv?g|TC1-Od znYmv*e8|u5nqgyJa-QoXv)<^eQTzE_Gi>}z&gM>>byv4pf^n%i`qA^2OsCfCR4mM` z%kP@u!G)B0o|DYl$JT#2f!{U5gAu`*?zHB&(_bFJ@0#JkioMdJ#t@$AG&00x%1|m7@J0Z%vdhe)#{In*X zu}IDaPMkIMGYhZhr#0~mM{uS)t-0ao5Uc=mg7l0?%535!Gowv~KZ~E%#4{+#d7cv@ z_GjId4fttIJmZp_Eu1)AGv}R%~dA%y<_l)F;yX)|m?BHOOKzq#{maY?-~BI9X=K zN~}#fpl7#8NY0*?MwU$1h&|t9mbfHFXU0rUl{A_U+KCX+7!G&w%_9Fv(0FkMH zfdKhN@S+hhMkndT!ONn1@Nj%g)cDznqI>Zy8wc0KRk5NkG&;B@8keUx=|mhv2%;f` zj>18Zq;1fFfX=`{oTM#M>6`TdLeU7FjzdFKl7VU&eblpmV4%5T0-Mv~((S9hS1KS*sGy$wxkQEJg zOImth=f+vlM_e8UcC~7{?rJ^7b@t!rDDJo6IUqd43a3X5ggD5^RV=EA2uxdaC|tC~ z%})Uum=>#a3Q(wJI*S}r5fMa*35N$!RniEP{R79OKWa-y4T~15#LqGH(oIa)q=us% zQ}Wm01A*x;R`^)rEKErra)#IFAz2(U#Xgoz+Ou!!btexkstNRkeuD>nt5b1aex zo`_{Cm!Ik}DZC-#<(S&@8+2K}YB(ilU~>K`ZC`^<#Q^m;E1aWPpeP<#QE8l?trTZ# zi+13F&2ItY7GKd$fC@*bJw~09SD?d~s3eHC)3g=KYv=Lfn2=!%9&d0GmR!Y8A`J*#!XwMVxjnG7UjqNIZj3EYE9f@niB zV#G;oEn#wmypL>sP`Pj&MMTr+i9_%^=rW3!NJ z&*SVTUQ3nN1&9T6^?FP&~+r9SyIw_;kX*I8Jv zsTS*R#~y6}tQoBEnRqJJ=VJW$v(eXHjM%Zhq}s8*9JF5ZXJW;WR`^`(EUaC+pZZQ< zeK8^nEx*2`8Z-kdjj3W`mkui(kv4i`7QIE4rtX}3Vc9E>Yj~IZO)+zdE11314Xia- z;lgMt*2NKi-a5Mx+Gj#IQElxMfq%JX6dG7PIxAWcAzE6j3oNX&tHoNWK2QX#HCf^FYAV(jL;RGufpr~v zuZ4A8(vJ151RWYDjrcSnMpUoP3SSHfq8;lx7?&7refW5{jWK~0rz1q6fz=mbMQa0#$xvci`FsaQ3IpKUj=9@gzxkHqa*k7{((oiwsxZ5v^Qnj(mH ztcP`jX8E;c&Cq=U>yfyu-~k&yL|=4NBU)OlPibZhPgAOkVfTsORsm}kD|`i#<@%F5 zrf^A;pU5|`{;1lq{)8TikxE#<=x12vc2dZW)epZeG2LXv@Q*pjm$X?~qW}#fm#(-DHkb#g~TYh79S)Tv>8We;K^|rYeYbDZkheaxOha#k{}u|C2t_ZZf= zGHAC(cg1dv9xl5zdgyfXN9b%?<8n7ETptlcyEU#18Z^rqy9yt?Ls+8+mGL04tkGRD zXhv*w3$x-LI?>WvV~u5vd5SThzB(zsK0!B{NIzR_ToGo48#F<*TcdBlpjp-^+T9h`=`gYv_e;t`%NqUMQizC+ zD-j#lCy18T8f!IkRG3?>H4YwVPCX@;71ALLJ_4Gtu{q8!V;R=C1%FxA7z|5UJ>}Mj zJvMGr>86&@*^G_uh>gv0L9|=r7D=dN!Alj|*@0dZetnsv-iQ5wt8+V6gp%oj$qf&^7jjIx@ctnV3X|1tVF=Jy+wXrd3 zYV8VG1CHAsOSMLki(j5ItTEbcx5ntC-5O&O_ShI3qnmX?XEQc>C0Jn*(P$VDA}MDn z9_==0mNka#c<4r9jWG#XXjx-)QVJ2)xCXH?Hb%6x)_B8ajcQ}Vb86unSff5vO{7|* zRNUxy%8Hzf<#Mejn$eN8&j&aM!os>;Q3N!1E`uzwZ=}Mx;$>EUOYQ$x5k{X z-5PU4c5BQF&`n6v&(>3}Lu~8}3ZmT_<}*Oc8sn3mH-t6jhKvffabr$c3K6l<7qKxf zK(w^hc*C;B>}q>Tk5k7xz#0u%;VyToHFm4~5~mRx&nb3mEOgnev9QWYYf+qTcnY1( z*yxAY*sThp-5Sp+2Fy5Wu`#RK z*y#Mu-&h)C=Ci{01F6>dAi^)F8rFE#ZMVj&NxL1T_L5Mtwlh#=an z@v7UPS=RVx$Z(u7Cu=NC$U@5+uO_7sVT}O+R=g}mw6xY(Wm)6#YGdQ;hl>hfjYh0+ zZz$Co35{R6HLS5VY_~=%WVgnf0eeqb=cXIELT58JZV0f#geHh~Ype|$G|L*VHjd-! zB3a|jfGo7E5erEn!Wsh+8)8c(y)`s5HXg4wHoh2Dv=i27%nB=Hc4@9R_9yveV#69+ z(KoF1##Y^KjcsweHMYZw7n92N*tij~u|Fw+n0pAtTMb5APIB(BtqX-Uw#AJKwsB*t zZqSTT^k&4yc8zFht+CRIjak*k#>Qc5Y4vpuEBqv$8XE`U3>?AG{LwOeC<&~A-S6uKEMbT)g+V8q53 z0YS7|qatF^ENi^f?W_928vBE?(CR54s|L-8joT0#pD092Zw<}tDKo2$jZLE(^o2E= zvcf~IRBPxVeyQECh90(C<13U|>y5)z#*HIxy75l>*<#~%#D*RcM7uTgutBq|@p5n{ z6V^B^&1Z{^uS_8#Hikr5@ewx(No$Sew%DlF8WUX2E`l|hvBIyERBIdoexF=87XOg2 zTjR%=-5Nhd?XmGQ>UrY=q!}A`L|NexiCh?%uSI`I2u9nu@#Cs@af6md(VwES(29*8 zV+PHLjXMz=KXbw9tznCeYI_PBc0Sa}JeL(74W?S-Sd_nnz=)00=o{9!@kh{ZjXxE; zHO{!`4Fy7H(;7n&8^9|W1~@A=`kw0ATv+2zMHX7t_#L^^s(`Z zWsRxT#zyPreQ$y_nzO>=YN|E9h5yf&qi9KH$Yza_tbolLCE0G9HA=FR^yUT9&(>3h zAvV4>-D=J$5GxpMv9V-UHeO4B*nnJFXj%g;8#Kcj!vo+;5-n|Pylz=zMzz++opcrD zu;;PD?;@$zpuW*6Xms+D`nug34dQldG}P?Y$dAw)CFohQo@$NX-25dU!jUCy19oe) zLzy|Jlys?Ljjpgpv$)XN95?Puvcliof@qslAl9H+>Ix5mJj-5NJW>5VORDu~FwlL-7=-WME7dTGqHBA%%$87>(GtF-o+w)>vj)BOYdwVGZ--#Thq0FJo9^NJv;?wGNaecLePCRdCjikVdwrC5>II@Qhm!?f8d;44Q?% zyz@6tiD<5lm&kMJ@7+BATT5>PP#QL|+kE0n_M+EFx z?{V9)-jk#^<_IliN=K))o>eh@oLc+1Iwpn$>Jc0Edj*Es-1FOzT?n#o6v{*|N zI;F-BT->8NxO3F3o&N&FHmvX;Iq>1c-69o^@iBB~8u*0+MD8wKlHI3f5O%z zDhZ;k>t5Y@qIeWtGCE-t8UV(HS;?3f(b56P=%b%~CbETf*t2d$UJmpxV7?5w!2}oW zQK47KgfKt%D2~bbnA>(HvSc&{CmanDXYERUQR%1*>A}O1SEn};LWCg7vvzPB1WDQk z9Tn*8B*aM?na=)!w?rd!P6!QASq7@n8wKGRI%|hF3JMol$60L%NBl~=U6~%{qtm_o zL4=8Lo5tU<@8iVB5stMGcCHR#Ma}7lfv}MI z>LgMT?$G(Ws|rwZLgM9B!iVp`7I#wHc7zimtYn8Sh<1c{}*OO z+A?2*aHp zJ|bRVCJ-Ko(oq6T!Urvc7gvX{ zPjvr}K2x5>lEYxhv?>TI;{0W6VjwT=7^DL*LP-|+8r^S*PD=uzq}lxl zVSBeAN`&*FWzVprZO~y7dhsB{Nm_b@SU8jpK@9`pjTXY5)%ozy;`mA+yomXHsgp!$ z%PKx>0k8d-ls;^)^Pi415Z(@3)SDw9zFJ?Y}Jk^HNI2AD-|R@&M`ogN_;4y9u(gg00SyH|(su|t*D0^udhN7rAgEVxViCF}_M zsr>bk212ik-WVx|&@gO~6LCP;FCmB$;bQo(pDJk^bc)jF;X^Nx5CGL(Ny5URG#n>B z?!y~YvmbV^t{?6$TtH_OIxycQYAV7TH9NwV=!f5$Q92;Re~;9N(wRCf38?Xuk>*BC z5GBGFG*;R&ENKGaOYk9G)BFD+#KNI;rcQhuVSfu@x9SjPhAwFig#Ti`j%UplL!)+t zLlyp7PQ!;c0q?s3>BAW=S`yGF1>w-BAWDQU!-qo^NfQV)`0%E%q@|BiEF4N_5SxL} ziqc?p2$%ox`>R0Mk@-3!V5&yxJs~^7>x1+PQP~fN1Mk+bM7S97+&@T-ry#t?^o>}o zy#gOzZ!pS{W=VpT4p&6w>Z0^ASZ8s9__z-TSU$Y6x_;Pm{)FFv@KWZxJd}!X9D0{E zrBJmJjYK^Wz5$jnTqf( zc*gSKlor8r3t^w?e7LLkLxX{^GxJ>?OhH((Hf%#!vKI4$E~B*Mb>Q6~`(erQ zD4n4cO4<=Zgdj?UZ)gmHBuyY(m0%DjY3UJSQH6$xPxw%`qO>|6_8pl2IS_VXzTVMP zgwG)MEFUfbrY~c1q?v@j-cA}LP00!%>_Kg(L}|%0rsiU#Spy#~F=-og^5NP5E1hK0 z(j)8zORR`eBOKwa7D9QQ(Ar|NtxNm$YWg$~c4fZ4dMd(aBQ}I3^Ar4c>5M2{9O7>e zHu_;cID-*tylOuzdDb9GAI9Lr`3b=&qx4N^zBnXl=@DLwewfeYafG*72>Vp$!~2JJ z8V7`zGhhEe3c}LH0UN^7Mk@b#JpW96nL%8SfcV`1(H|84{NkLdr>9!#(IjQkq2^0uR z&q1$TXU-NsBTBm%O4<=Zgw$Lhd|PD@BxxITiqdzW`8h=5sM90t2Os_%B|eVuddr8` zRX5U{JT&4@AiRS4Zcd~kJQKGgToT|vc4+wUbd=s8Eoc1iV2e%>YCI)M&%^~$M(IWu zD_IhdG=Xpve0Z8`PJT^~Fa%3{=cc+G;b044@9Gd<*rwtUAPh3!tx5{Q(jTiJ{436X zv(Z3U8KJjbON0#+Iy)#7xBCzx1W_W~3?Kew(geaSQC3nJk$mY9;!I&_1BLiF!dtB< zm6x;~M;hPKL)QV}mCQFJoQkkk(B{L^4EXR9Ia`!6_z-uIjFILzI4_A%<5hiFS}Q1s z65%%V!;FBW3546BIg3hKdW1K^hsU`*;X@1Iwbk{*R*T=94usvA@6LEC!ey!*VQn}6 z1x=$LW+vz@;s(O9^MNoB7fM#~;WAYaCBk=AR$ALFX#!z9%1Sd6l9nDJ&i_oYDCgZcjLPDOaqWk+}dUi&y8=fl^4_l=lDc!5Ia_Neg`AD$!{ zA3?-OQxs>VCrp0{geCCdYi`Mx9^v2wE4x4;K7r8chw{p~W0dyl^y$|?*pvB2s3{1` zJV_hEG7oxQxf!J=!}NA`iSSY&Y!{)%t0II5L6kl$RT%_Hnm||vAD#?LT6%=H!-tnD z#K#fdWFfq|x+ra-|6BlsS25pxu~dW?*?m|RfDiY{HBFgUr8mh-gjWKgkJ?T}c#%Pr z2zSI81PMktAMQ*th?BJR2=9opvMUwh;|K>?QF_*^RP0gu(X6}10%0%adjL~YmHe=* zOBIB)fA~?@P^;`B_z-JTG18P>r_z}@YCOe`RH(LmMRySLWY|<|m2(Mg+6 zhcC4F;XWX|miZn|rXswh3c^7^_<lYHs>;XSa#Ju2~Wgg4m`R_DWWTYNhj2zxW%gkUPdyQ&}@3WR$CvLD_8giFjQ z9Rq~TsqIvRcLfDeA}ogwho&H`2(hwT{tJZn!4hLslE)Dav=H{H&WEhmJ$D1)b<8(8 znu_rLDhNjc;cl}Z-UWoOm{B@WqjP1{c#0424+^40_%VDqG6ms&Xnxm!fp8RjI8h^c z0-@CpdsK(8M%JhmK-h=*rs}B(AF6_I91y-|M(O=P__7(Lj{#xhI5nPv@S&g}N`wdC z!*MAHKZOtP|1S`RVTs2ylE)EZ(2<8sdQ=ysuY8`U350!_Z)PAB;gpDdq?zKTpY4!Q z`VbJl6qEh%DIm-bQsXHIr$hu%B0LyjWmDXewn0Y)`q7WFhyDwMW8lN5G^)!H4zPT9 zWpxPKcX)0K5cXrf$0Ml-=Tt#B2MCXwKAe)|zbazPhtC6H%?LG~f^d#OlnB3o59g#H zJOm$3Ns7wVWlwm}TK2p~d_c&5vGlA5qpht6qn-Y~eGq_M&wO(e1~B=~w6bUHiEr5) zEZtx|BZ*jzzedEVl@ut?m}-k@AwK{prrH~Hs$zYrPXt>C*`zYVxsGRKq1arls$t5=u>6@DnUAONgo>~(qG)*BV7e1JpM;j z!6;&xzROSbm^$mMObHS%VPX#|^mfdQ#(2ZxXiZ?kmo7`@C4gW6^DRgkKeC(0GOtuo zqt;(hR^g#IoM! zWiLcn!@rX(8`}rs7k*fFUp2qbjs5bMTr6)6-XwF4Y8B~^EEs$z^SvBn4gU(WY&>z2 zwR-E{HDCB2=6eMK|4>=>0IR5D z-JUew?dW@5{18Yst>>6;d4$zd@e1pgxyCEvtlpK}J#h?iT z)5|JhWP`?DQAn3Q&}CtqXpkoy=&wwY6NyF(gvrNtv0A_UO}r|#IX(>WYSl!b5WQ~{j;at)f0Og1UYAyQh1)Ss&L(UaZl z(e!X5^KFQv_{g^@$YB@|bI}(pAGxE{L+NArh;&3HL9~JT;=B1+=)y;3xgn#_@DciX znLA3fbUw;@Ppcllgkh6+0l-aYIgttgn_4tf7yz2a>;RfY37k;JbSlOc-xjV9f}X13 zAG`x^XrGmf1c0WossP9<&8h`JgOTwLxNP}Q%=z7t=S+RRFOb~Kd|Q=NB-`D5WD`hA zi|pN{v^YUSTM7~kg}&`>Ls<(+c5>QA(Ors?RgqwTge0P+a|Ml^5{cZ-bVl-5vd01- z83YxyR3vfu1Ou^wWOvx+lhXG?G!hHFOrJn8Upy*^HlNg=)u5R`vO8=P8bO8e9FmBZ z76}$l5=qFIkDZa+uzOB(Ai0J4iq7&$34DUd!9Y^3+L2TQX{r!|AfKOmK zd}ZJ()!D2WA%5+P5p@Uu$C7z|3QQx8p{hl02FJI#zoQ02yv2@HqZ2- z@0Fc$6CX`3*?rWrf!S6{r)Reu4`8=4-;THyVjNi6OS%X#4y^Q0m{0Epln*qTnT0lT zgOwHss3eFI3PllqJQE)p3O4Xk`b&I>mL3YG|FRD>;v^_cJKIM&r&ROZkN0Ucx&g{< z%=ez23MBy_VaX(XRQ7U6ERwcBHY;1{ww4tV3ZD`Z0cx656t1P2@a2%C{cljPc0of_ zm!M?5=K$rTZbG?YdRZo*+|GO-xC|&V+{%_l`Rd7lvQ*(-5u4y;35|Qq@X-qR==P-0 zR|3PDg+YV_A%MY0WlI%FBVc@?2XT^?-bV=EvK5?eQe4Ds)!69e$?xR>ds3MY(1DIb)gcW7z1l!g989n4e(ayb2zES0&J&=q&I5arPZx zP89F|d6V2-xH~T4={l^djQ_otd4T<;d|ozdz5TxqZuL-p{@>v$H$1J8cxOZKg+gey}(9 z;t{pXi-5gV6q3&=#PYBgir!Me`j(+=Y4_*3rBS6osuTcg4^ehcWmZG?ImkZZh15!Z zj9Asf>LmrgUlBo71X8QUA?dOXm~>g)RcG?okbM-pb0rGqOS+f&lv-=#PJE@~81^V% zN&q!<6;xOE)NO$g{*K-1WE?yHA@Q={cO}m!nNby`ui{vXDO_buk@lBsu@SP5M+-JU^a(MHf zYG$>*n6{I6@@Jq|rtnHpx_zcVKw37Iby0Zzp}KlownFw96BM0}XS9g$vPoYo z=zR&Y&zc~uvJcFE%c3l~VdgEo(wxJxLNb;mah2tqJi1r%w~+l8mi3r|UZN~j-aEAD zSCD-H%bMl|t6h|pB-NhLp%P^Ojb)WbUKd4Ks=BSmKf59OB9=8d4%P~KSyqRVyYqSs zvM*s-WhAgzgx7g_YkdBF$c|%K6N6xVOn9X$Pvw4&%RjGRStWvCv8p_H^Eq|9Ddjq3 zUzMTgc=ReOyzJ8POVVGEeNBe6Oa)SWvI(6Ii%VfT}_F~rddSUMRD6<_*q4#>U}g!J-0NNJ{$!v4WZIx+&5 z7xcm`&6OU*UmXJ3_d<|f5^pD))2QxaRKw$7=_m}JRdS>E%0c#jShT~Bh{VtdVJM1E z=HUz75Q@st9+@Y>X^w;aN*q$^Q$uSIiaH!%9w~F4=8@{PVePkp(;A1O8Bs`iQYDB< zDrDXdK}ubElY^OQ#QlGd%#AR}`>JlX#4l2};S?sVX=#e2{erJB)v1u1dP8PLBEm;KXy7c{v1@ zknjpB3mxsE;LMaD>mY{lkx-47I`+8&3bTf*y_Iyf@%TX0rFUT1t*mhkE)*+TF93eGCXYij_#R1TPQ zRb4Xpxga>J$&h&p&*6ItS6PD6D|5G|fYa%Ptj$Pyi|%Dvt#+6Hehr*%%-8iOSR%6S zwMH&75{81aI`X=T!AFGG8uh7$1CD{Sh6-7i(QCc%`ayj!u;3;*Ylb1~q5~{=dD0%m zSXRp$Pn;|d&e}o9Iv)bdCgHV8o|;~66*!+jUS|<-lki%l1`jo>4bCTJ$U5yuK;gAQ zK5}o$eQ?%8UMJ8C#|FHtALIkhPi1g6FhQ2;0IO(yR#|#w;u}feY>1b;a#2+2URGIY z{?rt#*o{zCG7Q$?y2{){t{zx<2b_&fkeZ2JBXpIuo8lPrq#0EqNW~^$?WOQAtX-8F zJJw$WXA=ohZ9cHRMB84IFr-h7fOUdw!glGCApK(;3)iPDu_>nSgaS!NB%*7I*TRli zr()EvnF5(=6q53&uDJs;|G)<{*JNVZJP4V`uv2(~9mOH@D0Y)gRibNwcP+J0SBD<8 z#1ans!ThGm!!!?CsC*Z~$7q&W_N} zsWf`8A8UJ5VEQcZ2`nDZy9;*fR&y}Yun z@~BS?{$B{3y@Qa}8E>fkDpx@}`QV8@wZPfO0rvJm)6GF%6V{hL3fSx52zV+ziG5M$ z34`rRndtiB$*GRFR9`S%9PHiz*yhrselpmxd$MFv%YISFS`!CLGCk^#HETXrAExUc z2K&=!nWTqeJ|Pzw-K{S;2S{L_ggLt_^C->d)!WmjVTU;Yz21xCxKwzZlznYRVgnoK z1N#I7v+A?4#r8Wl*V& zGE+BzbFdfeZzCWW0Oi?L-gy>P5wMTKv+Ir%@ z6m|R=Mt8tuneZX^Qz}W93ICZ*fLS84dN>dn5azOzGLhBCdNa_+Wq+wuh81#PRF}y_ z)<7aD;j$Adm4!(zxa=Hi!QC)OlE7tWRU&KTAZMS;&d5}zkkhWqR3dBaCFh&V&dO94 zAt##4POC)L1mk<%&t-UGQHB>3=j-?v<9k}BGK?<};IdOx*3?H%rY6HSM(kSnNh>2V zz<$I%dde`y;z|%BLdLGRZ{#1DBa9Yvhth=}&?w6kACAXBs5*fjtQUXh} zd-^Yh!EMDjdl5rwc_NV|?5=a^9JnnZ(pz%N-HA#!Eq$@^caS|3F=bV=G?$fm>E`k( zkJCIht6OJqH^=PCequ>#X}Ls}aBSdaFIsv@=g%#Rs|heoeKUuB3~n4S;1xu(wDy#^ zrFDd!O#gmtEg#4U&Er5h|$MpbLr0zBJ-WTe9_@mkIHmc$W}j+xx3SlM~t zi6CZUVn`TShb6L18an*z@4&MOF&lZgX?@Gdfsj4Zw_n^o})f8O68X85?Q9a9$f7LPo7GKy4-TAUb+D@xl5hWx!}n~ zOfudwkuz`kF%f3cwIfG5g6B8Hd?LgxH>jME0n_?s^=K>b90-z;JGcBXk)>t!IAr75 zhnO|P+;T&r(#xwz$|M3^a|&y(=XUq{S} zac(&=5oYr4?zLVA&s9IUW#pEV5?LlysZzfxcrGJm*#Nhkn5cBC`sFJscrGGlNj=WV zi7+kd=fBPb&w0cws>eAw5vF;c+g}Dec;AZm<-GJMi7X+wt?J9*IUOhW{hFoumYU#v zng+y&eF2`6h?%NrmiXKRdtB$-D0y;1WaP@zQIyk3&zl8S{ZRotjiTgX46!7&`}stc z<`ySDe-bcY@sVg+!R9!B1^p2A;YB@)Sz5gpVbR zx4P9q9$FC@#%?XGds{2$v8T7$FeV6|H_`H%Oe{&CST2!eT59^^-M}*x%eg`fsbyJ( z$8Nw(g@)J5f+v8OmlSSUJ`rZ24{m=P1J7$=@|=)cmP>?byA$vHB6wa!%)bO?BFmH= zt)x=m!7(yE=hQGQXVnC8CQl!|;0$d9M^=1470&T^6nPcfAkM)c5JNgsTx9=kIU$YzdCrq*^lC( zFS}oGw?W^2vS!EbDBNuWc#je1vM*5!?x(R9_YHCxy(@7)jb-$8FqwAW;%eH6_O zZ(NCQYsB;O_}E>pr&<(cKFyBZTYG$7yrT|iGIo3KZiBupWKG5%9Jukp0X{s?Wb8qM z$Bn)|iOXJ6uw0J^eVg!d*`q~#qrgZJ4$bs(8HLAFL5k31Y?6yi#9%>0X2x=ozo+XolCLWGr;=}lnC-5Z zVS8($=W(Ri3!LYp`S~7Z6F6*!?GP3~=4>>+7y_B5VXIG^XYo;$3+IF=-<$#X99oI8 z@c79ivq6UrD@@4w9>JIo>)h6=7&w{#ImA*;ng!!~2%80K_$br(;$#pOMDPe-b0?M0 zz?)ydnKQZuXP|0&cnwaUV{bP=!mohy5>_gjU_PPlj63Ko68je2AvHuNj@W$sp+Cch z&$b;pL8pgE=`^J*%wrBf2qx6NyGLf95J;1WIr{WwOSjPZC&c9rRaC&}Vjc+4#Ru zja*kpja=7+$&?|9$dFf@VszdPGNF;{s<Qflk)lu%i@`~NTp*8e`709)# z;QGHua{bgdt{-yk2hKZkey(J$EhKZUn~~jQeDwCMN|+t+BrC&m>{lSUPGV|s2 zzC`C^wY=_9ja+|;7`g6N$n-3urE|T2dA%<&p)s$!R81zh-XC0L1mpTkggdaj{*C8# zw?bqEa_uJTb-42*^Ez$V;0wrg0671{UhjcA>@wkO<>WZe>%j-=@NW;);X_!5%Sa?5 zLmj@T075XKk*ioWgjEDHh%50%&V6To=ey7F@eMlB?{zS_!!h z1Q+m&EWhTsED<{Q&GMRK2^jL4WAz*Inv>)uQ{nlz#!Y|_4{=2xO(ya>de_cm$`x_B z1Iz0b6CgT~70gxD^VO2cVJwv$&h0Y5?O&UqVr6|Qtz{YbaU`eDMg7MBUGgJ0av*6kqfgIsYHMo#TG zkrm8UznR{AO|ZR{wt8{t0J$xAIbHtS|bM{*Vi#DH9yxP zQMyD$zuI<8`x&@disRxPU`&$VQLE)>$Zc4b#ojcd2Ck!$x5xshd2^1M2&L2#7}Frk6# zYbSPfXI#7Tq%%y)wOd$o(756aWKQ=Gkrm8UKDUsdG#2Dr*f`MH*N&~;rJ*CBBu*P&4(*EhoCaRrM~=bEH~ ztGq)Coq(`0(idg6_hnp%#JN&%9U9eSJgFzX zv?z71Daf^AnA6eoI_1bZY%Qb?PgJ;4aGey?WE$5Lscqx(Md4f*dW~EcVKdbqz2q#4lXaXV zBEw}hJpeAJCe%PE*M(kYXyE$w!PVCo*F_FZsa4$!A0RrB70gxDx!!*y*BM=ltVXVH zfy))m&(#y5%T2Yseus_rnm!B;hm2fT2FU7D7A4OsS*_~wM3~UX^}Dbp6Lok@ho<<+ z6;g-8A@0EPnkhlfN{U<%*QEapTpwA7@5$*ak?SaM)qIF+?Fe0quW?-;GIHGzFmnCT zPnOfNC^=WMl;2f5!b2Bzcs-{hxOV$6fG-met{W&XGHzyEi^d`6M?V26h-cT23H*=e_rb%yNeNChj%!PTzABcTz`s^MZk;}=Smh0yXtaY?1a%eyu+dK z7hG!x!}#Gf!gWVnQ)*mGh9KvsD3KM&6$ICRADP#=zUWEhIvQM02J&;QhZm3w{LxF! z-nfzLzNnGw{xDg(%%aq}md3uRp3H>CI=q+D5nM-Z zM7mnR)wJ)Aii~TXswuU+R&YSh;Rulx$kimc{`<%}Ji1fY0CF7zu11dhT$>=fbADcj zPXvuzPs&EFr|{al9naYV{jj8hs|k_OONeN%CxV(xaP4{|fbWQqI($;rlp5EHamYF4 zBeH_Is(N1UK9cK-^H*`Kp7bt;rRL|_G)h;qYkB<}YqaQxFZzsJFG*x^JBw1U!#c~9>urTB$!AgOT&v08YN0Tpk?T!WlL@ZhD>8n{n{d4q;SP+e z(+fGb6(TE;YlhA>Iq8vkUDm>T8M%%HSIc02uB`*~oh-&R*Ay{u&Bd8`(Oz@SLGq3P zi;{CCGi$EaTCxpX5r`QY+UvZL-z=nD5m!@cbr|1XKy)H2kZZci>u_?RM{;eX{F{PY z$APPjKR?%}ee~TijcY2_XuS^SriG1M(?jH?2^OW!^@I;xPy3kA$Td|vDF&`3H@AI@ zaZL+z2bS0B4#-Up5m|v;3yZwk9?A7axE=N%N#nuQPRh^q83%piP2*bJZ{%9SYvfwe zLEZvkQR-YzDd2j>!9&;krrhFwO(yE_oi!iF8P^hC?!dU#P$9P@1u2kgA(2On4I<<{9TugYSDaaMbqq71u@2WKq6e?9G4)a=<62+Ulv;bmH-K^*M2M_F zuBn1+$|Jcxv7*+G$aNyPo)6{c`T|Z^l;>l_+~&r9IJbqdAI@!w{qR{*Cy;{96=&95 zF9ey;$hEnu$wXdz)IIeXCaa2!;EVO?TqoU z|C2HxI&mnFYpQ|kBlCJO_{kaMIvHGDy!p9ylj!@W8rRMNBiAl|V;%15C9j4t3VL3z zU|zdPOlaiVIiSfzUY|>!{S)Kb#m^mBUh8=wx2u=P3go&$((}4f(v}XiQcMp&0^f1y z>U+p_3b?wP@^gJD&fW;eCqyR5?Zw!!M{2pRU_X2X?+a)|xxF1^y$_30=SrSSycB0b zLk@id&BGb5UYwVBER49C14AY+tRp&+70gx9xvqI6*UQs7XCv3C;OY_0&sE0J13s4^ zryscvVl7nT`kG?oIygvHIey#(&^tpt_b(+JN*J*KMUO$ME7f?w= zq93NuB?fqz(2&;>Eqbw~F1gbjTq*K8Ew0HJSMq9WF8M;+Be<@Y^!B>yk#%_6sbQm$ z>xbYP=*Z7?5RM-3xrD}bCT3F9;aReg>ueu+qn1U<^GaU9b`2u32gePqrL(74US|fm zQgEFmYch>%Bjh^UM`Q)&b*)iP&krm8U(ewJlBkSpGFwA0C<4aveUZfLuQY*U(^ouETKjaK^{$@ahMyuWKH- zzOKdVtIbCuGH|UF0oO3?1Q@uEpPhD;<#n~6c^LD$#;eJ+yf%>_cddiS3go(5OyeXR zLY!^0e+p8Z4z4%-`6-TY(D%)?bZ)^;NHo(()L3=5h5_G2XTj-Jw@DaWBWQFFbiY?h zOkK$+ZizDwBgIHmlW7!vNO5bJ$O@up?yK_8xte>Z?6N98;EoR{OgAp6_+O;Bw|{e_ z`UyrA*QjEwdt}T@?jDK0KF?N1yM`--jNCBC4=-U1dL{^M4Wzjz(%8ql?c+W1ZXt(%JeG% z8qH}cY1k|(4n{s{fPhTMX*Lc4!g3h}b~aN`rrR-^%^i@tSJv!UA>?Zpv1uxiQJO~+ z&@`-dUw_;@0cm~;t}$}HY{n|!71D+o`w`I~R>8-JF`8M}A0NYO4~-*M%5S7O+d6clGMQd0&f?(2@O2SD2rW1U;%pvAS&+*ZF0~f{ZT> zD>en|cnSt0;2NP;1jh=%kK`x`f&X&kyif+de z*-C-f$FgRp@r5v8K}1IR_L248w)aDPLDe%lW_GA2^8E~4@AL5=Pf4teO1}`IWwcGe z(A&n^nCN$vwD$QaR@_?-&e!fI%k@}z9L(7U<7=ZbA+NaD+s4`ixQy~8A8bN!E@OOC zA`tsj(PWG-`Q}s1?k6(FSLFAVhpsLLzKw>rCeMFA2iJ!W^+!bl^cyG|Ux#eu+tyD% z52baxTYW~p4OFsZkA9x1Y#w--q&xj}Q4}X5G#bb&&5IaDB|jfjq>RGic0jHXR)Bj;WeTzr>~G zw>{Qwk>7egvdor*BI+~EuQSMm#{6c7xs36>iF~W6T&DAlwRdPTjV~_7jn(rJ8Od+b z#fLj48_wWxn)hzLSrlo`1=pu|P7g%UO{ZBqOl~@P$5ac4wB_{vw-yfiN``r}t%4^c z8sgRXtcl$IkO%}#@=8^#c9;n{O}rnA)l#`^E&fHnF%+xi;4((@X{1yosL8Zui#JKJ zvqZ#b9+e*Ie~p8NCimMdLuOxqYqpf1=0e#>a{&$-GIg2@kQlk>&^Tgs!bX~3M9G~G zi69@%g)$Rznq(lcKsz7&YT69LUl8PWf@U3liZq%yFpGT=C3dv64il|)#6z{Wr09)r z*6scb^8FHAbA0*vp7I;7H*+HN8%5gnW+8GqDsjFwux6+73qvd%B#RSS$h?lwp7)fW z^PnBP^XVwW=0vz`txD2Lu1E_tXWm-d1t3-IQ?0#!M z()^ z@o_tnNaH{3nlxg?BUoQ4SxW56!^CViMYHT*Z5wHp3b^L+-iH&50X9U@EFoYZmU~Y& z5-Wtc-AluHkQhP`Dd{&^#t1P8aG6dF;kc||V(nCj6^al$T0?s#Aoh=}_cv`jcOg@2 z^T4$rny+H!-cSt{Gxvs{eiDmS%-rj$ahPDni%KPl_cwpYnX!H-=$t`yD+dBhC5X`X-)_X6#SQ z7_P_Cu9hkuRgG)iLhj8ldvBG-5nCFknPw5h0(c7kAORSw=^;G(e`?${Nb*){Ox0zS zX7&*;AUJc@+8^zbm&P@jMzgsCuplC%*?c(x&Fi9?ZXGxCKcx9JxRyEc)0DBBX{FQb zspXbN6YCi;ynq}#5vCtFV-e(Dh?2assPt^+Atl+*gq&t905KeP<3Cc7DKL2f8Ns=X zo<;KgG%P}s@oZvExDX{Wn$5$?L)k1;M$#*-v-;aI(p&(p72f>a%q5&PS|8S8%Dv=c z_tG?)*vk_AR-2Z;n2D?!C1r}%NS1NtUgE*ADnag>5r`S`>&3HPKsYWdxHa1F1jL9L zBX&uCm{?gs?6V13$w+J=xK{e}5sMvm7^`U>-iwK9dRd~?R3kRXOCH&?*z}B%ih0<< zggj%UV&?g{jGiM}F)vG8RxmLK5*y?tb~IyG5>!k>|JkdAyA~2#1g=$q{KSqJiRIpj z8i>W>cvQ*HJC-Xx(wnl_9w2t)VPXixNvu^d#e^8baaqB{$OYtzkJzymmmp*1MaHUC zT=pUo`vzQVL-~na!Zy}M(N1>kQov9Za}VNCNv}pM7a#079B~$#PK?}G;gcl%r(YOI zRYV{zW5n=A1L3%=U}D(rupnZ`+L-iERkYm_UCG!Ti#8&$#o*cy)`;OZrT54fP42n4 zp^e2Z2Mnz$_c(SX9sQ(~e68wSoC&q_;Uq2SvL5zYm1xC3Lb+fnPx637k;?% z6?#nMsKKf&4UozbaBYg_r=mt!R(@0ov6E5b?frfnhg{Pl)U!f512sYd)w4og+dx+? z`@d1a@my?wnE2A_)=La1U&%k9wB3;PF7V>E>!Xp=QgB7$`8dUXQ0Ye~S?`tmC-w$+ zcm7^C{JXxA-txEsY|MzGrIK+zm6eh-mN)q-l5AE9Un4;ITx_x{8gjBu-*Y5ls zK^{bm*Q6~W+I2H3c^#3;6@`={Y8siLM<*sUUWK-Vxa|K%B|QLG5b>q0=S|UihUafR z#`Fx?Sj3B*R)A}7{vIJOMWQ!Zto7uXz3daNKPt#0uP$A^a2*NeC)Pe} z=%e%6``A4NBUVc>^w@bV@z&|6#A4%>FB^O8y!K%x=lOenJ#XFEOG+q;7sLB;Xk8{qj*8*!T467wl%SR+O!Rxv zDaGkg$q@NovDOl3onRM8Ok{X!;XJSP#NL}tci29&C^ zV-)gA5D}G8!p=^9$SX;GY0?KINcy?_NoUzll=MKd|9wpQDsY|TwVj{Eydt>l6i0|! z(mP@DE;_)*lKz5&ZV+H&Nq-?uKR?gTR^E$I`qh3d>HiDUFUf03?;N800BA|?5}+TT z*OK1VPt&X=y_=VQ?ORKFcL)92x0dvmuoFq9=Sn0UzoLjIKSE9x8641>Nm1^;St?0p?I7fJ z32+%pI!SO>KbNtjzkt5oyhJ9F{y!P=x;waxCB3r(c`wOKhI4;|)rVX9Ba;5N{9sG} zW%0o*O!{hY{l)ukJ?Wh#x($Ms^nsYl6H%V@S22}8`?1AhB#<`2FB%!|htqhxy5e+sQdF zB)wuBPrk&2Jn8kkkT)>OWi09VB2nI}nzKfLY-E5WxE)Kn6MbI`a2ZQ_l@KAsWi06p zkmT!LE}NxdP_*X=IJk@@og_FA=Q5V`E-K^=p)!&5t`W$4Ln3xW#**G0%NXWoG84cV zh0GJut&)CI@e8VLRaD_e!0Dc#rzGsv9Ws7SUK+je${x(_T5!eV+U`fG#&5~nzER&9 zb{}6Mxr$e;>jC2z=xy`V*^}2h!FA2czCeFQA|;UTJ2t2d?X=x{2Sd|3j!2 z$losd#Dl5`UC@%eUBSRyH~e7F#x=3;%k&6!xDj27j8TK@CW73<9v!d6B9)0ROvj z#bI)289a<#G)<+-|JW~Ul0#gQtN+1OXZRndx$1W=iSj>U{Ey@MA1Wfx#=*cz`~zzX z353=b^2hat@2gl_)@wC|gt`&yn#A)Cs`AF@s@P4;3?$gEVA+}LSLjK4c)x;j$-OSo zGfnH5s4cj?lrm!)e&ss}>j2g>2qN`#`ciT|~RajLndm*Wqtg8-6)z@9e?{BAs!F~||iwVGAl^MJLeiPid-oyTP z7?O$$ul>rXW6c7nih}(@0FsIbul>@y^DmqLcOe<F5M!O5(PVN~; zNb))E6ham9I)Z?ug(@nYwjDYK?jp$Ruot}yfYRwPJx_x>6M4n3tdc@?P$}8IkA$ia z*mDsOyHBmxvPPA5I|En2T~q>l4gzBB=c)tJ2i^ZDfhy$n8v^2xOIImPr|(CvV#w=Y z7?KJLuU{mWsn-s07e`(PupZu4bg%E_UDo(Cp7~P9Yd4k^7pfI% zO8q7)P!*<|#9OZkz;ETYCl0(1?$SQGySnwNL8W>tO}Pf{GRSKu0%G^b&&CRQ_l)Az zQH8wl@l8^OtgC)jdh82lg1ap8+7ZALrRu6R@|&5%%b_X)_H77wLjbN(i`R-A0e3k+ z*ta5Jx&ZuMJ)1HABXE~TUJ(RL6M(DLuj19_qY8O#@j_Cn@LHt~9k=@mxU-PgrZ{>D z)oS_uzHhZeRTS(S5inH%{vhw&I4&356=bmgh^P0aqzC_ldc1z8hTxWv*Ln>8j-snp z$(B=_`l1SXtqY?{c&${ocKxmrxF17aYXb-x3xlOZCw8Ggw8dnZUjn0Z$6AFVuA% z=41C&Ed=&&5b&hIOCB&`<`i&eBd?S@OWBJR4HJehk)mV*FyQ^n6migWH<8qiU10) zg{t$#u5NI9kk^-Cu>K`fU(4^V>VZk|Ag?d5tn&hJfm&nnjJLsET>|?Y1pG^=zE)FK zz3oF)80?=T;CTVKK;Arb$S!c#Kwh6A;5nh1uYP-G>ObK2BCpwAOr-#vC%?VBPz_We zubEiZS>ZKL-EGCU6x}twVE+^W&kC>k^5tXWUO-g@>@yIsyY7|rjC^fqmtNqmg}kO? z)9WDfmXg#SH`F=*GPr9auaCo!)LPY5+49akgZ7~cd4;f5wi2r5^8BSIyMVh6^7;?~ zTMAV(^_3ZqWB2t0^7;VxNBTnIfbf}gX{r!9zpTSZw*rA;%gm8E;#kj;k7+XUcJ<=ljoHoD~v*=)!h z5vs*X`_X{eYoyT4hRhKGxI~&WuxMMl0S?)0$h=i}El~!08y81agl#soMRl zC%PRD-E3%!@cKr2SvlRE?uug{fx&MQs)bUiJjI17g{ zXwna8!C2EOO+Td-| zW?H3MNo+=BBRdMQWha}dWor|CjA+gikQ=2P%N^K1whqw8qimZk^0|7l&6fDsJTA?J zBuNj_dPMm-^eyg7(*`4{i4Cs2j%dwOwyr6LgYLG7=*0$CL3kaOR!o0MqF>D?J9Q;x z8B|Ku7t3u&6$b3V2kZAG6H;r3WU%vNH+JrJsB_^w?{YvxZ{X!htb!QXUOZg$`dtH?@U0FVT5RUP>M8RIt0Z9uL z9!AoK%Hsqo)e9leSn;HLs`qO`ZyB0so$C}1y&fHQ<@ zlJtvzx*gm-(W?jo&Jcj_Dr@eCRB+2G*c~BA`dFwYC`}rVTn+ACA+X!AtWSh$ytLrb z#RK5(?E`yZ1e`9)8n5IW+JhsgK5?+8Bj6`OH9<<9F(eJ#{gGE10)8(5KbFonzEcj| z12Do=2PCZ&ULonV6Bj=P_p8XuhGnf3ULnOaI`tH|UkiXe1p!63nDmi!`Ngd`7J3~c zOh&-40Q^Wv_V+6S?je4#TM_U(p?X)!82bH5aK9me-4a5TDCS_= zO;aA*Rkbm=heyC}LckRQ@B^vJ)ysH^9~pv-{}6D6@cKa6`(eBpxJTjM?)MRJxlm1$ z#@3(k0k}s8Amd*LBrOxF_m!~~Bcs4Q#s?YyU|GvWSyQEdn^i$xK?h{qMZl#7FKI>l z-%5getO^--2%y1Bx%%QdtN`QVkZ}tE7YWsSQj3bm@XWs#fsC6W1Qe<%(#m_^CxLqs z^16X#Ef!@>R(3nT#|Wp$kZ}zGmk6)-l#S=sj|DegS2M06;1YwEG;HYh`r!Tmd0ioZ z!fTQuO&^C@{s?)+9a!gu*Fe2jy{nf<8O59 zNRMV<(dW^!Bek5NK*nDoNb%F7PXmx~&JQWi(xaJ(awZBX&r`oyamYB0me|K2CXS#o zPT|AMN)m6hDR-4scW0diH;%h9PCCHWTjeTS9i?pU(Tm`ogQ`EHV5^{e*(}ne%)k18 z`wItTs0i3vsH#hQs@t9g_m`;p0|84b95Cg+^xD;DI)eKv1pFNVpB7#flwG@Ctpjca zRmVbLvk0%-${W2#6bJWw1U!mmJ*lf~*-GQ5``}H**Qh#-fXTWl<)%{O=D5M&UJ!tc zJOr$(t87)2W*z>-o4|#riXmW+N(SMb8V7*&Tz zS-L9ahVs*G+aKUwf`GpvU~L`HR#jRx^UO4GFGbZs1hfjTo6`F`oOo}u908*U_=ND1 zq@$I5TfqG-s`iJ_OIM{_k+yw)6Gy!(5O5!sRYwQ3RhG&vZ;RK{?@+Y|0h4r9%5_DR z&td-?jzY$-2>67qvQ<`|yVn7evJzFh5wMb8mdz~HtzHKAwEF=8e{q2A6;(eQwWakF zmwXKFRjB$I%aROU%E!lUVJEv90e2!`Z&~-MrP!a|dJx=eQ1uf6KCXME+*d~Vp8E{k z>kx1|0`?SM)s?SztoQ-k>ru5W1h$I0mkpF2nNQUQ_XY&qie>duMOl*KsD!=tkEq&$ zfR9VM%A_>S?1XoEo4k;*83A7wUNxoEnS1amyBSrR5b!bK1=71+Pj3V_f@N%UU|F&b zSW_uHqv;KBM^J^K*d9~3D&;@v*cxY3aBoAv^$6HglvP7|f59f~-L|7@9RgMqWtpU+ z<$j+B?i~n-C(HJ-D9fv)^>5n_+&`gebqH*!x>w47%I*F;E`$4L1YCt>$-=9Ka`o6$ zyu9r~)%OUPrRWjN7Ahfp=&3%26AD&?N?TC{2paOcD!Ly2RA5)avRVHajA zr>j!VDoLhS@y0ZV|Mmy>VO04{U@I%U?n>UyoA7q-2m&@jReN1! zb4inyUn~Xgqo`_t5th{fQ|?Gx8vcfqe@DQ2GT7P)FQ-(gROY|nK8~uo6862iD&>x{ zeSV?6;Qj*v@mAH=P6xC(l^xLw_%K36RZTzG%IK<;+tNp&&#_B6;fIVGKCrdbRkmtU zr$Ym7=0Z7?GuWc8+kWmH;>r0RR4nW~P zVX*a~mKVcNxHnpEqeqwGQ1}%uq->=}akP9n4k_)Z-xai!(Xu@~x++28o;d3NSutTN zxQc!+;i&%?i5y*%p>X#wBv+u8*Ab#AZ8=Hhy0Z4?jlM9 zEbkAQ=qua65)2QZVJ$x%5qyt13WdEvuvDW*RtFTW9tKNQYH1BaVYdpFqIzkTH2J&5lb!=l z5`s9RV8N53J#)2`Q>QdTLr+Qs3TLCVr0^;#x9IJ-44y(*7*-TZW#Lsy-doCo8-AuK zP`I)TmJ-4%Q$4lnN-gjd4nX0@L+B+`Wz`a2F2=3q>^>;`SP;t+fJNlH_m2(+PZ0+c zF0bNF&BCjUI>R4r3PIuGVX#ybWtCEE&2E+qo-#5N&Q!20p~_H8?ks^j>Xk!Yc0X7i z7l38tF}1!_z>|f%GBCp8LgkRVm1xioJQDIs#|R%6fTd;Us8rmx6z@ONmmy$rp>n9( z=Kin|JdcMVeKCenUI3O>&qq>lBhAXV+IAtTl4%X78lsz6Tgii`#c)Srv52C8C z@OoKVlKNOP@YD)H`a3dMUNNYY=hiGp1y3Cr(yJlw7lrCM>0bCWp2)fw6uvrR=_1Pd zpH%(xp?kseB&sUnIqqceQufV#9QPA^DoU3vTe=y%l-?Q5a066q!RciKV0l5Pnkz>G zGrytxOp--v_&+*Hj(f2;+P(34x+^l>i(Oo|EUlEHolO0} z(<}_>CP%()+5;K)i_=|~={D_83&1u~O8+{zEoMvn2;dzg)>4F6O46(Qw+=vB7hk^3-D`KKae(d`O*VJ8v=wEwRxIWk|AFUeEUS|rtg}_l z%Q{0Y9;%7^g|e!Sjp{(w+-}b*4~FS37M>#=U|&gdxq3fU|_^ z6S>MzZyoUX@xyS>I>0)^pi;jWhugn-I{G2)87xZ-{;Wl$#|O0o@Zd9>v_@FgbCMom zmh^4o)h)sELLAZ>M8H~9s2tMsGcRBrMY?JA!eFf@R9akFOsEPg z7Xp7`mFlKIT3w8=m7*SCZ}2GPM^488iq24h)ekyizwawx0L482KrTE&g6!0Hz&uhcV8 z`W$$MU|FU7V0}!e(v?2ZHxJUCTycvi^iuS*QC+E%J8(UC-UvWiG2|u2pjNvyu)_+h zhi@VvUUaOYEn90S^Wz`R1@I&NJh|^R^$-Y*<4Qpp-PrkdY{9cy{9@LwMP`JVnl9r zNtZq^iEa6P6;fXcp_im5C0+Wt;^RZW^FbU^yCb0J53NpV?1q}C`X~aa-5g*oA<9aV z4tgss1<%LG3){0*jIFIsC6e*)5%7E>Luy+rtE9n8sS%w#89bkQA+>b`tfD`(R+IA5 zTiylFEacTPj9wzbRO$89)#&vZ@@kG}LyZ2d*~(z+=V{>i9CvhA6Q!mz-r2>R@Dc9=gT0ZHVz;!p-NUt`UYZ_ap;iRPzGxo0hle#4?c-y%|~AK zkymlyRY+P=XGTx(EI?jQA+OfLtFn}~v1=djEHXiA-8gy)RUzf{io5><&o@y>eL}*r z1YlKVNZ;kyh?XF)+Q_SwP*qmS@46;|XBqOUiM(11RTb%Yv&*-^^DXkKfxPM(R7%O+ zU*hQZJ3pj)6tKQ6>lNT-<>JBCbLi&n}M6IC#F7AT=9#y{+nAy`&Fj ze0rL04o}`3v`!YPch$H1{_`1lRz)DS3i9e9>0UjR8u6y*>E`p~MLg>SgO}XYcB(FT z)?!%|gJ6A2*1cYq0v$WIrJLK6SEH?ygx4tfS#RcV;8~AlWg)MT!b_Gu>U0~&06!vN zIpj4_c)g>3Q)^BU@N7g?Y2-ChsAQ$%o@pn*vnfblZ?H}hfbYnk_TNz(JeyHf49gm> zdzqWa^;Z4h1y2M4GqJ4qgx4r_ZO4+Bl&z?;Bd-yBwuM@ER?z zX%oWcupL!tUaWg^`I)G;IFBJ;8=Yvf|p)GKr&da{_@vQBvIR3}xR zfY-0xDr8-8pqEgsQR~&u#pbXF0WV`&y9MADd6s|IN8s6us!IsCUZ{Rh_w8(q-SR#J zyoi9m2*4fkE6QV^fM-9dE+F7$p;|5f+8ft5c@7}p`4Cuk3Bc|0>77Ysz;h5)e_>gh zgld(%y#5!Z!Sfpeo<+c4glfB5KJ!_;_#Q&l83f!U%37rks{30v@Z|dFVqD8Eq1q~| z-N(hj6GPQ02Sz9WSIFTpPd)*jJOn&}W$h4N+tjL!AD;-G!>Ibx500JpA7RKk z;swhdq1q`|O0PE%JbwluD=!X~c>-{PwB*E9?1)a{8sk_PEGvcTePzVog(raL6smF& zaGIo7n+Zy>-pxCL=X9LDkziRQycWsH)9$*!a|TtvAz(;&1(h~~zW*6K=MeB<04z&| z*8+J~i#}t(gK5kZb`7m8TZ&_mSQlC0!SZe&d!nJh+a4 z+v8Z4s;j=1%XM5_5j;0gwJnTg39o+Aljmk&Gr#4aYr-vyMOpLY)r;C==WrWU5ieNY zQ*^+f6q~*gd$v0WxEae@EXtZMw;EaDK6vh;YEu9#-wV}3dGOueH-qOM0&YaW<)W;G z>U*Py;Em5IOW0pzHGf^w-2D&zY=)m&=ft85jFj z#u;v$Z-o@6j2d%j_SCA(vNQR?VsMr_ktIy}`#^tY*-7G-{SsN4zR6sClUe$Mnq|@) z-7@JLiI-ksm4D%L%rc~sUo*a=IY;7g8Z5IerANPJmLEB|<>!eo%Re);@^xnUfsb2$ zkqEO~?-Q2N%<_GDmPqMy6JeGe+N|L)W;sRHF%wyq+0uU9MrJuF#4SHhRC?*|L#wx8 zmhVNlm__eRxKfr`j#9YgtVEWXWAY{pVU{C9+;V=R z(u-^xSNQ_793J78UnjzJc=`_ijad$hbIbXOEbYHGEc*ttd_&@vUneR(qxJAoVP-kR z&n*`u!Ytgh@A59p@^v4#oRe!7N`@IOf7crKb++ z+tSA@2SmB$vuc7CSEx`Av&t-Kv!`uycB0a4RlSRUWtM&P^Eo?F=_#XT{yc(N_V$rq z!sxR^mdSHYb-BhYdxdn%M5QO$2jA<Uqm)TA-^c23mnMb;GP+#zbJcNCVvsxX94ZO%jz}rp>C@C#>|NI%eZUn57%deEl@DJgj5-5@D7K_E_g;mbp4+lSG&$ zpX^?)IkP+@FcVpp$joY`)sBN+;z7=Q{Y0e~FSS_S!7%shn9UMd7VEe<*~u*T>X^+F zSr)C{>|{k|xm#c=3G$w~rut)ApR`M0CbBG|{QY|}!~7{qehH(diAr~<9Y(pB<#rvj zMIualyH0BtFw2OJ*&-2U#*Ap6f0*TF9kXR3%)(2zy&^HoA9c)@i7?X#3?6x#S*{O| zU&5$WBFnTd4t-yVS+3DB>m@2Z)j##JHYiTt9B zPMDLw$)q{?C9=m<@)wa^SIIBR=ma_W8{9V~@{2M$F;4yl_br+HqKr<6lfQ9_TqVE6 z_fv`dMPzs5^cQ8vRPq;*{mWxE|0eUZVE$d^V|BRH{k^-?5+}aNFG2iWO<-yAPx!0? zwZz$T&5}-wQyET;(_g&Rsj8B{uxyW&mW}rwmU4R87P5ku-KE(6Dzp9uv#cB;zgV`V zyk54!G9|ObL|P`9w$&`ncm}kr8Z46smFhL0SdeL9&C((zvP|mL^~1-RWf@twloMcD zYfrmzjain6aLdOMSz69cm40NFMI~-oAyMh(IZG#PWR`Xxx2%{56RJ#~Uzu5^Dclmz z!o%E6qn6j2!7NiE+|sO)zsUKhMt@0uXGru{@b9_%{;^GI>mXiDi#Omgeg_Jne`DnSth(y%Sl& z&l^8s{Xb4)>y}c2(oMb1>&_AjG8fJ*I}6LMk{;)ni5+_|%f?Y|**uY@x$%kpY0R>r zms@sAWC<5WSG~t9>*<(X6+KQ-x@n5(UoB@(1~_JpO#ULV`xNp^&YbAOEV#Z#YeAM3 zf8QuWEXbrTw`?oQ5te4TZjm<3vbA1Li$s<%zTqc3m}N^Hvz?^JE-+0g^#|@^md(Oi z>DK8ox3tdETe@Y{nE9ufWk)}^{4|lJ`RatDMVO^Os9UNDFrj7YYc-i=2fg%Zi7-ut z7nQxpEZYS*rntshTj=Mr!lp}RcHPEV3*A!EOBa?|ZJ&DYTZZ{=q*vj5F~XE?K5M1E+?Y?R2d%*opqN;1p&GPe|C ze?#e|7Y-f7#z8nq#Vs2t3AmR!x3p7FVnHUsxMlrBmL+>-wmHEpXZg5g<3yGv`Ybw4 z&p4UH(=8J*Dt>IyAPw`Q2)AsK$g-Hf)W=%S`M%06nYTwyxF0mk!oaC4EblCQ^ zKGtxSG6&V|bdXq(nNn^k#w-TQBH!(K>vv{3F2pT;iAr|_HovxsS&oTwOELC0VA@Bw zS+C{jZ9lhck|@rMYXdV^FwD1n+*0&v2F$|!YSp~YEJx^!nkB+auljl4JH znfBeVGy?J@f5t3( z`N=Qo=g-Os7+E^be`y%A?CH}it@RUOn$>~k0JD6F{*s#9Qb~XbG5>Q;W~o1qu(nKu zX$rWX*WzT~&>@&X5$Agh($TFpGo1rf-%k4pKIVO>1@~1OC zILR!xO5Ac>BFm)162>e~eg=8AxuqCsFCi?^hf98?%i0xaHnNmPy+-%+$t@hg5F4JCUXJ^uTNju^=5OH=x; zF87$_t{}Gzi_*W>M^>ky&2z^EkgvWSR7Hr{T+) zWn9O6U*hfEBDh=qf9Gkf3zqFGt3J*=67-eOmo*gi>ENlzjVx%i7a8L z?0b?~o{5uRlJ^yfN;e&t_O{mBoYFA|D8vWrEKXmNUo-v*9aU2@TayZd6!vMT9%W?{ z_;9xH;cZWUtUGxqegtR>RFC{W&dxl*s`>rn^R!G0&77I6*-mId%{{3|$Ze(7r7SZ_ zN3xSETP0i}WV=d+Bxhz)w(25nwkshaR}0P3I1-X@OQeL~^EsdGxu@oP=Kk&VWLpTTgj;eNcM4!{29k9gfMIp*E_%b#Gj;Q`ybqqpgs zE*puz|6+FnH)-qr>!CQi-5z=H%S9Qi!}KT%$VCy7-A;^Qg~kHo1%Y0x?BOfe!Uuy~ zz%25QULJPGG3F8)&&F=<-|$eJX zPQ`mgJ4D4Z>NZSE(ej^6(DJ8a`44&BB;}W;F@zz>y^vn{Q^i2?+`9E=oQ^ldv+}2< z#0K1Euly$yGKgn(2mI~ohUsypdF4OjsPdmS1G`_nb?nVp{`*k$QN&;Vb6D_kw(R~a zELfNSJQn;r-l@X7?_j~Y`{fo}hk-+??hj7FhUe0fT$ev9B{bdrDeX@k>@5+s;rWF8 zqwc;FmqB>>U9tRfi)pO<1`AaA4JNpOJOmkv$((NMR+eoPgV8e2(OyA zc?mXlJKlpd&qaa_OAT)i5WD=+G`oF>agaIxR}?lZigJ-wy*MH?UG*ug8n@wdeyJh< z=w&@|W(qbe5s_upc(c-mrD-WsSSM?3`srvF(-L_%XA41WZeP;M-oZ)@aatHqcD`PX9SDi9x)nDe&syCT{ zw~=u+RrQ|;x7y|+t@?|w&~(-B&1Xv#vE$p9>~Cx~ld4mu(8LVi7KII)Jk8s|OI6kU zO>Mt3eEhLbbjPYcf}-`dzt=y9y&H4Ho7y(4Q}5TmV4eD~_KQpR>tB=X1~SejtM1q? z4jXd>5O1opyF51Ri8IYBf0i!)IVZ6E zLssASHI}~;imLr{zOn)K^nN+#D;p+B`IU_vQhsIQ7%9Ip*Jd}6a7fwx4yQ!{19Fj+ zk70$T%kMaQ2i}s8p+lEx!Kq{5iV(nZf0s8Ed=_%U=aW-zI$feq}2x>fWd< z|A;6p|Hud}|0s)=f3(4Fz~GR&d~94RMb7tqocxtXc;p%T{%-`$tB26k7gK zme54^@pg~OqYb8c+%y&d9otc z<#+bTGrHe&&(ja^^1E0(3hjPZLujJ=_u=I4nr0d=pG^MX?w3wl`68D8ITZbD_{;B+ z0Jc1s=>A!8T7Ec6%f}NyedMp~Ww9H0IHW57j2Kk*NJw&B{#kLM>F$qdV7$P~4@c!6 zb@zKlWDvgZPcZ;9GR-T0mM;IP;PQ(%y&J>wS3}XSmcRS~c&xw6lI0J?W4%7~4Z>r+ zKJ*Q?Y57CK>`o*OsmebSDF-CEC_=Ke<0=O_Leu5<`S)gAZ-MRm@>2or{$N`M;pIP? zhRPvfrg`O;lgS@k{&mZDK8@vn0Y%#*{_-!xq9&?+|DrH0|6-GtUz|hBFLv22RUA^6 zk8|`wn~Svki^4+F@v+Ozf6}uBe?wW zW2Vi=@>5W>GwLsYlml!jJ2Ck$kJ0i++qC>E!nFJ=@wS$;lMINQ_VmDNMmb!h@ zYJ!^lH=4BkXbvqu>eBLWO0t{W7!WNV571-6T%_gSXbMf2|H)Sm;>sJW`%(5cU-zS~ z&_wyq7*Kgrl4-pAy8LH?%YWhcUdLkjYoG{k4mjyw7o*7eS~(#G`Qy~&zr&{GPYl!Y z@x7NE`tHhMck5v!T0R~*F(4Od`FGet)8#iBazzC%e_~kvQFs4NQ)r_6nF*-8i%Gov z=Slg&lRrKAzK^itwNUg=%3uCuJl5ZykdyxbJl5+&--CFp*N47`ELuJui}AKY21L3a zHlcEIoQt&l2fPlm-5akD;Q!!tyo<)Q*}=p`wv+%2tV{W=<5`NX zm;c>xn_b9S2cev_zx=6K)NN|tpJveVr=@B6Po`-3(-Z9eNe(He5?iOTa;hTNZ+z1{ z@{ID|9XFwtmp?7dqtHX&lPRHz?$5TMa(aSkUir`K@}CZ#{3o>PFcHgN51~eezx-KI zZ~07d=zBgw%XchVewjhbFT>Lw{1O#kr29R?P&q5gMcRFK=-~}k-G6w}qD zHNm6E?w^CXUJ;Sy8(-rzU`961D}S-x_umLE|HD?pr(^kFL#TPgU;d&bu(eJ__ZK^~ z{3S73{!*Kkzbe9(nDLe08>?BAGEF>E(cT!C29HJIc(7%4k^p;_?iiouE|B({coAX z4*9zKE8fP#tT*{LCFLJ=`QN%i6WuQ`pz=G1XPX!+?FTfK-ws`B5!?yF08JS1EAw^CiY)8+s5 z`YX7e8{7AP^UBKXKEJMqnkfIEG*qTzESp#Uo4Wkhg3BMAigdv8t08nq%3uEOFtGdD zMfrP7TK?ZTwEVwaTK-$rpy0wQ78TtM&;kG{G;yv z-%MiDMU;P794hxFndX(hQ1APR;PMl*;<(>5u7S|uX(`;s^LF|PchF8?4yXrlY30hp0#eDdq=F97ab0%%6}&Y7?6v!`^Q*9)8+qr z_2(z>^3AmTqb}bxWDwr{;}THSI>j_re#0xh2R*Ux@0xVB8$!SPZ0I-H&dGRK--4>I zmtoQ0K&Y+!BC7#3ne5{BRVO68dzzbcvDv>)jI(>1S#ZdaL)dN4IE;(H2eO-=aWK<7 ziaQlp(+!ENVE{4Od5Pb)skUU-}oIW|;P5J@{-`ViKd>;;ec~sShY2M-6>ngi} zzp9VRG|!zo9Oce!f$q#b|Foo5Rd<1afK{{W$`jvwcugtz8{z_}Q``o!XyWk1=n5LFi?xG3F8qjqsz z;oubrxucH@bSG_H{|Vy!2%%F`ew<6g-oh0EXC!*{Y1)VL3p#OWI1}er)JB?2^O`lm zQ8>2;y0gV`Qi!t!Lfv!xIHObE>Kg**3iN7qlxJ4%Y(*zVV*ompe@2aevF+j9McfI* z+56X%uOiM*5IV#1<6LKZONa=Z>(Q$(Eg#MnbmBTY6Xz$?t`9Sf<7jur2R3WMl%+2q z&Q=KZu>CkUrM-1f1kPCWN`9zO?tGtys+-c8I6t5^)^p6mxm&w4ArR-Y?qBytoSz{S zj{9-O#k|E_1kQN$>MOrH-=P!ZVwpIbQ5$bF&BM7$yK{9Q&SgW^^+%j-5bBlmbP^Y6Lf+x;jR%MBTgDZ17m)iXCmIBN&;tw#nw^cnWZ~y z-KDB$geY+;QJY~YoSQVxb%E|&edL9gAkKCO4NmxRo_D>Kp#+YDUTrpfIJkIJ)$=YF zCC=BVIZ38@?nE8s&b5K=jBPrz2yu2m=v>#2GbidTZzXW%qE|n}d1mF#T6AJgl#3E) z9cptU3g;$`bA6yYf9^P(x$`@O&Nuux^K!g3x&+QV^osvjm%O8Y8H1{MEHgRZ!S%bU z=DAGc?wHD*>jK?*c%uCj;_QUbu&^KJjkvean7~|yO)Ky^D#Q{aX1raC2A{8iPPvjh0|zY z;M^H7Dt;c~`~{&AIewhaQ{Lix0%tXP^=E`%cMesPaBA?nK)#oSG%JZtR7Y8Ac3p~puz4S~nh4W89Q^uPoGUjP z8i+H~dZjPo{0*VY<9?h?cu|sFnBX6ZH@R&2MwW%(u*(gbm_~5kWtz)059dNh;hZ1X ztgclbEk&HY5V|7i$Jr9+mx(yePw3U*NtT7+yoF9|iE~l9gNs#G{p2~u-O)J10^Mo8 z_iOgC?;i+VmG1LQr&zmlK_Je3w;b^-;`|4p z>mz=g0}-d4{7_uo!e&dF`f%_vb@hQh99;Vp2eW~mJ0;qk3j&+voU#pDpPK`rF)=?* zOM`#Cz};z?X6v%DEM)HBmj=}>4K7M|UT0dGX$+^~L&}|oYu%vJubciX3?mLcurZqO z;~Y-Um8)B!R~;ReMdPqj_v*uiC~+1<00*;y9?n)<&YgxE>>!*6-@SS(;xvHJSl5qZ z(sSkN*639z%Ch)yOpA*WXI>0&Fw;DopIn9Wb)Y*Z%{b_E#AyhjTMa)>yBu=rUfs@R z3-c7v|}1FN}N{`fP)=)m@pyakgoksz98_9$9@X;^ac;4#$tvJ>jkREO1Uoueu8( z6pj;z>h6h5oN^ngPxl7$X6d=JHV|jiDeQx8ZW9RIneyZG413E~3!Gl)RgWmotZ?wx zE7d*2nK-j>D)%y(=HYD9I5mMdmyW&tF~n&Kp;(R|=j@cX_O`$|2fgZL@XQJae@j$- zc8ZI#Su=3%oRd&ETQp9!8#I-lt9kJn#AybhNtPdHi0v&PE^y98uljmf$W)$=b7zR1 ziBlSe>T|;i=U0tW6Npo3cF#kc<`BZK2>7p^Wa-tz(%vfQ0_Otss(+kkmP6P=={PJC zXBy6(3sM@#R>z&{z-A4dpT~Ce10Xax?#H<#<}KweaE7B-ml!^rN7GP!Nh}lR@g!6a zx0&Y6o!>Oh#z1#+R$hu1<8lv#(1S@o&M3oMk6z%6La#>n-I;=OXOv)+bLU~4JEPJH z=NH|qje+j`a8B7~#AyMcDQQ2>)fw+u*PvH+gk{ll$2%%t?Ql`zJcx7Wni$hOchVZC zHqf22Bd>i2aq=MasOiTUi|yI#iY(PPhuMn%EQ`irPY9?UYjaWJOpXE$W*W!Q&8iB- zdFQU4LlGw*LXSuMIOEdnm*)~^JWl2RES_0SF6192`I z6uJ#@3VU+4a2|0oamM3Rel*53Z|>~S?tBy2teyQX+k`kRA@sE2$C;LK`t>B< z!qFnhvgoPoxiih;qIBnWoXSsnjxn4@4ISmqra*T_w+|H{&Os2G5%%NE$nl;fBIXXh z72)GUGI7}BMyh8p4H+fQZA^2S=DD-oRXE=Uy3_mm9g7j?U2=fjtmK;FLw# zGf-F-?M}zB=!CxA);q^%4@;>o^9FkEG}7*T7wFDEC%2i6IEO%JmgC2nYXWrkR=v~BV1);gNALo4=*prR~&T{mso#Df|5}kP8=Ay*8 z3bo~7rg3+4v%U(%xqry)OAzM>2)z{d<9wV3_P8d2vl6{JG0n1&J?nCG;$tC7oYAPQ zOevfnG|tz7&02Krb)|@NB!pf``f*mryk|}coG;L;qPP#|vItbKj&V`qj6&@Tn`xdq zKj>y{2y~}kkBc5aoTDH#FYU)!pYfix9=$p_$}`Kk;~kaP8(fq)Bk@gQeOlpc)i||* z?tC?@A)7l#LnvYTajG5f5nsZc8uY45I1`6G1+2Q-;iAMD5ryiS7}Gp=e$zOc0^NDK zs$&`A90Q@(BYvDsmiL@8f%Bcg9!l zbnde42E;KTv@qt!*^=}gwkB|XLa$Cw`f!GsP`yQn66b<6RR83#fgaAIw!~@lXdq6D zS3i9Uaau!YQNoY&TZCT0NTXMSQ!I;i$D2F9MYt$&&c~^o_8jwYp3pdt2hN@AX24Fw zITk`oTtChqF2(s1y*k(Hfe+^oHxnlkgX%w%O!IK!YVI_8EYO{f^{WnBSfL2Glf*XW|S%t$9@8bksN}1>!t4<*{QCr!9ouclfzu&}J)M+i zRy{g11vMv`T$DIHQ0u@Xj&rWY>0<`rob}|)LlNgB2z_Sz-RYDD_PkYrb29#F_F$7` zA?}=x?sQ6XQR3jQqiRl0G0k&lh@;#Y9O%xBo%gRpoDL9L9rxpOOL`BD6*#9k>^ZSK zvvQ{!I?*l3MTv77YNt6&^Kc^Cogsnl{66cZ{)p2NLaC%5=PaB%$Ez8P(*z%O%QGvS zQ=(9FmJlV*si=i5g;T6?Mg-zKH1&~jh*JciHEBOiKNIqMt7e^zbEmzNiPHhantmo1 zB~BL`YR+a7cgNN^!vmW&YwOz|BTfiH>rFq-pakUiReRRpID57*%cAE_hkkLW8I<6n z#5ozY!EvT}%^Ioa&WJ#qahqR#8gVQLeI4=R3=Knmzm&*QgJ(4O6l9)RHmd^~STi)t zMTui20S7aU<7js-4Q$qf!#BqerxS!KV}2Ywo6A4PkvJs@_Pl16g}Bo<0X4-!lsH9c zs3}RXfefe7!}U1&&41+0^+<6tgsKyM3fuM`C@prV%fjq|(wP+OnbS44%|%Jk(S@4J z!c6lh9@17kS=ck%Ywi(FNmJS+p=OfD&2SpFAUJjqPMfEm zEkvAd5c<*e&y)wl-c#iT&O;`9kh~AaG@$0eFc&3GYZq!BGMVP#9Ox={ng-&Ot~j7K z;+zJdt%e`xF}#;2U!5~No`4p42G6Xf%#l&3c`U_6iE}hgna2|vN4t|7*sN92uZt0< zJA}4{{W#NYc4L{yQu7pgRp|I|4#T-K-R7diX=MWrW}4?tp2lew=+4}dE3QDC(;@V0 z)Q|IQn%(9nab}`dhsIbIGItJ2L(Q{kE=rt3aPG|X9OH9`G%L`Z5glgiMw~Msly>|$ zvzNH}+QcCfx%SL{;vC>WO(MoLj-%&J^FW-6$<9THa~6blS$>>F7P~!M;w(n5PGCu> zJB@MfEV8&LahfEdX0hj(htt-TZ;yRfVzc&pzt^$WNt=-(458h&pW^K#w7?sS#Np;$ zq$o=GC>kZ8=IvxAMI!@h-qjTC)LTN`6!&dNu}_aZA@uh?6d#}$R!mZ?z}B1`@liCu z)_h=PQULn1BE~f4MT1IPt#YP+S%N(hrZj|}*VxeahiFd5-EiM7JMAds>IGI#T)2bB z@5wGktXYNUbthSn`=7)9^(meMcZf>L&%)56i;20hV{!xUg2bvY7sY05kyhMPXxwOg z9uCxe=8f~nYn6XZI@i_3#E_=9B4=-~8XEpCu5sDYf|6`4_Ou(zN9Iz8y-}!H<8o09 z#OL=w&Dtc>Jc=is;JLJ*=H0`Qq7PV&_o1jnM^0C#omFvYab}b!l_&>JIMWyfJg+F~_Ts~33zJCE7px}xP~gdzw*VOA@tQZTfk2)RxLNC5aa8XkH zr;4r5ANmT(Er6+epz5tY-UA{9yB?F*(JL=uB_ZNAV|m@q?X7vCD>XPx+z{8a0h$4JR7V7_MzC8h8E|jdGSjMTJ%e@;KYkR(EV*`E=n){#M${vifN1@ z*R03vJa2XXJft`WtQPxF{2qfAgVcVr6P+30@Puk!?8J`z9^;~<*oht4X*12ESXqyG zF?r^ZJ&>Y5So!-<>@lFlh_nb^gA=jEa4`iG#SZMq9wU?DckIX>&mTt7WMDn!g?VMi zzmQ@8Som(6`9WY~jsq=h>BUAsXGU5)p`zHH034P{vBLx$%ruW;c|AIEPx+lsBE>+k zTJA&9#A1u>3NJP`MQ1MaN+k2**EDQwBG6<<(ow*{lA`J5^`KapzW6+(7zEbA`%tt< zvSnZ;MIJgcI?93*ifx#&MUsn>;urKM&taP9#Rv7E7(Fa~IZ_M;>(G5D4vMfPcqPTb z7UZ=Gv*3i{C-mZ=2p1*A&lYSv*z?DucvGFFG+BX1@c;d*#?QAjsYaY3U>&{>PAeDk zj!jFPBa)D3`f+}Yz{XZ?Ce9Yrjz}`i!`W)e^ZzC*-5{L!vUDrNITx%W!v6W%ItqFC z`H#PCZ9EpeYUdSA+}Vuov=)t%?tG6Lzh33x{NyN{PXgWP{O-Zi5GMlGQBgk*ehAD9 zDV+A`RfjMun&50gC)zU&MTzqr(_E%`I6rH5J`Qvz`PISW5$8Oxj&b}rMRCaMY)W@R z=v5~%P1N4}4LTveFO@hhYW$bH+#QXxD$t!FiJRIY&iP=qPWf^AT99{|EphsVA@3BE z6;0gP7>A90MF%BLEo%M3Y@mm;P2+qL=+05U{`)B6396!#$G~}Hrd$4g(3i3|( z&z&lCVqlu3*3GI$ZBR<#{H*8Bsz97jkMCYYoMB+Kwfs2e#~`nFSh_RRhP*IKLfzSb zPMja(qI9PcwV^iCxH}qWQDC#)7;-;ulzRbK?fvJx8;cFdbJUJrj9xvT;F;Cj!7sOQ z7#AhZS4>MQoGlvXvp{!dj2_KC9bE|4iE+O>BOSdN}SJ8yTxJ}cSkpC zb)Y*7(^Fa^P6=3@BYvFmF66xympBv9tAxm`rt&A~#CSIoXBBD_l1%e((i-RUKz9a~ z-?<5KE&;1+%#Ra`Lf%5vtb5R_*ZuB%j84R&nK&y^yT{}9aDLOx`XbPsO`{j=LY(1X zotp6DJdgu8t2nMoH2b8Ll9>KSf{yu zoJZr3w^X_F7<#qDU|GoAS&mLTDj4P5`2e-Yq6%k=Zq}E9IE&Z(ha2Wz3f38hALmIE z^4>P2JJZptWho!dd+5ZICKn}661C|};_mFw?xX_ej&t?TPaw`nuzH03I5QHE_ikL` zJd0kv6XBUvv)(}`W+b>Mao$Dk*|^3b?gZi-H1)Ex5XS~99QEUrg(2^K)vR*#>OH?Z z%g~9ka3;=MsFj-v=XZ^h3TzfMzq~i%Tn1Jz$B#2N1$iH&q&qL7SIfPk$=q2Ig^hCs zqjYB}YA+@f&UW3bHG%G|8GZC_#2E!vpOhbGz72UFDR&m2S05VO2-U1N(TVvs7bOnv zj2jn(nda?TJGDD&0^PYR1+x+7arshk@=iC_nfZ#2F1%f6I^aRt)k!jZ2)j(W_Mvo>}1}(22KVnK-YZ_O{J5 z59bS4;{>`hdCqgWh;s#418qOfas%>Kt7a`nuRim;GasE;Ze-#tU|L$?tk>>*6o@l^ z(F0gR?v-E-j{9*|I*^x2Nq0U$ufB-$%*vft4cNHS$;6q5+9xrl@n&gvRs=Tdp>FLi zMVza^IydRZ`ND#{waT3odbLIvp>SS8C%&*Uab89(j=-RaAu-1%L*6MX04{4p<9BF+t94R`%Gf5sv2J43p&3%&X_ z#j=q1EPT`7_-CAp(w%2f+ZAP+hjX5~%2f9^9PF*7Mj)3EVhO) z6i+1phh>jFb zaUM4S2eX&w&h2U^ZhUdz5qD-)^N$ec7O<|1`f=J}dqN7QJ$ki0!ZWKWgV+6P+aBDA1i@haAE_CEN-Ye%#Nz98g;nCfEIHL+I5GFAJGFc-;?&W#T++ z0S;C;w`-i@KzE*4xe+VQy$!4zQ+}K-DRSMfwkvw|dx~dP?%;L5+Aczr?mT1z4pul5 zG|okVIA^Ax{{V4r2WxDOALn$NT=%Oz1HJkK(KGg}Ds<;`n~M_X0Yp3_%rtNAjMsCg zBoJrJp3Wl>XB=2~F~rxbo@sL3ueKL@C6D#W9Xz+F?U~NRxjzXwSm8|2IK_c;XVm;D zixFo$Shv}JoO5F2x?gR7^lF!vh0Gni?pJ$GEEDHm)cV^B=QfQ~5{Prl^%d+eI03A2 zaX-$v2D$E6doFsl+u)g%J9yo%R^FH(n{^K!ch2=3^O`kL&z(DN1#`Kr+8-N4qo@G9d2<^;@pMDoe_q@nMiN~-N_rozWmF*6Rf*UKhCHmx$akc zIePVvmxauo&(NJw$xNJyQNY1WBYjR?e=gxmt6O&jiOio#eFy*qdPac zT$DJtPvBstdG6e)n{{a*PPYy}bwZpNSobIVIJZT~b-&u%@z$f96wj>OS&@R;+oD{Q zIJe<(=k|!gxr^WgHfu>@+f2l{2doENKhB*wm9_r}R}zuNnvkT1_Vl{ee_p5z42l5-GcxHw34!SeNx?k-Ramdd#SQgT(W#~>k!9|I4BOZ62h%?Q@ znM82RAe`ebth5p5ez4+>AEz`-uKU$KjlY9x65*MZJ9yo%wlvH|iE{&LPn%5haALYy zV*_#4A2bSY9LSvv*3^_A=eZQQ?pHf20r^c+JhQ^Vt8cZ>2~px)hsT{+357FB<3t0S zHU8K>`H1rXSkrU-IJ0eX-LLkAFyuEkd^m5Q6SHkDN}OvD@r5wcJa=x^IK$kaW=)@6 z&GxJZ!78=4! zzm_vOU5ASjXH*<;Fw;DoTeUkE2DiDSEfgEfwJ=Yl|Y)=W4!7jYg13%}m*oeh4PB-j0FKXV|z zAmziEjqZG!%)}X)0vyaV&z;*e&c%T^=9KC0BhF)B&5rnS)aL?F(b}<1_x#^#5$6f8UUvOBKjc9EVe*PwEnYjxKf>mjl{2D|VRLU$9w6n=A{NJHt$< z-R5)W{0QJ+HqgWAuifb%i1W|v2QNaLX<#h~`*D6pcaE_o&Q5g4bXXRG6Ny3X?@S}^ zoNGbtPVLStGx&O>yQ1}8q<9jn*P?!k-EqiotxVbDLjG|!PpEn{1T*fAb5R~{1}C9* zkIOXAlrkrn;<80=vMa>X!NRxV%%jXVIVR*E?}*^v05+!qirNlwWzvUS8BA4m@efg{{qF=% z7>izAIUf@|4ZWsCpxOMS+)gFP`J+|^Qwe%ajmd#tf`&MSgj?(jnSKpTZd+Q)^|aKoLoJ9@4MxE(B z0%bZmtw=avxy)Y@W(7G2% z5l?s6KAXFz?%a(NCtroRn`7NhU7q{0h}?_AG7ZhWBqmjn`}ewY4?DgE+mjD~&Yi5f za{ID~+{)gM6Sw!yllQIjf8^2l< zFPXdUy5AhodNbzE2g5e&s(VFP#`Cg>+#kj=RB>$iSc-C<|5*=9NBE`ZLRqjlx>Wf8eoC1n(qD-RI&QoE~rx=8o5u+m}V;UK5j9Xx+HOikHZ}tM0l_9XG88a~}-Gm^$nB zWf8g8hh-L;`>U8#Meeh}>T%Wfq#dQi^h}?XA1+jpvxB zV(vpRccL!OeOW~As+deeb5|#&%IeO6zB{mP@|g<%%|C(mZyq<#`0aB1X!0Bwm!`nD zH7&RFKAL!^y}g$>Qe>Z)yp!JEug9pi*u^ZyEox&n?irhD7e~lAe)utlt8oni;M|%v zzaZQ!Fs?@xL2)T+ zxSL$6ak#4-s&TlhlSC8F-6$p89slptK;kn~%K|k5ai6P<)~d#)AnNOT!iCr=+Oi#;7Wow%A1riVuy^ zaUAY2hiC%saHR#o4SjW4V}zRx#dxY3E$Pe?5Y?wgPL z;LzMTP~01xn`+4I2;6B(Q*ABol8wINX3J(FEMUgw%rI&OE2fT?qFg6c0n^o>uV*+yEKN zn_nERmm@_DcV3!m9B!yVGyykEX+dzC*4>gsxR;=KL>P=`qcRqOJKvEa1L1H3!&F=B zvN=~0p&Ey~L$>xRoVWjzqYZq4)|1j9GCRpTJ$BGz~Y@k)n2PRDx<8?(!7T zgma^n76kWUpBE|+?iDD;GeM(F#V2r=+a!T-Zn%`lq2xM4iVT>;U2hRhz}=vPOmz1J*ZnRCc#V%{>%~7gxxLe{x6L7aGEeLLU?o~G<+&n10 zD+$Kjw2VdIZZV~(;jT|oZL!PX?nqIM!%b8Haa#d*r_zGp4!C|1#>|}$#SfTZykf}s z1a4wXiW=@#lWL1y26vxDH4b-wglGb8veJU!X5P}H7U32^@#E;+d=;O--G{09OT*n6 zquOGZ!99|q8i#u{O*8?g--d$VmYs6S&j^=*V!Q##cr7Ah5x7TVQq*wwyHw+F`UuX( zak!^cK-2_WsnUYrN=$Zko%>Di(H$Ngp4fm8wH4e8ZOf?R-*e05Q zTcWfe=icA>Hjd4G1B%~A=iYH;EYj9RX(?*B1*!_BakzIKI*!A=mn52idtXX{&OLC> zPi+uxAr!BQf}yt~aPLKAG!2*W4V8fVI7Y{DxRnmk1l%V|W6t3>r8)KZF0kp3E_`*B zfv9gn@md3n-O3&hwbW)aYo$ff@vkk5lWHKtpXai1U*LcF3pM@)oAEaWR~r9<&Dg87 zEKu>A-j2s_{~J*kL2(t%$Gr&|S)=ye;7Ab>1ZpZmG>&TgYY|PL{zu1g)Z)sR9G4wx z|0A!x0Z|u2@uoN!|D|LUjcWYsN>QO2c=cGkl&b|mu{df$gD4p%P`^z|Ej!e<<4)Rv zs7s*u=QtEJNXsZ1wEzQ(mqIPBG>FDsEoels1Zv|r87EM;CZ(1g>Ng#JU5ltop?GHk z3iyv+c_jH2dqHDUhSsRxMu;X*n@}u)+B8AN3Dn0DY+KLOlKh0!vO|rPOt%sB9Vj{6fr7%gj6zTg94RW)l3bH$!qtN) zmOwq&BI5+=VgFB5chHevAnLnNax(5#2dgLq^`In8=S_f;{4mi3>Y)@%pdJ<>;{<9a zS8Cb0x~|8JdlB_LC^flF zf@2IBg`gg7N>QVBr&t2jq*wyAb%JioQ3p%OJC~~G=?b0${9XRukBGV)N-o3+aIB@m zs9#wXv<^#AqxRkp>TwiHpdO#1+j7(krIaP=xX&hSL(~tTWF)%UCZfV<)Z=X_D%9fN z_k-G&VhPlCX}T>(9cfA}y9w~pffFhabp@1MgU8kOihxXjb}<=Rp%xtA5KT;g6DSr( zEx9T|#)-LlwbHUf{b}!4oe=dyC>fiCf|KGhvPLbrK#2;qt}Utg{U7v$sLGVqzE)>LC2&Ftx>NI6HTC66ic9XijZ*vbwXNd*`bDK zO*<4(KZX+gQDs4=l#D`9Emw*f^(LEW0<|;65~y9GWSl^~_y37H^1x$0Mbwp0@+hKq zQBeqL7nzN{-}6raB@<#&L`|TcLa_wusc|w+pgw9yEjw55*}8oMqJ9D;r8!X0O+_K7 zrieeDvP1nY zZk~jwpF_!~1{Cy(%P0i3wh6BD36#p0+XYf@yKaCNQHvO`@q|L+qJ^$RH3h`ZGQ6-A?# zBoj0pKehfu4b-j>J zbQ<+siX~7ZaWYPz{$NNgJJiKbefuS%ehDSGoKV4eDhff3m@>3Rt%(s$On~z#mOvev zAmaq;Zz@T4sN){AMkDGPDA|pu!z>w@pbia7QKNqE5KW+7K(Pesg()&lp#G(jWPyrT z0!P2w`bk7x3(j9DD7YvhBNNmMZ7FKhUmcWH|E zLQsc0QdFqUE{Y{kM^Y?-YFl($@3>mlz?NEesQ0Yvb~&Pc1!YYT)lSGL1a)LmiW+tA zeo#kIEP;A?gl@}Go7hsz4)x`CT^CWmhOz?@_41UALQqHH0RB>_Ww0OAD=3ygy)sI- z<){bRQp*nY;-U^OA?gMwD?rpM6#+rLQbyM2t7W-rAmWP&a5cpesMo~h#;i<^TJZlw zUDM;p>k+jQ%G%;vz_o^qOi-^erKnv!U_YqWQ7nOaeUxs?QQImlJ6C%*uelddtDx*8 zM7_b1kqIi6B3>FbHmp(?aWE+`f4?lS%?~q$jAisMq7#+ zwXKxMMN9oj6vqkFv1vJwZOdJ?{-3B<9Y3T4qSioJS46#8MIoqTV>F$2x>ANGj^c#~ z!qr<|c_IP{&a$fjZtI z;{us89Rl8|px&*p*tUGG_EB1Pt{yV#{b7jeLRo)A zy*n+b2cTHIw>v(YSjK}Tz06R?|E!1qJ9fyLlE^|Lq;a3lT0aU z)b3IuuHHwn1nT_>IZ&ex`G2BrUvlyiMBM~s!y-^H*^-e7>iuCUYSgo&L{J}~SRA!% zC>cy_q zvO~RR?2Ek-bu*M*il~o7WfYBC@Ni6u8g-}|h?+oslwt|g#|^qI->pWtQp*l?;gt=~ zM%3@2>~chXJT9XU)W;ktYSfGOgZc!;5~x!xx-Cc5XKLA@x^qUdUs?PBWmhBW)P#&o zP@hOjQKOF759*T?OQ24V&}}*DRj$;sL*3lA+j>O(5z6kgpj~b^Z zKqVKz+oPT6U=C zCHJ&I)Ssd32}CWA$S4H0Ooi5{llOyKL9qntY&uS$KB3}ehnm-P=Q>2)24znn>I>2R zpw5m-QKM!Y+J&ogD3(Bd(V*M%-Rdb@YT2PSbq;EXsJ}qjvxxd)Tt*?T&UK`yQR5U# zpuSA81nMgm-Ik+1YfCLV)bpPzWM5nS3S|zWzLJnp2|V;2;G*W zI=0lZL(S=M^ z>2lLhHa`anUQ+}F^)(q;A6LtsR|64WOn^5imOxz?mm9M(IqE#6WrwUJo5 zJpl!88ZvTDP9w3DNx?!>iVCZ2)PArQDFlu6dRT6o9ac{5icmMA#QGh|-ikuOvV@F6uohWTRBjdMy;Ebo zO~(nWx8$Z-{`?>^+gqY~CzRn*nFa5}R2bF7ve!~l)L6^HL=$ek7bTj&de4?xc5dDO zRHuRH)*n!|7O|2M8HKp@Zd!^OYpF`7-Flzm3#_$jTy|KuF1qGD#QGD;Hds*bfhh?z zRssH9yfoJGFwult9~wjxSYIclmL1l$CftWuyP&K(0R$Q1!b-Q1uK&>3c>m~Dn*4=_H~44!Y%zJAdVAmedEY+*@Nj0&81RYT02Ovg1uWaiR&V4N0O2tUqE>%MNShVP&@?*1u4;CjteP zj*LRE{xGDdvDPGrCa|haq6w_suGF%_S`&MA6=MAdW&b9ipe8D#5Ueys5GOX3mK><( zR;^7mf%R`#YT04kICItLoSY^(P>#z*6?~(j5UhVvGPHJULxgC;EjLLtj#b{kky>_G zmvxEWfmi_LO`=e+$&gV9*6yejHC8P}6UY=yBx6^LHR*(DA*d4Q3zIkM2Z?KsbzDWuZLabaU z?|@ioQ$`_JhfxG^fcVLh0})kVZFh(!usXz~mL1l4CpPGZSWTe3Qv?cjC}T8M!LKP9 zTD!G_q6(~?E*U4V^lvD$!#cWKYkc!*(iFN0kcEqHpv35p@#<9vCyyYlZ3dLaY{0J|F>w4O21-!8(H?@B>6)PFxN|RDsnvNi=~qAS|`) zux^MwRgPGBP=2lfg}IK5La_QPR_)e*6jfj~HRZ;-i9=Mt?64*txbY~&%7^lyQ7CK{ zm5~WnUnMH6!dy!Z)NbjwWsNmd4$JZk;T9*F;6zSP`0KQ1MW)i^>l z;Z}2VB3iAyag}60@IwR)R0Vz39yHy}1@>YFGQi|DO zIkUp-45ARq?Kl(`xH1aCx`a9-url7hgtHCqApwQ0A~FiW8kvxy#yXUu3alf;WSns82Bl?(wRQOs zHewwD9Vf7Ea^$$|u%0Vwx(Bfih4RTUC_K)TQHWa^ zKY9~bM<(PzbWmWmF^DFx@a#mqvco!K%lY>r)?rXS#f8E)X&HrJ-5QsoZsHLsq6w^a zQKAW~DN4%%tLcyKoM?>giHAe^<6$UlpOlda)=icaHCCG#(FE3s38D$C$5K+u0tZ)VW?HF3wa;9pJsqRkGEaNPrrIL>7nIKkQ?1lx+OsCn&hCNrLitQ7v18KNtzw?$ zN)cBlY;p+x3(B8MQte<*o8@S&o{l}&?RmTy*yKnkf60WxE@2sfIQCpbipsI_XX8}k zjy;p28h7kzgKC~*g(rro#vQAOQjI${J3_TmmsS0OMKs~q9D{1yG5xKsc5H4+j$;~k z?8SuE>gm|L;mwzzV@E;x>q#i=Zpr|}vAMPswPP% zLHVqVaon+a>5O>ZIQ`uyn@>G(D=1$;JGMAZwNjV4 zvm{D1;n>m$)%YA+W=Tyu_Lf04?$}#tt<}@9AJ;wg8#;Cjlz)ZCvA(VhKpb1!}rP>hiZI|ZH!4xJ63B`jXU;DSZnok?Am2> z*^$3Bl>Zcg!t)#%fH<}>Ek*5EjYT!?SXG8Q+_5<^I*vQ`WrAwUT;|03jCkC!%`rNz z)EoD`O*Apbeh5>IJNBa~HSHLln2Q(FxMN#ft<}@9TT`$d9Xl4vcch{4qL>Uo9Q!dY zMeW%4DXMYDHXBsqjwMX0amT77RO60iT>fv$9s4z7+ftV~i$@UgLKflJZ}=DfVj6cW zos^n(Y`a4>?%0l)*6Qh4>#vGR(Xr#8d~X~IN7ym|acsLKMeW#cQL1sreo0V`JGL}Q zHSXBvG}X9cTQcHt$983GTk0~${&L8+!m-^ks&U8m*izGu{T-$ncWkezwR$@CXw9|* z(6Qs8;*c;DUao=?$M&RTRPESqgKFHdT@k8r$JR!v#vS`LPBre>j*NJoV-;Z2aiuOg zR?#3#H11eMLz8NrV-*Lfc*?PggVJ)G+AAv#PHC;4j(u|1xaZNaHc)Yl3x(IH)6*-ECjpL4OH0U_)*k2aaxMP23#N&<~k+E&5%N#o*O|}(|9hssU zckHNy)U;zq$EoJcv5I4&TC1mHO|HFiK04MGDo%(&;f->8{9k!KR&lf`Rqfc3Hr2Re ztsJUx$9_=cY+KK<3P{m$o?{gU+f?I@9iOpnsmmN|6DQ+@V{M~U;yw=^>pl>8GVMLW9^`#vk8T_xH157tX)!y+Of7$V(;?&47TF3 z#TiK`oRE|Oh+~~>DYB}U;lGgFp&FlK9bKw%$95}n?N}R=j^mECcc{i4J2hk5QkUiJ zmLlVXW2Ysk#vSV(mzs9$^eEN1V`oIPR!_%PxMPk($4-EX3!_jNb7TPG*y&2sj-3{k zBGb5Ir^cw}Iablqp&H*Si;`61j-4E)8h5Oxs+#2}b(v$mqGX(KtapTJ+_65E)U;!L z4XSa+E|ik@RYSe5_U!KN;7=TyoCp=R0fm!eDuOL)A9qZ*%jXT!Uq#AeZs4&&I zW8G}3amP+~sm2|O`-|MMo3A2N~#!vqxnlac4?Ao+_904*6KOOPVe#5 zSaj?psJJEpg^$=W0GVT#(jJPva(G-0)N`yPMK$hNTbF9wv0hU0j#=EX3o_zy$3|yt zTZ;dJiYtgm{7L$*ANj&*>Fnq8guLqoY*gj#)9PamOx6P>nk_G9w;$Y)r#vSW! zQjI%yMTBbHv8yxUamU7GY+LFw$HvP|y*<$TBwjHd|H5Bv-f_qDTbOq24o8mDj!led zt)7k*HhS9ECdx!7z*`e zRN~luDH&BecCSG-?$|vMs&U6gM5)Fd8yBY~aP=)(I-`VY!7192tN(_M$08?bsZfYTU8e4%N70QAMsDd)B4nxMR=TRO61# z&)BvUw}OfVaWYOgmWWb~JN8;cYTB{aEvj+H-Y~RQPshfs`*syNb~04FV?yDZF&Th3 z_F7Vk+OdR`yfXyu*!-{***Nal1VyeLdm%>0amQYgk{6FVwj^WQQkOZl)RF@+o^WiL zK{f8!vb5B+V{fIX#vOY*p|yHCHfl}oYv@>KsQ4%eg>Tt10C7x<+OegM9LO~8*kYGz z+_8HVxpr)UNyl-=UU#U*9eY1x+ftV~wme0~3CBK2P>nmbA}%%U*oRT7amPN2Xsw=( zeZH>4P;{&dRJc(nd_OD$5XU}Lns)31HBdYDeoPKz8h7kDhid#dwj@b4?%3O5s&U7v z9jcYO%(0pn(S&0gZK}1x5l~SZmYR0#8F;`0XDd~Sd?fLG=`Y=X*4a%p-GM7Nn#f*bNUh%4mtA;l2(zCG z6x(Z6N|F@sM zpW(_(y7mLq#`VtLb?P{Fr0of_^Re$|s-Qai?1ua4`&lZJ&Yo}Ph*!O{kA8aLX3X9T zX1Bz?hgDFLy@@5GVkR-`db&j8bAEQA((0Xk@WNf}@=|Y@eJJ+5mkL0#XZ*}pWbb3| zoBa?+YW2?k=IX1?!R&otb}Q_AUlo*O&)ZMm`?)fccD|L`xZc@&udZEz+55umqp|O2 ztDq!%;ePtwUuDwSk2Z6}tKQlBzWwj@Dp#n_%_< zFuSJ>Er+R~Bzqeb6*CFvFHo2|dpMnS_T{bqWbd#8VRl~=T3)DvlI-nORGs}|g{iam zNo1XU=gF(~VD>>U`y4!{EmlEE_A`<)s?J{G5>3pybD~nKxAUd;%RMpsV3<7!`+kWE zO0tJzGOEr#!X}!?KFE?`_AOvbMHxQ-zMabx353$ zoac9+OqNLtb(!$k#lfa22lm)-*90T>Tg1QV)cZb6zaH{#h(emFhQ|I8nAIj;l;qtM zU`gV)bLQP-a8_$O>#nvqd)0IpK8wp6nv09Eye}if>R9GQd<|HJ+8tMmmR`sk;DfZ= z>3IA~zxXfj7C%v^qb0VJJ}AtYu)G=nMBJQp!g2s1=Yttx89K&8u#RP@xw`?&nyp7y zq2&#bx5fi$cNsK*S$=I1)Ru$2oH>^KMwWG$v}~b{t!oLM1}r~*tywNw_J>d^o^PW( zda&y9JCmTY47Ch!=2$}BhB)SQ$#1&LChAX|4+s9&#XMX$ZWK;l10nqT@U2(+X&$JH zc_PkN=feSUG2iG_^SzrdZ;!ja5z_9%U01vH7`kfC+o+(k>)5;K&{08Jh)g`n(rOK2 zvCf+saXL(-x~Bot}5SnyU7mwnS;Fz31&PlTLqRUC%!-eIVpT z-H@g~i`409H9SeauD!1`b^5QKq|;m1{QeE5-wb)byCCfYHB_hPeea^FdhZrDlFc79 zXkEh1r`nw}F?|r^{T+q057khXzCB7)b^6C{#$@{6gw)@7Z1kKjwqviVw?N*o2&64l zLs|Ns2#wY0%fgJw^jmFW3GY3p&zo&?e6Pt{PC{#Ssevh*NhB0X)DK`i0)t8Y5(V@w|kc~9Grwkk{mSo*C# zf;#;(rK$JskJ7q?(~Ys6#$o!ckT(UJ|6C1a=?|MURi}RuW=uB!T!dJ{>36%A&BXL! zkoO|)J)(x{^t6=<>hv{kO456u5ha#z`q}OiTVwidkT)CmzE%y@>3M!XP1Wh^xRKoZ zD-l|kaQYWl99)g*CgjZxLfU#Yl%+ps(o~)PwbImke?uLdaQevw5$BbCIOOH|A#H;i z%F<`}|C|1eO48|X2WVZw>As#XPQ~;QkXK|v+P7*bOMk_rse12mue!4NLLaS5I6b{; z1->n8F%t4BJdn1@O#@i^8yeY4WkdoTCWx`fj&=``pdrr!>E?--D_MGa-?ZyPjK zr+=?Bb^0R35>D?px#mwyzXS5D6iC~u2C(!(3Xgs3G4|dj?FXf)(?4+0!i3Xb+!OnD z^qr8m+=jFt)lilmwrQ%~`!=Pi)0ahQUBc<5>*hpo?{`7oXBMPwS3_BPtwmFH`i?MT z@~m5pgTyW2^uhgyRAc(x5IPq3zEcfl>F)<=s!sn|X{x=4j`h*Hgwsc^eAM~0KEU)*5K1>8ZBLkjSh{olC~i7Es*?2H z+eB$yW7h|#pV#k1e9ONZLK*mm>H!xW_dl->^mVYmvZ1S@lP6wPj=Q-R(tb;U&NnGZ zeeD)_k0>m0SM+%p2c^*UeKub@{Kp_FcQ{;S|7V9^xaZ@AIsAs%4esz?ljiXq>TI#Y z7H*w_-*=3=4?C=m)?&(DNPiQbtk@2ls{61FxZ_g9XGnFa*kPL{K3Xew*!)nC?!)GX zgYnq|vr6B^?0t~_R(!k7bavA)&5P|&X7kSkaDvQkUN`%9qrvP>dzzH6c1t&F>7qfqd^iqFA*>zH6_VK>@_U)>> z?|ltthcb+G%svF^;YdT-by8$@YqdkZ?=)p3_x)$X_jhR8iaD752c%aT4Q1C!k=bq3 z4taKZl-i)|hW9;cdFzug`!J+e`x?rwlOnS->)m&jGLqT*8{YR#S3TYmv;TzjTC1V# zIw>-{t=b{qceXO3?1uMUzWd+fG5aq_U)k0fhl|8=eq{wU|-biM543nqa_ko5x|LjTU-@1T*ApQLYpIhpr$n2A% zl)^jjp{A{dH$Ng4zE<`iChE?YmBj%sxf!kY{&RMlyR}!`YD;9sIG+z0*JT zHk4f_MP{F>cF40&^VQk+p@#48l`sD~)Op(h>C1u*W!FiO*{9dL?=H$n?)&$K_kDa% z1218lG=cO_q77x&Ns-xSsvYuucU49*`>%%gJuj=r>6qOV(pP#K%C3_lv(JiByF9yF z-F@R58TtP2Kkpq*nf+4;vztNs>Oe!;by8$@ceO*FeYP@k_MHNk@5Oz`z7Z(i{NjI$ z?_ONlGEnK8d_KORzaK)q1CaiuveuVGoreVV2IZUHP!|tpwKk@7zSYHRbwX}{k1;7X&`Yc_xw0PD_C~pfAvDB* z^dF*h9FrTMn3n5j5!7;n)WHrDa<@d-Iw?0eOsp}v{>_eFiE@uX=r%v3Z+FpgOzsww zpq9JV;H=hm?$%qqoC&#MZpNhCZ7QTOxmTu3_^E%ApI9F9mnKG7zA~518mM}@xLH+Ck_%f zeYf5jWlYN56(QD`+*OBua-QeLLTGdl(xW~)j>+BWC#dBHdpN7L9l25JU@dpAm#vd> zqusrFA>jPoNq?}KMG$yz1 z{??zM+;|8*>x1-zY8I1wz{3LMIX9A!`nVB7lj7D1xn~Soh#Qk~&k~A#1Nncww)X5X zW(vwZ4xyykQSK=Sz3zpK=3Y9E$-UwxsO6?aIjgmubM94xGa>gH zA?L1^a zYfSFC4eht1+|v-sb3sNc<-z3UMroLqdnwGBkbBeSOvt@uF(&2S4ialj?# zgbI9+alFc8a&LKQn3kLE;!McpdpHwv3k=4jTmhj*pXYoVy$_+>BnTBpAft6e9jJb) zFq9uAsO4VsaVF#ngPaMuB0pnNuGl2jSaavz{gI7w&p@c$4H^2gFxFg=i-u{rc@fTp zTp1zuJXeOp#SM>@a$$>DV{(IgedgS)&qAm=02ytS2a_xF(J(Fdwwp5{S7~x4nyd0K zCgrLPVvgMZ{tJAm@0#LA?^3thTSwe)q3UD^t%^d%4MCa`Q_VGI2`r+VX>>XoQE1w!jl^=8bZ8~zZfXf^C5q*Ox-0*p!3 zTTI5J>R>-(Qg!_is`mNu)IO*>6++*lDi*A6q?$2UjaI4|13k1(w>s3%m{h%$GpYKm znwMOwD+1%%q3SdUZ9&yx2Bql}AS3RR6mhPG)&*&yR=tfgscLd2Rks|W>T4^HpNOi@ zL+D3T9qu6mrfRwgs#Zhaa0Ph+jIh``sXCIcld3-+q3XJAdw)mO=@8n9s<)ez##Bev zqq>V#Q;4nx%!A#?~;@3Yis=XE~zWR)>GKv1cMehD%rRpTzoq-xx|cd2^l2vyq^ zuEL$S2tep>RQ1_ppj*v|yYQ6H0DJ3E9b?kLxFxCjkcTm;`u7p4w!Li0PE>sf@|&RQ z!!#Jbs#eEDi0W2<4>BfOeZdTOi@8L5ZGiWkXeI!ay ztK#SK@`g;Rj^#|Mj`Op1Qnkeqs0bgh^>kb%L9qQVs3k3bNHFZMIIT`U&Z0fc%aI z!Q@mIpMKWusQL=zcScpepQdQl{N_P|N;Ur&&ZO!@TE?DNC)xy^V`I;&`JD}7$*Ha% zJo*k)oelYCpz5R`P0^|u6MY1=su5;Psy=HlCR?3Mh_!l#T9=&a(DzR}6IF8|-;Ju1 zEj3y{13Vibs8vs?M|Fyat&^%#4aQ`vZpD&QJ*n&b5US3B{Buxss!fwwt5dj^cwWsv zoio|$^ClgPTav2NJ&Z}!a|~k1sorq^E(=v(h5QRp^#vM&U)A&K^AVz|)r@<5j7ilQ ze#WHgi$TVu>IDX|7glFHREL$LDg#h`SqyIve-J=>MKFUr0Qh`vE)>@xSO4d zs&7F4H5O#dHfah|eZ@^stM;x(HP>eAr0N`tF{yfumsoPDd4VPUQFSil-+-#G`e_PN zoufu;)l2J9eO(=^Pk`5Lg3htxdG!W0FFDon_d9k*)p?MQ-@MCsBS@2(>gzs&N;Tst z6^BfotMd%DPPRJV&6rdjsE$oewI;k8-@Uh(5BWn-b-qQDnd&?Rwd#y0E!3)SdKiUN2oeDV-|j9*WxY6$G^Om zvCyE&tknVqwdw$y7V1_DgNzB){Bcpnr0VzxvER_8O*=mW!m~6E)$e2`p>PS@alfXawT{#F<^C16OR4p@UGE*&e6V$4=*^EimFlSP= z++ypb>N7{8ik}32H6fCRsv*dqhN=~Qn#@$oy#%%D?KWdlwTcjXzgq1g=o~AaSEnAK zYW2Hk_d?Zt$j4s+mr)(0$xO9ML9II8q=m?&YOTSTY;_SK_I`E75vu+X`Fc01E`a=5 zsJh5fqxCzh+5kbV`jp9-R9)<0OsX#NGA3J{d4#HK?5i(9)dI+W6;+qmG?}%!SV67& zj7bZ1tM73pRp0lpby9WC5vqPv{Bsah7ef9#RQ-Sk<5%^(`korCRi~P?Qma~i#-!?p ze4SLCtL7#5WOeTNclV%bA>_Y}svjAY##F5+L9IH2E65Yz;~-lnRhNbtld5kWq3SnR zWE7!l5#$%3>M{>aW~xgS)T%R0TBuuHZZRfRKT%rFvEmtEfnv$E`eDWs8&I_v@=H*4 zg-K~l^%DiP>Kx8wtDo9*Fs_rTD=o&PYVi@Oe)-Rs^{83``S`a)GgkR&GE-gYC8$;B znv6-+&j_*S)z4i7b*tq^s5yy*Q1#;8&%cbSWstwx3mIQpYP5a^hy(~~)dePFQgy9|F{!%F%a}X?R@uaoJ68wg zeex2jh9Un;R9&a0uvXV9s8x$iiqoxr#hFz7+QZgK)rd_jIn^`YuUL$#<&ggss^TL| z-PH5ySLzPas^uoF)2iS28I!8t#@!?08DPCl>ylF)>UsBPRIPyg?@;wSgQl=nzg1AH z)|j+Vt8NT3CRI0u8I!GkYZFUO^_Dd^Peav8$hT2-vxlZI)lCX&)m1)Ps8zREj7e2H z$e2{!ViQYFwRs=+^{83}`9GoR_a;qYsSGU;&onythx>K>_R7Xxb35T_)f&5=l zb$gH|vsSlpE%}+%x17l*tDOcNj9Ri){o|urb&pN!l2e_zyXRz zg1Xf$^{DRl(7{^u7lSd`>OPxTa;o=v2F^j%MUekb3S|7ErZClCBQ#p89*#05TFw8H zuM@52{}pEIr0U-RV#%qV)GBWYs=fmYjYXwDUc>Vg(ZLAAOd z)yI#GovRCuR`ZfmO`H7Zji|a97Np||u-~A`O!Z(~T)K(h(p}KnLkm$$s-_u?iB=c1 zA*9~}ENEjBOip#lo$KbJ>JnJc(GMBFduR$%{Ubn7x7va0OVty-Y@Jj!+>D76U_nP0 zvE)?8o&LfdsQNA}I1}Gl9X4qSQ;k30M60KB1*v+5QqU*B8BrSOY*U;7T_VJiQ|&t@ z>oin-4;J9Ric2#hoa)=}-d~HVAHag)CS*3XXfji6 z?jopFhj|&3s<*irld5LivEl?UqqHtL)$96vIUZFlSb+a*U1oEerZCl`xq^7LS}@8> z3-t+bFJC8BN4wZM+3M&hvE)=cjwzgksvp9FaRy|zq#^i~o>wzlaV@F(C|8iJKB^Q@ zU#dP9p^45tB3d0ACYGG)j5{B{3{^jZ1(W=c>GIMP{ZCb7w)POz4L+?FYORTGwoYnI zauG{TtI2V*7NXY2u;2yM($CmTD_xD&TF)C4r?sXNVo&YUZGy>Z6}^0VFVtEJ3v#27 znI5GnOe<53)>^Mvv`}l!4l*X&%JmaVPRm<(dp zV34hoT5tM^C8u>wuODZl)^b=-9DvO108L?9?bT?lRcO*etySb_c2C?L{F6??&E^4iS1s0xL9o;mAX`QS_ zYpwTHty=2?A03QLYFTPa$!QHc@46b)`Vm26sI}JCqqVLct#wDJb#niW>8P~|7T76} zd0LPRnARBqf?8`+gfZFH<}hQjtu5-<gFb>wRWh5$V6KOOVmkJbg6YL*Oywy9ii44k&E9!tuLUUtrs$T*h)b^ z5_?7nYORbYV^S-VuajC?VOp15TlYMCZ6DN%K*7m=$UIj~VQrlsq|sWdqrsTeI*E{e zsV+FlCYYSou3o=?hgx4k!I}7UdV!y&Fs)ubf?Degi!rIyCCHd;>r6kfl}+Qsns*cnAAGgPb@jD>CZge4z<=oK_7fN^%yjTY4vdt z)LI^sF{yQlhcT(u#~_xRR>tH_T~TWt6yVSQWcG>D6sC2VO;BrHWilqUuJ$k{wXQLU zC8ss%yb()LYdsVU#B=L%i>5HGzF~q|OJAfRlUf6OY@O6P(jS)jaOsMVQR^!xa4zQh z1!ywUy2?*bYt?h%R#4A{TfvcDxaD~M+K*aaL&3dxZe4AX0n@tHOHgaw<7P~@HOj@9 zY-?1MSaNrwd+>PYdU694JemTT*Qqq7^^X$OT2IuY^<+I-PaUDwtakVRjauJA!L%S`-l)=;)&T3jT2p+C z$+o6?8Ix^Ia}!Ihtp^5Ocp_?j2L-btkU20&Q<&DE072c>%k^l@tVe6s5o&$&(MadL z{6;94?}5x)R2tJ7V*Xcau8T3**4!v#vaNX$V#&32=)6@Ipw=cRSQv)Pp&pvTw1&9} z>b4g68IxKCCSy`-p@&#hEez;9jnAXS$LEY9W&ZO4rFk2_JKC_4=r}f}f2fCq_4FwzU zl)qg~W?FX!X|&e*%Ey@0`r6Bw)Y{-CmYmkmt>;Hj>w75pAq6t;^3xQibq`mNZ<_5O zEksqR^}RY+--%mIT9=&G_Y-#BiCSBs;1?fc>JI~%)@Ton)@}XFnbg{CuywMnUkIsR zMbPj+T&w;nF8)+o$*x09QR@dN_#Mx!`_yEn^?-|JYpnww#-!Fkb+B&hcUqRD*78~1 zPDZUCVIknT^*~gO(Jwv^+61-Mzx<9BS_@OWY@KLpA-IVpcP9>BK4ma!{R9hJc_4F) zMN?Q?aWBE*+*;VuMGH|?YPF0qCbf=<5KB($k8O_~jau7aVFo^(>KA;b^_ZVVtF{)l z;Y?~d-&YYgbtf*&@DNK*>)Gp0$0J*8hlL#t$Q*0Z6s9%aOHgZd;LS*_6IC->%Lvo4 z$!YyIF>(mCcEG|jypZ|0o2D?WCk%pG>(qL*POC@j^dr=I@0n-kq1H}Vi2qh|=946V zU)B4qr?`SVx6bCOvaPre1?0Ka!={Nzw3WKuzIcC^O{ldC7G4~MOuyPN)0$|}Xx-LD zoJpQv1csKL}U6CNw~3%fBm{08`}d5=izh2%WfLV8k=bo)Q!!uI1`P%668!Y zHrvmcXw3N&af{8fohIgZB#NDPqOn&E&O~Fc5pvea#$K}t>c(ETi0Q`Oh-0F$xr`G*%ShOf*&;cdTfvB*52+bF9?InP{xc z%UQ1NG#hp^CL1evaVE~O3dM9|l^$BBAC*-;%@Stv##m1traFq?2`l^pLHq)f3 zy0H%$r}Z?JHy1(|P0XaH;MYn7xM+n^RYOf>dQm=1QBXzbenXQHw1 ze4L5KHhMV|jcsysmTNnWZFVsx8`~V^OfSwlN`JtPjZtPc+GtpSo!vVxN3#SUmG95_`)6!y9~2s4$ShMs z^*L6UuApkHFvCYl4vRHbnCay#)>vVdo3mJBg>7A&#m=$9wo%SvjTN?waF%O3jb(=! zla1vBIE$TQh3ys7jdieSox?<9Cq^|(u(7*3wY?1++Yg23nvhxTqXD|Hg?ns*y0J68 zoQcM|x;Yb#o#o<8G>w20j*m+H zl*JnBM?=N)j_H^W_7T*N${}9PL}NqUoQcM6RpzmKz;@={8s+OmW5Xhx<;K?C7G_K~ zW(GJDjSW{!H#Wkeb^1{`GOAgEjXi(W)4Q>;-=Xk%12XlCH*2g5w-i@Ng%5fuNjEme z&6#NIAs1(&v4^6ZiF54X2xp?PN5Y)t+D@~N1{jl#J?7&~G&aQ~rW>2;;Y^%k(+tfL zY;5DSeqUf?hoJB+KV+_s(g4=j9L4mba*j<(8BiRZDfi!;$!ILeu5tUSV*Xsja4nP{vsz*(;CoMTl!#$;pFUd}{gHEv?MvD!E$ z8e3%QbqO~1Nbw5iD(Ns3ei4Dp4PhF<8guq8Zo08$7H6WdfuZ@w$k7%*LE6PMMz&)7OuiS5jXUc@5fdvrWiUT zh1>ADa&v$Nu*SY~6V#1uR7nmKjcttbb)vCN5zd@_K;h;vXQHt!0nS8YwvV&i*s`;_5(byk~sm6+qQOBxt ztmqiFF2TlL?mX-QZ0v6+IynHDySx;x8!O7P2&%@4+6Fm`HCE)fikq`8)>u)t$yuzi zq8txrv2(1by}?qK zQO-nTJtCat+D;Sagc*~K^$c((8ar1p-Pn0?Of+`BMaL%mp1*iv)Ol3?3q?2JYvn-~ z4bY7hUEw9D8|&-lOf=R{9qg7khrwB{?KE~LA^loebSM6axS^kTtt`6BmIyz^k)QJy-Q(g+ zG&ahkS%Qt#SgGT&F@U0{!;l3L8o(MmOF`Y(V?kQzFwxjpKWCz`aVBS?vGE?xL}QN| zoQcLJ5Ms|`6KsM`JH6dbi%(dbiF52p#dKp&#WB&CKT5|Y{HPrD#v`|2V@;r_zzta~ z!Zd(2_JW_FZfv|-$QpC;b)qqU+_9oD)5F(^#^(7r6OGNcILo!2cHVR|CL4Pz$eCy? zPr2yELVjB3FwxioH80`Dn&1BAN7z_XDEhz$S;q!wC~K@LNKiLc?dMFKW6nOs%~>ZJ ztMzau8e3#=CK`K(Q0#mXjlE+NjLpOUf}+J1W3sU&LC!>D@A`@9#@>r#qOteGdR>B# z${CBM7h+@0py(?DveJAsfHn4*V!E-_E`kmdjp>V0-PmUlzD_juxw4GSvz;cs2=H~H zv51ee+}OG=y^P7m*0?znjjdHoH?}U0iN@BObZo-sSohT@;(Pwoqo8QFAF|piA=X&j zPYj9AE{e9QB;D8#9!l4Z{b+C|8vBV*?0gdE*iSY==UCC$HjA@d+i7-tkTKcV4nJq2 zv7II{-Po=GXQHv6EzO!hi|0-C8}j}Rro{bb-#NYBZ;Rg%p9e*UjJV&B*Ajp2vH0Bq z?05KLD*gt;=KtVty%WFiuKC|a{Jb|?J-hB7f`mYU`-U^C)Ve`-VX#h)~>LaMr zFYq!Z(=Sx(5>DR~z2{s^KNgBF!{(>aO#G_${(O|EPQTQ{m`uOSAeL}?w=uISF#R|v zz83dB-A@Bp`V6%voqlzI79x}B*Qj*~r#~2e<9JLz9*PIx-e07d_*LyaP|x0Pa?whi zev?|4aC*yDV>2<`1;xW~?=SgjC`+HI_N4bdG(Zb=`mJhR!s+)#<}AbX6QKAm7i7(% znfO)h{S~z*oqmU(R_gRSO=1bBH?xBCFugStKM;Vd*=i_DpQHAq)9;H=l1{%rOf2E_ z+HG(Ai|J`lJQnxvn0c`JY`3UOtfQK=e{*pl~;q6ktqRM%FZwJMdxc5Ro4PfcTYN}4JaM41YUJ)gh zaQcPKPxubgv!VFi0A!WW@%UBky;M!r=}Xi?oxa2-m~eV|Ro3sAo&&|pT#!}frvWUz zyq>*(?4^Y|eW{yR!s(B<{^3+iZx6+v;okAZR^8OzE9=?&stB#q>8r!U5>78E-2E}8 zcYxxraPL)q8o>5m<0Gh>U*}~^p7ZP7#1c+_s%LEtrk@DKn{n^8bUc1ldtVeKs?#?{ z7?bIn!o*_fWBn=3n!=E*AWUfQ5?4=;T^wwha$t`QcTK>{s6KP-+rRxK71IqU{=tN- zcl)jv?(3U0ls=X`Al5SC2=&+b&NjE=d!g8mVF=@FtLadHu zsJXiV%NO!fhoj|5P|`05Ssz$5fLUIprfSRXCM_gO`ful}!yHR~LnbVX{|OSWYYCnP zEStZ!dl*`t48?o!9$)UF0otwcd zjEP5CNmn1SSm#X>xMp86rpMWsehL)-;f1zoDoCfdO}A;PN-zH1&zO9S9|{snIDP$9 zottBNXDI0(hPD|>pQUG+G*zXSc$FqHx%V3)v@YTFS38`)2Gjo!N`|B{h@xXw_*CJP%;wto~?$m^!6rA)#<~PrcNIbp>+wT?8dDH1lY+?zgcd~-FWBTb(a*Pdajr#U}l1Wo_dP{>bdA}b+ zNc~m4Mn9+ef8JOnKV_WXB&*k^c+Ho?|u60CeAyGGoj=Z-24C4xA)U*8mrS!4l*XwJNbzvy!S5o zzdeZQU7_R=FSI?qzP)!bX{t_t$YM;UKO7{MaQd$+pXi9`XF90f>lj*a= z#1c*)-*U<4n0_{tgz=p38KnU%{XCnXPA}z5rk7c?F5&bm7oGDYruTr7Mfi9>zrMX+ zXwp=jUTZKW(-#p+{P7-5Iq@h=KL<)aia^^7>)ZQ9HjUNkAG#Qm=^v_t6W;rfXQrNr z={=!j72fZ?>)X4>WJ&V9&8GpzWco^VaKh<>zWRJMrk@KXYjN)$rO)p7J~m5|>1$k! z$@Deq;DpoPXx4W!rk@8T8*%TKDt(rIxyh1b`nLhbWcqjN;DpnkXlH$b>E}bqkGS{C zl|D=FYqKPou78jY&jp$OgE~0j^zFMY8-eK;K*=w-_kK#BrC(+KH~r@TV={fWIym8U z^R;^)!}JTG(hcADe*-0ly^yt1&;MW7 z2V>QBu)ngQtD^fa_~{SaO)qGBtq(dEtHJuJsN`>xnTzY-w%4fMoJVynJIq<@um-P+ zO3yN!HO`GXZ}?wj;NOzm{MNAMsCp5Uws1q|uv^S<{+IqPc;|9esCu#~ZRVkc$i%lK zOOG-c6L&^wb3d`_VDba_9#kG_M>)nRCRy`knc zaXz7meMZvu2AzU`EI%b_d!tvab*Q*zZ+jEliSy0v7PqPF7Q^dgfAMHKzJ+hH5!xNV z7gd&xkg^9v>Pyktc$Eye_&t^KpB+L*+p}=sCTNG>lIJOGhc~<8QsntR$d03Ohl5R` z;@kHvhO6xV?C`3szhz?fW@z_^KQ5c?a7d8m;q|`iQD=)Cws7kdcby*3>ydva4%`Cm z{*1p5o9g>;s2!IgcUXtY9S$>St=M66yey|5P&gcnKYzyedLbIF#D1285d&q_mG|9Ybd);ip(BqQVQ?<_8?K2{YS(5 z-VoS(9cFKZ>}IZpvPYUUkMH{qJC4eI-=)@4cEkJrx`{Obvwwi>=D~)t>!iqi-yN(k z`yQL9%s$+3cF*v+`25r4N61bMG?ZN@MP}b?PzvvSv`JKE?`t^wjJ;8O)^73>WFH;> zNM`3+ofMgUpG_$|`vHTf%>J|C`@7TUubqk6+aSB8-O#@4q{wWaNhv)0!5~q}Zg}78 z4>!e2-X_~2``89MuahFP$Jms@vmZ8z%Iy6O@B2{q^D{7e2V|cRX=vYdQe^fcK}zA- zkJ>~jyWxFbbkf=)%-#vv&W9}ZKevoEXkIKuW{)%DsCBa>;nyVp0)S4(=hvI$j)r={;rcEv!4u73eSGZCQAEmIQy5) z?T*Im-H_eZYG~heQe^hiCZ+J~i9w<=dtbxZEeD`6AI@a$&| zqB8qX!}s?wMxPfjdkyBDi6Cx`$=x^j3tX7m2TJ=HkbSn7 zj$?9{h6(ECE(>s0Ydd%0AE4uy+?^hRy1Bay&T4H( z?ruWrGXiAzC*r2hxqB>Pjmb?Ib^J_}yBta%_CR*8FdfI_9*7Xsaz3@tVM6Y~0ADAX z8{=b4HusQP*O=Tt`SVUhxhtUbNk3#?9HCiEZoC?%d(uTA zjmhmeF4K9m_Jz`^*j%3|9mnMK%cPc@tk&t~CffuZCYpQBVoWwSB}l9>xflDb{{`jx zL20fFvae8^VsbAlV=Xr`LIGNCR+uv(_ey{TGyD|aizVS@4;OKrNv&zzDCVwas@m<$}Lm@ zS}y))&O~#C5fagIMPXu%$!+ZV%X*Z%8cJ&-kbS+6j$?8aYM3J;UcM>=v{1`cse>IR z3K)Gw6^h0c}zsh8C@2O#0?tK>pXu0>JoC&!PB8*8nD@?30 zxjtQQEk?O(p>!2CH$WZ719mHt#T7Zg-T@R%;HaA4gXL1|W zFfF$!Kml5AvyU?&x5dktl(XH$8k1|@b^I8V^Frz2C}iK}qT`s{b~Q}P?NAG~+@Sy+ z>@XqshmSESci2m;F}dO0ADV)4H$Yi)e1#a{rsK3+8AJ&xxw0k^&T4IZ;V)|%<}4;x z)-1r7kSjYXNUSlrE62?I1LgWdnahUkJG^uplWS!W)N;oLITLcn`8gAE$D52vIhTi6 zV{$bcvwuLj8=)*4U-<9#(Q!;J(tXJ3hO zH$hov1G4W8&~Z%eB*nDcNh-i$LhfXX7CKDGbqX>jz>k=fW<<9hTCgi%BoC&$JJd8;>w?V8ixi9ZddluyeLfM5u$bK+F$1%Bc{RFk# zc_wEoU98%b55MTG^#IT-=;vJKN4<{IUo!r^o;OcMX*){>{FfW12g!9)qCF zYeII3pQglG%{6gWcA1Z$R*kHgE86aP(sO^0NCoKuYL72st$&-yHT~$Qe)H!kX_>< zs8#Q9GbUB<!+n6{-$_vWM{msIh4ZYxNzjCC}9dy|fVZ zrRo^IPO3iSV(Vn94@HS3r#iXcshv@ED3nb$AbT+l!LRhoL$lxIT2gfqSCFcclmhBY z)p~v&tL)h@r6i|1(%gzq9;vrN*<0A^dj?Hmsvr0W>J#8a4`Wg_U@#_CUn1nZ2FX_6 zR9i|;HT>7vK~x%0Vvy?dhm` z8yF2pKe6OgPp|m>8B`q(WnZG|r)n}&U8P#ks-N2w zr(6BPVoa(=f{aPkFa5-lQw^qkA3)U+P_`ML0ajZyg{gkwBB)ir<4m^t9p92v-5BA= zis#i$VPeUtrrkYkKdO#|vYlbb{=%jyOm&T$pjO=$WK61V_cJC{cbJUHR(E=cC8yeE zL+>r9dOMUIupxUb4Z*MKd3C*)s8-#}+mfpLR9m=Cs_qZ)V@0b6e8iGd&6%<75>&kd z!hla!Ul}xosculCwdy}6Ekq_&|Mf5?RKqC-W1`hC5K8jNs{if3eT1raLikuz{l=rl z=vKdrYbM>qcTwS%_`l+&RKv%37?Y~4492ADv4oOTy&`(y*Qk0Igxdxod!wnwXw}VO zf~wVU2GuVkByxG;kIsK$(;a)=3H_qs@@IZQ{0ff#ZOb%3GjV{pjJJ} zU`(o>Ovrf=m8vJ(1f64rYA1_Wa;j$^>eU@p?}2bPe6`vdq$y1G$0$Lq+LgB@RnJmw zX;rt2A1hSdYF=`xnM>Q^k*T8~+$##%KUp-Hsm6WkA>LVq&$nqIYDv`#)WKTy!XR5G zTkYj1mYnJ(+veeEo_a5Y2YDfThfPzM>d(9_sd~9us8qAJd+1=TIxxbRRJ}P&EIHLa z8KEmsbu@(Uz;kss4Z*MKd3BGMC@M(R5e8$j)sckQxjND&=o~9ffZHu%$*KDL?Q4yy z_d(c)C%~@;O<}6P`3P#&`)tOf>irgD@?rHrkTI$1^Ak%>b;GtZ+N0|I5PkyR1LzkL zruw@@qqXXI7h_U&e3UV%`gnvfsX8G{EIHM}UXz`V$sU04lrUuL&j^|7VVg#4)n|i@ zN!7`I#-!?VCSy`{iicQos^@lE_baOUAUq3I|5O`hs{hdB*hPnUwR$N?5cQ?%%YMeB z>P(X{sXEI;EIHLDpZxk1RDBS_L43RNkGj9KY7Q7QTDLk^E!3*>)IO0()%gK_taw-j zeZ-Pet$FgLZKyg1!o@zwfhbL3s?9tEwdz8XG1+P%Unf>^(TWdsfrIzdDE)fY{sPO zc8geYs^@?H@?lgR3+2u51ZWecDNHp}F|GO=Z%eA~Rc&e2eJ(oKIaWMb?TZpiPIX+5 z8=Rl!7zgDp6LK;mG=-_QGYBfx@?*V>3DxrB+>D8HwfuM&V?wq3_$aaDREu{l$wt-j zP@WTjoOWsoQ*G~|(OR{wpE0T0&SXrgW_uWusyPO+f=y;Dynu+B`{UP zq|sXS6hC89wKHEQRsYY!)=AY<4Pwcunj;?AiK-KzyoUif9o;mAsh;d7s8zeEJt32- z-PB!zOsaN|@MB}=YWdk=V#%p)ZGHZgsQLtyd%Td-$xBn1YUdz9t$LA%F{#?yU`(oB zOepqNN2p$G6HHF^_2$#BN7W~x{2CYJ{GX4eFxAs6f?5@~CvUpdD{aQ4>QxqF@&vd# zNGv&3tIwJ2WSdY?P3$ussji)ZOK*#@O4skphXLvV@0bs2Z<%8I=pvp zoR;c`^4n4M%rH%1s&2)!>Tu4a>TsJNu9K=GEXJhj$RM%gR2Op!&H0uX|z@ia3)n>GTAz*`m%>HsXEgjmYnL+ zS&vRY)n}o6KB`{ir72AH;vhk-`i7q|sXEtWOsdZFFeX*!8^n@Rec^(WXQS$5C|_(r zj>kt+m}(!3pjIt#F(y?DqKrw^cho@VSn*`F*h}k@Q>}dRla{FZ9F%|JhMY?SG=-^N zZWGk1OAW@P>M}z5f~9Yw}>UDS`+9}iKf#)oD=vGpgzzo?xoiduX&)-NBhu-D$9OQgs(0rn<`}n4D_=@%_4? z>hn;3(1skZi>5Hu{w6`Kx=+=wPk{Ylwoa-Z2rwoeRtJ5=l2aYqxyN)=oemXEU66C5 zo2D?;0e*r?wSowKw}sBtiWHkDGND=l7GpxSqDhcga;i^{PwR@RFF?g{5y%R&B-CN!4ThY@Jj+&Lozcs!fO1KVwo=UxOv5`qQA3oXfx$p`tUY4h_&`raH_fs8vt47?Y}iHXP zI2l!6f{NY&$Qco#$xQVQgP>Nu(9f7`wU^15RK3WLXF|nIVaT~h-Cz2j zs>s3jv+}0z?EZenq}GilW3s`UJj9aIDi79nLakX)alapO?zL$O)4DH0P-_kKGA6Y~ z^L0||zA&vzPAlWB-WyTt6{r~JgPi--6sF}1(rB&qn1?Z`HP&EEYKb~nZ7*GgTDed$!v#4Hd({}N z^{9uS)_UG%OlnQH7?WBr1c@bgCmvka0e6%-2P)=xAm=fIrm#D4oQt5=dc|f;YR$G7 zlUlh!V##UkU%L5i)Or;v-okThT$H9Tt;cPGS}Vv^rB+ZKjO(PCRS(|X!ZqqSC5 zJzCZ3VBJ>D5o$fYvfw(@dIKsx#OJMvCK)iTXS@Wp)(4!)wk$VWC)@haMJ&0tDl&TI zqt;xgSQUnxXVqk;r9VZ`TA$XVwNf3d+gf#mTDw~2K7d;Dpkh6qTT^In_?7c=o{!{9^=5+>qN>!|LP%c% zRcx^dCa2XoYtHMa6@-dicy8%uKc@9!fJW=Kb{LFFt(}CJ)=ryXa#~9YXPt>!Z$ia> zJhuWqn!>bRHVJC2y35@=o0EB9@$1^|aCpQ0pzI_}74(nI4+Lv|izH@=p9K zN(=R!_;-Xcsr65oSaMoD`rp+Bwcduxqw(CD?V>46YmQ>7t;**A)v9dqU#-g2BhXe2vG6wkq}aI8|Gft$lPbGSOCLnwMB|ZRMwWvQR4om1m;X z>uPhXt+_!Ot=q~DFec8e$}TR(q*j+GvE;PUGm7xLXQ}y6d7ck)=J{y~)6zehp|yH) z1*z3jDd@J&jnKg4w7wj1%r4Yg0F`}g$a&LCQ<&D<9)eoS6J|_mT@qkSw$;Z+EIF-} zW0pIY7zI#ytqXGU44T5U@?8YA)>ZXrU0sjXHAkqmYx-|JP-`Jn-t32*{3sbPtpb~% z)*9etOtv-9&6sTKW*4#K+B)|36NaN!Ayf{>r_+TNO<`I^VS-xgwtBS8dbEZgp;jPg zs`E)v5mb&gAg4G$2288ePf%;!6J<=cH7dfGZ0p`IvE;9~2f)(h&`2^3xQi^_h>L*4oUO)Y{@@>!jAN5n{<{^>7~?fLgUs`KK3hK39{OR>VW2wbmg& zV^Zr6lQF4vSm`IHRo$t>`>3@Ds*bWC=SzboGp)5Qf=a8ZX@D`IRn<%>s5`OhC@-x` zPHX#=kMIgV^&O}>J_3oK+ZP-GGJQY`3Y*RlT5~> z*2x~mq*f<`SQ1+JBd+g!b;9$g^)6I(#dB+;NmH2CW_3qstuAUIGO2Z@hYm(2wYnO_ z9Ie!9Gwyc)_k9unmEbF0jzZsI7Qhv+261td7pBa_cW$ZgK~*0#+Tx}G`j<^t^|T2( zMvF}xU3IR-S(WXu^Mah^nhrbP&)I6*VHe<^h+Ax)?XU|y62-oITVpz`m%&-C?XZgo zIqSqPo36SD|3usz*3R#&>upPfpSeSe4E!&s^0+ulkFiTE%@S;^=Si=BijBPwRYPpZ z`AH3Bja?t4sk$+*pEJ?e4JK!zvHl*;L}ND^oGrGU-P}ZoH8#*k(8t-IOFm~3p2 zn={eaEiPiZv0I{?iN=N)nkCrS%9)kKDTW4@49+m3}#hMU}t+xp}$BM?jvN#jx*w;bML}MHLoQcN1 zF&UGMee2;&H1?fAOgFYMj)}%LdG)#k8~b4QhCi{frBHPs1=^>o0j#liEt;wu(=QPY z6OH{G;p;?WyThD`#(oKKCK}u0<4iR6tCzD}+d0RgZpLI|zqvRQjqO!TH?}X1iN^MO z=-7nckDVU**?Hr-463tDXn&j%(v4N8L};pNtQx|c#Tu(_65uS>Sank$XR*ern|V2l zHCBC;o3mJB)y-X;<=WU-b@M1=qOs~05zb&p7ca}Z0r-LzS0ft+eX#Ylva@XneE)K zz1;+LV;8F=hl$26RtGywoMWB{KUOq$NtiRySf2oAqOnVToaNe%%Vl21WMh}RITMXt z;UcCR>+9i6G}h0j8A>N|mGp%5X)!jo0;+Gbq5X*w8obz=j=e4S|Q z<^X4+u|Yo0L}RyjITMWyc5{|%JBd@n={dv&&8Q&%opV>*LE6v zFv6H@Y)qIl(bz))V!E-1J&T?@DR8I*qCL5dT=S(yT|3x%9&`aD8iX&tT@b>ILAr? zoQcLteVpamPGeaCG6(+57m}smrpjm?F*c;nUITssS4b>|xXn(E} zVvUv3P;pLRE>y>TbT6OzKg2%~H>X9>*he0TV#kWcJ~lWLjV&bmj!~cTn zWfo(yvE@O|L}Q;QrW;!kp>?{km4p(%5}y%Vdo(uo8B~AogZ3AxyM{G3(WbGEdF(2w z`fHOj@u=M3;Y>94jlr2{>{~+YQTeS+(8&;ueP?l&iz}ddV~{b~*d{+`qOr}2>BhFi zF>#LBVLCS9N9Bhp9oJ!FpF{N_7qq|BMFUu4zjz4h#`YMTiN<~<6l+2>_Nz_MIaV|l zwKx;!*l$73L}PpXoQcNvnT*NC^!s+q5T7VkA24X0ZtP$j6OH}u)$33&k#`r%hjy;U z#=d}>SgV_#VWRbw^H!kon#t2rvbS*)>|=0471jn%a9au#c>Ce_VZtg)J- zU7Y3Gc#hQ^9c4^3R?{-VS?nCEIYu$nSWT-q7Hh2LI65@(M`gcgm;11>2-KW|?=G%W zLv>>{?E*AbHO<@|q8oPuWiRZDJJ}TYWjcDvr zb#QElrnAG#0yNNJqOr?;oQZSn3NL4(vA%B3a&2c`KNn-NG5x^64DqO}xiUiQbYoY= zG11sHv@G#+Z1kNU;PX%F8mJlRhW58wYJ$2-s%ge8Wn;G(v`{xTn2>%Rs~Kz))Qt_X zI1`Nx4RR(LyVcKGuI)57%w$Y9cAJMYagLda>Bfe~G11rvA03O~bx;$)=dpYIG=McWNI~7$WFIZm zjXme(Of)vd&6#LyscjYLu@NjZKSimK$65e3&uW*z^Er;v9QHG2PgVI3^l< z(V}A$KF6|7GJn9v)vc^6(X{v5)samMdv1JBdCmLH$DE8bY8e47?)aTeI7H8rdTM^_;H1?^VG1=Hk zlQYrSDi1N;*y=bY8vD$r*WqtSe%@5S;r8!f{BPIYoYLpcl$55=L(MnwzX`G>{@P>l zy93$|we>XTH!e5-2Y>5bQ)q$zwo>!Ijre&V?`HEA%j&jz&LVABAW{;k@R?qjD(3w8P~53z*P zOS-&xET(@8HT!Vy->IQ2U4Q#Tr~hVCl1|@i5lc8dD|-K#nEoBq{Dphpq=vHeE%ogE zut`Ze{Z9|Egww?}wd#`QfCzkNuk6HZc7);*`wduI`pG+FS(zo+{igUiUjX?`_ zdOD%lThxReaoyXE?TG1Hpca3RYWwZBnxG$XJL}ndPLLMr^!9#Y3Ge+DbM$UZx1qK( z?tPa@1K8eo*R%Ii3|gquI}=KL?|BdJy&BWMhuX7((0;eACg{EIsb}w9U9?cAca0KD zc<*awygM7yw?gfC2DJaxqycR2ztyw%o@${^Ki5MCC!Bs`*W7b3{RgP^;NJC<2ut5r z&)$36l%&%ywumL1UbC@VS4{sAYOln-?>A`xOFvl8-utSBI=!EV4o*1zo7cvFj_E%^ z?G3p1gEkFd>4)ms`}Jy}PWM`LaKh==t@(5-rf-AVfho}b50eJ4^grv_`yg&4pX+W3 z)4>U+`(3}U#q{k^`w+gB`_rZYEd6huB%f^_R7ra8V*+$=!s$0`@IQg+JD~RQFtq>2 zqyaj;LyDImCdu@1QO4xn$47`IoPN>be~-fSolyIX8#<)eG=QZyQB!sLL?12Gd!OVb zmT>y<(*_n{`Yx!Q9)=E0O&Y+`^$+&y^l4FAsMDWUmIRU`eAw$YArW( zXl>E}mfproP^Z5iWK5=i;3pPKAL~zP))a3X%I4*TBEV{;k4q0?Oe#L*PCT6)P%_6ES7o~YQi&-ve zZF43pSB4prmRArG@0E0yq2}%eEI&^Daxq%&gGJXzphLEyCTPnx0fO2xlThr^-m&C2 z>aq?KmbDR+c%3do;Az0}-WhM;^>XTdSkx9DYaKi^fOVPk|D>G@yj0`&|IezVbCHp9 zP3?0^&LJ81+^5TzLX5u1CD|1rWC$gdK@z!)#8Hy1nV*-@iH+sL+r`~e=$>{;>~)`?lB zMTxgK%$xaZrxXswjlUT3Pr;WR6N7Xd$T#yu?5}u90ySK{h95DxVJ5D659E7rtKR2T zZRlNdr~5U6_6lR~>$T_IHFyrD{{{IM z;e9s{rUoqi5rd#gzc9p@NbeaS<~se#nO)z)^!<>3nGT&sd#M3Se@r8&(yy=>6X`ya znCtXY+K!)&=?5Th8{XF*YijLd4C*S=^L~`;MCPRDZSzx|>-27mzq%IF|AxHZLeOb! zQ)?fmQCF4zYlJb8zAH@3b$ZE_W#?l0LCE{d51q!z25j=<4eF}W_nM4}^nJ3=)Rd(^r4dx=|9Th`>HkKFxlYeJspAezKLq*s`!hN{6{ZF({b_@s zOwT_u#F&$w-zGrJb^7{Yv+XNI|3dz)c#nI=OAT21B#od-kNfsGk$y|^>HSK6_obxZ z<8}T}3pz~-QxHp^Y!FoGy2hAD$EN~ubG`Nri_@zy9Uy-s-rt{ZYV9v*)K#V5YcM9# z?+X%honCgJ@1>aD0`f=WoN?NfP@c$RrML`i5Q(jN&BbDh5MfuoZ;P8(HRrz&-#eDPT$lq zycW}sfc%#%==54sYkys%t}1=1pD~fH2Io4x`on^54**)9X#G{SAX9iSzzC zXCi%ikm_8g8)XvzsLcJVi|5vFAA;#^Ab)`Y zo!)9{?K2H(tJ3Ft7!&F9qr_aVeXf7bkC>hc`AaqE^mbEge@COPD*Yp!F_FH+N6dBl z@ZGhCFg*?O^Kk9&G`0434eF}WKeZSW=_^cPuG7bPvwC8BI^=(b=|)p)pQBM%m0l8I zOr#h4iMdXH$$QzCn4SUoU*qKGgsB1Bb@L2@D*dYvV?gZ>N6+}%f#-@P?=0;;x!{9nUxS}HZcuk`y-PD?Y1s=@!vne&lk z{x24*6DQ+WLh>QNoz~Dl3-LX3>d}zD4=0#z$Tmvrs1QM=^{2_0(Ar}#Cbaeji5+f_ zEbZGhinG8s90v{PmglGA{^uTPsim||@X2cm^x0_P^D_HX_|P+hKE}0rprEA%sdX|U z_8vM{$2X;^t9>#TkL_Tyf)s->XRQSgWXyS9C}^QG=B&Sf zu=}Tl&U@sa&M0>b6r_70H8(`ZsWj?ICq1zB6RmEmihXxe}h;h&tJ+yX6#}>^3W9 zcAJ%rvQKKU=@ZQE0I9!w3(sC`#Zj^Dk4&N>yC89P@udsSO-X541Lu4k zziySCif|A;H*1K%DuVGW*D(jn_Tp=2tPh7PP7ON`=iFuOQO-{?MR? zv22l|vT=ogDMJ&d?3no2RhUu-+RF)3mdLZkQ`B^wl-7S4w0~MR-n-R(>+yPV%X-jW z^~9}(?cJsEYjGamJAJG*wZdgOQRf`C-lrwZKA|G#BFt_8Eo3IjZj>UjKQSnUuY0*g zRAlc@yzb`)*WfFima9Q~BjLImrHJem8l~{;JcB4@Ctmk;+0TB9*=s<{)f26|QHsdU zw^~A`2M z-6%z5muQs2vsdXvMfTrD!oBu-cl+B#T7C}N?1X!*QHsbm4NBqJr4~`jPQ32rw>12L z*=s>Fj6~~hlp?arHA>;x6$Vj}{b%BJPnb6}4YR)hZEnJS-Y7+6S6Y<9v#WwcDLe7H zUkZJahuP~un;%NF?rM|z#Zp9ejUGqEqi3x}RAlc>oc(dz-`ZjJm!Q2LPL$m!MP%1& zl)~5Dpc56@dyIs8Z9s9o2ea3Mw#c6-yHSeBUTshc&t78@rFAFHuCGYlkJ(>=w%D5} zyHSeBj_8!avp+Y8itIlUXFuF~+jW?|0W|wl_XQRm$zKOGN)g#>RV^MQKIZGRPNNPY z`!6lw%=Ia^m0|YRpe;>!A8V8%vcJ?Rg|BuugkyD?UVx5qC)I)WLlly-B^1o2-Bq(?)09vJwj$?99#)aBv9ty^L zsZhyHkfAnnn)$fN~w7V0r+w`XC+04XIOm3bHwa%E9shm#w9u=Ylj)1Y9D1=y=O8sxa=*wzn>lhjeZ0<*`&DC1$n7E&`xN1SU9OIf zyn7SMb%lccKG3#@<$-F??a>G-xxIv9S2Z2Ey%s^c&XL<^GA88k`ii(6ZgNje>lHw` zQ=zb>3EIyQI*v{5UxT2OD@+M;7LzLkowJx+VGAE)j$C0&jo9Jjj%io42j#j!VOt+) zzeedeC0Cdxn<=?;S!XjxF5Mz1Cs&wZGA87XGKd{c&YJBz4dqUQ!V^r;e)rIEOs>6b zrsO&VsZhxsr*q~^?sy+#Lhb~O*x}?(XxHLCl*@*~ExApN?a4IkK6OJ3UB+Hgitv89HZcb<=+k~?4H%#pi*P;8ox+yxdvJXXkEXc9Y| z+-t)wx(?;efWkgL(EbV0aZK(Cji8eA5n`v+XA!jP9JyX5V?wUCLF{mHXKZ`HhjQJa zaDWAwDPcN}$@Mo0D!Ho-&Ya0z6XeX1yH;mR$PMrjv*qmXlTG|luKZZ8&35amx=Z_^ z>X}e@YX~x1MyN|nHCM-8nXNT~sOo&sRCsfcG3V2p!a+J?&PR2HxA+)yKD{ZtRU?*! zDt;z*PWS)ZimE-J@NPd^MX3u@P4y8}s>3)Fs>3x_CsgkuWN!_jdY45oIn|kWEjR;J z&w|2-J&>8^p)O1{Lno+IM-htc&W|jde&Hzmf9HmELiHh&F`*hTh$W}mc1eqIsOp8n z@djib<)to6_2?i$rTRpOF)`I~0mg)C+&ey@s^0M>r#kh45aQgG1awlT576a`1!HURM&ZlB{$V) zCY_Rrsux0`g{oaV)P+s;RGpww-5g>}sBQ@`CZ_tWpD{62%S$Xd)o%|xQi7^Ip>QXv zc9UJ0YIcxXE7ct##)Rt60mg*tFMh^^>P{Jwoa*sQatEX8MNs&c4w*T!GgCdo;Bg)F z6ufKfk%g!)RQE~+wE^~d__59g*cT<1oNBLw9~^_K7ei4?e6Z>spe{_che=RQwJ616 z%uy`@Ugu1;sD;7moT(PI3=&IDHL~czA5irYDDr5Kc~*$JFx9gyf=cx$J}seol$@5F zYEjz=KQ=biqNBsal2bir;0ceR>ZMTB5mnETU6|_m)H(L*D7FELPV^8&Eung1lrb^Y zlOl|Xsh%uDl2cvO{jR4_^)e{RM%D9WXQtXy<8hAasUF6J>Zwu2glae0&^{y1R8I?2 zU2>{-tm$h%u3ipB=UR~2Q>HQ1OMKK?Z2&J<5UOWO1+@Xr3Grhc)pG;Hl2c7v^uTyj zy#k7^z-OyVJ=BG%Uak{Vs+V#mR4?J=oYRQvI13Dy2`T576S`}wiXRIiaC$xZe2hIU<0wHFi(Le<`~Gn;B(gU300 z^~MlmLiMHqV`8c|%ZBzc9o0czs!L9F=%hbyLe<_-G#pj`Bh#4bRVKAoQ`JL^3Du$U zU^UfYepV+`hkJ=7r@DIHvtj;dEf(HAL@IV3<`n5u3PRH~mv8563J2xCI^^DtvVb!~`Pa;oF}1DB)f zHBj`e4>E_!E=+Z}MXiQ7#RY6I->FeX%YL>UvRKSziqr~ zRO8+n3e`(BQczR9j1W`3O!iAo^|o=DV^Q@+D83q1Cxm5d_1-EdnNq#VM-Z7%?WZv& zrrMtnQ|)gNOiuOTgDvKw>P=95a}Y9v5$eLG`m9D!ss2~)6s3BjpVbM~o4kyPy?V2U zSaPaQWPkn+s@@F6!+enWY?Qh%)yY1BO7%{zAf~EI1*{XQx@>44>pTJsjZnYjR9~#> zGXqrzLGgq5xcaLug-|bHtH#0mPSyiR&oWQS|txwQ>_m3W1S696C#$}RL^g}={{5) z0>xjVs(OFSruwdrS}WDhn^0Zbgz6VfsIF_K>XCRXGTeXKK8%OsZER5xmMm!hf;#XIqCHP=gBnCko>L8ZFGVoa$1Y%(VH z>MsUkLUm`5SaPaYPHO0ZszagpuOMVD@KYD2y3in~RQCiJ6RLaV!B{6$_sO-Zss81m zW0O<8t<$tMs5%T*wnEhpqyba?(4^KOm&%LO7%p8pqlDQLB@pY$vR^~wWE(%a;kZko*6*ZyJ2N^05X?Fs0&m5R3oTV z<37z6Q|;zsbwc&DxMO3F04uYpEXk*UEBf|siK-)D<#{QP`Ds+PQBMK+K7vZsD+|?B z&z9>%CREP}^J5*=b3??Eo9e@Drksna_rS`_HON%Yjq0~IWU41ZrF98c6cE%n|iIj!HHnOuxo_rc16 zCS;b##W5|@Uv?zRXjtq~@%cX^YJp`53Lte(jmJjecF|9z9>XOr1n|0GV)OrwBj>iX$TG@qZ z)mzkBX+05POlXY@GbXg23=vCC>*(bhvruaktelK{tHGo$Olu8~6I=e-CbTB;I-&Jk zGqt|ovSU4JJp?O524sFFyD+WKgXF5F^-6#-F|Akqj0vrfmsoPsnl~h87-|Jz<;)0V zuGOgv(^|*l#I)XOLTd)E6IwHyskNfjq4B8oFsz)9d+STtg=u}Ik*k{49D^}2t+_$Q zgw{NrSaQ=U_I|t+wH|?$OL1>)peFd0emPg>*HNNMYjK1zq4iOiF`>02L@YV2Pud5@ zpw?(uS?hz$jWUgCZ8E8~()!59n9!>BFebEWWL_>i~wb>$= z+_VtvHya$4gbeZLm9#zRRr12X^As0-8D>mjJLy7I}0X`L$9 zq_nzu>Dc774vu{3bkv#vCEf^R?u}9xruCOaP-*pOLhGz1w7kvKdiv*Y`=i!GD7nN3 znfpyLU|N5N2`a6NJdBBHT@+rjxO((2QM zR-Y!c`ZiOm&7$r{pjHq{uE)LguTBO^D+~MtmDT_sV`5s@X^e?!T~8><3jkfKDmJ0k z(@=7oAF^6_WgGc$n$?QOIWGfC28F2*RfX0qA;yH(tpQ@moy5({zxoEXo`I6Pf{=xS zlQ(+3mDM^*OigQ;#+c9=PDnjfmkhTECZ~1&z<)AO>scrn6@{!LBh-bR#8i`@(t3b1 zq4l7_>cq501&Jl6)w}x_7o*lBD0xDItTfq~X=U(}BTnMuCdH|fI7S|fOlXY_QeARd zw=dlFENVRmCC}pCIx0Y2nAXucK{c&llrb@_rz4CBt!Ki-lGFPB^xpQ1=E+dy!vVrL{<7Oib%TLhK}dXc0_K>$inl?R(;jP_n{=tWII-!n8Dl zpwe0%VoYd#8emLJYlWX!a#~mQeBcz+nhGVQUdYM}QWvJxg~y4LxJuTkleo$vh)igi zCb8tSrncxaAGKbBl6oDoy2`~dt+)%|LJMD`iJQ`@wHOmxbtbXowEns><2TfL8A^T( zK$g1P&a`qo)LNayT0TK>64kpoHLV|HU2N(M~p42z)B`ZdUy z(AuRlCZ_dUoK~Ap^|-%TeATP?%Ve*d7KN*Zm;hJKFt9<3b9evWpv5Bo}ALcAJu~i*HoW&-#>I6cu zNAX~x*dGqH2!nQ}d`vo@ZJkC3U;VAVA#kaf9i$|lysPw8r6K9e(NkM%M* zb0*e1$eA;-K00U4#QOR;b0+p5jWcIrR}!+PEhcuQMbKu>#IBM|O{~9%>eRjRYM){* z_t;}?A2|{y_ByN@8ip(-&L-xO=Rr+ukU>c{b0&66kTYjux9XfZ6T8jFnKQB5HO`!g z4JO3ym4hvUYGQYooH-L4BAJ@lopH?BV|tX1b-l;-w}|B7#HPclu_4I1TB8PRVh_qB zHL+0!6{?9n6y(gASU~5j!LlEV9`39*Tdwg{?;J!*31Ozbg(n3~w* zam<<6n24%#xySSuzrn|q)Hh(&t3Jr`)A9H<1KO;%>=h1@P)+PPFF`f2$sW#}iA|1j z=1lDQ2xrd3ri3|jCiX&zvs}w|c`?A4xK~c~bLLF!CCSvp)OS6qd*v%ZI@a|bJGRI6 zk8omd!m1VcIChgo4cNrqmg#C@v%FNOCiaepGiPE`e4IHGd(PlY?6DAM&cr^7W4V?+ zv87bT9>>A~g6JY1$3Dht=cXq1iJvoPk9|rgc16e4bLGpooVgDtmJ6#^;~u-+lpWL_ zE8|Aa>#m3ikTukx25gT_;+A4!Ut3hDCbrS!%$e9X z24~L1HU&9zCbn7U%$e90A7{CiJ+W^!#>B+%KZu*!W8V?Ny+f~HzmH?i#I||~y1rMg zd27NtoY)LlbpRjv?+H=^HnHEDm{>GGg=%8I`#Ezawp$w6bePTu ztTal{UUlqUl6j<;v*i|Anr%Fs#U^I9i90qnF*7y7>tYi#)54s^CT6CGILo!{jEn$d z&cw{4{G7!mX10|~PRu+yj>RTsdV+MU>piw3nwo*C;VHu~Xxi zGqKY&Rp)Y#-TL_V7vaQafq8iZvYwC)*u+|gsH>XTc_wGh#LhQ3b0&5{kTYju7wVij z6YJ^Y%$e9l8fUqdJ+X@kspm@bV*D@84gH))e)AH^)Wj~0W6s1b_lQH?KUW@i!uSz5 zv3J0{8}F4*(ee0|UXPhq8${K_t_gDHOzc{nGiPE0e4IHGyH4ZGnb`G&Vy{-6iCu3I zRC~;CGA8!e4F+e<9vc`WrY82^IOa_3u8690xySs${x{&nW`j9ihpb5!HDD8aI7CoQ z?2!Ox&csIhIddlVsFyQmVvl(^b0+p!lrv{yk4HGmwd_4MCd`BxRw3#!p7YttKOzg!VXU@c? z>YO&r(_xH;8u6yfo zoR|S7{*LdgkUztpWDxs?}2G*koBf)$|g2NqpoUVE9ALR z6I&7GbZ8 zh@UfOVxN0C%eCyuuJte`Cbl-pnKQ93BE;0h*2OVrV(Y2Q{k^h}H?KENY%Z9;;=OW? zPj*nxl@XJmn%Gt^XU@ca@Nni#?1w04&cuF{=4y{^3-dZ>V%tNU(qqD$#U@tTF2q@E zVx`9hIE&pYOWXT7i%qPwMU=B#%bwWxVaCM7PW5r-Osrdgn3~vW7H7`Hazcu^++$Pk z?OcNsTL7iK@YTg9vMHO`h14|mJQjOjS$d%?lzXhSr%8o2b0&6?!I?9$i-Vjw6T3v` z%$eAwKF)G2oLK2)8e?K&mlKM;;y5X2*IjNAR1>=*jyV(SE#7c)-1l7duGC6Z5 zcDKQqGqDjt&YX$eqjTm=>|P&d&cyE1ILo!{iH#(rUcr`*#Q);l(9d}VTYA4qOik>8 zC}+;ZMrn%Sp9#em*Ddjn9D8(V{g06n_s3^*NA}!^AH+WdrQ?Eee*i2E|H7#Ad)qrL z^{Q_6ACzrHz%8Q$mE~t4&XTi?_~_V}WlJsYdr9yw7C7Ha()*pD{F~vk zf9PF|mLEZBbriCvYSaM#svbQfRhR^A%a1I3Ush?1Ip4`rTJ0m|I{k<7kdNt0pfspK z_R9t}Q0dvP#?8Y?w;!>b8ybo9r+maHJ@H>>;D3Dn*lly{myAoH^o0OqhcxPfj{;%< z+0#4()c_`2j5*)lQ~JEgn9!OMA(ouh*KZ9v9<{j7fPY2AA8nR8I$$4B2m()P-r~as{zn-U(76stT>yI%7iXT^}*hY889* zbRMpn+`tFc?tBo9mO<$ve8_rBu9X?h3{qEnyL8a)4g9{zn6O-EFeZ#X2oiH`blG2% zFF~VEpmaIzsJC@$z>MDU6I4daJd6pWWl_e2(I*jNu8lIzJ8cCTEr-${eULrdOAVNj zp%GL@-&>3cqpc=m!srKsm}{eVBUL-l=u;^DEd<%`(ee0I-s|SXt=&0mzv@(pmcnS4 zk1=8Nn?}sFk(F_web!b$>3##U=gJ{7qxmLvRWsV>V@w$Rr7IzeTWZZIZ{I%P9H` z1}*laQr68PXxG{Q24$z2#ArsX6FeTJK%b2k9_O*-Q|pZHpV)+Mg-~{(3E4|M)GGD@ zAofB$`(vG;ayu`~nDba!c7BL4F~JK0j0xWh{luE#8}VIoJ^B_wSzkY7FY{6>=DR#d zQ2F-qF(!O_Ym5osK7{O<3*SB#!DjeYe*X}j$JAmd^W&r1r*i4cH_xE{%6EWV7&75| zorl#4-|M1`3E%4@#G2tdF=Nr4=(`fi2IIXaKR~URZ=p$0`QFNz@V(7ob;9@dAY;OJ zuuiNQzJV>T?MB}cD7zQ;Z&8R^G2fLILFIdQm@(lyLLQ8D!uK9I0Q*?y{&ugQj%|kT zfRnBsi@vL%>@f|pOQZ(#Ev5FcJs5jVDSO025IuzNBT>eL@8}3)!uL@b(hT1nZQeft zeN8BPIt3Wu8<>Q zzUnQ2+7B;=C{xXMYJf4}`;wnA;rp_eSTlTIpOiKSeaoP1rWdknJk*N$*69S5Z?49e znD1MJ*z?6(7D4-1XaCMHi8aG_@cmL}O!%(%F(!P!(ug&~cVYK81L#`=Wm|FoZlO;2Rr*?fqRQ98 zgPfb%58v@R;rqRp)d}CN9%9Y#?eIhIqtUk(%6_vT`#X(VG2gA+&3UI=wlhM7%J&o9x#NU(dDMPDS53C_5N{>>qs8p80Nz%XIE<`*kW*z6a#N$b|3T8mkk& z2MNh{5J|jVpD<*-7k%rYyp0ao+jZGX?S~y61-aZQ1KL@E5n{V8?7rw_>R4C_L-p*vqnQ!^A24ljveUMl) ze1or4osPb%pSlve1DVkQ1d+{LYd09Q5%%%J&QpW5V~6CVVgbzxaCQJZ?WJCVczpjEVX7_YrHxd><{_d@cG$p#0_($lgbt@T+|M-R~!=_QSv^W8(hy z-w0#E_r@?|!uO^SG4eg^RhZj+ZTg|*=TNQ(A^U(v4cIl0gC2s)a)_TXVRWaLF=3?3 zV_h3<-&Ju78m)!$k@!4&FiK6C(IJbVGP;+i3#0pFx?LB04O@PnZ0Oo(VT+TlLZdIB z{81gU|1~LGUB=IWAVEwL>5oJh6X~PF#A4}VgY?l_`ET}>75ohF|NCfdjj!zjOkW4( zPozLj3%R7&K8k&`Rz5yJUG4ND3$N|ufGo6Gp3TZ1(Rtkr`EL%zI_IOc^55luac$Xs z@zKN4@=GY+<$;_dycEPNR~iJRW%){3s4OQ0cwJ)4Mpr@I%<{2}U+puw9?DC@kkcke zLCkWyK~Pz4Z^E*~!|M`T{$f&{>sh9DJmq4v{0hn|e2|kKp$5#d$|9&NtK#OChZRu% zlb_cmwp?LQoomZyS9Aun+yLcyLC85;qXx{fP(o!{5T-(P#;aXgHhO*O=8WIjZ+a`V z{2IzXLCbal3TKwfJp`5I4{=6$mOabD5U)!-%gs@$b3Mx=x@}sBmK&jbV+e9OnACt- zu8T8@-N(znu&7YYa(R%m#FiW6YFt~6Jny#AX!#A4e;t9G6Fn5fEGIQ#`K(2S%5t5_ zSwhQ-3w%`P+Hym?pDWOE6O_N;gPe{!HDH!gErRNd$6vF_!wM*$Wb(SimOhQ@8d+AH z7fSG`uFbkTfR>w~;=&;0bPiJkWm$2t>?$oQE|P_6mT^~>5`V~FagFTf+A@FC**>(~ z0u{Y<$jOQ{VcAzQW!Wc0P+C@89LEyR@=Pxs>)P_0^=F=qmfu1}KMiuaY1DwtvWJJD zvg{k+EYGsf_-G$zi7kg`YB#*WqIK@rq6%f@+pM zEY1>J-r=D-*Oupx+xsM1eg_p@ypYq~qz26LR0-8A<6lw7W?7LHXP(${bn=!50-GnG z<@Zo=En0eI17>+$gw&PgbvkEx7M}5n(+I_8p4c*AQlaZvddg}(M$4^GF)#`_=jzme zS>9w2RF<6soH>>Q{hTGXoNQ5@Ys;Nkmpz1*KS0HuXn8@H8ZgUYA%ePME}>=lVj1GvviBoL+=iArpkj6kVmMy(eh^~{{StomJOKY8*%B*bI+VOmSFqvX4fUQ{4GRvt}Q=a^hF+8?t=0IUdR~~p$5$Iph-|! z&hc^ld`A-~kEcXU^UE*1` z)2Pn1W$Kz`_`I4Lg^JdA#)kx`0kcf?5tNn{Exeq?EGrU))H_>u0RQ5*8NBq=) z&GJ8zDa*bgf;Mw3FL7yklTOFFw%pQY@_lHz4=S%UAm=fI8ZgWF*X6NS827T8@o2VR@^Mpqk|^5zZXT>%*KS-k103ROfn@Q_KGN94+@l zrH+>4ebj)>a=3)ba#$0Vx4N_(ty73=%hg%GgwXN;RE|W;r|_TYCht8D`Uok@2O^y1 zS@>$Ba(I}t#Iu}WP@QYb$-cW@LCe3P@=>&W2IJ@^Eywr>Da*&3uzb*^zA|Sw8LIEYGrMImV^sYX%+b+H(1bQ|6=PKTtUZEnf&y z178}8P+cR-@}1!XS6Oe^aP}i;c?c?}q2)^vYQQYth%<5? ziKfOGGdu|_H*dP#es}gSRL;Ox!LP~&%u;>lototvLGrR$ zQkIpPkB)6|m>(J3x_A1kC~^Z-><_?c9*vHJRQi!YBKBAO!ABgBtMC86bKB_sDJl4a zjFl-Svl`^?qWm)3=Ntwg}T(L&dr%n! zH_=nhO_5E-XqgI?nYfQ?Eo#6lBVK~ivhrO&XUSPE^3bu3EqCb&&bV1vT91}#Q28G2 zx7Bn!ew8nU=7oqV%Xu1Swk1?X49*hI@&j3SxTl=kHa*q_MTS7-!T{tyY}6ml~_zJ5c$DpP;?!Lfu~BpR&+q_R|DZ?(y)t+*sY7C}$0^ zx^)_7g)#P}kFyoJ-EY0YS*~TXuS~|A-_%gK0so70Ll@`w4peR=WIz2nzgfQW8;zjN zI#_nUO+m$+Cuw(2lMAM=9DrlXfYbsXq~^(0s_)3E{Mt{g?GZUolV5ol6Hk-tLX3$g zs@)M{vF+PZJN(ZMwi*25%V=~IR4(yD>UM(~D5KOJ8bLI2z85g{XF{>paE|3-nQqs0 zv+O~A6sE$)cc@x?9&Ylxv~JjRFMbl9))p$4dm(kNY|8FX`CjU3&&YYD`D>7~JPXrP zcZ4{z?@&;=82{h7;jzwlX;ocp5~I1fJDrCnfAk%y9u1YI7t$tJ)I|+1?Ws7`*r3va z9x6lyaXL$M#>DVe1&NW?VPAK=(Qy~PnMm_M<==it3(5xS*)Q$s2z9lG=bXCzvJja_ zKVVRu>-4sDBmTnlW1y;~4r$NGAeKJKq^>f(3S^;7uWAvdI!bqOO4@9+5TkT=Lpf^8J5x}hJydlzA?-zjy0D?V6e6e;PVq7(hSJHyn9%C1 z5hJa`4&|x?vwlLO4p4QG57J%^Py;rUS9OBQ=rmb~Or&S~sgBa!4duw1+4f8H0YTy=GBsrO+$Fm>5d$Fk?cik4cQQ4m*_n$KCN38XXT+1JG!iY`}&xohLbW z-l}W3kx0K**11l9(p!Mn$I?!Ks+%=Pd&5WiEIrptP|f4U5Mv_!rT{V5>7DOd-xkwP zgsLG1q~)5_fThonYf|ZhEh+~Lf9{Li~PlBp@aP2dF)Rd*qYGUno>r|-H zN63R+r$1Bi<%^hpGE_Z;YoBFOQG3)4G7)sy&?@ve`W zvh??wSo;$pDpcv?0>oUW>&G4SFQ%UYRg*lB_MS-%So+*1*8WV83RU{EIx*Mje~cLN z4yJd4s+U5LHqS>5So(q{*8XCI3RU`4Y3Vw>$eQvDrgw&_H*oC>Olr!~7s{@fB<}C8 z`>9Z+PxlgYoj#y<-6Blapz0l5`v*R1z|udIT~+$q5h_&av%Jz|z%gN0mO$PlYOdzO;0me&2y5lQBIDs+L3`ZHbSXvh=X*s?tA_g(`iCMhCl2 z-?ezm22Ae)Re63$3!Bt{r7x2cRq3CGs8FS^2oQ6fer?+e@EU1aSEyQrYyZSY4Osf8 zO{_icf{}QfFNxB@uG8C_|6Pyir$SW?uKiP!8nE=dFhRBUst{u$y*fb5b^4bbkFwLd zL6zl&w0s{mVCjWkf-3zp4`U+zTa%dU^p8jR?RS5tLDdeNe4%W>(u>2?Ri$r_FecJ} ziV}03UcE5#1*T_1)oz^pN*^^~>8rd1ReIE9Or-yA5Oba0ZSdY%n4SYw2XO7HWK))2 z+Qi!TdngHwMEd^Z*Z$eU4>U|a9jaU6+RJ>@l%-ev|7)*~`|b@Vy}Ct!4tBlvhHg{q zF#QauPRF%ZnACu!SA_}6$ycX&7!&DfQDUys&+Fa&GEDCd)$K!&R_&t(EWOrCP^BMB z$bN?}(vP(Wx=x=_bJ_=(ekN3(;(@eUlNzw}`X<(XvY!f7dPiyLI{n3sH`(bup!!r? zdxMXfvh+2wt6F=P2o+8Bla?tV|sD9ZG zX&Yn%W~tt2D$7@c|G(wq8fS^m_}w9@Yh*dUwKu^TZ_#b$C1`mrRKMYcv~L2`fLY#S z5mc5TgR?wY;ZT|-)!1K=iCGSkA&o4nhbH=I&DN3QwxQ*DXlX*)7E?8*3+vSncnB)X zTVTj;+=P+<%Lk~$9?&e6k?YBB~-KQXHk-}+)pTWecHC< zH>?wuzf1E*meqgg2`mFQ4tx_WdqVX9wEQKY8p~PEh!9kk%0XH7H+h|^aHz73%2hYE z+?nV;zBT2FgJ^jXRL|BSZI=vUvwTmgE6evtC^ok|%f9y*A%b?DbH>#r5@q>onCco^ z?nrdT|6Z{)8!az}>RnMt+wGwS%yL1LptAfe$XT9cTfT??@7&0e{@wnnEVm`J{4voP zudg}__fy&>P`w>zxkp!x3Z-@l0Zo4aDq z0R5pl9DuY|QQ7N%e8gveSBZ;@qV)%f?)(;xCscXj1BJrE&iFY_bI zJ{ikpAu{J8Y4viYCSOplkae*wgIb5ZNLtkM$Tetm8B~9&L;AyE3Rf@b(nkjfDx;Nz z?5!YP&aOmP=SJx+hSFxcb@`BQUPgt>p?X6I(jTQJ_?504r$5FQD~7UO7OJ7Fw+Je& zujH|$b=aZ2|7hopXmkZse;0xD$0O8~4P~rJPz}ZMF(!ucokq-c`rRA%;NwP`4{E>z z=}-8n0ZV_G%)>5J7$S7mZ zKCNjZ4^~>K7S)l~VNc1coA%mow|hg)v3Sp!Xix(-lwgRUGHT~#%sC}B$9jlSy1SuF z{At2(sL%&$@Q<0NKdn(0wojjxt(C&boQa{F9HoQRP&!74k=9{{veukCAC3A#O}8+l zKP#KEp*&|%S7mgn#+VpNH$v{eCG3>Ip}#TxKTva)7t$vOWQP>`KDqQMIzg3wrYuxz z@8PF9*J}@@y8s5F{V=^B)bxu&`pZ#jz|vo}2&(j}bjHMa@8=`tIz8*0 z8Iv)+Kh)e1fb@`D5=)=Plbpxvn(M=qq}J{a5p$hBq4z&CF#T$%xfRzwt*Nz7x2UUH z`z>C^#M*E55ObaW?{VvX!1QaNW*DyhjQ}-ZYtPjQs&qZfm`EQQBIY`M_=ZA1re6y+ zBXRAyQEI@_XIKPP`h8x;MEXb%G1uvvmd)vj=>wo5piPiS*Hg z+&|j9v1!t2n0_79yb^-+Sxv2dwnc4K`UI(oOr*b}QJw3xm$m!50MoCBnp~XxyRs=; z`+GWdRq1bXCem|#ROdSViJD~{Fx?L|MgY>^YijLtE$XV$XNMUR>Fx~lZ|y^M+Ug&tzA(-;2q{Txgm2sIyvAzi(FVUu5IQCF27))*7% z9}{xF>z<$fqf)vJja_FYr^H>$Ok5a(*jJzY%K6aP1#P zsR3KN{RY9gsdQ5os`Szb)wxa|H}AL`F#RT|smHZ12~Y!;9@Yt}^jcY{((C+G=Q{nI znuhZ+{bs270@ognQUjL0%p$1LKbM6neQkv5T&KS07;wiS!?2o$K_OZQnF8{Z^>? z71v&5P*aw^GDJ|N{}N_Qr0 zr{6#CsFs+1JJcM)wVMVtW$9&dO)C9hmG2Y@(_>dZYmYWLi&@ql?dL3Z{iZhVO{B0K7Nxqzmg9p7EE^_1 zJOC|+KyCjBq}PV10ka&S5mc7f1~|*JaF(^#5|URxq1F>2sAf5lP~*>GYRCE#SpJxC z<&|i8C)D1BZ?qf2vV**mTzd~s60^KVqe9!oCyjMsc>_b=VYW~rvtD5ELIA&Y&8(B7D!g91sX=IuB$1twn*>E*l4ux9$ zDa!OO{Hifo*0whYD$9H0SaOzqH0syLGV$jyXWaW$5G{v6ZC?+huMbcIHOt!LO@hku zcn@c`CDe9^W6l}h5N35^mK!x-h_OeKVN1|66ZnzUIM?h^4JmXt6YQQYLIzeT5dW19ElHcsQ#FiI&sn)gS()A0k zLCbrf_H(?CZ}U+DW;s!=U0Hhn50*>(6w=tTA&_8}2Y2=V5iRe9+NC~7-w~n)%yOB8 z%JO523T>8${|2=m2RL)~b!fTMq6W;eE<#XQ zer9mySQeO^IhLR3j5(HdEq%le_oG%@(-tko+9#m)L;Se~~mDyDGq#^9rxl3=xaXyrqkeTmEQ0%zlM;Kh#bOLB{1# zYQWNcnCIN=nLFuKoQd>mQ{3_oKceWsU~ z>$QI|uhqAh{vg!O#kKcoYVH5AsH;kUFT$8epA#nLI{k>ceXTKl6x4oWLB^EE94?KluUkZpy>-hoJTcFJ$zK$`0~cdB)WiL6!c!!I((j8YJd=?dAR_ z+G2VDYIg=9<{K0v3gD*b1ZF_Hd@LCkgfnHQw@#q@`vc25dq3}|ZY*IU$8rT^h$ zOr-y*5p$h>ddUaHnEnXV{)21xH?{VGI(1d)f18Yn^n(U5*XgS_?k>gj(NNbK(+4)S z_8X;=Os_kFg4D;Wbw^kPU8mogHh3YXKMHkiqmXfv3}SnJkWO7y`cYoSoVC}r^$>HN z-dAg5VftfGcRZ#Kic$lXek&F@HNj>h!Ip{^s|<8Ete?Spxe z^GI9QDNIRdB+@&Fh`CN5SkdPYrjLO-{DG{D!A-4wh(%r1+AlO26X`t-Vy@G-XP^HW zrjLcXUM6JR+0@#H>eN-G`v|dJr=E>mr|()a)4sny0d-g7+J`o^_Td&qsq}t9#>CqD z>%?5AKXBc5%Q1Z%)D6V7-__LGN64-!{RRqRYrnxF=sNx2%$Kq-{Yj|1JqQ^inp*q4 zva3qJRTd%>Yrid$bozTeBUfPhc&NK81v2hyYVG&y)K#Sq^D!pUhik-Kul==@_gi85 z1gLue*M7fT61%@YXi-;{KGI}Nq~C84bDdt@cgy>jJ`w81;{AP8Q)>_C)K#TFE(_J< z$M~tvb^5`=7vIG6r=TtvhKxW{Yk$O|t}1<^EL7=FMX1ho`k>`GyD>cobuZxBM+c|@ zoBU%sL6!czEL7=J{8Z;U{f&*!;5Y50Jq>lQMIl3ds}4&aV^LR?9?}^T=lwMwvBSMT z_+rWMPqFrOsCyINRR3<#asTJ{2alcCy#QD94Ai}?Lq<`Q8ne}`RB7}Iy>3Q`3e_xU zhKaeJr8%VFCQN@8>gH*XQ4*jAEZx)zs#(s_7!$Lc>m%km{rtBo@o_M164Wg=Aj52G z?PV5qRp}pk7!&Cq%7a~}AGmAE5KMm#>M8<|QQp+rD|MD6p0Udbu}AK5i=gZDRR4D` zWBO#MTZ8wZN~zB#UoE?;wKw=ENuBrAeqyfEOSvZa>(!caF zCMLh$L(FyhlWR|(faz19?pvIEU6dNIwKrG8y2D`t=T1=C-Ix+t#wvnVxS>7QE!Rr;x5HZ*3 z{T5&K9;Q!)y8T|rSR0@QEPb6$P^IrP7!&D#1&O&%&)jvi{k-uK)I%6D)-|>E^%iwi z>Ho??WKMd0N`&fMr+4euX%VKs4E6ZaG8tbrwf3)d>MGOg+sHzdp6aJM*Xc8-O!x=W zUxE5|xc0B3)PPO?8;hVy_sBw(eoTbwT&MS& zuG4!QoH!fPUx)gO@VswpYVAMi)K#thk}zXp?U#m#xlTW^DrXp`Plx)O@fG?{QEI@} z{+SJ;2>(o`Hj|wv; z(jN*DbDjR%fCo#vhHy24<1@})h0atBdC84Pxm-Y_DcA394(+ldn=`-^O4Sx zL-iEswcTi$vS*it|1*Ex_S#(Ru@vejdmv-KA^YL478QS+B;#+nG{FBXK8wpZ=%-rz zg=e_DE5`=uXI&fS8wox^8nmYUSva$qka5ThU1~IHp+1|bpBg4;&#cJ8#QGN_oaM#X z3sKHupUu?2;AhPFY^LFTjacl=y0HvjyL%8?z6}j?BhaPZM-7x^Lx0JnWkbIZL7T-a z8~SOSIhHSl855Roo5X1Ux%lRN{K=bX-T(R-RcArNJAUZ0MyD?7oA(>8@e;JPKC*D2 z4FjT#Ip4hBC89CrY|MsP0b-<;#2-M;%AaOGDZB&q2LsUMbLxa&@dM&q9X-0J?`A+Z z=a&G7AT!3va2n+*-UahB^eYNdP|@IsKdN#8E& zjfwL0X{=7nycZ$$u+z}XBG?SyHdhY01byFy`d@IHe&wT9%D2ncA%fDk{;vpQ&V1|l zhZz$u4GzQ|+s(4?i0YxB8NTUPUf2hH4QLo1gf1I(id4S!e*_6i-!7Z{jEVg))XSKd z?=TNzVm~zc2CJ4@N)r2b(}q*+OYQGL1AaqTm(4+HuY4QgF1b4Ux68M(PVR>;-&zEb z3E%VxW5PEhOspC6)#q*f5`E`DLzV}+SO&FHzFof82&(yRC1meQG2hM>LFKENj0xXN zgIF_s`*pj2I{MCqhBI;hZk6qs?~igG(zoGsS*U!^kRHmndoV@Z>|+FXqCb4GtUZi(li@pn?0e_)Gmp^oB#eDaK2`b;$qKpaO zX%WVR@9S~LI=<6GRM!mOTW@>KezEug)V~#mE_;L2iuuMpmpPBW^=|~IP|mmhO+RCf zZ+)(pF=xK@Z+VC{!?#yT>O%Bg1oiWM&}F|tt(foMQG#;5^>es~GvE5T(gW*+@7%a! zWAm+_7omR5@O^gj7d_DTL#Y4QfG!73YQ=p2#?4*HL24@V&z`svY_+f%KsI zbyY@(Ovc2F{*?#YbupvWDM6}pZFI}zSL)Fy4_2q+&dUr?17_4kCn$|pw}~+37_CkX zGbW7EQl>JCBZ+SNx*nNc?{L1lETpD|(7KCaH0Q3nszxi;#2;MC*M zr~p=bYjomt4}cqqNOnEp)n?Ags*JH&9za{l(|o%Q6a3pSck4T z7Byf-XG9398TBNjp4(RUln2{&&WtWHsnE62UwunXMx!EF-8T$fyN9U(GwNXwR7So1 zjENcb@iHci`g(}DHtKHsI%4jH`n=l$Cmt)sCM#H_-(6!Ogr$0OnjaI?x2XP-=7^Mcx=pu`tGP<9q z3!?{Qx-xpuL&v%{nq4*Pbu=%hZepKDtbQ@V>zsWwHB8L4(Wl)P?L?z;SpB9Ky5f_ryvgVOzENVz=yjeh zW;9)<+jWl78zDN@wb8XdojD1ODqywYgRcLPL2O1>nbcJoy<;&ZjAqBxIY#dqROj00 zlEOIy(WnwuFT%&8ezE~Gx>~MN8NDB+BxJ&9pu$UQ@)kQ~XaltJ1Q845}5p1t39 zj)a7aluIuCp7)&hdEa-ZJ!baz{?WYW+w(l1@B5s~oVo0-bo4=j0;Qu3BALZ`j*2vj z%i7Ut+POW@(OTG06NWzL2C0DJ=zO6`N0knV(ot1H(YT{(i?pmA{j?nxqN6Wh!`FBm zo$pWq#nA;eiPDjiQZ#-Xebpq+>(RzI#bxbi`m!%qhExlj~P9F4N5s&w=N zNy`1v4-Sbe&U5r*g0!q1eY9rCCFtl&*zkKC`dn;M0mad!Q4*!29U>4l-lN|PHO_PN zdziGW9i1{_)*I+(Jrv=m_I*Z2sDR?=a#2+}+GSIqa8#5d8qDHcM@0~$xU3z0b4YL! zI@$n5fgto5qfr6H(G@`wg`=V-uRFXR6}1<1>8L}Laxgtdc z6h~J&BuYnJ5{kwhb+r_Y_o$mmn(OE`lfE`ld`#TuYZLcvF`1)cDC(61ea0oIfcwgO zy@Br<7HKAl=*aupM4v0g+L>19U|gSZ5jE~vgXK1P#pHbQUKag@-xX^1&)aPr+x}m4 zSqepqaHmbw2&A~&o*+@W+#XRi&*h?+s(CI~n2N^t_|YORt(V0|2Yp;F-WeK!F3X?@ zzvkO#QkaS=E_di8N|(!{s#fUGmiNfwm`ioYUcRr9&Rk~oS16C2`u%(8vK)#k4d^q) zpaSx*P!=sqkjUsOFa(Nj$A7)Sw51Ny?g(?qeXf{oFzrrF)z&*qyNe_@ZiT1ezusW= zmKiMW?gW>-dJfa>u@uewE0jg|nyS_lx1h+hNW)9H_g5&3%2KM<&0%pBrqr_RSjoKo zhGWMnplEdr`p88q9lKYMWXI%PgzQ+2pfkhnC5ltrYQj>)3r^Rr5MFRZ}&uWA~G!9Ao!8B%&AIu?G^W=5_2rp~;R- zYod7_dr0YGmL2=H-x~J*S``$%7=}L6h>ec{Xt%*(`*mi7RN1jvx~h2{dnTxAUdNsh zj^r^m+g9Vej?Iayn%A*sW2!dWVP2k#DjM(D^AT0^IyP5mvSTka(Y%h$GbuOg>)83_ z<-M_E)ll3c0ev2GsDRS3e{~XN$C`YG%dcZ|!fKq?v00X?dB@nygsOQRTc)X++p*%H zSRv!icCcf`of1l%*RkR*sz2|q=@!d-B+;?r?m^0Bn%lABy+ysOJN9W}*bUgR8YtGW zV^4_!vSY>hRt_JcW5oxXs^%VJ#eEG`b30btFRW^A$BO%Fs^)gAcmPT68R&IvfJ36} zSV2P3c*hR0RLwociVqc(~(qRr5M_q@`-!F{U@sykqPzQ;l0@uru&*{MQ?zV?{@V6^);jM{26( zos~xkO?0g2=q8$XRvr_f+^mnWX`lW3Dt4?6iq6Kn3oA|ql#ZPoB~f&&=oCR>ns*&L zRafJ@v+}f{s(BqdEv0H+$4<9Z&Fk2(xT?)|SQpQTDH`wCnNd~qIws$SksTW$;>0ml zbe2WAnZCNd@4)MS&B@tgDHQjK!+~oZ%9B6Z3J2Dz1hkvwpCD-Wozt<$-yh>{sE56l zYOvQkR2(1at-qqv4N_Ul7dxySr&@~UeK=WkGX9S@FwT3?*5_5xHg;er-*qqk+3yzK zIP63anpl}~b3EQuNZyOKqG4fGD|DF4(@a%+)?nHx2}R?#@F|ltwli7{ zGT2MYJ-1oV>UhVyh2QN50PgPb%Q2Yr4iqhQAU8*+0w8|?Aa^fYQR!7pZig_bcr;+A zvfNkrrS(V0mi~a9X@uf)6Oj8@g6hb9RV;syMeM8GCqy8lJ?LN;iqA<=ve;L}=LSh@ z#r9QeE%Tp?*nY}{&(Tp5iZ8}}HQk^BIkJL8JRcgbBb(ukg2Q=$|0anQmh zD4vGLr214$SG3%@2`ViuJfJBWZwh{`mJivKX+hFjW~(S?%}HqM8z_$91>*&aswn&F zMX_ROYr08+sBv3Q8j8ld6$_I_wleOkpZ=Zk2|D@~il5UU*NRdBWnaxVNR*D|s4hAE zS&^JIJ+S2UQAqy|isxfL=BEgx&=)u)O8QF?MdS4OI%!$c_Zc?hW~6V1;zb7Jz9Q@^ z^w$ikD(P=nipJ>+P13TazxwZyw;}y|D1H~$El9u(_4?A|uQl$R?#cOcwZ>Fe#vi2noiITor zQ#4LrLsIr@KfULY^N{`{6mPH~_pRpE{p2loggi1`rT(PzZL1ff_(t4J<;6SKT%1XzP~{v zan#vbn6#|vs|O4pf%NTQ_s6xbZf@kvuO`z1)rnts>vxA8rU_B+5n9M}GZ zMg^44e;FiE?swf#G~W5c!lY$QPv$*xHPU|rdyoUUUs_Z^p>K$hDCx&V6phmd>7->% zzj*2&?2P*z?2`@1Ez+ofLbsb)`$-lB%FYipNz0nvt3GEc(*FQ^IIi6mMHPB!GiyIn zBa)=!xx+`+^h4}kry~7Nut(zB%QPyW&?}l*`*{`xO8WUGX<5^k&AGfi(szPA8rNPS ziYoM~X4ZbGMkGleO;YyHuy^kK2k%MR{{{9{7UWioq6)pXnYE8oHGb5MOA$WnwFgG8 z{|4!QgFR7$+**qYDD?Vf);__YK)LoC!lY$QFV>%U4(b1ZeG9I=L8Af+J*lpfUu~v1 z6e#I8CrHbh-nnb;ElB?t?0a$TNs9_7^sky(``rcwO8Pxv(p>s&CVkfK|L3@WO#Jx( z(szM<&z0Dj=2Q;Vf@z{(&evF($Zb} z{;`S)--fEuC4l{z4!N6SR6ucA7$H%*T;`~n=W>~#vpCP?Q>GHfd-+p>v~-ugf2^Xz zye)^J%T|#42=?-aI2BM_{?dfL(qTPHHPH%PZFz)}rOUf*MdL2l7^J1S^#5ZOo6j!# z5?!_i`(p!gf2MqVr0*@*ucSzoz5FbpYRsiN$Yq+wUA`M7Jeb{-w~w( zip%u|iPGhlDOK}aerc+j=W>y%ahG>F6qoMO_s>9Vomg`ly4({=?#5pJ5u*Z%%QAyR z>9VvLm!+l}=eb<3#&MUv-}>?YGZ2AI9q`VgLtC(`9mxI5A&}y-t_j^cd+LG|$eb5q z8rbE!sxg=9z&P&m4iT5uOaDIuQM2>7_t0fKu)o7+v|UPFarQVVQe`jenrMX%MR<=a z&ex^Ax#ceV#$q$jg7k# zWqYu{$$`8!Q7WM9@o!=z3YR5k2@=zoODH)jsK&X+WyxSo(fA%87AGyurT?FSn10%V zUg)v|*qa^5YnPw`(q+j_LX<9trYKOl9MVMdTn>#WaopwY8fj@ROC}gT-=K;{FJtF; z07^6)@&Z9Bptw9jh|=Y)76nR|x0$Nuxtwe(8h3evLt3U!><(Kt^+Al?2qhEaO+Fj? zk6$*mM+!e~@ji6gW0B+Yq0@C+d*f^AoK29|QHQ*sFr<9wl-D_d5$-^hPW`;DhNt1D zQ~04%D`4dh*v^22qby7(Er#C6w6=C}hSuHFx4uG{=GrhN-} z7bg60-IX09aXpCUt}e^ZuBOg>{CYfua-rlxJRL6+CFJdL$$1v3>~LA^uu~6jANfGd zd!bTtfkv8p0Jp|nnFB-T@ZE@?q_u|Ao=(Bg7fkH*0}kM4d1cyln~#pP z#}$pQeMXG5tm*AjC8Lnu14`!N+U4`Dvi3WoR8`WS*AU{k{}cm7RajP&7_|$003i`j1P7AA$5*UX{MH&Ul&KHxEedqt#<0BjC`$0)HuASYG(GdH6S~F{}R2}iPS4Ai_>$NZI zG3t1v_l6P&*Zz=61(dZvqLTR98&yY~p0p`BYx>%W)Am66{!sFL6!IRWe0&sZe@rED z`gaaR%Fb_2kd`(5i1FV%k8}-6en~;z<0chQ=+m27drGH3N&h8CTGsSaF5lb%=?6f` zPVD@Xl#h>M?XhOo{-;KflD?Cq?2o#RZ|1Si9|)zbb;x_l6cr?W#_nq`1y%F*dugi( zC1<_%TV9`h6VeZY(hj)xnUs%@V(qhbUwi3Zs>bQX0Y9~3rc(7lJR8?AM)#wq_9VPIf6Iw%J&e< z_O^UpVxBxQk6ka*{7k)gQ2XO4f#VwE9DE}(k~NKRl58# zqH3PYb&jfeF85C;8h4pTl6O`}m!-Dj)63*G?JIQI7s|RDkdKDNpk9`B64r&wvQA-& zW18o3y`gH%r8-0}OHJ`VX}v6+>GvaUYYr~{7+v;*()+NNXK1o8xh#FaAyK$2ZTcMM zxqN`a*j=OdwtHD;jYR44nJ8&lpJjcl$Je0C{!se02KghxR6w3(rB65MrF%b9Ix|Rt zNattS#@*;ye8mo5yoN`2ItMKbfYOI`$Ui$qm2sk>gyLBBF@`ki^U5d1pb!*n#XQ!jBL!tC$v~>{` z!AJU@Wd0~oT6Sx)2$Z%aJ0wb5Qxc@L%vRT~U$7_8fl#_70r?l(R7J6MsVFUN-EC2z zv~`cEX#9}h5+SW+w(jjWiaoQ2pmci*@<&@#MX_~xj6`W`o2v0+>({6f$8Bx@KW)98 zH@yOF=}@{0F9u^oWyRJNhJxeA*53(56ph>Z*CdU)mGO zwH=Ox(s!^6*Cwb`j`$6l`PVxnGG;e}-I6T9f4zYkKPuh|D;oD37oCxQ-!>?Y{AN5- z?yY^g5?vkzr5^+#e}dR8%D$RtQB@>y`U+Fg_;I?@AT4Y9IRnRRK>E>8+AjwAH|kVC zp-<9Cl=QwN$+v?_`#L0MO@DV;mkW@743r**YoFBI+9z97RnkKdMdNGNg>|C0;7AEg zuf{8Xhhw31FrKYbL@DJ+xupryJ5uE5o#>4pDT9KFH@>fq*A$KW9V{TOUwQjj)*kGL9slY4xW z{wLk#k$yM1-@kerduw+Pl#VbV|Bf&fP+Xo9Ba!XXl@4=sj;3m!%d>ZL3Hdi;v^S*7 zqYcv1T>5`iQhxbIaXG39-E(Fkk54F?*UM7* z-L5p3Wk>k^hJ-z}q2Hs+!BBP#o*$-3MHQEq*(Azdj&7oPE-#L&ajwg^RL)BcDrRS>}cR5j`xU5}nS~_knx;zQW&cv&F z%%lQ}%d;F3rOUITs^+;oizMZR?5Q@1n9E(RwMfg_<&dKJXQ0cWPSgWnW&MIeba@JteTHYxb5Sa)xV*|BQMw!#Q?){e9hX-o zRL$$z=%hRE32cF{#bSj{@bTksB%Q}_rJ@=IT9983(OLfRS{)d31yZp`X z?a7NSf29ar4ui5y8sxtgk%j3kwX$!8C|x=+3S?TLLtEY>)BIijq*HX7%d$0odwk@- zC$&MBXF%B&9r71OsesbUX`-rh`JhFCgG?)J0z8rG&xd)=lv!HBc0`ixosDN}?_Ms4k%kq696xec?2UwJw=CWM# z+v5k#izm_L*--Y03Hd96R6udL${|s>aXpqoWj;waZ8T-d2t-BT%*r zdzmn)fa0s;cECl-e7U;P8G^KCb;Crt#GxVrE1Fz7T1|1 zub#uSE*gng&-)EC>U_y;D?#s@2@NGZmL>02jj|~H>8$j$KbSM&&H0O z59KGBkiXuh0vxg9HeU96BXypEllQsVeA zc0NgL4|u;@tbC+SqU_iOhN`*8SouXksb$%*0ZYDo9Xoabls{-eeszorC>^`QAyIbh z&V;IY9lOg?HLqiLo2uq@>>fkaypG))RyFS!Gc{G4?XY9)K9bz-4AET;|Hm7$V^f7D zJ9d8)&Fk0$ik4-^hR@Zn#ExAE<#QvD-x&4K>|gqgf8}==B+8CG9ac53V>2{W^Ex(@ zB=-#TIyTcG(XEGDP(CZ6YF@{lu~g0L*lbhL_%SxeP&MzYl-GLMvFAh_)4Yy7AEVq% zUj>POFdyGS+G8`6KNW#KuZJm5eia1zd=MuU3HZyN_FQPu7vcAe^E;f~e%Vvy;cZsp zbDIJAnTudql(9QIQE=85l{pPO>Fcg7ul5e)dogaO|P z$7q57ZRzr-g~)c$N{8*BnNeaftw z=<;GH{~CL_RigrUobcaJH6Rrv5lP-hVdYIu?#Af2_lRKMg9XIQlC>qI9%MrE^Cg3A*f2B1XAc zJ9;s)hJD<0Ih22i=ilEt6;K@gtC1)jt#uTQJNhD_XuL=3EYh-ebn&($C!(V^LEa#Ey9N2RL99hKQ?oOiC3$4SfD(F1o~ItU#ZP|?PM0uV(NN39c7RXD0> z9aS{XQN0K+fp>{sGp{2+);ngx2zqFA2yjCM^{3{ zkufM}AEu&;qk!nVbac3?aYsi4DVfE&$5F)*Dblib^m)r8-A`L1Ahe<>_cXWcLXxz~dlEgR5GJbiY`*rgG9bE+#!|*uj=!gpPTYLO_L5>Ykp`veu|no1nE zb)G?5%WOT}xzAd(bv0C6rb9tDQCYFIca%y?TbHOER6LRc1zLhCE4B`dlPGOXvlNZnddO5XZtG!#G_sZP+VFvM z%rWR_0#wY1Lcu{XDxf&ZkC4a?7w>BIR9MmYwc%+^(YT`-BxQfKnv)oP7&^KEDqb+5 z;9y-;kXNgw&mEql=T$m)G*{#@=id1@*C8?M9{n|J+k5C}B2>HB4XSaTqgO?4){bJND2MP*oDyld-G(nQ+3Kc6;P;gjtj*duBRq5z`mChZl5Ofyj^=M^;a4pngSJ@;!toxkP0Y{P86DSw9zC{I{MmBH123qn6#`N?VPjp zW^{BjRBTN^!HEtPP#m4qWN&!aqaO_ll#YH1D;jsSRU<8XN39-TgpO{3ia&!;FjVYz z#nCAiRh2#Z%~3SI*M3hZ8h7-EMOxO5Y6h3HcTR4F%GMeboN7`5#nI_e5{0A6oP?rz zjw-=YG|y3GE0eUW9UWad{3LXA8&u}%P%tb)1r$eThDnr;+N*n#JL(`B%;MZ5yD|`? z+^iinjy>jNbaXpZ_Dw*+aE%Hmj?M~_C>?c+C>nRvT~{>jXm635wWCYt58ekI-2s({ zIZ$v`ii#?Z&T&YTjzXrQaYwqLXx!0ZVbZd8G^D=A{pjdUs2q%YEs~%Dilg)5BuYnv zNRrp1%0Ui^EY90&$0tb3+R@}l)r;upE~q>$3nQk zszqAXj;1V~I0qfw4V94y6kKRf0mad%2#L~>+`XuAM`zn=oY$jsM1Qk(v~FaZ3((O$ zP*t#-CrKPP~MIdV2)@`N|$8Ftikk&F= zk3?_9-glS^l@H`V!MG?@QEZJDrKPR=EDDsirkaYzZQXB>)-qe$J0Fmbw(f_@>3D2i z9i}RZt!vS@H>9n{gNnwx^>|9rxUDB_(pqNgmd~~>L|YF)Bu0vZ7LgmYN$(rC$6~)#>v0`cKC5-}6GFx|ExTFegO@qqCCKTKlrz(oANfwFH)*?;OxUDxyQf$5Hkk~R?r|$VqKeY7_ zR2Jf~b(2X|6kAiGBuZQFMHG$OTBa)+--(4m(pqL~XODxfLt76+(MS_^KmRISj}ZZ%cySp(xL6Zo$;FxUH3vFb#Nv^1AhCzw88fEqKk-!OFfC{%UD zga6Jj6_75g_BKfrE~~nWZ=F?A;{Jby?LTqQr5RbAqI$xhx+O^XcWTZ#Qm7mybi$c{&u_ zXHo&h zWR5(SX9&7*S^0683Zlkc9`BHr?lRzaC7L?rW7f;3psKS81y9APfZ}q1Ng|_rF8hl> z>9U`r#(BLQ5mYqp^0+W*=`O$VbNOBTmWR;g(@<4_XU{Ck$4B}`OVtrg9CuTjfyHRUol9Oylt3LL5`T|!jVT$h!98>+^7sSfFK zuLSAoE*l&lmruv9cmrL|hN?DrC0bxp0qL@GheM)pS-B&kYM#sOP2#*g-b#(*y-XUE zo95F0dHk4n?%Ee!&VkCEQ7CvVMFphGs;{CX3YS$*6Rps}JzDu&T#fTwE=(yJcNxWK zZ=|`by3y}SR5)(-(dhD7sG5|5f<-|pptv+5BubZK991jCEvOn3RW;A$#<-$+E-Qbq zNlSNG;pcL}*!%_P@;Ruw!GVG$Iu(#EE4Qj7@2Xz8HB5obd7;BxUZJU)|8a@0n)pa} zd0pJ+xV*02g5l`$d8nF*d;IMP6_75gYJw!nURH-y&2?G%v!-hPE+^;|m+sQ{9B(&g z(G+w!7ke3of~8R^pt!8v-DTyUHU-LFrkZH}E`JGAZko$AN5*`5IdNL*D|Gn+RDBuNR%#rZsMrWp$PAh#reBz6uD_GKYiBMWqp^=(dCO!S%>HNhqlDg-A1L8AW^ui z{8|Jutwk=YisMu-&87bzrucZ;<>#VH3#v+TpdgW=0Zz(mtX0s)-so0`nmM~ z5wwa=-Z%zbz64e4O(<9sCb;6V>F2%Po!im~1-87GYg3e)*2~pD`dx|2tCxR`F6Tql z20VK{k5K`|HnjVZI=w{fG%H#s?QQo zuuc?^E~_CyRi(?1#By5P%j)w4B+aFNFDK2d+=ea}K=nCsDA-_=A;o1|jYQ$Hx|ObK zg$`|bkN?@r>ZAQ!`d^89K3x++m#;u|#DannP2%VruRcy_(q-Eii7oHt!7X?B!{Egy zqsv#Jx^Dss%EJU#df7ikqI7v&RMiR{+VUP*obPd2JvaZIANVu6d=08Y zQ7EVq1r(P}Uv;_Xc=cfxk*JqYJwPP?x63ocs?%InpJMnt_w>Jf+X?9Mb*S#6LqV-c zaK+__IEk{CBf_f2dI{BsTdL;Y%TqDh8_Z=^KXka_;0+(6%Qv992lleTq5|@Vb*ekq zBr=yP4CW}%#Q9Q(X}K{qZnhhj7ge?OZd}KRs;zLfpss4m3|6mGlepP#T<53~=l!rw zb(ff`^)y*-*EnhTb1dEu9aeWI3BL!%e^{q_Z;_jI$M$ymurqlfR9|jD!PkhRK|kJ9 z-6=tm?3nx!HKutTyCA5>c^$hTrD|TsF0@t6>)1tcRr5MFDyC|)9oC79ql(5mc1c9l zypCO}lO{VhI;d*h99Hi#Luy$bV>bn~+p%Mdp!((@6nrlVD96|+jjGCyU1zJB*Rkv4 zs^)cULQK`Xj@=MdHLqh6BdX?g>_%PHW;<+!(V(L7jzv?d=5=h6&}7FZYZNDsu_+O$ z;SX^AtL3!zE*X3NqvgO!-&w75cHq78j;)E}1B1Guq_mw)Vmw#`0dB^>=hx zjr~Aa+s6!9&uUt)(6;SXGo&*0P#2bLWv6%nJ*MPaUqSBil1NR7$iVea)>;k770(ZLOgIo3Lue}ks z5(X}_eQ<}IBl?0S1g^E2hC5l}PBVOP!ylfBpE9-i00zFFaUa6KmH0%_Y%>p0uL^Q?t&FC)Rx>O*7IxcZXN_2}2U1ocCE-W;Gfwr? zMS(>sTNHi@+FHx;|Mo+>4_I5hKN@q%gjHK|ayq;T)sIGDU?NC$&ek4X3yP#)p^^V`B>_V%Hq57FH3|y^K z6~*e)!oRfobczC{)fu*;ajP@qipH(Zijmebt8;pcKLV{Tf$EooFz~YoRZ*&G-T@+R{ZuLz~ z(YV#cB*{;_tCxs4vf6@QFZsxU!!7h1hw2p;3|ucdq4-@U79sr>M#u8u$B| zM%w@3cORpn6Z(AzsyCwF(kPWu{1zD`O25TnMdSUoHAUloOGr|Vhm9hR{APFUy85=q zCZg4Mq59`246HCjX?gAXAxxsQ`lF_3+}2MdFa7XVT4wd1M~~@+ zR+mEcUpX+aIzm;HuKwQS$m?b>-0$MZLkryMA2uaRtLn1?S=||kaU_Z2v_z^(R*kOkDZ)%|ou<5qhINo$$a*s{}KMyt!ArT~xCO*U0gtR5^x z+10*r3Y1p+#T1QO?H^S%ZgoI}w3b;tD(}z$T74gCj<#XocPXl(SUtQ6&g<$C0w=8= zsZ+A->QO;O<5rJKk=8P+*X%L%Qnb1PYKA&6@CQ*@u{tD9rDa!7j42vF0K!p4<6S)| zqG;UeP@S}vSuF{Ef`kq$q2_EnR=0{Oiq$g{R9aeP&&%GBT^(U68n=3up=jLd*UfQ`mRWsg(8X_~)m2b) zlLZ5Rk5Lt+s}sW{N~c>#?ObkLfDXOA$_30)!@3fjB zaMJ1wku0sww5cF!-0G}2X)UvQcI?~z(CQ~pGv9*H9>RfQbzYQ8Gn{Aj#fYNuu3EaH z@dMx`QBYcaDMfK)wFR$V&eTS*JHgdZvm^?kwgRd6UD$-_`CTZOvW<&u@_`y(!<%tM zpBBklk2yWg?P4n)6epytaUgxW`_l;U?;f<)QhLQBzjFPEE&#{Ir;C>r;>PC)(- zznA9hIvV|c3N_W}H#bV<6~AS15~bhrn4)pN6(U*ow=$x{alchMY5#}c^H*HNj)%{n zW|Ik_ps=C%bu_9k{eDG~e8E!ll|!QRyD_0?-0#;GY5#}c7i%}&gnmDVnqPDXb%|3c z#cz`rQ~Z2u@?whjSH75%et#C;*jl}N?vzQ8|HJRRMEPd)yB2Ex!RteJn@TBu{|u8T z`@2(9H178=l336A@%xuUqV)TBg0%m`Z>M|qT!VhUfZFyE2xNDuAP#0UTpy3+Q#ouGbJy47DfX`Fw~&c?#f!D2Z|fLn5SQTEUacpDROv4YjA~ z5DEn;PXU}FGzmDxAu$tR)g_H*BA^6nM|8bZO7(Z_S0?MHFVh2J;St3y$rWeIYlq(n&BQ4VkR?U6z zY6O%+t%2vkF*fBXE4VyNq6Cc5NXrCx!RR~+0Tobtbq<6EQ5rsq6K$NJO2AcORhaTNx)5F zRha;t4{SFK0o71@M;t=o7}Zh$x0xhL!0iTUnE+GUU3(P*YM}PMFocFCC{F?08zfNz z?iH)b1lUqJ`~(ElLhVB~giaB83gAI&cfd50v`hf_ai1FyPzSZs4G5jCQJw;LTqjYk z;0dv+On~7VCs!b#9%^T%Aaq8AYAJxH6C_H&42!f(fSrS1WtZy)sD0jq&~TIT6u`5B zDgn=lRb>J^9q4{N0ve%qeh@-u#hU@V=#VG@R)VxlfL9t1_zVF_sD0gn&^e-(vVvEm zR7?V16RXMuczeh=b|yPe`<4!&^MX`M0W21p1S}R#G68aehYv)+S5W(20zxChqL{oE zy&EG@0+xzZWdclCI^b3WY=qhmA`rSzNm9n=1AA1#`3U$LYCmxxG|Cc* zas`PviE;%Wi&bS>!CQ?tEJwg5sQn@ep-XJ4rL5rdFo_bdRwFGF;Dm*bUx|Qkpw`ZT z&}Ec{kK%GIzqTj=MPgN%01LMrc?$x*h1yCRLSuAE5P))vLOwZz)XO_s~&j^0h^(A6P^cG#wbq#Y!sRVY;;J>1UUG%zOxYU zJ=AW&^WdrkbajgI6u{3Ki4w5OCM^@-q*hun z0)BwHb{d4P6SX9uu8m2>1fXuutO0WeA0I}*k5HF~E0_?WS_&Z03?SE_z)UOne9wVr zAmAsc>lTL4L{UotbO};1xq>b!(lP|>EA0XS2S|-39bJ}2Rhiy=IbOb`Ti#!Ezq(;Rg z;3$$ZJ|A4$&waxA73u~%5W3S6iQ;NnHz-b`1RNhDEz=4n_j|P*SFj!GPL4w8ZkzIy z6`T|%Q38f)q-6putL?on0(L;%nK=+LDGeX#a$R@2pi00nv8qgfx-(bZhk)OpE)s*# zR9zAT;B13L2{A8DJmub7l>750u0mP4FvoFb(h5< zBtN-O0GFD(14aucnE)rw+pjkQ{)D=5VF*2(pjrxGY>-5`g0W&%nE(TV=1U0J33b=m z5PDSPDS&IN-2vB{q-6q}@Z)DA5bzh&O~IY~ghqJ^;3k7axq``I(lP;7I(uwKz~4}J zC+_4YBb28AZWGIrfZJ^f%mmmzGxu=>`~!9O;ZAmCrsGbY9~=h&>gMVYdM-@06u@&rlYr+O5;FnL{QLWz z2xtX$^Aix78>Ku2V8uw3fR{vICctr(tMU=h8tUGNKxm#twG_Z>8i^9{I!PIyaAHNN zw-K-h)V<|E$g)MEyj(AilPCd8#Huo_pgufd9|W|4x@A!ay-cO>QCzNi@J0me33VUlKX%Kotv{qTc=P4>C0c*voG6A}pU-v`6UQlPpA+!i#G{inAGD(tv zVuQ3yfK!a~CL*9c)K!Hcv{;x`R!|Y7ViHgx0y6>Ln36LT0Ue;O!G=&=qgo1}&LU9) z>P^xz0WKOluRQ_+P`Al|&^r;zQve%v5+&ekv8qgf+@de=Eww-{)NM&YXsIx!05&If z2YhdlmI<(NN$-;pkOy_Ym=IbPr#uDlbA&{>f|O2LCP3iWTk(Z>pd-}%5roikhw>D_ z4k1dwZwU&_1h~?E0&lzmL8$xJg3!t!ggz2x6~JCGDkcH#MPMetgjCxS1ayJ=&JhTG zY*8%*5Y$MNfKDW3d_H)4^cjaCpexk(a3HkW7K!3=UEe)Uq6F+MR+VW5leZX8BA^@8 z?;nQ{z5yu)U5o1XGf9(x-Uexz06Eql0R(i1`h)R2SgTW>(xN^Q5+xvC1ZDzUwC(-( z5wJJZABy{6oyb!F1={X_LrBWF4_2<9Fa-fUp#De=LhB8YDEGl(DH7!h4!23mw1T-C za|R+{AE+Ocf>2S6@{|=En;=mFj<38AAU>Hdwz2ql{X++b2M37BY*mI*Lz&o}YX8#oZ^ZwW)_tL6Yxf>cZb zrld&A1o-`#W3EKNK~R5p5JF!!2e`wbViIs?g0xJ49Ye35ihw>)e?OiF-!uofPlysQ zHI^-4_O=~gBOo8@@yF;w-#L`097PX@NtA#`G}1Dy;L7PgZ$iMqQ2!L32U~)arvRqg zBuc=OVpW*{Z_VAG9j1Muem0&5KZdE60+?lxC;`uiz)XPAqek3|fPPRv56^?GQL3c? zo==e|0dvKwG6D8~bl>9<&>!j-;CYa;sFnhlZ;~hhFB_y~0z6&5|6d3g0QHOTJlH0T zDS$VER7?Wi5Ua`rILy5DXap2M{o6K#c2FsN6n7PGS)@up+$1d%VBnxm7!o)H>X#c3 z`dz0y1+Ywr5>O~s_1}P}f0aiD&f;A>V|9b^}^&f&av%@q5^&4WK=fo&4CkKCK*8K`r{kkxTxPm=*S@;#K z`Y$y_^S+iJibP%+uIvIJ@W4R|Ve)hTNaMZjTD zUl#?vO>=;nFcp)4TCx292K3b{!=vjFa5&U|g)3;=96&xZNr00zU{~zR`w?&i)NjW9 zvR89}Z;jno@SRvyrWLHceD+iX90~P5YoK>%4)9}Ycfe0JX_){Yk1zNM0Y^dojyUMK z%>jNjshDihc7wD`fQQCU+5-VcL;c@j&^tB<*eOH_*qO=}Fnrk8A0glvXlP}F-bvJw zhiOBOMa2Z50Zh^|t>D9{*OemRSZLVG0KH3dfVMgnlYn+2FcaY4osm%pI1U;*raQ!IO(o7

    xI4F_4E?;EB(r9}rsNtA#C#i}v^x~v&;ECNn|h5o7iGU%{5RQSqzeRZpU|@_yxq^^zk_qtcvNfM0;6!LR z9Rc#|y$aw|eRsfVVbU@I`tRA}Zv=#);cN}`K9q)!bR*C(JVmNp!3dkQOn}F?@4{D+ zfs>$NWE}K^g;@n~o=L?d;CzF$On{rKAAb-5L!sf)FzEe6o&vZyNW~=J;uL9_0PEHb zIR*hIL&Fs|=mTPurvS!SBuao`l9mb3r`_Z1J)~2h;Ti+m}-H3lu3CCz>Jb80rv?f znE)Mvi*gZg1~fdPgMLh$YAJw+geCzGIV5HRteRi?A_C5Yh9?uCA1Cq@z!NblCIQpM zsxkq_bwrEaEE46l=sD3h z33y(tD$@#vjJmWd0?vYlm!qJE#mbcxydmtBs4^Pyp#4f8Qvk)HZxUdORb>LSTmNea0T)0+RSNWT#mW^xg`i46rA1CM0UDRgW_J}ALPMho z`bdrP6hM81L z0)3Q8c?#hBD2Z|fTZEHLfH!t-Vu$I)(6CJhUA~K~08&(6xi?KYBxV9UHYYELfJ>m^ zj|AwWMVw{3Jtp=ppQWq4RNXXM>Wj;Fg2f zc`zCp+u#bWXa>;OI<_02aSw;I|6V~~{Uhz~=MiujG~xwMzp^<%dyR^T6*P7rDdRI* zw@4#94=#tsE;*oI)f^ybQ#A?b6elgy3g$+%%MdUI8hc@jIhr`jr|?auNTG?Kwr@g3Fs$Q zm1za9bT8Jt?_t+R0$XyCM^?S`jBfF;3{Z5MFU;ll`DXgQdCR= zhT5cM0<0b}xGw_6L*too&~Gs)PXP=wNtA#yL|`Vs)kD6Ygn+A|@!T-zx5cQI0yrl~ zq6C~HR+R~`qj#s{5O57NUSxxQM}lf8fD0@VCE!Anv`m1aW6eSYTnml(n`HI7gfRs$ zTBl+Xa9NPFOo07|y?Y=6u7k#LDbVlLC{F>5O^_%7S6ZZH0&M!^l_L;vJv3f#f-YYf zDS&GuR7?V{6RXMus2uz9CIn1?#+!nm-)~Ya1#qK7q69<}q-6rURP@7A1l$0Pw^^V+ z7^gf1a7&a#3Ak0PDidI;GekqcL}@z!YeFH3s@DSzqqt1qP`S@Jg7pOn_alZb~8G zW@ucjfj(QOJY@w7F~A!Vu*fDY6X5>8$Fno}7HE7o4*IhOnE-?5 z9IPSWPG~GQL0=G|JOxlHM7e@8v8qgfsdqG9gMhoBu`USut7bERYKKG#s7a8P3DBv$ z&1eMN4UJz}pv!k@loceSR7?UKv8w+DJQeKq@P6#gkb9tUvkv+~hiWN+Z-piS-(?Nx z+J4sW2)Gv-x8e#G2SqV?sra#(75tQ-z)UOna?p462r!{>2d?0)Fy$#L_*H0f1>3V; z!P2{`*(?3~pz*H+=x+W6}eV+zWpf{=W{}Vgr<< zvm%~`s+ZJWXF}jXNVbpqC7tcYusEL7A?7AcgCzdC5g$^-WHD^;q(F*o1RjE9ZqwgI zuGkx?u^2XZQeK2@1RjQDUd)d)iiNm?Cv}Xot-vFY#1Bh->|JboDY)akMtGkJ2OfoF zr-)zDrIbTSoue-4F-Uff`z4J|Cv|a!z~hkY8uUxL+#(dW*G+dxPe8I;)GujFI;nfi zO_~nL?zUf&;iQrFPPs`>Lb8YMmo(Nb%;LDceIjmB43hiA{F26nSqvLIsb`#R1fGIq z&y-)%RjwN)saMcVdK!|wB7RAD9p{6Sybo&wGa$KN+%M@`J1wcVD+Fdja{r)T()Cta zlBP2uFbk4e)Gz6VXj;+%F*oTMNFHGOCEXZKOFA&+Ce4QALAqbkq)1v)A6E#>fn=YU zU(#ePEh#_llAeWRe#$RtitC2O@s{@ux=GJLvTwvM>6QeGVS^|2i?WTt^N{Qp_e+v5 z$9YnJ+fAAa$pJyXq&qAY!v;?((Ah@d1xOY|{gUo--6%V8RPkj1dUlR^=;5wIW`iuono=dc(yc#`gsUV`LdzNGuz7$xa&k2D{W zhx?KqOt1ttIO&Ku+X%c2$sHOVde4oK*-chos@Vre*1*u|YTKeMpXt_%-7Fbkda`X$2&&^d+rK zCtc-{RzmVBU(za_xnYAhVtkZs1U`V|__&|FL^{d)F^a&4kh~`7m$W*abge4{RzdRG zs9(~j>7?siA@C6-ulFUbO(#w8NC`+z@FlH_v30Y-8*zgx1U`o34Yr@X4e6wbDOMry z2_$dS{gR5)Ns~=CX*DD#`(DCI(@8gLZqgb^-t7CLt2~`_i%0qtlDGJhD%~Zp;=B>J zI&35G86dF)BTxm&SlBP=pST-@|8RRxSxg92L-HwK(!YY#+IwqZ2Fu9_)If5EAL&r}rVvk> zX}C$Xkeq4x*gLe9&0^T#Ynqi{8-Y4VK9l2@w1-#|PnxZ{N%fGNZTKa%O|Td?cq8T{ z*hZiMlF#~*I#?`*4W9Iz#x??tkbKUU)G^Fr*x*Uen`|SHgyi!HKYLv?7Q+Tln(MHQ zfCI@FG{2S?eTHh9vD4%-N9grwz5>K$e=Z1AL)!fYe( zH6&m1B^}_f7&ds)e2Z-aHbHW}<7Y2F!D86pNekSKz&DUw5cW&z=f)^WuNZ72@GT@? zvHX(yhgl38ob;Nz5%><0ulbS&h*N_ny>76qz-CC|Z^3N-t-3=Gu~-ZnJn4-D+X#FQ zN&H@2w#jwGX;ttygY=z|8nxDO6qAZ3Dp7c(bZ3KRX41=Jzvt0bkZ`*P1**@Wxk}a8^hu_ zX*rwc1b&6&^01%1p>a0||KUmR8%zjnhvfT~U(%^T7Q+TlT9IHIfgO-snd6sqdX&Ym z!IM5P*hb(tNPgf;Iy0U0VZu%N9g?ejNyF1gA8BsVACUaW@UwSzoW-!g?IldM5%?35 ziG*L0d^?{feeAeNJ0bar=9hF{gvGGIlUAE-Bk&g_SNoDKNU<0;c+wh&Z3O;?nxU)n*+&pzNB$+w=(|2N$cJ1T!7?yU((gVw4@CN6LRtMp$(Rwy=&7+MF}^l zH6)93{E{Z5lWfgR+5?id;g>WqomAqH+CZ|@mozDzROXTPgk+g7X>ydgVS{(C++-WM zZ6R5n@UwSII;p~OliESDQu9l?HJwxyc9ZskWR>Zcaok?D<0iF-WQ{NB&IpTP zgD2I7*+y;$NY?t2?n$v2Hh5B<#Wr#SkgRk3>`jfa7&drPgS(NN3(1DCU(&SnMl>2M zD>o04jh0{1!(kS~1}8c0Ms7z)I=&?DrG=98mBBW0gOJ3})_raXo=mV9HaKZxf^Fn> zg5=jZen~S77Q+Tl+N80K+|H21UsdHpnjK~_Z1ALSOtz8R1(M$+{F0t?SPUCH={t>W z!S@7k49fUr7EE_Othn<_5{6Z3Yu^dqHxW<(ITH!D86pq+b(kBX>VY zZqM;cD%4mE8$4-;!8USxLvn{N>HP$YVS^|AmS7vX`$O_~U(yE}i(!K&{h_gqTn&nWg!v;^<>9CF510ngB=9lE%Hn2FJ^tZ`2au0&! z-@c^JG#0}KPx{AU8@YWT`L8c&t;u58;7Pl}Y$G=xlDkYld+Qt)!-kjST!$OQc2i_is;ox-hC4HYx>h6(_0H?bz>4&(-5v09s zCgdIoPLH6Uy{+k_eRMbJC~)?P`X!~(Nj+n3($V1bwEdEPO(*s8NXLNF%a^nxowT1v zIu@M$d`W)g z%(3F!-a#H|FgOSKkp|`%EP)M{kRs;h&$_ovxGbA z3i?O7JL`rs%bj%xJrQ(gd*jS>XFYJ1a%cO1{;}cCdg9D>XZwQwN!XqB!dcv%?Fag5 z&7JkeSP`>9nd8n51pU*9J39zx33t{9^v`s6mX9;boec#2^PoEm z;mmYr`1QumQ||0A(AOI7>~Ngf?(7KAzX-dtV{jICXUBrRPIG62a29iC$AkW*JIOf# zXHj=L1ZR#r3xmEs;?9QREaA>h27QC>&Q8Ud<<3q6y(s9;PRE()&W7PE<<8Ckz1VPP zXX4CuXTw3a!|rSZ&f@OuEYM3dcXl?;V(#o5&`aG(4t^Q3H0n;z#hK&I&I7$H;?B;; zS;C!-1if5$XBXhia%UHUUJ-O>7vaowXQObIa%UHVUTL_qOK@hpvr9qe&qbqg7I(GF zK(E%^*?64A+}YKj*SM3MYj75Ir`O`lac9?oUK?>|*W)bV&L)Chr@ONoab~%*DCqS; zcXkubOm{W~XDN4fE9eb|JG&icwmZ8M{@2xg$2n28Zv&reVY6&@HxqUzx-&`)ND&3h z42lJn5fl*%v5N{u#D)sNihwu*_7=P1qefIjMU4duqK*hwga`;o4MoHP1Qisey!Tw^ z_rA}(zyH3U`@YV7PLkc(!-|?-J)XWC{Im9x=d)diE`wfB2~N#=`|VF z?iKmeeMqlOQ+ZK=dJyS#aq3}_M?EU4P){JeK1)qPdLyAdEy|J4h{{v}>Hqn;F;TI?}&oSu2W4)Q3oKa;cf3BJ~l{n^V*$qCE8} z(pv~^mMBNg7L}MK!!`WorqU)6@^50<{e39dT;8 z$fH(>D%47(|H)FTL?vo9(*L^DMp2Ra8R?xV>K9R-`W5M2g!Y>#M{W|8sm)05&QM!K zKD7hsJ!xvEs6g$4t;MN5A}-OyO(LI4z>cJ;y+j3SZ`d_)$`pB&C8|*S!futN+K5V25_YXi?I$Wy zDcI2z)mD_J+QF_1pkaSej%qI|QypN}XQ+-MpXvm=Ax#}1Do~wa$Kuq1B9A&qRH3@S z*0WSsQHkmXJMK~ki;7elcIy;ni}I8MyD@-9)k{>ST-f_$sAEMw)f=|Dl%bEPz}j)J z+r+8kMIO~xRH06Qoy=1GL?!A(*!#Iue^HS-33e()oh-^zr@(F-K*On`95p~xrZTYG zWvJ6cK6N_m{nOMLq5^d$?Dlc$ERjc@EviuG!0wQx&J~rYfv`Ke)On&Jbw2D)De3}I zo*D%EfB+f>i*nS3qB50*-8n;DB=V^tun$aA7mEtiP}m2>sY^s2b*ZRAT?V^LmbzS2 zqOO45)uo1siqw^`yQQeBM0x6J*arvDFkFPAt88U?$1mbyt)qDI3$#HGfFiqu%xho-1;qC9mA>>dF$c%mG2tEfzkhkaOv znjrG2iLeh(Q@4o<)a|g3h*S58JnDW?g?a$?ky$D)Dp3!@?&(qwiHg+2u#ZYnkBIWr zqp*(-py4r5j(S{Frk;R(Oon<@|?XkTcQ&6 zHtgOm^$zUg%hYt(eKXX%BA_6cd~eNln>0CvAPHACc4ABrl}OxP!8sgFb@>SNgb zUFs82k@8`ml%hTr<*8Y)PY$5rGf|G3Eh~mdewWvsyVGm4EYeac!E$s6G zXjmu8QR_uz>POh;XQ&M#pZW>*1!-!ds6hP;dr+MEMdVSxiYnA^um@+UO`;OD8TN%P zwMA5{tXP6ZZ8kWr>Q^KCo{{QTvMWR2$eg2GFXKq8zoK zs7$3`kIGPOMLyLI_DyMOe^G&I4|{Z+>LBu{PNE8R0PHbY>OfJ6Itcbym+B%aQe9!+ zoT9pk^3=hw#|6-;(xMz?i^`M(`<4vVUF1`T!1mJAp`rrS1NN

    M)T<9WJU+N5CGR zrH&MpsGhJVxYSXiB6T$Ei7DzBQJ(4r`?dgDl`G0o$BN2Sf7rKYsFOrKbu#Qb($oM^ zfy%(XGftf$@~E>!73v(=cV(%8q7rpJ?7LlRkf=yyVc(OYE)wObi(%gzK&!e$l%p;a zl_|La+?S!Q6#3L}*!QQY5uyT>gZ)69x<=$t*NQ6C^|13<>IPAXx)Jt+E;UM2q;7)! zP>LEY%2Q)tKO8`-8Y{|CH;c;DIM|P5s9Qun<-vY5P2DOgP~%}g7N;hNJZhq-Lfr=Y z@hl}j;~y_kcffwarS23Jsk>l5nWF9%<*9pMPYR$_-7Csb_le5X{ji_PP!EWFDi8ZV zY3e~yfqDq`({buykw-lus!)%@ekMyjCMr>n!+zGKo)8tOCt(*-)Fjx?`_xmgUr1B` z5f!MXVZRuso)LM}v!V)BfITHkJtrzrlVQK)QqPNu)C;hurl=Q1d1?ymmjh^3FNt#0 zR8g6F8TKm~>J^bsy$bu)G&N0Bpk9MLEl#~I@~AgN6{-mPwJi0fs6@R5`*oLkTU4ap zf&E5`nl8#y@4{wNt9nnAW9@xWnfd_sn;B|`$frJp{Z^WqDJoDO!G1eVeJt{*Pec{U zhy6~L`czb+X2G8BQlE*6)NI)Arl>ihJoP#3_X22DUx;$lm!dND73}vj)Yl@PnhX1b zH1(~hK+S_aBTmg1c~nVMp}vFtVU}7TDp3nz&vdCpq9XM@?2l5^5>cL73j5;#TGbDt z9JNeTrk2D0Btxwb`P53-ewtb(Dp0Foe;TJYh&<{iQH9zFdsdeESyZBaf&H0F{VFO_ zzrmiJqBe>0)MnUo0%%oRL^-M=DpOlwf1U}{qNT{Es$qYTrXr#ORRjCWIMqtzQMIB9 z6@~p(mZ}q#sCw96yHtayNX1}(lcID{o{Gbs8$fH(T9l(2MP;f9_O}_z5cyOB_PjK; zm#9GP4SRl^YKFa_NSUw~rYK94r}lxpD1g>tUr~-~BPvr#*xzTU{X{;Mg1tCRwG|a8 z`FXx1PVF!9sP>`?)dBX>EY(p|qB_C;!KDrm6{*g!m!+r!MS1EV*vkWGExL$uR98`% z>IQp7hB{c}Q)$>M)08bLP!8->ajLt>qYe>Os6%0|&Qd)@CF(HPWtTc!RHTl8y(UE+ zDaunlVXqCKwKz(YqmCApsbgTT%TT>UKIOt*pQer#6{y~@e~eRoL>_gVs6rhNdqbA$ zD=JYZ!2Zdl`iY9viLf`OsQ#inbrS5K186Ny7Uif@L}lt!*uP|`0V1Eu!2UH&ohB+! zr^Eg&PMsn0s53MYosveen45_Jyj%`SDWs7MWjy(LARC(2Xj!{!jJ#RZ}qYlB2( zYB21r8R|ljPi0~Mo~AAm6{sPw|Atu>a0bBSb!xgS{h7jT9BAYheEqr>+%w)ODf?bv^8V zv(ycu5_Kc&oh~&>RHSZ#y(>kH7Uiiiuy+U0T8xE*0(CQ-syH=HRv~;Q4L`CX$IMpfY4pE-E6HX+6*5WQvj=Eb^rtX1LlcDYv`P6-ITBWJ`MFr{s zIJI#qFY>4dMHT8HIMFQiu&6{m0;kTU9u*a-$KcebsK-Tl>Ipav0kjrRigMH>QJH!k zPAo&cAo8gf;pl1VB~gKT8BRP-O%r+4>!J$vCY;t;>Mc=;nhvMYrQQ`4sSn^ZrKlOA zJT()J5kPD4u_#CRqB1oLP9j6i7Wvc{aP~@5Uy2IUS8(=@Q{RX@YObh4&4bgNrRIxD zR0)phQs0S+)B-qGidrbjQ;Xp26F_V6y(mX57L}9dXORW}_s4|?CORW(VskLz0rl@tIJhdK9y8v2?A4NH8gQ!gX1ZV#Y zwNd0#Kf`ICrhX9>s9)i9h*Q6bJZh7uLT!fAF-vU`m8c4wPA;`oRHS}~b3lsvLzJif zgwr{I)?%9|M{O6CslVVHn4$g_`P2?L2c@ZhL=?(aMF2d4;(vy z)>0GYD2U2b6&xo+wGjDKOE}%rRJEu;Mc^C~r)oqV)k;*MYT+E3rJ|w|RR^bsOVx{t zR0EvDQdCTor*t@n2hdu^MLDXqs7y7&IU++fiG0d{b7Y!IhzitRaC*k6y+t0?EUHi@ zoTIXoB`Q(-z&YBb_7xSWHgJwfQAtsr+7C{z09wnGC`Yvwm8o`c+zhq9$fr8MIW|po z6cwmWaC*n714JIxSyZ78gwrQW9V9AIUEmz&Qe8zwsvDf+Q&d`%r))TV186NBQI6^^ zDpQBRIUz$GD)OlwaQdaG!$bw@a5yK%sa_(Fazz#DSUCN&RBus<>I3H_mpV>Vq>hJk za*FCJ%2Ox6IVFJBvY#kNohT|({o$ONp$3V3YA~DuY3f2zfy%gL6)t8Y%LqYeW_5S~%xssp~`~>UuZ>UFrr=k-8Dic`0g?C{Nu4=llR#%h947 zHAYmX#=^PKqiz;esBv(zS?U&1iSpoFGLsHZPQJ$Iz=i&fb%iBab>UL3? zx&zM840Wf-r|yDtNt(J_RG{vGb7`EqSL9Lmi7M3na4ySI4~R-s9?s=1^`NLoJp|{9 z6!owuPdx%>SOBf%qoN%3n5axW4(G}Y^@PZ$o`iE%nwlgkP*1_RI!^sZ zMO2_(g>zk;nkMq7*F+WSbvV~&sW(I=stD%>mwHoFq~3yaV~ToPl&9W-Gb(`Aa=Iu- zy(=nH@4>k#L%lEZsSn_cPE#{P1?odMW8&0Ikw<+bs!$)p8Jnd(5tS$(&do0Msi;WJ zf-^2feJ09Nv*FwlKx;Wil%qZum8mb_cp2(TkxzXE=hig!wWvUS1801knk(|CZ$%Yq z9-IkTYQCsMmEcTtsqaKZY5|~Ow_5fPT??pLkv8YTffpbTO`a$GV%i!FZ zrdEgw)Jiya#i>;yk6JCNP-QrGXQ?%!615i2{W)r#s7$Sg^FW6B5p5nTP#e(Z5w+qc zw0SrvX)QORO};|?j5ZIXs9(_LKDG8&w7JJ)?KiZ!t4M7^n>z~BX0(}@r?#NY1ht}q zHn#>Pt>so&Un>0$>vKO~%RgYvajBiKW(Uw(?t(STr*^~o)C*J%SiVbD!TQ*zTEhCs zqiSHybg5cc9|q8>>tKE0Q!!ZYyOa*=y#QKuYgp5LstMLR9<>*&w_R#)Sa1521*_;$ z`@nj`rP{!HJ%Co7f;G*j+QNF(rP{%IC4g4l9@bQ!>HzB{kLm<#ic1{;>jj_c4C{H1 zIuO=mmpTa6a{;vKF0h{Usjje|aj9;wo(`Z@9}G+Vez!UeYm&#B4eLpla$r5~Q{7=b z=23^hdeo&3h4n}Pt-1%ShkWWVSP#0?;js8oYSl-;x?gpVgms_CZckYEy3|py?)Isp zVX3dq>SJKtsk*&j-4QgkY8TdRK6NZC_1#n58`gxNq*eEUb*oPu2g~!Q<6+(6Qhj0F z>{BPe8tYO0V2yF96Jd=GpjG#WHOi+>f_0-yoeb-S09y4au&(o|Q(;}}Q3GII<5C$| zIiETW)(DR}9oBG{Is?|#0krBfVO{A{XTcigQfI@uB7jzX4y?<3>RedrXIb??SeLl0 zod@e;)jc295RbJBU|r-=gJ5L?Xw`#Z4fd%EVGVMrEUXIxXw?_NI?tzuz#8aL7sEQ& zrG~;f+ovvpb(Tk63hPXlx(wDC0krDNVV&kvSHQ}+)G$~B0%+A&!aBvLu7Y*4M_mo; zB$pZv>qMU#0jr-!Y8O*;tYBtPmMQRSrjjFa3=1(qbKfv4& zK&xH`bG=V3hq=zBR=`{vK&xH}v+Pr=V6OJ4)i77NR2k;-09y4Lm_PW`T9`{cY8}ia zF0~%!_dfL_%taox0p>!N`U&QO09y4%m?fY38RmSK`UU3PH1#XYuPfAVFuzi-Z4=Bd zRd+MY&sBE|%sHxCfjK+J6w-CCH>SGXbybF#|S!F*12 z>tQ~tx(zU&QQa8Kr*mAP!~BoR#bHiT-PSOlRNY3HPpEDaO!ZGABL>VzRW1SZ5!Kxb z=0g?E+Z*PCs@n`RpJUC0`GCqqR=k9H+XSV2-V@djQNaD%Tn2Xw^Ls z<|x%Y23gJs9RSs+)#6Qgv;ZBPv|sz#Oh}-Cx`)8L zQgsi7IZSnXz`P>I6^FsRT;&djss0v7by2rv)e=>~phIw{@Yx}@FD@z>*^UM@=JeqgKslI6b$E8j{^IuB+ z(ELZ4wG+`?QRUA{!Zx}G|y9O&qed)MRo_G`7*U)5Sq_Pvo;vb|MQBnXg))&9fIc5Ja&ho zd4O7bDVk3yvvviVPmWVpqPf3IU5(~`YTgJm_sz0463xe{dDo)3x6j)3XjXrdEpj88 zk14Zu6Pk}!^TwdLr_0*SXg(rGd1yYYK#fQ9p=#blGL~}aD+TCdG zmZ9!Na~GGoAI+W9)B|YlRH5={?hvOQL_*y`A`c-k%wz3IB-9-wG6@NF2Z=m|#HFhH zA0*TrB=R&8LxTlcJlE3?z>8nfnll zJ{~m_iQWOU$VW)HKJ_sY>JAe51c_r@);>kz=m1(|782?X68Q`Xbq9&eMnc^|B6E;X zcaX^ENc8Zy;tM1W4WLE7MB;xw{jZR4Jl4KL!gi?zNbrN!A`6jFcaX>;B-9-w@;wsj z4iZ_6gt~)7mLSntO<9V>0l^S0@&ghbeQFsJ9Xx6|675}T1rqxQ&>}05XzNj{kx02z z8HxP@XpuEYwDGC+NbKuT8+Kxn% zOZ|mJV*oAkHxhB5+JS`bQU4$j3!p{*MWWuPb|O*dQM-_cy3}qYY6EDIJxJ7efoe1) zA}&>hM0EhIrUeo$e5w|SDvydHfdE=f9gICbRS#pgM>W9M`@26SnX1sVXO+E)f@<8g-;y>W4T9lfw3%rR?`*6QlIJuV~I!ggt6GAj)L)h0IlX| z7z;h>7#Is&>R1@x1<-1G!+z!)Dut9cH_Eg5PujB)A&&%+p7V(kSO zWAfCCFh;BH6d0pa_azwWcWyOPVcd{m?qwL)tK7FRuFbPH4@SIWE?dDJo(mj=*kmctn8Q!8Lx>`^OW3~{MdFfIz9 z)vShbp+}Wr40fqCFa`zCYSzLy->25WIM1Wj!x$JqtN9VeIX<-k#@QbA6O6N5Y9ov@ z186lr!#Lfeet~hCOZ^IiZ;Mv*8;nzZ);7U7#iKUEI5~h;vjs+fpQ^w((WAD)=;u%Fb?vlRxl29sahDF18A+HFgp2^JoP$ylsxr11khSFz}VlXVldiylsxs? zx|BTiQUSD9^3+Rulsxs?xRgBg_6?x5lBb^KQ}Wa^JxZQ>%>lGl^3>bQr{t-Z@F)|8 z;ZhcirT|*2ePFcqsC{9?U8)TXJ%H9K38TTM>COuEF`91o zC?8D|lxCsHb6J~%rm+R;3p9=LsjtvNX)>qq+v-ks?BWwKP{84PAXr*7kv}z9wsrgT7OBkB6>4x7xnYcc>{RK>s@z{0omuC%Eo4 zelSJL9k)k*PS^H>zP<9lTGKa<_(fVLLf=;WU#<1CkJuos{?PyY-vbxVd%KggPJ;f2 zI?2hF+2K0@pdnWXsRQD|C z8`4~HHuUu>cMkM*s(UWQ1dRcYPgTA`R73V`=rE(WQS6@N3gP<>0-NDe8sqTf) ze@Jsh7W$G3brJN%syhVw_o{m_^o6QB6#9Z9bC*E>PUS9zK3{b&gFa7nFNglE>RthT zZkj8GLH}Ciu7v)T>Rtu?OVzy^`sb=U9QvFhSB!u@Tjg@lXQ}Q;=%1?YHPC(4y%zc> zX|A{q`bR2vJ@lEXdjs?jRrf~dAE@pq=fQrg{SK`5Ug*yhx#B+PPpjPh(4VTX_5k!rs+))Y zr0PBh{fRWY4?%xSY8syhk# zy{h{Z^n21=@gL}Ssoc}h?^NAqpx>do&q7zf1FJ1SpIGFI=b%qexyjIPt+4hybWe3( zfPRbWz6gC>n%ybT$Ew^*(8s9mROq8s_hsm#RQDC=Hx{|#Rp>XU+%)KCV4>ksM-h6oeFC+pxZ_2L+I%oH4}O_)%^&1SJnL(dKcCG1o}bg|NHb(cTMf>s#AZJ zO?~K{<(c>cEa)A|p}>aBv$sg#GwAIL49teUe>N1jXL!3{ z@EquE%M5%DJyi$=<~-97JW{`azF(GsFQF$>p#V-_a;*fug1)bs@HO;(!do=;ZL?eg z-#~B9{C8c|wsSjWq&ye;-tkcR?FIfrQvMctq7*9YT`nIW<$2JJ@Q^3HO&3UcKJ=#W zki|o4=SaB(y>)oVru4mXude+LdORPReN*wfzofhXx*neWxsw?u<%Q52!b5IL-gKyx z7eTKN4|#UjB6<0>-$Snp59wHc+lNwK3_ThTZF$|`H^)eM3G`Os*;A(+v0KVZq1S|m zd@}Uq9a8=QdL%rgb#B3{QeFnVWq8OJiy~i1c{%hJ`Oua-{uwhx$}6B(g=c?pL2dBE zZzXgsJY?OU*_BdWh1j0(knQ7VoGazki0uv!88&&{bSak++Z7LO+4qI@r%QPaV*iF` zPoGx5SjuY=`zJi)kkXM~OL-k)JHkV5uV2(t%IgvPD?CJhWt!Z{Ykx#+dp@+~!0i)j zrMv;LZQF{rMRw|BBe=62C)!Lu^xcT_yf>u=ys$ev31(8L?kVp$WgwUQ{E2Er|V`XP|=E z#?S=p9{ux)64;8^2DQcSi2a!V?*!aG_=+|X_ye)^8BX{Uv32qP2CC-n{=S6-wjs7g zP1ufDIkZL9DZ|IVB7wgUTOH?wzY$wm3QbtEbi6Bp9f+;SGw=^$%fk~sy6&HG z6o@T|2NR-Ih?PpA32(>rZc=W6*!(;LEfJd+o^b!&7rrQgYQ*NMEh310lMhW;HD#Rq zSu|RM*w-0OXoc8U@laq<{GFd9P>a|XYC;sT&%;|>Hg|SA3DhArC(a4=h<#QHO*nnx zdBLk_Kx|f?ff!<+h9^96KxU5wbi_VUTf`CjI3JqOXIaNPCD0nNk20Llh}g_{C@^E+ z_)-ZpAvQxzFcAA7yv4tF*W4?C1Y+;UIbkov-YtbDJUo8oPzmgf*z`OD&4|4do^aRP z%ytQwh`pt@un>DQADVD{|8hSG?1NY_!wLH$_C`DuNE!o!KpVtfQxlSiO$%?4pD{wd z^`rYC_G+9HQi#1=3QhQWX&-siMcX1a#b=-$VlTR(z_`l?UMzwA5u2Q5pgm%RN+|IB z@Ims2@@NOdo-H!a5wSku2}|-f%1_W}C&b*KuSE|)>}V}Cq4oA&gQVOUv7Ty+0}(qS z^z*N(XJP1A2^@r2j}#|#L9BZ!G~vn33+2HV?TVP4VW1mg2Zzrvee}xUWgd)J7ngxF zVx7Z*e@-9qgamBFI;k@_h_ws9%*};uD<#k!v6Px{2x7@x=nOZuAKzXAhazUFKo2xr zQVazax>`j7hoNC;j%PR=4Hu`w0jv2Q2^@ijizFyI5)Ik#7HbaQda#sxqTxby$fM9O zs1lkma>2;oC2%wvE+}%sF=#kBJRv*msMjRW3l04X47h0MR|-v-K4aA)2^@=tzCHuJ z(QsUNi^t*v50pS3H1tU^a2y(r&4ecOTzmC%5;z_Wy*vi`qT%S!8Bm&f$}$O@fQFt0 z2Ku4li0~Pv?XK@HffLbixc1+{E#5l2?Wf-^y^=;fxVBKE7 zH%j1I)bFES-*u?pI~@v4dH1$YC2&3J6Ddx(0rl}rC@{@!eS!pTM19O-U=-@3S}3rp zIS-;;Gyo^@EM-EsxU$Vx1#RM@Yx$%?wTa!@u)k!#B~!;cUnGlcD?1P zTO=?Mb(!$GiQ~?Nly5`bfOsfJpvpzi4KxRLJX9VBok>U#Rz?=I9G zQ4CEuHP=lpbyCJZ=y{dfsHj=KFyobUwd+Jw(g*?3V$2|S6qebgBy zq0S1Qq3!T{&yv7XsB6w}!hcY=mlxUsk95CY0#BpPP-l1sb@KT6@3-q+o8!SJ{w(U^ zrBHeN(Ad>dE}*UZ-NSxL4-(PIMG-TT#w#E^hkAv_Yplje1^{|3tLLy14MgNIAI2&ho(Xk)(!1@wgf&z zw0k^MUXwd%kCbO3YKISW(C*k1QvL|hgL9#Dhh9}o^rMwu)&1#D!NN$RUCX7A& zgRK%+isY{)PWS=IU-F^Av6H9vkiaq|e^wKgBl%N!i!blI>}Cn9KypK#6ILSmVSNUjY}c(ljZwh|~KxkhcV2FY?fG@;j#BVUrhS|nG6*ZrNoG`LKy zLvlqp-T%DrWpD#Q;s5=fH_Kb@oq6+vem;Ei&VJ54 z_uS>(cPE)jXR0dv<16I9BP$PIo5o+2tCmMXtCmz$KJ%EDk1H3BkNA97@;T1u>C-Nl zJ#qGBe8wZ5r%o9^Z^rlw&mK2^YDMMk9~I!_Df6dInu5oV$4E12_LPZpr-bHCn=xh1 z+=(-S6{2f&CGp|zpS?4h!l`gH1yFLN^_O>4RD5twWnC}@3CGqh3$46iS#{0gkguY$ zZbAmI(aTq_;?u_CJa`&&UFgc{RVzZ(wF@gMH~%dupz7tTm#qq|7*|o*))5C})OEGX z7B9apG@+t$%VJtK=DG-Y{CK?DmwyELmTL`}#GZ@C+1@<%{EEs=KTFEvikfAiT41lw z3;99|p`-0*aVr9}QLhO!d*-xR6UR?lQ1wk{ug_R8vljRO z-F;is0u}lY?XUA%5tHVPo3vmoS?X;p#Doxmwr+6bU53NEKb$fFCM-CY+*L_4jC{L4 z9kqby@+YhyM1S|^lNKtp?e2gTgx24Ez7<4I-j0JY7xoDZ`tC1;0m?Uy;npc$3v4`% z{eM>21j5d=!p0Hym9T}^PuK)2jBT*{Epr=8kQQirG-%?5acz(JOaL}>TigU-7f1$7 z0EDaUNi%>Uoooj9LMyMidiC`S7q5C%U^Xg83&O`^1wsi?+n%5a!T`1H zC2uy63mBfZPBRT#ysgDd!*FeW$qTMA*JV33dRp5y0P=DezP6oV6NJHQd)N$N@^1cf z95i`32*l=BNt1^l2RDBqVuHZk%~#Nz90@5TKXQN-B>7j=M6v=+u=($CGXxRdygY1z zppw2+`7H(zOnz{|~3eI_0>t=h*5IE4Zzzaxap<;*T_*sNE zf62m2$RrCd4Ii5_OM_KUe$VHW2Fj+($ZOH!qn1b8(snqY_is>0q4b-*c4{9h-Tmu= zPB`cvZ3Wn-wW6}|u>_zpM#+#wM}8l-fL2t|<})HzAmX?2tXK|aj8z*i$rAy9rrRj- z%#DBy@O+<%r5a<@#xDb47yuq>Iy+Bd43cQgji2zEh~P|<&yxcfM9A2t&jqb8X3BxE z6;=gc(klL~Vr3z+c&c>>1dlhOwMI;ZduX`9rG~SBI*vTDWXk&C<}4+9k_FoW0d9Te)gM)z~lkzIo=@ z&qDfDlwO=XgvO}*Jjg1Jy>{W!+QpCobC)e#T2UEmivT>@3JzswOm#avKpyEtV%Teq z164^Yv$L%8Le(p72#u9N|JkGixiWMvQFXpBP=?5g%JtXL_)&&}B@0)s3i)pY^mfu5 zWrAXMb^iJ1&j;!nuZ<&qXWLbw&#~GMzhXEWqnG1p&_bPYWt4 z*WO8^vQj{K-n<#JF?R0}sKsINDKrOeJ$005R$-x}{Xbzy9JPAcctk$5qGsXZP|dQ1 ziL-n4&tND@adpgyuXhMuFXySuT zpR%gK{5Lf-dd!|~wMvl-lXw5vTVZ#Za(&E?Jp;hm;z6W8=Wnl?S@87t&uXJlz4yEt zREmaP!{0}IN<2h^`Q?BTDa^n(E=>bpq8p+#?fGL^EeF$@w}B}o!VekA2U9s2+6oc! zXKTc{s1f@=m~p`nqU`-&bR(MurSW)%tAxi@Xp+WnP8d!y%>!L214;LBZ)rNtTpEKeJSN?Td@ckc3-@1;0HIXnBAF3lJI_qI zp@cX4mxHjhOayYju@_Qwr@HcrrjARy@M^(%SflN~Jm!Kl8w0o{vHvz#q};36e|gG{RBnCjzr^E)lsjh0pJ&{V8q??V zIW(RH`qI&@65&5fyQAgY{5%Lxjv>PdB?_W3P=os3sC)5M6n|gbJ;OLMJdkwHFo6vB zC)_iPCxfinOBLbl)TGK!j%HVRV6<2jS3Jph%)L><@OT++S4m`d#@(x^^3kZmdk2vgj{|` z+^EJJv~iUi)tG{I{5b>FC2}7-{9Lb`M42T?;dsYAAS_MEbwwiWhLWpVd2?A(JC`-z zOS+NCrOIipv~&4!yempHQO8R`H`=)X?HKX6A?4mp$8+wQ2~FSeV#G}Djly|%$Ln5q3>?&tc4Y_0^yJ>CJF%Q`%546rpnC?Hnm-+O&me1( zJpuO&vRrsF?Vdp<%?CkWI;V`_8|$Q2cM+9$Xfl)U54cxhtXfmyGB{+p*XDK4Aq)d$ zw4JeP?en=;VXRtv%7~O-R+PPExM8d)J5%nh^2;{GflL`3lD1vxGB_j+_r=TLkOkuY zWEmXNf*px6I3y9ZAI<#-W6>X7ih^A zALN$U6w9t4P)T16fV$*}QpNJvG3d$)S$%dq>rSpLk1A+!NgL=~N4G1nvS9CU*IoT0 z_qXm$kX7O>u-1jS99labaz`sG;6Hj?$(5D$NYE86o2~I8+E8NI$7xWrJN<03jyGM= zlC*Jg80t%O2yU=6UKJ}%$eoSGaHKRLryzIEb)mYjSKT-_URo}r-}ns|ma_R9r$waEZy+__3r5iKM)9QQ8e9r!t&q+!+eGCFeMG=QUxsiIyIaKQkS+cGz}+tUDHeGPxiT{XIE+Xe;(KLoH5;b zTf{Xz$(w?%$vM4R-w1Md;URhB2i#aMqs|9XE(CMvZ^e>^)jd6^FI1C@Em4WhiBskVVU<{NTNo6KT zh2$yF0-ZrJivFu=ad0?)+F0wKrOhLO#H0%`j$K5_W`LM`(?aLd&z5Js8f5msa_fr$1pyKV+qi9G zR5+0=Cu!S`^eT9>c(mqYn_^l#)Wh_TCzS+MGJo53hRXM8p(;5R-S&})nip6(oZ9vg zpN;^>W8qzeM~C-?jHASD^39(;`mjLG&LX^RM@Q8%ga9FEeG_;``^f}VLfHD2SC0q( zuFLcIMXQ&DBFk6SuByGZ1}+*_poNDZz|i2JKnmmzrnh}EtRb`HTbnmlf=qhPt8pb2 zdQe+o=h9d9@ND5OMINixC*b z=Xkw~IjeeSI*hnv0*qkU?3Ge)F_1WBXYUMXciPSYYT%`~8D&VCDwddCoi+|yIQQtC z<`6|3ogDbH)i_Fj#VQH549KdtU?v&=8n)O#Jp+G=TVN9AmBBm=Z6cq+u%yf&=@>EB zSXs9Wg!6=epsB|BFP!d|mrjq}MruR93CHij>hA`o;s_CR<-%1pp=CAre!FeZ3#gF^ zV1Ns4BM~zMoNav`GXzGp9ZZ-Yk|k~ZNi&FT);5$fgE)ykyfg@qVIOt{sBh10faEQZ zX4rHr8IKcFNrfmLULLV9!ic(4lfsB^h&Z!=I}6UuZKm|j&yp_+EnK`X!f%)OSy5>E z{OSJC+}Rg~CQqC@F*JYT^l6hr(`I7JqIS7x9(*fSP-8&e4iq4?WZOh90ELYWw&#PV zW-Kta=g_D$U^!P|@6h{`CICDi8s#ehB#1-rOPL^yVb3{~EK(L!(L1if2H*AOfV61n z$YlPJdOi@(KSE1a6`srzxT+jF&LkFUI{$7X;!=3nRB(AGgWsym2LtJDzo)pczhmEDm*_j4E;5?y5UUt&jC$O|dT)fAhD zpzhS)V1Xdx>X(D0K!XgbzcOluaClu7G(i@K-zk9dK#-(^3w&q}kYj1I~09aME3aC<0$=FjqtzCV6OLp_RYtRL z=V#04+o{oUEgC8E)DOKtkD*2OkDhS?{G0T^W(t^+V-%)9*V^46uQY*Hh7X^M z0+w^?I%LDoFNy$i)QZKpDd0O4H}Een0F_yQNa{K>4bUh91R;Jr6@)P1&Q6*k$hplA zn`xMY0W;t_#`F9%KzUo3UFTY8kl34B0wx-C`z=!~By6Wd)Io&^Foclp9@$(@USm!g2=>n=kH=>5XZHhe=|#8 zz(H(>+zgRxXBiN8Y|5A!c_d@UTnmVYFLwOgXQtxIp`905s5tl7{$|ijCC7&zyFO-t zk#jI&264dMzC3OQ$%lc7lPwD5m{a0HD;>w|}Vub-AAF0=5;ajL{!UJD&vO@ys5 z`kL6~v(RyRxZ{+71xA~99G$el7~q|!c`Y!uL*h?Xd7L`zSQ4?&(T~kr;()QX%Qh(c z^5bbUgvDu3zzku{kk2RcTr3G&!)6**jeERi2s&5OHBmq+3*!j34LLe(t_zzf3ArY&kk@10vKLZv@Ps#N-83 z8=LY}##KfeTg()U^HQ&gMXo>kMa%?2BX3+wb8|yFBHlESaWEN#Hf_2v&t({iTxhyD z&uGA4V$+PEl@~>!5}Lq;@xDP@JhkfyKN=wSbrF;OcWZ$#R1Lfi&~gh{+m3@KaM4?aZ*@`oIqsH=V<6C*v{}> z=E1`Ua*oI(c-Nt90K28<(wOaC z4kV!W?FndDVDclcWz$%n+R zdpk~)q7_3|`*EKWZF>4!;VexA%Z0@?)yo&xtT>Oa+i}6x3?Fc#EiDXdnxo{fK#g{% zH7}Ayfy5elmzOA5W77mHc3l@x;gC_lU7uFtz?VG2tHPmwtob*&j7#|}QrDINjod_=yN4{>FA!1m3sC%10-%<{p2I^LYeswZV$d)!rZoVHBF4~Q znJ#K*s0smEyEm+tBQy+g-5(R6(j*G0Nb?TEqjDW3L2R!3H-n>+Vo-=Zw|GILvN=nG z=&Wsy6{n%^yJ@jTPQkCgMM0&ph*WHhwefTbQ7AK~CPBk&3gK1nlA0AYi~Yt9-FfjG zB9{=dQmFe<&<>X%PER_(NY=V1q5x}R3p+tE*(ndrTQ@OmmnQ|Z?qZJv&LX<*fW3V<_4vZ}jpdOL)?HeBqT~-I=uKV?kEzYxO$>kQ z*8os4${1Ez;h*xQkgNzi*WVr}P{>HQLEJQW zpyJ#l@S_bCG+}cb&*0COzcnvYXBNVSZt~#SFbYomlKS#aV0Qk{wLw6RTFT2T(cMEe zS4UReAX|ugqhz!pjJ>~~Q06Er3c~NDsJw8_!hc4>JOo9g@u7?v!ukCDJ~M<9^&eT} zAhL}=vCwelz9nMjV*B)a1X9?XZTzDlCkuhIdru`~R4on=EL??)P!XSf6+R0HJJaXR z8$V4dYNM>a^X8L!bWBCf?B9EO+=3$LQxfamN&uB^K1&NV`{U8GH|~qXCA`9 zy$~@&7`W#WW(Wg!$RdYZ zu5P+N4d56YYhhgjps~j%fUE-uRGTroD4f;gh_h*T#KcFc=i>lCbzVB_(C-6QpwzRr zKLl-1*6p_6P_apXF%tI03~2861mMwJ|Aljn(OUvwb(cuq!@qVN4YcAI3gYT&i8K93 z0Rp~$gU3pLZs?pzGtuczvB6=$*o%Tw#efZ;4p^D8NGe(15VYdX4TUJM?&>7qCgn6} zA!$u8v~Hb@(IyyI1ef`&bck`?Hv?7}TBmMq+6qI%w(gDsHu|cCi)&Vf7B9LIC(n&9 zeX4n+W5>sctu(ONZSdTcQG7Mo`J0U3ahR8hB2&svc^zEI)4E2Z%bBxvqY|Jz5;@2> z4#uxQ$O)*uqazeyy@r-c(j|*f4bSjqxeShTLn~@m)-J=432!b>16PQINUN&`%nX$G zx>tIvKyFLceaCABa$~mcTlB{yQ)URWqgJ2{#`9xVASYsVGwF+ookQE+6G&-y&~G@n z_d_aVRTlY?jDoW&6k=%ho}@zhv&gYY6(_ik@+c6#EY}yp3M7(b-KDhB+IUQly=Nty z4AMdOejW&i(JbKPi4x53fN)-8`a;pnC7Hc-Be z9zA;9Sx&f=k#!5hP6oEdxdA5}U4Gpy3PTa{b<4dDdSe!SsmF<6-&nW7DM?;}blyt@ z`?j%gz~+&3yUzQAb~uNF_22dpjF8goa2yX-|0P$}O-MQsvab1F#))8;>U`V-gvAWj z*3OoQ1B_v`b9c%C##Ev6k)Q*NX6oFYaDb8Ooj-Si(RiIZ!ggwDyUtdx1I`yDoqHp8 zc*u`7>fE1l!V$F2=A<1i7t3`1BJ6;()OBtJ*cusG7j-`9gtNAFt&eBv^TnE9EYujC0^yMbJEQaNzWmm46(@t>xGnlPYxJb2jBUELpquB(1D| zE|r++T~Byb81QsH6SHGTzcXWpLXud})f!ZxI2r2dNGVX#9&6(YjC8NAy-Jic!H~lW zTHGJA%VIt}63#)5p`P|q$bp-qIfRV&RlEsa4)<479$XS};__cAFzoz2P=l8*7!KZ)(4cc4FC4r%t)!5{ z|7f{`Qk)CZylk@@-|iq^4lGTo_+>J9@H`Yr|I91Tn9>Hf;k_cIT@eD-^Y+Gaa6Z;Uxv)-%I zLMzJw9(-H0dfDQoHO3Z|K`jT1b4Oxi>ni)L0}g4y_uln}1!@VViGxAj_1lD1VeX`z zSpz=9dI(f9Sm0^`KhM>3CuxtoksED%7|5~axA7d6G?`ILUdXc=K&d1zg{_oQN1hE> zfvh5XP9SAg2mIS}Jfmqmi~JVZMmfR=PWGoq@Z)XVVQG1syplqO)c`$5c1hl>BYcs* z=i`h*Rw%Xh-((7lNvQ13)NiMZqYaI@k1i1T*@kE%^4wSiHAmtp{tM8wT^WxUBj|!i z=xXr-kzM48IMH%o48hqHA-JOQ&=YnIaI&{KW@5LejJ3ge3aGa+h z9*=wZOoIn9?&;ZHcctCagM4SyE%^dJmsGtCpm!G^sVcoGpKE$K-qrhD84Rp;y_-_* zHIP0#l)7lK1#*0?_h8Vy0v5gArvk1S8TN2}*ZcFNdktLR4X!HI%2o&H!P;W}T8g<$gL;1qbKIsi2j0Q!iz%?$ zgKjx^O{9o?D>%;9d#wqVmmAJ;J4jNM}Z!^ z!oBUNpM&9`YuhnM56W>RcebON4_=aTEgjUeW3H)@lY*0RXZy6&=NQ9xw#P2; zOBa;aE=4_c&UlSCjM;BcdyO|CnyG=bvtB}oWBEIJlS78sA_5Tpz7x}0pGyni?BLt+ z@&)9l{Za`AfBb)NA}fMH=sPZ2z6rT@;AV8+@u~M90R6RZOyE5T;2h=ep7$Vt)%Q*B zdl0}`%xlT_Ab``*w=(~C0kTEhXS`wfzx4*$tL*ax--8VtwfjC6e-9FPxV^6u0<_~= zi9Rix>%D)Cy$1;#DtrH#eh(6)w!IR44-&W$*Y~L+5_p|&T~&MFSveVqUXfVNZM;_s#g{E5fA=41tUz` zKgO;nwA~abWu0SYc22Gq8PlS#g-c1uO-H3UXVMb&Y}A&!a!uc00OZB#ix?;ivRi`X zOUTaK3=id4e^HZ*m>@ZST@j~?SDdeg%QrsTKGqsJ@U}h-$b)+mdOfDf*1ydp#hPv0 zjFk$~pNJJ?IcfOrwg0hXQ4)*}huXbb5}^BcrnG1p!dyGFKcl6A5r_6ibZGJ8+7MM7 zWm!@gy$dfuE(9vqp{zbiuLH&TLA~_cy*d5O6q8M@Y&XevVA-NRv{!GUc-WfO@nhq< z^~5l+ws#;{NVJ|Ab;7YoYV~=YaIC~zSt#0^A{r4RLu~fj|UXzmf#P<^~TNv`z=yA&L%8Q6cEygd{L_QE+hA zn;wNI9ErQ1aBEIxkHqmrT&pMSkSFVbR&UIS;9{lqOu%gx$Qh5;b5c$OcQIQ}NIMZ6 z9Cy@{Lungt!EQYgSi2@pQd*BoI1wB@cfAvKA~1J-b34a*b!c7#lj!p4(DE~&iPutE zJl|F(dbHx@((xT9$8`L1OZSeW16sVqZj9DD`Q4KpXQj3L3~sx56UZ{`=8l9eI6qgJ zTb@rsR`wNSVdWC4mhTh!Ce~ZfWem6r&LcAw_225TBV}~t!n;*oVp{v-0{LykU2jmN z9Rrpf?`Y%Bu zuao}-%Q%|541N1+K^-qyTW?JQZ3~IK4QgGh!bs1(NrmBP*(%44ZPMiBRqN7(Q;#eU zT369PJC78p#dOP#k%D(wMuFjCplh>v(WH!OLpJi9Z>r_T7T3RwdWKRKD_%PGxZ-@hF6^aQ=2t!$aU0R94NZS7c zuM&l^w11tN3xj5VqnZnYVE@LjQXr-n{r9K^ax!|i8im2L|NgjAAcoIFBMAqpn%f%v zP0j#wM#={3-w<;!5y#xSzuBXd$u#J{E2zYA=o|j1Q=goP?~gkX zG?H1+{}VNinKk^0utQljkF5@WCZa%~l@Gm?Q6SKe!{)v6Y_e4|n}&}_C^*o*hyLg^ zteOXg4*fQ%;NbLs1aMoYA`4oECFo&LZ+J*oOf5-`Dh);<)`55yHtak9bTy|X8*=Hvj{xht+la$q0!q#a0BqTv%9jVJFdhP_D#y=3_N zJPtT3Oz%9#Dcg@EtQ-??UTfxzi;!rCp7$2e*)U4FzT#9bssF4~jnt$EeFZt9CO2P$ zI+Uzmrfg^dA6Og&I6HisxnNj-*v63)h@o!JF=-&PYtkGX7Zppf>7PiUS&vOfmQSh2 zlj1r&4_P1B;04-b6KpvUC~z35370M*ol=eLu3Q+_qB*F|Ol#2`zovO~Xk&Y4irz;y z)1ITk;8z8RBlPr?R=CVEZi)e)jeseD#7OPduzaqTua0GNDFF+qAqw ztX4HUOv{E~F%ow2ZC|8yS}E+4?I))}k`0h$8DebRBFTC-q(G8w;QSW~g{x7zXT}Oz z^7w2HUY1nw%27$y)Gi=%k_!PgMAOGTO;HdinoowtJ;%^J6;_&FzMfHGWqz2 z)9|en>r7}EJiI2VL~%5^DXv7Jsk>T~0u47=HHYg`DqhKiuC)O*jwP3kJbYtDNkA_< zhrPg!F$M=)fYHOhmQ-@)Z=4$bepE@o@D8s^D{)c;=L40CU?C$|aM|tVBs5r~EPXSo zK}$JV7|>x^E*3;ISfg5eU8|Wcb<^R$PBehl8SrdQ58B{DVWOLU!`dZ z;V`>jWAI$)n zO)XQfvRe{+A55vFX7#f2bk9hurAt$Mh0+zOnO?)$!}xMAprD$aaDGCim7V&VKse)o z0QcOPR$xq>v(~4?!;t<(w9-@=<;c72u5f@IR(1o)mxDtoaN47njopE8z$#Wsv0)J- zci_IX7B5q&D}pM#l)XhtR))O47EDTKxN_;Q(PG)9mnL<*h;V--s>7mXdNz6$Si@W9 zXaBN@0xv<9T4O%Q$7Cq90UhpNlF)HW6`Pz^p_wq#!zv61fuIt@^t&jo;$f0)@+mN; zB$F}Jo=MV!d+thu)s!mYU^Z2H?uu*WGF5u+N^0?vDwCCVNiVz5qhggTx;UjmF`#{) zi55_b`Gib&yML7iQMPwmh;nS3hY`v3Q(6PUq9V@NZ&t6gELLlj;lon`ok*}mmYL?x> zzVR*yxiQn{&y4|3~OA{Ic%CtynO6j^YVx(V6=c!vYBISoqbgJ&AWGO0SVs}@d6csvNcZ#+Z)rfA_-5f7Pg+9{#R7vYm zr@HS+mXd{j*>2ukvJ6_eNEk0sxkuX_g}~xIpo4Tbq)JhtU$)N-gGx2zTlMlBK=(+b zghVOe?N57MiRAul`wL-Lw0!-$w=dy}mRry5zi}s*+raHRysqSO3g72j3rtG8zt}HD6baHIqQGYS~RDj zuj;uuUjHSa>>+}^mn78kariKQm|*W28Y6NJv+eZ%R#G+D+{8?j=4ErNb$2D@%(MR4+YLJ}ijJzAuVNnG}I&}sU z`H!%gRXX>`8xakb(~FU3b-a=_FGV%H%*m18r!-h*^vF;`gJnG!=?!SGGQs$T&gQ~e zsOM3geADb>Yf_`7Fzpz5*Q2F@p*_EhY0>$K#v}2fG%~|@I9im3HL2&pOi>ychJPL` zO2buf&qLv&G%`)tmMThP%n!DwixY`OKl6Y{F_7m*@E-FUT62NSu54LEM|7JKvI9Kw zc0gwb>r;O)VnSz^-&mYu-98vMVNC1xP!)Q5U#ku~7Tv1h zEjh%?-1^=Q>#zt_|B+f=_M1^@9WMgef0mXP$oFfJjH6G7CGsR)q&OJ$AD>d&B*S*U z$D_e=FRK6JF%6c3VE?CddO3jhpQe+{L9piu1uu3KIj*oqci!w%Xs%x1ulnLR<49Kb z329K|Dow79tL0trGdk7sJy%~>N+Fv&npN@+C8;n?Hax53CE#uydaM-W)3w6kc3+1_ zr&`|14CrK6u_^m{VmfZNN8ceWHyfnyUpln>NM_$lTC}+RJFRYchx+T3&NR+y`d-ip zuacmBPA6Ps|3xQTzW?w0lSiXkzUS$CT`OCXc#IY;y8ovY&NS}(Pf({@`hYC`a!Zd~ zjxy8aQ}_OJbleh@qjgy01=XiwQ0>fr)a33lDHTfg@J7z@C@jWVW)zZ7;v%Hn}H z!YY}(VYU01q!IL7Z3ma3D~5s<-dWSk}htZpM`Mb%!iCDUrqy z%pLBLN}rlS{5d+UMoO4GYLlg6cUQ&1=?uQq%+9FVAHyoXjP3k>RIOO14qT9SelJ*r zLO#y9C0vAp3)ar>28vK{3N!pbTtUGOl8h=4ETo?yLgBbH$Bh{vbK8jd-e}B-V9$*{ zh0xrDiR;YH8&gFnxSZ|&JXI+4GgpRx9Z;~dV*NC&Kx99xOUD#A3{k^OK5~Pr<>`eU(bN3?i!nDi+u^ay<}^YQi<)$W2KV2E}l=Rb>Fj2lJU+ z`6VL0I_ElYWSY`6@?548#wGhmIIS?CipBrZfC|G=&vMKsmo&UkV`O4n#lx^wDWx%S z-;OGHc%R3}2jVIW$LrHoo^qrc`CL%N!$vqVp~5gb-VLZQ%!0o}R2VkT8&MSou^#?M zQiVYbhF?mnFpR+?N~^J=*%fuNWLGpSOT#T;6`noo5D@m9lQD7lS%os$+8q9UTEWAK z`mkyPLZ*Jhy^63J-}ybAQb^<2($f}KV2pK|yyV=il4;=iW^+VUmW-1lJ*_dVXxTP= zGOWe3M)$Ntw0PN4RE9OX#AHG28TM!ejAcC>{$)x*z+%|5C#k>~vW@M-=75$!_9<0M zxooz`)f+tnD&2;LDhW?2t=Aw;Gnmm6ux)xQrQRr3^PKQRrYJ*Q$(_9hQ-+JSurItt68p7pi3L9S*BdGE<$V6e#a%f=LyZ%(~B4 zStwVPj7;>ZxMU*lkE&3d;Po}xxl9MCInVls%1oIQj~wY!NR^9DMow39Nl4C2s<`Cc z*l}qUiZLGkPeO%aNQVEXL~-kC_+J?n7h^p9l23(VNQVEMRH0-#dVgAhk~nU*V+wJU zv9r&yt}PI7Kcny7q)oI5k4Z@1kL|vg@R;)SJrL9LW2(}(J)p;9^3nH5M32X`rSCD1 z9*+r6-xFy)9#fdUtpP1wE-mT%Sy)fNhVJ`mQcu7x)%PQPh-7Bdcb`5+#*z1jeR>s4 zn*+bpsK8AQA$qyPqZhyo>U%t`CtxDAcE&-F`)r$4G270v$$a2`AT6~fkFAwAcddIP zI(8(En4~=KRyyThbsnL$0$GLE*}llo#!=? zgvN&CJZ_G}&+lkEZ>Q^7!+DqElG_i24Js^f+4yEcS%SR}=+I;~acIIa8B z8eXXz30WKJL&M2N;)@iar{R1fG0j_)h7*Rwm5HJ>oHOkFcyT$LHYC-kMwDbt7pGjrrNpOS+0bmT4#j#~!x8jH}WdVZT!$~3gH zRE)I5G!zI@&vOY4lCKJ7ZvCrB5ek_a|5~SjGGzMwY_y0BSw%b(E4Uc}30AnuRNC_`SqPETHC=S>q#`Ah7TC9QK0KyfJ7>ZwTHAtja8zFy9kU zBV~rGnFbi|ks8BlPMJ2}8dW3ND@N98IN2xqSNjT_9J+ELk~1wmX)mzZYDO$a$Ltrv z{nrProOvAI-6BlCPg!}hk}=C1PfWJ2S){UI`d4_Y*!*B>h*AILxuHi)Y z@BfOz&%y-(=cm-HhNBZa8Z480*qr$czj02AubFyY^g0<$AM|hXInm@BZp3mGx7UdVcC!WY%4Ly@v91IysahQQw{Z;8ZOT?B+1~3vGRCOicSm8w9O`xPQj0!P-vthfP;1>J$rE-GbBXt}#@DyARdlBL`I~7Qrr2A- zDrG__G-)Oz_4sU(toG2$+r1#k4=5$QWTveHM;R>a1RFACv2ZB3%Uc!;hk`YpvRLST zSEMYKDzs1P7O<4zKRep3zOq5OvGRD>p>Ob(#X~i+pXEN! z_`98{mS}lum}zb0H7JLI)Kl^D^f1?UmdV48(_CJtdE_m%JyD)*Or1usl#!r3t(W>y zraT^YgiW6Ec#t~v17Yywi<@m0%t>&n5(F0Oid3l8)$X6hA z9&-uhX8fSMPBB*(?MNV7AhP3O>Wmh7jw?L?qi-ohBE-+PGV5DY zHVe&-1Cs25zcp>6vFajCDxCq1dmn`750vYkhX;33FQv-j;fbEq z@4!-q9==&h4S34p;ofv=s60K~nNAIt7dO5hNj;M;%Qn8y8a$~yf8;RN;3vy;h#n1k z%kxM+)fha%Tb4`m>0Ihx$+DQ_hsRQHr^{nvHVl3kJY{5%@ngFmDK8N6i@T|JQsrrq zj`U`knpiCXhP^5?%}2Gh?~hu zj!B|^pU0-&TE@lEu4qvjDUIt%lQ*%XZYkRh7Pm_BNZDQ+D@%{`gxku~BOM`{EK3i| zY3fX{6k^~jHDq&msF&j$`9wnutnrs2q$z5aTQW{^1UA)bF{U(=w1{Mb`&N_zA!V7< zmYxbpZBN}8FUu#XGo9tRBtI3Ox~{y&mw+d|FE02l8L48jGOy+)IE^%^dBDE@6mRxC+&1Kpm&HuxAS&HQI z^HfFJ##Cf-Uq8$i)Oss(`2ot)k@zJd^}h-frJ77o zIwX1bg|Jyv$@(Td;{#>!NUEN|T*z0Ul6qLVdOn&ii$}(is$f|>GR_?nFN;U&)@P$- z@yPV(tVmfrGX7juo*tumFN>F@$SA7Uq{?Fwmukujw@l~jUkyN0z8fGHEa@u;%OBVk zF3TFDzs@Nyz{Wb^vhrLoifE`zO)?TMD$^%P=qm!{1wwk;{4zC3x1LdEAfz7zqve?= zS#xoj=EKKWusNsm_n zTR%#*4p9}A_y0l7gN@TCUq~x>d^~Y-|MPJr3S3){kE&1=l?@*y;sesqD{64I7Q~wt z#Q`h00nwY}U~vJ2cM?r$YaGUg=135lUh;yw;MBNm+#Wd5XNSwSbJHskCmeBZInE(R z&ed%FV#+}e>SH{1sKjLJc~J+vqVj={r5#Z5{QIOXxQSipmLsgB;wB=}^t%8^3vL1~ z>9KWe&<=+)4^Be$RG%V?`JB85%)ZrCoxM+3L|0}eQBIqbDStFpG-|DTKrOzsP#`_JH5Em@KM5#&6jsv{QP_xkWsm# z`Ju>)nrqSRCnW(bIKoyu2@tCZfVL;%fR4_y^IHTtnpc?z$rlLiQ`2TT-0wUs1_1Qp zxUk?8l+SnDRe03ix;k1$VmTeD@l(s*can%7!)V(@d5_LS&<8>_~i`0 z1x)@?h2a7CO|8TjUpUeX*&$5cL)+|vcp(1X%{FpQY?AVJ1Tiq{t*CssBVrZJF>2sD z1ZG9kZi&uQzo0@xLe5FQKXlHLML5^KH|@aTg?i6R9)Pp)gCGz->T?i6NJxapwy0eJ zqI(8dDvlP@Yp#y0x`DBM>amnv5N?8n@mpjnYiSF)gKMAP3kJg$Lkb$R<3^fe2BI~S zFA-?CFO+B_ztKjU1|vY3zcuCbH2HE;#lW^mzMKZiq(EdLGOv5`ERrsmWn?dm;57&X zk5G?cLJlpTh{y$l1IrR>to)A5z(ybyydj?07+4imBgZ19JuiiUG#QIvJotUWj2xC= z;0N9z=Bgl|rV#m!92po$=HX_$d7gCOKtPSdft`Vls2YbP8t4T|t~xkJOr17ZXBYdCqlXy9%QXBCoYU`w(>Z7oB4kA{=SZw7u3Mx~#? zJ)BhIcm`+S=Nd*Hwi(zO)o?OEojxT}zEU1Y>Nx4fOPao?TPAQ_-P zYB;I#1sx-B?HWh8x*zCEC^gC}qJi#=8p$R8z=%dHmnj2M44ru?Uo{RqtKsC*d_ay8 zC^%(@f8e_si{w(-fonB_cE(tq%d71RkXA}tb(HA3527cQqPRM&wMWe}FVBj&Gosxyyby#VZCo*ca z@{(-eDUDIGML2X;+R2MrG~`pjQBa4*#hvu1h(n+CI^igIL)V0zaNcY;baPsPpoUK< z5GY1NYrIYd4uV6c#GMEX3`0K%JK>x>3`G?TydZw)`m~dSIKUZaAe z-VR+IS4g6@wJHw!y~wNJpx@sLD-iT=cG`*H05ddSg<#Atk1IGBky%~^f{uSog#dg~ zTERd!E{rP>bo|R+1%m#4Ev-N>hUbM92s(a7%z==RW9SPWCxW$d=)($8lr&bszyWIL z^FgO1jz2?Q1qXZQ&}k_r2ltnUPF8TRw-4PBb8^UpIW~(dvhEmLwYd76r4h_!dKP9wyvXAlU&~jT}?-2nlp26uI?bYHX zI{!;)@nYV)87-byVDwf3tqGqr?K^2LUcP33HLk@&e9wQATD05|_qH~Aez`#Jp8*}e zU(~-5(cdxiY5Uk$KitDjunXOH~-Ds$rEhiQeL%LJxy9bVW*m;oNNK0)-yGSa7LA zn#?SR=BapOP`ONnkr+%%IW3TllA#$f1xBJXRV9rv*e_e>#wJMh@})J^tCp{TFJDwi zlE{2DsL&yi`B1`%k-$tyIT12(9Qa=(kI5;QOBS%<)fxvXKT2hx+Ycmj4C8#E+~BqE zsDKH|7m(P@KbcC!FQKHwWR8mC9$z0l9m<<5APm}@jv&<-W6O-k*fH(c*hMof0Y7Dx%s?sRXN?zOVW8?$|v82T24WM8@IZ3>X>HLAyE>uiy@gm{?Ov^7=`B6qMo z)gfX@0CX^7LSrj%79K5T$}6u2e1Iyf#3ZO`O;Uvu<&Qq^RpDUP{X3~wArUq`d7qNY zco&h-;K29j?@}t6^zspp6(g@}7@b7gipag(y8juQeLxtmC5-h^p}_!morCcj`z(~kf$ z>&(9d+v{^648MNtQ6T8oP8A3J`iFu8^xM-8L55#Xdld-!^*Z2oW8p(AZ3W|qL+F=nm&D1mag2(fDzvcL7doHyc;_*3(d_&=dR!`04bwXR9tJ_BMNIY*vI8ea z)hLVvE3dhF_4Rne7Fvk#9vI~V;V7pJ9M!13HdG5O>th;qU)=%e($NpiEs=a4c3@CXzviotGp~(Z}Nw-mdmHe{R(|u<~F90py-I&(nkv`q~Qd+#cYw7Nd>Ipc>?{4$z z3AlRdz6W@XkMc&M`|g0AfHVKj|7ayh>F@GIbOQYRvApiEK1g!vy8HW4oq#HNr{6U$ ztt0SPip$dTy@1%`XWUGtn_ z&8E%e9tDr&%cUv|w-CB63MzQmzFl9;C@|8nUsLh0MGu_jbMWM*C)t@!*MyjZ#F&nC z-x76Ta?D7UYf``>S(qCbZR&2N5!q+7d|iE{@QenpyCYn9Myu7`kSRQ)vFg5u#~eS} zsBU$-@QkLZ`(Z5mjQbX-?*UKYnfe~d=>wknwnqzin z>fe$sJX8NI3FDcagY8kbCTjozY`VJj-U0;&kGdb=nIcKSRH?fzRscwkyD44(a1X0) zWwZcb+pZa(0$`MBLLFLGbEO0z=F5`$vb{B)C;-I5UyzsjK_M1y^%ekP;e*KnKrC#E z6#!!4PvQlDShy)r0MNp^&qM(jowHD8+O!cThDN{ zs4@qVLt(ow&X{21Bva|~?r#JD&#~v=Y^}DJi5Z=hg0M}a1V`A|&R=FwK4>u)^j}M= z=+W+L#(NbQqdcA-2FkqHq2GnGcXel^wRkRw)=UckZ#PoL?7GvVT2^jY*PR{*J|A?R zCeNv+Gaeuva@kmGGd?>Cab5fGv>gi1>noCWDB@RNVHYk2x1Zz{Vjfb=tq0L=5WcTH z15Bl5r5NIQmc1_%G0KWSPj3Et5^&4X68&}U-=acoT3K?}v+iYs*aYT+6NrC%L2qsx zqhTa^e@!TH++$z+Zy#{x;Gy@zs4D@r8ilFTuIs#j9)V=a?wszrJ_!J|N;fq&Nt;7a z04)xoAT?J9>`;ty%?pxtD2my>p9TT7#gNo<0k%p;0QV&n)UdYw$Ox!y0f+SV;}mdM zxc6O;lO9d6?-kP9tl<%^j*pPRhTsW;jvJLitL!*Gs6Zeq_og#I*qlHG z=DN-3{pOI4Y*#pz`BXI?xmyl`0)f{%12zHvr%F zPr~iG*^T}hb0T=aZQn>rfnYPe;87qDk$t~W=-`pJeFG5%2Q#WWs6fE+c3&6>TWk1O zk=v)lRTya5J4E$19z=KF?iAoQ*LlO=z9$k21Y*)YJ?=#KxN2&jqr|Wi{41^EL0H<) z4FhAd%f~x_+P|vAAja)4$H8N>8UE9_zp7DisQt4_d1(Ij4q_bg*oWG)dquVi%M@>a zR;h|f-kw&Y7>ORWE>?sm)F`&=9yN+#`h~YbWjsCJuI8f4_o=xU!fVqN3V}RI+WrGI zipFPmx@>`Bfoi{7sf*pHU1o2N$nz{t`*+p4*eF-2QS@tRvO;A%V`!Y=v5tJ$hoZ|1 z<4P{Z@YFC+j{F2>Z;zr!QP`TOLf8U%C)z#$lq1s?$Z5#-vx&27l66q~1xgfWm+dm0 zu}4rgV%mcNusKj%8MpskiQ??E{Yy$+oTs*rQ=&NQZU3!Opd93Ee^H5(SLp4psc{_r z+fP@j;{>_=u#!#Qu(v-(Hiz4C9<_b18YkWzP~#-Zt!kXO{>dbej&>6dWTx*lMR1Rh z&50BDeyYZCiq+nr#L02Z_AP3hG`TEt9Qx#w=JxMLD-^cKm&@%ps&NvsZv~Wm;@?s= zAD1)jHEKTb{p)I+`2O)^g(B2M?H!0YP%?+?INd34fh5Y_7ZohhqN6=dSxkd{vM#g6 zP`cW_?P+k>5EAwGD@3uI?R`z5oH5;dSb<<*I?hw*kW+7af2&|&oI9$bPP3%nb(|G; zVx+fr9IwLAvW`!s6+CpNf=IxjvxdxPXF(;qN%gtH98oeQ(7T7-rkP ze+Cp7CdR(qVJAk86z?1HDlqhP-}7+=hMw+w1qgdXOW)h~SFZxY9N71pr~)JTbRez3 zh^GTUIP@?&``V)l3=?GUfgmu}LL^J(eNO=H5XRs%4@H3)Z5b0WR5te~9bgQu+Xe#w zn;Ub%*s-}^i)y|TIIAeW;%R=|0p`4_`RS;gniHpH8M3VQ0NUk{!MR@ZzJNmp<`m6s zNe3A7iRKnSt@iOFpyugO2N=*_Bppx$pg9q6fH5s_|8s*+2L=8KXJFrart9Z;HGA8>%_U99 zBT;}A8P4;V&9h>59(L8{L5GI1gl{_(R?Fhq%WcCEHInCEw+#i=NS?}UzR;nL1#sIl zaW#*hdoSDmppjU`EwOE{Ce*xDV$Gk^YOMSm__n_RsfyTG9s%8!@~N>rKf3KN88vdO z7&YM4V9EMgN`vHX(zZV()z~UFDMhXz@?G&fO_C2%rTYyOE-jtn82opNNb*bsEc;b_tPZ703Vs%~|{ z#pByk4mlFhtDSI(++>Fw2~aEuF}474)4%Im854ql8zLqECIX#JJ`(`3oiIBXlvfFz zKaM#ud_~vw-INJ|8A;czW}%pibS({kRrrW}R@L(R#bKdb<6l%V7ISvY~ivT`~2kj!uSJtkoy|zXcqIIA1lHLrL zn<#F8sD(bFs+U7h(~^wwHv-x8vqbi9wnWpfa~N**HbtX39Jv;Ij3?6lG?x8axQ0@> zCvtr^o_iwK=7{km2ZEapCUQ@tlyyICqI=tVeZ*y7GF`VKRI_a1qNO#6OG^xh(fqYP zylQOvX4(*eb zkHdH#y=e7{m8+<=_x))+j{+WVHV@#>ib?|~)SY9zfEd&jm3yCx8hHGQs$65S_XQsS z(p&^&FC^*u0e}>f|FPAI%KdLxD3Qi3zo(@_m1}CFNwWtQ*(tX_NJ*A-5b$YvVR=?c z{9e*Qjegrw=LDnYwXF9#sIdxYxh?DfqvN*R=mev4Za+TgphgyLe_zxAM$5ItoM3LD zwrol}$oU#!+Zz!l9OO4R$mL~yOVmLwhk;sd_t?eA#!JguCp}Af%gs)DmW=HcL5Cc6 z`0bxcIN&T6+pC;#mhuNa=>vV`Lb?5i?#p^iS{bi|7qZi{m0O-n=EUZ~Y|fV`Rq`ee z=4~)HAa9o7{jDU(c}~qNL@hErTJmXud~nk8Lz-kmuuvVC2e^U2D{H<4?p&X;Ktlc- zA^0zG098g|oVf7Zizk9)OC-lj+DU|HX`G&|wU#+E%P z2R#R^mUf>5E?K=R;(&A5Ye^&=a1LxOcgGxX$)N{=4mh*A=j>*CB zFOkACT5i)_K0J?Eh(DYDl*ytd&6+ot1I^a2iAZ6Fs1K&icnEvoq=XrQ4!-p(K@$Wr zn+*zIC@1s&=ORLpze20US9pfbC;Loz=-B#!U>*N$^^m31kYM1VAG~g z$3Za$bBfA4?hoM4j|C@JRNgL;KVtTrxj3dVA&y&^+UL!gGCMSJ`m~92a5K{-6g%b{ zvu0O?q((GcX#$`_HC$$TM(1sqA1*Mk*ZwVr=MP>sg~H_cY*rZRUBfp61zL3FhQ;B+ zGkRsiS3QMiZdf%eOB4Wby5T#4!ZZ47!xzmAlsGw4AmFRYhKW%VfI2P;n*fyYW$L(y z9^+xQnIDmBm=!gVqn#RL+L#Lvo>!*|1YlU>@#6W!`4>$?3&;ZF$obQerfZI)a^yQGX`%Zu?un=sG$)tG9oVgR{PNT4zc$Nqz z!7LiF{q!JUqjSP4DtAov3DMli7hDFG3!?d_ya9JS9fq#@IYIbva{~Aq_;t)3onHKT z+MG$#FTuliDdmPaFrv|$!Jnfqg-YIj)Odb4_c#{VI~K+9IA->g3unxl4Cfkd4&XUF zd)5s9gm3sU7R8JPnmuLCl(`1U6Zb?xQb~bhA#mH+6dp&-o-$Q5@80Mk7LU_rhJ>r4 z@`?Ka%5oq@o@fl@9}$8l?oQ?(kuQy3PUBJR|I7gTZ5(daKcb2xZna{}aaY=LYDJn_?5{+aYo+!xG0v+O@{ zw;v9-<^-W}eEwNB78=h8jv zDTP3f1QFN^=FOQoaR!s|1TSbRgVU#nrq7ymNoewv=@XGRciaco(LcWwpR9f%ZXqz* zu)`DCkMao zpKuAv>zYf_q?*Z3R&HNITgJ?qGzIK+kMrU2S+gfioIYjx&W))J2ocq zcPk3r!9W0if%7~B|KRyip*v(I?_ z8cAgT<_x&*Gd?^)GOl(c;SCgo)`JVTuf?AgV$c|HFPe*dB>PEpQg>6 zHh2ES=^_7AfL4>>hG{b|o-%2!pX?1U2S~(D!K35tZ;)Wr^!d~Mp}Dg!3{9RmcVYebs9&>{r^Y;sMo_illBN{MmuexDJyDM)-Jn}`wsoRB&#e+CR-5u|3|Zn z%EKEV(^r zd-DX27Q=m+_W-MkPOd?@9vJM36(K^5_y0SXCvaK;Uj`N?bp#T#x+fU>$B|~Csq+g=@$9NdTAe+G(B$g=wVX;2t}wps?a_G-D|Q^T*L;50HHC9GlCn}1|g zNvHFV=vfU9;VDZjQ{!kf|IBMZ8^lmU7`k4=U($IrieAGFf&3$X^1I=!c>bA>8`Jqm zp2ut05Y0bVp@|#rDB$_avavBHJkWOsD)P3`lX$%FOxu&m!ZU4s9FI9)XzbQ_;hEO9 zh6~R$uP<46ra4{S!ZXb|##ea8I+qC*q}VL(JslpzQb)KLjyoD1ykq#Xui_o5=U zh=>6g5th8Rpu`0RFb8g{2&jmoA|}-LpQ^47v)!xrz1QE@yItp;I{&G2s;aB2x_WBS z2n9bnd1nrZhLA^Ij6sdO(6r_gKZ$kk)lW#Sem8(cyLKE* zqZM?LnhuiL6*h-gie91I7Kt9t8s!}%>M%hAW^aZbdt!0zo-r=a^Vr(K_cfI z4LeA1PBC*zq1eUU9HaoOFTU83u_@FSpQie3rc!rM>~~~rO40sUb4bDW#r0JO30^He zQE`yq)#88X4icPG+{j6Sql?d098zTJ8DR$rE-XG*caY%1VlnAq4mseQ;x>w1DnO<- zQynB~XP4`C63tl`U#2)nX0I@_Rt+9@>id*gGB!7@06lq7Y87PPN;i70vn_{^1unx z9#cRHlK{;ozz19Qkr3D3QU8Ml&D-R}IcgPt;q<9-mhUh-s_iqxv^ z7*V|#!PRly;ib&fATDV{*%n3Lcxf0Z*0pb!J~wsg)oI{hdf3EseeWB|%E4f=IoI9T z7oGUjCU71={37ur*>e1K zy-;s9X7eQJ0uP683P;_UA!K}Aap&EL5s!Wk7RUsn<*7TEc%>i1&57Qf{G6ln?pB|Pez%BeShg7YuUAl-T4w?xb zW_&}DUSpYYd%%#Uw*{wfk|3BeVbh0X3?4nGPH!DGQmu)1nI=;x@bt!EnL?qaH&tYc z3e`Dkr098ey67(uYkDr6u`6uw$nfiRDM+a@zmaN5*&dRHwIaB?%@q7QePmwdLxHD{ zGgD-Wn5rN+GWy?HDM^NuPG|ynJljzx@5ba4wwXu}Jo0 zBva(i;X#?A;zm@NBHJeCWQq#^uqIQ45YvqmjZJ18RwNIJ7b22H08dFcdSIGS7L+{l z^|N7_BJkHF94(8^Sg1)JnX*!sDS&U?kA$tCxVdlleq9Emx4>7Md>KQKOnyBtb0L+P zV5NxpYd|ugabH$yq^IY;U3zxG+@(;teR~Kz9+U!}cmra0S;mV$3?cnOkz78DV%lnC zjz>M%l=rKMgGv1%sssPd)Q;}%JUDqrhrDYxRD~Vw-C2m?4qnx()jgVf+;Ky|RUv}5 zBjm0Sk>CEKJBwPxj(+YugnIiScQATp*#4b+HfmPee~-8tNw$-CQvvhVP_-_;*8y2~Jh0Al zXYt>6;Qd*(>cC(0*wM@*9~JL14^vPhc3d2AHHG#j?6|@sAGxKSM?P|OtBAW!a#`3t zA7vZlkqxY?bT^Is*KT%P7k1^*3j{klsjfU)rP8;ZVaEQt6oI@ ziQyfW=uqjxzHwN7&D%J#DvY^wh zpd8h7;Vw|IlsJVT=(8$TL|qtYWEGFQF=#cqB842)bkRMk;#D^edboby6;qscgsWb*AUqG}?Z%)nV#Q}cmn?L1t{Cc?hrG7Wl|!EXP;=8p#n}^e<4`4d4~%L?(+pn4 zR@XdK&>cayJml&ZT{&PZrW;v-KlyI-ib}eV6>_Mzu2|=mhrhzG!Hq-jv{mr+nL=&+ zHHKAL7aZQnyym8jx`RbaD3AN&JZ=7|n4Wjh$)9zef7$HTd&s>^P5E}2^;u8kW_&Ns2HjhLY+v|G*i(Qb zZ1H>ZX_wJ+`@9wKJv*C`-y<&krzRF{%zFxmZCh{Uyao6ksW&xm0lw$xB=9|K;QOew zs5hSrtW&)Ocq!k=cnfepz8>)w;JdZ>LcV*foAC`>s{@`I#8xqWA9B|qHg&BHd28Ss ziW6_YWVz?U?9}QQ$ z;D$w+cJcP(=tJp!ja{FH0pldo-F2I*9*+L8n_>K6r9yYj#qT?NBQC|^Bj$>C0&Xns zgb!R8g->bzaUzArHmoybDMCTG;_VSWZV^0J7^_Pz%TyfbG6DT8&K4a=W%w z*McF*t`D=-#4+yKwOgx3hLYWr$V#UvG#=d@Rjbiy{Jgs)Q=N_h%B~GcbvneyhN_Y2 zt4zD^2e}XyF4%pCTAdE-ci*5_r(-O&yI-z49ZuLCj8><^%-z=os?$+5ck}t%0ym(z zyH;q`cygA=k9Ye)y2vDCi&`gDsD5qI-R_KVX!)#+~#-DL&ZH^tu9Z|Z2)qC zn`sET>!^!7Me)aMb$N2b2U;PWe>8K~{%|!qb)man%@xvVC2!ZEP$8Mmo$TUm+2MV@ zov5l|rkcF?#UHu>?y3q`<5FwgwcB5fPTl6Nw<6W()bMu~tJUe$`&9iS>cXHeY0zM- z>J%4sO^HjxoT^jZloFTkJg#aK@=)E3?vGU$XT8{5`H2A!HjQ4YP6~Q(>7HKY_d=#I zLsh$oM_%zuV^>AJ*xc+(G!HiaM8Vc2elIq~v+BZ(7n_@Qk?O_fr%N1iiR45~(`ZD>EMlR-G5{$jx{6SDoYK zQ$EbBIz#u$&5M0z-iys$e!Awx<^}s_&Wp`mep=RxO_inO3d((H*Un9EwVS_-=giB;al0z3XQLs& z?#J@g)zJuG_ZYPrgYWU*eP5_LgZjHG^E*mL!df?cV7LJ>I~`ycVC;S&fxy+ z8m-RYs6&1 zgIrd5qh`=MckD4Z)S+KDH1w+p-hAk>!^7xlx{-mu;9zIcJIp0l<-l&h8_V?r@T#L2 z`{5lM#ngCPhUfIz4@y}C2w_aM@Bc!rLYu1o28JWc$PW*SP`fu}nlz4&pkea(1& z+HsJ%Uq$*Do~HbZdyxJvJWcYIy(381>e``a&+fgj(_#&uierXB7-D3?VE{ZUc0J+U zoHhFuWRL<#cMDkQ5Z+jeL7rYy$M9#(=PL0!^Zg!!Z|r?j-%faCsq#Su)LLD-4ZtRo zo|GetG;*}T^|Sn%Z{;YO1v2Q}X)3gcmkUA|-4vw-qc?42DoRGVRBxJ>ElLE91O`n- zaaAPvbx2%e5LXn>i)+fA(8YCg6tyUkF%n#Fz(`;`Sd`L4f}4_33=SB{oN3# zijg3PJ(&{;%KucvV37A_hm8cm%=Q}zvSxPHNWe424FrewiQL@1bH8qb`$A$)(2&6O z)2eYzc03(25(M{j-bhg4=VU|z*Tti72^U#9Zw7I40K`e1iT`h%Uqazq9|dt)%Mv9` z#3gS7qj+8f*SAn5dxr88ne0#%k?2c_XL3dY88Sn&BGI`^Cv15f4CEpeIw)sfU}x@# zI`}AU{7K^fvlI6DkeS4vMEiunnW!5az{D3RMgnTqG|wTyWcOa#-%2(g+?98XRO3UY z5O(8qzd`QbD|*%sMjhk^e37ad3D{bBL$)AGs5ko3t$xZN;PAP2{AAgEci`t9$KEpx zAM2|6rgz3-+GAfS2A3S&aM$RNC2GcR zsNW*W!W7TbFey5PwppyXJZJE`BXJ>tQHl7b2^4B#L~;ej8Zq+$iLTTy_YWIv?6BZI zDV|K~9_iE_-QBFiIq6~&v>%*fno|ceKTAT` z;n1XDG^*x>V(V3PYCeKPB%5fy`gx43i}&$LOU;>qHqQ^?71OaA}fGP z8j_k$9r-p`?2qlAFMbo6#puyIALmUY)U% zle+BUseTY9b>y~b{1SOGqZC}$>A?4e^G(k3y)xuD2o^gAPF%b>Lzi3%`)fbck*eFF zS4S8-tqG|;rUP)0xKcx+4kfUC6kYa;bD|)SC~RFaENCPEyz&9cM;sVbG%tVzSxz1J za|A{Sa_MurksxP3A2AYCT0Y%LV&sN-QG-Kwz~>bs0h5a66Ar}s(jDY^&EOE|{IJ1+ zyB0MHA;H?V>)tDLQ@?h14jF#O{ey=O9f=OkI#M68sjsAZVn>@CCYLQR*edNRj0) z<|K;}QJJ97-b*Q%2OEm-!zEoKfAKduigz|`6POwXby5ddTs)5SK!7q%&2lm>H}C;G ze1RK7fivhAOorXsv{^fP?0Mre%2G|v@r#d!*EVi*6TN4|2>cSTA+lkL>ZZ*l1Y6%x zYL+xKzV%0*o$klCQ#C{xp4w-%tvo&WXmZ*YhIK#;; z*~-h+MnV`|{wpsc|Caqa@-rG`oyo5XU~HlrzYmb8X>VlgSlsu<+;5n<<;x(kTO*oV zFV8q6MRgr@w%eNu+@hyyU7ro_}XZKR+;D}dmfRJh7nR`mP-Cc z5SfMV{1}DP__)rJ;y>h0pG-3NC3@IPiy^UPj9*BIE@9k#qonSV^?Bl4(x`KjOB!{; z*|AB7OE1NQO@7EumE&_Hhk#8xHiN5r&CJ-2zq{#Rsw~6q9CG*FcZ?m( z&Et;6=Lv3YCQAC29-#d69`~Yh6_>S|HOwfzn)+*ba})`%rdj%Z>e0{@F(*64nG z^}-0i;^rZ4ff+W-1ag8QrR~faQh!6anQ6Hw+~2b(AhW&uup+Qfryj+XFBEv7Rok|> zuRQ*qCX#L2c0f13WnUCY*3{ZL%j3IdwhEB?fd_`P4GckRc__d!Q70}TLu-K%2;e@p=`NB(t7;nvpdVfH zAtf14BHPM;QWC;#n$lf3b6OBd2)78(CW93}Q?hp8ftG;)Ca)epk&;pPtQ9$F&1|F$ zE&-)-NJ2AOFKIqTMG~r-wxGQlD}L6I1W?m9^whiZjG&Qh*%J5oj42!lfE%k52A5r8 z_73R(*HZavUxH4;SRU(&G&fG{wrPgcRHT!gR@!eccXjgvMW$bba> zhUE|%<_D!7^pKhrhg78MaB%Q$%5v$B3dbnfq9cjE-O8OxP;Tn(g?Xfqu`cu7nCscMQ%a9HEfQHsN+q$yU$JBS&q@(ZP`H0N4Vl zjo*eL#f|G|NOdGB?lMxdaU1wTppywm#&cEVSS~d)3Mp=$Lk*d4nG`RINGTpY_d-aW z(@)GmnioJw6P9TLNx=r9!F|6&(r~edcZA@Y)5(JRrW<*F=X$m4^`A*T2QoIxdX_xq7cl#IiOQc-;-OtR%uk`Q$Uh3sgRn|awWhfJcJX0s#ups))bm3U*R z3XW;FfZ?@?J7nXAfG3-Z#hnQ?tA8Y5Q;jITC=0|;HrT*tkRiewHPv^Zf2dp8%z|*m zG!~R4Ceha(4nou@n%R_uYwaz$dT2Ig6$t{ns3W1aLUIJa>)7hqh6ws1LxF6oF!EEQ zY}G3SZgjOHLOH23Iv=4H)0Dr43wh*-O$`j6atj<)813N@vY>x;s}*=oJW)3_irQoq z1KeXmb}rXUfa^~6gMPlz5t|iFL|{SInFsPE%W|OAl{Rp>H{Mb~JJzCcU=hXmQqm8b zdB9P?!5O3}(mXKaV<`PGQa}`r7An>}VsOca=;9wIjdiFB@TxOPLlVu!j5`YTdsNbR z_1emUNaHxJ4s0nG*Z6>+&v(r6Ji!)k)O|f_)Av3Y#s;`p7&b0mi5M4)C2NViSP?W> zs}GCN zkQZO82IWxLxcE*nE`E?QN94sXs=+!MHZJ~D#09=xVO-Ra7xh&`=3~uZov0WWekt=0 zd2yO*u+9h@7iTNR#ko?Zk-TWE8mx=M#>HidadEknxl&#(juyN5wF)rFknfCG` zs2Z$JVdJ8!VqA2SGCkx)FV$f62^$yv6yu`5lo=>52C0ID4@1%?=xWm^uGr#DT5Vdn zpovUeH1Hc2Lsj}n7G!!yY03|*!C_iG1!ZWK2CBHY1A0dJa4|{&D~O9RA^JSz{oPJo ziyF&VkrHK#W+}Y(62W(mSTJGBI;j>>th?a1Ny2v8lR0Eq*26)g6)gOciei_eRWY`# zuWqN!M2aozuR3TMqTLd9(1Jv}-9dXiPqd+mU5-}j*s?oxJMC#MHwqkaFrQd6V$1Fd zJ7^)wd#{rQ0k*8jL7SZ=T3i8(AEa+~m}n_oP;gB&KhZL(o%WPQw3$v?glMzE4mpKr z{8quqq>q;J*s^DIPQV{d3lQx&)lQ=oJGP8ZSaLGS(ZU^D_Hx)E7bMzZ#ZIH8KelX% z?x3ketH57zkiJMU6_~V%?oKX z8()p4y3j(PRkZN?jDyNS^YyHv6*%G`+Waih+TcXQ!zVl5^H)T23yc zJ%e0@v=Xg4Ek+mxxb#8@SDEYTi|+T~(lqD=|fX*0N7i6n818C))*Ng`p) z@KfHjgEk#0Rxu-Lmzy3TT6xexQ;7D2YNus#M0*+>aS%o(N;FkBNZgi8fN1l=cG@&Z zunN9v#L1L*T99b3NHLz5-nPO1JWUcwF0B&nH76}ZwB=EU91^TzbL%@XZ(N#Yo# zVWO?mB#|&m{Y2Z~prw#v6xfls587$T9MN`3630kJiS~{riIg`PAle5G zT0$qeqZPED;&D+ZTl%Zt5)=z^Z0V!0L>y?#e8G+_yE(yzKbD(W`5a{9{S51x*ZL(&Ns7mn9 zgR?ES{93NrD7(=^a_zhO|Q8^ccWy%CAG?JY=SQ8jS3+-kJuI_Ru{iXmJ-VH?K!x7TgJ7sQ zNRC5qY2=qQf~GI>7>ypUry}&?!RM@cvDpwimKEb++tKKy4a*-0Nj;_w&H)gA-=nZ| z;5NMWSzhKP8|Yg<(uUtH8%7Vf>JY>lu;L{F4;#kkq#nx#$3Q@YU}+$0mlHPp8k97$ zA$BMztHHKLx={_9X?vUXrk>*4^fE44cgnrr1 zXqC&h`UD={|E*P(dJ}T!rq<|8yWdtkG#rliW*diYstIg;>!?(2+OU3rLyp&n^{U@4 z$L)IaYLiBO*miDC+O_SxsIaSQf_7HpJTLTrY7y$`G{iI&Fw1aEjB=c75GNj zW%-8e=XSk4O{(MmqK}*zbp)?joAtD$VaGEdcOom^5_HxPY1h)#8L5bLbGw`aInjQc z14vPK-RjMV8UAuRf)xfmt?}pFSu6s>=WY_ej ziW$E9RWp1ir25?myG~}spXA-cxBQHpET3uD-w5B_AVA&1x72xa+<1%G3^(4Q8_lps zXiB^JM*w>YE8ZJ+?}9fs3skdf^J8Y2$<}!qY$)iKdCayP8pKR67Y>Lg5?>=U02ngCWqR{X8% z^t^;|K0S$7;tFU2#_C)-%$1r6)5MQed$R9TR(v?)0rQ2!k-Rjo?N_TuRA1XTcUco()<82w@z&ok{U~>d|#KD7! zB-=bLW2bSuHofncG_tFzgCdKMTj}kWzsSHnot5|s+8r}K#p-Bd$bM5qX2&fMp5q>)ARt2##9@xwb!XMevD+%s57{Q{M+h!@Ca z5oM=uyBgW?TRqFpKa~K_WF-wWr$sWmtuvtPD<9B&br7D0d3p`ZxM&!`#U*(bJ7P4s zl@I70_AUPwn$Kb-{vcb?D2(eiEOu&;O3+Ycv6HbTaVfA_?4Lolr9J*%tWfIW9L_K+ zX@U$a)&!|0NL?7E)D>a2>L5~WR9*y(fJ?3l&7FDMaV*v}z+wT7#ab$o6>FJWP2+R^?O{Yps!vHW{1>E9nrHf+d|p&on-7KZ{)j)>R6NUF(;u*tJ@t2a|8I*fq$X zhb#txi|OD(WMC%>kU?KuzFdnP;URsdvq4-3-x_NtmOWvR9`Y)KiOA#GK<|D zX0iT=N?(iBPtR2OyRg_T5u83&GBIQ3nv|b&#i3tWY;cgpZqKn23~H%XkQoC5E4yAa zhsB15SZs*SN*+>8)}y{VFaPRu78{wv8D=H7=qBs7;29&%>CIwe6c!tuWhIYgP1fX) zZ|SW)SuCRB46u^h^CoLZ=$&hx>&{|RGB_1hGSz3Yio+`gJn}n>;ps3IgIU8Y)*a!h z?{9vD#ZtgZ0t>S_()dK=>Ai>UVzC)8emaaFX|YB{J`XOqn#Ib(EH*RGN>YlMD;+&& z-1>nm_5^axLas3u>n^S3_8%fFHe16PVkMZpkXSP^6Zf7ol*LpZi#?NJB{PF2t6U!z zitS~w=b||MtYlWkWIdVx=)S|}u-JSkoDYSwk=^k8GrlJ-oAexuy#$3XLZO;9Suj`;^>_- zuQ`UrmP27hj>T5xB`daCZFso-ZjhoZRbOGTO4E$k>)}sB+Yri11yWxf9ow|VpEDYL84(5Hh`XIn!?`y2&J>Gsl zMwX9IrS|aDf5G3AVKI8q0e^Lz5f(dEr_^2zXNbl2bIAjsAMi2$bG9t@b%d>YQsqw? zGJuWsn-o8Kl5cVtC`80B$gtRVL3Bbm5A!bV2SELx;1c&jM60omi)1}${w61gtmJ%+ z53bIF`DaI&`0*xR{i@3YGgo-g9P17 zJ0r7a7P#ktTmX$Rr+~JylS*`2fDt7jwHAyhG0`|oiy(I{-Hlr1jiNTwE;+jKVo03J zN?HKlUQ`pWDSR!Cn(;(*NRs1WKw&(*V?bfxU6pI3KY9)%&clF1cjB3@ZIcmbqAYIZ zn;WDuySdh~mD|uhWZH0T)-3b;CmuQ;5DF`4pK;n?miel`v_XVY)LpWd<8=s|c%7{> zFUo#$3M3j~fCT5;eQcJwW0Z8z;pOAGL9a4fwsIS~!WI;j;@mB4mifk^1HOdz^I1vP zpwkAk%w04H@WaanQD$rMh~r_vCh>Y|W}M%;{J6`Y>jDhuLQXuh%ssOP-2X+HEnB$_ z7}ZG|LOHX{&kg-K1&GEN^<|wlm}Tz$mo|tp_tm7W91r6`iPz5>`XbaaXg~E3OSZ{o+NeL?x(Q-UFcuGc`16Usi8otw z;NgKw;@xYtzr7=-OoQ0vcp&p?f2vgD*$0UBXSGxAPdutgyzy51d+y)~L!s|qc$D*M zf6qlFV9oxt+9}7wL!QK&lsDsdeZ^bbpzaDh1bVf<`P$#Zv)U=g!{edEd(>y*B_BPX zCcdx42ozn3K3U-;8%ryLItmJ)BW)&5?4zg<)4L)&{S?}4{4C;@Bsr`1k59v(?0 zUa{5w{(QIo)lk=zl}z<&f7$5Y!?W5c$HT*{#7kK1@9{I=stt9`@UR>5DBn^E_ZR-O z+9}6F^Otz(s2RUgMzneu`kLc0*{l664@$tA{b{vRj)w zIUXh@B;Ip=Gk#rCZ?=G@Hkh>VYJcLn@vrf$cFOVQX(rwaiitOC>Q9THsx2#d9zJj# zPlzYlzs9rLDaXU~i7emCR{L8%sMZvyYR5`m^n2imXYIenv)U=g!<>x7TWqzzwY8q2 z{_`r#*@Qjt-XSP{)EqynopQWa{Tz=T;p9X+-Z(ElC7g$@t69mbAt#=kXvZ9i0mtjh zK_po0V`@bFARCSuRGUH*O(->jkr#eT)AIreKnw=&dR1cVDlAJKmdbr~Tt`imC;kfnri`KN54|UhD z5)B@;S47isPCQ|kHK?@gnv$t*mo+%E?6Mw4xLq5f)dRXk{~`5ZIn-UtN;WDUc8RG6 z!X(|ot}DWnro*yJOiW1{`OAJ-c8Tc?;&HpSWz2x)ss(gc;O=*S7!J`OE7>0KFwnYl zSO!|7IcZ>_G2RARPvP7^Oa@ZRa|HAQ|EIgycTm}ZmAvB>Q0ocAvg`jPpjO4@cI|Ps zYsHAeZDChOR`RizT}~TBK%JFJv`}ZIB7f1Wxb&kHP^%?#yL8nI=oi^S$L;sG89SaH zfjY60&%F%ntJy(>f!5=r3@9xJ*yV(QPNPK&wOTDV@L;}rKo9xq?LBP_)OBVhU;V$@ zsza9I~*u<+>en>^?LpcJzZGIcR7!i-~{&WLYz+WHqh!8xq(OW zW@LX;3l03;x6Bv29R_w~CBFnc40J|O80a)wR6S=E6_K6dh_;CA4tUC(-FZ9C>0seFXLAycv&u=1b1oKte|7C|VGh>YPRuyXF;;tJk?22V zUpY~ctG)QP2r33G`|5PzSnZt{9Diu>wa9Zli~XV(toFvY>ny%KV$5a7cj~s)-uR~q zi|cSr6J%!by-}QgR&sTYQu{QvYQJi%y~Mwau=tn0g0US(O!u?+&)g2Y zc@Y04P_Wv2^5lazv-nY<9*wYs&o6Z(eA;Vkez=Ln|3t1IVc7l%%95y^#fi4#SnWO3 zZR`asQ4e7CLWQfn>5G=J#IaGF@P}iy_p>t(jbn)uRGcuXuUY1jetLW5rSn>SQ;!D??@ z+w(O`oCnr{Rx z>L0$}2PB0h?f~oVkjc8ow{2HNkR|TYSz=U{CB_F$*7$rw{e^E?Vq6aF2un=znXF0q zNr%?XWQhkdEOBpuB_7hjOFWF!!+>}!M5!oUWsTL|#FQvYO!2csQIL4WbfvOHjQXEM zOv8ybi#M#1N%5^<5Nmwfk;zAV)dlH+nx zQdL|e>(=e|{KG6YSRpS<$)#e<~uVblmP|Oiw zsk3>|MY7h6s_7@QRNE+38mY5Rz(ta^s5kzK3(#Tz$#v4|>JiIJmLyxT>+myd)qLu|HPT6vhq5j@eZOD- z#4Bvo97ulamy*0ntWqOXEhLTK&sH749c7;;Y39l@-xFfUI4LPEMBL;2D8kT9xoe&Yej7!OpfQivU|l9 z`!_T-3q=Sx{@kBi(IgZyMY?jZqvU_CssydKB_jX*=!^gjr3+sf|X zX!lPb(U-+f$-9>sBQp+$KVEoqgI;B}Y~?n%uk6-(|F}NTej|&YmUY@7%Zwo)1o+`) z11~eigNB$WGsb?>$F`N-QyZ7jgj7EkKU49*J3*CtYR2=2r5rCGMvW5Bwz4~WX!q|R zh9U1c84tXMf7y0L`A!cw@X)18Jlo3dYj3JFFVUaH8wEY^&dy0aHJ9%^Q;wJK_PmK_ zTiI>!^MHL&htYmxulQXk;XLb*DBs1J6y$jBE4#~;^;;l@$B;|B;&*vo>Z!SWS7xOg z#~W$25!=e{4O5qnf!IJ6Z{iidmKmw1X1q2bDaY}~D5gJcE4#N%ICDJ2Zej5&eID_n z`=vN)#=ABzba*Ru*sO6~B(U)KfEFJx$7SJUo`k`e|F)J=*pAGKdXg z@m5~(>*|+!YR0qLDaUhP*`0XJQ?EeXZ7kl_D}LQ2++WmBtDSPZhg7qCww2u-S3gg4 z8n?4}d$0KQFym5l`K)%z@gB>Xc(#?@DdXOn3%tQB9*lU@mtMLoV9j_|JLPzI{FL#t zt?Ukt97sc5n8iDL#jnrbte;jp<#_HZyKjUlss9|p;@5e_?1E4u@8Bk2A&oW=X-9(dxZf*@3&yg%X zSoOdY&xn7GXSGv~H%~M1Y%9Cr&P(wuVVez{P$|n~nF<(MhbdWy}(tpgFP?`>+9aV@nB}!>JxZfk<)EQ^mTaENK3HSo0zv<8cofyI8iF?^C7lR9>qFwlC? z;Rdb~72obSd?9qi=%sX{yNksi{9hbr4e~6z+Jx*j2)j}NJB{0Adl(_R;*TkE)gwOD zkEbbzfkly$O<(STj=Nd>-w|icH63S-;A?iAH4-K{VW6`h!a&QJ+`w4SG%y({Fc6UGaSy1o&aumDUZC*(79|{?}-iF&RX1+%Dr*Vh<=jygL7~I`2W^UKYo+q2pF* z2Gm*WMN@SKPc&6$@I*kZ#{sfc1k`HgWEbs-p)RYyu0IozyJ6RTEdI3L!!D-{!Y-!` z!Y-!`!Y*g)5O!Hz4fmI-n-y(-wH4I;{+=TS-U+JCC;=AUu+NI{mo232F7Wz_m`qx1JcQKul^!kO%vF>_t# z|8Kj>p)A=|VaYC8@w-|qc|AU9kjh}2p{YK$EBr=r_(kkfjPk9S$v%ElN1x30B?I@d zWJtvsV9A>-)=imgdgmOL><3mqum)PJftlNeZv|<9%1Y-13U;HeT+!(omb@**ccUi5 zs);ou-1F-GV1SgDiQ!#kybjz1iv&mb?$F`@otQHgiqX{oTg4 zWyuM7ma79S$DZ4_f~zmY7DtuuxlKN5nvr}gvS?k?*IDw>C{901PPSN6B30k-*b5R^ zll_eUC>l!^hneQr3bxt)bIvQ5vt&Zy+ia7i5!0yBe7ft0KrZ#MWGaKYhLOz4UVBiF ze|yj`h%KzRR3%Yb8*|@-+T!@N!{E9w)dVT2sC;xmYmL^v*1A`ePml0DsBpBDJTK!S zStmC0KyNfV7@AO|V)03HfZeKRH9?DQpjMknw+s0gPa8822Odc3Q-2etO-%Tgz^l`B#HdOAs>gN;8L za*?dH{QL*UqY(hT9Y-h0Yt6FTbh4kXe|R|R7^=hoRqAY`x#;w@eDa0kS*iibKOrwA zpM<|yvaL?lNYWl&=OnQOgLED}HWxqHi=wi z;feMyX(E22&nFr$U!@hlbyj=O<_+x)3A`PpdBrcJk`6j*#+^hp()N1?|Q{=c!YyF@Weff=vMi}NP}n`@BN@zUp}_t zH*vt5_dp`S5+4RU>dW0((m{t+J~uqeE{^xH6+iwqEj?T|(;nM?s2emTSz?b@{M_n` zTl_4)b3EOO-(D+z$!1p+124rApLxa44bQE7mLE9Y7gqcZSn>Pe(aX;Q9$tCe?-jrM zT>L4kK2_&pjW9duanbHlUj;&|Ug%=+@3 z)&AIt!|Fj3-Yoq#>``APM+u7#3r~!*Bu%tGF}@`l$NSET-;Y-O_B}9i93(O<@q<_V zN=XGjYR0qd;&?}_`2AwVZ+K$xH0YYn5U`$P<>Sy@Wg!7%+!%wCzW~t*4WV}=BoSImB z{9{!tb%KsFf^k;}-c0#(EOk+^V3J|gqHL0-PSbFP3Z^Dr-ZyU@OP!J9QxndYitDv| zPilud$Sp#R;rFev{QF({S|Iek^qXur3H0QxmC+vV3a7 zIfv1+W5r>Xx)j!53hT!QrH;h-{0psyJ-|}`LPf(X#?G09GnLLGSt{UXsVfm9$JE3p zOE+J`Qq2`UHQ}7lcyrK&jajM{uv!6YuxW2%uofD$=W4tOo9Ay;JEta=wtHbSOSK2q z)v7Tyk%E~tHQ{_)`os}h8B2A7y?9&NIW;jMRoll>U7@23>~+i}^jy9rqOsz0!9!i3S25g&{i=;u=t&N+7c2JS42PUl&n|0{SCa_+)<-&OG#DXJ-Sn} z?s5BuPv$R7!_iXG{e|hoow?5Zg=rXTNP4_59iRW;%5~xf z;xRRG`O=O{`P2m3H0dNs_o<1#bNnChsR=Y0Dd|2naqpdfY~@oEsF6~VS0S33KsA!I zi8}CTY67i9(#)v|bOHuV^i->F3{h`o(5$Hm^n!xsIW_THn;Ym+43n*MP}Ls~kT@N- zsfnNbg2c;jOce;v2|+ou{v#{p=vEYWpPE>r?dk!sa+aKn-pCct(qrA)UGR)rMwlGW zeQKipWxE?d;y)}oAMSL+!+nEv&|%^kev>plbTL{V(Fo6DYT`$AZ!1X5V#yaX9(X6{ zq=Sx{@hrPIp8M3qld*?sDE|aYE>t}5M7?m};pR(eI>-hwG_&H&@fPalP|!9t@qBoG z1i7AM$t?O=SAV+Tx%$)c1IKfpD$u{bax3tjV#%dZ54_Vf2=K%5r)aN4G|Ol7HALfh z?o%NXmX4-Rzs+XJ6@Cvq#jNKw<5_lbJol-B1~V>f0lcSKa<%G#cYy{0epq;-{S(nD z-=#Vi!XJ*eDr?5iHWjkq!P4^~ffb3@10Hymo|^H*J%%tjp8M3qXJ^j;4ie9>WD86Pc10H<2!K?kb;ko(K@;k?KpDOsi@sb~a_bf|pQ9Q~Q@I!zf zmOsT^f{0f9TIpN}e>k4|RLI_?ooQ+p>v!9{+MlJTW;}66B}|UzJ~gqvs{gr=c#b7^ z20hBx-lcp&Qp*pkd}5?QM2_b^HPI>kdR<7&W68I39(dNvi&pu9q?R8Ro@E!u``Bs^ zwyBBdnjPtde9yDw`=~R2yFYV_pA~10r|V|>vrSD*59zl7Z$3+Y?A89<>SvIbjs95W zv;4sEz6_dpwyA>61B$;#t`}JHznVw+x+|oY4$GfnY$9pm{uc^xA^hQZU-(Tt+f>M# zGlqQzi3KeAdB_9L(o-{@7{?JN$8(=5s2v`47!p{Q-KTrt^;bv-9TuJ#XGxkU-=HX^ z>EL+oQy~rd?!6HbFR|oTUhU7)Q!}0zPn&p0EPvXjCZ4GLH%+~~%#w$K9_4eZFK+R( z;>^qEJ~h$n;JiM-!!qx8UhU5f&&{8f-wDq-H8H>4Pa^=ckR=ZnR7s{%?;BuvAgl z^wzz~HxrJzm6hHbWa$c@V-jbge$v^GZe*q7!eSEV(j4iS7!j|7oEoH5Nr;se>-a>h zLaBHbXVCZ{LTRa=m8MkVg9xS5vTW_jP{Ah<4y<^8JS&|6!Rab1EsIFAO3RhHD;D+u z$;Z+y1FUqGpY+etaYhP0h;ViPW6xrxPl5GRgq1$yH+87K(}P`K#N>v`wv<4}vw6}n zSHlTA)@3R6JW|gib-kGlJMg}_JNqXqU7+GbwwH6J##cfc7hQb|Nbtxr*@6!u+!VU& zOIErh$VwNX(7hruS4k+>Tq}N)l`adh(xrOA2N8~3z3U8Cx-!g4SL6#mh;YpW<#ATJ zMq#C^frb4u@^b@|@^fTuN5!$rqUd&40 z&*BUgd=R1eCF4@8^dqo70t@>}WVsTNzUuXNveHjOtW?(vK8UcoMern6y4TN2KUWJr zi16Ep$$MGpfecQi;DZPcj}EP1rC$TpB1HC$?_SN`F;x z1`0liaCWx*X;%6>uzm;Df}EM_61cW7tU~vEpK@|OP`{!^oe@G6yHPhM*hLlm|RYuoGqBGT%P~=B$hrM@j--i;|xnTR*a9Gq%T%j8dIm@ zg9vHNlBO@kB*l^(<+~hblZ^45gY*?ami|}H_|8E(pt5uT{o>RpNjAsNr0vNf6`)j0 z@S0^$Pu`G{?vr`* zFZ$0&Hmw$l+b}OB-6!)-8gNG|mR_k*TntH%$-M3JEc1bd%8Sti=crP0wVO`gsSUoE&MGgA&@Dzv zPSg=r{AwQE@`#4}x%h>HwbMWwo;7HqDy&@)rRqR5*dr>-TJ&6~Fov9{PHX=QuQewU z*GF3ha3e(jF^%h^iC%tVtyFw;b0s;_cdr7u$|iZbGfNu3iLdzqr4uWbun#wS$gTMf z`bOhQxXXx<#N*>G!+%mYeVB>577XR^TLWLt*_8$d%P`Xwr%L&m28?DXD;;F+JdKJV zLLzAkRHDVRl%|8^_>%=jJAz^q%NUChbTe&Qj#jyn|+6)g2s(4$y0Os~{jEYS!} zyf&(dXZz5`kUj4&hRAZ3nv-|pnGu|&lMXt(@a6`+B52vl%iKO>+F<)hgSiji+Zx(e zu+-dwifQ`zDIEg*@UlUKQgl%y$niRaO+4F&FWT?Bw-F>(vebO9T02)G9dvl%%?)~$ z*|L?}fMKxQ^k@4J#naccT?Or{Sn5UH!|%^)5a7rEZUeO`ac~>D!XIKhVEmA>n0U6IG?*SZ=~+muVX0R`9(YTFq=Sx{@s@>z zl!4bbYU0^GeDU=0G3xNvveZ(|18-$m>ZuuTjUwfE`TA!}JllsaYCU|+CWuwC)QW%y zo)(aLYQ|famvS8M7Tv_NefVNz{`3-vz0OjY19x=jX8bngq@J4bwq~Rp$HNnetS`0? zUmO}RWeCLJ%h&xLcsWh#sTpr~RLXI@VThwqKW#s0@We&O`~m0Cjj3VS`uvJ`MdnyuE%Y$MMD}X8CL%zW8YBi`4$`3dUxy z_#MbdJvEo_YiIfHvD)9gIpc2KOuO*R{yU-WO_ti`6~9CJ-@{uHlyba$_gn4H_TdZt z=*`bT>@AkcMLpv8T~6w$xqMbT<#>2-m-WT=lLkZfb^HkGHn7y&UhzAu{XIOZopL<9 zT_*8tAHE3mtuqwruz3HTSNwi5<5F|^tai%r9?P0|whvz{J>~AUz}v)9A9=;^SM~3e z&uXU}Z>rV)Y#+WDKeZ3dY2x*hPqQBJ`~7dm&uXU}4-*v9pSGVgc;Wkhhk&<*rM^(y z@$lgO_sVCrQ;wIi+Mn&i7bOSVUI2A?t>8e;1F!bqjGxs`IUXiOWch3#zQ}yv_*dZJ zb*Y0v54?Kn-z%ThPC4GppowSu@WmT#9=`|bwz1T=9`Q3CC<(LX`f0UOjyKC{f3^=_ z{A=B%mqF8Zmioafe#b`%i;kM{tai%rFefDa`Hau(&t5um_Sw+1gQbpSJp6eQRVaSc zjAyk|j;C7f&-USqR}!7ifiBdQU%lcdrUwYHW<0B%a=dw(Sw7o`FD^V~Be=euEcLrr z{KUk?U*lQrl;bVPnRvDjUu^iyM{D@ISSj<0pO{klOFUaU<#?E9lku~C_#!gr>p!4s zH!H2<6+bcA^VfJ*JLPz<`Z*pwDawyR<0lPnzO&C$Q1vz|t*<-li`-3*c`?GGgW`9P z{$qBG6Aao>g=md4b{ajH+Yibs9-ghIUvAeQHGH)iAHL``cV%zrd54vrh)QOELYD?& z!dn8F24Z5`P7?;w;(<7LMTCKvxHHYP4746}xPh3#r$E^qhYw%OoN)h-P=-11h8}jg zIS!N9h6&u6+%8Nu+i8481Jj7|u{?pfXd~>x-2asYU6I)moPiQ{Ic*SjIc*SjIcuS?%WBfxUuw-Cm{{Mr%L6d* zBUakdqe&Dr%l~)BT@eHzKe*!#=BqVTd|;xhHuX`+U2t>|$yKup-*0$--#831eV?$>4qpCp3#c=AWS9M@u>sh+6>itEnm;hHaKV&MpnDH1 z?dH{mIE@hjb=IW+%|NS<<_4~*`2!Of^%k1){x2)-9q?$XZa0TDiu9Q5LTDw^PV;W6 z0aeP8fh84D`2`HuALQBi>$2A%ud~wres=>4ZlzuxWLQd)z%s-P3rcnxZ?jmumNYW3 z^j3ehs#iKV(5OXv55ztNKkH!^IaVBm$L&hDRP8j1towYtSi>M$$}9R3v4%l3vdj4j zN5%EicZ2a6D;*kkn&b5f$GE?w&SR_fSir5%2&~FM3%xtVRaW6|hr}2FZ@kI)Xk$xe^w;ecl2{gNJ>QcPR zAa)7FC+Z})ILcq@cYZxX8{6<%mVPbF(o6D=cOvTNmVb3iSG+0_;qOE^zZ^ej-B^%U z1^7a#^CKP)A3wA{ORx2_^cuBbQ_8Cc)@^5LO=0QR ziFH`VvT5tSGylcXn=^dbH1%YZ3RV?i?~V)<>_a*6m5txC^v*oaXu+PBL*aMlv-CSb zmVO%xqeFAj!HHqoBlAuwW9j!pd~w*hDdmo-&7th0084+U6)f{Ud#65xrT0K#Ltyo> zBGxCp(HvivcWxmW68ZfMmi`k8 z{|pvvA-O5tJIAJBM+_~nJ9nt;uH4;%O{=TpjG!f7scnrt$@8l*5qpSdi`$ znH&}i(yIber~86*{M|iOVnO=-kknZx;8G%XZR{RM(t`9?X4x+gw|!@ce2q`(e?%-u zAI%v$J$9EIp8U=xzEF&QfFv14{f~wuy6tlowZ4jc)PYr=jmq~_P)c4Kb&+IkM+8@~ z$}|1ckx9umnv0}w!PJX)qp>U0lNpkt$yc76p=K|0KZz?=si5wx4@ufY9kkMkpe>FP z4K+b@n3d-TsM9oP#**{}Izx{uXvo$q%gw=3ZD|+zdfuJ6?fs8E3=#Ce?O^=X02PPz zikwk)BEwV0ZAa)O8owQ0g#UOHA>H+jXA-=A*ZANCUqIpumhR-GTX>7~Sh__yh(@|o zxX~E8Q>%;_X6PRH=FhJ{VjoL)4tdxu{7ZT)-NJ7~Bi$Z5V1D}N%1a@!pQXEGoVw*| z2W~E;gAUR?Ps4wsHc1*^t-|eu(sXdVQc=m_C;P`on&$s#4~YXTeVyWgx7N><;7`qX zmR*GBu>)r1ksf8x^d(Do&wJo$N_9L@4~b4Ti1KZSN;zJ>f9Wz-aofj7uB&$~&4zr% z(l=-xc$OZkd~SH62P8~hz8B3pZT}cZoqx`n2#K#*x=%sfFyklM8R@a`L~kHzqI{O$ zIo?9EeD;rlyzy)4cgS{-rTd}D+1pT!cy8sh{Lb;*cfd^S$ff}A8k1tNa?qf(CJZMEu) z?c*bl{rpoGh#h9>d%fD9rN@e&8=e?t5GKca+lrsu7c_Zp9>xyqlA=Ez9W`DZ98syAO4-<_d83^2)N@J<7g+ITl}mzbAP(; zxVf$8g1e#W50)s%w{9sNqIE+02z$_RLEmHggTSJvMW#f~zc> z`Fe&@S`b&rx-(*CyV%#fR*&u=`PiG2{A?zF)|vS>vb-H+W&iLaTiHJ}oFP`$BtWSq zI?f0yyOIFP0t&9OtgLyCQY|!`kZhHwRBIJyfR$YpqSVzvT;*8VH9X(73a*f^lb?8< zadyhEvaSJ2b=7f3SlRU%O7)21^s}-XvXtr-##Nq`_2v0)1f?(X-4r2Se+5@rRyHt4 zsarIhAyzghPpR8foB>ugBt)q@BDl)2vXLsK?u67xot2FZQtB>9jn!D$Jz+{k{J2tC z**KmWkJLD%CUVJ%d0a(V*+V?_5K<2z^_WiiqB)#lRyM^)sVP~UK~`20rc^A1E1i`k zqLfMoaHX-bG|x8;`KEaiy}d zXL-J7k?+|kD|=oi-uxWSFe`h}N2wRHID@QgVVF{jLb%ddSvE?kR|B}xSlLpZZyE9} z3$wBnLE^2*ehtsfAhDn^8)=6~T%Bo5GaZ?8lYL%Bq5tszSc1 zC@aHo1*u#Hr^3qK=Dc?TxYAhJ`%&V3fYkd)eXLOG;~dT~EBmiXDLsTMot1sYB|nGc zXBsQp$0hecavvnW43p$neq5=n>>$tg4e}k-S=qN5@$wOz`2RiU{Q%zg;QbgS-jM*V zG*U$$4jFSos+WD?eK&-Z@B}gOn1b zRHFc{G*;f&N2$hHoIzH85tqCek{2ti{4y@t1d^9Q@?RQBUJ=2G|4n(mrpVVc$jVzN z#A}hm8D{0JIj=Q%t-))n6R%wcr^3pw)+p6Jf)oFPTrvpBV33t}Qi#_nhcnE|yK-Jv z@VbK6O($OW3{HiW_vDg2A=wj>y}4v>NcM(gU(V|bUSIHT3RAxReq5=nd_a&=1M)bd ztb9<=?9NWjX+PuFfXi>iWZzVHIE5pN96 z(HT~LSAbG?={O^-JmRNRM8g^SKfJvUycE;__`k0tB-v1k{!B#PAxlY;8mUC7MG_@b zN~N%+zf`7wxBu15q^6&#BDDfNm2=O4h(8FM`}k0m zbX4aDhELeE6CxL&s=o@6^SJ6lX;a7Jze1$044Vg|!#ajj>tcV4N6tPDk@^AH{5U$4 zLXJvG-S)_J2T+9KMjAve<+YlGK1@aWpeP8DOH7C~m7Q8mQ-LN|-VBk;lejAoxjN;j zn(OV~YgCFN6(aw`TG#Se*C~H2zw#0k`5+R&Sl0)fTGyL<^pSCh;2kg0663W_II0_! zc*AoSqezCx4H&O2uhrIkTXp?siTU! zA0nMhQo0TI&Kg7-nohJXzBhIJn+%aV{IL1A1Vk?4Al=N|BR%eiNO!!q|DA+LH`S>X zOkVfP^#(-lO2L-Xu~snTsP6SWetgE=5W&0YmUA#xPu)@VPIcV+#b}5;;D;@>u~u)* zQS~)%zoJ?Vi1hQp7961>eR(V;xnszLFhu%etjn;L!eb3I&Z~OyHi!%|VawH6YoOvd z9Flrr)Yrd3(OU=HHK?HlombN-XhVxjVWA5J7#?=h)lv*eHDmI z;IY)?;Yrs&0FlWUYm@;ImB*T9oZoGALx@brSQ9YTG#+ba;`$Gs#hy3|V@<DGZTP1m%SZh{S@VgtLK246Ta; zq*QF;9)idss?$-j2z6ytSBAPW)IIAbmd_fv2O+X7MM}$c+yfAKE=fwytGN3ivWn_f zqi!|o5>&Sab!$-fQi52nRq!YUk#!m=y&~gL5+bjLNNIzFM+u0$PIYgf?se3aQ=Ngj za@4&UB$jXC{-y?zEdf&6V&Wcx$W}ioZ8dNYLgam_dmnZ0qi!43ZA0BQ)Fo5I@?#zM z07SMYNoj|QyB{Ju6QuN+f=4Ncd`@+{QMVg)`1p;wFHyG#bzf_wWXgDygvd7`Qrais zQ34|SgQRo-_x&0~4pQCss5^+d!&LVJ>JFpsNPt)#F>wz;B*s;j2p z5$evQy0cJsCh9Jxy85WQ7c)3KvqXa~oP~ByyYl6C_RCfjHnxd{* zkXT-cdovB9R|iPxY7_SmM9D9D;J*g$L5Q}Xx)!Kwfx1>y*9vv5P}e#|EN|3t4?y&$ zBq_C3arZ;CU4oR_D|nQG=q*&&0d*Zv*OBTvp{^t9ZqtZm7a5O|5WOQrN?j#9N&5Jd0ylhXYL?m>w5kw~epj7Ld` zK1fF3=tH>o!+QN`z5XU1VZDL0-arG7u-+pnVmVmHJpj?6Nm6=L#oZ6l;ne42G9D!% z`b3E6LJ}S&AUZ-NrI9-BSZ|b%l*R?|2z5_U-P0(4%7ExZo#-Z^ZlVcMmFgy=PDR~R zh3KaF@kod0bQ&Q?gJ_Nf(U}I(%?ja;|IhK0(p;=J$AIWOjg;mmaF-#fnWU79^>FNo z=A}q!fghszIz$Vo&qCA{qAunmx)|1r$q+4~K8pi*WI(ip`do;*g{af1&r+;cDnYc2 z`ds3N=wcnB&nAeMrAgcsh|(vOC_bq~SI7{3p88xFz#{{qtEkV_s9TM?1ogQ_gXkIw zqAvxAm$gAWG9mgh^@*cUbe#gx^;GvN>ei!f1J%8Ty4O&*k)FfG1Rlu{HG;&;rV#G< z|C>otdMkyy3emSEQhFQfy{$lWEA{zq5RXiVzDIq&kGl6!w@oIN+pyj?6{1P%^WzXi zKSt>%)aQ28ZAaZs>T@U7+o?cw7xnph5RXiV?oJUed;AdnLWd|>L&txy-d8F_P3m)R z2%>vY`VIBD4|V%ccYyjlki;VeqI8ssey>3kN2=%{>hlLbL=Wo_{V_y*9zop^338@T zFF&I$g}Ps;mtSQ(N<#FgNi2`y{u^5Vu8`7k6?eZ6H}Exp@MQ*F1-m#2^Lr%N_l_^z zePZ|sD8B>;v-$yITEz$9Cf0hV+pkXeldEEq=tTgT(a+xT+&iB_`RM^N>9T#!kBZK{`m3|6kAw0mNiuU|mOT}L&$Avo@0HV_ z+!rF#KW6!m$mf|)w(4>&Z2TL2KI&(d15AO>GcFzV@a?eiFZ4Ocv@Pe|9THep8@yxK z1F-QAKbg%kpCd$^rx#C|w+uEOOOPosvwTJu_^di(`Q3NI#-l+puV$9BHG$=6TPBsi z4I6((pS>hzS)d9mtGqJz%R6A>Pw4Y5hjXgvjNthiCkDdCA5!Eo!S*>f;uHAv`MS*N z0vit{$+L!SIcKbi7yib*26>bvGQcalc9O_8;bUeWJhEg>$^Yd|LS&(lY-9wetrFSg z3R$xxGFn%`|2KXRB#WVz3=Nx_bUNN#h47VrdE6D3q75#wUV-K6G=gP`pYZ-@qROsn z3GEmAa5a^b$%bL9Hz#mS)she#40Dyv!r)5{)1%5GD6E2F(;bF=Z+^kLwAjog4?|sE zV=$LU{?4d2jnU<45Ds88A-RJkG}L(hAdFVlH`@j!a~A)Q+jN zFca%G#ENhhggXU1!nj>pVLF@4ClAwAWiom;U6iyi!vgh+F-&y`chNnf`%-Im`=JyEWc4>vNhC||)hk3wYap>9fP}9N;J2`}M3*iU6+GcDj-K7=gX_w5p zJk=z#qhTJD)6V9=QROZSgCQPNJ-UF~r4?psg1O{pGc(9!G>nqoHe=r&9>y^E;ah*N zwsE_(!psRUmpn|^eKrG?w6ihRx4#L)oCo27UTx!cX@wyVT-L_JL^LL&XEQjxZI&jk znuB4^hwu=uwsE_(!o)+&B@eU6&tx>rFgfjPzIb5yQVeqegok;xjoYOarc`h?OOviJ zk0;W?+;wR3FBqmagdb0NbOEA8*j8!KttuSi>=`yQBzno+;8fJ8Q+Z4UIZ3~9E5W-`;+Q#kD3bQ`NT=KJd!;#T2 z<7GNeBNL+u_^xO8841FZe9fEGC1Yq^2#>GONcc6XQ3y&tuS@qmN+q%_p>)|uERfIc z(q(jg0zbh^lTFVL61$|vWRwdRB*@c11+E`ojNOaI^&mVMIjbjG75WoN7T2c%E<{$9 z`2O4_v$*!8RfZgki#!cm8|KUA+UL}zTsfwQ>$)-VP8jGS2+#1y7k(a|=G)?`AhWpK zd9}D)d9}F?IQ*1ro-ki?0}IKl>tYDc_sCZThEXcXmz%-jaxvKXa<#3^b;!@olXB$? z^Hrl)JH&_j5MJPsuL6F4r0-f>u6Q{Xm#Z(?T&_M~bNv`}am8g(J8s(1=SAegRfxFh z(ZBflaV|H5#pPnKxm^9w=1PTJT)HmeDxS1=HF7nCaH;IU#jhXEsqk6 zes$+-nNP&^e6OibB3B~_FVn?bqW)DuW^wWBjPP6i-gQnk*Rg;rU#o=qy5;1h4UkKM zFfQ;3$B7CIqf|7<&*+(N!jKu)33tBM3iFk!Qsos4)EL5RJ@Qq7!Q%QS^#9C-ZxgV( z^m^Q&h}v;L@4^?6>kS-*L1k~CFHsk!kZKiu6i2t!?_x`WENNBK)Rj9g$s!GhIMVOrcPbT^^PRsYTtYE z)yUNZ!tWSjE>ZugAhWpKd9}D)d9}H&boeRPhr)c7FS)N8a$N@DZ65imz%WWh^9pTi zak&_*>(Sk|Hdpfy%OU03Aa4IYMEsIXueES#5JnJ`IC_A z3JC92J-GPw!@1lH7MF{`=5k#NHrEaAe0?X2xW*h^x*oay2jTBbF_)-+RghU+{5m82 zR=;Qr~b zMHuKx2p{#xR|N)(>(=D|J6C5n*PnW&d})xnb?^H+H|j+sO^~Lpxu+96Oq?^Q6jLb>#jBn#Gap8qm%&{(s`?onriy>&}3$ z>uE5(aSEnCZ{oo!#XeXWvJYNhsu$V8df8UJCfNrY*@0o&lDBmG;B8jxUB#Aszz#l= zY{|!_eXv8f4?bfyyV=2)Ol303KFK!TZ`ub3*#Um2X`Rjy#Xk61vJZY`Hpke(AG)nN zq1XriNY+6P*fu#;*})mQZL`O)ZE8yPfuGr&&kpM7wyK_DAJmuZgNDqeF*|6Y+p4CD zeb7v@5AgE`dOA7Ru!HM#TXMZ(AGDV2gEq|OW_BR!w(3^JKIkmj2VIy=S9Z`{w^es3 z_CZg{KIp}4?q>&mbxTE_^R+vJr-9a80j&qV>z*?dN90GzL3O`zP&L$t2SX*xMjI9c?Q!3?@?8h$>T_A{?pQ>CpUq_k!>6i~UGH{d#>`Fv-K|x*O zqk_NU1j;JprC1Tz`77HM83I{IAd@P~;;KLvs4R<_0+}X|$tbIEZqZa_yQnU(3kqbu z%5@_Nfy`f7R%i%hA%RS)EGtL~WNKyEvm^$-vFx)q(l?$ZG4Q=*mrNqEA^5Mg5xXTM z2EN10HY!tz>@m|N3lLezNS7@}3w)y)|Ft$!mwcLu?=>4PnM`Ek^>kTTipVCYE*V-> zk_81atW?piR6$wV$Fqb*H;CP8B(gRlTclR5yC^{Fx)$uFFElI5o|7ueRwOISmdll8 z%TfZFE|3LLhOc$|?2RzvS`5leDP6WSL1g=wh>izK6(ZYjG9jtE)K6pwjda-xmB#8$SzO1WD1d8t)|QJsNJ_8r`TJ9*zUC5UX0Ny=oSGKI(< zb@`izCH4*wvzu!W*@zS=la17!8zQpNCKcGSIY}ZLkN;X5v74h389un%8G-d;5xdzMkP%7w&5`r%Wbxu4~l#GHKd-6qIXB%HetnCvx`O>|ng_0(5X4 zXk#_^ybC`_vbe~M$J#RCTCRI>1ti;@m9L4qh-+H6roW@2dx`m@T(gDwn)K(qw#aooXmh;sRctap z+2QK!_@i98K2bX^>b>M` zzX-W*04?hC;3_kjpX}r-ef-36qQnq!t?#(^Bjjog+Cs&Hi_9LaEjwHf>dYU_*AijA zHuQYt4CJ~Iv}e8YMOwt#vcokb$ox^R=Y;wC_LqN#BUc;Hp7+Yv^D6U`9WK5=M7h>T zqIQ%nx%@lix(T#3hPWLIS{hm9imcX|Kg#urD&nfv`}&`dt1W2jB@eE)GV_y_d_~r% z%pc`?!xV9y{=gA3-ro$`M%9C>BXg6TaRR^0#2iwt&BA>Be%@dix!QrY#VcQ3Rpuu< z`FaHdS{vnhPnfTIbHBI;x!QyFzE{3bZ*SS*+8{B1lrbTccT0C;; zjmXsjw6AmzuEzq*Pj~IZZ>7vg=xz&aFI{QtzCUV^lxo3Oji_gci!^PJVX})UtMD5ti zyz*P*x&v}+=^pLK=i}Mo;%l0e>q14u^~kXY$++4Ta_jm$xcGcLJ6umX*Ei*AV2HT- ze=b2?+f{dy)<9fN=`ebt>?6CJ$F5F^?=-K4RJe0-Z$C#@q8I_x@?Jo zE=21&X(J+LeX9E=S`a=j+FEM|V z3qL#)JU^cOdY=Z!^#J6~On7k33^G4i$yekD=FXb0&JT&W>TY~YL#{rM8}@r}g|nQm zBPIi*`6>|R>z&~P4~I~`nLo-^niRF;drSUIAXh)gEem`v$X%ZF;94DI zezKDWJ6j=Ff5?5=D_?J< zn4hfV3xB|f`J?%IO_;Cl1EXZ!WB}y8?v*b-K4*vPG}*4T`wNwOafMat(ysttk&KJ|E8xmnpgOwJjmydSl7QEs<*w~QU4Sk`^$Q(?Z=RLR|dT#rERr(XHu^YQF(?Kc@1ZO1Q!`I_FX_6p=047q!} z^2O)l+2J~9xVXOYi`sES-uO|-H3V|;chH2-kNBgs%ujZ>4x7v$&DX(@i0k9#6MG=n zP{{q>@4?0Ao;M(4w*&&AlER+ zJ?51!J|E8x*HP8Q^_MVT-FL0&grzvOM1757DM`-$!GiSKOsY}MZyvBYJLu%T@Pfk=H^M<>AI7pFEEYqam-QZ-X4CJ-( z8Xx#)m66y+-aAPeI<@ zUgHB_d&r!jt?FXvEgTcPP0gqbs#K^H?1= zPlLR$$M_KCbHdCS_9R^l1;X*+lPg~P0vV=5UV+E>fIrU7{AA9+e>8@+MUilP=zL%U zX^R}lEAkj0qI^!6Im4#`#!nea6;XdUx8E}nWS9YYWj>Goz~_XSGw>h!p$yAHB8E{u zldRFsguLZ`4+cIb%$(s}_jR#KI6lnXb>Wl9FbncldyNl#PMA5vmXND0UJ{NEMc=l% z2pMKW-deBmfzJsuXE5B?#jC>c;jGusB+wtG(PV<3}t;66S4q$#V zXK0|Yx|Cs;aD0gTAm4%v8svTMH9qh;Vdf0{M_?$!-h`+>%*h%3CNktg-Zw#yJn%VT z<_xuht~`7v9HZVn`uVNMkOz4O6%PhJC(NAToREv*h+mY4(emQ2ks%-QjwC!7_?$3v z2L2;Tv@MQGA_nEiZ9|b^0puMuJQ(<#Fmr~}1Fk&$8E_c>=IfIWZCFOuf(jt-&!h*# zT@v%-#ZV>_7v~%4cJ$pc`xm>3oa731}i7{nYu zD781j<+( z{&V^&{HixiUxg-`Dj`yZ=I~A*PZdw!Lo6%Uv+eYyebbi6X!`JvE-^#e`>xV5Oy9h| zhp$D}800staN}aVufng3|M&E@$K+TWIoAZ>ja zrtgpvA@8HbA-`3~qxW?-S&Z!TzV1r8zyF>-o+_Tcfd-4g(^qV!%dGV2Ok}06Ybe9? z9c}1)71LJ)`JGIU^!1WhjO?WEL5G?6`|s)Fsp9Dy?8M;dD>K=75Sf*}XALgHv9C|2 zW8cb!bsA#&iXs2rphxZrti^A z$G%=w`Yp!vl|cR=kFl@9u>PONz6!Sln!buM36Uzuyl)-HSO)0CWeO$)qL0Z;=%f$- zj#s*j_CEY;UR;Lhdn(hhult#c$d4l~g#1xnW1st7qyL<~0{1&Y|GoF|RPo+7&beZo z^rd|#g7-fDeS|8Qh5T8Wj(w+JzW+C@xCrv6dX0VVSC9UC`rNM!{rB|oRPppZ9pJr+ zOuGH4+o5thOkdQ@@YeD5BibrVpAPx?USps8O{D*xzIccslhgh0>Eo&5>6;|z zeV-{TF7JK2RW8HyEzfl9>$7e}A532<eT355c>4B9 z=`t&Q2bjp3_q~(p*mq}}_rAjPEr$F}9%Em&@4W7x@3JpmLuThed!&R&|N74RtE;Yc z=grZWKPP?o7cJ9e)}425S}(=kw^K0oeP-B82K1o9l0jW%CAoDhf&7oX#y-KFH|;0e z>FFX^#nbg%G7#N)3r+;tsb!u%o+{q^<|mjxp1xcyU1p_kfuGATeFyZ)w~kY$Z{*sG zy5PA#3;BEf9%G;2&Rf9$LO|x}6WnZ?rhTWthHW z!3@(^zh+#*^eu(_lOF zwRD-)`wR}g=`ySLz3NV1OMm6wcgpmwU3$k#Oy6^`0KZ`D`kap~ zmu5YEOGE55oZeUA_Z6q&iT?Ys?`MCyKWpOhT9V0l@7tJ2ms#oC{H$gPeF#2u;5OwvCsYMGt>O!G}>q^Z06}} zFS+U(#NQ1GmkcfbefoH+c>3N?GJm}HZA+!gtn_^x;xbI%0KwRI%6VV;!PVQ5brmdl z&|~Z?5G>Xgwsi0^PoH41zVO-vI}Pej$|QX}RXly$U8%C>eLEdye(U%=$l}tAccftK zJ7xNsFWurt*440JxX0L6AXuzV`-4oGr%$k0U*QkuWH$EkRPprf!IQE!-uu2vrOT|| zw>QLP*!w1{m2VxVOy7d7HP6BHy#Na;{zL$~brcKKde{ z^-j5DQYO8Rr;4Xv!I4 zPh5Dac=~?u^R%#u3x6Adr|*b6een?cW1$O*wO59elcmr#u%M{IxCZQxfAdoz*Z$0N zQmpz+zqDyw)iM;m2n!Yl+?i$7)1IqH^;gGAzSHm>hYM0L^SFWsSKz@h(|YS+QPH zj1Z0nA)K3n8EvWMSLo@DB+PiiI`LLI%ovee6aBkAgnvQ9!)Vx@tAfd+(ud0+ydPD^ z6ENdRm7XuDHQJ0Q)9!)rE)4cb0A}3HRXxoctL%Rp7L@oQe0>OJjMbc4<5Q((I1FL@ zDk9o2*KD<9l+ zI>c_)aYu}25{_z0@VmKV*Fj8{A=W+#Gy0_*RsZ1kyXv%r*sb`9eFqI@O!GOa9Hs5s zlgc30$;2JuALgn-N)tJ6D#Y-Qs>HgWYNp?*H9PdgC10$782(yMtg9bp4Cbn#p}PZt zIK;Zk5W6!8Gv-Q8t@*0iZO>~E3!=jyIvmDTj~UfR=6(yYo<4}(qrnU<;MB^~KL7J% z0mSY@RWDR6kR4T_`OxeUeIRzffqM{UL^VehPfa-(oe#0TD(-%mQLHW3dIaP;iwk-uV^@W6~qQ$to|5liQ%Z0Nlyo>+z&DQ%r7<&Rm+o(>iN)z>svH{ z*kA+qAk0|B&+7&C=6)}Cg4m-f?tYlvC&+5e?(2K*lcud9_LvL{7NubJLw-l~kn#Rg z-^C#IgbA_XNtivri8cFS5oe z@9bgn`vX7d2C;EIh>gNnj|Uyq6TVJ`&#!^lQ#!=PYA}1Wlit~*Q!AmLKeILthS?y@wk7q#qe}2NlEOqM*Hn-*J*RSq6 z3E~|Ta#GB4ZA##?>apO1A42R)L>@;BN%WcLr~=E=HZ>ceL)@p5^xBp)TF3&+D$3>a z_d&c~g0zusIkRd&UuPU!258?JaXg2I;}c1Fk@8rQ7pkL9LS z$1@a$w!&CvOhVBxIE0fQ3nJrmFlnFab;dva){v)091_oxJ>vc1;GR0(e#ef+!@-}$ z>uKM=W?W}Hv*5kAFy1Q=JG(+^o%7q}N*RtWPD_z~WTWx$w!z}vk1q$( zro7IWsBIxlyB=aSOpo*Hu2U!Y&#BMvu_Uvj@$iPj;yoxk@y3k0Jc^E9g;>pmN4$Gg z=I500@b<;*XuN(YCtm-c6R&p5wP#_x4G{Ai;&^zkV}4E@?^b4J9X^= zBK|OW=@bXo^E8imolNHF)bYAFcJ%!4_Q>K54LR}dYF2U_QnV(aiU;0!NFLRt-v3Mi+_4oalE6JkQMu_2$ zlDdW(c0J%doo%O#hjTS%N6+s`)rmKnUw_{&eXb1Sl|$?zkLwR73e3-`Bco{ox&mH4S>iv*tM@=BeZH>y*aBc|D64=ht7aM?O4=j&LS_ zh1d0G&A|Tec>Fr0@$g}R#aqO$zlMQfMHug0h&2m&oS!u}{J-Pz>y*aBClD5IvEOOG z$-lfq#+UaXc9qW~-Z&D9Zl})Y0A^<0|CSg|yk(LT@1xN6`WWwhh+VCD#Ixqp#M!Ci z@#~bHA3iIw^Lw6Oe}gtx{SX~}0I_Q%k9ZSh27c;z{5qxaR`Kia1%CbAf3yd=9&o}R zNO;7voAoo!E*`LrFiLV=%qBaRJoXET8 z3l0|__XvZ<#pfc7i^V7ZvwT&QS^46RFobKtAnUqM&)1A2zH_(HALafSVy%;6t_tmA zaow!5n2d`oz_9I)tVgO0^F?EeO3?IxZYo5YdgGfVLQZT;?t(8V*SQ2L)O_-|D5{Dqs7^Zzh&!Mmw4g1OJ?C?HqMlAU1Cm^gyZnE9F0p6bFNA` zKCTXJ+IkBv%>0nTU4rPux8WoivD9EUR9!NHgoRsGmJTR zX-lf#^9RJwz%PST(_q$W$%jX0rC{}3%x`DSF}%(HPT<}K5I+Z3OKK!4EYtipVEdoA zh!Ud9G;{9d?(fy|r#v(d;^zk;ex3<)?&qrewO=0X7ln8o1?J%bu6z0ER->#o#4kc# zTz;CP=nh7IWwO+0F2oxkWql-kLUL43=*ur3kq>bRV>L2i)>xCA%B3=_mSvbT&~yw3 zDfMR7`vl^bhj7QP;#!Q_ckGM1aFque3m2p2OiDSmo(Vm0vdXhsuX>R>t{8EUwz*sFXR-YiNh3jt@wq1Gx*I!h+{x)Y`h^gkx zOC9Rg=MjkCh_PDZH4-NSZoF*}415xuGlfG<4V^h^{(TT{Z{QxRu;lhazmJ~9Whm@L zqf&S&;ZRh|YZYwYs3n`MRj@;TVoKI>#H(P77moRzu7Y86GfVL*Sk>-@XVFzK%qFv3 zo1z1+d%djcr}Mj`R0B6t98}j+-6nDj4>9=Cf)*5FNI5 zoZN)2f?b<}=N*%BL?rbPsI&S|`^uvuv*lEaA7W7V5C^OPO3U%(As1u=MRZeolReeXo-q zXbHXclpfx(tpAB2#VJ{%G) z8J=Q2h2r4tbJnGrHLT;hRHx#%I-}Da5DVjJ&eVuG*#Jj=Yuyb8bSj}jd)>{>9FdcI z6r|3&fAxM;kq zP3Qco^YgoF;f3FzgPjn|Gd$w$OH__$<&DVs`B_&Vk&$?_mq{$%>=gm${2Hvi{(RJa z2C)S}k9a@Oc4EG*^ApA6Tr}Q_gcEO-;>3G>$tIlRz%Gd4kEsaT&+b$1cvjD6GOPV~ z-f6s5PCjR^NjmXXRyTgdc%MTof_D^Ae-XwLogdEwjrXE;31WYlz0RI?VE??Y@8mef z+YPa}SG;3Mavo&k{l&Uonan!BzfDpm8;!S4b@I7^x8GS+!cU{4FCbRp_c%Z9=alj6 zvCWCMk>~SG-amKU5n71x_CRb=LL3io|7>&O+1EOeJN*;y{>+Y^-v-`aHuC=R#6~@g zmA-^nSf_MQugu@dk9dFC&il)%*=t|JN_!!;O81D@fViOBspD}j8gG~EwBH_{&rJ<;reeHr zAhssp5l<4FpLKsC5d8cu4_Q?9`R(BSg}mcpud{F3RgIkAK8UUL7_V_^$o%m06UDP; zHpG^m-yYt6CU3vn-)q(foxKDiTbB~mnXjY`SHBdcqVVZZ+ZLm{GezER@x7- z*QE^NiO!GboyPl~x8DybC!ZbKj+~6~4nV9tA&!TWW^x{6-^dq)Cm8f@qP?B*Tc`ezm)Ho(*hlR53%>Wu0QVQ)bXtOG>J*$9pm}@ zgXi;P!>ylTyh9M%=5hTA`=_Y=cstX0f6C7J{muK!MXPr{it!FZ>|>AXPZ&>>Po8%Y z&%I7@qwoia?WoW#J=Q5UZqV5}MffZYAY5C*#E}PfT&IZs<+nO~`9p~@e_ly$ z06#+fHU-L?X?R=Es~^E14}iq z)G9?vHIuk2P;gU_l+MG_d01*k>(%yyet`}JxB7{$UJ&%UCKPlIkkZ8(?h+K-p^;J} zEH%Q?oe5HEoWxy$g1c$G%dm7AmhKG^-4#L5o0?E?f0C50!qSyk>YE~^<{Iu26!Z_0 z(sfw64oib|QfisRU4eq(GAZ5Y2feip1y3lXbW;%YHYOB|qNVl;(A&%S2i~aVEh*4% zQK8^zTIz(B9nta`lhnIi!(D;`ygOm3YZ7+_3T7yz)B{UBurymGrMvy0-=#yrd|Iy; zmhQz;o=kMTHQXgADAY-*FP8dZDQ1vTza;Jo6fBfTX#kc6V5yYW8{`LlpbiDknnX7= z2>K8c3Rd_?X_$t)1O=-UQhEYQPhcsblG2DI?g|vFrS(Q*317%5ST7UZxFG0bO(=MS zmL?=XpCChlAralA6z(b%Y*tBW3YMl|X{$m?)3G!iOCQLjG%Eo5OalsV`hcamSek>S z9aN`bDU79ED$(U@xJyv5M4gX@C~&rN`PJ@L%{)Rxe!YWvGlz{ zEK7r+>n0TZKKcme`|^A)@q=ym7uVyN_6Yca-9N&XPTt60ZSXORKp;p zH?Z^umi#&?ZSsR|=umipOiG)v^cI%tQr%W8y@RFtCeghg!rcdjl1fV3u(S-CmN z>7)eu-w7z}D?7tk?c{-ummh~x9}ceA?F;*d(6F?cA4*Txp>Uu^N;qVd;*eE1nChx0 zp|rXJg^vb_?i{qNftHU2Na@@ll-4w%FytqtT3D|Z)_aobElOf>ON73cm@G z(lZK_;#F3-KR`;8b=(6`c+gKuQ%&5l-eIcCQJ@sBxxyn1V1) ztw7J3RSrXGA*yzos7gAj^8AC=vuJ@7Bs}de1pmc*lO0Su?hoF>>x}_TxJW4^Nq3J~H;=AO~!5vV#DFj=tMUaa) zNH=rB!sK8m-HfW%h~G_hY6X+$&1|+2O5Z`1tU)9ga#Z*F-dXub1WMmaz?Lo{i1gGQ zRqxc*%O7|EN=_W)%Jk}_qZ`&0!p!6G5h5Zo0JG%XWN@QH(fgxYL38ni{RS<;8xS*q& zV2EWp=tt;r6zZ;J$@gQ{(!1d4I(O!HO*)k|GN}Qam3ra3{}&3teJ_u zR~6j^rN0DV%Um5IGkL7J`nEHF#f$GZtVQ~iMz7N2eklDN4f8c0_J==%Q2Ga+SYe2i zPH4DG5Qzmz>0}aj1tP@(ER}&D%6wRF5z&>Mrs0m3WmI>163R|T%V+&WcP3h%ftJfs zq*Of!WoMZXc`ivxHLzX{thb8l&PB_bXqlk8T4?D<%a;s^TTUZ=W?&=NnNiIh`aeYC8PmTv}$Wh1m~h?ZLdq|`VFWs(Vzt$tFv6zg4z z_1>qt%hB>OwA@B@IQJ`Sik8U~v22Ex&Cqgtl9aAW;;uksXM&Wj!FtWH-segtey6&w29$M0%Ri{DJL>O5%M(dr z8AQt-X!%cql_d~RbMoK*m+=CE3o$BtBp{y5v*n1|`-H(>{qvgd^*9R^8pk+g< z>*s^A2Q`Q`4iPVk3}p{ty(UyQ04)cgWmBpfg!+MK*(^vb2czX9XnA#jl!mIf`ym?e zlhQB)cdXZf>K>P&>@l=#MRg&x454M~6tNtMmLt*frX(qi#(k6q(RK+^8Y@HD7_4^- z)r~ixY&=?aq`C>He;O@s(}?9Hw48{RcZ5huRdM%2^v)nDO)+rCdN{aYX}Sz$)6nuB zs+*xg*$lMo6(G7<2JS&9n?rSTQ8EYn#XPE;kMemYL?1MXWiIv!4L{=VPj&gI%R}8j zKhYInodOA>kEBQ`lEhts=+Go7#j#!t>kXGk32%92MFy0WkTJe&VF-8pe-X9RQ&6U> z5FOUN>- zb6W2UthZZ-vOQGyCF;J!cpDPLr-?fJ{H$!RPDH`e=GfwF%TEG_n-?jIe0N+v`~RW#fsh<-zS zF0LJf#TS^cxDN5T_(IfOD8b@-0aCgMb@fn3$AZN;?k=vcz~Y8f*9dhDP5dQO>ZLL2 z8YAZ~5~+7-0(TjrN2$-tPWY=`n!6*4zqJ{!ma%X5z&y>>E`zv3ek3}#tBAh4|Y zq?<~xk{#g%<>_T&odjR z>du4mXVE7a2oMlo?-^hUIM3+TYXU}Jj6TT}fm+VHJ0!5IRwK}MAe5I%WH!ruju3I4 zzI}Mv_fWpjAX8#y`HU{`S@rv)ufG80#R{2MGt1eU!1A=|f3|!D%46u03^kNe%X9Rza8E^-b7x>6yf^9iBg06AJ(%t8M4Oag&9Ln)_htC?e z<(#o5Uijs+aN^lbBQn4%yLOVuh9ad;VX~$~SN?%Y78;3+i~zM&BHM zHcBCjp_U8{o0@bw-du(7mHzzq{yGzFjzIiDd@trUw6`|;M!=6Is_d#nj4rJ=?Qk{K zGP7idRbn@Vh9z>c0vx_dXJO_JNw(X%q$Ub~g1Cb3E~JO4V!r^1i?Eel@-WopH3oBu zmP+U zPDX|8P{E}Yre>14bj}9Xw3&>CxkXJon?FuI6~!>WL41tj5ytJ(3RBz9T=FpWf=ouk zbWEj%8QQMeH5ld?#K)^1VcagQFc)jgB@ffckz0c zm_Pbnb3TT_mlvl>9!Yb%w8AvkDu=nwkuanXDY< zMn99$Fujztv#I+-vJr;)3*xgBk1%eRR+yWD%q8yv?GsE!!`z?VHV0R>D#9@M+TmQ) zBg`!+R-L%C!gLaZxm{y+G|Yo?+S!!Po-hu>{0;H2?h(fA(h7s!$lmzb^l)S}jFR3q z*Dg7EFNQe@@qC|07`IC+%-#OVVR|_-8pdA4BDbry2`OjtBN*l%h!;v8VcagQFu1Z- z>1_HsG8$%ZdfR-u`-OS*t{RWY9%0-rtuXzPmBS2hWHijM^tNf(df)~O0}#jQig@UB zyR^a#@>dQsG{|H$%;Sl)F3`03_qSu1DiB|!dW3Piw89M2m`mOTo^WI|%t$3IOy{fa z4PltmAYNvAgmJsH!i-2(4l~-3(J)xFZ^+mMcHSXhg<+~fe5ubPjN7FZW?ZmxmJ*nluE{+RRMO+gdsDo7m}HxG&gR;#F&X80M-p+p-Lm%s$W;sC zzbIlZQU9tSv-0K6tHtHYtIf63&Gn%$Usn{@7=T>oLHu~)-*Z)HTZ_xZU|)}}wzawT zD6V|%5aw&udndm`uJa*&(rf(U=f~U870+%*S6{NZTz$ai`kG-`D>J)QQ9E{9w#q%6~oe_Sk-@DGq<~qQz ztaijjF2T4urQcN_BG-jbbfL%iCE~(&kC=19VCC!Iavd^RUD}REh4~7!)=9sw3q=jQ z#xFMm%@@A+#C&JY^^?x(Qm#MsO8L?t)ol1xt;}_%zN_zX!gUc8{V(+I``3TsI%c@I&JI-OI#=_5(0Mp=T?|Fns2Om% z$9AiKxtC0=eElIa2A;3KOeUlGI!~(1RY#saX2gEvst-lidyHSge*a&%PD(DWI|IJ1 zr@{2bDVYAei3h6``(S0rK6rttUStRBWn1-{WFO$CU{-a*v=83W?Sr>jt#=h$@&P;e zNU|j#oA$vD-9Gq?+3aQqUow@+B>N=Wc)w{M9ApQFbz6d;!dhTIOZLI9%;p$7_(Qi< zClveOAIUn%0ox|0Dmyqsw{7+qwoOgRKJYV}^VvZi-B#68?1TD}eSjadQm~xH?4XHm zOPVV7K{LrdxQf|a!w#;~ZPoRPeb8F6585!Bo7sV^+p1d?`=GOAA9P_hUD-i*-B#VD z*atl&`=A%Ixt|^M)h!kIYK(Sg@HEi6E1>njcinS_;)whxIjHWp4+iLvbC!-aJA%OXl;SwWz(Y=J3|3F0mg#LZ7tuA8r;%>H!DhZ`9x}Sr#(|GEE?pQC8vHqN&PuQC(mc6v%v) z>qZg+nZL5E&=AN%0-01aGrZoi1CNAhKr^mkdkfMQ@kPPh?ZgblD1($Z`~yEI?#4^>o>C zlgMV{zt%=rmTN>dPfC}S5*GZXkV{76x^u6Gh@CsnI(n)oTa>IUn_*Oz%_K1@#LW+) z%znd$@KizOeEgripTlHfjmQcEq)awqH&-IEm`gS*MP$~SMa*uNPGqFlSR1K3D@bHz zewPdjWUu1C)<*2KB$2&lx@0PmZB$&c0FiA%uhvHDhD{>d?3T$y_Kr(7KSgBL z`zWL~sXJdMvJVraOg1VD5?RtMLmhjQhS|+S3-%t4BU6a%^AstQjrg1AC$c>**<6Fj zzIMw(MD~qKHYZ7B``t2?$i5E{|70UE=3t4vImKk;3S#eFIWmpNesR^EEfd*qX)+&Z zA(=f0Xiw_S9O&0+XWWDV8$!{nK&1y1(&M1?xSzx#8(z0LZdlRxN#?>rV2RDLkGxK3!<<*J!v{wUWpS;RH5`V&_oS7RtD(mmSoq~j-( zcJ$5{f3<^h%@*dX(-qBjBG)BQRGJWT;g<#2`DKTTzY9XSaxuKMpsuC$ugA~JU5|=O zp=g=m!F5`e+p)2ef69dq00OS%%U4cCt|m~ls`7(5?O$c5JASg0uPcHq|CFo55OFmr zTlEZbT?R!jRd^1<1$B$-Oh5CJ9WMTQ3gucN%-7&6mZ7%F^v#gE2@a=t@%MVELj$Btk(N`Yh zmwuV!Cp%nq{VuMLWl=lkkGydUa$OBY-+GK+_@#a3Cp%mhY0MwZ*Jrwjt7pw>ry*B! zC_0q#=wJLTzwB_;ck)lUzQXX8?~nb)#7j_d4HW(C^WeJC$$NIV8ae(b*SC_0tKEBF zOhK*y6#ecsezi}qyl022agh0=T!&N<*I8Sq{)$}JLebw|;};*Fv%__%=Hg13BCcw^ z$9{oa*Fo`VUgKBQ6!Vi6uC(v|}z?KOV!`FM7?&hfjrstfbA zH`wY!JSf#Q~4;}@TgXNQZgFH^2&!hCJm3bm2zCMa&>HGXAzyx0GbUH$%A$!W*5 z^_;(}c5jPZZJ`){T0uCEF1y^hu6e#(Yp$nQ&*5L8A$6_w9RA`x&DRa8!U82h2}) zxO!{MALZ(AeLazU@SE1Z>YR9*tbg4C#SeLmUuD-iezL>WFX`eMEL_KYtmjqBkgEd} z4+?nnuNID<>~Ib8ySN??iu!%CX1OmR*R4=IO!nYv<@m`C*D%e+HAz^k6az0 zc!byZb(6~cWQS{nlYiR3o)+e-L7Og}k*gCFkM$bAZZ@*ZH7>~fQLf1eQ9HgdPQDDe zIz#b9kMRqC4vzWBO1{cunfaq!GyNj25$f@Okn1)mo@$8u7yc9-^OGH}4l46Ux#ovN zT$eB0K)AXWaCJ18Kgv}g%-6NU$@fpI+z!Q>$M}Um!N>e$hwC=x z4nJ?g=Z+#_zJ>*UXoXyNKyjhR_=P|J#~fvc>voy>qgY>I%ih9^)7O z^dR$-9j>kh^GCUs2Si+LMmFe=T-~6!Ea=g{_}9X+!-dbQ_C~o@Ya*^!yUbsMTz5k8 za>avdbe7vOD7&~`7UpZ+i%b4MuI^C0+H3rpkYIkYldro~=8xvFAD^?s)zffsZAyvSF+Q^OE65duV*EuM@%Y8(<5}TKdxwPPYim%%wKQ?YJIHkx z6yuwiVlF-(&kol_$(65d2@%(ze#t$^bvG2_`=DYjJ|E8x*E5QX>r-LAVo!b06S?kz z;t##XFFqg74i|r)hqmJv!hGGAvu+)7^@QT>UgH;^k7tLAzf(lHzVVCN@q#!$Zu_d- z3&o#%jbD5|o*k|ncRL;oiMWpK$+-x*dO`8mA&>sW=i}MonyI_`*O8=%>ztDfowYNy z&F_(~ERXm2L$v8!c~t_e9rI3?o%dj_EZh4eayeX@%Im&on4)O3am)JHBrhCWc@Gd&piXQ`Pp+^@PAYU(0}lRG|q7a96O zNj2Srfq!nAIYS@A#c)AN#Bg-;%QKMSK`5!=#ZcQdhsvxi`Y{ALAJ4lOLs{$E>1{Fc z%{nS7`a#Kgibo#m`kAB5^PtGAE*XpS8v8{IduyE25*Z$XlDd)y1OMzZbA|zii=n9` zV(8I&#v90>KuH7BgQ5O^Xp2D%!D@@Eh1cclU_ow1s) zQDn{#QW-yG=xT@{&M@AoOBn{rqCDLHO#^aWJPIZEDIN@b{UCFO2@KzAi${YZh9w<(lV{dp zQ1YNxf8c8cnKMk183fHkNEb02?jAb>8HPj2!(I%0T_AG?Rdq3p5snWv+x4r3439y{ z5YwYA_!>aw3{wmj!vsT=hZko4bO$m#4keH49t?a=cxr~#Ar_C=m11=A2Pv40w#AgB zh+$aAlW1J!2`Cw*crfreVdf000xpJ`rifu|HT4!`2tmnHUj2d32{UJiIk};E2n)xD zmwJ7qBf|(NQN0-WoG^2SLd}(j0$G%Y=IdK_K!%Y}GTroO3q@vrGH1wlGZYEOhi8oZ z1IX|sl+4jR82Fqpa|ZrnHnc5D6;U4E-P&<4GK_+fT*ZTd&j~YUnC0%1%R(ZCpN{Mw ziVUNnB;wT{_?$3vhUqERjx-Oe3=u)TbGaQsz4k^Ri7^?E~=8)Aj{zk=9P_ovmKkzwW<_sSPT?`)x z$A<+I?m3AJPeaKDF9tp*%$#9c$i?u9BFe+ks%2zOI{`|{O^@+`&j~YUc;C&iOE^Bf zSo2=`ZDEZ8bfzJsuXV~CoI4X%4cCGw? zysJ7HO7{GJynP9L6UF;}UJgM8jEW~7D;_8!Mma=4jp6|w7*SCXbp;gxfhd=vV&p2c z91%#Vm1804LEF>_Z52dW4lleSpdzBKc%dRjRJ>6C&&+0avh8la=0`vO{d^X7-uIn( zo_Xfj*~z9cT-rje3A5)Q|JVm_i$8r9hri|iWRI_J9RUuLXwgp1g~L?8(9?~>GDNVS z`pb;t>&f(A>}GbxVV);!amd&sRXaDu%fyW))1qCf3x}LgX4x?vh5gq((u}{g%{jF6 zdYYQ^KLDQxrSk>)I z=_%g2Hv9o~P(D7HS&d1)y0$55UE5?{U3=ciO5M08jk>l;K*X;sBs}SZHQ}TXZ1~+0 zVQU22FXNlGmV8V9w9D5aoTYrL^3Ul3`KHn0+MCvve65m# zO2f!^lvOoW-hs;}rIPZ^%aBFLw?8cEA?5qWsvGZpJv~{<_t~er_ zd*JeQv?w=>d{QbY-vXH)F?rZL~$#;9UbKi#-f6m^Tom z2QFWafS}wk@=2+re1#dZ2>A}NaAogn5f)td;2oCj+;?;SaJFdArNwjx}f ztvmFA-+50@3JIiqwm%}0?tP1cB2LPurKAmmcS5#vUl;FR3n5<~ExtA6ET3k7*XV%d z)2;{z$_>-|q*PMAs7)$!@SfonxKchjG4b9vBip&J)tGM-$TyP~57AuYyCx}M8NCCS z&;H8Lf!}$hR8qd8gy77iGUaO@&a|0xUk9shT)qM$%Uj0{XKL)uJBt>N(_Q4d)q-sp z`R=qRv+@pHJ}H%y53h};4=JDg#)RyB=UH{*@|9*g_ca+)G!F93ro~eY7y0ZjCLMV1 zv%gSu;POeSq^qtrK=eyE_w@?#R z;{#g3^JuL*wEHvfsg_hyzRIvDPY&LML+@Le5r;eP2M%-JhkAO;fM3+wG8lR5w*YGN z6fIsEa+c5O&Z|{fu)Mm#y47{vGH|-{YR_6#%UVAC?5B`Q%2(qRHYwi=flQm(`&L`H zy!U;r)g8R`%C~*-JF_9*Tw1(dbCJ*C&a0KB1eNUNbGY+rr3qVkO5Nsg?S1$y)Xco* zj>}5{VUzN$O=j9m`POH|q4(_zWGUaC%JF+3-#l9Up6()_!<|BM~Qi=V(_cA1fd`J1Rl<%C2xAlR15n7z`yU6Eo z=dJa#FO!3HdyD(r_e)4rjZ3d1ueJ~Wng_Qjb<1-fyizJD- zvCG%lTetVsE8pn#PYi*43usBJ(Elg-CM87Gq8iITUwB$t1Sw5%DdhJI|P~j2;>sHr&@HP+I^6G5xerMQhO5O6@ z2d|V$_P%c{4B7j>O$rPt-|m34LB1Qao%_@Y<<~*Jr)kMK9vAsqS+I;Af9lY_7O4C$ zbY?gAIc(NzU+AJh-W*Cc@=2+re0wa;Qof%uq!PD|pEKeh-yny%uikZE&FTm~fofDp zOL{6U@;PkQYoCW~)eY9Iu6ysZ4>tbLrhO)gGn*qT`J_}*J}ltUhm`O4aHh??b^PU( zHpuso!`xS|e8sz7@j&dg@YcYH=1X;&X#-<3%zG}SU zX^eLqTBm6G?v zg?dxrM2$9G1U~JUj)hYdDvTMFb2cQQ!bv!n>Xg%yM~+O<+CfN-GArIyqnrnmot6#9 zkK{fYqQZw&%IPazfu!2HZ9ghptWx1vKjn-L@%pk{V~sC%PkfaMpYc=S@G#}zwQlx% zsLXYfvH#e^&!)l%ke@OrXMEUlJ(9YmRpS$=a5k{=RLbcuUAOs8x^mNIiZb!0`zhy9 z&B`^=Gil1`zbX2dAMPaO3@|L$9sZ*>@BEjdk1KE|DCdcU<(d>Y`Rcc3Q*)y8{pBzS;>c180zOrg$vZH1(;Mf9*!mCv=n{@W0WPV!Uq$t2}W z_gcAfgX0F={x(IYpuj08aENpb4IVWA=^TpYXgGb8GgGm0%?=fhT<|MJb5S7vPDajf z=^CM*-D>+06rH6~bY_Zj!agh4+;HQ)d2J~ghHDO7^Zk}9-`Ic8HwH!LDHNTXpqzrR z7AY8cv zJ*_%?R7%lejh3J}bMNw6uDkT$J4?Q!=yE^YKFS?rVdW0i-!aZTlA;yBDos-EebO}~ zw4mP=Jt$hKQ?xumxx>O%fy4c|#-eX1`kV@PfO1C$EY~Q{r|ZuPP_)WJ(L{=J$NDYT z*i@Gt2fs(r8jYeW!<35;PSSlo_mR}0gDy-`bX5p$X!vOYzUUf-qAw=s>B%XU!mlVr zUxFRio#O`FoqaO0k{@Ull@{t!;8Dg8Y3fd*nf$!=KUn+e7)JW6-5Y$ zQuG3!3*Mt4Rt7uj$6KuOApFDeF!>9-o6`3$;JyCoT=rf-jG`CTlGduc@Lr5pf(3w<>{mcfi7X?xA-_0I!6i7bjfsCW>O}Z$I4lL?Fk* zO-|skpXo~Lsdu~bUN|r%`$H~xPw1kY`s+8zFXA{JZjSeO$&LRv-TjPmWWLhqa)%c$4J#J9F4g&4BkTMXw9GwBIx8f5VgGl;dIjDe$Jr@%P8TPddPnpy>5} z7d$x+*V}$r%?e%|4=Y!Jmn+9#hqqc|b<*fLirx@#!CR_`a_YyEM=WkS4GiV-1?`v&iUVXa-4EJtm_3{p&Wnj_04+#c-0gg;B%>8g~G7d zQGfm9IOTW?H4ATv9Dj?ioumV=hN5?PT=2}b;s3^yb2T$!1g<*0`GZ> z-W7JidroCo?5Mwfa-4F!m~P>fC>Guur=8ylcrQ?NkX!#W*VF$SPmWWLhi4^Gzj8VL z{39!e0B;pV?@74SuSR27?5MwfOBEKw4vvQhFoE~19DfH-yXZ&+tfuG?zYE@~5HAG( z)Q=~}DaU)x%kkKxMi2+% zuwQ{KV|~VXv9&TDwld?s53#&*>CSoKsf_86$?K_B;o%!&UBGJ%MMoIUyzuCjSvKdD zv4)boCiyet_!=G${+Tw;D}yWJ6@D>ThgZ&KU;B=?yboS4QFL^z_7Qqv=OD9elb2kJ z2wozF{V(*YZ8PK(PN=_Elq4PZM+l?7QWz(9DY&-Pi>-;AX7x zm_20e9f5Nw2KPYxWm~Tbobx2udoD*zu@rPq6c5)D>hhl9l*ZdaA z9}c=U4pWGp{wPd&m&jWBeN%Vrn?okh_RK78j*Hz}a!2eSC?*$a=1Od)ZQr?wei{Vw?>jr%G0>!!ltBXN1DisfSUg)RF znb>d{>lcB!V^aa&AKkE1f-Z=?n7kXj!j*SJ_^+N%{7SJ)!Z;PmyIHz!4!^ha?1w0J znTFFxdACW|ZDDWjXPqc^MS^B6_SM>cYP)~ao7lqu7Pg=ARL#P=TV46(`NJr7E%@S3 zpyZ8GEY~Ql|A5v_D0V%tuJ_T5@dm3(zc5w${gii)VFli+8g1_>qu9+l&OoirsCV}7 zz8kwdNxm7CH!)@9dLr2Kq%|o1_5@B8I9|0};cCH0n4`k_HqBIe`5b7$@ky#W(BPRXQf`~U+@jZ?g!TWewtCpCfwL?jdZV0d6Oim z$-&9trs&$EycEN(i+#)O;l*3lQS2dwZMm_rNS?#pcESGnZuBR77Yx0ag|fXI=UuQH zYm#sAT`=?n5$U`OwxsVpm-1aOs3{_ycfp?hXZ^K&7Yt<6kuJMn=e8L9CEo?Zh!tfz z?}GhOGj#~x1;c<4Wj68g>D9ikN8@*G{fO^^p}&bTPfa>RdcHg2%CGq@7}_iyIb)h4 zB4=EwiCx9U>$;zD9<9Y5Gv*@}iP?6>#DGI&qekETc{Q!gK|^;?MdT$Rhe+Dhq53ge zJ2k+DjEL-}J4AY3I)1|x%ts3Ak?BaxH(;^!TG-l#L~h=#*3LrL9Igr5cmr{3=lIyj z5jH+4tPLA%Vo2NMP9LU3(}pU}G6n9cQBF6-oYt{V)MMP(AiC5#ioTAyX;nQ@%Ts}H;xr-m)Ofy34|2i|&$zL9dq%P5E6 z2Xz$Yh-daPhRN~HF)X}8B;KQK-#-)q8z}l_$OZ3cpWrR=Ox>8B*_P^zgE{(`jp5~% zC;~5cxzDQK+)Wc&AYda!-}buToeaUvqkcTei{mX%Sa@;O!t1^3>nDNt3Ps=1T=2|3 z#SkT)+4F^s*Ds@;IbPhb@SaOrcvo-Rbph~RrD)QZ1)h_hQU{J#6SDADOFge%|L2Fm zdyS%aG1Ret;#O>`nOQ$`yxQuQo@Ix%Z63I^>RG? z+x3GY1Z<+{MTp#4jk`I*?#ZJ_B-rhWgPJEap&in3*KcK7t^Mv zd6!^z*?#67j@dZgyM|T2EwcU2E%>bj0q;=sOTP==wGREo2~YCkc-#CI-VUkf`+Ik< z1m3$8{n~KByIy0Q*&+Ljd4Cc%KEGf|$I|TJcw1$EVeh!4_t{@;fA}y2V2Sr_$OTW9 zQ$L=$va#@X$o4a2`weP)%mU!ygUsEk3!YQ|bkbAm&g*9wmY!eA_DeqW$(6vvXZt^T zvcPlFQ|iv~zV%ypyHl2)yO#~_3A`;7-Rm}A-=5%&f`6o*=GuhWnaym!K{`vbgX4WA z+i#a_zgzls$wk0civFs*)K8XEKc2acv+#a0tor>b_3X1|+1bE*pQ3*RT=4F9sGqr} zVr9$vjqd_d8^6&E~Nj;x;(-a`rp6L|Zio_|O^7d3kQ z3gCT6F;Bt;YpwV!NfUcW#6R{j2#{iRjkzg`C3Hj3e4$@zZkgy&R0sXN27?^6s3 zwVVPNtnHiC>Xt716fdvVJn4OkIR}S{<{ZV;V;@~(pQ7L|ui4>ov3bzP^HK74ijBiQ z#d}Ev9gb)f|1XdGNIxn`^OqScmGIK?XEmB%q_fltoX>@6evQIX>vWs}TE5YG?wfN| zXy02u{s@zYHgrHCYl1BBwIELH4y_Hd6xOuM-w09cNe;K&OPgmKG@mc!m+wH4I|39r z65Wi-+UPiuI@`xmc=#{F!++#lR%TgO180yT>`R7J)*Y$tNOeuI)I|!F^-NHtM}Va+ zMaqxV#XMgxmC7zlQKXlb`L5D%`Y3XxkEQw;ID-_qI?PhnA$1*6*CkjgpitTM35xXN z`EEk$Mx<^IGGBiUr;j4HC0S|!QrJ(A3{0`qKm%uxB6kN^N<~UVYKX>CgB2PZ%uUcmrpU zB9lEVH9?`WM-mjtQCVstQusNdNN$LwCWoo)i4;X<^L#l-u0`PFO|*ED3Y(S z)NG_?A@#J*QsDrV%`qslSYfI8NX`++hb);TH>NAa{Hl=WeD6*4BzU`y3w{(hp%_FhaFMAiMZ&en#If+xH$ZnqR{UDXS z@1e+#I`e&)!Wp8-UhdnDd>W4Z4Sr2ata1cUkZr*MWSUkS0)zexRy)M*~1%CQzHZ=_QG87#8Ash7%|Xq4Zc zMV2>5su@z}=qz|(U%N1sw^JzpW|jHcBi~ubcdMVJIs|cgD1V?|Y2%M8477cbQ7%mm+c;_g#+2%Mtl-ibYas+7Moz*3c7DvxWF|CNuW5&0BFz8Gb56%q$5Qz^gI+mUqXn(JBG-b$eZQ@r(~rtG!gaU~SJHAF z=}T6=-i69vgX=itIzqaRQ64CG=>{s_1lK7cT5z;(7xbR5|-;i zwava0uBCFrN9CXCw4kTV)zesaW`~ccd?(273{d%(K97gWzhYMgm4BUJsc!)GjY{R; z23hL6FiwTazfZB$4_+$Y4LwdWEVSO9wsYT`L**%j-Wcei1;kQYKRQz5s1} z4D_!JS-Aqq=f5tTLgjzJH7QIB0zu1lv*)AyXUnL3f0#B-H)z34n&rARb=C)E7+wFu zH8(&DZVg+mfyVex^G8udBe)9S8Yr>ULs%Q>Z3^eXh ztpe{)9XnAEQpKT3dS!Zo7Thnf9x#TtYTJ=2S|w>?8FD=!v4Y7B(|e_;;&8ZDAXiXg zjnTWeUw;=>w1#U_k`~~Oo_+~*!NZ9u{q8EKieunn9p~YI<$BDRSE%)-iZ))_h;Fdp zF^LsQKDzIw4ODRwTsx5~B(bLGZ!3#uP{k>5eTQ6AB-ZrA8U4DCql(ku+KXJ%CDu%B zZSzmNQ$;(t{y-~-lO7LMoQ3L~6`}?6!YtLnM-^x5v>>1Lj*5;DsH2A#JRM*uUjnC} z7A*9!)cMGFKJqQ$zAlLDg2-jucL5?VKxC1ZMP7)=3lUk8VyT`!s_3E9g0dt_U5tDe zBVU~R{D|};GQoYl5P2CQS0-5G6^Oh7ku_nKx+;OwPYYHBS*j26^+CQh+;=S^uSMiq z?(2)lzKC2OV37et1`zp*kEL$(QAIzU7QF6dshg4SX5@R5`))zxEr@)F`vxHLHbf>< zED|fd3N{$FBw6at1WrFK_#nYjD)Onw_YwCEM&w{b;)xr+dl7jrB0meW)DT1tLFCRL zOAYf;#Za9Vd=+4+2axXp7LQgNO_wa*vNijz;8YME>Musj&&1ep>Kz zilxRQ-+1Kvjr%4basnd%;J(KY`4}SiCt2h~L{3EHzX_Il(nl2`oeJ1@a;Rc5@=f+o zK~wIVipZ%UDrnAq(-E12$Tr-Ui^yC=p2U4K6I3zNPX(t0St+xTZ#MFs#(hsA@+m~N zZnD)4z(su1}Kk*^c?Ekxu(M0VxAC5T*%$ZjbX zxfGF05!oZjQqcrXKNVb@V5uVHD?+|YxvvzFrHH(o`^pemhRCbJEV2TT6^Oh#$WqVx zsG?G*g6je-^&Ij&hkTgakXnhzm598N`)UwbjmZ8!=6eB=FW~>xYz0z*HEP9bKUKVF zu+&R9*MzCy4xU=8Q^nc<72M79t%q+NeD`=+uM4BvYRDwx21TUDyqlA?mgHRk)k zz!{{15chqA$Zd$6tTNxnDphPpc$xd)+Xvt8e&+iAIe{zJsf>iMr+NdbOeE%Td-#S(Nt0NWn1aabjO0s_& zrEsGC;;hVgQ}~+V|7Hw5-VDpVW`2qv%*u=(0^cF{|4^Q<1@g5BQM?uR9R}ZFz+0VQ zk%z-~IDAKjSgN%TS31Ry;`xq-?`Yty=c(h6?>NM?;dofv#@qNQexjGWqAyJyfuh=j#ezSNOVd^b38s(kb4Z`+C6F1HOxR zKFsWK%a&QN6-55pCsu+vCP?I zMV_iTlzG%;UpC!9`h5w)(h^1TGTVk7B3nl;E}KC5Jpr~p6_KZe93qcge#DPYlYV!K zEpkPqVs5S3c^=VZ_qutctKj*vCL&K(9m+gB(R|dOq~E0xZtEiQq<}-D_X~aWT+;9G zv$cVUJkjqEdDzPDPW+zq0R~%Oh{zLs4w0?8q`LJa{nij$rHIHjibG_}$MfIFBmHKS z*~W@I-s=$AV%wBIW|Mv+$~-11$~?~F5P9fHeT#}nzd>P(u5{$=0;jqkQgHO;OG)pm zvz42Oyva$=gN@^FIhpipRkr*Sk#{+j*}U!c>Z3^SgEHAf0D>NxJ;-q2+3d%c6KhGo z3T3jJCXbxeFX#|?5MCNtMmm-`Sj~zuA9Ui`v}RJD(@DQfV@qNY`Gn?BW|L1&xGSG@ zzn`tEMPzQ+A+m9|mv=TN{UVJm&P8M-@gu7IdcIdz$T@=&wBa zVzvF_+|hov|7pg-*v{a~@s1&ybGEnb*16Xp_G608 zG}yi=i(&_V3E&3<7wN2~G5r!7Hc(lb9iTYv`w)v;!PD%YMo7--pb40n_a`qtQ+oh* zd{HZ`+F=@{-+9EotH>{llrX%=b9GT9nBV@v(G@5X@5ju;TM>@TO>tPUtjOK$f9%@U zg?S?-Y#auQt@Ib8!2IbyC!7Hod>t$wuXtp_SjIs$qk#FGVoNj^7<-Yt9k82S7v@sS#$hfEWz^<|(8E6hW+%m# z=`Jw#B2AcHswaI|ZG-J`VdF5Dr!rvX4r)3CFkeut2*PDHw`iNPUaH70MeAc^+Dy@| zvuqrux0(S{9`5}WVDQq^a*qp)y-2e*0i`a?O_q(rT$9Xz={s{emVAxAqF9CE0%I@I zgz2x~YO_+g3T^QA}ahQIYZ8NOqjTm6?0^SPE z1;$>a2{Tx!3o}F&HV)H2vu%P$ta$-2yC{Yy8s{!xFVch=s)-_HPa7#r=9G9_X4||o z`>h86^DV_*FkE1Qevx1Hw9#6o&FpF84PoQ8xx=5)1=h!Y8Vs24D7MDq0%I@Itjz>P z6e(*n(Xw$EHM4E*e8KZJV7{l=TGa){UZe>#Ib0Ve$FgyldotVRsdrY-0nBcStq-}t z*o!n_a=mq7W?ME6GbFQZj+t=w8-V$NVy|c}F!mx%m~fyj%zVqnVTNb6P3NjDZvtiy z#qd1q+|%qunlSm{x-f-FVdF3(6B%9Lj_p4`2ACfy_NL(iV=vN#S>zQ($}X_fvT>M) zGTSED?VA>WNm1-wzYC1LNE0R+s0&kK**MJD%(i*|q;;zR^Ap83t1dA1B2Ad($+|F= zK4If9kNEjIjoqXl^EakBPbf5JqUWwZhfD(AUW&aRvg6_F2V+nw`@Bw+!;~5mVzw%q z?I8rP&+ang9^`TC$=N)Rcj~+Vi+jnkabBU26R+2lLuZ25&lLMO?80lERgUEKiZ=sq zn#qgp2U;AanY=coGHhvHZ~KIe^O|Nj@k-oxR0VkbLb1;^XI}U`T$E$+s%0~I*>yE} z*>p|wO4@nNa@1>nw_A6D7hZ_}23<7s&Mw-q7KbsRx@~LnvT;c3Woz3sugytOPp;QI zN4*yA`-d%T_EBt)$C+1|te>Suiq*5r{cm(jvvX(&cWnmUuD&P|-=cGcTw9Rm*1TW!Kfz%cg6ZS93eBw;lC5e$Vy-@cNgEPIsBV zYH=77V*TFE!Q^G*kRFe=woUUoBw^EQtD|0D?n|}ucp7`C=xmqy3-6YQa%4N&@Y3yQ z>q}`~wmy*N)iNN;5+r!uvg<9LdYh!Q^G*kmh9@3u#_Qctv@f*EfDAUV(|t zegm(@RCH0mnU_=ls%7K6GR7I>Z}xjzozlEo2W-5sRpf9VdgP=p@%Y-f2^IBnnZIgr z7!yLj$GbZ{A^u<)3N_D8_0IThV*WWmd6ULC3lJgHZ^aE2|d zS9_nZab8C#b$K1_KXGCI@4)L|DjMW6e>wGg$NB!h^6C(@@w(3Exu!8qJtaj`%MDz_ z)$~P0Fn#f?aIFv*FZk207nStI%i=;e(v}Tc`r=iQ>kTz+c}rZptE4UO8R?6yTKeKc z5wl%fd?H+iuzaDUgTFG;7rVs8_gdPrM@?V+q@*u?7BTz8#UEPQwO>tN{HvH3(+yO!{=61V8^$gU@un{ZX*BI%4KddvSjA?=w7U?js;~@7 zP?-Jos_?yV4fWt+sA9&1hX*J;($jhU!sjti4xys^Yu!*s(bUBlet2137abb|bLwJ$ zT^rkPsvWmLt!s;5=+=&#Z#dW-aOXSV&P&zJJ5Pfx{ppwo2jjfRA#RaVT)-hOE2CC< z3lp%_(q*CQ5a+EM_l)jf3p&`8y0*fQgUwgh_O#((3p?2Su+^$tL8@+Cf#whwaIksm z=3S6*uzBm+@^uGW(7~qEwMCK+woqML5yQY6%bxVX`bH7Mz!{Ftc5**=&AhyVA(CElV+5AH`gHX->Q<}YFE;Ah%9Oe`wj8RRx71(PR>JCA3!_AH zu<`mX4|~!Fm31+MG+H5MbB?2}ZBG~KRnYQI2W~;X4UG8JH=L4B> zr3SODvgIvBioFJ&8Mib68@?Q5vw2yZU3)Fa;_UOTrqs19N!GRH=yh$=8AdJKc>&nc zZ`d$CjiA*${4d_m5wX6np# zxZM_Hw$?UV9#Z1%B~e~ph}qhBS(+UTBhSZd=9^Q(mTNHEDYm%WFteRzxA~c^U53p= z;hVe#H;V#Mdjetl8V;VeK0q9b%bi>(J;K^n;M+g6xog$dJXL`)BvwmRP?&Xr5$~V zhUL{u73FbWxsG~0d|BVq!Rs(8ddKU+>-_&y|8j4~K8B6gQy!;wylqcw_F(R%qOFPx zuPzPTjseBS3l9M44XJQOJI*`$xryL)I2CQL`(SSNuL~Nu9p&35yd4+mPP`sI=!<;t zI)aLfTF*iFK+xoMVFS10KzlpJ9Q9f?<|o#_j-(>ID_;A9N|RSlpU}Nw#^YdnJC-@> z^?Kjq`+`?%D#CZBoOxZ`!2L^Z#PD`}PH}3-X5Gtw1+Sy12wwnlh3}eyd+_ zUeAY|crB`EKLEUrrlQ|<7hacIx;IEWR`jy^1?TmW;l%5j%Z~tT<721@FNZtpb(Q8x z9}UCn3aejmUK<_tI%CiMpM%%2RNT~M{=%2n8+{5ABD+gE_saa4S$ z%luV#lOoD#7`^(~``3GZCtghpI`;&xf z-R7^6f>u`RRoC?dz6dA^6?ZXQ`j=dfHw-UX9_RJ9=EUo& z;K!rD>l7-!L~-FI*W(St>q157&v-r6#8I!eCwjgCueMZtMbL#;FIAM&FuZzL<#Aqz zIO_G*{K#A2bt)BK6LR4t*W(St>mp6mlk+;<GF6nvd7Y>`@%rb?SoiBb-fVRGvEbE?itq8b=rvdo^=lYjR~n)`&a1tnUcc_@+zPzTq~c*- z7hVlK-mbj$qH*=TPx7!wIE%J);IIl5|dKD}_DGpxeQSnl@`D>U@l+!T0q5)AJ=k=(g zUa8={oxtmSDlT!Gza9vRavFvg`$W(@IIkxYPVHDV;m~66>O{qHm-(w~ydlbI5MC7{ zQ=&Z13m=|2>;qibXdipt?o7oi1J3;me~M0&(=faq^ojB~uh~H-UK^)h&;h)a(j zbpaK>;xd2X&;N;X8iv>Slqiq$TAFlf#|?#_90p$9sQ68n`3rw~P?Xa!ye0%id7M|N z&xzNVinG54uM4Rd@0L057cTXRavFx$V+m0n=T#YY;`R9<%kiMpxH}bpm~!D&5)kDy z46lhPQ6A@2?Wk9$%IDd5>_Nq!y3JpeK2c7?@OsiJkMnxbQLn0lE@$hUo>cs$+x#Wx z=Z4`mIVkGMd96!1wc{IsmT!aCMO6Hq+x#Wh;|;-B&Wukv9J4h64^sW=sM z>0fd^-Y~q%lQv%OB%F9{+P}XLye^^QeIXZKay{NKyehpmUhg~VrS2X440!pec)#2H zCD-E(!z&T6@%q?NuQt7J7z|#QQVIK82(`ZW7YnlIJ-Hrl7+x#FHeNfuPVM;mJMXRs zugj>Ux!e3D*W(SttJ>aD?9R@vL}S4X|N?eB9bcwIpyZQSNBxgKvAUN0tX{p&ABy`DQM!gyUt zC8xN}UkyCpXMEX#&G&N~`9wR;ZR)q)gIWK;7<_@d@l{mPuGah|erh`7^Hru-Oh;k0 z_HOtdiPO6{6;o50+RVkPPwBOMCWnUt7aRu;y{Y6Jzr8P69OP%I*>jlgvvFvpIdRYy z-#8E)`cO%yTI0;(AU`+Fo-FGpHI-cG#zB5Ynmvb^2^)tt9w!cm zOrHJ%^{PynI}= zQ=B*~{b$2x;BXz4T9PVKIJA29Qsko5WfotxkpiN zTR3uHZwW3TYr%I5!rKCYHy2vj`PE~^S83SvYV)6v>OMx z_mDk@Xu_t$t&a1<>hVE#y8!_8f}r{ozi>`C;go$JyR*e=3<6a^Wz+ z(ldJwrB+_vAMWux^@oLreEbSH+(IQ&{4N|Gv-HfKLz$JAa~KwI;!xGQXBjx$N+r2& z{b6ECv}yJnDy+PmL(p-4I9HiJ8XRt;lCT>Gxi64Chi83)Kj(nwCWrf`_xB5zgTnwS ziRdnEA@=~X=kQ$6#^Eu?`QglEXN>@d+o|N4kPC;YmY(%;a9U5|2PteECMBJ8XgO)q zQg9eZC0ea#Uu!Kl-O@9A4xc7$9Htvi9DcaA-$rn_gG!3SE;{4}MLF4X*pw1^d4HJW zI6qvlF#aky+({)BZX9M>b;+K?>s}j&h~xb5`|r)!TzwantO&U1Fx#q2_8eZZb9lya zewZ;m6$S^DN?!1~aCj;x>XJQ&bqSG|x5ZM`sXr_&=+Xil?xvELk}e$NnlO6~tL+?0 zf=(Q+@b!EL90pOz2DknYNr}2-&*6DXL#{(ycj8by`$e|@Gnh)=aN|(m`@eIjvU6DJ zI6oZjxtra)@1c@+11@b*XqA(_4hbtS*I||6q{Ggt31h+GUMhLt>%u{<3G3zHw3fpU z)CdhZhqWmu4xff5z6=icQ3-zi!L}D?&69FXm_3K1!!{0>iX84){kzX)??()w62q-O z$Tea192zBU9Nu!AA6~qF>h0igKb6#e$KTRHt_ic|fS)n4aoDUn>Cmp{TX%!QP%7E& z)+gnfFnbRB?Hsl_&JSywTyKEGFe=&W)+gnfFnbPv*!#oh2`3$Xedn!d;4qv@esk-S za!r^$hrMm_YVCxTiyiPite09H*z+nWHHg@A6 z*M!+~*lp+Vi{iu~Y#iGQ97a;57g^JCA_X`W2~b#9iQ&6D#yVT(h?9%=Kxp&q~=_SIC#~jZ#MM zfaR<8SG~D>wVG(Mf~wj7>cBKt`7)%E@~zdSEJD7sQkgbWz77!9Jh*%v!dc39@O^z= zfPAB=^uk&L)RONaML;x+e7)4n@(x@+DV3COy?|g}mQMG+jzM8$Hd8(y`k;Am`S4Cs zc7ykp{=1Kdd}FAzx6h^b+23zJ@ZJ|t1Z7s;1D8)qCFR@b7Z_5$^BsC$mkdcU|6UW! zQofBHx_k)v#!~4m0T=oDYl2F{^uB>cW_brLpOi|<_i9LBNck?v=xL(&U6>&$Ls%GcAEX)_1!#rEDeEZe#7 zb?prHq3(Dp9h-EPuhz7Fz=OBeErH8d+ooi3>%cD_30b6kn+#!-^1Y2x&4bxY`QFu} z4ZUwdwsYT-^*??B`5vayDJf_9GT!}fnBHf9N9e$NpOi|vtzIg7-<=5=2l)z& zEN>l`tl9M-A!mC#90|eWVBsDc`+`Oq(g+kd(AR zJ}iN=Tlc*=^XjJ|-(yr-`|rG1^4Z^0I`H0Sf4}I!<&#oL`94;qEMo2(=F7C1@;wlg zHpur{wsT*_z=0zn-{Vx8{Qq?4wg369^x%EN>IF=K$x1eN-YWt^0x91oeqocn@3T;* z&6IDaU)mraI&z)f_o1HNGT;}rwhRXCIH(fxO{CJ#vbgh>eeD&nyt-(^+Rv!2TLxtg zciytkZ4zW9Uxk!P%J-!%_(}P`5hng1XUexbA&iYsg?V3VS;{wV+wf;0-xE~&V-|Pb zvK*)gEjX#+R*0JM z&n8UyYT1-5=Dv6@O9Cn1;WnwbeE7*}0c_2E@uM^1(EEC2JNNYo9nW5)m`cm9^E=Du zv{_#+e|vxrHdNrhFI>7Bq8dD}&hj2-RgK$}y5+gvI`F&PndMCiA#eORFftE0cr!o3 zPv1K5Yuqvp^4*y2+&8%Jh_;Y#8ZE~kICsADI&9XLw+;x{?B(mF+Vbj5sw2EMo05%u zQYyy9lut>B@}zvHW=JLEJ3S)~@(psB`|4db`};P&3-aaA^5L~!u(K8}eGEZ`(c=$o z<%cCRZCTwq$^wclug;`u8L-(9QM)(0_dY3=lB9P`O4e-Yhqy zU>MoSC#90|bxjEjIe0I$aAoi7kr4;^o^qJ`>b>)}88nN%ag|HUpH`fEU#*440q?lf zD(}D-E>bEfU*=~RV#h_kjUeUo+vO_^ir*xizcBpF{;z+8GYXlL&zFm?4|f3jdIR{mEu~8HeCch?G%=ZCvf^H2Y*oj zDg3@m{MiuY^yHB%e54=jqnuG@#k-=22b0$yw7Lt$s{#~XX;4mI=?Wx^3vO6U@#o>H zfopV#*O%oQYlJ4L*HV17m*T6C?k8P088dhH{E*^nk~me$86UQCJ(4>0p2PQ2d~Fz~ zLOK1V>o#8?w7G!d>w&e-pqxiFE7wHN?PnA=qWCMw^$KzgFf7*{{@t;c*HQd+;h^DbWwtm$4WS8njRHF@~)^ykoV-a~;yq-$t!Q0EzMQmj&?*gFd4 z%v7vgvqM|E70spCV&vKwqMYHyIviBJ;gTZ6kDoM z&V0Y+$~VS*YFtCH*EEVf1FV9uS*|6X6Wjjiq1bAJV$TCh zOIWU`_sBIPq7;7@t}0-~bjwwutScD#1;vv(&H&|DTT&mkBV<{NKql9aPHNR)$Dc08VDPZVC=oGJ(SSW!r`hn1X) zAb%gr9(m9|U9ag%mE+Kbw`n3$Gv8pdM>f4?bDLYKa-Nq}N<>zr9Lj9cz3W|Js_Y1| z9~kM#=`BMJk&UPS`B#!EZvf8^SRm)w$?p)^=$$cPjVgzs^6x9@$mvad4v|#WYX5Om zITQ6`JoSJlq^jtn{>LsKf8(_UfMDhtvKUkyq3Lmp!(l@6^{cy0<&;*PnjF=b6 zoMdx4Ccpo*cmO8Z*%ZGi#3ou6#SZd_w_Y*VnkHsUfAcq8oEb>d_*-q5cQfPoUv0ze zD{O4W&+(}i^!d7e)4$&XdJe_=8+K^yS;vBi&&ciuZNiu}W>6dkQ#gCcn9b9HWV)*7 z>%Vsx$M$Q(6u%V`XI9n1s|pCZ_2WHn#c@1L{sQl&^!+R6eEpTG_dfw1hS`8x(pq?{ zz5fkwO;W^hJlr+}-feg}ko`Or@aFiBx(0Z2DLxP#!?AvA!=jw}>$l!sKiqHx-W`4m zFXz?k?g8FBir=ZY;Jxx6@m{y%;Z`N^?haUZXXOt}0dGFVRdi^_`fWmhdDLIOw-X|c z>xrA3z+*qtmDY23-{t24FGBG_=!#BwxJ!zoUOe0~#li7#dlYy>gBD)#??a~oFQ4Lr zlP-AAg+w{^<5j96j^hniEW8oAh4;(-d*1}!0*c?Ox!|$ImU+~VS7M~Y%<+fSm8jo? za{Nu%(Qygzu*Mk@biv!Ci*oA4!&*(m@%mw1Ch*3}@z-x)%Wc4Wn&LxU#vc|6qMZ8i zf^uR$#Kf@uoe_}6FnB*;)l0B4!mb5KEh@E zVM+7f@Z>n@?7rhW~JuR;W9v%tO+Vv6HC4$gXR(-;;z>aU+1ryLItU;^)1IsV>X|JqT&E1~#w-39NX5C{98 zcygR_yyv_ek1flpSo_taXwKuxN0ZJx8F-}>&kNe|@Z&Z=7^o9A8Zz;AGhA#VWZL#C z%qG`oT!$dDZC5knz7H{*T)J~!cq(H$Wb%5dRe0;}#y^4Aa*EGUU3h)$&n(;ICD%}l z1Lu{o&arsm!9O#v$xCu&yuvRA>+s6i?CZT}^u6F!M)7&I#Hedu^{k)|9 zjF)}it$*+H+k;L8#TV8ZHtB6U0m1%f*;kEGJx$OJupFw%}tbskM;z2I&oZy1q z!|tTY&MH-QN~IrdD=!G}oxi-cx)pe;zv~NIdQ)Y09cS%bieBCyI#cCENxn-_d8s0D z&2N#c@lWkTm43Vp(85c3U1fn6_zRAm*_bM?3gLvSyL9ykU3=$)g;aTUm}Vaj0WOhM z@%yUUo^lOU_Qi%mU!~Tb&DfcLAA#KijqlmyT^SZM@~-mEPh1DtZUWX#UYb#x$|(xp zWXqeFvT{8U{HpZwWmK61tZBfS6|`KlQdd^pj((F1tQi{3C=9Zy%<_=#)hTb1EMs!; z(yEW|rOI#+CwjeY%WZkbn1*er5ZiLYP{b|laJOBsSMNOQCcX=XuF68$UXJrF*tquL z&-gAFdV+{_-Ua)0#oB}UE*OLskA8Ig@fluj~8KRe9EG%J%uUJ`PMq|1Z< zoJsmwJ~m`TWH;R*(o@>IJ@)l3Qdy5oM`FG~+2s?0Y{n6}dAHKfLnoQVOdNZ>f&cYR zUN&-sjZX@CXPr$9X`9^X!<1;+K>RqB)4}vP!w(EQ?H%!1n{1v_!pQZ z9P!TMoJH9&9fdjKNnQ*uw?q;3%U$lX@HP$V_!#hj^_AZRud~Xq*un3+I>R${6E?oD zh~97EvEI7I4s)=A-YzwSU*`#{dneR7kIhL69O+cu3GiGCAow> zcdVfJF4YCk>{F~9iD&kFVKeI|b?17^Xcj#s4r|@YJNKW~QFzT|#JVw%-s<#BsbgWq)~B_Lr&`RvW;3k>Y;`UGQW%vi+R! z%sVQ>}UU()->cw%>uzi5jn=N)+Zi{zf>|Z*)r3g>f+JXRb6Xyls9<&mFS; zzWhB=47``9vWZ)NnIMYJ=$}q_k{7Sv4ymUh^}ObvVOIg~WvXnhy4269e>&+Y+nM7T zvcG&O`%9P8jvfTOwN!a%DhoWP`bix)-dD2ycFFcDSbyggz{B$3u#gMh<6a@C>@Vip zgxO{Lnd>TM<9Of7_S>DZ`b)`asrkUe3jRp13tkQ@f*@OD|d;1r_+d!4ayNy3tj;x;(p1Gc8 zn7n@bWc&Rg+poB${c_-Kq{@@r#-CIFbZS4TJIDJ|w%^~f{hDn%Ee5<-sPYuI@#lo+ zR6nUZ!?W*G3@luQ?%ViPsywY$w{+R3*wD<+-;HaXqRM;?-Hlx&@T$O^qZBB}HU_X^ z@xlp7vnS%>rAc2d2E=PrS)hOqs_TNn!g5Jg;su};q=jb_5ls8{7#{j-zKPJT!5wi z^wXA-1kLBm_?7!n%Ki{Vj`YG;UyNE zN2+UzrTTfP3flyc9s!o>kJQabUCi^{8lb9M42tyfGT*>3PK6>@`dI4DBuVBkd4l>{HFiwRcw6jGy*8kl0K2a`BeirgJw zsj*0nMQVt~QV)BnYP?2~2mCDcSb(Y?H7GJlWvPi_oC-z8@YJLfRZR*}WIT_Y>Z7VD zIz=Aksp*KEj>snrmTzVfr%I8@9+sNprK;H)MRHV@nupX}q;f+n6$wz)e1jshdA_HS zDnM$kpZT6i;#4V;ud&n;q?RD{w9Zn?yi|o(h$4#>mMTW72&tt!Uul4UPtOJKTEw8#Oa|3`>>6w-bLzNq_%S3 z7NoWywJpSaA0%hA9I4Nd`c`F; zUxsli6xq%5q4!sPtyAPjo%zuFtG@M9WH0x9k9=6OM}7@4-yTH%fXLrfmP!S2dMNT2 zkNnw7ReLpx{G&79uVI`DV!l5S`G-dN%?+0N2dTf2YM~=lOAQk z@|}u&7aGiW1|m;KWKW%?&J0j>JA?B5JhFX?s@sPszn8*%=LB(jDE~_CJ2yeq=lUtX zx50epA@V##Udtmd(5bq!LiyM8$nNl87^eJw+}ATi)jhqGf3wQ+U7}F+#R@v)`d!o3&Z6pG8f|z8Ay*|WS8x63aqs^IlS&)L>r{P>bX^-d*Z*cm znBaQcPu16lty}?rc-x{AU{YwqWE6N~z;fN>IkV%~_o%v`K^vxrsQMPK<+??`ZvB{Z zsk*;L8)hTd0EuL~faMzE85;a_4OQQ3(1sNnRS)x8u3`G06H2C2^-zsAtnyGbR+#A>>FSYs_r*(n zFac|=Le-OGu1Wf4-(?R|HKxlAulT8Ys?0Sl^vc$bZ^8uEo4}e8whGMk|Fw5=f0z{7 z@SaZ9vjUcDw&%$EZ=XQbGY#6X4OmY}tht`czC7zQst#+k;ZtBmq${GI7kub+s-6$m zmnu~kB&`CU4*l9D@-@q!Bu2TK8-EID+>Jp7MHV#pBdD1GdBJ@hb`9zf3(T5222WV zJXfLWR|A&oHP89eYDQ4?D+X=s5~Au&66;ORm;qylQ}r9b>Y-8fJJR)zZd_Z04)8Y2 znAofFVzVH>IrL5V{Q)qkaQi6#?jReZ?<-V|&q?y{3A5CP@O_Y?{2|=;kw(=YA#zxN z`F1E&{V^g(_*m*wm8w5MWYEh}hK3W7qq%RVLDf5hls}I9zEY_AOXPbv#Uj5!BxZTG zdPC}41830o+0J<5{?_|8Q%xIKK=4^>nX^wXBhl2kJ~ zXt~CEdhMN`pqeor+R`UPHRC1LBc3kCSAW6;tN^ecm9EG1QKy}JF-&mXqEOAmlvQ9T zG~oQ1M^eobA=+{WuqGue*A)LdBmeG7HIx0cWk`x@rUfn6bWd!rXCKw%cxcN=jcRfw z)=baJ*m2jv1gxWfHI=3Cp#> zKlJK$=TJ>Pazwze&}+F0^_w={{sq-M4GK^DsAf^vaxD(MHn6l1CWUGiCa7j!?OEa0aO+mb6?&p&bLC_y#7GHpc^0QIu0V4c7HC@#&ufJdiht|zG@JmXd7T`jHtEz zo=t)KAEAv|9@@RjMH{j7C;DNoW2o)@8)##WgLdzSuROO}BwP9?l}A(NTWI&U7TUN; z^HpG(W4i(lH^J8r5^da~6>XK9xhhV82u1jPwvF2(s=*zeIZcneMH`DewELWsHhv+g zMY|lsNB#98ZT!+fyD!1lS8lavkEPu5oZD&RZVTmZuQoQ^+KPl73lTJ#R>t)yZX&Y@kB~i);{Hj0eqK#)Fl(Nvt z%6{?TZKsrv?Cj__D{VaIrj#YT>>>dE4x69wvOhw!@edcJd}?Kym!bKWk5X1d*wGbe z{teAlAsl5{ym;FvWi2bqDigvR^(0O!*)G`CsVQGGAoHcHvS%Nn2_ zg3%OAEhuXY%|_4+Mc7eOXf}oBo)9~-LDL4!{SrHBX{D?dK1w;r%dSVgR;YKFm$iXr z8)$y#Wt#1vc>^?$y4g_&Xtsyuk4|>f(Tlf@Qcm(RJL=g{?=&y#49!l^{MpVlZ-wTq z&^%{lM_r-W6`H?B*ikntW!>(hl#9HqJL=tmdVlb;p3v+G&C4OCc^5Pt(ELYYM|VTB zSC|%*@v@^nUc7Czpd2sji+X)sw4fp{>krL)q1lL+4S?nVXg1|#4?yz)Xf}5b-z^y?I$8 zG!voO*UL0tfhLCY1^wOZ=v8RCp?SZP9lh?w+eQnVyzC9sdjs_z;bmi>IU1S+?M!nl zG{@Q~YaB}$vc^GkoQtx?^RjoLIUbrr!mR8)l)VQlLwVUGlubn0Fe@v=UGuCdHd-(| z!j6)lnFP%jLhNXUm9nP$Xh9_WG(EiRLuh^o&515n_AxX+hUR29J6ht!+eTTbHg=R6 z!rMhzOYQ7vnG>JFv|y%}9j&lZ)^Z@&rr59Oj)ZWcC;GxR=a4yd~P!hWouEE z9%f~d7jGM7WpbPAP?iasnB7pe0rfVxC@agwj{H`9@==yDG6YaBV50?}at}e2<)REX za-f-yvV0q5$q{z631y%AXu(=;vjAlUDBEIVWm`gcyC`d$ogHm=;!~Kiig>-9sJFvM zSzowW*_WvICH!H2!qNB83`6rM_xA(Jey~y2F<$RD>ir0Rn?g+UWC(8;Wu4;Za2jQ& ze3W&@&C1TA-dWfzlGxF&4$8tvoOOZM`^`gH7>Tnka-5e?b}>W?cJs17Wy<=~Nm-Yj ztlr;vUxuYC+`~T}%KFDj3l2q4<}ZUcdC6av)$=EK@V1h_97FA|fOmN>EjY@{Dxs_r z%BomdSrr*?C;6)}@BZozdW9f+ z-%SfH@Olko@;7kOf{VOfBa}6ATks-FUrH-dR&*PMD9siY+Yg$xY&!ZuD%=xc!4gx& z>7;GPKjbWW&8FKr)pJncSD2pIrJ-nUjTmS)88CSISt{Hmv9L{OZV4M`Hhy-_+IOh% z3oncPgl1vLK(kTfdTEWRaEF@(kV3OSHqdOi&YRYi3b$KX6e=_~O9q+^*7V511I>E3@6M`8g|e4L z=0X$GZgJ-8em(sCW>lDGXW_lj%ySuN)|phNdp9b~wXz&RXa=1Inzgq*96CgW*%6j# z2+drFfo837FTOjH3bR5iTM?Q$b_30t$9K>CiV8PKEKCxb0h@uQby=%Q=cy1w5n?T& znQb-DtWnOE_&612*jd0PH2oF>&FZ#J4~?h7bSsPcgeIck;(S)S*n46j6|RY}&{1e^ z2pectz4B-6!Bn^^#Ntn(xjtl|S>@)VnaNbR(#?Wcp}9^r(5(FVoFg5maJiF3!a_4s zGSI9vdHk3GRJhE}!s)2y%DcS=niU(*>vEC`Ke4iyJgWKW$5sQ)3iHPde4YxIL|9-S z)m$;xWuRI9?4_5(RQR!%Wd~8swZ9pid$|)+UaL-pAG%qJ5!GCJ+{k9as)p$Ysc@l_ z zv@5E)_Hx8P)6zLD`%NnJhFIukE<*E+hF#Nac3^p>2o+$h6zeuZ^R(6)nr74f!zv|V z(I>(de}v{KSv^Zlvq|o_Di^VG1n-+{Lh~odK(q0Q^>_V=%ajsZt`s)IHUrJt7dE}sgEpT7&W~(D^E<17X00vdZ<#`y zPutnTsn9%PG0?2}MdQ$4Sak)?c|M_eIAWk_eQDOR%~-kxPOqx@P1r!Q#-URie#QE) zm#qT}n}O=x1o7UQ(mKdXIyYW_d889^deq=n|!l7VK`gU{U4 z5zE=Y`KqdUz-ORYWl_I}`(RBRIA2yZ_j?UAD?fee!bL2syV(M}@V?Jupjj!q#fc=^ zybd^@3k%J?ZUfDVT|3OFh9&+8Tk02@dt3&Z6&m!s0qwp}V)qM#=5D8fX8E<@SI5%k zd3JWwL1=#EFwiX5f8MXJ;Esix-MJ8&A-jQQ!uZN}q9-Q-=fh#4xyxptSvGM^?^?Kb z0-F!ogeKDd;;mWc^~1Lp;RcMvZo~*pNixu+x>dhRq|IaO>~4;#={3-_97+D=58MiZ z_q%;jO=Z!waKDo+yhdfpUGTyKVRk2+$q?l#_s|Q!#=Y<#?NL4DetZE^c-)g$WEPs; zCd`+CI(le!d+U5x@@1tPnT#*)e-z+L&_M z!(@B7TP7=m!`U5t!cFps&{Wss_rc9}O8d>LcT*<%Ko0f-u&V5(nbh2Hlb!7`CR=>% z+6oI5=Gd8^`oPVXlwQGU;zn;$ar0D2nAF@n zqsq9Oey$idS8ls>-Mpa6xEpZI){ois&|RuEVa;`L6QcBL zUK2NZlZu;{yv5zTqRP0N2V>jjmE}X~!Od5cZjG3@(VJAxIHcOJu zX2Q*GO0Q!zaice>xEW(D?q-}*$hez>N^fU3aice>xLN5e?q-cw$he!4QcM?U`tw_d;pPyf-{>@Pqc^FzNec;+ zS{KMvW!%kcv2FAIQ(s+zn{O!HE}6K|n^fFvuoicN)rRPcyLrpO!wWX1jdPTx+3(tD z_IS%^$K7wj-(gC>HLj8HnCB<}WqYH99d-(%JWRGlCwmPFY@bxD-m6@1r#nVAd9IV` z?NVhN7uJtiC>4jRXN$odf$LjJzr&{ILB+L4wWHzMAByoeMZtAYCsS}8mSXgxxQ;}G zjN_UTHp0~*(EWeFb%fIIitB9x7xo?sJ1VX?nSx8ttAb0%YZTY_sy&WtrXgQXK6z(P z;QEfz`+AJ|io-C6kNKtjp91y73axu%{Aof^fYF97gT<(W6r@1K0PI{zzP?DB2M_?}Qxu=ixTt_MWiMZ=u#id<88ZJEs1(yy(6qoK=h~hdO(cxNQ zF~T*^{?l0C`hn7)mW|udsDH)D6kOVM#_%isOLtCDTtDmEajhX=_f|c06L1})^x-Ds zR~&{>9@g(8ZgI{GL&PJFYk6%RbG%SO0@ zhb0?uouKqF4&(l{p^9op#f813!nVp6c9h1-6kK(@F|sJGdLbd>xVGAia9!VP5gS)e zQu=tOF)pM26(>{rm!4Op-|Kjd;%cDB^@Sl{lLq(h1YAE+`qa?XTn(M7`0=) zb~D(#eVWqeMoe&N=cnP)V^DDEFhp_b`e77TbFU6pIBbOL3HzfD0M{8xUt}@CrCmQ7 zEkMdw#jgu+3wCjxFSFT6h zIYn``*0&=TR}A7p@2b0g1g@VceYxxEabcggXbXm+WVqTzL|r~kTrlLTu-#itf$JAa zU*k5$6^DWIg+1oNcFA$wB#F8l*Pp&(e0eES<>b(Jfh$7knI2Dv z$Nc`lb)M4md?mo8AKMka^lKSPzwho5Ai!aiuRCo*#`$uq{mc70p1Ydzw2Qnh*V^lT zVB^HElz!Av4A(L@h~9Wo7Is+sW1T9lSH^rh47e^(`bnn=uG2P4^i>jEd<&2vE^Q%{<9bK!_p!Jd*BZ&zpMInC zpNo$Z3SVbkrHe~jIpw$}Y3&%pSMRY0aYwc6@05N)GU4kNU+Ll+DU*fTl7cXq44#aRoE$=cGT8pIj;9DM*VA4hfgwr>k>(pkO{7f>iLxpuIJSA ziv@M!@waNmU~zxGt;bS2}!Y z%f%emGDE&EP1VmpQIghJ0Q3;$Q3@!ex>gn2cZ8gj~9~ zw0VK!%CH%=V@mR8b%5({lA4)}UorQSN`)_MuNLRYabcrNH2#VmS9{bNoCRE0NV?u_ z+`nROK$Q-za%#WexPoCLTrE2F`wO`KA*sE`1lQowZAWZ5*YQL5lLN5#;^4+SjG934z8-IJ&r4S10V5MZ2$6q zkevZsWk~8_GJfH?=+ebi-6`yGTnBtc{p*e`Z2=!&+$Z(6nDnnVLc&hz@MTr)aa>0% zMz~VyJdT_72?-?ix0>M6Zqt3fsxXO{_G#kGrM1-Bv!By8O z>~UPDJVv-~-nM=raFr)%pxOAPjnAcnt3HTOUL02>Y=o=N1E2m5Top(fY&L%NvkN<= zf(uVJ3VR&aMTZft$NT?!Cva6H=^3v{|I*^|(!q7WrNi~N&j?q?o;CcyRf(h#J`-G8 zJYG7u4*Ftoy`NynSJsnveGgofNg8Q3erfS|>EJqS)8VRY$XD}$yRaUeP=%y7%*HP* z9xokSM_f8wH7!Q%*rU4t2jHqo(%WX^mlltg4z93IhpWEJ2-lde$F=~jY9zg9GwEMi zJYG7uj)rx(n#e}D>Mr`QGH_KVX{y}>mlltg4z3?{IwpG|;^U(Xf4f$Gp*)|@yYLoPtNju^}OJS#U_|o>ka9sTj`N}_e>s`QA zhop3$312PM^D7-(+NK$fYpAkqG%k+5T>Tu2qwA7{hgA&MbF!{?mM&k~E*p;PdBgR> zpAOwM1i0#vlp~wqYE#PXsBO#PxJEjS`hCjsyRHYW`XqfGGQriZl-p6;$HQ@rGUV%) zj|zVTuIotJW;4Onp_JQE+e^f8y=};s^T=ryuQnj*OSAE-qqlVXmv;Yw<9bgrYR3v& zUb_{z8j`fvWc=gDmu32s) zT}})Q)u~&Ab3y%}6?LGJfG()Jhjucc-w& zajmo);d*GN;|t)jk#s3+(!aFrkfqa(JwrNNXtp-we1~Q$`by2`()jFCARBg>-!FGvq75_HqEY+E7MI zv++xd$4dv-9r||s#*i<6!lPG!t1V^RU^aef@p$Rr>Y;DPqgJDKd_v0K0bDmw#!Y79 zmlltg4z4@Bx^_J2Ho~>FQ{6=1YDXDeEGGSHrFwp)gX^x44%g2iBU}l-^XxuMd&=l; zHNmCDZ@zBITgJ|82Y63odgUWDdQno-)1TX z?cQL?G4$89&z$N$BMd9%q`VCbH&Mpp9uo}OeZZ1q7@%*9IuRobNe{1i9T@DCF~kgm zcF(Wm7#`5K1-1`F=l|IL@S1eXpS%OXx}&Q!FMJwDkcELnB`-F4HyJ ztfxXkk7MW~8MQ^9>BG~3;Wo;cA)8?6>=brNj$x=;mt(k3Hp1}KlU4J8;daWvw};nuvC}X8;f}y9%XUQ=ns&zRJfMn1g-kLSFKQQ#9j5M?UaF@zw$uYd5*5w%7hT}t7 znb`f{J1Jwm8HT%^g3pp;cvY>-F}!IwK6K7~^HpGQP)5LE(iVNZ{~g2YYF&flGCynAse22ZL%P~v{8TE%_d%q|L4816$P&UEP z-zn^9ZE>|2B5qNaV@L`cVOZ`wBKz_o0jf4wJTc$ok(gXwN=!3?CYf57Wn9yaO2S zp^R@WCKw)Z{&x&}+@dbWkm@q(5BDU8SfA`m8AoLk43DXNmb@)?>M^Wv8(|o7YS~F( z=tmhR&HBS2t2mdEW7uvNbvX}f4abMWn+`D^?xl>M%`iOa6n09EVT&HaI>Ygy!m)4I zT6KTQxZp5pi^1Oij$xA?L$=}g;IpxxPfWOvGXAufV0bE29K%({lQGX5@wUj181;v0 zU%&e`FbtrKe`FI3T1=?5#nobH>lFAo1}rNZ%-xIRsm}w${ghczGQpt5geAvNM{P%r zVW;8vP@%=*3Bd3GWmY%Cpv8nG$52z!@vz%)e3;g++jqe5AZ6BZoA5BgD(sXTgZ9iI z=izI^@uALz+(E$Lq|AnP6AUk^ZCY{++Ov!t!}pR=f5`j!kL|$l5M?%tm|)Oi!jfZ1 zQ1NpNCk)4^X@e8p!0<3-UT@YPw3x8u7)WhLj^Ssk5f8mL_5TtW9-++kW*D@Xu*4Yf z3qPVSaSRu1Mi|OJg{2@%!lRUVv)iOCw3x8u82;2@m|M-te}@eFTjo}?V|{X(mF8Aw z3zbvs(GOE?G-Wb=QEkc_GW&48$ji1wKSr57oqBjxY04xCp=4YLISCHqWfR?y;paC5 z9qcqF*o(_1xr)ms$_6r9aoKy};xa_87JR2MN|YD(>wyg45-w!;YPTuxFf914@L1V6 ziOJq|YBCGWZDK1SeXYCS&aU=>lzD$#4-@poJQ>K~T{C@g- zLzPC~dpfE(eKAi=GDC>pv=$qozXo+6D_=${InbP|%#?TDPg3S|yGidGV~suCYwvyI zy|MPLz4vKUY4pudF>CZ`Pg|-NZaZyKq}N7jKd`*50-EK8-4^_s!E$r35YwLc*`s`x-kn8R(l<(y=dX&1Ba5hEQf! z$b`PxR^g&_=$o%XX7;X~K8-4kz7HgUS?hgGy|FT-_t`?44D>AsmvHL1|9IEmK;Ki8 ziJyzm-MLVw4*gD-Yrc5#3$Oxm>CmT9rO~$_B7A7{wN(9Tz3+ObrU&{~mUQfsTRn3K z^gT_P`>iJQtyEnwc-Kx}T1Y@H9r`q?H2OYt3m+PNZB)M+eeJB89_aIzbnLq@;N3c) z&qbL(x=rZQ?}NE^`f|Jia_P{gQKixMu_SzG^mTB?%9M+@ql$&kyjx2;_6`2zomHT3 zC}m#o8q-(WGcSIATbzbQUz`jYSDm!^>xX0QDKqbq7+OTmn;H^&TJKxt)MV&=`whmv z19Ei9fPaWvGB`acbvWpIhSrspjOjC)dDmZ5p>PV^#ZT9C$zZ*~%)9}qgdDowg=wSJ}tV|jE0$xpK zp?T%x64Eyz_xGis?>Sm`v(tn=gPAwxYlurupTW!<_jR!oOGKYWl}2AsN0rk1@?)rq zE?D80>2&nfwU>~-3m^Tk2=oo7bq==)eFigc+_(0YY`L_nEFg30aYP%s2@${3Uo!eM zsxB`_ilFfxcU;#e3hs($~D(*DUK8LF=B9{*UO}V;7J$`r>4^ z5=y;BG^`hJL^N?g3ht(qR_ySt=gUv@$_7WchC>s}5S(`U3;zu_iH zxaAbMi=VD};G+M!4`s!rT|{TkR@|QX%&SqQ^}drKVNav)v^7?yOdV&vnhf+kQqr;S zfa8l5pzlRm_m16!K7+;j4XsruC8y6|v3^5K^>n$t649qorP24RL!(86&A)kKWeRb8t5s&$;aoYreoiRJ8c3or%GmZ?{ev6w&M0o$G#YZu{|%Vt^( z#yW3OwTP&mWVJOoHvJV;chkBZaUD}skGVy`s&D;P;(fnPgr?nw@BE#L59yupCA;iH zT66ZHZG>{(2`Rsmf)9b|eyvWv2(Xhl<#;+01S`9{jc8H>>t-|*#&f7*a%DZXX5jVa0bO<(*&bp{*sGU;}i{D9j zJ1G4&m4ftTmh9c!he*%!51m#iJGyZ;KK2Zx>}>aS4Oj|5#6MDsvlU z{~dupAhf9GoLe(S{* zizrYBY}A3#>%yWa(7@#yaKH+Yo3>YXli%YOMgEDdy1j>^sIiR#jZo9(6-9yO*2g0M z`vD>wZLe!1|76YARJqmHHQuHGp7IT}1k$$JDYx~!wJDtRi+Q=mI)-GuX6&J)Kp)Hg`fmJs#yu41E932?zHS)BNP~_`Fh6k z$*}4hDByyxhujnxW*4;r!!4Ef4rv3C45L=^V*w%BvHe-{a|L}u6c~Y`5l#vuN}?$6 zvg^#in?Y2f14aQO+bxRxxwaRQ-$8r1Z4`J#qQEGpC<=@UrEQ!2D+OK;!=IDvbT+f`T}&?Vh<)>;R8lX@SY8HBGBET{^s}<{^ksYiyYOJ2YQkgvTuV ztQ-Yqy79J9;C+iQ77TLCc3z3`B z+Bs-yI~!B{&`NV>`9E;8qc6O8+bHQ) zo2Zs_Yv`r{H6~HuEASTb(bVhhOmPpCZgEi3ohsm@JLSb?HtnInK_?|eLX>o`L$z^l z#8GB!AqBpHxTl?@7HqN$9C1+au!92MJJ``tyuXM0WBlkx93Au0)b1fxb`ri%_$cs` zj~)GlXyCXLNIdKa=N>rYqQE(R0_S8(x-mk5^I_pU@T{E!OTev&SNHbsbz;sA8a@o_F! zITalE1S5@|?5MJxiaIzbvx<)$RmZ!MOzD$kc2qM&In}(BQ^(GZ>f&7oN7bzCsJ?`^ zgK{c**il0l;GmqgAqxE9P^-1IPFh(5XV(GN+WRP{QHUwp@xI9m{|+iLCH;AG<_%xzUWmAzU0^&Zt^1~qlu?K zhoX^AwdfT~yYf$rr{t$?H2npMroZ7(i{6L?UkisQxtC1SUv|^$VXFl z4Wi@@D0UZaF~*UxTd#gMO$rUHhr?4X7qyib1x+o+0|M_;oOyf-%2x@0YV{)zKEzrU;6Ns zkDF-5G>MY7J1OZaNiEv#djHW6Q)tFZF4VA6(mu`Ce%HB6tKXs-_d^^)7krEJaf6+b z_IfGjZN^7Z{SZz23TKbcmQFNnin4LL5v2F{h^97ylBMhl%a%h3p%GDFYUQdlZM^d6 zgI=@D_NTt8K*{*(2Q-4vywk%sgX=ZPHfYLjnm)$HT2g4HakXbX4W@4qcUIj-(HTkZABZs=Zb1dA2|$c(jD{WU7&3{T`XOTYNp?2 zHPEzd>2}9L+O`b2NwVM*Q3JZl_S-EiZV-O9+C}Y*b9T`h^_Opa92e9MFz4mWmBE+U zA5am+Xx2MmUm#J@wlE8Im`$d6I%Ht8ZrO_CZ>FLx5(}k-<_?vQ7@KvTp1yMg6%{yG zs20`CNN^h1to`6^?;fS1O~CnjSZG!>!ddH)Zd8Mc@_{qaAv7C%4Q$rzzUi~)s3-`W z!(^e^A#9*&&1qXWii&bPEFKn`^*jceHI5`Unnp$0!1;tHs`+MTBb?O_@9gvl6>S90 zhlI_{cCvxZY9C#A{4FY451jplW`@hCHLDKU^lTR@$^_24Rm~Ar1DjPMy}MLHp5tZt zjs-8YX2z3l1I@}Ey0t$@+i$S3d`f6e4;g4y+EM2Go5<6Ev!hFB&NH%E@%h(Y&8F>* zEi4}tnk$TKR_I^8=ThXEz-hAy&D@BA_wtoT++PEEEcm?6Ei^x|8fccw-TT6?$dlbH zUyf>K-eNP*OlUBsYE>lLuvyI^Z0>g&XqNqHZ(=5rdEhLkp3#?X1I;qk8n#ZMBFV`X z4TQ}rAp=dSS8rQyDq4%t;&&;knSR>HyX8#P3lphmwZs-ZqMBG(VPn8xH(Od^GO|Rc z&{>6~W2#_@wCZX?WHO7n_QsGG(Hkl@7hzg`N@t6(QJ06cp7{qQj!D zP8K0XWlH>5)ERM8btYn1lnAq^17wx$LdHYaqDR2D!VS~oadr_hWyIQ1J!O%oXsC}Z z6fs#Dm|Qo{%SptuL{ryW5gKfa(7JJsA9ikI4-CCV{+oSlL5-=i7g_MzM`y$MfMql$ zU@!PnendPvJ`34p8`D!pVj)}RW-?{W6|&PFCY$48$Lz&$r4N>jaJAm=*#um#lfN@E zR6|_z;X!$o4z7hRVUOeb%*Epq##hIX?cqra0B02WyIAya#8-S^T~AbJaF)sJRFzPJ z$(d}W5C5axO~_JZ$fC`}WZd-^VNMCw!qRuz(Nw^YKG*WYCF=*k@CNz2B9V@xM4|hP zkJ(@^<}crc|JQ;mdbu!r3|Hn6r3(R9=3zXA7R418Dcirt8{QFmnE~u`9e_29`9v*ZDN<4 z(vD?TEj>CCA$li=v9ClyF4{U1pQx!YC+k{Sr}eU33kQfa@*t zJBkkl3a(0y(#54r8!E1T5f#@wNyT+^5)}d0Sn?y`FyssC?WK!LnfL^*jL|Btj4@g} zF3elA?o$^lruJPo*&ufCK zy`yybQUX8~*KoJmj>9FDuW{|V5OBRq{`+MUT%A0ni|baOu*b)VmNtPav!zSL<=HZ# z3vhYJ|6s%f*Xp&;a6p$BA5SPJn(G?imEc{?7^a2>O$xb|Jx{s3@IBL5)C1lK?TtCaXs zl2H{`w${JaT2)*_fA?Y$Ghs6MpA4Je8sZYbN~ax_bXvuQ+g8zeTS{@LxDHNO{5)_? zA^#AoF|N1}{+i>$z%W^yCvV61Z7Qze8m@Z14tD^qspNm!VT=nm!i1gD;VaQ0>~UN! z4cDz6m9Jj?s2F6=zG@_H`UtqDlmEGp39fhTrHe~h7!$bCFF6HY>A4zT1#RDM z2V67AKf+>yYf35OQkM2qT(79@nEtHRzuwsW%530DCjX0e6I?UhrOTJHI4N+kyP$0G zpQRi3IYYVggMc%W{E03-9Fe->#%eJ*(UnmqXP3Y-8UN$bS)RJ$UaP3fx;EQ`5*?zj z2Svru);i!gFw7$V$he_E#jw~X?5LL}XLj?8sYr02pSI zA2-r<)18W8xoW567_=0ZW9X#uP}`|u*wFa*-oW4`|7&qwR>iO~EY79m7_@YjW3XtK zO(oGi?{ijr@pyY+c%S^QhmCoNTeacS#nrY&OzO%pG}Cx!X;*pZyZHR)z%YmWZ^$MX z^s7lF!=R<93$Un|$%tQ2^3F{Lj?hi5PC&%D%s~9F~JfwA)&(gB_*x)3YV94WkTFEg?(|Aa>scrFU-dMJbm4eMzW;`f&&;A<* zErsM5W`@+Z@Oo4XyK61_5EvGaf0osxEo9GsZwoD5@}MPT@d z{7dX67!EpxoswhFvQ3U*sZ+(U+@fL_vF*4@+7)F~2L>N@Ih*nDp6friMND?cF>KIy$dc8zs5|eqmw+J^8yZb`Fr2Ec zmIo~pxH;!S4#={q3wJpjldj4i$SdML_W;_^8Rac8a%hEW8 z-N@b**Xj*a{~phRg1u?Lu!8)%Li)B4H&ElQi!-cm#`V+7HYPjbKoNiOImFFmjcrj8 z@6V?_Om&6aGCji%H zi81=*?+-Tyo~b| zbH|wDy67tQaGL*;L;1>4|1VyAm}-lD3F#C&`7ebX-4`(`*O32Q+$ABtO$m>z2-ge> zf4VA8Hqi~3ak2^a;<8CD$go8}*4{*!$+YR6`Iu;9b@lrZ-U~CCe)^sef(%;}vMc)H=u>zEeJC37W?&lVTT9txKxcE8 zutpY@zBw_%D1C8jshqyJ5rxwiHySDQX;&_%N@k~_%|t4F(QPLT5R-BGq8kN;jMEoG z71QJNVOurRVK0?FY_3)$ij32TE!LV0^wl?@?>ck(8aQ@6RkZ==OQYV7tqFJMyb;Knt62e-C-+6-@lK2!Pft< zlm%POI=TOE=)<#c0x~;Y-uq%!;keAk=)20XZ^jKEM|o-VwQviW*85t!Vr2?_H#jsI zT=w@Bqwn9xzQlR1-$7pnW%sd}(5G$FV(^rUSHI7qWMkh^ftU{l3VqswkxJjyj(vD8 zLm1TP>tGc!jXsrSJ{~Ic^$Kfxpzq1zy)XM;$G!n8FV6#gnUwvg&zQdd-;aG7RT_PL zJQ^+0nK!3jC|0J>cb`gq8P?%n2p8{t|2p=``#awc`qokQFtgrQ%7IJV_{Do)yv$aT zu}`B)qwj&@y$=sq6{pWBX)?q>)goeP4$pOWlQ;GQHR~yRtXJQ&#B<#-uo?T?mUu1Y zkuKH2lU(At?ip(^aWhGFMYr-H{bLV4-~sQvo5J{j*cTrjI^5%b@U?+*rdp#9cn_tV z&s-c1Hq+&-aW)xqDwT3iS}FGgj!%2xF!$#W-gv@do|7HnDY4vhc=l*wm>vBp(cVNm z<^HLh6O82k<*QY(Ss#e-5DxB2A44Byt3a<8~37Y~Z%d?~9%U)jd@3qC=? zGI+3!LKG}7iK1Wy*EiLrK@d4;?<5ZetJu||D&h7CjqamhWtsNA6QN-B2tWmE`0%z< zu(nfGtmC-PKKE@3)(TUw4HPlMM<3$}Ugz4kx8ZDv927j@i9QJ)Y;22p5F?L&PD*POu|Dw2M&YvkrD-_fhahnX<=N z*->XV%^U`L7OP0I+uQ2+2j@_*i-Wd<)ZpzBQ@q_l!P`P{&$Z`2@ZN(I?C#;uwfjG3 zzGuE3p}lr6+namqD^swqlX82w#F^$ggQIrUTL8n?vcKGa5rcm&e5Z*x8P^;C%vt_|)7X@EO(d$6? zx#p|D*U<7&A_YfVDflK3)(Q!Ox%KSje$Jjx!MB|h92=&bEt;?GmcgAGuB702FWz8f zqD9oozTa2R+2}nAPVmyqd0xsXl0;F?7uFAd-%AvnVxiz<)J*cCT5y^JpYUkh1fNh$ zn-gjCW`jc%Om&^TI6$GJhW{bL>AgR8q{B6eJZ#V&OV7yZdE5c`ZR*Khh}W|v7?n9ysZ>m z!@KF42+iv1qhPv?m8HXPI!L|3%hpR2T|jTmBY1l#xP_N(McEdVZRcg%QMMgrJ8evJX9#Z>1$SB4(Jl#Z2jxD+J?!>U za5s9)AYN}DwDw}8yxGMx55UT;A#C zWM@a;J84!YFJ(8fvZJG6Dr)1T;E&wqG1xrjq2LJzD?5Rs6FB;bdpPB$;3-JY@Oo$M z_#{*C7hW%7#U~#H&+~fcQSUs4?Q#}a$tx$}?V!90tX^J4J3isb$p5LG4^Mj@^u7Ke zn2OdsIv!QI}Xp8bB=;$!hY++ZP1YP82M=g~nL1$t&bQJN- z4{RBk58Oq0*TccB=)p^@YLUa_6H!h7+g_pR z|6Ud>m921T=518;p^JqMOf$iPukuiF#%PvFt(8@ciWWLpBq20Us(i+1(i6EO@JL0v^<=JNT5ElBl zkd4MCVh>^ADiAV$jj)HXaGgYD(Fe0Og$Y+uRHj^Kvv$HqQ*kcJ5LwhlX2WDuPZ?l~ z?zQ1d3?w1rL+}hljTnZ7j1SV=N4nWS9hE7QThV7$Ho-+@m>U^~t6(qLCG90&84K>E=@Cm=Wl)q7u>#BjcXiP^ zeX_UfQ$sN~C2XXe$q1jPT3J2z(w-_q?5>Eo6J?Pf5qzxdvJGX3<6~ufF+B=|$pKKg z`G7E9=rMr)T`mD|-9(mj!~)EIOS)X=3`;SxC?^GBjv>G+E@6;4IfDZh^~cIM!00v0 z+lpZZ)3NEGRGa1MAsgF-jtQ|YaXO3il0yqK6S?5i6=nJpP zi|KI;G1mgefP6<_kg!zC`)8}I#07EYFp}2Dv7?3c<+Fm9XKW9@6$f!hJjsba) zz>wuoF(jqUcmx=N$df|GJRp%0c1p|xGA&V;V?cT!Fyx49xML{&g9mY%33-&0Z8yR2 zoNA}!7)E$?7=p@W%KC$>@z8WZ)@)$NM-CS^e5h@asM;wxhF3y549NHd4+R_}ff5 zyDTRDG&}$9uZ%gj*<@H4jp*A~k8#%*%?O5Doqm|;--DUq=1?>mR;?|X4sb&`7&C4LWoTPf!|kBL9c z&cFLpVszEt585U4qZrmZ$v++0{}=piqnsb&E+Mu1YIgqJpOQVO{!Tbzn)i(n`-5<^ zopO-m>t-;ud9?tAxlx*Tsf(FoFEiJs%^MS?@#a14<#fjeVmZG!y&p|s-L43WxS?XW z&W7PP#ty@v1Y(~?IH)KtC9qiOiIuS^Aoj)T^1vb{%4E3M(iOYvbhv&Cjk1h;1Gsij z4i-1!`Qo^OYjhYCTV6nTwhSmKh6^1Qc?r2WlZz%yTeRg8Tm+&v}D|~5@C*zAPNyfM1)D58( zhuTgBu3adP{2$@ct{IN2R!C$>SS*ga0CMZQk5{kvCII4|N^Q3>K*I|&TNb3K4I0d| z$I6tBrk@WK;Nf%4S6D2UuMyzq)~f@k#Zw$$a}8iC1Au*p z@4EtkyKxWTS^;j3Tpd6y=;Q!#$0C}g#m(!7`4hJ3cii)7TYPtV|h}cdLZ_J1#Bp=D7MtjE3c{t7abouCFQgKCcO` zeL4)vw67(u+Nh@`k^+~&&i*r*GU{p5HOKW(@h~a(F{#|}LH&U1Amu)6H^z09S3*1n z(=aI}+UK}%S1NuQ%N^{hH{h)iz;y_Bt<2i-iIDKg&ROA0OK>&5w1iXeh1-+5wpIAj z_~*EuD&CH{&sz89J&w|ZZz%U^vv#a37ssVV&;pmxVgCiLc$tDr>xUfIbH3tyy&%7N z-C-n$35O|nxWl*|qbsk%pTbvthwxc)T*`_xtIu&I77s^qUy%C_*i;|5zNOs6hzTzJ z8l8g6?)&e!l+|+;*K5VwaoT!onUlY?1+F8M`?^^>HnzoLxOTn{tK%H!>n#Jm-f^E= zeDWf2eMh-(neb(FJ;p6&v+*nT_3!;lOE)+!k2beY^u*8YgI(no-2QEkHGtC%0A6f;e|Z4>o^q#}0E|mol$O;eEy@g_AAObhQa}1CSLpXn!8Qjt z3s*!uadTYFUVQyy;5tgVvwSAR)d~wcti{ZF9K~J9<|D0gzlqu8xIQet>o4~si`kal z+>d-|BB}O0h!Tq&Gf}k#q25cowW-e8hu&} z$7Bk9THwihU!eGw-G8U=NcTnmfW99ocY{@b!Kn1vYhB6!ea9)cz+*z6K3ckV`t*_3wbQ3jrO|gjQk=fcI+@b@ zwA7o^cTg@)-=TlGcrDvkHpl~gCn$GM+(fMQK7A0$>C62&B;fH2(9JGh{TOL}@#^&y z`r>4^;`U6(zMw{xN+0%734Gect1Y9by$?IAG`;vOyGgTlSwYQ7%Kb5Jh80_OV@{c| zzx6YZ<;JpWL{V{OXx$vEs)$VMJ4w+nFK{Q`Jx}5v2p?B z4Q3x$k;@mAJjp&VgiqU}k|)@Q1W1O+QOUp%K46b@?hn2w&%Hd#hn$Z&;b@CPyy&&^ ziw~pnPn37Nm5RReq8@*dr5@#WfEn7+z!sIUG$pqwRA@&nPmC<@Hm=twrZVN0vobxs zEX`g_me&=Q;`P?sipetWDPGr~6e*@Rd8%AYmfNp*-P{w!edK;&EnatzrMRqHh{-e# zaMk4A#bq^IQ0Ffu>&#_Ud{GgCFv?{K7wxDgL|pa*j%Y^%C0x28SlIP^heh4|a7TG`o@)ml8fGTjklsHOB@CZaas{vJY5336=Hr8*@(q zy1^;R^LS_nF>BZ+*gXW>d3g@X3x?=}!49#FFYoj4Z%6Xpr@YVYGSu+_^p!`j)Jd|8jM#gZ~c7Z8?>mGix!Ud#{F_f!j@2TT66aD;mXJM=TqL92o?MtqLcw1wa6Lj z(qTq2<^AHMLhRd3ajK|N9q?iEU>{6?ttKMRUNYEf#m*m<;3R?CWKot2e@iW)8EDqKrSgk&D5VB8n}vjCOP_&eUFXVgM$-p>NsJbu*}`j}S?9&Q zBUaD{7d?zyq1oJHpjmrLLe>kEGSkT#NNC#J2AZ{QX?VjtN}1+jtt>PVTe5Wu{khky zesuo;N}23tT}5a%Ro1HXn%1(;b0;a~J>abA6q-#O1~zNF@!Flql=6<3by}g>*lwU% zeTQt@Kq+qlXH~DzY-BUgtY+=@Pzy?V12`+GHXB+EG^-vNe&I1nc@;P-s5To|3^c0@ zY}?lI7kq3q5Sot~@mXn?rFwZvc@8)&ZlU?KksGKXFlvU&@8_qH=!b>JmF&_q_Fv_5zca9 zOD*)|$1t1xE(y(deFioY64Qp4qm+k$^MX@oPWKvUmfilRZ#$*j51i*zoAW&enq_7$ z`uYf^+zXt)s5Y^3RJ?!E=z4Qb(V|N5ekKz2o}6Ma(6kh7Ig>=GAIfb0ifUq7#2B#u zB@deznG7+l$tM5ZZ+8nx-3Xhah31{=S;lD6iB+eU z(%OSoHqQ&q+hl<~M$>Yje2?7-5)jJ#By1|1=Qj_+sI^)WwHLW@4$EG$Q{G8_j_iC! zhncJeys#)&IY)N3ls^)BKZ?4_2KKLlU~(%{0~Z#`Tj>>dPV?3v+tF=b$$i#Z=eo$_ zh!js#-e<7o@$ibguK3mv1dN(6x{8TNF;-Th^=ZVFqAtrNS=7j;1$N)BW2i~u57zZI@vLMG1qzPLcFOEJm+ons2Hvc zK6?fj&QjibP;Q7pI|b&iWEeE+7zX{rv$kFtLAd^z@^a%`M>BB+yz-Y-4_U%jlNu26 zQ=S@-=lrN`=obmUP<}gaTxyU%9K-Z8a$IV#Vax6}DE|c+Z)Y?$$j1W*zJDUo)F6K( za`a-U!J#=VQ0-Oa*NBzWAb%9>zmAw(mm1tQb{XQLH{G=49a~&#u({{9I<)LL7cE_m znEV+v>cEfsy_4AOFEgJ+F>%4KPL9^Tw9cWp1z}Sc&UzZvrbm_d0mNm8+ zqy`5jG+##flbr^sLA{^%eNXvQC41H? z4|=1iLHP9s2-SzE^nwOrIM3)2YWW%AXUa!kZD}=~9EeV-FTm{(K7+-iDZ5 zml`~MsOkmEPjOM912MTSH5mVB%LbIcP^Q9uh{<)S!M=)rp+kLyT29o`r3OPr+AB~# zqPoICsHIB{?mj>1KFUwEQK35&ml_Ni*J3T@FZEF27%46_@DF=AmGVCgQ=tdGbg98l z)~{Po{z?xOV6@k#29NGM+n4fJg{fe2I4(7)a;d{Zl)u(N1+%SjsX_HqEsj%ux{nIx zJL6J=GM$>fP5GG?D)WnE;Z=icK;>Hmr?6WMDo?G zs;`>%wXIfsK>3?dYd_e~r3U4%oU2dyg&rz6f?B%NpnZ54PI+sX3b2f)PYr4p9J`0| ziyTz&vrJ1?+l4O#^}8Ei-beX6VQ`d15Y=nRBXt`H7GQVQ-fDsw>G5I!_Zvo zh-#Xo2D^se{SKubgyyQS&@@gBZvJ`3E=t|+U_*+~G)@g(9MQN6rS5^|r>afk)ZkHj za4DsRpt)4oG)WEW*1GdeO8o+wsWuB<=<~CTQ-j*p4k?t1ix0!B(0tctzOKw?Uv!aX&JsN0#i@a zyGd#wPZ{$dtu8`RHYXg_jHU)7!)#(?GK6X-slhuxZ%O2-0cKaBX`C9YoYkWvPYp0d z3r*wHV2^YAF`gP=o)?nj%B^`~Q*}T)A>_BO=8JSZuO}_Qb+q)z&S_x16_JJA~lGEvkX9xBB>_P{z_^P<&?Q%vQ(}&%EgY^i@7#Q z4JJ-Hp8^c$DgO!35=)7SK|2LzyJQ$N>KF!nYB1o^femo|E9DQxS;e|GNew2tZC8;R z?D{8~6yiRD)a{w7aDi~{t595OAXoB{T*)4n8r1Kwc>u{(owPPXj;0234Lhyw=!m8U za!tEIYB1}Qk1Vv-r+l}Ek{ZbM93hc32T0PcH%c@$V zseybm8q+FA7Z&8s)|k5n@-4E#U4!wiGB=RiMaJ)-TH;cJT8*nEkbE0rym79$)L?Pj ztyv`Bff#QBVpm;iVCgkvImtbIRFD*oOAYGPncR?M2WrhhoUBU?Y7H#fKyokCT7V*5 zYEU%h&c{jaW1)h@C~~<411ZDgzkBb$o8-PODp&>>!(3|7h)A7dFB8f4%2b#n#ia)S z4{u)rCv*M(KQFBN821qxa)%~K5}G6tG0r43B$1;bA;ia-V`*}&E6r*Zc4HhnSc}h` zyR*n=XV(^@NkS^7Ldfxdz2BdCzu$X&#<%U~@&7y?!_4b^zF+U-^S(FPvIh3f!q+6ZkALNHkb4`zo1x?z8q9BAzX8a7CGZAOE6=LImTHf= zLGB*{?KH|^lPh5i3B5{m||8uS>MQ6FTB9(*9@8yb9CcKCFVhv5nZHUxQx2EE#U zF#_ZfxI$4;&Nnn@VXTSyHPQjTny8g$XmBpI*#{txMql-$d_#k)H~)?Yd5jf&P3^GN z%ae?20CAHy4+MFf13b+YNSJNGR#JX11i@t?Y`1fb2I3x(iI_@^wkVKzbHhAHOtTVS zM3RgVw0r(D7u=H}(TkF!^-NN`=l^7%qPro{g_0wwcVbh!=WjTF@?A(gWF(H1^pKvFG~928=b+C6_qd;b%VRNX=fHj~uu`5#+z|3gTsf|C8YP3@ll z=;gNqkW>*R`*NGwJ^z|5d-Q^&@+jHc5b++R=ijhnsm7301|@sSOtPOvqn}*r#c=8# zNGfR{Ee4a+?)h(@dG#_R#h_$2Zd1GG|9aaN#UZH(O1{i&M(O!q*|s=od;$`0hDcM)Bo}M;{KsEWK7d4QXs|tJlG;80Kie#6 z3W--y@;Po(yXPM?>aW1|*L38~60sSj=RcuSi9WEs4dQGgME{?Vi8k_A^y!&mUjoOj5h&-+64iCbZ{|eSwIi z==oy@DMC{ly5J{f(%2CiwkqmPH)Npz-`Ipk(l{lA|C5CRe5W(ob_3GLLIJ+@BQ!A@ z!2X#^``@F1xg$m=V(0KW9KM00tW1UIkw=UMu#ZS7lo%NeVCOJ5tx%%@>`F3S(jCq_ z8hEj1T7QId0}kIc*yUSgK?&bQd{|45t}jgAJeJ4$|&hq#V18faws z<2YjY8)O|0kaCBFV-QIo{tAadgpOdyI~v&Aan>4ieG}vo`En!5XyEu=tF9C-0#pfu zJkcEavNy7sNX}Ful#Qmymy1^Q%l6gwqToAi0$<38lqO;Doh353T!UZgW^cZXFm8eT zJ{vKl<$Gn9ZqVx!@RZThSGKDGrUbQd#l_Xgo;-E@BjBlk>-yzw;Cj@?S@q3d9cnNN zJT(m9sqTo3EIf~+U^83peFUB-4IOQ3Z-B?B?jvyP!)V{r+6dWE;0H)MmSmx;_cf~Sw32=)o##|rLS z7V-ej>$nI{FkE{}a#8SnV1(os@$<66wYtimO}3W@&r~!x zMFv-n&^j5eyFHW!o@ow9?h=ON?n0}F^v>{?Q0pTHeoWvxBeX){;Oe?xfJZ_w0 zc8p|Tvf1SQ@{cj#nTrVLBEs{W<+>R5#(r}IJo8bbrvsAvnz>d#o$2os}f`010uvkZML(}BAvXSs`8=Qv)y51vnrkURiC zgA}gyh8)|b#VYWuG=gV^4DQlGtDJRwcET&*S?z#i9LpyU6#L0<^fLq#pfhq-QCpR%UoHfXT@Rkm?T|d&##qU3nWojA-U7P?dmV|h}Q0sB71bR7so@@OL@k5d>cdAvNKXWVY^ z9Jb-d03Nr*SRQw{jB)$ZNYX>{Sk#;&e9e)iv0FES$LGM02|Vc{T>*2`ZAI%K$qLC< z)S54REs*}+n0yXAM=@PTFkRS$vUDA{8h4GH2%c|jkUS5y7TFjpd9i6w^ZCz$Cujsu zrVO4F2FCK7P^zyxUj{tc4oJpfT=G&gVG}@Sby}qBba?S{?<6GY zAvx9x$)AdJE!Ukbl8J#ji|IOx>H5*m40_J#hjg;;N0JeeZTMLwv{uQp>OWT(Jm(es zSio~hr0bG3r&#yH;JIjnWGsuxYZPWMd98HD-uxhVe#LZM#&lf~>AGV3{!&jYHorR{ zIW7#z8*E(bGn3bPsRnrdFoP!?0?#!QV|lKH?>6Xs20VW$kh~r>?PkVGj@NzaY=r3k zcHjrobz7wCAN|X>7xhPy5t2W*LUMvg*Jj=KyQXdj&t25KYXPrLW(K`ryy|cB1Cq>; z`~_-m5n5a1yBA6f2XE0ZekAag;OX*~u+_TUwF7vIJ0STh)JjyC!Q>?AsY#nZ0&i(E zcuR%ATaKs8Th39|QE>`*%PNq(Eey#!Y+TD>n*8PHzrd@3ew@r4C*b|J|O$-AtOyceyiZ>{8gx_N)r zML)H}_`!5N8e%N3!JN6N+Xy6~hSLbi2ZYuEx%k3w{NQ~|58nEA@HP_ZYUEgETJt=3 z8!C{Tf?9_ZW-$4%bbWPBd+;_ze@!u6%|*JJEA>_eyMg!dFeD$ukK4wzJf@zPE4~5V zCv5mJfVY*zSl*|MrJD2zB1sR)E(aw0&5V_trmK1r#|^{jbS`5vv1 zWQAlOelkS5j_3l*;$`r*$8Tz4m2S0kw-#E@Sk}w? z74Qy4ghLQvc^)?0h51fW!X?~h8K%21-OmZFj+Ww^q<6tP0uheDXq4v>jjL=-zrB7Z zct;_^VG_7I39XmxM>i~A1l}=-@LgNJS(pwJo4t&iGZEoCXw>RJHSYuoKl*%gGQmUL z8sU1Zjqc=B$0Ob;7BcaYd-2vg%~;w{@&NAXL>rR~kZXT|JkEOSawjZBGZb|aG0!}l zWNPsicqLrQmJp)Ydf=UDx!$+oOYDeS;;&TdmZF4t8h^tS)X8R`q{a! zf#E~{Nn|ZI=bQ7>&+yrCy&qYtkdcN#crk5ZxSs4n2$tEc-5yve-y zdIP#MS6*;}_lSv3j(P(ou5~m#?!0Xic#j+D)&uV`BWEe0u2o7l2X7Yo%22?YDSVyK zPpwq_7w~>-rn?fnC(K;yq^{h+p--qYUJo*}Ve?VV3A@H6NzCxil zI<5Ezyg#9@Q|RkQ;p@Ee>CM@XfcK)F?q%@)EYkIhZrsGbUIFi~=nE%ey}t-wzlGno zoty~XtLWAHvrKa}DE%H^F-YSyyD7rxmQfmA%d1 z+y>s;2;)!mbyL8&qkH410biZ>5XN<6-4QVEhZ~O=QyhFnjC5w#C%UG-qM?QJV)}xw zIQqJ)fUg+$FX=Wefi4Bt8QG&1Ydb9HZczH;nGl~t@Kq0-&3pzHZ{)1Xp|UAuu7IzafgT9(RS~|bE1vId&w{TO`l={{uZHmTi2PmWM;`@W zUG!BIebpAe9(6Qm{cZ=GCJxhCWZ$DMHQHL|+ZjS99U(2}eS$xv${cFOd5r3Zqq1HyRP3clwAjE=I=QmhpCUO*Ua5ytZZ zMkhywq%(E#Oaj7aZwFr|k>oD++t$sSz=tDOvfs+rMfiF}$qe7Z0`RIHH4#R4;j5>- zd)wJW@byMt*c5TYX;OmFJdZ4d9!q))%`15BlzXqZ&+@<9kAbbt7t^RUF zP4Ep?P!oNLF_-T>-OH2PpvD9f-N5C0&%^^YG2B2-xCcHQx02%#zW0rsH97Q3(kG|E z_o0FA?ea}AaMmt}T4}7zAblaD2mPpr}@GIqS)B@jp z^fki{zPZBJf{W2V>? z2!3q_=T{ES+Gc!Ji!9^b1y+yu^8{A@~xE z5WI}O0%30Oh}70-=nlRw%@F*<49;T?&N^ z3Iy+k!FfXX`d0UX^~YbpmlTGq7&|ym3f3w4?`1Fi1il@5$SRAzz7KPQXQdNjS{TUa5o z_`C{anbFsD!I~jY==bQ4;PZze>oo&7XNI{!Nor$${RQv^^pJ%;PUjp4XU#K>Y1{80 z_>Nd1>zyz-7g#xKp>9dLq^;mPW`nHpc5p5hzG8K4zMK;P-*E?IeP9OXGQs*pz7kt@ z9QZO7$eLjS=ci$AaE0{ZHPbTiWrZPYP8h!IYQ-As%P~XjKs$Uj*-Ull#p=x$@6Ib_YX5W_^Y2rhyL@IUO@KcYY` z$+}(5chLL{2SLXq)502(b;?ZLKNFKClO!@pe@H{Jc6yTv#~|xHJ&6;O^eGyWkCfRs z_gBaog*cB`nWR_NkgT|VojdHp?6#3?XOeEahGdOb=WV-& zWyVg*4wH1*G$gC{bsjo}1uskrAd{3O4asU5*^5g;){7=mikakLtA=FN8nxP#gRJ&u zQWcowA&Z7&m9yS2Uc-8XI8*gZ@}OBmvhq1+)iGEZ9i&n+$yAeuWTi%i%ubNiL`P~i zlRRM5kgQnmyLYQVRz1X->|l~91`SDlMdbvhy_SWvF-&s5UPH3NQ>H=nv4KLIJB>_o zpH4%veCDN&DcH)%q_ty`*!mYN$>l2B*Hwh9;(F3#GRfqShGf~E3m)wV!TX4Fo5Cdb zC>oMw>fC`}vC+1Y#+ym*mNg_xUt9U(3)u1_&M(bOa+gCxvefe%I@QG2heBQ>5y>qt z+B76f#K zOFkmGy@F0dvd9bNpBjNZ1jLCmiujNgtVBpd5_+ubL%JC@(%pzietjpbA*m}lcGmaU zSCL7dB_b&&^R&ywc>7uX>msKH(47$2^CgmiD`k6RW;2&$wL`1rFX&DP>{&C(-3|@O zs*^^Rt4nu6V9%XN?y_r0R{0^c{4Kf@0!Ic+a;Hs0vT}uz*&ooI5IFK+k`75jveNqr zJ-?(oA#h~FBzIUfBr8^1cK;;Z34tRgCb`|BA*uiIcJ;Y*Cj^ennB>=H4ao`v&fR~F z?t#XRB$G@sX-JkgF8}E^JsyeOTPB%k)Q~Lq&(z;;(c_WWeP)u|3>uPU`})h_alQ#y zmIfBBzFIqXP> znB*phhGfh;Nl$mAd!TWo!X)GE8j{7D-k6+B_dw%Fh)LRQ8j?jz?fGmy-2;syEhhQ7 zq#;?vH^}fJ-2;syxrpT9+gdi^vq@hKpnITkq{wW3s1;A$GyZD>=^khti84vW!oBY^ zvi?%_FOxxNXhV;w>PH!;DZ%i7JRr{Np<9>QFcXpBI<}ss& zWR)Gw8f4Nl4>&!;Y#udeNLH4^S69+A4>d~D~I8((Wy$%h@vQ@J)chQ|sI1|PsJ$4PrGAXI2pQJmV zaHfq(;>rQ5aiWBj{^Q!fR&?hR&g3ykm!u(CYR-bDxRb0Tj-_{Vo3d3yvSg3NOk3-{h z5tB?cYDg9<+os|#^f)w5M={9*1`Wxg@78#=0X+_l(_Kt5MXw=QBxU)gIrKO*PNy-+ z{W=XvXjby?>-0D@PS-KXy&(-r-Mt#a@Wcg~T)tnxD{s0$cnB=1t4ath8YU6&O*B{`b50k8G){xYH zHZ+LG^=C_DQHe>`F=gGrLT(woyZ}{C?X{d*~S_oS0{lj~Fy0%l*{O zmrl<(;lw|a#QspEZsy9Pve!4h+LxYj!i5DUSyQJWS*Fr&4kJC|gbNoD$tXJ=ujaJB zPR}^u!U&V>rxnjqTN?d-m7a0Jg%>9IrdB*lZnU;KP0u)aB@2@r9@4;B;)hnBm#5bs z;Ph%lGRjWJ`OAJ^OLscr8VIvFK?`S0vb6OE-RX#HEKG8iUBi1ZXUbQP(VdRChQlNm z+cYGL%6-1m)18jEM#LmnNg9$x9_gVQO?Nut8WfY%-s$+#m3@hHr=xc+5hQ)@C_5d4 zE5AcYoLj{;w1}j9QD)xdi@ZNyq~7q@M)YD7+!)0qFYxl2OA=Bo#Wn&tCy7gT5y>S} zLWqLwiNyU&O#5d8_w$qR)BDQKd*JDb8w1o{431jljXZL)kc8gh5vRaY+D^7o5t~#} z%cgF4%NNps?BB*cV-ZPpDk!)ZM_k{92@PYUP8MZtF^~zPh@3i|bjXkI;T&^BE@8F> z<;mVjT(4AVxK*jBm0gP9Dxt?&BHYc!|0_LF)-}JyOY`JL(R`yH%pUC|xp<&$I#-1Yh(^Xo{*F3n&hn{enOo;0r zaFww{!KG$6u|;hEM*i2t)tUx~$wkNYj6`I}LvdB)w@J9Fg!2UsZK(){k zM}-I2CzJ=^qiX$VV+U7#b0mVT6yCi}-7) zJQr?J0xz+{lHJ6X*B{#|o2v#y^S8xL(mcjS(n}tZX0@pxG>W0QgJXEY!Z9rA`C3QB z0N`pKj)FntRpBv+GD0ytsplA;k~xMJ)=Yw-2)Ld!N5LQpbm1|GibODw?WB>s$L*vl zh8^9_6)x$DBZi{jdfE{M!+S;&OY#s5*h$B@i~@G4wTa4E=N*LyayUpGFKNz|}b%1;hL> zvr~8s3%M@E@S2`ucukatPS>VQMhqpv)zuLN!xEmB!edy*bt#5HqCC7IFa$Q8_aKH+ z;OY^rJbY^W?{Qekbt#6S0>hgU&x?5(w+11G(%>>j!?4=%-!ZJ^x)j538_$ckOc4w# zbPbERZX<>=;Ob}0n-}aaz~TPq|AIknzwP?mx@wz|6lOGvYowXudPm1`mF!%s58^5d zu7Ua9SsWKm@kXA)l#%GTc5|#0*SmU->s?lER_NxX6iY{3<-j%A93@`Kwug&rKTjvc zHBOYJ@dDRc!yoSH2^Ki=7QJzkUYmtqYuf-;gtGT)R zCB#(`Tw|3exW2JHTwFmTvqy0)HFI3cbR1WemF?Rhu1esthN9rgb}%~+Ctlz2bW&WO zit@Ew;Oc(m&_{@?GPov%qu@HNf4I2L@^n&Ms|2o9GLP4|1>cc(eHCzh7_I&K(fDw2 zomZGWiVM#ju>Rm$iQ{VE|H6v6s)9?BqQvW>joEoP`S>eOC&jhF#&LaS;<%ixJK$t# zOf_)Lvqi!6yW`>F`oqlZQCxO2#}zNi*W<6;YJ#|`gKMEZ3a-BtX6NC=>u;V;iYq~s zugwD2-g(!qAg&tVijCH;-Znm5Tz7doDXuL7*A|)Q^ziw#B(jo9>ul8#&J1J9M`?B zHG=D7BV@>Rk#we6kIjU4;NQ$o=%GEfWUP?=J_~j;_ktSt1h@UM`^$C zsL;d3^_ZU7qqq(!JYI(-j_ZSo%W;w}=238MjnaPMVI*ef;pAgeo=%D@vgU|$Qpp|@ z$8}>@JQ;r(!1Z;M_6v_YJzQK**qA+v%P-1(nkZjqgJrrPu6p3wDMu+^t@O;!!-?0^ zJe?HRH==xf!^&58^O-x%WW-e;Tzm87BcD^tJBL@Oc^o{r#nMDEWQwvBWM!$lIpFS& z%N8+@f$M-JZ)`XQF+W(C*wAqyo)F88fgBVgM-a%Ycq_TcsVj@obpvo6*5!50r!fEJ zlocL5%k9SH3ejqlXY$==zw+mP(j93CF1I1CKXy|x9z17uNK)0Q1rV$E;wE^Nmy4;SV0*owx5?PXv=m5n$ zAq99`Ouh#-0Pbq@Qym1@7+gxh7s&4jjhxvdPRaAY2u9X&nOt;$ViJ)8%n<-jY5=Uz z+*S_(HUZbS(E#?AiBs}C7@)c=&E%p36f=wz;28lhqyg~Jv3JQdSyOPGjRtTa1;-pm z&*C@!Wf>IHj}+i}0q~**z!l}|I1ykoaQz$&;7}7o_}~btn*~@xqDOFknAxKMe-!}l z>m!ZD9`eN*2CO94imby*8uK`~ev1Zhgv<;+7@)fE;eP`Z6PE-axw;@yi}C7$f&lIN zu3{F(G)F;4lv+H7;rkzDaQwf_Vlk^p0hSg3%V_{?=cw8o0k**F6rur~ATfjwj-a|5 z<$p(TwS(EC0QKPl?X$b8e$yTYu64z<1b0Q7cHr_Y#?rbGSruj&X!{&l3umHZe%Y+7RO4t!KeV$Z7ziVV1S~%rvO_BfJO~~JGYD{Q?9MR-J&o6)!ifv zj0#ZQvBPN5vskqE6kuxs@EHw&(?{)@g8-ibck99cR5!*jFeO`|Tet!NJ`L_p zg#oB;S0ac+CE4;X0gCpX0_tD zEeBD6W&yCT2EZ|n73m1@8E~5m18}#2ArukB34zG-z%q!}>o7SA@HGK&kOsgV7namP zfNjD3T44aHJ7tL@0r0qyIesueu|PxtVx3{_;4lqtK@H!lhl;8=-AaI9Pq z;F&JnViDkT;2vivL?!vjP!Qln?)bp~#o7@C_`U!*StEjz)>OZV0NaCmQego8YAOiu z>c1?5-`JQg1vpIr{73`f(0$ckMSvZ^J-sjh|1vNqqLSRmLyO+bh}9$taJB$APXl0j z?c&D~U`KGzDGb2dd9qWjB==0YK}QF8n(I=43kASfL%}lW*j1}20(>6aiwXfSa!iQ; z;t`B&6=$^Q0LA(e1^9`~E6EBCfJ^uFe-i~>YlBET--PALq)XAQZ*sI|C5o~T9# zSXN=W6rf80^lAX?s(+Hqy1fi;S788R2P5)`GT1p!RHFkF>r@mVc1Kxv>xc$Gdy|vB z5MWnurxylb*HA%#ul~yj)-*F+3J_mp3}Db+u#!xw(e(}j>;~@Rg#oA@QY4N<1pEEV z2#S>}3NXjS0iM(VIMmjgyh&aGcTT7fm1JOuML_@@tmLLe&tkEJMFE}>07Du8moLm} zh5);R`%GZ~PB7&LqgE0z<^14UEY`9p!1Ds&MGb(X2mH|q0rmj*`N9DF&`=QINB^=6 zibX975WAMF3|`RyczN=Zq@jKl+`kqE;B1C3R~ejdWW)zYu&tHJQGkC6fY(C>E6Gj$ z`o|GqPjLTP7=Vim%!w$2OaEmA#XKklc*|07-tw;0ee!(r3ho8&+q!>WH#81)Fr4K7 z2L>+JQ38UC++rKaSx-@0zQ8S7p${)!MJlfu1(hfOD{$Y$F`c)}x5!26M(*dq0PQ@$ z1Yq8)uYJw-ypC{sgQujN7f!URukWaFZ-SRgJ{Bpt_+^k|e>t?%2Yh(#(Gf5qx(eWS z*wLZCv!Eq{_=Pv3-70K{}>{?N*3@}#I=NTM)IqQj30C4wiwIAW_j>xP1zvgcxju4a z%5RkD{W@-|Oe9;OW(z?O8WsW-V%Fyp_*;Ysjp))uWPPEKghXiK3>XGELKEk` zFpJ1T?9mL&NAFk*F1%JO-4_lfJogOl5)9O-mgMCbc2_NU5OUR zI#z;^Jke69rbfV_fy8PN+317SBGMwYl0QB456)7?;N4iPUE%7qwUB z7v+KCx?6B14_`Pl2b4fhF?gloKl$RoapjG>ic7?pJIY;q zaW>)_41S$CO1wm^Bp6g&qLC;(F10;nxctQo1#tOGgj2hW`Vw*BYo%DUc!}~La21Rf zdHE1u_Cxv!8-5IsKHR`qezV+j&09+$ z9nZJ>8;A1zF^dw)`SA38kbX8q|CmMkjS$mH|JyRS)}21Ef4>g0QzcpqFqO9v5Z+yz zQqI8yQ_35!^*l8Z0uaKF6#~V0QUWpNVjYXTh$IVSyA?>$Tew!maGgKpc@QXx8YOiQ zC}U!*KpFYnOSNW0ptJ(n0RyDe;Gj}!T6+IB^M_=VpvtpQQRkA+0Y*;puB*?~# z3sVd>#!9KD|77*~fe@%_!;b+1H8_kwjZjRNm#;&hdKj{Ebdb_S$F-VBZ{7KRECgyJ zx<^p6u1MFTHp{>UaY({+eQ$%5mYkJhG#EQS(+2|e9r!UpprOPJ1{&$6%v;ePNqWdW z7lM>Fdd5m=Bil>+>p-9>qHBVhIDU*|Y@oUI#<_X_APLj;ixEQSJN9>3Wk(BH%@4lqLdxc4E@Pl4>W(ayjS5q#Z& z9}_IR!UaEW5W1z5MduV+TVC0I(AjzX)WE!^Vh(DbACt3zN^7!ICP;J`)) zu{ajpjy1ymCoSaHcq<&l@Eok}U}^_zSiVdDApilZ4i0`R!H!16e&Br*9IS?dmCanR zis|&cXX`;=k_`?v4nukoBN3b`!@){caMz~zr-vYCIC`8V5#B5WI1_(8Zed0OlCGGg zOgaP>g(0Vi1p*e48Oy@fNz;FZz|s(YtPqfd)+fs6we_Ux!*xxy$y2o1_;CogB#^b_o^X`&k=96Fa*|_xWPU0{@c~Y zLtwW9KPCvQ5(bm)8~Xh@90L2Skkb-UEHheX@_n9H!4M9NGb5@$^%_fstLm)#BInV1Ma6lM5Zf@*7g*Eyc zgmBCTfpnQ`DaQ9-(P3H7(m~EkXwai@)_1y;Lp_f}AP4>7je>zphhT-C-G2B{2%L66 zP7enJj!K*ratvC%tv&>Pu;a%FffH8F`qB1Wv0Ip~^XRLu41r5_&iciWV*jW(lJK=~ z01^HweEn|vWRJNv1h8v=!mWqERe|sii|*{yJrD@vYatyC{uSm1uS+A(r<{VoH3?1} zM;JHtoOLVoN&TYFBFPRXPJ|$E$I4mvbYHg*UxUD19h~^y3>i8bV`UUE{JgQ#RmcDX zoH!>#MllCx6*ukMVgbm&m7^2CSRtdN!day)CqvbPkWtD4C$3`qwoA`gDZ6ahtswz2 z%1Llyodr^GZJ#w_du@OEU&eQNCDe*HK}xEQvr?rZ#;+GZMm0U0K&L5kn6q5g)#m5U zLPpInoY;=7y)VRBe*4&j@I}a|V}}#TCh*VKqs5GRddTi*2mcaM6EhyOL3TTQi9SMk zjWLOh&ESu<5nfX}q$~`9qqdp+YVN>~33ipSlV49c;6N!EcFdE>uV>6~pqvddo+b4; z<5_G~Dq6sG$U=T~z_w(L0WwS`^6Pm8KNd)T!Omc&zht_g`)Vs>yol^hHds41Oa!|~ z_|e1uiaPSEn*lPqI>1q%n#2b6;P)oT=t)iXw86rz7Koi2B9guFO@s}ZqqRbQ^$o$& zcO}ReU?sl>=pf~;1Zlq-$ghD&AE<|nLDc3OVMdS|ZMG4U&>w%OeGY%Da(RP&6J)%N&EZpM+TdWUjFHv`+o$z`j8SM~lo2ws@@!NO_GCJG2+I!*fp@z#KVWX!Td#&iea&5`kAhK%`k@@u{kGUmy!bd{AkU%J}x zSMk@rfQ*mru#gave}W7L z*7K{_uyi&vR?17dEdz%wgp6I-DZhcN?t;}r*U7qmC}iw$z<#VWDSZU1uW5g?`X?d7 z8G@7-t&sA1m>V2qud|>^Nyyl*hm=>4HB4v?*Ewd|uvFpwuPMEeHNwcXM(X;_n_USq z4m!{nYL0bq);LS*sOuQ-!|2O`T9bsqNy_63bl3vp`ypk78B(UpTx*7P^sa9=LWb7_ zDPt5!nIl+pt!*p~&qIda0V(fWA!U(ZEq2VmQ0ryLNJn4O@bjsT8~oHUb)>Z%WE{~$ z%Ipv<-eE>w#xVoLHZnoRHxBaaxDF2V3F+_w-C)c&1;1o=Lq;O9$ruv$;|mFCJtUG( zjCP;WdWA>^MQE5WM6R!i`iwS`(neTF*cok{g~+`llXx@QB!$q%pq#q<2-A@=!%Ar5QO;{(a&swdqJe~# z(H7%3$oxPeF=ez*DQ#+q1T#XzI!5F+pzdc9p#hFUr`zZ>0N!oB??;*4>RI&N;DO^< zMZ=`363JpHxzwy7S;W-(t>Tb9(?aSylf0x(dE~VTzhpb^LH1N^B;%Om_I5@Mo4Q$- zm$!iI33}4&Ez;2b+NM)6=|{f$S(RfSFxdElFv)b zdoD@%xpntS^lz?WYsn(s;%`lT}7t*jP948MxORu zlEr`AcDN{<_{m86%S^Hwk9;o4nD@Uqh`rqJvG;zL2$E9gYOH8@FZNfb#Vg@Nj+yk_ zBa)sNvxa2R{xfT12{~>j-T#QBtGkx>B1g~u{u!JI-~b_PiAWxP)2Lw+c1*mGjsp;h z3`8Q5?vh%Py41R(UWOB?Ix?DJl07Zl<^o>dOD$NPa1nC)q4)Ddkfh!HvX*4YwR2Wa zf}B?kWXKhfbR82Z5;jZRoU8M75jO+e;N*TQF5P^Nv;oRNEZF4<=NGcQ{6&_)J$@xmdzqVDxI2w z<8d1qmov$wS~ekd7ye1G92|_`xSvVBYuE6uTRY7-8|M=gGOrMk#Ca2Jn>_<{Wafm> zu$^|d;)q;HyrnF9r*3R2WREnH$(V??Yp;&^$t79jK$YGba9#%yy-ID8(ruSCBw=g& zkFViW5k{^vL*&Am8);W^+0;GXcHj=k?rR{kP!aDqWrcWiCZYDTgha6W=h&FGe;UVL zc6{nT10g$XB=cZI5)t`vb|m5_mt-0F#`V59zh)=%Y)n$JYDkv0cN{bovVX#OG}JT6 zSr!e+QcKd;xFGus#<;G9Ns4!2F7G9OEH<$x&Oc&`s<1x@{*@uyVexCPCkb(U9igei`^*$fM+YXSP8?*CfoD^DL{6P($Zm%| z9nx}nNpMOdm9hBi1UVk1i|EhUH@r981X{WLD9Sirx` zN)}a!IC(%<1Qz@r!Y`3`tV)braf)jw{12JfO81iwp zCAV$1_7}lN>|i-k*VrQIV6;01fCzBPEmDFiqi{A-jb0M+gdF(?40g~)I65Sj|`sD%xQIU#f+rvl70GdT+I zb1MxT$&^izOu<_n`^$SKAg;H-Z`bF=#kL#Zx(~BMY?EZO!b9kUmLL<_*%0|n9zu(k z@&8C=CNzp60sqI?5DZ^B)F2^-E0gctM+_stpJ39)fGa@626+mNA=2~^U5a6gg=0t* zacDoHg#$6X4gM_%E_VT9alrK?VuL(|$DlTpM3-XtTEt<8h{J2!6YC*{k>LM2S{%xU zhz;@-9)sGf6J3g7r-%bR=!`WA^P*|V8k-TrJK*0LEe=)xdwGbwggAy|ndikmD=!cB zNr9IU!zl3Me2{it)FvkAQ}{TjuS}v$WX=R0RK}JUlKjU5ddY;@}f;*tmG>Z-`+G z_&w3$@WlV2JgA)~f`ej66LH8e^1N8S@+N7c#)3aBS{&M#hz;`ayohw+7%f3Yo>m(b z>HZNpis49z=fyWRj^SG=ZWdw~2mYgmD0%ThnAjjs;W4P4RiaBVC?<}9-H3s8^VNAj zZAA>@!LLYBFuW2XHpo+W3~JY!=u!;Xc8=j&5r2acVnK7$$)KOq4j_QZcbh9%8$27(|DIVmOEKK-c8GdEUV>JX2-;3B)iF z{O3$j@?un;GFdnbYKM;Crx-3+IEG*J9K)bK4VNH>_rZSw!D+rX$J&Vv@)SM}qBBM? zkmd789B}!ZV_28HdLLq#1pZ%jQ80|RstEoAh5%QkaUd)63_}&NqlolGTPl6q{fR3a zF&}{cYBUV*oBlfnapeWgi$5)N9$kH9zi?{Ci|BeX`2UQS1ykkRu4xzUUpJ4_Lrj;t zz9EXiEuETtY?{h6IoAs@OacE5Svw1I_2WgeFiX#DM=Kh%N=9ZEh%Ci$TVYv{rn7Sl zFD;(=5@MJN{(p?x7;uY2ZhvYV{w)S|E`(u7E5f_eX)%#z0pn0U_N(QH;X_EnNfGVp zuv+==7}S{?j-iBs$Dx$W;}9J6b#=rr4bnV^JRNO#7=GV)zKsaBG%!dGP%o@Y)*+6; z*4k-A47gpPl|4#c{9ym@7|t_Q6+;_QFP=4V3~!cC>xLL+Lt2|C?L)31bK&El&Xf}% zG!E^;JPsY~97CUC`-dZjIgs{Tw7e*0VTma`26bMaV|ZTFi%udAzh(b+3Ng%uwC8P6 z@IEW#0;W1p3SPUtKt|AWIbv!SA82l+Y z?J*zHx<-qGI&VvC6&}M)dmaou9K1aAvTzKkeJ;;O3=1HwM>tAeh#_;~G2CSk)H2yy z&oT6sIfhA{;4EVJ7}9#1qhJt2=0anLtez1dG%xyFIfj8E4x=*W97hZbA+5h73I;J` zE@FYY@XSNShcX4!HZ4#go*F!eOXn zVY(ECuYus87^WLIhL04E;YxZ}?CZqX zAZ@xO3WmJ>sKQ~W8O{@jSrW%EN5tW>!Gu0yK83Vdauf`C`%#6%P{*DJ!#r$Tc=C(1 z&bf}RmqXe-leX)~(i1UJ_+s#wEsyI(c6PWpE!G~v!0zKrTWW8yrH>iGtbnvdp}b(& zdQV1UnHeNta1v9;*2@T;(C!%U|HwKqqa|30TvI#wO&%imt3>3)^d2oEE7UTQdmSom zrBuCGxfsN?64Gq>-lZIuC~E?j$a{_pw+B-I5ezD>r}EHLT%ycTTpxei{nHaOFzUF2Wgx06?TS8YdsM+YUhrPTD}HbbJIvZ=6-njimdq( z9>tYt;T2$eq@Tps6Vn`q(*tIHg#gz;T9Qt?0_2*<)SMOl3yLdfFNkZU^iAzCMG@C$kfvA*fh%u&tm4Ys z?x|Hm3zyH#;!1Jlh!S^F%3mc;g?@DJ4I#jdkcMZ0@^oq+*r@c(Q`A*}c^euPU~dZp zBLXMp|0%$bTrhAyDoal(WDfsxNIPqef=hH(ADp3igG6xUegv-F4o0WAE}9GCx@6Ps zneq?f!jZwxhW|gf@OVoeT)!F$;<{?7IIzesh$|k?y~t5;iM10EuK~=oXxi}f4kHpd znvc2GBYC{=XbqF2@xqQ688qd2X~lt#T3RW6v1ctiRZ=f@2}Twg(Ys-{9xE6x zyeMPphT<;7g;y6CqLi zb+mkF-uY(`*VmB#oDwBo|E}fWIgDQ(SQBzB^-^3f@V+)4kIh%&FmTN}^%#l(w?ld- zlQzJ}K3xKUm$=A&UPdci;KUG%03>IE^9K%_kUj2ZeA*zWHys zMBkU-BIl7caCry%Ya=cPr1!E%iC5l!H7#h7lScmymzZ~;8QQ;KK|65O+#*z&tgr3F z!^F{WT+2kQ1nul$Cei}W(m``qwv7p>M3(^A1 z?Zg&&h`qToq5WnezsW;s20~L0n=sn!5TRW{tLj7K<|s(R^P}vcG>Ong*%=MDxi9#L zV8O%VxoI;Tgf>1bXqc=SQi1ScjPiv~jiVaA)HSo7SQzQ{Q%MpMJ*vgFZ~iSAuS$`wAbdxH2-!*|op1Zk)g5&{t_N|Oj} zA``>X&cgQr*CjMHd{e?qke0qB;X;KkR#~~H=SB=)GNdoCLO*KWeECZ_4W9@Vk((nC z-Dy^)E5i4YEjLXKpQIPG{1;`p^ljH+XqqR(HNx~Dfrrftg9jWH%vc)z4 zj#R^=`-wP!+=sD%BQ*`M?zs@GT!+zuBaa}KM+}hq69IjsK3>LE-vp^=FhX#oK?pxq z*#4A4el^y^kw$h%ZAh&&HNlZ4NJow?2BMrQ9+QB7Gi&=>Rsw-Mm@QFG6;Fy?b%~xT z#?&*(=Oy}b#M8RDPZjrG+|*1@6=N`%WLsH7QYW9SdY+yt#@Iw8)eywuwg?OZq2Z98 zMk2BjvvPy&>ewqXX45`6Qp!xSib#PsnSa!99F3qZ!0$d|Mhwn&jU z=1{*JY0fA&B43Vt5{|G|kvhzu4s z1cG1i9fV(+w!B7Wo%Tlx8o{5M?~aQJr#6kH;i1Jw6t*R=+g{qf!#eM;!tG%4##9~M)V*&3j2Pm%yR(IuY>An_7DvzuT z1(a6>!k%)`JAH~mQblA1QOhhbUrO(A3-9c*kW>X(r%!OXJ$fth6#KFQEP$lwNUT6`S%)# zKZY!;0?H!cYl*JtH%kvgyn?K$4p3qx4r6Kf(LRfYKztUmB=q%(@b#(T+g+VjKzxn~ zytBffVE>TSua$b2^}=+B#}feF`5{nN314x#Ka#2^Lj3p0`a}=P8sTeg_;Ba=Cm{X@ zWUVs8Iy}0<3?@nSZtPwQ@#m1W-VDli6KCykOdA#d6vY3GtawDY)5ux7>?eng4M6-Q z8N6R1Ymb4ml5O)0ue%{0=ZJl=n3dvUDrKKE_EdWe)D_g)j#-(a<5~x--x}ptApQ?z zIZ^AN@O8+3tL&Ev5PuC>-^ifI!k5eT!pt_Y5dVn;Uc3WA@#wihuXMJ4(J2tW9JS7( zmS6Zvv$kyTV;JIBA?pJAN)L0b49ll&UY!c@YmkK~m7~JfG257)qb@`IdSqR9fO1^; zQY2gH=7(TiDG9uH6;Oi0SC+Nch}rufuA3cvIBZn1g|8e-=TYUiLfor1@Rh?DejDO2 zPMYgq7-@mH-V*q#qSk5Q>wC%F>9gJt*WUrYI;eG4`1-+GV)=SI#J!Hb8lqN6_&R4P zU2Dl6h#P{wTA%%8sgScVn>uD<}7ZeWTk}18%(UlPQwiSHsF;JImK)&sWTlJ;7f(L`Bw0D#pAw}bj(*~W$XMd6=aB8WC3qa6J%E5zA~#> zvPW!b0dY&s;O!?vW(@<^s%e{SSp5~O{u>Lx8))zmJ!jRHUYhyQ9$5VkzV$G~nRSJ) zN3E^8^g{3zLg0M|4H|^6`j%3o8gGNR%E%h8gU=I<%%FFg(I1pDy=B{&J>7yLTMsDbCCGsPP=^J&R(`?tE_!4`C-VuQ@a3WJf^#-eN4U*+g3GoIGE>B>hpD-l>Y=!eiO~#v#aj-okBk)i)_QpaQ-1h+I&W`JBvI-IeyH zuY1wUkH`g8ncao?UdFe-(SHeXIap{}%+PUXeR@q2 zxu7cZ%`i9kmZPIS@!qQ0$eN;X)^ugrZ|3$uj^&g4{4%Etty%K9q$4fqT|MNcw@fj3 z%A9MxySOVBhj|jc=`GWw;|Albr?dN(q_+li(?d!3m3>WaO9?Fypo}h0k&Jsk#XVDZDCkfUx|zv z$$*KB8IP6@q2$`DIDD$X{u09>KVC975SNjg5T0|n9{l*8$^65BzcQ~Oucigh>ln$e zzpePe|8Ltk%708l>l;TP$pD$R9FTcWpuBJJ8z&Dz5^CJFK@e?3x)Z@7q1Lt1t3eR^ zl0h&-u(+PHip$HqgI|SUj2%Bl2$oVftF+v2Po3RJvOut87=oB=X0W_HY2hW{v}a5y-~eq+-+ z&maj|uOn-)!VM0!#8*lg0>L2`B!?krv2oUL!@JwQSP8*l1|&NmIKs?XZ-+`KbMGK2 zgdZyeN9j3hbm-RNrB{)JzDA+1v4S?3k7ioNGaH7=jCIoVC#Kb-N~=Ao#HX$&SchW(h71 z(Z9@c`<4O;vn}{5_=y>U%W(eb0{OMoV*@YF^k$~n2ycZAKL$9`g0wNg zI0FP%W7FX>kzd$A2fqqII&GA-D$(?m>rpxxwH*dGB}kXCetTz6gUe(aN>H)}43P zpAW$U5`Od$JR~z#@UZoZO24f_k{SId;M`$kEay($m(qsMAm}zi(1j>{++fgem^QE8 z2S~z}7Srb3EwuK?8|M9nty_8sKUN4HwJ?LhV|tH&)IShBg6MXjKWCV+ocpBxGhLXb z;|hK(5X{muRxnG>sP^915DePU4{D`27|WSzno_sQ5(wsCx^naoJSoz3%F#S*yNe{$ z*sBNUAuHFCb+h)JY7W6Oi0+IIf+21&_@iZi$0Z*j$%K9saJr3L%d2Z&<@cfxJa2&D zPYwuP6zRI8|K6|;>+^*$`mur2FSOF+>Z4ZNf*?*`1TSN{u9%s@;8oq)dv{tu@b?h< zF@rM@W-R9s$vLw_B?#j9F!+ZVg4cD76};}a)omskGH#@b5;C)1Q5C7m#5j!)ORn+{0vD8!~ z8PSgd&J#w)a(=5TdUWf{kX2j{Suu9VDrIJ@tkSv<8%+BRvPxpQGHu{IDYQ<>2ZLW$ zhpe(Pe$0@iH*qa}xXh&vv5-}P_%Va?`!HiU&q`7!UsK4c?7)u+vZ`@bR&{%zWa>a9 zN$3Z)L{>V_nRYebj9RrUkW~}YRY#<&u5G|~fmKK{g7b_Xoae3F*9G0P^~2vmRy{;# z2tif@8)IcPH2K_Dp)mQL?|c5{dD40N-gAF*=46u0;S5ww_9(ju)CJl z+SQa9cZvK}BDdU7rvt`n&X|iUBqh)Y`%hDM_h+4Y)5aN= zM_TS*iwgFJSTV?jilH{WsbXk!Ps93yP%(sU*VGU;&Xi3XpSMh{Y{hmP2iq0)?WlOniHb);s2Jzhn<}2r`rSPy#w8gHf>yB_usp-87d~KsF=V) zCTX(QWJlorkKSUI4I5vwV&fvG-n22z(x&NkKcZr)6%|w1woP;BO%=~tf;-!dLB%ss zww@3+rrY$UjY}<7$H*WmW(3&Xfr{ttdQ-*ovD44x?nT8c)?<+y8#9ew%L3tDfsk#XQ#3;!>J{kJrVie*v$-!dn=TTt4Ize856(AeFEiY)ps zOF_jd_9661KX3D}NDsSgpfkY#%MH+6W1svJ)=?+u1+L z`@Ltu`V)cpOlKAASU>*Wdx7#?A7E3LSy8dk!6P?B+1-h~B9~3oW z_~p+lwz15%si@fDln=sAC4FA^RAwpWV5|tc*_|~XvC5{S zmdN>Q%207wV|PY8W|K{y2Zl^<-j`Vcc6XrSD@8Va6`Hs8?>(r9vh}cc$chujy1sEA z8{OB*EH}Heb)AaIUZ=IqlmD8*EEl_5QSn_!Hl2)39kbYminA)SV+g~pH-!;X4!y)K z-DnB1JG;6#t9N|6!YTf*|E+a5v;6GNu1Q`~ZdbTwp!su^0fcL4>~2H2woD^j*Y)f8 z?SCO$$Hneegso8tY!GVyM$rw-aJ!n`xoY2UjqQ z0h=;li;x7iQa>tvb27p$Rc6N!Rsyo=DyL)2su|33AlxR3@HLujYUfP#wjY6TTN|?j z2(w{LeUq2X<<|DaKOd7enM1KHrmNK+h``Kig{i1eHj|&L*WstrOga=q<(?D(b7cGBdmd5Tjgzq*s zZixEg6gG$w9;`AuhVU@A?B!6KKJ|S$!owA2``JZ2V|vrRJDe-$-gXCF+mp{O6CS~G z5<7l)g#YOmXU<0W0XLhfhK>2(rRq&=s+qoNudp;8cG6Tc;n5DgDg20KSdZ>MB0P!> z0rqoUGVjcQ*z_ZGZBjn(On7Wm_IliXqV@Fo%wiYc9Lm=9fL(9eH^TO(R>FYeS&t{8 z2tR4lo5D{#e(n@75g3Ra{I=}2D^U${UhhF z?4PmH_4~uqjXY*Jh8!QsF0MJ3-R?)PB#RW>JKf*qI$dIMXSc-1bJ@v+5(v-c!PvZiH7F zy;j-sDj%E1EY@oU>y@p_UOBO{e^0ZgZFY>^T?pqYvguWS<=yYMWR{=ZS#=YAf;k8y~YY1;Jwriv9voX8oFw2hcI@YvFmAy9Gmegs%_O?w7 zw#kLPzsU^Qd|Nx6>8I)Hs(ik!@OC4Ofa_?J{p*>YGXp-X1i(jIz#4P6~JyiY;6)JVQeUA()`4a~B$>AKjn zs6k8z?rZ4$toehx=<2h4hOKagMQ;jM_^S;u3I@#TVNL{0;o_475 z{Qk^hO?6q5H6+({wO0Dj$?k|WP?;S=q`g%(wRdO6&KDulPGff)A{}K7Bb^+UTbvO@ zu5~awib!Xd?A68EbL`HMh+J=FHtTt#(bU!6rFoxhX0aw4Yr5Gfd);EGpPu>^BHb*^ zb|Z3|(R5p^PLFTjVis%a&YF5Dve)hY54UM6nB`}8J0f=)O?PTzV?Q@W#Lk-Rtf{ZD z$#-e5jz07=BK=fm#}FB0Z1Ny?>CXD>lKTTScDEriI3U+G)KR+i)SHM5aWFfIh{I^Q z$NuQ()&rTvnufEc`;6otu-K-l_abt?h1qUI9x|F9wmn~x^a`_B6FXIkj8f&gM#sMP z^smRP7`wX=QH>@wdMYq&F(Qw$rbk)R<3{r1v^zGR`i)r{yW0?%Xf#c9e?4Y)D?}!+ zrU|U+DI@vG?jlEn=MkCYV0IJ{ejFj*vm;K|*7rAmhR9SmyDNxH^UJ2`_NF8Eevinr zc4mhVdCu6bSr)JBP%}hkTA0mx&bG;3a{^Dg*p>StvjgnTrf^vr)tlIyj-PZ%J_dfl ze?F&UWS&cJip;ki9=ANkEGxTCv3kk8ij523x{4+gh%9717pt;Yx^=dDdJRO<*p;na z?EZ2{Z(=UEY5wOMIz{h}*6=MV8ybBX4hm$TIfDvJ19LW_~PA|KJyz5P{G9 z7|Ai#<+0B1oP9SU?5%C@4)$X7zEuaZS+Y9K-SI6=xWH%0io9X0>y6k;_PT77UuW0U zu4}zy0+Km%Z|+(S+77$Z`!=WS#$4o?Px*@KJ8ZIeF==bAIlgW{2h^XZfs^J zQB`N;vRR(k2|nQkpOGuF$*lt;AKKMZ{d~+~Jp$HCrb(-H{Igl$lMC=^(jwax*=xJD zsU$cQk!|cv<6CwJ_MJ?A-}m-Kvoq?0PhJq&X+`9dknFYFQG4>uDa=w?kI*HPtKF59 z$tH%_XQRp0BBgfOt2D6RF_q1*aDexST{7>Q!!?LyR<5x->v>3~5vg##FnZ}iX4%=i z3|2OagH;Fa`y)DCd2K!Tp5?`WVW{O*#5_9@(4a# zTZA3o>rcI?RYuD{)vOyo8#bxI{oPQfQ~i=1@HUf)`Z+j`kPf0A8|+~U7v zj<>L0|PQ8H0xftsaL*#d-Oyl=h=UE?iW0nPx-`t4&WmNvJKtb{|a}fD6#O^907i0}1 z7u*AaQ|?FPUya>ap{|qb+UK%F|Mm>0`40FTiWNCgeO;9)$_FRLj6`LM#=f2Ix?~Q; zw&BjHG@k;WL-A0iMfR#=`>Rf2LsZuBv+usMbuD-3O>7Rug)7S0bca?qyDRL4&*;_2 z68mLBZB#a5>v>hVWO~Ko*T((@J|6_1Ua_)HdTc4lIaywk_w-v z`6l@Eik0>4dK#6s=)}_RK0xJ-Dw~SJa>?|Hi+{P-0Y0AvpI))DiL7B|kLZ%tx3VcD zda_=D7`w}+eS7RXhkd|i!RXDt1KQh)N;W_e-`OhfjK$84zaN!-Sa$ogOQu)6wqf_3 zG#>|_Ua|6~nCvw$5Pr8-eN+yzV;?(4tUA5oLF>{Cn(w1>h#!@A*krHap@|cJJ&8(( zgG~j(db0PMcpCe@a&KDk_;cX%iB#Ul3U-%K`4QTi=kI8b$_Ewf``V4l;eNeW<$d<9 zC*5aJIf~V9Bx`!uXd2;q%NCuF%12q#7IVFnKN8DIz9E_~06Ka=U zz*hSV8^U6rb8Nn7|D9nup}ohZ@|e!POWnzCVK-Pdi@|jIhYhF;Qw*Y$W&`QEmt^CL zbz%ePv}9l9?#jM<%-+FUu+QE8bnCO^B>kpN-9Zs-AUhtp`( zDqr%*RPoauwnY~)TaBE3Je5cA0Y|>%ktuc)W=mI(o$PZl9yv$jOCFhQGl^{R>DlgO zJc12-M){IQR#QwOo3|f1^BW$)$4~i^Mg?NlE+M=d4 z4z+B{BiJae#+NMez=fDe-myLo_Co zcKYoN5qU>ckNnwY5?Om?G-aWP?5XIH=MUZKcH#U#@5&8!_AMPviJ9(mHr729jrmmc_%uji!774z7a z9r%)a*DGA{y(>qdrA2(PL3l+J2lh(S)1|Muw02a!9_Kd++(VIU7>O?#v9yQNB(nAA zQ+DhTkuSO8kq6lMO?>aTh}o*exUC)$IV%*8EM=b=TprnS)42D5(1e<8u+S z#m<)PPYdQGnP+>=gxP#^Q{`(BInJ&#+qq35o4s+zR}DnuNL7z)YgVPEA5LjFR7BqA z*CVentJ0Nk+V`-RboOYlVN^ZxYSm=zP3Bsf-zXycTlL7R943)heDB--hluR0=#h%u zB(gEaT|*V;!_0bQ8=FaFqoL<}wG_-71A1g@#U!%f)h&mP5RsjT&G(R2R+GpE-n8ng zL}Xh+onyoNdSvsMNo4&!C%-!@m`z-IWV5JAWWDO+zrI^U)|YuU z4VgsNeRsk310s@rYQ}DSi>?fqMAli6`Ba{W6vtOQl06$Q-=f+lONP8lk?d<6e90rP z&`ct0Em^SOXA${}TaRq)Hi@ix{pNo0NcM`!Zk*Z3WfEB<$6op;kKkW((IXo=O(Lt; z{-x2KA~I^%BO9nDk*VKy{zGg#`{6i2Q^vXxr;5CXq=~()M%{k=taRwF4%R7;yCq@#Dk~RGnE{Gl{g+ z3D=JwEBXELNE%S5^{_#8y>~A+SNz$&LgP#J2+;sK*Iqw>Lu}$?8z5amC()XgHiS z8xoIuyT5YjkHGHNo%*_Kgp(H>rwBHz%9p%ihXW>&)#o6nb^~eo&lgO0bz6<>X)2crxtA$J=tCimI&>|6Ok#+ya zEYGAfUDi*cNH#1VXYT$`GhyQ1jvq}Fkx{=Mc|bLZw7mNF)YT&LuojP`p=t8i@U-s5 ztX#22iw#TjCEuf?3Rm3guJI-J_z*O|A>1p#mlWsZihFlD_>z08TK0EbwO&N_4d{`X zQ9W}1p^&~8R!ec*)KWxFl#vD{xx=Zna(R0X!}d-Keg=(l37cvWYE*}Mmj zRP82fx6EA-@CoJv?sy~(KMQY)8u#{Wk~Q8PR%GtC`i5CWM!VUeUi@9|qDTzAzwt2@g3$mx1L4xCW*$OB&)HGX<* z_vb`pu0PH^@U_(>GO6_6?dc*iJEli|@Wo(?WTO^*$+rDK1zW_=j*Q6GSLLo-AR_5Sks=SqOd?x_SADljL_TZh zOU?{MO(I+N?|$SP5joYZN0x_7B3rbM{@6}LPSEtoV8A4@`N6cur;Er(Wj)zfRxjV8 zW|Nx^t0y8K;tR@?y{cax*|e>a|A~lnIP}N^Zj;C>Uu%6~5^0@$^Vk9&!AE-a$d9cik@b6e z*((!|WFyIX6+9a*o9U{_rKl)TPiA?If;FA;)xlA%EEhdpzQ*ZEj5t%0QeBY?NQBTWl zY2EJ;k@Kv4$sf)4qLTTRRX-A_{cy>Z(?#UJnjX0}WD;3xe{N+n5&5Ugvp8T9Su>|s z=Tjo`cfO#t`}`)6HC*qn4e$s)Ldcgq&mzqvvijbe)5I|p8-dg#3*9D>sa5~MRQZyx{avR?Wb$FV65m4(%RJvvO(Lt6x9qo-v-k)wUvlQ# z4wJ~FM^2qv%Om&*vmVLzKmGY`JVy9)+k^4P=o3{&hD;(Y4Lgp1lt=Ipay>HNE+cc~ zkyY)H@82ViAKAc{9_h82MAo`)Ts1mz)USRS$*!<)M61i$gW4eZdA#LOf8$%h#@$$k5i9)Eo#C{xoOp~ zwj#2psz<(R)YD)l?;P{jei3=2jLZ#~FsoJW{^e5<+1#x&SNlyOlXk?s|BA>)E8ej6tXDeLsdOV@}Nu{N9?;rDLH$n!Jaj`4tsb~wxaazm^qvM z!dK@Q>?u**Bla+Z?Fh)c?R6@wjQtTxhb3ayRCSKQp5)R!V&Chapcl2-{$}Syn4x8DX(!hS+5B;@$j;|ex5#LC(COGO2;|P^J2d} z|6k?BE>CuGT*7*>Yf$KMl-E<5%jc^!OB z(Rq~Db9Q}~EqyMajvdNQ7*jq*>2#}knJU)F?*C&tX1moTuPU@#Rb)vXr87snD4qJX zu4eB=DZ5bmyv;lv_M2dRYyO*b(j7XF(s2bYN@w5?-yCA;e1g&!FL^@iJ9mXoZq0v_ z&a$dI5gVA}-;80eFQtq8S9)r(jZfK)()l6t>abs)=v(tYrt`nucPh5Hbskk`vGH76 zYL$7Vg&ZvFlszb2>^INr;2<5tKMEGF0SE1}^4z1>rvGhT?3VyKkn&o_-u_rR{IzMh z{#;w+f6F>J#PZsU(q*m$c@1&toc|`Tw^f}-d94b`ymDf)UJs3%e}Uz-52aa-1bGdQ z>YV>3ueDa4M|r(!)awo7ah$yAzEqaiew4nNs9yKkbSud_4dlv0$wV^5IRNc(@AR|8e& zQN4Vc%+>tbvS2;>QOjNIN>VI3WUVfcNd2O@HdhJkU zz4DG0A7OcgP`W))y(R>7&VN&{eyYx+ymlGKqI+C2ul9FuVV~Zn97O4^Sc1oKlH~k1 zc@1$?$!otu)~n2@*Ob7bVwTq-l+0%X-ytzi@!% zRe{n_qW8yXiVpg3@){M>dGt6|8udD2)N9R@dt5B9FiI;E)oTU|5V!v(ug5i=M|mAH z>h+~jug728QJv)#LFutX^_mscIsZ*wldA4t$DMNj`bK}9crGwnJ^M7vs}iNhV+r>A zmnFx@iwz0KZ`|9huyZT3+!E!vAm9= z^e<>^QnCS${r07f7$uvV`UJ8EbbX$ZKgx=lnN$ z)p6-O%B#9n=2h1v>*Wgfxrya<3}w~b3G!O`AJ?m~yGma1??mx>H44eRj{d!veFB*B zIm)b|1bOBD$MtHdR>`Z0ChOHKD)TznDT{@re1Wnnl>~X^`E|~J^EkG(={$NI+qv}9 z*|PSQ#}_@z21Zi8L|NNQUbfgLhglliAKA||^zJ;Jl>zRFPdm9!$PNLysn^C|su{a) z_r?6oJ&Ll9_NtqzvoHC`ORyi+S0~t=Y?4jaYiFn7jNQe#?hnTP3T2%yDdYdh9#xgy z#n`29bc%%;FE z`)icl6ivV$DmeyQe1gyU#O@Z7HMz~mJ8j;|#~Awr%5DuLVE1?EIT~#7nZIP;X5@Xl zk@xIhPVkQyzd>2gM0xjiUCtJx1d@Hbk@uZ8S(BH7OZi*+NtE?Yly`UMN9o!@KP?>jWUxPjD#J6=B`wYs4 zC(65KfHU~bV2kk)?s0Z$Ux&>534>i8E&q_Qze5@O@w54JCn>}k{ARFIH2y!oQQl9; zyvrsU^}g0#$PZ=CqHIEfyv<%u*v}XVth1jq>ODCmAIpa~{mDRvZ;3SnwYZLX?pxd>}QO;ryF@c?VLY@v42F_vkCHMKN;0I zvflBLVD1xphLQIyzpTjs>#JWeb_``R6XeZ)#CkdVtV{QZ{k%=?Cv)AB-EGQ)Z1+w1 z31xE>^O{7yw&@%rZ!y};ePX|0m28(&vJV}9qAO#cL)lA~1Z?Bb*gyx6D<;_s zjJzAn9W|b@e@5B7XaY7n&x_v-wiwaoHnA5Pd8Zk9pI@<*pF;eCvR4x2U9QE^#&aif z$gX?DPBZde>X0?D51hr{8-7JudZN7dnbiA0s0y1MVd{sbZkuE`{i6LFjQtzRG6M-} zveTt=jGBC+>K^6o_Dl9Et7O|I*T0sre@EF0EdhJ0j=88NVq~5-5IZX>*`D|*2z#Gj zF)o9@@0>?jwmkuRgI|Xmd2dp5kJzh?dcPWzdGEactAULD2g-6C3E1yRj=^5%uEKsj zAoG4RAlcJruegP=|3ujvN&@z~@^LfRMfNJ}Jhx=$yCr*F((79o`!AH`#S*Zq9-h)M z8@mQV74}=IWWS?I_U#R8ZD#DhQTA4%{iNz4xnRF8w}tAx#wOWCPRaJPe_=Rd|AVqM zmz;*^$83?Rry+tZzBj~kCw8%2vfr~y_MY=8IgI@;%8C>1gH=zx1bbQ4yw_PJd%dxL zTXxm2#n=~6w$7QL-c?UG1)Dv|<2TB?Br4e(qcZQjS+}rLvs4SpHYD1=tDa&D_B?A9 z_9kOL*{n(S_}uBE85=0u6f)1-^gV5MpbC4dL*~8BV81$U)|HH%gtDy(9!pd9OdTyA z%Yeb&smi>|cdlgT4XM>o7WlugpSA07s`oDAvD~dlc5=Fv9c!j0qimPMye910E;`3} zUQTuE9N#;$*JIa_>Znft^pH|l-RV0T`zj~#2KR!3QRf_k$n^5{1s?}v0tuqzC9M3pt! zfAbHg7`q0_DiX1ckE{*$CFfF~T4ha+D3V<`;*R$iyC%v$btI@sKUGiCU=P%Ek7{x> zB-zKJlKpb)QEdBCYoY8jYXY`0G-0sq{wnM*+>#wN>V52~Z8pZPjj}I73E16q%th~) zw@HukK5o?egux!)aQbq_u7k4UiRx_(K^b}9Xw~7wK54K|sj?c`miPe&{}`3*+Z(sYW9<4U z`@x!kUDK&^40c`V5&I{%WdCf`d)jmPd>^!;?59uyHUgKkQ=~`iUyXYIZm^gAUH2Gc zH$d61|A%_VzuC^$N$fui_Ft;3NsHZ&ZfER_#a2$6;O*v;Bl!5studc98u5EPfmtOo~eO)ctF1jNKSPSk2kt7z+?L`B<_G(diz~ zJDBX2>{O%Pw{L#?S;oGCwTBY0PfL!$KFc;%+=yL6);n0sV4wNzsUeKr1i=~!>dmg% zr*jPUHv!!vb{&IVPc>@d+Hf6XUx{FyMC{LXjPZKHE+43y#I{;xO&Tha{qW7rDjB;e zf>uX@np8@Tk@w+f6?UVLWM2`L?4OSwy_d0@A=ucOfE`kFj=>hcG~hnveWhEnn;G?< z(IwQMv6~}!WheoApZjulsa^Mo-NLAMD}(Ks_ZbUIZGm8mMD_kya*Vt`@mFEDG1ynB zvL^j1!)(o|EfH*!h`lwYa}4%&Rre_GYpk*+?G(wbc{h8?TT)vgc#XrnCZ^BJO>%w2 zZXc5Dj#0_B_V3S9NNtT^2dg=oT_{w~(a3v)UH6FH$t~HPjd~x|=6%H2Z4m4fO29V0 zPGqnPSwiAQ>@G&VZ3g>Hy{FiDajJq~mqhh`!>Mx&wpV(@?rN}aR%K1xxhed)a}|PJ z6R=I|o$J@vN9r}?R8o^r}<~1>8XUD3rZwpCw&!}X#Z{MQ>V_$<{ z534zwUCdU$88umH*FDPncDH2rHtHRHb&kQF?b1EUdq_yKheaj($=LMQ8M`BbL#+we&zP{MJFBoA z&WnblQ1WFPhP)O*hd%*wvZi-8(w(B}9;JJqU#2_4BGc`6Joi?{?u6idu>|b#4xMAL zCkAwn*bf@)hXazmSzXLN+DN?)!3PtuAC(+~J+^8oMmc5PkGLdzO81Y87`roqqY~BR zVaYMrqoP&ve$*z}kJ%-A;AZ{_KmJo)Y)rDBFzQ{a&NZVL zy9d^yixBb4K{lH(t@#XKyZA5dLQ)J^c;=62dlbA?57O&>=Dqr8^~VL zBjhZ{MacQ*pS_YHZ$@yII{~trdO5PYrh9~($oO^FOhU|vmoLB;+Eu?ohvg|57 zLcSQf2>Ef>pL#RoEeO73O@QodzZ}^mpnHU5AE4=H7Yh_w)aMsne+^^bir_p)0(M)Q z&N0&MsOlcE7ltJJm8fJtacoXc#_o>bqC|POlpKT2Po>0-*o)ngy~JSG=~KuK?NV<; zaB(O>-o_U)40cmj6?TTfUZ%;sub8&m%h){-%t*wpBRK}!>a4LWalW7oj&Y^n;E+of|q`IT>rG0&Dx=J3^qIMjNgdu z2}yRYQSYQqt41>R?Fg<;@K~~WM0Ad1$FEevePX|6)cXyCtz}l@pCaCY;A;u$&1N>a zoE?>QBDQ9*y_&2^+Vn1q8M`-vS|WDXB=5tTzCL0X$k(CZ8fTV$-UNoUBUs=xe+c83 zvEc}#6y??`$U^xHXUIigJp2kn-icsQqUx4vdUpf4H>7)%Ofdt5R zFGt2N1jVU@+!ehD`Sh5@br^CWf}bb}kooeVFlzah^a#1vauL$GYu-VI9E9LrdjjN} zE}jj)8OS`RaN=2(1};JlU;EY_40$(#2V4n|xdFYqfqY%J#D)hQ7a>#U9{HOg2O}7C zCqQN?dVd4yshZ{2?u(FDPpk1RLk>akc%o=LxDGBnP5zsjXdsayIi2buB z*}od>KM%KfpRw;j@aJd(_Ef9RG1$*Ub&uG;8|**)GVkTP{}{m7_agXvBKAa8=NRls zRqOqiD)auwDcOBGw(iB)_aXR~mLTuPoR_o5*>#WdzM$yra@Zt$V%N>P8T)<&FQ^IF z54v@Zk@rYd_c*&eDJt2?M!latzIQZZKY;RTN&>b+(>Vs4oifL7#7>p>&Z&BX%u=UB@qLk~y~dAjWJ!02WWlgM3 z$$oaz1^%JaLnyDOC8$X+ht4tBy%pUfc0)z78`~uN_2wUsXY7Yj-cU`z?xyJ+gWcV! zd&IsXD%n>W^)48fpTpQAQQkyJ!0zJLIR^X2fbJ2ynNjZ+2K)7~yALz=D3r6grA!BX zD>~|!i{4W@g>;kHtqgV>zpRPxj@lnG_Gpy1O2od(p>vG9+bX(8?5k8+lWUxkz4+)R z);0AJlwYMK$h*0!a}0JXo9+?2og&#CY?7U{V9pbaJqG3N)CBBCew|~mo49n3*d3#i z-N~r;!`hrpjQuFeuT>JT>jZR;!LA?DJz{q@>fOa){~Wx3He;(O@0_UKsaBn1uxmth zkJvVY-PJE^lJnF;z7IZza$5p6n;ci?80@5~^}bn^HMzwp*+Ti zdl@@^fmiNR-rW_+?qQSc{6ialX6(mN-d#<={wZ)d`xm$F5xZwpvTrx)y=r6wc0`^! z4&}X+1ne^*og-_)<}%hjV)xc0`%Z)X;;=jKV(ceS-aApfPbfOaV4sZX9Yl=n@<{@kSAQF|5k09EEa$SK*QGM&vBdjiS_XbEak>C!ny-bWm|M|lrc zBzve$vTGkczlO0VqI|HLfL(4@^G9ywu4kAE_m%Ns0S%_6Mr&(PKGAk!;l_*_Pm!S2On0C?BIH zU>65;j*++DuY1IPOrFcIv)8%zk90ER6qJv(BtRCKq-%W8O33jSBS#)}@>9*JD1XA9 z0GXrc85vowl&c}+#EVal)}A@XpV&^6PfT!nbZD95GGzQZ^V}!oBFGI#JXD^Xc{PJ;f2IS*(;PC29#-4`qDKT?)#eDTLc6?G1$)4tv?CCDa zeqU2>V(e#8J}p7sY?9{7+4EK1qf$I)lk8aryQrV-N5-Cx^5>ih@}3dUImRRRlBRpa zo^7z_+GXB(v)*}&v1g!sb|SXPxlDYj6V5003o)6u%OcsgYyVVd?B`JaqAfw*Cg(DT zW=5;z{jy)O=LaPF%58(5XY83Me>s+bZE`LXpH4;Qz0fJyuNd|I)jzm5W6whQLVp6b z$+=8?0v5?$Y}9*+!Ty6!#BE7^9_5P@)!XD;CO&10WM>%cWp-JUmRCE=7<)F#GZL{) z&Sm10yhye?CTp_NBH2f$oZrUSb5OqAmY^mk=Q8nWVI+H%U$V0UlKsrq&-nY*T$Hbh zC19JJ%N%-4;aq;BebD2S>|CSXpGJRZ$k;ES+~ZHc?xqoh{V|?9kEpsw?AMHXzhSVu zt?jynv0p^_Yl-S@axN2}tcLT6tr={uUDjmGEhknp_Dd+&60uFrWez={RmnR)CTsGx zMY7vj?mNfWE|eG864b=xTqZstj?DWVzhtioNcLC#V@DYKWt6`YOTccf>Ny(q9;WCX z)uhNN*~Lb^zjv)X$=LHyUgS@}HaVAxPrAeT#D34H_d0`pPaO|CMoFEI^7j(e+vHs4 zP=BpT-s=ta2D_}uuJE~qjJ*Km>l3j}&Sl~g`^daE#$-)Cv`Du7sifx^dm+j{u$kAy z>|Ey19nmUzZ}v;})_`RHxb&fG8G8}RH^&mN&CX?dDplCqoRS?d>ODC2O)tiN1?AiP z3D{=mGPkN#*z8a&E$JoDbsLI|KlX;g~BzxoZdtPPibd>M6C8&wnxy*G@eSNflm-!{TJRsSd z26pVq*h^4e7E8c3JD2IGRAC=TPx|qi9vwM-297c3G31C#KJ3>`as&NyIigmuXp*eJmzx@})(x2Pog3 zVC-cm|J;_KCT8a{O`}!vW}}q){(U?k*?XsSoWR&_lt*I;*k%rm zpnJsrL6v#O;^%jaJ*?#As~LMG%74(z^Nvp=$XSwo(IrHQ&E6K{gOUu{a@evq47m#B z=MtPS#pgw=ioE3GmS2^Nkn=sYKV!%&lwW#<5Pgt6KK)`9L+qsLA#J!&^^tb3Xtg43 zM2uP+AZ;WGOGBiM36X4sw8x^P8Y69jO6m%vJ>@6W1ZhqisVk8-Um?{LX=xg%W=LBi z;+i9Ed6c{sNLv*n)e>nQ;k82AYYy^SBkfH$sWwQ(xl}g{bu! zr1?c$TcoWQt?iJuQM7hJ+Tj4j-GH>uG*ULCeIep*MA}zQ^134JgoD&gNIONsax2n) zR!DZo;-HA@fyME!7WBm86IN=y9g9zk9(Q2zcTtjdEI#KV)d!3Ju#xJE#eWORT}ZEH zC$B%!QyruRAibvG4Mcif(PI$O>&K||ZlpIRVHu3{CION|kls=yH5BP>gc^qQwr=u< zBfW!zlmqFVU8L?o`VDqc_aeQULh3%G-x?)#Khk@tq#i(eZx^W%Nbln$^&ryk(nvjo z^nqd>4a+jZ!3rid}QZHl4{X#9kl1BsNEyR*>BrIuIGR01EF_ugdYAKeyXeBQL zOXdmX#*(FO@|I)CZyKqUSn{u(R2G&d+emq^w62p>E|xZNka`_U6+5Xnu=EuHJRg=050F}mr4Iz4kDw%O5P!49JZ6H zK*nc6g^>}Bk{3b7*BYrxWSmk+eTt0l?4%AO;|C|HBgptkC3O@Tzle2whK%3sH)ECIKh`2A28Gk09LS}r#<}@;u0L7g_W?O~ScgSq-Cv_H?*OIV&kId`b zB!58W^&wI}BGYCg^#?NFkCFNtnOikd{~&X_pVS3p?zVD;BxD|Rk*bEwaEMe2GLHsG zRY#_Hy+RFSp5T@RHIezP=vy0^-wUrUGJm#FYdvKCW+zo2nSVG)H9+PC;Wfgt6eoFC zU{$_CstH!T&4mS5V%0{KR5PsF>L=A4tG0(owZy8hom4AiH4^03$huDO+92x&(L+Jj z&7$=xWZi0`9#ko8KG)Gf$L50JVQS<6&X-I2AzMd~(W$Z)6omN!gL*50JVOSsPSReUP=uMXE2dJ`$=QvH~i3cOmN& zE-dJeti2kk0mv$Kks64skV0w@vcdsUcOy%@uVOH=j;Z7gLDrX1QbUn-JV0s~vQDa` zh9m2=M#_P#vr$s_ApSCrdy#ccc=sXe*8sKNkF4_=sRxktSCrHUWL@CGf(Ma}D5-~# zog5(bFtTf^q(&mUE*BPzLbf$ZYBaJNyGT8P>}Cq7G01Ku)T782&swO+ZfmF3$B^AY zw2nn~rvQ16BfAS17K}sojdoH`Ap2&O)OcjyD!d8E?xB!35!ttMVZoEgw%bWPh3vj6 zsY%H0ZznYw*@F~PPa}JXN@@zShucX_MfSbIb0Yfzjl5@&{g8{)v&eqTPii`{$BDgo z2C^pz?>S^Y<)+q|$bQ;MY8JAc4pPq}`&r@5M)q^Un}h7kO=UPSh>5UH1t z{iUCj3)#orq+Uk$H%?OXkbTNQYCf{R6W#)3{~)}D$o|Pjt&5QTiler<+)$nq;?_asPH~P&N1QbM$VTZ zYTbjJ<9R6o}>_|3V2e47lx;X@FMWE5MCubt%dg~JXiUt$6MT5CMBMlA zJSO6PfM=YD`w^ZAHj0bE^OTj;Pw-3*kva#@R6nVo;h84let~DY@P377c7R%cgXe`P zso&vo3GX~S^ELARfM=0H>Q8tUb78?>@GJ?C`Wv21JE?!*S+0=!7oL?GsSEIAlb2+H zXSJPsNr30o0I4K+-msIZ22Y+sDjA-9jZ_LeZ>ywI;Suj;N!8&g3XoR=p0##THQ`yO zkg5gG`Y5T|@QCA$q&o0y5?)<+wy4xv51wsyQuX24!G$Hs3eU$bQVrnQt&(a8&)z7h zM(`XEUSoKIF7mE`=O7oBq$coGxJX?IPo+w#DLjXxq?*Aa&M%Xi!}EoUycY0$#f2rQ zB|KldNVS6Jq)MtaJf{^>ZQ%J%Bc;IegYd3`CnmhB;W-zg)@$JT)lI4`Jm;;X+F{un zeo`H<>@DGS#Iofv@;YJJcS2og)XDmBpqt@%OtecZm7c6_mMd}7DvumVmSTfRypZo=w5Zc;a6^<9F}4XXzVbqiLDL z9#}oXO_ZKkEuIxgy|8+;mAu=rdW`6M2Ub5O;(BBCIHBxVJ;6b7cVe}8RwUhx)$@cm z7^@cuH3X{{i5|nTI%=aH4y^v#PU=3aKI}uZxkIfZUse_at(=3vUu~dpoFg3f^>y)~R@N zo}J4iC*EAag(Ybk-puindKPcy+DOg7n`^nSBt3^WzZYsIv}6~TNwc8UP)I!wt&UK$ zq198#n**((P;;R**2sGSTGJ@07ooLKNWBEDjZiLVSE=N^46U6|^PqKzk~bgPbwVwG z)K$nDSJ8K&X;JdlK+AWLDunhn7nY!E!lR0*_zMy(s5eJs>Q zXnTbE0NMfGXi3@xEhyB7&_Yr2HbbjWNNs^uDb!YIhXdq&1nmnqscq1{vXa^k?P~|A z0JLvJ>keq&hRE9q?TnMu$I#BkNbQ35qm9%j(0&rFyP^GJC2tS3-yEd&LOUNKwGY}~ zB5pslfBfW?A}>WFRffFy^C*bCS}J+v$g3k-L&&QaCGQ~e8YrX=A+M1}ssedeL`j8_ z*Hj@DL0)r})ThXsE!KM&d2_{jk09^G7_}Zn-pe*ppCNC)h&zV7g`)Ly!?agz5F@;-`jRV^8LziXsYkoQNFR4VfRR!CJx-oGlT8t_^) zQZ?bNrjV)yZ;DE)HoVm}Qgz_186{O0Uhx`MtscDfL~DI`t)kTmZzF}`8o+ynN~$5e zS8Ajh!P{IR)fnEEDyb{rZLN`N0yR>Z)cTM zOL)6zq*}pyqe7}Ryf>+&+Q8dQBc;H5Yn0Sg@ZRnqbv3-=J+#_2@bqO~2o z{oUlXhj(CzR0ntmi`I_t4i&A}!aH2Fc7pd_E5%(0@BJdKGrS{2>-F$HELyw3J4&?P z0PiDi>S2TTQ4x0|ykkXcS9r&X)|=oRFIsPg_em@D=mzg35qAr`Pm9)D;dP4E?(j|% zt+&BD-Az4u!26tt>k04kqO}*ib42Uy@V+2g?||23r5?TEohRb#@GcOocf$LMXzc^< zV$s?c-X(78(GT8?D5<;Pb!(*h!@ELw1K`b4$QuZ6j!J3}ysI@*cf$8)(7v8lBsr%sdtEBFScfIf) zfOmsN-UxU8x)=jZ%8BWF?cJ4Hx}NAO5Wq}9v0p>c#mr2Jpu3M!W$3om%^I>?^jW3oe1v< z;XMiOw+eYr!FyUIH3{DDqNFCn`-AYFhBqd>De(R*ys7a1Dm*8==M@XPReJ{BKQ&U* z;QdD>^(?#>gf|`eNeX#0kl#2;>N(_JDZH7;ZzjB1$d5nIpGSUc;mt<=RjP&Es?9Sk>5@w^#bxc2=7JYzRN93H5YOVqNH9%ZeD=YeB{njNi9I`3_GcX$ekqizeUJh z9wqM;e}$jCEaYc7No6D7Va9&TBxm15047pWlD922eOC~P5A2!-*S52ElE zC&e8?VGp4yP}s{)UKoXTp&}^k6C3cNB&93H2EY zN7%?ahQg6TeU8G>PV&A$p(@muC>-l2FN(tPF;ZWl@JSn~<0yREP3mhDP7RSdfx>4+ z>o+Kz=_KzY3ZM6r`WA&R2z3gDFU80^jlx$HQfE-OSR?fv3NwT{i^645^1esmN}+y0 zVYWivk0{JlNySk3nnvm;6ly}9L!mcH-p?p}Tc}@9xJD)KR}>ZpNd1OFO3G60cNCUz z%Tnz;3O^9)4-{^;llLbIKN9LM6z&k}Zxrs*sP!Kd?h)!=6z+GCcL9Z^0j`oQC@dEW zC_JQ+mxRIy7nbB|DE!n#Dj9`G0;E#FFXPQ_$*Cy(!cM9>3Zqd{HBk7qN~$IbztKq5 zLgBYjQngViUK5k+pzsIb)kWbsg<9*O@K>Sgqwo)*tSJ23MXe1`ctNO!C`wYvYlNa? zjZ|Y4iKC_DD^OI+PF@of)rpe25=He@QcY3RKqJ)*MUA4Qnxm+RLaGIdng&R_wi>CcP}D&obv25v4UoD9MV+~@B)3D+O|)Mnw?~n9 z9wm1`QFnTPlRKiQhiJVPMdH(ir61 zVRlke;B&Z0O@;5?04XPY4{%{geg?h=U8JVL_i%vJv+#}P!je24zA<)EGvHHQ zq@IKCaV{*$GvRx}PHGl>6I`U8hwsS%soC&N=E9OZ2fisTQgh*R21vaC-?Lm;l3#>x zhMm+)@Xd6Qa=|y73rq6L@XfW8ng^dadrzJZpDRG#0{G^0VM$&H-$ECuMew~6AoU7- z>0DTn)8JcbC$$*9Oc$wi_?B~FNnQfqN;|2g@MXD3Wx$scAe9MUE*F;MW$?Y`BISnf zjR2|T@a1t~NnQb8zMa%c_}+4nS_R*`Tv(E`;48F~%7)M9B9#N*+5jmJeCxQdB(H{V zy^B;Xd>aC!UWIQH7nbDL;M;5`^*Vf8-K5@tZ@buc--K_6@HF^74pD0!e7miryzuQ6 zaryA=cam2CU#XweTkw_JNWBf;LE*gvUqy_(cj2pal3D}bVbNL$-%-(81mCd`wff-u z(n_irzORJ07QPb>^4^2*q??oHvywu#+l9@r}YOL-EbrvLpvle2ehPQQSR1UI@iKg?A9e z@mGsOD2~5cRG_#o53?kPQQR*|DuUtxTv(DTQ9Lk8>QfZIu8}%|;$l0gqbPpQMd}!e z*GEZxj^d3%eSzW+HS)eh@m7^o6vf*WQeUBXN0iiY6n`STuTi{5cqdRS-s6+ML2;Sg z!fweYQ4m&1eTy|~qNGlt;Gmtl&p%9*9RpY zq57iaRh7JcD0x$;yHFzbu$2BNc}t_#0VsJVN@^fVdlx%mA8jg}30a6Z>d?M66DA_C2y(lT=jh2-AP*N_`{V1sr>H(Bg zs$8awK*(6hf(sCP$N-tLLqMyN=^nyjYi37JE=!d@|}y+7?gY; zAoVCpVq92KRFs_4NIiyT#6(p^+Mgl7EDH0vjwsjmL&+QEHul4XHv+ z#D-czJ&6tV?9}=cHZ%}w5;ine$eWA}O;l1(V?#5creH%$Zdp>MVnb_>1{IyQ82k(z-G*K=V>c@7(Hu#=jJ4dN9zWfnI4zn1Pk-pToo zk8lj(r$<6O{)M-dm=t?M3R@rr(bFC}W zt{rVj>)N$LbaSbY+%z}c>gKn-Kc~N*kJsn>{cex!_RLx52iTrO;=&j;5sChO>M0}! z#HmS0g!os~YAzCvG!=;^Y4ecS5ahadk@!xg^O4vj)Ax{YW%@o6TO(Ze0TSC~-2x<< z@4pL?_*teOK|4?7x<%0Xy41(e`YF_6Xcwu}5@`Kh>Jw;}2B=7uq40`X0I`Ky8KILZP-nZ|PFop;rZ{AE0{`>PP5pRO%<_?ObXH zbiYFV4EQCrB z73weOXQ2Z^b6sj5^u7UVKlBR}>Hzc$Rq7w;7rWF!=mQk$ z5cH5r9fm&8rH(+qB2ZEJU*XWNR470n>QXJB4-ZgBK_8(|Eun{1sulF>T&gwn8x^Vw z`pqg;4Sl3bd7;Z=d--1!(B-kc{QdvBBGb0e?+I{SJLvZ*)X~uISE*y5Kj2b+=wlSB zJ@m0Ebu9FVOC1M&e1PfzT^{+%-({{(kZC9A6J^>N`Xq(xxwC+&FX&r9nD z{iT4X{HOeF)Ow9Vod~^FrA~rAHA6zZ&B7?iBhLPpHV^O8;bRrA*u)TH>1?4 z(C1W8`L165?GSZ3^tl15C-iv=)eHK3mpTLb2P)MY`a)@ELSLk?odtcdv_8<|0k*TD zFOzl-^n}6|gs!X9zn~id>Rjk6q@4%-Gim2T|6E#M=$5p9LvK_(%yq-8m6vAeK%>>p<$BfCN#WK;`C-Tyk0@&>wFsClr|C#i{fmf z(6A*$-GPQ*gOq}XzXH_VXgHuy_rieaKQOBEY!ATb5TYJ}(M`^K7)B3;Z5)i=vhEQW z=la>k!?;lNIE;{J0*oueoIVL-gy<<4H^$hWhH-m|iozHz)5$Q##o1nfF(E*`1ml?$ zRRiNiQ7w#Vl~noVF{Ak&PzPhS$~GM}zf@59Ri`PxtJEu~eZ^0`iYdG0(q_TP1=(i9 zSR0_`z{soATc|ldM7@ogQl5GTH3MXa3gi12+dLTCMeoA+NoAXlDL;m(_h9_0Q17Fr zPl@^f#@{Nn0LH!$wGhUEJoOQh9+z5#WXmY^F_Nui8b`82jBP2BokP?zB)iJV%aJ@G z%JwOeC;O=clHDutwAPS3P1fm1_R6!>BYCDuH6VFTj53fM7@?9#Ug4)!AUQ;#OeC+W zz|(pql2@zLXGn%a)aRJ`K$u#Em(M9tY1G~-=UJ$|BgmFP?Oif$MD2Z|FHrkHoYU2) zeK#-QO_70ctnQn?!qHj#Sw8!W<>q2UAhm_QRBSC#?^_935c$2j&>j zL73wdwnH$-iw?tlLS;JwbD~>Ol?UcC0jdSe7h}{>Fl%^CtGqDZEwTAvz8|I9z+C93 z+M@0Pm1+m`6NNe&=BFX*7?=%V%8zN&rL~8dQrV7$nT}G&!EBV)0cKWON0?tKoOXh_ zE<|;PX$Pn-Fdey8C&1hsXFCyf=fI~F*EAUkHMqOJ!btdYLcB!*a*IuqwAJlb- zvYm~(&SC0eOpD~H{#Yru*s4n~{e=?S0L;8ip)SM9H7+#}Gv>;45N3^$y_aLwxCp0L zVAi8yYA|L!ChM-mtO+r;A(%BWNDalTNqK4vKD#?bJ&e!f9$GaP>Ji!d2tFGxD*s<$ zPY1YeJm!BOr<6Y5?#2{){wUqRO9=&q%c(^%hcI(c4(O zG{yD~7M&fU<{{NFPrZu|KTc8e%Rk>JQSV`KL8k9xu@h(e0E>$;Y5^8EMW}^X{B@Z6 z5R1PFQfrYuTGoAqbmutRI;49`TaWa4E}MFXkFUn6~^sQk{MTafKr zq{pVH?~s190#DUOBnHWJ6Vek>Y@3l7T%xuh{d94pkCRevBMp8!_>CGXwLrBDe)M2EzE7TDrX0TOz zklvZ9v}z#nMu}>HbjhWTLSjywYKipT5Y-Baxe=;0(uWkP3W@o0UNx+vqHJCy7D)5K z^15tokoc%XwT0!cz*F50i6wFBXjq*T>KG)JMJPWkdH$_#kA&Oke4O0PF!}3&jSl3EB71qr$w$oval4&nk_sX<4tOsR!7OY47T=zN}+n1=BXzU>C z-b7>9JlkwE%Bzg(IcPksl04P((J)oC5N0sQ_Awe>lv5UCbuqxU6sr&Tsb$C_LVb#C zbp@Vk4cVim)g#+6z-A!ZEk>L+Bk$h!T=^$fH9gWOpm z>L8Nd6mN24PLN0ChRmbPrKi zV9lu!YB1KEu2NTGO|LvP1o@UBYAB|?BiCgZ>W){~u0q|S3OwH7SiMr-T?^~gFm)ZQH$~UOdPj5vtoLNcjmXr*x$Y)dA4$6z)-q|gz{=%0 z9SO^pb}OuJrQHT=tF+r;?UXhO)}PYufVE%c-aC;&ic*mAO1lf0_R{V~rmM7jkU1sl zDgW`_i_96)?nCBZ(*A=?KRNk+WI{2n8;#762=xFmVQCK{bBnZxkdaqG-Z9AhH_mkr zBNLT%V_`j8VjBnRMVE@en(n6_f%STrdKA_i(Rf(%Vr-AWS|EBHnW-w<6R?&?8Wt#-+cWF<<+8t+m2G*fG^(->2q(zaDdztq+WI9Tl zjLeBKu6rJt)1IYb9t1iL1ws0O+n@cX|>4QuCTp~%ws8P zDl(H)Y8o=lxBEI+Ln_JRoepb6h>F3wAw|6c>$VC!-dADW6{TK-b$^PQ0c&gp9`Eb0 z9t%)2VLj=m-az`SJoP3Pt(9v(3v)jTv(3hge2kid_5EbsTWCBv#r8HDd%Dy+Fj@tu zxiDWYQ7RgCg{XOG*duxu4Tqv^^I;5%P~~^g!$j}HxK>nt7d_I?Y585WBCY%`TAsnY zAHsMj&*?`n#>;dO40#9S{TRk`E~krOG~Yv)pssI_?GxnwCyJwPZk%l?rp<^^%V4(3 zQ_C^!-VpUE%swe90ke0B(y)4oO6f4qtH9%}N1Y~WfH^t9W*~Qov?Nmg6x#|c356&V zOQy=@uEdf^nC&yn?k?9Lh1nOoY@cIImpHWwQ*TkJG#Z<4off8cRoF6EzqbO9w-M|2 z%Z@Lw{!ol+LXgVC4v5yn z?ond1VfTzv1=wdsCKoVtBGd-h17+Q}um_92gFUpw z=|Dbx{Y%h`M$*iHUQ^8uPJY5{vwC3$>DK{N7HOW51u zR4ZsJV^nL{I~A%5+Nv;B4f_v~7h0pp2YX*-=<&6Imh)3>VIMA0?VzpAQ%9rFN~Mm0 zwmwGrQD_^c+CwXfjz!_P5ZiIkHc0D$Le~;oM`)Y;R3{VyF4Y;Do2R;<&@)DLg|=OE zJPK!r*t$VeBGd^e$YY7`L}>De63WswcDwVX7Ajqh!Y!(4Lak8-@EzoSq5oSwD3a3S(8O546d$ z<7^ZjmmTLodnv|g5QRx0>R-@mWqK|Oa(nij2dz%p`6x_rxvnn?Q$_zqVR|Kbd>5eb zYLM!O!i+d|AqsC+;PG9A!fZL^VlL3mX@jtQdy4BWMq-Z>{ zmq#n~JqG8_F!eaHS6ATiJpt!Fmzsd=4GQ&NIAem;lgNcj)I>NDm3j(w^W~IDa3)B5 z8s;0KXW%?7JD!C(N8yeroEM_hb1;3fcQTyXJlped>SELja9)-6BAl7B<0Uw=L!AB( z&N~%&d^K?16-|Njeu=FX&WECx;Vf3!rove&ng*vn%2o$wg=jj={(iO?oKjNipe~9f96hopo zii70jr6>-Olb4}*mCJR@QM^X

    $2DG3yB7HKHn7Uen}#XCjyDBdHdG@y9D$UyNy zIVFkWxBz#oK=IK$Wuo|moVOCiiD9x(zJk&G z*trhHgzU}3NXdEYQB20T&PMj96jeZRl}sIEf622IQCuz4@=s27mDs*Uab1uq{|x1C z*|7n|qRUqPY05sCeurZ7BkM+F55_p%gyPl|wHY~2oZ5oo&k@Q+u4SJ39>rZQwG}ye zz3bbC;vP9=JBkMsPJcl0aFF^DO)aFAeFGU9MP|6 z>QrL;4cWO7>UT7qU4h593)y;62~Fqc+5SK_B|H8^)1`j4zmUzU)Zb{j!lia2YsaWP zXc``;_9FXTh}wsy>r>QzWVgw>18BNc^beZu5FJF*-741|LiVW$br?;}x7Z_?dU~kR b+IV2Z0u(T71NXLRf%oM3sLfGW(mV8j=l>4| diff --git a/impl1/s1_impl1.p2t b/impl1/s1_impl1.p2t deleted file mode 100644 index de0af6f..0000000 --- a/impl1/s1_impl1.p2t +++ /dev/null @@ -1,10 +0,0 @@ --w --l 5 --i 6 --y --n 1 --t 1 --s 1 --c 0 --e 0 --exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF diff --git a/impl1/s1_impl1.p3t b/impl1/s1_impl1.p3t deleted file mode 100644 index 3d2e48b..0000000 --- a/impl1/s1_impl1.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "s1_impl1.log" --o "s1_impl1.csv" --pr "s1_impl1.prf" diff --git a/impl1/s1_impl1.pad b/impl1/s1_impl1.pad deleted file mode 100644 index 9c4860c..0000000 --- a/impl1/s1_impl1.pad +++ /dev/null @@ -1,702 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LFE5UM5G-45F -Performance Grade: 8 -PACKAGE: CABGA381 -Package Status: Final Version 1.38 - -Wed Jun 16 09:20:00 2021 - -Pinout by Port Name: -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties | -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ -| FEE_DATAFINISHED_OUT | D13/1 | LVCMOS25_OUT | PT53A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[0] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[10] | J19/2 | LVCMOS25_OUT | PR32A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[11] | R3/8 | LVCMOS25_OUT | PB15B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[12] | N5/6 | LVCMOS25_OUT | PL59B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[13] | G16/2 | LVCMOS25_OUT | PR17C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[14] | P5/6 | LVCMOS25_OUT | PL59D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[15] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[16] | N19/3 | LVCMOS25_OUT | PR59A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[17] | B15/1 | LVCMOS25_OUT | PT69A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[18] | A15/1 | LVCMOS25_OUT | PT67A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[19] | K5/6 | LVCMOS25_OUT | PL44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[1] | N3/6 | LVCMOS25_OUT | PL62A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[20] | V1/8 | LVCMOS25_OUT | PB6B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[21] | G19/2 | LVCMOS25_OUT | PR29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[22] | T2/8 | LVCMOS25_OUT | PB13A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[23] | H20/2 | LVCMOS25_OUT | PR29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[24] | K19/2 | LVCMOS25_OUT | PR32B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[25] | H17/2 | LVCMOS25_OUT | PR20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[26] | L19/3 | LVCMOS25_OUT | PR35C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[27] | C20/2 | LVCMOS25_OUT | PR23A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[28] | F19/2 | LVCMOS25_OUT | PR26B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[29] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[2] | G18/2 | LVCMOS25_OUT | PR17B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[30] | D20/2 | LVCMOS25_OUT | PR23C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[31] | H18/2 | LVCMOS25_OUT | PR20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[3] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[4] | E18/2 | LVCMOS25_OUT | PR14C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[5] | F16/2 | LVCMOS25_OUT | PR11D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[6] | A16/1 | LVCMOS25_OUT | PT74A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[7] | L3/6 | LVCMOS25_OUT | PL62C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[8] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[9] | F20/2 | LVCMOS25_OUT | PR26C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_WRITE_OUT | C13/1 | LVCMOS25_OUT | PT51B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_TRG_RELEASE_OUT | E13/1 | LVCMOS25_OUT | PT53B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| LVL1_INVALID_TRG_IN | R16/3 | LVCMOS25_IN | PR44C | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| LVL1_TRG_DATA_VALID_IN | A9/0 | LVCMOS25_IN | PT33A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| LVL1_TRG_DATA_VALI_IN_rising | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| burst | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON | -| discard | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[0] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[10] | K20/2 | LVCMOS25_OUT | PR32D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[11] | U2/8 | LVCMOS25_OUT | PB13B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[12] | N4/6 | LVCMOS25_OUT | PL59C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[13] | J16/2 | LVCMOS25_OUT | PR20D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[14] | M4/6 | LVCMOS25_OUT | PL59A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[15] | J20/2 | LVCMOS25_OUT | PR32C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[16] | P18/3 | LVCMOS25_OUT | PR59D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[17] | C15/1 | LVCMOS25_OUT | PT69B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[18] | E14/1 | LVCMOS25_OUT | PT58B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[19] | L4/6 | LVCMOS25_OUT | PL44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[1] | M3/6 | LVCMOS25_OUT | PL62B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[20] | Y2/8 | LVCMOS25_OUT | PB9B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[21] | K18/2 | LVCMOS25_OUT | PR29D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[22] | W1/8 | LVCMOS25_OUT | PB9A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[23] | J18/2 | LVCMOS25_OUT | PR29C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[24] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[25] | J17/2 | LVCMOS25_OUT | PR20C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[26] | L20/3 | LVCMOS25_OUT | PR35A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[27] | D19/2 | LVCMOS25_OUT | PR23B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[28] | G20/2 | LVCMOS25_OUT | PR26D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[29] | T1/8 | LVCMOS25_OUT | PB4B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[2] | F17/2 | LVCMOS25_OUT | PR17A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[30] | E19/2 | LVCMOS25_OUT | PR23D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[31] | H16/2 | LVCMOS25_OUT | PR17D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[3] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[4] | F18/2 | LVCMOS25_OUT | PR14D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[5] | D17/2 | LVCMOS25_OUT | PR11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[6] | B16/1 | LVCMOS25_OUT | PT74B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[7] | N1/6 | LVCMOS25_OUT | PL65D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[8] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[9] | E20/2 | LVCMOS25_OUT | PR26A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_empty1 | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_rden | A19/1 | LVCMOS25_OUT | PT85A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| finished | D14/1 | LVCMOS25_OUT | PT58A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[0] | N20/3 | LVCMOS25_OUT | PR59B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[1] | A10/0 | LVCMOS25_OUT | PT36A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[2] | R20/3 | LVCMOS25_OUT | PR62B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[3] | U16/3 | LVCMOS25_OUT | PR68C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_finished | A4/7 | LVCMOS25_OUT | PL11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_out_valid | C9/0 | LVCMOS25_OUT | PT27A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_release | E7/0 | LVCMOS25_OUT | PT9A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[0] | G5/7 | LVCMOS25_OUT | PL29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[1] | H3/7 | LVCMOS25_OUT | PL29D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[2] | E3/7 | LVCMOS25_OUT | PL20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[3] | C2/7 | LVCMOS25_OUT | PL23D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[4] | B6/0 | LVCMOS25_OUT | PT4B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[5] | B1/7 | LVCMOS25_OUT | PL23B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[6] | E5/7 | LVCMOS25_OUT | PL20C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[7] | M5/6 | LVCMOS25_OUT | PL53A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[8] | F1/6 | LVCMOS25_OUT | PL35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[0] | J3/6 | LVCMOS25_OUT | PL38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[10] | A8/0 | LVCMOS25_OUT | PT18B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[11] | D6/0 | LVCMOS25_OUT | PT6B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[12] | B8/0 | LVCMOS25_OUT | PT15B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[13] | P19/3 | LVCMOS25_OUT | PR59C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[14] | P1/6 | LVCMOS25_OUT | PL68A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[15] | C17/1 | LVCMOS25_OUT | PT78B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[16] | G3/7 | LVCMOS25_OUT | PL32A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[17] | G1/6 | LVCMOS25_OUT | PL35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[18] | J5/6 | LVCMOS25_OUT | PL38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[19] | R1/8 | LVCMOS25_OUT | PB4A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[1] | E2/7 | LVCMOS25_OUT | PL32D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[20] | K3/6 | LVCMOS25_OUT | PL38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[21] | G2/6 | LVCMOS25_OUT | PL35A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[22] | H4/7 | LVCMOS25_OUT | PL29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[23] | J4/6 | LVCMOS25_OUT | PL38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[24] | H1/6 | LVCMOS25_OUT | PL41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[25] | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[26] | K1/6 | LVCMOS25_OUT | PL41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[27] | F2/7 | LVCMOS25_OUT | PL32C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[28] | H2/6 | LVCMOS25_OUT | PL35C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[29] | A17/1 | LVCMOS25_OUT | PT80A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[2] | F3/7 | LVCMOS25_OUT | PL32B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[30] | E16/2 | LVCMOS25_OUT | PR11C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[31] | R18/3 | LVCMOS25_OUT | PR65B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[3] | C16/1 | LVCMOS25_OUT | PT76A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[4] | E4/7 | LVCMOS25_OUT | PL17A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[5] | C3/7 | LVCMOS25_OUT | PL17C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[6] | F4/7 | LVCMOS25_OUT | PL20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[7] | B3/7 | LVCMOS25_OUT | PL14D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[8] | E8/0 | LVCMOS25_OUT | PT13A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[9] | C7/0 | LVCMOS25_OUT | PT11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_discard | B11/0 | LVCMOS25_OUT | PT38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[0] | D3/7 | LVCMOS25_OUT | PL17D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[10] | B17/1 | LVCMOS25_OUT | PT78A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[11] | U17/3 | LVCMOS25_OUT | PR68B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[1] | D9/0 | LVCMOS25_OUT | PT20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[2] | A6/0 | LVCMOS25_OUT | PT4A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[3] | C6/0 | LVCMOS25_OUT | PT11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[4] | F5/7 | LVCMOS25_OUT | PL20D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[5] | C4/7 | LVCMOS25_OUT | PL14A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[6] | D8/0 | LVCMOS25_OUT | PT13B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[7] | D5/7 | LVCMOS25_OUT | PL17B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[8] | B4/7 | LVCMOS25_OUT | PL14B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[9] | B20/1 | LVCMOS25_OUT | PT85B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[0] | A11/0 | LVCMOS25_OUT | PT36B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[10] | T17/3 | LVCMOS25_OUT | PR68D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[11] | D18/2 | LVCMOS25_OUT | PR14A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[1] | A13/1 | LVCMOS25_OUT | PT49B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[2] | B10/0 | LVCMOS25_OUT | PT33B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[3] | C12/1 | LVCMOS25_OUT | PT44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[4] | E12/1 | LVCMOS25_OUT | PT47B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[5] | D12/1 | LVCMOS25_OUT | PT47A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[6] | E11/1 | LVCMOS25_OUT | PT42B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[7] | D11/1 | LVCMOS25_OUT | PT42A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[8] | B13/1 | LVCMOS25_OUT | PT51A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[9] | A12/1 | LVCMOS25_OUT | PT49A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_valid | A7/0 | LVCMOS25_OUT | PT18A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[0] | E9/0 | LVCMOS25_OUT | PT20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[1] | C11/0 | LVCMOS25_OUT | PT38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[2] | E6/0 | LVCMOS25_OUT | PT6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[3] | D7/0 | LVCMOS25_OUT | PT9B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[0] | A3/7 | LVCMOS25_OUT | PL14C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[1] | B5/7 | LVCMOS25_OUT | PL11C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[2] | A5/7 | LVCMOS25_OUT | PL11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[3] | C5/7 | LVCMOS25_OUT | PL11D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[0] | V2/8 | LVCMOS25_OUT | PB11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[1] | L5/6 | LVCMOS25_OUT | PL44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[2] | K2/6 | LVCMOS25_OUT | PL41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[3] | K4/6 | LVCMOS25_OUT | PL44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_lvl1 | E1/7 | LVCMOS25_IN | PL26D | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_lvl1_invalid | W2/8 | LVCMOS25_IN | PB11B | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_offset[0] | D10/0 | LVCMOS25_OUT | PT29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[1] | C10/0 | LVCMOS25_OUT | PT31B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[2] | E10/0 | LVCMOS25_OUT | PT29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[3] | D1/7 | LVCMOS25_OUT | PL26B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[4] | C1/7 | LVCMOS25_OUT | PL26A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[5] | D2/7 | LVCMOS25_OUT | PL26C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[6] | A2/7 | LVCMOS25_OUT | PL23A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[7] | B9/0 | LVCMOS25_OUT | PT31A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[8] | B2/7 | LVCMOS25_OUT | PL23C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset_valid | D15/1 | LVCMOS25_OUT | PT71A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_out_valid | E15/1 | LVCMOS25_OUT | PT71B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_valid_vect[0] | U20/3 | LVCMOS25_OUT | PR62D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_valid_vect[1] | E17/2 | LVCMOS25_OUT | PR14B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_trig | H5/7 | LVCMOS25_IN | PL29C | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_window_end | C14/1 | LVCMOS25_OUT | PT56B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| last_buf_empty | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| rd_clk | B12/1 | LVCMOS25_IN | PT44A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| release_out | A14/1 | LVCMOS25_OUT | PT56A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| reset_dc | C8/0 | LVCMOS25_IN | PT15A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[0] | R2/8 | LVCMOS25_IN | PB15A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[1] | T3/8 | LVCMOS25_IN | PB18A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[2] | T19/3 | LVCMOS25_IN | PR65A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 2.5V | -| 1 | 2.5V | -| 2 | 2.5V | -| 3 | 2.5V | -| 6 | 2.5V | -| 7 | 2.5V | -| 8 | 2.5V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | BC Enable | -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ -| A2/7 | hades_offset[6] | | LVCMOS25_OUT | PL23A | LDQ29 | | -| A3/7 | hades_hit_valid[0] | | LVCMOS25_OUT | PL14C | LDQ17 | | -| A4/7 | hades_buf_finished | | LVCMOS25_OUT | PL11A | ULC_GPLL0T_IN/LDQ17 | | -| A5/7 | hades_hit_valid[2] | | LVCMOS25_OUT | PL11B | ULC_GPLL0C_IN/LDQ17 | | -| A6/0 | hades_drop_cmp_buf[2] | | LVCMOS25_OUT | PT4A | ULC_GPLL1T_IN | | -| A7/0 | hades_drop_cmp_buf_valid | | LVCMOS25_OUT | PT18A | | | -| A8/0 | hades_dbg2_out[10] | | LVCMOS25_OUT | PT18B | | | -| A9/0 | LVL1_TRG_DATA_VALID_IN | LOCATED | LVCMOS25_IN | PT33A | GR_PCLK0_1 | | -| A10/0 | hades_buf_drop[1] | | LVCMOS25_OUT | PT36A | PCLKT0_1 | | -| A11/0 | hades_drop_cmp_buf_coarse[0] | | LVCMOS25_OUT | PT36B | | | -| A12/1 | hades_drop_cmp_buf_coarse[9] | | LVCMOS25_OUT | PT49A | | | -| A13/1 | hades_drop_cmp_buf_coarse[1] | | LVCMOS25_OUT | PT49B | | | -| A14/1 | release_out | | LVCMOS25_OUT | PT56A | | | -| A15/1 | FEE_DATA_OUT[18] | | LVCMOS25_OUT | PT67A | | | -| A16/1 | FEE_DATA_OUT[6] | | LVCMOS25_OUT | PT74A | | | -| A17/1 | hades_dbg2_out[29] | | LVCMOS25_OUT | PT80A | | | -| A18/1 | unused, PULL:DOWN | | | PT83A | | | -| A19/1 | fifo_rden | | LVCMOS25_OUT | PT85A | URC_GPLL1T_IN | | -| B1/7 | hades_dbg2_coarse[5] | | LVCMOS25_OUT | PL23B | LDQ29 | | -| B2/7 | hades_offset[8] | | LVCMOS25_OUT | PL23C | VREF1_7/LDQ29 | | -| B3/7 | hades_dbg2_out[7] | | LVCMOS25_OUT | PL14D | LDQ17 | | -| B4/7 | hades_drop_cmp_buf[8] | | LVCMOS25_OUT | PL14B | LDQ17 | | -| B5/7 | hades_hit_valid[1] | | LVCMOS25_OUT | PL11C | LDQ17 | | -| B6/0 | hades_dbg2_coarse[4] | | LVCMOS25_OUT | PT4B | ULC_GPLL1C_IN | | -| B8/0 | hades_dbg2_out[12] | | LVCMOS25_OUT | PT15B | | | -| B9/0 | hades_offset[7] | | LVCMOS25_OUT | PT31A | | | -| B10/0 | hades_drop_cmp_buf_coarse[2] | | LVCMOS25_OUT | PT33B | GR_PCLK0_0 | | -| B11/0 | hades_discard | | LVCMOS25_OUT | PT38A | PCLKT0_0 | | -| B12/1 | rd_clk | | LVCMOS25_IN | PT44A | PCLKT1_0 | | -| B13/1 | hades_drop_cmp_buf_coarse[8] | | LVCMOS25_OUT | PT51A | | | -| B15/1 | FEE_DATA_OUT[17] | | LVCMOS25_OUT | PT69A | | | -| B16/1 | fifo_data_out[6] | | LVCMOS25_OUT | PT74B | | | -| B17/1 | hades_drop_cmp_buf[10] | | LVCMOS25_OUT | PT78A | | | -| B18/1 | unused, PULL:DOWN | | | PT80B | | | -| B19/1 | unused, PULL:DOWN | | | PT83B | | | -| B20/1 | hades_drop_cmp_buf[9] | | LVCMOS25_OUT | PT85B | URC_GPLL1C_IN | | -| C1/7 | hades_offset[4] | | LVCMOS25_OUT | PL26A | LDQ29 | | -| C2/7 | hades_dbg2_coarse[3] | | LVCMOS25_OUT | PL23D | LDQ29 | | -| C3/7 | hades_dbg2_out[5] | | LVCMOS25_OUT | PL17C | LDQ17 | | -| C4/7 | hades_drop_cmp_buf[5] | | LVCMOS25_OUT | PL14A | LDQ17 | | -| C5/7 | hades_hit_valid[3] | | LVCMOS25_OUT | PL11D | LDQ17 | | -| C6/0 | hades_drop_cmp_buf[3] | | LVCMOS25_OUT | PT11A | | | -| C7/0 | hades_dbg2_out[9] | | LVCMOS25_OUT | PT11B | | | -| C8/0 | reset_dc | | LVCMOS25_IN | PT15A | | | -| C9/0 | hades_buf_out_valid | | LVCMOS25_OUT | PT27A | | | -| C10/0 | hades_offset[1] | | LVCMOS25_OUT | PT31B | | | -| C11/0 | hades_hit_out_i[1] | | LVCMOS25_OUT | PT38B | | | -| C12/1 | hades_drop_cmp_buf_coarse[3] | | LVCMOS25_OUT | PT44B | | | -| C13/1 | FEE_DATA_WRITE_OUT | | LVCMOS25_OUT | PT51B | | | -| C14/1 | hades_window_end | | LVCMOS25_OUT | PT56B | | | -| C15/1 | fifo_data_out[17] | | LVCMOS25_OUT | PT69B | | | -| C16/1 | hades_dbg2_out[3] | | LVCMOS25_OUT | PT76A | | | -| C17/1 | hades_dbg2_out[15] | | LVCMOS25_OUT | PT78B | | | -| C18/2 | unused, PULL:DOWN | | | PR11A | URC_GPLL0T_IN/RDQ17 | | -| C20/2 | FEE_DATA_OUT[27] | | LVCMOS25_OUT | PR23A | RDQ29 | | -| CCLK/8 | | | | CCLK | MCLK/SCK | | -| D1/7 | hades_offset[3] | | LVCMOS25_OUT | PL26B | LDQ29 | | -| D2/7 | hades_offset[5] | | LVCMOS25_OUT | PL26C | LDQ29 | | -| D3/7 | hades_drop_cmp_buf[0] | | LVCMOS25_OUT | PL17D | LDQ17 | | -| D5/7 | hades_drop_cmp_buf[7] | | LVCMOS25_OUT | PL17B | LDQSN17 | | -| D6/0 | hades_dbg2_out[11] | | LVCMOS25_OUT | PT6B | | | -| D7/0 | hades_hit_out_i[3] | | LVCMOS25_OUT | PT9B | | | -| D8/0 | hades_drop_cmp_buf[6] | | LVCMOS25_OUT | PT13B | | | -| D9/0 | hades_drop_cmp_buf[1] | | LVCMOS25_OUT | PT20A | | | -| D10/0 | hades_offset[0] | | LVCMOS25_OUT | PT29A | | | -| D11/1 | hades_drop_cmp_buf_coarse[7] | | LVCMOS25_OUT | PT42A | PCLKT1_1 | | -| D12/1 | hades_drop_cmp_buf_coarse[5] | | LVCMOS25_OUT | PT47A | GR_PCLK1_0 | | -| D13/1 | FEE_DATAFINISHED_OUT | | LVCMOS25_OUT | PT53A | | | -| D14/1 | finished | | LVCMOS25_OUT | PT58A | | | -| D15/1 | hades_offset_valid | | LVCMOS25_OUT | PT71A | | | -| D16/1 | unused, PULL:DOWN | | | PT76B | | | -| D17/2 | fifo_data_out[5] | | LVCMOS25_OUT | PR11B | URC_GPLL0C_IN/RDQ17 | | -| D18/2 | hades_drop_cmp_buf_coarse[11] | | LVCMOS25_OUT | PR14A | RDQ17 | | -| D19/2 | fifo_data_out[27] | | LVCMOS25_OUT | PR23B | RDQ29 | | -| D20/2 | FEE_DATA_OUT[30] | | LVCMOS25_OUT | PR23C | VREF1_2/RDQ29 | | -| E1/7 | hades_lvl1 | LOCATED | LVCMOS25_IN | PL26D | LDQ29 | | -| E2/7 | hades_dbg2_out[1] | | LVCMOS25_OUT | PL32D | PCLKC7_0/LDQ29 | | -| E3/7 | hades_dbg2_coarse[2] | | LVCMOS25_OUT | PL20B | LDQ17 | | -| E4/7 | hades_dbg2_out[4] | | LVCMOS25_OUT | PL17A | LDQS17 | | -| E5/7 | hades_dbg2_coarse[6] | | LVCMOS25_OUT | PL20C | LDQ17 | | -| E6/0 | hades_hit_out_i[2] | | LVCMOS25_OUT | PT6A | | | -| E7/0 | hades_buf_release | | LVCMOS25_OUT | PT9A | | | -| E8/0 | hades_dbg2_out[8] | | LVCMOS25_OUT | PT13A | | | -| E9/0 | hades_hit_out_i[0] | | LVCMOS25_OUT | PT20B | | | -| E10/0 | hades_offset[2] | | LVCMOS25_OUT | PT29B | | | -| E11/1 | hades_drop_cmp_buf_coarse[6] | | LVCMOS25_OUT | PT42B | | | -| E12/1 | hades_drop_cmp_buf_coarse[4] | | LVCMOS25_OUT | PT47B | GR_PCLK1_1 | | -| E13/1 | FEE_TRG_RELEASE_OUT | | LVCMOS25_OUT | PT53B | | | -| E14/1 | fifo_data_out[18] | | LVCMOS25_OUT | PT58B | | | -| E15/1 | hades_raw_out_valid | | LVCMOS25_OUT | PT71B | | | -| E16/2 | hades_dbg2_out[30] | | LVCMOS25_OUT | PR11C | RDQ17 | | -| E17/2 | hades_raw_valid_vect[1] | | LVCMOS25_OUT | PR14B | RDQ17 | | -| E18/2 | FEE_DATA_OUT[4] | | LVCMOS25_OUT | PR14C | RDQ17 | | -| E19/2 | fifo_data_out[30] | | LVCMOS25_OUT | PR23D | RDQ29 | | -| E20/2 | fifo_data_out[9] | | LVCMOS25_OUT | PR26A | RDQ29 | | -| F1/6 | hades_dbg2_coarse[8] | | LVCMOS25_OUT | PL35B | PCLKC6_1/LDQ41 | | -| F2/7 | hades_dbg2_out[27] | | LVCMOS25_OUT | PL32C | PCLKT7_0/LDQ29 | | -| F3/7 | hades_dbg2_out[2] | | LVCMOS25_OUT | PL32B | PCLKC7_1/LDQ29 | | -| F4/7 | hades_dbg2_out[6] | | LVCMOS25_OUT | PL20A | LDQ17 | | -| F5/7 | hades_drop_cmp_buf[4] | | LVCMOS25_OUT | PL20D | LDQ17 | | -| F16/2 | FEE_DATA_OUT[5] | | LVCMOS25_OUT | PR11D | RDQ17 | | -| F17/2 | fifo_data_out[2] | | LVCMOS25_OUT | PR17A | RDQS17 | | -| F18/2 | fifo_data_out[4] | | LVCMOS25_OUT | PR14D | RDQ17 | | -| F19/2 | FEE_DATA_OUT[28] | | LVCMOS25_OUT | PR26B | RDQ29 | | -| F20/2 | FEE_DATA_OUT[9] | | LVCMOS25_OUT | PR26C | RDQ29 | | -| G1/6 | hades_dbg2_out[17] | | LVCMOS25_OUT | PL35D | PCLKC6_0/LDQ41 | | -| G2/6 | hades_dbg2_out[21] | | LVCMOS25_OUT | PL35A | PCLKT6_1/LDQ41 | | -| G3/7 | hades_dbg2_out[16] | | LVCMOS25_OUT | PL32A | PCLKT7_1/LDQ29 | | -| G5/7 | hades_dbg2_coarse[0] | | LVCMOS25_OUT | PL29B | LDQSN29 | | -| G16/2 | FEE_DATA_OUT[13] | | LVCMOS25_OUT | PR17C | RDQ17 | | -| G18/2 | FEE_DATA_OUT[2] | | LVCMOS25_OUT | PR17B | RDQSN17 | | -| G19/2 | FEE_DATA_OUT[21] | | LVCMOS25_OUT | PR29A | GR_PCLK2_1/RDQS29 | | -| G20/2 | fifo_data_out[28] | | LVCMOS25_OUT | PR26D | RDQ29 | | -| H1/6 | hades_dbg2_out[24] | | LVCMOS25_OUT | PL41C | LDQ41 | | -| H2/6 | hades_dbg2_out[28] | | LVCMOS25_OUT | PL35C | PCLKT6_0/LDQ41 | | -| H3/7 | hades_dbg2_coarse[1] | | LVCMOS25_OUT | PL29D | LDQ29 | | -| H4/7 | hades_dbg2_out[22] | | LVCMOS25_OUT | PL29A | GR_PCLK7_1/LDQS29 | | -| H5/7 | hades_trig | LOCATED | LVCMOS25_IN | PL29C | GR_PCLK7_0/LDQ29 | | -| H16/2 | fifo_data_out[31] | | LVCMOS25_OUT | PR17D | RDQ17 | | -| H17/2 | FEE_DATA_OUT[25] | | LVCMOS25_OUT | PR20B | RDQ17 | | -| H18/2 | FEE_DATA_OUT[31] | | LVCMOS25_OUT | PR20A | RDQ17 | | -| H20/2 | FEE_DATA_OUT[23] | | LVCMOS25_OUT | PR29B | RDQSN29 | | -| J1/6 | hades_dbg2_out[25] | | LVCMOS25_OUT | PL41B | LDQSN41 | | -| J3/6 | hades_dbg2_out[0] | | LVCMOS25_OUT | PL38C | GR_PCLK6_1/LDQ41 | | -| J4/6 | hades_dbg2_out[23] | | LVCMOS25_OUT | PL38A | GR_PCLK6_0/LDQ41 | | -| J5/6 | hades_dbg2_out[18] | | LVCMOS25_OUT | PL38B | LDQ41 | | -| J16/2 | fifo_data_out[13] | | LVCMOS25_OUT | PR20D | RDQ17 | | -| J17/2 | fifo_data_out[25] | | LVCMOS25_OUT | PR20C | RDQ17 | | -| J18/2 | fifo_data_out[23] | | LVCMOS25_OUT | PR29C | GR_PCLK2_0/RDQ29 | | -| J19/2 | FEE_DATA_OUT[10] | | LVCMOS25_OUT | PR32A | PCLKT2_1/RDQ29 | | -| J20/2 | fifo_data_out[15] | | LVCMOS25_OUT | PR32C | PCLKT2_0/RDQ29 | | -| K1/6 | hades_dbg2_out[26] | | LVCMOS25_OUT | PL41D | LDQ41 | | -| K2/6 | hades_invalid_dl[2] | | LVCMOS25_OUT | PL41A | LDQS41 | | -| K3/6 | hades_dbg2_out[20] | | LVCMOS25_OUT | PL38D | LDQ41 | | -| K4/6 | hades_invalid_dl[3] | | LVCMOS25_OUT | PL44A | LDQ41 | | -| K5/6 | FEE_DATA_OUT[19] | | LVCMOS25_OUT | PL44B | VREF1_6/LDQ41 | | -| K18/2 | fifo_data_out[21] | | LVCMOS25_OUT | PR29D | RDQ29 | | -| K19/2 | FEE_DATA_OUT[24] | | LVCMOS25_OUT | PR32B | PCLKC2_1/RDQ29 | | -| K20/2 | fifo_data_out[10] | | LVCMOS25_OUT | PR32D | PCLKC2_0/RDQ29 | | -| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | | -| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | | -| L3/6 | FEE_DATA_OUT[7] | | LVCMOS25_OUT | PL62C | LDQ65 | | -| L4/6 | fifo_data_out[19] | | LVCMOS25_OUT | PL44C | LDQ41 | | -| L5/6 | hades_invalid_dl[1] | | LVCMOS25_OUT | PL44D | LDQ41 | | -| L16/3 | FEE_DATA_OUT[8] | | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | | -| L17/3 | fifo_data_out[3] | | LVCMOS25_OUT | PR38B | RDQ41 | | -| L18/3 | last_buf_empty | | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | | -| L19/3 | FEE_DATA_OUT[26] | | LVCMOS25_OUT | PR35C | PCLKT3_0/RDQ41 | | -| L20/3 | fifo_data_out[26] | | LVCMOS25_OUT | PR35A | PCLKT3_1/RDQ41 | | -| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | | -| M3/6 | fifo_data_out[1] | | LVCMOS25_OUT | PL62B | LDQ65 | | -| M4/6 | fifo_data_out[14] | | LVCMOS25_OUT | PL59A | LDQ65 | | -| M5/6 | hades_dbg2_coarse[7] | | LVCMOS25_OUT | PL53A | LDQS53 | | -| M17/3 | FEE_DATA_OUT[3] | | LVCMOS25_OUT | PR41B | RDQSN41 | | -| M18/3 | fifo_data_out[8] | | LVCMOS25_OUT | PR38D | RDQ41 | | -| M19/3 | FEE_DATA_OUT[15] | | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | | -| M20/3 | fifo_data_out[24] | | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | | -| N1/6 | fifo_data_out[7] | | LVCMOS25_OUT | PL65D | LDQ65 | | -| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | | -| N3/6 | FEE_DATA_OUT[1] | | LVCMOS25_OUT | PL62A | LDQ65 | | -| N4/6 | fifo_data_out[12] | | LVCMOS25_OUT | PL59C | LDQ65 | | -| N5/6 | FEE_DATA_OUT[12] | | LVCMOS25_OUT | PL59B | LDQ65 | | -| N16/3 | burst | | LVCMOS25_OUT | PR41A | RDQS41 | | -| N17/3 | fifo_empty1 | | LVCMOS25_OUT | PR44A | RDQ41 | | -| N18/3 | LVL1_TRG_DATA_VALI_IN_rising | | LVCMOS25_OUT | PR41C | RDQ41 | | -| N19/3 | FEE_DATA_OUT[16] | | LVCMOS25_OUT | PR59A | RDQ65 | | -| N20/3 | hades_buf_drop[0] | | LVCMOS25_OUT | PR59B | RDQ65 | | -| P1/6 | hades_dbg2_out[14] | | LVCMOS25_OUT | PL68A | LDQ65 | | -| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | | -| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | | -| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | | -| P5/6 | FEE_DATA_OUT[14] | | LVCMOS25_OUT | PL59D | LDQ65 | | -| P16/3 | discard | | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | | -| P17/3 | fifo_data_out[0] | | LVCMOS25_OUT | PR41D | RDQ41 | | -| P18/3 | fifo_data_out[16] | | LVCMOS25_OUT | PR59D | RDQ65 | | -| P19/3 | hades_dbg2_out[13] | | LVCMOS25_OUT | PR59C | RDQ65 | | -| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | | -| PL47A/6 | unused, PULL:DOWN | | | PL47A | LDQ53 | | -| PL47B/6 | unused, PULL:DOWN | | | PL47B | LDQ53 | | -| PL47C/6 | unused, PULL:DOWN | | | PL47C | LDQ53 | | -| PL47D/6 | unused, PULL:DOWN | | | PL47D | LDQ53 | | -| PL50A/6 | unused, PULL:DOWN | | | PL50A | LDQ53 | | -| PL50B/6 | unused, PULL:DOWN | | | PL50B | LDQ53 | | -| PL50C/6 | unused, PULL:DOWN | | | PL50C | LDQ53 | | -| PL50D/6 | unused, PULL:DOWN | | | PL50D | LDQ53 | | -| PL53B/6 | unused, PULL:DOWN | | | PL53B | LDQSN53 | | -| PL53C/6 | unused, PULL:DOWN | | | PL53C | LDQ53 | | -| PL53D/6 | unused, PULL:DOWN | | | PL53D | LDQ53 | | -| PL56A/6 | unused, PULL:DOWN | | | PL56A | LDQ53 | | -| PL56B/6 | unused, PULL:DOWN | | | PL56B | LDQ53 | | -| PL56C/6 | unused, PULL:DOWN | | | PL56C | LDQ53 | | -| PL56D/6 | unused, PULL:DOWN | | | PL56D | LDQ53 | | -| PR47A/3 | unused, PULL:DOWN | | | PR47A | RDQ53 | | -| PR47B/3 | unused, PULL:DOWN | | | PR47B | RDQ53 | | -| PR47C/3 | unused, PULL:DOWN | | | PR47C | RDQ53 | | -| PR47D/3 | unused, PULL:DOWN | | | PR47D | RDQ53 | | -| PR50A/3 | unused, PULL:DOWN | | | PR50A | RDQ53 | | -| PR50B/3 | unused, PULL:DOWN | | | PR50B | RDQ53 | | -| PR50C/3 | unused, PULL:DOWN | | | PR50C | RDQ53 | | -| PR50D/3 | unused, PULL:DOWN | | | PR50D | RDQ53 | | -| PR53B/3 | unused, PULL:DOWN | | | PR53B | RDQSN53 | | -| PR53C/3 | unused, PULL:DOWN | | | PR53C | RDQ53 | | -| PR53D/3 | unused, PULL:DOWN | | | PR53D | RDQ53 | | -| PR56A/3 | unused, PULL:DOWN | | | PR56A | RDQ53 | | -| PR56B/3 | unused, PULL:DOWN | | | PR56B | RDQ53 | | -| PR56C/3 | unused, PULL:DOWN | | | PR56C | RDQ53 | | -| PR56D/3 | unused, PULL:DOWN | | | PR56D | RDQ53 | | -| PT22A/0 | unused, PULL:DOWN | | | PT22A | | | -| PT22B/0 | unused, PULL:DOWN | | | PT22B | | | -| PT24A/0 | unused, PULL:DOWN | | | PT24A | | | -| PT24B/0 | unused, PULL:DOWN | | | PT24B | | | -| PT27B/0 | unused, PULL:DOWN | | | PT27B | | | -| PT60A/1 | unused, PULL:DOWN | | | PT60A | | | -| PT60B/1 | unused, PULL:DOWN | | | PT60B | | | -| PT62A/1 | unused, PULL:DOWN | | | PT62A | | | -| PT62B/1 | unused, PULL:DOWN | | | PT62B | | | -| PT65A/1 | unused, PULL:DOWN | | | PT65A | | | -| PT65B/1 | unused, PULL:DOWN | | | PT65B | | | -| PT67B/1 | unused, PULL:DOWN | | | PT67B | | | -| R1/8 | hades_dbg2_out[19] | | LVCMOS25_OUT | PB4A | D7/IO7 | | -| R2/8 | trig[0] | LOCATED | LVCMOS25_IN | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | | -| R3/8 | FEE_DATA_OUT[11] | | LVCMOS25_OUT | PB15B | DOUT/CSON | | -| R16/3 | LVL1_INVALID_TRG_IN | | LVCMOS25_IN | PR44C | RDQ41 | | -| R17/3 | FEE_DATA_OUT[0] | | LVCMOS25_OUT | PR44D | RDQ41 | | -| R18/3 | hades_dbg2_out[31] | | LVCMOS25_OUT | PR65B | RDQSN65 | | -| R20/3 | hades_buf_drop[2] | | LVCMOS25_OUT | PR62B | RDQ65 | | -| T1/8 | fifo_data_out[29] | | LVCMOS25_OUT | PB4B | D6/IO6 | | -| T2/8 | FEE_DATA_OUT[22] | | LVCMOS25_OUT | PB13A | SN/CSN | | -| T3/8 | trig[1] | LOCATED | LVCMOS25_IN | PB18A | WRITEN | | -| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | | -| T17/3 | hades_drop_cmp_buf_coarse[10] | | LVCMOS25_OUT | PR68D | LRC_GPLL0C_IN/RDQ65 | | -| T18/3 | unused, PULL:DOWN | | | PR65D | RDQ65 | | -| T19/3 | trig[2] | LOCATED | LVCMOS25_IN | PR65A | RDQS65 | | -| T20/3 | unused, PULL:DOWN | | | PR62C | RDQ65 | | -| TCK/40 | | | | TCK | | | -| TDI/40 | | | | TDI | | | -| TDO/40 | | | | TDO | | | -| TMS/40 | | | | TMS | | | -| U1/8 | FEE_DATA_OUT[29] | | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | | -| U2/8 | fifo_data_out[11] | | LVCMOS25_OUT | PB13B | CS1N | | -| U16/3 | hades_buf_drop[3] | | LVCMOS25_OUT | PR68C | LRC_GPLL0T_IN/RDQ65 | | -| U17/3 | hades_drop_cmp_buf[11] | | LVCMOS25_OUT | PR68B | RDQ65 | | -| U18/3 | unused, PULL:DOWN | | | PR68A | RDQ65 | | -| U19/3 | unused, PULL:DOWN | | | PR65C | RDQ65 | | -| U20/3 | hades_raw_valid_vect[0] | | LVCMOS25_OUT | PR62D | RDQ65 | | -| V1/8 | FEE_DATA_OUT[20] | | LVCMOS25_OUT | PB6B | D4/MOSI2/IO4 | | -| V2/8 | hades_invalid_dl[0] | | LVCMOS25_OUT | PB11A | D1/MISO/IO1 | | -| W1/8 | fifo_data_out[22] | | LVCMOS25_OUT | PB9A | D3/IO3 | | -| W2/8 | hades_lvl1_invalid | | LVCMOS25_IN | PB11B | D0/MOSI/IO0 | | -| W4/50 | | | | HDTXP0_D0CH0 | | | -| W5/50 | | | | HDTXN0_D0CH0 | | | -| W8/50 | | | | HDTXP0_D0CH1 | | | -| W9/50 | | | | HDTXN0_D0CH1 | | | -| W13/51 | | | | HDTXP0_D1CH0 | | | -| W14/51 | | | | HDTXN0_D1CH0 | | | -| W17/51 | | | | HDTXP0_D1CH1 | | | -| W18/51 | | | | HDTXN0_D1CH1 | | | -| W20/51 | | | | REFCLKN_D1 | | | -| Y2/8 | fifo_data_out[20] | | LVCMOS25_OUT | PB9B | D2/IO2 | | -| Y5/50 | | | | HDRXP0_D0CH0 | | | -| Y6/50 | | | | HDRXN0_D0CH0 | | | -| Y7/50 | | | | HDRXP0_D0CH1 | | | -| Y8/50 | | | | HDRXN0_D0CH1 | | | -| Y11/50 | | | | REFCLKP_D0 | | | -| Y12/50 | | | | REFCLKN_D0 | | | -| Y14/51 | | | | HDRXP0_D1CH0 | | | -| Y15/51 | | | | HDRXN0_D1CH0 | | | -| Y16/51 | | | | HDRXP0_D1CH1 | | | -| Y17/51 | | | | HDRXN0_D1CH1 | | | -| Y19/51 | | | | REFCLKP_D1 | | | -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "FEE_DATAFINISHED_OUT" SITE "D13"; -LOCATE COMP "FEE_DATA_OUT[0]" SITE "R17"; -LOCATE COMP "FEE_DATA_OUT[10]" SITE "J19"; -LOCATE COMP "FEE_DATA_OUT[11]" SITE "R3"; -LOCATE COMP "FEE_DATA_OUT[12]" SITE "N5"; -LOCATE COMP "FEE_DATA_OUT[13]" SITE "G16"; -LOCATE COMP "FEE_DATA_OUT[14]" SITE "P5"; -LOCATE COMP "FEE_DATA_OUT[15]" SITE "M19"; -LOCATE COMP "FEE_DATA_OUT[16]" SITE "N19"; -LOCATE COMP "FEE_DATA_OUT[17]" SITE "B15"; -LOCATE COMP "FEE_DATA_OUT[18]" SITE "A15"; -LOCATE COMP "FEE_DATA_OUT[19]" SITE "K5"; -LOCATE COMP "FEE_DATA_OUT[1]" SITE "N3"; -LOCATE COMP "FEE_DATA_OUT[20]" SITE "V1"; -LOCATE COMP "FEE_DATA_OUT[21]" SITE "G19"; -LOCATE COMP "FEE_DATA_OUT[22]" SITE "T2"; -LOCATE COMP "FEE_DATA_OUT[23]" SITE "H20"; -LOCATE COMP "FEE_DATA_OUT[24]" SITE "K19"; -LOCATE COMP "FEE_DATA_OUT[25]" SITE "H17"; -LOCATE COMP "FEE_DATA_OUT[26]" SITE "L19"; -LOCATE COMP "FEE_DATA_OUT[27]" SITE "C20"; -LOCATE COMP "FEE_DATA_OUT[28]" SITE "F19"; -LOCATE COMP "FEE_DATA_OUT[29]" SITE "U1"; -LOCATE COMP "FEE_DATA_OUT[2]" SITE "G18"; -LOCATE COMP "FEE_DATA_OUT[30]" SITE "D20"; -LOCATE COMP "FEE_DATA_OUT[31]" SITE "H18"; -LOCATE COMP "FEE_DATA_OUT[3]" SITE "M17"; -LOCATE COMP "FEE_DATA_OUT[4]" SITE "E18"; -LOCATE COMP "FEE_DATA_OUT[5]" SITE "F16"; -LOCATE COMP "FEE_DATA_OUT[6]" SITE "A16"; -LOCATE COMP "FEE_DATA_OUT[7]" SITE "L3"; -LOCATE COMP "FEE_DATA_OUT[8]" SITE "L16"; -LOCATE COMP "FEE_DATA_OUT[9]" SITE "F20"; -LOCATE COMP "FEE_DATA_WRITE_OUT" SITE "C13"; -LOCATE COMP "FEE_TRG_RELEASE_OUT" SITE "E13"; -LOCATE COMP "LVL1_INVALID_TRG_IN" SITE "R16"; -LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9"; -LOCATE COMP "LVL1_TRG_DATA_VALI_IN_rising" SITE "N18"; -LOCATE COMP "burst" SITE "N16"; -LOCATE COMP "clk" SITE "P3"; -LOCATE COMP "discard" SITE "P16"; -LOCATE COMP "fifo_data_out[0]" SITE "P17"; -LOCATE COMP "fifo_data_out[10]" SITE "K20"; -LOCATE COMP "fifo_data_out[11]" SITE "U2"; -LOCATE COMP "fifo_data_out[12]" SITE "N4"; -LOCATE COMP "fifo_data_out[13]" SITE "J16"; -LOCATE COMP "fifo_data_out[14]" SITE "M4"; -LOCATE COMP "fifo_data_out[15]" SITE "J20"; -LOCATE COMP "fifo_data_out[16]" SITE "P18"; -LOCATE COMP "fifo_data_out[17]" SITE "C15"; -LOCATE COMP "fifo_data_out[18]" SITE "E14"; -LOCATE COMP "fifo_data_out[19]" SITE "L4"; -LOCATE COMP "fifo_data_out[1]" SITE "M3"; -LOCATE COMP "fifo_data_out[20]" SITE "Y2"; -LOCATE COMP "fifo_data_out[21]" SITE "K18"; -LOCATE COMP "fifo_data_out[22]" SITE "W1"; -LOCATE COMP "fifo_data_out[23]" SITE "J18"; -LOCATE COMP "fifo_data_out[24]" SITE "M20"; -LOCATE COMP "fifo_data_out[25]" SITE "J17"; -LOCATE COMP "fifo_data_out[26]" SITE "L20"; -LOCATE COMP "fifo_data_out[27]" SITE "D19"; -LOCATE COMP "fifo_data_out[28]" SITE "G20"; -LOCATE COMP "fifo_data_out[29]" SITE "T1"; -LOCATE COMP "fifo_data_out[2]" SITE "F17"; -LOCATE COMP "fifo_data_out[30]" SITE "E19"; -LOCATE COMP "fifo_data_out[31]" SITE "H16"; -LOCATE COMP "fifo_data_out[3]" SITE "L17"; -LOCATE COMP "fifo_data_out[4]" SITE "F18"; -LOCATE COMP "fifo_data_out[5]" SITE "D17"; -LOCATE COMP "fifo_data_out[6]" SITE "B16"; -LOCATE COMP "fifo_data_out[7]" SITE "N1"; -LOCATE COMP "fifo_data_out[8]" SITE "M18"; -LOCATE COMP "fifo_data_out[9]" SITE "E20"; -LOCATE COMP "fifo_empty1" SITE "N17"; -LOCATE COMP "fifo_rden" SITE "A19"; -LOCATE COMP "finished" SITE "D14"; -LOCATE COMP "hades_buf_drop[0]" SITE "N20"; -LOCATE COMP "hades_buf_drop[1]" SITE "A10"; -LOCATE COMP "hades_buf_drop[2]" SITE "R20"; -LOCATE COMP "hades_buf_drop[3]" SITE "U16"; -LOCATE COMP "hades_buf_finished" SITE "A4"; -LOCATE COMP "hades_buf_out_valid" SITE "C9"; -LOCATE COMP "hades_buf_release" SITE "E7"; -LOCATE COMP "hades_dbg2_coarse[0]" SITE "G5"; -LOCATE COMP "hades_dbg2_coarse[1]" SITE "H3"; -LOCATE COMP "hades_dbg2_coarse[2]" SITE "E3"; -LOCATE COMP "hades_dbg2_coarse[3]" SITE "C2"; -LOCATE COMP "hades_dbg2_coarse[4]" SITE "B6"; -LOCATE COMP "hades_dbg2_coarse[5]" SITE "B1"; -LOCATE COMP "hades_dbg2_coarse[6]" SITE "E5"; -LOCATE COMP "hades_dbg2_coarse[7]" SITE "M5"; -LOCATE COMP "hades_dbg2_coarse[8]" SITE "F1"; -LOCATE COMP "hades_dbg2_out[0]" SITE "J3"; -LOCATE COMP "hades_dbg2_out[10]" SITE "A8"; -LOCATE COMP "hades_dbg2_out[11]" SITE "D6"; -LOCATE COMP "hades_dbg2_out[12]" SITE "B8"; -LOCATE COMP "hades_dbg2_out[13]" SITE "P19"; -LOCATE COMP "hades_dbg2_out[14]" SITE "P1"; -LOCATE COMP "hades_dbg2_out[15]" SITE "C17"; -LOCATE COMP "hades_dbg2_out[16]" SITE "G3"; -LOCATE COMP "hades_dbg2_out[17]" SITE "G1"; -LOCATE COMP "hades_dbg2_out[18]" SITE "J5"; -LOCATE COMP "hades_dbg2_out[19]" SITE "R1"; -LOCATE COMP "hades_dbg2_out[1]" SITE "E2"; -LOCATE COMP "hades_dbg2_out[20]" SITE "K3"; -LOCATE COMP "hades_dbg2_out[21]" SITE "G2"; -LOCATE COMP "hades_dbg2_out[22]" SITE "H4"; -LOCATE COMP "hades_dbg2_out[23]" SITE "J4"; -LOCATE COMP "hades_dbg2_out[24]" SITE "H1"; -LOCATE COMP "hades_dbg2_out[25]" SITE "J1"; -LOCATE COMP "hades_dbg2_out[26]" SITE "K1"; -LOCATE COMP "hades_dbg2_out[27]" SITE "F2"; -LOCATE COMP "hades_dbg2_out[28]" SITE "H2"; -LOCATE COMP "hades_dbg2_out[29]" SITE "A17"; -LOCATE COMP "hades_dbg2_out[2]" SITE "F3"; -LOCATE COMP "hades_dbg2_out[30]" SITE "E16"; -LOCATE COMP "hades_dbg2_out[31]" SITE "R18"; -LOCATE COMP "hades_dbg2_out[3]" SITE "C16"; -LOCATE COMP "hades_dbg2_out[4]" SITE "E4"; -LOCATE COMP "hades_dbg2_out[5]" SITE "C3"; -LOCATE COMP "hades_dbg2_out[6]" SITE "F4"; -LOCATE COMP "hades_dbg2_out[7]" SITE "B3"; -LOCATE COMP "hades_dbg2_out[8]" SITE "E8"; -LOCATE COMP "hades_dbg2_out[9]" SITE "C7"; -LOCATE COMP "hades_discard" SITE "B11"; -LOCATE COMP "hades_drop_cmp_buf[0]" SITE "D3"; -LOCATE COMP "hades_drop_cmp_buf[10]" SITE "B17"; -LOCATE COMP "hades_drop_cmp_buf[11]" SITE "U17"; -LOCATE COMP "hades_drop_cmp_buf[1]" SITE "D9"; -LOCATE COMP "hades_drop_cmp_buf[2]" SITE "A6"; -LOCATE COMP "hades_drop_cmp_buf[3]" SITE "C6"; -LOCATE COMP "hades_drop_cmp_buf[4]" SITE "F5"; -LOCATE COMP "hades_drop_cmp_buf[5]" SITE "C4"; -LOCATE COMP "hades_drop_cmp_buf[6]" SITE "D8"; -LOCATE COMP "hades_drop_cmp_buf[7]" SITE "D5"; -LOCATE COMP "hades_drop_cmp_buf[8]" SITE "B4"; -LOCATE COMP "hades_drop_cmp_buf[9]" SITE "B20"; -LOCATE COMP "hades_drop_cmp_buf_coarse[0]" SITE "A11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[10]" SITE "T17"; -LOCATE COMP "hades_drop_cmp_buf_coarse[11]" SITE "D18"; -LOCATE COMP "hades_drop_cmp_buf_coarse[1]" SITE "A13"; -LOCATE COMP "hades_drop_cmp_buf_coarse[2]" SITE "B10"; -LOCATE COMP "hades_drop_cmp_buf_coarse[3]" SITE "C12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[4]" SITE "E12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[5]" SITE "D12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[6]" SITE "E11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[7]" SITE "D11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[8]" SITE "B13"; -LOCATE COMP "hades_drop_cmp_buf_coarse[9]" SITE "A12"; -LOCATE COMP "hades_drop_cmp_buf_valid" SITE "A7"; -LOCATE COMP "hades_hit_out_i[0]" SITE "E9"; -LOCATE COMP "hades_hit_out_i[1]" SITE "C11"; -LOCATE COMP "hades_hit_out_i[2]" SITE "E6"; -LOCATE COMP "hades_hit_out_i[3]" SITE "D7"; -LOCATE COMP "hades_hit_valid[0]" SITE "A3"; -LOCATE COMP "hades_hit_valid[1]" SITE "B5"; -LOCATE COMP "hades_hit_valid[2]" SITE "A5"; -LOCATE COMP "hades_hit_valid[3]" SITE "C5"; -LOCATE COMP "hades_invalid_dl[0]" SITE "V2"; -LOCATE COMP "hades_invalid_dl[1]" SITE "L5"; -LOCATE COMP "hades_invalid_dl[2]" SITE "K2"; -LOCATE COMP "hades_invalid_dl[3]" SITE "K4"; -LOCATE COMP "hades_lvl1" SITE "E1"; -LOCATE COMP "hades_lvl1_invalid" SITE "W2"; -LOCATE COMP "hades_offset[0]" SITE "D10"; -LOCATE COMP "hades_offset[1]" SITE "C10"; -LOCATE COMP "hades_offset[2]" SITE "E10"; -LOCATE COMP "hades_offset[3]" SITE "D1"; -LOCATE COMP "hades_offset[4]" SITE "C1"; -LOCATE COMP "hades_offset[5]" SITE "D2"; -LOCATE COMP "hades_offset[6]" SITE "A2"; -LOCATE COMP "hades_offset[7]" SITE "B9"; -LOCATE COMP "hades_offset[8]" SITE "B2"; -LOCATE COMP "hades_offset_valid" SITE "D15"; -LOCATE COMP "hades_raw_out_valid" SITE "E15"; -LOCATE COMP "hades_raw_valid_vect[0]" SITE "U20"; -LOCATE COMP "hades_raw_valid_vect[1]" SITE "E17"; -LOCATE COMP "hades_trig" SITE "H5"; -LOCATE COMP "hades_window_end" SITE "C14"; -LOCATE COMP "last_buf_empty" SITE "L18"; -LOCATE COMP "rd_clk" SITE "B12"; -LOCATE COMP "release_out" SITE "A14"; -LOCATE COMP "reset_dc" SITE "C8"; -LOCATE COMP "trig[0]" SITE "R2"; -LOCATE COMP "trig[1]" SITE "T3"; -LOCATE COMP "trig[2]" SITE "T19"; - -#PLL -LOCATE COMP "pll0inst/PLLInst_0" SITE "PLL_BL0" ; - - - - -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:20:03 2021 - diff --git a/impl1/s1_impl1.par b/impl1/s1_impl1.par deleted file mode 100644 index ffbb001..0000000 --- a/impl1/s1_impl1.par +++ /dev/null @@ -1,323 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:19:35 2021 - -/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t -s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset -/home/hadaq/mmichalek/lattice/simplified/promote.xml - - -Preference file: s1_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -2.994 209210 -1.015 9647 48 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 48 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Lattice Place and Route Report for Design "s1_impl1_map.ncd" -Wed Jun 16 09:19:35 2021 - -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf -Preference file: s1_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file s1_impl1_map.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 187/245 76% used - 187/203 92% bonded - IOLOGIC 35/245 14% used - - SLICE 692/21924 3% used - - EBR 4/108 3% used - PLL 1/4 25% used - - -Number of Signals: 1594 -Number of Connections: 3725 - -Pin Constraint Summary: - 7 out of 186 pins locked (3% locked). - -The following 5 signals are selected to use the primary clock routing resources: - pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0) - pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0) - rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0) - pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - - -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -............. -Finished Placer Phase 0. REAL time: 8 secs - -Starting Placer Phase 1. -................. -Placer score = 788909. -Finished Placer Phase 1. REAL time: 24 secs - -Starting Placer Phase 2. -. -Placer score = 774601 -Finished Placer Phase 2. REAL time: 25 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 12 (8%) - GR_PCLK : 0 out of 12 (0%) - PLL : 1 out of 4 (25%) - DCS : 0 out of 2 (0%) - DCC : 0 out of 60 (0%) - CLKDIV : 0 out of 4 (0%) - -Quadrant TL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - - PRIMARY : 5 out of 16 (31%) - -Quadrant TR Clocks: - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8 - - PRIMARY : 2 out of 16 (12%) - -Quadrant BL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - - PRIMARY : 5 out of 16 (31%) - -Quadrant BR Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - - PRIMARY : 5 out of 16 (31%) - -Edge Clocks: - - No edge clock selected. - - ---------------- End of Clock Report --------------- - - -+ -I/O Usage Summary (final): - 187 out of 245 (76.3%) PIO sites used. - 187 out of 203 (92.1%) bonded PIO sites used. - Number of PIO comps: 186; differential: 1. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+------------+------------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | -+----------+----------------+------------+------------+------------+ -| 0 | 27 / 27 (100%) | 2.5V | - | - | -| 1 | 29 / 33 ( 87%) | 2.5V | - | - | -| 2 | 31 / 32 ( 96%) | 2.5V | - | - | -| 3 | 27 / 33 ( 81%) | 2.5V | - | - | -| 6 | 28 / 33 ( 84%) | 2.5V | - | - | -| 7 | 32 / 32 (100%) | 2.5V | - | - | -| 8 | 13 / 13 (100%) | 2.5V | - | - | -+----------+----------------+------------+------------+------------+ - -Total placer CPU time: 24 secs - -Dumping design to file s1_impl1.dir/5_1.ncd. - -0 connections routed; 3725 unrouted. -Starting router resource preassignment - -Completed router resource preassignment. Real time: 39 secs - -Start NBR router at Wed Jun 16 09:20:14 CEST 2021 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021 - -Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021 -Level 1, iteration 1 -21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; -Estimated worst slack/total negative slack: -2.876ns/-158.654ns; real time: 41 secs -Level 2, iteration 1 -46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-159.217ns; real time: 41 secs -Level 3, iteration 1 -167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; -Estimated worst slack/total negative slack: -2.962ns/-163.305ns; real time: 42 secs -Level 4, iteration 1 -81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-177.384ns; real time: 42 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021 -Level 1, iteration 1 -53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-171.398ns; real time: 43 secs -Level 4, iteration 1 -54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 2 -35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 3 -24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 4 -12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 5 -8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 43 secs -Level 4, iteration 6 -5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 44 secs -Level 4, iteration 7 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 8 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 9 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.896ns; real time: 44 secs - -Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 156 (4.19%) - Estimated worst slack : -2.994ns - Timing score : 209210 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -Total CPU time 46 secs -Total REAL time: 47 secs -Completely routed. -End of route. 3725 routed (100.00%); 0 unrouted. - -Generating "par" statistics. - - - The Delay Summary Report - - The SCORE FOR THIS DESIGN is: 284326 - - - The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 - - The AVERAGE CONNECTION DELAY for this design is: 0.79 ( 0.79) - The AVERAGE CONNECTION DELAY on CRITICAL NETS is: 0.00 ( 0.00) - The CLOCK SKEW AVERAGE for this design is: 0.03 - The MAXIMUM PIN DELAY IS: 4.32 ( 4.32) - The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.37 ( 3.37) - - Listing Pin Delays by value: (nsec) - - d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 - --------- --------- --------- --------- --------- --------- - 3725 0 0 0 0 0 - -Hold time timing score: 9, hold timing errors: 18 - - -Timing score: 209210 - -Dumping design to file s1_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -2.994 -PAR_SUMMARY::Timing score> = 209.210 -PAR_SUMMARY::Worst slack> = -1.015 -PAR_SUMMARY::Timing score> = 9.647 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 48 secs -Total REAL time to completion: 48 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. diff --git a/impl1/s1_impl1.prf b/impl1/s1_impl1.prf deleted file mode 100644 index 7f26db5..0000000 --- a/impl1/s1_impl1.prf +++ /dev/null @@ -1,196 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.11.2.446 -- WARNING: Map write only section -- Wed Jun 16 09:19:31 2021 - -SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG INBUF=OFF ; -PGROUP "tdc0" BBOX 1 4 DEVSIZE - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271"; -LOCATE PGROUP "tdc0" SITE "R68C14D" ; -PGROUP "tdc22" BBOX 1 4 DEVSIZE - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351"; -LOCATE PGROUP "tdc22" SITE "R66C41D" ; -PGROUP "tdc3" BBOX 1 4 DEVSIZE - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431"; -LOCATE PGROUP "tdc3" SITE "R66C49D" ; -PGROUP "lvl1_tdc" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514"; -LOCATE PGROUP "lvl1_tdc" SITE "R25C3D" ; -PGROUP "hades_dec_pos" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732"; -LOCATE PGROUP "hades_dec_pos" SITE "R27C2D" ; -PGROUP "hades_dec_neg" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729"; -LOCATE PGROUP "hades_dec_neg" SITE "R30C2D" ; -PGROUP "hades_tdc_pos" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619"; -LOCATE PGROUP "hades_tdc_pos" SITE "R28C3D" ; -PGROUP "hades_tdc_neg" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627"; -LOCATE PGROUP "hades_tdc_neg" SITE "R29C3D" ; -PGROUP "lvl1_pad" BBOX 1 1 DEVSIZE - COMP "SLICE_743"; -LOCATE PGROUP "lvl1_pad" SITE "R25C2D" ; -PGROUP "gate2" BBOX 1 1 DEVSIZE - COMP "SLICE_745"; -LOCATE PGROUP "gate2" SITE "R67C41D" ; -PGROUP "trig3" BBOX 1 1 DEVSIZE - COMP "SLICE_746"; -LOCATE PGROUP "trig3" SITE "R67C49D" ; -LOCATE COMP "clk" SITE "P3" ; -LOCATE COMP "hades_lvl1" SITE "E1" ; -LOCATE COMP "hades_trig" SITE "H5" ; -LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9" ; -LOCATE COMP "trig[2]" SITE "T19" ; -LOCATE COMP "trig[1]" SITE "T3" ; -LOCATE COMP "trig[0]" SITE "R2" ; -FREQUENCY NET "clk_c" 100.000000 MHz ; -FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; -FREQUENCY PORT "clk" 100.000000 MHz ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK NET "trig*" ; -BLOCK NET "reset*" ; -FREQUENCY NET "pll_clks*" 300.000000 MHz ; -PROHIBIT SITE "IOL_B18A" ; -PROHIBIT SITE "IOL_B15A" ; -PROHIBIT SITE "IOL_L29C" ; -PROHIBIT SITE "IOL_L29B" ; -PROHIBIT SITE "IOL_L29D" ; -COMMERCIAL ; diff --git a/impl1/s1_impl1.pt b/impl1/s1_impl1.pt deleted file mode 100644 index 7850c7d..0000000 --- a/impl1/s1_impl1.pt +++ /dev/null @@ -1,10 +0,0 @@ --v -10 - - - --fullname --gt --sethld --sp 8 --sphld m diff --git a/impl1/s1_impl1.srd b/impl1/s1_impl1.srd deleted file mode 100644 index 36d89c352dc3d8acc38db1134737e0a7539464fa..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 167663 zcmZshRZtvU(590>AcP>n-QC?Kf#5E|CAc%VOMu|+4#9&nxVzin4g(DCFuj^uk}039DyzYcJ(oQuFD9jNn%Esv^0L8Qg41$w@$u9pB^HBlxCPFkL0yr^2}L;z zSEW3Pa;ss%m<_*NxHFf~E0b_NASk=bkM1bgy!o6&8v6zmM7MQMb-^qMpmEm0{r+h+kx|3S409_2JCDd z76-h)%+NmR3WYn8vr=C*`G31w3eK#Fb|ef|@}Q+t|Mo@h{6@d@7j}Sn-};ED|DMMz z7rOC!XzF;!W8lY~fI12jB*3QUBeJ|?{N?8Fw9E(avMOyvRZOgn<=Z!zpvoyRkrOaI8@QWGrs}?hl%u zSgTm;4<|`XIX0;)y!<&iocz~zyPPj9)(V2te}aNQr{jjl5d4+n>`#U1Zhq4t`vTiZ z)Mq>v!Y7zKJBPg}hbrKxdhDo-c}&A=FE4IE2R|qeoJoPQBEE#=bs??jahJe%idL2RQ9y*-Wyv>h|5}XlV`0D z#!%?+C}A;nFIoDM)-3i0J~Y2JuL1$$wQpr~HC)^#C&=R6GWG=@8#u1330t{o-#ZXZ zB@G%pL?T7))6En9h~(o=HZRZ>YyCT@J^j-{RBTIlY0%s4f}C}9=aSt7f!}=7Wx7E3 zX_oENChd51>35PR&erV64`VLlR7!UJ=NOac#)&1pH zR^v6Bw>8!jLTUq76J-}v$Y@%_66|~>uhrsGeLzdP9FtWqEF3xq;VpV>1>?n>jpa)+w;^t_}R3dOQ-Tqo60 z&Y~7lbl&P&-l{eBL6o#r_eO41dsgj(B=wC)0R;k0G;@F}*7CX{)U>P0kZQxxeS=@? zpjc;RV~|5g$uMcmjWjvO9~HEfByZp$Q&7-acter#-#~?vwUh5`oNzPtHzy4LzT|F- z-Cq5?$3)%}bCTD?y0o5#uy)T66Hz2!{-qXN-6La^Oi%j8hm);e4D&fz{{bEIc~rpc`p)*iy{l5# zGw5YaXUBA(&dvJ(%p{e|VYMQ`?vGM@q%Q3)vGC>0U;dCU@2gMsZ@j@%|8GY;WimYy zGumq6{M5-=doy4pZ*O>2Q!qrD)K>iS7ruh<1*d(U z8x?4cC!3j>5n+C-)fbk4ct>@k{aYQvFjNvUU5UboM^kg=QCu=W1RINUmoI@o}NOP`*s+Cs?9nDe+ z(Kf~oxswljgy86P%?8FtYg4JP+MInte(X?L&UT4b)}r)_Zl#I8f@tV4!;jnNN$0MM za%zp6{N-ITA9cPdl~Sl1M3IJ$cgNQaN>51+HazvsW>5h*v}naYUnDcRTRTd+rXeOq zeLWd26T5b$ssjcHX&tB%A217n&QfQpgUSh!sv?UFKVWn-nT{CxGlA;)l8DZS1qXFb zbBET2;Y&9+_*yRQH)0L+LXo{vFUvue?FtS20;hk~`JWY+eJ8(((u$K3f{R55--t
    BITGEN: Bitstream Generator Diamond (64-bit) 3.11.2.446
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-Wed May 26 19:56:50 2021
-
-
-Command: bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g DisableUES:FALSE -g ES:No -e -s /home/hadaq/mmichalek/lattice/simplified/s1.sec -k /home/hadaq/mmichalek/lattice/simplified/s1.bek -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
-
-Loading design for application Bitgen from file s1_impl1.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: 8
-Loading device for application Bitgen from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from s1_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                        CfgMode  |                      Disable**  |
-+---------------------------------+---------------------------------+
-|                        DONE_EX  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                        DONE_OD  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                          2.4**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                    CONFIG_MODE  |                         JTAG**  |
-+---------------------------------+---------------------------------+
-|                        WAKE_UP  |                           21**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                             ES  |                           No**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                     DisableUES  |                        FALSE**  |
-+---------------------------------+---------------------------------+
-|            SLAVE_PARALLEL_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                      DONE_PULL  |                           ON**  |
-+---------------------------------+---------------------------------+
-|               CONFIG_IOVOLTAGE  |                          2.5**  |
-+---------------------------------+---------------------------------+
-|                        TRANSFR  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 10.27.
- 
-Saving bit stream in "s1_impl1.bit".
-Total CPU Time: 11 secs 
-Total REAL Time: 12 secs 
-Peak Memory Usage: 576 MB
-
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    - - diff --git a/impl1/s1_impl1_cck.rpt b/impl1/s1_impl1_cck.rpt deleted file mode 100644 index 298f602..0000000 --- a/impl1/s1_impl1_cck.rpt +++ /dev/null @@ -1,274 +0,0 @@ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 - -# Written on Wed Jun 16 09:19:18 2021 - -##### DESIGN INFO ####################################################### - -Top View: "top_tf" -Constraint File(s): (none) - - - - -##### SUMMARY ############################################################ - -Found 0 issues in 0 out of 0 constraints - - -##### DETAILS ############################################################ - - - -Clock Relationships -******************* - -Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System pll0|CLKOS3_inferred_clock | 5.000 | No paths | No paths | No paths -System top_tf|rd_clk | 5.000 | No paths | No paths | No paths -pll0|CLKOS3_inferred_clock System | 5.000 | No paths | No paths | 5.000 -pll0|CLKOS3_inferred_clock pll0|CLKOS3_inferred_clock | 5.000 | 5.000 | 2.500 | 2.500 -pll0|CLKOS3_inferred_clock top_tf|rd_clk | Diff grp | No paths | No paths | No paths -pll0|CLKOP_inferred_clock pll0|CLKOS3_inferred_clock | No paths | Diff grp | Diff grp | No paths -pll0|CLKOP_inferred_clock pll0|CLKOP_inferred_clock | 5.000 | 5.000 | No paths | No paths -pll0|CLKOS_inferred_clock pll0|CLKOS3_inferred_clock | No paths | Diff grp | Diff grp | No paths -pll0|CLKOS_inferred_clock pll0|CLKOS_inferred_clock | 5.000 | 5.000 | No paths | No paths -pll0|CLKOS2_inferred_clock pll0|CLKOS3_inferred_clock | No paths | Diff grp | Diff grp | No paths -pll0|CLKOS2_inferred_clock pll0|CLKOS2_inferred_clock | 5.000 | 5.000 | No paths | No paths -top_tf|rd_clk System | 5.000 | No paths | No paths | No paths -top_tf|rd_clk pll0|CLKOS3_inferred_clock | Diff grp | No paths | No paths | No paths -top_tf|rd_clk top_tf|rd_clk | 5.000 | No paths | No paths | No paths -========================================================================================================================================================================= - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - -Unconstrained Start/End Points -****************************** - -p:FEE_DATAFINISHED_OUT -p:FEE_DATA_OUT[0] -p:FEE_DATA_OUT[1] -p:FEE_DATA_OUT[2] -p:FEE_DATA_OUT[3] -p:FEE_DATA_OUT[4] -p:FEE_DATA_OUT[5] -p:FEE_DATA_OUT[6] -p:FEE_DATA_OUT[7] -p:FEE_DATA_OUT[8] -p:FEE_DATA_OUT[9] -p:FEE_DATA_OUT[10] -p:FEE_DATA_OUT[11] -p:FEE_DATA_OUT[12] -p:FEE_DATA_OUT[13] -p:FEE_DATA_OUT[14] -p:FEE_DATA_OUT[15] -p:FEE_DATA_OUT[16] -p:FEE_DATA_OUT[17] -p:FEE_DATA_OUT[18] -p:FEE_DATA_OUT[19] -p:FEE_DATA_OUT[20] -p:FEE_DATA_OUT[21] -p:FEE_DATA_OUT[22] -p:FEE_DATA_OUT[23] -p:FEE_DATA_OUT[24] -p:FEE_DATA_OUT[25] -p:FEE_DATA_OUT[26] -p:FEE_DATA_OUT[27] -p:FEE_DATA_OUT[28] -p:FEE_DATA_OUT[29] -p:FEE_DATA_OUT[30] -p:FEE_DATA_OUT[31] -p:FEE_DATA_WRITE_OUT -p:FEE_TRG_RELEASE_OUT -p:LVL1_INVALID_TRG_IN -p:LVL1_TRG_DATA_VALID_IN -p:LVL1_TRG_DATA_VALI_IN_rising -p:burst -p:clk -p:discard -p:fifo_data_out[0] -p:fifo_data_out[1] -p:fifo_data_out[2] -p:fifo_data_out[3] -p:fifo_data_out[4] -p:fifo_data_out[5] -p:fifo_data_out[6] -p:fifo_data_out[7] -p:fifo_data_out[8] -p:fifo_data_out[9] -p:fifo_data_out[10] -p:fifo_data_out[11] -p:fifo_data_out[12] -p:fifo_data_out[13] -p:fifo_data_out[14] -p:fifo_data_out[15] -p:fifo_data_out[16] -p:fifo_data_out[17] -p:fifo_data_out[18] -p:fifo_data_out[19] -p:fifo_data_out[20] -p:fifo_data_out[21] -p:fifo_data_out[22] -p:fifo_data_out[23] -p:fifo_data_out[24] -p:fifo_data_out[25] -p:fifo_data_out[26] -p:fifo_data_out[27] -p:fifo_data_out[28] -p:fifo_data_out[29] -p:fifo_data_out[30] -p:fifo_data_out[31] -p:fifo_empty1 -p:fifo_rden -p:finished -p:hades_buf_drop[0] -p:hades_buf_drop[1] -p:hades_buf_drop[2] -p:hades_buf_drop[3] -p:hades_buf_finished -p:hades_buf_out_valid -p:hades_buf_release -p:hades_dbg2_coarse[0] -p:hades_dbg2_coarse[1] -p:hades_dbg2_coarse[2] -p:hades_dbg2_coarse[3] -p:hades_dbg2_coarse[4] -p:hades_dbg2_coarse[5] -p:hades_dbg2_coarse[6] -p:hades_dbg2_coarse[7] -p:hades_dbg2_coarse[8] -p:hades_dbg2_out[0] -p:hades_dbg2_out[1] -p:hades_dbg2_out[2] -p:hades_dbg2_out[3] -p:hades_dbg2_out[4] -p:hades_dbg2_out[5] -p:hades_dbg2_out[6] -p:hades_dbg2_out[7] -p:hades_dbg2_out[8] -p:hades_dbg2_out[9] -p:hades_dbg2_out[10] -p:hades_dbg2_out[11] -p:hades_dbg2_out[12] -p:hades_dbg2_out[13] -p:hades_dbg2_out[14] -p:hades_dbg2_out[15] -p:hades_dbg2_out[16] -p:hades_dbg2_out[17] -p:hades_dbg2_out[18] -p:hades_dbg2_out[19] -p:hades_dbg2_out[20] -p:hades_dbg2_out[21] -p:hades_dbg2_out[22] -p:hades_dbg2_out[23] -p:hades_dbg2_out[24] -p:hades_dbg2_out[25] -p:hades_dbg2_out[26] -p:hades_dbg2_out[27] -p:hades_dbg2_out[28] -p:hades_dbg2_out[29] -p:hades_dbg2_out[30] -p:hades_dbg2_out[31] -p:hades_discard -p:hades_drop_cmp_buf[0] -p:hades_drop_cmp_buf[1] -p:hades_drop_cmp_buf[2] -p:hades_drop_cmp_buf[3] -p:hades_drop_cmp_buf[4] -p:hades_drop_cmp_buf[5] -p:hades_drop_cmp_buf[6] -p:hades_drop_cmp_buf[7] -p:hades_drop_cmp_buf[8] -p:hades_drop_cmp_buf[9] -p:hades_drop_cmp_buf[10] -p:hades_drop_cmp_buf[11] -p:hades_drop_cmp_buf_coarse[0] -p:hades_drop_cmp_buf_coarse[1] -p:hades_drop_cmp_buf_coarse[2] -p:hades_drop_cmp_buf_coarse[3] -p:hades_drop_cmp_buf_coarse[4] -p:hades_drop_cmp_buf_coarse[5] -p:hades_drop_cmp_buf_coarse[6] -p:hades_drop_cmp_buf_coarse[7] -p:hades_drop_cmp_buf_coarse[8] -p:hades_drop_cmp_buf_coarse[9] -p:hades_drop_cmp_buf_coarse[10] -p:hades_drop_cmp_buf_coarse[11] -p:hades_drop_cmp_buf_valid -p:hades_hit_out_i[0] -p:hades_hit_out_i[1] -p:hades_hit_out_i[2] -p:hades_hit_out_i[3] -p:hades_hit_valid[0] -p:hades_hit_valid[1] -p:hades_hit_valid[2] -p:hades_hit_valid[3] -p:hades_invalid_dl[0] -p:hades_invalid_dl[1] -p:hades_invalid_dl[2] -p:hades_invalid_dl[3] -p:hades_lvl1 -p:hades_lvl1_invalid -p:hades_offset[0] -p:hades_offset[1] -p:hades_offset[2] -p:hades_offset[3] -p:hades_offset[4] -p:hades_offset[5] -p:hades_offset[6] -p:hades_offset[7] -p:hades_offset[8] -p:hades_offset_valid -p:hades_raw_out_valid -p:hades_raw_valid_vect[0] -p:hades_raw_valid_vect[1] -p:hades_trig -p:hades_window_end -p:last_buf_empty -p:release_out -p:reset_dc -p:trig[0] -p:trig[1] -p:trig[2] - - -Inapplicable constraints -************************ - -(none) - - -Applicable constraints with issues -********************************** - -(none) - - -Constraints with matching wildcard expressions -********************************************** - -(none) - - -Library Report -************** - - -# End of Constraint Checker Report diff --git a/impl1/s1_impl1_cck.rpt.db b/impl1/s1_impl1_cck.rpt.db deleted file mode 100644 index 33612a25abcc09ccda948d7859cc45d1eae869ad..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#y$ZrW3Y@Gy=5 diff --git a/impl1/s1_impl1_iotiming.html b/impl1/s1_impl1_iotiming.html deleted file mode 100644 index c3584bb..0000000 --- a/impl1/s1_impl1_iotiming.html +++ /dev/null @@ -1,269 +0,0 @@ - -I/O Timing Report - - -
    I/O Timing Report
-Loading design for application iotiming from file s1_impl1.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: 9
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-Loading design for application iotiming from file s1_impl1.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: M
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-// Design: top_tf
-// Package: CABGA381
-// ncd File: s1_impl1.ncd
-// Version: Diamond (64-bit) 3.11.2.446
-// Written on Wed Jun 16 09:20:37 2021
-// M: Minimum Performance Grade
-// iotiming s1_impl1.ncd s1_impl1.prf -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 9, 8):
-
-// Input Setup and Hold Times
-
-Port                   Clock  Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-LVL1_INVALID_TRG_IN    rd_clk R    -0.242      M       2.049     8
-LVL1_TRG_DATA_VALID_IN rd_clk R    -0.242      M       2.049     8
-hades_lvl1             clk    F     2.162      8       1.169     M
-hades_lvl1_invalid     clk    R    -0.529      8       1.138     M
-hades_trig             clk    F     2.282      8       0.712     M
-
-
-// Clock to Output Delay
-
-Port                         Clock  Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-FEE_DATAFINISHED_OUT         rd_clk R     5.311         8        2.067          M
-FEE_DATA_OUT[0]              rd_clk R     8.637         8        5.249          M
-FEE_DATA_OUT[10]             rd_clk R     7.965         8        4.919          M
-FEE_DATA_OUT[11]             rd_clk R     8.348         8        5.096          M
-FEE_DATA_OUT[12]             rd_clk R     8.295         8        5.082          M
-FEE_DATA_OUT[13]             rd_clk R     8.705         8        5.299          M
-FEE_DATA_OUT[14]             rd_clk R     8.495         8        5.173          M
-FEE_DATA_OUT[15]             rd_clk R     8.386         8        5.119          M
-FEE_DATA_OUT[16]             rd_clk R     9.036         8        5.453          M
-FEE_DATA_OUT[17]             rd_clk R     8.626         8        5.229          M
-FEE_DATA_OUT[18]             rd_clk R     8.622         8        5.246          M
-FEE_DATA_OUT[19]             rd_clk R     8.108         8        4.987          M
-FEE_DATA_OUT[1]              rd_clk R     8.763         8        5.277          M
-FEE_DATA_OUT[20]             rd_clk R     8.695         8        5.268          M
-FEE_DATA_OUT[21]             rd_clk R     8.276         8        5.092          M
-FEE_DATA_OUT[22]             rd_clk R     8.532         8        5.199          M
-FEE_DATA_OUT[23]             rd_clk R     8.304         8        5.100          M
-FEE_DATA_OUT[24]             rd_clk R     8.280         8        5.083          M
-FEE_DATA_OUT[25]             rd_clk R     8.697         8        5.287          M
-FEE_DATA_OUT[26]             rd_clk R     8.529         8        5.194          M
-FEE_DATA_OUT[27]             rd_clk R     8.687         8        5.296          M
-FEE_DATA_OUT[28]             rd_clk R     8.632         8        5.249          M
-FEE_DATA_OUT[29]             rd_clk R     8.555         8        5.214          M
-FEE_DATA_OUT[2]              rd_clk R     8.715         8        5.294          M
-FEE_DATA_OUT[30]             rd_clk R     8.514         8        5.199          M
-FEE_DATA_OUT[31]             rd_clk R     8.519         8        5.194          M
-FEE_DATA_OUT[3]              rd_clk R     8.357         8        5.108          M
-FEE_DATA_OUT[4]              rd_clk R     8.716         8        5.293          M
-FEE_DATA_OUT[5]              rd_clk R     8.884         8        5.392          M
-FEE_DATA_OUT[6]              rd_clk R     8.803         8        5.322          M
-FEE_DATA_OUT[7]              rd_clk R     8.785         8        5.315          M
-FEE_DATA_OUT[8]              rd_clk R     8.395         8        5.107          M
-FEE_DATA_OUT[9]              rd_clk R     8.309         8        5.083          M
-FEE_DATA_WRITE_OUT           rd_clk R     5.311         8        2.067          M
-FEE_TRG_RELEASE_OUT          rd_clk R     5.311         8        2.067          M
-LVL1_TRG_DATA_VALI_IN_rising rd_clk R     5.988         8        2.652          M
-burst                        rd_clk R     5.985         8        2.605          M
-discard                      rd_clk R     5.080         8        2.333          M
-fifo_data_out[0]             rd_clk R     8.408         8        5.132          M
-fifo_data_out[10]            rd_clk R     7.965         8        4.919          M
-fifo_data_out[11]            rd_clk R     8.348         8        5.096          M
-fifo_data_out[12]            rd_clk R     8.448         8        5.158          M
-fifo_data_out[13]            rd_clk R     8.654         8        5.273          M
-fifo_data_out[14]            rd_clk R     8.648         8        5.249          M
-fifo_data_out[15]            rd_clk R     7.943         8        4.904          M
-fifo_data_out[16]            rd_clk R     9.189         8        5.529          M
-fifo_data_out[17]            rd_clk R     8.779         8        5.305          M
-fifo_data_out[18]            rd_clk R     9.117         8        5.486          M
-fifo_data_out[19]            rd_clk R     8.108         8        4.987          M
-fifo_data_out[1]             rd_clk R     8.763         8        5.277          M
-fifo_data_out[20]            rd_clk R     8.873         8        5.361          M
-fifo_data_out[21]            rd_clk R     8.150         8        5.026          M
-fifo_data_out[22]            rd_clk R     8.710         8        5.292          M
-fifo_data_out[23]            rd_clk R     8.304         8        5.100          M
-fifo_data_out[24]            rd_clk R     8.545         8        5.205          M
-fifo_data_out[25]            rd_clk R     8.697         8        5.287          M
-fifo_data_out[26]            rd_clk R     8.682         8        5.269          M
-fifo_data_out[27]            rd_clk R     8.687         8        5.296          M
-fifo_data_out[28]            rd_clk R     8.785         8        5.324          M
-fifo_data_out[29]            rd_clk R     8.555         8        5.214          M
-fifo_data_out[2]             rd_clk R     8.715         8        5.294          M
-fifo_data_out[30]            rd_clk R     8.514         8        5.199          M
-fifo_data_out[31]            rd_clk R     8.672         8        5.269          M
-fifo_data_out[3]             rd_clk R     8.357         8        5.108          M
-fifo_data_out[4]             rd_clk R     8.716         8        5.293          M
-fifo_data_out[5]             rd_clk R     9.037         8        5.468          M
-fifo_data_out[6]             rd_clk R     8.957         8        5.398          M
-fifo_data_out[7]             rd_clk R     8.963         8        5.408          M
-fifo_data_out[8]             rd_clk R     8.395         8        5.107          M
-fifo_data_out[9]             rd_clk R     8.462         8        5.159          M
-fifo_empty1                  clk    R     6.338         8        3.901          M
-fifo_rden                    rd_clk R     9.015         8        4.309          M
-finished                     rd_clk R     5.699         8        2.640          M
-hades_buf_drop[1]            clk    R     4.373         8        2.516          M
-hades_buf_finished           clk    R     5.004         8        3.223          M
-hades_buf_out_valid          clk    R     4.373         8        2.516          M
-hades_buf_release            clk    R     5.056         8        3.233          M
-hades_dbg2_coarse[0]         clk    R     5.517         8        3.457          M
-hades_dbg2_coarse[1]         clk    R     5.565         8        3.485          M
-hades_dbg2_coarse[2]         clk    R     6.422         8        3.891          M
-hades_dbg2_coarse[3]         clk    R     5.749         8        3.576          M
-hades_dbg2_coarse[4]         clk    R     6.730         8        4.066          M
-hades_dbg2_coarse[5]         clk    R     6.629         8        3.989          M
-hades_dbg2_coarse[6]         clk    R     6.270         8        3.843          M
-hades_dbg2_coarse[7]         clk    R     7.034         8        4.220          M
-hades_dbg2_coarse[8]         clk    R     6.138         8        3.750          M
-hades_dbg2_out[0]            clk    R     4.373         8        2.516          M
-hades_dbg2_out[10]           clk    R     5.455         8        3.421          M
-hades_dbg2_out[11]           clk    R     5.684         8        3.543          M
-hades_dbg2_out[12]           clk    R     5.446         8        3.434          M
-hades_dbg2_out[16]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[17]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[18]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[1]            clk    R     4.373         8        2.516          M
-hades_dbg2_out[20]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[21]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[22]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[23]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[24]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[25]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[26]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[27]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[28]           clk    R     4.373         8        2.516          M
-hades_dbg2_out[2]            clk    R     4.373         8        2.516          M
-hades_dbg2_out[4]            clk    R     5.601         8        3.511          M
-hades_dbg2_out[5]            clk    R     5.147         8        3.282          M
-hades_dbg2_out[6]            clk    R     5.274         8        3.349          M
-hades_dbg2_out[7]            clk    R     5.147         8        3.282          M
-hades_dbg2_out[8]            clk    R     5.245         8        3.329          M
-hades_dbg2_out[9]            clk    R     5.236         8        3.332          M
-hades_discard                clk    R     5.876         8        3.609          M
-hades_drop_cmp_buf[0]        clk    R     4.849         8        3.145          M
-hades_drop_cmp_buf[1]        clk    R     5.102         8        3.255          M
-hades_drop_cmp_buf[2]        clk    R     5.292         8        3.360          M
-hades_drop_cmp_buf[3]        clk    R     5.275         8        3.342          M
-hades_drop_cmp_buf[4]        clk    R     5.205         8        3.328          M
-hades_drop_cmp_buf[5]        clk    R     5.149         8        3.303          M
-hades_drop_cmp_buf[6]        clk    R     4.937         8        3.174          M
-hades_drop_cmp_buf[7]        clk    R     5.330         8        3.397          M
-hades_drop_cmp_buf[8]        clk    R     5.190         8        3.317          M
-hades_drop_cmp_buf_coarse[0] clk    R     5.257         8        3.329          M
-hades_drop_cmp_buf_coarse[1] clk    R     5.665         8        3.523          M
-hades_drop_cmp_buf_coarse[2] clk    R     5.260         8        3.330          M
-hades_drop_cmp_buf_coarse[3] clk    R     5.770         8        3.582          M
-hades_drop_cmp_buf_coarse[4] clk    R     5.512         8        3.459          M
-hades_drop_cmp_buf_coarse[5] clk    R     5.675         8        3.526          M
-hades_drop_cmp_buf_coarse[6] clk    R     5.490         8        3.439          M
-hades_drop_cmp_buf_coarse[7] clk    R     5.333         8        3.360          M
-hades_drop_cmp_buf_coarse[8] clk    R     5.655         8        3.532          M
-hades_drop_cmp_buf_coarse[9] clk    R     5.740         8        3.562          M
-hades_drop_cmp_buf_valid     clk    R     5.087         8        3.238          M
-hades_hit_out_i[0]           clk    R     5.277         8        3.312          M
-hades_hit_out_i[1]           clk    R     5.091         8        3.241          M
-hades_hit_out_i[2]           clk    R     5.226         8        3.328          M
-hades_hit_out_i[3]           clk    R     5.455         8        3.423          M
-hades_hit_valid[0]           clk    R     4.969         8        3.196          M
-hades_hit_valid[1]           clk    R     4.807         8        3.119          M
-hades_hit_valid[2]           clk    R     4.969         8        3.196          M
-hades_hit_valid[3]           clk    R     4.695         8        3.062          M
-hades_invalid_dl[0]          clk    R     4.420         8        2.938          M
-hades_invalid_dl[1]          clk    R     5.004         8        3.220          M
-hades_invalid_dl[2]          clk    R     4.671         8        3.052          M
-hades_invalid_dl[3]          clk    R     4.976         8        3.211          M
-hades_offset[0]              clk    R     4.373         8        2.516          M
-hades_offset[1]              clk    R     4.373         8        2.516          M
-hades_offset[2]              clk    R     4.373         8        2.516          M
-hades_offset[3]              clk    R     4.373         8        2.516          M
-hades_offset[4]              clk    R     4.373         8        2.516          M
-hades_offset[5]              clk    R     4.373         8        2.516          M
-hades_offset[6]              clk    R     4.373         8        2.516          M
-hades_offset[7]              clk    R     4.373         8        2.516          M
-hades_offset[8]              clk    R     4.373         8        2.516          M
-hades_offset_valid           clk    R     6.416         8        3.925          M
-hades_raw_out_valid          clk    R     4.373         8        2.516          M
-hades_window_end             clk    R     6.286         8        3.867          M
-last_buf_empty               rd_clk R     7.396         8        3.504          M
-release_out                  rd_clk R     6.079         8        2.759          M
-WARNING: you must also run trce with hold speed: 8
-WARNING: you must also run trce with setup speed: M
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    - - diff --git a/impl1/s1_impl1_lattice.synproj b/impl1/s1_impl1_lattice.synproj deleted file mode 100644 index fa95682..0000000 --- a/impl1/s1_impl1_lattice.synproj +++ /dev/null @@ -1,41 +0,0 @@ --a "ECP5UM5G" --d LFE5UM5G-45F --t CABGA381 --s 8 --frequency 200 --optimization_goal Timing --bram_utilization 100 --ramstyle Auto --romstyle auto --dsp_utilization 100 --use_dsp 1 --use_carry_chain 1 --carry_chain_length 0 --force_gsr Auto --resource_sharing 0 --propagate_constants 1 --remove_duplicate_regs 1 --mux_style Auto --max_fanout 1000 --fsm_encoding_style Auto --twr_paths 3 --fix_gated_clocks 1 --loop_limit 1950 - - - --use_io_insertion 1 --resolve_mixed_drivers 0 --use_io_reg auto - --ifd --lpf 1 --p "/home/hadaq/mmichalek/lattice/simplified" --ver "/home/hadaq/mmichalek/lattice/simplified/top.v" --top top - - --p "/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data" "/home/hadaq/mmichalek/lattice/simplified/impl1" "/home/hadaq/mmichalek/lattice/simplified" - --ngd "s1_impl1.ngd" - diff --git a/impl1/s1_impl1_map.asd b/impl1/s1_impl1_map.asd deleted file mode 100644 index d2dd4e1..0000000 --- a/impl1/s1_impl1_map.asd +++ /dev/null @@ -1,96 +0,0 @@ -[ActiveSupport MAP] -Device = LFE5UM5G-45F; -Package = CABGA381; -Performance = 8; -LUTS_avail = 43848; -LUTS_used = 630; -FF_avail = 44051; -FF_used = 934; -INPUT_LVCMOS25 = 10; -INPUT_LVDS = 1; -OUTPUT_LVCMOS25 = 175; -IO_avail = 203; -IO_used = 187; -EBR_avail = 108; -EBR_used = 4; -; -; start of DSP statistics -MULT18X18D = 0; -MULT9X9D = 0; -ALU54B = 0; -ALU24B = 0; -PRADD18A = 0; -PRADD9A = 0; -DSP_MULT_avail = 144; -DSP_MULT_used = 0; -DSP_ALU_avail = 72; -DSP_ALU_used = 0; -DSP_PRADD_avail = 144; -DSP_PRADD_used = 0; -; end of DSP statistics -; -; Begin EBR Section -Instance_Name = fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1; -Type = PDPW16KD; -Width = 32; -Depth_R = 512; -Depth_W = 512; -REGMODE = NOREG; -RESETMODE = ASYNC; -ASYNC_RESET_RELEASE = SYNC; -GSR = DISABLED; -MEM_LPC_FILE = fifo40_dc.lpc; -Instance_Name = genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0; -Type = PDPW16KD; -Width = 24; -Depth_R = 512; -Depth_W = 512; -REGMODE = NOREG; -RESETMODE = SYNC; -ASYNC_RESET_RELEASE = SYNC; -GSR = DISABLED; -MEM_LPC_FILE = fifo32dc.lpc; -Instance_Name = genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0; -Type = PDPW16KD; -Width = 24; -Depth_R = 512; -Depth_W = 512; -REGMODE = NOREG; -RESETMODE = SYNC; -ASYNC_RESET_RELEASE = SYNC; -GSR = DISABLED; -MEM_LPC_FILE = fifo32dc.lpc; -Instance_Name = genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0; -Type = PDPW16KD; -Width = 24; -Depth_R = 512; -Depth_W = 512; -REGMODE = NOREG; -RESETMODE = SYNC; -ASYNC_RESET_RELEASE = SYNC; -GSR = DISABLED; -MEM_LPC_FILE = fifo32dc.lpc; -; End EBR Section -; Begin PLL Section -Instance_Name = pll0inst/PLLInst_0; -Type = EHXPLLL; -CLKOP_Post_Divider_A_Input = DIVA; -CLKOS_Post_Divider_B_Input = DIVB; -CLKOS2_Post_Divider_C_Input = DIVC; -CLKOS3_Post_Divider_D_Input = DIVD; -FB_MODE = CLKOP; -CLKI_Divider = 1; -CLKFB_Divider = 3; -CLKOP_Divider = 2; -CLKOS_Divider = 2; -CLKOS2_Divider = 2; -CLKOS3_Divider = 2; -CLKOP_Desired_Phase_Shift(degree) = 0; -CLKOP_Trim_Option_Rising/Falling = FALLING; -CLKOP_Trim_Option_Delay = 0; -CLKOS_Desired_Phase_Shift(degree) = 45; -CLKOS_Trim_Option_Rising/Falling = FALLING; -CLKOS_Trim_Option_Delay = 0; -CLKOS2_Desired_Phase_Shift(degree) = 90; -CLKOS3_Desired_Phase_Shift(degree) = 135; -; End PLL Section diff --git a/impl1/s1_impl1_map.cam b/impl1/s1_impl1_map.cam deleted file mode 100644 index 439d2ae..0000000 --- a/impl1/s1_impl1_map.cam +++ /dev/null @@ -1,473 +0,0 @@ -[ START MERGED ] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty[2] -genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN pll_clks[3] -genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.CN pll_clks[2] -genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.CN pll_clks[1] -genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.CN pll_clks[0] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty[1] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 fifo_empty1_c -fifo_colector_inst/fifo40_inst/invout_0 last_buf_empty_c -fifo_colector_inst/fifo40_inst/invout_1 fifo_colector_inst/fifo40_inst/Full -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg hades_trig_c -reset_dl_i[2] reset_dl[2] -[ END MERGED ] -[ START CLIPPED ] -GND -VCC -hades_tdc_bundle_inst/VCC -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC -fifo_colector_inst/fifo40_inst/VCC -fifo_colector_inst/fifo40_inst/rRst -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst -pll0inst/CLKINTFB -pll0inst/REFCLK -pll0inst/INTLOCK -pll0inst/LOCK -hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1 -hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0 -hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1 -hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0 -hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1 -hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0 -hades_tdc_bundle_inst/N_73 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0_COUT -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0_COUT -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0_S1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0_S0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2 -hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1 -hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT -fifo_colector_inst/fifo40_inst/a1_S1_2 -fifo_colector_inst/fifo40_inst/a1_COUT_2 -fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2 -fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2 -fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2 -fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2 -fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2 -fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2 -fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2 -fifo_colector_inst/fifo40_inst/CIN -fifo_colector_inst/fifo40_inst/a0_S1_2 -fifo_colector_inst/fifo40_inst/a0_COUT_2 -fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2 -fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2 -fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2 -fifo_colector_inst/fifo40_inst/empty_cmp_1_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2 -fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2 -fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2 -fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2 -fifo_colector_inst/fifo40_inst/CIN_0 -fifo_colector_inst/fifo40_inst/co4_1 -fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2 -fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2 -fifo_colector_inst/fifo40_inst/CIN_1 -fifo_colector_inst/fifo40_inst/co4 -fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2 -fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2 -fifo_colector_inst/fifo40_inst/CIN_2 -fifo_colector_inst/fifo40_inst/Q_1[35] -fifo_colector_inst/fifo40_inst/Q_1[34] -fifo_colector_inst/fifo40_inst/Q_1[33] -fifo_colector_inst/fifo40_inst/Q_1[32] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] -[ END CLIPPED ] -[ START DESIGN PREFS ] -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.11.2.446 -- WARNING: Map write only section -- Wed Jun 16 09:19:31 2021 - -SYSCONFIG SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE BACKGROUND_RECONFIG=OFF DONE_EX=OFF DONE_OD=ON DONE_PULL=ON MCCLK_FREQ=2.4 TRANSFR=OFF CONFIG_IOVOLTAGE=2.5 CONFIG_SECURE=OFF WAKE_UP=21 COMPRESS_CONFIG=OFF CONFIG_MODE=JTAG INBUF=OFF ; -PGROUP "tdc0" BBOX 1 4 DEVSIZE - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270" - COMP "genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271"; -LOCATE PGROUP "tdc0" SITE "R68C14D" ; -PGROUP "tdc22" BBOX 1 4 DEVSIZE - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350" - COMP "genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351"; -LOCATE PGROUP "tdc22" SITE "R66C41D" ; -PGROUP "tdc3" BBOX 1 4 DEVSIZE - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430" - COMP "genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431"; -LOCATE PGROUP "tdc3" SITE "R66C49D" ; -PGROUP "lvl1_dec" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736"; -LOCATE PGROUP "lvl1_dec" SITE "R26C2D" ; -PGROUP "lvl1_tdc" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514"; -LOCATE PGROUP "lvl1_tdc" SITE "R25C3D" ; -PGROUP "hades_dec_pos" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732"; -LOCATE PGROUP "hades_dec_pos" SITE "R27C2D" ; -PGROUP "hades_dec_neg" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729"; -LOCATE PGROUP "hades_dec_neg" SITE "R30C2D" ; -PGROUP "hades_tdc_pos" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619"; -LOCATE PGROUP "hades_tdc_pos" SITE "R28C3D" ; -PGROUP "hades_tdc_neg" BBOX 1 4 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626" - COMP "hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627"; -LOCATE PGROUP "hades_tdc_neg" SITE "R29C3D" ; -PGROUP "lvl1_pad" BBOX 1 1 DEVSIZE - COMP "SLICE_743"; -LOCATE PGROUP "lvl1_pad" SITE "R25C2D" ; -PGROUP "gate2" BBOX 1 1 DEVSIZE - COMP "SLICE_745"; -LOCATE PGROUP "gate2" SITE "R67C41D" ; -PGROUP "trig3" BBOX 1 1 DEVSIZE - COMP "SLICE_746"; -LOCATE PGROUP "trig3" SITE "R67C49D" ; -LOCATE COMP "clk" SITE "P3" ; -LOCATE COMP "hades_lvl1" SITE "E1" ; -LOCATE COMP "hades_trig" SITE "H5" ; -LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9" ; -LOCATE COMP "trig[2]" SITE "T19" ; -LOCATE COMP "trig[1]" SITE "T3" ; -LOCATE COMP "trig[0]" SITE "R2" ; -FREQUENCY NET "clk_c" 100.000000 MHz ; -FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; -FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; -FREQUENCY PORT "clk" 100.000000 MHz ; -SCHEMATIC END ; -[ END DESIGN PREFS ] diff --git a/impl1/s1_impl1_map.hrr b/impl1/s1_impl1_map.hrr deleted file mode 100644 index 9d8b8ea..0000000 --- a/impl1/s1_impl1_map.hrr +++ /dev/null @@ -1,272 +0,0 @@ ---------------------------------------------------- -Report for cell top_tf - Instance path: top_tf - Cell usage: - cell count Res Usage(%) - SLIC 692.00 100.0 - IOLGC 35.00 100.0 - LUT4 388.00 100.0 - IOREG 35 100.0 - IOBUF 186 100.0 - PFUREG 899 100.0 - RIPPLE 121 100.0 - EBR 4 100.0 -SUB MODULES - cell count SLC Usage(%) - trb_adapter 1 1.0 - tdc_channel_fifo_out_2 1 16.6 - tdc_channel_fifo_out_3 1 16.6 - tdc_channel_fifo_out 1 16.6 - pll0 1 0.1 - hades_tdc_bundle 1 32.6 - fifo_colector 1 15.6 ---------------------------------------------------- -Report for cell tdc_channel_fifo_out_3 - Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - SLIC 115.00 16.6 - LUT4 53.00 13.7 - PFUREG 154 17.1 - RIPPLE 26 21.5 - EBR 1 25.0 -SUB MODULES - cell count SLC Usage(%) - tdc4ddr_short_4 1 2.3 - output_decoder8_2_1 1 2.3 - fifo32dc_1 1 11.8 ---------------------------------------------------- -Report for cell fifo32dc_1 - Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst - Cell usage: - cell count Res Usage(%) - SLIC 81.50 11.8 - LUT4 48.00 12.4 - PFUREG 102 11.3 - RIPPLE 26 21.5 - EBR 1 25.0 ---------------------------------------------------- -Report for cell output_decoder8_2_1 - Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/dec_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - LUT4 4.00 1.0 - PFUREG 26 2.9 ---------------------------------------------------- -Report for cell tdc4ddr_short_4 - Instance path: top_tf/genblk1[2].tdc_channel_fifo_out_inst/tdc_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell tdc_channel_fifo_out_2 - Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - SLIC 115.00 16.6 - LUT4 53.00 13.7 - PFUREG 154 17.1 - RIPPLE 26 21.5 - EBR 1 25.0 -SUB MODULES - cell count SLC Usage(%) - tdc4ddr_short_3 1 2.3 - output_decoder8_2_0 1 2.3 - fifo32dc_0 1 11.8 ---------------------------------------------------- -Report for cell fifo32dc_0 - Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst - Cell usage: - cell count Res Usage(%) - SLIC 81.50 11.8 - LUT4 48.00 12.4 - PFUREG 102 11.3 - RIPPLE 26 21.5 - EBR 1 25.0 ---------------------------------------------------- -Report for cell output_decoder8_2_0 - Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/dec_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - LUT4 4.00 1.0 - PFUREG 26 2.9 ---------------------------------------------------- -Report for cell tdc4ddr_short_3 - Instance path: top_tf/genblk1[1].tdc_channel_fifo_out_inst/tdc_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell tdc_channel_fifo_out - Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst - Cell usage: - cell count Res Usage(%) - SLIC 115.00 16.6 - LUT4 53.00 13.7 - PFUREG 154 17.1 - RIPPLE 26 21.5 - EBR 1 25.0 -SUB MODULES - cell count SLC Usage(%) - tdc4ddr_short_2 1 2.3 - output_decoder8_2 1 2.3 - fifo32dc 1 11.8 ---------------------------------------------------- -Report for cell fifo32dc - Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst - Cell usage: - cell count Res Usage(%) - SLIC 81.50 11.8 - LUT4 48.00 12.4 - PFUREG 102 11.3 - RIPPLE 26 21.5 - EBR 1 25.0 ---------------------------------------------------- -Report for cell output_decoder8_2 - Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/dec_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - LUT4 4.00 1.0 - PFUREG 26 2.9 ---------------------------------------------------- -Report for cell tdc4ddr_short_2 - Instance path: top_tf/genblk1[0].tdc_channel_fifo_out_inst/tdc_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell fifo_colector - Instance path: top_tf/fifo_colector_inst - Cell usage: - cell count Res Usage(%) - SLIC 108.00 15.6 - LUT4 95.00 24.5 - PFUREG 142 15.8 - RIPPLE 26 21.5 - EBR 1 25.0 -SUB MODULES - cell count SLC Usage(%) - fifo40_dc 1 11.7 ---------------------------------------------------- -Report for cell fifo40_dc - Instance path: top_tf/fifo_colector_inst/fifo40_inst - Cell usage: - cell count Res Usage(%) - SLIC 81.00 11.7 - LUT4 46.00 11.9 - PFUREG 102 11.3 - RIPPLE 26 21.5 - EBR 1 25.0 ---------------------------------------------------- -Report for cell trb_adapter - Instance path: top_tf/trb_adapter_inst - Cell usage: - cell count Res Usage(%) - SLIC 7.00 1.0 - LUT4 4.00 1.0 - PFUREG 7 0.8 ---------------------------------------------------- -Report for cell hades_tdc_bundle - Instance path: top_tf/hades_tdc_bundle_inst - Cell usage: - cell count Res Usage(%) - SLIC 225.50 32.6 - LUT4 124.00 32.0 - PFUREG 287 31.9 - RIPPLE 17 14.0 -SUB MODULES - cell count SLC Usage(%) - hades_tdc_channel_raw_out 1 16.8 - hades_LVL1_raw_out 1 9.7 ---------------------------------------------------- -Report for cell hades_tdc_channel_raw_out - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst - Cell usage: - cell count Res Usage(%) - SLIC 116.00 16.8 - LUT4 35.00 9.0 - PFUREG 163 18.1 - RIPPLE 8 6.6 -SUB MODULES - cell count SLC Usage(%) - trig_inv 1 0.0 - tdc4ddr_short_0 1 2.3 - tdc4ddr_short_1 1 2.3 - output_decoder8_0_1 1 3.3 - output_decoder8_0_0 1 3.3 ---------------------------------------------------- -Report for cell output_decoder8_0_1 - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - Cell usage: - cell count Res Usage(%) - SLIC 23.00 3.3 - LUT4 13.00 3.4 - PFUREG 32 3.6 ---------------------------------------------------- -Report for cell output_decoder8_0_0 - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - Cell usage: - cell count Res Usage(%) - SLIC 23.00 3.3 - LUT4 15.00 3.9 - PFUREG 32 3.6 ---------------------------------------------------- -Report for cell tdc4ddr_short_1 - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell tdc4ddr_short_0 - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell trig_inv - Instance path: top_tf/hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1 - Cell usage: - cell count Res Usage(%) ---------------------------------------------------- -Report for cell hades_LVL1_raw_out - Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst - Cell usage: - cell count Res Usage(%) - SLIC 66.83 9.7 - LUT4 48.00 12.4 - PFUREG 74 8.2 - RIPPLE 5 4.1 -SUB MODULES - cell count SLC Usage(%) - tdc4ddr_short 1 2.3 - output_decoder8_0 1 3.6 ---------------------------------------------------- -Report for cell output_decoder8_0 - Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst - Cell usage: - cell count Res Usage(%) - SLIC 25.00 3.6 - LUT4 16.00 4.1 - PFUREG 33 3.7 ---------------------------------------------------- -Report for cell tdc4ddr_short - Instance path: top_tf/hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst - Cell usage: - cell count Res Usage(%) - SLIC 16.00 2.3 - PFUREG 24 2.7 ---------------------------------------------------- -Report for cell pll0 - Instance path: top_tf/pll0inst - Cell usage: - cell count Res Usage(%) - SLIC 1.00 0.1 - LUT4 1.00 0.3 diff --git a/impl1/s1_impl1_map.ncd b/impl1/s1_impl1_map.ncd deleted file mode 100644 index a83bac380e09b0d0831199fa396d8fb25f5d0160..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1016509 zcmeEv2Y6h?)%I$4WsFU==~aYg8vy+`F~SWuN*uDtmJA9;HnL1fah!zoN(d#C zB-AuWNJ#I!_mJLu&zIg4{&&vYyXVfCbET_Qev4H`&+~%snKS23Iq&qjd+4FR`(0hr z+n$sw&W5n5c8j`fB6USj$CeT|LUb1*7f(C-&ty`!}F0O-6tV!Hew_P|4oWpj5zO!TaCER z6So<$G2bK||S)TF+#M49w*Q=&|IxhYX5ecO~tucS(p zN#8bQ(zi{Sw6+tOq+}m1GucE{cC06+B00trlaZr6G3EUzPfU6D+@Xo`?iF_v<=syp z<^3?vHs$?LPfU3~gv5!wQ~Ep`&6M|prHy9F`$3+V@;=`alkIt)nDTz0C#Jj~;E5^k z`+H)_`+lC7^1iPpro8V%;zZslAzneXP~PWC8!eRgIi8sEzPBf)ywCQ;^vbif zLmTDYE2%chyH`?elt8bf+9>Z{Nwrbly^?C9yxWpW3Od(Bh_<=rd44$8ad zX&sbzucSIC?_NoDP~N=`hmvO-MoymXZ*04mkWw;ivzU-lDr~EmkWwOSqnMCV8f=@G zkW%r>CeijZwh9xvRQR?A6H+QpTY(8F<;~XLoXS9l5+>Uq+sW8EWdpX4u~nLoQif%X zHj`ajbqQU{u=M<9%CMIPayQvRG*gCcwQ(lMtW<5GgxOI7C!vKBW(NrgDOs>%goKn5 zW`_s~DJ9H~5E4>Km>nP_q*N1je2|b*P1vrTGeIwt4r!Zx+Y_<@+v>{^gKhL}>zUA{ z4BK`kA*Bpk#wDbb2I>B`!I$oD+k5H$wz-$?Z(Doo{+wYdM_E6%t(TmzO}*rVZRsT^ zY(p}Nk(0&`E*@7R<&hD z6`!ee?R+)eYO*HmB=%riy2B%sukzqlJ!^Jqn^l?WEvqtBTvlbOx%oEDn|5v~4~}lz zo|0m!xNNFaZ`o9-+EP`MwMN9uRBLuX6xG_`ri+`#;ZGAeLq=UnLPp&rFDFVvl9v(+G6@d1 zOrnNcCc)vBNz|}i2}&=AB!?+$nQGY19n!5Pd1+@98Fi_K4@vNS^R|J}9YY&Cv@wxg zbIPnuwVYX-3L~>N)pTZUs_V?!RNI-giP7U}Cu^LNovFs{7ms#JHrq z`LgY03{p0h)RC~AZcRd;x|>PpQ{7KOpK5;+`c#mU&?gU=gg*JeB=pG(#@A2!0VOAs zAJ{qN_?DBNU}u|?(5Dt)68hu`$NHXDj#>`g;q3b4eOZ^x3Fj3<-L%vES-JDF@|u0lK0Nwt|MZc1i)aoaWed40XT z<({tfUFFpq)+d(X67^zd3Rx8Cjad}QwX-Nvv1Cys$IhZiew{^;+&WD$QOuN=^kTL% zfiydbVz$$OEQ;jQSrmzISroHYoZXhrVlivQ*{zH$7PD5I-S9}Wn5ekSl(R$oG>eHU zw4?egidn1BZm49jn6(P+wo4X^S*y@)&SbHewF>PPPMXC;6=v?v?5I4=VxkJ|a6F4* z)+)4HL}?ZinaSMa+MT4s?T~(S;L5UHj=y4P^Vr79>@kriyT>#MeQNp+wDz}c*|KA3 zjMoe0|FgC3QA20dy3Gw2a{GU!oTpFxkPlR=OCH$`v$>g_|L z17pJ@7dLco8yOrP8{RfzP7==PUcGW<@7nJEt`)Rlw)Z*xt7v#d8-az*TQ7CRRHm~= z2g`BDoH&Br06J9JiCfUrzL2cUWnD6#*vv3{apZVXF(IcCA*p8hW1Y;X zZ5bXJ-f_v$pwy!}Jk;vBdw>g?y+l$)>dH-?GS#N8T=JBuN_FK%Pnqg9q0IY$N}7rH zy0V{U;+(D=rJ1XjDnhT`Hkste7r2-cN%rzrBFp<)<-y?{n+HZ^wb>2BXqiH682V*k zcMMasy+W{OWK*=gnzKh|Q?&i8Q9Vb?c+RGwl4`1ERo725)v~JVr$p|cv7IAFCE;!sEok;qVK)y`w7qg`qJ-$$O^dyh5UEqNJ3MV-b&9svP}$?cDcYXj z+p}FM+I|UAji+e0c;jwcb6;cAGK9vRChRqcKI>t9QG45OqYNE%B<|t{~{jUahwz`*2~|t8}~Ds9W~x z+-^7O%3hV*{YG8ct8u&Gs4M%`lI+7p2EF>WV-&T%y*?&7uo!jA&e4zsUUl2$20h7M zZQJ9G(F}r;oY;0;;8mgBcT7|FD$$;SPgD1*(Jn%yse2V^k5HzmdsS%{B+}Hq%Cv_r z)71ScqPkC0k1B~}f|CCN>f*p0@Jdd-h9qADwpJT7EvkTQL zyehB@AL+(D548&*=@C4)um@w)Blt-ouQ=ZK3TH=BaX`B#IdMe)jns-hVxl*C?r5)F zOc>AeN_#J3!g!u@+KU?##`ApC-t3q#UgWCmNOtC_Ig&qgvzwC>zQglwyE{2yJg;H3 zS4t*~=lQR_b24E(&yDQ{<%ID(-?EEw@vte;jwTjIxWsMOuaC?%Q^q!{lDM%^u0=AnzY>fxRteZaMDMhu- zy6GKc+<&oddb3%IYL#{EY+b9TsF7e*s?tL=Rav7{VEa_|KNrZ{*m;_2Drzb!Z?%&& zRaMrhouR3!vP$jrOjVUNYUgIEs_d`q#7tH7O2DqZXoVROmP^1czG$klHk+w7_a@cR z!J!eCOLqP>mqLdw+dg)6iNY&9B-c&UnoNkDWgW8O+!dwr`nAjKX6m_JEBbrN{j1zp z*(uh1Qte-5bxagbk7#&^zcpJ~rl}Nzom#1?vKZ{dN>hy&XxJ)oP*shbnpJI;DQS(@ zkXhAMnWie8)=sF@1W2c~2RK#L$Z0E8Nx4c?r7R&kfl^ILr;e_HX?c-OZ6{BvRq0F7 zflbY-msavi&1&3tSIXT^m{e6+n|89Ks>&wFPLxztS(|o}q^io=w7a*es;tfQwm)9X ztdu}>I8!NCulup{A~gZBV(p5ir;E7i_(G)-Bjc7mg6$|_CoqMKzg*@=y2R8rN>Xf#b(p>`^xY0CPvo4T5&mrmj- zZ~vaRwts!EIc(#04ff*qL2<43^{?t*cUEtYqDXE(-zb`{V{Pw>-mZ0;K`P6m{B8-o zO?h;92lf?33aFQ?-?Vdd$CwDAAf|OxXLSilS^K?3GhRQ8p6x7OJ8sN1pa#s-h@)Z||xqijwyB`l_NRS#NK&DvGj( z7bmOG){QnDTufDSfUW5(hermtU0EI)v0JI8`qp1?PH!jeyXT`JVns@mx>#ylhji^O zZXs@6=Ca%#4p0KfkQRf+pjrUYObZ}_X#vD2Er6J#1rS5D04i85fQqsbz$KEFztp0# zo7)vjT!ztyocuDhyVqKbv=Xs<(prqP60x6j(qg2QNGYvE(kj+2Dk!h8JHc8&s;M*| zX-X>*yKAexBdtW5(tM;Ttwih&Yvmp6BWbC%6Y@#~b_F~A)&kN>#7?cX7-=P9r_EZ7 zv=Xtqlv<3m60vjNN(?TMv_#p-ZY2Vjh@IMM0cj;-XRca|)R(8VBX(m?GnM8ec7CbF zNMlXfyX~A&v1Dh6T0mNf*x8>JBdtX2%ub7u<|B62ro~9}5j!KR#9$vudxf2BRU)vD z*r}BkkX9mg+N8xuD-k;<(qg10H_b=v1V=NK<|ApA>|8~$WTz%tKw62|iH8;=twik1 zLW_}BB6j;ii;?Cdb_1dkgMB0|f}IOgBCwA{ADHqxSv&gIVx+a+c12%{;c}T%>(*;! ztVMOg6JJt-*sx1r<8(S8}>_0^o$i>pyYU^V7o!)~v=mA+j zg%6_tt9U|+dC~h-%!|&CE+8*ab7sqB&S_XR) z#BWLLij;4ja^;ItT)`Dr5@Q#Y{FmA_Bt@Q526lx=(NA#&yZ)o-r?`S$-BI*Y>ejB_ z82zW5cgFiqKOJ{7rues)`B-&f{pxcb!k@8KcbEAO&pJ3S0-g47eV+0YIMWZvtKp+zi|T z+zQ+VyaIS7@G9VT;11wU0OeADH*gQ|YTz}%Yk}7RuLtf0?gQQcyb-t`coXnu-~r$* zz*~X00dEK10lX7<7w~T2J-~Z`_W|z*J^*|W_z>`6;3L3CfsX+n2R;FyUg|#ud>Z%+ z@LAwY1bi8I5cmr4Rp4vD*MV;U-vqt|d>i-<@Lk}0!1sY406zqN1pFBI z3Gh?kXTZ;aUjV-Zeg*s*_zmz|;QxT%0lx?S0Q?d76Yyu?FTh`czX5*-{sH_G_!sbR z;6K1ax!kNAPzU6J0#F3%0R+t23z!Y;4a@=N0{Z~_0{a2`0|x*H0`q|Rz(K&lz#+h) zz+u4Qz!AWaz)`@_z%jtFKm%|b@Ce{|-~`}A;3VK=U;(fYSOlB`oC-V=I1M-*Xaq_? z6VME_0Ifh9&<=C}i-AtyQNS6%65!FmV}LV(E?_Cp4fFuLKp(ISI1A_p&IXnPD}a^2 zDquBm4zLDT3#&If%Aa#feV1g0vmzH0T%*~2g<-jzyPob*bEE;L%B z7X2n0o#Ggfl*)wFb3=dt^lqCt^%$Go(Mb%crx%5U>ERIU^nnI;OW3K zfNOwf0?z`T4Lk>UF7Q0y`M?W+7XmK=UJSehxE6RRa2@b6;CkQ&;6~sk;N`&0z%9V7 zz-_=QfL8*q0&WNH0PY0t0`3Ox0bUKf26!#-I^gxdy}*6I8-Oz&n6<0`CIe4ZH_dJm4}c#6KLUOX`~>(Z z@H61&z%PJb0>1)&4g3c9E%1N9?||O}e*pdn{0aCo@E72(z~6ws1OEX23H%HAH}D_e zpH%ZIq+m9%H!ug73+w~z3+xB% z4;%m-2+RZK0|x;I1BU>I0*3*I14jTy0!INy1IGZz0u8`%z$1X;ffIlefs=rffd#-q zU=eT%a4PUf;56WLpb;nmO~@`PC67wUqf+vyl>Dy%R7xI|l1HWFQ7L&;N*%9+i?urQ}g5c~nXsm6AuLb* z?CO!GdZeiyX{tw>>XDXuq$4-y%JRjV$41MWhX?SK-;Mv!->kmAa;Xuy^km3=LN+^! z?@H?tdof;@P$Usjkr2gk-M5e;iZP)`B9v}I6vss!B&4K>s*oboP(l>PMcpN&6ju?s zZ;0c%7UzuWrD$xn``K%EOKWx%+m)KQZGIWHi874h`Y&no%dkz9VHDTRA-&fx!!|d^ zahm-CYg0t-8{)XG#r^191$|F$^KjYq#ErCRU`|?D9o6tmno3Nsxg5xUr z0XG%Xl^{0?%U#nfcazO>H`Ofn6Yah+Kj6Np(jAtvc87RF9;wRT54;I@ zGujZeUw(IJl4!d_<44Bnj4v9;HU5kyD2FB}hh{N{W-*7RD2HY-cP4;lF^6U`XUw8m z%%NG#p;^qKS|3ve-T2`~&i0k{;{3S0(^0Na4=z~#Uwumczab^=!b zR{~c7R|8K3o&-D@cnYu!cq*_PcpC6@;2FR*z%zko0nY}W13VXa9`JnN1;7h|7XdE@ zUIJVTycD<&co}d#a0757a1-!y;AY?!;8x%^;1$3tfmZ>y19t#-0(Sv-1NQ*023`Za z7I+=-df;B*KHv?&8_}h`4|qTD0pNqcH-T>f-v+(|d>8m0@O|J1zz=~R0Y3(Q0yo_c z*dI6mI1p$7T7fp89aswV#w0F*d0?6e72@;_ktf znz+;*x^byHWKkT~FGK1MS&__%GE8)bLeVcn>JC{eey?9()E%-Sy;qcB^j^0N{qB&B zB)Y0br_vGuZV4m;+?OW;+_WbG+=Rv5At%Rnhy3hyhaAM+m78#uyXj`Rn{1Z5sb;yK zX!nh_JLHsAy2Hk--67iUI@9JI3LFL;jy7Z&s>7QdqM^qhnzY=-0Gj$7n))1?`W%}2 z9GdzZn))1?`W%}2+;-q{U=-K^i~&1=D}XBjH1)Zw0W|eFH1#<&^*J>4IW+Y-H1)aN z0Gj&T(*ZQ~xoZG4^*J>4xn~1t>T_u7b7<;wXzFul>T_u7b7<;wXzFt>0j>pJ3S0-g z47eV+0oi>k@HXJ>z&n6<0`CIe4ZH_Z_$=@_;Pb#2fG+}H0=^792z&+jD)2Sn>%cbvbOm+j3hK}m)S)Y=Lsw9T zuAuJw0J?%YbOm+j3hI6gpev~RDeyDk=fE$3Ujn}ZehvHv_$}~%!0&+H1AhSi2>c27 zGw>JSufX4czXSgO{t5gG_&4w$;32pJiY#9T;2-${Pz36MS-@VvY+!F-4lozk2iOE2g>S41UHtS)t9yaS6ffCRJGy{FWS;&ApJKVAxBKqU*P|9E_$FjJ4aHXaV zq}d@WlBh$Ci*zL{l483rYI8*KdyyX*x78Q5IHEW%%0b3eMD82nxUNOFJ9INm-JuY< zr4@HAu9W(b#aS0t@youfl+tJiu7JlhKcTw z75(mz!xCMUTS$ojw*(Ra?#mMaZrT$8Zso?^At%Rnhy3hyhaAM+m78#uyXj`Rn{1Z5 zsb;yKX!nh_JLHtjqgBz(+qUB4eA`Cjbx!yj{?-6D0cde@XmN6AadK#Ja%gdKXmN6A zadK#Ja%gdKzXN^``~mnQ@F(EU09w%;TG1R@(HvUQ99q#FTG1R@(HvUQ99q#FT2VBh zxjOu(E)Sp;twSqXhgP%>t!N!u(K@uEb!bKF(2CZf6|F-nT8CD&4y|Y%TG6@#fCGVf zz;1R&_zzM*Kz)8T#zye?)un2e| z@FL*Fz;(dOfa`%9fExjn8Iqo>M}F#8;2(5%v!yXET&UphUf|`x&A=_dt-x)-D}Yx5 zuL5od?f~ut?gH)x?g3s6yasqJ@H*i2fU$QU@CM+G!2Q6RfHwmV0B-@_3cL+?JMa$R zoxr<*cLVPM-V3}Bct7v~;Df-20CYh)bV0d~0v`iD4txR`Jq0)wcqDKda5?~Yt1AI; z+`49<1!x7@fOen*SPXOmj{?pBmH>|i9s`^SbOB3&ZlDL~1^R$xz*#^)a5k_UKmpgS z1Xcm7fpdU0z*=A(upZa|oC}->oDW<8JQmmpJPx=Jcsx)BE&>LCO~7Vg5Eufs02c$7 z0K>o&fJ=d`z-7P)unpJ_Tn>x^JAg4@CvXLDC2$pRHSk2>Nx+kVrvSTvrvkfyrvXm~ zo&j6~JQH{p@ND2Yz;l7;0nZ0sfUX{OQbe5;{{Z|E_!IDF;4i>mfxiKN2mS&46ZjYK zZ{R<`LvYeVfJ1@9fWraQX+7$+9(7ueI;}@p*Q2b(FySU7)&B7?LCW9_IhMuUrYohc zezBuSq7FwC$AxbtERtfoFKTl{aa{PMj0@M4B6w^<6vu@xC#3XVMdZFAj_X=b~6F?PSuuolp;7SOO3(6AQJuolp;7SOO3(6AQJuolp;7SOO3(6AP^ z1D6A%zz$#xK*L(N0zkuBK*L%m2;Kjg8fNO!50@ndA1Fi>d0B!_s0$vW>4BP_T3fu;~ z0(d3xD&ThD4&YAUE;P9J18)LQR>jW%pGD(Z0A>Mu0Y?BQ0*ioCfHQz4z$O4?mOIFN zWR|{u+SFQZEcch2+RLW$K8Xz4zhj~+ris1p_&#a0kNrtf?8ASNf*ewi`yB9j;0wSP zfiD4HMvC76yb(aE3rKb0&A)s~m46g8Q$=;M5J zgz*m8<0bd8c0elbmKAhwl;F-X)fV+WvfL8;r0bUEd4uEdqZ@}Mye*pgk z{ssIS_z&<9DiG$1bpR@{2r3mJDAohB08pwp8`v9|1Hhq+Zv^1TML2R1j$4G|)+0_m z;?zU89=i2#zWOq75io!kP<2OlU^~j2N3TXT7>9UpH~vF^zJ{&s@idwzv;mI8I@_3M zs<4ud9c5c796nz*4>l2>+-(zylP6NaIteTI4U9B#K;=8v<+ZC;Z^SR-CYzsqDxorD z?{ynimO!VgjAL+;XRj)^Vs=y>cBBb2rPLQRyCIY}I^t7qD{n!vaRw+YZ6f4=vC&QC zfx&_8V?$yZjAktNQ;f7<0$dBc6dr@-uZZTah~}?|=C6JwunJfW-NTjd=a}E3rCj`E zH#F$)(BTpLiGlL=%XVG`Z(6&mzh`YP8l~KgyR8b241xGtkf19^aq)U!)7Bw3lzyK$ zQfaoO&2jfjgvzi35@F?Lo3xaelxz+YF{uFdY&THE^i2yl@)d-)xaLJ{H&Dd% zO$%r76@6;eb;wuP`am|a^ZlH+in-<>UD+rHq&5PJ>por<2Zl1{3nuW(W=4EU* zaNL;Vc}lbJl)cVhy|$@5)`3p$rrr1t{YAodJg|_KOE8;}qDDs)MQziBt&Y&xYhCP% z)TFdHdeKXo9U8cY56 zF7|V}*v)Ai*G*t7_0!nlmr93QDsfylGqKdokI7<(n;8)CnTe%teki(|84|fU ziTJMM#Z5Iu^^@G85UPg;JKn%yjsmY@1&KlM$1>YM!3 zm;BV1{L~9iG>ItrsW17dFZro2`Kd4YsqgSp-{Gge-A{eHpZa#c?A!g+xBIDY_fy~Q zr@q}yJ=RiMv5<{l02>(8=GSwFu^2FbeQ`N`<^a*_?`;<9%r|^Za(J#EeYG$tnjLF8 ziU+x=!K%P%TQ))C#@+Z2{Yj0Ir*WWbL#AB@iyTP%O%vJ|W1HE7LzVkdX1RjyFxB0R zg_B!=TY=jEtdQ5e5_lDGJ8%bZCvX>VH-M$UIxGd&VJWZc5 zrI|)<%Wms?xF=}G3#OT4p=qSsOe-oxrWIvT6xB3`p3pRiEHw6L94|y_QcO$5deKWv z)5$`z=O>xQ@vId^HBGE1^fO1}c-Es=s7Y}Pf%KHrxo&&)K;w8 zqH(;?a_fP#{92%Kyol(hp2qR67LDVD$Snyok~V!RD;bHKb|Z1?%}Cso8;P56BXO(3 zNZe!_iC^Y4j^_kXWx1&~A{xiLS}kt6Ny|+*iQJTv$W1zl+_aO(O+1O*)W>62_ocDa ze=m*W-8|4Zo<(t7H-WL#Pa}=vIl4(BjpJDq$8|FkOWpiXbT>03a&r>Lb?F&P{hI4= zGeZ{LoJ5U)>zJhHrkX^4l4%^zIW}4}j(0^gju#@|foL2rwA}0)^UZ#iXdEvh`l+XJ zysJgycp>r&k;d_^7LDVD$geya#|te#^)!wbT7K$j9Pet;I9`bS)YCZL)uM5{5c#R6 zalFv-Q%~b~q2;HZ#__B*pANBNG(x)&rFcj@v>VMM{T+~0*jS<=FNe-H$6BJ35q89S z7|!401VSF0!1<$qqXC>i$R7(d0LKB30B~9$e*$nKa1wAbumD&HECO%>A&(OX`9}gc zfsj8PK#}GR-;RtwQ-F&oX3NrU;|&d#XfTyOd^e?BC?b#endIcCOH;&6PuHT!aEhX9 zF-;MlQgAJr!JB3gimt^p#b#;I4Ei*SP;@P(DSG8-28)_SD7qHY6uojZgG|jL6kUsH zie5RI!Kr4^E5|fNuN=*wR zo@rjA>B;noI!R5RDCvrxOrI#fm;AFvEK3&8v~e>SijSOMSwLh+NB_d+i@@69*uhJgMO z^Il&{EcJAWX`YnW;z_A=Jt>u?C#8~erI=lsy%~`*NU25gbd~f%S4l6VN_rtx(hI4Q zUPwiH6EjGW=0u1{cOpcjJrN?(p9m3oNQ8)dBtk@95+Nc#>by5m6W+Wx5f;yT6QXDc zXa;00yRGjz^IjI3@fXc|g$P}wAGJ*rngN6xndZGhq$b6TTUjqL?`5G$U#l6(2$7l; zGni$)$e!uwSxEMjB&$hj^rM<)MObs+N&{N|oiy)tBhtKAh}>c_wrJifwA{>-mY*e> z_lk&q>S^BVYSFw`h#H-2o0+GXUa*ppxM?>Mx897zO}UY{2{#hADvZQUwvqT{PV-() z5Y@ArY9pd~ud7A#ULkT5P7&RdlgLdviQKf4$W1(n+|_X?3;c{J}8T7K$j-Yc~H)YH7z)uMT?5H)(Kr+KfdMe|-E@>5UqUZLfup60zm z%TGPcds!=G-rKwzsi!|}-pirMd9QgFeSt3j07hYN0p1F{4R|~74&a@@yMT8C?*ZNm zybpLk@B!e1z=wbj10MlC3VaOsIPeJoqtiTgW+s~VzIiuv=r1`zc4t>K>QWTNh`(e9 zkGi63kw$BZqL{mwZwewCx}s|_O;OAuN_NnySoG#=G&)oi#eAq_2fVtXn?@Q{DvDk? z(jZe;bS16uIQ#wC|2foq8#mfgbh~oMCnK;tLTY5OV_FB ziJVA>sOZV`iQ22^$@Gajsp!e{i7Kh+$@GcxOU`@ih`2|CBA)?13w#dvJn#kJi@=wF zF9Qz(Uje=fd=2%?-ddK)YH7z)uMT?5V<8`W}ar=%SuM#rrk(fS2Gef)4jH1B0m9M{cEEOqlk(cR3D$jwO{*QIAH^=ppydpSX5(alN3 zch@mV&rLOn{3O%7*L?xadtDLDdxgk#d}E&Gy+X^)K54o2Ln1dzB=S>F^Iq3H&3lE& zFGQO6x>_{v6(Ya#Xx=Nd{M6IDS7`aEr+KfdMe|-E@>5UqURR6ey+Y)tp60zm%TGPc zdxe&tdYbpLR?57$Za11o`qSpU9GaZ>+7atvxJZm$lmd293b@8uSPh&5tO3>n>wxvZ z2H;%aJm7rb0^qU0M&NM(CWnQ`17+YMU;x+zY(}b*(^+>f)eNQz%XdSE{*sFB%q2}x zjQH)mSF;F3*P9Y%ZGD4(!g068((46L8?>Z3Ck_hRjXzj-K8&s;NZ0qXtK} zZKuzZ8v~JUQ+eR3O;>F;JwCr-ZyP8L#A4GbB(%q~Yr1r{n@C{W+H=mKs!s&R_Dvh1 zhz-#b;_+TfG+iTW#wjpfr-+S{CB);| zH6tLldt^%GZ*HW~J}brvpo^3&-XC9WfZLdl4V22n#e{J;P!ygUD2mVx6q$AdMb_QG zaZ^jzJ~=Dq^AwyFdmBA9RQUS*vC-j+@wEoSv6j-Z6}F#Be5_*5;P8&k1Ec1?2+IG# z-S`jv?G?%Kz`_HaO0g%q62&TmMOtLApp6U`^pU}$)?~1#HyJEyP6ms*lfk0)4s(hn zYN))@NzoF8l%gfdDn&~aS&Eh@xfCr?fGJv{98Jwco6o`6*d^0V%1&p$M7Ru_mk6V{qVk=%BFu{`T*8Sf z!o0Y`QJlCUY~SG#o7?!4FWej?gXoQV5E?OV@g$zDOElC!+K1qaRMx$C z#kL|R*HPqDNi3fm+bN|6P~B-Us1eZusNK*4sHxBbsCCc+s6o&Ih}lYj{d$HLAWEc? z^QN?%H;J4lF5e|;B5?@Omx@}8bd6nK*A%BOHD&2bO+ornQ;I^0Ef1Pvvxk{9Kq`DJ zk}Bziu999zmGnZYq!&^py^xCZCbl(1niC-+-H8y9_C$zCe(~e z37Xvab3(pv^oh#KfS<>+d)pv87-R9=C`OxnH3x`y#D)yr6R(cNLVI3hzp=dIa(r-c zU~uPlHJZpEzunYO;x!y#sw5E*zhCIbVxi4uOpPVXaDb_zL_lmv=*MEAT^Zw2aqv*D zBBx|3a!RKnr`IZSdaoiEgVM@-)5fHBy@m}{hMxA?9tRv@Ryjw8E*_wd;+k)GTy0iu zmbIVVh4Ny(edBM_MpyI`LHj37Scl|zZXh{XS|IsMTA(O+*Q_XgH&9f88z}0*4HT8( z28tSS14XsaDtBDS(U%=Lqasw4(UHm0rH`y!U2Z9F!FO|MDV)vB^A(*Mq!h-VKUS-$ z5-5`3#?-2*5>ub>f`hz~ zVf&b`L!m#3@7r@bu>qb6E*8PXBDh!t7mHX3EN%p_5Lh&xjD^4=&Q=sJ0tNt_ttjGb zMR5=q0=57b1D61p%om>kTncOjE(1n@Z2(4o#mj+FU;$d`o(Mb%ZNX8%(E!?# zdbB0=XiMtRmej8YkXEOiSihSZ36@f!dr~S#PfC94Ny%qDDfz1>C13TV@lN|U{yLhbC{{S^I$DaN zyS73lt-M;SHQ04D&7!ydLuIX46sr<;9Zj?7t^W|46^mkh#jc}i7NO|onpy$HqF0X8 zDCml=#WY2)9H}u;EPCabrs$O;HA0F-uN;NqKIWS^UO#;py!A!Ei-DH_*8(pEt^-~M zTo2p;+z8wRyd1b0xCOWsxDB`mcs1}E;I+W(fY$@}0{6kklMe2$C>LM2J0gOk=$1Dz zUs3dGkQ`iBbS=EPCabrs$O;Ik;lcD@UPNSveKuXh%{^t%{x~9a_#zG&~hOk!L&FQtXMG*zuR5 zC(|d|vC4a8`b6tg(Ua*DZB9i`rcbma6+M|g!P1JJOrPLhMNg(rFsh;_(r0wu@w+thAMp z)D&gnXwCuAlK9Zbpgp3B&<87V=5VMZKZ<_eX#Lt{<({tfUFCDTR`mCj`&TJHaWsym zsjS2YlJ_+$fabf&z1BST;7W`F)8vjO=3Ko9h%U6yR8oG z<>DHTRn*>1Kl;G$wu;)TDdV2MnRiQ}_*zdQjsMV}2sG9>@EG;CHSyz$=HRN>Ng3y` zzR5JVak2x$VrQa<-ak5X-eTKHlb#26<3IFAKSh8E6g3%a@i4tfq|3dmb)c|Jw}ILA zfzi+a?eglb)^2;xgM)3snw-cM$kddS8P}0AlNBj5_F8u1KlEqcp|uLep42n;q|Df3 zZm>NmGxns+*wbX}NYJZ+>b+d0g?kjJzcZwd|jd1!) z-DE%)kyx`kGP$saSD3*i&e~y(v5W*~Q$*<{7UohcniFxxB98>pQh1qb?`S=RWY2IZ zVUflb@f`wWq`w?-4kg0ll%vLDr=zLan-qiFVUBAnrDRN5Bg={Ndnt-h5hfJJE5d}@ zL`9fTJ;pi0&lktc%>nxhwVa=$({<$!$wrN?JJgJXrjR5FTv?>3F~}$~`x1(tP}3A& z>9(XairhdXOnO31Q+xo8O>!HSFzE@6NhuU}%hi$WWp2aJ;8cyhgb<&0@|%&_U8{QV zGjlX#;g|1CU&_96bO>8zxw_r>5B){T;wt+=_8pZ|yAe$i(}UzoxFnsIH1CeykxRaW zmD66rZA$Vb>;cY8hSZm^a>`2*laplP*m0AuX6gL+cZ1BtrF}zdzdh1+VwU;;$A*<_oj#$GRd$l` zGQwKXhSipV9b=|M7B60WuG2`nscJs!oIXlbqAeZgJqfM(Htq3yT6@;Cqp}hTb6CNV z%K@Qj0UoRr8lM@Y^%V|C4A{Civ~<%NVj|uVPRo(rX22WGS_&>jko{cc#WWYEy2TG~ z57T95ZwYGq)~$`vSN4%;{MBJ6eGC3yShlJM|74CHa>>Bp(2nxfE4G%(+ws#}sEJi8 z&oa|oextpp8HM(@^!3^Ir6`=;3I$sIN>Nze1_hC+C>eAjHhNKSX{nhgv5_NfQq2)V zTVq!YZ5}g;mdQC(QvQR_>;VqgkWF=M}M5o^f!dzl{xKrAPT1qdC%Q8p<~o!i9A zsE4I#I`)oJw4yq$$whW_s=B8-k!7=loT!ZPEDP0!)I?CJ)A2e^vQ}a?hZ}|F z1a|36UnaXka{{|&%{WmIGfuq;%?a#^rfwX&LURJUf<@!l6`DsVeA60-sLf5bOzYD>IRwIy^8 zPf3@c^})WHWPX|@L1fL6P)V~SsH<5LDruGkSv5;SCC!qcr)Ej0q*)S#)GP^=G)sbl znkAu0CE>uDC7}}c;+rmRioXhDs3*Mcpvc8pOKPOp5k9Bb z5gI9WgvTj%ghq-T;cto^p^;)oc$;EJXr$N?zNXj_8Yy;!rzv)XMv5KbXNn!6kzz-9 znPNw1#O<;1uy}aeEZ#LQ;f2uID8p47;ys=X5w6*25)HnzA;VQ0f>E9g5x&6Y)tt22 zv~y%|>ku7^E@R;ryW#djJj2^I+Kcr(W>nuS80NiMglBxS@F(@nf|K5xMR>+H3$IY$ zELiNlS%hbNa~59_y!YNL!n3`(Bs@^fvuG*2H;eF$Zx(*3zFGK!_hu2E@y)_7)i(=Y z@ZK!KGrn2)rTS*!3*MVWc*Zviztr9=eL=oihO0J2t$H>@c*fKV-&Wr&YSnwQ2+#Ot z;oIt)MXh>o7U3D+EPPviv#3??%_3a2Ac{W6NJQPljFGQnypcr0=V9kP{iL@YsH4DPsr3DeJSrBe3Er?*vf^a`+K?G|S zg!4%YB3QE^Tu)jM!I}l(c+!FhJ~`X?%3a#gUMqZ6zE%Whd##A1y;iule60x1_F54s zdaXHqNlPwfUMT7zdTp#CgEb4H9;5{ktXUAHBQ1#F6ZMLYlUy!g7%ie`FBN4YUn+v5 z1%3Y78!a4*!kceX#!9mIbSt8Sd@Djhw<5CaTM-Jn6_IVCNpr{W>98mJTG3o;0{CYM-cx1!SI^O*DHoGDlNgc<>61J#1cozNyj)%R>kTtt|})s9ijymK9%of{s7A@)^OrS#h3hEq-P;2 zzNC(0Bg$74Zv0VgF~C38|w zV#jWSe_xLe8+ryNI-1BSIJB>~w`{HfuI*jX+qJH@yn4fW&)j@P$w}QwW22kO1A_zG z$MDMo)a@%VMExITRLteWzW!DH>(1)!QD1$Krscf*WcA(Buz2|)vDxx@Yx~#hxt{0i zI4?di^~G#dyta~?IIrH;*a4N7q9VLdCBA5%M0^qI$Cq1TZhRT4#23Rl5nqHV@x_Qt z#22ATd@-03@kOW-UyOr9d=aX|7eg2kUxX_0#ppxC7okdgF>ny^MW_;AbR8nT2vy<> z4-@f4s2^W$g1GTzs1jdzn20YzmH5KLM0^pd#1|eW;)_rvzVI*+UxX_0g@=jwB2gf9>xyzhYy-k1gEGjV%KG z*uuHo*dox6EnLfuEdu@6!m-@gBG8X5+{%qD0{z&+sodBi(2p%#%8e}o{n)~x+}I+} zk1gEEjV%HXr4d{ID*I^#GsME>5INGDuP8Z#j8nZqh7tp3`Tg0#5&npgzVINEaEPww zq~dfv724+`{DkaJ=izB6O*a7?%X1TfPQbntV813I#^3f*kO^{P9PFRFmj{mybX2_I zm1aTIsv><{t3!+7l7DTXSL9{B;f(X_uh?YfK z5W$)S(Yi(t-%qEC{EQ z7DTXSK{%bXAc8du!s(<15v*AdPA4shV9kPXI%z=!YZiplNed!avml&KS`fjS1>tnk zf(TabNQuFgxFaP(mH5KrM0^pd#25Z1;)_rvzVJ2?UxX_0g|CVDB21`!>8BXzfXPY;-QgETQ4kX(cj&R4>CN2zZ^Z}=-&m{UcPd5Pj6>; z_lBkh^PkSnb&X3JuWH2Ksq0GkS6f?GS7&E;?m51W$zVjoC^?m18#IvAMNv+X|URJ-7Ur@iYv7%oz zC1mQOkSid+HU-7=dR9mA%s=DToYz$m*PDMQ8$g5`0aS$WZ|Ky zk}f%6sGh34+Danbr!%ldm7aSyrf#;Tn^Dt_Vo_p$RE&+I&Y^{NKrmz|xR z_}{wT^-F+;HKooq4Qm?lpT1IOUqfFb{sVXH?CD?EwRA;qPlNTrPW-QdJg~F7x52t! zX9=c2qXz3~on7lLSk;{*S{ME-(agV+M5~%!ro`~03Wi?zE9PpCUb6zdsHy({O)oTK z4!uhJTrzZP;^!vwd{fo*i<&k;zq``tXLwk9teefO+p7jyw|8LOw6Lz3Sw^gD;b&sq z%d2KxG>VwnteeZMn^S|V+b6JYT3FZ0EF;#n@iVdR=BioOV#l>Jn|1p!>-Mcd*6kly zH!ZAdXO%)13nQ^%UL-YfgZ3omK+vWwfO$*x=GrNdwo%~E} zyR~YzwW(|iYl+dy=VaCr=Ld4^5pu}2#M`QN{&v;*XX;ww!QA&8RD*rbA%R|dgkEwj zaW(ff)c2gj&(!z4qH6kesPvm*Yl(+3>kh3!)*T*LH!ZAN!z?4#t>tH8-7BkR-QxcR z)*Z>LJE8_zcT`~Aw6Ja+vy51`o}Yv(!2Ttq}PRK>XJFEA3{cwiv^NSb9rv%Nv{wt>hYv1Qj2tGe8K7UvB zKCd5*2tJ?r;Q5Kc=cmQz@2=kG^@9n)=QI2KNx|o*#pmy--skn>0m0`p`~1nl=cmQz zUtPV=>!$*O&u8}e1;OX1#phpBz0d1g@z?UYjdGce?$J$rg|3wK1|45jHUHA*#u-mq zQt?-A&MmCLwb4a^Lwkfnd0zXZi>cT1Gp&ujwt7zK8|`{O!oDxBY5xzeg`N^Putzu` z*Fs-cwa??%?J31#ms|JwuolX<`zs$LI5qhEwD|n%tM_?*i#hmw=J~=SgU?Tk&)-|U z&rfEbH?;FgJAYd6`DyX_`>OZ(u+M7;cU6CE>Ga_9)8g}QsNUzpKJOHLzA^axwD|lR ztM_?*pZ7UpEtI}&R5MGUr5aoU#Yd~cxB2j$$N%3S50guvH;5(B`(rAVCi|hvCVl%j z+%B);b~!$C6WFi^*dP`|^Vd}G{rX1oOub&-&X*C|YOuG#2W$er_5i=c_452NZf}#v z9jy3MmgX`-{+ZSDPv6v@VfV{BnRbh7kamv>wA&-|BT2gkrkUC2&L79mM7w8IPdk0z zdxp_&3DfS38l>H$1MQ}TcDV8w_ijWxT=$BfiFVJfns&|l*82>j-I+|g$J8M0x&rN{ zg?6}M7SoJqhub&tGturj)zePj{huKh%)6OxOKXsBJ%Mi1LN{FWiRndj!zGCLndtW1 z>glE*JP0d_RjerX26pTbcE}aQ=T-0h`VoYgx}vy@d!N1vd?z?;TTjEb^-`u8 z(XN}HiFPllo_6}Nkr}e0xQ^+zwg%~j4+00eO#|Jqk{kDGL^rHm#m_{y7gtX={gjA) zeJ@%D;!dw>&i9q}dA`@DWcL-+Y`eNXXue4#q{{51IdwN?9ki+(;L_c>ZP8 z`@DWGAozS{pMPxd`DyX_>#O&9eJ_57e6n(54X%woE^ug%a7f(O&Oe>kLTPREhUz(` zZ?xw z!RM#N=U-mE&rfEbH?;FgJAYB|`DyX_o2&Qvu+KZi&-V=kpPv?=zolxQZw>prQ}p>w z!RM#N=Wngv=kS?EMz0WY(jWX>nuR+@F2(+6P+8xL=Biha5XQJKC>S?F%{?CvL z<~x~gV>L*(D+1l7g>LhiUPQNp_?hT-MfG&k4<3XS#VS@5uMF(iBkYhXidRU|dRGxa`KRn5OP{W!!7n`1qhY4@ZWq}@{j z?WToxr!dWkcBk?)(eCQ%X{Vpam|?VgD${OP4bpCRpxw04?vYG0qTOlyOtgDq^|aGZ zZ_F^-J)LRyv>K!x4(o((YV3h;YREz6=}a@C9e$cT`3=3old7kker#lhtSCN{>2^&G z((PG+Zqw4sm6%>cH~gHrL$@baPdELPh<<%9T+>#rGCezRVvle_t|LCBdY{*iXy`s4 zuJ0*6|D53S)8g~Hs`q*Qd_?g1%-6J^8+?9ReEzA``@DWQA^3b|pMPHP`DyX_-PQZN zenKGld}g12e(?Ee@%g7!@ALY(fZ+3)ef|Z(=cmQzpI)`kx9fZHGvt$%FRa0}(H8{{ z?GX-%``U$VycSApqtB?GQ~E}`-j9T}P-R`{#eoBRgadLd^qT5@Uf<=`eLk#(Dn9>` z;Pcbs^Uti_=k+b-;PaX13)cpppBA5gR`otVnSI{S&MWQwOM}l(i_bs1dY=#byi@#q z-*v&~r^V-=Q@ziJecmbh{L6yRPm9k#w|bw~_jzmkla<%k;1cK!fjWDHI&ujVpR!3tFm#)Ou_-YU!K(VP&t1mA%&nChQR=$d$c~**sm};-9H2 zd#~qS<#jdKtK1v7v`4rkR`zn@``^XHGxaKu%f>bRXu%Ad6TN{cc3%xr?2Un9(?PLf z;*tF@!2S*pL&>K z6nhI(?137j*jod|riEgMFr|oMhw?M^V&!ZU(~n!skd?i+Gqv7UgVcIQpw_fd>oBGg zQR{GiCTd-jiCT;G(-r#FwQxmQxyJL(;QxEX|K)n#KsNu@k2dK39j>V<{{61t-_zpX zo3i=0ey$++cjl|d?+*SwE&jbZn}6$@`oX_5`}cc-e@}~l4`%akeP=!RcV_>7Z}9JF z@$aE*{;lt)2mj9O-|q|lJuUvdC7XZid)PDNvx)Do!S%=w1itJMzKA=+xjDT4Nb8Xo zXXB5)L9O=>Vf|5ApZQ?$_dVk8a{cj=Z2qn94(t9M)*luB{!sAmY4PvjZ2qlp%?AI@ zJih;M@b78y?Q~bc&M}vb;i-T{?=-^?C zbczoCvEbm-;^3EMbZ~u-w6;H2`0*NCdi+G-$sXZ}TzcGFEIp1~GB7x_qdYdaxx8uT z$l%tY~xVCp$Bs2ev zr1>?m-kMm_7fbpgNnzQ#wbtrh%Nv)MR&F>yYU8_CEU!G&clTEQJ!{3fwUvkB>b~ zbIj#|zBRjwdEioDv!y_(qp78{f7RK&-Rn!`(vk~$*J*rc=<8nH3HrdMH;k9V9-Ko%>wy{%P_4H%!U<^{v@)<^cm?9#EMpsPll&2Odld z58gN>9_U-RVIEN3T=)xt1JlBR`=`QzQnb=RKV*@kr4;iE82U&k%mb)`)gIuB!TYDh z``3lAO`j|VHxT~Sgu z0!sS+ai6*f%6nl0iyH^@y)fGR`k&hX_)2j4X>s}=Rp<2jE^y-Da$gC%z;Y|tIKABi zu zpH}DZ6Yk~8q0HjOcqn7W^qrmIEF10Rej~X3w7C7xbho!ZEnO<B5HPxLtBqzG=*0gT=!!>Ysli_F=*0gT>@5!S&+_VXd)Jn`dmGGM4y00 z3ROT$IBFEOTC_e$}%6o<{s!QT$i{3B7IBt7KKH-dKPt^(zA$YbV~Q41xwHDTDY)6BziPVDiM>I zQYBD|c*U#yQ)8IIC}jBiIdj(wf8UE3g@68#fA8T3fl=ldbzl@)s+?d{kr`tcRs0S= z)A!Zzy9010VjMB*a(-?$4BIh2!}L90t)E)DXcu)*OVLlo9h9NlE+aUlXFB_-AF2J+ zj{~a$t11^_$M2_J!K|Tv3ctnXuxfN{bW?d?aA5n`(5Q2JvPs`R-jwK~sJH3F9pauP zjguP0VSw0)+s5%gu4~-|tGcs|-Dt$)-6}?oei}FtIFZ5$ajUrg0_C$4(F#?QzKg7M z8#IN9rZWrBRoFhHGS}IK$qtXkCNaTLxiQJ<&Ck?sRA-g%KT%Jyu#W*v~uv@Al5Hb zV*N4@D-bIivFcA^A`!7p=Vu~TVH{%VJK!^dSie$<_3J>aK&*_!I+=+?#A@VcB35x6 zV(EMDGlE#ZQHk~2K&(KljKo^NL?U99_?d`RKMt|<{r(w2tp8Jq^}9fZ0lzl857Fu98tMHGmQ$>8;4VU3z*+N_vq z^~|){%(T4%(*n~nGVKgz5;1KFKNHgqnam_&S{FYP z(+=imV%j0;Ol#54choe~=EY1qkePN6Gi`ogT3}j6rY&VA5!1T)nV5DcKNHgq8;5E7 zfsdMI+95I14rZnu#!NdjFfA}GBhz}ANyM~XekP_J&d$O+OM+(@Z-iX4=urv<7C{v4LrUX&ISz z7Bh*M*3Zwxw4?c%n0CxKOq+RUMCu+9GwnEL+6m0G;{($I(=sycY-SQMZ8<*^(~jk5 zVp_vEOq+RUMCwk8nRX&GZ2>dwkB7+Hw4Bn3fyoG**j#Mr2pw z+#{V}j6eKDU%81N)>OVbIR4iL`TU~#S&o(FLy?^;OOyU6R4!Myh#9mnFeor6g+X~{ z1bxu+5&TRHI$r6EjHsp2`Ak}ie$L}L3AR+ec7rc>Rz7cIKI8dc`EKU~Oj6GQ*PR;o zJg0Eaa~kvJk%2dXHz~Xk=YR_jy1XgiR|3($R6g5TJc6H1&r>`yBd_#R9S?I}HO9O; zoq5&7yeb7=1zu(36@Gm%=8@@-3ix%l_}Pr;ibwG?@#^S|ywcBbJj{9367#B=dDX_e zY7M*!yvoQc{OViGBjOc)4l8~pULC{F#H(Yo@v2onvGFkHRY%OLcIH(l^J;P6Rp3=d zUf~zFVjdB%@DoMxGx4f{pNUt;W#pB9KI0k5`IY@mk;G3S#H$gsG(o>GQdyRu9|`>L ztW79WEBZXO{Y8YjM=_;!DWH~dCC6FZ}SrS)@ zi7cHN$)X>Bs1>qwGg+1fvIMeZBunB}Fp=eqjAYSIFw_cJdYLRefh>V68Of5k*h^%2 zbVjo1hY)IoEX$ZIeSs{2EE&m?xSLC4IWr?!^fL&xLY96e%UOXefh-xxk~mCCWLc4s zEc(HMS|Q7FCd=7@EP*T;$&xq^N@Q7;ku3UYfm$KUN+!#SK$bw3jAU8OTa`qXbFz`8 zO+NxqD`Z*CWLXu+63CK~ENcW=)@CG&zOP>^WLd*xIVX@MkR>Bo)(Nt#&qx-12ft>n zziL}tn2{~|CVtJZV68Oc%-WNFGs z7X1`Lt&rskCd%$1yLm@Ur;Yzb`1$ddwgk3hWXoK^7VWpy4S~dU&klVPzh>C- zJZ8&t16u-HGO}e~!Iq4dqdW9n{F-6Q3z#j>4{Ql+$;g)d1zQeKMq=w$^mq4`OC9>w z{WXc7`CA_SQs%Cui*|J_Z18{eZ_>Y&nek`;Citn$7ZN$>(*ZALp1dgVB=97KC*pof zz5HbJf0#FPzvZE^(M{!n!GY~#L!;&4ksV{F$E?x!@U_d9-HR4j;w)^a5DBubQ-0nPS$F>o4SI!<_na$LVqOE&c0~Jq~^j_N>wpB8kJAT}w~tV%n65HrmfMPnJY0 z)~#(=x7Ma$-P-c%b9>j8yL%gS8oey0(RJJb-M}5t^?^o#MkzEB->xbCgK0zCF^O;0 z5RGsLGyXYrb7#4}E}d43_09j`B(0)>oauYaFfQ5cG@{!X{|C-1Jx+GAB!AfaMzznm zDUcNXz8ynnQ-h9cx$jH#vGI302jWW{cWr9Z6 zS4X26bBf_jOr!e)jRK7_(&z?3qZ_NEk$#HdxysqoT|KxDQMnU=8xRY2nd7JnCvzZm zoI`fiolSi+ktZ6NR_;SQ5O@@Ll#xfT5j=WPbv)9KFnfhs34Tj5mgGDF|H*o$Ce(OE?l9T^s6JcfqP|jXStl_qO=L&|9N^ z2C{eXcw(vMHn3V}Y&1o~7UP#{o70<9AS zT0aE>=?5ojg+QNW0(~YBC=e(kfi?&NojU~r=|?7Ng+QNY0(~wJC=e(kfzA^II)4fT z($7lN3W2`J1o}cCP#{o70$m^o^w=p7NIy$aD+Ky76X;8UK!HFR2{a@Kv}Fne(ho?~ z3W2`D1bQ$KC=e(kfi4yVx?~Cj(oa3q3W2`H1o~HR`T;ZO`+-4$ zK^Ym;B^b1H3JlT@Bh(Coe#8v=VPH^TP(}uI3kLN}fkFCdgqmT{PnbbJ4h#wm%E+Kz z!Jxh=Fi1a+ko+*@!|+<(&*E!&KP3XukCFd^x%BhErNE^WF3C?jeBb3#{s;U__k|AT zXS$Ym$P~DypImsDbM03#*M7-d`wesL*MVz+YZ zV6Od{x%Q{PwZOHET>B|=iMaMNekQIR$D^AGA0la>Z~acNIy?e zD+Kx%6X>6TK!HFR3DhqLboLYoq#viK6$1T-3H0wkpg^FE1X?Z#v|pmU}`ApI;wtq`cl1S$jq z1p;Lx&_+R^$4!Ai`T>brASYv-hn`YKp6=%APBUndIGiR=M!p$K>IL(<^}=<0%au7W8%S|o%0fe!Yt9yDoSFB#v-`%jhv9t56#w827 zPFcFJVQufS#?IqcuWDG+*tw>mud%bQVcEL1ojv{Qx|Xi!?P=&gs&Q9~+ zCCB%#I=7*_*9c1uE7q+w|G@tm@GpABy0zui=k~5GclS2ra;03+NOKS24|naNb&dS; z#vFdt{ZOJuBrBSP80lewDS;{3m{R<+%ar0@GcjdsaC3QhWXIU)5oKC+%GAnw^^x4m z91*w^xRZ@Lg%7&iDSV_l?$q{iouipMM+NQ#?quZ7y99UMR~>h1`=rjX%$;KbcLH}Z za_23AJMXBDJGFgC=Q!q0L*P!}PDbv$QE=zYRdJ_HKcAEQRu3lQCCv9b*YzxEv`Yl> z!AuKd)1RG+M|sS`cUyXq1sg_X`?5P#ul*Lpz%i+o!Z+TA2=+UDK4A zklZEJr$3XN^;9N6v{||+5F`*Jg&=iIh{n2HuJD2C2%(?BdAJhdlt73;h>V1IcXfo& zPYXO;32|y5L?A>)LcFy)Lg+^T9htqcyi_gC6y%no`BZ~Zj~ z+63C9&_?`*P5uGi>7d_UdrNgRnlU@*ZA_!qK%+pTj5Kx z^Dpyd^@Y>=ZT00u9{Fwc6@f>AM;UqaZo#A5tK*S=jG+e3ZLbVm30z6xiuklf{*FxC zFsHbio5YU~bWD6eVL5Jko>f}1VCk7%3oAd~K@aqqPV?g(^i3N26_3j2Ir~cZDUb1f z&m;Og4SuI1`V|lLLaFi_9{BL)YW$c7eSl_F)XzY+hR18?1nvaxq;RLm{fhZ4P2Iov z*&N=k`!_!~;W^*O&&}p}*%Y`o@hOIfA=lQ$TwBXr+rV5~AGj8{mXT}!VJ;EZ9^z-> z+FATeT`UJOu*j2PbNUKwFqVLxDhnKp6>ii6GGM6bPgrnWz;4UBU#qI1nfh zC?kQMAP98n6bPiBm8ca0J%I@{90(K$l#xJN1%WP`0)h0i6tzO2txTXx1Azj8G7{)2 zL7=OrKp_2qM6D2Lgb8$6AW$GsMgl!i5a>x$Adr6Qp;idAoe8up5GW8RBY~bQ2=tUG z5J*4DP%8u)WddCu2owmEkwCiyfu345ftnlj^9i*=pfM)UjzFM5po|3CEeQ0qDG*3M ziLfhiz=y6~IA?m|hc%V!7vujX@C27GDo1)&PV(1*aY*9|X3);SpunJv3_3?JXw4KD zq#s4783tX&47xHfC@?4^gVqWLt(yXa^s@*x!=NWJgRTw?3Jm&x?41W-9L3duPtr-I zhR_KKATT7hW#H~4OSXst(%s3vSklRoY}pt%Y)QrrLN>CDsiODZLP>!X5)xAXBy>n` zq<7MRGzck#kU|>&?99%*-MP2rZck|Uc>I5?+jny_yYt>RW#_#ap9BqQ1g#7}5blf+ z8G_CRg3cm>h#;Q?t9doLD2) ze6scrV2QK#Pq^l+Ere^%+Tj6M!~G#b&e~OywJU+OYk;+@i8W%)Cu=VPOPsZT!8K>? z2)O2~9a%nWN!)cJ0$V#=3z%IGm|aJh5oQjUX{I0Nn)u zy_WzYfP4aUng-DJ007~h2$2bCdOr~KJ|c(+@<~uiBd9q5LAWbIWC;2I5Og;YLH)UxdgIbPo{pK_Z9<@<~vuMo?P-f^cVq$Pn~lAm~Fx5E0~)pv4+NO9Bvt zdm}`KppODUA0dK>AfE)aYXlwTi=e@tTsm85PT>v+Q> z6YVP+yIoFsWqU`adzN?1&GoG^4}48F_6!d6u3X*D{xq^r`ApXMSjex+4iwndksb%V zevIQ`zUzn^H)8DJ@NpuANbyHX{5d-*@#lS!GBr9<*fgPQorW*nKQys!Qw^fI3y zc8DE+?9_hG&Q9%*%3~+m?mG7ZJD(zUh#jBod{blRJLRzxZBL#1ft~w^9b(5PJ73Y* z`C57GMB7Q{L15j&-k|04GPdye3Gp?~)w}`Kq9Ea7|yj zF~}Jb4+BOI5k`cOPmF$`Vf1);7~x(z5ya?Gz~~Xeh%oYr(YG{=zFQtfxT{VCG5QQ( z^l8F~F!G7fV;V+ZFApQ!UnhbXeGV}CEMY_#`NZf88b)6#4+a$fx7^N6^Jhp5CnuzAU;Re@l|4j*zn25SIc7qUu=&68;=ni#D-5c zJ}=ow9e;!or82T{-NeM$cwxh)4Vw#_w@rz#mC-SK{K}%LSwa5>tZaOpupw+5u+h%2 zsreGDbnvs+)O)PbFshmr^lt%1-z1C(BcB*)p7}Luq*fY6_zHRi9Z|jm7=4>CB8+@u zr1^8zr~sGJFv8c}BZ$%W0Hf~`Mud@1jJ~c7>eOm|X&B+F^%2DA2Y}J{2_wSDCq|EI z7=60DR}AT$R=yMuIWxnvn zod_a`(N6)RpAbfbkxz`YSeF{L4?szCqgLGCAc7eE95DJBVMG}D#OPkFH@dH^L0v2E znh-&ZehC=;f-oYCd}4IJhS3A%VN^9<3{L_^PY_0gkxz^s)G&IeJdCQwi{V#*(NlyG zVdN8|hc%2IDGwvui{Wxh43FGKeLAyX-gKJ%uWP|{=lmw)ld-e<{8`;w{ns2GeQ)*O z5J$w3PmZ)bZfibS9!IzvLj?S`e@m1k7k6_?JA9zk+d*MD+c;)f zvSVJ?F`e@pWv|08_%@w$^L>_6Jd$ibnic#gk7Rqd>vmXYtIln#Et_yaTuQ&+tSqR2G`tq`_*urGQM8}*UiTDu>n}~ z_F@PjYk!ceJqxV;30V6hu|}-VtPyKIS=$p>;;iij*PONE;hM8{LIBph{UJig+6$7kzXEH22iE>ZtPyKIS=$>} z;;iih*POKiTyxe=ET6SD+-c%M`vqH+e~zX7O!5l{q_15kS4 z`gQ<_19f@;fN=MTr~vd|0O&si5CP;9pffap&I|w$?l=(@fGnHB|BnD7fP4aUmIlz- z0RX~XCL#h*U5)C2>eyn|3UfSKyTY9B)pkosw<)P($3DdP1Z&Rn#PVdXs_}Hsa&=Lk z&Z^H1Vx3L=CZ6wJZRS|ty&BRC4j3~@NMjaO&u4i;T;FSK@@ghYr&pRie_eMvZwiMq zdGmL1_E8oy+^NL%#%HVC%!A9#hS2z_DKj_tTgzM zaRt9JuHa|J75vU9t7~PqcqpSR>qW|X(X1|bS+*VaevR4$fdC?ad;)Z}2GBJD0K&ZE^IzM@&f#N+|LB|2)a-%J^W2?dvBuA&9_G#37ll0 z*X;%by^07Tf_xG*q7gJ2fFN_#AgToI4g|fL2qJ=f5;Ud}v>^aNxGzFv`k+05pgo8n zBFHB}Cusz23_uX>j1U=u_6CCXB7%q@p9F2v2zpBZf^cty$PlzI5VQ{wLASh>){(m}KoxVC@aS+UtomV$COO zy8ug^wO!$wv(^dMoVBj00?(whzdY&1b~hrfCwO;09~p9bXnN|wIp!= zgs1@YCIF~|03v{V0(7|s&=mmy!aWfp6Vh}H5Og#VL{yhM)`(lqQ0RAfE)~G=kn7fFRr%AuBOr#Jg{z!>GYbPcCM_;5&jgAyHO>CVy(nKbSBNLVP)xFTm^bkA5 zjz4y4erso^=J(~X6K!{$Jh0P8><~LX*?Cf9=hx-26KzkO6~InEu|w?mWalRuJHIH8 zooGAh3<5g?#166Jlbs)E>^xo;J1N{h$GTTffRiI!UK1qQcgc=~d{xjnxTY`N7~~9z zm4ML@VMG}D#OP@aqi4&*2=~&7AV$N0(JI1-F!G7fQyNCUDGwvuRVRWNtpSWy6GnuQ zPmF%1Vf4%LFv9(HB8bsi!01@Qh%oYr(T_BYeq0_#xYN#h%kn8-F;xfY8LOu5XXvR_ zQhfT8=v}$Ggp>2sA$okV^f&^90C51M27pM^#9}qSD-Q_V2PdpR98W+H5I%u;qC6mQ zZ-KA^aRLEBK==gWr{w{Gy8wh0hynpYK==gW`{edozHT1@Hr5dv#D-5cepMD5&G@=}1lU+lY!Dkh+4y;RY~YLS5nyA4*dR81vhl-> z>qf`67K{Lu_1h*!$H#1OD$V#x`K6Y5g*>Nsx@*C7=ln()={22MFmF1&U|!dP&iV6; zV!o2?-L8RO|hXWnj*-!QBU_rw;s;2%!aBZCZ6x+d_ z9(;j()Iv|$D|-&{kG+8=<0lasgoXne+S*?I4eq9oFKS<6F@4!_bR7fT#&o9<9h_{R zoA0xP2`AZt_X-{>Jfr=_CfRRnH2V$Kmz)fqA#Wi#2o480wBz0DPlSGg_ZuIEYop(& zx9r?!9L-sOg*#06g7_T>Ol;WI*(8QuolVB@i^0W)UvgBIK1K}4W|6W}BxU13*=C?@ zf+!=(d{TB7P{k=*57(TsE8&_`c9lD2_$s>tWod&li4y?EraWDWyIG{{R7u$uplmBp zHc6BbWj-mp11RE@y&bMOWmm&Br|cSc%J8N85957Vm)VyAQx?=R3^mc!S-+mW@#8kh z+!Qdk9hf_fm?P$VGWQN(iZgc;Tyy5Gg=@~-b?(gJ-T^lw%o&}UdTA#|jShoK{_et< zsl5zyvoj=Hr<-iqos!QawumhUw)A&;Hv>DIt#`vUXX|=*mT+%^$ZQaJHgrg55i|si z12o#1?e!x735RCX6_OU*tspXxOamn65F`YNPe{fzNH(}bg8LUl29omtl5+_Xg2X2z zCuxvubcY0YK!^+^7XT#Z6C?zQPe?Xtki5km65P*V#4^7x)z5%!rEG4rJOd%b7ZM3X zf&&S0AJC7~2=1YpU*X$RS~oVgxcEMIwD#QPB4jqMVGh#+!+NPFcKzt7&C#J>*L#w)M* zS8>S9&B|MF_k+lc!7hU_*rfywLE`|8{>tlofP}yDy1*S0+Bt9Xz zP=n+mcS!KX|Hwdc6+m(&K|+xDgydokl1tnn!B^`e1IaZ2$<+i2LE;mVOEpL?bB6?9 zh7av4uWN|}BEf+K?Uh$-4_C`y6!Eq7>!EwNj-VhY9H7u=cD`19q2v># z+W;MolHN;AxT4gGFYVum_fpm|Uf4)_4@%N|i6kP)CrP*4Ns9jhu6d`l87E0d9pl1U zale3bEQIm>!{k}3_OMB{53PIml9jZH*`XmGXeVT?0rC?kI4X1(^WjuaZx$ z3@{Y?5DdlcA)bgQe>}zRweu9aKOj%I`#}WGDElx$L(n)tqYcku54k~NoLn}taoxnk z*f_csOsluEL4YpDJg5x(a~uY0y#czKk3v`T5u%2uaiB&Yx^1&}HE{=L17ORQBHS0j z>ar7Ziarh$eT*m~ihNR}#ht~^2VSh_WrEa|BHRrjLKJ-hDEdF5h$!+&(FIyxbRqCk z21U5XL4+v!6j1a@qKGK+Nzp|bMHdI5s10{Eh!92h0Y&!`MMRNLiZ0P8x-<|)xI;mN zD0%=Wx}PW_ihNRZnMTp&fhfXV3nE0(LqO4kL=jQslcFm$imnVq5$=yLW?x)ofpzWe zgPD$mIJVE-mCgITc7l7eB^upg=PXWa>LYhzdzermR2)#z7J=dphc^pgiXA?6&x5wA z@jQ4Gx|&CbAL7S>A8k1(X4&)KZ~~2e!>z0F!4vLz5J69#&j3%KCZ32VpFDljK6HzH zDlO!^2yV;HJ-i`kSE+>A%Z-80eJd6@kBiNz^FX^c15&@ArF)amR)T^7M7!>1)Ij@#K@I$26Y47Hs~s7k$^nm&JGde>D$25w}>a=$tO>bYCL^9AWv1}AMst_={v*| z@#K@I&uBb-HXu(`;~(*T;OTqB6Y=Der_X6TeLf&hxPQbw7Ux#;pp|*knFaIai7oKc z^PAWO{|sAs8(%iDjl7L7%{{!^+gbGbV0Ng3{ZIJCb|=}n5^h^`xokG%um=Rf)ih1LFHBG0R zrZbYfWY}=~35wfK2{*#cCvHE~aQiu2^X~1zfVklv8Fv=rmXMGcLrpfgl&8YL`7rFL zKcA<=%y>8VGnBiZ6L-X&Pwu`Cobkw!pTRZf?i0bdTY`ITL|_lgUl2qDkpo0p_+so+ zr9oosYPo4*>(r5hJ-KwY(6R*YoT74Y#gn`f;xWHZ5Htjh12lTf;)~GJ@Sf+tfgoCx zzr-LiDr-(X#;|su~x-XMm@ti6`R8Cr|&;c=}&Jo~p(L@LAyL_rw$N%jpOE~%G)P1k&7vf}Bp(&O%NJqY@SnsAvEsmr z7Df}-w&IDGxD}6N2VZ^<>kF=b5g-JJ10dRRVf+i_btd>KA+lk>ylJ*IfVodVdI8&d zY98MpU^zRBby=c=T^J&sMt;S%qe`^T&G-2^q&3;dHk>k!VRhJds>FS9{>?iXeIKg- z5Ke@X15VmLRPlT5ekyUxR@%mf0r7{*!wp}0ysLPB4zUBA;EnG9mxj&X_~vl-uNZ4d z&Kf|MY+vDX8@R@F)9QVICGYhE_qjH*%_aAbtUeMFS|N?K{m<^?jRYQ0}Sp24DLt_5`#V&{Eo(; z<@9FGpk+6G&Y&OBb=M*Y<_c*gnJ%G31k>w`mN$JqSb1xNk&c7!1<4Ebc}9U4RL48#!b_z)R} zUJDHEPYe-5J{h`0W9ZI64B?IokzwcnVCZ$k5HaMFp?7Hvy*m&?xW_?c7&-_TI*=G5 zhI}&g9*v>*24V>JH;4>F2LnTm#1Jv$lcBpbhTa#5A>7;G2FrUn`5M~@Y)UVf$3vUu zH?a#APdJYS9kS3uLwro<{P|_P=1ynXtGaZyV{Wc*mGqB8-`;t=?>>aXq`&W;OI#6G zKDqj!#?|eCxWfGpBGWe=27S|^#1Jv$lc8%ghOQ075bk{t8HU~f485KhB8Gf2be+b~ z^??||-4r6j(0pKM9x+4=`DEw@jiDO@F%)s%g(hHV0Wm}j`DExOjiH-^Fw_!p--W}0 zp@qZ{G31k>w`vUC5{RLQ`z{;_3>`rX5ko#1x>aN7wm=Nwz6;kmzVDvyQt!IWO}&hl z-c8f9`?fp5QPSUbCy6Se$|qGH(5Sk)EUHGwMr<1?wBT+H(K|sk-U6LfGhszo`NJwU zV#g{rS{bZxPlpI%)e2ZGBCH52pID7)SZ$~bR=D#+1hHBSShW#Wgq2UMPSUX2SQ)Hv z--ifd)ecxKA*={1pIB|uuzE{nu)^ITB8b%+0jr}3E5gbrR%5y%3y^%O+*l@V*sn82`j?NCsqXws}n1N)gs)FB7#_T0al%a6=CHQ zt92Sy>nnp5?phH+tTKRAny@0Qd}1}IVKr14tZ;9O2x8R@SY-(-!pbLBD>bZERR*i7 z@v>M3SS=;22rHjh4Qp7ft_)UH<7M$?z$!;r5mr92TBBigY-O;*y)5pry4&-L*5(lIOXaNRx>yF6h>*!je6956Eu`iz|h*Brb4%3y~(ZroDb0dmZm zrqfN+83|xAY}ECm)U6=uh&rFtodT3`>bAi(r*5D!)Zu;|cNS9zC&{xd&e-Ua#db9r zL(#P5QSLdz#wtr}Wwl|!p)d_j%{wAK(> zgqBaV7HeoNsT^8W;}3EiptY9JBD8#>)vlp+ROQgB8lR980IlN*EkesDS_?I_4zC$D~A^D>=8k4 zXuY9wXjP3j##;cbO@tPqwMS|<})gqBaV7HDWSRSqrO8{?D3 zZoCj2CVl7Ufyj&(Gfoz^gs-rV3A0xNbJmA6z+1anFti5loG9#M#l|EY^jeAI^_b5yy!$ zuX}m23WT3AVVZvdC$88SUXftLzHG2gN?1=dVSS1H2e57>SP51KSoN6CHvxBJ7PnS)9a0uAQ=|4H zVi)5c9_QGHZN{ie4BPBuIQ4qoVgHRrZ9_MF^p@nKw`9q~IQC|K8v34dh#g|bfgQc? zdB4{8+*28raF>p#uyh`vD)vX#p1}cm>>~SE$gj!{6w+Dj%tdxE&qw9S+#lglTS<1j zdHmxL!1XZ#g+OrtB@O{w#+i%ppTV_pP+a_exHgUjuAhSIX5)Gr4wjJitm;V?Cf98* zY~D6ium*Ic@P+*Iih-NXEMUk@cP;3Yuq7;fCE8as200BY-@Q7~-tF%!ELIu+XX0f) z`2G`w7vbfAmv-=d{F{Ie$Ln#pHt>o+I5oMxux@nSmZ`Bx8!^rJDrHo*Zu%7TMxP{H z2p0!jw4>wdhXD@*m-^L?ctmS`@?K(q7;s=fix93~>1gxOT5i0LY@Tf1r_B$RHLGaG zmllsIo>g=$m{#+NdB(;3rg@nK>G_Q%P6+NVo)GZ4LG222xK_Kubiu6cmXdB$QpYAP zF`jzP^2BoESYC0}knUNoF6#N2zUCL~MS%Ju&hFIAvA%n?5;w3U`Ak;)z(`{jR^JN+ z)b|>@TbN1G>6K>JS=XJ;o5JBt-uzvheU!xvcPeqc@!2Xj^Wbu`Su%cVij9w^v|%^{ zrLzmTEq0Mo_r)%n)x{iE8vMw(f?pX|@H68IerJ@`wX)l+Jyw?WB4xd3Ru{Z1+ZFtZ zmu347epjFAAL#6rMWsQ54Z{Oj^(3*FHo}R2%|613|FS&G#}^4(i!DDPr_q*)b%{p* z02zIZ8#)<%nMVID&FCLLX>4Ns_{qt&spF3@&P*TKxNc%%Y`m~x(}vCP?#Q@mPT7xC zZ*9hx`<^Mb{CUdaWpi)5Rx&@ccTDDImP&nA@19uqz~#n!DDj#9!0a~IPuc5V`7T)g zi03SSB`=^HOEK!kWPWBbJSSD6aaXLE5@CIiU?o`jD5K0Cs^%a&tTp=ufE8bBBv@;g zCyX_lhX_`JH4vy8?%a{|C>zLFlX=Df;AAVF|B9)A9n&C z**rcrGPT)^i8Vwm30r(@3wbNKg83x^lfVoF<{#}~*8SEenB%E zE$mOJ;VWMuI*5)Sbku0EW;NfDbh!HM714ov0nIWUUnM$-jv#c@K5XwhY9Ez!xULWu z(Sf_&%rYI15gkNF5IX8UV5g(*9y~bT+(mK`?$6R(Jc3d|_?=B%P3fjgsiUH=k!6!* z2eIt>TkMuy|9|e5jXQtz6k9giMa3BX&*Ks7mJL#k`9YKTj#)hWo>~5U_C4&28jBT8 zlUYRUH{{NyUni3%lMiI_@6t^EJ#whyI!#75omhnXR~(J;aLl~)G4uFt!Imu|tU@mY zz9kX(CLurw1VNx?KRW_72M0g^_gX;q+EVrpJEW9i{@;=2|7|jVGXFs4{~FEw8v~d> z?gxOGf5vLS3t z{C`2_Pv#%U{CCjIf2RQEk1q+&%mC;~iNF(t03i?vf!#C&)NbZw%mMIKV5|pFjlFFB zZC!#_5AZ8#{!fwlllccS|5t0~zi)sZ!2b%c&DtdbiU}|C|BW>NUz7Qh`3ExpJv8&* zOPar{yEFa<2wwr7nE}x6Bm%!B1PFmZ2t2PL@b3T!;H$uu9{@cg&HrgKe=`3-=KojC z{Qnie{Qa*02O9uAE6xA+Wd3CSfz1DJn)&~ueDiO^SAb_`0Q5(Rz#j+!LLd+V|FI)b zr_Kf_eGbruuL4(o0Q6^R{(mC#C-Vp%sq&?*ZoX0_uu$5cYJlX@&lW{NmGA;Or1i;8CCsPk(>d$DV{w!kZ<_3a`@fFqO$W+wWV@+(Y%s%kF)YR@eYWp=~ zpEdE7hlgc-jcM-nY{#{M>{4@8%lK&CQSAy-R=Ywz1uZ%1BnQ;ZbGs@~(*=<%UE6aM3vR*W+3tpD(3Vy}QvV8}?tIzZg zboR=k(xAbH;Q>$~J4^@6JHgJ@sn=p`>yL2VSa7jf=h}JA#~>EZ4ZhQ|r65~UGWHoa ztlZpQ&CAT|q?y-}nNzDCq*af;Hz``s0t|)-Q)O_}XbZ(#V@u z&JKzIGiT!*c6>zI+rZ~Y18*P$Cj$>+;PoH38@SW<$X?AmzKXgOGkn-L*)V>ve%Z*g z4VA?gUW1$+B?UVW1w=s*3gSPpQxJbbx{8&)WAb8rm9-Z`feq;S_ThYF&#m4zw^h?# zvB$XA+H3vJ5{R7$2m&Gq5H$LGTO zK;c2$L0`J;ZJjh*uF11Vj)ZYPBuK zYxfTT1ir580z}1nh}|U+uO=V}h(JJSn~vAMP6APSwAEsK_16W6iuDkCN+9+iAP9&c zK-6hl5Z28pABZL9qNcWd-~vR&dWgLx5PK021VkVpv`q=?c0?Q`3{gwMwsy7zUpjU& zetnW`oiB)Yt1!9tnn3R>jej39elq?b#&30>FxHXlp7&||_`T9I&??=W@ z#vjD^>z=c}J*xYQ>oW2Zd>I*cmS|#22u-#ZrEGzXzbiG~7J08FzgAlL{$%B3n0|~#_b+M#*yn2V<*{%K=}Id@z|moGk@+3${Z=ob9l{5ZGp{5 zXLc7NA@?rwTx2^y^71<3g?I_XOQ)TeST~Tde%r+8_?Tb-q>j97n%FvZr0ImT1Ydw2 zabQI(GIOVlCgEtU`D8f2WOO_JdYFSGF$WScL`)!JCNyHU0vkby!B?nD>|La9Ha_1L z$H05`E(c3i8i^HRB@io98Y|n&Vnuc;_?qr4oMCJ8_3ZW7NmDrE$sKkC62$i-3zE(XOvx)fp_Um{I^F_}J@eh|~InP)fsnnPu)Uxw-9%es{{{iCGmx0C6U z=?60X12xm%-*pu#iLb1q8`%!$?U~$QXID=)(R?EjgN)=s_Z}^oo(bhmbdpN8e_3!ENE#B!525iN?3Dh)aLEhmc-Y0 z4|Jr6Gvi_5#}r#Qe=M?avT%8Tg#E+;i$xnJ4%F27vS`h9vn`3Q;-bcE40c2Z;9<<2 zWXv?oDQTFa8}qlNF}uE|m%|!-IX3*mnyz9_*svx|!;rpnT=uTB( zAF94$5ZGI}JiV2pw{rg8%GDode=Ao%g!|Wm)Nw~*Z3pkR6u$O&5kitY>2rRGG`Tn@ zCfRpM=HO^LD0U96=}Y@|P3%XpT0vM5R{pSx9c{-db^riW;Z-^X`>A z70GD@cUsZjeaDWeoPpy@qzSCwa5~Y!hZoBrnLN!Qg3KXeU6nI=d_6PiVDjhz4t^Zc zhsfs1<^$P$x^gy;FMA%2**rVk3eGV!55Mwb?<>jP$=(Cmd$w$Qx9p|e)?C6OsqZEJ zRb<>`+<}aHb7hPhUqd|)YsmQ<{)z>l271RcT#OHUb-J3~@z6USpYM3KXzzG>DuWZg zz+36*@0w!s=WPkS@u4?9{@(aZx|zG@`66x2_`+~A)@|^!3Kz&jJ;hN{#yH7eNHRaG*J3@KvT!plu<7;-^2g4WYuKVfvo!RfL4vK?^b%Cava$?*?Ay4|4BeQ#}`~L zLk24Ilp{k^CM>=T#~1U%=D8=(JeTIVKIgelYV+Jrmd2CmxZI2{>mH0@WV|M7O8Xn# z7mDqhCbAT^=Ra&O{#beTjIY@?A@)3NxG9K5+q7{EvQNuCkt~}=K0!u4@gJ0D+4#!r zd%GSLlWqBOh+GQ6n2UpArm66OBImO0(&%QR0S((|By6Id|j}7)7(U+Nv0XdG#{3xi7(}qZ<=o*((4<-<4UDu2etFJcstKMjNQy({kgteh8^@0TLtg-j57dYalQlC=(?$O zh0WU>D*YPqoV=oj%nBP~6;^3o=o%2kmaB#drH0MnQ^R4J8tO;JPv%PH=HB1ax;V`* z4VyoUn;ftGoI{=G@`a%_{n-w~JizR`I{TIvR;AOqd`I&U%^C&D+D!v%&-F1=YBY_A zT?w=EXYwpU!8G|(!&lcat*#qHb2B=*c}rpBlr4qz+ct=H2Na;{KANUKsnoGGeCl|> zu8#U&BI+2~yl!&q*xFjQ3mnVKW#t|3^%G^Mn&EqvPfu%?|ST(pDs&{5aUX-YfW z!>65(Xxe$wSvyNGbfVduovu`JM)*|nQB5UJIjdxG^{C`brING4r;?9pD*2VOO4_PN zC1)#@oD)8kd|Xq>uboxWT0JV6Rw_9+d@A`rO(nl^R>`93QOS8qCFh4vC7;k#@>^$> zv{a8uE>J4DFnlWcq^6SJIjf|(dQ@_eQpv^PQ^}_^l|1dNl2rAmNN*~R6$z@6Z?E2|ba6-cbn!uri@zbdsG`?acPd@HD}1`RN7KdM5nZ5j@o2uUVv}6caqd0g z)5V80UHrq;#rl&{1=B;Til%yOHf5^fuJEaXjqwbJ;=ZN14DT-fS*(gGn(46tys3)! zhffu^X{va!SQS+?(PLvqQxzWwpDNgB+eXE|id9iX^E@_8F;#I-_*C&WO%?wxRz(#} z^H|Sls^Y`pQw5v%*r@nVu_~%)md9LTO;vm}e5!bdri%X-tD=e~dCc$9RK>@`rwTR$ zwNdfEVpUYp9FIBonX33i_*8L+rizz}RZ&G#Jmx`Ws^U}OQw4h$V5OoVW>JL^57>+{ z5%m>T=B{L_1Z5-YDq+4crb-?NpGwZqR8p&{BvqAu2oEZiJQO~a zumBVrC3U(=X6wyVF5i>MS2mLQVWo&i!l#I{G)2UV6;bG2%4&tj)W!zcr~J}f8bbPS zSvok-p2-b%cJ*X4je`Sx)3eUOHGS#E{K_GAh98T=WJx+?l7%8khe*P!yIoW||7DK- zqL63*uuWC-M)ZC<%l>Wb864nOiN+$^{|Z^ zcGR1O=2uSB@C|AjqR=$VmgmO|G!5TWO~bds*EF23H4QuIO+)IH(=>dWnuaJe4XD?} z%Mjr(15LwsRMYU?@HGt=XibB8(%qV+2d;IF4tBk`;7H4Z`=4`cfFB7 zy?>&vl3y#8{3d)Vxm;7p9=b|UuZyUw*VVlQ10v$eK31B&>)QpB_2Qv}=d-bTdUx*}$4C1(Z{@du@dKZZ{cS8Iyc zM^gm)+Wci$QJVoh{7LEI&*9SpJ8i%Q#J-vyX6s$~4CvuGrH8+SPY>5>de~3X!)(2n zoB=&Nuk`TO@ach_^I+rQHJTn~>n+d>=-~yWhrfkS57%pY*k98FI^~XL|L}LEhkt}m z5A3WB8xOD5^nlK@qp62~Dm}ayK0Vy1>EU&n9;$M3{V%1Fe}_*a?Bo+083$+@nXS3? z47iK_N9p0e;nTy-njQ`;(!(pp$>4vqTo8rjf>}EMbOsuRmt@1x5DQY(*HP8oX z4Z|zPjl7|T8ioio472s_vGNT=L#=8U>cZDB+@duMjatL-%5frZh*QH5-iBfQwhe{R z$<15VR^#NZpGqA-&a!Mz(*oO)bfCbtct!V@ZRFMLx}|JVZ6_;sNcGxN zR-|fYe;P~QRkmSg>Nq3NaiSyYs5jHQsODkU@HG$HwdUba(L8LLIBnhdrqROaI6jz( z0%Yyi|TwxnU2bi9N%o ziAhZpZz$3P+G9kMiM^C2_70yWwrZM~Cp0m-Y3s7U+toqMmwxrHI#tPZ8sqBARqXR8dF$ zI;DsM!l#H+G({}b6;Va~^npqd2Zc`&6Ph9p2Suia0oYia1GA#1Xn8 zs;G}RL@8o!_!O~GQ^b+FBC4p5I8-U(u<$8jlctD-u81n?BVMl*@rLjz;w_pYl0p&2 zV%dgG6Pvbf9IKuQ-8`j;`QcN<22BwuP{ice_}IFwV^uS;UZC{Q6h1wSX?kb|Js5)~ zKDnM9P0YY*~!y?f#Y~HY8>)5O|(KE0nlT?aGg-;RdHAS>q6|r`<;*V#bqij}MXbGPd z)@WL2)3o5;N!~eAPCfQ>qWwAc@ZYc#rVW1}cK&d=9zKhxw+wG@DVpiEvlSIT1Fb`= zY8~3b*E$@lwGNAIt%KKIoz>VnET+~W^sU2e?bR>?t-})4I<$wcby%yl4ohsUgV%PQ z)z~^5MXf{VTZh@&L1YG6hc~L$p(A{)!*N>c&~9rTyv~iT#@69Y)H;N|b(pPvZDyc# zI9jz1$AqtSI9_WVjGWTgj3F$Y#o+T>k#_ZVYb{u zXP|Xhrdo$w_*#b(wbtQHw${OG^RH@b9o|f>L+D$F+45PQf!1NUY8`sQ*E+1zT8E=; zt%KJNVAa?<^it~(-qvCKwDDxY+(ZNM93C*7#&YfaU$#|F*UIkp_V#p7XK#N;zHeby zXW#O|s&qP+?`S@vxpCD%w!1yw-QAe$8^{{EG6KYn zw^7$DT}LK2*xA*S%`6mOcZjcZeJp|TPb2?LZXmm~kZ1oG+Y|BZ*k8j_iGNO%ycN+) z?7t##nO^#1aidVBuAWRDJ`b6nP=_!O1lknVmAuOb{ZPYbPjbU z)bHk)&jCNRCSGk%T%XDIbgmIe>$%UC_}suUQ8_m7e#yL-2KEc}%^Y?Cx$n@E@67bU zm%VH^DRs3=hShp{D3^x>_37@O&ZTC7`AlYDb<(_G&&0H2UgRv_%oz|5AimmZh+idD zA?DX+HVh50HU0~}n?Zk1s#QFUu{G`NQM*D>I}koQWHd$Pj=okQ7U6VsmVz(5!-6&M*z|5q%p}Y0+nBehse$9dr-1=Y1KFwzfM*Un zX7!&CzUpW58e50fJ-%-1RKeJYVC#K!Px zqDRxjazqpElg%nQI$#scI>WfoW|*VVOn2w{a)ZmVnW}0T*cM%8%W!h|S_bAQVCyz} zFjc%Fnuc*|8p7N(6ovoh44Z}qE8iqG(4MVSN7(fxPh-P6kH4C9`7T6qO zZ8N%97|mC#?C2P?Q8+bxjRM>G(KcG>Q;h;w!)!TFvI@)OEBmIKomOJ1VQcu*(4?s$ zZ&O2R$t)dmJp*cBXF-~3*cLuDu-!LpH1ylmFk9QF&43!%!Goq6wues*hihtBVOPU! z?Nc=aYB*h~;f(O9;RsC)19mmc)`mbcpoTM*8qNxz8ra64wnk~tu7=s#d1VIFaJEvz zIpI@7LQ}(#T@ACf#l;M$VOpu--0-P^?Y?TGVWnLSv$dDN45;BerH1pvr-qcKhE;Yo z%vR9$45;A(rG^W`rv|nQu8oFayBex!7JZRY!^PoKLyM+{)pj*h(JcBBrG`txr-ntE z8rIm^Xcm2)Qp5G(Q$xF^h7;^+sG?c)4N46+ zhEEMgX=*6g)lfyV=$n)pZVsOs*jB@~M(ISm8med({Z^%hTf(P?4owZ~>}sf@S@f++ z4Y!3)4R6xau->kQDw;*#uGH|h@Tr0AaBORoMr>-RqDl1Il@{I+J}n%hX<^i+g({ju zzf)=9j__%rQ`5qjO$${tg}zg1;a%a=0^3#D)*@}NX`zZ{(C=1Scu)AWkk+(tl1&R$ zG=YAv(!yQg(?Ukm!bY1Gs%ZZFKBa~ChffP^CuduWw8^H0Dw;mut+eog@M)o2)52S9 zTBxGg^9Pj{?g^h3mTFo!*`|dmnmm6>#>CWf=TiDB_} z6B)MO1kl?*)ZE;ucAJDW{$%(No~I$a8L!o9rT9}s@hnrkVbg}qV!tY}nK0iu zSWz3zh{Agn@%M#~_%~?8Z{Zr4937j0rZeL8f4{2#2f|nXuh;7TR9^q1>!#Kj8y8kp zWbK1W4-bV;4-J|gCN(`&(Uk0ArH4ntr-wP39=6)`P))J5k19QUI(&NALDR#OriUt8 z()^6l!)L>%haELNY}52mMT?rBQ+oJ(`1G)oriarsJyg-M<`q-yb2%jEy)AVqbriUt8;QXf2!?(hxhgWNQI9t<070su=t@QAn@abW9O%LbT z^-xVww%=8H_+I$*u!p9HX-yARG@t&y(!&qJr-wZ?J)EoQp^E0yKU8}7QTX(*m!^mF zG(A+&eEM;vhaZPe4|{8RIA7C470suAqV(|7@abV6O%E4ndZ?oL^v{$YejYwO?5pYF zLQM}_`phy67@ zT%zfrissY5R(kkN`1J5vO%Ipa^-x9ew!c+s_+9wa@H$Nmm)X@&MYHLrl^UK2pBfI( z)Nr|74OKLm{=HJev*A<2ftnhwu&bep=F)#qYWQRL)NqidhAZuAsG_O#pOhN@96mKP zYHGO3u7)a_Nk6C5@R#tZ;b2V-SKHN4MHA`gl^XsUJ~bSoso@&C8med>{en`%-@>Pc zxtbcTwX30urqO>_YWPR^)NrV#hU=y#H=VTB3PJxs>!L8kiTzVm|#yYJUujkch zHRArR~3#wPxo~8_IKp_;NYlS-#~^1AhqZESc=BpTz^hn zacL~JYpkBg~VbtG9Zs-fo;6+d4K?7#%@^lx8oq^M9%eUkYCp)@oIFldQrj4d$E^qhLaPVq$E( zz=w`3I#2+CXFoXkxL+szKtdYDco8q#k0j3|&T3lZvJaZZOq5S8;u+zIcwzBOKGo`yC}rG{k*LijQL{|6*d5=Qbh&A>vU5q7`!VY}mlQ^VmSt9TE-7pTO=H${E-6d|O=DJc zE-5SoLx@)oL&&*yQWB7qFd?j@lvG#B8MKttM9QTssfm=cCQ?!pDQ8Wjq$W&W(R-Gf zFmXlGNKKfuqG_ZiQqG!4Nlm1jHNhX9X~Ox*o24d9n6bNQmYQgG)DpQ=S@ zg5~0pMreYiac&J-geF)T=hmP_Xo972ZVg(5CRiG08*Jg4sAB^T$5yw6D}p6)uHzQ2 z2bRRSid(oESQ2N;Y2jL^OJ|4qyk{3xF2Aqv_k;Gv@)H9|DVHBC1 zvx&A!90pv{NE`;7&A3(KFyL&)trCX;(Uf9ZZ{?b(H)`2g6|GzqJdv|5TKU8CM9#`+ z<;viRoVC#^s7PlA92MUxl)(&Iq`{OS@XO?!E3wVQV$j75+awk)X4odNa52L+u8cZ1 zm2rHiHbF(+?ZMkj*z?ZXYBQ}c@2smfvu^UvnrahD$mE^%)FzsyOkO~P>A=h+=WL{l zxen?wdFR$^F;@Xg;*88sThx+G~-3Yf7fjrk`dCK~#RFXld{?0x9=2f+_bj0xI`3f-3hkqFHlKBic3h zG@@a1Pa_&7_cVeTnFiH_O;>0wi&=M_Yc9N!r9RPecon;*;1%qef>*C=3SPOcDR|Yo zrr;Ipnu1rWOo0*NSsh}IEwjKXOw6!dQ+Su+S?OYK?OKXwrKdbAJ>^;HDbGq5GirIK zSfzVDte8&AEU-!!lWEr!o|P^p(yn=UTDq7-yXN6p>0$!ynulklH+x#T=c9<3v)gU7 z*qR_rEn?Q}nun+I#f;fC4^K-M(`DB@JS|;JmRJP zMV{ud$opA5Eq#$^rHh%d>(hExy60_(NwHfYt)7-HCd96JcviZY47=vxS?OXL?3#yX zrHcu$YaX7J?pcVK{JIq)roOHzJS|;JdtLMJv~+XM>o$xs=e({-c#XIY#>_ddYc9Ov zRW4X>>e)A#Q(m`X%qg#H5?=S}PO#SBobtNn!fW3>7jE$@veRw z8Cb1|$*yZLVy^3+#Jl>%OxHaZ@9JOTUHxL3>t2v|^@~ZadoK3s-_NoDJeXU`7n=E- zL}S%*Nf}NFlUt@H3*r@oQ{KEIC_8WQ>cS~+uF|se7Oy;<^5&gS*?EgsCHvy_%?+gN zti_8&hpai*WoIp3e>r5$4YKU4#alCnta%GucGlu$n?u$dfU>g|@96NXhxu!pa8{_<#oJIeSnR2}|@h08>W3u2U=f@N; z-Ti0g((EyZPyU?#Gh>muE_cS88vmKG=xdkE_`tz`W-OxKB{SY!`Ol2)lHigVZ%_PZ zX5xhPJBG(?X-4aclUSkfZ?#ExtK~eEkee$|+&27YmNGNLYfY?@_|GlrN|abpDIqsk zq=X}53Awp4C01%m$jue1W)4*exw%p$R)9*#&BO}tSW3LLl&MlYGtRsJJ4?A})Nm3q z7%gWGV;tJWM!&WglA46yiL&^*mGq88 zbD#uO7(+ShZ6O3E$L5H3$?#Vr-(Ls)J%kY}G+ABz9W(J6^Zu zg3ovzmIcL-*eji4NNkN5#gJeFA#>XVw;?LUkYE)@F(gHAy7=IH zrea7+a7rjShNRTIONk*VHSbblNJ`DSgcy=ivvvzU7~oyE@>3}_Yq#Ko0X|bNJ8QS# zg8@EfDLZSo;DZ4^*eN?}*Wd$t3`q%f&3*0N)TqUfl$y1h8nqabQnPkbqZUI_YSwOQ z)M7|V&DvFse2P(yg>W^N5JOVxU6&9;Qfk&E#E_Jlwf`8B5^^@Z=nRis>x(;xP8qiO z=arCicw$IAZ@R1)l1k-jk0Gg4uADs;>` z;vQWTL*kj4tG|279z)`pnX9|IXbb#5rmMHR*uL3+W~IcCcs^z+F(jUux#Fb7ka%WR zQVfZAZmvMtV@NzRD=CJ=Gq;jrNW61%MM{ey@y^YaDJ_P?J2zLTv=|ca++3;BVo1Dm zDZPY=aA4jB=Su?cW&o{0Osx` z-WX^vUquT3mV?eAG0sLY&n~bIkEJhoGQkJ(Mk4Ww1W&|YbQy`n%MLsde`RGP60a># zt#HK|S`nHIA(1cTxLW8O5?ghM)dn{UqZkrfg;5NN-8-LRNNnao=aAT{ zgU%tbRR^6zQanyF&)$>+Ozph`@3TFluIL<+q8XH^IQzg{dt)P#@ByTn17Ou}8)9O4 zPz(uP{WBFqQi4-L$uT6Q=3Pn*NvV045<^mI-X+A4l$y0$@PQUXQfk(2!3SClNvT=8 z1s`ZJB&BBU7JQ(^kd&IWYw&?RhNOh7ON}8ZHETCDYB40GX6>d%Erz7jtliY8#gLSm zwW}KKF(jpCT|x{=sacm0LsDwiCB%@FnzjEJk`i(*F@~gsoWm1C;(60$#gJ4gS9=Ue zrE;~$kW?sFErz60x!Pk$DwQjLNvmQ=O3u~#!dymF=`kdg$yAFWVVPDghQvEFSEqL^ zhQu?sQesFvGjnx$x5top=2cP*iFa-##E^Jq=Heb*6hq>fnXA9M7DM8hnX9|I7DM8h znX9+E7DM8hSt&6jo|%;rL*kj4D^6MriDzad#gKUC<_eTOhQu?ol43|ab1Nx^#5*@v zq_h|k@7!FO(qc%wb904Ciy`sO&6O%GhQvF!5@JX^Gb<&A#5*$=jTXg_u-t;gkksw8 zVbg}qg^|tUVl6?QVJEZa2@avc6Rk-GYf}v87@xn z|B?%Pv%Q6${&b-`*OToq?vdTl=*SV{TSnT`gTslAB+G9&*^w~*80Uwi2L}@3j}Q(R z!hyjd_HS3#NZyrA@_$qO-)8o2CfD4;zGiI~0G642&J9#UGZkk?mv| ziyKcQ>R|`@u;Q{I({H>+7ZM!S;F>oF+gg*vU5fZDT)Grv33wgL1RA+K2N7H^Q)qKkGliJzOSdsR4KGOf zHsNV_7vqse48`5cqL_>!tRoZJ@(e-{M`=opqc*`S*foWxFLILi-mZD@KEpMIr#GV5 z`atG^0pM93bgqZp%UsNxU0Qd}ZSuFX1a2@zU1eZuqp$S2p5hp+h#@czk6eUi>;_!|C;vjjLlk ze+A-|jn7yHU)i`-v4~snm5o~!ix>r8*|=4)h)3|1jcXPAvSOcSRrtCa@0bE#*?7kf z_{v5QZhdhkTR^sM;j8@{9h)d@;xC5qT!#JR;xh(dhsn{x$oR>H5ndj~9$QM`1@63M zeB4O7b**k%z_GtB$hv}4zTRJxnFH3i|4)M~{t2SI+ z@N+3&mhS3x%>0r3)P{6S#i8_d;Z<@XCqS-ABhWT^(vC?MOHeI}}_Ph^Q zYK3E%XCAKoEN{}iYSgrIy!GJ?x>pXSmE$>ZBlpU|v~fHKKF9FN!Ob^5$D4Am98CMh z?}0buUOBi~w}>L!qdS`|WIBgB3vAJ|FtRr3R%o7EV$n}rLs-P9M*mI9jorK$#T5O< zy&T?_>%Va&D=$VVMZa+)DKC2A-L-0S12``_UHvC!DX4by=)<^nhZQ05ofmzm z{u8$bEibxE{U>fcQ(p9t`cK?CBIa{oGPPexOFpm(cS4kakWg*yXil1 zHB8Z&=|<){jL(bCtLQhbCc`@`{U@&D9~K&5RI~mYKe1Iszi~Ah(fbtr#?@*>Z&UOe zSF;h(P({CSwHvX*TJ#&Y);rIwQ~!w^CgMQzZmZ}gZhd8*_fthbaqArOykjc*iCb@& z=RHx;Pu#k{Jnwpne&T|fjJWc86M>!36RTk}_ymus>hI~vvDm6YLc|BLOBF*^^B9kz z$}U^Yq&HOuSPg+2Y<1r{-u8yw0H zbhM=w=F+U_l>-CWzM+mKJavCzXdu^H=+F0bba%4a>|1Kyk}huNWe#S0j6g2=*@*4p zpEJ1u`EhV4+b=)&{8>hr)RixdDe(oV^<=CEZfKHpIwVjgYd}+6ElS@R4f*& zwT6hzF_mcsg~h~Myglb0X3EvB_q;KSvqEzGtq_ue4`1q8ita9+gstxCnTX-a9P?%! zQ}LY4RD+JGcrU(#`DEf^Zkw`@@9soalR|wt~40=3_9Nv zZ%ITV=R4wUN4zJWUha59ysem%>l;$35WVnv+EJOAQ)Xg>(=d?jW;gGch^uA?mVy;( z>KQ4L*SRWEyzWMl@jBl@8a*!)NyTg3%#88il#EyWE<7_66{nQE_Ui|SGF@w&lJL6U z*#eqVLau>2#vqb_FO+d^q$894>G=1&Lgn{%!xZ1!GQbje=D-cWtq86zw**{KY9$Z5 z39cm96kI>9DY#x-Q*gDorV#p&E~ZF*dsT+Oz^x21u2(6LGHmsUe9x;>);ID!uS}Qk zc~!c6&nwd9dtQw$-}6e8-?JBUvKd#47DgLy3~u55KfJw166cJx^|mDiBvrm2%@Qv^ zKWI;E4&K=!GnVrp*E-y-Id5}H&GiSVVf3x%&D#*;Ms`udsHJ@w7KF_nw{K}KW3U^4 z=CQ|$=d-ccjxWS&YFR>-xbCKNS=hSqzf8U}5j&cFVBPem41w{#{?1G$Z%XUNFe%H1 z{U<7z<@_0uGt0g9-k1J+-?1JV8Rk<}xzIf!frM7AR$+X<2FjL7ytWUoPFuSI09Lu3aavI7y>L5S>NM0N-wn~TT} zMP!E|vW1AO8IdhQWUYv-4UsKIWJ?g)QHbn~h^zyVy$O*WjmWwYSuY~XBeH%(wgQn2 zAhJP3b`l~x1CgDH$j(A!=OD6aM0PGBI}eeakH{`SWEUc`ixAnxi0l$Xb}1se43S-q z$gV(SS0b{j5ZTp;>>5O-T2f0}cO8=MdPH^uBD)ol-G<0+M`Uk9WN$}g??7blL}Yg$ zvO5vkyAav?5!u~{>;s7GgNW=NM0PJCyAP4wkH{WCWDg>;hY;B#i0n~B_Gv`+8ASG3 zMD{sE_IX711w{5mMD`^__GLu&6-4$`MD`dW`x+wqIwJc9BKsyH`xYYmHX{2DBKs~P z`yL|uJ|g=8BKsjC`w=309FhGPk^Kab{S=Y?43YgDk^KUZ{SuKqfykajWKSWoUm>zz zBeLHhvfm=I-yyQ65!o|{?DvT5Sw!{+MD|BS_9sO4XGHcKBKr#>dmfSf6_LGw$o_`N zUPNU7Etb{PAhLQy)_}<7AhI10*^Y>8Cq%Y0BHIO#?TW}=g~)b8WUoeKyCbqa5ZRuH zY%fH%HzL~yk?o7f_CsW^L1guSaBWKxFd}*?dH{0FgBzvW1B3a71k);q>Ga_q2WXOE02AOZw zAoH!7#Ylcj5Lr7SI|`8@bFi9YkaQVDwhWQ=AhKRW)`!UQh^!xxtw3Z0h-?s%4I#3X zh-?)i8%AWS5!o6h-?IrjUuu!M79BuorK6X zBC<`0>@A4wWJETO$WB3I6NqdxBHMzFB6|>#J%q>} zMr4m5vPTiwrxDp_5ZPxD+2;`1=MmW#5ZM=%gamx$~MMD`>idkT^L3X%O9k^Kgd{T7k^4v{^L$euxDzei-x zBC_ z`!6E&9$aX?xJ0r4P5ZSJX>{WgiY#|~` zAhH%jwiuDU5s`HuvNs_zWXxK71CkCIpVlH{!dhg!R(m&+--i&{&k-5Yf7Bv`V z)FORAEz;iCB5ivu(vH_6ZFViv7S|%}ZY|Qr)*)?49nx;pA#Fq*!g<{R#r0QrFe00a z$PPnfZ$M=85m^%=I~gj}?nPAw`x)xEGPBd66aE{Ybh85ZQx>>>)(GXD9ot$k4)IyPZDMqMjGw!6#OUPaErpR& zwix?26i!<=zG<|OC~Q6Tlx?T4Gg`L~E6>5&Yh=dV(pum?hgKWmk+LqVf(HqZCY>8ydkqXN7z?8ZBQA)Jy@TwPK{QrQfsE;r;R6>%7lt|o_&yK zN|SWQOU&`#{5f_jBCzuJtv9c6hIkxHe2fK(t- zsfLU5T2n0A<|a~kU9D0{Q6(y5u~8veQ6W3nDnyzkJiTg4EFyU?wd(016^K+SRUwc{ zRS1aGqjt$3R^n0Hj7RMjk2;5aJX=;MqWg65)2HRVz@tJc^{9|aJu0M9kE%qKc&=9C zxt3zjRs0apK`1lN6h9ZFQqKjc)N?^9^;{LvS89FXbat5A$oRIcQ)81X=8!$!GVyrz zY&@*W@0O1jQ_TgKkV*wNzFO)VbfgSTQCtayEHdsmr|!7sELkuZnyOdT=GCg(Q}J_xOL0|Iq+kt)q)~paQWfY$;Q*~O7?;8UEJ@W^1)w#% zSKgVx00K0i26r*_Zcv#~`ARWMcdkIeCf~f&VO1&=fjzFgk+Lg!QaFsiI&BcihNX6C zaVik0RL2&lI<8oBnwv=Fb(KmbMU|)!-oCF96=F;lph9G|*Q%#i?Yl)J?*%FZQmG12 zhEuC51X8IA0g-xC^}|X$D(_T|6_0967BVrw zq*B4-t(B=jlgiK(>y=OlA2b}V?zrY8Suhxys#h4#soPWcQmg6}xnuRHmAGR*+&Dqp zu`yYIJ60y7Zch~qw+D5sDzu^&&c`JMaeGELy`i{5)$OT*Yt_9dL#;$r@zKhO;$Do& z0^Cb+RaK;54F^6_Sf^A~s~%k80BD18DICC()DJ5Ft?1Ub^Uh?wsvFP%bnE*`)hRP7 zUnyp(yj>qr)&XXzY9s~?glfhVTfql$ljee`mwK`) z6^g(fSKdg_O6IEyU7}DnSd1x$45e%kDb3atRJF_d08y`Gpk_j*QleV5UZ9#qi%9;k z{Ab!SHCfMWh~+S7#YbB0sl*Khb8eCUqC;iJ(ZZCUs-Mt!cwH<17NU9&H-a7Eq}w z1&m1zJ5=qKZA_|Q)0R%f3Rab@3NF`{*ivr6I5%M}+ZQz!o6{jmGu~ZXC>5`~h(M$i z4~|foT;~$gIm9MR%6qj-Q)pVbfsZ}yA|!2BD<)iw3FU2-trGLF7FH))l`?9ki>e21 zx--)$?>ShZyepo<3N5ZxR;a9#V1@EA&^9RaT=yq!GwVE9p?tV^8dfO!q*Bqr3gsi) z?NI1>?oV17L*m2u)3HL)Cr!$(KG>u3w>W1&spq>ts-iYnseJBadUF`FStu2MR@o{9 zE0xa^&w^*Yz~fnEt5bfdll(j#_JI3{Qukypl9a0#bQ3l5M!;RCwpdhGEQ%M4REG|E z?I}}1FQi1Of2i3kQ>h=;Y$+Cg$3%DR0-$gF;Vsf6~D1 zI)75$uAh$;iau%JcAXc>+w}{e&~f)C4cxBtLV3FmUWGMKDEg$q+jU+lZ`Ut^M?J;; zQG>VZyj0$aJz2qan9QH{Y9yJv3C7BS;Nq- z&ygb4PQ`X87VTIpQa+~eL-i&AM7zizLc6X+(5|nQsnic^)SEgG9bcU4gkq6;(EvYG z?IMU&0|Fvt^dM3e2_mI9B?85zvnuxCdU<1PPkJdVY67=SB)K#3$i{UO6Jz5Aek2=n z!{u(p{D>6hM|-U@8Yn1}SF@Oy>WRzMH{j(cu+$u}>~ci#%8htAEwQ6t;(NDVBrT!ra@elBtlnNy83MlHO>u8_s3R~Mz48-E%YwOFkh8VM*y86Ypm@>0f~9-$l7#&%`UrxCh= zk%_GsWouAOnNPz`<6tHLV-Z_1%G9n3`ZVkW4^|9}K5WG(OM_y{d>VG@2P+1~8@6K9 zivZa!2)D*E??IcAreVIc+>h_@^C1N)ii}`K|jB|$A6J735kZKFm;Hc~; z5{7+ZJJJ}(HK*9u{5YXa=1K>jt>2>xj;S{)Fc?=Nc2ck$ zKj_Bpw^(bb2Z~aej}Vlq-VuNZdU>@-szmVa1w=ly;rDK3CGoclAHph0S(c@elq_H+ z@lp>Gr8d|qNtK{Vg)s_Ll1v4aq{inUQa^&$=~sO1nf=SF07y{5j!e6cJxbp zP#@6Vc&T%-dQ&B+QkB_Q>P@DCx1V5dP;V*~)SDCqwm1Ho>Z4F^>cubEn-W#d-gv2p zLA|LWz}}QdnN3W2_$ZO3-eir`sJF(D%E#2YR8IMuwvS=;CT}FBo}hB}#!GzzR&T|n zg1te#$y88DU~f=wDize56a}_7{;u%jP;Y8g0qjkQDraxJ)cH_vstB+*B~oSsE_F&| zsW(|8HEKx$Qk^eb=*kT`_}k9^!|F}mNK8FJ{*=G3{RGsTTCxIrQ=-b*8!z>6s5eyv*qah5vxzB33MI1Co2n$W-UX>HsJy*# z=a)}n^(Jow+<7WtZ-tW#4-gSH+o+0#@q|(rh$^8j>G;RT^q)e?RSK(_s$3+)&&fNma?ssy{6m7DB12 z;|AR-Q6+WD%Y6tb7j(P5@@+C7@*IJb3T?9GX)965f?Hnh!$`THTX@<^6wBLWK2S+O zscLWmx>ce|>Xw)L2vRQS_VkMC*5ai6C|0bj(HbaLipmCPlNmL`2N$1KrN-1!y{cpo zRiKisr6xtG#tTDLs;XiTsi9cjO_tgG9$^d$vNkobIzGv;u3ZjcFCC~=Ny-uv|YElzQ5jd z&1ky2X3o($KG*%~zyH0rZruu9ZPm?(Wj79eD7X;i3ob)FN_GQ6!G(xO>RqxPNf=2B zhMXAThkZ_Y}Qxlih$&ydffNbZZHs$Zo+ReU2mPDUJ~3i#My?K9;guP^1TgeDP+e zw@lfsj;eUO6#XaAoqAQW$i2pe74 zgDA3Fut=Y?ZhDIIY5C&K>dF61*)1s2gF(J{Gt}Fp>{drryj?o@6p@Uic$3{iTYcFr zh&socRi^(XyIm~krg%e?FWwCGwz3-#iZ?`rjjp9a6xl6UM6YM+sXc*IzId|*!;h!z z78KFjq&ea(UNGDUtm-h_B~cD{g(Wnr=|7Rc#bNz_$!Fy96>TjT9-Tndv&!D7swa*nJ2Rt_}2GOyLG{x<0Y{CcSWN$o-OV*`gBP`{#47aBa~2 zatar|!VRJf{lMtmQz7JO|$_-YC_kn0OKh%)fC)ciH!vXvpe4_phrmYn}L zg&WA}LiL>SZ0YLj!ev)Md>^zHd~Fu?jTA0?g&Rbz{aX(BK2099eDzJ?GWQYR`FwnZ zYx(M1DcnF#H#l|ouW&72eOtIx$l}YbdEN7~a4lbbCxr`N;RaC#|60EKu5hUu#rK@G z@UP{o@1<}9IbGzK)4!IlzAs!VDe*mbE%;i#`aud8zQPTn4F0uz^+VxO)QIoGTJW`e z^`jJSAgAkkyZhH)&ox)ttN&v#dzTHwC}Aa9TEg0!z1B?mDVMUH$!Gg^+y*P{V6z^% zmW9oNBTl@_qqn(P>nxrhbVAhH$#$8OasG)oUpcfd&WM(BZn1*1t-QI)S^0_yM69FR zNxGAC6NDZLX9*_r>oWZQ$xtlNU<>|PuBej&uDbr6fJh&JZ^ zQixIOAaeG6+vW@$ZM6H95Tn*XuRREySpG5II4c0nv@H#LsVqJ0{P8%NcmQ7WSOuv8y)=OYGulD`4xZtKNvsxcaYlF6=44lDB7dd%t=yX&<8fLWjhu8l+?0NQ)oE@>&ML*g#FP7AJ;oKcy zO^!AIV2WeH+ifl%r(=0<+m$gzb;f&?cCe|m%H(a2Ssid1r5!Lun@`U~qVQCEZ`%bn z#WB<^{nLYMv3&n-L6phc9E z@``(}#__VgED_WYCf&UaW*Oug!iZcQkaj_Sr{G#F-)8{p#MpBec1bRC^^5?&zF7hVvx=jZceb>P_XJEhK#be(~pPf*d>CgBA# z8Xo8-?fLo4a9j0G(+^#$|-+c=U}n z!~&4@xbf)3(v#{I6i^37*44(hh|!blK=g(#jI581Zxzr}Rs!n4$U4{fHUT}g4n+KS zVPw5({B{Cj_NibHPzOfVoyKo3pr_Xv5%FCZSw9-zE}&UR&v174eXE6x3ip&0ZZNM@>4ZDV*JsQ-3-<|izBs=VZdoNod_C@IDO~uX$`aiD ziwoxrOYiwbuZxw#W;t~BCd;Lmw+H35~;y+9TPH$Mi}@Zk};@7GLmQ{`&t|s15-!P1wFV{P5?p${H8NQZ@AY0E zI{2Rwf%3P6>`-0S=Zr>G7iagBuRItkeg60(~lWVcAjW)iYv60%#?WoV!LLXS)l%m=`WZjrby3f=j3O7phm2hpQ|d z>hByn{T~y7^4EmypLJQkNXTxTkZnrHwkBlT6Eb*49hbT+k})BVWJ~}f*=G_MUr5Nl zl8}A9E-S8{kX<_=yM97;lQ3?yO4h%J`RBT>ly1wB|#NyJn4s<*{k zc>3YN`co3o7E>+GERT*i?F`}$m=`bh2ALQ!Nbt7Uv#uYBP!INcN+O=ZAbJXeNCZ_b zAId@1o#8KD;;EM3)$Ws6628~g9pS*%oqVsSpsJ^!s;8ieCCt38UDHTFIC3^P` z-Aq0r(CCag9O7P%DPE4o{i6b~0u8&8K?~GFmjb&cG=^#pjooWR#VfqV>&mVnjR_&t z16bqWdUB&9o(t( z;?=lHVMBLNc2;oF9TZ7eEJLUDZyPS!VDcJlBMD%UVkmop|Hdv zQGy_i(YG=TrFc#ZbxZT-?S7{e#tmnPSL%S@*3Wc%|-Hf18|3uW;@}|g}WdnM${LOM} zhR!VuxOb|Gw*VYjAlO->a|Yn5TN&zGK@~)bZcwDPk@ZfmpDeu11G~urOI&g|t9Kf- zB?=w9xMS!CdP*Xm;@xaLbyod{7p^3tt;h3J5alq4<@f4i7jCj3g9Nh|uqVGqqM(Zm zqNgwjfm2`*J%vFef+|1ELDdG8cX;2s$pR}K3E!*afW3xUcRXvA#=u%+UgvLjLt%+UdP)$aG5S{bBCfjN z{Gj#w4~RaUJT7E6gxJkzcI&+#6fV?ccAwf<()H?)o z#x@picebHaKIkV4ANJ5L3tb~XE3MPb2rBhYM4c^fDc~cr0XtNv}My3Sh=DY`+Cu12<9g%^0LWwF>}3k+vVglGF#3L!yulSoIin8_h3 z*c{-8ktpP>_MFZyFI+H2|Do_j3m6GfgD8qIaJ1IKziT~PzWKawet+3Yp)0e6tmJXi zU`x!K0eN=!qC@^KVmLy^%piA<;p&URX8Xq~np89ZiU_*>n*|FH6cQ0S{S(4dhzcf@ z{4f%MXyy$2nN7Buh^CJ#n$SYggcgb>i8^axuRce?^a;5X6a^Dy2i9#JOaNE0^xr99 z=mFd|mdb;_Lw6nMPWzbs_<0`9tzFzII9{iz5aIa2)5B9+wr>ibydM!x2VF;{;W*`} zG<=YKR2n{N9!pOOA0QtQ9@jhZkh>XZL>Sa+?UI8oB5j!XB+lp`8;D~bfo|HeDd^k{ z)P~|ur9kUeEkT1#x`A2^6kRoZ+{#S(K)a!~?eJFaeMU?Lnq(Rr-HoYLwx1O!heXmo z%@asg#z*(x3N*=dx^u~4;cKfn(e<|+f=g4S*LE|o&7Hm=0}D0HHDrZus5VcGuD(5C z7rkY)aWU4sYwB@AEdEG!QuYV&2nq=BNuN$i6^=}H51Jvp8?Vi^S)$;nc zQmARJo%6b(T3-LQP&LI&y0v>=Uz`hheV<3YT$$IO5xR}?`n7|I)YZFAT|_6>Q}hOj zh*gR3sq#7^<@L+e5c`*}i>^=?U9m2@Qe9NnzF*hAU)R2msu1eqI7I4?o41COxRRYB zVJ!u^wx17Q(ruP{5hDd6PW7DU}3)48EQ$#q3mJVJk^O^BS z*Dp%r(9Is(mCuZSFXsMf9114kwB=(jOHDo?jdN5O;UCwTkG;$~`M@*|gSv29^6~D` z>j`nVvGLa9?Jq@OvoP@9IXlTlNkT9!*?8yZB>M;(g6%26Ic?c^-<+FfL#zp=B^x`Z zKB@EZBWwsYPO7(MV{gVx-Y3n5NE1v;Hul!tq)y$Buwfy9S8&?0v6qu4cca6t7A*l7Tc$l`z?b_UU_&OTcWnuKG!TRgH5t|L>*hAw%9%aRi$Lj z-(;Xi*0CjOi|w=0{$+TRmL65dmZ&YZPgMszc6q2_q;pS`s~%m)Za6CXWOczZKx8Wc zEz4-xit@MdJXi;C@2Y`|CJBggyr1OvE^SS^s%_nO3xHtqCy}ZTHg6GW zO-LfvaX95+&givRX9-4fs~&^(DI?(r7%cbgye1n--bl9AQWfUz!|*`drH-oFNk$4! z$w-W)67fUr3$S0-*=}y(W-unZv1X{?LXb%9$Z{@V=GPZhA3aW+3NM9Wj7!cZ-@w+9tS)SMRp4o(YYNxb;3gq z9XjOx<%>6W%xG|ll-+_NJs9MOx9G$0g;qROPv9>YjzR-H8P&tk$Q63|!Odeb+#WpxMVjD!(6WdG)0$VFGA0$)?9QhVePTyKdedz?Q ze9H_VpKq-+d`JRSzKz)CFtYcp6~dQE;4%g3i){{AJ`7(xOsEtS@-3pAzP0l8vI$)I zmRU+Z-&z^=hy<#98?nt{Wba!mI*&-;%C};h1J-Qr zDl&_2y^*b|xnhE@j4asBMqa4i=CR`9N}%>QLV%Ga%3$OOwRpTobqj`|Vq%FXC3|ew zBkFV5K%(nrEI2E5ZNc!$DI?(r7-Xo0BGlpu9@Q;G06{=V#5^T3QqWCC(ga6#<0;uK zh+0=wA-Jr%xr*$@VH5=yqI|(+wcL|rHy{*ThzOe=#}N@lb_*8KNftfD>67lcAlS|7 zq^qXv78KFBo_z6URpC=ocB`W*-ekA%l#HZ!;{*^t)Tx~e3)EGQv5M=vHtVF zMET;)>hR~uZa^sB5D_-IE(=j)H%!R^Pd!DImoMI|w7z!AZb1>f<(ebj;swJe0;_rg zcS)4PT_X#I*Gb^wu>O_v70KnbLs~F=aspM8Q>xB9M)vb2E6%T*z@kSgP^6gdg`_{^^XD3kQ+lXxrBYWRk(RsrJu6!%DIbgM5_*|hf zaLc!da{AUv#TzAXxP`3Y3{He#E@$lkYB;N3WZE8mK34p=Q1zEG$X z7xFEloW8ZP>?R3Z`IZwSS$yk_Y*o!oQ?S9JeZdA%>opx+MQ%%mHxn+KkD|+Nad*1H zwSoTTDcnF#*E)8uxrJ*(?k$AN7M1vNm2OVHHuxQx!iBGJgD8W4Z5Y}hT()h*_o#fs zknC&&!gLBZkkjqXIsI#?c}BQwWr*+5Yr)r&(e1#iC8T@PM>L}r|t02C|tOZ}o zS4XFC137)vpu2x{8>;22V}#4xM|?S+)V==-*Yee|DO~spH;7vMSGbn1juS2wviNd5 zCMRFZSI4Jt13BFynA5+OuWl(^sz&j>R=#+aoh@ITkivzpaDym=e=T3#O1M-~;>%W1 zPXAiIx^)USkkehWIsI$->Ndiqs1aZGb8_;ve05?97rw#`qSpTP*M`lNzaQKd%pM!u zl&}&lEn(doAwz3sr+=%eS|cv6&(x2wS?@uiPw*03aXz9zM{k+4*4dh&-6&-QH;Et> zj0hrHO0dOp&9(!(cb5tm)eC0sqog#CDRf0jcapB0DQ{_-T_}+TCy6IXc-!VvdM6%o zmqYcg8qB?I^Y$Ps#l1EM*=G0JFt=5RQR^U*DzYHj0JlwuQR^VmS+gM8&~`f^My-R$ zn3@IA2DRG@F=`z|M$-(4Zg?Sn?jT%7k|=)2@)>Z;_!*i%?NqxQk%0AL2p zswNrEmSfUjmvAEta8;>f7|bkqeV;j7uq-r1;mcx72D&Z>TE5ra485p*sInlE1#{YC z>S_bMgBS5+Q6dZGjK|z7+eYoflZAmSm>WIjqA;WO!DQty1Ew!Hee@m>Yy<%;MPX~$ z;lc9qy|SN-SN92&rKal2M5)P!w=4L1JuBW9=XcFjwR^QiQNEqu`#>lYSv;4BS6Nl4 zFKKvHMf2SJY5zKizE&d(h? zTwK_GCdyX~-9z^d3h+~-DN`*G-6$Fwvdd%wOx>1f`!m-U{ z6HL$1ZZH`{ZvI1y zxz=M=XVyn)2h0MFxHb}nr`kuf-Pv;hE9924Gd zbD#c_Ah#=H2GxP?QQE<#(khd;J!W;9X_R)r6m7nL6N$o8?Y(Wc)eNfh*pBukf@`sS z|1v?8$=e>YI@aW90|2HtlA|M0ciMJ$&Y(I@?Nku$(73e1+bR>#s*UB9$-NrUktbOq zs3Ad9pfP?D$R8`H`+O@bd{OI>;ovKt{s@-K0G~pBbuC zz>eQ!ogY0l13%yYqN7W~gP-t%r~yBBv)0}N`+ZqDu32e+Yn>Qqp}k3FzdNfLbu3SaTN!mmP`;^~R%z)58t+y^_Hzz*nsh zeaS3ZO<4Bc z4qsxyRjrIH(?dM&+fulJTpv|B;g0qYUrW4QxY${I$%mbAMMRsC|{5JG4TaN{fNr2 z4er@zS-CR4M-VK;YaBwf+}6j2d);FBYGw4^UY&lPvEycc^vLCR?|Q!ugAYb67`|EL zh(w`F7k3Ij)Ke1i)NK8!`MT($l|;1lIGzfk(Lu4DLG0Y$pS(dPMhp_7TkKhZi9|sc z8AMNE5N)7g5Iu!KB!VhG%t6(TR{q&jb)RAVRWNA6_gZ8n99U!(RXqh&Jq1-g1yw{j zc-c|azodB8U8q%5cC4&~Ihb{$nO=t|&92(o{?!SAD-APtyObDSK zz*0{(#-Ldv+|G;q!>d=WR`-5UHz?`>T%Zeqn!{9f^y;5pmvV_N(xq;yEWk^;gPk8d zgsT)bbO&W;1sB~xk%YxEbXxze+@c#y%JAtsyOjUr0p5h{Z4Is?jM_V;LUnn4T{WvM zqeEedMWO^j8l!JT7~It#sEQ;&bY4kt{Vs!YBIY}LzH$#b)9nE zI-%0tWOn8s`9jQfzjf<{$}kq&Sh(HUhWj2CXI#%)H|C*T7W#Scq|!RwjG$8gL{$E? z{0nOeP0F?^;7yTn*?^ube^az)u)HkbhT?V6UGcI&u(L+z48Rp#L!A^|jGUqy6fqmO zF|uAgvdO}_DG%%>3tz80d`A#z(3U84@ZyyEQxfsi+4ZN+t&8rzl8Ck*%Tqy=!yuO5 zt2@ZuWZ~-pg{ffyd-8iE3cAQ3dJ2OOI0XjLQy4@dsPe-cRBceXxc9xAEc`E2ApupD z91`&qy!4brJOx!f1yw{jc)7{Kx=W;Zg`OjSQNBbXG=_wpl8C3^rKjMP#a~ORBg+++ z^z__h0elTgEP5)0cuIxrIlF99JY}MG^|tH5k~EuQlVO2 zzdX^Qu*4!gB?!_OeXDyBSKXp{(E9xqM4wI`7qTp*=QF$Y-YW_hYBIY}LzH$lyLHMd z36<_9vu_XmG#^*%epePM!*gt7;dW;mO67xovTzj-?Xu8U0z0L3x*0*G{)wowY zOC-;J4zr^NA~w-`-w974D%dX|Ek>e{v)XeyzkD^;F^mhkKyX`k`_(hRWuzR zxMBMqBGLU}c#5FtAtH2ozYk9#Dwt66!$<_pw$?mIG+kTKgcdLoq@oGMx<`|}q!tB} z?(Gz?f{C(2)@@54;3}4Mg=PedkpXTSOXU%*p}VDRr+w&n{6*g6Ztda^!SPJhCBpH8 zXN0G=Y~K_SaEkF;6fv52%` z;`(&#-fseN%p=fETQ&uqyMfwJe1jBd-Kr&Mut_&itATDP(BH1il<(#mYK!z~=CyK9 z7cuq(nq(Rr-HoYLwl@~j->u9vPas(tuWJc=0!=cVW~lFEUt7h|t%SY*TbU}owwr-% z?sPL5Sg2{PAuDu4wRxg$B-9X=?yA!v>$FEL-!b-Y$bQ^&J)&GldRDNoh6(PC+q|`R z;vu_ihAZ79IyU@JqT}i!26R1jyYQ4oAw(J55HFzeZMaHL0v?>pti`16493> zBIqR|HY8%yN2DCPdF!TN!?qn`(N!9j*Ec9czY$m_gXN^odEG!QuTQ5yQ~iRmu62MK zsO9w;fqrvkrk(S;fm&YIZHhgCCYg55>jr9h{U|a0*2+vf=XC?Mynb{FG|9AkUN=&FQ7+bdJ;p4Sc4^7^qU)HK)5dEHPguOBB=O)!0+fmn-x7 zvx9||*G~u{@>Gx0h!SzuR3eV~O2kTlL>!b?UPq+7{;9eWpRS8OQx|=QLk!F4(kwM6y~+u;c=MW)S% z)R86PsfICWU97seZ7DJ#`OrGDL@klMQ>*LSmLe0R533_f)DqdwyieXGZEeE#;dNw* zS|Z!q6qBc>kqP8S)R84>iEQubOrDlTX6fOPb!3TJBHO!clc%SVsZ$?SN0z81vL8Oq z@W|zU>_~s6SbcOIxmg$TqsN(P7|K(@v}7~w)6-qkII2h=)0NM(&qjA!1_<>9gs7R} zrv3PF_ho>{KI|U09^iehxyLdW#m(ft}q-4xoL6>hbLPz@|onG%P=C92&gS1 zpE&Nd3=o;)@tvd2=ZSkS14N<_(6Wq{ttgKieNkwk+JUiE1TpNf(xXWNq8#rh`Mpbr zI{2)o>%P|u1Zx)(srq2^RwCAfBw`(hQy$hc+pM1lBiX8lyd&MT(+Y#-K1J62@T)@| ze9jxmeXkb?wvr^$1WQIDMlh0k93uTtcH@U;xE2fJ!EUy2qbW>}HA4j#qI|*SPzPU- z-GESVAyU|IHbNqdq`B(%LRZ&QEE496H(Ptslq|9vu7N?mcyp+OFQx2OM^)I!ZajsN z6mN+1L)ncVc8xb%KGPJl$AYxt4N<;$bEt!_$ZkL=-ViBlIC&%yMpC@7nysf;fzB6i zwgRXrb7VJM1A~0==1>P;OWCcCs<4sWcnTva-Vo`BvKv3_8gI6SsU?6OyB&%*MET;) zp$@(-y8)qiL!_|bsGmd_N%6*3iJoG6BVWAPDy)_?BD>)l803pLhdTIX%5HU3g^ldS zQy59{hDbk@-S}bGc(ZlndC$O|v1Kbw@rEd0ygAgtw`DgV6mN(WHXQJf2qP)p*oV_o z?49L{H#_1LUHpx@s^1Xhh_~o_y@SuoUDOkD7or^Q3I`IcravcvD~J6k)G^(STwXa~ zUrV%d^@|Bq898FxxleG@ffeWHCU8|Ii){{AV{1j`mxapME#D%_>02wQ7ZSMg?T_>O z)=I;#CQ#+uh;0rd`+1@j!uLtw%C};h1J-OG&m2pzOMU>OGR=(ahfh*tsB)@O1 z4Esg`Rlbeb<}kANtreZS6S(rN*yeyW-&*nXEuk_d$+w7d`qoOt^Afo7?N9Uj)=Hl5 zBv9qsh;0rdd*51tr(17&fXKIEn*-K-YlX`9#FpYhzD1PNw^o)#-@X7uzWrHN-+Cik zRdarVu8b_$&PHCS-sZ95;(kIsAuyAX5oIuPggW@XM|BH^K*+?1R7!3Nx=F-g1Bo~w z(7hH4MzWe@F=ZtDfVvq9&dNwuf&IXvx&=cZ6cC6sPmz((4I^oSgGfJ=-S}Y%+Uj-x zU^lC7_Q`G>Mp1Af$`@Q#%l$}p146-tNMUo*3c;lb4kuakLr$OMi#My2_NVNIYhaKs z-mEJ8Ny=_@RE3S~##0zc@rFo0l->AY*Lbsv>wxUWNhie{qI~gY_2tiGHy{*mh!i%P z>+yz>6mJ}p(hoV>lrP?_cDo>DH(UdQeDP+L>Mv4utD`DxWH+9|NQyT^`l0N`54*;j zRe=X(x7!4tD&7#~i#MxzesiZ?|1q3p&FyT+SUrWeU>CkCG?-Vo)BH><;cC%XZmctfPH z*&1|{2qP)pIN+(LIFy+$-mJ8~f68vS1_n9eEnYDEpXb_<#hi9QOI( zo$f|1uN|`Knw6_RPM~UX8nMOjZTkeb9a(Yyzyz+!WUF@@@>R6hmoTN!-pquRRx%eD(AcF64xZs5@WFSI-bGRipTRZ7uj(zItW~ z7jnWy)Sa*8t7i$9N=kgW^EJ!#-j^E(Enhu5g$p_1BI?f9^3`*MOHm`fUtbIVTE2R2 z3Kw$1MbwtBzr1U%{Q0`)33FQ@rV(h}Ca5i+!9riZg-JCoHKvD;wfN3z+2Les2b z7Uv@hbo7=vPYv!9p1Sj7aF!5*uA^d zckqb>A_mgMDNr|#ZQeX_MQnM;$LvDc!nzj-^(c65#*n-hvTgJBuEw3+YlGj5g&4IC zA}=3gL9}7-B|?l^2a)6FSrBc&d#Mnk)Ru+qsC5uIf|>!*6&1wKD};N? zMEsl}S&sM_nm=DH%&2|1vKyU&>+IfXkNFy5M(u;ij${_h8ISo|VMgtP$*xou%#9xN zb;69=2a}zN9GK;;ls*Z)L7=x)zyQiAk{qCWHw>+dzFC-2`(SdCAPeTS$9$VGqxQjM zH#rODjK_SZFr)UtWJfUz=0=bC9$`l9gUN1O2F$8bu^MCDdxaZefJ@zx0oUDvIlJKd z%!dSfyF~c%)?^OYGJGxHe?*v3`%vZ0xh$B|9`iqh8MP1Q9mG9DuAlLk9~WlSKA5~g zlZEF-kNH2sjM@j2w@)%)`hwF(@23SDK>$n5*&23uu)LD5Ec(V(EU2zbl$zQGw_4Lm z`o;NObN)N@lhrJ!ykeyHf#7;tk%(4Qz9X`BS69RG?d~1JjYrSe#e(a;B8&Y`&_G2x zqEPPQIM#Et3qjUJZw!cInDa^n zu9|LxCypModgX4EBbab(Gud3i(e5Hy7riI&vEVe>^y5L4$&ViMy9!?bgb7F8lzn;@ zHN0!>W|Vc&3j?B!nb9hfYdvOllHK)M0NCj);D~D@5t>jayTfK(bxPaO{?FiAEZ_U@Aj;%zk69gdaV?1JN70FtR>2{we|WR|4w5 z$U4`!R;K$!9f`+XoHy%Bl9&Yfr-T$2!QLPYv-;DVJrIdB#)zwX|gDvdYxBp0oe%67r&z@hL zpPSz4M}U8V-1|$7d7pr7YhuGKtA^R#_pKH(Jns5_3K#RDN=97s^!h@$|9~&Jh&thp z+S%i-OW}q~(iL<|aQ81RoHH!F=d;0)N`g2_*Yh#GN z)}Q)YUG(?5NEW26W@AnwVk}{=AD0E;K&{zBw8Vm|s>PP+As%-!g^TAHJ2K*0@>_o~ z;bLcMUFE}0xT8JO<6bg_i!)IrBd(47>n|l-!dCu8)CqUAXL{Vrq;P|OdlVrVacvY` ze}r)9TJkRgYbV@M|9adjq;T;ss&v8~wX@xEy#9*9B~!t-M^)Jgca*Qky-ErfzNnHB z*UGW=R~0VVRPl_c6Yi*;J?_<0xFMcZ8MeVa`z$M0#-md-EW~RZLbP=2!}f4y_wJsb z-M@FST5c~tbXV0R!;L#PT92H#vKTxqj4*ml1JTm=6BEss@!Av{(0Z{ z70XfSL80-u)Iu0(|KRW-U&rV@q%L}BUG%WJ=;3wIBkH0@)|&ny}jJY zDIXoL7O5^#R!z?jjVW5OVYFF>5hEE^jAWQGl3~Y4h9M&vmW*VWGLm7-NQN;Z8P<$s zm@|?sXFPjv$j=T!Ka4UbEs?F-rWki3`CzEMA&_8s+)spf;8Bc@;S*|WnL z$9L5~t9gc*WwdY9SEqev{cEcEwDyg9>$LB#TF~k-ATFbQqy9SWJ8ZOSrRLMxH|nwe z<75*(8Hb@esr{0Tt;2cN`s_rs1f|wf%Ik8F)%02aA+m{Rp@|YBt$U-O_n#k|7?Wkx zdQ$gBqtlG_*og_XPAQbuy-~=|ScjdMO0}NUy-~!^Sbv?kxLT)VOY7b!;AgD6PDG0` zYCWlYqj;aO-a2t<=}u{x*1gdXHDjH1;`A zS}jrYN#&c3Q5&rYp16{)l zVY`&eokwl(s{(x9eSP%y%)7&UBSE0{dG|ynt^v5$Io3xn%Lt%Oq4p{F)d0Ao{_Azz zwfCNt8639f))=_M*z2RMSpg&&9Jce;0Ne|u>!U5%e_ffuVf$|lz`Z%TUR$v}0VEk5 zz6;k7+&iM{wFle#x0NXzz8BXJ+}oh*wfPz$q&Xb6Bi9hzd!OsI>)LzoVK^Li>>WV} zpGseUZQq@bC>Khe7Z9{ia!L?sZRXB((Ov4IQ|qGB>Y`miqI zUG)08=nZudDL~EBrz9dsB_gUM!bymf&zF8G-T7lUx-uHO$iB7g-d|k*dS%>~2lbQr zaLH%UR|8=A@C_+|R2(n)1o~hG6;dtwMO!$`qRALqo897`<&Kgfxdn`Opw7AHH22UVRu2 zjq)L%7+-&Vk8rs%A3irAC?B2?MD*|8nRU@!>!Q2WMR%`@?h!=FhlrF9pAnvt60FNg z^sM?*&#sG}Qx}nA)E1pqB6@*D_*^2KgecC3d}18+Yo8cjoU>yjvt=Hf{D^nW4a-;8 zDa+kU_`Lfi@0@(c-ie3o#eBI(GWka`IY=^jNV0#yV3IvBA(NBz95gpeCO1hYKS?G> zNhVK8CRa%&Ur8osNhWVe_QnLaHzj0mPRQPpki9h_ds{;G_Jr&m3E4XnvUeq9@2|^> z6BDxACS;ouvKQ86gT!-#&57r>CS>O%WD5yd97Cc1l%1pe+qQMNUuQA6C?LnuG>lD|r>bqEr7$Fa>cP0d!G)`a@e5s3 z)#P(2Oc+fDRH7p=2Uibci_}xs@R?>QOc+uI)W9P!7pxw}X6jSdO2dR%`GD$s1m?i% zVQj`eb)7U!n4J%Hq#7LTPf3#@;1|QDu9t=hD_?^?G4xkiPJ+8#nR1WwY#(w1)I$#QP_w&EQ)2D z$!e2nDGC-lD~ZBp-CSP%qZg0SjV=PTt%yP|SwdJ%Fh0IAY7`Hcg zbc$gT#iyET=V>VliF250Z}6y;G>PIfO|=8H6otHb?^Jt(N2a7n6rX6Sov5WKq|JM! z+8aC~B~7CEG*j(JEkz+~-ZRzS;NdB062)(YPgPq}OJS5Xccxk#JS-(maQ1O)O30_=2O_xT@ih1DI^ZEe<#l6id@M zmIS7%Evy<2S%8UN+~R=Kez7!-<4cZeGpmL}9$=Cgw>V&07)#SQJ`q&gS~VOp0TbM~ z#lZtsA8$StRQp>s9CE?wsTK$KPf0zW!>t5{Z!;X6an}m2pY_A)RQca83yt0-M0-JX z%^|Qz#8Z^|dP*XmV#L=|6g3h(ASjU%(H5fz1M{lLAJl!->u>3akC#7W;stSu1i*SV zGqxTgz4Gzipg*DlO8hVq1xl;a|NQdqHFMkjsfME6h|rdr*BkFBvE+^S!-R|7QDgTV z?OrTZT>n6iTOQRCh}PuJ4&=2$X1rDd;%;6XyFAVJn1!o(MA6yc)wEyTvbesQeYtaH zG{x$@_FQn2wVgUl<@kinQeBrh7VU*oj!1h%OSRvkYB4{BM4T zsy(fsguQC5kfQzIR>2!_idq$?>brjyX?OCPxPHQzq<(@({e`TrEzeWUJ`w=a{aA5 zg1bThMqTvsAX@Tv!eKPi&G>#yImK(|J{9?{(4vgaQW~lh_YF@; z#Jo)+T$2(tijPQP+snAKSJ?G7DNNTwVZ|j1ON7FR%GS!i)!WWCZtfygSWivZP5~=b zf(Z&#;i;yo*e=znDOKuL;hk8yk-j5UnvDphgJ#YeURb_MFuVJ}zVf{Sd+}xcX#`e* zQ`E7THsJw1wFTqcC&ZeRWR|EOB2r#!=uO*7Jl!ko`sq6YuDppV3TV73h2>2+pj~6D z`T}Ti#&%NAkb|Wi4n{j!1y!USs$kBhv1Yr*XL?m!o@TotVJHH+02fu7;@WojT|KTV z34~iW0WrQ>kR{P;d;538+y%BJdKIb|QcvM#(I#Y8r%~m1%XW9i*6Ok7(PN22ZYL-k zc7_Vn^4dKFN)!oHU6&Z=sdk{&{dVHrh-pCRu>gX38`;vj&^?8K!g^Ou2qB~zAz072 zmk@|~A>1=$m3ADg58OM2fWksRWF%HUu37L8J&5bzZworBgOkm1wt^o~BikA1zlfQ7 z9RA-K^k`_iFoRy4v1)G@AQ7`*D|PFJAXVQngtI_Ua|!{`2%xJnls*qKV_9L&gOrEw zqlJLbqGtWd3akyltYFr!rz8q?FIWiBQ!E5X#1xB~!lzZG|I(7+-Q z3d2E9NyJmo(o@hv)Rco2VrQo~)Lp|MC2uh}$~Afl4tfd>dI}DW{jg*Vv`{|BQz;7~ zg@J~F`QRaifi%L%AnXqF}*Z%#I3F0k^;T>ab3A4+`0)G zgDeSE8$5PnZn>FIRTon*5UTP#mT1^{eD*(RiTOM@%ZkeWX9x4+_SG4-La-dU2X885 zVA@lsqz4k?&Bo?x1>>OgwY{Q6$BHikV57C2>8!_`FAP+c>4Xp>sFCTcBiv62gt$z{ zHf}o(7V?WiU}%c%B#dS(LKSmx#-e?nhjBgnMIoe=`Uq_tu0DaNk@XC8zqrv;1-Y^71CAxPDK4B-M0)Le>209}=#{JOGRdfzv{zx>7e3x&c;m_m(d zTQheEW!5k7Uz9=#9Y2~JA~G_EnGCRtP*Hh+KpqgBEQ68Kno(J(c6ZDrUj?Ce3JBOA zQNtzJ7~#eq!7c63oR(k_Q5f_HXNg`DRFml4LBzPSs%Q!1ty}4OdZ{M!qS`7haB+SO z8yyvSL#WP5xfNcTBU?x$2Z}s_19^>Hi1b6*gCDLY;(|Rah5oOCffTBqgQ#6F7(#WZ z%h`kG6by*uX0oh}y-6AykLtoIPkx@qtKgrZ$lX@`{hwg<#NA{~AQ? z@`sgX(d{j$ruabAE|sX+qC1pOP4R)KX?zUNv0JRHzPqVR&bTR)BWh~$Fm*7D?sI4yy;|B>0 z`QlC8d|@TabOJ%Xh*&f=l%FXYMs!6N4ayf{(GwXe@`YG5g)m>(0D6L0FzCq_h}!zXFn*T6kT2fa+85qX zHnLWCX}a}qbe5q6(a2EY?3xW1zZ40Mk;&bN8jju7%C8~Z+9SAHm*&I)kxI0k!EzEk zBZySnA<|Pi&eqBvHt_sP_TXr_0tZpUz^UwE2q(%OG^emZq!NuCd5Ive+K#tV_0%hZ z)tZ$oAwFyf`*q45m=|r^#fKqmO4*~1AUDe%JOz2h2O|AY_TY!Bs&y;x*Tgr_z`SVNE!}J`m}LvIjqG5+61||4#PcRU5?zqIU6N2)C0xXio8gNN(n^l|+zNd^|e@ zgPwX-5VeaB8|wcrWe?1Yw(a7>5Voi6QAd!QWe=W$yy63qekgnJ!zS@zMZ@o956;pn zJ`lBw4@0=4>_Kyi4@7dawvt!^fV|@4IUyMI!&e7UyZEpQ=MO1+U|zIs8Xxi6!EFS= zxG9q(YHIS4wSzwsI4yyrYX>`oz@R5zAZqIi z8>Fl24O}*-LHXi^t$pDQWh3jM1PvKV5RDAQTJxe?GB4-!eMiClV`W)1-qwzWFx;Rt z)=y!ev@j5rKWg$CmcuB7!K$oyyuB+Am(a%sDGZbr1|mme^{LRrHQ?b=)mU}QgyX?#pm@BqD-V}Q#>T}%7$_|aMCFef@NnIH zth&a+@nEq|Jl@rnhwJBKlj0!^loke}@<)f|p_9_q&!>bz6(}AYAZ#`d5Qg>hi={A7 zS{R6$@o=T#*u{lG1tlIFF>cGl`uQbN7$_|aM9p|uKfk0fs6NDl)8cJ;SU*tpi#tTAc5D#A9Xv@R;`DIcVC@l;`&3ITpzpOAASjB^jHrn#Aettv>1Eqz5 zXf-_CSXk>Ah-p|!w%L7%3%y+wRU0ObLev}(=g94eOkvlx zyJjYT;UmSpY5V^06V*J3*ik8N8=j&J(k(`8DikjaPw69?gRMb!`rX_$%VC>haNi(b z)s08~Yn#J^i^KUnyUyA@Un)Lvb%pzbLSvB76;VKzzbXF`ufHr*A49D^g8C`n?v=`i z-$%PtWi&8C*T}kor>(MHDR6lL#dqR)0z&o_cuwDT#RM5%s4e z;;Bd0pOT2D9#wxzBA$ABc#8X^WN1RJ_kr+~L>~+yd|I3zL_DQ0*YcD(enrpw@2q~> zd)}42?+fh`QThh5+QrQ&5qxp8o|1^CaI>D0h^KI~o|1^CaI>D0h^KI~o|1^CaI>D0 zh^KI~o|1^C9v!TzrzGO3$JC#ah^HP~e@Y^rdR+Y}iFoSq^`|7_sVCH*l8C3CSbs_) zo_bRKDT#RM$@Qls;;E<9pOT2Do?3rOBA$9${V9ofN5FI;`dXWA9yk7FwFzO=l$}?x&3s_b(dFmmhKuvN<}~1re?{%%TIq~v6*`aD*r{H< z23fw+EOV-9*r=|M)gsw)X1D#Js)X3M)93o=MMJW9{H`{_RnQr2-)<)!k6u(G*~jf8 zY}~%xN<1FD=)^D)w~w%K`*s`gc=VzS15DgL!p80UkM>4yY%ny%?IUd5zTG}N9=(OY zpcc1}uyOl#>+txG)EO8KU-PKE;<#lv`5rf`|5++(dIU7 zNqa=iwYOe75$!ossY`oA&9%2)I}vRK)0VVH)LeV(wG+_}Ei(vdkEpr!)@vuCjZ@l^ z_K2EmZ@qRR+RtQWBkd72*WP;VM6}IFThbm;bM39yPDHzZ%($dIqUPHBUVC{}BD5v# z5jEDn`tJ4>)jTsnX^*I`{hoz==g#|e%c<(@sJly!MM73qicMke$eNm-Vp26YAv_hY z80t%Lqw9+{73l3>JZrdXZrAzlR^o*{`}QAs_ClrA`HS-xl+R2&3wF{%ilHm3OUtxd zPA-PFyc*hlw%WaI&^ysCgb&lMJ2^1%T-wyCtvtc1?NU!HHNq`UKJ(=1;pwN|&VTpr z%uOe6-!k03V>q|lPmLyD0M1|`=)Qf&wr#x=54p``eE{%q+Aj}eb=Ji5Jy3Z|p4!An z;;1{?P7La>qENgbhzOKrOu4)=KEGG2-4qlUow>uhoT?Y{VS>Zkd;1P=XlM7>*e{f^ z&k0l_WA`2ygiDM)x3F(^m;26VNq4F`CSU5V=M#oxIc0F`&}!V5yy4C|uvmWMz?!|4 z*UdExe`OX#SblJu<(sXW-naU&Q?wXt5H{3rrJ3Q;ap1IxgKAD`muzz^LuH6fBGe?)pI@^ac z#|~!~FDi{S8KvY416p(%<6Ox`w`mTG;~KAqa(A1R8Vc)h{WpfTSz+tHIfw|rcI=E_!WU^t!s}^>xu3 zY9bd#A&^E)GP~1%|LnW+1p4BM9$iQS!G8se)q29mz~Zih76R65OO+<8Lxtr{%Ke{* zCIRlhDTv5${kI?r9jE`+ny4VX@4Yu;E%-ruqFSRanFuPu z1Sm0~zl#YXwZ#u3Q7}QIcF02#(bnOa_^RLwJ{Zc)X+bd%%O`Y8F_8$LAW~b5g3^&K zS&4Yct9@Y4^w7*boGCl>-Yp#`G{zoYsdDdR-$i?7=jV+zw45dHpHsaP@vB^n5l!xA3KI_ z!qwA~tN5#Lklge4jdGo6`d(F%(#tHxC4|U)tShM)EU@SKYUr> zv_`>cn^3*WsjQV<2~H@kVQ_jqs`ax`yP}8eny^@1q!4Brg%Jzvx<>J8yKgh@;H~cEyOw1N<;=9q*YH5s(J0;2O_-^T3ozt2Xgru*}*4my*3)@fE}bm5aqRl&t`hHw75jw z4rG!wvV+eL*H=tRhd^4{EJr-JbuTrh8MQMpq=V^8)9luK^?ztlRQ&L7}FZ9z%I4-skaDu?lQ4BhUF)3!R8=H|5Q zdtokZH?Z@o6>o`t6=+KI>$>PSb3P$(n_+L^^^R3YDEox`r$A)| zsiP9M!(8i5Y$_ioZ6*W%cvBf+wl#fIi235^hH`Zr&n*yh_z3?OV?jY}6c=p7N3w~; zbMVk}ISgChU_K#XP>uDRpURZAwZUAn8GE_Mb^{wgV5|QtE%H>3ZtQZPIoA&$mj7-o zYv8?vL-PjL$i|(O{JrY1sw;fa1IrXw4gr(XE2S3IruI{01dssl|6gWs?}HH=__c`J zN)37qYD6{&xu{$J2%DGwf{U@I30yV^NRbVKs2g~QLzi|f4y$(ood4k-r#Xac7>Ry0 zMi;^qnin5{b33CzNvLn61(XbHt88nAb7!ezLC6>HjlW z0HYK|5M}a+4^76uYOS*RNP`>r0F(|yr!qI=8JW9yXwWnz%Gs~tt>xR}zsPt2Ok8p- zu^V} zgFC|upmboc)VzscWYSV#V#OyWmOT-vEljK*N)$Yp&+2|H`s9?=1DK4kMj`8UxRckx zZHmh3=z!IUJdG7H9`=;+5b1{;&nGM7v!`EI-+?`gUOkG}1<@KsvDe`g*%QD-6f>!k zJ+-5Z@f6sI^h4}PVCS=^-y^tl%AUjq^wuaoy$*NrI=G2AfZD$!K4m$f1&|0I${=@+mqfWLZwYcsX?NTfKgYc_#S%zt&<( z#Sxy$hwrPPyQc7iTO#}*%7^a@iMt8^Z*~5Mf@lr+`yuu2Df~dTFZ>|N$KMY@_YnTy z16lQFM#eSZ?^E{96n-G9k(q9pkH61n_Z0p=>io$RYrx<4|9hqI;V=9k>cGF+Sgn?K zJ_2xY^BQsGf*iyHu-{7lsDN*=5^zSwei`9o0zR@1{I?*=$=Gip|A&A#1QhyMU%(j| z`|acZ6!3H%nEsxVvEMrWF9FZ21e}qv-!}fZfH&5G>ESsU`z_;72>7U#fHN>=MPbKq z<{0;3hTho%r!dueHRTr5feuMz1l)bGp?8i4cZC(@pLR77QAKIqowe4hE!eruqH0h2 zT-k?0Q}$sUAV*YSAHREM+tJk<`feGQsf6H}gXDlOL*nRaSMsTzw3`gEVFIewuC?FD zLaIc62%#*|AM2t&)kS}Z8UTodzi^%h(%Z-BJHHko!Bfv&g;&pjIN*8>@ zdA~K*#ZLwvBwcQbUC`x(Aj+=GXuNn`9-7hxAE91$T}FN6C+QE9E;k59pnxqn5Sm?= zQM-6u9+}bwyP#fnT}JKVC$Eo^E;p&$g+r6sbs4pb*X6M(U9b!4W!GiYE`Cwzanj}b zb-QqSIlC^ScJaDAF{KN3LA~s{jM~L7wmeC?+_-L+E~9qwx>V(%D@vscc0rU& zmvDZnR=Y$;EUpy{pxOmdRy{_2<7=pA$Txs0$1!hTLp^+*@GR+ZJ?z04#N0Bg9;5N$ z^>}Vd58?yW(t0c|lsDDc;mE1#BHqa|&fXFDFbyfL9z-ng71yYXu2~o1BmMB&^{1{= z7hSh55}ClS!(_!3$QJCQLFS8{=gX*YQjoDKl{RYGaDy9V&|}oOUXK^0^a$h&R9izm ze327f41r(N`4MH+W7IERkC)0GfXXkdBxTiO)Gxlcsg6Rrq)a!EJrHHpW7HmAkLtdk zQ9VdPEZeT39=@n~wfsU?mS0#}%&NzzU%Vc#OX)#>LA5p1!xuBJmmXwJ#RsCSdW^=0 z*W-;TJ%|tX6SC?t>K9+cyjgmX{bdhCS@jsThu7n+DLt?UYwtPqa4$@hi$S~G3llpn zI>)MW0p$v8pVtVmLjS!CcqsI+AYxHA9`Nk?&)L1Z7R!rbXLs6wF;#8aT&#q6PWUk$ zQ6iSxB;puF|M}sEtV2s(M)5vNj);o;)qYsOfQ|7;M92Jc_+fna<$(2#C zsSkS}U$Qj8vqQUBxwjBR90=*1R}<-nvI^#eiEJlBVLSa0R})o{?Qk`=B;to(O`4NsoaN2w>bM4FpW6nh`mWplC|^>t&uZ(Khm@lV@7*UT zhtcAE&`^W;jjk#|RfjxWf}(rVb^1RJ=mfHK#LOKOawdtDip-+ZAA)4>s<$U7mcuON z&dgEA`}f7FGas%u{5(M5jQ+cWNP8~tsf+%#F8a5+h}^HX-dBI>{dLg?>Y^XjMR-ol z|D^uZPwS$e)kRn$%aQrm-_?PKdoxCB^Gib*RwoEoh`3vf+>z|tpVVANE~Ndzcwn5Z zr;kvyA!_VjQWQf9l2&B6)l;~N6%0zpCRX+77Q!h#-TU_*W68eQex+Q7}7@hi`v%gzYl`W9NzRp8^!< zk%tpD2%^I)6bSooGrc!OI5ZX!4x+=izdFM9>83Fqx9E#-fa+6XG%$By=RXbgezBu5 z4BCHjuyKR-SI2JJCP-uV6Ff&}1dm27x~B)2_@Dr2jiEc@7fhPVd;U9-WBUXzegUgb zIoQCw!F?WJ;@<^8Yck+Va{G@J81KFVLjOg85;}#%YTUP^w)7uhnS7Z5XbtxjlnGhO z5;*$eQU_Rcr3EVVnUAc-g-bbF5i+U8Z?%RIi{Ayit_??DUFu+r)&o#MTD9?`)g68FMMJ9^2@wOF3ldqDuX$?~s%y?H#duhM1N@P--BwFi*SwXg6HA+?AtvG&> z8+^g}P*2nums@L4LCZ@jI9ZrzV_d68CSN1t(wdA*MY}e%ecAc&6m3Se_l4d?zbPIb zM5`$~mwMX@mC4tNHUOBq_+bE88`{43td3wgZ=d9j4H|03?BcHsJ= z9a<~CzqYh}3HoSRUbKS>eHPL1b_0%nc}2T>Y7M&<-(6ddRUxWlWc}X;Ky;8=ExPTD zUtoEItcc0fZND8b*Cu|eYV`5aK_u}cYoBdA=}Q^ykM?N|E9!$(*+}jf9$QA+n9jQC z+9WM3|0UQqy}~-W=Vd&msyCP1O7(NXuW^=oy0RHd=7{t|4Xw`&ZLzT4mk2*Rul^L< zVA{%Iyun+2);thtz7L{uaY_`FD83Yw7}*Bn*x>RW95tuaAXC+AQRTM`#h0*>% z9*%@7(;Ms$yXE&#y!-n$hwh8nW6$%v%M)L^OH)G!lkfD<(OCzlL3K8=yd6~G?CVK&S;LZLNRL{U;A4oK)4!00Os znL?y3rRtO@M9WHKwKtO7mPv1tTWGwL(2!z;hIo^9I%+X`dcic%>X+;w4RA&-4dN{- zzhkduo8I}ML!y9cEj*aZ1a`fwRuOu;>)`5|A;@xpZy3()+P`bK|Ge|79ds=;XuTx* zRyTgwws|$*>RzVzxx20>$9>3^Gt9{0L^(htQ$?XfW(GxlgB-c!3=LNBYlNDmsWyqM z!1&$83cF@E43D?>Oeg;4P2p}jqcBk-0*$nwfmWtqjM7sQ1+!}G<*7)-Q;doXv@6Bi zGER2AdgAXe(}~MC`?%>v$R)tg)=SoGZ>g}u0VhD)&U{5QJ-`PVA}o$utq}DZLX99XeE+OCweT zPn~?`$!Ks;qUoAw1=CdF-fL zd)L1G<*&!SNmnRd8=A+Z>Ih6tWLNAJiGoXIRfYgHk0{oDZeic-uEn|GY$=?&&?|M> zGR|IFQ>yoXAVR4=ewBzm%)qEFtf%PJ#H>27o}y3dDY~?tk_a;pgghl<(N;mnkx7Y4 zM*8A)HQMU-YW_{Nrv{e^qWY48Vqtjdj_t=EfBc!H`6sJkqFmdOA4x3g9ZD?f9+8ax z5y|Kvk&GS^$><`Hj6M>{=p>PhULsi>XiMkQeo(D<6Yj)ug|&NqW?|3%`NciEc5mc^ z4jRJxp9(gPvkgKG51lkAUnbgj(Vp4)xzR5xop#BMm5BQ$$cI5z5`uTLwi9W0>f~ciNBcF2^zm(U*EpGxUJxDKfQ00=8DD;2j z585w?kLld12<8N`35q4yCVb4~#|B-~{VR$4om+i%vs zMUXOgh_C_KG^@GG4?{T3KPG6{#>o<4CWF_~cJ(a;r%Sa%=qyj#i*-SmNtY4l+f=Og zpE3t%a{jyW_BFqWt+{cZ_JJJSJV0i2e*Ec&kBjg}0u<=|{|ut8X+8bThibR393q7z za6*sDRD+Q!t49VEQ=-s^Ty(Ac8LJg4jrd~^|D7^dKoN=6B!^{Z0+cuu7FA}dHv2}+ z1vmpW15xpa6>OuYupmQU26OrD^hufPqd^xr_`iZEcXWC1Xb%x2fisj+@GIR@-7DaT zK^avRl%0b&3XG~BN)(>TU}rm9(ff4D&H<$l``lsa!K-afw`>Cv2Rl@<5M4^{m|jMe zxiBg}EM5}=hQ6M`f_9vu_gPu+V*y3M^6?!OIIuBMSnK1u>WUI-w+^D&UAgeyENu5n)O2 zW-zLq@961^!TtXTF{sG+L=fc;OAr1fZ&WwlfFy8?N+`*w5>Z8=qGFIp&0sD&Hq!gD z*VxTlWiG-162zcp=7d2fT{L2QeZHbT0XV5q;Fzluc>F1buL}5sAxPvpDm|Q%0obN8 zy|1N!@qmDXCp@GBE!jm1 z72?xlH!EF7&rj^9Fv-&zT=3rD8mIUqSeVa4FG+%feAE-0~|3L-WP2Qn(?=fRRrG{94GYBP61rlgn>c ze(<3@ld)^#@F+WVG=4RKa%2Ed?fDRTZ314PC3e}s_|*mahS0b1tw1}~%r2%E=iO0- zlJ3lK#v@6Ao@uMTj^PzJlu{ssSf6n*sle_Fc9(a%`CFC$>DwtcS&O#>B7}Ya zGeJag+vhz3i9T0<3a{v?FVvswNSt&5B+KgbS|K0Dh8NO2jC8-E{2ZDCgplu?cIs$%7<$`F14Hv{` zKM;01`?24BO`=>Vw;FQnJ3i3d)cQMt6n>YJv2XwT;VFF8hI&xK#{IGHdL`WHZEh@3 z!g*;x#Mn}m4j{dVj##gSJ^qB>-0t!YZeu?6P=UTZAS9U6oDk4saEb84`T z6sfKE0Gv=z}0PLy9!VsNDu>ASU_$#?j^Rj#w)o8~Z=6h^wBz7a)|a5p}B~Jo^gq_a4z*RYCJm*AgMIqVa(kmd%Jxy^tai zWuZiifg@d5Wg*5c{ayaG3YTN5O6gB2vxd$u-Z?_FLj1EwbZ4Su)_|x5RLm+Hl7Ll5 zV+z&LdWt%l1lP%6HisFD)<=I3e55!;lqC*5;$LMjnpYe$?kbJZ?-hqc7^aZH^b`go z=sFq9CjMi8Q-q;DNlo=Er7oxFjUwhN{4;*=CPmX&X#&io#hSYCinc7 zm>yg+AjI{@;J6@N{%wnqNv)Y_>VZPiq!u$FVmo7SsQ?p$w{cf^J$HUj`Rnm$_4uU$ zL7fE=?@G5pT(Vr`CNbkv@YjeN)sk8VQ~r2e(2rEwMwuPMZ*=IFeC5Q|D zqyVq^SD49uU3@Ztt)^K*IHdJ+ph0xXTBD!6{%R5Gf?%cv@7K~cG7E#3lBZiEY z4c^#aR_w8}*i&cZWnW$rQ?b|5xk_ZQ7d*j`gT28U`^$+vu_*S`@p;+1)idw=%L`sT zEd+V-`dX(q@(m|OBXRFS&)|*y6;klQ(wfC|3cV`hmj`s*!Icd|x9&H7B@gWKUp?qF zF;f1c&L`O^HSyF+)+v`S{HQ&l7iXd+%RpM9^r*dbEp*55sAK$^NcHm8=$c4qHeM4! zwn8MA&Dt$dnv@j}3c;Y>@#Y}ve+e6J7D6Xzg^ZP7T{Fo{nEf*bxp_ z`lzGk#da1Szpk(&9IzFwd9jai*w+(wgabCE{OYb%O5Q%^*D5C7=#gBh`5e3(@{UBB zrSv&1Nl|FwTje6V5!LMt&-zbHO+8rvF9-nCvi+9@5vBj27evcdm=T1{hNqsIf`Ee{ zf~Yvu0K#UOQ%@Jf3&W4a;^jdEi{hU_vc77eo*h|7ZZ=Z*_gPAYK%H zEEcZ_BC+^;5UqlR-3~wX+!RDmxi5$yD*o00!e7olRb7$lV)n)1*P`*tAQFwg2GJ^L z_`A`kUML>I2uk;b5k$pb4u?@6FlNGt@evQ^R(@G;j%OhV(?ij@3;T!F?9p#YPo3`@ zbbFQjRu)3Uv|mqYZIN9eo*G=f4abdsRE%y&V6=)kB0M}tKXqO79Nj7_zZJ(f2347* z=_v)qlWR{E{E+%$aJlf*a^aJ5t-qvVqPpwcx%MrgnV2@h!_)TL(EH_Dekmz+ zIt8>T7Y0WJ<(hCj%DeUx3g5SeW@3&A56{tW@n0a0{8k(hi6bI$WX$HN!DWMTO*kIw zIaU`KxT22D=!m0)X^u-H#C2IWN-hkmyZ0tOjS;oq83Q~ZD8D*@kul#VhtgXYcrsrE zt53LVu7fCzlxW$l6--rY(yl+!f}DnkZl(U15|LMlRf_xKJ;4;K^`l=N7`d!{xZqRe zM0KaJ8%&-Z+LbL3$rgRC#3GN36hMo6&mYd7cfNgVna{`DLg>_wyxkoZjbNhQ1p%Hp zX7SM=S}oHN=Tzu3ez$L;da-ttX|S`%N2MN0rc1pfQ=gox_l-uG1}rg^Pd}1}spZIt z>V;Z|uA(-~wj_#ts-iYLc6guqd|bUpe?J`B(#(`XpQ%0>9`y9|{^R zXV=v+wJF6!b*68WX@C;>sIQ=8gTCUYFTY7K4Ol(-G>D21=3#0xn~CZSpJV#G(5`%n zDDo)_;0=80XHmZsQyP&^FAVVND<24=Za%dM*2MRP4lOOAAc}m7k_~+7Cv(3S7L90w z7N+W_@6W^3=6Mr86#DZ+yYeZb$fqnYHt?yRQ~ps{G?MVC<`wS?8g=uj|6c8nJ-REe z+1ih)CJDv$@QK~eWUEsgu4B-2f|!P|_a2VeXlkvdYSjfg4u+Kq!B7*Zu>DL!7(XC? zL2eRE$S4|+<)%+Jgz=+cb?=H}!-|F2kjt1-7N2Se<0lB!Y{v?S7e_Kikw)-S|{oFw0Tq9Gff z`l6vzFt7nezTtkQ<=D6z@fYWJ&+pnd?~m-A>x0?7^zf{pBTTfG!8jrjy;ZXh_)0_p zt~ooIS|UBg^ixkE;;F$^gR0B%Tw0)%d&F)9exf?!QYJYa>15!N2=F+=)!RJIwdt;< zb#qylIG-8xQk!Q65hh%z&1f=PPH5fUj?ZnAeL!@Ml5t2==H!@DSNs^aG(M>p-E@{W zp*Z1nIK}XkeV6Rh8>Nr9K5@rUn_^PZ^?%>$RT&kl6&Wp@xF@|7B^s7?b z-g@WDEdIES-ojE|k2Y+`j;q@|U~zF2%F_L0v}GJM%RU92eJRxWyLWG}_p@)eV~ca@ zW(CTdL+D|f0e$?m)3=;-_uh$z?0XJoAA3>t^iyv)+_LHPO~W%coxFX^aQhC+5|dS3 zT^f9F?x90ZDOaXH{8-oZ!dH0)3jqp|x4AXCeTQ$&H6B{5>Q~p|+2OY%EuIskOIq|V z?3b_F&N{ZbxOPA!j5PC!U|mYOOq0HpdxDxAq<%ao zQqpCboc1M1wb0|!gYV*6P zUl-p=NtbKW$NaylO-{FtaQ{}5Hhs*$S8aYX_3MIH=wqZ<&*~uSY&EmJGY#t6{rIPY z4JnvpgFf0%Rf9*Semb~CN}6oYhx+Mi@aCzX4sMo`CL8o|ex@3{Y3iqgo1~=427Qp< zO%2{S_0z$PQqp9DKEm&z25*@9>EH$_X|h2d-uG04*H8U)aJ`f?*`SZ@d;k9s1}bCI z%B+M<6sv)dgq?seP!XF}W(91b$OeL!mV=sZTy7AvfIUxUOGt~$a~?{I3myjWAwwp3 zh$4jGL5~oEM -Project Summary - - -
    
-            Lattice Mapping Report File for Design Module 'top_tf'
-
-
-
-Design Information
-
-Command line:   map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
-     s1_impl1.ngd -o s1_impl1_map.ncd -pr s1_impl1.prf -mp s1_impl1.mrp -lpf
-     /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf -lpf
-     /home/hadaq/mmichalek/lattice/simplified/s1.lpf -xref_sym -xref_sig -tdm
-     -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LFE5UM5G-45FCABGA381
-Target Performance:   8
-Mapper:  sa5p00g,  version:  Diamond (64-bit) 3.11.2.446
-Mapped on:  06/16/21  09:19:26
-
-
-Design Summary
-   Number of registers:    934 out of 44457 (2%)
-      PFU registers:          899 out of 43848 (2%)
-      PIO registers:           35 out of   609 (6%)
-   Number of SLICEs:       692 out of 21924 (3%)
-      SLICEs as Logic/ROM:    692 out of 21924 (3%)
-      SLICEs as RAM:            0 out of 16443 (0%)
-      SLICEs as Carry:        121 out of 21924 (1%)
-   Number of LUT4s:        630 out of 43848 (1%)
-      Number used as logic LUTs:        388
-      Number used as distributed RAM:     0
-      Number used as ripple logic:      242
-      Number used as shift registers:     0
-   Number of PIO sites used: 187 out of 203 (92%)
-      Number of PIO sites used for single ended IOs: 185
-      Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
-     comps in NCD)
-   Number of block RAMs:  4 out of 108 (4%)
-   Number of GSRs:  0 out of 1 (0%)
-   JTAG used :      No
-   Readback used :  No
-   Oscillator used :  No
-   Startup used :   No
-   DTR used :   No
-   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
-   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
-   Number of DCC:  0 out of 60 (0%)
-   Number of DCS:  0 out of 2 (0%)
-   Number of PLLs:  1 out of 4 (25%)
-   Number of DDRDLLs:  0 out of 4 (0%)
-   Number of CLKDIV:  0 out of 4 (0%)
-   Number of ECLKSYNC:  0 out of 10 (0%)
-   Number of ECLKBRIDGECS:  0 out of 2 (0%)
-   Number of DCUs:  0 out of 2 (0%)
-   Number of DCU Channels:  0 out of 4 (0%)
-   Number of EXTREFs:  0 out of 2 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-
-
-        Number Of Mapped DSP Components:
-   --------------------------------
-   MULT18X18D          0
-   MULT9X9D            0
-   ALU54B              0
-   ALU24B              0
-   PRADD18A            0
-   PRADD9A             0
-   --------------------------------
-   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
-   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
-   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
-   Number of clocks:  6
-     Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk )
-     Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver:
-     pll0inst/PLLInst_0 )
-     Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver:
-     pll0inst/PLLInst_0 )
-     Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver:
-     pll0inst/PLLInst_0 )
-     Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver:
-     pll0inst/PLLInst_0 )
-     Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk )
-   Number of Clock Enables:  18
-     Net reset_dl[2]: 7 loads, 7 LSLICEs
-     Net N_248_i: 1 loads, 0 LSLICEs
-     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
-     LSLICEs
-     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
-     LSLICEs
-     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
-     LSLICEs
-     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
-     LSLICEs
-     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15
-     LSLICEs
-     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15
-     LSLICEs
-     Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs
-     Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs
-     Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs
-     Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs
-     Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs
-     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6
-     LSLICEs
-     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads,
-     6 LSLICEs
-     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads,
-     13 LSLICEs
-     Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10
-     loads, 1 LSLICEs
-     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1
-     LSLICEs
-   Number of LSRs:  13
-     Net reset_dl[2]: 37 loads, 33 LSLICEs
-     Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
-
-     loads, 1 LSLICEs
-     Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
-     loads, 1 LSLICEs
-     Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1
-     loads, 1 LSLICEs
-     Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs
-     Net fifo_rden_c: 1 loads, 1 LSLICEs
-     Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs
-     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sy
-     nced7_rising_i: 3 loads, 3 LSLICEs
-     Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced
-     7_rising_i: 4 loads, 4 LSLICEs
-     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4
-     loads, 4 LSLICEs
-     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1
-     LSLICEs
-     Net valid_fast_RNI999V: 9 loads, 0 LSLICEs
-     Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_risin
-     g_i: 4 loads, 4 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net reset_dl[2]: 59 loads
-     Net fifo_colector_inst/iterator[0]: 47 loads
-     Net fifo_colector_inst/iterator[1]: 23 loads
-     Net fifo_colector_inst/in_empty_pmux_i: 22 loads
-     Net un1_hit_i_2_0_a2: 20 loads
-     Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads
-     Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
-     Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
-     Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads
-     Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads
-
-
-
-
-Symbol Cross Reference
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0 (PFU) covers blocks:
-     w_gctr_cia
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6 (PFU) covers blocks:
-     r_gctr_cia
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12 (PFU) covers blocks:
-     empty_cmp_ci_a
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13 (PFU) covers blocks:
-     empty_cmp_0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14 (PFU) covers blocks:
-     empty_cmp_1
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15 (PFU) covers blocks:
-     empty_cmp_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16 (PFU) covers blocks:
-     empty_cmp_3
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17 (PFU) covers blocks:
-     empty_cmp_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19 (PFU) covers blocks:
-     full_cmp_ci_a
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20 (PFU) covers blocks:
-     full_cmp_0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21 (PFU) covers blocks:
-     full_cmp_1
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22 (PFU) covers blocks:
-     full_cmp_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23 (PFU) covers blocks:
-     full_cmp_3
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24 (PFU) covers blocks:
-     full_cmp_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26 (PFU) covers blocks:
-     w_gctr_cia
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32 (PFU) covers blocks:
-     r_gctr_cia
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38 (PFU) covers blocks:
-     empty_cmp_ci_a
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39 (PFU) covers blocks:
-     empty_cmp_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40 (PFU) covers blocks:
-     empty_cmp_1
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41 (PFU) covers blocks:
-     empty_cmp_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42 (PFU) covers blocks:
-     empty_cmp_3
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43 (PFU) covers blocks:
-     empty_cmp_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45 (PFU) covers blocks:
-     full_cmp_ci_a
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46 (PFU) covers blocks:
-     full_cmp_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47 (PFU) covers blocks:
-     full_cmp_1
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48 (PFU) covers blocks:
-     full_cmp_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49 (PFU) covers blocks:
-     full_cmp_3
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50 (PFU) covers blocks:
-     full_cmp_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52 (PFU) covers blocks:
-     w_gctr_cia
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58 (PFU) covers blocks:
-     r_gctr_cia
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64 (PFU) covers blocks:
-     empty_cmp_ci_a
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65 (PFU) covers blocks:
-     empty_cmp_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66 (PFU) covers blocks:
-     empty_cmp_1
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67 (PFU) covers blocks:
-     empty_cmp_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68 (PFU) covers blocks:
-     empty_cmp_3
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69 (PFU) covers blocks:
-     empty_cmp_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71 (PFU) covers blocks:
-     full_cmp_ci_a
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72 (PFU) covers blocks:
-     full_cmp_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73 (PFU) covers blocks:
-     full_cmp_1
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74 (PFU) covers blocks:
-     full_cmp_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75 (PFU) covers blocks:
-     full_cmp_3
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76 (PFU) covers blocks:
-     full_cmp_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1
-fifo_colector_inst/fifo40_inst/SLICE_78 (PFU) covers blocks: w_gctr_cia
-fifo_colector_inst/fifo40_inst/SLICE_79 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_101,
-     fifo_colector_inst/fifo40_inst/FF_100, w_gctr_0
-fifo_colector_inst/fifo40_inst/SLICE_80 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_99, fifo_colector_inst/fifo40_inst/FF_98,
-     w_gctr_1
-fifo_colector_inst/fifo40_inst/SLICE_81 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_97, fifo_colector_inst/fifo40_inst/FF_96,
-     w_gctr_2
-fifo_colector_inst/fifo40_inst/SLICE_82 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_95, fifo_colector_inst/fifo40_inst/FF_94,
-     w_gctr_3
-fifo_colector_inst/fifo40_inst/SLICE_83 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_93, fifo_colector_inst/fifo40_inst/FF_92,
-     w_gctr_4
-fifo_colector_inst/fifo40_inst/SLICE_84 (PFU) covers blocks: r_gctr_cia
-fifo_colector_inst/fifo40_inst/SLICE_85 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_71, fifo_colector_inst/fifo40_inst/FF_70,
-     r_gctr_0
-fifo_colector_inst/fifo40_inst/SLICE_86 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_69, fifo_colector_inst/fifo40_inst/FF_68,
-     r_gctr_1
-fifo_colector_inst/fifo40_inst/SLICE_87 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_67, fifo_colector_inst/fifo40_inst/FF_66,
-     r_gctr_2
-fifo_colector_inst/fifo40_inst/SLICE_88 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_65, fifo_colector_inst/fifo40_inst/FF_64,
-     r_gctr_3
-fifo_colector_inst/fifo40_inst/SLICE_89 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_63, fifo_colector_inst/fifo40_inst/FF_62,
-     r_gctr_4
-fifo_colector_inst/fifo40_inst/SLICE_90 (PFU) covers blocks: empty_cmp_ci_a
-fifo_colector_inst/fifo40_inst/SLICE_91 (PFU) covers blocks: empty_cmp_0
-fifo_colector_inst/fifo40_inst/SLICE_92 (PFU) covers blocks: empty_cmp_1
-fifo_colector_inst/fifo40_inst/SLICE_93 (PFU) covers blocks: empty_cmp_2
-fifo_colector_inst/fifo40_inst/SLICE_94 (PFU) covers blocks: empty_cmp_3
-fifo_colector_inst/fifo40_inst/SLICE_95 (PFU) covers blocks: empty_cmp_4
-fifo_colector_inst/fifo40_inst/SLICE_96 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_1, a0
-fifo_colector_inst/fifo40_inst/SLICE_97 (PFU) covers blocks: full_cmp_ci_a
-fifo_colector_inst/fifo40_inst/SLICE_98 (PFU) covers blocks: full_cmp_0
-fifo_colector_inst/fifo40_inst/SLICE_99 (PFU) covers blocks: full_cmp_1
-fifo_colector_inst/fifo40_inst/SLICE_100 (PFU) covers blocks: full_cmp_2
-fifo_colector_inst/fifo40_inst/SLICE_101 (PFU) covers blocks: full_cmp_3
-fifo_colector_inst/fifo40_inst/SLICE_102 (PFU) covers blocks: full_cmp_4
-fifo_colector_inst/fifo40_inst/SLICE_103 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_0, a1
-hades_tdc_bundle_inst/SLICE_104 (PFU) covers blocks: hit_valid25_0_I_27_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105 (PFU) covers
-     blocks: un1_coarse_1_0_I_1_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106 (PFU) covers
-     blocks: un1_coarse_1_0_I_9_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107 (PFU) covers
-     blocks: un1_coarse_1_0_I_21_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108 (PFU) covers
-     blocks: un1_coarse_1_0_I_27_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109 (PFU) covers
-     blocks: un1_buf_positive_0_I_1_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110 (PFU) covers
-     blocks: un1_buf_positive_0_I_9_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111 (PFU) covers
-     blocks: un1_buf_positive_0_I_21_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112 (PFU) covers
-     blocks: un1_buf_positive_0_I_27_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 (PFU) covers blocks:
-     un1_window_8_cry_0_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 (PFU) covers blocks:
-     un1_window_8_cry_1_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115 (PFU) covers blocks:
-     un1_window_8_cry_3_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116 (PFU) covers blocks:
-     un1_window_8_cry_5_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117 (PFU) covers blocks:
-     un1_window_8_s_7_0
-hades_tdc_bundle_inst/SLICE_118 (PFU) covers blocks: hit_valid25_0_I_1_0
-hades_tdc_bundle_inst/SLICE_119 (PFU) covers blocks: hit_valid25_0_I_9_0
-hades_tdc_bundle_inst/SLICE_120 (PFU) covers blocks: hit_valid25_0_I_21_0
-hades_tdc_bundle_inst/SLICE_121 (PFU) covers blocks: hit_out_i_RNO[0],
-     buf_finished5_0_a2_0, hades_tdc_bundle_inst/hit_out_i[0]
-hades_tdc_bundle_inst/SLICE_122 (PFU) covers blocks: SUM1_1_x2, N_50_i_i,
-     hades_tdc_bundle_inst/hit_out_i[1], hades_tdc_bundle_inst/hit_out_i[3]
-hades_tdc_bundle_inst/SLICE_123 (PFU) covers blocks: hit_out_i_6_f1_0[2],
-     hit_valid_pmux_iv_0_a2_2, hades_tdc_bundle_inst/hit_out_i[2]
-trb_adapter_inst/SLICE_124 (PFU) covers blocks:
-     trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1]
-fifo_colector_inst/SLICE_125 (PFU) covers blocks: in_empty_pmux_0_RNIDRET,
-     in_empty_pmux_0, fifo_colector_inst/buffer_wr_enable
-fifo_colector_inst/SLICE_126 (PFU) covers blocks: data_buffer_3[0],
-     data_buffer_3_0[0], fifo_colector_inst/data_buffer[0]
-fifo_colector_inst/SLICE_127 (PFU) covers blocks: data_buffer_3[1],
-     data_buffer_3_0[1], fifo_colector_inst/data_buffer[1]
-fifo_colector_inst/SLICE_128 (PFU) covers blocks: data_buffer_3[2],
-     data_buffer_3_0[2], fifo_colector_inst/data_buffer[2]
-fifo_colector_inst/SLICE_129 (PFU) covers blocks: data_buffer_3[3],
-     data_buffer_3_0[3], fifo_colector_inst/data_buffer[3]
-fifo_colector_inst/SLICE_130 (PFU) covers blocks: data_buffer_3[4],
-     data_buffer_3_0[4], fifo_colector_inst/data_buffer[4]
-fifo_colector_inst/SLICE_131 (PFU) covers blocks: data_buffer_3[5],
-     data_buffer_3_0[5], fifo_colector_inst/data_buffer[5]
-fifo_colector_inst/SLICE_132 (PFU) covers blocks: data_buffer_3[6],
-     data_buffer_3_0[6], fifo_colector_inst/data_buffer[6]
-fifo_colector_inst/SLICE_133 (PFU) covers blocks: data_buffer_3[7],
-     data_buffer_3_0[7], fifo_colector_inst/data_buffer[7]
-fifo_colector_inst/SLICE_134 (PFU) covers blocks: data_buffer_3_0[8],
-     data_buffer_3_0[9], fifo_colector_inst/data_buffer[8],
-     fifo_colector_inst/data_buffer[9]
-fifo_colector_inst/SLICE_135 (PFU) covers blocks: data_buffer_3_0[10],
-     data_buffer_3_0[11], fifo_colector_inst/data_buffer[10],
-     fifo_colector_inst/data_buffer[11]
-fifo_colector_inst/SLICE_136 (PFU) covers blocks: data_buffer_3_0[12],
-     data_buffer_3_0[13], fifo_colector_inst/data_buffer[12],
-     fifo_colector_inst/data_buffer[13]
-fifo_colector_inst/SLICE_137 (PFU) covers blocks: data_buffer_3_0[14],
-     data_buffer_3_0[15], fifo_colector_inst/data_buffer[14],
-     fifo_colector_inst/data_buffer[15]
-fifo_colector_inst/SLICE_138 (PFU) covers blocks: data_buffer_3_0[16],
-     data_buffer_3_0[17], fifo_colector_inst/data_buffer[16],
-     fifo_colector_inst/data_buffer[17]
-fifo_colector_inst/SLICE_139 (PFU) covers blocks: data_buffer_3_0[18],
-     data_buffer_3_0[19], fifo_colector_inst/data_buffer[18],
-     fifo_colector_inst/data_buffer[19]
-fifo_colector_inst/SLICE_140 (PFU) covers blocks: data_buffer_3_0[20],
-     data_buffer_3_0[21], fifo_colector_inst/data_buffer[20],
-     fifo_colector_inst/data_buffer[21]
-fifo_colector_inst/SLICE_141 (PFU) covers blocks: data_buffer_3_0[22],
-     data_buffer_3_0[23], fifo_colector_inst/data_buffer[22],
-     fifo_colector_inst/data_buffer[23]
-fifo_colector_inst/SLICE_142 (PFU) covers blocks: data_buffer_3_0[24],
-     data_buffer_3_0[25], fifo_colector_inst/data_buffer[24],
-     fifo_colector_inst/data_buffer[25]
-fifo_colector_inst/SLICE_143 (PFU) covers blocks: data_buffer_3_0[26],
-     data_buffer_3_0[27], fifo_colector_inst/data_buffer[26],
-     fifo_colector_inst/data_buffer[27]
-fifo_colector_inst/SLICE_144 (PFU) covers blocks: data_buffer_3_0[28],
-     data_buffer_3_0[29], fifo_colector_inst/data_buffer[28],
-     fifo_colector_inst/data_buffer[29]
-fifo_colector_inst/SLICE_145 (PFU) covers blocks: data_buffer_3_0[30],
-     data_buffer_3_0[31], fifo_colector_inst/data_buffer[30],
-     fifo_colector_inst/data_buffer[31]
-fifo_colector_inst/SLICE_146 (PFU) covers blocks:
-     fifo_colector_inst/data_buffer[32], fifo_colector_inst/data_buffer[33]
-fifo_colector_inst/fifo40_inst/SLICE_147 (PFU) covers blocks: XOR2_t8, XOR2_t7,
-     fifo_colector_inst/fifo40_inst/FF_61, fifo_colector_inst/fifo40_inst/FF_60
-fifo_colector_inst/fifo40_inst/SLICE_148 (PFU) covers blocks: XOR2_t6, XOR2_t5,
-     fifo_colector_inst/fifo40_inst/FF_59, fifo_colector_inst/fifo40_inst/FF_58
-fifo_colector_inst/fifo40_inst/SLICE_149 (PFU) covers blocks: XOR2_t4, XOR2_t3,
-     fifo_colector_inst/fifo40_inst/FF_57, fifo_colector_inst/fifo40_inst/FF_56
-fifo_colector_inst/fifo40_inst/SLICE_150 (PFU) covers blocks: XOR2_t2, XOR2_t1,
-     fifo_colector_inst/fifo40_inst/FF_55, fifo_colector_inst/fifo40_inst/FF_54
-fifo_colector_inst/fifo40_inst/SLICE_151 (PFU) covers blocks: XOR2_t0,
-     fifo_colector_inst/fifo40_inst/FF_53, fifo_colector_inst/fifo40_inst/FF_52
-fifo_colector_inst/fifo40_inst/SLICE_152 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_31, fifo_colector_inst/fifo40_inst/FF_30
-fifo_colector_inst/fifo40_inst/SLICE_153 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_29, fifo_colector_inst/fifo40_inst/FF_28
-fifo_colector_inst/fifo40_inst/SLICE_154 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_27, fifo_colector_inst/fifo40_inst/FF_26
-fifo_colector_inst/fifo40_inst/SLICE_155 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_25, fifo_colector_inst/fifo40_inst/FF_24
-fifo_colector_inst/fifo40_inst/SLICE_156 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_23, fifo_colector_inst/fifo40_inst/FF_22
-fifo_colector_inst/fifo40_inst/SLICE_157 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_11, fifo_colector_inst/fifo40_inst/FF_10
-fifo_colector_inst/fifo40_inst/SLICE_158 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_9, fifo_colector_inst/fifo40_inst/FF_8
-fifo_colector_inst/fifo40_inst/SLICE_159 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_7, fifo_colector_inst/fifo40_inst/FF_6
-fifo_colector_inst/fifo40_inst/SLICE_160 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_5, fifo_colector_inst/fifo40_inst/FF_4
-fifo_colector_inst/fifo40_inst/SLICE_161 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_3, fifo_colector_inst/fifo40_inst/FF_2
-fifo_colector_inst/fifo40_inst/SLICE_162 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_51, fifo_colector_inst/fifo40_inst/FF_50
-fifo_colector_inst/fifo40_inst/SLICE_163 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_49, fifo_colector_inst/fifo40_inst/FF_48
-fifo_colector_inst/fifo40_inst/SLICE_164 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_47, fifo_colector_inst/fifo40_inst/FF_46
-fifo_colector_inst/fifo40_inst/SLICE_165 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_45, fifo_colector_inst/fifo40_inst/FF_44
-fifo_colector_inst/fifo40_inst/SLICE_166 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_43, fifo_colector_inst/fifo40_inst/FF_42
-fifo_colector_inst/fifo40_inst/SLICE_167 (PFU) covers blocks: XOR2_t17,
-     XOR2_t16, fifo_colector_inst/fifo40_inst/FF_91,
-     fifo_colector_inst/fifo40_inst/FF_90
-fifo_colector_inst/fifo40_inst/SLICE_168 (PFU) covers blocks: XOR2_t15,
-     XOR2_t14, fifo_colector_inst/fifo40_inst/FF_89,
-     fifo_colector_inst/fifo40_inst/FF_88
-fifo_colector_inst/fifo40_inst/SLICE_169 (PFU) covers blocks: XOR2_t13,
-     XOR2_t12, fifo_colector_inst/fifo40_inst/FF_87,
-     fifo_colector_inst/fifo40_inst/FF_86
-fifo_colector_inst/fifo40_inst/SLICE_170 (PFU) covers blocks: XOR2_t11,
-     XOR2_t10, fifo_colector_inst/fifo40_inst/FF_85,
-     fifo_colector_inst/fifo40_inst/FF_84
-fifo_colector_inst/fifo40_inst/SLICE_171 (PFU) covers blocks: XOR2_t9,
-     fifo_colector_inst/fifo40_inst/FF_83, fifo_colector_inst/fifo40_inst/FF_82
-fifo_colector_inst/fifo40_inst/SLICE_172 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_41, fifo_colector_inst/fifo40_inst/FF_40
-fifo_colector_inst/fifo40_inst/SLICE_173 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_39, fifo_colector_inst/fifo40_inst/FF_38
-fifo_colector_inst/fifo40_inst/SLICE_174 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_37, fifo_colector_inst/fifo40_inst/FF_36
-fifo_colector_inst/fifo40_inst/SLICE_175 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_35, fifo_colector_inst/fifo40_inst/FF_34
-fifo_colector_inst/fifo40_inst/SLICE_176 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_33, fifo_colector_inst/fifo40_inst/FF_32
-fifo_colector_inst/fifo40_inst/SLICE_177 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_21, fifo_colector_inst/fifo40_inst/FF_20
-fifo_colector_inst/fifo40_inst/SLICE_178 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_19, fifo_colector_inst/fifo40_inst/FF_18
-fifo_colector_inst/fifo40_inst/SLICE_179 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_17, fifo_colector_inst/fifo40_inst/FF_16
-fifo_colector_inst/fifo40_inst/SLICE_180 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_15, fifo_colector_inst/fifo40_inst/FF_14
-fifo_colector_inst/fifo40_inst/SLICE_181 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_13, fifo_colector_inst/fifo40_inst/FF_12
-fifo_colector_inst/fifo40_inst/SLICE_182 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_81, fifo_colector_inst/fifo40_inst/FF_80
-fifo_colector_inst/fifo40_inst/SLICE_183 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_79, fifo_colector_inst/fifo40_inst/FF_78
-fifo_colector_inst/fifo40_inst/SLICE_184 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_77, fifo_colector_inst/fifo40_inst/FF_76
-fifo_colector_inst/fifo40_inst/SLICE_185 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_75, fifo_colector_inst/fifo40_inst/FF_74
-fifo_colector_inst/fifo40_inst/SLICE_186 (PFU) covers blocks:
-     fifo_colector_inst/fifo40_inst/FF_73, fifo_colector_inst/fifo40_inst/FF_72
-fifo_colector_inst/SLICE_187 (PFU) covers blocks: un5_in_read_enable,
-     fifo_colector_inst/iterator[0], fifo_colector_inst/iterator[1]
-trb_adapter_inst/SLICE_188 (PFU) covers blocks: buf_rden4, burst,
-     trb_adapter_inst/buf_rden
-fifo_colector_inst/SLICE_189 (PFU) covers blocks: in_read_enable_0_.fb,
-     in_read_enable_1_.fb, fifo_colector_inst/in_read_enable[0],
-     fifo_colector_inst/in_read_enable[1]
-fifo_colector_inst/SLICE_190 (PFU) covers blocks: in_read_enable_2_.fb,
-     fifo_colector_inst/in_read_enable[2]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204 (PFU) covers blocks:
-     valid_internal_RNO,
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206 (PFU) covers
-     blocks: XOR2_t8, XOR2_t7,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207 (PFU) covers
-     blocks: XOR2_t6, XOR2_t5,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208 (PFU) covers
-     blocks: XOR2_t4, XOR2_t3,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209 (PFU) covers
-     blocks: XOR2_t2, XOR2_t1,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210 (PFU) covers
-     blocks: XOR2_t0, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226 (PFU) covers
-     blocks: XOR2_t17, XOR2_t16,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227 (PFU) covers
-     blocks: XOR2_t15, XOR2_t14,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228 (PFU) covers
-     blocks: XOR2_t13, XOR2_t12,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229 (PFU) covers
-     blocks: XOR2_t11, XOR2_t10,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230 (PFU) covers
-     blocks: XOR2_t9, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245 (PFU) covers
-     blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
-genblk1[0].tdc_channel_fifo_out_inst/SLICE_246 (PFU) covers blocks:
-     fifo_in_data_11_.fb, genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[11]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
-genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271 (PFU) covers blocks:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284 (PFU) covers blocks:
-     valid_internal_RNO,
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286 (PFU) covers
-     blocks: XOR2_t8, XOR2_t7,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287 (PFU) covers
-     blocks: XOR2_t6, XOR2_t5,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288 (PFU) covers
-     blocks: XOR2_t4, XOR2_t3,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289 (PFU) covers
-     blocks: XOR2_t2, XOR2_t1,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290 (PFU) covers
-     blocks: XOR2_t0, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306 (PFU) covers
-     blocks: XOR2_t17, XOR2_t16,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307 (PFU) covers
-     blocks: XOR2_t15, XOR2_t14,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308 (PFU) covers
-     blocks: XOR2_t13, XOR2_t12,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309 (PFU) covers
-     blocks: XOR2_t11, XOR2_t10,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310 (PFU) covers
-     blocks: XOR2_t9, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325 (PFU) covers
-     blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
-genblk1[1].tdc_channel_fifo_out_inst/SLICE_326 (PFU) covers blocks:
-     fifo_in_data_11_.fb, genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[11]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
-genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351 (PFU) covers blocks:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6],
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7]
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364 (PFU) covers blocks:
-     valid_internal_RNO,
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366 (PFU) covers
-     blocks: XOR2_t8, XOR2_t7,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367 (PFU) covers
-     blocks: XOR2_t6, XOR2_t5,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368 (PFU) covers
-     blocks: XOR2_t4, XOR2_t3,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369 (PFU) covers
-     blocks: XOR2_t2, XOR2_t1,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370 (PFU) covers
-     blocks: XOR2_t0, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386 (PFU) covers
-     blocks: XOR2_t17, XOR2_t16,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387 (PFU) covers
-     blocks: XOR2_t15, XOR2_t14,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388 (PFU) covers
-     blocks: XOR2_t13, XOR2_t12,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389 (PFU) covers
-     blocks: XOR2_t11, XOR2_t10,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390 (PFU) covers
-     blocks: XOR2_t9, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405 (PFU) covers
-     blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72
-genblk1[2].tdc_channel_fifo_out_inst/SLICE_406 (PFU) covers blocks:
-     fifo_in_data_11_.fb, genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[11]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7],
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]
-genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431 (PFU) covers blocks:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7]
-hades_tdc_bundle_inst/SLICE_432 (PFU) covers blocks: buf_finished_RNO,
-     buf_finished5_0_a2_0, hades_tdc_bundle_inst/buf_finished
-hades_tdc_bundle_inst/SLICE_433 (PFU) covers blocks:
-     hades_tdc_bundle_inst/buf_release
-hades_tdc_bundle_inst/SLICE_434 (PFU) covers blocks: coarse_RNI8DE6[0],
-     drop_cmp_buf_coarse_2_axbxc1, hades_tdc_bundle_inst/coarse[0],
-     hades_tdc_bundle_inst/coarse[1]
-hades_tdc_bundle_inst/SLICE_435 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_axbxc2, coarse_RNI6RPP[2],
-     hades_tdc_bundle_inst/coarse[2], hades_tdc_bundle_inst/coarse[3]
-hades_tdc_bundle_inst/SLICE_436 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_axbxc4, drop_cmp_buf_coarse_2_axbxc5,
-     hades_tdc_bundle_inst/coarse[4], hades_tdc_bundle_inst/coarse[5]
-hades_tdc_bundle_inst/SLICE_437 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_axbxc6, drop_cmp_buf_coarse_2_axbxc7,
-     hades_tdc_bundle_inst/coarse[6], hades_tdc_bundle_inst/coarse[7]
-hades_tdc_bundle_inst/SLICE_438 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_axbxc8, drop_cmp_buf_coarse_2_ac0_5,
-     hades_tdc_bundle_inst/coarse[8]
-hades_tdc_bundle_inst/SLICE_439 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hitbuffer_1_[3],
-     hades_tdc_bundle_inst/hitbuffer_1_[4]
-hades_tdc_bundle_inst/SLICE_440 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hitbuffer_1_[5],
-     hades_tdc_bundle_inst/hitbuffer_1_[6]
-hades_tdc_bundle_inst/SLICE_441 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hitbuffer_1_[7],
-     hades_tdc_bundle_inst/hitbuffer_1_[8]
-hades_tdc_bundle_inst/SLICE_442 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hitbuffer_1_[9],
-     hades_tdc_bundle_inst/hitbuffer_1_[10]
-hades_tdc_bundle_inst/SLICE_443 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hitbuffer_1_[11]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444 (PFU) covers blocks:
-     trig_dl_RNI41GL1[3], discard_en,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard
-hades_tdc_bundle_inst/SLICE_445 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_1[0],
-     hades_tdc_bundle_inst/drop_cmp_buf_1[1]
-hades_tdc_bundle_inst/SLICE_446 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_1[2],
-     hades_tdc_bundle_inst/drop_cmp_buf_1[3]
-hades_tdc_bundle_inst/SLICE_447 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_1[4],
-     hades_tdc_bundle_inst/drop_cmp_buf_1[5]
-hades_tdc_bundle_inst/SLICE_448 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_1[6],
-     hades_tdc_bundle_inst/drop_cmp_buf_1[7]
-hades_tdc_bundle_inst/SLICE_449 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_1[8]
-hades_tdc_bundle_inst/SLICE_450 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[0],
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1]
-hades_tdc_bundle_inst/SLICE_451 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[2],
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3]
-hades_tdc_bundle_inst/SLICE_452 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[4],
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5]
-hades_tdc_bundle_inst/SLICE_453 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[6],
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7]
-hades_tdc_bundle_inst/SLICE_454 (PFU) covers blocks:
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8]
-hades_tdc_bundle_inst/SLICE_455 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_ac0_15, drop_cmp_buf_coarse_2_ac0_9_0,
-     hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[9]
-hades_tdc_bundle_inst/SLICE_456 (PFU) covers blocks: drop_cmp_buf_valid_4_iv_i,
-     hades_tdc_bundle_inst/drop_cmp_buf_valid
-hades_tdc_bundle_inst/SLICE_457 (PFU) covers blocks: hit_valid_1_RNO[0],
-     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[0]
-hades_tdc_bundle_inst/SLICE_458 (PFU) covers blocks: hit_valid_1_RNO[1],
-     drop_cmp_buf_valid_0_sqmuxa_0_a2, hades_tdc_bundle_inst/hit_valid_1[1]
-hades_tdc_bundle_inst/SLICE_459 (PFU) covers blocks: hit_valid_1_RNO[2],
-     hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[2]
-hades_tdc_bundle_inst/SLICE_460 (PFU) covers blocks: hit_valid_1_RNO[3],
-     SUM1_0_0_o2, hades_tdc_bundle_inst/hit_valid_1[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[1],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463 (PFU) covers blocks:
-     offset_valid_RNO,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[0],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[13],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[15],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[17],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[19],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[21],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486 (PFU) covers
-     blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487 (PFU) covers
-     blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488 (PFU) covers
-     blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489 (PFU) covers
-     blocks: valid_internal_RNO, un1_out_internal35_1_0_m3,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
-     ut_buffered1[0], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[0].in_clk_synced[0]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
-     ut_buffered1[1], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[1].in_clk_synced[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
-     ut_buffered1[2], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[2].in_clk_synced[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
-     ut_buffered1[3], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[3].in_clk_synced[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
-     ut_buffered1[4], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[0].in_clk_synced[4]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
-     ut_buffered1[5], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[1].in_clk_synced[5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
-     ut_buffered1[6], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[2].in_clk_synced[6]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
-     ut_buffered1[7], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen
-     blk1[3].in_clk_synced[7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
-     ut_buffered[0]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
-     ut_buffered[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
-     ut_buffered[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
-     ut_buffered[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o
-     ut_buffered[4]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o
-     ut_buffered[5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o
-     ut_buffered[6]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o
-     ut_buffered[7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516 (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518 (PFU) covers blocks:
-     window_RNO[0], un1_reset_0_a2_2,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519 (PFU) covers blocks:
-     window_6[1], window_6[3],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 (PFU) covers blocks:
-     window_0_sqmuxadup, un1_invalid_dl,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521 (PFU) covers blocks:
-     window_6[4], window_6[5],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522 (PFU) covers blocks:
-     window_6[6], window_6[7],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6],
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[3],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[5],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[7],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[9],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527 (PFU) covers
-     blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528 (PFU) covers
-     blocks: buf_negative_ready_RNIG7JA,
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out_valid
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535 (PFU) covers
-     blocks: buf_negative_ready_4_f0_0_0,
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541 (PFU) covers
-     blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542 (PFU) covers
-     blocks: buf_positive_ready_4_iv_i_0,
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
-     t/in_synced[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
-     t/in_synced[2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
-     t/in_synced[4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
-     t/in_synced[6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555 (PFU)
-     covers blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7, hades_
-     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556 (PFU)
-     covers blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0, hade
-     s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557 (PFU)
-     covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1, hades_
-     tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558 (PFU)
-     covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_tdc_bun
-     dle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[0][0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[0][2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[0][4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[0][6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[1][0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[1][2],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[1][4],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/dl[1][6],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/in_synced[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-     nst/dec_neg_inst/in_synced[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/in_synced[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-     nst/dec_neg_inst/in_synced[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/in_synced[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-     nst/dec_neg_inst/in_synced[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/in_synced[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-     nst/dec_neg_inst/in_synced[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571
-     (PFU) covers blocks: out_internal_2_1_0_.m11_i, out_internal_2_1_0_.m15_i, 
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inter
-     nal[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/o
-     ut_internal[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572
-     (PFU) covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_o5,
-      hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inte
-     rnal[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573
-     (PFU) covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_t
-     dc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575 (PFU)
-     covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576
-     (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[0],
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577
-     (PFU) covers blocks:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[0].in_clk_synced[0]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[1].in_clk_synced[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[2].in_clk_synced[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[3].in_clk_synced[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[0].in_clk_synced[4]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[1].in_clk_synced[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[2].in_clk_synced[6]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/tdc_inst/genblk1[3].in_clk_synced[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_ch
-     annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[0].out_buffered[0]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[1].out_buffered[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[2].out_buffered[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[3].out_buffered[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[0].out_buffered[4]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[1].out_buffered[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[2].out_buffered[6]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619 (PFU)
-     covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins
-     t/genblk1[3].out_buffered[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[0].out_buffered[0]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[1].out_buffered[1]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[2].out_buffered[2]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[3].out_buffered[3]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[0].out_buffered[4]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[1].out_buffered[5]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[2].out_buffered[6]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627
-     (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t
-     dc_neg_inst/genblk1[3].out_buffered[7]
-hades_tdc_bundle_inst/SLICE_628 (PFU) covers blocks: SUM0_1_0_x2, SUM1_0_0,
-     hades_tdc_bundle_inst/hit_i[0], hades_tdc_bundle_inst/hit_i[1]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629 (PFU) covers blocks:
-     window_end5_0_a2, discard4_0_a2_0,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end
-trb_adapter_inst/SLICE_631 (PFU) covers blocks:
-     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1],
-     trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2]
-trb_adapter_inst/SLICE_632 (PFU) covers blocks: trb_adapter_inst/buf_rden_prev
-trb_adapter_inst/SLICE_633 (PFU) covers blocks: trb_adapter_inst/finished_prev
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 (PFU) covers blocks:
-     offset_1_sqmuxa_i_0, offset_1_sqmuxa_i_0_o2
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635 (PFU) covers blocks:
-     un1_reset_0_a2_1, discard4_0_a2_0
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636 (PFU) covers
-     blocks: LUT4_16, LUT4_23
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637 (PFU) covers
-     blocks: LUT4_19, LUT4_21
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638 (PFU) covers
-     blocks: LUT4_6, LUT4_13
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639 (PFU) covers
-     blocks: LUT4_9, LUT4_11
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640 (PFU) covers
-     blocks: LUT4_16, LUT4_23
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641 (PFU) covers
-     blocks: LUT4_19, LUT4_21
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642 (PFU) covers
-     blocks: LUT4_6, LUT4_13
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643 (PFU) covers
-     blocks: LUT4_9, LUT4_11
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644 (PFU) covers
-     blocks: LUT4_16, LUT4_23
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645 (PFU) covers
-     blocks: LUT4_19, LUT4_21
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646 (PFU) covers
-     blocks: LUT4_6, LUT4_13
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647 (PFU) covers
-     blocks: LUT4_9, LUT4_11
-fifo_colector_inst/fifo40_inst/SLICE_648 (PFU) covers blocks: LUT4_6, LUT4_13
-fifo_colector_inst/fifo40_inst/SLICE_649 (PFU) covers blocks: LUT4_9, LUT4_11
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650 (PFU) covers blocks:
-     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651 (PFU) covers blocks:
-     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652 (PFU) covers blocks:
-     un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0
-hades_tdc_bundle_inst/SLICE_653 (PFU) covers blocks:
-     hit_valid_pmux_iv_0_a2_2_RNITDG11, hit_valid_pmux_iv_0_a2_2
-hades_tdc_bundle_inst/SLICE_654 (PFU) covers blocks: hit_valid_pmux_iv_0_0,
-     hit_valid_pmux_iv_0_a2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655 (PFU) covers
-     blocks: LUT4_23, LUT4_14
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656 (PFU) covers
-     blocks: LUT4_22, LUT4_15
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657 (PFU) covers
-     blocks: LUT4_20, LUT4_18
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658 (PFU) covers
-     blocks: LUT4_13, LUT4_4
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659 (PFU) covers
-     blocks: LUT4_12, LUT4_5
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660 (PFU) covers
-     blocks: LUT4_10, LUT4_8
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661 (PFU) covers
-     blocks: LUT4_23, LUT4_14
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662 (PFU) covers
-     blocks: LUT4_22, LUT4_15
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663 (PFU) covers
-     blocks: LUT4_20, LUT4_18
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664 (PFU) covers
-     blocks: LUT4_13, LUT4_4
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665 (PFU) covers
-     blocks: LUT4_12, LUT4_5
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666 (PFU) covers
-     blocks: LUT4_10, LUT4_8
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667 (PFU) covers
-     blocks: LUT4_23, LUT4_14
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668 (PFU) covers
-     blocks: LUT4_22, LUT4_15
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669 (PFU) covers
-     blocks: LUT4_20, LUT4_18
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670 (PFU) covers
-     blocks: LUT4_13, LUT4_4
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671 (PFU) covers
-     blocks: LUT4_12, LUT4_5
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672 (PFU) covers
-     blocks: LUT4_10, LUT4_8
-fifo_colector_inst/fifo40_inst/SLICE_673 (PFU) covers blocks: LUT4_23, LUT4_14
-fifo_colector_inst/fifo40_inst/SLICE_674 (PFU) covers blocks: LUT4_22, LUT4_15
-fifo_colector_inst/fifo40_inst/SLICE_675 (PFU) covers blocks: LUT4_21, LUT4_19
-fifo_colector_inst/fifo40_inst/SLICE_676 (PFU) covers blocks: LUT4_20, LUT4_18
-fifo_colector_inst/fifo40_inst/SLICE_677 (PFU) covers blocks: LUT4_13, LUT4_4
-fifo_colector_inst/fifo40_inst/SLICE_678 (PFU) covers blocks: LUT4_12, LUT4_5
-fifo_colector_inst/fifo40_inst/SLICE_679 (PFU) covers blocks: LUT4_10, LUT4_8
-fifo_colector_inst/SLICE_680 (PFU) covers blocks: in_empty_pmux_u,
-     in_empty_pmux_0
-hades_tdc_bundle_inst/SLICE_681 (PFU) covers blocks:
-     un1_buf_positive_0_I_9_0_RNO_0, drop_cmp_buf_coarse_2_ac0_3
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682 (PFU) covers blocks:
-     un1_reset_0_a2_c, discard4_0_a2_0
-hades_tdc_bundle_inst/SLICE_683 (PFU) covers blocks: buf_out12,
-     hit_valid_pmux_iv_0_a2_2
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684 (PFU) covers blocks:
-     discard4_0_a2_0_3, window_RNIOA5C[2]
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685 (PFU) covers
-     blocks: LUT4_3, LUT4_2
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686 (PFU) covers
-     blocks: LUT4_1, LUT4_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687 (PFU) covers
-     blocks: LUT4_3, LUT4_2
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688 (PFU) covers
-     blocks: LUT4_1, LUT4_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689 (PFU) covers
-     blocks: LUT4_3, LUT4_2
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690 (PFU) covers
-     blocks: LUT4_1, LUT4_0
-fifo_colector_inst/fifo40_inst/SLICE_691 (PFU) covers blocks: LUT4_0, LUT4_1
-fifo_colector_inst/fifo40_inst/SLICE_692 (PFU) covers blocks: LUT4_3, LUT4_2
-hades_tdc_bundle_inst/SLICE_693 (PFU) covers blocks: un1_hit_i_2_0_a2,
-     SUM1_0_0_o2_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694
-     (PFU) covers blocks: un1_out_internal35_1_0_o5, out_internal_2_1_0_.m15_i_1
-     
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695 (PFU)
-     covers blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696 (PFU)
-     covers blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697 (PFU) covers
-     blocks: un1_coarse_1_0_I_9_0_RNO, un1_buf_positive_0_I_9_0_RNO
-hades_tdc_bundle_inst/SLICE_698 (PFU) covers blocks: un1_coarse_1_0_I_9_RNO_0,
-     drop_cmp_buf_coarse_2_ac0_7
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699 (PFU) covers
-     blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700 (PFU) covers
-     blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0
-hades_tdc_bundle_inst/SLICE_701 (PFU) covers blocks:
-     drop_cmp_buf_coarse_2_ac0_13_0, drop_cmp_buf_coarse_2_ac0_9_0
-fifo_colector_inst/fifo40_inst/SLICE_702 (PFU) covers blocks: LUT4_16, LUT4_17
-fifo_colector_inst/fifo40_inst/SLICE_703 (PFU) covers blocks: LUT4_7, LUT4_11
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704 (PFU) covers
-     blocks: LUT4_7, LUT4_11
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705 (PFU) covers
-     blocks: LUT4_17, LUT4_21
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706 (PFU) covers
-     blocks: LUT4_7, LUT4_11
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707 (PFU) covers
-     blocks: LUT4_17, LUT4_21
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708 (PFU) covers
-     blocks: LUT4_7, LUT4_11
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709 (PFU) covers
-     blocks: LUT4_17, LUT4_21
-hades_tdc_bundle_inst/SLICE_710 (PFU) covers blocks: hit_valid_pmux_iv_0_m2,
-     drop_cmp_buf_valid_0_sqmuxa_0_a2
-genblk1[2].tdc_channel_fifo_out_inst/SLICE_711 (PFU) covers blocks: AND2_t20,
-     genblk1[2].tdc_channel_fifo_out_inst/fifo_wren
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712 (PFU) covers
-     blocks: AND2_t19
-genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713 (PFU) covers blocks:
-     valid_internal_RNO_0
-genblk1[1].tdc_channel_fifo_out_inst/SLICE_714 (PFU) covers blocks: AND2_t20,
-     genblk1[1].tdc_channel_fifo_out_inst/fifo_wren
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715 (PFU) covers
-     blocks: AND2_t19
-genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716 (PFU) covers blocks:
-     valid_internal_RNO_0
-genblk1[0].tdc_channel_fifo_out_inst/SLICE_717 (PFU) covers blocks: AND2_t20,
-     genblk1[0].tdc_channel_fifo_out_inst/fifo_wren
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718 (PFU) covers
-     blocks: AND2_t19
-genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719 (PFU) covers blocks:
-     valid_internal_RNO_0
-fifo_colector_inst/fifo40_inst/SLICE_720 (PFU) covers blocks: AND2_t19
-fifo_colector_inst/fifo40_inst/SLICE_721 (PFU) covers blocks: AND2_t20
-fifo_colector_inst/SLICE_722 (PFU) covers blocks: iterator_RNI7U5I[1]
-trb_adapter_inst/SLICE_723 (PFU) covers blocks: LVL1_TRG_DATA_VALI_IN_rising
-trb_adapter_inst/SLICE_724 (PFU) covers blocks: release_out,
-     trb_adapter_inst/finished
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725
-     (PFU) covers blocks: valid_RNI97O31,
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726
-     (PFU) covers blocks: in_synced_RNIT1GT[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727
-     (PFU) covers blocks: un1_out_internal35_1_0_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728
-     (PFU) covers blocks: out_internal_2_1_0_.m11_i_0
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729
-     (PFU) covers blocks: out_internal_2_1_0_.m11_i_m3
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730 (PFU)
-     covers blocks: in_synced_RNIB4EQ[7]
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731 (PFU)
-     covers blocks: valid_RNI8UMR,
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid
-hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732 (PFU)
-     covers blocks: un1_out_internal35_1_0_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 (PFU) covers
-     blocks: valid_fast_RNI999V
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734 (PFU) covers
-     blocks: in_synced_RNI3HPF[7]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735 (PFU) covers
-     blocks: un1_out_internal35_1_0_0
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (PFU) covers
-     blocks: valid_fast_RNI5DQ71,
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737 (PFU) covers blocks:
-     un1_reset_0_a2_2
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 (PFU) covers blocks:
-     window_6[2]
-hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739 (PFU) covers blocks:
-     window_RNICU4C[3]
-SLICE_740 (PFU) covers blocks: drop_cmp_buf_0_sqmuxa_0_a2, reset_dl[2]
-hades_tdc_bundle_inst/SLICE_741 (PFU) covers blocks: hit_out_i_6_i_a2_0[0]
-pll0inst/SLICE_742 (PFU) covers blocks: GND
-SLICE_743 (PFU) covers blocks: hades_lvl1_pad_RNINMH5
-SLICE_744 (PFU) covers blocks: trig_pad_RNII4FF[0]
-SLICE_745 (PFU) covers blocks: trig_pad_RNIJ5FF[1]
-SLICE_746 (PFU) covers blocks: trig_pad_RNIK6FF[2]
-SLICE_747 (PFU) covers blocks: hades_trig_pad_RNIE1B4
-hades_raw_valid_vect[0] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[0]
-fifo_data_out[0] (PIC/PIO) covers blocks: fifo_data_out_pad[0]
-clk (PIC/PIO) covers blocks: clk_pad
-hades_drop_cmp_buf_valid (PIC/PIO) covers blocks: hades_drop_cmp_buf_valid_pad
-hades_drop_cmp_buf_coarse[11] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[11]
-hades_drop_cmp_buf_coarse[10] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[10]
-hades_drop_cmp_buf_coarse[9] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[9]
-hades_drop_cmp_buf_coarse[8] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[8]
-hades_drop_cmp_buf_coarse[7] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[7]
-hades_drop_cmp_buf_coarse[6] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[6]
-hades_drop_cmp_buf_coarse[5] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[5]
-hades_drop_cmp_buf_coarse[4] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[4]
-hades_drop_cmp_buf_coarse[3] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[3]
-hades_drop_cmp_buf_coarse[2] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[2]
-hades_drop_cmp_buf_coarse[1] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[1]
-hades_drop_cmp_buf_coarse[0] (PIC/PIO) covers blocks:
-     hades_drop_cmp_buf_coarse_pad[0]
-hades_drop_cmp_buf[11] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[11]
-hades_drop_cmp_buf[10] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[10]
-hades_drop_cmp_buf[9] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[9]
-hades_drop_cmp_buf[8] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[8]
-hades_drop_cmp_buf[7] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[7]
-hades_drop_cmp_buf[6] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[6]
-hades_drop_cmp_buf[5] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[5]
-hades_drop_cmp_buf[4] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[4]
-hades_drop_cmp_buf[3] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[3]
-hades_drop_cmp_buf[2] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[2]
-hades_drop_cmp_buf[1] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[1]
-hades_drop_cmp_buf[0] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[0]
-hades_dbg2_coarse[8] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[8]
-hades_dbg2_coarse[7] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[7]
-hades_dbg2_coarse[6] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[6]
-hades_dbg2_coarse[5] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[5]
-hades_dbg2_coarse[4] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[4]
-hades_dbg2_coarse[3] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[3]
-hades_dbg2_coarse[2] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[2]
-hades_dbg2_coarse[1] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[1]
-hades_dbg2_coarse[0] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[0]
-hades_dbg2_out[31] (PIC/PIO) covers blocks: hades_dbg2_out_pad[31]
-hades_dbg2_out[30] (PIC/PIO) covers blocks: hades_dbg2_out_pad[30]
-hades_dbg2_out[29] (PIC/PIO) covers blocks: hades_dbg2_out_pad[29]
-hades_dbg2_out[28] (PIC/PIO) covers blocks: hades_dbg2_out_pad[28],
-     hades_tdc_bundle_inst_hitbuffer_1_io[23]
-hades_dbg2_out[27] (PIC/PIO) covers blocks: hades_dbg2_out_pad[27],
-     hades_tdc_bundle_inst_hitbuffer_1_io[22]
-hades_dbg2_out[26] (PIC/PIO) covers blocks: hades_dbg2_out_pad[26],
-     hades_tdc_bundle_inst_hitbuffer_1_io[21]
-hades_dbg2_out[25] (PIC/PIO) covers blocks: hades_dbg2_out_pad[25],
-     hades_tdc_bundle_inst_hitbuffer_1_io[20]
-hades_dbg2_out[24] (PIC/PIO) covers blocks: hades_dbg2_out_pad[24],
-     hades_tdc_bundle_inst_hitbuffer_1_io[19]
-hades_dbg2_out[23] (PIC/PIO) covers blocks: hades_dbg2_out_pad[23],
-     hades_tdc_bundle_inst_hitbuffer_1_io[18]
-hades_dbg2_out[22] (PIC/PIO) covers blocks: hades_dbg2_out_pad[22],
-     hades_tdc_bundle_inst_hitbuffer_1_io[17]
-hades_dbg2_out[21] (PIC/PIO) covers blocks: hades_dbg2_out_pad[21],
-     hades_tdc_bundle_inst_hitbuffer_1_io[16]
-hades_dbg2_out[20] (PIC/PIO) covers blocks: hades_dbg2_out_pad[20],
-     hades_tdc_bundle_inst_hitbuffer_1_io[15]
-hades_dbg2_out[19] (PIC/PIO) covers blocks: hades_dbg2_out_pad[19]
-hades_dbg2_out[18] (PIC/PIO) covers blocks: hades_dbg2_out_pad[18],
-     hades_tdc_bundle_inst_hitbuffer_1_io[14]
-hades_dbg2_out[17] (PIC/PIO) covers blocks: hades_dbg2_out_pad[17],
-     hades_tdc_bundle_inst_hitbuffer_1_io[13]
-hades_dbg2_out[16] (PIC/PIO) covers blocks: hades_dbg2_out_pad[16],
-     hades_tdc_bundle_inst_hitbuffer_1_io[12]
-hades_dbg2_out[15] (PIC/PIO) covers blocks: hades_dbg2_out_pad[15]
-hades_dbg2_out[14] (PIC/PIO) covers blocks: hades_dbg2_out_pad[14]
-hades_dbg2_out[13] (PIC/PIO) covers blocks: hades_dbg2_out_pad[13]
-hades_dbg2_out[12] (PIC/PIO) covers blocks: hades_dbg2_out_pad[12]
-hades_dbg2_out[11] (PIC/PIO) covers blocks: hades_dbg2_out_pad[11]
-hades_dbg2_out[10] (PIC/PIO) covers blocks: hades_dbg2_out_pad[10]
-hades_dbg2_out[9] (PIC/PIO) covers blocks: hades_dbg2_out_pad[9]
-hades_dbg2_out[8] (PIC/PIO) covers blocks: hades_dbg2_out_pad[8]
-hades_dbg2_out[7] (PIC/PIO) covers blocks: hades_dbg2_out_pad[7]
-hades_dbg2_out[6] (PIC/PIO) covers blocks: hades_dbg2_out_pad[6]
-hades_dbg2_out[5] (PIC/PIO) covers blocks: hades_dbg2_out_pad[5]
-hades_dbg2_out[4] (PIC/PIO) covers blocks: hades_dbg2_out_pad[4]
-hades_dbg2_out[3] (PIC/PIO) covers blocks: hades_dbg2_out_pad[3]
-hades_dbg2_out[2] (PIC/PIO) covers blocks: hades_dbg2_out_pad[2],
-     hades_tdc_bundle_inst_hitbuffer_1_io[2]
-hades_dbg2_out[1] (PIC/PIO) covers blocks: hades_dbg2_out_pad[1],
-     hades_tdc_bundle_inst_hitbuffer_1_io[1]
-hades_dbg2_out[0] (PIC/PIO) covers blocks: hades_dbg2_out_pad[0],
-     hades_tdc_bundle_inst_hitbuffer_1_io[0]
-hades_buf_drop[3] (PIC/PIO) covers blocks: hades_buf_drop_pad[3]
-hades_buf_drop[2] (PIC/PIO) covers blocks: hades_buf_drop_pad[2]
-hades_buf_drop[1] (PIC/PIO) covers blocks: hades_buf_drop_pad[1],
-     hades_tdc_bundle_inst_buf_drop_1io[1]
-hades_buf_drop[0] (PIC/PIO) covers blocks: hades_buf_drop_pad[0]
-hades_invalid_dl[3] (PIC/PIO) covers blocks: hades_invalid_dl_pad[3]
-hades_invalid_dl[2] (PIC/PIO) covers blocks: hades_invalid_dl_pad[2]
-hades_invalid_dl[1] (PIC/PIO) covers blocks: hades_invalid_dl_pad[1]
-hades_invalid_dl[0] (PIC/PIO) covers blocks: hades_invalid_dl_pad[0]
-hades_discard (PIC/PIO) covers blocks: hades_discard_pad
-hades_hit_valid[3] (PIC/PIO) covers blocks: hades_hit_valid_pad[3]
-hades_hit_valid[2] (PIC/PIO) covers blocks: hades_hit_valid_pad[2]
-hades_hit_valid[1] (PIC/PIO) covers blocks: hades_hit_valid_pad[1]
-hades_hit_valid[0] (PIC/PIO) covers blocks: hades_hit_valid_pad[0]
-hades_hit_out_i[3] (PIC/PIO) covers blocks: hades_hit_out_i_pad[3]
-hades_hit_out_i[2] (PIC/PIO) covers blocks: hades_hit_out_i_pad[2]
-hades_hit_out_i[1] (PIC/PIO) covers blocks: hades_hit_out_i_pad[1]
-hades_hit_out_i[0] (PIC/PIO) covers blocks: hades_hit_out_i_pad[0]
-hades_buf_finished (PIC/PIO) covers blocks: hades_buf_finished_pad
-hades_buf_release (PIC/PIO) covers blocks: hades_buf_release_pad
-hades_buf_out_valid (PIC/PIO) covers blocks: hades_buf_out_valid_pad,
-     hades_tdc_bundle_inst_buf_out_validio
-hades_window_end (PIC/PIO) covers blocks: hades_window_end_pad
-hades_offset_valid (PIC/PIO) covers blocks: hades_offset_valid_pad
-hades_offset[8] (PIC/PIO) covers blocks: hades_offset_pad[8],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8]
-hades_offset[7] (PIC/PIO) covers blocks: hades_offset_pad[7],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7]
-hades_offset[6] (PIC/PIO) covers blocks: hades_offset_pad[6],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]
-hades_offset[5] (PIC/PIO) covers blocks: hades_offset_pad[5],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]
-hades_offset[4] (PIC/PIO) covers blocks: hades_offset_pad[4],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]
-hades_offset[3] (PIC/PIO) covers blocks: hades_offset_pad[3],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]
-hades_offset[2] (PIC/PIO) covers blocks: hades_offset_pad[2],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]
-hades_offset[1] (PIC/PIO) covers blocks: hades_offset_pad[1],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]
-hades_offset[0] (PIC/PIO) covers blocks: hades_offset_pad[0],
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]
-hades_lvl1_invalid (PIC/PIO) covers blocks: hades_lvl1_invalid_pad,
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0]
-hades_lvl1 (PIC/PIO) covers blocks: hades_lvl1_pad,
-     hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0]
-hades_raw_valid_vect[1] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[1]
-hades_raw_out_valid (PIC/PIO) covers blocks: hades_raw_out_valid_pad,
-     hades_tdc_bundle_inst_referenced_out_validio
-hades_trig (PIC/PIO) covers blocks: hades_trig_pad
-release_out (PIC/PIO) covers blocks: release_out_pad
-finished (PIC/PIO) covers blocks: finished_pad
-last_buf_empty (PIC/PIO) covers blocks: last_buf_empty_pad
-discard (PIC/PIO) covers blocks: discard_pad
-burst (PIC/PIO) covers blocks: burst_pad
-LVL1_TRG_DATA_VALI_IN_rising (PIC/PIO) covers blocks:
-     LVL1_TRG_DATA_VALI_IN_rising_pad
-FEE_TRG_RELEASE_OUT (PIC/PIO) covers blocks: FEE_TRG_RELEASE_OUT_pad,
-     trb_adapter_inst_FEE_TRG_RELEASE_OUTio
-FEE_DATAFINISHED_OUT (PIC/PIO) covers blocks: FEE_DATAFINISHED_OUT_pad,
-     trb_adapter_inst_FEE_DATAFINISHED_OUTio
-FEE_DATA_WRITE_OUT (PIC/PIO) covers blocks: FEE_DATA_WRITE_OUT_pad,
-     trb_adapter_inst_FEE_DATA_WRITE_OUTio
-FEE_DATA_OUT[31] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[31]
-FEE_DATA_OUT[30] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[30]
-FEE_DATA_OUT[29] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[29]
-FEE_DATA_OUT[28] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[28]
-FEE_DATA_OUT[27] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[27]
-FEE_DATA_OUT[26] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[26]
-FEE_DATA_OUT[25] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[25]
-FEE_DATA_OUT[24] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[24]
-FEE_DATA_OUT[23] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[23]
-FEE_DATA_OUT[22] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[22]
-FEE_DATA_OUT[21] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[21]
-FEE_DATA_OUT[20] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[20]
-FEE_DATA_OUT[19] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[19]
-FEE_DATA_OUT[18] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[18]
-FEE_DATA_OUT[17] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[17]
-FEE_DATA_OUT[16] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[16]
-FEE_DATA_OUT[15] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[15]
-FEE_DATA_OUT[14] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[14]
-FEE_DATA_OUT[13] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[13]
-FEE_DATA_OUT[12] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[12]
-FEE_DATA_OUT[11] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[11]
-FEE_DATA_OUT[10] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[10]
-FEE_DATA_OUT[9] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[9]
-FEE_DATA_OUT[8] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[8]
-FEE_DATA_OUT[7] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[7]
-FEE_DATA_OUT[6] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[6]
-FEE_DATA_OUT[5] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[5]
-FEE_DATA_OUT[4] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[4]
-FEE_DATA_OUT[3] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[3]
-FEE_DATA_OUT[2] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[2]
-FEE_DATA_OUT[1] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[1]
-FEE_DATA_OUT[0] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[0]
-LVL1_INVALID_TRG_IN (PIC/PIO) covers blocks: LVL1_INVALID_TRG_IN_pad,
-     trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0]
-LVL1_TRG_DATA_VALID_IN (PIC/PIO) covers blocks: LVL1_TRG_DATA_VALID_IN_pad,
-     trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0]
-fifo_empty1 (PIC/PIO) covers blocks: fifo_empty1_pad
-fifo_rden (PIC/PIO) covers blocks: fifo_rden_pad
-fifo_data_out[31] (PIC/PIO) covers blocks: fifo_data_out_pad[31]
-fifo_data_out[30] (PIC/PIO) covers blocks: fifo_data_out_pad[30]
-fifo_data_out[29] (PIC/PIO) covers blocks: fifo_data_out_pad[29]
-fifo_data_out[28] (PIC/PIO) covers blocks: fifo_data_out_pad[28]
-fifo_data_out[27] (PIC/PIO) covers blocks: fifo_data_out_pad[27]
-fifo_data_out[26] (PIC/PIO) covers blocks: fifo_data_out_pad[26]
-fifo_data_out[25] (PIC/PIO) covers blocks: fifo_data_out_pad[25]
-fifo_data_out[24] (PIC/PIO) covers blocks: fifo_data_out_pad[24]
-fifo_data_out[23] (PIC/PIO) covers blocks: fifo_data_out_pad[23]
-fifo_data_out[22] (PIC/PIO) covers blocks: fifo_data_out_pad[22]
-fifo_data_out[21] (PIC/PIO) covers blocks: fifo_data_out_pad[21]
-fifo_data_out[20] (PIC/PIO) covers blocks: fifo_data_out_pad[20]
-fifo_data_out[19] (PIC/PIO) covers blocks: fifo_data_out_pad[19]
-fifo_data_out[18] (PIC/PIO) covers blocks: fifo_data_out_pad[18]
-fifo_data_out[17] (PIC/PIO) covers blocks: fifo_data_out_pad[17]
-fifo_data_out[16] (PIC/PIO) covers blocks: fifo_data_out_pad[16]
-fifo_data_out[15] (PIC/PIO) covers blocks: fifo_data_out_pad[15]
-fifo_data_out[14] (PIC/PIO) covers blocks: fifo_data_out_pad[14]
-fifo_data_out[13] (PIC/PIO) covers blocks: fifo_data_out_pad[13]
-fifo_data_out[12] (PIC/PIO) covers blocks: fifo_data_out_pad[12]
-fifo_data_out[11] (PIC/PIO) covers blocks: fifo_data_out_pad[11]
-fifo_data_out[10] (PIC/PIO) covers blocks: fifo_data_out_pad[10]
-fifo_data_out[9] (PIC/PIO) covers blocks: fifo_data_out_pad[9]
-fifo_data_out[8] (PIC/PIO) covers blocks: fifo_data_out_pad[8]
-fifo_data_out[7] (PIC/PIO) covers blocks: fifo_data_out_pad[7]
-fifo_data_out[6] (PIC/PIO) covers blocks: fifo_data_out_pad[6]
-fifo_data_out[5] (PIC/PIO) covers blocks: fifo_data_out_pad[5]
-fifo_data_out[4] (PIC/PIO) covers blocks: fifo_data_out_pad[4]
-fifo_data_out[3] (PIC/PIO) covers blocks: fifo_data_out_pad[3]
-fifo_data_out[2] (PIC/PIO) covers blocks: fifo_data_out_pad[2]
-fifo_data_out[1] (PIC/PIO) covers blocks: fifo_data_out_pad[1]
-trig[2] (PIC/PIO) covers blocks: trig_pad[2]
-trig[1] (PIC/PIO) covers blocks: trig_pad[1]
-trig[0] (PIC/PIO) covers blocks: trig_pad[0]
-reset_dc (PIC/PIO) covers blocks: reset_dc_pad, reset_dl_0io[1]
-rd_clk (PIC/PIO) covers blocks: rd_clk_pad
-genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
-     covers block:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
-     covers block:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD)
-     covers block:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 (PDPW16KD) covers block:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
-pll0inst/PLLInst_0 (EHXPLLL) covers block: pll0inst/PLLInst_0
-
-
-Signal Cross Reference
-Signal FEE_DATA_OUT_c[0] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO18
-   Load Comps: fifo_data_out[0]:I0, FEE_DATA_OUT[0]:I0
-Signal clk_c - Driver Comp: clk:O0
-   Load Comps: pll0inst/PLLInst_0:CLKI
-Signal reset_dl[1] - Driver Comp: reset_dc_MGIOL:O2
-   Load Comps: SLICE_740:I4
-Signal pll_clks[3] - Driver Comp: pll0inst/PLLInst_0:CLKOS3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_79:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_80:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_81:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_82:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_83:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_103:I15,
-        hades_tdc_bundle_inst/SLICE_121:I15,
-        hades_tdc_bundle_inst/SLICE_122:I15,
-        hades_tdc_bundle_inst/SLICE_123:I15, fifo_colector_inst/SLICE_125:I15,
-        fifo_colector_inst/SLICE_126:I15, fifo_colector_inst/SLICE_127:I15,
-        fifo_colector_inst/SLICE_128:I15, fifo_colector_inst/SLICE_129:I15,
-        fifo_colector_inst/SLICE_130:I15, fifo_colector_inst/SLICE_131:I15,
-        fifo_colector_inst/SLICE_132:I15, fifo_colector_inst/SLICE_133:I15,
-        fifo_colector_inst/SLICE_134:I15, fifo_colector_inst/SLICE_135:I15,
-        fifo_colector_inst/SLICE_136:I15, fifo_colector_inst/SLICE_137:I15,
-        fifo_colector_inst/SLICE_138:I15, fifo_colector_inst/SLICE_139:I15,
-        fifo_colector_inst/SLICE_140:I15, fifo_colector_inst/SLICE_141:I15,
-        fifo_colector_inst/SLICE_142:I15, fifo_colector_inst/SLICE_143:I15,
-        fifo_colector_inst/SLICE_144:I15, fifo_colector_inst/SLICE_145:I15,
-        fifo_colector_inst/SLICE_146:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_152:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_153:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_154:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_155:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_156:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_157:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_158:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_159:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_160:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_161:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_171:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_182:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_183:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_184:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_185:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_186:I15,
-        fifo_colector_inst/SLICE_187:I15, fifo_colector_inst/SLICE_189:I15,
-        fifo_colector_inst/SLICE_190:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I15,
-        hades_tdc_bundle_inst/SLICE_432:I15,
-        hades_tdc_bundle_inst/SLICE_433:I15,
-        hades_tdc_bundle_inst/SLICE_434:I15,
-        hades_tdc_bundle_inst/SLICE_435:I15,
-        hades_tdc_bundle_inst/SLICE_436:I15,
-        hades_tdc_bundle_inst/SLICE_437:I15,
-        hades_tdc_bundle_inst/SLICE_438:I15,
-        hades_tdc_bundle_inst/SLICE_439:I15,
-        hades_tdc_bundle_inst/SLICE_440:I15,
-        hades_tdc_bundle_inst/SLICE_441:I15,
-        hades_tdc_bundle_inst/SLICE_442:I15,
-        hades_tdc_bundle_inst/SLICE_443:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I15,
-        hades_tdc_bundle_inst/SLICE_445:I15,
-        hades_tdc_bundle_inst/SLICE_446:I15,
-        hades_tdc_bundle_inst/SLICE_447:I15,
-        hades_tdc_bundle_inst/SLICE_448:I15,
-        hades_tdc_bundle_inst/SLICE_449:I15,
-        hades_tdc_bundle_inst/SLICE_450:I15,
-        hades_tdc_bundle_inst/SLICE_451:I15,
-        hades_tdc_bundle_inst/SLICE_452:I15,
-        hades_tdc_bundle_inst/SLICE_453:I15,
-        hades_tdc_bundle_inst/SLICE_454:I15,
-        hades_tdc_bundle_inst/SLICE_455:I15,
-        hades_tdc_bundle_inst/SLICE_456:I15,
-        hades_tdc_bundle_inst/SLICE_457:I15,
-        hades_tdc_bundle_inst/SLICE_458:I15,
-        hades_tdc_bundle_inst/SLICE_459:I15,
-        hades_tdc_bundle_inst/SLICE_460:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I15,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I15, hade
-        s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:I15,
-         hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544
-        :I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLIC
-        E_545:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_546:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
-        _inst/SLICE_547:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
-        t/dec_inst/SLICE_548:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
-        t_inst/dec_inst/SLICE_549:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_inst/SLICE_550:I15, hades_tdc_bundle_inst/hades_tdc_chan
-        nel_raw_out_inst/dec_inst/SLICE_551:I15, hades_tdc_bundle_inst/hades_tdc
-        _channel_raw_out_inst/dec_inst/SLICE_552:I15, hades_tdc_bundle_inst/hade
-        s_tdc_channel_raw_out_inst/dec_inst/SLICE_553:I15, hades_tdc_bundle_inst
-        /hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:I15, hades_tdc_bundle
-        _inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:I15, hades_tdc_b
-        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:I15, hades_
-        tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:I15, h
-        ades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:I
-        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
-        ICE_559:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
-        g_inst/SLICE_560:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-        st/dec_neg_inst/SLICE_561:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_562:I15, hades_tdc_bundle_inst/hades_tdc_
-        channel_raw_out_inst/dec_neg_inst/SLICE_563:I15, hades_tdc_bundle_inst/h
-        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564:I15, hades_tdc_bund
-        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565:I15, hades
-        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566:I
-        15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL
-        ICE_567:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne
-        g_inst/SLICE_568:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-        st/dec_neg_inst/SLICE_569:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_570:I15, hades_tdc_bundle_inst/hades_tdc_
-        channel_raw_out_inst/dec_neg_inst/SLICE_571:I15, hades_tdc_bundle_inst/h
-        ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572:I15, hades_tdc_bund
-        le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573:I15, hades
-        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:I15, 
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:
-        I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/S
-        LICE_576:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_n
-        eg_inst/SLICE_577:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/tdc_inst/SLICE_591:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_
-        out_inst/tdc_inst/SLICE_595:I15, hades_tdc_bundle_inst/hades_tdc_channel
-        _raw_out_inst/tdc_neg_inst/SLICE_607:I15, hades_tdc_bundle_inst/hades_td
-        c_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I15, hades_tdc_bundle_inst
-        /hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:I15, hades_tdc_bundle
-        _inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:I15, hades_tdc_b
-        undle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623:I15, ha
-        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_62
-        7:I15, hades_tdc_bundle_inst/SLICE_628:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I15, hades_tdc_bundle_ins
-        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I15, hades_tdc_b
-        undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I15,
-        SLICE_740:I15, hades_dbg2_out[28]_MGIOL:I6, hades_dbg2_out[27]_MGIOL:I6,
-        hades_dbg2_out[26]_MGIOL:I6, hades_dbg2_out[25]_MGIOL:I6,
-        hades_dbg2_out[24]_MGIOL:I6, hades_dbg2_out[23]_MGIOL:I6,
-        hades_dbg2_out[22]_MGIOL:I6, hades_dbg2_out[21]_MGIOL:I6,
-        hades_dbg2_out[20]_MGIOL:I6, hades_dbg2_out[18]_MGIOL:I6,
-        hades_dbg2_out[17]_MGIOL:I6, hades_dbg2_out[16]_MGIOL:I6,
-        hades_dbg2_out[2]_MGIOL:I6, hades_dbg2_out[1]_MGIOL:I6,
-        hades_dbg2_out[0]_MGIOL:I6, hades_buf_drop[1]_MGIOL:I6,
-        hades_buf_out_valid_MGIOL:I6, hades_offset[8]_MGIOL:I6,
-        hades_offset[7]_MGIOL:I6, hades_offset[6]_MGIOL:I6,
-        hades_offset[5]_MGIOL:I6, hades_offset[4]_MGIOL:I6,
-        hades_offset[3]_MGIOL:I6, hades_offset[2]_MGIOL:I6,
-        hades_offset[1]_MGIOL:I6, hades_offset[0]_MGIOL:I6,
-        hades_lvl1_invalid_MGIOL:I6, hades_lvl1_MGIOL:I6,
-        hades_raw_out_valid_MGIOL:I6, reset_dc_MGIOL:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR,
-        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKW
-Signal reset_dl[2] - Driver Comp: SLICE_740:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I16,
-        hades_tdc_bundle_inst/SLICE_122:I16,
-        hades_tdc_bundle_inst/SLICE_123:I16,
-        genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I16,
-        genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I16,
-        genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I16,
-        hades_tdc_bundle_inst/SLICE_432:I16,
-        hades_tdc_bundle_inst/SLICE_433:I16,
-        hades_tdc_bundle_inst/SLICE_434:I16,
-        hades_tdc_bundle_inst/SLICE_435:I16,
-        hades_tdc_bundle_inst/SLICE_436:I16,
-        hades_tdc_bundle_inst/SLICE_437:I16,
-        hades_tdc_bundle_inst/SLICE_438:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I16,
-        hades_tdc_bundle_inst/SLICE_456:I14,
-        hades_tdc_bundle_inst/SLICE_457:I14,
-        hades_tdc_bundle_inst/SLICE_458:I14,
-        hades_tdc_bundle_inst/SLICE_459:I14,
-        hades_tdc_bundle_inst/SLICE_460:I14,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I9,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I16,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I14,
-        hades_tdc_bundle_inst/SLICE_628:I16, hades_tdc_bundle_inst/SLICE_653:I4,
-        hades_tdc_bundle_inst/SLICE_693:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I16,
-        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I16,
-        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I16, hades_tdc_bundle_ins
-        t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I2, hades_tdc_bu
-        ndle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I3,
-        SLICE_740:I1, hades_buf_drop[1]_MGIOL:I9, FEE_TRG_RELEASE_OUT_MGIOL:I9,
-        FEE_DATAFINISHED_OUT_MGIOL:I9, FEE_DATA_WRITE_OUT_MGIOL:I9
-Signal hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_710:O1
-   Load Comps: hades_buf_drop[1]_MGIOL:I10
-Signal hades_buf_drop_c[1] - Driver Comp: hades_buf_drop[1]_MGIOL:O0
-   Load Comps: hades_buf_drop[1]:I1
-Signal hades_tdc_bundle_inst.buf_out12 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_683:O0
-   Load Comps: hades_buf_out_valid_MGIOL:I10
-Signal N_248_i - Driver Comp: hades_tdc_bundle_inst/SLICE_653:O2
-   Load Comps: hades_buf_out_valid_MGIOL:I8
-Signal hades_buf_out_valid_c - Driver Comp: hades_buf_out_valid_MGIOL:O0
-   Load Comps: hades_buf_out_valid:I1
-Signal hades_lvl1_invalid_c - Driver Comp: hades_lvl1_invalid:O0
-   Load Comps: hades_lvl1_invalid_MGIOL:I5
-Signal hades_invalid_dl_c[0] - Driver Comp: hades_lvl1_invalid_MGIOL:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I4,
-        hades_invalid_dl[0]:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I2
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I4,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I2
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I3
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I3
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I4,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:O2
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:O2
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I2
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I4,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I2
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I3
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I3
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I4,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I8,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:O2
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:O2
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I8
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I8
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O4
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O3
-   Load Comps:
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I14,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
-   Load Comps: fifo_colector_inst/SLICE_128:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
-   Load Comps: fifo_colector_inst/SLICE_129:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
-   Load Comps: fifo_colector_inst/SLICE_130:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
-   Load Comps: fifo_colector_inst/SLICE_131:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
-   Load Comps: fifo_colector_inst/SLICE_132:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
-   Load Comps: fifo_colector_inst/SLICE_133:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
-   Load Comps: fifo_colector_inst/SLICE_138:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
-   Load Comps: fifo_colector_inst/SLICE_138:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
-   Load Comps: fifo_colector_inst/SLICE_139:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
-   Load Comps: fifo_colector_inst/SLICE_139:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
-   Load Comps: fifo_colector_inst/SLICE_140:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
-   Load Comps: fifo_colector_inst/SLICE_140:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
-   Load Comps: fifo_colector_inst/SLICE_141:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
-   Load Comps: fifo_colector_inst/SLICE_141:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
-   Load Comps: fifo_colector_inst/SLICE_142:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
-   Load Comps: fifo_colector_inst/SLICE_142:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
-   Load Comps: fifo_colector_inst/SLICE_143:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
-   Load Comps: fifo_colector_inst/SLICE_143:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
-   Load Comps: fifo_colector_inst/SLICE_144:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
-   Load Comps: fifo_colector_inst/SLICE_144:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
-   Load Comps: fifo_colector_inst/SLICE_145:I2
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
-   Load Comps: fifo_colector_inst/SLICE_145:I8
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
-   Load Comps: fifo_colector_inst/SLICE_126:I4
-Signal genblk1[2].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
-   Load Comps: fifo_colector_inst/SLICE_127:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I6,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I7,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O1
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I13
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I12
-Signal fifo_empty[2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O3
-   Load Comps: fifo_colector_inst/SLICE_125:I6, fifo_colector_inst/SLICE_680:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I1,
-        fifo_colector_inst/SLICE_722:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:O6
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I17
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I0
-Signal fifo_read[2] - Driver Comp: fifo_colector_inst/SLICE_190:O3
-   Load Comps: fifo_colector_inst/SLICE_190:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I12
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
-     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I16
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I1,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I7
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I2,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I8
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I3,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I9
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I0,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I6
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I0
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I1
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
-     Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:O2
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I3
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I4
-Signal trig_c_i[2] - Driver Comp: SLICE_746:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I5,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I5
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I4
-Signal pll_clks[2] - Driver Comp: pll0inst/PLLInst_0:CLKOS2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I15, ha
-        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:I1
-        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
-        94:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
-        t/SLICE_606:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
-        c_neg_inst/SLICE_610:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
-        t_inst/tdc_inst/SLICE_614:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/tdc_inst/SLICE_618:I15, hades_tdc_bundle_inst/hades_tdc_chan
-        nel_raw_out_inst/tdc_neg_inst/SLICE_622:I15, hades_tdc_bundle_inst/hades
-        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:I15
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I4
-Signal pll_clks[1] - Driver Comp: pll0inst/PLLInst_0:CLKOS
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I15, ha
-        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:I1
-        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
-        93:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
-        t/SLICE_605:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
-        c_neg_inst/SLICE_609:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
-        t_inst/tdc_inst/SLICE_613:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/tdc_inst/SLICE_617:I15, hades_tdc_bundle_inst/hades_tdc_chan
-        nel_raw_out_inst/tdc_neg_inst/SLICE_621:I15, hades_tdc_bundle_inst/hades
-        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:I15
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I4
-Signal pll_clks[0] - Driver Comp: pll0inst/PLLInst_0:CLKOP
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I15,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I15,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I15,
-        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I15,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I15, ha
-        des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:I1
-        5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5
-        92:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins
-        t/SLICE_604:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td
-        c_neg_inst/SLICE_608:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou
-        t_inst/tdc_inst/SLICE_612:I15, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/tdc_inst/SLICE_616:I15, hades_tdc_bundle_inst/hades_tdc_chan
-        nel_raw_out_inst/tdc_neg_inst/SLICE_620:I15, hades_tdc_bundle_inst/hades
-        _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:I15,
-        pll0inst/PLLInst_0:CLKFB
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O4
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
-     Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O3
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I4
-Signal genblk1[2].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
-     genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O0
-   Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I2
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I0
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I4,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I2
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I3
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I3
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I4,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:O2
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:O2
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I2
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I0
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I4,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I2
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I3
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I3
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I4,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:O2
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:O2
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I8
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I8
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O4
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O3
-   Load Comps:
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I14,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
-   Load Comps: fifo_colector_inst/SLICE_135:I2
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
-   Load Comps: fifo_colector_inst/SLICE_135:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
-   Load Comps: fifo_colector_inst/SLICE_136:I2
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
-   Load Comps: fifo_colector_inst/SLICE_136:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
-   Load Comps: fifo_colector_inst/SLICE_137:I2
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
-   Load Comps: fifo_colector_inst/SLICE_137:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
-   Load Comps: fifo_colector_inst/SLICE_142:I1
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
-   Load Comps: fifo_colector_inst/SLICE_142:I7
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
-   Load Comps: fifo_colector_inst/SLICE_143:I1
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
-   Load Comps: fifo_colector_inst/SLICE_143:I7
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
-   Load Comps: fifo_colector_inst/SLICE_144:I1
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
-   Load Comps: fifo_colector_inst/SLICE_144:I7
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
-   Load Comps: fifo_colector_inst/SLICE_145:I1
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
-   Load Comps: fifo_colector_inst/SLICE_145:I7
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
-   Load Comps: fifo_colector_inst/SLICE_126:I2, fifo_colector_inst/SLICE_126:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
-   Load Comps: fifo_colector_inst/SLICE_127:I2, fifo_colector_inst/SLICE_127:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
-   Load Comps: fifo_colector_inst/SLICE_128:I2, fifo_colector_inst/SLICE_128:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
-   Load Comps: fifo_colector_inst/SLICE_129:I2, fifo_colector_inst/SLICE_129:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
-   Load Comps: fifo_colector_inst/SLICE_130:I2, fifo_colector_inst/SLICE_130:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
-   Load Comps: fifo_colector_inst/SLICE_131:I2, fifo_colector_inst/SLICE_131:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
-   Load Comps: fifo_colector_inst/SLICE_132:I2, fifo_colector_inst/SLICE_132:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
-   Load Comps: fifo_colector_inst/SLICE_133:I2, fifo_colector_inst/SLICE_133:I8
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
-   Load Comps: fifo_colector_inst/SLICE_134:I2
-Signal genblk1[1].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
-   Load Comps: fifo_colector_inst/SLICE_134:I8
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I6,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O1
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I13
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I12
-Signal fifo_empty[1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O3
-   Load Comps: fifo_colector_inst/SLICE_125:I2, fifo_colector_inst/SLICE_680:I8,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:O6
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I17
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I0
-Signal fifo_read[1] - Driver Comp: fifo_colector_inst/SLICE_189:O4
-   Load Comps: fifo_colector_inst/SLICE_189:I7,
-        genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I0
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I12
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
-     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I16
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I0
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I1,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I7
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I2,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I8
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I3,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I9
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I0,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I6
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I0
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I1
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
-     Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:O2
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I3
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I4
-Signal trig_c_i[1] - Driver Comp: SLICE_745:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I5,
-        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I5
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O4
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
-     Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O3
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I4
-Signal genblk1[1].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
-     genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O0
-   Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I2
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I4,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I2
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I3
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I3
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I4,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:O2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:O2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I2
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 -
-     Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I4,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I2
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I3
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I3
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 -
-     Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I4,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I8,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:O2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:O2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I8
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I8
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O4
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O3
-   Load Comps:
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I14,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[18] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0
-   Load Comps: fifo_colector_inst/SLICE_139:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[19] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1
-   Load Comps: fifo_colector_inst/SLICE_139:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[20] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2
-   Load Comps: fifo_colector_inst/SLICE_140:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[21] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3
-   Load Comps: fifo_colector_inst/SLICE_140:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[22] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4
-   Load Comps: fifo_colector_inst/SLICE_141:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[23] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5
-   Load Comps: fifo_colector_inst/SLICE_141:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[0] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18
-   Load Comps: fifo_colector_inst/SLICE_126:I1, fifo_colector_inst/SLICE_126:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[1] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19
-   Load Comps: fifo_colector_inst/SLICE_127:I1, fifo_colector_inst/SLICE_127:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[2] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20
-   Load Comps: fifo_colector_inst/SLICE_128:I1, fifo_colector_inst/SLICE_128:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[3] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21
-   Load Comps: fifo_colector_inst/SLICE_129:I1, fifo_colector_inst/SLICE_129:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[4] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22
-   Load Comps: fifo_colector_inst/SLICE_130:I1, fifo_colector_inst/SLICE_130:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[5] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23
-   Load Comps: fifo_colector_inst/SLICE_131:I1, fifo_colector_inst/SLICE_131:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[6] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24
-   Load Comps: fifo_colector_inst/SLICE_132:I1, fifo_colector_inst/SLICE_132:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[7] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25
-   Load Comps: fifo_colector_inst/SLICE_133:I1, fifo_colector_inst/SLICE_133:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[8] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26
-   Load Comps: fifo_colector_inst/SLICE_134:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[9] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27
-   Load Comps: fifo_colector_inst/SLICE_134:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[10] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28
-   Load Comps: fifo_colector_inst/SLICE_135:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[11] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29
-   Load Comps: fifo_colector_inst/SLICE_135:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[12] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30
-   Load Comps: fifo_colector_inst/SLICE_136:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[13] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31
-   Load Comps: fifo_colector_inst/SLICE_136:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[14] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32
-   Load Comps: fifo_colector_inst/SLICE_137:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[15] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33
-   Load Comps: fifo_colector_inst/SLICE_137:I7
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[16] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34
-   Load Comps: fifo_colector_inst/SLICE_138:I1
-Signal genblk1[0].un1_tdc_channel_fifo_out_inst[17] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35
-   Load Comps: fifo_colector_inst/SLICE_138:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I6,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O1
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I13
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I12
-Signal fifo_empty1_c - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O3
-   Load Comps: fifo_colector_inst/SLICE_125:I1, fifo_colector_inst/SLICE_680:I7,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I1,
-        fifo_empty1:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:O6
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I17
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I0
-Signal fifo_read[0] - Driver Comp: fifo_colector_inst/SLICE_189:O3
-   Load Comps: fifo_colector_inst/SLICE_189:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I12
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i -
-     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I16
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I1,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I7
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I2,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I8
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I3,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I9
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I0,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I6
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I0
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I1
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 -
-     Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:O2
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I3
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I4
-Signal trig_c_i[0] - Driver Comp: SLICE_744:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I5,
-        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I5
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O4
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver
-     Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O3
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I4
-Signal genblk1[0].tdc_channel_fifo_out_inst/fb_0 - Driver Comp:
-     genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O0
-   Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I12
-Signal fifo_colector_inst/data_buffer_3[31] - Driver Comp:
-     fifo_colector_inst/SLICE_145:O1
-   Load Comps: fifo_colector_inst/SLICE_145:I13
-Signal fifo_colector_inst/in_empty_pmux_i - Driver Comp:
-     fifo_colector_inst/SLICE_125:O2
-   Load Comps: fifo_colector_inst/SLICE_125:I12,
-        fifo_colector_inst/SLICE_126:I14, fifo_colector_inst/SLICE_127:I14,
-        fifo_colector_inst/SLICE_128:I14, fifo_colector_inst/SLICE_129:I14,
-        fifo_colector_inst/SLICE_130:I14, fifo_colector_inst/SLICE_131:I14,
-        fifo_colector_inst/SLICE_132:I14, fifo_colector_inst/SLICE_133:I14,
-        fifo_colector_inst/SLICE_134:I14, fifo_colector_inst/SLICE_135:I14,
-        fifo_colector_inst/SLICE_136:I14, fifo_colector_inst/SLICE_137:I14,
-        fifo_colector_inst/SLICE_138:I14, fifo_colector_inst/SLICE_139:I14,
-        fifo_colector_inst/SLICE_140:I14, fifo_colector_inst/SLICE_141:I14,
-        fifo_colector_inst/SLICE_142:I14, fifo_colector_inst/SLICE_143:I14,
-        fifo_colector_inst/SLICE_144:I14, fifo_colector_inst/SLICE_145:I14,
-        fifo_colector_inst/SLICE_146:I14
-Signal fifo_colector_inst/iterator_RNI7U5I[1] - Driver Comp:
-     fifo_colector_inst/SLICE_722:O0
-   Load Comps: fifo_colector_inst/SLICE_134:I16,
-        fifo_colector_inst/SLICE_135:I16, fifo_colector_inst/SLICE_136:I16,
-        fifo_colector_inst/SLICE_137:I16, fifo_colector_inst/SLICE_138:I16,
-        fifo_colector_inst/SLICE_139:I16, fifo_colector_inst/SLICE_140:I16,
-        fifo_colector_inst/SLICE_141:I16, fifo_colector_inst/SLICE_142:I16,
-        fifo_colector_inst/SLICE_143:I16, fifo_colector_inst/SLICE_144:I16,
-        fifo_colector_inst/SLICE_145:I16
-Signal fifo_colector_inst/data_buffer[31] - Driver Comp:
-     fifo_colector_inst/SLICE_145:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI31
-Signal fifo_colector_inst/data_buffer[0] - Driver Comp:
-     fifo_colector_inst/SLICE_126:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI0
-Signal fifo_colector_inst/data_buffer[1] - Driver Comp:
-     fifo_colector_inst/SLICE_127:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI1
-Signal fifo_colector_inst/data_buffer[2] - Driver Comp:
-     fifo_colector_inst/SLICE_128:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI2
-Signal fifo_colector_inst/data_buffer[3] - Driver Comp:
-     fifo_colector_inst/SLICE_129:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI3
-Signal fifo_colector_inst/data_buffer[4] - Driver Comp:
-     fifo_colector_inst/SLICE_130:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI4
-Signal fifo_colector_inst/data_buffer[5] - Driver Comp:
-     fifo_colector_inst/SLICE_131:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI5
-Signal fifo_colector_inst/data_buffer[6] - Driver Comp:
-     fifo_colector_inst/SLICE_132:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI6
-Signal fifo_colector_inst/data_buffer[7] - Driver Comp:
-     fifo_colector_inst/SLICE_133:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI7
-Signal fifo_colector_inst/data_buffer[8] - Driver Comp:
-     fifo_colector_inst/SLICE_134:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI8
-Signal fifo_colector_inst/data_buffer[9] - Driver Comp:
-     fifo_colector_inst/SLICE_134:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI9
-Signal fifo_colector_inst/data_buffer[10] - Driver Comp:
-     fifo_colector_inst/SLICE_135:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI10
-Signal fifo_colector_inst/data_buffer[11] - Driver Comp:
-     fifo_colector_inst/SLICE_135:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI11
-Signal fifo_colector_inst/data_buffer[12] - Driver Comp:
-     fifo_colector_inst/SLICE_136:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI12
-Signal fifo_colector_inst/data_buffer[13] - Driver Comp:
-     fifo_colector_inst/SLICE_136:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI13
-Signal fifo_colector_inst/data_buffer[14] - Driver Comp:
-     fifo_colector_inst/SLICE_137:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI14
-Signal fifo_colector_inst/data_buffer[15] - Driver Comp:
-     fifo_colector_inst/SLICE_137:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI15
-Signal fifo_colector_inst/data_buffer[16] - Driver Comp:
-     fifo_colector_inst/SLICE_138:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI16
-Signal fifo_colector_inst/data_buffer[17] - Driver Comp:
-     fifo_colector_inst/SLICE_138:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI17
-Signal fifo_colector_inst/data_buffer[18] - Driver Comp:
-     fifo_colector_inst/SLICE_139:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI18
-Signal fifo_colector_inst/data_buffer[19] - Driver Comp:
-     fifo_colector_inst/SLICE_139:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI19
-Signal fifo_colector_inst/data_buffer[20] - Driver Comp:
-     fifo_colector_inst/SLICE_140:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI20
-Signal fifo_colector_inst/data_buffer[21] - Driver Comp:
-     fifo_colector_inst/SLICE_140:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI21
-Signal fifo_colector_inst/data_buffer[22] - Driver Comp:
-     fifo_colector_inst/SLICE_141:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI22
-Signal fifo_colector_inst/data_buffer[23] - Driver Comp:
-     fifo_colector_inst/SLICE_141:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI23
-Signal fifo_colector_inst/data_buffer[24] - Driver Comp:
-     fifo_colector_inst/SLICE_142:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI24
-Signal fifo_colector_inst/data_buffer[25] - Driver Comp:
-     fifo_colector_inst/SLICE_142:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI25
-Signal fifo_colector_inst/data_buffer[26] - Driver Comp:
-     fifo_colector_inst/SLICE_143:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI26
-Signal fifo_colector_inst/data_buffer[27] - Driver Comp:
-     fifo_colector_inst/SLICE_143:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI27
-Signal fifo_colector_inst/data_buffer[28] - Driver Comp:
-     fifo_colector_inst/SLICE_144:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI28
-Signal fifo_colector_inst/data_buffer[29] - Driver Comp:
-     fifo_colector_inst/SLICE_144:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI29
-Signal fifo_colector_inst/data_buffer[30] - Driver Comp:
-     fifo_colector_inst/SLICE_145:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI30
-Signal fifo_colector_inst/data_buffer[32] - Driver Comp:
-     fifo_colector_inst/SLICE_146:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI32
-Signal fifo_colector_inst/data_buffer[33] - Driver Comp:
-     fifo_colector_inst/SLICE_146:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI33
-Signal fifo_colector_inst/fifo40_inst/wptr_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_182:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW0
-Signal fifo_colector_inst/fifo40_inst/wptr_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_182:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW1
-Signal fifo_colector_inst/fifo40_inst/wptr_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_183:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW2
-Signal fifo_colector_inst/fifo40_inst/wptr_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_183:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW3
-Signal fifo_colector_inst/fifo40_inst/wptr_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_184:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW4
-Signal fifo_colector_inst/fifo40_inst/wptr_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_184:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW5
-Signal fifo_colector_inst/fifo40_inst/wptr_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_185:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW6
-Signal fifo_colector_inst/fifo40_inst/wptr_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_185:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW7
-Signal fifo_colector_inst/fifo40_inst/wptr_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_186:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW8
-Signal fifo_colector_inst/fifo40_inst/wren_i - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_721:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_80:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_81:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_82:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_83:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_97:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_97:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_171:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_182:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_183:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_184:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_185:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_186:I14,
-        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CEW
-Signal fifo_colector_inst/fifo40_inst/rptr_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_162:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR5
-Signal fifo_colector_inst/fifo40_inst/rptr_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_162:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR6
-Signal fifo_colector_inst/fifo40_inst/rptr_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_163:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR7
-Signal fifo_colector_inst/fifo40_inst/rptr_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_163:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR8
-Signal fifo_colector_inst/fifo40_inst/rptr_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_164:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR9
-Signal fifo_colector_inst/fifo40_inst/rptr_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_164:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR10
-Signal fifo_colector_inst/fifo40_inst/rptr_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_165:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR11
-Signal fifo_colector_inst/fifo40_inst/rptr_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_165:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR12
-Signal fifo_colector_inst/fifo40_inst/rptr_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_166:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR13
-Signal fifo_colector_inst/fifo40_inst/rden_i - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_720:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_86:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_87:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_88:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_89:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_90:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_90:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_151:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_162:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_163:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_164:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_165:I14,
-        fifo_colector_inst/fifo40_inst/SLICE_166:I14,
-        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CER,
-        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:OCER
-Signal rd_clk_c - Driver Comp: rd_clk:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_86:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_87:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_88:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_89:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_96:I15,
-        trb_adapter_inst/SLICE_124:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_151:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_162:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_163:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_164:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_165:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_166:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_172:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_173:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_174:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_175:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_176:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_177:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_178:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_179:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_180:I15,
-        fifo_colector_inst/fifo40_inst/SLICE_181:I15,
-        trb_adapter_inst/SLICE_188:I15, trb_adapter_inst/SLICE_631:I15,
-        trb_adapter_inst/SLICE_632:I15, trb_adapter_inst/SLICE_633:I15,
-        trb_adapter_inst/SLICE_724:I15, FEE_TRG_RELEASE_OUT_MGIOL:I6,
-        FEE_DATAFINISHED_OUT_MGIOL:I6, FEE_DATA_WRITE_OUT_MGIOL:I6,
-        LVL1_INVALID_TRG_IN_MGIOL:I6, LVL1_TRG_DATA_VALID_IN_MGIOL:I6,
-        fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKR
-Signal FEE_DATA_OUT_c[18] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO0
-   Load Comps: FEE_DATA_OUT[18]:I0, fifo_data_out[18]:I0
-Signal FEE_DATA_OUT_c[19] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO1
-   Load Comps: FEE_DATA_OUT[19]:I0, fifo_data_out[19]:I0
-Signal FEE_DATA_OUT_c[20] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO2
-   Load Comps: FEE_DATA_OUT[20]:I0, fifo_data_out[20]:I0
-Signal FEE_DATA_OUT_c[21] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO3
-   Load Comps: FEE_DATA_OUT[21]:I0, fifo_data_out[21]:I0
-Signal FEE_DATA_OUT_c[22] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO4
-   Load Comps: FEE_DATA_OUT[22]:I0, fifo_data_out[22]:I0
-Signal FEE_DATA_OUT_c[23] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO5
-   Load Comps: FEE_DATA_OUT[23]:I0, fifo_data_out[23]:I0
-Signal FEE_DATA_OUT_c[24] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO6
-   Load Comps: FEE_DATA_OUT[24]:I0, fifo_data_out[24]:I0
-Signal FEE_DATA_OUT_c[25] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO7
-   Load Comps: FEE_DATA_OUT[25]:I0, fifo_data_out[25]:I0
-Signal FEE_DATA_OUT_c[26] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO8
-   Load Comps: FEE_DATA_OUT[26]:I0, fifo_data_out[26]:I0
-Signal FEE_DATA_OUT_c[27] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO9
-   Load Comps: FEE_DATA_OUT[27]:I0, fifo_data_out[27]:I0
-Signal FEE_DATA_OUT_c[28] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO10
-   Load Comps: FEE_DATA_OUT[28]:I0, fifo_data_out[28]:I0
-Signal FEE_DATA_OUT_c[29] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO11
-   Load Comps: FEE_DATA_OUT[29]:I0, fifo_data_out[29]:I0
-Signal FEE_DATA_OUT_c[30] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO12
-   Load Comps: FEE_DATA_OUT[30]:I0, fifo_data_out[30]:I0
-Signal FEE_DATA_OUT_c[31] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO13
-   Load Comps: FEE_DATA_OUT[31]:I0, fifo_data_out[31]:I0
-Signal FEE_DATA_OUT_c[1] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO19
-   Load Comps: FEE_DATA_OUT[1]:I0, fifo_data_out[1]:I0
-Signal FEE_DATA_OUT_c[2] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO20
-   Load Comps: FEE_DATA_OUT[2]:I0, fifo_data_out[2]:I0
-Signal FEE_DATA_OUT_c[3] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO21
-   Load Comps: FEE_DATA_OUT[3]:I0, fifo_data_out[3]:I0
-Signal FEE_DATA_OUT_c[4] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO22
-   Load Comps: FEE_DATA_OUT[4]:I0, fifo_data_out[4]:I0
-Signal FEE_DATA_OUT_c[5] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO23
-   Load Comps: FEE_DATA_OUT[5]:I0, fifo_data_out[5]:I0
-Signal FEE_DATA_OUT_c[6] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO24
-   Load Comps: FEE_DATA_OUT[6]:I0, fifo_data_out[6]:I0
-Signal FEE_DATA_OUT_c[7] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO25
-   Load Comps: FEE_DATA_OUT[7]:I0, fifo_data_out[7]:I0
-Signal FEE_DATA_OUT_c[8] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO26
-   Load Comps: FEE_DATA_OUT[8]:I0, fifo_data_out[8]:I0
-Signal FEE_DATA_OUT_c[9] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO27
-   Load Comps: FEE_DATA_OUT[9]:I0, fifo_data_out[9]:I0
-Signal FEE_DATA_OUT_c[10] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO28
-   Load Comps: FEE_DATA_OUT[10]:I0, fifo_data_out[10]:I0
-Signal FEE_DATA_OUT_c[11] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO29
-   Load Comps: FEE_DATA_OUT[11]:I0, fifo_data_out[11]:I0
-Signal FEE_DATA_OUT_c[12] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO30
-   Load Comps: FEE_DATA_OUT[12]:I0, fifo_data_out[12]:I0
-Signal FEE_DATA_OUT_c[13] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO31
-   Load Comps: FEE_DATA_OUT[13]:I0, fifo_data_out[13]:I0
-Signal FEE_DATA_OUT_c[14] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO32
-   Load Comps: FEE_DATA_OUT[14]:I0, fifo_data_out[14]:I0
-Signal FEE_DATA_OUT_c[15] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO33
-   Load Comps: FEE_DATA_OUT[15]:I0, fifo_data_out[15]:I0
-Signal FEE_DATA_OUT_c[16] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO34
-   Load Comps: FEE_DATA_OUT[16]:I0, fifo_data_out[16]:I0
-Signal FEE_DATA_OUT_c[17] - Driver Comp:
-     fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO35
-   Load Comps: FEE_DATA_OUT[17]:I0, fifo_data_out[17]:I0
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w29 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_161:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_648:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_691:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_691:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I6
-Signal fifo_colector_inst/fifo40_inst/wcount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_83:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_171:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_171:I5,
-        fifo_colector_inst/fifo40_inst/SLICE_186:I5,
-        fifo_colector_inst/fifo40_inst/SLICE_691:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_691:I7
-Signal fifo_colector_inst/fifo40_inst/wptr_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_186:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_691:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_691:I8
-Signal fifo_colector_inst/fifo40_inst/full_cmp_clr - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_691:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I7
-Signal fifo_colector_inst/fifo40_inst/full_d - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_103:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I12
-Signal fifo_colector_inst/fifo40_inst/Full - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_103:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I1
-Signal fifo_colector_inst/fifo40_inst/empty_d - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_96:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I12
-Signal last_buf_empty_c - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_96:O3
-   Load Comps: trb_adapter_inst/SLICE_188:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_720:I1, last_buf_empty:I0
-Signal fifo_colector_inst/fifo40_inst/rcount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_89:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_151:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_151:I5,
-        fifo_colector_inst/fifo40_inst/SLICE_166:I5,
-        fifo_colector_inst/fifo40_inst/SLICE_692:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_692:I7
-Signal fifo_colector_inst/fifo40_inst/rptr_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_166:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_692:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_692:I8
-Signal fifo_colector_inst/fifo40_inst/ircount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_85:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I12
-Signal fifo_colector_inst/fifo40_inst/rcount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_85:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_91:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_162:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r29 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_181:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_692:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_692:I6
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r28 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_181:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I1
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r27 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_180:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I2
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r26 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_180:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I3,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I7
-Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_673:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_673:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_674:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I6
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r25 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_179:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I7
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r24 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_179:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I8
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r23 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_178:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I9
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r22 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_178:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I3
-Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_674:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_674:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_702:I0
-Signal fifo_colector_inst/fifo40_inst/wcount_r8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_675:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_675:I6
-Signal fifo_colector_inst/fifo40_inst/wcount_r7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_676:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_676:I6
-Signal fifo_colector_inst/fifo40_inst/wcount_r5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_675:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I7
-Signal fifo_colector_inst/fifo40_inst/wcount_r4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_676:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I1
-Signal fifo_colector_inst/fifo40_inst/wcount_r3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_702:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I7
-Signal fifo_colector_inst/fifo40_inst/wcount_r2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_702:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I1
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r21 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_177:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_674:I6
-Signal fifo_colector_inst/fifo40_inst/wcount_r1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_674:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I7
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r20 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_177:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I7
-Signal fifo_colector_inst/fifo40_inst/wcount_r0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_673:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I1
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w28 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_161:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_648:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I7
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w27 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_160:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_648:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I2
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w26 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_160:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I3,
-        fifo_colector_inst/fifo40_inst/SLICE_648:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I3,
-        fifo_colector_inst/fifo40_inst/SLICE_649:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I3,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I7
-Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_677:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_678:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I0
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w25 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_159:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_649:I4,
-        fifo_colector_inst/fifo40_inst/SLICE_678:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I1
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w24 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_159:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I9,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I2
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w23 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_158:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I2,
-        fifo_colector_inst/fifo40_inst/SLICE_703:I3
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w22 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_158:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I3
-Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_678:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I4,
-        fifo_colector_inst/fifo40_inst/SLICE_677:I8,
-        fifo_colector_inst/fifo40_inst/SLICE_678:I7
-Signal fifo_colector_inst/fifo40_inst/rcount_w8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_703:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I1
-Signal fifo_colector_inst/fifo40_inst/rcount_w7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_679:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_679:I6
-Signal fifo_colector_inst/fifo40_inst/rcount_w5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_649:O2
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I7
-Signal fifo_colector_inst/fifo40_inst/rcount_w4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_679:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I1
-Signal fifo_colector_inst/fifo40_inst/rcount_w3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_703:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I7
-Signal fifo_colector_inst/fifo40_inst/rcount_w2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_648:O2
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I1
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w21 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_157:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_678:I6
-Signal fifo_colector_inst/fifo40_inst/rcount_w1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_678:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I7
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w20 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_157:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I7
-Signal fifo_colector_inst/fifo40_inst/rcount_w0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_677:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I1
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_set - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_692:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I6
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_clr - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_692:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I7
-Signal fifo_colector_inst/fifo40_inst/full_cmp_set - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_691:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I6
-Signal fifo_colector_inst/fifo40_inst/iwcount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_79:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I12
-Signal fifo_colector_inst/fifo40_inst/wcount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_79:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_98:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_182:I4
-Signal fifo_colector_inst/fifo40_inst/iwcount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_79:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I13
-Signal fifo_colector_inst/fifo40_inst/wcount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_79:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_98:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_182:I5
-Signal fifo_colector_inst/fifo40_inst/iwcount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_80:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I12
-Signal fifo_colector_inst/fifo40_inst/wcount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_80:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_99:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_167:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_183:I4
-Signal fifo_colector_inst/fifo40_inst/iwcount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_80:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I13
-Signal fifo_colector_inst/fifo40_inst/wcount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_80:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_99:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_183:I5
-Signal fifo_colector_inst/fifo40_inst/iwcount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_81:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I12
-Signal fifo_colector_inst/fifo40_inst/wcount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_81:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_100:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_168:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_184:I4
-Signal fifo_colector_inst/fifo40_inst/iwcount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_81:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I13
-Signal fifo_colector_inst/fifo40_inst/wcount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_81:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_100:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_184:I5
-Signal fifo_colector_inst/fifo40_inst/iwcount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_82:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I12
-Signal fifo_colector_inst/fifo40_inst/wcount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_82:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_101:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_169:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_185:I4
-Signal fifo_colector_inst/fifo40_inst/iwcount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_82:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I13
-Signal fifo_colector_inst/fifo40_inst/wcount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_82:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_101:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_185:I5
-Signal fifo_colector_inst/fifo40_inst/iwcount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_83:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I12
-Signal fifo_colector_inst/fifo40_inst/wcount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_83:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_102:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_170:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_171:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_186:I4
-Signal fifo_colector_inst/fifo40_inst/iwcount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_83:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I13
-Signal fifo_colector_inst/fifo40_inst/w_gdata_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_167:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I12
-Signal fifo_colector_inst/fifo40_inst/w_gcount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_167:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I4
-Signal fifo_colector_inst/fifo40_inst/w_gdata_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_167:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I13
-Signal fifo_colector_inst/fifo40_inst/w_gcount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_167:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I5
-Signal fifo_colector_inst/fifo40_inst/w_gdata_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_168:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I12
-Signal fifo_colector_inst/fifo40_inst/w_gcount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_168:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I4
-Signal fifo_colector_inst/fifo40_inst/w_gdata_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_168:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I13
-Signal fifo_colector_inst/fifo40_inst/w_gcount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_168:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I5
-Signal fifo_colector_inst/fifo40_inst/w_gdata_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_169:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I12
-Signal fifo_colector_inst/fifo40_inst/w_gcount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_169:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I4
-Signal fifo_colector_inst/fifo40_inst/w_gdata_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_169:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I13
-Signal fifo_colector_inst/fifo40_inst/w_gcount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_169:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I5
-Signal fifo_colector_inst/fifo40_inst/w_gdata_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_170:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I12
-Signal fifo_colector_inst/fifo40_inst/w_gcount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_170:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I4
-Signal fifo_colector_inst/fifo40_inst/w_gdata_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_170:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I13
-Signal fifo_colector_inst/fifo40_inst/w_gcount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_170:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I5
-Signal fifo_colector_inst/fifo40_inst/w_gdata_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_171:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_171:I12
-Signal fifo_colector_inst/fifo40_inst/w_gcount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_171:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_171:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I5
-Signal fifo_colector_inst/fifo40_inst/ircount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_85:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I13
-Signal fifo_colector_inst/fifo40_inst/rcount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_85:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_91:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_162:I5
-Signal fifo_colector_inst/fifo40_inst/ircount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_86:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I12
-Signal fifo_colector_inst/fifo40_inst/rcount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_86:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_92:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_147:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_163:I4
-Signal fifo_colector_inst/fifo40_inst/ircount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_86:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I13
-Signal fifo_colector_inst/fifo40_inst/rcount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_86:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_92:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_163:I5
-Signal fifo_colector_inst/fifo40_inst/ircount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_87:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I12
-Signal fifo_colector_inst/fifo40_inst/rcount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_87:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_93:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_148:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_164:I4
-Signal fifo_colector_inst/fifo40_inst/ircount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_87:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I13
-Signal fifo_colector_inst/fifo40_inst/rcount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_87:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_93:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_164:I5
-Signal fifo_colector_inst/fifo40_inst/ircount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_88:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I12
-Signal fifo_colector_inst/fifo40_inst/rcount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_88:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_94:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_149:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_165:I4
-Signal fifo_colector_inst/fifo40_inst/ircount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_88:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I13
-Signal fifo_colector_inst/fifo40_inst/rcount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_88:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_94:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I1,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I6,
-        fifo_colector_inst/fifo40_inst/SLICE_165:I5
-Signal fifo_colector_inst/fifo40_inst/ircount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_89:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I12
-Signal fifo_colector_inst/fifo40_inst/rcount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_89:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_95:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_150:I7,
-        fifo_colector_inst/fifo40_inst/SLICE_151:I0,
-        fifo_colector_inst/fifo40_inst/SLICE_166:I4
-Signal fifo_colector_inst/fifo40_inst/ircount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_89:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I13
-Signal fifo_colector_inst/fifo40_inst/r_gdata_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_147:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I12
-Signal fifo_colector_inst/fifo40_inst/r_gcount_0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_147:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I4
-Signal fifo_colector_inst/fifo40_inst/r_gdata_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_147:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I13
-Signal fifo_colector_inst/fifo40_inst/r_gcount_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_147:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I5
-Signal fifo_colector_inst/fifo40_inst/r_gdata_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_148:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I12
-Signal fifo_colector_inst/fifo40_inst/r_gcount_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_148:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I4
-Signal fifo_colector_inst/fifo40_inst/r_gdata_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_148:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I13
-Signal fifo_colector_inst/fifo40_inst/r_gcount_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_148:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I5
-Signal fifo_colector_inst/fifo40_inst/r_gdata_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_149:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I12
-Signal fifo_colector_inst/fifo40_inst/r_gcount_4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_149:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I4
-Signal fifo_colector_inst/fifo40_inst/r_gdata_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_149:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I13
-Signal fifo_colector_inst/fifo40_inst/r_gcount_5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_149:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I5
-Signal fifo_colector_inst/fifo40_inst/r_gdata_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_150:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I12
-Signal fifo_colector_inst/fifo40_inst/r_gcount_6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_150:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I4
-Signal fifo_colector_inst/fifo40_inst/r_gdata_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_150:O1
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I13
-Signal fifo_colector_inst/fifo40_inst/r_gcount_7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_150:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I5
-Signal fifo_colector_inst/fifo40_inst/r_gdata_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_151:O0
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_151:I12
-Signal fifo_colector_inst/fifo40_inst/r_gcount_8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_151:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_151:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I5
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_172:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_172:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I5
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_173:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_173:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I5
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_174:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_174:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I5
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_175:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_175:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I5
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_176:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I4
-Signal fifo_colector_inst/fifo40_inst/w_gcount_r9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_176:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I5
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_152:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_152:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I5
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_153:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_153:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I5
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w4 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_154:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w5 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_154:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I5
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w6 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_155:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w7 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_155:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I5
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w8 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_156:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I4
-Signal fifo_colector_inst/fifo40_inst/r_gcount_w9 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_156:O4
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I5
-Signal fifo_colector_inst/fifo40_inst/w_gctr_ci - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_78:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I17
-Signal fifo_colector_inst/fifo40_inst/co0 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_79:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I17
-Signal fifo_colector_inst/fifo40_inst/co1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_80:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I17
-Signal fifo_colector_inst/fifo40_inst/co2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_81:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I17
-Signal fifo_colector_inst/fifo40_inst/co3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_82:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I17
-Signal fifo_colector_inst/fifo40_inst/r_gctr_ci - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_84:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I17
-Signal fifo_colector_inst/fifo40_inst/co0_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_85:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I17
-Signal fifo_colector_inst/fifo40_inst/co1_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_86:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I17
-Signal fifo_colector_inst/fifo40_inst/co2_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_87:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I17
-Signal fifo_colector_inst/fifo40_inst/co3_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_88:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I17
-Signal fifo_colector_inst/fifo40_inst/cmp_ci - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_90:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I17
-Signal fifo_colector_inst/fifo40_inst/co0_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_91:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I17
-Signal fifo_colector_inst/fifo40_inst/co1_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_92:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I17
-Signal fifo_colector_inst/fifo40_inst/co2_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_93:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I17
-Signal fifo_colector_inst/fifo40_inst/co3_2 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_94:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I17
-Signal fifo_colector_inst/fifo40_inst/empty_d_c - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_95:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I17
-Signal fifo_colector_inst/fifo40_inst/cmp_ci_1 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_97:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I17
-Signal fifo_colector_inst/fifo40_inst/co0_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_98:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I17
-Signal fifo_colector_inst/fifo40_inst/co1_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_99:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I17
-Signal fifo_colector_inst/fifo40_inst/co2_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_100:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I17
-Signal fifo_colector_inst/fifo40_inst/co3_3 - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_101:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I17
-Signal fifo_colector_inst/fifo40_inst/full_d_c - Driver Comp:
-     fifo_colector_inst/fifo40_inst/SLICE_102:O6
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I17
-Signal fifo_rden_c - Driver Comp: trb_adapter_inst/SLICE_188:O3
-   Load Comps: trb_adapter_inst/SLICE_188:I1, trb_adapter_inst/SLICE_632:I4,
-        fifo_colector_inst/fifo40_inst/SLICE_720:I0,
-        trb_adapter_inst/SLICE_724:I16, FEE_DATA_WRITE_OUT_MGIOL:I10,
-        fifo_rden:I0
-Signal fifo_colector_inst/buffer_wr_enable - Driver Comp:
-     fifo_colector_inst/SLICE_125:O3
-   Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I0
-Signal fifo_colector_inst/iterator[1] - Driver Comp:
-     fifo_colector_inst/SLICE_187:O4
-   Load Comps: fifo_colector_inst/SLICE_125:I4, fifo_colector_inst/SLICE_126:I3,
-        fifo_colector_inst/SLICE_126:I9, fifo_colector_inst/SLICE_127:I3,
-        fifo_colector_inst/SLICE_127:I9, fifo_colector_inst/SLICE_128:I3,
-        fifo_colector_inst/SLICE_128:I9, fifo_colector_inst/SLICE_129:I3,
-        fifo_colector_inst/SLICE_129:I9, fifo_colector_inst/SLICE_130:I3,
-        fifo_colector_inst/SLICE_130:I9, fifo_colector_inst/SLICE_131:I3,
-        fifo_colector_inst/SLICE_131:I9, fifo_colector_inst/SLICE_132:I3,
-        fifo_colector_inst/SLICE_132:I9, fifo_colector_inst/SLICE_133:I3,
-        fifo_colector_inst/SLICE_133:I9, fifo_colector_inst/SLICE_146:I5,
-        fifo_colector_inst/SLICE_187:I1, fifo_colector_inst/SLICE_189:I1,
-        fifo_colector_inst/SLICE_190:I0, fifo_colector_inst/SLICE_680:I1,
-        fifo_colector_inst/SLICE_722:I0
-Signal fifo_colector_inst/iterator[0] - Driver Comp:
-     fifo_colector_inst/SLICE_187:O3
-   Load Comps: fifo_colector_inst/SLICE_125:I0, fifo_colector_inst/SLICE_126:I0,
-        fifo_colector_inst/SLICE_126:I6, fifo_colector_inst/SLICE_127:I0,
-        fifo_colector_inst/SLICE_127:I6, fifo_colector_inst/SLICE_128:I0,
-        fifo_colector_inst/SLICE_128:I6, fifo_colector_inst/SLICE_129:I0,
-        fifo_colector_inst/SLICE_129:I6, fifo_colector_inst/SLICE_130:I0,
-        fifo_colector_inst/SLICE_130:I6, fifo_colector_inst/SLICE_131:I0,
-        fifo_colector_inst/SLICE_131:I6, fifo_colector_inst/SLICE_132:I0,
-        fifo_colector_inst/SLICE_132:I6, fifo_colector_inst/SLICE_133:I0,
-        fifo_colector_inst/SLICE_133:I6, fifo_colector_inst/SLICE_134:I0,
-        fifo_colector_inst/SLICE_134:I6, fifo_colector_inst/SLICE_135:I0,
-        fifo_colector_inst/SLICE_135:I6, fifo_colector_inst/SLICE_136:I0,
-        fifo_colector_inst/SLICE_136:I6, fifo_colector_inst/SLICE_137:I0,
-        fifo_colector_inst/SLICE_137:I6, fifo_colector_inst/SLICE_138:I0,
-        fifo_colector_inst/SLICE_138:I6, fifo_colector_inst/SLICE_139:I0,
-        fifo_colector_inst/SLICE_139:I6, fifo_colector_inst/SLICE_140:I0,
-        fifo_colector_inst/SLICE_140:I6, fifo_colector_inst/SLICE_141:I0,
-        fifo_colector_inst/SLICE_141:I6, fifo_colector_inst/SLICE_142:I0,
-        fifo_colector_inst/SLICE_142:I6, fifo_colector_inst/SLICE_143:I0,
-        fifo_colector_inst/SLICE_143:I6, fifo_colector_inst/SLICE_144:I0,
-        fifo_colector_inst/SLICE_144:I6, fifo_colector_inst/SLICE_145:I0,
-        fifo_colector_inst/SLICE_145:I6, fifo_colector_inst/SLICE_146:I4,
-        fifo_colector_inst/SLICE_187:I0, fifo_colector_inst/SLICE_187:I5,
-        fifo_colector_inst/SLICE_189:I2, fifo_colector_inst/SLICE_189:I6,
-        fifo_colector_inst/SLICE_680:I6
-Signal fifo_colector_inst/fb_0 - Driver Comp: fifo_colector_inst/SLICE_189:O0
-   Load Comps: fifo_colector_inst/SLICE_189:I12
-Signal fifo_colector_inst/in_empty_pmux_0 - Driver Comp:
-     fifo_colector_inst/SLICE_680:O1
-   Load Comps: fifo_colector_inst/SLICE_680:I0
-Signal fifo_colector_inst/fb_0_0 - Driver Comp: fifo_colector_inst/SLICE_190:O0
-   Load Comps: fifo_colector_inst/SLICE_190:I12
-Signal fifo_colector_inst/fb_0_1 - Driver Comp: fifo_colector_inst/SLICE_189:O1
-   Load Comps: fifo_colector_inst/SLICE_189:I13
-Signal fifo_colector_inst/un5_in_read_enable - Driver Comp:
-     fifo_colector_inst/SLICE_187:O0
-   Load Comps: fifo_colector_inst/SLICE_187:I12
-Signal fifo_colector_inst/in_empty_pmux - Driver Comp:
-     fifo_colector_inst/SLICE_680:O0
-   Load Comps: fifo_colector_inst/SLICE_189:I16,
-        fifo_colector_inst/SLICE_190:I16
-Signal fifo_colector_inst/data_buffer_3[0] - Driver Comp:
-     fifo_colector_inst/SLICE_126:O2
-   Load Comps: fifo_colector_inst/SLICE_126:I12
-Signal fifo_colector_inst/data_buffer_3[1] - Driver Comp:
-     fifo_colector_inst/SLICE_127:O2
-   Load Comps: fifo_colector_inst/SLICE_127:I12
-Signal fifo_colector_inst/data_buffer_3[2] - Driver Comp:
-     fifo_colector_inst/SLICE_128:O2
-   Load Comps: fifo_colector_inst/SLICE_128:I12
-Signal fifo_colector_inst/data_buffer_3[3] - Driver Comp:
-     fifo_colector_inst/SLICE_129:O2
-   Load Comps: fifo_colector_inst/SLICE_129:I12
-Signal fifo_colector_inst/data_buffer_3[4] - Driver Comp:
-     fifo_colector_inst/SLICE_130:O2
-   Load Comps: fifo_colector_inst/SLICE_130:I12
-Signal fifo_colector_inst/data_buffer_3[5] - Driver Comp:
-     fifo_colector_inst/SLICE_131:O2
-   Load Comps: fifo_colector_inst/SLICE_131:I12
-Signal fifo_colector_inst/data_buffer_3[6] - Driver Comp:
-     fifo_colector_inst/SLICE_132:O2
-   Load Comps: fifo_colector_inst/SLICE_132:I12
-Signal fifo_colector_inst/data_buffer_3[7] - Driver Comp:
-     fifo_colector_inst/SLICE_133:O2
-   Load Comps: fifo_colector_inst/SLICE_133:I12
-Signal fifo_colector_inst/data_buffer_3[8] - Driver Comp:
-     fifo_colector_inst/SLICE_134:O0
-   Load Comps: fifo_colector_inst/SLICE_134:I12
-Signal fifo_colector_inst/data_buffer_3[9] - Driver Comp:
-     fifo_colector_inst/SLICE_134:O1
-   Load Comps: fifo_colector_inst/SLICE_134:I13
-Signal fifo_colector_inst/data_buffer_3[10] - Driver Comp:
-     fifo_colector_inst/SLICE_135:O0
-   Load Comps: fifo_colector_inst/SLICE_135:I12
-Signal fifo_colector_inst/data_buffer_3[11] - Driver Comp:
-     fifo_colector_inst/SLICE_135:O1
-   Load Comps: fifo_colector_inst/SLICE_135:I13
-Signal fifo_colector_inst/data_buffer_3[12] - Driver Comp:
-     fifo_colector_inst/SLICE_136:O0
-   Load Comps: fifo_colector_inst/SLICE_136:I12
-Signal fifo_colector_inst/data_buffer_3[13] - Driver Comp:
-     fifo_colector_inst/SLICE_136:O1
-   Load Comps: fifo_colector_inst/SLICE_136:I13
-Signal fifo_colector_inst/data_buffer_3[14] - Driver Comp:
-     fifo_colector_inst/SLICE_137:O0
-   Load Comps: fifo_colector_inst/SLICE_137:I12
-Signal fifo_colector_inst/data_buffer_3[15] - Driver Comp:
-     fifo_colector_inst/SLICE_137:O1
-   Load Comps: fifo_colector_inst/SLICE_137:I13
-Signal fifo_colector_inst/data_buffer_3[16] - Driver Comp:
-     fifo_colector_inst/SLICE_138:O0
-   Load Comps: fifo_colector_inst/SLICE_138:I12
-Signal fifo_colector_inst/data_buffer_3[17] - Driver Comp:
-     fifo_colector_inst/SLICE_138:O1
-   Load Comps: fifo_colector_inst/SLICE_138:I13
-Signal fifo_colector_inst/data_buffer_3[18] - Driver Comp:
-     fifo_colector_inst/SLICE_139:O0
-   Load Comps: fifo_colector_inst/SLICE_139:I12
-Signal fifo_colector_inst/data_buffer_3[19] - Driver Comp:
-     fifo_colector_inst/SLICE_139:O1
-   Load Comps: fifo_colector_inst/SLICE_139:I13
-Signal fifo_colector_inst/data_buffer_3[20] - Driver Comp:
-     fifo_colector_inst/SLICE_140:O0
-   Load Comps: fifo_colector_inst/SLICE_140:I12
-Signal fifo_colector_inst/data_buffer_3[21] - Driver Comp:
-     fifo_colector_inst/SLICE_140:O1
-   Load Comps: fifo_colector_inst/SLICE_140:I13
-Signal fifo_colector_inst/data_buffer_3[22] - Driver Comp:
-     fifo_colector_inst/SLICE_141:O0
-   Load Comps: fifo_colector_inst/SLICE_141:I12
-Signal fifo_colector_inst/data_buffer_3[23] - Driver Comp:
-     fifo_colector_inst/SLICE_141:O1
-   Load Comps: fifo_colector_inst/SLICE_141:I13
-Signal fifo_colector_inst/data_buffer_3[24] - Driver Comp:
-     fifo_colector_inst/SLICE_142:O0
-   Load Comps: fifo_colector_inst/SLICE_142:I12
-Signal fifo_colector_inst/data_buffer_3[25] - Driver Comp:
-     fifo_colector_inst/SLICE_142:O1
-   Load Comps: fifo_colector_inst/SLICE_142:I13
-Signal fifo_colector_inst/data_buffer_3[26] - Driver Comp:
-     fifo_colector_inst/SLICE_143:O0
-   Load Comps: fifo_colector_inst/SLICE_143:I12
-Signal fifo_colector_inst/data_buffer_3[27] - Driver Comp:
-     fifo_colector_inst/SLICE_143:O1
-   Load Comps: fifo_colector_inst/SLICE_143:I13
-Signal fifo_colector_inst/data_buffer_3[28] - Driver Comp:
-     fifo_colector_inst/SLICE_144:O0
-   Load Comps: fifo_colector_inst/SLICE_144:I12
-Signal fifo_colector_inst/data_buffer_3[29] - Driver Comp:
-     fifo_colector_inst/SLICE_144:O1
-   Load Comps: fifo_colector_inst/SLICE_144:I13
-Signal fifo_colector_inst/data_buffer_3[30] - Driver Comp:
-     fifo_colector_inst/SLICE_145:O0
-   Load Comps: fifo_colector_inst/SLICE_145:I12
-Signal finished_c - Driver Comp: trb_adapter_inst/SLICE_724:O3
-   Load Comps: trb_adapter_inst/SLICE_633:I4, trb_adapter_inst/SLICE_724:I0,
-        finished:I0, FEE_DATAFINISHED_OUT_MGIOL:I10
-Signal trb_adapter_inst/finished_prev - Driver Comp:
-     trb_adapter_inst/SLICE_633:O3
-   Load Comps: trb_adapter_inst/SLICE_724:I1
-Signal trb_adapter_inst/buf_rden_prev - Driver Comp:
-     trb_adapter_inst/SLICE_632:O3
-   Load Comps: trb_adapter_inst/SLICE_724:I4
-Signal trb_adapter_inst/buf_rden4 - Driver Comp: trb_adapter_inst/SLICE_188:O0
-   Load Comps: trb_adapter_inst/SLICE_188:I12
-Signal trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - Driver Comp:
-     LVL1_TRG_DATA_VALID_IN_MGIOL:O2
-   Load Comps: trb_adapter_inst/SLICE_631:I4
-Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - Driver Comp:
-     trb_adapter_inst/SLICE_631:O3
-   Load Comps: trb_adapter_inst/SLICE_188:I8, trb_adapter_inst/SLICE_631:I5,
-        trb_adapter_inst/SLICE_723:I0
-Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - Driver Comp:
-     trb_adapter_inst/SLICE_631:O4
-   Load Comps: trb_adapter_inst/SLICE_188:I7, trb_adapter_inst/SLICE_723:I1
-Signal trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - Driver Comp:
-     LVL1_INVALID_TRG_IN_MGIOL:O2
-   Load Comps: trb_adapter_inst/SLICE_124:I4
-Signal discard_c - Driver Comp: trb_adapter_inst/SLICE_124:O3
-   Load Comps: trb_adapter_inst/SLICE_188:I6, discard:I0
-Signal burst_c - Driver Comp: trb_adapter_inst/SLICE_188:O1
-   Load Comps: trb_adapter_inst/SLICE_188:I0, burst:I0
-Signal LVL1_TRG_DATA_VALI_IN_rising_c - Driver Comp:
-     trb_adapter_inst/SLICE_723:O0
-   Load Comps: LVL1_TRG_DATA_VALI_IN_rising:I0
-Signal release_out_c - Driver Comp: trb_adapter_inst/SLICE_724:O0
-   Load Comps: release_out:I0, FEE_TRG_RELEASE_OUT_MGIOL:I10
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_120:O6
-   Load Comps: hades_tdc_bundle_inst/SLICE_104:I17
-Signal hades_tdc_bundle_inst/hit_valid25 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_104:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_456:I2,
-        hades_tdc_bundle_inst/SLICE_458:I1, hades_tdc_bundle_inst/SLICE_458:I7,
-        hades_tdc_bundle_inst/SLICE_710:I7
-Signal hades_tdc_bundle_inst/buf_finished5 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_432:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_432:I12
-Signal hades_buf_finished_c - Driver Comp: hades_tdc_bundle_inst/SLICE_432:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_433:I4, hades_buf_finished:I0
-Signal hades_dbg2_out_c[12] - Driver Comp: hades_tdc_bundle_inst/SLICE_443:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_449:I4, hades_dbg2_out[12]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - Driver Comp: SLICE_740:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_445:I14,
-        hades_tdc_bundle_inst/SLICE_446:I14,
-        hades_tdc_bundle_inst/SLICE_447:I14,
-        hades_tdc_bundle_inst/SLICE_448:I14,
-        hades_tdc_bundle_inst/SLICE_449:I14,
-        hades_tdc_bundle_inst/SLICE_450:I14,
-        hades_tdc_bundle_inst/SLICE_451:I14,
-        hades_tdc_bundle_inst/SLICE_452:I14,
-        hades_tdc_bundle_inst/SLICE_453:I14,
-        hades_tdc_bundle_inst/SLICE_454:I14, hades_tdc_bundle_inst/SLICE_455:I14
-        
-Signal hades_drop_cmp_buf_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_449:O3
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I8, hades_drop_cmp_buf[8]:I0
-Signal hades_tdc_bundle_inst/hades_raw_out_valid - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I0,
-        hades_tdc_bundle_inst/SLICE_459:I6, hades_tdc_bundle_inst/SLICE_460:I6,
-        hades_tdc_bundle_inst/SLICE_628:I0, hades_tdc_bundle_inst/SLICE_628:I8,
-        hades_tdc_bundle_inst/SLICE_693:I1, hades_tdc_bundle_inst/SLICE_693:I8
-Signal hades_tdc_bundle_inst/hit_i[0] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_628:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I1,
-        hades_tdc_bundle_inst/SLICE_459:I7, hades_tdc_bundle_inst/SLICE_460:I7,
-        hades_tdc_bundle_inst/SLICE_628:I1, hades_tdc_bundle_inst/SLICE_628:I7,
-        hades_tdc_bundle_inst/SLICE_693:I2, hades_tdc_bundle_inst/SLICE_693:I7
-Signal hades_tdc_bundle_inst/hit_i[1] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_628:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I4,
-        hades_tdc_bundle_inst/SLICE_459:I4, hades_tdc_bundle_inst/SLICE_460:I4,
-        hades_tdc_bundle_inst/SLICE_628:I6, hades_tdc_bundle_inst/SLICE_693:I3,
-        hades_tdc_bundle_inst/SLICE_693:I6
-Signal un1_hit_i_2_0_a2 - Driver Comp: hades_tdc_bundle_inst/SLICE_693:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_439:I14,
-        hades_tdc_bundle_inst/SLICE_440:I14,
-        hades_tdc_bundle_inst/SLICE_441:I14,
-        hades_tdc_bundle_inst/SLICE_442:I14,
-        hades_tdc_bundle_inst/SLICE_443:I14, hades_dbg2_out[28]_MGIOL:I8,
-        hades_dbg2_out[27]_MGIOL:I8, hades_dbg2_out[26]_MGIOL:I8,
-        hades_dbg2_out[25]_MGIOL:I8, hades_dbg2_out[24]_MGIOL:I8,
-        hades_dbg2_out[23]_MGIOL:I8, hades_dbg2_out[22]_MGIOL:I8,
-        hades_dbg2_out[21]_MGIOL:I8, hades_dbg2_out[20]_MGIOL:I8,
-        hades_dbg2_out[18]_MGIOL:I8, hades_dbg2_out[17]_MGIOL:I8,
-        hades_dbg2_out[16]_MGIOL:I8, hades_dbg2_out[2]_MGIOL:I8,
-        hades_dbg2_out[1]_MGIOL:I8, hades_dbg2_out[0]_MGIOL:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
-     _internal35_1_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_
-     out_inst/dec_neg_inst/SLICE_573:O2
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_573:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed7_rising_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out
-     _inst/dec_neg_inst/SLICE_726:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec
-        _neg_inst/SLICE_572:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out
-        _inst/dec_neg_inst/SLICE_573:I16
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_i
-     nternal - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst
-     /dec_neg_inst/SLICE_573:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_725:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
-     nst/SLICE_725:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I2, hades
-        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
-        1
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
-     ernal[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
-     t/dec_neg_inst/SLICE_571:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_576:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
-     nst/SLICE_576:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I4
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_571:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
-     ernal[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
-     t/dec_neg_inst/SLICE_571:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_576:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
-     nst/SLICE_576:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I5
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_571:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I13
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int
-     ernal[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins
-     t/dec_neg_inst/SLICE_572:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_577:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
-     nst/SLICE_577:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I4
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i
-     nst/SLICE_572:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I12
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_563:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_567:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_567:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_573:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_728:I0
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_563:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_567:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_567:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_573:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_694:I6, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_728:I1
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_564:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_568:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_568:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_573:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_694:I0, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_694:I7, hades_tdc_bundle_inst/hades_tdc_c
-        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I0
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_564:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_568:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_568:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_694:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_694:I8, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_727:I0, hades_tdc_bundle_inst/hades_tdc_c
-        hannel_raw_out_inst/dec_neg_inst/SLICE_729:I1
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_565:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_569:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_569:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_694:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_694:I9, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_727:I1, hades_tdc_bundle_inst/hades_tdc_c
-        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I2
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_565:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_569:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_569:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_572:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_694:I3, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_neg_inst/SLICE_727:I2, hades_tdc_bundle_inst/hades_tdc_c
-        hannel_raw_out_inst/dec_neg_inst/SLICE_728:I3, hades_tdc_bundle_inst/had
-        es_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729:I2
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_566:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_570:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_570:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_572:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_727:I3
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_566:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_570:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_726:I0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync
-     ed[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d
-     ec_neg_inst/SLICE_570:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_726:I1
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_559:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_563:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_559:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_563:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_560:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_564:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_560:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_564:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_561:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_565:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_561:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_565:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_562:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_566:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7]
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_562:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_566:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_620:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_559:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_621:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_559:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_622:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_560:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_623:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_560:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_624:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_561:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_625:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_561:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_626:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_562:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] -
-     Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i
-     nst/SLICE_627:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_562:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
-     _internal35_1_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_r
-     aw_out_inst/dec_neg_inst/SLICE_694:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_573:I3
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
-     _internal35_1_0_0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_ra
-     w_out_inst/dec_neg_inst/SLICE_727:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_573:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_729:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I1
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out
-     _internal31_1_i_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel
-     _raw_out_inst/dec_neg_inst/SLICE_572:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        neg_inst/SLICE_571:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_neg_inst/SLICE_572:I0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0
-     - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg
-     _inst/SLICE_728:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I3
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I1, hades
-        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I
-        0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - Driver
-     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLI
-     CE_725:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I14
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1
-     _0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-     neg_inst/SLICE_694:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst
-        /SLICE_571:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
-     ernal35_1_i - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O2
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_558:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_
-     rising_i - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins
-        t/SLICE_556:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/de
-        c_inst/SLICE_557:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-        st/dec_inst/SLICE_558:I16
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_inter
-     nal - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_731:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I2, hades
-        _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
-     l[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_574:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I4
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
-     l[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_574:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I5
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O2
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_556:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna
-     l[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_575:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I4
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
-     ernal31_1_i_0_0 - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O2
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_557:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_551:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_556:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_558:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_696:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_696:I6
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_551:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_558:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_695:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_696:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_696:I7
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_552:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_556:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_558:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_695:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_inst/SLICE_695:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
-        ut_inst/dec_inst/SLICE_696:I2, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/dec_inst/SLICE_696:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_552:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_557:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_695:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_695:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_inst/SLICE_732:I0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_553:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_557:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_695:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_695:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_inst/SLICE_732:I1
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_553:I5
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_556:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_557:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_695:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/dec_inst/SLICE_696:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
-        ut_inst/dec_inst/SLICE_732:I2
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_554:I4
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_556:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_
-        inst/SLICE_557:I4, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        dec_inst/SLICE_732:I3
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_554:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_730:I0
-Signal
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7]
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_730:I1
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_547:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_547:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_548:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_548:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_549:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_549:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_550:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_550:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_543:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_543:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_544:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_544:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_545:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_545:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_546:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_546:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_557:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst
-        /SLICE_558:I3
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int
-     ernal35_1_0_0 - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_558:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_556:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - Driver
-     Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I14
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I2
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI
-        CE_555:I3
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_607:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_607:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_607:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_623:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_611:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_627:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_611:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_611:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_606:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_606:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_606:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_622:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_610:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_626:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_610:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_610:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_605:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_621:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_605:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_605:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_609:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_625:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_609:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_609:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_604:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_620:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_604:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_604:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf
-     fered1[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_608:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_624:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_
-     synced[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in
-     st/tdc_neg_inst/SLICE_608:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_608:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_591:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_615:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_619:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_595:I4
-Signal hades_trig_c_i - Driver Comp: SLICE_747:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_588:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst
-        /SLICE_589:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
-        inst/SLICE_590:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/
-        tdc_inst/SLICE_591:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/tdc_inst/SLICE_592:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_o
-        ut_inst/tdc_inst/SLICE_593:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/tdc_inst/SLICE_594:I5, hades_tdc_bundle_inst/hades_tdc_chann
-        el_raw_out_inst/tdc_inst/SLICE_595:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_614:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_590:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_594:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_618:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_589:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_613:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_617:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_593:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_588:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_612:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync
-     ed[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_592:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere
-     d1[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI
-        CE_616:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I0
-Signal hades_dbg2_coarse_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_435:I2,
-        hades_tdc_bundle_inst/SLICE_435:I7, hades_tdc_bundle_inst/SLICE_438:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I5,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I5,
-        hades_tdc_bundle_inst/SLICE_681:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I7,
-        hades_dbg2_coarse[2]:I0, hades_offset[5]_MGIOL:I10
-Signal hades_dbg2_coarse_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I9,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I9,
-        hades_tdc_bundle_inst/SLICE_434:I7, hades_tdc_bundle_inst/SLICE_435:I1,
-        hades_tdc_bundle_inst/SLICE_435:I8, hades_tdc_bundle_inst/SLICE_438:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I4,
-        hades_tdc_bundle_inst/SLICE_681:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I2,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I8,
-        hades_dbg2_coarse[1]:I0, hades_offset[4]_MGIOL:I10
-Signal hades_dbg2_coarse_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I8,
-        hades_tdc_bundle_inst/SLICE_434:I0, hades_tdc_bundle_inst/SLICE_434:I6,
-        hades_tdc_bundle_inst/SLICE_435:I0, hades_tdc_bundle_inst/SLICE_435:I9,
-        hades_tdc_bundle_inst/SLICE_438:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I5,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I5,
-        hades_tdc_bundle_inst/SLICE_681:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I3,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I9,
-        hades_dbg2_coarse[0]:I0, hades_offset[3]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I0
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I6
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
-     _19 - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O1
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I0
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - Driver
-     Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I14,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I4
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O3
-   Load Comps: hades_dbg2_out[0]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I5
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O4
-   Load Comps: hades_dbg2_out[1]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I4
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O3
-   Load Comps: hades_dbg2_out[2]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I4
-Signal hades_tdc_bundle_inst/hades_raw_out[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_439:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I5
-Signal hades_tdc_bundle_inst/hades_raw_out[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_439:I5
-Signal hades_tdc_bundle_inst/hades_raw_out[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_440:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I5
-Signal hades_tdc_bundle_inst/hades_raw_out[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_440:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I4,
-        hades_tdc_bundle_inst/SLICE_681:I3
-Signal hades_tdc_bundle_inst/hades_raw_out[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_441:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I5
-Signal hades_tdc_bundle_inst/hades_raw_out[8] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_441:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I4
-        
-Signal hades_tdc_bundle_inst/hades_raw_out[9] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_442:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I5
-        
-Signal hades_tdc_bundle_inst/hades_raw_out[10] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_442:I5
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I4
-        
-Signal hades_tdc_bundle_inst/hades_raw_out[11] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_443:I4
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I5
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[12] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O4
-   Load Comps: hades_dbg2_out[16]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I4
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[13] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O3
-   Load Comps: hades_dbg2_out[17]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I5
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[14] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O4
-   Load Comps: hades_dbg2_out[18]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I4
-Signal hades_tdc_bundle_inst.hades_raw_out[15] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O3
-   Load Comps: hades_dbg2_out[20]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I5
-Signal hades_tdc_bundle_inst.hades_raw_out[16] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O4
-   Load Comps: hades_dbg2_out[21]_MGIOL:I10
-Signal hades_tdc_bundle_inst.hades_raw_out[17] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O3
-   Load Comps: hades_dbg2_out[22]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I5
-Signal hades_tdc_bundle_inst.hades_raw_out[18] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O4
-   Load Comps: hades_dbg2_out[23]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I4,
-        hades_tdc_bundle_inst/SLICE_698:I3
-Signal hades_tdc_bundle_inst.hades_raw_out[19] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O3
-   Load Comps: hades_dbg2_out[24]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I5
-Signal hades_tdc_bundle_inst.hades_raw_out[20] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O4
-   Load Comps: hades_dbg2_out[25]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I4
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[21] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O3
-   Load Comps: hades_dbg2_out[26]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O3
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I5
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[22] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O4
-   Load Comps: hades_dbg2_out[27]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O4
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I4
-        
-Signal hades_tdc_bundle_inst.hades_raw_out[23] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:O3
-   Load Comps: hades_dbg2_out[28]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I12
-Signal hades_dbg2_coarse_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I3,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I3,
-        hades_tdc_bundle_inst/SLICE_435:I6, hades_tdc_bundle_inst/SLICE_436:I0,
-        hades_tdc_bundle_inst/SLICE_436:I6, hades_tdc_bundle_inst/SLICE_437:I0,
-        hades_tdc_bundle_inst/SLICE_438:I9,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I4,
-        hades_tdc_bundle_inst/SLICE_681:I0, hades_tdc_bundle_inst/SLICE_698:I0,
-        hades_tdc_bundle_inst/SLICE_698:I6, hades_dbg2_coarse[3]:I0,
-        hades_offset[6]_MGIOL:I10
-Signal hades_dbg2_coarse_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_436:I1,
-        hades_tdc_bundle_inst/SLICE_436:I7, hades_tdc_bundle_inst/SLICE_455:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I5,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I5,
-        hades_tdc_bundle_inst/SLICE_681:I1, hades_tdc_bundle_inst/SLICE_698:I1,
-        hades_tdc_bundle_inst/SLICE_698:I7, hades_tdc_bundle_inst/SLICE_701:I6,
-        hades_dbg2_coarse[4]:I0, hades_offset[7]_MGIOL:I10
-Signal hades_dbg2_coarse_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I9,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I9,
-        hades_tdc_bundle_inst/SLICE_436:I8, hades_tdc_bundle_inst/SLICE_455:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I4,
-        hades_tdc_bundle_inst/SLICE_701:I7, hades_dbg2_coarse[5]:I0,
-        hades_offset[8]_MGIOL:I10
-Signal hades_dbg2_coarse_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I0,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I0,
-        hades_tdc_bundle_inst/SLICE_437:I1, hades_tdc_bundle_inst/SLICE_437:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I5,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I5,
-        hades_tdc_bundle_inst/SLICE_701:I0, hades_dbg2_coarse[6]:I0
-Signal hades_dbg2_coarse_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I1,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I1,
-        hades_tdc_bundle_inst/SLICE_437:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I4,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I4,
-        hades_tdc_bundle_inst/SLICE_701:I1, hades_dbg2_coarse[7]:I0
-Signal hades_dbg2_coarse_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_438:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I6,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I6,
-        hades_tdc_bundle_inst/SLICE_438:I0, hades_tdc_bundle_inst/SLICE_455:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I5,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I5,
-        hades_dbg2_coarse[8]:I0
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I12
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I0,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I0,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_681:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I2,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I2,
-        hades_tdc_bundle_inst/SLICE_436:I2, hades_tdc_bundle_inst/SLICE_436:I9,
-        hades_tdc_bundle_inst/SLICE_437:I3, hades_tdc_bundle_inst/SLICE_681:I2,
-        hades_tdc_bundle_inst/SLICE_698:I2, hades_tdc_bundle_inst/SLICE_698:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N
-     _14 - Driver Comp: hades_tdc_bundle_inst/SLICE_681:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I6
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14
-     - Driver Comp: hades_tdc_bundle_inst/SLICE_698:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I6
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I3
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I3
-        
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
-     tmp[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I17
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_698:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I8
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_
-     tmp[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I17
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_701:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I2,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I8,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I2,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I8,
-        hades_tdc_bundle_inst/SLICE_437:I2, hades_tdc_bundle_inst/SLICE_437:I8,
-        hades_tdc_bundle_inst/SLICE_438:I1
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_438:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I3,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I9,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I3,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I9,
-        hades_tdc_bundle_inst/SLICE_437:I9, hades_tdc_bundle_inst/SLICE_438:I3,
-        hades_tdc_bundle_inst/SLICE_455:I4
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_701:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I7,
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I7,
-        hades_tdc_bundle_inst/SLICE_438:I2, hades_tdc_bundle_inst/SLICE_455:I9
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
-     cry - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:I17
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
-     ata_tmp[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I17
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d
-     ata_tmp[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I17
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _27_cry - Driver Comp:
-     hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:O6
-   Load Comps:
-        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:I17
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I12,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I16
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I16
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I6
-Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I14,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I1,
-        hades_offset[8]_MGIOL:I8, hades_offset[7]_MGIOL:I8,
-        hades_offset[6]_MGIOL:I8, hades_offset[5]_MGIOL:I8,
-        hades_offset[4]_MGIOL:I8, hades_offset[3]_MGIOL:I8,
-        hades_offset[2]_MGIOL:I8, hades_offset[1]_MGIOL:I8,
-        hades_offset[0]_MGIOL:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I2
-Signal hades_discard_c - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_123:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I0,
-        hades_tdc_bundle_inst/SLICE_741:I0, hades_discard:I0
-Signal valid_fast_RNI999V - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:O0
-   Load Comps: hades_offset[8]_MGIOL:I9, hades_offset[7]_MGIOL:I9,
-        hades_offset[6]_MGIOL:I9, hades_offset[5]_MGIOL:I9,
-        hades_offset[4]_MGIOL:I9, hades_offset[3]_MGIOL:I9,
-        hades_offset[2]_MGIOL:I9, hades_offset[1]_MGIOL:I9,
-        hades_offset[0]_MGIOL:I9
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
-     _1_i - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O2
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I12
-Signal
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i
-     - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I16,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I16
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I4
-Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O3
-   Load Comps: hades_offset[0]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I5
-Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O4
-   Load Comps: hades_offset[1]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O2
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31
-     _1_i_0 - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O2
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I4
-Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:O3
-   Load Comps: hades_offset[2]_MGIOL:I10
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I6
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I7
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I3
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I3
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35
-     _1_0_0 - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I3
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O1
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I4
-Signal hades_lvl1_c_i - Driver Comp: SLICE_743:O0
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I5,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O3
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] -
-     Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O4
-   Load Comps:
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I3
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O4
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I2
-Signal hades_invalid_dl_c[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I1,
-        hades_invalid_dl[3]:I0
-Signal hades_invalid_dl_c[2] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O4
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I0,
-        hades_invalid_dl[2]:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I9,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I12
-Signal hades_tdc_bundle_inst/SUM1_0_0 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_628:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_628:I13
-Signal ANB3 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I7,
-        hades_tdc_bundle_inst/SLICE_122:I6, hades_tdc_bundle_inst/SLICE_123:I1,
-        hades_tdc_bundle_inst/SLICE_432:I2, hades_tdc_bundle_inst/SLICE_432:I7,
-        hades_tdc_bundle_inst/SLICE_653:I1, hades_tdc_bundle_inst/SLICE_654:I8,
-        hades_tdc_bundle_inst/SLICE_683:I7, hades_hit_out_i[3]:I0
-Signal ANB2 - Driver Comp: hades_tdc_bundle_inst/SLICE_123:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I9,
-        hades_tdc_bundle_inst/SLICE_122:I7, hades_tdc_bundle_inst/SLICE_123:I3,
-        hades_tdc_bundle_inst/SLICE_123:I7, hades_tdc_bundle_inst/SLICE_432:I0,
-        hades_tdc_bundle_inst/SLICE_653:I3, hades_tdc_bundle_inst/SLICE_654:I0,
-        hades_tdc_bundle_inst/SLICE_654:I7, hades_hit_out_i[2]:I0
-Signal ANB1 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I6,
-        hades_tdc_bundle_inst/SLICE_122:I1, hades_tdc_bundle_inst/SLICE_122:I8,
-        hades_tdc_bundle_inst/SLICE_123:I2, hades_tdc_bundle_inst/SLICE_123:I6,
-        hades_tdc_bundle_inst/SLICE_432:I3, hades_tdc_bundle_inst/SLICE_432:I6,
-        hades_tdc_bundle_inst/SLICE_653:I2, hades_tdc_bundle_inst/SLICE_654:I6,
-        hades_tdc_bundle_inst/SLICE_683:I8, hades_hit_out_i[1]:I0
-Signal ANB0 - Driver Comp: hades_tdc_bundle_inst/SLICE_121:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I0,
-        hades_tdc_bundle_inst/SLICE_121:I8, hades_tdc_bundle_inst/SLICE_122:I0,
-        hades_tdc_bundle_inst/SLICE_122:I9, hades_tdc_bundle_inst/SLICE_123:I4,
-        hades_tdc_bundle_inst/SLICE_432:I1, hades_tdc_bundle_inst/SLICE_653:I0,
-        hades_tdc_bundle_inst/SLICE_683:I6, hades_tdc_bundle_inst/SLICE_710:I0,
-        hades_hit_out_i[0]:I0
-Signal hades_tdc_bundle_inst/N_50_i_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_122:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_122:I13
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I12
-Signal hades_window_end_c - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_741:I1, hades_window_end:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I4,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I13
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O4
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I7,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I3
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I13
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O4
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I1,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I7
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I12
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I13
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O4
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I3,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I9
-Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - Driver Comp:
-     hades_lvl1_MGIOL:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I4
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I5
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I12
-Signal hades_offset_valid_c - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O3
-   Load Comps: hades_offset_valid:I0, hades_raw_out_valid_MGIOL:I10
-Signal hades_invalid_dl_c[1] - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O3
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I5,
-        hades_invalid_dl[1]:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I14
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:O2
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I1
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - Driver Comp:
-     hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I0
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I8,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I2,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I8
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O1
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 -
-     Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O0
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I6,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I0,
-        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I6
-Signal hades_tdc_bundle_inst/N_59_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_628:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_628:I12
-Signal hades_tdc_bundle_inst/N_46_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_122:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_122:I12
-Signal hades_tdc_bundle_inst/N_44 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_693:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_458:I2
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:O6
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I17
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O6
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I17
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O6
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I17
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - Driver
-     Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O6
-   Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I17
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_435:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_435:I13,
-        hades_tdc_bundle_inst/SLICE_451:I5
-Signal hades_dbg2_out_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_445:I4, hades_dbg2_out[4]:I0
-Signal hades_dbg2_out_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_445:I5, hades_dbg2_out[5]:I0
-Signal hades_dbg2_out_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_446:I4, hades_dbg2_out[6]:I0
-Signal hades_dbg2_out_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_446:I5, hades_dbg2_out[7]:I0
-Signal hades_dbg2_out_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_447:I4, hades_dbg2_out[8]:I0
-Signal hades_dbg2_out_c[9] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_447:I5, hades_dbg2_out[9]:I0
-Signal hades_dbg2_out_c[10] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_448:I4, hades_dbg2_out[10]:I0
-Signal hades_dbg2_out_c[11] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_448:I5, hades_dbg2_out[11]:I0
-Signal hades_tdc_bundle_inst/N_246_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_457:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I12
-Signal hades_hit_valid_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_457:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I3,
-        hades_tdc_bundle_inst/SLICE_457:I7, hades_tdc_bundle_inst/SLICE_654:I3,
-        hades_hit_valid[0]:I0
-Signal hades_tdc_bundle_inst/N_243_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_458:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_458:I12
-Signal hades_hit_valid_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_458:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_456:I1,
-        hades_tdc_bundle_inst/SLICE_458:I4, hades_tdc_bundle_inst/SLICE_710:I1,
-        SLICE_740:I0, hades_hit_valid[1]:I0
-Signal hades_tdc_bundle_inst/N_245_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_459:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_459:I12
-Signal hades_hit_valid_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_459:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_459:I1,
-        hades_tdc_bundle_inst/SLICE_459:I9, hades_tdc_bundle_inst/SLICE_710:I2,
-        hades_hit_valid[2]:I0
-Signal hades_tdc_bundle_inst/N_244_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_460:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_460:I12
-Signal hades_hit_valid_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_460:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_460:I1,
-        hades_tdc_bundle_inst/SLICE_460:I9, hades_tdc_bundle_inst/SLICE_683:I1,
-        hades_hit_valid[3]:I0
-Signal hades_tdc_bundle_inst/N_247_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_121:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I12
-Signal hades_tdc_bundle_inst/hit_out_i_6[2] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_123:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_123:I12
-Signal hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_456:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_456:I12
-Signal hades_drop_cmp_buf_valid_c - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_456:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_456:I0,
-        hades_tdc_bundle_inst/SLICE_458:I0, hades_tdc_bundle_inst/SLICE_458:I6,
-        hades_tdc_bundle_inst/SLICE_710:I6, hades_drop_cmp_buf_valid:I0
-Signal hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_434:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_434:I12,
-        hades_tdc_bundle_inst/SLICE_450:I4
-Signal hades_drop_cmp_buf_coarse_c[0] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_450:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_118:I8,
-        hades_drop_cmp_buf_coarse[0]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_434:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_434:I13,
-        hades_tdc_bundle_inst/SLICE_450:I5
-Signal hades_drop_cmp_buf_coarse_c[1] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_450:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_118:I6,
-        hades_drop_cmp_buf_coarse[1]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_435:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_435:I12,
-        hades_tdc_bundle_inst/SLICE_451:I4
-Signal hades_drop_cmp_buf_coarse_c[2] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_451:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I2,
-        hades_drop_cmp_buf_coarse[2]:I0
-Signal hades_drop_cmp_buf_coarse_c[3] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_451:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I0,
-        hades_drop_cmp_buf_coarse[3]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_436:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_436:I12,
-        hades_tdc_bundle_inst/SLICE_452:I4
-Signal hades_drop_cmp_buf_coarse_c[4] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_452:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I8,
-        hades_drop_cmp_buf_coarse[4]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_436:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_436:I13,
-        hades_tdc_bundle_inst/SLICE_452:I5
-Signal hades_drop_cmp_buf_coarse_c[5] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_452:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I6,
-        hades_drop_cmp_buf_coarse[5]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_437:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_437:I12,
-        hades_tdc_bundle_inst/SLICE_453:I4
-Signal hades_drop_cmp_buf_coarse_c[6] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_453:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I2,
-        hades_drop_cmp_buf_coarse[6]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_437:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_437:I13,
-        hades_tdc_bundle_inst/SLICE_453:I5
-Signal hades_drop_cmp_buf_coarse_c[7] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_453:O4
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I0,
-        hades_drop_cmp_buf_coarse[7]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_438:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_438:I12,
-        hades_tdc_bundle_inst/SLICE_454:I4
-Signal hades_drop_cmp_buf_coarse_c[8] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_454:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I7,
-        hades_drop_cmp_buf_coarse[8]:I0
-Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_455:O2
-   Load Comps: hades_tdc_bundle_inst/SLICE_455:I12
-Signal hades_drop_cmp_buf_coarse_c[9] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_455:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I6,
-        hades_drop_cmp_buf_coarse[9]:I0
-Signal hades_drop_cmp_buf_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O3
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_118:I9, hades_drop_cmp_buf[0]:I0
-Signal hades_drop_cmp_buf_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O4
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_118:I7, hades_drop_cmp_buf[1]:I0
-Signal hades_drop_cmp_buf_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O3
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I3, hades_drop_cmp_buf[2]:I0
-Signal hades_drop_cmp_buf_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O4
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I1, hades_drop_cmp_buf[3]:I0
-Signal hades_drop_cmp_buf_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O3
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I9, hades_drop_cmp_buf[4]:I0
-Signal hades_drop_cmp_buf_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O4
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I7, hades_drop_cmp_buf[5]:I0
-Signal hades_drop_cmp_buf_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O3
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I3, hades_drop_cmp_buf[6]:I0
-Signal hades_drop_cmp_buf_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O4
-     
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I1, hades_drop_cmp_buf[7]:I0
-Signal hades_buf_release_c - Driver Comp: hades_tdc_bundle_inst/SLICE_433:O3
-   Load Comps: hades_tdc_bundle_inst/SLICE_457:I2,
-        hades_tdc_bundle_inst/SLICE_457:I6, hades_tdc_bundle_inst/SLICE_458:I3,
-        hades_tdc_bundle_inst/SLICE_458:I8, hades_tdc_bundle_inst/SLICE_459:I0,
-        hades_tdc_bundle_inst/SLICE_459:I8, hades_tdc_bundle_inst/SLICE_460:I0,
-        hades_tdc_bundle_inst/SLICE_460:I8, hades_buf_release:I0
-Signal hades_tdc_bundle_inst/N_90 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_683:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_683:I0
-Signal hades_tdc_bundle_inst/N_80 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_432:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_654:I2
-Signal hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_741:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_121:I4
-Signal hades_tdc_bundle_inst/N_66 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_654:O1
-   Load Comps: hades_tdc_bundle_inst/SLICE_654:I1
-Signal hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_654:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_683:I2
-Signal hades_tdc_bundle_inst/N_45 - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_710:O0
-   Load Comps: hades_tdc_bundle_inst/SLICE_654:I9
-Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_118:O6
-   Load Comps: hades_tdc_bundle_inst/SLICE_119:I17
-Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - Driver Comp:
-     hades_tdc_bundle_inst/SLICE_119:O6
-   Load Comps: hades_tdc_bundle_inst/SLICE_120:I17
-Signal pll0inst/GND - Driver Comp: pll0inst/SLICE_742:O0
-   Load Comps: pll0inst/PLLInst_0:STDBY
-Signal LVL1_TRG_DATA_VALID_IN_c - Driver Comp: LVL1_TRG_DATA_VALID_IN:O0
-   Load Comps: LVL1_TRG_DATA_VALID_IN_MGIOL:I5
-Signal LVL1_INVALID_TRG_IN_c - Driver Comp: LVL1_INVALID_TRG_IN:O0
-   Load Comps: LVL1_INVALID_TRG_IN_MGIOL:I5
-Signal reset_dc_c - Driver Comp: reset_dc:O0
-   Load Comps: reset_dc_MGIOL:I5
-Signal hades_lvl1_c - Driver Comp: hades_lvl1:O0
-   Load Comps: SLICE_743:I0, hades_lvl1_MGIOL:I5
-Signal FEE_TRG_RELEASE_OUT_c - Driver Comp: FEE_TRG_RELEASE_OUT_MGIOL:O0
-   Load Comps: FEE_TRG_RELEASE_OUT:I1
-Signal FEE_DATA_WRITE_OUT_c - Driver Comp: FEE_DATA_WRITE_OUT_MGIOL:O0
-   Load Comps: FEE_DATA_WRITE_OUT:I1
-Signal FEE_DATAFINISHED_OUT_c - Driver Comp: FEE_DATAFINISHED_OUT_MGIOL:O0
-   Load Comps: FEE_DATAFINISHED_OUT:I1
-Signal hades_raw_out_valid_c - Driver Comp: hades_raw_out_valid_MGIOL:O0
-   Load Comps: hades_raw_out_valid:I1
-Signal hades_dbg2_out_c[0] - Driver Comp: hades_dbg2_out[0]_MGIOL:O0
-   Load Comps: hades_dbg2_out[0]:I1
-Signal hades_dbg2_out_c[1] - Driver Comp: hades_dbg2_out[1]_MGIOL:O0
-   Load Comps: hades_dbg2_out[1]:I1
-Signal hades_dbg2_out_c[2] - Driver Comp: hades_dbg2_out[2]_MGIOL:O0
-   Load Comps: hades_dbg2_out[2]:I1
-Signal hades_dbg2_out_c[16] - Driver Comp: hades_dbg2_out[16]_MGIOL:O0
-   Load Comps: hades_dbg2_out[16]:I1
-Signal hades_dbg2_out_c[17] - Driver Comp: hades_dbg2_out[17]_MGIOL:O0
-   Load Comps: hades_dbg2_out[17]:I1
-Signal hades_dbg2_out_c[18] - Driver Comp: hades_dbg2_out[18]_MGIOL:O0
-   Load Comps: hades_dbg2_out[18]:I1
-Signal hades_dbg2_out_c[20] - Driver Comp: hades_dbg2_out[20]_MGIOL:O0
-   Load Comps: hades_dbg2_out[20]:I1
-Signal hades_dbg2_out_c[21] - Driver Comp: hades_dbg2_out[21]_MGIOL:O0
-   Load Comps: hades_dbg2_out[21]:I1
-Signal hades_dbg2_out_c[22] - Driver Comp: hades_dbg2_out[22]_MGIOL:O0
-   Load Comps: hades_dbg2_out[22]:I1
-Signal hades_dbg2_out_c[23] - Driver Comp: hades_dbg2_out[23]_MGIOL:O0
-   Load Comps: hades_dbg2_out[23]:I1
-Signal hades_dbg2_out_c[24] - Driver Comp: hades_dbg2_out[24]_MGIOL:O0
-   Load Comps: hades_dbg2_out[24]:I1
-Signal hades_dbg2_out_c[25] - Driver Comp: hades_dbg2_out[25]_MGIOL:O0
-   Load Comps: hades_dbg2_out[25]:I1
-Signal hades_dbg2_out_c[26] - Driver Comp: hades_dbg2_out[26]_MGIOL:O0
-   Load Comps: hades_dbg2_out[26]:I1
-Signal hades_dbg2_out_c[27] - Driver Comp: hades_dbg2_out[27]_MGIOL:O0
-   Load Comps: hades_dbg2_out[27]:I1
-Signal hades_dbg2_out_c[28] - Driver Comp: hades_dbg2_out[28]_MGIOL:O0
-   Load Comps: hades_dbg2_out[28]:I1
-Signal hades_offset_c[0] - Driver Comp: hades_offset[0]_MGIOL:O0
-   Load Comps: hades_offset[0]:I1
-Signal hades_offset_c[1] - Driver Comp: hades_offset[1]_MGIOL:O0
-   Load Comps: hades_offset[1]:I1
-Signal hades_offset_c[2] - Driver Comp: hades_offset[2]_MGIOL:O0
-   Load Comps: hades_offset[2]:I1
-Signal hades_offset_c[3] - Driver Comp: hades_offset[3]_MGIOL:O0
-   Load Comps: hades_offset[3]:I1
-Signal hades_offset_c[4] - Driver Comp: hades_offset[4]_MGIOL:O0
-   Load Comps: hades_offset[4]:I1
-Signal hades_offset_c[5] - Driver Comp: hades_offset[5]_MGIOL:O0
-   Load Comps: hades_offset[5]:I1
-Signal hades_offset_c[6] - Driver Comp: hades_offset[6]_MGIOL:O0
-   Load Comps: hades_offset[6]:I1
-Signal hades_offset_c[7] - Driver Comp: hades_offset[7]_MGIOL:O0
-   Load Comps: hades_offset[7]:I1
-Signal hades_offset_c[8] - Driver Comp: hades_offset[8]_MGIOL:O0
-   Load Comps: hades_offset[8]:I1
-Signal hades_trig_c - Driver Comp: hades_trig:O0
-   Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst
-        /SLICE_604:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_
-        neg_inst/SLICE_605:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i
-        nst/tdc_neg_inst/SLICE_606:I5, hades_tdc_bundle_inst/hades_tdc_channel_r
-        aw_out_inst/tdc_neg_inst/SLICE_607:I5, hades_tdc_bundle_inst/hades_tdc_c
-        hannel_raw_out_inst/tdc_neg_inst/SLICE_608:I5, hades_tdc_bundle_inst/had
-        es_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:I5, hades_tdc_bundle_
-        inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:I5, hades_tdc
-        _bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I5,
-        SLICE_747:I0
-Signal trig_c[2] - Driver Comp: trig[2]:O0
-   Load Comps: SLICE_746:I0
-Signal trig_c[1] - Driver Comp: trig[1]:O0
-   Load Comps: SLICE_745:I0
-Signal trig_c[0] - Driver Comp: trig[0]:O0
-   Load Comps: SLICE_744:I0
-   Number of warnings:  13
-   Number of errors:    0
-     
-
-
-Design Errors/Warnings
-
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic
-     error in "BLOCK NET "tdc_out*" ;": tdc_out* does not match any nets in the
-     design. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic
-     error in "LOCATE COMP "reset" SITE "D11" ;": COMP "reset" cannot be found
-     in design. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic
-     error in "UGROUP "trig_gate0" BBOX 1 1 
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO
-     	BLKNAME trig_pad_RNII4FF[0];": Block
-     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1" of UGROUP
-     "trig_gate0" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO" of UGROUP
-     "trig_gate0" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2" of UGROUP
-     "trig_gate0" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO" of UGROUP
-     "trig_gate0" not found in design This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic
-     error in "LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;": UGROUP "trig_gate0"
-     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic
-     error in "UGROUP "tdc_ch0" BBOX 1 6 
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de   ....
-     _inst/dec_inst/out_internal[2]
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;":
-     Block "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP
-     "tdc_ch0" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc_ch0"
-     not found in designBlock
-
-     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]" of UGROUP "tdc_ch0"
-     not found in designBlock "genblk1[0].tdc_cha   ....   out_internal[1]" of
-     UGROUP "tdc_ch0" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]" of UGROUP
-     "tdc_ch0" not found in design This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic
-     error in "LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;": UGROUP "tdc_ch0"
-     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic
-     error in "UGROUP "tdc2" BBOX 1 6 
-     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst
-     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC
-     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
-     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_   ....
-     st/dec_inst/valid
-     	BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal
-     	BLKNAME
-     genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
-     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]" of
-     UGROUP "tdc2" not found in designBlock
-     "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc2" not
-     found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]"
-     of UGROUP "tdc2" not found in designBlock "genblk1[1].td   ....
-     ternal[2]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channe
-     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "tdc2" not
-     found in design This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic
-     error in "LOCATE UGROUP "tdc2" SITE "R65C41D" ;": UGROUP "tdc2" cannot be
-     found for 'LOCATE UGROUP'. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic
-     error in "UGROUP "dec3" BBOX 1 6 
-     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst
-     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC
-     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0]
-     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_   ....
-     st/dec_inst/valid
-     	BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal
-     	BLKNAME
-     genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block
-     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]" of
-     UGROUP "dec3" not found in designBlock
-     "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "dec3" not
-     found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]"
-     of UGROUP "dec3" not found in designBlock "genblk1[2].td   ....
-     ternal[2]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channe
-     l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "dec3" not
-     found in design This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic
-     error in "LOCATE UGROUP "dec3" SITE "R65C49D" ;": UGROUP "dec3" cannot be
-     found for 'LOCATE UGROUP'. This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic
-     error in "UGROUP "tdc0_neg" BBOX 1 4 
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_cl
-     k_synced[0]
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b
-     uffered1[0]
-
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_   ....   enblk1[0].tdc_c
-     hannel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3]
-     	BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_b
-     uffered[7];": Block "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genb
-     lk1[0].in_clk_synced[0]" of UGROUP "tdc0_neg" not found in designBlock "gen
-     blk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]"
-     of UGROUP "tdc0_neg" not found in designBlock
-     "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b   ....
-     of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_
-     out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]" of UGROUP "tdc0_neg" not
-     found in design This preference has been disabled.
-WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic
-     error in "LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;": UGROUP "tdc0_neg"
-     cannot be found for 'LOCATE UGROUP'. This preference has been disabled.
-WARNING - map: Semantic error in "PGROUP "lvl1_dec" BBOX 1 6  DEVSIZE
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464"
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465"
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474"
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_ins   ....
-     inst/SLICE_734"
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735"
-     	COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";":
-     Group lvl1_dec is invalid because BBOX size is too small to accommodate all
-     the components. This preference has been disabled.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+
-| IO Name             | Direction | Levelmode | IO         |
-|                     |           |  IO_TYPE  | Register   |
-+---------------------+-----------+-----------+------------+
-| hades_raw_valid_vect[0]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[0]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| clk                 | INPUT     | LVDS      |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_valid| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[11]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[10]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[9]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[8]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[7]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[6]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[5]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[4]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| hades_drop_cmp_buf_coarse[3]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[2]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[1]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf_coarse[0]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[11]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[10]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[9]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[8]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[7]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[6]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[5]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[4]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[3]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[2]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[1]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_drop_cmp_buf[0]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[8]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[7]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[6]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[5]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[4]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[3]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[2]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[1]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_coarse[0]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[31]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[30]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[29]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| hades_dbg2_out[28]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[27]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[26]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[25]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[24]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[23]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[22]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[21]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[20]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[19]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[18]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[17]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[16]  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[15]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[14]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[13]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[12]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[11]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[10]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[9]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[8]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[7]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[6]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[5]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[4]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[3]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[2]   | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_dbg2_out[1]   | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-| hades_dbg2_out[0]   | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_buf_drop[3]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_buf_drop[2]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_buf_drop[1]   | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_buf_drop[0]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_invalid_dl[3] | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_invalid_dl[2] | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_invalid_dl[1] | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_invalid_dl[0] | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_discard       | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_valid[3]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_valid[2]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_valid[1]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_valid[0]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_out_i[3]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_out_i[2]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_out_i[1]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_hit_out_i[0]  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_buf_finished  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_buf_release   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_buf_out_valid | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_window_end    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_offset_valid  | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_offset[8]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[7]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[6]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[5]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[4]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-| hades_offset[3]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[2]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[1]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_offset[0]     | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_lvl1_invalid  | INPUT     | LVCMOS25  | IN         |
-+---------------------+-----------+-----------+------------+
-| hades_lvl1          | INPUT     | LVCMOS25  | IN         |
-+---------------------+-----------+-----------+------------+
-| hades_raw_valid_vect[1]| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| hades_raw_out_valid | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| hades_trig          | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| release_out         | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| finished            | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| last_buf_empty      | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| discard             | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| burst               | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| LVL1_TRG_DATA_VALI_IN_rising| OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_TRG_RELEASE_OUT | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| FEE_DATAFINISHED_OUT| OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_WRITE_OUT  | OUTPUT    | LVCMOS25  | OUT        |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[31]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[30]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[29]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[28]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[27]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[26]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[25]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[24]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[23]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[22]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| FEE_DATA_OUT[21]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[20]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[19]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[18]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[17]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[16]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[15]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[14]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[13]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[12]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[11]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[10]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[9]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[8]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[7]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[6]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[5]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[4]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[3]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[2]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[1]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| FEE_DATA_OUT[0]     | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| LVL1_INVALID_TRG_IN | INPUT     | LVCMOS25  | IN         |
-+---------------------+-----------+-----------+------------+
-| LVL1_TRG_DATA_VALID_IN| INPUT     | LVCMOS25  | IN         |
-+---------------------+-----------+-----------+------------+
-| fifo_empty1         | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_rden           | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[31]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[30]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| fifo_data_out[29]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[28]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[27]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[26]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[25]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[24]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[23]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[22]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[21]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[20]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[19]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[18]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[17]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[16]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[15]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[14]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[13]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[12]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[11]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[10]   | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[9]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[8]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[7]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[6]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[5]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[4]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[3]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| fifo_data_out[2]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-| fifo_data_out[1]    | OUTPUT    | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| trig[2]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| trig[1]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| trig[0]             | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-| reset_dc            | INPUT     | LVCMOS25  | IN         |
-+---------------------+-----------+-----------+------------+
-| rd_clk              | INPUT     | LVCMOS25  |            |
-+---------------------+-----------+-----------+------------+
-
-
-
-Removed logic
-
-Block GSR_INST undriven or does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/VCC undriven or
-     does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/VCC undriven or
-     does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/VCC undriven
-     or does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/VCC
-     undriven or does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/VCC undriven
-     or does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/VCC
-     undriven or does not drive anything - clipped.
-Block trb_adapter_inst/VCC undriven or does not drive anything - clipped.
-Block fifo_colector_inst/VCC undriven or does not drive anything - clipped.
-Block genblk1[0].tdc_channel_fifo_out_inst/VCC undriven or does not drive
-     anything - clipped.
-Block genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
-     drive anything - clipped.
-Block genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
-     drive anything - clipped.
-Block genblk1[1].tdc_channel_fifo_out_inst/VCC undriven or does not drive
-     anything - clipped.
-Block genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
-     drive anything - clipped.
-Block genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
-     drive anything - clipped.
-Block genblk1[2].tdc_channel_fifo_out_inst/VCC undriven or does not drive
-     anything - clipped.
-Block genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not
-     drive anything - clipped.
-Block genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not
-     drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg was
-     merged into signal hades_trig_c
-Signal reset_dl_i[2] was merged into signal reset_dl[2]
-Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.
-     CN was merged into signal pll_clks[0]
-Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.
-     CN was merged into signal pll_clks[1]
-
-Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.
-     CN was merged into signal pll_clks[2]
-Signal genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN was merged into signal
-     pll_clks[3]
-Signal fifo_colector_inst/fifo40_inst/invout_0 was merged into signal
-     last_buf_empty_c
-Signal fifo_colector_inst/fifo40_inst/invout_1 was merged into signal
-     fifo_colector_inst/fifo40_inst/Full
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
-     into signal fifo_empty1_c
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
-     into signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
-     into signal fifo_empty[1]
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
-     into signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged
-     into signal fifo_empty[2]
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged
-     into signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full
-Signal GND undriven or does not drive anything - clipped.
-Signal VCC undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/VCC undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC undriven or does not
-     drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC undriven or does
-     not drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/VCC undriven or does not drive anything -
-     clipped.
-Signal fifo_colector_inst/fifo40_inst/rRst undriven or does not drive anything -
-     clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does
-     not drive anything - clipped.
-Signal pll0inst/CLKINTFB undriven or does not drive anything - clipped.
-Signal pll0inst/REFCLK undriven or does not drive anything - clipped.
-Signal pll0inst/INTLOCK undriven or does not drive anything - clipped.
-Signal pll0inst/LOCK undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1 undriven or does not drive
-
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/N_73 undriven or does not drive anything - clipped.
-     
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1
-     undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT
-     undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1
-     undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0
-     undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1 undriven or does not
-     drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _27_0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _27_0_COUT undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _21_0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _21_0_S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _9_0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _9_0_S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _1_0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I
-     _1_0_S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1 undriven or does
-     not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
-     0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_
-     0_COUT undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
-     0_S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_
-     0_S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
-     _S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0
-     _S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
-     _S1 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0
-     _S0 undriven or does not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2 undriven or does
-     not drive anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1 undriven or does not drive
-     anything - clipped.
-Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/a1_S1_2 undriven or does not drive
-
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/a1_COUT_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/CIN undriven or does not drive anything -
-     clipped.
-Signal fifo_colector_inst/fifo40_inst/a0_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/a0_COUT_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2 undriven or does not
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2 undriven or does not
-
-     drive anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/CIN_0 undriven or does not drive anything
-     - clipped.
-Signal fifo_colector_inst/fifo40_inst/co4_1 undriven or does not drive anything
-     - clipped.
-Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/CIN_1 undriven or does not drive anything
-     - clipped.
-Signal fifo_colector_inst/fifo40_inst/co4 undriven or does not drive anything -
-     clipped.
-Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2 undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/CIN_2 undriven or does not drive anything
-     - clipped.
-Signal fifo_colector_inst/fifo40_inst/Q_1[35] undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/Q_1[34] undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/Q_1[33] undriven or does not drive
-     anything - clipped.
-Signal fifo_colector_inst/fifo40_inst/Q_1[32] undriven or does not drive
-     anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
-
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0 undriven
-     or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
-     not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14
-     undriven or does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
-
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
-     does not drive anything - clipped.
-Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0 undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_0 undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_0 undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_0 undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_0
-
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
-     not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0
-     undriven or does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
-
-     does not drive anything - clipped.
-Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1 undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1 undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1 undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1 undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1
-
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does
-     not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1
-     undriven or does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or
-     does not drive anything - clipped.
-Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or
-     does not drive anything - clipped.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1/out_RN
-     O was optimized away.
-Block reset_dl_RNISCAF[2] was optimized away.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buff
-     ered1_4_.CN was optimized away.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buff
-     ered1_5_.CN was optimized away.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buff
-     ered1_6_.CN was optimized away.
-
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_7_.CN was
-     optimized away.
-Block fifo_colector_inst/fifo40_inst/INV_0 was optimized away.
-Block fifo_colector_inst/fifo40_inst/INV_1 was optimized away.
-Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
-     away.
-Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
-     away.
-Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
-     away.
-Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
-     away.
-Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized
-     away.
-Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized
-     away.
-Block GND was optimized away.
-Block VCC was optimized away.
-Block hades_tdc_bundle_inst/VCC was optimized away.
-Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC was optimized away.
-Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC was optimized
-     away.
-Block fifo_colector_inst/fifo40_inst/VCC was optimized away.
-Block fifo_colector_inst/fifo40_inst/OR2_t18 was optimized away.
-Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
-     
-Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
-     away.
-Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
-     
-Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
-     away.
-Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away.
-     
-Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized
-     away.
-
-
-
-Memory Usage
-
-/fifo_colector_inst/fifo40_inst:
-    EBRs: 1
-    RAM SLICEs: 0
-    Logic SLICEs: 81
-    PFU Registers: 102
-    -Contains EBR pdp_ram_0_0_1:  TYPE= PDPW16KD,  Width= 32,  Depth_R= 512,
-         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= ASYNC,  ASYNC_RESET_RELEASE=
-         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo40_dc.lpc
-/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst:
-    EBRs: 1
-    RAM SLICEs: 0
-    Logic SLICEs: 81
-    PFU Registers: 102
-    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
-         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
-         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
-
-/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst:
-    EBRs: 1
-    RAM SLICEs: 0
-    Logic SLICEs: 81
-    PFU Registers: 102
-    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
-         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
-         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
-/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst:
-    EBRs: 1
-    RAM SLICEs: 0
-    Logic SLICEs: 81
-    PFU Registers: 102
-    -Contains EBR pdp_ram_0_0_0:  TYPE= PDPW16KD,  Width= 24,  Depth_R= 512,
-         Depth_W= 512,  REGMODE= NOREG,  RESETMODE= SYNC,  ASYNC_RESET_RELEASE=
-         SYNC,  GSR= DISABLED,  MEM_LPC_FILE= fifo32dc.lpc
-
-     
-
-
-
-PLL/DLL Summary
----------------
-
-PLL 1:                                     Pin/Node Value
-  PLL Instance Name:                                pll0inst/PLLInst_0
-  PLL Type:                                         EHXPLLL
-  Input Clock:                             PIN      clk_c
-  Input Clock2:                                     NONE
-  Input Clock select:                               NONE
-  Output Clock(P):                         NODE     pll_clks[0]
-  Output Clock(S):                         NODE     pll_clks[1]
-  Output Clock(S2):                        NODE     pll_clks[2]
-  Output Clock(S3):                        NODE     pll_clks[3]
-  Feedback Signal:                         NODE     pll_clks[0]
-  Reset Signal:                                     NONE
-  Standby Signal:                          NODE     pll0inst/GND
-  PLL LOCK signal:                                  NONE
-  PLL Internal LOCK Signal:                         NONE
-  Input Clock Frequency (MHz):                      100.0000
-  Output Clock(P) Frequency (MHz):                  300.0000
-  Output Clock(S) Frequency (MHz):                  300.0000
-  Output Clock(S2) Frequency (MHz):                 300.0000
-  Output Clock(S3) Frequency (MHz):                 300.0000
-  CLKOP Post Divider A Input:                       DIVA
-  CLKOS Post Divider B Input:                       DIVB
-  CLKOS2 Post Divider C Input:                      DIVC
-  CLKOS3 Post Divider D Input:                      DIVD
-  Pre Divider A Input:                              NONE
-  Pre Divider B Input:                              NONE
-  Pre Divider C Input:                              NONE
-  Pre Divider D Input:                              NONE
-  FB_MODE:                                          CLKOP
-  CLKI Divider:                                     1
-  CLKFB Divider:                                    3
-  CLKOP Divider:                                    2
-  CLKOS Divider:                                    2
-  CLKOS2 Divider:                                   2
-
-  CLKOS3 Divider:                                   2
-  Fractional N Divider:                             NONE
-  CLKOP Desired Phase Shift(degree):                0
-  CLKOP Trim Option Rising/Falling:                 FALLING
-  CLKOP Trim Option Delay:                          0
-  CLKOS Desired Phase Shift(degree):                45
-  CLKOS Trim Option Rising/Falling:                 FALLING
-  CLKOS Trim Option Delay:                          0
-  CLKOS2 Desired Phase Shift(degree):               90
-  CLKOS2 Trim Option Rising/Falling:                NONE
-  CLKOS2 Trim Option Delay:                         NONE
-  CLKOS3 Desired Phase Shift(degree):               135
-  CLKOS3 Trim Option Rising/Falling:                NONE
-  CLKOS3 Trim Option Delay:                         NONE
-
-
-
-ASIC Components
----------------
-
-Instance Name: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-         Type: PDPW16KD
-Instance Name: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-         Type: PDPW16KD
-Instance Name: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0
-         Type: PDPW16KD
-Instance Name: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1
-         Type: PDPW16KD
-Instance Name: pll0inst/PLLInst_0
-         Type: EHXPLLL
-
-
-
-PGROUP Utilization
-
-PGROUP "tdc0":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "tdc22":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "tdc3":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "lvl1_tdc":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "hades_dec_pos":
-   Logic contained: 23 SLICEs, 6 PFUs
-   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "hades_dec_neg":
-   Logic contained: 23 SLICEs, 6 PFUs
-   Bounded Area:    6 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "hades_tdc_pos":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "hades_tdc_neg":
-   Logic contained: 16 SLICEs, 4 PFUs
-   Bounded Area:    4 PFUs (DEVSIZE) (ANCHORED)
-
-PGROUP "lvl1_pad":
-   Logic contained: 1 SLICEs, 1 PFUs
-   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "gate2":
-   Logic contained: 1 SLICEs, 1 PFUs
-   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
-PGROUP "trig3":
-   Logic contained: 1 SLICEs, 1 PFUs
-   Bounded Area:    1 PFUs (DEVSIZE) (ANCHORED)
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 4 secs  
-   Total REAL Time: 5 secs  
-   Peak Memory Usage: 361 MB
-        
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-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
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    - - diff --git a/impl1/s1_impl1_ngd.asd b/impl1/s1_impl1_ngd.asd deleted file mode 100644 index c265c78..0000000 --- a/impl1/s1_impl1_ngd.asd +++ /dev/null @@ -1 +0,0 @@ -[ActiveSupport NGD] diff --git a/impl1/s1_impl1_pad.html b/impl1/s1_impl1_pad.html deleted file mode 100644 index 183da5b..0000000 --- a/impl1/s1_impl1_pad.html +++ /dev/null @@ -1,767 +0,0 @@ - -PAD Specification File - - -
    PAD Specification File
-***************************
-
-PART TYPE:        LFE5UM5G-45F
-Performance Grade:      8
-PACKAGE:          CABGA381
-Package Status:                     Final          Version 1.38
-
-Wed Jun 16 09:20:00 2021
-
-Pinout by Port Name:
-+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
-| Port Name                     | Pin/Bank | Buffer Type  | Site  | BC Enable | Properties                        |
-+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
-| FEE_DATAFINISHED_OUT          | D13/1    | LVCMOS25_OUT | PT53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[0]               | R17/3    | LVCMOS25_OUT | PR44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[10]              | J19/2    | LVCMOS25_OUT | PR32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[11]              | R3/8     | LVCMOS25_OUT | PB15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[12]              | N5/6     | LVCMOS25_OUT | PL59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[13]              | G16/2    | LVCMOS25_OUT | PR17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[14]              | P5/6     | LVCMOS25_OUT | PL59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[15]              | M19/3    | LVCMOS25_OUT | PR35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[16]              | N19/3    | LVCMOS25_OUT | PR59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[17]              | B15/1    | LVCMOS25_OUT | PT69A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[18]              | A15/1    | LVCMOS25_OUT | PT67A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[19]              | K5/6     | LVCMOS25_OUT | PL44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[1]               | N3/6     | LVCMOS25_OUT | PL62A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[20]              | V1/8     | LVCMOS25_OUT | PB6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[21]              | G19/2    | LVCMOS25_OUT | PR29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[22]              | T2/8     | LVCMOS25_OUT | PB13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[23]              | H20/2    | LVCMOS25_OUT | PR29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[24]              | K19/2    | LVCMOS25_OUT | PR32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[25]              | H17/2    | LVCMOS25_OUT | PR20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[26]              | L19/3    | LVCMOS25_OUT | PR35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[27]              | C20/2    | LVCMOS25_OUT | PR23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[28]              | F19/2    | LVCMOS25_OUT | PR26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[29]              | U1/8     | LVCMOS25_OUT | PB6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[2]               | G18/2    | LVCMOS25_OUT | PR17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[30]              | D20/2    | LVCMOS25_OUT | PR23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[31]              | H18/2    | LVCMOS25_OUT | PR20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[3]               | M17/3    | LVCMOS25_OUT | PR41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[4]               | E18/2    | LVCMOS25_OUT | PR14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[5]               | F16/2    | LVCMOS25_OUT | PR11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[6]               | A16/1    | LVCMOS25_OUT | PT74A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[7]               | L3/6     | LVCMOS25_OUT | PL62C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[8]               | L16/3    | LVCMOS25_OUT | PR38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_OUT[9]               | F20/2    | LVCMOS25_OUT | PR26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_DATA_WRITE_OUT            | C13/1    | LVCMOS25_OUT | PT51B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| FEE_TRG_RELEASE_OUT           | E13/1    | LVCMOS25_OUT | PT53B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| LVL1_INVALID_TRG_IN           | R16/3    | LVCMOS25_IN  | PR44C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| LVL1_TRG_DATA_VALID_IN        | A9/0     | LVCMOS25_IN  | PT33A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| LVL1_TRG_DATA_VALI_IN_rising  | N18/3    | LVCMOS25_OUT | PR41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| burst                         | N16/3    | LVCMOS25_OUT | PR41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| clk                           | P3/6     | LVDS_IN      | PL68C |           | CLAMP:ON                          |
-| discard                       | P16/3    | LVCMOS25_OUT | PR44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[0]              | P17/3    | LVCMOS25_OUT | PR41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[10]             | K20/2    | LVCMOS25_OUT | PR32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[11]             | U2/8     | LVCMOS25_OUT | PB13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[12]             | N4/6     | LVCMOS25_OUT | PL59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[13]             | J16/2    | LVCMOS25_OUT | PR20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[14]             | M4/6     | LVCMOS25_OUT | PL59A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[15]             | J20/2    | LVCMOS25_OUT | PR32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[16]             | P18/3    | LVCMOS25_OUT | PR59D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[17]             | C15/1    | LVCMOS25_OUT | PT69B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[18]             | E14/1    | LVCMOS25_OUT | PT58B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[19]             | L4/6     | LVCMOS25_OUT | PL44C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[1]              | M3/6     | LVCMOS25_OUT | PL62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[20]             | Y2/8     | LVCMOS25_OUT | PB9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[21]             | K18/2    | LVCMOS25_OUT | PR29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[22]             | W1/8     | LVCMOS25_OUT | PB9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[23]             | J18/2    | LVCMOS25_OUT | PR29C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[24]             | M20/3    | LVCMOS25_OUT | PR35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[25]             | J17/2    | LVCMOS25_OUT | PR20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[26]             | L20/3    | LVCMOS25_OUT | PR35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[27]             | D19/2    | LVCMOS25_OUT | PR23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[28]             | G20/2    | LVCMOS25_OUT | PR26D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[29]             | T1/8     | LVCMOS25_OUT | PB4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[2]              | F17/2    | LVCMOS25_OUT | PR17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[30]             | E19/2    | LVCMOS25_OUT | PR23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[31]             | H16/2    | LVCMOS25_OUT | PR17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[3]              | L17/3    | LVCMOS25_OUT | PR38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[4]              | F18/2    | LVCMOS25_OUT | PR14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[5]              | D17/2    | LVCMOS25_OUT | PR11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[6]              | B16/1    | LVCMOS25_OUT | PT74B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[7]              | N1/6     | LVCMOS25_OUT | PL65D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[8]              | M18/3    | LVCMOS25_OUT | PR38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_data_out[9]              | E20/2    | LVCMOS25_OUT | PR26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_empty1                   | N17/3    | LVCMOS25_OUT | PR44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| fifo_rden                     | A19/1    | LVCMOS25_OUT | PT85A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| finished                      | D14/1    | LVCMOS25_OUT | PT58A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_drop[0]             | N20/3    | LVCMOS25_OUT | PR59B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_drop[1]             | A10/0    | LVCMOS25_OUT | PT36A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_drop[2]             | R20/3    | LVCMOS25_OUT | PR62B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_drop[3]             | U16/3    | LVCMOS25_OUT | PR68C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_finished            | A4/7     | LVCMOS25_OUT | PL11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_out_valid           | C9/0     | LVCMOS25_OUT | PT27A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_buf_release             | E7/0     | LVCMOS25_OUT | PT9A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[0]          | G5/7     | LVCMOS25_OUT | PL29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[1]          | H3/7     | LVCMOS25_OUT | PL29D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[2]          | E3/7     | LVCMOS25_OUT | PL20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[3]          | C2/7     | LVCMOS25_OUT | PL23D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[4]          | B6/0     | LVCMOS25_OUT | PT4B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[5]          | B1/7     | LVCMOS25_OUT | PL23B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[6]          | E5/7     | LVCMOS25_OUT | PL20C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[7]          | M5/6     | LVCMOS25_OUT | PL53A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_coarse[8]          | F1/6     | LVCMOS25_OUT | PL35B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[0]             | J3/6     | LVCMOS25_OUT | PL38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[10]            | A8/0     | LVCMOS25_OUT | PT18B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[11]            | D6/0     | LVCMOS25_OUT | PT6B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[12]            | B8/0     | LVCMOS25_OUT | PT15B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[13]            | P19/3    | LVCMOS25_OUT | PR59C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[14]            | P1/6     | LVCMOS25_OUT | PL68A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[15]            | C17/1    | LVCMOS25_OUT | PT78B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[16]            | G3/7     | LVCMOS25_OUT | PL32A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[17]            | G1/6     | LVCMOS25_OUT | PL35D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[18]            | J5/6     | LVCMOS25_OUT | PL38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[19]            | R1/8     | LVCMOS25_OUT | PB4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[1]             | E2/7     | LVCMOS25_OUT | PL32D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[20]            | K3/6     | LVCMOS25_OUT | PL38D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[21]            | G2/6     | LVCMOS25_OUT | PL35A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[22]            | H4/7     | LVCMOS25_OUT | PL29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[23]            | J4/6     | LVCMOS25_OUT | PL38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[24]            | H1/6     | LVCMOS25_OUT | PL41C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[25]            | J1/6     | LVCMOS25_OUT | PL41B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[26]            | K1/6     | LVCMOS25_OUT | PL41D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[27]            | F2/7     | LVCMOS25_OUT | PL32C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[28]            | H2/6     | LVCMOS25_OUT | PL35C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[29]            | A17/1    | LVCMOS25_OUT | PT80A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[2]             | F3/7     | LVCMOS25_OUT | PL32B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[30]            | E16/2    | LVCMOS25_OUT | PR11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[31]            | R18/3    | LVCMOS25_OUT | PR65B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[3]             | C16/1    | LVCMOS25_OUT | PT76A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[4]             | E4/7     | LVCMOS25_OUT | PL17A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[5]             | C3/7     | LVCMOS25_OUT | PL17C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[6]             | F4/7     | LVCMOS25_OUT | PL20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[7]             | B3/7     | LVCMOS25_OUT | PL14D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[8]             | E8/0     | LVCMOS25_OUT | PT13A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_dbg2_out[9]             | C7/0     | LVCMOS25_OUT | PT11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_discard                 | B11/0    | LVCMOS25_OUT | PT38A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[0]         | D3/7     | LVCMOS25_OUT | PL17D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[10]        | B17/1    | LVCMOS25_OUT | PT78A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[11]        | U17/3    | LVCMOS25_OUT | PR68B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[1]         | D9/0     | LVCMOS25_OUT | PT20A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[2]         | A6/0     | LVCMOS25_OUT | PT4A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[3]         | C6/0     | LVCMOS25_OUT | PT11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[4]         | F5/7     | LVCMOS25_OUT | PL20D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[5]         | C4/7     | LVCMOS25_OUT | PL14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[6]         | D8/0     | LVCMOS25_OUT | PT13B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[7]         | D5/7     | LVCMOS25_OUT | PL17B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[8]         | B4/7     | LVCMOS25_OUT | PL14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf[9]         | B20/1    | LVCMOS25_OUT | PT85B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[0]  | A11/0    | LVCMOS25_OUT | PT36B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[10] | T17/3    | LVCMOS25_OUT | PR68D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[11] | D18/2    | LVCMOS25_OUT | PR14A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[1]  | A13/1    | LVCMOS25_OUT | PT49B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[2]  | B10/0    | LVCMOS25_OUT | PT33B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[3]  | C12/1    | LVCMOS25_OUT | PT44B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[4]  | E12/1    | LVCMOS25_OUT | PT47B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[5]  | D12/1    | LVCMOS25_OUT | PT47A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[6]  | E11/1    | LVCMOS25_OUT | PT42B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[7]  | D11/1    | LVCMOS25_OUT | PT42A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[8]  | B13/1    | LVCMOS25_OUT | PT51A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_coarse[9]  | A12/1    | LVCMOS25_OUT | PT49A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_drop_cmp_buf_valid      | A7/0     | LVCMOS25_OUT | PT18A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_out_i[0]            | E9/0     | LVCMOS25_OUT | PT20B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_out_i[1]            | C11/0    | LVCMOS25_OUT | PT38B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_out_i[2]            | E6/0     | LVCMOS25_OUT | PT6A  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_out_i[3]            | D7/0     | LVCMOS25_OUT | PT9B  |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_valid[0]            | A3/7     | LVCMOS25_OUT | PL14C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_valid[1]            | B5/7     | LVCMOS25_OUT | PL11C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_valid[2]            | A5/7     | LVCMOS25_OUT | PL11B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_hit_valid[3]            | C5/7     | LVCMOS25_OUT | PL11D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_invalid_dl[0]           | V2/8     | LVCMOS25_OUT | PB11A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_invalid_dl[1]           | L5/6     | LVCMOS25_OUT | PL44D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_invalid_dl[2]           | K2/6     | LVCMOS25_OUT | PL41A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_invalid_dl[3]           | K4/6     | LVCMOS25_OUT | PL44A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_lvl1                    | E1/7     | LVCMOS25_IN  | PL26D |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| hades_lvl1_invalid            | W2/8     | LVCMOS25_IN  | PB11B |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| hades_offset[0]               | D10/0    | LVCMOS25_OUT | PT29A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[1]               | C10/0    | LVCMOS25_OUT | PT31B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[2]               | E10/0    | LVCMOS25_OUT | PT29B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[3]               | D1/7     | LVCMOS25_OUT | PL26B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[4]               | C1/7     | LVCMOS25_OUT | PL26A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[5]               | D2/7     | LVCMOS25_OUT | PL26C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[6]               | A2/7     | LVCMOS25_OUT | PL23A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[7]               | B9/0     | LVCMOS25_OUT | PT31A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset[8]               | B2/7     | LVCMOS25_OUT | PL23C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_offset_valid            | D15/1    | LVCMOS25_OUT | PT71A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_raw_out_valid           | E15/1    | LVCMOS25_OUT | PT71B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_raw_valid_vect[0]       | U20/3    | LVCMOS25_OUT | PR62D |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_raw_valid_vect[1]       | E17/2    | LVCMOS25_OUT | PR14B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| hades_trig                    | H5/7     | LVCMOS25_IN  | PL29C |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| hades_window_end              | C14/1    | LVCMOS25_OUT | PT56B |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| last_buf_empty                | L18/3    | LVCMOS25_OUT | PR38C |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| rd_clk                        | B12/1    | LVCMOS25_IN  | PT44A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| release_out                   | A14/1    | LVCMOS25_OUT | PT56A |           | DRIVE:8mA CLAMP:ON SLEW:SLOW      |
-| reset_dc                      | C8/0     | LVCMOS25_IN  | PT15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| trig[0]                       | R2/8     | LVCMOS25_IN  | PB15A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| trig[1]                       | T3/8     | LVCMOS25_IN  | PB18A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-| trig[2]                       | T19/3    | LVCMOS25_IN  | PR65A |           | PULL:DOWN CLAMP:ON HYSTERESIS:ON  |
-+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 2.5V  |
-| 1    | 2.5V  |
-| 2    | 2.5V  |
-| 3    | 2.5V  |
-| 6    | 2.5V  |
-| 7    | 2.5V  |
-| 8    | 2.5V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
-| Pin/Bank | Pin Info                      | Preference | Buffer Type  | Site         | Dual Function            | BC Enable |
-+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
-| A2/7     | hades_offset[6]               |            | LVCMOS25_OUT | PL23A        | LDQ29                    |           |
-| A3/7     | hades_hit_valid[0]            |            | LVCMOS25_OUT | PL14C        | LDQ17                    |           |
-| A4/7     | hades_buf_finished            |            | LVCMOS25_OUT | PL11A        | ULC_GPLL0T_IN/LDQ17      |           |
-| A5/7     | hades_hit_valid[2]            |            | LVCMOS25_OUT | PL11B        | ULC_GPLL0C_IN/LDQ17      |           |
-| A6/0     | hades_drop_cmp_buf[2]         |            | LVCMOS25_OUT | PT4A         | ULC_GPLL1T_IN            |           |
-| A7/0     | hades_drop_cmp_buf_valid      |            | LVCMOS25_OUT | PT18A        |                          |           |
-| A8/0     | hades_dbg2_out[10]            |            | LVCMOS25_OUT | PT18B        |                          |           |
-| A9/0     | LVL1_TRG_DATA_VALID_IN        | LOCATED    | LVCMOS25_IN  | PT33A        | GR_PCLK0_1               |           |
-| A10/0    | hades_buf_drop[1]             |            | LVCMOS25_OUT | PT36A        | PCLKT0_1                 |           |
-| A11/0    | hades_drop_cmp_buf_coarse[0]  |            | LVCMOS25_OUT | PT36B        |                          |           |
-| A12/1    | hades_drop_cmp_buf_coarse[9]  |            | LVCMOS25_OUT | PT49A        |                          |           |
-| A13/1    | hades_drop_cmp_buf_coarse[1]  |            | LVCMOS25_OUT | PT49B        |                          |           |
-| A14/1    | release_out                   |            | LVCMOS25_OUT | PT56A        |                          |           |
-| A15/1    | FEE_DATA_OUT[18]              |            | LVCMOS25_OUT | PT67A        |                          |           |
-| A16/1    | FEE_DATA_OUT[6]               |            | LVCMOS25_OUT | PT74A        |                          |           |
-| A17/1    | hades_dbg2_out[29]            |            | LVCMOS25_OUT | PT80A        |                          |           |
-| A18/1    |     unused, PULL:DOWN         |            |              | PT83A        |                          |           |
-| A19/1    | fifo_rden                     |            | LVCMOS25_OUT | PT85A        | URC_GPLL1T_IN            |           |
-| B1/7     | hades_dbg2_coarse[5]          |            | LVCMOS25_OUT | PL23B        | LDQ29                    |           |
-| B2/7     | hades_offset[8]               |            | LVCMOS25_OUT | PL23C        | VREF1_7/LDQ29            |           |
-| B3/7     | hades_dbg2_out[7]             |            | LVCMOS25_OUT | PL14D        | LDQ17                    |           |
-| B4/7     | hades_drop_cmp_buf[8]         |            | LVCMOS25_OUT | PL14B        | LDQ17                    |           |
-| B5/7     | hades_hit_valid[1]            |            | LVCMOS25_OUT | PL11C        | LDQ17                    |           |
-| B6/0     | hades_dbg2_coarse[4]          |            | LVCMOS25_OUT | PT4B         | ULC_GPLL1C_IN            |           |
-| B8/0     | hades_dbg2_out[12]            |            | LVCMOS25_OUT | PT15B        |                          |           |
-| B9/0     | hades_offset[7]               |            | LVCMOS25_OUT | PT31A        |                          |           |
-| B10/0    | hades_drop_cmp_buf_coarse[2]  |            | LVCMOS25_OUT | PT33B        | GR_PCLK0_0               |           |
-| B11/0    | hades_discard                 |            | LVCMOS25_OUT | PT38A        | PCLKT0_0                 |           |
-| B12/1    | rd_clk                        |            | LVCMOS25_IN  | PT44A        | PCLKT1_0                 |           |
-| B13/1    | hades_drop_cmp_buf_coarse[8]  |            | LVCMOS25_OUT | PT51A        |                          |           |
-| B15/1    | FEE_DATA_OUT[17]              |            | LVCMOS25_OUT | PT69A        |                          |           |
-| B16/1    | fifo_data_out[6]              |            | LVCMOS25_OUT | PT74B        |                          |           |
-| B17/1    | hades_drop_cmp_buf[10]        |            | LVCMOS25_OUT | PT78A        |                          |           |
-| B18/1    |     unused, PULL:DOWN         |            |              | PT80B        |                          |           |
-| B19/1    |     unused, PULL:DOWN         |            |              | PT83B        |                          |           |
-| B20/1    | hades_drop_cmp_buf[9]         |            | LVCMOS25_OUT | PT85B        | URC_GPLL1C_IN            |           |
-| C1/7     | hades_offset[4]               |            | LVCMOS25_OUT | PL26A        | LDQ29                    |           |
-| C2/7     | hades_dbg2_coarse[3]          |            | LVCMOS25_OUT | PL23D        | LDQ29                    |           |
-| C3/7     | hades_dbg2_out[5]             |            | LVCMOS25_OUT | PL17C        | LDQ17                    |           |
-| C4/7     | hades_drop_cmp_buf[5]         |            | LVCMOS25_OUT | PL14A        | LDQ17                    |           |
-| C5/7     | hades_hit_valid[3]            |            | LVCMOS25_OUT | PL11D        | LDQ17                    |           |
-| C6/0     | hades_drop_cmp_buf[3]         |            | LVCMOS25_OUT | PT11A        |                          |           |
-| C7/0     | hades_dbg2_out[9]             |            | LVCMOS25_OUT | PT11B        |                          |           |
-| C8/0     | reset_dc                      |            | LVCMOS25_IN  | PT15A        |                          |           |
-| C9/0     | hades_buf_out_valid           |            | LVCMOS25_OUT | PT27A        |                          |           |
-| C10/0    | hades_offset[1]               |            | LVCMOS25_OUT | PT31B        |                          |           |
-| C11/0    | hades_hit_out_i[1]            |            | LVCMOS25_OUT | PT38B        |                          |           |
-| C12/1    | hades_drop_cmp_buf_coarse[3]  |            | LVCMOS25_OUT | PT44B        |                          |           |
-| C13/1    | FEE_DATA_WRITE_OUT            |            | LVCMOS25_OUT | PT51B        |                          |           |
-| C14/1    | hades_window_end              |            | LVCMOS25_OUT | PT56B        |                          |           |
-| C15/1    | fifo_data_out[17]             |            | LVCMOS25_OUT | PT69B        |                          |           |
-| C16/1    | hades_dbg2_out[3]             |            | LVCMOS25_OUT | PT76A        |                          |           |
-| C17/1    | hades_dbg2_out[15]            |            | LVCMOS25_OUT | PT78B        |                          |           |
-| C18/2    |     unused, PULL:DOWN         |            |              | PR11A        | URC_GPLL0T_IN/RDQ17      |           |
-| C20/2    | FEE_DATA_OUT[27]              |            | LVCMOS25_OUT | PR23A        | RDQ29                    |           |
-| CCLK/8   |                               |            |              | CCLK         | MCLK/SCK                 |           |
-| D1/7     | hades_offset[3]               |            | LVCMOS25_OUT | PL26B        | LDQ29                    |           |
-| D2/7     | hades_offset[5]               |            | LVCMOS25_OUT | PL26C        | LDQ29                    |           |
-| D3/7     | hades_drop_cmp_buf[0]         |            | LVCMOS25_OUT | PL17D        | LDQ17                    |           |
-| D5/7     | hades_drop_cmp_buf[7]         |            | LVCMOS25_OUT | PL17B        | LDQSN17                  |           |
-| D6/0     | hades_dbg2_out[11]            |            | LVCMOS25_OUT | PT6B         |                          |           |
-| D7/0     | hades_hit_out_i[3]            |            | LVCMOS25_OUT | PT9B         |                          |           |
-| D8/0     | hades_drop_cmp_buf[6]         |            | LVCMOS25_OUT | PT13B        |                          |           |
-| D9/0     | hades_drop_cmp_buf[1]         |            | LVCMOS25_OUT | PT20A        |                          |           |
-| D10/0    | hades_offset[0]               |            | LVCMOS25_OUT | PT29A        |                          |           |
-| D11/1    | hades_drop_cmp_buf_coarse[7]  |            | LVCMOS25_OUT | PT42A        | PCLKT1_1                 |           |
-| D12/1    | hades_drop_cmp_buf_coarse[5]  |            | LVCMOS25_OUT | PT47A        | GR_PCLK1_0               |           |
-| D13/1    | FEE_DATAFINISHED_OUT          |            | LVCMOS25_OUT | PT53A        |                          |           |
-| D14/1    | finished                      |            | LVCMOS25_OUT | PT58A        |                          |           |
-| D15/1    | hades_offset_valid            |            | LVCMOS25_OUT | PT71A        |                          |           |
-| D16/1    |     unused, PULL:DOWN         |            |              | PT76B        |                          |           |
-| D17/2    | fifo_data_out[5]              |            | LVCMOS25_OUT | PR11B        | URC_GPLL0C_IN/RDQ17      |           |
-| D18/2    | hades_drop_cmp_buf_coarse[11] |            | LVCMOS25_OUT | PR14A        | RDQ17                    |           |
-| D19/2    | fifo_data_out[27]             |            | LVCMOS25_OUT | PR23B        | RDQ29                    |           |
-| D20/2    | FEE_DATA_OUT[30]              |            | LVCMOS25_OUT | PR23C        | VREF1_2/RDQ29            |           |
-| E1/7     | hades_lvl1                    | LOCATED    | LVCMOS25_IN  | PL26D        | LDQ29                    |           |
-| E2/7     | hades_dbg2_out[1]             |            | LVCMOS25_OUT | PL32D        | PCLKC7_0/LDQ29           |           |
-| E3/7     | hades_dbg2_coarse[2]          |            | LVCMOS25_OUT | PL20B        | LDQ17                    |           |
-| E4/7     | hades_dbg2_out[4]             |            | LVCMOS25_OUT | PL17A        | LDQS17                   |           |
-| E5/7     | hades_dbg2_coarse[6]          |            | LVCMOS25_OUT | PL20C        | LDQ17                    |           |
-| E6/0     | hades_hit_out_i[2]            |            | LVCMOS25_OUT | PT6A         |                          |           |
-| E7/0     | hades_buf_release             |            | LVCMOS25_OUT | PT9A         |                          |           |
-| E8/0     | hades_dbg2_out[8]             |            | LVCMOS25_OUT | PT13A        |                          |           |
-| E9/0     | hades_hit_out_i[0]            |            | LVCMOS25_OUT | PT20B        |                          |           |
-| E10/0    | hades_offset[2]               |            | LVCMOS25_OUT | PT29B        |                          |           |
-| E11/1    | hades_drop_cmp_buf_coarse[6]  |            | LVCMOS25_OUT | PT42B        |                          |           |
-| E12/1    | hades_drop_cmp_buf_coarse[4]  |            | LVCMOS25_OUT | PT47B        | GR_PCLK1_1               |           |
-| E13/1    | FEE_TRG_RELEASE_OUT           |            | LVCMOS25_OUT | PT53B        |                          |           |
-| E14/1    | fifo_data_out[18]             |            | LVCMOS25_OUT | PT58B        |                          |           |
-| E15/1    | hades_raw_out_valid           |            | LVCMOS25_OUT | PT71B        |                          |           |
-| E16/2    | hades_dbg2_out[30]            |            | LVCMOS25_OUT | PR11C        | RDQ17                    |           |
-| E17/2    | hades_raw_valid_vect[1]       |            | LVCMOS25_OUT | PR14B        | RDQ17                    |           |
-| E18/2    | FEE_DATA_OUT[4]               |            | LVCMOS25_OUT | PR14C        | RDQ17                    |           |
-| E19/2    | fifo_data_out[30]             |            | LVCMOS25_OUT | PR23D        | RDQ29                    |           |
-| E20/2    | fifo_data_out[9]              |            | LVCMOS25_OUT | PR26A        | RDQ29                    |           |
-| F1/6     | hades_dbg2_coarse[8]          |            | LVCMOS25_OUT | PL35B        | PCLKC6_1/LDQ41           |           |
-| F2/7     | hades_dbg2_out[27]            |            | LVCMOS25_OUT | PL32C        | PCLKT7_0/LDQ29           |           |
-| F3/7     | hades_dbg2_out[2]             |            | LVCMOS25_OUT | PL32B        | PCLKC7_1/LDQ29           |           |
-| F4/7     | hades_dbg2_out[6]             |            | LVCMOS25_OUT | PL20A        | LDQ17                    |           |
-| F5/7     | hades_drop_cmp_buf[4]         |            | LVCMOS25_OUT | PL20D        | LDQ17                    |           |
-| F16/2    | FEE_DATA_OUT[5]               |            | LVCMOS25_OUT | PR11D        | RDQ17                    |           |
-| F17/2    | fifo_data_out[2]              |            | LVCMOS25_OUT | PR17A        | RDQS17                   |           |
-| F18/2    | fifo_data_out[4]              |            | LVCMOS25_OUT | PR14D        | RDQ17                    |           |
-| F19/2    | FEE_DATA_OUT[28]              |            | LVCMOS25_OUT | PR26B        | RDQ29                    |           |
-| F20/2    | FEE_DATA_OUT[9]               |            | LVCMOS25_OUT | PR26C        | RDQ29                    |           |
-| G1/6     | hades_dbg2_out[17]            |            | LVCMOS25_OUT | PL35D        | PCLKC6_0/LDQ41           |           |
-| G2/6     | hades_dbg2_out[21]            |            | LVCMOS25_OUT | PL35A        | PCLKT6_1/LDQ41           |           |
-| G3/7     | hades_dbg2_out[16]            |            | LVCMOS25_OUT | PL32A        | PCLKT7_1/LDQ29           |           |
-| G5/7     | hades_dbg2_coarse[0]          |            | LVCMOS25_OUT | PL29B        | LDQSN29                  |           |
-| G16/2    | FEE_DATA_OUT[13]              |            | LVCMOS25_OUT | PR17C        | RDQ17                    |           |
-| G18/2    | FEE_DATA_OUT[2]               |            | LVCMOS25_OUT | PR17B        | RDQSN17                  |           |
-| G19/2    | FEE_DATA_OUT[21]              |            | LVCMOS25_OUT | PR29A        | GR_PCLK2_1/RDQS29        |           |
-| G20/2    | fifo_data_out[28]             |            | LVCMOS25_OUT | PR26D        | RDQ29                    |           |
-| H1/6     | hades_dbg2_out[24]            |            | LVCMOS25_OUT | PL41C        | LDQ41                    |           |
-| H2/6     | hades_dbg2_out[28]            |            | LVCMOS25_OUT | PL35C        | PCLKT6_0/LDQ41           |           |
-| H3/7     | hades_dbg2_coarse[1]          |            | LVCMOS25_OUT | PL29D        | LDQ29                    |           |
-| H4/7     | hades_dbg2_out[22]            |            | LVCMOS25_OUT | PL29A        | GR_PCLK7_1/LDQS29        |           |
-| H5/7     | hades_trig                    | LOCATED    | LVCMOS25_IN  | PL29C        | GR_PCLK7_0/LDQ29         |           |
-| H16/2    | fifo_data_out[31]             |            | LVCMOS25_OUT | PR17D        | RDQ17                    |           |
-| H17/2    | FEE_DATA_OUT[25]              |            | LVCMOS25_OUT | PR20B        | RDQ17                    |           |
-| H18/2    | FEE_DATA_OUT[31]              |            | LVCMOS25_OUT | PR20A        | RDQ17                    |           |
-| H20/2    | FEE_DATA_OUT[23]              |            | LVCMOS25_OUT | PR29B        | RDQSN29                  |           |
-| J1/6     | hades_dbg2_out[25]            |            | LVCMOS25_OUT | PL41B        | LDQSN41                  |           |
-| J3/6     | hades_dbg2_out[0]             |            | LVCMOS25_OUT | PL38C        | GR_PCLK6_1/LDQ41         |           |
-| J4/6     | hades_dbg2_out[23]            |            | LVCMOS25_OUT | PL38A        | GR_PCLK6_0/LDQ41         |           |
-| J5/6     | hades_dbg2_out[18]            |            | LVCMOS25_OUT | PL38B        | LDQ41                    |           |
-| J16/2    | fifo_data_out[13]             |            | LVCMOS25_OUT | PR20D        | RDQ17                    |           |
-| J17/2    | fifo_data_out[25]             |            | LVCMOS25_OUT | PR20C        | RDQ17                    |           |
-| J18/2    | fifo_data_out[23]             |            | LVCMOS25_OUT | PR29C        | GR_PCLK2_0/RDQ29         |           |
-| J19/2    | FEE_DATA_OUT[10]              |            | LVCMOS25_OUT | PR32A        | PCLKT2_1/RDQ29           |           |
-| J20/2    | fifo_data_out[15]             |            | LVCMOS25_OUT | PR32C        | PCLKT2_0/RDQ29           |           |
-| K1/6     | hades_dbg2_out[26]            |            | LVCMOS25_OUT | PL41D        | LDQ41                    |           |
-| K2/6     | hades_invalid_dl[2]           |            | LVCMOS25_OUT | PL41A        | LDQS41                   |           |
-| K3/6     | hades_dbg2_out[20]            |            | LVCMOS25_OUT | PL38D        | LDQ41                    |           |
-| K4/6     | hades_invalid_dl[3]           |            | LVCMOS25_OUT | PL44A        | LDQ41                    |           |
-| K5/6     | FEE_DATA_OUT[19]              |            | LVCMOS25_OUT | PL44B        | VREF1_6/LDQ41            |           |
-| K18/2    | fifo_data_out[21]             |            | LVCMOS25_OUT | PR29D        | RDQ29                    |           |
-| K19/2    | FEE_DATA_OUT[24]              |            | LVCMOS25_OUT | PR32B        | PCLKC2_1/RDQ29           |           |
-| K20/2    | fifo_data_out[10]             |            | LVCMOS25_OUT | PR32D        | PCLKC2_0/RDQ29           |           |
-| L1/6     |     unused, PULL:DOWN         |            |              | PL65C        | LDQ65                    |           |
-| L2/6     |     unused, PULL:DOWN         |            |              | PL62D        | LDQ65                    |           |
-| L3/6     | FEE_DATA_OUT[7]               |            | LVCMOS25_OUT | PL62C        | LDQ65                    |           |
-| L4/6     | fifo_data_out[19]             |            | LVCMOS25_OUT | PL44C        | LDQ41                    |           |
-| L5/6     | hades_invalid_dl[1]           |            | LVCMOS25_OUT | PL44D        | LDQ41                    |           |
-| L16/3    | FEE_DATA_OUT[8]               |            | LVCMOS25_OUT | PR38A        | GR_PCLK3_0/RDQ41         |           |
-| L17/3    | fifo_data_out[3]              |            | LVCMOS25_OUT | PR38B        | RDQ41                    |           |
-| L18/3    | last_buf_empty                |            | LVCMOS25_OUT | PR38C        | GR_PCLK3_1/RDQ41         |           |
-| L19/3    | FEE_DATA_OUT[26]              |            | LVCMOS25_OUT | PR35C        | PCLKT3_0/RDQ41           |           |
-| L20/3    | fifo_data_out[26]             |            | LVCMOS25_OUT | PR35A        | PCLKT3_1/RDQ41           |           |
-| M1/6     |     unused, PULL:DOWN         |            |              | PL65B        | LDQSN65                  |           |
-| M3/6     | fifo_data_out[1]              |            | LVCMOS25_OUT | PL62B        | LDQ65                    |           |
-| M4/6     | fifo_data_out[14]             |            | LVCMOS25_OUT | PL59A        | LDQ65                    |           |
-| M5/6     | hades_dbg2_coarse[7]          |            | LVCMOS25_OUT | PL53A        | LDQS53                   |           |
-| M17/3    | FEE_DATA_OUT[3]               |            | LVCMOS25_OUT | PR41B        | RDQSN41                  |           |
-| M18/3    | fifo_data_out[8]              |            | LVCMOS25_OUT | PR38D        | RDQ41                    |           |
-| M19/3    | FEE_DATA_OUT[15]              |            | LVCMOS25_OUT | PR35D        | PCLKC3_0/RDQ41           |           |
-| M20/3    | fifo_data_out[24]             |            | LVCMOS25_OUT | PR35B        | PCLKC3_1/RDQ41           |           |
-| N1/6     | fifo_data_out[7]              |            | LVCMOS25_OUT | PL65D        | LDQ65                    |           |
-| N2/6     |     unused, PULL:DOWN         |            |              | PL65A        | LDQS65                   |           |
-| N3/6     | FEE_DATA_OUT[1]               |            | LVCMOS25_OUT | PL62A        | LDQ65                    |           |
-| N4/6     | fifo_data_out[12]             |            | LVCMOS25_OUT | PL59C        | LDQ65                    |           |
-| N5/6     | FEE_DATA_OUT[12]              |            | LVCMOS25_OUT | PL59B        | LDQ65                    |           |
-| N16/3    | burst                         |            | LVCMOS25_OUT | PR41A        | RDQS41                   |           |
-| N17/3    | fifo_empty1                   |            | LVCMOS25_OUT | PR44A        | RDQ41                    |           |
-| N18/3    | LVL1_TRG_DATA_VALI_IN_rising  |            | LVCMOS25_OUT | PR41C        | RDQ41                    |           |
-| N19/3    | FEE_DATA_OUT[16]              |            | LVCMOS25_OUT | PR59A        | RDQ65                    |           |
-| N20/3    | hades_buf_drop[0]             |            | LVCMOS25_OUT | PR59B        | RDQ65                    |           |
-| P1/6     | hades_dbg2_out[14]            |            | LVCMOS25_OUT | PL68A        | LDQ65                    |           |
-| P2/6     |     unused, PULL:DOWN         |            |              | PL68B        | LDQ65                    |           |
-| P3/6     | clk+                          | LOCATED    | LVDS_IN      | PL68C        | LLC_GPLL0T_IN/LDQ65      |           |
-| P4/6     | clk-                          |            | LVDS_IN      | PL68D        | LLC_GPLL0C_IN/LDQ65      |           |
-| P5/6     | FEE_DATA_OUT[14]              |            | LVCMOS25_OUT | PL59D        | LDQ65                    |           |
-| P16/3    | discard                       |            | LVCMOS25_OUT | PR44B        | VREF1_3/RDQ41            |           |
-| P17/3    | fifo_data_out[0]              |            | LVCMOS25_OUT | PR41D        | RDQ41                    |           |
-| P18/3    | fifo_data_out[16]             |            | LVCMOS25_OUT | PR59D        | RDQ65                    |           |
-| P19/3    | hades_dbg2_out[13]            |            | LVCMOS25_OUT | PR59C        | RDQ65                    |           |
-| P20/3    |     unused, PULL:DOWN         |            |              | PR62A        | RDQ65                    |           |
-| PL47A/6  |     unused, PULL:DOWN         |            |              | PL47A        | LDQ53                    |           |
-| PL47B/6  |     unused, PULL:DOWN         |            |              | PL47B        | LDQ53                    |           |
-| PL47C/6  |     unused, PULL:DOWN         |            |              | PL47C        | LDQ53                    |           |
-| PL47D/6  |     unused, PULL:DOWN         |            |              | PL47D        | LDQ53                    |           |
-| PL50A/6  |     unused, PULL:DOWN         |            |              | PL50A        | LDQ53                    |           |
-| PL50B/6  |     unused, PULL:DOWN         |            |              | PL50B        | LDQ53                    |           |
-| PL50C/6  |     unused, PULL:DOWN         |            |              | PL50C        | LDQ53                    |           |
-| PL50D/6  |     unused, PULL:DOWN         |            |              | PL50D        | LDQ53                    |           |
-| PL53B/6  |     unused, PULL:DOWN         |            |              | PL53B        | LDQSN53                  |           |
-| PL53C/6  |     unused, PULL:DOWN         |            |              | PL53C        | LDQ53                    |           |
-| PL53D/6  |     unused, PULL:DOWN         |            |              | PL53D        | LDQ53                    |           |
-| PL56A/6  |     unused, PULL:DOWN         |            |              | PL56A        | LDQ53                    |           |
-| PL56B/6  |     unused, PULL:DOWN         |            |              | PL56B        | LDQ53                    |           |
-| PL56C/6  |     unused, PULL:DOWN         |            |              | PL56C        | LDQ53                    |           |
-| PL56D/6  |     unused, PULL:DOWN         |            |              | PL56D        | LDQ53                    |           |
-| PR47A/3  |     unused, PULL:DOWN         |            |              | PR47A        | RDQ53                    |           |
-| PR47B/3  |     unused, PULL:DOWN         |            |              | PR47B        | RDQ53                    |           |
-| PR47C/3  |     unused, PULL:DOWN         |            |              | PR47C        | RDQ53                    |           |
-| PR47D/3  |     unused, PULL:DOWN         |            |              | PR47D        | RDQ53                    |           |
-| PR50A/3  |     unused, PULL:DOWN         |            |              | PR50A        | RDQ53                    |           |
-| PR50B/3  |     unused, PULL:DOWN         |            |              | PR50B        | RDQ53                    |           |
-| PR50C/3  |     unused, PULL:DOWN         |            |              | PR50C        | RDQ53                    |           |
-| PR50D/3  |     unused, PULL:DOWN         |            |              | PR50D        | RDQ53                    |           |
-| PR53B/3  |     unused, PULL:DOWN         |            |              | PR53B        | RDQSN53                  |           |
-| PR53C/3  |     unused, PULL:DOWN         |            |              | PR53C        | RDQ53                    |           |
-| PR53D/3  |     unused, PULL:DOWN         |            |              | PR53D        | RDQ53                    |           |
-| PR56A/3  |     unused, PULL:DOWN         |            |              | PR56A        | RDQ53                    |           |
-| PR56B/3  |     unused, PULL:DOWN         |            |              | PR56B        | RDQ53                    |           |
-| PR56C/3  |     unused, PULL:DOWN         |            |              | PR56C        | RDQ53                    |           |
-| PR56D/3  |     unused, PULL:DOWN         |            |              | PR56D        | RDQ53                    |           |
-| PT22A/0  |     unused, PULL:DOWN         |            |              | PT22A        |                          |           |
-| PT22B/0  |     unused, PULL:DOWN         |            |              | PT22B        |                          |           |
-| PT24A/0  |     unused, PULL:DOWN         |            |              | PT24A        |                          |           |
-| PT24B/0  |     unused, PULL:DOWN         |            |              | PT24B        |                          |           |
-| PT27B/0  |     unused, PULL:DOWN         |            |              | PT27B        |                          |           |
-| PT60A/1  |     unused, PULL:DOWN         |            |              | PT60A        |                          |           |
-| PT60B/1  |     unused, PULL:DOWN         |            |              | PT60B        |                          |           |
-| PT62A/1  |     unused, PULL:DOWN         |            |              | PT62A        |                          |           |
-| PT62B/1  |     unused, PULL:DOWN         |            |              | PT62B        |                          |           |
-| PT65A/1  |     unused, PULL:DOWN         |            |              | PT65A        |                          |           |
-| PT65B/1  |     unused, PULL:DOWN         |            |              | PT65B        |                          |           |
-| PT67B/1  |     unused, PULL:DOWN         |            |              | PT67B        |                          |           |
-| R1/8     | hades_dbg2_out[19]            |            | LVCMOS25_OUT | PB4A         | D7/IO7                   |           |
-| R2/8     | trig[0]                       | LOCATED    | LVCMOS25_IN  | PB15A        | HOLDN/DI/BUSY/CSSPIN/CEN |           |
-| R3/8     | FEE_DATA_OUT[11]              |            | LVCMOS25_OUT | PB15B        | DOUT/CSON                |           |
-| R16/3    | LVL1_INVALID_TRG_IN           |            | LVCMOS25_IN  | PR44C        | RDQ41                    |           |
-| R17/3    | FEE_DATA_OUT[0]               |            | LVCMOS25_OUT | PR44D        | RDQ41                    |           |
-| R18/3    | hades_dbg2_out[31]            |            | LVCMOS25_OUT | PR65B        | RDQSN65                  |           |
-| R20/3    | hades_buf_drop[2]             |            | LVCMOS25_OUT | PR62B        | RDQ65                    |           |
-| T1/8     | fifo_data_out[29]             |            | LVCMOS25_OUT | PB4B         | D6/IO6                   |           |
-| T2/8     | FEE_DATA_OUT[22]              |            | LVCMOS25_OUT | PB13A        | SN/CSN                   |           |
-| T3/8     | trig[1]                       | LOCATED    | LVCMOS25_IN  | PB18A        | WRITEN                   |           |
-| T16/3    |     unused, PULL:DOWN         |            |              | PR53A        | RDQS53                   |           |
-| T17/3    | hades_drop_cmp_buf_coarse[10] |            | LVCMOS25_OUT | PR68D        | LRC_GPLL0C_IN/RDQ65      |           |
-| T18/3    |     unused, PULL:DOWN         |            |              | PR65D        | RDQ65                    |           |
-| T19/3    | trig[2]                       | LOCATED    | LVCMOS25_IN  | PR65A        | RDQS65                   |           |
-| T20/3    |     unused, PULL:DOWN         |            |              | PR62C        | RDQ65                    |           |
-| TCK/40   |                               |            |              | TCK          |                          |           |
-| TDI/40   |                               |            |              | TDI          |                          |           |
-| TDO/40   |                               |            |              | TDO          |                          |           |
-| TMS/40   |                               |            |              | TMS          |                          |           |
-| U1/8     | FEE_DATA_OUT[29]              |            | LVCMOS25_OUT | PB6A         | D5/MISO2/IO5             |           |
-| U2/8     | fifo_data_out[11]             |            | LVCMOS25_OUT | PB13B        | CS1N                     |           |
-| U16/3    | hades_buf_drop[3]             |            | LVCMOS25_OUT | PR68C        | LRC_GPLL0T_IN/RDQ65      |           |
-| U17/3    | hades_drop_cmp_buf[11]        |            | LVCMOS25_OUT | PR68B        | RDQ65                    |           |
-| U18/3    |     unused, PULL:DOWN         |            |              | PR68A        | RDQ65                    |           |
-| U19/3    |     unused, PULL:DOWN         |            |              | PR65C        | RDQ65                    |           |
-| U20/3    | hades_raw_valid_vect[0]       |            | LVCMOS25_OUT | PR62D        | RDQ65                    |           |
-| V1/8     | FEE_DATA_OUT[20]              |            | LVCMOS25_OUT | PB6B         | D4/MOSI2/IO4             |           |
-| V2/8     | hades_invalid_dl[0]           |            | LVCMOS25_OUT | PB11A        | D1/MISO/IO1              |           |
-| W1/8     | fifo_data_out[22]             |            | LVCMOS25_OUT | PB9A         | D3/IO3                   |           |
-| W2/8     | hades_lvl1_invalid            |            | LVCMOS25_IN  | PB11B        | D0/MOSI/IO0              |           |
-| W4/50    |                               |            |              | HDTXP0_D0CH0 |                          |           |
-| W5/50    |                               |            |              | HDTXN0_D0CH0 |                          |           |
-| W8/50    |                               |            |              | HDTXP0_D0CH1 |                          |           |
-| W9/50    |                               |            |              | HDTXN0_D0CH1 |                          |           |
-| W13/51   |                               |            |              | HDTXP0_D1CH0 |                          |           |
-| W14/51   |                               |            |              | HDTXN0_D1CH0 |                          |           |
-| W17/51   |                               |            |              | HDTXP0_D1CH1 |                          |           |
-| W18/51   |                               |            |              | HDTXN0_D1CH1 |                          |           |
-| W20/51   |                               |            |              | REFCLKN_D1   |                          |           |
-| Y2/8     | fifo_data_out[20]             |            | LVCMOS25_OUT | PB9B         | D2/IO2                   |           |
-| Y5/50    |                               |            |              | HDRXP0_D0CH0 |                          |           |
-| Y6/50    |                               |            |              | HDRXN0_D0CH0 |                          |           |
-| Y7/50    |                               |            |              | HDRXP0_D0CH1 |                          |           |
-| Y8/50    |                               |            |              | HDRXN0_D0CH1 |                          |           |
-| Y11/50   |                               |            |              | REFCLKP_D0   |                          |           |
-| Y12/50   |                               |            |              | REFCLKN_D0   |                          |           |
-| Y14/51   |                               |            |              | HDRXP0_D1CH0 |                          |           |
-| Y15/51   |                               |            |              | HDRXN0_D1CH0 |                          |           |
-| Y16/51   |                               |            |              | HDRXP0_D1CH1 |                          |           |
-| Y17/51   |                               |            |              | HDRXN0_D1CH1 |                          |           |
-| Y19/51   |                               |            |              | REFCLKP_D1   |                          |           |
-+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "FEE_DATAFINISHED_OUT"  SITE  "D13";
-LOCATE  COMP  "FEE_DATA_OUT[0]"  SITE  "R17";
-LOCATE  COMP  "FEE_DATA_OUT[10]"  SITE  "J19";
-LOCATE  COMP  "FEE_DATA_OUT[11]"  SITE  "R3";
-LOCATE  COMP  "FEE_DATA_OUT[12]"  SITE  "N5";
-LOCATE  COMP  "FEE_DATA_OUT[13]"  SITE  "G16";
-LOCATE  COMP  "FEE_DATA_OUT[14]"  SITE  "P5";
-LOCATE  COMP  "FEE_DATA_OUT[15]"  SITE  "M19";
-LOCATE  COMP  "FEE_DATA_OUT[16]"  SITE  "N19";
-LOCATE  COMP  "FEE_DATA_OUT[17]"  SITE  "B15";
-LOCATE  COMP  "FEE_DATA_OUT[18]"  SITE  "A15";
-LOCATE  COMP  "FEE_DATA_OUT[19]"  SITE  "K5";
-LOCATE  COMP  "FEE_DATA_OUT[1]"  SITE  "N3";
-LOCATE  COMP  "FEE_DATA_OUT[20]"  SITE  "V1";
-LOCATE  COMP  "FEE_DATA_OUT[21]"  SITE  "G19";
-LOCATE  COMP  "FEE_DATA_OUT[22]"  SITE  "T2";
-LOCATE  COMP  "FEE_DATA_OUT[23]"  SITE  "H20";
-LOCATE  COMP  "FEE_DATA_OUT[24]"  SITE  "K19";
-LOCATE  COMP  "FEE_DATA_OUT[25]"  SITE  "H17";
-LOCATE  COMP  "FEE_DATA_OUT[26]"  SITE  "L19";
-LOCATE  COMP  "FEE_DATA_OUT[27]"  SITE  "C20";
-LOCATE  COMP  "FEE_DATA_OUT[28]"  SITE  "F19";
-LOCATE  COMP  "FEE_DATA_OUT[29]"  SITE  "U1";
-LOCATE  COMP  "FEE_DATA_OUT[2]"  SITE  "G18";
-LOCATE  COMP  "FEE_DATA_OUT[30]"  SITE  "D20";
-LOCATE  COMP  "FEE_DATA_OUT[31]"  SITE  "H18";
-LOCATE  COMP  "FEE_DATA_OUT[3]"  SITE  "M17";
-LOCATE  COMP  "FEE_DATA_OUT[4]"  SITE  "E18";
-LOCATE  COMP  "FEE_DATA_OUT[5]"  SITE  "F16";
-LOCATE  COMP  "FEE_DATA_OUT[6]"  SITE  "A16";
-LOCATE  COMP  "FEE_DATA_OUT[7]"  SITE  "L3";
-LOCATE  COMP  "FEE_DATA_OUT[8]"  SITE  "L16";
-LOCATE  COMP  "FEE_DATA_OUT[9]"  SITE  "F20";
-LOCATE  COMP  "FEE_DATA_WRITE_OUT"  SITE  "C13";
-LOCATE  COMP  "FEE_TRG_RELEASE_OUT"  SITE  "E13";
-LOCATE  COMP  "LVL1_INVALID_TRG_IN"  SITE  "R16";
-LOCATE  COMP  "LVL1_TRG_DATA_VALID_IN"  SITE  "A9";
-LOCATE  COMP  "LVL1_TRG_DATA_VALI_IN_rising"  SITE  "N18";
-LOCATE  COMP  "burst"  SITE  "N16";
-LOCATE  COMP  "clk"  SITE  "P3";
-LOCATE  COMP  "discard"  SITE  "P16";
-LOCATE  COMP  "fifo_data_out[0]"  SITE  "P17";
-LOCATE  COMP  "fifo_data_out[10]"  SITE  "K20";
-LOCATE  COMP  "fifo_data_out[11]"  SITE  "U2";
-LOCATE  COMP  "fifo_data_out[12]"  SITE  "N4";
-LOCATE  COMP  "fifo_data_out[13]"  SITE  "J16";
-LOCATE  COMP  "fifo_data_out[14]"  SITE  "M4";
-LOCATE  COMP  "fifo_data_out[15]"  SITE  "J20";
-LOCATE  COMP  "fifo_data_out[16]"  SITE  "P18";
-LOCATE  COMP  "fifo_data_out[17]"  SITE  "C15";
-LOCATE  COMP  "fifo_data_out[18]"  SITE  "E14";
-LOCATE  COMP  "fifo_data_out[19]"  SITE  "L4";
-LOCATE  COMP  "fifo_data_out[1]"  SITE  "M3";
-LOCATE  COMP  "fifo_data_out[20]"  SITE  "Y2";
-LOCATE  COMP  "fifo_data_out[21]"  SITE  "K18";
-LOCATE  COMP  "fifo_data_out[22]"  SITE  "W1";
-LOCATE  COMP  "fifo_data_out[23]"  SITE  "J18";
-LOCATE  COMP  "fifo_data_out[24]"  SITE  "M20";
-LOCATE  COMP  "fifo_data_out[25]"  SITE  "J17";
-LOCATE  COMP  "fifo_data_out[26]"  SITE  "L20";
-LOCATE  COMP  "fifo_data_out[27]"  SITE  "D19";
-LOCATE  COMP  "fifo_data_out[28]"  SITE  "G20";
-LOCATE  COMP  "fifo_data_out[29]"  SITE  "T1";
-LOCATE  COMP  "fifo_data_out[2]"  SITE  "F17";
-LOCATE  COMP  "fifo_data_out[30]"  SITE  "E19";
-LOCATE  COMP  "fifo_data_out[31]"  SITE  "H16";
-LOCATE  COMP  "fifo_data_out[3]"  SITE  "L17";
-LOCATE  COMP  "fifo_data_out[4]"  SITE  "F18";
-LOCATE  COMP  "fifo_data_out[5]"  SITE  "D17";
-LOCATE  COMP  "fifo_data_out[6]"  SITE  "B16";
-LOCATE  COMP  "fifo_data_out[7]"  SITE  "N1";
-LOCATE  COMP  "fifo_data_out[8]"  SITE  "M18";
-LOCATE  COMP  "fifo_data_out[9]"  SITE  "E20";
-LOCATE  COMP  "fifo_empty1"  SITE  "N17";
-LOCATE  COMP  "fifo_rden"  SITE  "A19";
-LOCATE  COMP  "finished"  SITE  "D14";
-LOCATE  COMP  "hades_buf_drop[0]"  SITE  "N20";
-LOCATE  COMP  "hades_buf_drop[1]"  SITE  "A10";
-LOCATE  COMP  "hades_buf_drop[2]"  SITE  "R20";
-LOCATE  COMP  "hades_buf_drop[3]"  SITE  "U16";
-LOCATE  COMP  "hades_buf_finished"  SITE  "A4";
-LOCATE  COMP  "hades_buf_out_valid"  SITE  "C9";
-LOCATE  COMP  "hades_buf_release"  SITE  "E7";
-LOCATE  COMP  "hades_dbg2_coarse[0]"  SITE  "G5";
-LOCATE  COMP  "hades_dbg2_coarse[1]"  SITE  "H3";
-LOCATE  COMP  "hades_dbg2_coarse[2]"  SITE  "E3";
-LOCATE  COMP  "hades_dbg2_coarse[3]"  SITE  "C2";
-LOCATE  COMP  "hades_dbg2_coarse[4]"  SITE  "B6";
-LOCATE  COMP  "hades_dbg2_coarse[5]"  SITE  "B1";
-LOCATE  COMP  "hades_dbg2_coarse[6]"  SITE  "E5";
-LOCATE  COMP  "hades_dbg2_coarse[7]"  SITE  "M5";
-LOCATE  COMP  "hades_dbg2_coarse[8]"  SITE  "F1";
-LOCATE  COMP  "hades_dbg2_out[0]"  SITE  "J3";
-LOCATE  COMP  "hades_dbg2_out[10]"  SITE  "A8";
-LOCATE  COMP  "hades_dbg2_out[11]"  SITE  "D6";
-LOCATE  COMP  "hades_dbg2_out[12]"  SITE  "B8";
-LOCATE  COMP  "hades_dbg2_out[13]"  SITE  "P19";
-LOCATE  COMP  "hades_dbg2_out[14]"  SITE  "P1";
-LOCATE  COMP  "hades_dbg2_out[15]"  SITE  "C17";
-LOCATE  COMP  "hades_dbg2_out[16]"  SITE  "G3";
-LOCATE  COMP  "hades_dbg2_out[17]"  SITE  "G1";
-LOCATE  COMP  "hades_dbg2_out[18]"  SITE  "J5";
-LOCATE  COMP  "hades_dbg2_out[19]"  SITE  "R1";
-LOCATE  COMP  "hades_dbg2_out[1]"  SITE  "E2";
-LOCATE  COMP  "hades_dbg2_out[20]"  SITE  "K3";
-LOCATE  COMP  "hades_dbg2_out[21]"  SITE  "G2";
-LOCATE  COMP  "hades_dbg2_out[22]"  SITE  "H4";
-LOCATE  COMP  "hades_dbg2_out[23]"  SITE  "J4";
-LOCATE  COMP  "hades_dbg2_out[24]"  SITE  "H1";
-LOCATE  COMP  "hades_dbg2_out[25]"  SITE  "J1";
-LOCATE  COMP  "hades_dbg2_out[26]"  SITE  "K1";
-LOCATE  COMP  "hades_dbg2_out[27]"  SITE  "F2";
-LOCATE  COMP  "hades_dbg2_out[28]"  SITE  "H2";
-LOCATE  COMP  "hades_dbg2_out[29]"  SITE  "A17";
-LOCATE  COMP  "hades_dbg2_out[2]"  SITE  "F3";
-LOCATE  COMP  "hades_dbg2_out[30]"  SITE  "E16";
-LOCATE  COMP  "hades_dbg2_out[31]"  SITE  "R18";
-LOCATE  COMP  "hades_dbg2_out[3]"  SITE  "C16";
-LOCATE  COMP  "hades_dbg2_out[4]"  SITE  "E4";
-LOCATE  COMP  "hades_dbg2_out[5]"  SITE  "C3";
-LOCATE  COMP  "hades_dbg2_out[6]"  SITE  "F4";
-LOCATE  COMP  "hades_dbg2_out[7]"  SITE  "B3";
-LOCATE  COMP  "hades_dbg2_out[8]"  SITE  "E8";
-LOCATE  COMP  "hades_dbg2_out[9]"  SITE  "C7";
-LOCATE  COMP  "hades_discard"  SITE  "B11";
-LOCATE  COMP  "hades_drop_cmp_buf[0]"  SITE  "D3";
-LOCATE  COMP  "hades_drop_cmp_buf[10]"  SITE  "B17";
-LOCATE  COMP  "hades_drop_cmp_buf[11]"  SITE  "U17";
-LOCATE  COMP  "hades_drop_cmp_buf[1]"  SITE  "D9";
-LOCATE  COMP  "hades_drop_cmp_buf[2]"  SITE  "A6";
-LOCATE  COMP  "hades_drop_cmp_buf[3]"  SITE  "C6";
-LOCATE  COMP  "hades_drop_cmp_buf[4]"  SITE  "F5";
-LOCATE  COMP  "hades_drop_cmp_buf[5]"  SITE  "C4";
-LOCATE  COMP  "hades_drop_cmp_buf[6]"  SITE  "D8";
-LOCATE  COMP  "hades_drop_cmp_buf[7]"  SITE  "D5";
-LOCATE  COMP  "hades_drop_cmp_buf[8]"  SITE  "B4";
-LOCATE  COMP  "hades_drop_cmp_buf[9]"  SITE  "B20";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[0]"  SITE  "A11";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[10]"  SITE  "T17";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[11]"  SITE  "D18";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[1]"  SITE  "A13";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[2]"  SITE  "B10";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[3]"  SITE  "C12";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[4]"  SITE  "E12";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[5]"  SITE  "D12";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[6]"  SITE  "E11";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[7]"  SITE  "D11";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[8]"  SITE  "B13";
-LOCATE  COMP  "hades_drop_cmp_buf_coarse[9]"  SITE  "A12";
-LOCATE  COMP  "hades_drop_cmp_buf_valid"  SITE  "A7";
-LOCATE  COMP  "hades_hit_out_i[0]"  SITE  "E9";
-LOCATE  COMP  "hades_hit_out_i[1]"  SITE  "C11";
-LOCATE  COMP  "hades_hit_out_i[2]"  SITE  "E6";
-LOCATE  COMP  "hades_hit_out_i[3]"  SITE  "D7";
-LOCATE  COMP  "hades_hit_valid[0]"  SITE  "A3";
-LOCATE  COMP  "hades_hit_valid[1]"  SITE  "B5";
-LOCATE  COMP  "hades_hit_valid[2]"  SITE  "A5";
-LOCATE  COMP  "hades_hit_valid[3]"  SITE  "C5";
-LOCATE  COMP  "hades_invalid_dl[0]"  SITE  "V2";
-LOCATE  COMP  "hades_invalid_dl[1]"  SITE  "L5";
-LOCATE  COMP  "hades_invalid_dl[2]"  SITE  "K2";
-LOCATE  COMP  "hades_invalid_dl[3]"  SITE  "K4";
-LOCATE  COMP  "hades_lvl1"  SITE  "E1";
-LOCATE  COMP  "hades_lvl1_invalid"  SITE  "W2";
-LOCATE  COMP  "hades_offset[0]"  SITE  "D10";
-LOCATE  COMP  "hades_offset[1]"  SITE  "C10";
-LOCATE  COMP  "hades_offset[2]"  SITE  "E10";
-LOCATE  COMP  "hades_offset[3]"  SITE  "D1";
-LOCATE  COMP  "hades_offset[4]"  SITE  "C1";
-LOCATE  COMP  "hades_offset[5]"  SITE  "D2";
-LOCATE  COMP  "hades_offset[6]"  SITE  "A2";
-LOCATE  COMP  "hades_offset[7]"  SITE  "B9";
-LOCATE  COMP  "hades_offset[8]"  SITE  "B2";
-LOCATE  COMP  "hades_offset_valid"  SITE  "D15";
-LOCATE  COMP  "hades_raw_out_valid"  SITE  "E15";
-LOCATE  COMP  "hades_raw_valid_vect[0]"  SITE  "U20";
-LOCATE  COMP  "hades_raw_valid_vect[1]"  SITE  "E17";
-LOCATE  COMP  "hades_trig"  SITE  "H5";
-LOCATE  COMP  "hades_window_end"  SITE  "C14";
-LOCATE  COMP  "last_buf_empty"  SITE  "L18";
-LOCATE  COMP  "rd_clk"  SITE  "B12";
-LOCATE  COMP  "release_out"  SITE  "A14";
-LOCATE  COMP  "reset_dc"  SITE  "C8";
-LOCATE  COMP  "trig[0]"  SITE  "R2";
-LOCATE  COMP  "trig[1]"  SITE  "T3";
-LOCATE  COMP  "trig[2]"  SITE  "T19";
-
-#PLL
-LOCATE  COMP  "pll0inst/PLLInst_0"  SITE  "PLL_BL0" ;
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.11.2.446.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Jun 16 09:20:03 2021
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    - - diff --git a/impl1/s1_impl1_par.html b/impl1/s1_impl1_par.html deleted file mode 100644 index 780e93e..0000000 --- a/impl1/s1_impl1_par.html +++ /dev/null @@ -1,391 +0,0 @@ - -Place & Route Report - - -
    PAR: Place And Route Diamond (64-bit) 3.11.2.446.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-Wed Jun 16 09:19:35 2021
-
-/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t
-s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset
-/home/hadaq/mmichalek/lattice/simplified/promote.xml
-
-
-Preference file: s1_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            -2.994       209210       -1.015       9647         48           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 48 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "s1_impl1_map.ncd"
-Wed Jun 16 09:19:35 2021
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.11.2.446.
-Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf
-Preference file: s1_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file s1_impl1_map.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: 8
-Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)     187/245          76% used
-                    187/203          92% bonded
-   IOLOGIC           35/245          14% used
-
-   SLICE            692/21924         3% used
-
-   EBR                4/108           3% used
-   PLL                1/4            25% used
-
-
-Number of Signals: 1594
-Number of Connections: 3725
-
-Pin Constraint Summary:
-   7 out of 186 pins locked (3% locked).
-
-The following 5 signals are selected to use the primary clock routing resources:
-    pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0)
-    pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
-    pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0)
-    rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0)
-    pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0)
-
-
-No signal is selected as Global Set/Reset.
-.
-Starting Placer Phase 0.
-.............
-Finished Placer Phase 0.  REAL time: 8 secs 
-
-Starting Placer Phase 1.
-.................
-Placer score = 788909.
-Finished Placer Phase 1.  REAL time: 24 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  774601
-Finished Placer Phase 2.  REAL time: 25 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 1 out of 12 (8%)
-  GR_PCLK    : 0 out of 12 (0%)
-  PLL        : 1 out of 4 (25%)
-  DCS        : 0 out of 2 (0%)
-  DCC        : 0 out of 60 (0%)
-  CLKDIV     : 0 out of 4 (0%)
-
-Quadrant TL Clocks:
-  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
-  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
-  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196
-  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17
-  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12
-
-  PRIMARY  : 5 out of 16 (31%)
-
-Quadrant TR Clocks:
-  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3
-  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8
-
-  PRIMARY  : 2 out of 16 (12%)
-
-Quadrant BL Clocks:
-  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5
-  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
-  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132
-  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4
-  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4
-
-  PRIMARY  : 5 out of 16 (31%)
-
-Quadrant BR Clocks:
-  PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
-  PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
-  PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115
-  PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9
-  PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8
-
-  PRIMARY  : 5 out of 16 (31%)
-
-Edge Clocks:
-
-  No edge clock selected.
-
-
-
-
-
-+
-I/O Usage Summary (final):
-   187 out of 245 (76.3%) PIO sites used.
-   187 out of 203 (92.1%) bonded PIO sites used.
-   Number of PIO comps: 186; differential: 1.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+------------+------------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
-+----------+----------------+------------+------------+------------+
-| 0        | 27 / 27 (100%) | 2.5V       | -          | -          |
-| 1        | 29 / 33 ( 87%) | 2.5V       | -          | -          |
-| 2        | 31 / 32 ( 96%) | 2.5V       | -          | -          |
-| 3        | 27 / 33 ( 81%) | 2.5V       | -          | -          |
-| 6        | 28 / 33 ( 84%) | 2.5V       | -          | -          |
-| 7        | 32 / 32 (100%) | 2.5V       | -          | -          |
-| 8        | 13 / 13 (100%) | 2.5V       | -          | -          |
-+----------+----------------+------------+------------+------------+
-
-Total placer CPU time: 24 secs 
-
-Dumping design to file s1_impl1.dir/5_1.ncd.
-
-0 connections routed; 3725 unrouted.
-Starting router resource preassignment
-
-Completed router resource preassignment. Real time: 39 secs 
-
-Start NBR router at Wed Jun 16 09:20:14 CEST 2021
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021
-
-Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021
-Level 1, iteration 1
-21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.876ns/-158.654ns; real time: 41 secs 
-Level 2, iteration 1
-46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-159.217ns; real time: 41 secs 
-Level 3, iteration 1
-167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.962ns/-163.305ns; real time: 42 secs 
-Level 4, iteration 1
-81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-177.384ns; real time: 42 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021
-Level 1, iteration 1
-53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-171.398ns; real time: 43 secs 
-Level 4, iteration 1
-54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
-Level 4, iteration 2
-35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-180.675ns; real time: 43 secs 
-Level 4, iteration 3
-24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
-Level 4, iteration 4
-12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.068ns; real time: 43 secs 
-Level 4, iteration 5
-8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 43 secs 
-Level 4, iteration 6
-5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.304ns; real time: 44 secs 
-Level 4, iteration 7
-1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
-Level 4, iteration 8
-1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.750ns; real time: 44 secs 
-Level 4, iteration 9
-0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
-
-Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-173.131ns; real time: 44 secs 
-
-Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: -2.994ns/-172.896ns; real time: 44 secs 
-
-Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 156 (4.19%)
-  Estimated worst slack<setup> : -2.994ns
-  Timing score<setup> : 209210
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 46 secs 
-Total REAL time: 47 secs 
-Completely routed.
-End of route.  3725 routed (100.00%); 0 unrouted.
-
-Generating "par" statistics.
-
-
-   The Delay Summary Report
-
-   The SCORE FOR THIS DESIGN is: 284326
-
-
-   The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
-
-   The AVERAGE CONNECTION DELAY for this design is:          0.79 (  0.79)
-   The AVERAGE CONNECTION DELAY on CRITICAL NETS is:         0.00 (  0.00)
-   The CLOCK SKEW AVERAGE for this design is:                0.03
-   The MAXIMUM PIN DELAY IS:                                 4.32 (  4.32)
-   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:     3.37 (  3.37)
-
-   Listing Pin Delays by value: (nsec)
-
-    d <= 10    < d <= 20   < d <= 30   < d <= 40   < d <= 50    d > 50
-   ---------   ---------   ---------   ---------   ---------   ---------
-        3725           0           0           0           0           0
-
-Hold time timing score: 9, hold timing errors: 18
-
-
-Timing score: 209210 
-
-Dumping design to file s1_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = -2.994
-PAR_SUMMARY::Timing score<setup/<ns>> = 209.210
-PAR_SUMMARY::Worst  slack<hold /<ns>> = -1.015
-PAR_SUMMARY::Timing score<hold /<ns>> = 9.647
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 48 secs 
-Total REAL time to completion: 48 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
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    - - diff --git a/impl1/s1_impl1_scck.rpt b/impl1/s1_impl1_scck.rpt deleted file mode 100644 index 5daaa5a..0000000 --- a/impl1/s1_impl1_scck.rpt +++ /dev/null @@ -1,70 +0,0 @@ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 - -# Written on Wed Jun 16 09:19:17 2021 - -##### FILES SYNTAX CHECKED ############################################## -Constraint File(s): (none) - -#Run constraint checker to find more issues with constraints. -######################################################################### - - - -No issues found in constraint syntax. - - - -Clock Summary -************* - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------- -0 - System 200.0 MHz 5.000 system system_clkgroup 0 - -0 - pll0|CLKOS3_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_0 787 - -0 - top_tf|rd_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_4 64 - -0 - pll0|CLKOP_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_1 36 - -0 - pll0|CLKOS2_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_3 36 - -0 - pll0|CLKOS_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_2 36 -=============================================================================================================== - - -Clock Load Summary -****************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System 0 - - - - - -pll0|CLKOS3_inferred_clock 787 pll0inst.PLLInst_0.CLKOS3(EHXPLLL) reset_dl[2:1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv) - -top_tf|rd_clk 64 rd_clk(port) fifo_colector_inst.fifo40_inst.FF_1.CK - - - -pll0|CLKOP_inferred_clock 36 pll0inst.PLLInst_0.CLKOP(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv) - -pll0|CLKOS2_inferred_clock 36 pll0inst.PLLInst_0.CLKOS2(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv) - -pll0|CLKOS_inferred_clock 36 pll0inst.PLLInst_0.CLKOS(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv) -============================================================================================================================================================================================================================================================= diff --git a/impl1/s1_impl1_scck.rpt.db b/impl1/s1_impl1_scck.rpt.db deleted file mode 100644 index 33612a25abcc09ccda948d7859cc45d1eae869ad..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#y$ZrW3Y@Gy=5 diff --git a/impl1/s1_impl1_summary.html b/impl1/s1_impl1_summary.html deleted file mode 100644 index a6e896e..0000000 --- a/impl1/s1_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -
    
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    s1 project summary
    Module Name:s1Synthesis:SynplifyPro
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:State:
    Target Device:LFE5UM5G-45F-8BG381CDevice Family:ECP5UM5G
    Device Type:LFE5UM5G-45FPackage Type:CABGA381
    Performance grade:8Operating conditions:COM
    Logic preference file:s1.lpf
    Physical Preference file:impl1/s1_impl1.prf
    Product Version:3.11.2.446Patch Version:
    Updated:2021/06/16 12:37:07
    Implementation Location:/home/hadaq/mmichalek/lattice/simplified/impl1
    Project File:/home/hadaq/mmichalek/lattice/simplified/s1.ldf
    
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    - - diff --git a/impl1/s1_impl1_synplify.html b/impl1/s1_impl1_synplify.html deleted file mode 100644 index 20d85e7..0000000 --- a/impl1/s1_impl1_synplify.html +++ /dev/null @@ -1,1812 +0,0 @@ - -Synthesis Report - - -
    Synthesis Report
-#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
-#install: /opt/synplicity/O-2018.09-SP1
-#OS: Linux 
-#Hostname: lxhadeb07
-
-# Wed Jun 16 09:19:13 2021
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb.
-VHDL syntax check successful!
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
-@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
-@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
-@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
-@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
-@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope.
-@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared.
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
-@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out
-@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg
-Verilog syntax check successful!
-File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work.
-Running optimization stage 1 on EHXPLLL .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work.
-Running optimization stage 1 on pll0 .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work.
-Running optimization stage 1 on tdc4ddr_short .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work.
-Running optimization stage 1 on output_decoder8 .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work.
-Running optimization stage 1 on hades_LVL1_raw_out .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work.
-Running optimization stage 1 on trig_inv .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work.
-Running optimization stage 1 on hades_tdc_channel_raw_out .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work.
-Running optimization stage 1 on hades_tdc_bundle .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work.
-Running optimization stage 1 on trb_adapter .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work.
-Running optimization stage 1 on AND2 .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work.
-Running optimization stage 1 on INV .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work.
-Running optimization stage 1 on OR2 .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work.
-Running optimization stage 1 on XOR2 .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work.
-Running optimization stage 1 on ROM16X1A .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work.
-Running optimization stage 1 on PDPW16KD .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work.
-Running optimization stage 1 on FD1P3BX .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work.
-Running optimization stage 1 on FD1P3DX .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work.
-Running optimization stage 1 on FD1S3DX .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work.
-Running optimization stage 1 on FD1S3BX .......
-@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work.
-Running optimization stage 1 on CCU2C .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work.
-Running optimization stage 1 on fifo40_dc .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work.
-Running optimization stage 1 on fifo_colector .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work.
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work.
-Running optimization stage 1 on fifo32dc .......
-@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work.
-Running optimization stage 1 on tdc_channel_fifo_out .......
-Running optimization stage 1 on top_tf .......
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-
-Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Divided design in to 1 groups
-@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog "
-Compiling work_top_tf_verilog as a separate process
-Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
-
-Distributed Compiler Report
-***************************
-
-DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
-==============================================================================================================================================================================
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:16 2021
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:16 2021
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N|Running in 64-bit mode
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:17 2021
-
-###########################################################]
-Premap Report
-
-# Wed Jun 16 09:19:17 2021
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
-
-@A: MF827 |No constraint file specified.
-@N: MF284 |Setting synthesis effort to medium for the design
-@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt 
-Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-@N: MF284 |Setting synthesis effort to medium for the design
-@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
-@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
-@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@N: MH105 |UMR3 is only supported for HAPS-80.
-@N: MH105 |UMR3 is only supported for HAPS-80.
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-syn_allowed_resources : blockrams=108  set on top level netlist top_tf
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-
-Clock Summary
-******************
-
-          Start                          Requested     Requested     Clock        Clock                   Clock
-Level     Clock                          Frequency     Period        Type         Group                   Load 
----------------------------------------------------------------------------------------------------------------
-0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
-                                                                                                               
-0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
-                                                                                                               
-0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
-                                                                                                               
-0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
-                                                                                                               
-0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
-                                                                                                               
-0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
-===============================================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
-Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-System                         0         -                                      -                                                                                     -                 -                                                                    
-                                                                                                                                                                                                                                                             
-pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
-                                                                                                                                                                                                                                                             
-top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
-                                                                                                                                                                                                                                                             
-pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
-                                                                                                                                                                                                                                                             
-pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
-                                                                                                                                                                                                                                                             
-pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
-=============================================================================================================================================================================================================================================================
-
-@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
-4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
-0 instances converted, 895 sequential instances remain driven by gated/generated clocks
-
-===================================== Non-Gated/Non-Generated Clocks ======================================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
------------------------------------------------------------------------------------------------------------
-@KP:ckid0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
-===========================================================================================================
-======================================================================================== Gated/Generated Clocks ========================================================================================
-Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-@KP:ckid0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
-@KP:ckid0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
-@KP:ckid0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
-@KP:ckid0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
-========================================================================================================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Jun 16 09:19:18 2021
-
-###########################################################]
-Map & Optimize Report
-
-# Wed Jun 16 09:19:18 2021
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
-
-@N: MF284 |Setting synthesis effort to medium for the design
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-@N: MF284 |Setting synthesis effort to medium for the design
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog))
-@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog))
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-
-Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:02s		    -0.86ns		 187 /       525
-   2		0h:00m:02s		    -0.86ns		 184 /       525
-@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   3		0h:00m:04s		    -0.74ns		 186 /       526
-
-
-   4		0h:00m:04s		    -0.74ns		 186 /       526
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
-
-Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
-
-@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3].
-@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0].
-@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1].
-@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2].
-@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk.
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Wed Jun 16 09:19:25 2021
-#
-
-
-Top view:               top_tf
-Requested Frequency:    200.0 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -0.652
-
-                               Requested     Estimated      Requested     Estimated                Clock        Clock              
-Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
------------------------------------------------------------------------------------------------------------------------------------
-pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
-pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
-pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
-pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
-top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
-System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
-===================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
------------------------------------------------------------------------------------------------------------------------------------------------
-Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
------------------------------------------------------------------------------------------------------------------------------------------------
-System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
-System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
-pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
-pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
-pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
-pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
-top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
-top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
-===============================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOP_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                               Arrival          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-=============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                               Required          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-==============================================================================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS2_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                                Arrival          
-Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-==============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                                Required          
-Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                     
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-===============================================================================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS3_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                      Starting                                                               Arrival           
-Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
-                                                                      Clock                                                                                    
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
-===============================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                              Starting                                                                   Required           
-Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
-                                                              Clock                                                                                         
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-============================================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.942
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -0.652
-
-    Number of logic level(s):                7
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_0                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
-=============================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.882
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.593
-
-    Number of logic level(s):                6
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
-=============================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.882
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.593
-
-    Number of logic level(s):                6
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
-=============================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                               Arrival          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-=============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                               Required          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-==============================================================================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: top_tf|rd_clk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                         Starting                                               Arrival          
-Instance                                 Reference         Type        Pin     Net              Time        Slack
-                                         Clock                                                                   
------------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
-fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
-fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
-fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
-fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
-fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
-fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
-=================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                 Starting                                              Required          
-Instance                                         Reference         Type         Pin      Net           Time         Slack
-                                                 Clock                                                                   
--------------------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
-fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
-fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
-fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
-fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
-fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
-fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
-=========================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.686
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.103
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
-w_gcount_r29                                   Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
-wcount_r0                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
-=============================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.686
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.103
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
-w_gcount_r29                                   Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
-fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
-wcount_r1                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
-=============================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.640
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.148
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
-w_gcount_r28                                   Net          -        -       -         -           3         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
-wcount_r0                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
-=============================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                   Starting                                     Arrival          
-Instance                                                           Reference     Type     Pin     Net           Time        Slack
-                                                                   Clock                                                         
----------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
-=================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                        Starting                                       Required          
-Instance                                                                Reference     Type         Pin     Net         Time         Slack
-                                                                        Clock                                                            
------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
-=========================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um5g_45f-8
-
-Register bits: 934 of 43848 (2%)
-PIC Latch:       0
-I/O cells:       186
-Block Rams : 4 of 108 (3%)
-
-
-Details:
-AND2:           8
-CCU2C:          121
-EHXPLLL:        1
-FD1P3AX:        69
-FD1P3BX:        8
-FD1P3DX:        232
-FD1P3IX:        50
-FD1S3AX:        321
-FD1S3BX:        4
-FD1S3DX:        164
-FD1S3IX:        41
-FD1S3JX:        10
-GSR:            1
-IB:             11
-IFS1P3DX:       5
-INV:            20
-OB:             173
-OBZ:            2
-OFS1P3DX:       17
-OFS1P3IX:       13
-OR2:            4
-ORCALUT4:       180
-PDPW16KD:       4
-PUR:            1
-ROM16X1A:       96
-VHI:            25
-VLO:            6
-XOR2:           72
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
-
-Process took 0h:00m:07s realtime, 0h:00m:07s cputime
-# Wed Jun 16 09:19:25 2021
-
-###########################################################]
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    - - diff --git a/impl1/s1_impl1_synplify.lpf b/impl1/s1_impl1_synplify.lpf deleted file mode 100644 index fda6a86..0000000 --- a/impl1/s1_impl1_synplify.lpf +++ /dev/null @@ -1,45 +0,0 @@ -# -# Logical Preferences generated for Lattice by Synplify maprc, Build 4745R. -# - -# Period Constraints -#FREQUENCY NET "pll0inst/pll_clks[3]" 200.0 MHz; -#FREQUENCY NET "pll0inst/pll_clks[0]" 200.0 MHz; -#FREQUENCY NET "pll0inst/pll_clks[1]" 200.0 MHz; -#FREQUENCY NET "pll0inst/pll_clks[2]" 200.0 MHz; -#FREQUENCY PORT "rd_clk" 200.0 MHz; - - -# Output Constraints - -# Input Constraints - -# Point-to-point Delay Constraints - - - -# Block Path Constraints -#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[2]"; -#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[1]"; -#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[0]"; -#BLOCK PATH FROM CLKNET "rd_clk_c" TO CLKNET "pll0inst/pll_clks[3]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "rd_clk_c"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[1]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[0]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[2]" TO CLKNET "pll0inst/pll_clks[3]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "rd_clk_c"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[2]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[0]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[1]" TO CLKNET "pll0inst/pll_clks[3]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "rd_clk_c"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[2]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[1]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[0]" TO CLKNET "pll0inst/pll_clks[3]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "rd_clk_c"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[2]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[1]"; -#BLOCK PATH FROM CLKNET "pll0inst/pll_clks[3]" TO CLKNET "pll0inst/pll_clks[0]"; - -BLOCK ASYNCPATHS; - -# End of generated Logical Preferences. diff --git a/impl1/s1_impl1_synplify.tcl b/impl1/s1_impl1_synplify.tcl deleted file mode 100644 index bb23f2b..0000000 --- a/impl1/s1_impl1_synplify.tcl +++ /dev/null @@ -1,84 +0,0 @@ -#-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file - -#device options -set_option -technology ECP5UM5G -set_option -part LFE5UM5G_45F -set_option -package BG381C -set_option -speed_grade -8 - -#compilation/mapping options -set_option -symbolic_fsm_compiler true -set_option -resource_sharing false - -#use verilog 2001 standard option -set_option -vlog_std v2001 - -#map options -set_option -frequency 200 -set_option -maxfan 1000 -set_option -auto_constrain_io 0 -set_option -disable_io_insertion false -set_option -retiming false; set_option -pipe true -set_option -force_gsr auto -set_option -compiler_compatible 0 -set_option -dup false - -set_option -default_enum_encoding default - -#simulation options - - -#timing analysis options -set_option -num_critical_paths 3 - - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#synplifyPro options -set_option -fix_gated_and_generated_clocks 1 -set_option -update_models_cp 0 -set_option -resolve_multiple_driver 0 - - - -#-- add_file options -set_option -hdl_define -set SBP_SYNTHESIS -set_option -include_path {/home/hadaq/mmichalek/lattice/simplified} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd} -add_file -verilog {/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/modules2.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/top2.v} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd} -add_file -vhdl -lib "work" {/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/hades_modules.v} -add_file -verilog {/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v} - -#-- top module name -set_option -top_module top_tf - -#-- set result format/file last -project -result_file {/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi} - -#-- error message log file -project -log_file {s1_impl1.srf} - -#-- set any command lines input by customer - - -#-- run Synplify with 'arrange HDL file' -project -run hdl_info_gen -fileorder -project -run diff --git a/impl1/s1_impl1_synplify_tmp2.lpf b/impl1/s1_impl1_synplify_tmp2.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/s1_impl1_synplify_tmp4.lpf b/impl1/s1_impl1_synplify_tmp4.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/s1_impl1_synplify_tmp8.lpf b/impl1/s1_impl1_synplify_tmp8.lpf deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/s1_impl1_trce.asd b/impl1/s1_impl1_trce.asd deleted file mode 100644 index cf448ab..0000000 --- a/impl1/s1_impl1_trce.asd +++ /dev/null @@ -1,23 +0,0 @@ -[ActiveSupport TRCE] -; Setup Analysis -Fmax_0 = - (-); -Fmax_1 = 158.003 MHz (300.000 MHz); -Fmax_2 = 562.430 MHz (300.000 MHz); -Fmax_3 = 562.430 MHz (300.000 MHz); -Fmax_4 = 562.430 MHz (300.000 MHz); -Fmax_5 = 370.096 MHz (100.000 MHz); -Fmax_6 = 562.430 MHz (300.000 MHz); -Failed = 1 (Total 7); -Clock_ports = 2; -Clock_nets = 6; -; Hold Analysis -Fmax_0 = - (-); -Fmax_1 = -1.015 ns (0.000 ns); -Fmax_2 = 0.157 ns (0.000 ns); -Fmax_3 = 0.157 ns (0.000 ns); -Fmax_4 = 0.157 ns (0.000 ns); -Fmax_5 = - (-); -Fmax_6 = - (-); -Failed = 1 (Total 7); -Clock_ports = 2; -Clock_nets = 6; diff --git a/impl1/s1_impl1_tw1.html b/impl1/s1_impl1_tw1.html deleted file mode 100644 index a3a6db9..0000000 --- a/impl1/s1_impl1_tw1.html +++ /dev/null @@ -1,743 +0,0 @@ - -Lattice Map TRACE Report - - -
    Map TRACE Report
-
-Loading design for application trce from file s1_impl1_map.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: 8
-Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
-Wed Jun 16 09:19:34 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
-Design file:     s1_impl1_map.ncd
-Preference file: s1_impl1.prf
-Device,speed:    LFE5UM5G-45F,8
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[3]" 300.000000 MHz (78 errors)
    • 
-                3875 items scored, 78 timing errors detected.
-Warning: 181.028MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "clk" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  370.096MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-            3875 items scored, 78 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 1.095ns (weighted slack = -2.190ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
-
-   Delay:               2.537ns  (44.3% logic, 55.7% route), 5 logic levels.
-
- Constraint Details:
-
-      2.537ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
-      1.667ns delay constraint less
-      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.095ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.CLK to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5   e 0.156 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
-ROUTE        10   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
-C1TOFCO_DE  ---     0.278 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
-ROUTE         1   e 0.001 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
-FCITOF1_DE  ---     0.273 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
-ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
-CTOF_DEL    ---     0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
-ROUTE         1   e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
-                  --------
-                    2.537   (44.3% logic, 55.7% route), 5 logic levels.
-
-Warning: 181.028MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.722ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
-      3.333ns delay constraint less
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
-ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.722ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
-      3.333ns delay constraint less
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
-ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.722ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.728ns  (42.4% logic, 57.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
-      3.333ns delay constraint less
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
-ROUTE         1   e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.728   (42.4% logic, 57.6% route), 1 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.298ns
-         The internal maximum frequency of the following component is 370.096 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
-
-   Delay:               2.702ns -- based on Minimum Pulse Width
-
-Report:  370.096MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  181.028 MHz|   5 *
-                                        |             |             |
-FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks*" 300.000000    |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-1 preference(marked by "*" above) not met.
-
-----------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
-----------------------------------------------------------------------------
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/valid_fast                        |       5|      48|     61.54%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_reset_0_a2_2_0                |      10|      46|     58.97%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_1_0_S1           |       1|      33|     42.31%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/window_6[2]                       |       1|      33|     42.31%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_0                |       1|      21|     26.92%
-                                        |        |        |
-valid_fast_RNI999V                      |       9|      18|     23.08%
-                                        |        |        |
-hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
-_inst.offset_1_sqmuxa_i_0               |      11|      18|     23.08%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_4                |       1|      15|     19.23%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_2                |       1|      15|     19.23%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_reset_0_a2_c                  |       7|      14|     17.95%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/N_97                              |       3|      14|     17.95%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/discard4_0_a2_0_3                 |       3|      12|     15.38%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_s_7_0_S0             |       1|       8|     10.26%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/window_6[7]                       |       1|       8|     10.26%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/G_25_0_a3_5_0                     |       1|       8|     10.26%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/G_25_0_a3_4_0                     |       1|       8|     10.26%
-                                        |        |        |
-----------------------------------------------------------------------------
-
-
-Clock Domains Analysis
-------------------------
-
-Found 6 clocks:
-
-Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
-   No transfer within this clock domain is found
-
-Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
-   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-
-   Data transfers from:
-   Clock Domain: rd_clk_c   Source: rd_clk.PAD
-      Not reported because source and destination domains are unrelated.
-
-   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
-   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-
-Clock Domain: clk_c   Source: clk.PAD   Loads: 1
-   No transfer within this clock domain is found
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 78  Score: 41485
-Cumulative negative slack: 24538
-
-Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
-Wed Jun 16 09:19:34 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf 
-Design file:     s1_impl1_map.ncd
-Preference file: s1_impl1.prf
-Device,speed:    LFE5UM5G-45F,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[3]" 300.000000 MHz (0 errors)
    •             3875 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "clk" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-            3875 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.096ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3]  (from pll_clks[3] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3]  (to pll_clks[3] +)
-
-   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (from pll_clks[3])
-ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] (to pll_clks[3])
-                  --------
-                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.096ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
-ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.096ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
-ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.096ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.199ns  (70.9% logic, 29.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
-ROUTE         1   e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.199   (70.9% logic, 29.1% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.096 ns|   1  
-                                        |             |             |
-FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.096 ns|   1  
-                                        |             |             |
-FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.096 ns|   1  
-                                        |             |             |
-FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.096 ns|   1  
-                                        |             |             |
-FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks*" 300.000000    |             |             |
-MHz ;                                   |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 6 clocks:
-
-Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
-   No transfer within this clock domain is found
-
-Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
-   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-
-   Data transfers from:
-   Clock Domain: rd_clk_c   Source: rd_clk.PAD
-      Not reported because source and destination domains are unrelated.
-
-   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
-   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-
-Clock Domain: clk_c   Source: clk.PAD   Loads: 1
-   No transfer within this clock domain is found
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 78 (setup), 0 (hold)
-Score: 41485 (setup), 0 (hold)
-Cumulative negative slack: 24538 (24538+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
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    - - diff --git a/impl1/s1_impl1_twr.html b/impl1/s1_impl1_twr.html deleted file mode 100644 index d6ea0cc..0000000 --- a/impl1/s1_impl1_twr.html +++ /dev/null @@ -1,4240 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file s1_impl1.ncd.
-Design name: top_tf
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LFE5UM5G-45F
-Package:     CABGA381
-Performance: 8
-Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
-Package Status:                     Final          Version 1.38.
-Performance Hardware Data Status:   Final          Version 55.1.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446
-Wed Jun 16 09:20:29 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
-Design file:     s1_impl1.ncd
-Preference file: s1_impl1.prf
-Device,speed:    LFE5UM5G-45F,8
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[3]" 300.000000 MHz (280 errors)
    • 
-                3875 items scored, 280 timing errors detected.
-Warning: 158.003MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY PORT "clk" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  370.096MHz is the maximum frequency for this preference.
-
-
  • FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-Report:  562.430MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-            3875 items scored, 280 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 1.497ns (weighted slack = -2.994ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
-
-   Delay:               2.939ns  (38.2% logic, 61.8% route), 5 logic levels.
-
- Constraint Details:
-
-      2.939ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
-      1.667ns delay constraint less
-      0.000ns skew and
-      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.497ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
-ROUTE        10     0.731     R29C37C.F0 to     R31C37A.A1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
-C1TOFCO_DE  ---     0.278     R31C37A.A1 to    R31C37A.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113
-ROUTE         1     0.000    R31C37A.FCO to    R31C37B.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0
-FCITOF1_DE  ---     0.273    R31C37B.FCI to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
-ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
-CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
-ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
-                  --------
-                    2.939   (38.2% logic, 61.8% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.396ns (weighted slack = -2.792ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
-
-   Delay:               3.050ns  (22.0% logic, 78.0% route), 3 logic levels.
-
- Constraint Details:
-
-      3.050ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.396ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.050   (22.0% logic, 78.0% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.387ns (weighted slack = -2.774ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]  (to pll_clks[3] +)
-
-   Delay:               3.041ns  (22.0% logic, 78.0% route), 3 logic levels.
-
- Constraint Details:
-
-      3.041ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.387ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.435     R25C31B.F0 to   IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.041   (22.0% logic, 78.0% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26C.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
-
-   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
-
-   Delay:               3.011ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.011   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.354ns (weighted slack = -2.708ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
-
-   Delay:               3.008ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      3.008ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.354ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.639     R29C37C.Q0 to     R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.C0 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.008   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]  (to pll_clks[3] +)
-
-   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.396     R25C31B.F0 to   IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26B.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]  (to pll_clks[3] +)
-
-   Delay:               3.002ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.396     R25C31B.F0 to   IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    3.002   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L26A.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.345ns (weighted slack = -2.690ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]  (to pll_clks[3] +)
-
-   Delay:               2.999ns  (22.3% logic, 77.7% route), 3 logic levels.
-
- Constraint Details:
-
-      2.999ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds
-      1.667ns delay constraint less
-     -0.063ns skew and
-      0.076ns RST_SET requirement (totaling 1.654ns) by 1.345ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.630     R29C37C.Q0 to     R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOOFX_DEL  ---     0.239     R27C31A.D1 to   R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634
-ROUTE        11     0.306   R27C31A.OFX0 to     R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0
-CTOF_DEL    ---     0.141     R25C31B.D0 to     R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733
-ROUTE         9     1.393     R25C31B.F0 to   IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3])
-                  --------
-                    2.999   (22.3% logic, 77.7% route), 3 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.717 PLL_BL0.CLKOS3 to   IOL_L23A.CLK pll_clks[3]
-                  --------
-                    1.717   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Error: The following path exceeds requirements by 1.337ns (weighted slack = -2.674ns)
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast  (from pll_clks[3] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2]  (to pll_clks[3] +)
-
-   Delay:               2.779ns  (34.7% logic, 65.3% route), 4 logic levels.
-
- Constraint Details:
-
-      2.779ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds
-      1.667ns delay constraint less
-      0.000ns skew and
-      0.225ns LSR_SET requirement (totaling 1.442ns) by 1.337ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R29C37C.CLK to     R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3])
-ROUTE         5     0.281     R29C37C.Q0 to     R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast
-CTOF_DEL    ---     0.141     R29C37C.C0 to     R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736
-ROUTE        10     0.730     R29C37C.F0 to     R31C37B.B0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0
-CTOF1_DEL   ---     0.392     R31C37B.B0 to     R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114
-ROUTE         1     0.404     R31C37B.F1 to     R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1
-CTOF_DEL    ---     0.141     R29C37A.D0 to     R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738
-ROUTE         1     0.400     R29C37A.F0 to    R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3])
-                  --------
-                    2.779   (34.7% logic, 65.3% route), 4 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C37C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE       446     1.654 PLL_BL0.CLKOS3 to    R29C36C.CLK pll_clks[3]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-Warning: 158.003MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
-ROUTE         1     0.251      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
-ROUTE         1     0.251     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R28C6B.CLK to      R28C6B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (from pll_clks[2])
-ROUTE         1     0.251      R28C6B.Q0 to      R28C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R28C6A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
-ROUTE         1     0.251     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R66C51D.CLK to     R66C51D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (from pll_clks[2])
-ROUTE         1     0.251     R66C51D.Q0 to     R66C51A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51D.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C51A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R68C14B.CLK to     R68C14B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (from pll_clks[2])
-ROUTE         1     0.251     R68C14B.Q0 to     R68C14A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R68C14A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R25C5D.CLK to      R25C5D.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (from pll_clks[2])
-ROUTE         1     0.251      R25C5D.Q0 to      R25C5A.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5D.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R25C5A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
-ROUTE         1     0.251     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R66C41B.CLK to     R66C41B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (from pll_clks[2])
-ROUTE         1     0.251     R66C41B.Q0 to     R66C41A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41B.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to    R66C41A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6]  (from pll_clks[2] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6]  (to pll_clks[2] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R29C3D.CLK to      R29C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 (from pll_clks[2])
-ROUTE         1     0.251      R29C3D.Q0 to      R29C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] (to pll_clks[2])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3D.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654 PLL_BL0.CLKOS2 to     R29C3A.CLK pll_clks[2]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.685ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.765ns  (40.4% logic, 59.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.765ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.685ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R68C16C.CLK to     R68C16C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
-ROUTE         1     0.456     R68C16C.Q0 to     R68C16A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.765   (40.4% logic, 59.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16A.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.840ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.610ns  (50.5% logic, 49.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.610ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.840ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.308    R68C16C.CLK to     R68C16C.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1])
-ROUTE         1     0.302     R68C16C.Q1 to     R68C16C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.610   (50.5% logic, 49.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C16C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
-ROUTE         1     0.251      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
-ROUTE         1     0.251     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R29C6D.CLK to      R29C6D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 (from pll_clks[1])
-ROUTE         1     0.251      R29C6D.Q0 to      R29C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] (to pll_clks[1])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6D.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R29C6A.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R68C14D.CLK to     R68C14D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (from pll_clks[1])
-ROUTE         1     0.251     R68C14D.Q0 to     R68C14C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14D.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R66C50C.CLK to     R66C50C.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (from pll_clks[1])
-ROUTE         1     0.251     R66C50C.Q0 to     R66C50B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
-ROUTE         1     0.251      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (to pll_clks[1] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R28C5C.CLK to      R28C5C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (from pll_clks[1])
-ROUTE         1     0.251      R28C5C.Q0 to      R28C5A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to     R28C5A.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
-ROUTE         1     0.251     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     1.654  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
-ROUTE         1     0.251      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
-ROUTE         1     0.251     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R28C4D.CLK to      R28C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (from pll_clks[0])
-ROUTE         1     0.251      R28C4D.Q0 to      R28C4C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4D.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
-ROUTE         1     0.251     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R66C52D.CLK to     R66C52D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (from pll_clks[0])
-ROUTE         1     0.251     R66C52D.Q0 to     R66C52A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52D.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R68C15C.CLK to     R68C15C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (from pll_clks[0])
-ROUTE         1     0.251     R68C15C.Q0 to     R68C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R25C5B.CLK to      R25C5B.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (from pll_clks[0])
-ROUTE         1     0.251      R25C5B.Q0 to      R25C5C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.560ns  (55.2% logic, 44.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.309    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
-ROUTE         1     0.251     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.560   (55.2% logic, 44.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290    R66C43D.CLK to     R66C43D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (from pll_clks[0])
-ROUTE         1     0.251     R66C43D.Q0 to     R66C43A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43D.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 2.890ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (to pll_clks[0] -)
-
-   Delay:               0.541ns  (53.6% logic, 46.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 meets
-      3.333ns delay constraint less
-      0.000ns skew and
-     -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.290     R29C3B.CLK to      R29C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 (from pll_clks[0])
-ROUTE         1     0.251      R29C3B.Q0 to      R29C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] (to pll_clks[0])
-                  --------
-                    0.541   (53.6% logic, 46.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3B.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     1.654  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
-                  --------
-                    1.654   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 7.298ns
-         The internal maximum frequency of the following component is 370.096 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SIOLOGIC   CLK            reset_dc_MGIOL
-
-   Delay:               2.702ns -- based on Minimum Pulse Width
-
-Report:  370.096MHz is the maximum frequency for this preference.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed:  The following path meets requirements by 1.555ns
-         The internal maximum frequency of the following component is 562.430 MHz
-
- Logical Details:  Cell type  Pin name       Component name
-
-   Destination:    SLICE      CLK            hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624
-
-   Delay:               1.778ns -- based on Minimum Pulse Width
-
-Report:  562.430MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  158.003 MHz|   5 *
-                                        |             |             |
-FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-FREQUENCY PORT "clk" 100.000000 MHz ;   |  100.000 MHz|  370.096 MHz|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks*" 300.000000    |             |             |
-MHz ;                                   |  300.000 MHz|  562.430 MHz|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-1 preference(marked by "*" above) not met.
-
-----------------------------------------------------------------------------
-Critical Nets                           |   Loads|  Errors| % of total
-----------------------------------------------------------------------------
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/N_97                              |       3|     141|     50.36%
-                                        |        |        |
-hades_tdc_bundle_inst.hades_LVL1_raw_out|        |        |
-_inst.offset_1_sqmuxa_i_0               |      11|     130|     46.43%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/discard4_0_a2_0_3                 |       3|     122|     43.57%
-                                        |        |        |
-valid_fast_RNI999V                      |       9|      82|     29.29%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/valid_fast                        |       5|      82|     29.29%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_reset_0_a2_2_0                |      10|      66|     23.57%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_reset_0_a2_c                  |       7|      52|     18.57%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/window[7]                         |       3|      45|     16.07%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/window[5]                         |       3|      45|     16.07%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_4                |       1|      44|     15.71%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/window_6[2]                       |       1|      44|     15.71%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_1_0_S1           |       1|      43|     15.36%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_2                |       1|      38|     13.57%
-                                        |        |        |
-hades_tdc_bundle_inst/hades_LVL1_raw_out|        |        |
-_inst/un1_window_8_cry_0                |       1|      33|     11.79%
-                                        |        |        |
-----------------------------------------------------------------------------
-
-
-Clock Domains Analysis
-------------------------
-
-Found 6 clocks:
-
-Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
-   No transfer within this clock domain is found
-
-Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
-   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-
-   Data transfers from:
-   Clock Domain: rd_clk_c   Source: rd_clk.PAD
-      Not reported because source and destination domains are unrelated.
-
-   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
-   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-
-Clock Domain: clk_c   Source: clk.PAD   Loads: 1
-   No transfer within this clock domain is found
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 280  Score: 209210
-Cumulative negative slack: 139580
-
-Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
-Wed Jun 16 09:20:29 2021
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf 
-Design file:     s1_impl1.ncd
-Preference file: s1_impl1.prf
-Device,speed:    LFE5UM5G-45F,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY NET "clk_c" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[3]" 300.000000 MHz (18 errors)
    • 
-                3875 items scored, 18 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[2]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[1]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks[0]" 300.000000 MHz (0 errors)
    •             24 items scored, 0 timing errors detected.
-
-
  • FREQUENCY PORT "clk" 100.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-
  • FREQUENCY NET "pll_clks*" 300.000000 MHz (0 errors)
    •             0 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY NET "clk_c" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-            3875 items scored, 18 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Error: The following path exceeds requirements by 1.015ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.328ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R29C3C.CLK to      R29C3C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 (from pll_clks[0])
-ROUTE         1     0.195      R29C3C.Q0 to      R30C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] (to pll_clks[3])
-                  --------
-                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C3C.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R30C3B.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 1.015ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.328ns  (40.5% logic, 59.5% route), 1 logic levels.
-
- Constraint Details:
-
-      0.328ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R68C15A.CLK to     R68C15A.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (from pll_clks[0])
-ROUTE         1     0.195     R68C15A.Q0 to     R66C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
-                  --------
-                    0.328   (40.5% logic, 59.5% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C15A.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 1.000ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
-
- Constraint Details:
-
-      0.343ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 1.000ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R25C5C.CLK to      R25C5C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (from pll_clks[0])
-ROUTE         1     0.210      R25C5C.Q0 to      R25C8C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] (to pll_clks[3])
-                  --------
-                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C5C.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.939ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.404ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.939ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R28C4C.CLK to      R28C4C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (from pll_clks[0])
-ROUTE         1     0.271      R28C4C.Q0 to      R27C6B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] (to pll_clks[3])
-                  --------
-                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C4C.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R27C6B.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.928ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.415ns  (32.0% logic, 68.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.415ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.928ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R66C52A.CLK to     R66C52A.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (from pll_clks[0])
-ROUTE         1     0.282     R66C52A.Q0 to     R66C47D.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
-                  --------
-                    0.415   (32.0% logic, 68.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C52A.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.914ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4]  (from pll_clks[0] -)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4]  (to pll_clks[3] -)
-
-   Delay:               0.429ns  (31.0% logic, 69.0% route), 1 logic levels.
-
- Constraint Details:
-
-      0.429ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
-      0.093ns M_HLD and
-      0.000ns delay constraint less
-     -1.250ns skew less
-      0.000ns feedback compensation requirement (totaling 1.343ns) by 0.914ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R66C43A.CLK to     R66C43A.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (from pll_clks[0])
-ROUTE         1     0.296     R66C43A.Q0 to     R66C39B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3])
-                  --------
-                    0.429   (31.0% logic, 69.0% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OP_DE  ---     0.000   PLL_BL0.CLKI to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43A.CLK pll_clks[0]
-                  --------
-                    0.715   (11.5% logic, 88.5% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.588ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
-
-   Delay:               0.340ns  (39.1% logic, 60.9% route), 1 logic levels.
-
- Constraint Details:
-
-      0.340ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds
-      0.094ns M_HLD and
-      0.000ns delay constraint less
-     -0.834ns skew less
-      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.588ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R66C41C.CLK to     R66C41C.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (from pll_clks[1])
-ROUTE         1     0.207     R66C41C.Q0 to     R66C39B.M1 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
-                  --------
-                    0.340   (39.1% logic, 60.9% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C41C.CLK pll_clks[1]
-                  --------
-                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C39B.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.585ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
-
-   Delay:               0.343ns  (38.8% logic, 61.2% route), 1 logic levels.
-
- Constraint Details:
-
-      0.343ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds
-      0.094ns M_HLD and
-      0.000ns delay constraint less
-     -0.834ns skew less
-      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.585ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R66C50B.CLK to     R66C50B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (from pll_clks[1])
-ROUTE         1     0.210     R66C50B.Q0 to     R66C47D.M1 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
-                  --------
-                    0.343   (38.8% logic, 61.2% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C50B.CLK pll_clks[1]
-                  --------
-                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C47D.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.575ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
-
-   Delay:               0.353ns  (37.7% logic, 62.3% route), 1 logic levels.
-
- Constraint Details:
-
-      0.353ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds
-      0.094ns M_HLD and
-      0.000ns delay constraint less
-     -0.834ns skew less
-      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.575ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R25C4A.CLK to      R25C4A.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (from pll_clks[1])
-ROUTE         1     0.220      R25C4A.Q0 to      R25C8C.M1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] (to pll_clks[3])
-                  --------
-                    0.353   (37.7% logic, 62.3% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C4A.CLK pll_clks[1]
-                  --------
-                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to     R25C8C.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-Error: The following path exceeds requirements by 0.524ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5]  (from pll_clks[1] -)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5]  (to pll_clks[3] -)
-
-   Delay:               0.404ns  (32.9% logic, 67.1% route), 1 logic levels.
-
- Constraint Details:
-
-      0.404ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds
-      0.094ns M_HLD and
-      0.000ns delay constraint less
-     -0.834ns skew less
-      0.000ns feedback compensation requirement (totaling 0.928ns) by 0.524ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    R68C14C.CLK to     R68C14C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (from pll_clks[1])
-ROUTE         1     0.271     R68C14C.Q0 to     R66C15A.M1 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3])
-                  --------
-                    0.404   (32.9% logic, 67.1% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS_DE  ---     0.416   PLL_BL0.CLKI to  PLL_BL0.CLKOS pll0inst/PLLInst_0
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R68C14C.CLK pll_clks[1]
-                  --------
-                    1.131   (44.0% logic, 56.0% route), 2 logic levels.
-
-      Source Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-      Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-PADI_DEL    ---     0.082         P3.PAD to       P3.PADDI clk
-ROUTE         1     0.017       P3.PADDI to   PLL_BL0.CLKI clk_c
-CLKI2OS3_D  ---     1.250   PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0
-ROUTE       446     0.616 PLL_BL0.CLKOS3 to    R66C15A.CLK pll_clks[3]
-                  --------
-                    1.965   (67.8% logic, 32.2% route), 2 logic levels.
-
-      Destination Clock f/b:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-CLKFB2OP_D  ---     0.000  PLL_BL0.CLKFB to  PLL_BL0.CLKOP pll0inst/PLLInst_0
-ROUTE        25     0.654  PLL_BL0.CLKOP to  PLL_BL0.CLKFB pll_clks[0]
-                  --------
-                    0.654   (0.0% logic, 100.0% route), 1 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C52B.CLK to     R66C52B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
-ROUTE         1     0.119     R66C52B.Q1 to     R66C52B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R68C15B.CLK to     R68C15B.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
-ROUTE         1     0.119     R68C15B.Q1 to     R68C15B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R28C3B.CLK to      R28C3B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
-ROUTE         1     0.119      R28C3B.Q1 to      R28C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C42D.CLK to     R66C42D.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
-ROUTE         1     0.119     R66C42D.Q1 to     R66C42D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R25C4B.CLK to      R25C4B.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (from pll_clks[2])
-ROUTE         1     0.119      R25C4B.Q1 to      R25C4B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R25C4B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2]  (to pll_clks[2] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R29C5B.CLK to      R29C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 (from pll_clks[2])
-ROUTE         1     0.119      R29C5B.Q1 to      R29C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] (to pll_clks[2])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R29C5B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C52B.CLK to     R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2])
-ROUTE         1     0.119     R66C52B.Q0 to     R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C52C.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142     R28C3B.CLK to      R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2])
-ROUTE         1     0.119      R28C3B.Q0 to      R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to     R28C3A.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R68C15B.CLK to     R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2])
-ROUTE         1     0.119     R68C15B.Q0 to     R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R68C15D.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2]  (from pll_clks[2] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2]  (to pll_clks[2] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C42D.CLK to     R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2])
-ROUTE         1     0.119     R66C42D.Q0 to     R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42D.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616 PLL_BL0.CLKOS2 to    R66C42B.CLK pll_clks[2]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R25C3C.CLK to      R25C3C.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
-ROUTE         1     0.119      R25C3C.Q1 to      R25C3C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C44B.CLK to     R66C44B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
-ROUTE         1     0.119     R66C44B.Q1 to     R66C44B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R29C4D.CLK to      R29C4D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
-ROUTE         1     0.119      R29C4D.Q1 to      R29C4D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C51B.CLK to     R66C51B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
-ROUTE         1     0.119     R66C51B.Q1 to     R66C51B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (to pll_clks[1] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R28C3D.CLK to      R28C3D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
-ROUTE         1     0.119      R28C3D.Q1 to      R28C3D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C51B.CLK to     R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1])
-ROUTE         1     0.119     R66C51B.Q0 to     R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C51C.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142     R28C3D.CLK to      R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1])
-ROUTE         1     0.119      R28C3D.Q0 to      R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R28C3C.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142     R25C3C.CLK to      R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1])
-ROUTE         1     0.119      R25C3C.Q0 to      R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3C.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R25C3B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142     R29C4D.CLK to      R29C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1])
-ROUTE         1     0.119      R29C4D.Q0 to      R29C4A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to     R29C4A.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1]  (from pll_clks[1] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1]  (to pll_clks[1] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C44B.CLK to     R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1])
-ROUTE         1     0.119     R66C44B.Q0 to     R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44B.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        24     0.616  PLL_BL0.CLKOS to    R66C44D.CLK pll_clks[1]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-            24 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C49B.CLK to     R66C49B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
-ROUTE         1     0.119     R66C49B.Q1 to     R66C49B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R68C16D.CLK to     R68C16D.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
-ROUTE         1     0.119     R68C16D.Q1 to     R68C16D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R28C5B.CLK to      R28C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
-ROUTE         1     0.119      R28C5B.Q1 to      R28C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141    R66C43B.CLK to     R66C43B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
-ROUTE         1     0.119     R66C43B.Q1 to     R66C43B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R25C6D.CLK to      R25C6D.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (from pll_clks[0])
-ROUTE         1     0.119      R25C6D.Q1 to      R25C6D.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R25C6D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.157ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]  (to pll_clks[0] +)
-
-   Delay:               0.260ns  (54.2% logic, 45.8% route), 1 logic levels.
-
- Constraint Details:
-
-      0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.157ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.141     R29C4B.CLK to      R29C4B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 (from pll_clks[0])
-ROUTE         1     0.119      R29C4B.Q1 to      R29C4B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] (to pll_clks[0])
-                  --------
-                    0.260   (54.2% logic, 45.8% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R29C4B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C49B.CLK to     R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0])
-ROUTE         1     0.119     R66C49B.Q0 to     R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C49C.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142     R28C5B.CLK to      R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0])
-ROUTE         1     0.119      R28C5B.Q0 to      R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to     R28C5D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R68C16D.CLK to     R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0])
-ROUTE         1     0.119     R68C16D.Q0 to     R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16D.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R68C16B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.158ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0]  (from pll_clks[0] +)
-   Destination:    FF         Data in        genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0]  (to pll_clks[0] +)
-
-   Delay:               0.261ns  (54.4% logic, 45.6% route), 1 logic levels.
-
- Constraint Details:
-
-      0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets
-      0.103ns M_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling 0.103ns) by 0.158ns
-
- Physical Path Details:
-
-      Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.142    R66C43B.CLK to     R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0])
-ROUTE         1     0.119     R66C43B.Q0 to     R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0])
-                  --------
-                    0.261   (54.4% logic, 45.6% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43B.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        25     0.616  PLL_BL0.CLKOP to    R66C43C.CLK pll_clks[0]
-                  --------
-                    0.616   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-================================================================================
-Preference: FREQUENCY PORT "clk" 100.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-================================================================================
-Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ;
-            0 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY NET "clk_c" 100.000000 MHz ;  |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks[3]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|    -1.015 ns|   1 *
-                                        |             |             |
-FREQUENCY NET "pll_clks[2]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.157 ns|   1  
-                                        |             |             |
-FREQUENCY NET "pll_clks[1]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.157 ns|   1  
-                                        |             |             |
-FREQUENCY NET "pll_clks[0]" 300.000000  |             |             |
-MHz ;                                   |     0.000 ns|     0.157 ns|   1  
-                                        |             |             |
-FREQUENCY PORT "clk" 100.000000 MHz ;   |            -|            -|   0  
-                                        |             |             |
-FREQUENCY NET "pll_clks*" 300.000000    |             |             |
-MHz ;                                   |            -|            -|   0  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-1 preference(marked by "*" above) not met.
-
-No net is responsible for more than 10% of the timing errors.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 6 clocks:
-
-Clock Domain: rd_clk_c   Source: rd_clk.PAD   Loads: 38
-   No transfer within this clock domain is found
-
-Clock Domain: pll_clks[3]   Source: pll0inst/PLLInst_0.CLKOS3   Loads: 446
-   Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;
-
-   Data transfers from:
-   Clock Domain: rd_clk_c   Source: rd_clk.PAD
-      Not reported because source and destination domains are unrelated.
-
-   Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-   Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP
-      Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ;   Transfers: 12
-
-Clock Domain: pll_clks[2]   Source: pll0inst/PLLInst_0.CLKOS2   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[1]   Source: pll0inst/PLLInst_0.CLKOS   Loads: 24
-   Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ;
-
-Clock Domain: pll_clks[0]   Source: pll0inst/PLLInst_0.CLKOP   Loads: 25
-   Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ;
-
-Clock Domain: clk_c   Source: clk.PAD   Loads: 1
-   No transfer within this clock domain is found
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 18  Score: 9647
-Cumulative negative slack: 9647
-
-Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 280 (setup), 18 (hold)
-Score: 209210 (setup), 9647 (hold)
-Cumulative negative slack: 149227 (139580+9647)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
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    - - diff --git a/impl1/s1_impl1_vho.sdf b/impl1/s1_impl1_vho.sdf deleted file mode 100644 index f5b641c..0000000 --- a/impl1/s1_impl1_vho.sdf +++ /dev/null @@ -1,26828 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "top_tf") - (DATE "Wed Jun 16 09:20:42 2021") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.11.2.446") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_79") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_79I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_80") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_80I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_81") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_81I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_82") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_82I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_83") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_83I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_85") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_85I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_86") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_86I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_87") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_87I) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_88") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_88I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_89") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_89I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_90") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_90I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_91") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_91I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_92") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_92I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_93") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_93I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_94") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_94I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_95") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_95I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_96") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_96I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_97") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_97I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_98") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_98I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_99") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_99I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_100") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_100I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_101") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_101I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_102") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_102I) - (DELAY - (ABSOLUTE - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_103") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_103I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_104") - (INSTANCE hades_tdc_bundle_inst_SLICE_104I) - (DELAY - (ABSOLUTE - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I) - (DELAY - (ABSOLUTE - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I) - (DELAY - (ABSOLUTE - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I) - (DELAY - (ABSOLUTE - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F1 (352:372:392)(352:372:392)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F1 (352:372:392)(352:372:392)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F1 (352:372:392)(352:372:392)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I) - (DELAY - (ABSOLUTE - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_118") - (INSTANCE hades_tdc_bundle_inst_SLICE_118I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_119") - (INSTANCE hades_tdc_bundle_inst_SLICE_119I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_120") - (INSTANCE hades_tdc_bundle_inst_SLICE_120I) - (DELAY - (ABSOLUTE - (IOPATH D1 FCO (112:195:278)(112:195:278)) - (IOPATH C1 FCO (112:195:278)(112:195:278)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH D0 FCO (112:195:278)(112:195:278)) - (IOPATH C0 FCO (112:195:278)(112:195:278)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_121") - (INSTANCE hades_tdc_bundle_inst_SLICE_121I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_122") - (INSTANCE hades_tdc_bundle_inst_SLICE_122I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_123") - (INSTANCE hades_tdc_bundle_inst_SLICE_123I) - (DELAY - (ABSOLUTE - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_124") - (INSTANCE trb_adapter_inst_SLICE_124I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_125") - (INSTANCE fifo_colector_inst_SLICE_125I) - (DELAY - (ABSOLUTE - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_126") - (INSTANCE fifo_colector_inst_SLICE_126I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_127") - (INSTANCE fifo_colector_inst_SLICE_127I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_128") - (INSTANCE fifo_colector_inst_SLICE_128I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_129") - (INSTANCE fifo_colector_inst_SLICE_129I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_130") - (INSTANCE fifo_colector_inst_SLICE_130I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_131") - (INSTANCE fifo_colector_inst_SLICE_131I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_132") - (INSTANCE fifo_colector_inst_SLICE_132I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_133") - (INSTANCE fifo_colector_inst_SLICE_133I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_134") - (INSTANCE fifo_colector_inst_SLICE_134I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_135") - (INSTANCE fifo_colector_inst_SLICE_135I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_136") - (INSTANCE fifo_colector_inst_SLICE_136I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_137") - (INSTANCE fifo_colector_inst_SLICE_137I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_138") - (INSTANCE fifo_colector_inst_SLICE_138I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_139") - (INSTANCE fifo_colector_inst_SLICE_139I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_140") - (INSTANCE fifo_colector_inst_SLICE_140I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_141") - (INSTANCE fifo_colector_inst_SLICE_141I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_142") - (INSTANCE fifo_colector_inst_SLICE_142I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_143") - (INSTANCE fifo_colector_inst_SLICE_143I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_144") - (INSTANCE fifo_colector_inst_SLICE_144I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_145") - (INSTANCE fifo_colector_inst_SLICE_145I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_146") - (INSTANCE fifo_colector_inst_SLICE_146I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_147") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_147I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_148") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_148I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_149") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_149I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_150") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_150I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_151") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_151I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_152") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_152I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_153") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_153I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_154") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_154I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_155") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_155I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_156") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_156I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_157") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_157I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_158") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_158I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_159") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_159I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_160") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_160I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_161") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_161I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_162") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_162I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_163") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_163I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_164") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_164I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_165") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_165I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_166") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_166I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_167") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_167I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_168") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_168I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_169") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_169I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_170") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_170I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_171") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_171I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_172") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_172I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_173") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_173I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_174") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_174I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_175") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_175I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_176") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_176I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_177") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_177I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_178") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_178I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_179") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_179I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_180") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_180I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_181") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_181I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_182") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_182I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_183") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_183I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_184") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_184I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_185") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_185I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_186") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_186I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_187") - (INSTANCE fifo_colector_inst_SLICE_187I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_188") - (INSTANCE trb_adapter_inst_SLICE_188I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_189") - (INSTANCE fifo_colector_inst_SLICE_189I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_190") - (INSTANCE fifo_colector_inst_SLICE_190I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_SLICE_246") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I) - (DELAY - (ABSOLUTE - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_SLICE_326") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_SLICE_406") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_432") - (INSTANCE hades_tdc_bundle_inst_SLICE_432I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_433") - (INSTANCE hades_tdc_bundle_inst_SLICE_433I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_434") - (INSTANCE hades_tdc_bundle_inst_SLICE_434I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_435") - (INSTANCE hades_tdc_bundle_inst_SLICE_435I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_436") - (INSTANCE hades_tdc_bundle_inst_SLICE_436I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_437") - (INSTANCE hades_tdc_bundle_inst_SLICE_437I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_438") - (INSTANCE hades_tdc_bundle_inst_SLICE_438I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_439") - (INSTANCE hades_tdc_bundle_inst_SLICE_439I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_440") - (INSTANCE hades_tdc_bundle_inst_SLICE_440I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_441") - (INSTANCE hades_tdc_bundle_inst_SLICE_441I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_442") - (INSTANCE hades_tdc_bundle_inst_SLICE_442I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_443") - (INSTANCE hades_tdc_bundle_inst_SLICE_443I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_445") - (INSTANCE hades_tdc_bundle_inst_SLICE_445I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_446") - (INSTANCE hades_tdc_bundle_inst_SLICE_446I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_447") - (INSTANCE hades_tdc_bundle_inst_SLICE_447I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_448") - (INSTANCE hades_tdc_bundle_inst_SLICE_448I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_449") - (INSTANCE hades_tdc_bundle_inst_SLICE_449I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_450") - (INSTANCE hades_tdc_bundle_inst_SLICE_450I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_451") - (INSTANCE hades_tdc_bundle_inst_SLICE_451I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_452") - (INSTANCE hades_tdc_bundle_inst_SLICE_452I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_453") - (INSTANCE hades_tdc_bundle_inst_SLICE_453I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_454") - (INSTANCE hades_tdc_bundle_inst_SLICE_454I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_455") - (INSTANCE hades_tdc_bundle_inst_SLICE_455I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_456") - (INSTANCE hades_tdc_bundle_inst_SLICE_456I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_457") - (INSTANCE hades_tdc_bundle_inst_SLICE_457I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_458") - (INSTANCE hades_tdc_bundle_inst_SLICE_458I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_459") - (INSTANCE hades_tdc_bundle_inst_SLICE_459I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_460") - (INSTANCE hades_tdc_bundle_inst_SLICE_460I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD CE (posedge CLK) (-88:-86:-85)(88:89:90)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (negedge CLK) (-148:-148:-148)(148:156:164)) - (SETUPHOLD DI0 (negedge CLK) (-148:-148:-148)(148:156:164)) - (SETUPHOLD LSR (negedge CLK) (165:204:243)(-165:-151:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (negedge CLK) (-166:-157:-148)(166:173:181)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - (IOPATH CLK Q1 (237:263:289)(237:263:289)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M1 (negedge CLK) (-134:-116:-99)(134:149:164)) - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_628") - (INSTANCE hades_tdc_bundle_inst_SLICE_628I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_631") - (INSTANCE trb_adapter_inst_SLICE_631I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M1 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_632") - (INSTANCE trb_adapter_inst_SLICE_632I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_633") - (INSTANCE trb_adapter_inst_SLICE_633I) - (DELAY - (ABSOLUTE - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_648") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_648I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_649") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_649I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (156:197:239)(156:197:239)) - (IOPATH C1 OFX0 (156:197:239)(156:197:239)) - (IOPATH B1 OFX0 (156:197:239)(156:197:239)) - (IOPATH A1 OFX0 (156:197:239)(156:197:239)) - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_653") - (INSTANCE hades_tdc_bundle_inst_SLICE_653I) - (DELAY - (ABSOLUTE - (IOPATH D0 OFX0 (156:197:239)(156:197:239)) - (IOPATH C0 OFX0 (156:197:239)(156:197:239)) - (IOPATH B0 OFX0 (156:197:239)(156:197:239)) - (IOPATH A0 OFX0 (156:197:239)(156:197:239)) - (IOPATH M0 OFX0 (113:132:151)(113:132:151)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_654") - (INSTANCE hades_tdc_bundle_inst_SLICE_654I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_673") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_673I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_674") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_674I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_675") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_675I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_676") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_676I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_677") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_677I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_678") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_678I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_679") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_679I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_680") - (INSTANCE fifo_colector_inst_SLICE_680I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_681") - (INSTANCE hades_tdc_bundle_inst_SLICE_681I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_683") - (INSTANCE hades_tdc_bundle_inst_SLICE_683I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_691") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_691I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_692") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_692I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_693") - (INSTANCE hades_tdc_bundle_inst_SLICE_693I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_698") - (INSTANCE hades_tdc_bundle_inst_SLICE_698I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_701") - (INSTANCE hades_tdc_bundle_inst_SLICE_701I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_702") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_702I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_703") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_703I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_710") - (INSTANCE hades_tdc_bundle_inst_SLICE_710I) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (119:130:141)(119:130:141)) - (IOPATH C1 F1 (119:130:141)(119:130:141)) - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_SLICE_711") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_SLICE_714") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_SLICE_717") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - (SETUPHOLD LSR (negedge CLK) (164:203:243)(-164:-150:-137)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I) - (DELAY - (ABSOLUTE - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_720") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_720I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_SLICE_721") - (INSTANCE fifo_colector_inst_fifo40_inst_SLICE_721I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_SLICE_722") - (INSTANCE fifo_colector_inst_SLICE_722I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_723") - (INSTANCE trb_adapter_inst_SLICE_723I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "trb_adapter_inst_SLICE_724") - (INSTANCE trb_adapter_inst_SLICE_724I) - (DELAY - (ABSOLUTE - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732") - (INSTANCE hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (239:264:290)(239:264:290)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - (TIMINGCHECK - (SETUPHOLD M0 (negedge CLK) (-134:-116:-98)(134:148:163)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739") - (INSTANCE hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_740") - (INSTANCE SLICE_740I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - ) - ) - (TIMINGCHECK - (SETUPHOLD M0 (posedge CLK) (-153:-135:-117)(153:167:181)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "hades_tdc_bundle_inst_SLICE_741") - (INSTANCE hades_tdc_bundle_inst_SLICE_741I) - (DELAY - (ABSOLUTE - (IOPATH C0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_743") - (INSTANCE SLICE_743I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_744") - (INSTANCE SLICE_744I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_745") - (INSTANCE SLICE_745I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_746") - (INSTANCE SLICE_746I) - (DELAY - (ABSOLUTE - (IOPATH D0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "SLICE_747") - (INSTANCE SLICE_747I) - (DELAY - (ABSOLUTE - (IOPATH A0 F0 (119:130:141)(119:130:141)) - ) - ) - ) - (CELL - (CELLTYPE "hades_raw_valid_vect_0_B") - (INSTANCE hades_raw_valid_vect_0_I) - ) - (CELL - (CELLTYPE "fifo_data_out_0_B") - (INSTANCE fifo_data_out_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "clkB") - (INSTANCE clkI) - (DELAY - (ABSOLUTE - (IOPATH clkS PADDI (437:437:437)(437:437:437)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge clkS) (1250:1250:1250)) - (WIDTH (negedge clkS) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_validB") - (INSTANCE hades_drop_cmp_buf_validI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufvalid (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_11_B") - (INSTANCE hades_drop_cmp_buf_coarse_11_I) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_10_B") - (INSTANCE hades_drop_cmp_buf_coarse_10_I) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_9_B") - (INSTANCE hades_drop_cmp_buf_coarse_9_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse9 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_8_B") - (INSTANCE hades_drop_cmp_buf_coarse_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_7_B") - (INSTANCE hades_drop_cmp_buf_coarse_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_6_B") - (INSTANCE hades_drop_cmp_buf_coarse_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_5_B") - (INSTANCE hades_drop_cmp_buf_coarse_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_4_B") - (INSTANCE hades_drop_cmp_buf_coarse_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_3_B") - (INSTANCE hades_drop_cmp_buf_coarse_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_2_B") - (INSTANCE hades_drop_cmp_buf_coarse_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_1_B") - (INSTANCE hades_drop_cmp_buf_coarse_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_coarse_0_B") - (INSTANCE hades_drop_cmp_buf_coarse_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbufcoarse0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_11_B") - (INSTANCE hades_drop_cmp_buf_11_I) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_10_B") - (INSTANCE hades_drop_cmp_buf_10_I) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_9_B") - (INSTANCE hades_drop_cmp_buf_9_I) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_8_B") - (INSTANCE hades_drop_cmp_buf_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_7_B") - (INSTANCE hades_drop_cmp_buf_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_6_B") - (INSTANCE hades_drop_cmp_buf_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_5_B") - (INSTANCE hades_drop_cmp_buf_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_4_B") - (INSTANCE hades_drop_cmp_buf_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_3_B") - (INSTANCE hades_drop_cmp_buf_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_2_B") - (INSTANCE hades_drop_cmp_buf_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_1_B") - (INSTANCE hades_drop_cmp_buf_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_drop_cmp_buf_0_B") - (INSTANCE hades_drop_cmp_buf_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdropcmpbuf0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_8_B") - (INSTANCE hades_dbg2_coarse_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_7_B") - (INSTANCE hades_dbg2_coarse_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_6_B") - (INSTANCE hades_dbg2_coarse_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_5_B") - (INSTANCE hades_dbg2_coarse_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_4_B") - (INSTANCE hades_dbg2_coarse_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_3_B") - (INSTANCE hades_dbg2_coarse_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_2_B") - (INSTANCE hades_dbg2_coarse_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_1_B") - (INSTANCE hades_dbg2_coarse_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_coarse_0_B") - (INSTANCE hades_dbg2_coarse_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2coarse0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_31_B") - (INSTANCE hades_dbg2_out_31_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_30_B") - (INSTANCE hades_dbg2_out_30_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_29_B") - (INSTANCE hades_dbg2_out_29_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_28_B") - (INSTANCE hades_dbg2_out_28_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out28 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_28_MGIOL") - (INSTANCE hades_dbg2_out_28_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_27_B") - (INSTANCE hades_dbg2_out_27_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out27 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_27_MGIOL") - (INSTANCE hades_dbg2_out_27_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_26_B") - (INSTANCE hades_dbg2_out_26_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out26 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_26_MGIOL") - (INSTANCE hades_dbg2_out_26_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_25_B") - (INSTANCE hades_dbg2_out_25_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out25 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_25_MGIOL") - (INSTANCE hades_dbg2_out_25_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_24_B") - (INSTANCE hades_dbg2_out_24_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out24 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_24_MGIOL") - (INSTANCE hades_dbg2_out_24_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_23_B") - (INSTANCE hades_dbg2_out_23_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out23 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_23_MGIOL") - (INSTANCE hades_dbg2_out_23_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_22_B") - (INSTANCE hades_dbg2_out_22_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out22 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_22_MGIOL") - (INSTANCE hades_dbg2_out_22_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_21_B") - (INSTANCE hades_dbg2_out_21_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out21 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_21_MGIOL") - (INSTANCE hades_dbg2_out_21_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_20_B") - (INSTANCE hades_dbg2_out_20_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out20 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_20_MGIOL") - (INSTANCE hades_dbg2_out_20_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_19_B") - (INSTANCE hades_dbg2_out_19_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_18_B") - (INSTANCE hades_dbg2_out_18_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out18 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_18_MGIOL") - (INSTANCE hades_dbg2_out_18_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_17_B") - (INSTANCE hades_dbg2_out_17_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out17 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_17_MGIOL") - (INSTANCE hades_dbg2_out_17_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_16_B") - (INSTANCE hades_dbg2_out_16_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out16 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_16_MGIOL") - (INSTANCE hades_dbg2_out_16_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_15_B") - (INSTANCE hades_dbg2_out_15_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_14_B") - (INSTANCE hades_dbg2_out_14_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_13_B") - (INSTANCE hades_dbg2_out_13_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_12_B") - (INSTANCE hades_dbg2_out_12_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out12 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_11_B") - (INSTANCE hades_dbg2_out_11_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out11 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_10_B") - (INSTANCE hades_dbg2_out_10_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out10 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_9_B") - (INSTANCE hades_dbg2_out_9_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out9 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_8_B") - (INSTANCE hades_dbg2_out_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_7_B") - (INSTANCE hades_dbg2_out_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_6_B") - (INSTANCE hades_dbg2_out_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_5_B") - (INSTANCE hades_dbg2_out_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_4_B") - (INSTANCE hades_dbg2_out_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdbg2out4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_3_B") - (INSTANCE hades_dbg2_out_3_I) - ) - (CELL - (CELLTYPE "hades_dbg2_out_2_B") - (INSTANCE hades_dbg2_out_2_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_2_MGIOL") - (INSTANCE hades_dbg2_out_2_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_1_B") - (INSTANCE hades_dbg2_out_1_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_1_MGIOL") - (INSTANCE hades_dbg2_out_1_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_0_B") - (INSTANCE hades_dbg2_out_0_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesdbg2out0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_dbg2_out_0_MGIOL") - (INSTANCE hades_dbg2_out_0_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_buf_drop_3_B") - (INSTANCE hades_buf_drop_3_I) - ) - (CELL - (CELLTYPE "hades_buf_drop_2_B") - (INSTANCE hades_buf_drop_2_I) - ) - (CELL - (CELLTYPE "hades_buf_drop_1_B") - (INSTANCE hades_buf_drop_1_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesbufdrop1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_buf_drop_1_MGIOL") - (INSTANCE hades_buf_drop_1_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_buf_drop_0_B") - (INSTANCE hades_buf_drop_0_I) - ) - (CELL - (CELLTYPE "hades_invalid_dl_3_B") - (INSTANCE hades_invalid_dl_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesinvaliddl3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_invalid_dl_2_B") - (INSTANCE hades_invalid_dl_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesinvaliddl2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_invalid_dl_1_B") - (INSTANCE hades_invalid_dl_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesinvaliddl1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_invalid_dl_0_B") - (INSTANCE hades_invalid_dl_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesinvaliddl0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_discardB") - (INSTANCE hades_discardI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesdiscard (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_valid_3_B") - (INSTANCE hades_hit_valid_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitvalid3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_valid_2_B") - (INSTANCE hades_hit_valid_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitvalid2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_valid_1_B") - (INSTANCE hades_hit_valid_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitvalid1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_valid_0_B") - (INSTANCE hades_hit_valid_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitvalid0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_out_i_3_B") - (INSTANCE hades_hit_out_i_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitouti3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_out_i_2_B") - (INSTANCE hades_hit_out_i_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitouti2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_out_i_1_B") - (INSTANCE hades_hit_out_i_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitouti1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_hit_out_i_0_B") - (INSTANCE hades_hit_out_i_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeshitouti0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_buf_finishedB") - (INSTANCE hades_buf_finishedI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesbuffinished (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_buf_releaseB") - (INSTANCE hades_buf_releaseI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesbufrelease (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_buf_out_validB") - (INSTANCE hades_buf_out_validI) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesbufoutvalid (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_buf_out_valid_MGIOL") - (INSTANCE hades_buf_out_valid_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_window_endB") - (INSTANCE hades_window_endI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadeswindowend (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_validB") - (INSTANCE hades_offset_validI) - (DELAY - (ABSOLUTE - (IOPATH PADDO hadesoffsetvalid (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_8_B") - (INSTANCE hades_offset_8_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_8_MGIOL") - (INSTANCE hades_offset_8_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_7_B") - (INSTANCE hades_offset_7_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_7_MGIOL") - (INSTANCE hades_offset_7_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_6_B") - (INSTANCE hades_offset_6_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_6_MGIOL") - (INSTANCE hades_offset_6_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_5_B") - (INSTANCE hades_offset_5_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_5_MGIOL") - (INSTANCE hades_offset_5_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_4_B") - (INSTANCE hades_offset_4_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_4_MGIOL") - (INSTANCE hades_offset_4_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_3_B") - (INSTANCE hades_offset_3_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_3_MGIOL") - (INSTANCE hades_offset_3_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_2_B") - (INSTANCE hades_offset_2_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_2_MGIOL") - (INSTANCE hades_offset_2_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_1_B") - (INSTANCE hades_offset_1_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_1_MGIOL") - (INSTANCE hades_offset_1_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_offset_0_B") - (INSTANCE hades_offset_0_I) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesoffset0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_offset_0_MGIOL") - (INSTANCE hades_offset_0_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD CE (posedge CLK) (-27:-27:-27)(48:48:48)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_lvl1_invalidB") - (INSTANCE hades_lvl1_invalidI) - (DELAY - (ABSOLUTE - (IOPATH hadeslvl1invalid PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge hadeslvl1invalid) (2500:2500:2500)) - (WIDTH (negedge hadeslvl1invalid) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "hades_lvl1_invalid_MGIOL") - (INSTANCE hades_lvl1_invalid_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK INFF (301:301:301)(301:301:301)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_lvl1B") - (INSTANCE hades_lvl1I) - (DELAY - (ABSOLUTE - (IOPATH hadeslvl1 PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge hadeslvl1) (2500:2500:2500)) - (WIDTH (negedge hadeslvl1) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "hades_lvl1_MGIOL") - (INSTANCE hades_lvl1_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK INFF (301:301:301)(301:301:301)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_raw_valid_vect_1_B") - (INSTANCE hades_raw_valid_vect_1_I) - ) - (CELL - (CELLTYPE "hades_raw_out_validB") - (INSTANCE hades_raw_out_validI) - (DELAY - (ABSOLUTE - (IOPATH IOLDO hadesrawoutvalid (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "hades_raw_out_valid_MGIOL") - (INSTANCE hades_raw_out_valid_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "hades_trigB") - (INSTANCE hades_trigI) - (DELAY - (ABSOLUTE - (IOPATH hadestrig PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge hadestrig) (2500:2500:2500)) - (WIDTH (negedge hadestrig) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "release_outB") - (INSTANCE release_outI) - (DELAY - (ABSOLUTE - (IOPATH PADDO releaseout (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "finishedB") - (INSTANCE finishedI) - (DELAY - (ABSOLUTE - (IOPATH PADDO finishedS (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "last_buf_emptyB") - (INSTANCE last_buf_emptyI) - (DELAY - (ABSOLUTE - (IOPATH PADDO lastbufempty (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "discardB") - (INSTANCE discardI) - (DELAY - (ABSOLUTE - (IOPATH PADDO discardS (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "burstB") - (INSTANCE burstI) - (DELAY - (ABSOLUTE - (IOPATH PADDO burstS (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "LVL1_TRG_DATA_VALI_IN_risingB") - (INSTANCE LVL1_TRG_DATA_VALI_IN_risingI) - (DELAY - (ABSOLUTE - (IOPATH PADDO LVL1TRGDATAVALIINrising (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_TRG_RELEASE_OUTB") - (INSTANCE FEE_TRG_RELEASE_OUTI) - (DELAY - (ABSOLUTE - (IOPATH IOLDO FEETRGRELEASEOUT (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_TRG_RELEASE_OUT_MGIOL") - (INSTANCE FEE_TRG_RELEASE_OUT_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "FEE_DATAFINISHED_OUTB") - (INSTANCE FEE_DATAFINISHED_OUTI) - (DELAY - (ABSOLUTE - (IOPATH IOLDO FEEDATAFINISHEDOUT (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATAFINISHED_OUT_MGIOL") - (INSTANCE FEE_DATAFINISHED_OUT_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_WRITE_OUTB") - (INSTANCE FEE_DATA_WRITE_OUTI) - (DELAY - (ABSOLUTE - (IOPATH IOLDO FEEDATAWRITEOUT (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_WRITE_OUT_MGIOL") - (INSTANCE FEE_DATA_WRITE_OUT_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK IOLDO (841:841:841)(841:841:841)) - ) - ) - (TIMINGCHECK - (SETUPHOLD TXDATA0 (posedge CLK) (93:93:93)(-73:-73:-73)) - (SETUPHOLD LSR (posedge CLK) (76:76:76)(-71:-71:-71)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_31_B") - (INSTANCE FEE_DATA_OUT_31_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT31 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_30_B") - (INSTANCE FEE_DATA_OUT_30_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT30 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_29_B") - (INSTANCE FEE_DATA_OUT_29_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT29 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_28_B") - (INSTANCE FEE_DATA_OUT_28_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT28 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_27_B") - (INSTANCE FEE_DATA_OUT_27_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT27 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_26_B") - (INSTANCE FEE_DATA_OUT_26_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT26 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_25_B") - (INSTANCE FEE_DATA_OUT_25_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT25 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_24_B") - (INSTANCE FEE_DATA_OUT_24_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT24 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_23_B") - (INSTANCE FEE_DATA_OUT_23_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT23 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_22_B") - (INSTANCE FEE_DATA_OUT_22_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT22 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_21_B") - (INSTANCE FEE_DATA_OUT_21_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT21 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_20_B") - (INSTANCE FEE_DATA_OUT_20_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT20 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_19_B") - (INSTANCE FEE_DATA_OUT_19_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT19 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_18_B") - (INSTANCE FEE_DATA_OUT_18_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT18 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_17_B") - (INSTANCE FEE_DATA_OUT_17_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT17 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_16_B") - (INSTANCE FEE_DATA_OUT_16_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT16 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_15_B") - (INSTANCE FEE_DATA_OUT_15_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT15 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_14_B") - (INSTANCE FEE_DATA_OUT_14_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT14 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_13_B") - (INSTANCE FEE_DATA_OUT_13_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT13 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_12_B") - (INSTANCE FEE_DATA_OUT_12_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT12 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_11_B") - (INSTANCE FEE_DATA_OUT_11_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT11 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_10_B") - (INSTANCE FEE_DATA_OUT_10_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT10 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_9_B") - (INSTANCE FEE_DATA_OUT_9_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT9 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_8_B") - (INSTANCE FEE_DATA_OUT_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_7_B") - (INSTANCE FEE_DATA_OUT_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_6_B") - (INSTANCE FEE_DATA_OUT_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_5_B") - (INSTANCE FEE_DATA_OUT_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_4_B") - (INSTANCE FEE_DATA_OUT_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_3_B") - (INSTANCE FEE_DATA_OUT_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_2_B") - (INSTANCE FEE_DATA_OUT_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_1_B") - (INSTANCE FEE_DATA_OUT_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "FEE_DATA_OUT_0_B") - (INSTANCE FEE_DATA_OUT_0_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO FEEDATAOUT0 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "LVL1_INVALID_TRG_INB") - (INSTANCE LVL1_INVALID_TRG_INI) - (DELAY - (ABSOLUTE - (IOPATH LVL1INVALIDTRGIN PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LVL1INVALIDTRGIN) (2500:2500:2500)) - (WIDTH (negedge LVL1INVALIDTRGIN) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "LVL1_INVALID_TRG_IN_MGIOL") - (INSTANCE LVL1_INVALID_TRG_IN_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK INFF (301:301:301)(301:301:301)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "LVL1_TRG_DATA_VALID_INB") - (INSTANCE LVL1_TRG_DATA_VALID_INI) - (DELAY - (ABSOLUTE - (IOPATH LVL1TRGDATAVALIDIN PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge LVL1TRGDATAVALIDIN) (2500:2500:2500)) - (WIDTH (negedge LVL1TRGDATAVALIDIN) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "LVL1_TRG_DATA_VALID_IN_MGIOL") - (INSTANCE LVL1_TRG_DATA_VALID_IN_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK INFF (301:301:301)(301:301:301)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "fifo_empty1B") - (INSTANCE fifo_empty1I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifoempty1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_rdenB") - (INSTANCE fifo_rdenI) - (DELAY - (ABSOLUTE - (IOPATH PADDO fiforden (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_31_B") - (INSTANCE fifo_data_out_31_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout31 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_30_B") - (INSTANCE fifo_data_out_30_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout30 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_29_B") - (INSTANCE fifo_data_out_29_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout29 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_28_B") - (INSTANCE fifo_data_out_28_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout28 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_27_B") - (INSTANCE fifo_data_out_27_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout27 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_26_B") - (INSTANCE fifo_data_out_26_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout26 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_25_B") - (INSTANCE fifo_data_out_25_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout25 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_24_B") - (INSTANCE fifo_data_out_24_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout24 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_23_B") - (INSTANCE fifo_data_out_23_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout23 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_22_B") - (INSTANCE fifo_data_out_22_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout22 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_21_B") - (INSTANCE fifo_data_out_21_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout21 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_20_B") - (INSTANCE fifo_data_out_20_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout20 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_19_B") - (INSTANCE fifo_data_out_19_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout19 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_18_B") - (INSTANCE fifo_data_out_18_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout18 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_17_B") - (INSTANCE fifo_data_out_17_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout17 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_16_B") - (INSTANCE fifo_data_out_16_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout16 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_15_B") - (INSTANCE fifo_data_out_15_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout15 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_14_B") - (INSTANCE fifo_data_out_14_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout14 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_13_B") - (INSTANCE fifo_data_out_13_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout13 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_12_B") - (INSTANCE fifo_data_out_12_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout12 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_11_B") - (INSTANCE fifo_data_out_11_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout11 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_10_B") - (INSTANCE fifo_data_out_10_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout10 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_9_B") - (INSTANCE fifo_data_out_9_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout9 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_8_B") - (INSTANCE fifo_data_out_8_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout8 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_7_B") - (INSTANCE fifo_data_out_7_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout7 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_6_B") - (INSTANCE fifo_data_out_6_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout6 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_5_B") - (INSTANCE fifo_data_out_5_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout5 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_4_B") - (INSTANCE fifo_data_out_4_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout4 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_3_B") - (INSTANCE fifo_data_out_3_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout3 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_2_B") - (INSTANCE fifo_data_out_2_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout2 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "fifo_data_out_1_B") - (INSTANCE fifo_data_out_1_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO fifodataout1 (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "trig_2_B") - (INSTANCE trig_2_I) - (DELAY - (ABSOLUTE - (IOPATH trig2 PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge trig2) (2500:2500:2500)) - (WIDTH (negedge trig2) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "trig_1_B") - (INSTANCE trig_1_I) - (DELAY - (ABSOLUTE - (IOPATH trig1 PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge trig1) (2500:2500:2500)) - (WIDTH (negedge trig1) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "trig_0_B") - (INSTANCE trig_0_I) - (DELAY - (ABSOLUTE - (IOPATH trig0 PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge trig0) (2500:2500:2500)) - (WIDTH (negedge trig0) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "reset_dcB") - (INSTANCE reset_dcI) - (DELAY - (ABSOLUTE - (IOPATH resetdc PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge resetdc) (2500:2500:2500)) - (WIDTH (negedge resetdc) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "reset_dc_MGIOL") - (INSTANCE reset_dc_MGIOLI) - (DELAY - (ABSOLUTE - (IOPATH CLK INFF (301:301:301)(301:301:301)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (264:264:264)(215:215:215)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1351:1351:1351)) - (WIDTH (negedge CLK) (1351:1351:1351)) - ) - ) - (CELL - (CELLTYPE "rd_clkB") - (INSTANCE rd_clkI) - (DELAY - (ABSOLUTE - (IOPATH rdclk PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge rdclk) (2500:2500:2500)) - (WIDTH (negedge rdclk) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0") - (INSTANCE genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I) - (DELAY - (ABSOLUTE - (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22)) - (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14)) - (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18)) - (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17)) - ) - (TIMINGCHECK - (WIDTH (posedge CLKA) (562:562:562)) - (WIDTH (negedge CLKA) (562:562:562)) - (WIDTH (posedge CLKB) (561:561:561)) - (WIDTH (negedge CLKB) (561:561:561)) - ) - ) - (CELL - (CELLTYPE "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0") - (INSTANCE genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I) - (DELAY - (ABSOLUTE - (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22)) - (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14)) - (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18)) - (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17)) - ) - (TIMINGCHECK - (WIDTH (posedge CLKA) (562:562:562)) - (WIDTH (negedge CLKA) (562:562:562)) - (WIDTH (posedge CLKB) (561:561:561)) - (WIDTH (negedge CLKB) (561:561:561)) - ) - ) - (CELL - (CELLTYPE "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0") - (INSTANCE genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I) - (DELAY - (ABSOLUTE - (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22)) - (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14)) - (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18)) - (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17)) - ) - (TIMINGCHECK - (WIDTH (posedge CLKA) (562:562:562)) - (WIDTH (negedge CLKA) (562:562:562)) - (WIDTH (posedge CLKB) (561:561:561)) - (WIDTH (negedge CLKB) (561:561:561)) - ) - ) - (CELL - (CELLTYPE "fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1") - (INSTANCE fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I) - (DELAY - (ABSOLUTE - (IOPATH CLKB DOA17 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA16 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA15 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA14 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA13 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA12 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA11 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA10 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA9 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA8 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA7 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA6 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA5 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA4 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA3 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA2 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA1 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOA0 (1412:1415:1418)(1412:1415:1418)) - (IOPATH CLKB DOB0 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB1 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB2 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB3 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB4 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB5 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB6 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB7 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB8 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB9 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB10 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB11 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB12 (1417:1420:1424)(1417:1420:1424)) - (IOPATH CLKB DOB13 (1417:1420:1424)(1417:1420:1424)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DIA17 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA16 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA15 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA14 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA13 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA12 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA11 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA10 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA9 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA8 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA7 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA6 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA5 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA4 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA3 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA2 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA1 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD DIA0 (posedge CLKA) (57:57:57)(12:12:12)) - (SETUPHOLD ADA13 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA12 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA11 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA10 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA9 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA8 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA7 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA6 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD ADA5 (posedge CLKA) (65:65:65)(4:4:4)) - (SETUPHOLD CEA (posedge CLKA) (54:54:54)(22:22:22)) - (SETUPHOLD OCEB (posedge CLKB) (65:65:65)(-14:-14:-14)) - (SETUPHOLD CEB (posedge CLKB) (89:89:89)(18:18:18)) - (SETUPHOLD ADB5 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB6 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB7 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB8 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB9 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB10 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB11 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB12 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD ADB13 (posedge CLKB) (59:59:59)(26:26:26)) - (SETUPHOLD DIB0 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB1 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB2 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB3 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB4 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB5 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB6 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB7 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB8 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB9 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB10 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB11 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB12 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB13 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB14 (posedge CLKA) (74:74:74)(17:17:17)) - (SETUPHOLD DIB15 (posedge CLKA) (74:74:74)(17:17:17)) - ) - (TIMINGCHECK - (WIDTH (posedge CLKA) (562:562:562)) - (WIDTH (negedge CLKA) (562:562:562)) - (WIDTH (posedge CLKB) (561:561:561)) - (WIDTH (negedge CLKB) (561:561:561)) - ) - ) - (CELL - (CELLTYPE "pll0inst_PLLInst_0") - (INSTANCE pll0inst_PLLInst_0I) - (DELAY - (ABSOLUTE - (IOPATH CLKI CLKOS3 (0:0:0)(0:0:0)) - (IOPATH CLKI CLKOS2 (0:0:0)(0:0:0)) - (IOPATH CLKI CLKOS (0:0:0)(0:0:0)) - (IOPATH CLKI CLKOP (0:0:0)(0:0:0)) - (IOPATH CLKFB CLKOS3 (0:0:0)(0:0:0)) - (IOPATH CLKFB CLKOS2 (0:0:0)(0:0:0)) - (IOPATH CLKFB CLKOS (0:0:0)(0:0:0)) - (IOPATH CLKFB CLKOP (0:0:0)(0:0:0)) - ) - ) - ) - (CELL - (CELLTYPE "top_tf") - (INSTANCE ) - (DELAY - (ABSOLUTE - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/B1 (535:620:706) - (535:620:706)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/M1 (500:574:649) - (500:574:649)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/A0 (631:731:831) - (631:731:831)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/C0 (239:335:432) - (239:335:432)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/M0 (506:586:667) - (506:586:667)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CE (346:392:438) - (346:392:438)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CE (346:392:438) - (346:392:438)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CE (238:280:322) - (238:280:322)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CE (238:280:322) - (238:280:322)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CE (238:280:322) - (238:280:322)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CE (238:280:322) - (238:280:322)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CE (374:438:502) - (374:438:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CE (374:438:502) - (374:438:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CE (374:438:502) - (374:438:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CE (374:438:502) - (374:438:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/A1 (780:910:1040) - (780:910:1040)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/B1 (682:797:913) - (682:797:913)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CE (378:445:512) - (378:445:512)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CE (378:445:512) - (378:445:512)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CE (618:701:785) - (618:701:785)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CE (618:701:785) - (618:701:785)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CE (618:701:785) - (618:701:785)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CE (618:701:785) - (618:701:785)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CE (364:414:465) - (364:414:465)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CE (364:414:465) - (364:414:465)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CE (378:445:512) - (378:445:512)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CE (378:445:512) - (378:445:512)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA - (709:835:961)(709:835:961)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_79I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_79I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_80I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_80I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_81I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_81I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_82I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_82I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_83I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_83I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_103I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_121I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_122I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_122I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_123I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_125I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_126I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_127I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_128I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_129I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_130I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_131I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_132I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_133I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_134I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_134I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_135I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_135I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_136I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_136I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_137I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_137I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_138I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_138I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_139I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_139I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_140I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_140I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_141I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_141I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_142I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_142I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_143I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_143I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_144I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_144I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_145I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_145I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_146I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_146I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_152I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_152I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_153I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_153I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_154I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_154I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_155I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_155I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_156I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_156I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_157I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_157I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_158I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_158I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_159I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_159I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_160I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_160I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_161I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_161I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_167I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_167I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_168I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_168I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_169I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_169I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_170I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_170I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_171I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_171I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_182I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_182I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_183I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_183I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_184I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_184I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_185I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_185I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_186I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_SLICE_186I/CLK (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_187I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_187I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_189I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_189I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 fifo_colector_inst_SLICE_190I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_432I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_433I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_434I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_434I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_435I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_435I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_436I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_436I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_437I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_437I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_438I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_439I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_439I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_440I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_440I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_441I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_441I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_442I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_442I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_443I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_445I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_445I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_446I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_446I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_447I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_447I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_448I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_448I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_449I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_450I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_450I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_451I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_451I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_452I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_452I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_453I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_453I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_454I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_455I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_456I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_457I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_458I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_459I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_460I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_628I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_tdc_bundle_inst_SLICE_628I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 SLICE_740I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_28_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_27_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_26_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_25_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_24_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_23_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_22_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_21_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_20_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_18_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_17_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_16_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_2_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_1_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_dbg2_out_0_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_buf_drop_1_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_buf_out_valid_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_8_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_7_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_6_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_5_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_4_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_3_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_2_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_1_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_offset_0_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_lvl1_invalid_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_lvl1_MGIOLI/CLK (1523:1620:1717) - (1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 hades_raw_out_valid_MGIOLI/CLK - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 reset_dc_MGIOLI/CLK (1523:1620:1717) - (1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKA - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CLKB - (1523:1620:1717)(1523:1620:1717)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS3 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CLKA (1523:1620:1717) - (1523:1620:1717)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/A1 (633:733:833) - (633:733:833)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/M1 (465:526:588) - (465:526:588)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/A0 (363:431:500) - (363:431:500)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/B0 (648:740:832) - (648:740:832)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/D1 (217:258:299) - (217:258:299)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/C0 (643:779:916) - (643:779:916)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/M0 (640:715:790) - (640:715:790)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/A1 (521:614:707) - (521:614:707)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/M1 (336:378:420) - (336:378:420)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/B0 (397:470:544) - (397:470:544)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/A0 (785:904:1023) - (785:904:1023)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/C1 (246:345:444) - (246:345:444)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/D0 (747:840:933) - (747:840:933)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/M0 (345:392:439) - (345:392:439)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/A1 (633:733:833) - (633:733:833)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/B1 (405:479:553) - (405:479:553)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/B0 (405:479:553) - (405:479:553)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/M1 (336:378:420) - (336:378:420)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/B0 (649:744:840) - (649:744:840)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/D1 (354:412:471) - (354:412:471)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/D0 (214:255:297) - (214:255:297)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/M0 (347:397:448) - (347:397:448)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/C0 (379:498:618) - (379:498:618)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/M1 (477:545:613) - (477:545:613)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/M1 (506:576:646) - (506:576:646)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/D1 (489:568:647) - (489:568:647)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/D0 (489:568:647) - (489:568:647)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/A0 (637:739:842) - (637:739:842)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/D1 (221:264:308) - (221:264:308)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/B0 (517:597:677) - (517:597:677)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/M0 (610:683:757) - (610:683:757)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/B1 (396:464:532) - (396:464:532)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/M1 (476:535:594) - (476:535:594)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/A0 (366:437:509) - (366:437:509)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/A0 (495:581:667) - (495:581:667)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/C0 (244:343:443) - (244:343:443)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/M0 (473:532:592) - (473:532:592)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CE (624:710:797) - (624:710:797)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/CE (624:710:797) - (624:710:797)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CE (516:598:681) - (516:598:681)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/CE (516:598:681) - (516:598:681)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CE (516:598:681) - (516:598:681)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/CE (516:598:681) - (516:598:681)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/A1 (785:908:1031) - (785:908:1031)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/B1 (797:920:1044) - (797:920:1044)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CE (368:427:487) - (368:427:487)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/CE (368:427:487) - (368:427:487)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CE (627:705:784) - (627:705:784)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/CE (627:705:784) - (627:705:784)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CE (497:563:630) - (497:563:630)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/CE (497:563:630) - (497:563:630)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CE (781:890:999) - (781:890:999)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/CE (781:890:999) - (781:890:999)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CE (504:578:652) - (504:578:652)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/CE (504:578:652) - (504:578:652)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CE (471:532:593) - (471:532:593)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/CE (471:532:593) - (471:532:593)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/CE (499:566:634) - (499:566:634)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/CE (770:878:986) - (770:878:986)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB - (808:923:1038)(808:923:1038)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB - (808:923:1038)(808:923:1038)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/A1 (494:576:659) - (494:576:659)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/M1 (606:677:748) - (606:677:748)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/B0 (406:486:566) - (406:486:566)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/B0 (406:486:566) - (406:486:566)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/D1 (214:255:297) - (214:255:297)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/C0 (244:343:443) - (244:343:443)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/M0 (603:674:745) - (603:674:745)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/A1 (260:318:376) - (260:318:376)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/A1 (654:759:865) - (654:759:865)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/A1 (393:475:558) - (393:475:558)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/A0 (393:475:558) - (393:475:558)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/M1 (348:397:446) - (348:397:446)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/B0 (527:617:707) - (527:617:707)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/C1 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/C0 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/M0 (347:397:448) - (347:397:448)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/A1 (499:584:670) - (499:584:670)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/B1 (536:621:707) - (536:621:707)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/B0 (536:621:707) - (536:621:707)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/M1 (466:520:574) - (466:520:574)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/B0 (383:450:517) - (383:450:517)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/A0 (627:735:843) - (627:735:843)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/D1 (222:269:317) - (222:269:317)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/D0 (347:403:459) - (347:403:459)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/M0 (476:538:601) - (476:538:601)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/B1 (278:332:386) - (278:332:386)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/B0 (532:624:716) - (532:624:716)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/M1 (472:538:604) - (472:538:604)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/M1 (237:278:319) - (237:278:319)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/B1 (403:475:548) - (403:475:548)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/B0 (403:475:548) - (403:475:548)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/B0 (519:602:686) - (519:602:686)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/D1 (354:412:471) - (354:412:471)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/C0 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/M0 (237:279:321) - (237:279:321)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/A1 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/B1 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/OFX0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/A0 (506:597:689) - (506:597:689)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/OFX0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/B1 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/A0 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/B1 (637:721:806) - (637:721:806)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/D1 (92:112:133) - (92:112:133)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/B0 (640:728:817) - (640:728:817)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/A1 (386:469:552) - (386:469:552)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/D1 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/D0 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/B1 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/A1 (380:457:535) - (380:457:535)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/A0 (507:591:675) - (507:591:675)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 - fifo_colector_inst_SLICE_125I/B1 (940:1113:1287)(940:1113:1287)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 - fifo_colector_inst_SLICE_680I/D0 (1017:1200:1383)(1017:1200:1383)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/A0 (734:884:1035) - (734:884:1035)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I/Q0 - fifo_colector_inst_SLICE_722I/A0 (925:1106:1288)(925:1106:1288)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/A1 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/B0 (522:598:674) - (522:598:674)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/B1 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/OFX0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/A0 (489:568:648) - (489:568:648)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/OFX0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/B1 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/B0 (634:717:800) - (634:717:800)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/B1 (397:468:540) - (397:468:540)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/A0 (384:465:547) - (384:465:547)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/D1 (94:116:138) - (94:116:138)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/D1 (218:259:300) - (218:259:300)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/D0 (218:259:300) - (218:259:300)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/B1 (374:431:489) - (374:431:489)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/A1 (380:457:535) - (380:457:535)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/B0 (522:598:674) - (522:598:674)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I/FCO - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/C0 (233:323:413)(233:323:413)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/A1 (915:1059:1204) - (915:1059:1204)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/B1 (687:805:924) - (687:805:924)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/B0 (687:805:924) - (687:805:924)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/M1 (340:383:426) - (340:383:426)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/A0 (911:1054:1198) - (911:1054:1198)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/D0 (500:587:675) - (500:587:675)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/M0 (340:384:429) - (340:384:429)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/CE (375:447:520) - (375:447:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/A1 (505:595:686) - (505:595:686)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/B1 (519:602:685) - (519:602:685)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CE (352:401:451) - (352:401:451)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/CE (352:401:451) - (352:401:451)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CE (352:401:451) - (352:401:451)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/CE (352:401:451) - (352:401:451)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/CE (219:251:284) - (219:251:284)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CE (364:423:482) - (364:423:482)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/CE (364:423:482) - (364:423:482)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CE (369:430:492) - (369:430:492)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/CE (369:430:492) - (369:430:492)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CE (400:482:564) - (400:482:564)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/CE (400:482:564) - (400:482:564)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CE (400:482:564) - (400:482:564)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/CE (400:482:564) - (400:482:564)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CE (364:430:496) - (364:430:496)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/CE (364:430:496) - (364:430:496)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CE (656:774:892) - (656:774:892)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/CE (656:774:892) - (656:774:892)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CE (369:430:492) - (369:430:492)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/CE (369:430:492) - (369:430:492)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA - (865:1020:1175)(865:1020:1175)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/A1 (260:318:376) - (260:318:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/A1 (915:1059:1204) - (915:1059:1204)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/A1 (672:798:925) - (672:798:925)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/A0 (672:798:925) - (672:798:925)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/M1 (340:383:426) - (340:383:426)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/A0 (366:437:509) - (366:437:509)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/A0 (537:651:766) - (537:651:766)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/C1 (528:673:819) - (528:673:819)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/C0 (528:673:819) - (528:673:819)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/M0 (343:390:438) - (343:390:438)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/A1 (687:832:977) - (687:832:977)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/A1 (408:510:612) - (408:510:612)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/A0 (408:510:612) - (408:510:612)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/M1 (336:378:420) - (336:378:420)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/B0 (400:476:553) - (400:476:553)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/B0 (941:1081:1222) - (941:1081:1222)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/C1 (392:523:654) - (392:523:654)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/C0 (262:381:501) - (262:381:501)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/M0 (242:280:318) - (242:280:318)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/A1 (897:1021:1146) - (897:1021:1146)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/D1 (616:696:776) - (616:696:776)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/D0 (616:696:776) - (616:696:776)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/M1 (340:383:426) - (340:383:426)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/A0 (369:440:512) - (369:440:512)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/B0 (796:904:1012) - (796:904:1012)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/B1 (384:447:511) - (384:447:511)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/A0 (781:897:1013) - (781:897:1013)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/M0 (340:384:429) - (340:384:429)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/B0 (538:624:711) - (538:624:711)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/M1 (484:548:612) - (484:548:612)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/M1 (484:548:612) - (484:548:612)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/B1 (538:624:711) - (538:624:711)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/B0 (538:624:711) - (538:624:711)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/B0 (422:512:602) - (422:512:602)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/B0 (791:896:1001) - (791:896:1001)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/C1 (507:629:751) - (507:629:751)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/A0 (639:742:845) - (639:742:845)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/M0 (482:544:606) - (482:544:606)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/B1 (556:662:769) - (556:662:769)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/B1 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/B0 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/M1 (478:538:599) - (478:538:599)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/A0 (650:770:890) - (650:770:890)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/D0 (221:264:308) - (221:264:308)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/M0 (475:534:593) - (475:534:593)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/CE (511:584:658) - (511:584:658)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CE (670:765:860) - (670:765:860)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/CE (670:765:860) - (670:765:860)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CE (670:765:860) - (670:765:860)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/CE (670:765:860) - (670:765:860)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/A1 (699:838:978) - (699:838:978)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/B1 (825:964:1103) - (825:964:1103)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CE (505:576:647) - (505:576:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/CE (505:576:647) - (505:576:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CE (505:576:647) - (505:576:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/CE (505:576:647) - (505:576:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CE (527:604:682) - (527:604:682)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/CE (527:604:682) - (527:604:682)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CE (528:605:683) - (528:605:683)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/CE (528:605:683) - (528:605:683)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CE (794:897:1000) - (794:897:1000)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/CE (794:897:1000) - (794:897:1000)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CE (631:710:790) - (631:710:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/CE (631:710:790) - (631:710:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CE (631:710:790) - (631:710:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/CE (631:710:790) - (631:710:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CE (527:604:682) - (527:604:682)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/CE (527:604:682) - (527:604:682)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CE (635:716:798) - (635:716:798)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/CE (635:716:798) - (635:716:798)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CE (551:635:720) - (551:635:720)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/CE (551:635:720) - (551:635:720)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB - (541:628:715)(541:628:715)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB - (541:628:715)(541:628:715)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/A1 (260:318:376) - (260:318:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/B1 (686:804:923) - (686:804:923)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/B1 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/B0 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/M1 (478:538:599) - (478:538:599)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/A0 (537:651:766) - (537:651:766)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/C1 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/D0 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/M0 (477:539:602) - (477:539:602)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/A1 (260:318:376) - (260:318:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/B1 (660:768:876) - (660:768:876)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/A1 (820:978:1137) - (820:978:1137)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/A0 (820:978:1137) - (820:978:1137)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/M1 (775:899:1024) - (775:899:1024)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/B0 (553:664:776) - (553:664:776)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/C1 (245:347:449) - (245:347:449)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/B0 (837:994:1152) - (837:994:1152)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/M0 (777:908:1040) - (777:908:1040)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/A1 (636:737:838) - (636:737:838)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/A1 (393:475:558) - (393:475:558)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/A0 (393:475:558) - (393:475:558)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/M1 (626:718:811) - (626:718:811)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/A0 (632:732:832) - (632:732:832)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/B1 (930:1068:1207) - (930:1068:1207)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/C0 (246:345:444) - (246:345:444)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/M0 (628:721:815) - (628:721:815)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/A0 (511:604:697) - (511:604:697)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/M1 (354:406:458) - (354:406:458)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/M1 (348:397:446) - (348:397:446)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/B1 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/B0 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/B0 (383:450:517) - (383:450:517)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/B0 (529:622:716) - (529:622:716)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/C1 (242:341:441) - (242:341:441)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/D0 (222:269:317) - (222:269:317)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/M0 (346:396:447) - (346:396:447)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/A1 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/A1 (489:568:648) - (489:568:648)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/OFX0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/B0 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/OFX0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/A1 (686:799:913) - (686:799:913)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/A0 (380:457:535) - (380:457:535)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/B1 (377:436:495) - (377:436:495)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/B0 (404:481:558) - (404:481:558)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/A1 (517:615:713) - (517:615:713)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/D1 (94:116:138) - (94:116:138)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/C0 (220:306:393) - (220:306:393)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/B1 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/A1 (380:457:535) - (380:457:535)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/A0 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 - fifo_colector_inst_SLICE_125I/D0 (643:747:851)(643:747:851)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 - fifo_colector_inst_SLICE_680I/A1 (682:812:942)(682:812:942)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/A0 (682:812:942) - (682:812:942)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/B1 (409:493:578) - (409:493:578)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/B0 (409:493:578) - (409:493:578)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/B1 (419:505:592) - (419:505:592)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/OFX0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/B0 (652:755:859) - (652:755:859)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/OFX0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/B1 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/A0 (395:487:579) - (395:487:579)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/B1 (524:617:711) - (524:617:711)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/A0 (513:618:723) - (513:618:723)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/D1 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/D1 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/D0 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/B1 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/A1 (489:568:648) - (489:568:648)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/A0 (395:487:579) - (395:487:579)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I/FCO - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/C0 (381:503:625)(381:503:625)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/B1 (535:620:706) - (535:620:706)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/M1 (336:378:420) - (336:378:420)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/A0 (631:731:831) - (631:731:831)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/C0 (244:343:443) - (244:343:443)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/M0 (338:383:428) - (338:383:428)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CE (247:294:342) - (247:294:342)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/CE (247:294:342) - (247:294:342)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CE (247:294:342) - (247:294:342)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/CE (247:294:342) - (247:294:342)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/A1 (513:609:705) - (513:609:705)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/B1 (528:616:704) - (528:616:704)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/CE (372:436:500) - (372:436:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CE (361:416:471) - (361:416:471)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/CE (361:416:471) - (361:416:471)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CE (364:423:482) - (364:423:482)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/CE (364:423:482) - (364:423:482)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/CE (353:403:453) - (353:403:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CE (361:416:471) - (361:416:471)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/CE (361:416:471) - (361:416:471)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEA - (593:694:796)(593:694:796)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/B1 (926:1046:1166) - (926:1046:1166)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/A1 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/A0 (391:472:554) - (391:472:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/M1 (336:378:420) - (336:378:420)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/B0 (383:450:517) - (383:450:517)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/A0 (515:616:717) - (515:616:717)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/D1 (222:269:317) - (222:269:317)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/C0 (247:349:452) - (247:349:452)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/M0 (340:388:437) - (340:388:437)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/A1 (517:607:697) - (517:607:697)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/C1 (246:348:451) - (246:348:451)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/A0 (386:465:544) - (386:465:544)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/M1 (471:536:601) - (471:536:601)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/A0 (635:738:841) - (635:738:841)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/C1 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/C0 (248:350:453) - (248:350:453)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/M0 (467:531:595) - (467:531:595)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/A1 (1026:1169:1313) - (1026:1169:1313)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/C1 (510:641:772) - (510:641:772)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/C0 (510:641:772) - (510:641:772)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/M1 (368:420:473) - (368:420:473)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/A0 (915:1053:1191) - (915:1053:1191)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/B1 (781:895:1009) - (781:895:1009)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/B0 (669:776:883) - (669:776:883)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/M0 (470:533:597) - (470:533:597)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/D0 (207:244:282) - (207:244:282)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/M1 (218:252:287) - (218:252:287)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/M1 (218:252:287) - (218:252:287)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/B1 (531:613:696) - (531:613:696)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/B0 (531:613:696) - (531:613:696)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/A0 (523:624:725) - (523:624:725)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/B0 (542:638:735) - (542:638:735)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/B1 (672:780:888) - (672:780:888)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/C0 (252:357:463) - (252:357:463)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/M0 (247:292:338) - (247:292:338)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/A1 (646:751:857) - (646:751:857)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/B1 (553:647:741) - (553:647:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/B0 (553:647:741) - (553:647:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/M1 (494:557:621) - (494:557:621)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/B0 (380:444:508) - (380:444:508)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/A0 (648:756:864) - (648:756:864)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/D0 (367:430:494) - (367:430:494)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/M0 (468:524:581) - (468:524:581)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CE (486:549:612) - (486:549:612)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/CE (486:549:612) - (486:549:612)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CE (378:437:496) - (378:437:496)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/CE (378:437:496) - (378:437:496)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CE (378:437:496) - (378:437:496)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/CE (378:437:496) - (378:437:496)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CE (488:551:615) - (488:551:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/CE (488:551:615) - (488:551:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CE (488:551:615) - (488:551:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/CE (488:551:615) - (488:551:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/A1 (545:650:756) - (545:650:756)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/B1 (671:776:881) - (671:776:881)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CE (395:462:529) - (395:462:529)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/CE (395:462:529) - (395:462:529)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CE (633:715:798) - (633:715:798)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/CE (633:715:798) - (633:715:798)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CE (645:726:807) - (645:726:807)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/CE (645:726:807) - (645:726:807)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CE (639:717:795) - (639:717:795)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/CE (639:717:795) - (639:717:795)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CE (395:462:529) - (395:462:529)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/CE (395:462:529) - (395:462:529)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/CE (374:430:486) - (374:430:486)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/CE (214:243:272) - (214:243:272)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CE (229:265:301) - (229:265:301)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/CE (229:265:301) - (229:265:301)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CE (645:726:807) - (645:726:807)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/CE (645:726:807) - (645:726:807)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/CEB - (553:650:747)(553:650:747)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/OCEB - (553:650:747)(553:650:747)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/A1 (260:318:376) - (260:318:376)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/A1 (897:1021:1146) - (897:1021:1146)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/C1 (511:634:758) - (511:634:758)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/C0 (511:634:758) - (511:634:758)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/M1 (340:383:426) - (340:383:426)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/A0 (363:431:500) - (363:431:500)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/A0 (1176:1329:1483) - (1176:1329:1483)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/C1 (642:778:915) - (642:778:915)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/D0 (487:556:626) - (487:556:626)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/M0 (239:273:308) - (239:273:308)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/A1 (262:322:382) - (262:322:382)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/A1 (674:782:891) - (674:782:891)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/B1 (824:939:1054) - (824:939:1054)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/B0 (824:939:1054) - (824:939:1054)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/M1 (466:520:574) - (466:520:574)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/B0 (400:476:553) - (400:476:553)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/A0 (653:764:875) - (653:764:875)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/A1 (535:636:738) - (535:636:738)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/A0 (671:786:902) - (671:786:902)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/M0 (367:413:460) - (367:413:460)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/B1 (277:329:381) - (277:329:381)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/A1 (646:751:857) - (646:751:857)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/B1 (553:647:741) - (553:647:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/B0 (553:647:741) - (553:647:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/M1 (364:415:467) - (364:415:467)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/B0 (1173:1321:1470) - (1173:1321:1470)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/D1 (747:847:948) - (747:847:948)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/C0 (637:778:919) - (637:778:919)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/M0 (470:533:597) - (470:533:597)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/B1 (275:325:375) - (275:325:375)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/A0 (519:610:702) - (519:610:702)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/M1 (474:531:589) - (474:531:589)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/M1 (609:681:753) - (609:681:753)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/C1 (646:784:922) - (646:784:922)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/C0 (646:784:922) - (646:784:922)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/B0 (378:438:499) - (378:438:499)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/B0 (912:1030:1148) - (912:1030:1148)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/D1 (487:556:626) - (487:556:626)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/C0 (372:479:587) - (372:479:587)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/M0 (610:683:757) - (610:683:757)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/B1 (522:598:674) - (522:598:674)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/B1 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/OFX0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/B0 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/OFX0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/B1 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/B1 (637:721:806) - (637:721:806)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/A0 (625:729:833) - (625:729:833)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/D1 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/D1 (214:254:295) - (214:254:295)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/D0 (95:119:143) - (95:119:143)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/B1 (374:431:489) - (374:431:489)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/A1 (380:457:535) - (380:457:535)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/A0 (507:591:675) - (507:591:675)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 - fifo_colector_inst_SLICE_125I/A0 (693:800:907)(693:800:907)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 - fifo_colector_inst_SLICE_680I/C1 (592:732:873)(592:732:873)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/A0 (529:624:719) - (529:624:719)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I/Q0 - fifo_empty1I/PADDO (2169:2376:2583)(2169:2376:2583)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/A1 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/A1 (506:597:689) - (506:597:689)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/OFX0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/B0 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/OFX0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/B1 (633:724:815) - (633:724:815)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/B0 (522:598:674) - (522:598:674)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/B1 (397:468:540) - (397:468:540)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/B0 (643:733:823) - (643:733:823)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/D1 (94:116:138) - (94:116:138)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/D1 (94:116:138) - (94:116:138)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/D0 (218:259:300) - (218:259:300)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/B1 (374:431:489) - (374:431:489)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/A1 (258:314:370) - (258:314:370)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/A0 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I/FCO - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/C0 (363:464:566)(363:464:566)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_78I/FCO - fifo_colector_inst_fifo40_inst_SLICE_79I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_79I/B1 (277:329:381)(277:329:381)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_98I/B1 (396:464:532)(396:464:532)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_167I/B1 (405:479:553)(405:479:553)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_167I/B0 (405:479:553)(405:479:553)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_182I/M1 (476:535:594)(476:535:594)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_79I/B0 (378:438:499)(378:438:499)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_98I/A0 (763:874:986)(763:874:986)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_167I/D0 (217:258:299)(217:258:299)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_182I/M0 (476:535:594)(476:535:594)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/F1 - fifo_colector_inst_fifo40_inst_SLICE_79I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/F0 - fifo_colector_inst_fifo40_inst_SLICE_79I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_79I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_79I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_80I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_80I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_81I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_81I/CE (494:562:630)(494:562:630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_82I/CE (481:540:599)(481:540:599)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_82I/CE (481:540:599)(481:540:599)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_83I/CE (481:540:599)(481:540:599)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_83I/CE (481:540:599)(481:540:599)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_97I/A1 (503:591:680)(503:591:680)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_97I/B1 (517:598:679)(517:598:679)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_167I/CE (245:290:336)(245:290:336)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_167I/CE (245:290:336)(245:290:336)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_168I/CE (493:560:627)(493:560:627)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_168I/CE (493:560:627)(493:560:627)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_169I/CE (520:597:675)(520:597:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_169I/CE (520:597:675)(520:597:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_170I/CE (628:709:791)(628:709:791)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_170I/CE (628:709:791)(628:709:791)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_171I/CE (375:432:490)(375:432:490)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_171I/CE (375:432:490)(375:432:490)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_182I/CE (206:230:254)(206:230:254)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_182I/CE (206:230:254)(206:230:254)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_183I/CE (638:726:814)(638:726:814)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_183I/CE (638:726:814)(638:726:814)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_184I/CE (638:726:814)(638:726:814)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_184I/CE (638:726:814)(638:726:814)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_185I/CE (524:604:685)(524:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_185I/CE (524:604:685)(524:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_186I/CE (245:290:336)(245:290:336)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_SLICE_186I/CE (245:290:336)(245:290:336)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_721I/F0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CEA (800:910:1021)(800:910:1021)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_79I/FCO - fifo_colector_inst_fifo40_inst_SLICE_80I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_80I/A1 (260:318:376)(260:318:376)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_99I/B1 (399:468:538)(399:468:538)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_168I/D1 (486:554:622)(486:554:622)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_168I/D0 (486:554:622)(486:554:622)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_183I/M1 (768:853:939)(768:853:939)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_80I/A0 (366:437:509)(366:437:509)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_99I/A0 (643:752:861)(643:752:861)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_167I/C1 (244:343:443)(244:343:443)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_168I/C0 (510:635:760)(510:635:760)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_183I/M0 (999:1107:1216)(999:1107:1216)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/F1 - fifo_colector_inst_fifo40_inst_SLICE_80I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/F0 - fifo_colector_inst_fifo40_inst_SLICE_80I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_80I/FCO - fifo_colector_inst_fifo40_inst_SLICE_81I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_81I/A1 (260:318:376)(260:318:376)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_100I/A1 (497:581:665)(497:581:665)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_169I/C1 (772:918:1065)(772:918:1065)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_169I/C0 (772:918:1065)(772:918:1065)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_184I/M1 (504:563:622)(504:563:622)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_81I/B0 (403:480:557)(403:480:557)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_100I/B0 (924:1048:1172)(924:1048:1172)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_168I/C1 (393:512:631)(393:512:631)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_169I/A0 (663:779:895)(663:779:895)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_184I/M0 (492:559:627)(492:559:627)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/F1 - fifo_colector_inst_fifo40_inst_SLICE_81I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/F0 - fifo_colector_inst_fifo40_inst_SLICE_81I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_81I/FCO - fifo_colector_inst_fifo40_inst_SLICE_82I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_82I/B1 (277:329:381)(277:329:381)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_101I/A1 (499:584:670)(499:584:670)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_170I/B1 (531:613:696)(531:613:696)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_170I/B0 (531:613:696)(531:613:696)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_185I/M1 (471:527:584)(471:527:584)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_82I/B0 (380:444:508)(380:444:508)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_101I/B0 (510:588:666)(510:588:666)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_169I/D1 (354:412:471)(354:412:471)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_170I/D0 (354:412:471)(354:412:471)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_185I/M0 (738:823:908)(738:823:908)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/F1 - fifo_colector_inst_fifo40_inst_SLICE_82I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/F0 - fifo_colector_inst_fifo40_inst_SLICE_82I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_82I/FCO - fifo_colector_inst_fifo40_inst_SLICE_83I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_83I/B1 (275:325:375)(275:325:375)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_171I/D0 (600:675:751)(600:675:751)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_171I/M1 (611:683:756)(611:683:756)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_186I/M1 (475:532:590)(475:532:590)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/C1 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/C0 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_83I/B0 (378:438:499)(378:438:499)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_102I/B0 (512:589:667)(512:589:667)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_170I/D1 (487:556:626)(487:556:626)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_171I/C0 (511:636:761)(511:636:761)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_186I/M0 (480:541:603)(480:541:603)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/F1 - fifo_colector_inst_fifo40_inst_SLICE_83I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_83I/F0 - fifo_colector_inst_fifo40_inst_SLICE_83I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_84I/FCO - fifo_colector_inst_fifo40_inst_SLICE_85I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_85I/B1 (275:325:375)(275:325:375)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_91I/B1 (616:738:860)(616:738:860)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_147I/C1 (891:1100:1309)(891:1100:1309)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_147I/C0 (891:1100:1309)(891:1100:1309)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_162I/M1 (990:1147:1304)(990:1147:1304)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_85I/A0 (363:431:500)(363:431:500)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_91I/B0 (617:740:864)(617:740:864)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_147I/D0 (993:1157:1321)(993:1157:1321)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_162I/M0 (1117:1284:1452)(1117:1284:1452)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/F1 - fifo_colector_inst_fifo40_inst_SLICE_85I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/F0 - fifo_colector_inst_fifo40_inst_SLICE_85I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_85I/CE (397:471:546)(397:471:546)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_85I/CE (397:471:546)(397:471:546)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_86I/CE (511:593:675)(511:593:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_86I/CE (511:593:675)(511:593:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_87I/CE (511:593:675)(511:593:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_87I/CE (511:593:675)(511:593:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_88I/CE (269:332:396)(269:332:396)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_88I/CE (269:332:396)(269:332:396)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_89I/CE (269:332:396)(269:332:396)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_89I/CE (269:332:396)(269:332:396)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_90I/A1 (994:1174:1355)(994:1174:1355)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_90I/B1 (1008:1181:1354)(1008:1181:1354)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_147I/CE (523:604:685)(523:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_147I/CE (523:604:685)(523:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_148I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_148I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_149I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_149I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_150I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_150I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_151I/CE (728:859:991)(728:859:991)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_151I/CE (728:859:991)(728:859:991)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_162I/CE (523:604:685)(523:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_162I/CE (523:604:685)(523:604:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_163I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_163I/CE (972:1123:1274)(972:1123:1274)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_164I/CE (832:954:1077)(832:954:1077)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_164I/CE (832:954:1077)(832:954:1077)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_165I/CE (561:649:737)(561:649:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_165I/CE (561:649:737)(561:649:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_166I/CE (710:830:951)(710:830:951)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_SLICE_166I/CE (710:830:951)(710:830:951)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CEB (632:753:874)(632:753:874)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_720I/F0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/OCEB (632:753:874)(632:753:874)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_85I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_85I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_86I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_86I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_87I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_87I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_88I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_88I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_89I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_89I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_96I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_124I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_147I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_147I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_148I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_148I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_149I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_149I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_150I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_150I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_151I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_151I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_162I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_162I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_163I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_163I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_164I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_164I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_165I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_165I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_166I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_166I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_172I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_172I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_173I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_173I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_174I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_174I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_175I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_175I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_176I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_176I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_177I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_177I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_178I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_178I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_179I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_179I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_180I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_180I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_181I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_SLICE_181I/CLK - (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_188I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_631I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_631I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_632I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_633I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI trb_adapter_inst_SLICE_724I/CLK (1588:1665:1742) - (1588:1665:1742)) - (INTERCONNECT rd_clkI/PADDI FEE_TRG_RELEASE_OUT_MGIOLI/CLK (1627:1716:1805) - (1627:1716:1805)) - (INTERCONNECT rd_clkI/PADDI FEE_DATAFINISHED_OUT_MGIOLI/CLK (1627:1716:1805) - (1627:1716:1805)) - (INTERCONNECT rd_clkI/PADDI FEE_DATA_WRITE_OUT_MGIOLI/CLK (1627:1716:1805) - (1627:1716:1805)) - (INTERCONNECT rd_clkI/PADDI LVL1_INVALID_TRG_IN_MGIOLI/CLK (1627:1716:1805) - (1627:1716:1805)) - (INTERCONNECT rd_clkI/PADDI LVL1_TRG_DATA_VALID_IN_MGIOLI/CLK (1627:1716:1805) - (1627:1716:1805)) - (INTERCONNECT rd_clkI/PADDI fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/CLKB - (1627:1716:1805)(1627:1716:1805)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_85I/FCO - fifo_colector_inst_fifo40_inst_SLICE_86I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_86I/A1 (260:318:376)(260:318:376)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_92I/B1 (724:861:999)(724:861:999)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_148I/A1 (710:854:999)(710:854:999)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_148I/A0 (710:854:999)(710:854:999)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_163I/M1 (1084:1231:1379)(1084:1231:1379)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_86I/B0 (380:444:508)(380:444:508)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_92I/A0 (764:914:1065)(764:914:1065)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_147I/A1 (694:823:953)(694:823:953)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_148I/B0 (623:743:864)(623:743:864)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_163I/M0 (547:649:751)(547:649:751)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/F1 - fifo_colector_inst_fifo40_inst_SLICE_86I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/F0 - fifo_colector_inst_fifo40_inst_SLICE_86I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_86I/FCO - fifo_colector_inst_fifo40_inst_SLICE_87I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_87I/A1 (262:322:382)(262:322:382)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_93I/A1 (603:735:867)(603:735:867)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_149I/A1 (739:885:1031)(739:885:1031)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_149I/A0 (739:885:1031)(739:885:1031)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_164I/M1 (614:705:796)(614:705:796)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_87I/B0 (380:444:508)(380:444:508)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_93I/A0 (605:739:874)(605:739:874)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_148I/D1 (537:649:762)(537:649:762)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_149I/D0 (679:794:910)(679:794:910)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_164I/M0 (396:469:543)(396:469:543)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/F1 - fifo_colector_inst_fifo40_inst_SLICE_87I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/F0 - fifo_colector_inst_fifo40_inst_SLICE_87I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_87I/FCO - fifo_colector_inst_fifo40_inst_SLICE_88I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_88I/B1 (275:325:375)(275:325:375)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_94I/B1 (813:941:1069)(813:941:1069)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_150I/D1 (801:938:1076)(801:938:1076)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_150I/D0 (801:938:1076)(801:938:1076)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_165I/M1 (386:457:529)(386:457:529)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_88I/B0 (380:444:508)(380:444:508)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_94I/B0 (620:746:873)(620:746:873)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_149I/C1 (597:763:930)(597:763:930)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_150I/C0 (597:763:930)(597:763:930)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_165I/M0 (485:567:649)(485:567:649)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/F1 - fifo_colector_inst_fifo40_inst_SLICE_88I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/F0 - fifo_colector_inst_fifo40_inst_SLICE_88I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_88I/FCO - fifo_colector_inst_fifo40_inst_SLICE_89I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_89I/B1 (275:325:375)(275:325:375)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_151I/D0 (517:624:732)(517:624:732)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_151I/M1 (528:632:737)(528:632:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_166I/M1 (528:632:737)(528:632:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/D1 (654:776:898)(654:776:898)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/D0 (654:776:898)(654:776:898)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_89I/B0 (378:438:499)(378:438:499)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_95I/B0 (625:754:884)(625:754:884)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_150I/C1 (597:763:930)(597:763:930)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_151I/B0 (756:896:1037)(756:896:1037)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_166I/M0 (696:810:925)(696:810:925)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/F1 - fifo_colector_inst_fifo40_inst_SLICE_89I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_89I/F0 - fifo_colector_inst_fifo40_inst_SLICE_89I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_90I/FCO - fifo_colector_inst_fifo40_inst_SLICE_91I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F1 - fifo_colector_inst_fifo40_inst_SLICE_91I/A1 (395:487:579)(395:487:579)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F1 - fifo_colector_inst_fifo40_inst_SLICE_91I/A0 (380:457:535)(380:457:535)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_91I/FCO - fifo_colector_inst_fifo40_inst_SLICE_92I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_702I/F1 - fifo_colector_inst_fifo40_inst_SLICE_92I/A1 (395:487:579)(395:487:579)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_702I/F0 - fifo_colector_inst_fifo40_inst_SLICE_92I/B0 (394:464:534)(394:464:534)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_92I/FCO - fifo_colector_inst_fifo40_inst_SLICE_93I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F1 - fifo_colector_inst_fifo40_inst_SLICE_93I/B1 (504:575:647)(504:575:647)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F1 - fifo_colector_inst_fifo40_inst_SLICE_93I/B0 (409:493:578)(409:493:578)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_93I/FCO - fifo_colector_inst_fifo40_inst_SLICE_94I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F0 - fifo_colector_inst_fifo40_inst_SLICE_94I/A1 (657:782:907)(657:782:907)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_676I/F0 - fifo_colector_inst_fifo40_inst_SLICE_676I/D1 (92:112:133)(92:112:133)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 - fifo_colector_inst_fifo40_inst_SLICE_94I/A0 (515:621:728)(515:621:728)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 - fifo_colector_inst_fifo40_inst_SLICE_673I/D1 (97:123:149)(97:123:149)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 - fifo_colector_inst_fifo40_inst_SLICE_674I/D1 (97:123:149)(97:123:149)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 - fifo_colector_inst_fifo40_inst_SLICE_702I/C1 (224:314:404)(224:314:404)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_673I/F0 - fifo_colector_inst_fifo40_inst_SLICE_702I/D0 (97:123:149)(97:123:149)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_94I/FCO - fifo_colector_inst_fifo40_inst_SLICE_95I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_692I/F0 - fifo_colector_inst_fifo40_inst_SLICE_95I/B1 (374:431:489)(374:431:489)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_692I/F1 - fifo_colector_inst_fifo40_inst_SLICE_95I/A1 (258:314:370)(258:314:370)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F0 - fifo_colector_inst_fifo40_inst_SLICE_95I/A0 (640:753:866)(640:753:866)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_675I/F0 - fifo_colector_inst_fifo40_inst_SLICE_675I/D1 (92:112:133)(92:112:133)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_95I/FCO - fifo_colector_inst_fifo40_inst_SLICE_96I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/F0 - fifo_colector_inst_fifo40_inst_SLICE_96I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 - trb_adapter_inst_SLICE_188I/C0 (2119:2373:2627)(2119:2373:2627)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_720I/D0 (803:911:1020)(803:911:1020)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_96I/Q0 last_buf_emptyI/PADDO - (2267:2485:2703)(2267:2485:2703)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_97I/FCO - fifo_colector_inst_fifo40_inst_SLICE_98I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F1 - fifo_colector_inst_fifo40_inst_SLICE_98I/A1 (507:591:675)(507:591:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F1 - fifo_colector_inst_fifo40_inst_SLICE_98I/B0 (522:598:674)(522:598:674)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_98I/FCO - fifo_colector_inst_fifo40_inst_SLICE_99I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_703I/F0 - fifo_colector_inst_fifo40_inst_SLICE_99I/A1 (506:597:689)(506:597:689)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_648I/OFX0 - fifo_colector_inst_fifo40_inst_SLICE_99I/B0 (504:575:647)(504:575:647)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_99I/FCO - fifo_colector_inst_fifo40_inst_SLICE_100I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_649I/OFX0 - fifo_colector_inst_fifo40_inst_SLICE_100I/B1 (394:464:534)(394:464:534)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F1 - fifo_colector_inst_fifo40_inst_SLICE_100I/A0 (507:591:675)(507:591:675)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_100I/FCO - fifo_colector_inst_fifo40_inst_SLICE_101I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F0 - fifo_colector_inst_fifo40_inst_SLICE_101I/B1 (636:728:821)(636:728:821)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_679I/F0 - fifo_colector_inst_fifo40_inst_SLICE_679I/D1 (92:112:133)(92:112:133)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 - fifo_colector_inst_fifo40_inst_SLICE_101I/A0 (512:609:706)(512:609:706)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 - fifo_colector_inst_fifo40_inst_SLICE_677I/D1 (95:119:143)(95:119:143)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 - fifo_colector_inst_fifo40_inst_SLICE_678I/D1 (95:119:143)(95:119:143)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_677I/F0 - fifo_colector_inst_fifo40_inst_SLICE_703I/B0 (400:475:551)(400:475:551)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_101I/FCO - fifo_colector_inst_fifo40_inst_SLICE_102I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_691I/F0 - fifo_colector_inst_fifo40_inst_SLICE_102I/B1 (374:431:489)(374:431:489)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_691I/F1 - fifo_colector_inst_fifo40_inst_SLICE_102I/A1 (258:314:370)(258:314:370)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_703I/F1 - fifo_colector_inst_fifo40_inst_SLICE_102I/A0 (377:449:521)(377:449:521)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_102I/FCO - fifo_colector_inst_fifo40_inst_SLICE_103I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_103I/F0 - fifo_colector_inst_fifo40_inst_SLICE_103I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_103I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_721I/C0 (233:323:413)(233:323:413)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_120I/FCO - hades_tdc_bundle_inst_SLICE_104I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 - hades_tdc_bundle_inst_SLICE_456I/B0 (825:948:1071)(825:948:1071)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 - hades_tdc_bundle_inst_SLICE_458I/C1 (672:823:974)(672:823:974)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 - hades_tdc_bundle_inst_SLICE_458I/C0 (672:823:974)(672:823:974)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_104I/F0 - hades_tdc_bundle_inst_SLICE_710I/C1 (386:499:612)(386:499:612)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/D1 (740:836:933) - (740:836:933)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/D1 (344:403:463) - (344:403:463)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_SLICE_434I/B1 (278:332:386)(278:332:386)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_SLICE_435I/D1 (208:248:288)(208:248:288)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_SLICE_435I/D0 (208:248:288)(208:248:288)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_SLICE_438I/D1 (208:248:288)(208:248:288)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/M0 - (830:934:1039)(830:934:1039)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/M0 (390:450:510) - (390:450:510)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_SLICE_681I/D1 (340:396:452)(340:396:452)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/B1 (411:489:568) - (411:489:568)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/B0 (411:489:568) - (411:489:568)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 hades_dbg2_coarse_1_I/PADDO - (1479:1645:1811)(1479:1645:1811)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q1 hades_offset_4_MGIOLI/TXDATA0 - (1167:1312:1457)(1167:1312:1457)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/C1 - (764:916:1069)(764:916:1069)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/C1 (374:491:609) - (374:491:609)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_434I/C1 (238:337:437)(238:337:437)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_434I/D0 (95:120:145)(95:120:145)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_435I/A1 (382:463:545)(382:463:545)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_435I/A0 (382:463:545)(382:463:545)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_438I/B1 (397:470:544)(397:470:544)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/M1 - (1224:1363:1503)(1224:1363:1503)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/M1 - (963:1079:1196)(963:1079:1196)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_SLICE_681I/B1 (532:624:716)(532:624:716)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/D1 (237:292:347) - (237:292:347)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/D0 (237:292:347) - (237:292:347)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 hades_dbg2_coarse_0_I/PADDO - (1432:1597:1762)(1432:1597:1762)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/Q0 hades_offset_3_MGIOLI/TXDATA0 - (1148:1290:1432)(1148:1290:1432)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/B1 - (832:940:1049)(832:940:1049)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/M1 - (931:1023:1115)(931:1023:1115)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/A1 - (1002:1125:1248)(1002:1125:1248)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/M0 (233:270:308) - (233:270:308)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/D1 (324:369:414) - (324:369:414)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/A1 (380:455:531) - (380:455:531)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_698I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/C1 (233:323:413) - (233:323:413)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/B1 - (799:908:1018)(799:908:1018)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/B1 - (804:916:1029)(804:916:1029)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_SLICE_436I/D1 (194:223:253)(194:223:253)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_SLICE_455I/A1 (519:610:702)(519:610:702)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/M0 - (1886:2089:2293)(1886:2089:2293)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/M0 - (1315:1458:1601)(1315:1458:1601)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 - hades_tdc_bundle_inst_SLICE_701I/B1 (534:617:701)(534:617:701)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 hades_dbg2_coarse_5_I/PADDO - (2336:2605:2875)(2336:2605:2875)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q1 hades_offset_8_MGIOLI/TXDATA0 - (2183:2440:2698)(2183:2440:2698)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/A1 - (985:1109:1234)(985:1109:1234)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/M1 (465:518:572) - (465:518:572)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/D0 (208:243:278) - (208:243:278)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/C0 - (785:926:1068)(785:926:1068)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/M1 (335:377:419) - (335:377:419)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/B0 (403:480:557) - (403:480:557)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/B0 (408:488:568) - (408:488:568)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_436I/B1 (808:929:1050)(808:929:1050)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_436I/B0 (808:929:1050)(808:929:1050)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_437I/B0 (673:779:886)(673:779:886)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_681I/B0 (283:344:406)(283:344:406)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_698I/B1 (283:344:406)(283:344:406)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F1 - hades_tdc_bundle_inst_SLICE_698I/B0 (283:344:406)(283:344:406)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/A0 (534:635:737) - (534:635:737)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/A0 (403:493:584) - (403:493:584)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_435I/C1 (246:348:451)(246:348:451)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_436I/A1 (652:756:861)(652:756:861)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_436I/A0 (652:756:861)(652:756:861)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_437I/A0 (517:607:697)(517:607:697)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_438I/C1 (246:348:451)(246:348:451)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/M0 - (934:1049:1164)(934:1049:1164)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/M0 (494:564:635) - (494:564:635)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_681I/A0 (403:493:584)(403:493:584)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_698I/A1 (403:493:584)(403:493:584)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 - hades_tdc_bundle_inst_SLICE_698I/C0 (372:487:602)(372:487:602)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 hades_dbg2_coarse_3_I/PADDO - (1627:1811:1995)(1627:1811:1995)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q1 hades_offset_6_MGIOLI/TXDATA0 - (1473:1645:1818)(1473:1645:1818)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/D1 (464:524:585) - (464:524:585)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/C1 (371:477:584) - (371:477:584)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 - hades_tdc_bundle_inst_SLICE_438I/D0 (482:547:612)(482:547:612)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F0 - hades_tdc_bundle_inst_SLICE_455I/B1 (377:436:495)(377:436:495)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/C1 (622:762:903) - (622:762:903)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/D1 (217:263:310) - (217:263:310)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_SLICE_438I/C0 (120:200:281)(120:200:281)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_SLICE_455I/C1 (248:353:458)(248:353:458)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/M1 - (1500:1660:1821)(1500:1660:1821)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/M1 - (1048:1175:1302)(1048:1175:1302)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/Q0 hades_dbg2_coarse_8_I/PADDO - (1914:2148:2383)(1914:2148:2383)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/B1 (540:627:715) - (540:627:715)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/B0 (540:627:715) - (540:627:715)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/B1 (540:627:715) - (540:627:715)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/B0 (540:627:715) - (540:627:715)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_SLICE_437I/B1 (400:470:541)(400:470:541)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_SLICE_437I/D0 (329:377:425)(329:377:425)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_701I/F1 - hades_tdc_bundle_inst_SLICE_438I/A0 (390:471:552)(390:471:552)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/A1 (658:768:879) - (658:768:879)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/A0 (658:768:879) - (658:768:879)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/A1 (392:476:561) - (392:476:561)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/A0 (392:476:561) - (392:476:561)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_SLICE_437I/A1 (518:611:704)(518:611:704)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_SLICE_438I/B0 (380:444:508)(380:444:508)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F1 - hades_tdc_bundle_inst_SLICE_455I/M0 (343:390:438)(343:390:438)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/D0 (598:673:749) - (598:673:749)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/C0 - (753:895:1037)(753:895:1037)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_SLICE_437I/D1 (194:223:253)(194:223:253)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/M0 - (1501:1651:1802)(1501:1651:1802)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/M0 - (1151:1281:1412)(1151:1281:1412)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 - hades_tdc_bundle_inst_SLICE_701I/A0 (385:461:538)(385:461:538)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q1 hades_dbg2_coarse_7_I/PADDO - (2712:2996:3280)(2712:2996:3280)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/C0 (620:749:878) - (620:749:878)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/D0 (488:557:627) - (488:557:627)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_SLICE_437I/C1 (245:347:449)(245:347:449)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_SLICE_437I/C0 (245:347:449)(245:347:449)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/M1 - (1751:1937:2124)(1751:1937:2124)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/M1 - (1181:1311:1441)(1181:1311:1441)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 - hades_tdc_bundle_inst_SLICE_701I/C0 (242:338:434)(242:338:434)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/Q0 hades_dbg2_coarse_6_I/PADDO - (2074:2294:2515)(2074:2294:2515)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/B0 (552:632:713) - (552:632:713)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/B1 (507:582:657) - (507:582:657)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/M1 (483:544:606) - (483:544:606)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/A1 - (975:1106:1238)(975:1106:1238)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/M0 (772:859:947) - (772:859:947)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_681I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/D1 (208:243:278) - (208:243:278)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/C1 (496:616:737) - (496:616:737)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/M1 (465:525:586) - (465:525:586)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/D0 (211:251:291) - (211:251:291)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/C0 (237:330:423) - (237:330:423)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/M1 (595:667:740) - (595:667:740)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I/FCO - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I/FCI (0:0:0) - (0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/C0 (380:490:601) - (380:490:601)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/C1 (247:345:444) - (247:345:444)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/C1 (247:345:444) - (247:345:444)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/C0 (247:345:444) - (247:345:444)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/C1 (375:490:606) - (375:490:606)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/C0 (375:490:606) - (375:490:606)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/C1 (375:490:606) - (375:490:606)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/C0 (375:490:606) - (375:490:606)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/B1 (545:639:733) - (545:639:733)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/B1 (662:762:863) - (662:762:863)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/B1 (386:453:520) - (386:453:520)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/B0 (386:453:520) - (386:453:520)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/C1 (517:648:779) - (517:648:779)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/B0 (550:643:737) - (550:643:737)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/D0 (363:427:491) - (363:427:491)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/C0 (257:365:473) - (257:365:473)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/D0 (232:284:337) - (232:284:337)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/A1 (525:628:731) - (525:628:731)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/B1 (540:635:730) - (540:635:730)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/B0 (540:635:730) - (540:635:730)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/B1 (540:635:730) - (540:635:730)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/B0 (540:635:730) - (540:635:730)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/A1 (525:628:731) - (525:628:731)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/A0 (525:628:731) - (525:628:731)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/C1 (243:339:436) - (243:339:436)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/C0 (243:339:436) - (243:339:436)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/D0 (325:370:416) - (325:370:416)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I/FCO - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/A1 (683:804:925) - (683:804:925)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/D1 (220:267:314) - (220:267:314)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/D0 (220:267:314) - (220:267:314)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/A0 (517:618:719) - (517:618:719)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/D1 (748:848:949) - (748:848:949)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/M0 (477:539:602) - (477:539:602)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/M0 (788:887:986) - (788:887:986)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/M0 (376:428:481) - (376:428:481)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/B0 (527:617:707) - (527:617:707)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/A0 (517:618:719) - (517:618:719)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/D0 (211:251:291) - (211:251:291)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/D0 (321:362:404) - (321:362:404)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I/FCO - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/A1 (500:588:677) - (500:588:677)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/A1 (391:478:566) - (391:478:566)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/C0 (248:353:458) - (248:353:458)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/B1 (400:476:553) - (400:476:553)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/B0 (515:596:677) - (515:596:677)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/A0 (494:576:659) - (494:576:659)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/D1 (482:556:631) - (482:556:631)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/B0 (777:888:1000) - (777:888:1000)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/D1 (482:556:631) - (482:556:631)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/C0 (220:306:393) - (220:306:393)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/D1 (208:243:278) - (208:243:278)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/D0 (321:362:404) - (321:362:404)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I/FCO - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/B1 (397:470:544) - (397:470:544)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/C1 (242:338:434) - (242:338:434)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/C0 (242:338:434) - (242:338:434)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/B0 (506:579:653) - (506:579:653)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/B1 (399:468:538) - (399:468:538)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/B0 (399:468:538) - (399:468:538)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/D1 (321:362:404) - (321:362:404)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/D0 (211:251:291) - (211:251:291)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I/FCO - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/B0 (504:575:647) - (504:575:647)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/A0 (380:454:528) - (380:454:528)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/A1 (385:461:538) - (385:461:538)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/A0 (385:461:538) - (385:461:538)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/D1 (208:243:278) - (208:243:278)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q0 - hades_tdc_bundle_inst_SLICE_118I/D1 (471:536:602)(471:536:602)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q0 hades_drop_cmp_buf_0_I/PADDO - (895:994:1094)(895:994:1094)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q0 - hades_tdc_bundle_inst_SLICE_118I/C1 (351:450:550)(351:450:550)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q0 - hades_drop_cmp_buf_coarse_0_I/PADDO (1199:1350:1502)(1199:1350:1502)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q1 - hades_tdc_bundle_inst_SLICE_118I/B1 (397:464:531)(397:464:531)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_450I/Q1 - hades_drop_cmp_buf_coarse_1_I/PADDO (1527:1719:1911)(1527:1719:1911)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q1 - hades_tdc_bundle_inst_SLICE_118I/A1 (673:781:890)(673:781:890)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_445I/Q1 hades_drop_cmp_buf_1_I/PADDO - (1068:1208:1348)(1068:1208:1348)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_118I/FCO - hades_tdc_bundle_inst_SLICE_119I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q1 - hades_tdc_bundle_inst_SLICE_119I/D1 (344:401:458)(344:401:458)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q1 - hades_drop_cmp_buf_coarse_5_I/PADDO (1528:1724:1921)(1528:1724:1921)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q1 - hades_tdc_bundle_inst_SLICE_119I/C1 (653:787:921)(653:787:921)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q1 hades_drop_cmp_buf_5_I/PADDO - (1165:1280:1395)(1165:1280:1395)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q0 - hades_tdc_bundle_inst_SLICE_119I/B1 (527:614:701)(527:614:701)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_452I/Q0 - hades_drop_cmp_buf_coarse_4_I/PADDO (1408:1582:1757)(1408:1582:1757)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q0 - hades_tdc_bundle_inst_SLICE_119I/A1 (671:775:879)(671:775:879)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_447I/Q0 hades_drop_cmp_buf_4_I/PADDO - (1199:1324:1450)(1199:1324:1450)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q1 - hades_tdc_bundle_inst_SLICE_119I/D0 (343:399:456)(343:399:456)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q1 - hades_drop_cmp_buf_coarse_3_I/PADDO (1621:1818:2016)(1621:1818:2016)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q0 - hades_tdc_bundle_inst_SLICE_119I/C0 (384:497:611)(384:497:611)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q0 hades_drop_cmp_buf_2_I/PADDO - (1253:1395:1537)(1253:1395:1537)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q0 - hades_tdc_bundle_inst_SLICE_119I/B0 (526:612:699)(526:612:699)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_451I/Q0 - hades_drop_cmp_buf_coarse_2_I/PADDO (1197:1351:1505)(1197:1351:1505)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q1 - hades_tdc_bundle_inst_SLICE_119I/A0 (797:913:1029)(797:913:1029)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_446I/Q1 hades_drop_cmp_buf_3_I/PADDO - (1226:1373:1521)(1226:1373:1521)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_119I/FCO - hades_tdc_bundle_inst_SLICE_120I/FCI (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_449I/Q0 - hades_tdc_bundle_inst_SLICE_120I/D1 (488:559:630)(488:559:630)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_449I/Q0 hades_drop_cmp_buf_8_I/PADDO - (1182:1308:1435)(1182:1308:1435)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/Q0 - hades_tdc_bundle_inst_SLICE_120I/C1 (417:539:662)(417:539:662)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/Q0 - hades_drop_cmp_buf_coarse_9_I/PADDO (1586:1785:1985)(1586:1785:1985)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_454I/Q0 - hades_tdc_bundle_inst_SLICE_120I/B1 (509:583:658)(509:583:658)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_454I/Q0 - hades_drop_cmp_buf_coarse_8_I/PADDO (1537:1718:1900)(1537:1718:1900)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q1 - hades_tdc_bundle_inst_SLICE_120I/D0 (323:366:410)(323:366:410)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q1 - hades_drop_cmp_buf_coarse_7_I/PADDO (1250:1414:1579)(1250:1414:1579)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q0 - hades_tdc_bundle_inst_SLICE_120I/C0 (351:450:550)(351:450:550)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_453I/Q0 - hades_drop_cmp_buf_coarse_6_I/PADDO (1380:1557:1735)(1380:1557:1735)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q0 - hades_tdc_bundle_inst_SLICE_120I/B0 (542:630:718)(542:630:718)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q0 hades_drop_cmp_buf_6_I/PADDO - (936:1059:1182)(936:1059:1182)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q1 - hades_tdc_bundle_inst_SLICE_120I/A0 (642:743:845)(642:743:845)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_448I/Q1 hades_drop_cmp_buf_7_I/PADDO - (1325:1450:1576)(1325:1450:1576)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_121I/D1 (475:546:617)(475:546:617)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_122I/D1 (203:240:278)(203:240:278)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_122I/B0 (386:453:520)(386:453:520)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_123I/A1 (711:850:989)(711:850:989)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_123I/C0 (680:843:1007)(680:843:1007)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_432I/D1 (232:284:337)(232:284:337)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_432I/C0 (369:484:599)(369:484:599)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_653I/A0 (982:1137:1292)(982:1137:1292)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_654I/C1 (257:365:473)(257:365:473)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 - hades_tdc_bundle_inst_SLICE_683I/C1 (257:365:473)(257:365:473)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q0 hades_hit_out_i_1_I/PADDO - (1061:1198:1336)(1061:1198:1336)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_121I/C1 (580:743:907)(580:743:907)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_122I/B1 (738:876:1014)(738:876:1014)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_123I/B1 (410:490:570)(410:490:570)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_123I/B0 (410:490:570)(410:490:570)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_432I/A0 (873:1034:1195)(873:1034:1195)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_653I/B0 (689:803:917)(689:803:917)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_654I/B1 (888:1041:1194)(888:1041:1194)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 - hades_tdc_bundle_inst_SLICE_654I/B0 (888:1041:1194)(888:1041:1194)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/Q0 hades_hit_out_i_2_I/PADDO - (1200:1335:1471)(1200:1335:1471)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_121I/B1 (386:456:526)(386:456:526)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_121I/D0 (100:131:163)(100:131:163)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_122I/C1 (389:520:651)(389:520:651)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_122I/C0 (389:520:651)(389:520:651)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_123I/M0 (671:775:879)(671:775:879)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_432I/D0 (225:275:326)(225:275:326)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_653I/C0 (1002:1211:1421)(1002:1211:1421)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_683I/D1 (225:275:326)(225:275:326)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 - hades_tdc_bundle_inst_SLICE_710I/D0 (228:284:341)(228:284:341)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/Q0 hades_hit_out_i_0_I/PADDO - (1178:1350:1522)(1178:1350:1522)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_121I/A1 (529:628:727)(529:628:727)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_122I/A1 (262:322:382)(262:322:382)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_123I/A0 (705:838:971)(705:838:971)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_432I/B1 (414:493:573)(414:493:573)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_432I/B0 (414:493:573)(414:493:573)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_653I/D0 (584:676:769)(584:676:769)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_654I/A1 (399:486:574)(399:486:574)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 - hades_tdc_bundle_inst_SLICE_683I/A1 (399:486:574)(399:486:574)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/Q1 hades_hit_out_i_3_I/PADDO - (1365:1533:1701)(1365:1533:1701)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_121I/OFX0 - hades_tdc_bundle_inst_SLICE_121I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_741I/F0 - hades_tdc_bundle_inst_SLICE_121I/M0 (332:370:409)(332:370:409)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_121I/LSR (639:721:804) - (639:721:804)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_122I/LSR (634:721:808) - (634:721:808)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_122I/LSR (634:721:808) - (634:721:808)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_123I/LSR (1166:1305:1444) - (1166:1305:1444)) - (INTERCONNECT SLICE_740I/Q0 genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/LSR - (1645:1867:2089)(1645:1867:2089)) - (INTERCONNECT SLICE_740I/Q0 genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/LSR - (1933:2188:2444)(1933:2188:2444)) - (INTERCONNECT SLICE_740I/Q0 genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/LSR - (2737:3090:3444)(2737:3090:3444)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_432I/LSR (396:467:538) - (396:467:538)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_433I/LSR (747:838:929) - (747:838:929)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_434I/LSR (1628:1818:2008) - (1628:1818:2008)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_434I/LSR (1628:1818:2008) - (1628:1818:2008)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_435I/LSR (1628:1818:2008) - (1628:1818:2008)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_435I/LSR (1628:1818:2008) - (1628:1818:2008)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_436I/LSR (1741:1938:2135) - (1741:1938:2135)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_436I/LSR (1741:1938:2135) - (1741:1938:2135)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_437I/LSR (1611:1796:1982) - (1611:1796:1982)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_437I/LSR (1611:1796:1982) - (1611:1796:1982)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_438I/LSR (1628:1818:2008) - (1628:1818:2008)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/LSR (1466:1631:1797) - (1466:1631:1797)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_456I/CE (342:389:437) - (342:389:437)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_457I/CE (487:554:622) - (487:554:622)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_458I/CE (357:414:471) - (357:414:471)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_459I/CE (357:414:471) - (357:414:471)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_460I/CE (379:442:506) - (379:442:506)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/LSR (1573:1755:1937) - (1573:1755:1937)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/LSR - (1545:1730:1916)(1545:1730:1916)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/LSR - (1545:1730:1916)(1545:1730:1916)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/LSR - (1832:2051:2270)(1832:2051:2270)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/LSR - (1832:2051:2270)(1832:2051:2270)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/LSR - (1810:2021:2233)(1810:2021:2233)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/LSR - (1810:2021:2233)(1810:2021:2233)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/LSR - (1567:1760:1953)(1567:1760:1953)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/LSR - (1567:1760:1953)(1567:1760:1953)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/LSR - (1107:1248:1390)(1107:1248:1390)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/LSR - (1107:1248:1390)(1107:1248:1390)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/LSR - (1567:1760:1953)(1567:1760:1953)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/LSR - (1567:1760:1953)(1567:1760:1953)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/LSR - (1810:2021:2233)(1810:2021:2233)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/LSR - (1810:2021:2233)(1810:2021:2233)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/LSR - (1810:2021:2233)(1810:2021:2233)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/A1 (1763:2002:2242) - (1763:2002:2242)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/A0 (1763:2002:2242) - (1763:2002:2242)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/M0 (1443:1617:1791) - (1443:1617:1791)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/C1 (1219:1435:1652) - (1219:1435:1652)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/C0 (1219:1435:1652) - (1219:1435:1652)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/C1 (1598:1848:2099) - (1598:1848:2099)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/C0 (1598:1848:2099) - (1598:1848:2099)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/LSR - (825:932:1039)(825:932:1039)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/LSR - (1383:1548:1714)(1383:1548:1714)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/LSR - (1383:1548:1714)(1383:1548:1714)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/LSR - (1253:1406:1560)(1253:1406:1560)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/LSR - (956:1074:1192)(956:1074:1192)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/CE (713:813:913) - (713:813:913)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/CE (717:820:923) - (717:820:923)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_628I/LSR (660:759:859) - (660:759:859)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_628I/LSR (660:759:859) - (660:759:859)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_653I/M0 (1320:1477:1634) - (1320:1477:1634)) - (INTERCONNECT SLICE_740I/Q0 hades_tdc_bundle_inst_SLICE_693I/A0 (927:1074:1222) - (927:1074:1222)) - (INTERCONNECT SLICE_740I/Q0 genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/LSR - (2499:2836:3174)(2499:2836:3174)) - (INTERCONNECT SLICE_740I/Q0 genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/LSR - (2243:2540:2837)(2243:2540:2837)) - (INTERCONNECT SLICE_740I/Q0 genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/LSR - (1775:2008:2242)(1775:2008:2242)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/A0 - (1591:1814:2037)(1591:1814:2037)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/C0 - (1173:1382:1591)(1173:1382:1591)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/B0 - (1648:1856:2064)(1648:1856:2064)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/A0 - (2024:2286:2549)(2024:2286:2549)) - (INTERCONNECT SLICE_740I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/C0 (1219:1435:1652) - (1219:1435:1652)) - (INTERCONNECT SLICE_740I/Q0 SLICE_740I/D0 (100:131:163)(100:131:163)) - (INTERCONNECT SLICE_740I/Q0 hades_buf_drop_1_MGIOLI/LSR (1068:1212:1357) - (1068:1212:1357)) - (INTERCONNECT SLICE_740I/Q0 FEE_TRG_RELEASE_OUT_MGIOLI/LSR (1463:1651:1839) - (1463:1651:1839)) - (INTERCONNECT SLICE_740I/Q0 FEE_DATAFINISHED_OUT_MGIOLI/LSR (1463:1651:1839) - (1463:1651:1839)) - (INTERCONNECT SLICE_740I/Q0 FEE_DATA_WRITE_OUT_MGIOLI/LSR (1566:1755:1944) - (1566:1755:1944)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/F1 - hades_tdc_bundle_inst_SLICE_122I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_122I/F0 - hades_tdc_bundle_inst_SLICE_122I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_SLICE_123I/D0 (1195:1358:1521)(1195:1358:1521)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/A0 (836:976:1117) - (836:976:1117)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/M0 (791:897:1004) - (791:897:1004)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/B1 (855:991:1127) - (855:991:1127)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/B0 (855:991:1127) - (855:991:1127)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/A1 (705:834:963) - (705:834:963)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/A0 (705:834:963) - (705:834:963)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/B1 (855:991:1127) - (855:991:1127)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/B0 (855:991:1127) - (855:991:1127)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/C1 (250:352:454) - (250:352:454)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/A0 (506:597:688) - (506:597:688)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/A0 (705:834:963) - (705:834:963)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/A0 - (524:619:715)(524:619:715)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/B0 (567:657:748) - (567:657:748)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/B0 (694:798:902) - (694:798:902)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_tdc_bundle_inst_SLICE_741I/A0 (1025:1173:1321)(1025:1173:1321)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/Q0 - hades_discardI/PADDO (1677:1899:2121)(1677:1899:2121)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_123I/OFX0 - hades_tdc_bundle_inst_SLICE_123I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT LVL1_INVALID_TRG_IN_MGIOLI/INFF trb_adapter_inst_SLICE_124I/M0 - (515:570:626)(515:570:626)) - (INTERCONNECT trb_adapter_inst_SLICE_124I/Q0 trb_adapter_inst_SLICE_188I/C1 - (514:639:764)(514:639:764)) - (INTERCONNECT trb_adapter_inst_SLICE_124I/Q0 discardI/PADDO (275:331:387) - (275:331:387)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_125I/C0 - (565:731:897)(565:731:897)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_126I/D1 - (588:734:881)(588:734:881)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_126I/D0 - (588:734:881)(588:734:881)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_127I/D1 - (417:520:623)(417:520:623)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_127I/D0 - (417:520:623)(417:520:623)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_128I/D1 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_128I/D0 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_129I/D1 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_129I/D0 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_130I/C1 - (266:384:502)(266:384:502)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_130I/C0 - (266:384:502)(266:384:502)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_131I/D1 - (345:405:465)(345:405:465)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_131I/D0 - (345:405:465)(345:405:465)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_132I/C1 - (251:356:462)(251:356:462)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_132I/C0 - (251:356:462)(251:356:462)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_133I/B1 - (906:1097:1288)(906:1097:1288)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_133I/B0 - (906:1097:1288)(906:1097:1288)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_134I/D1 - (715:870:1026)(715:870:1026)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_134I/D0 - (715:870:1026)(715:870:1026)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_135I/D1 - (588:734:881)(588:734:881)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_135I/D0 - (588:734:881)(588:734:881)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_136I/D1 - (732:898:1065)(732:898:1065)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_136I/A0 - (1013:1224:1435)(1013:1224:1435)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_137I/D1 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_137I/D0 - (403:502:602)(403:502:602)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_138I/D1 - (580:720:861)(580:720:861)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_138I/B0 - (886:1070:1255)(886:1070:1255)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_139I/D1 - (580:720:861)(580:720:861)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_139I/A0 - (871:1063:1256)(871:1063:1256)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_140I/D1 - (732:898:1065)(732:898:1065)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_140I/D0 - (732:898:1065)(732:898:1065)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_141I/D1 - (651:772:894)(651:772:894)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_141I/D0 - (651:772:894)(651:772:894)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_142I/D1 - (558:691:825)(558:691:825)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_142I/C0 - (435:589:743)(435:589:743)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_143I/D1 - (395:495:596)(395:495:596)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_143I/B0 - (408:491:575)(408:491:575)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_144I/B1 - (711:850:989)(711:850:989)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_144I/B0 - (711:850:989)(711:850:989)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_145I/B1 - (712:852:992)(712:852:992)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_145I/C0 - (442:600:759)(442:600:759)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_146I/M0 - (714:865:1017)(714:865:1017)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_187I/C0 - (123:206:290)(123:206:290)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_187I/M1 - (417:511:606)(417:511:606)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_189I/C1 - (435:589:743)(435:589:743)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_189I/C0 - (435:589:743)(435:589:743)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q0 fifo_colector_inst_SLICE_680I/D1 - (410:509:608)(410:509:608)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 - fifo_colector_inst_SLICE_125I/DI0 (4:8:12)(4:8:12)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_126I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_127I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_128I/CE - (544:637:730)(544:637:730)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_129I/CE - (544:637:730)(544:637:730)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_130I/CE - (1052:1246:1440)(1052:1246:1440)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_131I/CE - (944:1133:1323)(944:1133:1323)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_132I/CE - (944:1133:1323)(944:1133:1323)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_133I/CE - (340:381:423)(340:381:423)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_134I/CE - (340:381:423)(340:381:423)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_134I/CE - (340:381:423)(340:381:423)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_135I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_135I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_136I/CE - (842:982:1123)(842:982:1123)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_136I/CE - (842:982:1123)(842:982:1123)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_137I/CE - (538:627:717)(538:627:717)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_137I/CE - (538:627:717)(538:627:717)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_138I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_138I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_139I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_139I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_140I/CE - (842:982:1123)(842:982:1123)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_140I/CE - (842:982:1123)(842:982:1123)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_141I/CE - (673:777:881)(673:777:881)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_141I/CE - (673:777:881)(673:777:881)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_142I/CE - (735:870:1006)(735:870:1006)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_142I/CE - (735:870:1006)(735:870:1006)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_143I/CE - (563:659:756)(563:659:756)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_143I/CE - (563:659:756)(563:659:756)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_144I/CE - (627:758:889)(627:758:889)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_144I/CE - (627:758:889)(627:758:889)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_145I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_145I/CE - (885:1043:1202)(885:1043:1202)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_146I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/OFX0 fifo_colector_inst_SLICE_146I/CE - (1020:1193:1367)(1020:1193:1367)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_125I/M0 - (696:825:954)(696:825:954)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_126I/A1 - (602:747:893)(602:747:893)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_126I/A0 - (602:747:893)(602:747:893)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_127I/A1 - (602:747:893)(602:747:893)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_127I/A0 - (602:747:893)(602:747:893)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_128I/A1 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_128I/A0 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_129I/A1 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_129I/A0 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_130I/A1 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_130I/A0 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_131I/A1 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_131I/A0 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_132I/A1 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_132I/A0 - (429:536:643)(429:536:643)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_133I/A1 - (737:897:1057)(737:897:1057)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_133I/A0 - (737:897:1057)(737:897:1057)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_146I/M1 - (957:1109:1261)(957:1109:1261)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_187I/B0 - (379:440:501)(379:440:501)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_189I/A0 - (556:674:793)(556:674:793)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_190I/A0 - (556:674:793)(556:674:793)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_680I/B0 - (570:681:792)(570:681:792)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/Q1 fifo_colector_inst_SLICE_722I/D0 - (573:698:824)(573:698:824)) - (INTERCONNECT fifo_colector_inst_SLICE_125I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_721I/B0 (713:819:926)(713:819:926)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 - fifo_colector_inst_SLICE_126I/C1 (569:712:855)(569:712:855)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 - fifo_colector_inst_SLICE_126I/C0 (569:712:855)(569:712:855)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 - fifo_colector_inst_SLICE_126I/B1 (795:925:1056)(795:925:1056)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 - fifo_colector_inst_SLICE_126I/B0 (795:925:1056)(795:925:1056)) - (INTERCONNECT fifo_colector_inst_SLICE_126I/OFX0 - fifo_colector_inst_SLICE_126I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 - fifo_colector_inst_SLICE_126I/M0 (754:866:979)(754:866:979)) - (INTERCONNECT fifo_colector_inst_SLICE_126I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA0 (679:781:883)(679:781:883)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 - fifo_colector_inst_SLICE_127I/C1 (569:712:855)(569:712:855)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 - fifo_colector_inst_SLICE_127I/C0 (569:712:855)(569:712:855)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 - fifo_colector_inst_SLICE_127I/B1 (795:921:1047)(795:921:1047)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 - fifo_colector_inst_SLICE_127I/B0 (795:921:1047)(795:921:1047)) - (INTERCONNECT fifo_colector_inst_SLICE_127I/OFX0 - fifo_colector_inst_SLICE_127I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 - fifo_colector_inst_SLICE_127I/M0 (749:870:991)(749:870:991)) - (INTERCONNECT fifo_colector_inst_SLICE_127I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA1 (669:776:884)(669:776:884)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 - fifo_colector_inst_SLICE_128I/C1 (681:819:957)(681:819:957)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 - fifo_colector_inst_SLICE_128I/C0 (681:819:957)(681:819:957)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 - fifo_colector_inst_SLICE_128I/B1 (692:784:877)(692:784:877)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 - fifo_colector_inst_SLICE_128I/B0 (692:784:877)(692:784:877)) - (INTERCONNECT fifo_colector_inst_SLICE_128I/OFX0 - fifo_colector_inst_SLICE_128I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 - fifo_colector_inst_SLICE_128I/M0 (663:750:838)(663:750:838)) - (INTERCONNECT fifo_colector_inst_SLICE_128I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA2 (438:515:593)(438:515:593)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 - fifo_colector_inst_SLICE_129I/C1 (568:698:829)(568:698:829)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 - fifo_colector_inst_SLICE_129I/C0 (568:698:829)(568:698:829)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 - fifo_colector_inst_SLICE_129I/B1 (579:664:749)(579:664:749)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 - fifo_colector_inst_SLICE_129I/B0 (579:664:749)(579:664:749)) - (INTERCONNECT fifo_colector_inst_SLICE_129I/OFX0 - fifo_colector_inst_SLICE_129I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 - fifo_colector_inst_SLICE_129I/M0 (663:750:838)(663:750:838)) - (INTERCONNECT fifo_colector_inst_SLICE_129I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA3 (550:634:719)(550:634:719)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 - fifo_colector_inst_SLICE_130I/D1 (683:773:863)(683:773:863)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 - fifo_colector_inst_SLICE_130I/D0 (683:773:863)(683:773:863)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 - fifo_colector_inst_SLICE_130I/B1 (452:531:611)(452:531:611)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 - fifo_colector_inst_SLICE_130I/B0 (452:531:611)(452:531:611)) - (INTERCONNECT fifo_colector_inst_SLICE_130I/OFX0 - fifo_colector_inst_SLICE_130I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 - fifo_colector_inst_SLICE_130I/M0 (663:750:838)(663:750:838)) - (INTERCONNECT fifo_colector_inst_SLICE_130I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA4 (550:634:719)(550:634:719)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 - fifo_colector_inst_SLICE_131I/C1 (294:399:504)(294:399:504)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 - fifo_colector_inst_SLICE_131I/C0 (294:399:504)(294:399:504)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 - fifo_colector_inst_SLICE_131I/B1 (866:986:1106)(866:986:1106)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 - fifo_colector_inst_SLICE_131I/B0 (866:986:1106)(866:986:1106)) - (INTERCONNECT fifo_colector_inst_SLICE_131I/OFX0 - fifo_colector_inst_SLICE_131I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 - fifo_colector_inst_SLICE_131I/M0 (713:802:892)(713:802:892)) - (INTERCONNECT fifo_colector_inst_SLICE_131I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA5 (550:634:719)(550:634:719)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 - fifo_colector_inst_SLICE_132I/D1 (266:309:353)(266:309:353)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 - fifo_colector_inst_SLICE_132I/D0 (266:309:353)(266:309:353)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 - fifo_colector_inst_SLICE_132I/B1 (727:832:937)(727:832:937)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 - fifo_colector_inst_SLICE_132I/B0 (727:832:937)(727:832:937)) - (INTERCONNECT fifo_colector_inst_SLICE_132I/OFX0 - fifo_colector_inst_SLICE_132I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 - fifo_colector_inst_SLICE_132I/M0 (713:802:892)(713:802:892)) - (INTERCONNECT fifo_colector_inst_SLICE_132I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA6 (698:799:900)(698:799:900)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 - fifo_colector_inst_SLICE_133I/D1 (577:673:770)(577:673:770)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 - fifo_colector_inst_SLICE_133I/D0 (577:673:770)(577:673:770)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 - fifo_colector_inst_SLICE_133I/C1 (569:712:855)(569:712:855)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 - fifo_colector_inst_SLICE_133I/C0 (569:712:855)(569:712:855)) - (INTERCONNECT fifo_colector_inst_SLICE_133I/OFX0 - fifo_colector_inst_SLICE_133I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 - fifo_colector_inst_SLICE_133I/M0 (720:831:943)(720:831:943)) - (INTERCONNECT fifo_colector_inst_SLICE_133I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA7 (539:638:737)(539:638:737)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 - fifo_colector_inst_SLICE_134I/C1 (578:720:863)(578:720:863)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 - fifo_colector_inst_SLICE_134I/A1 (864:991:1118)(864:991:1118)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 - fifo_colector_inst_SLICE_134I/C0 (449:578:707)(449:578:707)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 - fifo_colector_inst_SLICE_134I/B0 (737:854:971)(737:854:971)) - (INTERCONNECT fifo_colector_inst_SLICE_134I/F1 fifo_colector_inst_SLICE_134I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_134I/F0 fifo_colector_inst_SLICE_134I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_134I/LSR - (919:1045:1172)(919:1045:1172)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_134I/LSR - (919:1045:1172)(919:1045:1172)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_135I/LSR - (645:739:834)(645:739:834)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_135I/LSR - (645:739:834)(645:739:834)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_136I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_136I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_137I/LSR - (980:1137:1295)(980:1137:1295)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_137I/LSR - (980:1137:1295)(980:1137:1295)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_138I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_138I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_139I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_139I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_140I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_140I/LSR - (681:791:902)(681:791:902)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_141I/LSR - (957:1107:1258)(957:1107:1258)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_141I/LSR - (957:1107:1258)(957:1107:1258)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_142I/LSR - (505:582:660)(505:582:660)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_142I/LSR - (505:582:660)(505:582:660)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_143I/LSR - (636:725:814)(636:725:814)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_143I/LSR - (636:725:814)(636:725:814)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_144I/LSR - (505:582:660)(505:582:660)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_144I/LSR - (505:582:660)(505:582:660)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_145I/LSR - (645:739:834)(645:739:834)) - (INTERCONNECT fifo_colector_inst_SLICE_722I/F0 fifo_colector_inst_SLICE_145I/LSR - (645:739:834)(645:739:834)) - (INTERCONNECT fifo_colector_inst_SLICE_134I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA8 (411:495:580)(411:495:580)) - (INTERCONNECT fifo_colector_inst_SLICE_134I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA9 (411:495:580)(411:495:580)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 - fifo_colector_inst_SLICE_135I/B1 (721:835:950)(721:835:950)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 - fifo_colector_inst_SLICE_135I/A1 (907:1049:1192)(907:1049:1192)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 - fifo_colector_inst_SLICE_135I/C0 (596:745:894)(596:745:894)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 - fifo_colector_inst_SLICE_135I/B0 (609:716:824)(609:716:824)) - (INTERCONNECT fifo_colector_inst_SLICE_135I/F1 fifo_colector_inst_SLICE_135I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_135I/F0 fifo_colector_inst_SLICE_135I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_135I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA10 (409:491:573)(409:491:573)) - (INTERCONNECT fifo_colector_inst_SLICE_135I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA11 (409:491:573)(409:491:573)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 - fifo_colector_inst_SLICE_136I/B1 (607:710:814)(607:710:814)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 - fifo_colector_inst_SLICE_136I/A1 (593:704:815)(593:704:815)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 - fifo_colector_inst_SLICE_136I/D0 (579:674:770)(579:674:770)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 - fifo_colector_inst_SLICE_136I/C0 (449:578:707)(449:578:707)) - (INTERCONNECT fifo_colector_inst_SLICE_136I/F1 fifo_colector_inst_SLICE_136I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_136I/F0 fifo_colector_inst_SLICE_136I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_136I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA12 (410:490:570)(410:490:570)) - (INTERCONNECT fifo_colector_inst_SLICE_136I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA13 (524:615:706)(524:615:706)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 - fifo_colector_inst_SLICE_137I/C1 (528:642:757)(528:642:757)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 - fifo_colector_inst_SLICE_137I/B1 (574:656:738)(574:656:738)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 - fifo_colector_inst_SLICE_137I/C0 (416:523:631)(416:523:631)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 - fifo_colector_inst_SLICE_137I/A0 (672:768:865)(672:768:865)) - (INTERCONNECT fifo_colector_inst_SLICE_137I/F1 fifo_colector_inst_SLICE_137I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_137I/F0 fifo_colector_inst_SLICE_137I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_137I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA14 (488:561:635)(488:561:635)) - (INTERCONNECT fifo_colector_inst_SLICE_137I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA15 (375:441:508)(375:441:508)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 - fifo_colector_inst_SLICE_138I/C1 (744:903:1063)(744:903:1063)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA17 - fifo_colector_inst_SLICE_138I/B1 (607:712:817)(607:712:817)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA16 - fifo_colector_inst_SLICE_138I/D0 (424:499:575)(424:499:575)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 - fifo_colector_inst_SLICE_138I/C0 (634:791:949)(634:791:949)) - (INTERCONNECT fifo_colector_inst_SLICE_138I/F1 fifo_colector_inst_SLICE_138I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_138I/F0 fifo_colector_inst_SLICE_138I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_138I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA16 (411:495:580)(411:495:580)) - (INTERCONNECT fifo_colector_inst_SLICE_138I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIA17 (654:756:859)(654:756:859)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 - fifo_colector_inst_SLICE_139I/B1 (783:916:1049)(783:916:1049)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB1 - fifo_colector_inst_SLICE_139I/A1 (864:991:1118)(864:991:1118)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB0 - fifo_colector_inst_SLICE_139I/D0 (583:665:748)(583:665:748)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 - fifo_colector_inst_SLICE_139I/B0 (783:916:1049)(783:916:1049)) - (INTERCONNECT fifo_colector_inst_SLICE_139I/F1 fifo_colector_inst_SLICE_139I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_139I/F0 fifo_colector_inst_SLICE_139I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_139I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB0 (409:491:573)(409:491:573)) - (INTERCONNECT fifo_colector_inst_SLICE_139I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB1 (409:491:573)(409:491:573)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 - fifo_colector_inst_SLICE_140I/B1 (813:952:1091)(813:952:1091)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB3 - fifo_colector_inst_SLICE_140I/A1 (722:847:972)(722:847:972)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB2 - fifo_colector_inst_SLICE_140I/C0 (578:720:863)(578:720:863)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 - fifo_colector_inst_SLICE_140I/B0 (660:775:891)(660:775:891)) - (INTERCONNECT fifo_colector_inst_SLICE_140I/F1 fifo_colector_inst_SLICE_140I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_140I/F0 fifo_colector_inst_SLICE_140I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_140I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB2 (410:490:570)(410:490:570)) - (INTERCONNECT fifo_colector_inst_SLICE_140I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB3 (410:490:570)(410:490:570)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 - fifo_colector_inst_SLICE_141I/B1 (759:877:996)(759:877:996)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB5 - fifo_colector_inst_SLICE_141I/A1 (690:791:892)(690:791:892)) - (INTERCONNECT - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOB4 - fifo_colector_inst_SLICE_141I/C0 (546:665:784)(546:665:784)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 - fifo_colector_inst_SLICE_141I/A0 (744:870:997)(744:870:997)) - (INTERCONNECT fifo_colector_inst_SLICE_141I/F1 fifo_colector_inst_SLICE_141I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_141I/F0 fifo_colector_inst_SLICE_141I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_141I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB4 (375:441:508)(375:441:508)) - (INTERCONNECT fifo_colector_inst_SLICE_141I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB5 (278:349:420)(278:349:420)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA9 - fifo_colector_inst_SLICE_142I/C1 (596:759:922)(596:759:922)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA1 - fifo_colector_inst_SLICE_142I/A1 (740:885:1030)(740:885:1030)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA8 - fifo_colector_inst_SLICE_142I/B0 (755:892:1029)(755:892:1029)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA0 - fifo_colector_inst_SLICE_142I/A0 (646:768:891)(646:768:891)) - (INTERCONNECT fifo_colector_inst_SLICE_142I/F1 fifo_colector_inst_SLICE_142I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_142I/F0 fifo_colector_inst_SLICE_142I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_142I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB6 (557:657:757)(557:657:757)) - (INTERCONNECT fifo_colector_inst_SLICE_142I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB7 (669:776:884)(669:776:884)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA11 - fifo_colector_inst_SLICE_143I/C1 (458:588:718)(458:588:718)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA3 - fifo_colector_inst_SLICE_143I/B1 (574:656:738)(574:656:738)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA2 - fifo_colector_inst_SLICE_143I/D0 (391:443:495)(391:443:495)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA10 - fifo_colector_inst_SLICE_143I/A0 (601:713:826)(601:713:826)) - (INTERCONNECT fifo_colector_inst_SLICE_143I/F1 fifo_colector_inst_SLICE_143I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_143I/F0 fifo_colector_inst_SLICE_143I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_143I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB8 (669:776:884)(669:776:884)) - (INTERCONNECT fifo_colector_inst_SLICE_143I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB9 (757:889:1022)(757:889:1022)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA13 - fifo_colector_inst_SLICE_144I/D1 (572:679:787)(572:679:787)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA5 - fifo_colector_inst_SLICE_144I/A1 (593:704:815)(593:704:815)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA4 - fifo_colector_inst_SLICE_144I/C0 (449:578:707)(449:578:707)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA12 - fifo_colector_inst_SLICE_144I/A0 (740:885:1030)(740:885:1030)) - (INTERCONNECT fifo_colector_inst_SLICE_144I/F1 fifo_colector_inst_SLICE_144I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_144I/F0 fifo_colector_inst_SLICE_144I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_144I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB10 (557:657:757)(557:657:757)) - (INTERCONNECT fifo_colector_inst_SLICE_144I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB11 (557:657:757)(557:657:757)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA15 - fifo_colector_inst_SLICE_145I/D1 (596:704:812)(596:704:812)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA7 - fifo_colector_inst_SLICE_145I/C1 (451:583:716)(451:583:716)) - (INTERCONNECT - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA6 - fifo_colector_inst_SLICE_145I/D0 (424:497:571)(424:497:571)) - (INTERCONNECT - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DOA14 - fifo_colector_inst_SLICE_145I/B0 (779:917:1055)(779:917:1055)) - (INTERCONNECT fifo_colector_inst_SLICE_145I/F1 fifo_colector_inst_SLICE_145I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_145I/F0 fifo_colector_inst_SLICE_145I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_145I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB12 (522:609:696)(522:609:696)) - (INTERCONNECT fifo_colector_inst_SLICE_145I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB13 (522:609:696)(522:609:696)) - (INTERCONNECT fifo_colector_inst_SLICE_146I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB14 (334:432:531)(334:432:531)) - (INTERCONNECT fifo_colector_inst_SLICE_146I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DIB15 (411:495:580)(411:495:580)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/F1 - fifo_colector_inst_fifo40_inst_SLICE_147I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/F0 - fifo_colector_inst_fifo40_inst_SLICE_147I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_152I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_147I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_152I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/F1 - fifo_colector_inst_fifo40_inst_SLICE_148I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/F0 - fifo_colector_inst_fifo40_inst_SLICE_148I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_153I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_148I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_153I/M1 (360:408:456)(360:408:456)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/F1 - fifo_colector_inst_fifo40_inst_SLICE_149I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/F0 - fifo_colector_inst_fifo40_inst_SLICE_149I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_154I/M0 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_149I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_154I/M1 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/F1 - fifo_colector_inst_fifo40_inst_SLICE_150I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/F0 - fifo_colector_inst_fifo40_inst_SLICE_150I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_155I/M0 (461:518:576)(461:518:576)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_150I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_155I/M1 (360:408:456)(360:408:456)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/F0 - fifo_colector_inst_fifo40_inst_SLICE_151I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_156I/M0 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_151I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_156I/M1 (231:266:302)(231:266:302)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_152I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_157I/M0 (495:566:638)(495:566:638)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_152I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_157I/M1 (495:566:638)(495:566:638)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_153I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_158I/M0 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_153I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_158I/M1 (461:518:576)(461:518:576)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_154I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_159I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_154I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_159I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_155I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_160I/M0 (360:408:456)(360:408:456)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_155I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_160I/M1 (461:518:576)(461:518:576)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_156I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_161I/M0 (609:679:750)(609:679:750)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_156I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_161I/M1 (609:679:750)(609:679:750)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_677I/B1 (666:772:879)(666:772:879)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_677I/A1 (545:655:765)(545:655:765)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_157I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_678I/B1 (559:661:764)(559:661:764)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_678I/B0 (504:575:647)(504:575:647)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_678I/D0 (217:260:304)(217:260:304)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_158I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_703I/D0 (217:260:304)(217:260:304)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_678I/C0 (243:338:434)(243:338:434)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_679I/C1 (243:338:434)(243:338:434)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_703I/C0 (243:338:434)(243:338:434)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_649I/M0 (476:534:593)(476:534:593)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_678I/A0 (391:471:552)(391:471:552)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_679I/A1 (391:471:552)(391:471:552)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_159I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_703I/A0 (391:471:552)(391:471:552)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_648I/D1 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_648I/D0 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_649I/D1 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_649I/D0 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_677I/A0 (513:607:701)(513:607:701)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_679I/B1 (528:614:700)(528:614:700)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_648I/C1 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_648I/C0 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_649I/A1 (503:590:677)(503:590:677)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_649I/C0 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_677I/C0 (244:345:446)(244:345:446)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_160I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_679I/C0 (244:345:446)(244:345:446)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_648I/A1 (513:607:701)(513:607:701)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_648I/A0 (513:607:701)(513:607:701)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_649I/C1 (369:481:593)(369:481:593)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_649I/A0 (513:607:701)(513:607:701)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_677I/D0 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_679I/D0 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_703I/D1 (226:272:318)(226:272:318)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_648I/B1 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_648I/B0 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_649I/B1 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_649I/B0 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_677I/B0 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_679I/B0 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/A1 (543:649:756)(543:649:756)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/A0 (543:649:756)(543:649:756)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_161I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_703I/B1 (422:506:591)(422:506:591)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_162I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB5 (539:638:737)(539:638:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_162I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB6 (522:609:696)(522:609:696)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_163I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB7 (506:584:662)(506:584:662)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_163I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB8 (411:495:580)(411:495:580)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_164I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB9 (539:638:737)(539:638:737)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_164I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB10 (410:490:570)(410:490:570)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_165I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB11 (724:835:947)(724:835:947)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_165I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB12 (409:491:573)(409:491:573)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADB13 (781:928:1076)(781:928:1076)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/C1 (242:340:439)(242:340:439)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_166I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/C0 (242:340:439)(242:340:439)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/F1 - fifo_colector_inst_fifo40_inst_SLICE_167I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/F0 - fifo_colector_inst_fifo40_inst_SLICE_167I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_172I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_167I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_172I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/F1 - fifo_colector_inst_fifo40_inst_SLICE_168I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/F0 - fifo_colector_inst_fifo40_inst_SLICE_168I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_173I/M0 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_168I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_173I/M1 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/F1 - fifo_colector_inst_fifo40_inst_SLICE_169I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/F0 - fifo_colector_inst_fifo40_inst_SLICE_169I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_174I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_169I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_174I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/F1 - fifo_colector_inst_fifo40_inst_SLICE_170I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/F0 - fifo_colector_inst_fifo40_inst_SLICE_170I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_175I/M0 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_170I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_175I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/F0 - fifo_colector_inst_fifo40_inst_SLICE_171I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_176I/M0 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_171I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_176I/M1 (203:227:251)(203:227:251)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_172I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_177I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_172I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_177I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_173I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_178I/M0 (231:259:288)(231:259:288)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_173I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_178I/M1 (332:370:409)(332:370:409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_174I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_179I/M0 (462:512:562)(462:512:562)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_174I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_179I/M1 (462:512:562)(462:512:562)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_175I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_180I/M0 (361:401:441)(361:401:441)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_175I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_180I/M1 (461:518:576)(461:518:576)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_176I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_181I/M0 (504:576:649)(504:576:649)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_176I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_181I/M1 (504:576:649)(504:576:649)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_673I/C1 (475:591:707)(475:591:707)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_673I/A1 (382:457:532)(382:457:532)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_177I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_674I/B1 (397:464:531)(397:464:531)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_674I/D0 (208:243:278)(208:243:278)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_674I/B0 (397:464:531)(397:464:531)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_178I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_702I/B1 (397:464:531)(397:464:531)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_674I/A0 (500:585:671)(500:585:671)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_676I/B1 (515:592:670)(515:592:670)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_702I/D1 (214:251:289)(214:251:289)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_674I/C0 (359:464:569)(359:464:569)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_675I/A1 (382:461:541)(382:461:541)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_676I/A1 (385:461:538)(385:461:538)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_179I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_702I/A1 (503:590:677)(503:590:677)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_673I/A0 (499:584:670)(499:584:670)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_675I/B1 (525:619:714)(525:619:714)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_676I/C1 (355:458:562)(355:458:562)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_673I/B0 (680:793:907)(680:793:907)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_675I/C1 (368:488:608)(368:488:608)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_180I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_676I/B0 (680:793:907)(680:793:907)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_673I/D0 (217:258:299)(217:258:299)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_675I/D0 (214:257:301)(214:257:301)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_676I/D0 (217:258:299)(217:258:299)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_673I/C0 (354:456:558)(354:456:558)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_675I/B0 (417:506:595)(417:506:595)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_676I/A0 (498:582:667)(498:582:667)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/A1 (538:649:760)(538:649:760)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_181I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_692I/A0 (538:649:760)(538:649:760)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_182I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA5 (375:441:508)(375:441:508)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_182I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA6 (249:301:354)(249:301:354)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_183I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA7 (522:609:696)(522:609:696)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_183I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA8 (391:468:546)(391:468:546)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_184I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA9 (391:468:546)(391:468:546)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_184I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA10 (249:301:354)(249:301:354)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_185I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA11 (278:349:420)(278:349:420)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_185I/Q1 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA12 (391:468:546)(391:468:546)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q0 - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/ADA13 (376:435:494)(376:435:494)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/B1 (527:606:685)(527:606:685)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_186I/Q1 - fifo_colector_inst_fifo40_inst_SLICE_691I/B0 (527:606:685)(527:606:685)) - (INTERCONNECT fifo_colector_inst_SLICE_187I/F0 fifo_colector_inst_SLICE_187I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_188I/B1 - (384:447:511)(384:447:511)) - (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_631I/M1 - (206:233:261)(206:233:261)) - (INTERCONNECT trb_adapter_inst_SLICE_631I/Q0 trb_adapter_inst_SLICE_723I/B0 - (384:447:511)(384:447:511)) - (INTERCONNECT trb_adapter_inst_SLICE_631I/Q1 trb_adapter_inst_SLICE_188I/A1 - (366:434:502)(366:434:502)) - (INTERCONNECT trb_adapter_inst_SLICE_631I/Q1 trb_adapter_inst_SLICE_723I/D0 - (197:228:259)(197:228:259)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_188I/D0 - (93:114:136)(93:114:136)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_632I/M0 - (2781:3054:3327)(2781:3054:3327)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 - fifo_colector_inst_fifo40_inst_SLICE_720I/C0 (2117:2371:2626)(2117:2371:2626)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 trb_adapter_inst_SLICE_724I/LSR - (2780:3049:3318)(2780:3049:3318)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 FEE_DATA_WRITE_OUT_MGIOLI/TXDATA0 - (2802:3087:3372)(2802:3087:3372)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/Q0 fifo_rdenI/PADDO (3622:3972:4322) - (3622:3972:4322)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/F1 trb_adapter_inst_SLICE_188I/B0 - (276:327:379)(276:327:379)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/F1 burstI/PADDO (275:331:387) - (275:331:387)) - (INTERCONNECT trb_adapter_inst_SLICE_188I/F0 trb_adapter_inst_SLICE_188I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/Q1 fifo_colector_inst_SLICE_189I/B1 - (275:325:375)(275:325:375)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I/D0 (194:223:253) - (194:223:253)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/Q0 fifo_colector_inst_SLICE_189I/D0 - (93:114:136)(93:114:136)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I/B0 (542:630:718) - (542:630:718)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/F1 fifo_colector_inst_SLICE_189I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_189I/F0 fifo_colector_inst_SLICE_189I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_189I/LSR - (202:222:243)(202:222:243)) - (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_189I/LSR - (202:222:243)(202:222:243)) - (INTERCONNECT fifo_colector_inst_SLICE_680I/F0 fifo_colector_inst_SLICE_190I/LSR - (202:222:243)(202:222:243)) - (INTERCONNECT fifo_colector_inst_SLICE_190I/Q0 fifo_colector_inst_SLICE_190I/D0 - (93:114:136)(93:114:136)) - (INTERCONNECT fifo_colector_inst_SLICE_190I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I/D0 (384:456:529) - (384:456:529)) - (INTERCONNECT fifo_colector_inst_SLICE_190I/F0 fifo_colector_inst_SLICE_190I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/M0 (637:705:774) - (637:705:774)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/M0 (378:426:475) - (378:426:475)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/M1 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/M1 (337:378:419) - (337:378:419)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/A0 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/D0 (208:243:278) - (208:243:278)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/A0 (506:597:689) - (506:597:689)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/B0 (380:441:502) - (380:441:502)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/M0 (208:235:263) - (208:235:263)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/A1 (366:434:502) - (366:434:502)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/C0 (222:308:394) - (222:308:394)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/B1 (380:441:502) - (380:441:502)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/B0 (380:441:502) - (380:441:502)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/C1 (242:340:439) - (242:340:439)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/A0 (512:607:702) - (512:607:702)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/D1 (214:251:289) - (214:251:289)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/D0 (214:251:289) - (214:251:289)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/C0 (216:299:382) - (216:299:382)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I/OFX0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/C0 (114:188:262) - (114:188:262)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/F0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I/F0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/LSR (331:365:400) - (331:365:400)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/M0 (1329:1479:1629) - (1329:1479:1629)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/B0 (1340:1487:1634) - (1340:1487:1634)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/M0 (1291:1409:1528) - (1291:1409:1528)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/M1 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/B1 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/A1 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/B0 (521:604:688) - (521:604:688)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/D0 (217:260:304) - (217:260:304)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/A0 (625:726:828) - (625:726:828)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/C0 (238:331:424) - (238:331:424)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/A1 (760:868:976) - (760:868:976)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/C0 (504:622:741) - (504:622:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/M0 (477:535:594) - (477:535:594)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/A0 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/D1 (465:527:589) - (465:527:589)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/B0 (536:620:705) - (536:620:705)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/C1 (360:466:573) - (360:466:573)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/C0 (360:466:573) - (360:466:573)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/C1 (231:323:416) - (231:323:416)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/C0 (231:323:416) - (231:323:416)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/D0 (217:258:299) - (217:258:299)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/B1 (389:456:523) - (389:456:523)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/B1 (401:472:543) - (401:472:543)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/B0 (401:472:543) - (401:472:543)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/A1 (390:474:559) - (390:474:559)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/A0 (390:474:559) - (390:474:559)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/C0 (246:348:451) - (246:348:451)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/C0 (373:489:605) - (373:489:605)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/A1 (377:455:533) - (377:455:533)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/A0 (377:455:533) - (377:455:533)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/D1 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/D0 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/B0 (391:461:532) - (391:461:532)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/D0 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/C1 (242:344:446) - (242:344:446)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/D1 (205:241:277) - (205:241:277)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/D0 (205:241:277) - (205:241:277)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/B1 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I/B0 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/A0 (374:447:520) - (374:447:520)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I/B0 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/A1 (533:632:732) - (533:632:732)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/A0 (533:632:732) - (533:632:732)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I/B1 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 - (521:610:700)(521:610:700)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 - (539:638:737)(539:638:737)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 - (564:666:768)(564:666:768)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 - (547:644:741)(547:644:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 - (411:495:580)(411:495:580)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 - (411:495:580)(411:495:580)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 - (539:638:737)(539:638:737)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 - (652:750:849)(652:750:849)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 - (669:776:884)(669:776:884)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/B0 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/M0 (609:679:750) - (609:679:750)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/M1 (609:679:750) - (609:679:750)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/F1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/M1 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/C1 (236:331:427) - (236:331:427)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/A0 (360:425:490) - (360:425:490)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/C0 (219:303:388) - (219:303:388)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/B0 (394:460:527) - (394:460:527)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/D0 (195:225:256) - (195:225:256)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/A1 (628:725:822) - (628:725:822)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/C0 (242:338:434) - (242:338:434)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/M0 (475:532:590) - (475:532:590)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/B0 (523:609:695) - (523:609:695)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/B1 (534:618:702) - (534:618:702)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/A0 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/A1 (372:446:521) - (372:446:521)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/A0 (372:446:521) - (372:446:521)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/D1 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/D0 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/A0 (366:437:509) - (366:437:509)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/D1 (224:271:318) - (224:271:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/C1 (230:321:412) - (230:321:412)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/C0 (230:321:412) - (230:321:412)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/B1 (403:475:548) - (403:475:548)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/B0 (403:475:548) - (403:475:548)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/C0 (230:321:412) - (230:321:412)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/B0 (403:475:548) - (403:475:548)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/D1 (226:272:318) - (226:272:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/D0 (226:272:318) - (226:272:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/C1 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/C0 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/D0 (226:272:318) - (226:272:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/C0 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/D1 (226:272:318) - (226:272:318)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/B1 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/B0 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/A1 (537:639:742) - (537:639:742)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I/A0 (537:639:742) - (537:639:742)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/B0 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I/A0 (537:639:742) - (537:639:742)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/A1 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I/A0 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I/B1 (412:489:567) - (412:489:567)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 - (547:644:741)(547:644:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 - (652:750:849)(652:750:849)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 - (434:524:615)(434:524:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 - (434:524:615)(434:524:615)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 - (547:644:741)(547:644:741)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 - (540:631:723)(540:631:723)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 - (564:666:768)(564:666:768)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/C1 (482:593:705) - (482:593:705)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I/C0 (482:593:705) - (482:593:705)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/D0 (93:114:136)(93:114:136)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 - (348:456:565)(348:456:565)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 - (593:725:858)(593:725:858)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 - (593:725:858)(593:725:858)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 - (608:749:891)(608:749:891)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 - (608:749:891)(608:749:891)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 - (608:749:891)(608:749:891)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 - (484:612:740)(484:612:740)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 - (484:612:740)(484:612:740)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/F0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/M1 (485:549:613) - (485:549:613)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/M1 (384:438:492) - (384:438:492)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/M1 (347:394:442) - (347:394:442)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/M1 (485:549:613) - (485:549:613)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/M1 (347:394:442) - (347:394:442)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/M1 (477:536:595) - (477:536:595)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/M1 (477:536:595) - (477:536:595)) - (INTERCONNECT SLICE_744I/F0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/M1 (384:438:492) - (384:438:492)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOP pll0inst_PLLInst_0I/CLKFB (1523:1620:1717) - (1523:1620:1717)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/M0 (231:266:302) - (231:266:302)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/CLK (1484:1569:1654) - (1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT pll0inst_PLLInst_0I/CLKOS2 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/CLK - (1484:1569:1654)(1484:1569:1654)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/Q1 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/M0 (361:401:441) - (361:401:441)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/M1 (350:408:466) - (350:408:466)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/M0 (504:576:649) - (504:576:649)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/M1 (403:466:529) - (403:466:529)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/M0 (350:408:466) - (350:408:466)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/M0 (378:444:510) - (378:444:510)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/M0 (248:296:345) - (248:296:345)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/M1 (350:408:466) - (350:408:466)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/M0 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/M1 (350:408:466) - (350:408:466)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/M1 (464:523:583) - (464:523:583)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/B0 (394:460:527) - (394:460:527)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/D0 (208:243:278) - (208:243:278)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/B0 (391:455:520) - (391:455:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/A0 (363:431:500) - (363:431:500)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/M0 (234:273:312) - (234:273:312)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/D1 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/D0 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/B1 (425:514:604) - (425:514:604)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/B0 (425:514:604) - (425:514:604)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/A1 (513:615:718) - (513:615:718)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/A0 (513:615:718) - (513:615:718)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/C1 (256:369:482) - (256:369:482)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/C0 (256:369:482) - (256:369:482)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/D0 (191:218:246) - (191:218:246)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I/OFX0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/C0 (114:188:262) - (114:188:262)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/F0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I/F0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/LSR (349:403:458) - (349:403:458)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/M0 (637:722:808) - (637:722:808)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/A0 (1268:1479:1690) - (1268:1479:1690)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/M0 (875:987:1100)(875:987:1100)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/M1 (378:444:510) - (378:444:510)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/M1 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/M0 (378:444:510) - (378:444:510)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/M1 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/M1 (255:307:360) - (255:307:360)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/B1 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/A1 (386:467:548) - (386:467:548)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/A1 (386:467:548) - (386:467:548)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/C0 (233:323:413) - (233:323:413)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/B0 (397:468:540) - (397:468:540)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/A0 (509:602:695) - (509:602:695)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/D0 (220:267:314) - (220:267:314)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/D1 (230:287:345) - (230:287:345)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/B0 (403:480:557) - (403:480:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/M0 (488:562:637) - (488:562:637)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/A0 (388:471:554) - (388:471:554)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/B1 (417:506:595) - (417:506:595)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/C0 (244:345:446) - (244:345:446)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/C1 (266:384:503) - (266:384:503)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/A0 (783:918:1053) - (783:918:1053)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/A1 (372:446:521) - (372:446:521)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/A0 (372:446:521) - (372:446:521)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/D0 (372:450:529) - (372:450:529)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/A1 (653:776:899) - (653:776:899)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/B1 (687:805:924) - (687:805:924)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/B0 (687:805:924) - (687:805:924)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/C1 (225:312:400) - (225:312:400)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/C0 (225:312:400) - (225:312:400)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/C0 (505:641:778) - (505:641:778)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/C0 (505:641:778) - (505:641:778)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/D1 (243:309:376) - (243:309:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/D0 (243:309:376) - (243:309:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/D1 (243:309:376) - (243:309:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/D0 (243:309:376) - (243:309:376)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/A0 (650:770:890) - (650:770:890)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/D0 (369:444:520) - (369:444:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/D1 (369:444:520) - (369:444:520)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/A1 (529:642:755) - (529:642:755)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/C0 (386:516:647) - (386:516:647)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/B1 (426:520:615) - (426:520:615)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I/B0 (426:520:615) - (426:520:615)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/B0 (565:677:789) - (565:677:789)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I/A0 (551:670:790) - (551:670:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/A1 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/A0 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I/A1 (551:670:790) - (551:670:790)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 - (706:813:920)(706:813:920)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 - (798:922:1047)(798:922:1047)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 - (706:813:920)(706:813:920)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 - (567:657:747)(567:657:747)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 - (570:664:759)(570:664:759)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 - (495:603:712)(495:603:712)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 - (567:673:779)(567:673:779)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 - (698:861:1024)(698:861:1024)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 - (748:863:979)(748:863:979)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/D1 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/D0 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/F1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/M1 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/D1 (338:392:446) - (338:392:446)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/A1 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/D0 (339:385:431) - (339:385:431)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/A0 (625:719:814) - (625:719:814)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/B0 (640:726:813) - (640:726:813)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/C0 (373:480:587) - (373:480:587)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/D1 (478:541:605) - (478:541:605)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/A0 (629:725:822) - (629:725:822)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/M0 (233:270:308) - (233:270:308)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/B0 (534:618:702) - (534:618:702)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/A1 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/D0 (464:524:585) - (464:524:585)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/B1 (528:615:702) - (528:615:702)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/B0 (528:615:702) - (528:615:702)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/C1 (247:345:444) - (247:345:444)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/C0 (247:345:444) - (247:345:444)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/D0 (346:402:459) - (346:402:459)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/B1 (778:881:984) - (778:881:984)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/A1 (399:485:572) - (399:485:572)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/A0 (399:485:572) - (399:485:572)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/A1 (399:485:572) - (399:485:572)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/A0 (399:485:572) - (399:485:572)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/B0 (526:611:697) - (526:611:697)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/B0 (674:776:878) - (674:776:878)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/C1 (254:359:464) - (254:359:464)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/C0 (254:359:464) - (254:359:464)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/B1 (403:480:557) - (403:480:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/B0 (403:480:557) - (403:480:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/C0 (254:359:464) - (254:359:464)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/C0 (385:501:617) - (385:501:617)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/D1 (230:279:328) - (230:279:328)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/D1 (343:398:454) - (343:398:454)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/D0 (343:398:454) - (343:398:454)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/D1 (200:232:265) - (200:232:265)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I/D0 (200:232:265) - (200:232:265)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/A0 (393:475:558) - (393:475:558)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I/A0 (775:893:1012) - (775:893:1012)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/A1 (533:632:732) - (533:632:732)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I/A0 (533:632:732) - (533:632:732)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I/B1 (408:482:557) - (408:482:557)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 - (540:631:723)(540:631:723)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 - (652:750:849)(652:750:849)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 - (564:666:768)(564:666:768)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 - (677:785:894)(677:785:894)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 - (478:579:680)(478:579:680)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 - (591:698:806)(591:698:806)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 - (688:811:935)(688:811:935)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 - (695:824:953)(695:824:953)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 - (706:824:943)(706:824:943)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/C1 (222:308:394) - (222:308:394)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I/C0 (222:308:394) - (222:308:394)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/D0 (95:120:145)(95:120:145)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 - (427:523:619)(427:523:619)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 - (539:642:746)(539:642:746)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 - (294:377:460)(294:377:460)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 - (406:496:586)(406:496:586)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 - (675:793:912)(675:793:912)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 - (675:793:912)(675:793:912)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 - (429:526:624)(429:526:624)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 - (429:526:624)(429:526:624)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/F0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/M1 (632:716:800) - (632:716:800)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/M1 (493:559:626) - (493:559:626)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/M1 (626:706:787) - (626:706:787)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/M1 (525:596:667) - (525:596:667)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/M1 (632:716:800) - (632:716:800)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/M1 (340:384:428) - (340:384:428)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/M1 (340:384:428) - (340:384:428)) - (INTERCONNECT SLICE_745I/F0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/M1 (493:559:626) - (493:559:626)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/M0 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/Q1 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/M1 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/M0 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/M1 (361:401:441) - (361:401:441)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/M0 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/M1 (490:549:609) - (490:549:609)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/M1 (208:235:263) - (208:235:263)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/C0 (222:308:394) - (222:308:394)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/B0 (504:575:647) - (504:575:647)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/A0 (377:449:521) - (377:449:521)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/C0 (239:338:437) - (239:338:437)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/M0 (206:233:261) - (206:233:261)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/A1 (366:434:502) - (366:434:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/A0 (366:434:502) - (366:434:502)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/D1 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/D0 (197:228:259) - (197:228:259)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/B1 (400:473:547) - (400:473:547)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/B0 (400:473:547) - (400:473:547)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/C1 (368:472:577) - (368:472:577)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/C0 (368:472:577) - (368:472:577)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/D0 (191:218:246) - (191:218:246)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I/OFX0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/D0 (208:243:278) - (208:243:278)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/F0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I/F0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/LSR (331:365:400) - (331:365:400)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/M0 (1161:1296:1431) - (1161:1296:1431)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/B0 (690:802:914)(690:802:914)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/M0 (467:520:573)(467:520:573)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/B1 (394:464:534) - (394:464:534)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/A1 (363:429:496) - (363:429:496)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/A1 (382:461:541) - (382:461:541)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/D0 (208:243:278) - (208:243:278)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/B0 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/B0 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/C0 (242:338:434) - (242:338:434)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/D1 (341:398:456) - (341:398:456)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/C0 (242:338:434) - (242:338:434)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/M0 (344:390:436) - (344:390:436)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/A0 (389:468:548) - (389:468:548)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/B1 (377:436:495) - (377:436:495)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/A0 (389:468:548) - (389:468:548)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/D1 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/D0 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/D1 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/D0 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/D0 (218:258:299) - (218:258:299)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/A1 (499:583:668) - (499:583:668)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/B1 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/B0 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/B1 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/B0 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/B0 (401:471:541) - (401:471:541)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/A0 (386:464:542) - (386:464:542)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/C1 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/C0 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/C1 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/C0 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/C0 (243:338:434) - (243:338:434)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/D0 (218:258:299) - (218:258:299)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/C1 (391:509:628) - (391:509:628)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/A1 (543:649:756) - (543:649:756)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/A0 (543:649:756) - (543:649:756)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/A1 (543:649:756) - (543:649:756)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I/A0 (543:649:756) - (543:649:756)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/A0 (395:478:562) - (395:478:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I/B0 (409:485:561) - (409:485:561)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/B1 (409:485:561) - (409:485:561)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/B0 (409:485:561) - (409:485:561)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I/A1 (543:649:756) - (543:649:756)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB5 - (723:854:985)(723:854:985)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB6 - (723:854:985)(723:854:985)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB7 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB8 - (411:495:580)(411:495:580)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB9 - (598:721:844)(598:721:844)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB10 - (670:773:876)(670:773:876)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB11 - (598:721:844)(598:721:844)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB12 - (598:721:844)(598:721:844)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADB13 - (869:1009:1149)(869:1009:1149)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/C1 (351:451:552) - (351:451:552)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/C0 (351:451:552) - (351:451:552)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/M0 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/M1 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/F1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/M0 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/M1 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/M0 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/M1 (479:537:596) - (479:537:596)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/M1 (231:266:302) - (231:266:302)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/D1 (208:243:278) - (208:243:278)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/B1 (397:464:531) - (397:464:531)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/A0 (489:568:648) - (489:568:648)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/C0 (242:340:439) - (242:340:439)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/C0 (242:340:439) - (242:340:439)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/D0 (217:258:299) - (217:258:299)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/A1 (363:431:500) - (363:431:500)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/A0 (498:583:668) - (498:583:668)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/M0 (207:234:262) - (207:234:262)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/B0 (401:472:543) - (401:472:543)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/B1 (379:440:501) - (379:440:501)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/B0 (401:472:543) - (401:472:543)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/D1 (222:265:308) - (222:265:308)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/D0 (222:265:308) - (222:265:308)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/D1 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/D0 (362:422:483) - (362:422:483)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/D0 (222:265:308) - (222:265:308)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/C1 (499:621:744) - (499:621:744)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/B1 (405:478:551) - (405:478:551)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/B0 (405:478:551) - (405:478:551)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/B1 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/B0 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/B0 (405:478:551) - (405:478:551)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/B0 (545:635:725) - (545:635:725)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/C1 (398:519:641) - (398:519:641)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/C0 (398:519:641) - (398:519:641)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/C1 (538:676:815) - (538:676:815)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/C0 (538:676:815) - (538:676:815)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/C0 (398:519:641) - (398:519:641)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/C0 (538:676:815) - (538:676:815)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/C1 (398:519:641) - (398:519:641)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/A1 (667:781:896) - (667:781:896)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/A0 (667:781:896) - (667:781:896)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/A1 (523:617:712) - (523:617:712)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I/A0 (523:617:712) - (523:617:712)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/A0 (667:781:896) - (667:781:896)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I/A0 (523:617:712) - (523:617:712)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/A1 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I/A0 (385:461:538) - (385:461:538)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I/B1 (682:788:895) - (682:788:895)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA5 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA6 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA7 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA8 - (521:610:700)(521:610:700)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA9 - (411:495:580)(411:495:580)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA10 - (539:638:737)(539:638:737)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA11 - (539:638:737)(539:638:737)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA12 - (522:609:696)(522:609:696)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/ADA13 - (710:840:970)(710:840:970)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/A1 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I/A0 (382:457:532) - (382:457:532)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/C0 (117:194:272)(117:194:272)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA15 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA13 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA12 - (427:518:610)(427:518:610)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA11 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIA9 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB9 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB8 - (550:655:761)(550:655:761)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I/DIB6 - (720:856:993)(720:856:993)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/F0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/M1 (343:387:432) - (343:387:432)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/M1 (487:551:616) - (487:551:616)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/M1 (617:693:769) - (617:693:769)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/M1 (343:387:432) - (343:387:432)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/M1 (617:693:769) - (617:693:769)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/M1 (380:431:483) - (380:431:483)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/M1 (487:551:616) - (487:551:616)) - (INTERCONNECT SLICE_746I/F0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/M1 (481:542:603) - (481:542:603)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I/M0 (203:227:251) - (203:227:251)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/Q1 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/F0 - hades_tdc_bundle_inst_SLICE_432I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/Q0 - hades_tdc_bundle_inst_SLICE_433I/M0 (744:829:914)(744:829:914)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/Q0 hades_buf_finishedI/PADDO - (1026:1137:1249)(1026:1137:1249)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_432I/F1 - hades_tdc_bundle_inst_SLICE_654I/A0 (258:314:370)(258:314:370)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_457I/B1 (928:1054:1180)(928:1054:1180)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_457I/D0 (632:721:811)(632:721:811)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_458I/D1 (615:700:786)(615:700:786)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_458I/D0 (615:700:786)(615:700:786)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_459I/C1 (522:652:782)(522:652:782)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_459I/C0 (522:652:782)(522:652:782)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_460I/B1 (648:740:832)(648:740:832)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 - hades_tdc_bundle_inst_SLICE_460I/C0 (378:488:598)(378:488:598)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_433I/Q0 hades_buf_releaseI/PADDO - (1031:1166:1301)(1031:1166:1301)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F1 - hades_tdc_bundle_inst_SLICE_434I/DI1 (3:6:10)(3:6:10)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F1 - hades_tdc_bundle_inst_SLICE_450I/M1 (670:760:850)(670:760:850)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F0 - hades_tdc_bundle_inst_SLICE_434I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_434I/F0 - hades_tdc_bundle_inst_SLICE_450I/M0 (643:724:806)(643:724:806)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_SLICE_435I/B1 (386:453:520)(386:453:520)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_SLICE_435I/C0 (120:200:281)(120:200:281)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_SLICE_438I/A1 (372:446:521)(372:446:521)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/M1 - (1029:1155:1282)(1029:1155:1282)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/M1 (487:554:622) - (487:554:622)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_SLICE_681I/C1 (253:358:463)(253:358:463)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/C1 (253:358:463) - (253:358:463)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/A0 (509:603:697) - (509:603:697)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 hades_dbg2_coarse_2_I/PADDO - (2163:2415:2667)(2163:2415:2667)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/Q0 hades_offset_5_MGIOLI/TXDATA0 - (1830:2041:2252)(1830:2041:2252)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F1 - hades_tdc_bundle_inst_SLICE_435I/DI1 (3:6:10)(3:6:10)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F1 - hades_tdc_bundle_inst_SLICE_451I/M1 (684:774:864)(684:774:864)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F0 - hades_tdc_bundle_inst_SLICE_435I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_435I/F0 - hades_tdc_bundle_inst_SLICE_451I/M0 (513:583:653)(513:583:653)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_436I/C1 (222:311:400)(222:311:400)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_436I/D0 (95:120:145)(95:120:145)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_455I/D1 (358:419:481)(358:419:481)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/M1 - (1225:1368:1512)(1225:1368:1512)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/M1 - (891:1002:1113)(891:1002:1113)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_681I/C0 (769:924:1080)(769:924:1080)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_698I/D1 (632:725:818)(632:725:818)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_698I/D0 (632:725:818)(632:725:818)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 - hades_tdc_bundle_inst_SLICE_701I/D1 (358:419:481)(358:419:481)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 hades_dbg2_coarse_4_I/PADDO - (2449:2712:2975)(2449:2712:2975)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/Q0 hades_offset_7_MGIOLI/TXDATA0 - (1544:1734:1924)(1544:1734:1924)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F1 - hades_tdc_bundle_inst_SLICE_436I/DI1 (3:6:10)(3:6:10)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F1 - hades_tdc_bundle_inst_SLICE_452I/M1 (360:411:462)(360:411:462)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F0 - hades_tdc_bundle_inst_SLICE_436I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_436I/F0 - hades_tdc_bundle_inst_SLICE_452I/M0 (359:408:458)(359:408:458)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F1 - hades_tdc_bundle_inst_SLICE_437I/DI1 (3:6:10)(3:6:10)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F1 - hades_tdc_bundle_inst_SLICE_453I/M1 (514:585:657)(514:585:657)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F0 - hades_tdc_bundle_inst_SLICE_437I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_437I/F0 - hades_tdc_bundle_inst_SLICE_453I/M0 (513:583:653)(513:583:653)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F0 - hades_tdc_bundle_inst_SLICE_438I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_438I/F0 - hades_tdc_bundle_inst_SLICE_454I/M0 (669:757:846)(669:757:846)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/Q1 - hades_tdc_bundle_inst_SLICE_439I/M1 (643:727:811)(643:727:811)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/Q0 - hades_tdc_bundle_inst_SLICE_439I/M0 (511:579:647)(511:579:647)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_439I/CE (345:387:430)(345:387:430)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_439I/CE (345:387:430)(345:387:430)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_440I/CE (345:387:430)(345:387:430)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_440I/CE (345:387:430)(345:387:430)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_441I/CE (469:520:571)(469:520:571)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_441I/CE (469:520:571)(469:520:571)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_442I/CE (1077:1195:1313)(1077:1195:1313)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_442I/CE (1077:1195:1313)(1077:1195:1313)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 - hades_tdc_bundle_inst_SLICE_443I/CE (817:912:1007)(817:912:1007)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_28_MGIOLI/CE - (1280:1433:1586)(1280:1433:1586)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_27_MGIOLI/CE - (1259:1404:1550)(1259:1404:1550)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_26_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_25_MGIOLI/CE - (1426:1598:1771)(1426:1598:1771)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_24_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_23_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_22_MGIOLI/CE - (1162:1289:1416)(1162:1289:1416)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_21_MGIOLI/CE - (1253:1395:1538)(1253:1395:1538)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_20_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_18_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_17_MGIOLI/CE - (1280:1433:1586)(1280:1433:1586)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_16_MGIOLI/CE - (1205:1335:1465)(1205:1335:1465)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_2_MGIOLI/CE - (1205:1335:1465)(1205:1335:1465)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_1_MGIOLI/CE - (1259:1404:1550)(1259:1404:1550)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F0 hades_dbg2_out_0_MGIOLI/CE - (1431:1606:1781)(1431:1606:1781)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q0 - hades_tdc_bundle_inst_SLICE_445I/M0 (614:687:760)(614:687:760)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q0 hades_dbg2_out_4_I/PADDO - (1518:1682:1846)(1518:1682:1846)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q1 - hades_tdc_bundle_inst_SLICE_445I/M1 (495:557:620)(495:557:620)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_439I/Q1 hades_dbg2_out_5_I/PADDO - (1127:1260:1393)(1127:1260:1393)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/Q1 - hades_tdc_bundle_inst_SLICE_440I/M1 (511:579:647)(511:579:647)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/Q0 - hades_tdc_bundle_inst_SLICE_440I/M0 (511:579:647)(511:579:647)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q0 - hades_tdc_bundle_inst_SLICE_446I/M0 (466:526:587)(466:526:587)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q0 hades_dbg2_out_6_I/PADDO - (1239:1379:1519)(1239:1379:1519)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q1 - hades_tdc_bundle_inst_SLICE_446I/M1 (597:669:741)(597:669:741)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_440I/Q1 hades_dbg2_out_7_I/PADDO - (1127:1260:1393)(1127:1260:1393)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/Q1 - hades_tdc_bundle_inst_SLICE_441I/M1 (643:727:811)(643:727:811)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/Q0 - hades_tdc_bundle_inst_SLICE_441I/M0 (651:728:806)(651:728:806)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q0 - hades_tdc_bundle_inst_SLICE_447I/M0 (467:520:573)(467:520:573)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q0 hades_dbg2_out_8_I/PADDO - (1198:1344:1490)(1198:1344:1490)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q1 - hades_tdc_bundle_inst_SLICE_447I/M1 (464:523:583)(464:523:583)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_441I/Q1 hades_dbg2_out_9_I/PADDO - (1206:1344:1482)(1206:1344:1482)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/Q1 - hades_tdc_bundle_inst_SLICE_442I/M1 (462:512:562)(462:512:562)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/Q0 - hades_tdc_bundle_inst_SLICE_442I/M0 (462:512:562)(462:512:562)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q0 - hades_tdc_bundle_inst_SLICE_448I/M0 (674:754:834)(674:754:834)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q0 hades_dbg2_out_10_I/PADDO - (1359:1529:1700)(1359:1529:1700)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q1 - hades_tdc_bundle_inst_SLICE_448I/M1 (674:754:834)(674:754:834)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_442I/Q1 hades_dbg2_out_11_I/PADDO - (1563:1746:1930)(1563:1746:1930)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/Q0 - hades_tdc_bundle_inst_SLICE_443I/M0 (332:370:409)(332:370:409)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_443I/Q0 - hades_tdc_bundle_inst_SLICE_449I/M0 (834:923:1013)(834:923:1013)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_443I/Q0 hades_dbg2_out_12_I/PADDO - (1372:1531:1691)(1372:1531:1691)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/C1 (117:192:268) - (117:192:268)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/DI0 (3:4:6)(3:4:6)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/A1 (662:777:892) - (662:777:892)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/D0 (494:571:649) - (494:571:649)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/D0 (195:225:256) - (195:225:256)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/D0 (1158:1302:1447) - (1158:1302:1447)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/B0 (1197:1357:1517) - (1197:1357:1517)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/Q0 - hades_invalid_dl_3_I/PADDO (1007:1114:1221)(1007:1114:1221)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/C0 (1348:1559:1770) - (1348:1559:1770)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I/M0 (1253:1366:1480) - (1253:1366:1480)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/D0 (1316:1456:1597) - (1316:1456:1597)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q1 - hades_invalid_dl_2_I/PADDO (738:827:917)(738:827:917)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/B0 (397:470:544) - (397:470:544)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/C0 (497:613:730) - (497:613:730)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/A0 (964:1088:1213) - (964:1088:1213)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I/M0 (807:890:974) - (807:890:974)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/A0 (1134:1269:1405) - (1134:1269:1405)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I/CE (202:222:243) - (202:222:243)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_445I/CE (632:718:805) - (632:718:805)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_445I/CE (632:718:805) - (632:718:805)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_446I/CE (632:718:805) - (632:718:805)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_446I/CE (632:718:805) - (632:718:805)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_447I/CE (518:597:676) - (518:597:676)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_447I/CE (518:597:676) - (518:597:676)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_448I/CE (518:597:676) - (518:597:676)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_448I/CE (518:597:676) - (518:597:676)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_449I/CE (757:851:945) - (757:851:945)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_450I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_450I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_451I/CE (780:870:960) - (780:870:960)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_451I/CE (780:870:960) - (780:870:960)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_452I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_452I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_453I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_453I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_454I/CE (1057:1179:1302) - (1057:1179:1302)) - (INTERCONNECT SLICE_740I/F0 hades_tdc_bundle_inst_SLICE_455I/CE (1122:1258:1395) - (1122:1258:1395)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_455I/OFX0 - hades_tdc_bundle_inst_SLICE_455I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 - hades_tdc_bundle_inst_SLICE_456I/D0 (483:561:639)(483:561:639)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 - hades_tdc_bundle_inst_SLICE_458I/M0 (375:435:495)(375:435:495)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 - hades_tdc_bundle_inst_SLICE_710I/C0 (400:512:625)(400:512:625)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 SLICE_740I/C0 (378:499:621) - (378:499:621)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/Q0 hades_hit_valid_1_I/PADDO - (851:951:1052)(851:951:1052)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 - hades_tdc_bundle_inst_SLICE_456I/C0 (120:200:281)(120:200:281)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 - hades_tdc_bundle_inst_SLICE_458I/B1 (651:746:842)(651:746:842)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 - hades_tdc_bundle_inst_SLICE_458I/B0 (651:746:842)(651:746:842)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 - hades_tdc_bundle_inst_SLICE_710I/D1 (362:423:484)(362:423:484)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/Q0 hades_drop_cmp_buf_validI/PADDO - (1045:1188:1332)(1045:1188:1332)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_456I/F0 - hades_tdc_bundle_inst_SLICE_456I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 - hades_tdc_bundle_inst_SLICE_457I/D1 (200:237:274)(200:237:274)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 - hades_tdc_bundle_inst_SLICE_457I/C0 (123:206:290)(123:206:290)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 - hades_tdc_bundle_inst_SLICE_654I/C0 (389:509:629)(389:509:629)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/Q0 hades_hit_valid_0_I/PADDO - (984:1099:1214)(984:1099:1214)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_457I/B0 (977:1118:1259)(977:1118:1259)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_459I/D1 (929:1055:1181)(929:1055:1181)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_460I/D1 (799:913:1027)(799:913:1027)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_628I/C1 (537:668:800)(537:668:800)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_628I/C0 (537:668:800)(537:668:800)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_693I/D1 (512:588:665)(512:588:665)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/Q0 - hades_tdc_bundle_inst_SLICE_693I/D0 (512:588:665)(512:588:665)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_457I/A0 (667:780:893)(667:780:893)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_459I/B1 (794:906:1018)(794:906:1018)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_460I/A1 (537:638:740)(537:638:740)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_628I/D1 (211:251:292)(211:251:292)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_628I/A0 (380:458:536)(380:458:536)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_693I/B1 (394:464:535)(394:464:535)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q0 - hades_tdc_bundle_inst_SLICE_693I/B0 (394:464:535)(394:464:535)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_457I/OFX0 - hades_tdc_bundle_inst_SLICE_457I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_457I/M0 (623:702:782)(623:702:782)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_459I/M0 (623:702:782)(623:702:782)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_460I/M0 (493:561:629)(493:561:629)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_628I/A1 (262:322:382)(262:322:382)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_693I/C1 (226:316:406)(226:316:406)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/Q1 - hades_tdc_bundle_inst_SLICE_693I/C0 (226:316:406)(226:316:406)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_693I/F1 - hades_tdc_bundle_inst_SLICE_458I/A0 (767:878:989)(767:878:989)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_458I/OFX0 - hades_tdc_bundle_inst_SLICE_458I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 - hades_tdc_bundle_inst_SLICE_459I/A1 (368:443:518)(368:443:518)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 - hades_tdc_bundle_inst_SLICE_459I/D0 (98:126:154)(98:126:154)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 - hades_tdc_bundle_inst_SLICE_710I/B0 (547:641:736)(547:641:736)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/Q0 hades_hit_valid_2_I/PADDO - (984:1099:1214)(984:1099:1214)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_459I/OFX0 - hades_tdc_bundle_inst_SLICE_459I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 - hades_tdc_bundle_inst_SLICE_460I/C1 (225:317:410)(225:317:410)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 - hades_tdc_bundle_inst_SLICE_460I/D0 (98:126:154)(98:126:154)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 - hades_tdc_bundle_inst_SLICE_683I/A0 (645:754:863)(645:754:863)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/Q0 hades_hit_valid_3_I/PADDO - (755:847:940)(755:847:940)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_460I/OFX0 - hades_tdc_bundle_inst_SLICE_460I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/M1 (206:233:261) - (206:233:261)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/Q0 - hades_invalid_dl_1_I/PADDO (1011:1130:1249)(1011:1130:1249)) - (INTERCONNECT hades_lvl1_invalid_MGIOLI/INFF - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I/M0 (1212:1349:1486) - (1212:1349:1486)) - (INTERCONNECT hades_lvl1_invalid_MGIOLI/INFF hades_invalid_dl_0_I/PADDO - (490:550:610)(490:550:610)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/D0 (212:250:288) - (212:250:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/C1 (381:494:608) - (381:494:608)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/C0 (381:494:608) - (381:494:608)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/B1 (523:607:692) - (523:607:692)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/B0 (523:607:692) - (523:607:692)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/A1 (774:891:1008) - (774:891:1008)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/A0 (774:891:1008) - (774:891:1008)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/A0 (509:601:693) - (509:601:693)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/CE (484:544:605) - (484:544:605)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/D0 - (220:263:306)(220:263:306)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_8_MGIOLI/CE (1066:1186:1307)(1066:1186:1307)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_7_MGIOLI/CE (967:1102:1237)(967:1102:1237)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_6_MGIOLI/CE (1196:1328:1460)(1196:1328:1460)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_5_MGIOLI/CE (1052:1164:1276)(1052:1164:1276)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_4_MGIOLI/CE (1066:1186:1307)(1066:1186:1307)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_3_MGIOLI/CE (1066:1186:1307)(1066:1186:1307)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_2_MGIOLI/CE (1103:1252:1402)(1103:1252:1402)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_1_MGIOLI/CE (1103:1252:1402)(1103:1252:1402)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/OFX0 - hades_offset_0_MGIOLI/CE (1097:1243:1390)(1097:1243:1390)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/Q0 - hades_offset_validI/PADDO (2204:2432:2661)(2204:2432:2661)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I/Q0 - hades_raw_out_valid_MGIOLI/TXDATA0 (2050:2267:2485)(2050:2267:2485)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/M1 - (747:836:925)(747:836:925)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/M0 - (679:770:861)(679:770:861)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/Q0 - hades_offset_0_MGIOLI/TXDATA0 (822:916:1010)(822:916:1010)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I/Q1 - hades_offset_1_MGIOLI/TXDATA0 (868:964:1061)(868:964:1061)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/M0 - (768:847:927)(768:847:927)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I/Q0 - hades_offset_2_MGIOLI/TXDATA0 (864:980:1097)(864:980:1097)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/M1 (462:512:562) - (462:512:562)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/M0 (462:512:562) - (462:512:562)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CE - (1079:1190:1302)(1079:1190:1302)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/CE - (1079:1190:1302)(1079:1190:1302)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CE - (846:936:1027)(846:936:1027)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/CE - (846:936:1027)(846:936:1027)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CE - (825:916:1008)(825:916:1008)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/CE - (825:916:1008)(825:916:1008)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CE - (955:1058:1161)(955:1058:1161)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/CE - (955:1058:1161)(955:1058:1161)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CE (655:730:806) - (655:730:806)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/CE (655:730:806) - (655:730:806)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CE - (955:1058:1161)(955:1058:1161)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/CE - (955:1058:1161)(955:1058:1161)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CE - (825:916:1008)(825:916:1008)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/CE - (825:916:1008)(825:916:1008)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/CE - (825:916:1008)(825:916:1008)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/CE (346:391:437) - (346:391:437)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CE (655:730:806) - (655:730:806)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/CE (655:730:806) - (655:730:806)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/CE (785:872:960) - (785:872:960)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/DI0 (4:8:12) - (4:8:12)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/Q0 - hades_dbg2_out_0_MGIOLI/TXDATA0 (752:861:971)(752:861:971)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I/Q1 - hades_dbg2_out_1_MGIOLI/TXDATA0 (593:693:793)(593:693:793)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/M0 (609:679:750) - (609:679:750)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/Q0 - hades_dbg2_out_2_MGIOLI/TXDATA0 (407:470:534)(407:470:534)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I/Q1 - hades_dbg2_out_16_MGIOLI/TXDATA0 (407:470:534)(407:470:534)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/M1 (461:518:576) - (461:518:576)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/Q0 - hades_dbg2_out_17_MGIOLI/TXDATA0 (705:812:919)(705:812:919)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I/Q1 - hades_dbg2_out_18_MGIOLI/TXDATA0 (706:813:920)(706:813:920)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/Q0 - hades_dbg2_out_20_MGIOLI/TXDATA0 (966:1096:1226)(966:1096:1226)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I/Q1 - hades_dbg2_out_21_MGIOLI/TXDATA0 (868:1008:1148)(868:1008:1148)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/M0 (334:374:415) - (334:374:415)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/C0 (654:782:911) - (654:782:911)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/Q0 - hades_dbg2_out_22_MGIOLI/TXDATA0 (822:916:1010)(822:916:1010)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I/Q1 - hades_dbg2_out_23_MGIOLI/TXDATA0 (910:1029:1149)(910:1029:1149)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/M0 - (931:1023:1115)(931:1023:1115)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/Q1 - hades_tdc_bundle_inst_SLICE_698I/A0 (688:792:897)(688:792:897)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/Q0 - hades_dbg2_out_24_MGIOLI/TXDATA0 (996:1129:1262)(996:1129:1262)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I/Q1 - hades_dbg2_out_25_MGIOLI/TXDATA0 (1001:1144:1288)(1001:1144:1288)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/M1 (231:266:302) - (231:266:302)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/M0 (722:795:869) - (722:795:869)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/Q0 - hades_dbg2_out_26_MGIOLI/TXDATA0 (1011:1145:1279)(1011:1145:1279)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I/Q1 - hades_dbg2_out_27_MGIOLI/TXDATA0 (506:580:654)(506:580:654)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/M0 (360:408:456) - (360:408:456)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I/Q0 - hades_dbg2_out_28_MGIOLI/TXDATA0 (592:692:792)(592:692:792)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/M1 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/M0 - (488:545:602)(488:545:602)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/M1 - (488:545:602)(488:545:602)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/M1 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/M0 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/M0 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/M1 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/M1 - (378:426:475)(378:426:475)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/M0 - (361:401:441)(361:401:441)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/M0 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/M1 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/M1 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/M0 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/M0 - (515:570:625)(515:570:625)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/M1 - (515:570:625)(515:570:625)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/M0 - (635:712:789)(635:712:789)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/M1 - (635:712:789)(635:712:789)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/M0 - (511:579:647)(511:579:647)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/M1 - (409:467:526)(409:467:526)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/M0 - (488:550:612)(488:550:612)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/M1 - (488:550:612)(488:550:612)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/M1 - (337:378:419)(337:378:419)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/B0 - (397:464:531)(397:464:531)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/C0 - (243:338:434)(243:338:434)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/A0 - (499:583:668)(499:583:668)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/A1 - (505:593:681)(505:593:681)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/A0 - (505:593:681)(505:593:681)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/D0 - (337:388:439)(337:388:439)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/C0 - (351:450:550)(351:450:550)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/D1 - (337:388:439)(337:388:439)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/D0 - (337:388:439)(337:388:439)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/C1 - (250:352:454)(250:352:454)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/A0 - (521:622:723)(521:622:723)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/C0 - (250:352:454)(250:352:454)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/B1 - (408:488:568)(408:488:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/B0 - (408:488:568)(408:488:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/C1 - (250:352:454)(250:352:454)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/C0 - (250:352:454)(250:352:454)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/A1 - (385:461:538)(385:461:538)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/A1 - (385:461:538)(385:461:538)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/D1 - (205:241:277)(205:241:277)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/D0 - (205:241:277)(205:241:277)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/D0 - (205:241:277)(205:241:277)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/D1 - (217:258:299)(217:258:299)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/D1 - (217:258:299)(217:258:299)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/A1 - (394:481:569)(394:481:569)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/A0 - (394:481:569)(394:481:569)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/A0 - (394:481:569)(394:481:569)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/B1 - (414:492:571)(414:492:571)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/B0 - (414:492:571)(414:492:571)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/B1 - (414:492:571)(414:492:571)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/C1 - (368:479:590)(368:479:590)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/B1 - (414:492:571)(414:492:571)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/B0 - (414:492:571)(414:492:571)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/C0 - (515:641:768)(515:641:768)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/D0 - (355:411:468)(355:411:468)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/M0 - (501:569:637)(501:569:637)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/C0 - (380:491:603)(380:491:603)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/C0 - (216:299:382)(216:299:382)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/D0 - (214:257:301)(214:257:301)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/B0 - (276:327:379)(276:327:379)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/B0 - (391:455:520)(391:455:520)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/A0 - (258:314:370)(258:314:370)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I/LSR - (751:833:915)(751:833:915)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/LSR - (361:408:455)(361:408:455)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/LSR - (751:833:915)(751:833:915)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/LSR - (751:833:915)(751:833:915)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I/M0 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/C1 - (114:188:262)(114:188:262)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I/M0 - (1020:1122:1225)(1020:1122:1225)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/M0 - (1252:1375:1499)(1252:1375:1499)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/M1 - (493:559:626)(493:559:626)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/M1 - (243:279:315)(243:279:315)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/M1 - (350:399:448)(350:399:448)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/M1 - (344:390:436)(344:390:436)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/M1 - (623:701:779)(623:701:779)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/M1 - (350:399:448)(350:399:448)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/M1 - (623:701:779)(623:701:779)) - (INTERCONNECT SLICE_743I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/M1 - (493:559:626)(493:559:626)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/Q1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/M1 (203:227:251) - (203:227:251)) - (INTERCONNECT hades_lvl1_MGIOLI/INFF - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I/M0 (690:764:838) - (690:764:838)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/D1 (344:393:442) - (344:393:442)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I/A0 (494:576:658) - (494:576:658)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/D0 (327:375:423) - (327:375:423)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/D1 (483:556:630) - (483:556:630)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I/C0 (396:517:639) - (396:517:639)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/C0 - (554:685:816)(554:685:816)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/Q0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/C0 - (120:200:281)(120:200:281)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I/LSR (363:421:480) - (363:421:480)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/LSR (602:676:750) - (602:676:750)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/LSR (602:676:750) - (602:676:750)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/DI0 (6:11:17)(6:11:17)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/LSR (337:377:418) - (337:377:418)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/LSR (337:377:418) - (337:377:418)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/LSR (337:377:418) - (337:377:418)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/LSR (337:377:418) - (337:377:418)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I/LSR (331:365:400) - (331:365:400)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I/M0 (380:431:482) - (380:431:482)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I/A1 (382:461:541) - (382:461:541)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I/M0 (626:700:775) - (626:700:775)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/Q1 - hades_tdc_bundle_inst_SLICE_681I/D0 (217:260:304)(217:260:304)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I/M0 (389:435:482) - (389:435:482)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/D0 (220:269:319) - (220:269:319)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/C0 (242:341:441) - (242:341:441)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/A0 (368:443:518) - (368:443:518)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/C0 - (836:986:1137)(836:986:1137)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I/C0 (372:479:587) - (372:479:587)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/A0 (363:431:500) - (363:431:500)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/B0 (773:873:974) - (773:873:974)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CE (335:373:412) - (335:373:412)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I/CE (335:373:412) - (335:373:412)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CE (471:532:593) - (471:532:593)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/CE (471:532:593) - (471:532:593)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CE (651:724:797) - (651:724:797)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I/CE (651:724:797) - (651:724:797)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CE (651:724:797) - (651:724:797)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I/CE (651:724:797) - (651:724:797)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CE (488:549:610) - (488:549:610)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I/CE (488:549:610) - (488:549:610)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CE (363:419:476) - (363:419:476)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I/CE (363:419:476) - (363:419:476)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I/M0 (461:518:576) - (461:518:576)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/D0 (676:753:831) - (676:753:831)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/D0 - (93:114:136)(93:114:136)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/M1 (332:370:409) - (332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/M0 (332:370:409) - (332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CE (231:266:301) - (231:266:301)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I/CE (231:266:301) - (231:266:301)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CE (491:549:608) - (491:549:608)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/CE (491:549:608) - (491:549:608)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CE (814:898:982) - (814:898:982)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I/CE (814:898:982) - (814:898:982)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CE (814:898:982) - (814:898:982)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I/CE (814:898:982) - (814:898:982)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CE (541:608:676) - (541:608:676)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I/CE (541:608:676) - (541:608:676)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CE (378:433:488) - (378:433:488)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I/CE (378:433:488) - (378:433:488)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I/M0 (231:259:288) - (231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/D0 (647:731:816) - (647:731:816)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/D0 - (93:114:136)(93:114:136)) - (INTERCONNECT hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I/DI0 (0:0:0) - (0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/M1 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/M0 - (361:401:441)(361:401:441)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/M1 - (609:679:750)(609:679:750)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/M0 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/M0 - (361:401:441)(361:401:441)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/M1 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/M1 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/M0 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/M1 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/M0 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/M1 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/M1 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/M1 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/M1 - (208:235:263)(208:235:263)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/C0 - (222:308:394)(222:308:394)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/B0 - (520:601:682)(520:601:682)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/D0 - (214:251:289)(214:251:289)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/C1 - (362:468:575)(362:468:575)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/A0 - (505:594:683)(505:594:683)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/C0 - (359:464:570)(359:464:570)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/C0 - (359:464:570)(359:464:570)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/B1 - (405:478:551)(405:478:551)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/B0 - (405:478:551)(405:478:551)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/B1 - (549:642:735)(549:642:735)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/D0 - (231:279:328)(231:279:328)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/B0 - (549:642:735)(549:642:735)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/D1 - (231:279:328)(231:279:328)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/D0 - (231:279:328)(231:279:328)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/D1 - (231:279:328)(231:279:328)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/D0 - (231:279:328)(231:279:328)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/D1 - (469:533:598)(469:533:598)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/B1 - (409:485:561)(409:485:561)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/B1 - (409:485:561)(409:485:561)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/B0 - (409:485:561)(409:485:561)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/C0 - (381:494:607)(381:494:607)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/C1 - (242:344:446)(242:344:446)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/A1 - (397:487:578)(397:487:578)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/A1 - (397:487:578)(397:487:578)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/A0 - (397:487:578)(397:487:578)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/A0 - (366:437:509)(366:437:509)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/A1 - (517:615:713)(517:615:713)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/A0 - (674:795:917)(674:795:917)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/C1 - (648:798:948)(648:798:948)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/C1 - (648:798:948)(648:798:948)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/A1 - (674:795:917)(674:795:917)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/B0 - (405:481:558)(405:481:558)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/D0 - (334:384:435)(334:384:435)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/C0 - (247:345:444)(247:345:444)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/M0 - (244:281:318)(244:281:318)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/D0 - (334:384:435)(334:384:435)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/B0 - (374:431:489)(374:431:489)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/C0 - (236:331:427)(236:331:427)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/B0 - (394:464:534)(394:464:534)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/A0 - (261:320:380)(261:320:380)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/A0 - (261:320:380)(261:320:380)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/LSR - (336:373:411)(336:373:411)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/LSR - (336:373:411)(336:373:411)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/LSR - (336:373:411)(336:373:411)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/LSR - (336:373:411)(336:373:411)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/M0 - (536:594:653)(536:594:653)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/OFX0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I/M1 - (462:512:562)(462:512:562)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/D1 - (89:107:126)(89:107:126)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/OFX0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/OFX0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/M1 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/M0 - (461:518:576)(461:518:576)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/M1 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/M0 - (461:518:576)(461:518:576)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/M1 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/M1 - (479:537:596)(479:537:596)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/M0 - (592:653:715)(592:653:715)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/M1 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/M1 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/M0 - (360:408:456)(360:408:456)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/M1 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/M1 - (231:266:302)(231:266:302)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/M1 - (208:235:263)(208:235:263)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/C0 - (222:308:394)(222:308:394)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/C1 - (242:338:434)(242:338:434)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/C0 - (242:338:434)(242:338:434)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/D0 - (195:225:256)(195:225:256)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/B1 - (516:595:674)(516:595:674)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/B0 - (516:595:674)(516:595:674)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/A1 - (389:468:548)(389:468:548)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/B0 - (377:436:495)(377:436:495)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/D1 - (226:272:318)(226:272:318)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/D0 - (226:272:318)(226:272:318)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/D1 - (226:272:318)(226:272:318)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/D0 - (226:272:318)(226:272:318)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/A0 - (363:431:500)(363:431:500)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/D0 - (337:389:441)(337:389:441)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/B1 - (408:482:557)(408:482:557)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/B0 - (408:482:557)(408:482:557)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/D0 - (467:530:594)(467:530:594)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/C0 - (219:303:388)(219:303:388)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/C0 - (246:345:444)(246:345:444)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/C1 - (246:345:444)(246:345:444)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/C0 - (246:345:444)(246:345:444)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/A0 - (389:473:557)(389:473:557)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/C0 - (648:796:945)(648:796:945)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/A1 - (397:482:568)(397:482:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/A0 - (397:482:568)(397:482:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/A0 - (397:482:568)(397:482:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/B0 - (377:436:495)(377:436:495)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/A0 - (397:482:568)(397:482:568)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/D0 - (359:418:478)(359:418:478)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/A1 - (512:599:686)(512:599:686)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/C0 - (238:331:424)(238:331:424)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/D0 - (191:218:246)(191:218:246)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/D1 - (191:218:246)(191:218:246)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/B1 - (278:333:388)(278:333:388)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/B0 - (278:333:388)(278:333:388)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/B0 - (278:333:388)(278:333:388)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/D0 - (208:243:278)(208:243:278)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/C0 - (238:335:433)(238:335:433)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/A0 - (363:429:496)(363:429:496)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/A0 - (380:457:535)(380:457:535)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/F1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/DI1 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/LSR - (619:683:748)(619:683:748)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/LSR - (619:683:748)(619:683:748)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/LSR - (619:683:748)(619:683:748)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/LSR - (619:683:748)(619:683:748)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I/M1 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/OFX0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/DI0 - (0:0:0)(0:0:0)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/M0 - (332:370:409)(332:370:409)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I/M0 - (231:259:288)(231:259:288)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/M1 - (541:613:685)(541:613:685)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/M1 - (494:561:628)(494:561:628)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/M1 - (494:561:628)(494:561:628)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/M1 - (392:448:505)(392:448:505)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/M1 - (541:613:685)(541:613:685)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/M1 - (643:724:805)(643:724:805)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/M1 - (494:560:626)(494:560:626)) - (INTERCONNECT SLICE_747I/F0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/M1 - (541:613:685)(541:613:685)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/M1 - (568:641:715)(568:641:715)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/M1 - (568:641:715)(568:641:715)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/M1 - (703:791:880)(703:791:880)) - (INTERCONNECT hades_trigI/PADDI SLICE_747I/A0 (872:1002:1133)(872:1002:1133)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/Q1 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I/Q0 - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/F1 - hades_tdc_bundle_inst_SLICE_628I/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_628I/F0 - hades_tdc_bundle_inst_SLICE_628I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/B1 (523:609:695) - (523:609:695)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I/A0 (388:471:554) - (388:471:554)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I/C1 (244:345:446) - (244:345:446)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/OFX0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/Q0 - hades_tdc_bundle_inst_SLICE_741I/C0 (894:1044:1195)(894:1044:1195)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I/Q0 - hades_window_endI/PADDO (2102:2316:2531)(2102:2316:2531)) - (INTERCONNECT LVL1_TRG_DATA_VALID_IN_MGIOLI/INFF trb_adapter_inst_SLICE_631I/M0 - (3148:3448:3749)(3148:3448:3749)) - (INTERCONNECT trb_adapter_inst_SLICE_632I/Q0 trb_adapter_inst_SLICE_724I/M0 - (203:227:251)(203:227:251)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 trb_adapter_inst_SLICE_633I/M0 - (369:423:478)(369:423:478)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 trb_adapter_inst_SLICE_724I/A0 - (389:473:557)(389:473:557)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 finishedI/PADDO (797:901:1006) - (797:901:1006)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/Q0 FEE_DATAFINISHED_OUT_MGIOLI/TXDATA0 - (367:427:488)(367:427:488)) - (INTERCONNECT trb_adapter_inst_SLICE_633I/Q0 trb_adapter_inst_SLICE_724I/B0 - (374:431:489)(374:431:489)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I/M0 (207:234:262) - (207:234:262)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I/M0 (207:234:262) - (207:234:262)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I/C1 (237:331:425) - (237:331:425)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/F0 - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I/M0 (364:415:467) - (364:415:467)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I/M0 (334:374:415) - (334:374:415)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I/C1 (501:640:780) - (501:640:780)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/F0 - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I/B1 (403:478:553) - (403:478:553)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I/M0 (464:523:583) - (464:523:583)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I/A1 (388:471:554) - (388:471:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I/A1 (388:471:554) - (388:471:554)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I/M0 (207:234:262) - (207:234:262)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/F0 - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I/C1 (118:195:273) - (118:195:273)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 - fifo_colector_inst_fifo40_inst_SLICE_648I/M0 (235:267:299)(235:267:299)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 - fifo_colector_inst_fifo40_inst_SLICE_677I/C1 (118:195:273)(118:195:273)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_678I/F0 - fifo_colector_inst_fifo40_inst_SLICE_678I/C1 (118:195:273)(118:195:273)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_653I/OFX0 hades_buf_out_valid_MGIOLI/CE - (261:306:351)(261:306:351)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_710I/F0 - hades_tdc_bundle_inst_SLICE_654I/D1 (321:362:404)(321:362:404)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_654I/F1 - hades_tdc_bundle_inst_SLICE_654I/D0 (191:218:246)(191:218:246)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_654I/F0 - hades_tdc_bundle_inst_SLICE_683I/D0 (89:107:126)(89:107:126)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 - fifo_colector_inst_fifo40_inst_SLICE_673I/B1 (379:440:501)(379:440:501)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 - fifo_colector_inst_fifo40_inst_SLICE_674I/C1 (118:195:273)(118:195:273)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_SLICE_674I/F0 - fifo_colector_inst_fifo40_inst_SLICE_702I/C0 (118:195:273)(118:195:273)) - (INTERCONNECT fifo_colector_inst_SLICE_680I/F1 fifo_colector_inst_SLICE_680I/A0 - (258:314:370)(258:314:370)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_683I/F1 - hades_tdc_bundle_inst_SLICE_683I/B0 (272:320:369)(272:320:369)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_683I/F0 - hades_buf_out_valid_MGIOLI/TXDATA0 (592:692:792)(592:692:792)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I/F1 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/B0 - (391:455:520)(391:455:520)) - (INTERCONNECT hades_tdc_bundle_inst_SLICE_710I/F1 hades_buf_drop_1_MGIOLI/TXDATA0 - (752:861:971)(752:861:971)) - (INTERCONNECT genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/Q0 - genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I/D0 (191:218:246)(191:218:246)) - (INTERCONNECT genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/Q0 - genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I/D0 (191:218:246)(191:218:246)) - (INTERCONNECT genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/Q0 - genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I/D0 (89:107:126)(89:107:126)) - (INTERCONNECT trb_adapter_inst_SLICE_723I/F0 LVL1_TRG_DATA_VALI_IN_risingI/PADDO - (512:577:643)(512:577:643)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/F0 release_outI/PADDO (534:611:688) - (534:611:688)) - (INTERCONNECT trb_adapter_inst_SLICE_724I/F0 FEE_TRG_RELEASE_OUT_MGIOLI/TXDATA0 - (641:730:819)(641:730:819)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_8_MGIOLI/LSR (1055:1166:1277)(1055:1166:1277)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_7_MGIOLI/LSR (1078:1215:1353)(1078:1215:1353)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_6_MGIOLI/LSR (1164:1278:1393)(1164:1278:1393)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_5_MGIOLI/LSR (1204:1319:1435)(1204:1319:1435)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_4_MGIOLI/LSR (1164:1280:1396)(1164:1280:1396)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_3_MGIOLI/LSR (1164:1280:1396)(1164:1280:1396)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_2_MGIOLI/LSR (975:1111:1247)(975:1111:1247)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_1_MGIOLI/LSR (969:1102:1236)(969:1102:1236)) - (INTERCONNECT - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I/F0 - hades_offset_0_MGIOLI/LSR (975:1111:1247)(975:1111:1247)) - (INTERCONNECT hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I/F0 - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I/D0 - (211:251:291)(211:251:291)) - (INTERCONNECT reset_dc_MGIOLI/INFF SLICE_740I/M0 (890:996:1103)(890:996:1103)) - (INTERCONNECT pll0inst_SLICE_742I/F0 pll0inst_PLLInst_0I/STDBY (369:416:463) - (369:416:463)) - (INTERCONNECT hades_lvl1I/PADDI SLICE_743I/D0 (723:821:919)(723:821:919)) - (INTERCONNECT hades_lvl1I/PADDI hades_lvl1_MGIOLI/DI (21:21:22)(21:21:22)) - (INTERCONNECT trig_0_I/PADDI SLICE_744I/D0 (330:373:416)(330:373:416)) - (INTERCONNECT trig_1_I/PADDI SLICE_745I/D0 (1230:1366:1503)(1230:1366:1503)) - (INTERCONNECT trig_2_I/PADDI SLICE_746I/D0 (1480:1613:1747)(1480:1613:1747)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA0 - fifo_data_out_0_I/PADDO (2121:2332:2543)(2121:2332:2543)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA0 - FEE_DATA_OUT_0_I/PADDO (2312:2542:2772)(2312:2542:2772)) - (INTERCONNECT clkI/PADDI pll0inst_PLLInst_0I/CLKI (56:56:56)(56:56:56)) - (INTERCONNECT hades_dbg2_out_28_MGIOLI/IOLDO hades_dbg2_out_28_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_27_MGIOLI/IOLDO hades_dbg2_out_27_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_26_MGIOLI/IOLDO hades_dbg2_out_26_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_25_MGIOLI/IOLDO hades_dbg2_out_25_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_24_MGIOLI/IOLDO hades_dbg2_out_24_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_23_MGIOLI/IOLDO hades_dbg2_out_23_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_22_MGIOLI/IOLDO hades_dbg2_out_22_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_21_MGIOLI/IOLDO hades_dbg2_out_21_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_20_MGIOLI/IOLDO hades_dbg2_out_20_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_18_MGIOLI/IOLDO hades_dbg2_out_18_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_17_MGIOLI/IOLDO hades_dbg2_out_17_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_16_MGIOLI/IOLDO hades_dbg2_out_16_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_2_MGIOLI/IOLDO hades_dbg2_out_2_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_1_MGIOLI/IOLDO hades_dbg2_out_1_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_dbg2_out_0_MGIOLI/IOLDO hades_dbg2_out_0_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_buf_drop_1_MGIOLI/IOLDO hades_buf_drop_1_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_buf_out_valid_MGIOLI/IOLDO hades_buf_out_validI/IOLDO - (23:23:23)(23:23:23)) - (INTERCONNECT hades_offset_8_MGIOLI/IOLDO hades_offset_8_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_7_MGIOLI/IOLDO hades_offset_7_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_6_MGIOLI/IOLDO hades_offset_6_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_5_MGIOLI/IOLDO hades_offset_5_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_4_MGIOLI/IOLDO hades_offset_4_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_3_MGIOLI/IOLDO hades_offset_3_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_2_MGIOLI/IOLDO hades_offset_2_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_1_MGIOLI/IOLDO hades_offset_1_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_offset_0_MGIOLI/IOLDO hades_offset_0_I/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT hades_lvl1_invalidI/PADDI hades_lvl1_invalid_MGIOLI/DI (69:71:74) - (69:71:74)) - (INTERCONNECT hades_raw_out_valid_MGIOLI/IOLDO hades_raw_out_validI/IOLDO - (23:23:23)(23:23:23)) - (INTERCONNECT FEE_TRG_RELEASE_OUT_MGIOLI/IOLDO FEE_TRG_RELEASE_OUTI/IOLDO - (23:23:23)(23:23:23)) - (INTERCONNECT FEE_DATAFINISHED_OUT_MGIOLI/IOLDO FEE_DATAFINISHED_OUTI/IOLDO - (23:23:23)(23:23:23)) - (INTERCONNECT FEE_DATA_WRITE_OUT_MGIOLI/IOLDO FEE_DATA_WRITE_OUTI/IOLDO (23:23:23) - (23:23:23)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB13 - FEE_DATA_OUT_31_I/PADDO (2203:2425:2648)(2203:2425:2648)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB13 - fifo_data_out_31_I/PADDO (2334:2567:2801)(2334:2567:2801)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB12 - FEE_DATA_OUT_30_I/PADDO (2209:2426:2643)(2209:2426:2643)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB12 - fifo_data_out_30_I/PADDO (2209:2426:2643)(2209:2426:2643)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB11 - FEE_DATA_OUT_29_I/PADDO (2229:2456:2684)(2229:2456:2684)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB11 - fifo_data_out_29_I/PADDO (2229:2456:2684)(2229:2456:2684)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB10 - FEE_DATA_OUT_28_I/PADDO (2301:2531:2761)(2301:2531:2761)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB10 - fifo_data_out_28_I/PADDO (2431:2672:2914)(2431:2672:2914)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB9 - FEE_DATA_OUT_27_I/PADDO (2373:2594:2816)(2373:2594:2816)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB9 - fifo_data_out_27_I/PADDO (2373:2594:2816)(2373:2594:2816)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB8 - FEE_DATA_OUT_26_I/PADDO (2209:2433:2658)(2209:2433:2658)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB8 - fifo_data_out_26_I/PADDO (2340:2575:2811)(2340:2575:2811)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB7 - FEE_DATA_OUT_25_I/PADDO (2363:2594:2826)(2363:2594:2826)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB7 - fifo_data_out_25_I/PADDO (2363:2594:2826)(2363:2594:2826)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB6 - FEE_DATA_OUT_24_I/PADDO (2025:2217:2409)(2025:2217:2409)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB6 - fifo_data_out_24_I/PADDO (2225:2449:2674)(2225:2449:2674)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB5 - FEE_DATA_OUT_23_I/PADDO (2053:2243:2433)(2053:2243:2433)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB5 - fifo_data_out_23_I/PADDO (2053:2243:2433)(2053:2243:2433)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB4 - FEE_DATA_OUT_22_I/PADDO (2200:2430:2661)(2200:2430:2661)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB4 - fifo_data_out_22_I/PADDO (2358:2598:2839)(2358:2598:2839)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB3 - FEE_DATA_OUT_21_I/PADDO (2034:2219:2405)(2034:2219:2405)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB3 - fifo_data_out_21_I/PADDO (1922:2100:2279)(1922:2100:2279)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB2 - FEE_DATA_OUT_20_I/PADDO (2319:2571:2824)(2319:2571:2824)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB2 - fifo_data_out_20_I/PADDO (2477:2739:3002)(2477:2739:3002)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB1 - FEE_DATA_OUT_19_I/PADDO (1846:2041:2237)(1846:2041:2237)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB1 - fifo_data_out_19_I/PADDO (1846:2041:2237)(1846:2041:2237)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB0 - FEE_DATA_OUT_18_I/PADDO (2286:2518:2751)(2286:2518:2751)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOB0 - fifo_data_out_18_I/PADDO (2693:2969:3246)(2693:2969:3246)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA17 - FEE_DATA_OUT_17_I/PADDO (2275:2518:2761)(2275:2518:2761)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA17 - fifo_data_out_17_I/PADDO (2405:2659:2914)(2405:2659:2914)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA16 - FEE_DATA_OUT_16_I/PADDO (2647:2909:3171)(2647:2909:3171)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA16 - fifo_data_out_16_I/PADDO (2777:3050:3324)(2777:3050:3324)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA15 - FEE_DATA_OUT_15_I/PADDO (2094:2307:2521)(2094:2307:2521)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA15 - fifo_data_out_15_I/PADDO (1736:1907:2078)(1736:1907:2078)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA14 - FEE_DATA_OUT_14_I/PADDO (2174:2402:2630)(2174:2402:2630)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA14 - fifo_data_out_14_I/PADDO (2304:2543:2783)(2304:2543:2783)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA13 - FEE_DATA_OUT_13_I/PADDO (2403:2621:2840)(2403:2621:2840)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA13 - fifo_data_out_13_I/PADDO (2357:2573:2789)(2357:2573:2789)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA12 - FEE_DATA_OUT_12_I/PADDO (2018:2224:2430)(2018:2224:2430)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA12 - fifo_data_out_12_I/PADDO (2148:2365:2583)(2148:2365:2583)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA11 - FEE_DATA_OUT_11_I/PADDO (2042:2262:2483)(2042:2262:2483)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA11 - fifo_data_out_11_I/PADDO (2042:2262:2483)(2042:2262:2483)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA10 - FEE_DATA_OUT_10_I/PADDO (1765:1932:2100)(1765:1932:2100)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA10 - fifo_data_out_10_I/PADDO (1765:1932:2100)(1765:1932:2100)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA9 - FEE_DATA_OUT_9_I/PADDO (2042:2243:2444)(2042:2243:2444)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA9 - fifo_data_out_9_I/PADDO (2172:2384:2597)(2172:2384:2597)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA8 - FEE_DATA_OUT_8_I/PADDO (2083:2306:2530)(2083:2306:2530)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA8 - fifo_data_out_8_I/PADDO (2083:2306:2530)(2083:2306:2530)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA7 - FEE_DATA_OUT_7_I/PADDO (2418:2669:2920)(2418:2669:2920)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA7 - fifo_data_out_7_I/PADDO (2576:2837:3098)(2576:2837:3098)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA6 - FEE_DATA_OUT_6_I/PADDO (2433:2685:2938)(2433:2685:2938)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA6 - fifo_data_out_6_I/PADDO (2563:2827:3092)(2563:2827:3092)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA5 - FEE_DATA_OUT_5_I/PADDO (2561:2790:3019)(2561:2790:3019)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA5 - fifo_data_out_5_I/PADDO (2691:2931:3172)(2691:2931:3172)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA4 - FEE_DATA_OUT_4_I/PADDO (2391:2621:2851)(2391:2621:2851)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA4 - fifo_data_out_4_I/PADDO (2391:2621:2851)(2391:2621:2851)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA3 - FEE_DATA_OUT_3_I/PADDO (2077:2284:2492)(2077:2284:2492)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA3 - fifo_data_out_3_I/PADDO (2077:2284:2492)(2077:2284:2492)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA2 - FEE_DATA_OUT_2_I/PADDO (2390:2620:2850)(2390:2620:2850)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA2 - fifo_data_out_2_I/PADDO (2390:2620:2850)(2390:2620:2850)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA1 - FEE_DATA_OUT_1_I/PADDO (2345:2621:2898)(2345:2621:2898)) - (INTERCONNECT fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I/DOA1 - fifo_data_out_1_I/PADDO (2345:2621:2898)(2345:2621:2898)) - (INTERCONNECT LVL1_INVALID_TRG_INI/PADDI LVL1_INVALID_TRG_IN_MGIOLI/DI (21:21:22) - (21:21:22)) - (INTERCONNECT LVL1_TRG_DATA_VALID_INI/PADDI LVL1_TRG_DATA_VALID_IN_MGIOLI/DI - (21:21:22)(21:21:22)) - (INTERCONNECT reset_dcI/PADDI reset_dc_MGIOLI/DI (21:21:22)(21:21:22)) - ) - ) - ) -) diff --git a/impl1/s1_impl1_vho.vho b/impl1/s1_impl1_vho.vho deleted file mode 100644 index 9c28730..0000000 --- a/impl1/s1_impl1_vho.vho +++ /dev/null @@ -1,174140 +0,0 @@ - --- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.11.2.446 - --- ldbanno -n VHDL -o s1_impl1_vho.vho -noslice -w -neg -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd --- Netlist created on Wed Jun 16 09:19:26 2021 --- Netlist written on Wed Jun 16 09:20:42 2021 --- Design is for device LFE5UM5G-45F --- Design is for package CABGA381 --- Design is for performance grade 8 - --- entity ccu2B0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu2B0 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; - - end ccu2B0; - - architecture Structure of ccu2B0 is - begin - inst1: CCU2C - generic map (INIT0 => X"0000", INIT1 => X"66AA", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity gnd - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity gnd is - port (PWR0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; - - end gnd; - - architecture Structure of gnd is - begin - INST1: VLO - port map (Z=>PWR0); - end Structure; - --- entity vcc - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity vcc is - port (PWR1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; - - end vcc; - - architecture Structure of vcc is - begin - INST1: VHI - port map (Z=>PWR1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity svmuxregsre - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity svmuxregsre is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF svmuxregsre : ENTITY IS TRUE; - - end svmuxregsre; - - architecture Structure of svmuxregsre is - begin - INST01: FL1P3DX - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); - end Structure; - --- entity svmuxregsre0001 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity svmuxregsre0001 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF svmuxregsre0001 : ENTITY IS TRUE; - - end svmuxregsre0001; - - architecture Structure of svmuxregsre0001 is - begin - INST01: FL1P3BX - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); - end Structure; - --- entity ccu20002 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20002 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; - - end ccu20002; - - architecture Structure of ccu20002 is - begin - inst1: CCU2C - generic map (INIT0 => X"CCCC", INIT1 => X"CCCC", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20003 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20003 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20003 : ENTITY IS TRUE; - - end ccu20003; - - architecture Structure of ccu20003 is - begin - inst1: CCU2C - generic map (INIT0 => X"AAAA", INIT1 => X"AAAA", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20003 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20003 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20004 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20004 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20004 : ENTITY IS TRUE; - - end ccu20004; - - architecture Structure of ccu20004 is - begin - inst1: CCU2C - generic map (INIT0 => X"CCCC", INIT1 => X"AAAA", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity ccu20005 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20005 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20005 : ENTITY IS TRUE; - - end ccu20005; - - architecture Structure of ccu20005 is - begin - inst1: CCU2C - generic map (INIT0 => X"AAAA", INIT1 => X"CCCC", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20005 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20005 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20006 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20006 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20006 : ENTITY IS TRUE; - - end ccu20006; - - architecture Structure of ccu20006 is - begin - inst1: CCU2C - generic map (INIT0 => X"99AA", INIT1 => X"99CC", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20007 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20007 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20007 : ENTITY IS TRUE; - - end ccu20007; - - architecture Structure of ccu20007 is - begin - inst1: CCU2C - generic map (INIT0 => X"99CC", INIT1 => X"99AA", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20008 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20008 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20008 : ENTITY IS TRUE; - - end ccu20008; - - architecture Structure of ccu20008 is - begin - inst1: CCU2C - generic map (INIT0 => X"99AA", INIT1 => X"99AA", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20009 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20009 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20009 : ENTITY IS TRUE; - - end ccu20009; - - architecture Structure of ccu20009 is - begin - inst1: CCU2C - generic map (INIT0 => X"0000", INIT1 => X"0000", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20003 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20003 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20005 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20005 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20010 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20010 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20010 : ENTITY IS TRUE; - - end ccu20010; - - architecture Structure of ccu20010 is - begin - inst1: CCU2C - generic map (INIT0 => X"99CC", INIT1 => X"99CC", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20010 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20010 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_100: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_101: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_98: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_99: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_1: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_96: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_97: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_94: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_95: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20005 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_92: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_93: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_4: ccu20005 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58" - ); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_70: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_71: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20003 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_68: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_69: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_1: ccu20003 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61" - ; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_66: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_67: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_64: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_65: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_62: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_63: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_0: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_1: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_2: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_3: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_4: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_1: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_a0: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_0: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_1: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_2: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_3: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20010 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_4: ccu20010 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77" - ; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_a1: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_78 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_78 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_78"); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_78 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_78; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_78 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_w_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_79 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_79 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_79"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_79 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_79; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_79 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_100: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_101: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_w_gctr_0: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_80 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_80 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_80"; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_80 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_80; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_80 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20003 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_98: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_99: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_w_gctr_1: ccu20003 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_81 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_81 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_81"; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_81 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_81; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_81 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_96: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_97: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_w_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_82 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_82 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_82"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_82 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_82; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_82 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_94: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_95: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_w_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_83 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_83 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_83"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_83 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_83; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_83 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_92: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_93: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_w_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_84 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_84 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_84"); - - port (FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_84 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_84; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_84 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_r_gctr_cia: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (FCO_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO <= FCO_out; - - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_85 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_85 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_85"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_85 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_85; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_85 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20005 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_70: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_71: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_r_gctr_0: ccu20005 - port map (A0=>A0_ipd, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_86 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_86 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_86"; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_86 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_86; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_86 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_68: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_69: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_r_gctr_1: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_87 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_87 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_87"; - - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_87 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_87; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_87 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20004 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_66: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_67: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_r_gctr_2: ccu20004 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (A1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_88 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_88 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_88"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_88 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_88; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_88 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_64: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_65: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_r_gctr_3: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_89 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_89 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_89"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_89 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_89; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_89 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20002 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_62: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_63: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - fifo_colector_inst_fifo40_inst_r_gctr_4: ccu20002 - port map (A0=>GNDI, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, B0_ipd, DI1_dly, DI0_dly, CE_dly, CLK_dly, - FCI_ipd, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_90 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_90 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_90"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_90 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_90; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_90 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_91 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_91 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_91"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_91 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_91; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_91 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20010 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_0: ccu20010 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_92 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_92 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_92"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_92 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_92; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_92 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_1: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_93 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_93 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_93"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_93 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_93; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_93 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20008 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_2: ccu20008 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_94 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_94 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_94"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_94 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_94; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_94 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20010 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_3: ccu20010 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_95 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_95 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_95"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_95 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_95; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_95 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20010 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_empty_cmp_4: ccu20010 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_96 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_96 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_96"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_96 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_96; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_96 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0001 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_1: svmuxregsre0001 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_a0: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_97 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_97 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_97"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_97 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_97; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_97 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component ccu2B0 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_ci_a: ccu2B0 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>VCCI, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, CO1=>FCO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_98 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_98 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_98"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_98 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_98; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_98 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_0: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_99 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_99 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_99"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_99 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_99; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_99 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20006 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_1: ccu20006 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_100 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_100 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_100"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_100 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_100; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_100 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_2: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_101 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_101 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_101"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_101 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_101; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_101 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_3: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_102 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_102 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_102"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_102 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_102; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_102 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20007 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_full_cmp_4: ccu20007 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_103 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_103 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_103"; - - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_103 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_103; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_103 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component ccu20009 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_a1: ccu20009 - port map (A0=>GNDI, B0=>GNDI, C0=>VCCI, D0=>VCCI, A1=>GNDI, B1=>GNDI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20011 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20011 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20011 : ENTITY IS TRUE; - - end ccu20011; - - architecture Structure of ccu20011 is - begin - inst1: CCU2C - generic map (INIT0 => X"5003", INIT1 => X"0000", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_104 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_104 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_104"; - - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (FCI: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_104 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_104; - - architecture Structure of hades_tdc_bundle_inst_SLICE_104 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20011 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid25_0_I_27_0: ccu20011 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (FCI_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20012 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20012 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20012 : ENTITY IS TRUE; - - end ccu20012; - - architecture Structure of ccu20012 is - begin - inst1: CCU2C - generic map (INIT0 => X"500C", INIT1 => X"1842", INJECT1_0 => "NO", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20012 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_1_0: ccu20012 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, - CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20013 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20013 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20013 : ENTITY IS TRUE; - - end ccu20013; - - architecture Structure of ccu20013 is - begin - inst1: CCU2C - generic map (INIT0 => X"0069", INIT1 => X"0609", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - component ccu20013 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_0: ccu20013 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 8 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20014 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20014 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20014 : ENTITY IS TRUE; - - end ccu20014; - - architecture Structure of ccu20014 is - begin - inst1: CCU2C - generic map (INIT0 => X"8007", INIT1 => X"070F", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - component ccu20014 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_21_0: ccu20014 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 8 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20015 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20015 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20015 : ENTITY IS TRUE; - - end ccu20015; - - architecture Structure of ccu20015 is - begin - inst1: CCU2C - generic map (INIT0 => X"a003", INIT1 => X"0000", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108" - ; - - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (FCI: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20015 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_0: ccu20015 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (FCI_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20012 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_1_0: ccu20012 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, - CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20016 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20016 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20016 : ENTITY IS TRUE; - - end ccu20016; - - architecture Structure of ccu20016 is - begin - inst1: CCU2C - generic map (INIT0 => X"0069", INIT1 => X"0069", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - component ccu20016 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0: ccu20016 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 8 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20017 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20017 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20017 : ENTITY IS TRUE; - - end ccu20017; - - architecture Structure of ccu20017 is - begin - inst1: CCU2C - generic map (INIT0 => X"8007", INIT1 => X"007F", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - component ccu20017 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_21_0: ccu20017 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 8 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112" - ; - - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (FCI: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20015 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_0: ccu20015 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (FCI_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20018 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20018 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20018 : ENTITY IS TRUE; - - end ccu20018; - - architecture Structure of ccu20018 is - begin - inst1: CCU2C - generic map (INIT0 => X"5003", INIT1 => X"C90C", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20018 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0_0: ccu20018 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>C1_ipd, D1=>VCCI, CI=>GNDI, S0=>open, S1=>open, - CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20019 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20019 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20019 : ENTITY IS TRUE; - - end ccu20019; - - architecture Structure of ccu20019 is - begin - inst1: CCU2C - generic map (INIT0 => X"a90a", INIT1 => X"a90a", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20019 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0: ccu20019 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, - S1=>F1_out, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - FCI_ipd, F0_out, F1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F1, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20019 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0: ccu20019 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, - S1=>F1_out, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - FCI_ipd, F0_out, F1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F1, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20020 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20020 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20020 : ENTITY IS TRUE; - - end ccu20020; - - architecture Structure of ccu20020 is - begin - inst1: CCU2C - generic map (INIT0 => X"C90C", INIT1 => X"C90C", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20020 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0: ccu20020 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>VCCI, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, - S1=>F1_out, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - FCI_ipd, F0_out, F1_out, FCO_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F1, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F1, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F1, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20021 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20021 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20021 : ENTITY IS TRUE; - - end ccu20021; - - architecture Structure of ccu20021 is - begin - inst1: CCU2C - generic map (INIT0 => X"900a", INIT1 => X"5003", INJECT1_0 => "NO", - INJECT1_1 => "NO") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117" - ; - - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20021 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0: ccu20021 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>VCCI, D0=>VCCI, A1=>VCCI, B1=>VCCI, - C1=>VCCI, D1=>VCCI, CI=>FCI_ipd, S0=>F0_out, S1=>open, - CO1=>open); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (B0_ipd, A0_ipd, FCI_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20022 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20022 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20022 : ENTITY IS TRUE; - - end ccu20022; - - architecture Structure of ccu20022 is - begin - inst1: CCU2C - generic map (INIT0 => X"500C", INIT1 => X"9009", INJECT1_0 => "NO", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_118 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_118 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_118"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_118 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_118; - - architecture Structure of hades_tdc_bundle_inst_SLICE_118 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20022 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid25_0_I_1_0: ccu20022 - port map (A0=>VCCI, B0=>VCCI, C0=>VCCI, D0=>VCCI, A1=>A1_ipd, B1=>B1_ipd, - C1=>C1_ipd, D1=>D1_ipd, CI=>GNDI, S0=>open, S1=>open, - CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20023 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20023 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20023 : ENTITY IS TRUE; - - end ccu20023; - - architecture Structure of ccu20023 is - begin - inst1: CCU2C - generic map (INIT0 => X"8241", INIT1 => X"9009", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_119 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_119 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_119"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_119 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_119; - - architecture Structure of hades_tdc_bundle_inst_SLICE_119 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - component ccu20023 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid25_0_I_9_0: ccu20023 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>A1_ipd, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 8 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity ccu20024 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity ccu20024 is - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF ccu20024 : ENTITY IS TRUE; - - end ccu20024; - - architecture Structure of ccu20024 is - begin - inst1: CCU2C - generic map (INIT0 => X"8241", INIT1 => X"0852", INJECT1_0 => "YES", - INJECT1_1 => "YES") - port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, - C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_120 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_120 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_120"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); - tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_120 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_120; - - architecture Structure of hades_tdc_bundle_inst_SLICE_120 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal FCI_ipd : std_logic := 'X'; - signal FCO_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component ccu20024 - port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; - D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; - C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; - S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid25_0_I_21_0: ccu20024 - port map (A0=>A0_ipd, B0=>B0_ipd, C0=>C0_ipd, D0=>D0_ipd, A1=>VCCI, - B1=>B1_ipd, C1=>C1_ipd, D1=>D1_ipd, CI=>FCI_ipd, S0=>open, - S1=>open, CO1=>FCO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(FCI_ipd, FCI, tipd_FCI); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, FCI_ipd, FCO_out) - VARIABLE FCO_zd : std_logic := 'X'; - VARIABLE FCO_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FCO_zd := FCO_out; - - VitalPathDelay01 ( - OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_FCO, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_FCO, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_FCO, - PathCondition => TRUE), - 3 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_FCO, - PathCondition => TRUE), - 4 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_FCO, - PathCondition => TRUE), - 5 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_FCO, - PathCondition => TRUE), - 6 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_FCO, - PathCondition => TRUE), - 7 => (InputChangeTime => FCI_ipd'last_event, - PathDelay => tpd_FCI_FCO, - PathCondition => TRUE)), - GlitchData => FCO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut4 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut4 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; - - end lut4; - - architecture Structure of lut4 is - begin - INST10: ROM16X1A - generic map (initval => X"3332") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40025 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40025 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; - - end lut40025; - - architecture Structure of lut40025 is - begin - INST10: ROM16X1A - generic map (initval => X"00FF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity svmuxregsre0026 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity svmuxregsre0026 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF svmuxregsre0026 : ENTITY IS TRUE; - - end svmuxregsre0026; - - architecture Structure of svmuxregsre0026 is - begin - INST01: FL1P3IY - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); - end Structure; - --- entity selmux2 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity selmux2 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; - - end selmux2; - - architecture Structure of selmux2 is - begin - INST1: MUX21 - port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_121 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_121 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_121"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_121 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_121; - - architecture Structure of hades_tdc_bundle_inst_SLICE_121 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component lut4 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40025 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_121_K1: lut4 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1 - ); - hades_tdc_bundle_inst_hit_out_i_RNO_0: lut40025 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_out_i_0: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_SLICE_121_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_hit_out_i_RNO_0_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_121_hades_tdc_bundle_inst_SLICE_121_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, DI0_dly, - M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40027 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40027 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; - - end lut40027; - - architecture Structure of lut40027 is - begin - INST10: ROM16X1A - generic map (initval => X"6AAA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40028 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40028 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; - - end lut40028; - - architecture Structure of lut40028 is - begin - INST10: ROM16X1A - generic map (initval => X"3C3C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_122 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_122 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_122"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_122 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_122; - - architecture Structure of hades_tdc_bundle_inst_SLICE_122 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40027 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_50_i_i: lut40027 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_1_x2: lut40028 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_out_i_3: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hit_out_i_1: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40029 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40029 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; - - end lut40029; - - architecture Structure of lut40029 is - begin - INST10: ROM16X1A - generic map (initval => X"6666") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40030 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40030 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; - - end lut40030; - - architecture Structure of lut40030 is - begin - INST10: ROM16X1A - generic map (initval => X"CDCC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_123 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_123 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_123"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_123 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_123; - - architecture Structure of hades_tdc_bundle_inst_SLICE_123 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40029 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40030 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_123_K1: lut40029 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_out_i_6_f1_0_2: lut40030 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0 - ); - hades_tdc_bundle_inst_hit_out_i_2: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_SLICE_123_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_hit_out_i_6_f1_0_2_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_123_hades_tdc_bundle_inst_SLICE_123_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trb_adapter_inst_SLICE_124 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_124 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_124"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_124 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_124; - - architecture Structure of trb_adapter_inst_SLICE_124 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40031 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40031 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; - - end lut40031; - - architecture Structure of lut40031 is - begin - INST10: ROM16X1A - generic map (initval => X"3333") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40032 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40032 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; - - end lut40032; - - architecture Structure of lut40032 is - begin - INST10: ROM16X1A - generic map (initval => X"05F5") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_125 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_125 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_125"; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_125 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_125; - - architecture Structure of fifo_colector_inst_SLICE_125 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40031 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40032 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_125_K1: lut40031 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>GNDI, - Z=>fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_in_empty_pmux_0_RNIDRET: lut40032 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0 - ); - fifo_colector_inst_buffer_wr_enable: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_SLICE_125_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_125_fifo_colector_inst_in_empty_pmux_0_RNIDRET_H0 - , - D1=>fifo_colector_inst_SLICE_125_fifo_colector_inst_SLICE_125_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, D0_ipd, C0_ipd, A0_ipd, DI0_dly, M0_ipd, - CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40033 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40033 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; - - end lut40033; - - architecture Structure of lut40033 is - begin - INST10: ROM16X1A - generic map (initval => X"FAEE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40034 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40034 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; - - end lut40034; - - architecture Structure of lut40034 is - begin - INST10: ROM16X1A - generic map (initval => X"5044") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_126 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_126 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_126"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_126 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_126; - - architecture Structure of fifo_colector_inst_SLICE_126 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40033 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_126_K1: lut40033 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1 - ); - fifo_colector_inst_data_buffer_3_0: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0 - ); - fifo_colector_inst_data_buffer_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_126_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_126_fifo_colector_inst_data_buffer_3_0_H0 - , - D1=>fifo_colector_inst_SLICE_126_fifo_colector_inst_SLICE_126_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_127 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_127 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_127"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_127 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_127; - - architecture Structure of fifo_colector_inst_SLICE_127 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40033 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_127_K1: lut40033 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1 - ); - fifo_colector_inst_data_buffer_3_1: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0 - ); - fifo_colector_inst_data_buffer_1: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_127_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_127_fifo_colector_inst_data_buffer_3_1_H0 - , - D1=>fifo_colector_inst_SLICE_127_fifo_colector_inst_SLICE_127_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40035 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40035 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; - - end lut40035; - - architecture Structure of lut40035 is - begin - INST10: ROM16X1A - generic map (initval => X"EEFA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40036 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40036 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; - - end lut40036; - - architecture Structure of lut40036 is - begin - INST10: ROM16X1A - generic map (initval => X"4450") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_128 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_128 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_128"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_128 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_128; - - architecture Structure of fifo_colector_inst_SLICE_128 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40035 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40036 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_128_K1: lut40035 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1 - ); - fifo_colector_inst_data_buffer_3_2: lut40036 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0 - ); - fifo_colector_inst_data_buffer_2: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_128_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_128_fifo_colector_inst_data_buffer_3_2_H0 - , - D1=>fifo_colector_inst_SLICE_128_fifo_colector_inst_SLICE_128_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_129 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_129 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_129"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_129 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_129; - - architecture Structure of fifo_colector_inst_SLICE_129 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40035 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40036 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_129_K1: lut40035 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1 - ); - fifo_colector_inst_data_buffer_3_3: lut40036 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0 - ); - fifo_colector_inst_data_buffer_3: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_129_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_129_fifo_colector_inst_data_buffer_3_3_H0 - , - D1=>fifo_colector_inst_SLICE_129_fifo_colector_inst_SLICE_129_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40037 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40037 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; - - end lut40037; - - architecture Structure of lut40037 is - begin - INST10: ROM16X1A - generic map (initval => X"EFEA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40038 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40038 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; - - end lut40038; - - architecture Structure of lut40038 is - begin - INST10: ROM16X1A - generic map (initval => X"4540") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_130 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_130 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_130"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_130 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_130; - - architecture Structure of fifo_colector_inst_SLICE_130 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40037 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40038 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_130_K1: lut40037 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1 - ); - fifo_colector_inst_data_buffer_3_4: lut40038 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0 - ); - fifo_colector_inst_data_buffer_4: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_130_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_130_fifo_colector_inst_data_buffer_3_4_H0 - , - D1=>fifo_colector_inst_SLICE_130_fifo_colector_inst_SLICE_130_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_131 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_131 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_131"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_131 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_131; - - architecture Structure of fifo_colector_inst_SLICE_131 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40033 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40034 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_131_K1: lut40033 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1 - ); - fifo_colector_inst_data_buffer_3_5: lut40034 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0 - ); - fifo_colector_inst_data_buffer_5: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_131_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_131_fifo_colector_inst_data_buffer_3_5_H0 - , - D1=>fifo_colector_inst_SLICE_131_fifo_colector_inst_SLICE_131_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40039 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40039 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; - - end lut40039; - - architecture Structure of lut40039 is - begin - INST10: ROM16X1A - generic map (initval => X"FEAE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40040 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40040 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; - - end lut40040; - - architecture Structure of lut40040 is - begin - INST10: ROM16X1A - generic map (initval => X"5404") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_132 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_132 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_132"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_132 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_132; - - architecture Structure of fifo_colector_inst_SLICE_132 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40039 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40040 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_132_K1: lut40039 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1 - ); - fifo_colector_inst_data_buffer_3_6: lut40040 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0 - ); - fifo_colector_inst_data_buffer_6: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_132_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_132_fifo_colector_inst_data_buffer_3_6_H0 - , - D1=>fifo_colector_inst_SLICE_132_fifo_colector_inst_SLICE_132_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40041 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40041 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; - - end lut40041; - - architecture Structure of lut40041 is - begin - INST10: ROM16X1A - generic map (initval => X"FBEA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40042 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40042 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; - - end lut40042; - - architecture Structure of lut40042 is - begin - INST10: ROM16X1A - generic map (initval => X"5140") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_133 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_133 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_133"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_133 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_133; - - architecture Structure of fifo_colector_inst_SLICE_133 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1: Std_logic; - - signal fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0: Std_logic; - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40041 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40042 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_SLICE_133_K1: lut40041 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1 - ); - fifo_colector_inst_data_buffer_3_7: lut40042 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0 - ); - fifo_colector_inst_data_buffer_7: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_SLICE_133_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_SLICE_133_fifo_colector_inst_data_buffer_3_7_H0 - , - D1=>fifo_colector_inst_SLICE_133_fifo_colector_inst_SLICE_133_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40043 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40043 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; - - end lut40043; - - architecture Structure of lut40043 is - begin - INST10: ROM16X1A - generic map (initval => X"AAF0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40044 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40044 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; - - end lut40044; - - architecture Structure of lut40044 is - begin - INST10: ROM16X1A - generic map (initval => X"F0CC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_134 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_134 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_134"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_134 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_134; - - architecture Structure of fifo_colector_inst_SLICE_134 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40043 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40044 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_9: lut40043 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_8: lut40044 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_9: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_8: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40045 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40045 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; - - end lut40045; - - architecture Structure of lut40045 is - begin - INST10: ROM16X1A - generic map (initval => X"CCAA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40046 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40046 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; - - end lut40046; - - architecture Structure of lut40046 is - begin - INST10: ROM16X1A - generic map (initval => X"CCF0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_135 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_135 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_135"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_135 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_135; - - architecture Structure of fifo_colector_inst_SLICE_135 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40046 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_11: lut40045 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_10: lut40046 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_11: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_10: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40047 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40047 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; - - end lut40047; - - architecture Structure of lut40047 is - begin - INST10: ROM16X1A - generic map (initval => X"FA50") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_136 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_136 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_136"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_136 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_136; - - architecture Structure of fifo_colector_inst_SLICE_136 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40047 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_13: lut40045 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_12: lut40047 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_13: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_12: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40048 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40048 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; - - end lut40048; - - architecture Structure of lut40048 is - begin - INST10: ROM16X1A - generic map (initval => X"F0AA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_137 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_137 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_137"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_137 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_137; - - architecture Structure of fifo_colector_inst_SLICE_137 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40044 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40048 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_15: lut40044 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_14: lut40048 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_15: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_14: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40049 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40049 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; - - end lut40049; - - architecture Structure of lut40049 is - begin - INST10: ROM16X1A - generic map (initval => X"F3C0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_138 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_138 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_138"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_138 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_138; - - architecture Structure of fifo_colector_inst_SLICE_138 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40044 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40049 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_17: lut40044 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_16: lut40049 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_17: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_16: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40050 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40050 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; - - end lut40050; - - architecture Structure of lut40050 is - begin - INST10: ROM16X1A - generic map (initval => X"DD88") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_139 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_139 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_139"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_139 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_139; - - architecture Structure of fifo_colector_inst_SLICE_139 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40050 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_19: lut40045 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_18: lut40050 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_19: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_18: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_140 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_140 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_140"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_140 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_140; - - architecture Structure of fifo_colector_inst_SLICE_140 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40046 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_21: lut40045 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_20: lut40046 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_21: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_20: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_141 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_141 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_141"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_141 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_141; - - architecture Structure of fifo_colector_inst_SLICE_141 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40043 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40045 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_23: lut40045 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_22: lut40043 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_23: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_22: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40051 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40051 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; - - end lut40051; - - architecture Structure of lut40051 is - begin - INST10: ROM16X1A - generic map (initval => X"CACA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_142 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_142 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_142"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_142 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_142; - - architecture Structure of fifo_colector_inst_SLICE_142 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40048 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40051 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_25: lut40048 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_24: lut40051 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - fifo_colector_inst_data_buffer_25: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_24: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40052 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40052 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; - - end lut40052; - - architecture Structure of lut40052 is - begin - INST10: ROM16X1A - generic map (initval => X"BB88") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_143 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_143 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_143"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_143 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_143; - - architecture Structure of fifo_colector_inst_SLICE_143 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40044 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40052 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_27: lut40044 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_26: lut40052 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_27: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_26: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, B0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40053 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40053 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; - - end lut40053; - - architecture Structure of lut40053 is - begin - INST10: ROM16X1A - generic map (initval => X"EE22") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40054 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40054 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; - - end lut40054; - - architecture Structure of lut40054 is - begin - INST10: ROM16X1A - generic map (initval => X"B8B8") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_144 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_144 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_144"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_144 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_144; - - architecture Structure of fifo_colector_inst_SLICE_144 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40053 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40054 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_29: lut40053 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_28: lut40054 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - fifo_colector_inst_data_buffer_29: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_28: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40055 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40055 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; - - end lut40055; - - architecture Structure of lut40055 is - begin - INST10: ROM16X1A - generic map (initval => X"FC30") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40056 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40056 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; - - end lut40056; - - architecture Structure of lut40056 is - begin - INST10: ROM16X1A - generic map (initval => X"CFC0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_145 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_145 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_145"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_145 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_145; - - architecture Structure of fifo_colector_inst_SLICE_145 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40055 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40056 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_3_0_31: lut40055 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_3_0_30: lut40056 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_data_buffer_31: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_data_buffer_30: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI1_dly, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_146 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_146 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_146"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_146 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_146; - - architecture Structure of fifo_colector_inst_SLICE_146 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_data_buffer_33: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_data_buffer_32: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40057 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40057 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; - - end lut40057; - - architecture Structure of lut40057 is - begin - INST10: ROM16X1A - generic map (initval => X"5A5A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40058 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40058 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; - - end lut40058; - - architecture Structure of lut40058 is - begin - INST10: ROM16X1A - generic map (initval => X"0FF0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_147 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_147 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_147"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_147 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_147; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_147 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40058 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t7: lut40057 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t8: lut40058 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_60: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_61: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40059 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40059 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; - - end lut40059; - - architecture Structure of lut40059 is - begin - INST10: ROM16X1A - generic map (initval => X"55AA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40060 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40060 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; - - end lut40060; - - architecture Structure of lut40060 is - begin - INST10: ROM16X1A - generic map (initval => X"6666") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_148 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_148 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_148"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_148 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_148; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_148 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40060 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t5: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t6: lut40060 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_58: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_59: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40061 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40061 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; - - end lut40061; - - architecture Structure of lut40061 is - begin - INST10: ROM16X1A - generic map (initval => X"5A5A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40062 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40062 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; - - end lut40062; - - architecture Structure of lut40062 is - begin - INST10: ROM16X1A - generic map (initval => X"55AA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_149 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_149 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_149"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_149 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_149; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_149 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40062 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t3: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t4: lut40062 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_56: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_57: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40063 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40063 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; - - end lut40063; - - architecture Structure of lut40063 is - begin - INST10: ROM16X1A - generic map (initval => X"0FF0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_150 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_150 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_150"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_150 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_150; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_150 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40058 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t1: lut40058 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t2: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_54: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_55: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40064 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40064 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; - - end lut40064; - - architecture Structure of lut40064 is - begin - INST10: ROM16X1A - generic map (initval => X"33CC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_151 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_151 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_151"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_151 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_151; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_151 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t0: lut40064 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_52: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_53: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_152 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_152 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_152"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_152 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_152; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_152 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_30: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_31: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_153 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_153 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_153"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_153 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_153; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_153 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_28: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_29: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_154 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_154 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_154"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_154 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_154; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_154 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_26: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_27: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_155 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_155 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_155"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_155 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_155; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_155 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_24: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_25: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_156 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_156 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_156"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_156 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_156; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_156 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_22: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_23: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_157 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_157 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_157"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_157 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_157; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_157 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_10: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_11: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_158 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_158 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_158"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_158 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_158; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_158 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_8: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_9: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_159 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_159 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_159"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_159 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_159; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_159 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_160 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_160 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_160"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_160 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_160; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_160 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_161 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_161 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_161"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_161 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_161; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_161 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_162 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_162 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_162"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_162 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_162; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_162 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_50: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_51: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_163 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_163 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_163"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_163 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_163; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_163 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_48: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_49: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_164 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_164 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_164"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_164 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_164; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_164 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_46: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_47: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_165 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_165 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_165"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_165 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_165; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_165 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_44: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_45: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_166 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_166 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_166"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_166 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_166; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_166 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_42: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_43: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40065 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40065 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; - - end lut40065; - - architecture Structure of lut40065 is - begin - INST10: ROM16X1A - generic map (initval => X"3C3C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40066 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40066 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; - - end lut40066; - - architecture Structure of lut40066 is - begin - INST10: ROM16X1A - generic map (initval => X"33CC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_167 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_167 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_167"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_167 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_167; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_167 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t16: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t17: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_90: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_91: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_168 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_168 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_168"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_168 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_168; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_168 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40058 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t14: lut40058 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t15: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_88: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_89: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_169 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_169 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_169"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_169 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_169; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_169 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t12: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t13: lut40061 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_86: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_87: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_170 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_170 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_170"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_170 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_170; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_170 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t10: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_XOR2_t11: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_fifo40_inst_FF_84: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_85: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_171 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_171 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_171"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_171 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_171; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_171 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_XOR2_t9: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_82: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_fifo40_inst_FF_83: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_172 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_172 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_172"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_172 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_172; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_172 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_40: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_41: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_173 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_173 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_173"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_173 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_173; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_173 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_38: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_39: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_174 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_174 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_174"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_174 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_174; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_174 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_36: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_37: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_175 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_175 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_175"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_175 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_175; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_175 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_34: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_35: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_176 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_176 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_176"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_176 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_176; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_176 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_32: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_33: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_177 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_177 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_177"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_177 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_177; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_177 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_20: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_21: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_178 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_178 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_178"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_178 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_178; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_178 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_18: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_19: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_179 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_179 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_179"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_179 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_179; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_179 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_16: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_17: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_180 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_180 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_180"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_180 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_180; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_180 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_14: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_15: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_181 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_181 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_181"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_181 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_181; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_181 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_12: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_13: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_182 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_182 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_182"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_182 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_182; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_182 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_80: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_81: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_183 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_183 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_183"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_183 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_183; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_183 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_78: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_79: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_184 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_184 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_184"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_184 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_184; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_184 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_76: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_77: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_185 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_185 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_185"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_185 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_185; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_185 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_74: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_75: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_186 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_186 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_186"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_186 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_186; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_186 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_FF_72: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_FF_73: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40067 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40067 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; - - end lut40067; - - architecture Structure of lut40067 is - begin - INST10: ROM16X1A - generic map (initval => X"0303") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_187 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_187 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_187"; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_187 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_187; - - architecture Structure of fifo_colector_inst_SLICE_187 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40067 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_un5_in_read_enable: lut40067 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_iterator_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_iterator_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, - Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40068 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40068 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; - - end lut40068; - - architecture Structure of lut40068 is - begin - INST10: ROM16X1A - generic map (initval => X"0404") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40069 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40069 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; - - end lut40069; - - architecture Structure of lut40069 is - begin - INST10: ROM16X1A - generic map (initval => X"CFCC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity trb_adapter_inst_SLICE_188 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_188 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_188"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_188 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_188; - - architecture Structure of trb_adapter_inst_SLICE_188 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40068 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40069 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trb_adapter_inst_burst: lut40068 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - trb_adapter_inst_buf_rden4: lut40069 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - trb_adapter_inst_buf_rden: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI0_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40070 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40070 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; - - end lut40070; - - architecture Structure of lut40070 is - begin - INST10: ROM16X1A - generic map (initval => X"FCFC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40071 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40071 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; - - end lut40071; - - architecture Structure of lut40071 is - begin - INST10: ROM16X1A - generic map (initval => X"FF05") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_189 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_189 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_189"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_189 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_189; - - architecture Structure of fifo_colector_inst_SLICE_189 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40070 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40071 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_in_read_enable_1_fb: lut40070 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_in_read_enable_0_fb: lut40071 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - fifo_colector_inst_in_read_enable_1: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - fifo_colector_inst_in_read_enable_0: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, A0_ipd, DI1_dly, - DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40072 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40072 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; - - end lut40072; - - architecture Structure of lut40072 is - begin - INST10: ROM16X1A - generic map (initval => X"FFAA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_190 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_190 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_190"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_190 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_190; - - architecture Structure of fifo_colector_inst_SLICE_190 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40072 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_in_read_enable_2_fb: lut40072 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_in_read_enable_2: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity inverter - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity inverter is - port (I: in Std_logic; Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; - - end inverter; - - architecture Structure of inverter is - begin - INST1: INV - port map (A=>I, Z=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40073 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40073 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; - - end lut40073; - - architecture Structure of lut40073 is - begin - INST10: ROM16X1A - generic map (initval => X"080D") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40073 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40073 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40058 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40057 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40058 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40074 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40074 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; - - end lut40074; - - architecture Structure of lut40074 is - begin - INST10: ROM16X1A - generic map (initval => X"6666") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40074 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40074 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40028 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40028 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40028 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40065 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, C0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40075 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40075 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; - - end lut40075; - - architecture Structure of lut40075 is - begin - INST10: ROM16X1A - generic map (initval => X"FFCC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_SLICE_246"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_SLICE_246; - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40075 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40075 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, B0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40076 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40076 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40076 : ENTITY IS TRUE; - - end lut40076; - - architecture Structure of lut40076 is - begin - INST10: ROM16X1A - generic map (initval => X"080B") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40076 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40076 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40060 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40074 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40074 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40060 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40062 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40062 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308" - ; - - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40074 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40074 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40058 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40058 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40059 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310" - ; - - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40074 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40074 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_SLICE_326"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_SLICE_326; - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40072 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40072 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40077 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40077 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40077 : ENTITY IS TRUE; - - end lut40077; - - architecture Structure of lut40077 is - begin - INST10: ROM16X1A - generic map (initval => X"00B1") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40077 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO: lut40077 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t7: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t8: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_60: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_61: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t5: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t6: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_58: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_59: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t3: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t4: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_56: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_57: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t1: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t2: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_54: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_55: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t0: lut40028 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_52: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_53: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_30: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_31: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_28: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_29: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_26: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_27: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_24: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_25: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_22: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_23: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_10: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_11: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_8: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_9: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_50: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_51: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_48: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_49: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_46: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_47: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_44: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_45: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_42: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_43: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t16: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t17: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_90: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_91: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t14: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t15: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_88: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_89: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40062 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t12: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t13: lut40062 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_86: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_87: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, A0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40066 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t10: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t11: lut40066 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_84: svmuxregsre - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_85: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, B0_ipd, DI1_dly, DI0_dly, - CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_XOR2_t9: lut40065 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_82: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_83: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, M1_dly, CE_dly, CLK_dly, - F0_out, Q0_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_40: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_41: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_38: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_39: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_36: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_37: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_34: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_35: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_32: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_33: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_20: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_21: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_18: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_19: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_16: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_17: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_14: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_15: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_12: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_13: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_80: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_81: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_78: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_79: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_76: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_77: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_74: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_75: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_72: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_FF_73: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40078 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40078 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40078 : ENTITY IS TRUE; - - end lut40078; - - architecture Structure of lut40078 is - begin - INST10: ROM16X1A - generic map (initval => X"FCFC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_SLICE_406"; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_SLICE_406; - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40078 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_11_fb: lut40078 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_11: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40079 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40079 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40079 : ENTITY IS TRUE; - - end lut40079; - - architecture Structure of lut40079 is - begin - INST10: ROM16X1A - generic map (initval => X"0033") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40080 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40080 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40080 : ENTITY IS TRUE; - - end lut40080; - - architecture Structure of lut40080 is - begin - INST10: ROM16X1A - generic map (initval => X"0200") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_432 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_432 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_432"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_432 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_432; - - architecture Structure of hades_tdc_bundle_inst_SLICE_432 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40079 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40080 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_buf_finished5_0_a2_0: lut40079 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_buf_finished_RNO: lut40080 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_buf_finished: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_433 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_433 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_433"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_433 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_433; - - architecture Structure of hades_tdc_bundle_inst_SLICE_433 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_buf_release: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, LSR_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40081 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40081 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40081 : ENTITY IS TRUE; - - end lut40081; - - architecture Structure of lut40081 is - begin - INST10: ROM16X1A - generic map (initval => X"00FF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_434 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_434 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_434"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_434 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_434; - - architecture Structure of hades_tdc_bundle_inst_SLICE_434 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40028 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40081 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc1: lut40028 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_coarse_RNI8DE6_0: lut40081 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_coarse_1: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_coarse_0: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, DI1_dly, DI0_dly, LSR_dly, - CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40082 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40082 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40082 : ENTITY IS TRUE; - - end lut40082; - - architecture Structure of lut40082 is - begin - INST10: ROM16X1A - generic map (initval => X"78F0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40083 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40083 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40083 : ENTITY IS TRUE; - - end lut40083; - - architecture Structure of lut40083 is - begin - INST10: ROM16X1A - generic map (initval => X"5AF0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_435 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_435 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_435"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_435 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_435; - - architecture Structure of hades_tdc_bundle_inst_SLICE_435 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40082 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40083 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_coarse_RNI6RPP_2: lut40082 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc2: lut40083 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_coarse_3: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_coarse_2: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40084 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40084 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40084 : ENTITY IS TRUE; - - end lut40084; - - architecture Structure of lut40084 is - begin - INST10: ROM16X1A - generic map (initval => X"7F80") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40085 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40085 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40085 : ENTITY IS TRUE; - - end lut40085; - - architecture Structure of lut40085 is - begin - INST10: ROM16X1A - generic map (initval => X"7788") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_436 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_436 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_436"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_436 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_436; - - architecture Structure of hades_tdc_bundle_inst_SLICE_436 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40084 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40085 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc5: lut40084 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc4: lut40085 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_coarse_5: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_coarse_4: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, - A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40086 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40086 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40086 : ENTITY IS TRUE; - - end lut40086; - - architecture Structure of lut40086 is - begin - INST10: ROM16X1A - generic map (initval => X"7F80") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40087 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40087 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40087 : ENTITY IS TRUE; - - end lut40087; - - architecture Structure of lut40087 is - begin - INST10: ROM16X1A - generic map (initval => X"78F0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_437 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_437 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_437"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_437 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_437; - - architecture Structure of hades_tdc_bundle_inst_SLICE_437 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40086 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40087 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc7: lut40086 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc6: lut40087 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_coarse_7: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_coarse_6: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40088 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40088 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40088 : ENTITY IS TRUE; - - end lut40088; - - architecture Structure of lut40088 is - begin - INST10: ROM16X1A - generic map (initval => X"8000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40089 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40089 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40089 : ENTITY IS TRUE; - - end lut40089; - - architecture Structure of lut40089 is - begin - INST10: ROM16X1A - generic map (initval => X"78F0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_438 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_438 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_438"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_438 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_438; - - architecture Structure of hades_tdc_bundle_inst_SLICE_438 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40088 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40089 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_5: lut40088 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_axbxc8: lut40089 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_coarse_8: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_439 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_439 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_439"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_439 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_439; - - architecture Structure of hades_tdc_bundle_inst_SLICE_439 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hitbuffer_1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_440 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_440 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_440"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_440 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_440; - - architecture Structure of hades_tdc_bundle_inst_SLICE_440 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hitbuffer_1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_441 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_441 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_441"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_441 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_441; - - architecture Structure of hades_tdc_bundle_inst_SLICE_441 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_8: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hitbuffer_1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_442 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_442 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_442"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_442 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_442; - - architecture Structure of hades_tdc_bundle_inst_SLICE_442 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_10: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hitbuffer_1_9: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_443 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_443 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_443"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_443 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_443; - - architecture Structure of hades_tdc_bundle_inst_SLICE_443 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_11: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40090 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40090 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40090 : ENTITY IS TRUE; - - end lut40090; - - architecture Structure of lut40090 is - begin - INST10: ROM16X1A - generic map (initval => X"F0F8") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40091 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40091 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40091 : ENTITY IS TRUE; - - end lut40091; - - architecture Structure of lut40091 is - begin - INST10: ROM16X1A - generic map (initval => X"EEE0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40090 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40091 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en: lut40090 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_RNI41GL1_3: lut40091 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_445 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_445 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_445"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_445 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_445; - - architecture Structure of hades_tdc_bundle_inst_SLICE_445 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_446 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_446 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_446"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_446 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_446; - - architecture Structure of hades_tdc_bundle_inst_SLICE_446 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_447 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_447 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_447"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_447 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_447; - - architecture Structure of hades_tdc_bundle_inst_SLICE_447 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_448 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_448 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_448"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_448 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_448; - - architecture Structure of hades_tdc_bundle_inst_SLICE_448 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_449 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_449 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_449"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_449 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_449; - - architecture Structure of hades_tdc_bundle_inst_SLICE_449 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_1_8: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_450 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_450 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_450"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_450 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_450; - - architecture Structure of hades_tdc_bundle_inst_SLICE_450 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_451 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_451 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_451"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_451 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_451; - - architecture Structure of hades_tdc_bundle_inst_SLICE_451 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_452 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_452 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_452"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_452 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_452; - - architecture Structure of hades_tdc_bundle_inst_SLICE_452 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_453 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_453 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_453"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_453 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_453; - - architecture Structure of hades_tdc_bundle_inst_SLICE_453 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_454 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_454 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_454"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_454 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_454; - - architecture Structure of hades_tdc_bundle_inst_SLICE_454 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_8: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CE_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40092 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40092 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40092 : ENTITY IS TRUE; - - end lut40092; - - architecture Structure of lut40092 is - begin - INST10: ROM16X1A - generic map (initval => X"8000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40093 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40093 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40093 : ENTITY IS TRUE; - - end lut40093; - - architecture Structure of lut40093 is - begin - INST10: ROM16X1A - generic map (initval => X"0000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_455 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_455 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_455"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_455 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_455; - - architecture Structure of hades_tdc_bundle_inst_SLICE_455 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40092 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_455_K1: lut40092 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1 - ); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_1_9: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_SLICE_455_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_15_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_455_hades_tdc_bundle_inst_SLICE_455_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, - CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40094 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40094 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40094 : ENTITY IS TRUE; - - end lut40094; - - architecture Structure of lut40094 is - begin - INST10: ROM16X1A - generic map (initval => X"3F30") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_456 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_456 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_456"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_456 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_456; - - architecture Structure of hades_tdc_bundle_inst_SLICE_456 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40094 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i: lut40094 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_valid: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, DI0_dly, CE_dly, CLK_dly, - F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40095 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40095 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40095 : ENTITY IS TRUE; - - end lut40095; - - architecture Structure of lut40095 is - begin - INST10: ROM16X1A - generic map (initval => X"3300") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40096 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40096 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40096 : ENTITY IS TRUE; - - end lut40096; - - architecture Structure of lut40096 is - begin - INST10: ROM16X1A - generic map (initval => X"00F4") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_457 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_457 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_457"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_457 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_457; - - architecture Structure of hades_tdc_bundle_inst_SLICE_457 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0: Std_logic; - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40095 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40096 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_457_K1: lut40095 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_1_RNO_0: lut40096 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0 - ); - hades_tdc_bundle_inst_hit_valid_1_0: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - hades_tdc_bundle_inst_SLICE_457_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_hit_valid_1_RNO_0_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_457_hades_tdc_bundle_inst_SLICE_457_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40097 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40097 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40097 : ENTITY IS TRUE; - - end lut40097; - - architecture Structure of lut40097 is - begin - INST10: ROM16X1A - generic map (initval => X"003F") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40098 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40098 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40098 : ENTITY IS TRUE; - - end lut40098; - - architecture Structure of lut40098 is - begin - INST10: ROM16X1A - generic map (initval => X"0015") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_458 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_458 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_458"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_458 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_458; - - architecture Structure of hades_tdc_bundle_inst_SLICE_458 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0: Std_logic; - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40097 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40098 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_458_K1: lut40097 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_1_RNO_1: lut40098 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0 - ); - hades_tdc_bundle_inst_hit_valid_1_1: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - hades_tdc_bundle_inst_SLICE_458_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_hit_valid_1_RNO_1_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_458_hades_tdc_bundle_inst_SLICE_458_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40099 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40099 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40099 : ENTITY IS TRUE; - - end lut40099; - - architecture Structure of lut40099 is - begin - INST10: ROM16X1A - generic map (initval => X"0B0A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40100 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40100 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40100 : ENTITY IS TRUE; - - end lut40100; - - architecture Structure of lut40100 is - begin - INST10: ROM16X1A - generic map (initval => X"0F00") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_459 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_459 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_459"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_459 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_459; - - architecture Structure of hades_tdc_bundle_inst_SLICE_459 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0: Std_logic; - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40099 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40100 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_459_K1: lut40099 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1 - ); - hades_tdc_bundle_inst_hit_valid_1_RNO_2: lut40100 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_1_2: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - hades_tdc_bundle_inst_SLICE_459_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_hit_valid_1_RNO_2_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_459_hades_tdc_bundle_inst_SLICE_459_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40101 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40101 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40101 : ENTITY IS TRUE; - - end lut40101; - - architecture Structure of lut40101 is - begin - INST10: ROM16X1A - generic map (initval => X"3230") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_460 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_460 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_460"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_460 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_460; - - architecture Structure of hades_tdc_bundle_inst_SLICE_460 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0: Std_logic; - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40100 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40101 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_460_K1: lut40101 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1 - ); - hades_tdc_bundle_inst_hit_valid_1_RNO_3: lut40100 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_1_3: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - hades_tdc_bundle_inst_SLICE_460_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_hit_valid_1_RNO_3_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_460_hades_tdc_bundle_inst_SLICE_460_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dl_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40102 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40102 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40102 : ENTITY IS TRUE; - - end lut40102; - - architecture Structure of lut40102 is - begin - INST10: ROM16X1A - generic map (initval => X"5500") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40102 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_valid_RNO: lut40102 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_valid: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, - F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_1: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_0: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_12: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_2: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_14: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_13: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_16: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_15: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_18: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_17: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_20: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_19: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_22: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_21: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_23: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40103 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40103 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40103 : ENTITY IS TRUE; - - end lut40103; - - architecture Structure of lut40103 is - begin - INST10: ROM16X1A - generic map (initval => X"7350") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40104 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40104 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40104 : ENTITY IS TRUE; - - end lut40104; - - architecture Structure of lut40104 is - begin - INST10: ROM16X1A - generic map (initval => X"FFEF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity svmuxregsre0105 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity svmuxregsre0105 is - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF svmuxregsre0105 : ENTITY IS TRUE; - - end svmuxregsre0105; - - architecture Structure of svmuxregsre0105 is - begin - INST01: FL1P3JY - generic map (GSR => "DISABLED") - port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40103 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40104 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_o7: lut40103 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i: lut40104 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40106 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40106 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40106 : ENTITY IS TRUE; - - end lut40106; - - architecture Structure of lut40106 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40107 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40107 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40107 : ENTITY IS TRUE; - - end lut40107; - - architecture Structure of lut40107 is - begin - INST10: ROM16X1A - generic map (initval => X"73FF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40106 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40107 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1: lut40106 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i: lut40107 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40108 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40108 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40108 : ENTITY IS TRUE; - - end lut40108; - - architecture Structure of lut40108 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40106 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40108 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1: lut40108 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: lut40106 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40109 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40109 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40109 : ENTITY IS TRUE; - - end lut40109; - - architecture Structure of lut40109 is - begin - INST10: ROM16X1A - generic map (initval => X"3011") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40109 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO: lut40109 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal_RNO_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40110 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40110 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40110 : ENTITY IS TRUE; - - end lut40110; - - architecture Structure of lut40110 is - begin - INST10: ROM16X1A - generic map (initval => X"CCC3") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40111 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40111 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40111 : ENTITY IS TRUE; - - end lut40111; - - architecture Structure of lut40111 is - begin - INST10: ROM16X1A - generic map (initval => X"CFC3") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40110 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40111 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1: lut40110 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0: lut40111 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0 - ); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNO_0_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - DI0_dly, M0_ipd, LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40112 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40112 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40112 : ENTITY IS TRUE; - - end lut40112; - - architecture Structure of lut40112 is - begin - INST10: ROM16X1A - generic map (initval => X"FF10") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40112 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3: lut40112 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1: lut40112 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40113 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40113 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40113 : ENTITY IS TRUE; - - end lut40113; - - architecture Structure of lut40113 is - begin - INST10: ROM16X1A - generic map (initval => X"FAC8") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40113 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup: lut40113 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0 - ); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40114 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40114 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40114 : ENTITY IS TRUE; - - end lut40114; - - architecture Structure of lut40114 is - begin - INST10: ROM16X1A - generic map (initval => X"FF04") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40114 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5: lut40114 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4: lut40114 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40115 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40115 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40115 : ENTITY IS TRUE; - - end lut40115; - - architecture Structure of lut40115 is - begin - INST10: ROM16X1A - generic map (initval => X"FF02") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40115 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7: lut40115 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6: lut40115 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, - F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_4: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_3: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_6: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_5: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_8: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_7: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_10: svmuxregsre0026 - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_9: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out, - Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_11: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CE_dly, LSR_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40116 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40116 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40116 : ENTITY IS TRUE; - - end lut40116; - - architecture Structure of lut40116 is - begin - INST10: ROM16X1A - generic map (initval => X"F000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40116 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_RNIG7JA: lut40116 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_raw_out_valid: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40117 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40117 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40117 : ENTITY IS TRUE; - - end lut40117; - - architecture Structure of lut40117 is - begin - INST10: ROM16X1A - generic map (initval => X"5808") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40117 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4_f0_0_0: lut40117 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, - CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CE_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40118 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40118 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40118 : ENTITY IS TRUE; - - end lut40118; - - architecture Structure of lut40118 is - begin - INST10: ROM16X1A - generic map (initval => X"7520") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CE_NOTIN: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40118 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready_4_iv_i_0: lut40118 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_NOTIN, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CE_INVERTERIN: inverter - port map (I=>CE_dly, Z=>CE_NOTIN); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, CE_dly, - CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40119 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40119 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40119 : ENTITY IS TRUE; - - end lut40119; - - architecture Structure of lut40119 is - begin - INST10: ROM16X1A - generic map (initval => X"50DC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40120 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40120 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40120 : ENTITY IS TRUE; - - end lut40120; - - architecture Structure of lut40120 is - begin - INST10: ROM16X1A - generic map (initval => X"FEFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40119 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40120 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_o7: lut40119 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i: lut40120 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40121 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40121 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40121 : ENTITY IS TRUE; - - end lut40121; - - architecture Structure of lut40121 is - begin - INST10: ROM16X1A - generic map (initval => X"5FDF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40106 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40121 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1: lut40106 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i: lut40121 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_H0 - , - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40122 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40122 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40122 : ENTITY IS TRUE; - - end lut40122; - - architecture Structure of lut40122 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40106 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40122 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1: lut40122 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: lut40106 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_H0 - , - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40123 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40123 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40123 : ENTITY IS TRUE; - - end lut40123; - - architecture Structure of lut40123 is - begin - INST10: ROM16X1A - generic map (initval => X"4045") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40123 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO: lut40123 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal_RNO_H0 - , - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40124 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40124 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40124 : ENTITY IS TRUE; - - end lut40124; - - architecture Structure of lut40124 is - begin - INST10: ROM16X1A - generic map (initval => X"FFDD") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40125 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40125 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40125 : ENTITY IS TRUE; - - end lut40125; - - architecture Structure of lut40125 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFD") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40124 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40125 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m15_i: lut40124 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i: lut40125 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, DI1_dly, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, - Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_negedge, - SetupLow => tsetup_DI1_CLK_noedge_negedge, - HoldHigh => thold_DI1_CLK_noedge_negedge, - HoldLow => thold_DI1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40126 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40126 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40126 : ENTITY IS TRUE; - - end lut40126; - - architecture Structure of lut40126 is - begin - INST10: ROM16X1A - generic map (initval => X"75FD") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40127 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40127 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40127 : ENTITY IS TRUE; - - end lut40127; - - architecture Structure of lut40127 is - begin - INST10: ROM16X1A - generic map (initval => X"DFFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component svmuxregsre0105 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40126 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40127 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5: lut40126 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0: lut40127 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2: svmuxregsre0105 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40128 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40128 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40128 : ENTITY IS TRUE; - - end lut40128; - - architecture Structure of lut40128 is - begin - INST10: ROM16X1A - generic map (initval => X"4501") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40128 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO: lut40128 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal_RNO_H0 - , - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M0_ipd, - LSR_dly, CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_negedge, - SetupLow => tsetup_DI0_CLK_noedge_negedge, - HoldHigh => thold_DI0_CLK_noedge_negedge, - HoldLow => thold_DI0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_in_clk_synced_0: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered1_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_in_clk_synced_1: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered1_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_in_clk_synced_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered1_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_in_clk_synced_3: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered1_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_in_clk_synced_4: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered1_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_in_clk_synced_5: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered1_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_in_clk_synced_6: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered1_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611" - ; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_in_clk_synced_7: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered1_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_negedge, - SetupLow => tsetup_M1_CLK_noedge_negedge, - HoldHigh => thold_M1_CLK_noedge_negedge, - HoldLow => thold_M1_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered_0: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered_3: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_0_out_buffered_4: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_1_out_buffered_5: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_2_out_buffered_6: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627" - ; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_genblk1_3_out_buffered_7: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40129 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40129 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40129 : ENTITY IS TRUE; - - end lut40129; - - architecture Structure of lut40129 is - begin - INST10: ROM16X1A - generic map (initval => X"5AAA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_628 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_628 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_628"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI1_CLK : VitalDelayType := 0 ns; - tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_628 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_628; - - architecture Structure of hades_tdc_bundle_inst_SLICE_628 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal DI1_ipd : std_logic := 'X'; - signal DI1_dly : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40057 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40129 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_0_0: lut40129 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM0_1_0_x2: lut40057 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - hades_tdc_bundle_inst_hit_i_1: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hit_i_0: svmuxregsre0026 - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(DI1_ipd, DI1, tipd_DI1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, C0_ipd, A0_ipd, DI1_dly, - DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI1_CLK : x01 := '0'; - VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI1_dly, - TestSignalName => "DI1", - TestDelay => tisd_DI1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI1_CLK_noedge_posedge, - SetupLow => tsetup_DI1_CLK_noedge_posedge, - HoldHigh => thold_DI1_CLK_noedge_posedge, - HoldLow => thold_DI1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI1_CLK_TimingDatash, - Violation => tviol_DI1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - F1_zd := F1_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40130 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40130 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40130 : ENTITY IS TRUE; - - end lut40130; - - architecture Structure of lut40130 is - begin - INST10: ROM16X1A - generic map (initval => X"0004") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI0_CLK : VitalDelayType := 0 ns; - tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal DI0_ipd : std_logic := 'X'; - signal DI0_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1: Std_logic; - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40130 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1: lut40130 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1 - ); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end: svmuxregsre - port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5_0_a2_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(DI0_ipd, DI0, tipd_DI0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, M0_ipd, - CLK_dly, OFX0_out, Q0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI0_CLK : x01 := '0'; - VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI0_dly, - TestSignalName => "DI0", - TestDelay => tisd_DI0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI0_CLK_noedge_posedge, - SetupLow => tsetup_DI0_CLK_noedge_posedge, - HoldHigh => thold_DI0_CLK_noedge_posedge, - HoldLow => thold_DI0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI0_CLK_TimingDatash, - Violation => tviol_DI0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - OFX0_zd := OFX0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trb_adapter_inst_SLICE_631 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_631 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_631"; - - tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M1_CLK : VitalDelayType := 0 ns; - tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_631 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_631; - - architecture Structure of trb_adapter_inst_SLICE_631 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M1_ipd : std_logic := 'X'; - signal M1_dly : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - signal Q1_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2: svmuxregsre - port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q1_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M1_ipd, M1, tipd_M1); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M1_dly, M0_dly, CLK_dly, Q0_out, Q1_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - VARIABLE Q1_zd : std_logic := 'X'; - VARIABLE Q1_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M1_CLK : x01 := '0'; - VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M1_dly, - TestSignalName => "M1", - TestDelay => tisd_M1_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M1_CLK_noedge_posedge, - SetupLow => tsetup_M1_CLK_noedge_posedge, - HoldHigh => thold_M1_CLK_noedge_posedge, - HoldLow => thold_M1_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M1_CLK_TimingDatash, - Violation => tviol_M1_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - Q1_zd := Q1_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q1, - PathCondition => TRUE)), - GlitchData => Q1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trb_adapter_inst_SLICE_632 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_632 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_632"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_632 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_632; - - architecture Structure of trb_adapter_inst_SLICE_632 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - trb_adapter_inst_buf_rden_prev: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trb_adapter_inst_SLICE_633 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_633 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_633"; - - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_633 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_633; - - architecture Structure of trb_adapter_inst_SLICE_633 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - begin - trb_adapter_inst_finished_prev: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (M0_dly, CLK_dly, Q0_out) - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40131 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40131 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40131 : ENTITY IS TRUE; - - end lut40131; - - architecture Structure of lut40131 is - begin - INST10: ROM16X1A - generic map (initval => X"DC50") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M0: in Std_logic; OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40100 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40131 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1: lut40100 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0: lut40131 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0 - ); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40132 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40132 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40132 : ENTITY IS TRUE; - - end lut40132; - - architecture Structure of lut40132 is - begin - INST10: ROM16X1A - generic map (initval => X"0002") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40132 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1: lut40132 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0 - ); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1_H0 - , - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40133 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40133 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40133 : ENTITY IS TRUE; - - end lut40133; - - architecture Structure of lut40133 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40134 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40134 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40134 : ENTITY IS TRUE; - - end lut40134; - - architecture Structure of lut40134 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40133 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40134 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1: lut40133 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40134 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K0K1MUX: selmux2 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - , - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40133 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40134 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1: lut40133 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40134 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K0K1MUX: selmux2 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - , - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40133 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40134 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1: lut40133 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40134 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K0K1MUX: selmux2 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - , - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40133 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40134 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1: lut40133 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40134 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - ); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K0K1MUX: selmux2 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - , - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40135 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40135 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40135 : ENTITY IS TRUE; - - end lut40135; - - architecture Structure of lut40135 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40136 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40136 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40136 : ENTITY IS TRUE; - - end lut40136; - - architecture Structure of lut40136 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40135 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40136 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1: lut40135 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40136 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K0K1MUX: selmux2 - port map ( - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - , - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40137 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40137 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40137 : ENTITY IS TRUE; - - end lut40137; - - architecture Structure of lut40137 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40138 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40138 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40138 : ENTITY IS TRUE; - - end lut40138; - - architecture Structure of lut40138 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40137 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40138 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1: lut40137 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40138 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K0K1MUX: selmux2 - port map ( - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - , - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40139 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40139 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40139 : ENTITY IS TRUE; - - end lut40139; - - architecture Structure of lut40139 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40140 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40140 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40140 : ENTITY IS TRUE; - - end lut40140; - - architecture Structure of lut40140 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40139 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40140 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1: lut40139 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40140 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K0K1MUX: selmux2 - port map ( - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - , - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40141 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40141 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40141 : ENTITY IS TRUE; - - end lut40141; - - architecture Structure of lut40141 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40142 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40142 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40142 : ENTITY IS TRUE; - - end lut40142; - - architecture Structure of lut40142 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40141 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40142 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1: lut40141 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40142 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - ); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K0K1MUX: selmux2 - port map ( - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - , - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40141 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40142 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1: lut40141 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16: lut40142 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K0K1MUX: selmux2 - port map ( - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_16_H0 - , - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40133 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40134 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1: lut40133 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19: lut40134 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K0K1MUX: selmux2 - port map ( - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_19_H0 - , - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40143 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40143 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40143 : ENTITY IS TRUE; - - end lut40143; - - architecture Structure of lut40143 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40144 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40144 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40144 : ENTITY IS TRUE; - - end lut40144; - - architecture Structure of lut40144 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40143 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40144 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1: lut40143 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6: lut40144 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K0K1MUX: selmux2 - port map ( - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_6_H0 - , - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40145 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40145 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40145 : ENTITY IS TRUE; - - end lut40145; - - architecture Structure of lut40145 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40146 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40146 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40146 : ENTITY IS TRUE; - - end lut40146; - - architecture Structure of lut40146 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40145 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40146 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1: lut40145 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9: lut40146 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - ); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K0K1MUX: selmux2 - port map ( - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_9_H0 - , - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40147 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40147 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40147 : ENTITY IS TRUE; - - end lut40147; - - architecture Structure of lut40147 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40148 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40148 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40148 : ENTITY IS TRUE; - - end lut40148; - - architecture Structure of lut40148 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_648 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_648 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_648"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_648 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_648; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_648 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1: Std_logic; - - signal fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40147 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40148 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_SLICE_648_K1: lut40147 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1 - ); - fifo_colector_inst_fifo40_inst_LUT4_6: lut40148 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0 - ); - fifo_colector_inst_fifo40_inst_SLICE_648_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_LUT4_6_H0 - , - D1=>fifo_colector_inst_fifo40_inst_SLICE_648_fifo_colector_inst_fifo40_inst_SLICE_648_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40149 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40149 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40149 : ENTITY IS TRUE; - - end lut40149; - - architecture Structure of lut40149 is - begin - INST10: ROM16X1A - generic map (initval => X"9669") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_649 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_649 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_649"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_649 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_649; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_649 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1: Std_logic; - - signal fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40148 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40149 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_SLICE_649_K1: lut40149 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1 - ); - fifo_colector_inst_fifo40_inst_LUT4_9: lut40148 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0 - ); - fifo_colector_inst_fifo40_inst_SLICE_649_K0K1MUX: selmux2 - port map ( - D0=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_LUT4_9_H0 - , - D1=>fifo_colector_inst_fifo40_inst_SLICE_649_fifo_colector_inst_fifo40_inst_SLICE_649_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40150 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40150 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40150 : ENTITY IS TRUE; - - end lut40150; - - architecture Structure of lut40150 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40151 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40151 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40151 : ENTITY IS TRUE; - - end lut40151; - - architecture Structure of lut40151 is - begin - INST10: ROM16X1A - generic map (initval => X"3FAE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40150 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40151 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1: lut40150 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1 - ); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40151 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - ); - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K0K1MUX: selmux2 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - , - D1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40152 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40152 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40152 : ENTITY IS TRUE; - - end lut40152; - - architecture Structure of lut40152 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40153 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40153 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40153 : ENTITY IS TRUE; - - end lut40153; - - architecture Structure of lut40153 is - begin - INST10: ROM16X1A - generic map (initval => X"7F4E") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40152 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40153 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1: lut40152 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1 - ); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40153 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - ); - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K0K1MUX: selmux2 - port map ( - D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - , - D1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40154 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40154 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40154 : ENTITY IS TRUE; - - end lut40154; - - architecture Structure of lut40154 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40155 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40155 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40155 : ENTITY IS TRUE; - - end lut40155; - - architecture Structure of lut40155 is - begin - INST10: ROM16X1A - generic map (initval => X"74FE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0: Std_logic; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40154 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40155 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1: lut40154 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1 - ); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40155 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - ); - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K0K1MUX: selmux2 - port map ( - D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0_H0 - , - D1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 5 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 6 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 7 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 8 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40156 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40156 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40156 : ENTITY IS TRUE; - - end lut40156; - - architecture Structure of lut40156 is - begin - INST10: ROM16X1A - generic map (initval => X"FFFE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_653 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_653 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_653"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_653 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_653; - - architecture Structure of hades_tdc_bundle_inst_SLICE_653 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal OFX0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1: Std_logic; - - signal hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component selmux2 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - Z: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40156 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_SLICE_653_K1: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, - Z=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1 - ); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11: lut40156 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, - Z=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0 - ); - hades_tdc_bundle_inst_SLICE_653_K0K1MUX: selmux2 - port map ( - D0=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2_RNITDG11_H0 - , - D1=>hades_tdc_bundle_inst_SLICE_653_hades_tdc_bundle_inst_SLICE_653_K1_H1 - , SD=>M0_ipd, Z=>OFX0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_ipd, OFX0_out) - VARIABLE OFX0_zd : std_logic := 'X'; - VARIABLE OFX0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - OFX0_zd := OFX0_out; - - VitalPathDelay01 ( - OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_OFX0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_OFX0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_OFX0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_OFX0, - PathCondition => TRUE), - 4 => (InputChangeTime => M0_ipd'last_event, - PathDelay => tpd_M0_OFX0, - PathCondition => TRUE)), - GlitchData => OFX0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40157 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40157 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40157 : ENTITY IS TRUE; - - end lut40157; - - architecture Structure of lut40157 is - begin - INST10: ROM16X1A - generic map (initval => X"1000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40158 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40158 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40158 : ENTITY IS TRUE; - - end lut40158; - - architecture Structure of lut40158 is - begin - INST10: ROM16X1A - generic map (initval => X"FF20") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_654 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_654 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_654"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_654 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_654; - - architecture Structure of hades_tdc_bundle_inst_SLICE_654 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40157 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40158 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2: lut40157 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0: lut40158 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40159 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40159 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40159 : ENTITY IS TRUE; - - end lut40159; - - architecture Structure of lut40159 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40160 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40160 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40160 : ENTITY IS TRUE; - - end lut40160; - - architecture Structure of lut40160 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40160 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40159 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40160 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40161 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40161 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40161 : ENTITY IS TRUE; - - end lut40161; - - architecture Structure of lut40161 is - begin - INST10: ROM16X1A - generic map (initval => X"C33C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40161 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40161 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40159 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40162 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40162 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40162 : ENTITY IS TRUE; - - end lut40162; - - architecture Structure of lut40162 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40163 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40163 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40163 : ENTITY IS TRUE; - - end lut40163; - - architecture Structure of lut40163 is - begin - INST10: ROM16X1A - generic map (initval => X"9696") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40162 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40163 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40162 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40164 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40164 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40164 : ENTITY IS TRUE; - - end lut40164; - - architecture Structure of lut40164 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40160 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40164 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40160 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40165 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40165 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40165 : ENTITY IS TRUE; - - end lut40165; - - architecture Structure of lut40165 is - begin - INST10: ROM16X1A - generic map (initval => X"A55A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40160 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40165 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40165 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40160 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40166 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40166 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40166 : ENTITY IS TRUE; - - end lut40166; - - architecture Structure of lut40166 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40167 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40167 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40167 : ENTITY IS TRUE; - - end lut40167; - - architecture Structure of lut40167 is - begin - INST10: ROM16X1A - generic map (initval => X"9966") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40166 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40167 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40166 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40167 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40160 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40159 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40160 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40168 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40168 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40168 : ENTITY IS TRUE; - - end lut40168; - - architecture Structure of lut40168 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40165 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40168 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40165 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40168 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40169 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40169 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40169 : ENTITY IS TRUE; - - end lut40169; - - architecture Structure of lut40169 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40163 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40169 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40169 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40170 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40170 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40170 : ENTITY IS TRUE; - - end lut40170; - - architecture Structure of lut40170 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40164 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40170 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40170 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40171 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40171 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40171 : ENTITY IS TRUE; - - end lut40171; - - architecture Structure of lut40171 is - begin - INST10: ROM16X1A - generic map (initval => X"9966") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40172 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40172 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40172 : ENTITY IS TRUE; - - end lut40172; - - architecture Structure of lut40172 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40171 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40172 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40171 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40172 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40173 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40173 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40173 : ENTITY IS TRUE; - - end lut40173; - - architecture Structure of lut40173 is - begin - INST10: ROM16X1A - generic map (initval => X"A55A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40166 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40173 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40166 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40173 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40168 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_14: lut40168 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_23: lut40159 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40174 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40174 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40174 : ENTITY IS TRUE; - - end lut40174; - - architecture Structure of lut40174 is - begin - INST10: ROM16X1A - generic map (initval => X"9966") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40174 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_15: lut40174 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_22: lut40159 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40175 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40175 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40175 : ENTITY IS TRUE; - - end lut40175; - - architecture Structure of lut40175 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40163 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40175 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_18: lut40175 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_20: lut40163 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40164 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_4: lut40164 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_13: lut40164 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40176 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40176 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40176 : ENTITY IS TRUE; - - end lut40176; - - architecture Structure of lut40176 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40161 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40176 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_5: lut40161 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_12: lut40176 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40177 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40177 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40177 : ENTITY IS TRUE; - - end lut40177; - - architecture Structure of lut40177 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40178 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40178 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40178 : ENTITY IS TRUE; - - end lut40178; - - architecture Structure of lut40178 is - begin - INST10: ROM16X1A - generic map (initval => X"C33C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40177 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40178 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_8: lut40177 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_10: lut40178 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_673 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_673 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_673"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_673 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_673; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_673 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40160 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40175 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_14: lut40160 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_23: lut40175 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_674 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_674 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_674"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_674 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_674; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_674 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40161 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40166 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_15: lut40161 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_LUT4_22: lut40166 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_675 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_675 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_675"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_675 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_675; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_675 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40162 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_19: lut40162 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_21: lut40064 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40179 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40179 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40179 : ENTITY IS TRUE; - - end lut40179; - - architecture Structure of lut40179 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40180 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40180 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40180 : ENTITY IS TRUE; - - end lut40180; - - architecture Structure of lut40180 is - begin - INST10: ROM16X1A - generic map (initval => X"9966") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_676 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_676 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_676"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_676 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_676; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_676 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40179 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40180 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_18: lut40179 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_20: lut40180 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_677 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_677 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_677"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_677 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_677; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_677 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40159 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40164 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_4: lut40164 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_13: lut40159 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_678 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_678 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_678"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_678 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_678; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_678 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40161 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40176 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_5: lut40161 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_LUT4_12: lut40176 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40181 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40181 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40181 : ENTITY IS TRUE; - - end lut40181; - - architecture Structure of lut40181 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_679 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_679 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_679"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_679 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_679; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_679 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40178 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40181 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_8: lut40181 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_10: lut40178 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40182 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40182 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40182 : ENTITY IS TRUE; - - end lut40182; - - architecture Structure of lut40182 is - begin - INST10: ROM16X1A - generic map (initval => X"EE22") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_SLICE_680 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_680 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_680"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_680 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_680; - - architecture Structure of fifo_colector_inst_SLICE_680 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40043 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40182 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_in_empty_pmux_0: lut40043 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_in_empty_pmux_u: lut40182 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40183 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40183 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40183 : ENTITY IS TRUE; - - end lut40183; - - architecture Structure of lut40183 is - begin - INST10: ROM16X1A - generic map (initval => X"C000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40184 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40184 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40184 : ENTITY IS TRUE; - - end lut40184; - - architecture Structure of lut40184 is - begin - INST10: ROM16X1A - generic map (initval => X"8778") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_681 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_681 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_681"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_681 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_681; - - architecture Structure of hades_tdc_bundle_inst_SLICE_681 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40183 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40184 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_3: lut40183 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0_RNO_0: lut40184 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40185 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40185 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40185 : ENTITY IS TRUE; - - end lut40185; - - architecture Structure of lut40185 is - begin - INST10: ROM16X1A - generic map (initval => X"0030") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40186 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40186 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40186 : ENTITY IS TRUE; - - end lut40186; - - architecture Structure of lut40186 is - begin - INST10: ROM16X1A - generic map (initval => X"0200") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40185 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40186 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0: lut40185 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c: lut40186 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40187 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40187 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40187 : ENTITY IS TRUE; - - end lut40187; - - architecture Structure of lut40187 is - begin - INST10: ROM16X1A - generic map (initval => X"0005") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40188 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40188 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40188 : ENTITY IS TRUE; - - end lut40188; - - architecture Structure of lut40188 is - begin - INST10: ROM16X1A - generic map (initval => X"FF88") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_683 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_683 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_683"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_683 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_683; - - architecture Structure of hades_tdc_bundle_inst_SLICE_683 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40187 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40188 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_valid_pmux_iv_0_a2_2: lut40187 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_buf_out12: lut40188 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40189 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40189 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40189 : ENTITY IS TRUE; - - end lut40189; - - architecture Structure of lut40189 is - begin - INST10: ROM16X1A - generic map (initval => X"0001") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40189 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNIOA5C_2: lut40189 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3: lut40189 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40190 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40190 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40190 : ENTITY IS TRUE; - - end lut40190; - - architecture Structure of lut40190 is - begin - INST10: ROM16X1A - generic map (initval => X"4242") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40191 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40191 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40191 : ENTITY IS TRUE; - - end lut40191; - - architecture Structure of lut40191 is - begin - INST10: ROM16X1A - generic map (initval => X"2424") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40190 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40191 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40190 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40191 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40192 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40192 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40192 : ENTITY IS TRUE; - - end lut40192; - - architecture Structure of lut40192 is - begin - INST10: ROM16X1A - generic map (initval => X"8811") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40193 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40193 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40193 : ENTITY IS TRUE; - - end lut40193; - - architecture Structure of lut40193 is - begin - INST10: ROM16X1A - generic map (initval => X"4422") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40192 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40193 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40192 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40193 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40194 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40194 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40194 : ENTITY IS TRUE; - - end lut40194; - - architecture Structure of lut40194 is - begin - INST10: ROM16X1A - generic map (initval => X"4422") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40195 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40195 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40195 : ENTITY IS TRUE; - - end lut40195; - - architecture Structure of lut40195 is - begin - INST10: ROM16X1A - generic map (initval => X"2244") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40194 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40195 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40194 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40195 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40196 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40196 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40196 : ENTITY IS TRUE; - - end lut40196; - - architecture Structure of lut40196 is - begin - INST10: ROM16X1A - generic map (initval => X"8181") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40197 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40197 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40197 : ENTITY IS TRUE; - - end lut40197; - - architecture Structure of lut40197 is - begin - INST10: ROM16X1A - generic map (initval => X"1818") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40196 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40197 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40196 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40197 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40198 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40198 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40198 : ENTITY IS TRUE; - - end lut40198; - - architecture Structure of lut40198 is - begin - INST10: ROM16X1A - generic map (initval => X"4242") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40199 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40199 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40199 : ENTITY IS TRUE; - - end lut40199; - - architecture Structure of lut40199 is - begin - INST10: ROM16X1A - generic map (initval => X"1818") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40198 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40199 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_2: lut40198 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_3: lut40199 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40196 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40197 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_0: lut40196 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_1: lut40197 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40200 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40200 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40200 : ENTITY IS TRUE; - - end lut40200; - - architecture Structure of lut40200 is - begin - INST10: ROM16X1A - generic map (initval => X"2424") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40201 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40201 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40201 : ENTITY IS TRUE; - - end lut40201; - - architecture Structure of lut40201 is - begin - INST10: ROM16X1A - generic map (initval => X"8181") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_691 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_691 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_691"; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_691 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_691; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_691 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40200 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40201 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_1: lut40200 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_LUT4_0: lut40201 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40202 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40202 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40202 : ENTITY IS TRUE; - - end lut40202; - - architecture Structure of lut40202 is - begin - INST10: ROM16X1A - generic map (initval => X"500A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40203 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40203 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40203 : ENTITY IS TRUE; - - end lut40203; - - architecture Structure of lut40203 is - begin - INST10: ROM16X1A - generic map (initval => X"05A0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_692 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_692 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_692"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_692 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_692; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_692 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40202 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40203 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_2: lut40202 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_LUT4_3: lut40203 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, A1_ipd, D0_ipd, C0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40204 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40204 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40204 : ENTITY IS TRUE; - - end lut40204; - - architecture Structure of lut40204 is - begin - INST10: ROM16X1A - generic map (initval => X"F3FF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40205 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40205 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40205 : ENTITY IS TRUE; - - end lut40205; - - architecture Structure of lut40205 is - begin - INST10: ROM16X1A - generic map (initval => X"0400") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_693 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_693 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_693"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_693 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_693; - - architecture Structure of hades_tdc_bundle_inst_SLICE_693 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40204 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40205 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SUM1_0_0_o2_0: lut40204 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_un1_hit_i_2_0_a2: lut40205 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40206 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40206 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40206 : ENTITY IS TRUE; - - end lut40206; - - architecture Structure of lut40206 is - begin - INST10: ROM16X1A - generic map (initval => X"7F6E") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40207 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40207 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40207 : ENTITY IS TRUE; - - end lut40207; - - architecture Structure of lut40207 is - begin - INST10: ROM16X1A - generic map (initval => X"7350") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40206 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40207 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m15_i_1: lut40206 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5: lut40207 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40208 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40208 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40208 : ENTITY IS TRUE; - - end lut40208; - - architecture Structure of lut40208 is - begin - INST10: ROM16X1A - generic map (initval => X"50DC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40209 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40209 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40209 : ENTITY IS TRUE; - - end lut40209; - - architecture Structure of lut40209 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40208 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40209 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1: lut40208 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_3: lut40209 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40210 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40210 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40210 : ENTITY IS TRUE; - - end lut40210; - - architecture Structure of lut40210 is - begin - INST10: ROM16X1A - generic map (initval => X"7DFC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40211 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40211 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40211 : ENTITY IS TRUE; - - end lut40211; - - architecture Structure of lut40211 is - begin - INST10: ROM16X1A - generic map (initval => X"DD11") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40210 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40211 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1_0: lut40210 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_m3: lut40211 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40212 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40212 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40212 : ENTITY IS TRUE; - - end lut40212; - - architecture Structure of lut40212 is - begin - INST10: ROM16X1A - generic map (initval => X"965A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40213 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40213 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40213 : ENTITY IS TRUE; - - end lut40213; - - architecture Structure of lut40213 is - begin - INST10: ROM16X1A - generic map (initval => X"965A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40212 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40213 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_9_0_RNO: lut40212 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_0_RNO: lut40213 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40214 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40214 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40214 : ENTITY IS TRUE; - - end lut40214; - - architecture Structure of lut40214 is - begin - INST10: ROM16X1A - generic map (initval => X"8800") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40215 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40215 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40215 : ENTITY IS TRUE; - - end lut40215; - - architecture Structure of lut40215 is - begin - INST10: ROM16X1A - generic map (initval => X"956A") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_698 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_698 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_698"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_698 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_698; - - architecture Structure of hades_tdc_bundle_inst_SLICE_698 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40214 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40215 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_7: lut40214 - port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_9_RNO_0: lut40215 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40216 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40216 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40216 : ENTITY IS TRUE; - - end lut40216; - - architecture Structure of lut40216 is - begin - INST10: ROM16X1A - generic map (initval => X"7350") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40217 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40217 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40217 : ENTITY IS TRUE; - - end lut40217; - - architecture Structure of lut40217 is - begin - INST10: ROM16X1A - generic map (initval => X"7FFC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - component lut40216 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40217 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1: lut40216 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m15_i_3: lut40217 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - B0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40218 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40218 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40218 : ENTITY IS TRUE; - - end lut40218; - - architecture Structure of lut40218 is - begin - INST10: ROM16X1A - generic map (initval => X"7FBA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40219 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40219 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40219 : ENTITY IS TRUE; - - end lut40219; - - architecture Structure of lut40219 is - begin - INST10: ROM16X1A - generic map (initval => X"F055") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40218 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40219 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2_1_0_m11_i_1_0: lut40218 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_m3: lut40219 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40220 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40220 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40220 : ENTITY IS TRUE; - - end lut40220; - - architecture Structure of lut40220 is - begin - INST10: ROM16X1A - generic map (initval => X"CC00") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity lut40221 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40221 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40221 : ENTITY IS TRUE; - - end lut40221; - - architecture Structure of lut40221 is - begin - INST10: ROM16X1A - generic map (initval => X"A0A0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_701 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_701 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_701"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_701 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_701; - - architecture Structure of hades_tdc_bundle_inst_SLICE_701 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40220 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40221 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0: lut40220 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0: lut40221 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, C0_ipd, A0_ipd, F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40222 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40222 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40222 : ENTITY IS TRUE; - - end lut40222; - - architecture Structure of lut40222 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_702 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_702 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_702"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_702 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_702; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_702 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40063 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40222 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_17: lut40222 - port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - fifo_colector_inst_fifo40_inst_LUT4_16: lut40063 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 2 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE), - 3 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_703 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_703 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_703"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_703 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_703; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_703 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40170 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_LUT4_11: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - fifo_colector_inst_fifo40_inst_LUT4_7: lut40170 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40223 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40223 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40223 : ENTITY IS TRUE; - - end lut40223; - - architecture Structure of lut40223 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40223 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40223 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40224 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40224 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40224 : ENTITY IS TRUE; - - end lut40224; - - architecture Structure of lut40224 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40224 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40224 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40059 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40162 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40059 - port map (A=>A1_ipd, B=>GNDI, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40162 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40225 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40225 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40225 : ENTITY IS TRUE; - - end lut40225; - - architecture Structure of lut40225 is - begin - INST10: ROM16X1A - generic map (initval => X"6996") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707" - ; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40064 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40225 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40064 - port map (A=>GNDI, B=>B1_ipd, C=>GNDI, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40225 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal A1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40061 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40224 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_11: lut40061 - port map (A=>A1_ipd, B=>GNDI, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_7: lut40224 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(A1_ipd, A1, tipd_A1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => A1_ipd'last_event, - PathDelay => tpd_A1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709" - ; - - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C1_ipd : std_logic := 'X'; - signal B1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40065 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40181 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_21: lut40065 - port map (A=>GNDI, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_LUT4_17: lut40181 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(B1_ipd, B1, tipd_B1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C1_ipd, B1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, - F0_out, F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => B1_ipd'last_event, - PathDelay => tpd_B1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40226 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40226 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40226 : ENTITY IS TRUE; - - end lut40226; - - architecture Structure of lut40226 is - begin - INST10: ROM16X1A - generic map (initval => X"F000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_710 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_710 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_710"; - - tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_710 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_710; - - architecture Structure of hades_tdc_bundle_inst_SLICE_710 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D1_ipd : std_logic := 'X'; - signal C1_ipd : std_logic := 'X'; - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal F1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40046 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - component lut40226 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa_0_a2: lut40226 - port map (A=>GNDI, B=>GNDI, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - hades_tdc_bundle_inst_hit_valid_pmux_iv_0_m2: lut40046 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D1_ipd, D1, tipd_D1); - VitalWireDelay(C1_ipd, C1, tipd_C1); - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D1_ipd, C1_ipd, D0_ipd, C0_ipd, B0_ipd, F0_out, - F1_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE F1_zd : std_logic := 'X'; - VARIABLE F1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - F1_zd := F1_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, - Paths => (0 => (InputChangeTime => D1_ipd'last_event, - PathDelay => tpd_D1_F1, - PathCondition => TRUE), - 1 => (InputChangeTime => C1_ipd'last_event, - PathDelay => tpd_C1_F1, - PathCondition => TRUE)), - GlitchData => F1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40227 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40227 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40227 : ENTITY IS TRUE; - - end lut40227; - - architecture Structure of lut40227 is - begin - INST10: ROM16X1A - generic map (initval => X"0F00") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_SLICE_711"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_SLICE_711; - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40227 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_2_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40228 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40228 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40228 : ENTITY IS TRUE; - - end lut40228; - - architecture Structure of lut40228 is - begin - INST10: ROM16X1A - generic map (initval => X"5500") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40228 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40228 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40229 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40229 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40229 : ENTITY IS TRUE; - - end lut40229; - - architecture Structure of lut40229 is - begin - INST10: ROM16X1A - generic map (initval => X"FF0F") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40229 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40229 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_SLICE_714"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_SLICE_714; - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40227 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_1_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40228 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40228 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40230 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40230 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40230 : ENTITY IS TRUE; - - end lut40230; - - architecture Structure of lut40230 is - begin - INST10: ROM16X1A - generic map (initval => X"FF33") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40230 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40230 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, B0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_SLICE_717"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_SLICE_717; - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40227 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t20: lut40227 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - genblk1_0_tdc_channel_fifo_out_inst_fifo_wren: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_negedge, - SetupLow => tsetup_LSR_CLK_noedge_negedge, - HoldHigh => thold_LSR_CLK_noedge_negedge, - HoldLow => thold_LSR_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40231 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40231 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40231 : ENTITY IS TRUE; - - end lut40231; - - architecture Structure of lut40231 is - begin - INST10: ROM16X1A - generic map (initval => X"4444") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718" - ; - - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (B0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40231 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_AND2_t19: lut40231 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40232 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40232 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40232 : ENTITY IS TRUE; - - end lut40232; - - architecture Structure of lut40232 is - begin - INST10: ROM16X1A - generic map (initval => X"F5F5") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40232 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal_RNO_0: lut40232 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40233 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40233 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40233 : ENTITY IS TRUE; - - end lut40233; - - architecture Structure of lut40233 is - begin - INST10: ROM16X1A - generic map (initval => X"00F0") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_720 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_720 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_720"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_720 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_720; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_720 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40233 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_AND2_t19: lut40233 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40234 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40234 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40234 : ENTITY IS TRUE; - - end lut40234; - - architecture Structure of lut40234 is - begin - INST10: ROM16X1A - generic map (initval => X"0C0C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_SLICE_721 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_SLICE_721 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_SLICE_721"; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_SLICE_721 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_SLICE_721; - - architecture Structure of fifo_colector_inst_fifo40_inst_SLICE_721 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40234 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_AND2_t20: lut40234 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_colector_inst_SLICE_722 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_SLICE_722 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_SLICE_722"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_SLICE_722 : ENTITY IS TRUE; - - end fifo_colector_inst_SLICE_722; - - architecture Structure of fifo_colector_inst_SLICE_722 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40228 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - fifo_colector_inst_iterator_RNI7U5I_1: lut40228 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40235 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40235 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40235 : ENTITY IS TRUE; - - end lut40235; - - architecture Structure of lut40235 is - begin - INST10: ROM16X1A - generic map (initval => X"00CC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity trb_adapter_inst_SLICE_723 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_723 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_723"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_723 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_723; - - architecture Structure of trb_adapter_inst_SLICE_723 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40235 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trb_adapter_inst_LVL1_TRG_DATA_VALI_IN_rising: lut40235 - port map (A=>GNDI, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, B0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40236 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40236 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40236 : ENTITY IS TRUE; - - end lut40236; - - architecture Structure of lut40236 is - begin - INST10: ROM16X1A - generic map (initval => X"4444") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity trb_adapter_inst_SLICE_724 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trb_adapter_inst_SLICE_724 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trb_adapter_inst_SLICE_724"; - - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_LSR : VitalDelayType := 0 ns; - tpw_LSR_posedge : VitalDelayType := 0 ns; - tpw_LSR_negedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF trb_adapter_inst_SLICE_724 : ENTITY IS TRUE; - - end trb_adapter_inst_SLICE_724; - - architecture Structure of trb_adapter_inst_SLICE_724 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre0026 - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40236 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trb_adapter_inst_release_out: lut40236 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - trb_adapter_inst_finished: svmuxregsre0026 - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>LSR_dly, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (B0_ipd, A0_ipd, M0_dly, LSR_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_LSR : x01 := '0'; - VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => LSR_ipd, - TestSignalName => "LSR", - Period => tperiod_LSR, - PulseWidthHigh => tpw_LSR_posedge, - PulseWidthLow => tpw_LSR_negedge, - PeriodData => periodcheckinfo_LSR, - Violation => tviol_LSR_LSR, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40237 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40237 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40237 : ENTITY IS TRUE; - - end lut40237; - - architecture Structure of lut40237 is - begin - INST10: ROM16X1A - generic map (initval => X"5000") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40237 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_RNI97O31: lut40237 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, - Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40229 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_RNIT1GT_7: lut40229 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40238 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40238 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40238 : ENTITY IS TRUE; - - end lut40238; - - architecture Structure of lut40238 is - begin - INST10: ROM16X1A - generic map (initval => X"5D0C") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40238 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0: lut40238 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40239 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40239 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40239 : ENTITY IS TRUE; - - end lut40239; - - architecture Structure of lut40239 is - begin - INST10: ROM16X1A - generic map (initval => X"0ACE") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40239 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i_0: lut40239 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40240 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40240 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40240 : ENTITY IS TRUE; - - end lut40240; - - architecture Structure of lut40240 is - begin - INST10: ROM16X1A - generic map (initval => X"AF05") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 : ENTITY IS TRUE; - - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40240 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2_1_0_m11_i_m3: lut40240 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40241 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40241 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40241 : ENTITY IS TRUE; - - end lut40241; - - architecture Structure of lut40241 is - begin - INST10: ROM16X1A - generic map (initval => X"CFCF") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40241 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_RNIB4EQ_7: lut40241 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40227 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_RNI8UMR: lut40227 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40242 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40242 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40242 : ENTITY IS TRUE; - - end lut40242; - - architecture Structure of lut40242 is - begin - INST10: ROM16X1A - generic map (initval => X"50DC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - - - -- entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - - entity hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732; - - - architecture Structure of hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40242 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40242 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40243 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40243 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40243 : ENTITY IS TRUE; - - end lut40243; - - architecture Structure of lut40243 is - begin - INST10: ROM16X1A - generic map (initval => X"EFCC") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40243 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast_RNI999V: lut40243 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40244 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40244 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40244 : ENTITY IS TRUE; - - end lut40244; - - architecture Structure of lut40244 is - begin - INST10: ROM16X1A - generic map (initval => X"F3F3") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734" - ; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40244 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_RNI3HPF_7: lut40244 - port map (A=>GNDI, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, B0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40238 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: lut40238 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40245 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40245 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40245 : ENTITY IS TRUE; - - end lut40245; - - architecture Structure of lut40245 is - begin - INST10: ROM16X1A - generic map (initval => X"AEAA") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns; - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - signal CLK_NOTIN: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component inverter - port (I: in Std_logic; Z: out Std_logic); - end component; - component lut40245 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast_RNI5DQ71: lut40245 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_fast: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - CLK_INVERTERIN: inverter - port map (I=>CLK_dly, Z=>CLK_NOTIN); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, M0_dly, CLK_dly, - F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_negedge, - SetupLow => tsetup_M0_CLK_noedge_negedge, - HoldHigh => thold_M0_CLK_noedge_negedge, - HoldLow => thold_M0_CLK_noedge_negedge, - CheckEnabled => TRUE, - RefTransition => '\', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40188 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2: lut40188 - port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40115 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2: lut40115 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40246 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40246 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40246 : ENTITY IS TRUE; - - end lut40246; - - architecture Structure of lut40246 is - begin - INST10: ROM16X1A - generic map (initval => X"0001") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739" - ; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739; - - - architecture Structure of hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal B0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - component lut40246 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_RNICU4C_3: lut40246 - port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(B0_ipd, B0, tipd_B0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 2 => (InputChangeTime => B0_ipd'last_event, - PathDelay => tpd_B0_F0, - PathCondition => TRUE), - 3 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_740 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_740 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_740"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_M0_CLK : VitalDelayType := 0 ns; - tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_740 : ENTITY IS TRUE; - - end SLICE_740; - - architecture Structure of SLICE_740 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal C0_ipd : std_logic := 'X'; - signal M0_ipd : std_logic := 'X'; - signal M0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - signal Q0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component svmuxregsre - port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; - SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; - Q: out Std_logic); - end component; - component lut40233 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa_0_a2: lut40233 - port map (A=>GNDI, B=>GNDI, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - reset_dl_2: svmuxregsre - port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, - LSR=>GNDI, Q=>Q0_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(M0_ipd, M0, tipd_M0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, C0_ipd, M0_dly, CLK_dly, F0_out, Q0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - VARIABLE Q0_zd : std_logic := 'X'; - VARIABLE Q0_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_M0_CLK : x01 := '0'; - VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => M0_dly, - TestSignalName => "M0", - TestDelay => tisd_M0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_M0_CLK_noedge_posedge, - SetupLow => tsetup_M0_CLK_noedge_posedge, - HoldHigh => thold_M0_CLK_noedge_posedge, - HoldLow => thold_M0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => M0_CLK_TimingDatash, - Violation => tviol_M0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - F0_zd := F0_out; - Q0_zd := Q0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_Q0, - PathCondition => TRUE)), - GlitchData => Q0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40247 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40247 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40247 : ENTITY IS TRUE; - - end lut40247; - - architecture Structure of lut40247 is - begin - INST10: ROM16X1A - generic map (initval => X"0505") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity hades_tdc_bundle_inst_SLICE_741 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_tdc_bundle_inst_SLICE_741 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_tdc_bundle_inst_SLICE_741"; - - tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_tdc_bundle_inst_SLICE_741 : ENTITY IS TRUE; - - end hades_tdc_bundle_inst_SLICE_741; - - architecture Structure of hades_tdc_bundle_inst_SLICE_741 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal C0_ipd : std_logic := 'X'; - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40247 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0: lut40247 - port map (A=>A0_ipd, B=>GNDI, C=>C0_ipd, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(C0_ipd, C0, tipd_C0); - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (C0_ipd, A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => C0_ipd'last_event, - PathDelay => tpd_C0_F0, - PathCondition => TRUE), - 1 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity pll0inst_SLICE_742 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity pll0inst_SLICE_742 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "pll0inst_SLICE_742"); - - port (F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF pll0inst_SLICE_742 : ENTITY IS TRUE; - - end pll0inst_SLICE_742; - - architecture Structure of pll0inst_SLICE_742 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40093 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - pll0inst_GND: lut40093 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (F0_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0 <= F0_out; - - - END PROCESS; - - end Structure; - --- entity SLICE_743 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_743 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_743"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_743 : ENTITY IS TRUE; - - end SLICE_743; - - architecture Structure of SLICE_743 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40081 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_lvl1_pad_RNINMH5: lut40081 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_744 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_744 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_744"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_744 : ENTITY IS TRUE; - - end SLICE_744; - - architecture Structure of SLICE_744 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40081 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trig_pad_RNII4FF_0: lut40081 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_745 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_745 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_745"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_745 : ENTITY IS TRUE; - - end SLICE_745; - - architecture Structure of SLICE_745 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40081 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trig_pad_RNIJ5FF_1: lut40081 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity SLICE_746 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_746 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_746"; - - tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (D0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_746 : ENTITY IS TRUE; - - end SLICE_746; - - architecture Structure of SLICE_746 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal D0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40081 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - trig_pad_RNIK6FF_2: lut40081 - port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>D0_ipd, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(D0_ipd, D0, tipd_D0); - END BLOCK; - - VitalBehavior : PROCESS (D0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => D0_ipd'last_event, - PathDelay => tpd_D0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity lut40248 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity lut40248 is - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - - ATTRIBUTE Vital_Level0 OF lut40248 : ENTITY IS TRUE; - - end lut40248; - - architecture Structure of lut40248 is - begin - INST10: ROM16X1A - generic map (initval => X"5555") - port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); - end Structure; - --- entity SLICE_747 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity SLICE_747 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "SLICE_747"; - - tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (A0: in Std_logic; F0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF SLICE_747 : ENTITY IS TRUE; - - end SLICE_747; - - architecture Structure of SLICE_747 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal A0_ipd : std_logic := 'X'; - signal F0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component lut40248 - port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; - Z: out Std_logic); - end component; - begin - hades_trig_pad_RNIE1B4: lut40248 - port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(A0_ipd, A0, tipd_A0); - END BLOCK; - - VitalBehavior : PROCESS (A0_ipd, F0_out) - VARIABLE F0_zd : std_logic := 'X'; - VARIABLE F0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - F0_zd := F0_out; - - VitalPathDelay01 ( - OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, - Paths => (0 => (InputChangeTime => A0_ipd'last_event, - PathDelay => tpd_A0_F0, - PathCondition => TRUE)), - GlitchData => F0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity sapiobuf - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity sapiobuf is - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - - ATTRIBUTE Vital_Level0 OF sapiobuf : ENTITY IS TRUE; - - end sapiobuf; - - architecture Structure of sapiobuf is - begin - INST5: OBZ - port map (I=>I, T=>T, O=>PAD); - end Structure; - --- entity hades_raw_valid_vect_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_raw_valid_vect_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_raw_valid_vect_0_B"); - - port (hadesrawvalidvect0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_raw_valid_vect_0_B : ENTITY IS TRUE; - - end hades_raw_valid_vect_0_B; - - architecture Structure of hades_raw_valid_vect_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesrawvalidvect0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component sapiobuf - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_raw_valid_vect_pad_0: sapiobuf - port map (I=>GNDI, T=>VCCI, PAD=>hadesrawvalidvect0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesrawvalidvect0_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesrawvalidvect0 <= hadesrawvalidvect0_out; - - - END PROCESS; - - end Structure; - --- entity sapiobuf0249 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity sapiobuf0249 is - port (I: in Std_logic; PAD: out Std_logic); - - ATTRIBUTE Vital_Level0 OF sapiobuf0249 : ENTITY IS TRUE; - - end sapiobuf0249; - - architecture Structure of sapiobuf0249 is - begin - INST5: OB - port map (I=>I, O=>PAD); - end Structure; - --- entity fifo_data_out_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_0_B : ENTITY IS TRUE; - - end fifo_data_out_0_B; - - architecture Structure of fifo_data_out_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout0_out) - VARIABLE fifodataout0_zd : std_logic := 'X'; - VARIABLE fifodataout0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout0_zd := fifodataout0_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout0, OutSignalName => "fifodataout0", OutTemp => fifodataout0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout0, - PathCondition => TRUE)), - GlitchData => fifodataout0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity sapiobuf0250 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity sapiobuf0250 is - port (Z: out Std_logic; PAD: in Std_logic); - - ATTRIBUTE Vital_Level0 OF sapiobuf0250 : ENTITY IS TRUE; - - end sapiobuf0250; - - architecture Structure of sapiobuf0250 is - begin - INST1: IB - port map (I=>PAD, O=>Z); - end Structure; - --- entity clkB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity clkB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "clkB"; - - tipd_clkS : VitalDelayType01 := (0 ns, 0 ns); - tpd_clkS_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_clkS : VitalDelayType := 0 ns; - tpw_clkS_posedge : VitalDelayType := 0 ns; - tpw_clkS_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; clkS: in Std_logic); - - ATTRIBUTE Vital_Level0 OF clkB : ENTITY IS TRUE; - - end clkB; - - architecture Structure of clkB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal clkS_ipd : std_logic := 'X'; - - component sapiobuf0250 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - clk_pad: sapiobuf0250 - port map (Z=>PADDI_out, PAD=>clkS_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(clkS_ipd, clkS, tipd_clkS); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, clkS_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_clkS_clkS : x01 := '0'; - VARIABLE periodcheckinfo_clkS : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => clkS_ipd, - TestSignalName => "clkS", - Period => tperiod_clkS, - PulseWidthHigh => tpw_clkS_posedge, - PulseWidthLow => tpw_clkS_negedge, - PeriodData => periodcheckinfo_clkS, - Violation => tviol_clkS_clkS, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => clkS_ipd'last_event, - PathDelay => tpd_clkS_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_validB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_validB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_validB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufvalid : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufvalid: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_validB : ENTITY IS TRUE; - - end hades_drop_cmp_buf_validB; - - architecture Structure of hades_drop_cmp_buf_validB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufvalid_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_valid_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufvalid_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufvalid_out) - VARIABLE hadesdropcmpbufvalid_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufvalid_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufvalid_zd := hadesdropcmpbufvalid_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufvalid, OutSignalName => "hadesdropcmpbufvalid", OutTemp => hadesdropcmpbufvalid_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufvalid, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufvalid_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_11_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_11_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_11_B"); - - port (hadesdropcmpbufcoarse11: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_11_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_11_B; - - architecture Structure of hades_drop_cmp_buf_coarse_11_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdropcmpbufcoarse11_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_11: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdropcmpbufcoarse11_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdropcmpbufcoarse11_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse11 <= hadesdropcmpbufcoarse11_out; - - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_10_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_10_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_10_B"); - - port (hadesdropcmpbufcoarse10: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_10_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_10_B; - - architecture Structure of hades_drop_cmp_buf_coarse_10_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdropcmpbufcoarse10_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_10: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdropcmpbufcoarse10_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdropcmpbufcoarse10_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse10 <= hadesdropcmpbufcoarse10_out; - - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_9_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_9_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_9_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse9 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse9: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_9_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_9_B; - - architecture Structure of hades_drop_cmp_buf_coarse_9_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse9_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_9: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse9_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse9_out) - VARIABLE hadesdropcmpbufcoarse9_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse9_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse9_zd := hadesdropcmpbufcoarse9_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse9, OutSignalName => "hadesdropcmpbufcoarse9", OutTemp => hadesdropcmpbufcoarse9_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse9, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse9_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_8_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_8_B; - - architecture Structure of hades_drop_cmp_buf_coarse_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse8_out) - VARIABLE hadesdropcmpbufcoarse8_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse8_zd := hadesdropcmpbufcoarse8_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse8, OutSignalName => "hadesdropcmpbufcoarse8", OutTemp => hadesdropcmpbufcoarse8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse8, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_7_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_7_B; - - architecture Structure of hades_drop_cmp_buf_coarse_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse7_out) - VARIABLE hadesdropcmpbufcoarse7_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse7_zd := hadesdropcmpbufcoarse7_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse7, OutSignalName => "hadesdropcmpbufcoarse7", OutTemp => hadesdropcmpbufcoarse7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse7, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_6_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_6_B; - - architecture Structure of hades_drop_cmp_buf_coarse_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse6_out) - VARIABLE hadesdropcmpbufcoarse6_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse6_zd := hadesdropcmpbufcoarse6_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse6, OutSignalName => "hadesdropcmpbufcoarse6", OutTemp => hadesdropcmpbufcoarse6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse6, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_5_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_5_B; - - architecture Structure of hades_drop_cmp_buf_coarse_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse5_out) - VARIABLE hadesdropcmpbufcoarse5_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse5_zd := hadesdropcmpbufcoarse5_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse5, OutSignalName => "hadesdropcmpbufcoarse5", OutTemp => hadesdropcmpbufcoarse5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse5, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_4_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_4_B; - - architecture Structure of hades_drop_cmp_buf_coarse_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse4_out) - VARIABLE hadesdropcmpbufcoarse4_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse4_zd := hadesdropcmpbufcoarse4_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse4, OutSignalName => "hadesdropcmpbufcoarse4", OutTemp => hadesdropcmpbufcoarse4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse4, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_3_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_3_B; - - architecture Structure of hades_drop_cmp_buf_coarse_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse3_out) - VARIABLE hadesdropcmpbufcoarse3_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse3_zd := hadesdropcmpbufcoarse3_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse3, OutSignalName => "hadesdropcmpbufcoarse3", OutTemp => hadesdropcmpbufcoarse3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse3, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_2_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_2_B; - - architecture Structure of hades_drop_cmp_buf_coarse_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse2_out) - VARIABLE hadesdropcmpbufcoarse2_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse2_zd := hadesdropcmpbufcoarse2_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse2, OutSignalName => "hadesdropcmpbufcoarse2", OutTemp => hadesdropcmpbufcoarse2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse2, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_1_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_1_B; - - architecture Structure of hades_drop_cmp_buf_coarse_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse1_out) - VARIABLE hadesdropcmpbufcoarse1_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse1_zd := hadesdropcmpbufcoarse1_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse1, OutSignalName => "hadesdropcmpbufcoarse1", OutTemp => hadesdropcmpbufcoarse1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse1, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_coarse_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_coarse_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_coarse_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbufcoarse0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbufcoarse0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_coarse_0_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_coarse_0_B; - - architecture Structure of hades_drop_cmp_buf_coarse_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbufcoarse0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_coarse_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbufcoarse0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbufcoarse0_out) - VARIABLE hadesdropcmpbufcoarse0_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbufcoarse0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbufcoarse0_zd := hadesdropcmpbufcoarse0_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbufcoarse0, OutSignalName => "hadesdropcmpbufcoarse0", OutTemp => hadesdropcmpbufcoarse0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbufcoarse0, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbufcoarse0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_11_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_11_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_11_B"); - - port (hadesdropcmpbuf11: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_11_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_11_B; - - architecture Structure of hades_drop_cmp_buf_11_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdropcmpbuf11_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_11: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdropcmpbuf11_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdropcmpbuf11_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf11 <= hadesdropcmpbuf11_out; - - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_10_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_10_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_10_B"); - - port (hadesdropcmpbuf10: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_10_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_10_B; - - architecture Structure of hades_drop_cmp_buf_10_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdropcmpbuf10_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_10: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdropcmpbuf10_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdropcmpbuf10_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf10 <= hadesdropcmpbuf10_out; - - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_9_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_9_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_9_B"); - - port (hadesdropcmpbuf9: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_9_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_9_B; - - architecture Structure of hades_drop_cmp_buf_9_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdropcmpbuf9_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_9: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdropcmpbuf9_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdropcmpbuf9_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf9 <= hadesdropcmpbuf9_out; - - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_8_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_8_B; - - architecture Structure of hades_drop_cmp_buf_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf8_out) - VARIABLE hadesdropcmpbuf8_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf8_zd := hadesdropcmpbuf8_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf8, OutSignalName => "hadesdropcmpbuf8", OutTemp => hadesdropcmpbuf8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf8, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_7_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_7_B; - - architecture Structure of hades_drop_cmp_buf_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf7_out) - VARIABLE hadesdropcmpbuf7_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf7_zd := hadesdropcmpbuf7_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf7, OutSignalName => "hadesdropcmpbuf7", OutTemp => hadesdropcmpbuf7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf7, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_6_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_6_B; - - architecture Structure of hades_drop_cmp_buf_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf6_out) - VARIABLE hadesdropcmpbuf6_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf6_zd := hadesdropcmpbuf6_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf6, OutSignalName => "hadesdropcmpbuf6", OutTemp => hadesdropcmpbuf6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf6, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_5_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_5_B; - - architecture Structure of hades_drop_cmp_buf_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf5_out) - VARIABLE hadesdropcmpbuf5_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf5_zd := hadesdropcmpbuf5_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf5, OutSignalName => "hadesdropcmpbuf5", OutTemp => hadesdropcmpbuf5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf5, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_4_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_4_B; - - architecture Structure of hades_drop_cmp_buf_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf4_out) - VARIABLE hadesdropcmpbuf4_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf4_zd := hadesdropcmpbuf4_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf4, OutSignalName => "hadesdropcmpbuf4", OutTemp => hadesdropcmpbuf4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf4, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_3_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_3_B; - - architecture Structure of hades_drop_cmp_buf_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf3_out) - VARIABLE hadesdropcmpbuf3_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf3_zd := hadesdropcmpbuf3_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf3, OutSignalName => "hadesdropcmpbuf3", OutTemp => hadesdropcmpbuf3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf3, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_2_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_2_B; - - architecture Structure of hades_drop_cmp_buf_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf2_out) - VARIABLE hadesdropcmpbuf2_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf2_zd := hadesdropcmpbuf2_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf2, OutSignalName => "hadesdropcmpbuf2", OutTemp => hadesdropcmpbuf2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf2, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_1_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_1_B; - - architecture Structure of hades_drop_cmp_buf_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf1_out) - VARIABLE hadesdropcmpbuf1_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf1_zd := hadesdropcmpbuf1_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf1, OutSignalName => "hadesdropcmpbuf1", OutTemp => hadesdropcmpbuf1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf1, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_drop_cmp_buf_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_drop_cmp_buf_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_drop_cmp_buf_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdropcmpbuf0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdropcmpbuf0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_drop_cmp_buf_0_B : ENTITY IS TRUE; - - end hades_drop_cmp_buf_0_B; - - architecture Structure of hades_drop_cmp_buf_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdropcmpbuf0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_drop_cmp_buf_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdropcmpbuf0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdropcmpbuf0_out) - VARIABLE hadesdropcmpbuf0_zd : std_logic := 'X'; - VARIABLE hadesdropcmpbuf0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdropcmpbuf0_zd := hadesdropcmpbuf0_out; - - VitalPathDelay01 ( - - OutSignal => hadesdropcmpbuf0, OutSignalName => "hadesdropcmpbuf0", OutTemp => hadesdropcmpbuf0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdropcmpbuf0, - PathCondition => TRUE)), - GlitchData => hadesdropcmpbuf0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_8_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_8_B; - - architecture Structure of hades_dbg2_coarse_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse8_out) - VARIABLE hadesdbg2coarse8_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse8_zd := hadesdbg2coarse8_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse8, OutSignalName => "hadesdbg2coarse8", OutTemp => hadesdbg2coarse8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse8, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_7_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_7_B; - - architecture Structure of hades_dbg2_coarse_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse7_out) - VARIABLE hadesdbg2coarse7_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse7_zd := hadesdbg2coarse7_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse7, OutSignalName => "hadesdbg2coarse7", OutTemp => hadesdbg2coarse7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse7, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_6_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_6_B; - - architecture Structure of hades_dbg2_coarse_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse6_out) - VARIABLE hadesdbg2coarse6_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse6_zd := hadesdbg2coarse6_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse6, OutSignalName => "hadesdbg2coarse6", OutTemp => hadesdbg2coarse6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse6, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_5_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_5_B; - - architecture Structure of hades_dbg2_coarse_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse5_out) - VARIABLE hadesdbg2coarse5_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse5_zd := hadesdbg2coarse5_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse5, OutSignalName => "hadesdbg2coarse5", OutTemp => hadesdbg2coarse5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse5, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_4_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_4_B; - - architecture Structure of hades_dbg2_coarse_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse4_out) - VARIABLE hadesdbg2coarse4_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse4_zd := hadesdbg2coarse4_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse4, OutSignalName => "hadesdbg2coarse4", OutTemp => hadesdbg2coarse4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse4, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_3_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_3_B; - - architecture Structure of hades_dbg2_coarse_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse3_out) - VARIABLE hadesdbg2coarse3_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse3_zd := hadesdbg2coarse3_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse3, OutSignalName => "hadesdbg2coarse3", OutTemp => hadesdbg2coarse3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse3, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_2_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_2_B; - - architecture Structure of hades_dbg2_coarse_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse2_out) - VARIABLE hadesdbg2coarse2_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse2_zd := hadesdbg2coarse2_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse2, OutSignalName => "hadesdbg2coarse2", OutTemp => hadesdbg2coarse2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse2, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_1_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_1_B; - - architecture Structure of hades_dbg2_coarse_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse1_out) - VARIABLE hadesdbg2coarse1_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse1_zd := hadesdbg2coarse1_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse1, OutSignalName => "hadesdbg2coarse1", OutTemp => hadesdbg2coarse1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse1, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_coarse_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_coarse_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_coarse_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2coarse0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2coarse0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_coarse_0_B : ENTITY IS TRUE; - - end hades_dbg2_coarse_0_B; - - architecture Structure of hades_dbg2_coarse_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2coarse0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_coarse_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2coarse0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2coarse0_out) - VARIABLE hadesdbg2coarse0_zd : std_logic := 'X'; - VARIABLE hadesdbg2coarse0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2coarse0_zd := hadesdbg2coarse0_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2coarse0, OutSignalName => "hadesdbg2coarse0", OutTemp => hadesdbg2coarse0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2coarse0, - PathCondition => TRUE)), - GlitchData => hadesdbg2coarse0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_31_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_31_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_31_B"); - - port (hadesdbg2out31: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_31_B : ENTITY IS TRUE; - - end hades_dbg2_out_31_B; - - architecture Structure of hades_dbg2_out_31_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out31_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_31: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out31_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out31_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out31 <= hadesdbg2out31_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_30_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_30_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_30_B"); - - port (hadesdbg2out30: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_30_B : ENTITY IS TRUE; - - end hades_dbg2_out_30_B; - - architecture Structure of hades_dbg2_out_30_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out30_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_30: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out30_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out30_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out30 <= hadesdbg2out30_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_29_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_29_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_29_B"); - - port (hadesdbg2out29: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_29_B : ENTITY IS TRUE; - - end hades_dbg2_out_29_B; - - architecture Structure of hades_dbg2_out_29_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out29_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_29: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out29_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out29_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out29 <= hadesdbg2out29_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_28_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_28_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_28_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out28 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out28: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_28_B : ENTITY IS TRUE; - - end hades_dbg2_out_28_B; - - architecture Structure of hades_dbg2_out_28_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out28_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_28: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out28_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out28_out) - VARIABLE hadesdbg2out28_zd : std_logic := 'X'; - VARIABLE hadesdbg2out28_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out28_zd := hadesdbg2out28_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out28, OutSignalName => "hadesdbg2out28", OutTemp => hadesdbg2out28_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out28, - PathCondition => TRUE)), - GlitchData => hadesdbg2out28_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity mfflsre - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity mfflsre is - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF mfflsre : ENTITY IS TRUE; - - end mfflsre; - - architecture Structure of mfflsre is - begin - INST01: FD1P3DX - generic map (GSR => "DISABLED") - port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); - end Structure; - --- entity hades_dbg2_out_28_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_28_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_28_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_28_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_28_MGIOL; - - architecture Structure of hades_dbg2_out_28_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_23: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_27_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_27_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_27_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out27 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out27: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_27_B : ENTITY IS TRUE; - - end hades_dbg2_out_27_B; - - architecture Structure of hades_dbg2_out_27_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out27_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_27: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out27_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out27_out) - VARIABLE hadesdbg2out27_zd : std_logic := 'X'; - VARIABLE hadesdbg2out27_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out27_zd := hadesdbg2out27_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out27, OutSignalName => "hadesdbg2out27", OutTemp => hadesdbg2out27_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out27, - PathCondition => TRUE)), - GlitchData => hadesdbg2out27_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_27_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_27_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_27_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_27_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_27_MGIOL; - - architecture Structure of hades_dbg2_out_27_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_22: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_26_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_26_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_26_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out26 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out26: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_26_B : ENTITY IS TRUE; - - end hades_dbg2_out_26_B; - - architecture Structure of hades_dbg2_out_26_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out26_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_26: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out26_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out26_out) - VARIABLE hadesdbg2out26_zd : std_logic := 'X'; - VARIABLE hadesdbg2out26_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out26_zd := hadesdbg2out26_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out26, OutSignalName => "hadesdbg2out26", OutTemp => hadesdbg2out26_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out26, - PathCondition => TRUE)), - GlitchData => hadesdbg2out26_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_26_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_26_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_26_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_26_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_26_MGIOL; - - architecture Structure of hades_dbg2_out_26_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_21: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_25_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_25_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_25_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out25 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out25: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_25_B : ENTITY IS TRUE; - - end hades_dbg2_out_25_B; - - architecture Structure of hades_dbg2_out_25_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out25_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_25: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out25_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out25_out) - VARIABLE hadesdbg2out25_zd : std_logic := 'X'; - VARIABLE hadesdbg2out25_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out25_zd := hadesdbg2out25_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out25, OutSignalName => "hadesdbg2out25", OutTemp => hadesdbg2out25_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out25, - PathCondition => TRUE)), - GlitchData => hadesdbg2out25_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_25_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_25_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_25_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_25_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_25_MGIOL; - - architecture Structure of hades_dbg2_out_25_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_20: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_24_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_24_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_24_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out24 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out24: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_24_B : ENTITY IS TRUE; - - end hades_dbg2_out_24_B; - - architecture Structure of hades_dbg2_out_24_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out24_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_24: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out24_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out24_out) - VARIABLE hadesdbg2out24_zd : std_logic := 'X'; - VARIABLE hadesdbg2out24_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out24_zd := hadesdbg2out24_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out24, OutSignalName => "hadesdbg2out24", OutTemp => hadesdbg2out24_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out24, - PathCondition => TRUE)), - GlitchData => hadesdbg2out24_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_24_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_24_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_24_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_24_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_24_MGIOL; - - architecture Structure of hades_dbg2_out_24_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_19: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_23_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_23_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_23_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out23 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out23: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_23_B : ENTITY IS TRUE; - - end hades_dbg2_out_23_B; - - architecture Structure of hades_dbg2_out_23_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out23_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_23: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out23_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out23_out) - VARIABLE hadesdbg2out23_zd : std_logic := 'X'; - VARIABLE hadesdbg2out23_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out23_zd := hadesdbg2out23_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out23, OutSignalName => "hadesdbg2out23", OutTemp => hadesdbg2out23_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out23, - PathCondition => TRUE)), - GlitchData => hadesdbg2out23_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_23_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_23_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_23_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_23_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_23_MGIOL; - - architecture Structure of hades_dbg2_out_23_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_18: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_22_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_22_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_22_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out22 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out22: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_22_B : ENTITY IS TRUE; - - end hades_dbg2_out_22_B; - - architecture Structure of hades_dbg2_out_22_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out22_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_22: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out22_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out22_out) - VARIABLE hadesdbg2out22_zd : std_logic := 'X'; - VARIABLE hadesdbg2out22_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out22_zd := hadesdbg2out22_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out22, OutSignalName => "hadesdbg2out22", OutTemp => hadesdbg2out22_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out22, - PathCondition => TRUE)), - GlitchData => hadesdbg2out22_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_22_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_22_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_22_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_22_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_22_MGIOL; - - architecture Structure of hades_dbg2_out_22_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_17: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_21_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_21_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_21_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out21 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out21: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_21_B : ENTITY IS TRUE; - - end hades_dbg2_out_21_B; - - architecture Structure of hades_dbg2_out_21_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out21_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_21: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out21_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out21_out) - VARIABLE hadesdbg2out21_zd : std_logic := 'X'; - VARIABLE hadesdbg2out21_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out21_zd := hadesdbg2out21_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out21, OutSignalName => "hadesdbg2out21", OutTemp => hadesdbg2out21_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out21, - PathCondition => TRUE)), - GlitchData => hadesdbg2out21_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_21_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_21_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_21_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_21_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_21_MGIOL; - - architecture Structure of hades_dbg2_out_21_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_16: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_20_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_20_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_20_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out20 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out20: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_20_B : ENTITY IS TRUE; - - end hades_dbg2_out_20_B; - - architecture Structure of hades_dbg2_out_20_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out20_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_20: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out20_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out20_out) - VARIABLE hadesdbg2out20_zd : std_logic := 'X'; - VARIABLE hadesdbg2out20_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out20_zd := hadesdbg2out20_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out20, OutSignalName => "hadesdbg2out20", OutTemp => hadesdbg2out20_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out20, - PathCondition => TRUE)), - GlitchData => hadesdbg2out20_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_20_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_20_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_20_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_20_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_20_MGIOL; - - architecture Structure of hades_dbg2_out_20_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_15: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_19_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_19_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_19_B"); - - port (hadesdbg2out19: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_19_B : ENTITY IS TRUE; - - end hades_dbg2_out_19_B; - - architecture Structure of hades_dbg2_out_19_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out19_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_19: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out19_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out19_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out19 <= hadesdbg2out19_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_18_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_18_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_18_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out18 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out18: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_18_B : ENTITY IS TRUE; - - end hades_dbg2_out_18_B; - - architecture Structure of hades_dbg2_out_18_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out18_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_18: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out18_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out18_out) - VARIABLE hadesdbg2out18_zd : std_logic := 'X'; - VARIABLE hadesdbg2out18_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out18_zd := hadesdbg2out18_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out18, OutSignalName => "hadesdbg2out18", OutTemp => hadesdbg2out18_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out18, - PathCondition => TRUE)), - GlitchData => hadesdbg2out18_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_18_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_18_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_18_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_18_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_18_MGIOL; - - architecture Structure of hades_dbg2_out_18_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_14: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_17_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_17_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_17_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out17 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out17: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_17_B : ENTITY IS TRUE; - - end hades_dbg2_out_17_B; - - architecture Structure of hades_dbg2_out_17_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out17_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_17: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out17_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out17_out) - VARIABLE hadesdbg2out17_zd : std_logic := 'X'; - VARIABLE hadesdbg2out17_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out17_zd := hadesdbg2out17_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out17, OutSignalName => "hadesdbg2out17", OutTemp => hadesdbg2out17_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out17, - PathCondition => TRUE)), - GlitchData => hadesdbg2out17_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_17_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_17_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_17_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_17_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_17_MGIOL; - - architecture Structure of hades_dbg2_out_17_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_13: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_16_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_16_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_16_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out16 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out16: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_16_B : ENTITY IS TRUE; - - end hades_dbg2_out_16_B; - - architecture Structure of hades_dbg2_out_16_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out16_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_16: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out16_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out16_out) - VARIABLE hadesdbg2out16_zd : std_logic := 'X'; - VARIABLE hadesdbg2out16_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out16_zd := hadesdbg2out16_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out16, OutSignalName => "hadesdbg2out16", OutTemp => hadesdbg2out16_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out16, - PathCondition => TRUE)), - GlitchData => hadesdbg2out16_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_16_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_16_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_16_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_16_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_16_MGIOL; - - architecture Structure of hades_dbg2_out_16_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_12: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_15_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_15_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_15_B"); - - port (hadesdbg2out15: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_15_B : ENTITY IS TRUE; - - end hades_dbg2_out_15_B; - - architecture Structure of hades_dbg2_out_15_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out15_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_15: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out15_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out15_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out15 <= hadesdbg2out15_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_14_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_14_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_14_B"); - - port (hadesdbg2out14: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_14_B : ENTITY IS TRUE; - - end hades_dbg2_out_14_B; - - architecture Structure of hades_dbg2_out_14_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out14_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_14: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out14_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out14_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out14 <= hadesdbg2out14_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_13_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_13_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_13_B"); - - port (hadesdbg2out13: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_13_B : ENTITY IS TRUE; - - end hades_dbg2_out_13_B; - - architecture Structure of hades_dbg2_out_13_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out13_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_13: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out13_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out13_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out13 <= hadesdbg2out13_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_12_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_12_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_12_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out12 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out12: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_12_B : ENTITY IS TRUE; - - end hades_dbg2_out_12_B; - - architecture Structure of hades_dbg2_out_12_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out12_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_12: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out12_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out12_out) - VARIABLE hadesdbg2out12_zd : std_logic := 'X'; - VARIABLE hadesdbg2out12_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out12_zd := hadesdbg2out12_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out12, OutSignalName => "hadesdbg2out12", OutTemp => hadesdbg2out12_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out12, - PathCondition => TRUE)), - GlitchData => hadesdbg2out12_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_11_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_11_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_11_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out11 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out11: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_11_B : ENTITY IS TRUE; - - end hades_dbg2_out_11_B; - - architecture Structure of hades_dbg2_out_11_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out11_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_11: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out11_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out11_out) - VARIABLE hadesdbg2out11_zd : std_logic := 'X'; - VARIABLE hadesdbg2out11_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out11_zd := hadesdbg2out11_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out11, OutSignalName => "hadesdbg2out11", OutTemp => hadesdbg2out11_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out11, - PathCondition => TRUE)), - GlitchData => hadesdbg2out11_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_10_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_10_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_10_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out10 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out10: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_10_B : ENTITY IS TRUE; - - end hades_dbg2_out_10_B; - - architecture Structure of hades_dbg2_out_10_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out10_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_10: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out10_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out10_out) - VARIABLE hadesdbg2out10_zd : std_logic := 'X'; - VARIABLE hadesdbg2out10_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out10_zd := hadesdbg2out10_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out10, OutSignalName => "hadesdbg2out10", OutTemp => hadesdbg2out10_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out10, - PathCondition => TRUE)), - GlitchData => hadesdbg2out10_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_9_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_9_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_9_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out9 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out9: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_9_B : ENTITY IS TRUE; - - end hades_dbg2_out_9_B; - - architecture Structure of hades_dbg2_out_9_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out9_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_9: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out9_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out9_out) - VARIABLE hadesdbg2out9_zd : std_logic := 'X'; - VARIABLE hadesdbg2out9_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out9_zd := hadesdbg2out9_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out9, OutSignalName => "hadesdbg2out9", OutTemp => hadesdbg2out9_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out9, - PathCondition => TRUE)), - GlitchData => hadesdbg2out9_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_8_B : ENTITY IS TRUE; - - end hades_dbg2_out_8_B; - - architecture Structure of hades_dbg2_out_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out8_out) - VARIABLE hadesdbg2out8_zd : std_logic := 'X'; - VARIABLE hadesdbg2out8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out8_zd := hadesdbg2out8_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out8, OutSignalName => "hadesdbg2out8", OutTemp => hadesdbg2out8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out8, - PathCondition => TRUE)), - GlitchData => hadesdbg2out8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_7_B : ENTITY IS TRUE; - - end hades_dbg2_out_7_B; - - architecture Structure of hades_dbg2_out_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out7_out) - VARIABLE hadesdbg2out7_zd : std_logic := 'X'; - VARIABLE hadesdbg2out7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out7_zd := hadesdbg2out7_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out7, OutSignalName => "hadesdbg2out7", OutTemp => hadesdbg2out7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out7, - PathCondition => TRUE)), - GlitchData => hadesdbg2out7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_6_B : ENTITY IS TRUE; - - end hades_dbg2_out_6_B; - - architecture Structure of hades_dbg2_out_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out6_out) - VARIABLE hadesdbg2out6_zd : std_logic := 'X'; - VARIABLE hadesdbg2out6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out6_zd := hadesdbg2out6_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out6, OutSignalName => "hadesdbg2out6", OutTemp => hadesdbg2out6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out6, - PathCondition => TRUE)), - GlitchData => hadesdbg2out6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_5_B : ENTITY IS TRUE; - - end hades_dbg2_out_5_B; - - architecture Structure of hades_dbg2_out_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out5_out) - VARIABLE hadesdbg2out5_zd : std_logic := 'X'; - VARIABLE hadesdbg2out5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out5_zd := hadesdbg2out5_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out5, OutSignalName => "hadesdbg2out5", OutTemp => hadesdbg2out5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out5, - PathCondition => TRUE)), - GlitchData => hadesdbg2out5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdbg2out4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdbg2out4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_4_B : ENTITY IS TRUE; - - end hades_dbg2_out_4_B; - - architecture Structure of hades_dbg2_out_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdbg2out4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdbg2out4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdbg2out4_out) - VARIABLE hadesdbg2out4_zd : std_logic := 'X'; - VARIABLE hadesdbg2out4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out4_zd := hadesdbg2out4_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out4, OutSignalName => "hadesdbg2out4", OutTemp => hadesdbg2out4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdbg2out4, - PathCondition => TRUE)), - GlitchData => hadesdbg2out4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_3_B"); - - port (hadesdbg2out3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_3_B : ENTITY IS TRUE; - - end hades_dbg2_out_3_B; - - architecture Structure of hades_dbg2_out_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesdbg2out3_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_3: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesdbg2out3_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesdbg2out3_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out3 <= hadesdbg2out3_out; - - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_2_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_2_B : ENTITY IS TRUE; - - end hades_dbg2_out_2_B; - - architecture Structure of hades_dbg2_out_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_2: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out2_out) - VARIABLE hadesdbg2out2_zd : std_logic := 'X'; - VARIABLE hadesdbg2out2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out2_zd := hadesdbg2out2_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out2, OutSignalName => "hadesdbg2out2", OutTemp => hadesdbg2out2_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out2, - PathCondition => TRUE)), - GlitchData => hadesdbg2out2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_2_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_2_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_2_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_2_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_2_MGIOL; - - architecture Structure of hades_dbg2_out_2_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_2: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_1_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_1_B : ENTITY IS TRUE; - - end hades_dbg2_out_1_B; - - architecture Structure of hades_dbg2_out_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_1: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out1_out) - VARIABLE hadesdbg2out1_zd : std_logic := 'X'; - VARIABLE hadesdbg2out1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out1_zd := hadesdbg2out1_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out1, OutSignalName => "hadesdbg2out1", OutTemp => hadesdbg2out1_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out1, - PathCondition => TRUE)), - GlitchData => hadesdbg2out1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_1_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_1_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_1_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_1_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_1_MGIOL; - - architecture Structure of hades_dbg2_out_1_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_1: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_0_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesdbg2out0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesdbg2out0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_0_B : ENTITY IS TRUE; - - end hades_dbg2_out_0_B; - - architecture Structure of hades_dbg2_out_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesdbg2out0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_dbg2_out_pad_0: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesdbg2out0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesdbg2out0_out) - VARIABLE hadesdbg2out0_zd : std_logic := 'X'; - VARIABLE hadesdbg2out0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdbg2out0_zd := hadesdbg2out0_out; - - VitalPathDelay01 ( - - OutSignal => hadesdbg2out0, OutSignalName => "hadesdbg2out0", OutTemp => hadesdbg2out0_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesdbg2out0, - PathCondition => TRUE)), - GlitchData => hadesdbg2out0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_dbg2_out_0_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_dbg2_out_0_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_dbg2_out_0_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_dbg2_out_0_MGIOL : ENTITY IS TRUE; - - end hades_dbg2_out_0_MGIOL; - - architecture Structure of hades_dbg2_out_0_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hitbuffer_1_io_0: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_drop_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_drop_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_drop_3_B"); - - port (hadesbufdrop3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_drop_3_B : ENTITY IS TRUE; - - end hades_buf_drop_3_B; - - architecture Structure of hades_buf_drop_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesbufdrop3_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_drop_pad_3: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesbufdrop3_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesbufdrop3_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufdrop3 <= hadesbufdrop3_out; - - - END PROCESS; - - end Structure; - --- entity hades_buf_drop_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_drop_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_drop_2_B"); - - port (hadesbufdrop2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_drop_2_B : ENTITY IS TRUE; - - end hades_buf_drop_2_B; - - architecture Structure of hades_buf_drop_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesbufdrop2_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_drop_pad_2: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesbufdrop2_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesbufdrop2_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufdrop2 <= hadesbufdrop2_out; - - - END PROCESS; - - end Structure; - --- entity hades_buf_drop_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_drop_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_drop_1_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesbufdrop1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesbufdrop1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_drop_1_B : ENTITY IS TRUE; - - end hades_buf_drop_1_B; - - architecture Structure of hades_buf_drop_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesbufdrop1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_drop_pad_1: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesbufdrop1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesbufdrop1_out) - VARIABLE hadesbufdrop1_zd : std_logic := 'X'; - VARIABLE hadesbufdrop1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufdrop1_zd := hadesbufdrop1_out; - - VitalPathDelay01 ( - - OutSignal => hadesbufdrop1, OutSignalName => "hadesbufdrop1", OutTemp => hadesbufdrop1_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesbufdrop1, - PathCondition => TRUE)), - GlitchData => hadesbufdrop1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity mfflsre0251 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity mfflsre0251 is - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF mfflsre0251 : ENTITY IS TRUE; - - end mfflsre0251; - - architecture Structure of mfflsre0251 is - begin - INST01: FD1P3IX - generic map (GSR => "DISABLED") - port map (D=>D0, SP=>SP, CK=>CK, CD=>LSR, Q=>Q); - end Structure; - --- entity hades_buf_drop_1_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_drop_1_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_drop_1_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_drop_1_MGIOL : ENTITY IS TRUE; - - end hades_buf_drop_1_MGIOL; - - architecture Structure of hades_buf_drop_1_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_buf_drop_1io_1: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_drop_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_drop_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_drop_0_B"); - - port (hadesbufdrop0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_drop_0_B : ENTITY IS TRUE; - - end hades_buf_drop_0_B; - - architecture Structure of hades_buf_drop_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesbufdrop0_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_drop_pad_0: sapiobuf0249 - port map (I=>GNDI, PAD=>hadesbufdrop0_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesbufdrop0_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufdrop0 <= hadesbufdrop0_out; - - - END PROCESS; - - end Structure; - --- entity hades_invalid_dl_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_invalid_dl_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_invalid_dl_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesinvaliddl3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesinvaliddl3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_invalid_dl_3_B : ENTITY IS TRUE; - - end hades_invalid_dl_3_B; - - architecture Structure of hades_invalid_dl_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesinvaliddl3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_invalid_dl_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesinvaliddl3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl3_out) - VARIABLE hadesinvaliddl3_zd : std_logic := 'X'; - VARIABLE hadesinvaliddl3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesinvaliddl3_zd := hadesinvaliddl3_out; - - VitalPathDelay01 ( - - OutSignal => hadesinvaliddl3, OutSignalName => "hadesinvaliddl3", OutTemp => hadesinvaliddl3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesinvaliddl3, - PathCondition => TRUE)), - GlitchData => hadesinvaliddl3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_invalid_dl_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_invalid_dl_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_invalid_dl_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesinvaliddl2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesinvaliddl2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_invalid_dl_2_B : ENTITY IS TRUE; - - end hades_invalid_dl_2_B; - - architecture Structure of hades_invalid_dl_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesinvaliddl2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_invalid_dl_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesinvaliddl2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl2_out) - VARIABLE hadesinvaliddl2_zd : std_logic := 'X'; - VARIABLE hadesinvaliddl2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesinvaliddl2_zd := hadesinvaliddl2_out; - - VitalPathDelay01 ( - - OutSignal => hadesinvaliddl2, OutSignalName => "hadesinvaliddl2", OutTemp => hadesinvaliddl2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesinvaliddl2, - PathCondition => TRUE)), - GlitchData => hadesinvaliddl2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_invalid_dl_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_invalid_dl_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_invalid_dl_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesinvaliddl1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesinvaliddl1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_invalid_dl_1_B : ENTITY IS TRUE; - - end hades_invalid_dl_1_B; - - architecture Structure of hades_invalid_dl_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesinvaliddl1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_invalid_dl_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesinvaliddl1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl1_out) - VARIABLE hadesinvaliddl1_zd : std_logic := 'X'; - VARIABLE hadesinvaliddl1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesinvaliddl1_zd := hadesinvaliddl1_out; - - VitalPathDelay01 ( - - OutSignal => hadesinvaliddl1, OutSignalName => "hadesinvaliddl1", OutTemp => hadesinvaliddl1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesinvaliddl1, - PathCondition => TRUE)), - GlitchData => hadesinvaliddl1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_invalid_dl_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_invalid_dl_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_invalid_dl_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesinvaliddl0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesinvaliddl0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_invalid_dl_0_B : ENTITY IS TRUE; - - end hades_invalid_dl_0_B; - - architecture Structure of hades_invalid_dl_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesinvaliddl0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_invalid_dl_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesinvaliddl0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesinvaliddl0_out) - VARIABLE hadesinvaliddl0_zd : std_logic := 'X'; - VARIABLE hadesinvaliddl0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesinvaliddl0_zd := hadesinvaliddl0_out; - - VitalPathDelay01 ( - - OutSignal => hadesinvaliddl0, OutSignalName => "hadesinvaliddl0", OutTemp => hadesinvaliddl0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesinvaliddl0, - PathCondition => TRUE)), - GlitchData => hadesinvaliddl0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_discardB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_discardB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_discardB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesdiscard : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesdiscard: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_discardB : ENTITY IS TRUE; - - end hades_discardB; - - architecture Structure of hades_discardB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesdiscard_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_discard_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesdiscard_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesdiscard_out) - VARIABLE hadesdiscard_zd : std_logic := 'X'; - VARIABLE hadesdiscard_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesdiscard_zd := hadesdiscard_out; - - VitalPathDelay01 ( - - OutSignal => hadesdiscard, OutSignalName => "hadesdiscard", OutTemp => hadesdiscard_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesdiscard, - PathCondition => TRUE)), - GlitchData => hadesdiscard_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_valid_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_valid_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_valid_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitvalid3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitvalid3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_valid_3_B : ENTITY IS TRUE; - - end hades_hit_valid_3_B; - - architecture Structure of hades_hit_valid_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitvalid3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_valid_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitvalid3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid3_out) - VARIABLE hadeshitvalid3_zd : std_logic := 'X'; - VARIABLE hadeshitvalid3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitvalid3_zd := hadeshitvalid3_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitvalid3, OutSignalName => "hadeshitvalid3", OutTemp => hadeshitvalid3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitvalid3, - PathCondition => TRUE)), - GlitchData => hadeshitvalid3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_valid_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_valid_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_valid_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitvalid2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitvalid2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_valid_2_B : ENTITY IS TRUE; - - end hades_hit_valid_2_B; - - architecture Structure of hades_hit_valid_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitvalid2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_valid_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitvalid2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid2_out) - VARIABLE hadeshitvalid2_zd : std_logic := 'X'; - VARIABLE hadeshitvalid2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitvalid2_zd := hadeshitvalid2_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitvalid2, OutSignalName => "hadeshitvalid2", OutTemp => hadeshitvalid2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitvalid2, - PathCondition => TRUE)), - GlitchData => hadeshitvalid2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_valid_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_valid_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_valid_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitvalid1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitvalid1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_valid_1_B : ENTITY IS TRUE; - - end hades_hit_valid_1_B; - - architecture Structure of hades_hit_valid_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitvalid1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_valid_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitvalid1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid1_out) - VARIABLE hadeshitvalid1_zd : std_logic := 'X'; - VARIABLE hadeshitvalid1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitvalid1_zd := hadeshitvalid1_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitvalid1, OutSignalName => "hadeshitvalid1", OutTemp => hadeshitvalid1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitvalid1, - PathCondition => TRUE)), - GlitchData => hadeshitvalid1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_valid_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_valid_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_valid_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitvalid0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitvalid0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_valid_0_B : ENTITY IS TRUE; - - end hades_hit_valid_0_B; - - architecture Structure of hades_hit_valid_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitvalid0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_valid_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitvalid0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitvalid0_out) - VARIABLE hadeshitvalid0_zd : std_logic := 'X'; - VARIABLE hadeshitvalid0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitvalid0_zd := hadeshitvalid0_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitvalid0, OutSignalName => "hadeshitvalid0", OutTemp => hadeshitvalid0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitvalid0, - PathCondition => TRUE)), - GlitchData => hadeshitvalid0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_out_i_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_out_i_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_out_i_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitouti3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitouti3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_out_i_3_B : ENTITY IS TRUE; - - end hades_hit_out_i_3_B; - - architecture Structure of hades_hit_out_i_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitouti3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_out_i_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitouti3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti3_out) - VARIABLE hadeshitouti3_zd : std_logic := 'X'; - VARIABLE hadeshitouti3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitouti3_zd := hadeshitouti3_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitouti3, OutSignalName => "hadeshitouti3", OutTemp => hadeshitouti3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitouti3, - PathCondition => TRUE)), - GlitchData => hadeshitouti3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_out_i_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_out_i_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_out_i_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitouti2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitouti2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_out_i_2_B : ENTITY IS TRUE; - - end hades_hit_out_i_2_B; - - architecture Structure of hades_hit_out_i_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitouti2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_out_i_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitouti2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti2_out) - VARIABLE hadeshitouti2_zd : std_logic := 'X'; - VARIABLE hadeshitouti2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitouti2_zd := hadeshitouti2_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitouti2, OutSignalName => "hadeshitouti2", OutTemp => hadeshitouti2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitouti2, - PathCondition => TRUE)), - GlitchData => hadeshitouti2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_out_i_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_out_i_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_out_i_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitouti1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitouti1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_out_i_1_B : ENTITY IS TRUE; - - end hades_hit_out_i_1_B; - - architecture Structure of hades_hit_out_i_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitouti1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_out_i_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitouti1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti1_out) - VARIABLE hadeshitouti1_zd : std_logic := 'X'; - VARIABLE hadeshitouti1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitouti1_zd := hadeshitouti1_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitouti1, OutSignalName => "hadeshitouti1", OutTemp => hadeshitouti1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitouti1, - PathCondition => TRUE)), - GlitchData => hadeshitouti1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_hit_out_i_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_hit_out_i_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_hit_out_i_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeshitouti0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeshitouti0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_hit_out_i_0_B : ENTITY IS TRUE; - - end hades_hit_out_i_0_B; - - architecture Structure of hades_hit_out_i_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeshitouti0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_hit_out_i_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeshitouti0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeshitouti0_out) - VARIABLE hadeshitouti0_zd : std_logic := 'X'; - VARIABLE hadeshitouti0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeshitouti0_zd := hadeshitouti0_out; - - VitalPathDelay01 ( - - OutSignal => hadeshitouti0, OutSignalName => "hadeshitouti0", OutTemp => hadeshitouti0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeshitouti0, - PathCondition => TRUE)), - GlitchData => hadeshitouti0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_finishedB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_finishedB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_finishedB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesbuffinished : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesbuffinished: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_finishedB : ENTITY IS TRUE; - - end hades_buf_finishedB; - - architecture Structure of hades_buf_finishedB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesbuffinished_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_finished_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesbuffinished_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesbuffinished_out) - VARIABLE hadesbuffinished_zd : std_logic := 'X'; - VARIABLE hadesbuffinished_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbuffinished_zd := hadesbuffinished_out; - - VitalPathDelay01 ( - - OutSignal => hadesbuffinished, OutSignalName => "hadesbuffinished", OutTemp => hadesbuffinished_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesbuffinished, - PathCondition => TRUE)), - GlitchData => hadesbuffinished_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_releaseB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_releaseB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_releaseB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesbufrelease : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesbufrelease: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_releaseB : ENTITY IS TRUE; - - end hades_buf_releaseB; - - architecture Structure of hades_buf_releaseB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesbufrelease_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_release_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesbufrelease_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesbufrelease_out) - VARIABLE hadesbufrelease_zd : std_logic := 'X'; - VARIABLE hadesbufrelease_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufrelease_zd := hadesbufrelease_out; - - VitalPathDelay01 ( - - OutSignal => hadesbufrelease, OutSignalName => "hadesbufrelease", OutTemp => hadesbufrelease_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesbufrelease, - PathCondition => TRUE)), - GlitchData => hadesbufrelease_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_out_validB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_out_validB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_out_validB"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesbufoutvalid : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesbufoutvalid: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_out_validB : ENTITY IS TRUE; - - end hades_buf_out_validB; - - architecture Structure of hades_buf_out_validB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesbufoutvalid_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_buf_out_valid_pad: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesbufoutvalid_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesbufoutvalid_out) - VARIABLE hadesbufoutvalid_zd : std_logic := 'X'; - VARIABLE hadesbufoutvalid_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesbufoutvalid_zd := hadesbufoutvalid_out; - - VitalPathDelay01 ( - - OutSignal => hadesbufoutvalid, OutSignalName => "hadesbufoutvalid", OutTemp => hadesbufoutvalid_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesbufoutvalid, - PathCondition => TRUE)), - GlitchData => hadesbufoutvalid_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_buf_out_valid_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_buf_out_valid_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_buf_out_valid_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_buf_out_valid_MGIOL : ENTITY IS TRUE; - - end hades_buf_out_valid_MGIOL; - - architecture Structure of hades_buf_out_valid_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_buf_out_validio: mfflsre - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_window_endB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_window_endB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_window_endB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadeswindowend : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadeswindowend: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_window_endB : ENTITY IS TRUE; - - end hades_window_endB; - - architecture Structure of hades_window_endB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadeswindowend_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_window_end_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadeswindowend_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadeswindowend_out) - VARIABLE hadeswindowend_zd : std_logic := 'X'; - VARIABLE hadeswindowend_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadeswindowend_zd := hadeswindowend_out; - - VitalPathDelay01 ( - - OutSignal => hadeswindowend, OutSignalName => "hadeswindowend", OutTemp => hadeswindowend_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadeswindowend, - PathCondition => TRUE)), - GlitchData => hadeswindowend_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_validB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_validB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_validB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_hadesoffsetvalid : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; hadesoffsetvalid: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_validB : ENTITY IS TRUE; - - end hades_offset_validB; - - architecture Structure of hades_offset_validB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal hadesoffsetvalid_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_valid_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>hadesoffsetvalid_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, hadesoffsetvalid_out) - VARIABLE hadesoffsetvalid_zd : std_logic := 'X'; - VARIABLE hadesoffsetvalid_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffsetvalid_zd := hadesoffsetvalid_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffsetvalid, OutSignalName => "hadesoffsetvalid", OutTemp => hadesoffsetvalid_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_hadesoffsetvalid, - PathCondition => TRUE)), - GlitchData => hadesoffsetvalid_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_8_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_8_B : ENTITY IS TRUE; - - end hades_offset_8_B; - - architecture Structure of hades_offset_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_8: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset8_out) - VARIABLE hadesoffset8_zd : std_logic := 'X'; - VARIABLE hadesoffset8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset8_zd := hadesoffset8_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset8, OutSignalName => "hadesoffset8", OutTemp => hadesoffset8_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset8, - PathCondition => TRUE)), - GlitchData => hadesoffset8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_8_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_8_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_8_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_8_MGIOL : ENTITY IS TRUE; - - end hades_offset_8_MGIOL; - - architecture Structure of hades_offset_8_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_7_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_7_B : ENTITY IS TRUE; - - end hades_offset_7_B; - - architecture Structure of hades_offset_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_7: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset7_out) - VARIABLE hadesoffset7_zd : std_logic := 'X'; - VARIABLE hadesoffset7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset7_zd := hadesoffset7_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset7, OutSignalName => "hadesoffset7", OutTemp => hadesoffset7_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset7, - PathCondition => TRUE)), - GlitchData => hadesoffset7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_7_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_7_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_7_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_7_MGIOL : ENTITY IS TRUE; - - end hades_offset_7_MGIOL; - - architecture Structure of hades_offset_7_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_6_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_6_B : ENTITY IS TRUE; - - end hades_offset_6_B; - - architecture Structure of hades_offset_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_6: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset6_out) - VARIABLE hadesoffset6_zd : std_logic := 'X'; - VARIABLE hadesoffset6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset6_zd := hadesoffset6_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset6, OutSignalName => "hadesoffset6", OutTemp => hadesoffset6_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset6, - PathCondition => TRUE)), - GlitchData => hadesoffset6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_6_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_6_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_6_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_6_MGIOL : ENTITY IS TRUE; - - end hades_offset_6_MGIOL; - - architecture Structure of hades_offset_6_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_5_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_5_B : ENTITY IS TRUE; - - end hades_offset_5_B; - - architecture Structure of hades_offset_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_5: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset5_out) - VARIABLE hadesoffset5_zd : std_logic := 'X'; - VARIABLE hadesoffset5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset5_zd := hadesoffset5_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset5, OutSignalName => "hadesoffset5", OutTemp => hadesoffset5_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset5, - PathCondition => TRUE)), - GlitchData => hadesoffset5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_5_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_5_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_5_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_5_MGIOL : ENTITY IS TRUE; - - end hades_offset_5_MGIOL; - - architecture Structure of hades_offset_5_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_4_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_4_B : ENTITY IS TRUE; - - end hades_offset_4_B; - - architecture Structure of hades_offset_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_4: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset4_out) - VARIABLE hadesoffset4_zd : std_logic := 'X'; - VARIABLE hadesoffset4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset4_zd := hadesoffset4_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset4, OutSignalName => "hadesoffset4", OutTemp => hadesoffset4_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset4, - PathCondition => TRUE)), - GlitchData => hadesoffset4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_4_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_4_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_4_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_4_MGIOL : ENTITY IS TRUE; - - end hades_offset_4_MGIOL; - - architecture Structure of hades_offset_4_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_3_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_3_B : ENTITY IS TRUE; - - end hades_offset_3_B; - - architecture Structure of hades_offset_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_3: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset3_out) - VARIABLE hadesoffset3_zd : std_logic := 'X'; - VARIABLE hadesoffset3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset3_zd := hadesoffset3_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset3, OutSignalName => "hadesoffset3", OutTemp => hadesoffset3_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset3, - PathCondition => TRUE)), - GlitchData => hadesoffset3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_3_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_3_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_3_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_3_MGIOL : ENTITY IS TRUE; - - end hades_offset_3_MGIOL; - - architecture Structure of hades_offset_3_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_2_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_2_B : ENTITY IS TRUE; - - end hades_offset_2_B; - - architecture Structure of hades_offset_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_2: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset2_out) - VARIABLE hadesoffset2_zd : std_logic := 'X'; - VARIABLE hadesoffset2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset2_zd := hadesoffset2_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset2, OutSignalName => "hadesoffset2", OutTemp => hadesoffset2_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset2, - PathCondition => TRUE)), - GlitchData => hadesoffset2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_2_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_2_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_2_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_2_MGIOL : ENTITY IS TRUE; - - end hades_offset_2_MGIOL; - - architecture Structure of hades_offset_2_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_1_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_1_B : ENTITY IS TRUE; - - end hades_offset_1_B; - - architecture Structure of hades_offset_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_1: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset1_out) - VARIABLE hadesoffset1_zd : std_logic := 'X'; - VARIABLE hadesoffset1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset1_zd := hadesoffset1_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset1, OutSignalName => "hadesoffset1", OutTemp => hadesoffset1_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset1, - PathCondition => TRUE)), - GlitchData => hadesoffset1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_1_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_1_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_1_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_1_MGIOL : ENTITY IS TRUE; - - end hades_offset_1_MGIOL; - - architecture Structure of hades_offset_1_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_0_B"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesoffset0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesoffset0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_0_B : ENTITY IS TRUE; - - end hades_offset_0_B; - - architecture Structure of hades_offset_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesoffset0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_offset_pad_0: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesoffset0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesoffset0_out) - VARIABLE hadesoffset0_zd : std_logic := 'X'; - VARIABLE hadesoffset0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesoffset0_zd := hadesoffset0_out; - - VitalPathDelay01 ( - - OutSignal => hadesoffset0, OutSignalName => "hadesoffset0", OutTemp => hadesoffset0_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesoffset0, - PathCondition => TRUE)), - GlitchData => hadesoffset0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_offset_0_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_offset_0_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_offset_0_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CE : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_CE_CLK : VitalDelayType := 0 ns; - tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_offset_0_MGIOL : ENTITY IS TRUE; - - end hades_offset_0_MGIOL; - - architecture Structure of hades_offset_0_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CE_ipd : std_logic := 'X'; - signal CE_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>CE_dly, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CE_ipd, CE, tipd_CE); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CE_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CE_CLK : x01 := '0'; - VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CE_dly, - TestSignalName => "CE", - TestDelay => tisd_CE_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_CE_CLK_noedge_posedge, - SetupLow => tsetup_CE_CLK_noedge_posedge, - HoldHigh => thold_CE_CLK_noedge_posedge, - HoldLow => thold_CE_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CE_CLK_TimingDatash, - Violation => tviol_CE_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity sapiobuf0252 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity sapiobuf0252 is - port (Z: out Std_logic; PAD: in Std_logic); - - ATTRIBUTE Vital_Level0 OF sapiobuf0252 : ENTITY IS TRUE; - - end sapiobuf0252; - - architecture Structure of sapiobuf0252 is - begin - INST1: IBPD - port map (I=>PAD, O=>Z); - end Structure; - --- entity hades_lvl1_invalidB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_lvl1_invalidB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_lvl1_invalidB"; - - tipd_hadeslvl1invalid : VitalDelayType01 := (0 ns, 0 ns); - tpd_hadeslvl1invalid_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_hadeslvl1invalid : VitalDelayType := 0 ns; - tpw_hadeslvl1invalid_posedge : VitalDelayType := 0 ns; - tpw_hadeslvl1invalid_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; hadeslvl1invalid: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_lvl1_invalidB : ENTITY IS TRUE; - - end hades_lvl1_invalidB; - - architecture Structure of hades_lvl1_invalidB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal hadeslvl1invalid_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - hades_lvl1_invalid_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>hadeslvl1invalid_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(hadeslvl1invalid_ipd, hadeslvl1invalid, tipd_hadeslvl1invalid); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, hadeslvl1invalid_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_hadeslvl1invalid_hadeslvl1invalid : x01 := '0'; - VARIABLE periodcheckinfo_hadeslvl1invalid : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => hadeslvl1invalid_ipd, - TestSignalName => "hadeslvl1invalid", - Period => tperiod_hadeslvl1invalid, - PulseWidthHigh => tpw_hadeslvl1invalid_posedge, - PulseWidthLow => tpw_hadeslvl1invalid_negedge, - PeriodData => periodcheckinfo_hadeslvl1invalid, - Violation => tviol_hadeslvl1invalid_hadeslvl1invalid, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => hadeslvl1invalid_ipd'last_event, - PathDelay => tpd_hadeslvl1invalid_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity smuxlregsre - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity smuxlregsre is - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - - ATTRIBUTE Vital_Level0 OF smuxlregsre : ENTITY IS TRUE; - - end smuxlregsre; - - architecture Structure of smuxlregsre is - begin - INST01: IFS1P3DX - generic map (GSR => "DISABLED") - port map (D=>D0, SP=>SP, SCLK=>CK, CD=>LSR, Q=>Q); - end Structure; - --- entity hades_lvl1_invalid_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_lvl1_invalid_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_lvl1_invalid_MGIOL"; - - tipd_DI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_INFF : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI_CLK : VitalDelayType := 0 ns; - tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_lvl1_invalid_MGIOL : ENTITY IS TRUE; - - end hades_lvl1_invalid_MGIOL; - - architecture Structure of hades_lvl1_invalid_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI_ipd : std_logic := 'X'; - signal DI_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal INFF_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component smuxlregsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0: smuxlregsre - port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI_ipd, DI, tipd_DI); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out) - VARIABLE INFF_zd : std_logic := 'X'; - VARIABLE INFF_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI_CLK : x01 := '0'; - VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI_dly, - TestSignalName => "DI", - TestDelay => tisd_DI_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI_CLK_noedge_posedge, - SetupLow => tsetup_DI_CLK_noedge_posedge, - HoldHigh => thold_DI_CLK_noedge_posedge, - HoldLow => thold_DI_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI_CLK_TimingDatash, - Violation => tviol_DI_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - INFF_zd := INFF_out; - - VitalPathDelay01 ( - OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_INFF, - PathCondition => TRUE)), - GlitchData => INFF_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_lvl1B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_lvl1B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_lvl1B"; - - tipd_hadeslvl1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_hadeslvl1_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_hadeslvl1 : VitalDelayType := 0 ns; - tpw_hadeslvl1_posedge : VitalDelayType := 0 ns; - tpw_hadeslvl1_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; hadeslvl1: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_lvl1B : ENTITY IS TRUE; - - end hades_lvl1B; - - architecture Structure of hades_lvl1B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal hadeslvl1_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - hades_lvl1_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>hadeslvl1_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(hadeslvl1_ipd, hadeslvl1, tipd_hadeslvl1); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, hadeslvl1_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_hadeslvl1_hadeslvl1 : x01 := '0'; - VARIABLE periodcheckinfo_hadeslvl1 : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => hadeslvl1_ipd, - TestSignalName => "hadeslvl1", - Period => tperiod_hadeslvl1, - PulseWidthHigh => tpw_hadeslvl1_posedge, - PulseWidthLow => tpw_hadeslvl1_negedge, - PeriodData => periodcheckinfo_hadeslvl1, - Violation => tviol_hadeslvl1_hadeslvl1, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => hadeslvl1_ipd'last_event, - PathDelay => tpd_hadeslvl1_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_lvl1_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_lvl1_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_lvl1_MGIOL"; - - tipd_DI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_INFF : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI_CLK : VitalDelayType := 0 ns; - tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_lvl1_MGIOL : ENTITY IS TRUE; - - end hades_lvl1_MGIOL; - - architecture Structure of hades_lvl1_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI_ipd : std_logic := 'X'; - signal DI_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal INFF_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component smuxlregsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0: smuxlregsre - port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI_ipd, DI, tipd_DI); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out) - VARIABLE INFF_zd : std_logic := 'X'; - VARIABLE INFF_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI_CLK : x01 := '0'; - VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI_dly, - TestSignalName => "DI", - TestDelay => tisd_DI_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI_CLK_noedge_posedge, - SetupLow => tsetup_DI_CLK_noedge_posedge, - HoldHigh => thold_DI_CLK_noedge_posedge, - HoldLow => thold_DI_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI_CLK_TimingDatash, - Violation => tviol_DI_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - INFF_zd := INFF_out; - - VitalPathDelay01 ( - OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_INFF, - PathCondition => TRUE)), - GlitchData => INFF_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_raw_valid_vect_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_raw_valid_vect_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_raw_valid_vect_1_B"); - - port (hadesrawvalidvect1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_raw_valid_vect_1_B : ENTITY IS TRUE; - - end hades_raw_valid_vect_1_B; - - architecture Structure of hades_raw_valid_vect_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal hadesrawvalidvect1_out : std_logic := 'X'; - - signal GNDI: Std_logic; - signal VCCI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component sapiobuf - port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_raw_valid_vect_pad_1: sapiobuf - port map (I=>GNDI, T=>VCCI, PAD=>hadesrawvalidvect1_out); - DRIVEGND: gnd - port map (PWR0=>GNDI); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - END BLOCK; - - VitalBehavior : PROCESS (hadesrawvalidvect1_out) - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesrawvalidvect1 <= hadesrawvalidvect1_out; - - - END PROCESS; - - end Structure; - --- entity hades_raw_out_validB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_raw_out_validB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_raw_out_validB"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_hadesrawoutvalid : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; hadesrawoutvalid: out Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_raw_out_validB : ENTITY IS TRUE; - - end hades_raw_out_validB; - - architecture Structure of hades_raw_out_validB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal hadesrawoutvalid_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - hades_raw_out_valid_pad: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>hadesrawoutvalid_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, hadesrawoutvalid_out) - VARIABLE hadesrawoutvalid_zd : std_logic := 'X'; - VARIABLE hadesrawoutvalid_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - hadesrawoutvalid_zd := hadesrawoutvalid_out; - - VitalPathDelay01 ( - - OutSignal => hadesrawoutvalid, OutSignalName => "hadesrawoutvalid", OutTemp => hadesrawoutvalid_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_hadesrawoutvalid, - PathCondition => TRUE)), - GlitchData => hadesrawoutvalid_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_raw_out_valid_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_raw_out_valid_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_raw_out_valid_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_raw_out_valid_MGIOL : ENTITY IS TRUE; - - end hades_raw_out_valid_MGIOL; - - architecture Structure of hades_raw_out_valid_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component mfflsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - hades_tdc_bundle_inst_referenced_out_validio: mfflsre - port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, - Q=>IOLDO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity hades_trigB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity hades_trigB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "hades_trigB"; - - tipd_hadestrig : VitalDelayType01 := (0 ns, 0 ns); - tpd_hadestrig_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_hadestrig : VitalDelayType := 0 ns; - tpw_hadestrig_posedge : VitalDelayType := 0 ns; - tpw_hadestrig_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; hadestrig: in Std_logic); - - ATTRIBUTE Vital_Level0 OF hades_trigB : ENTITY IS TRUE; - - end hades_trigB; - - architecture Structure of hades_trigB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal hadestrig_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - hades_trig_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>hadestrig_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(hadestrig_ipd, hadestrig, tipd_hadestrig); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, hadestrig_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_hadestrig_hadestrig : x01 := '0'; - VARIABLE periodcheckinfo_hadestrig : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => hadestrig_ipd, - TestSignalName => "hadestrig", - Period => tperiod_hadestrig, - PulseWidthHigh => tpw_hadestrig_posedge, - PulseWidthLow => tpw_hadestrig_negedge, - PeriodData => periodcheckinfo_hadestrig, - Violation => tviol_hadestrig_hadestrig, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => hadestrig_ipd'last_event, - PathDelay => tpd_hadestrig_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity release_outB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity release_outB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "release_outB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_releaseout : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; releaseout: out Std_logic); - - ATTRIBUTE Vital_Level0 OF release_outB : ENTITY IS TRUE; - - end release_outB; - - architecture Structure of release_outB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal releaseout_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - release_out_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>releaseout_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, releaseout_out) - VARIABLE releaseout_zd : std_logic := 'X'; - VARIABLE releaseout_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - releaseout_zd := releaseout_out; - - VitalPathDelay01 ( - - OutSignal => releaseout, OutSignalName => "releaseout", OutTemp => releaseout_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_releaseout, - PathCondition => TRUE)), - GlitchData => releaseout_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity finishedB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity finishedB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "finishedB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_finishedS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; finishedS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF finishedB : ENTITY IS TRUE; - - end finishedB; - - architecture Structure of finishedB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal finishedS_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - finished_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>finishedS_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, finishedS_out) - VARIABLE finishedS_zd : std_logic := 'X'; - VARIABLE finishedS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - finishedS_zd := finishedS_out; - - VitalPathDelay01 ( - OutSignal => finishedS, OutSignalName => "finishedS", OutTemp => finishedS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_finishedS, - PathCondition => TRUE)), - GlitchData => finishedS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity last_buf_emptyB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity last_buf_emptyB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "last_buf_emptyB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_lastbufempty : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; lastbufempty: out Std_logic); - - ATTRIBUTE Vital_Level0 OF last_buf_emptyB : ENTITY IS TRUE; - - end last_buf_emptyB; - - architecture Structure of last_buf_emptyB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal lastbufempty_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - last_buf_empty_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>lastbufempty_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, lastbufempty_out) - VARIABLE lastbufempty_zd : std_logic := 'X'; - VARIABLE lastbufempty_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - lastbufempty_zd := lastbufempty_out; - - VitalPathDelay01 ( - - OutSignal => lastbufempty, OutSignalName => "lastbufempty", OutTemp => lastbufempty_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_lastbufempty, - PathCondition => TRUE)), - GlitchData => lastbufempty_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity discardB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity discardB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "discardB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_discardS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; discardS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF discardB : ENTITY IS TRUE; - - end discardB; - - architecture Structure of discardB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal discardS_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - discard_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>discardS_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, discardS_out) - VARIABLE discardS_zd : std_logic := 'X'; - VARIABLE discardS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - discardS_zd := discardS_out; - - VitalPathDelay01 ( - OutSignal => discardS, OutSignalName => "discardS", OutTemp => discardS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_discardS, - PathCondition => TRUE)), - GlitchData => discardS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity burstB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity burstB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "burstB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_burstS : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; burstS: out Std_logic); - - ATTRIBUTE Vital_Level0 OF burstB : ENTITY IS TRUE; - - end burstB; - - architecture Structure of burstB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal burstS_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - burst_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>burstS_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, burstS_out) - VARIABLE burstS_zd : std_logic := 'X'; - VARIABLE burstS_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - burstS_zd := burstS_out; - - VitalPathDelay01 ( - OutSignal => burstS, OutSignalName => "burstS", OutTemp => burstS_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_burstS, - PathCondition => TRUE)), - GlitchData => burstS_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LVL1_TRG_DATA_VALI_IN_risingB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity LVL1_TRG_DATA_VALI_IN_risingB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LVL1_TRG_DATA_VALI_IN_risingB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_LVL1TRGDATAVALIINrising : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; LVL1TRGDATAVALIINrising: out Std_logic); - - ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALI_IN_risingB : ENTITY IS TRUE; - - end LVL1_TRG_DATA_VALI_IN_risingB; - - architecture Structure of LVL1_TRG_DATA_VALI_IN_risingB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal LVL1TRGDATAVALIINrising_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - LVL1_TRG_DATA_VALI_IN_rising_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>LVL1TRGDATAVALIINrising_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, LVL1TRGDATAVALIINrising_out) - VARIABLE LVL1TRGDATAVALIINrising_zd : std_logic := 'X'; - VARIABLE LVL1TRGDATAVALIINrising_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - LVL1TRGDATAVALIINrising_zd := LVL1TRGDATAVALIINrising_out; - - VitalPathDelay01 ( - - OutSignal => LVL1TRGDATAVALIINrising, OutSignalName => "LVL1TRGDATAVALIINrising", OutTemp => LVL1TRGDATAVALIINrising_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_LVL1TRGDATAVALIINrising, - PathCondition => TRUE)), - GlitchData => LVL1TRGDATAVALIINrising_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_TRG_RELEASE_OUTB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_TRG_RELEASE_OUTB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_TRG_RELEASE_OUTB"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_FEETRGRELEASEOUT : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; FEETRGRELEASEOUT: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_TRG_RELEASE_OUTB : ENTITY IS TRUE; - - end FEE_TRG_RELEASE_OUTB; - - architecture Structure of FEE_TRG_RELEASE_OUTB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal FEETRGRELEASEOUT_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_TRG_RELEASE_OUT_pad: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>FEETRGRELEASEOUT_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, FEETRGRELEASEOUT_out) - VARIABLE FEETRGRELEASEOUT_zd : std_logic := 'X'; - VARIABLE FEETRGRELEASEOUT_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEETRGRELEASEOUT_zd := FEETRGRELEASEOUT_out; - - VitalPathDelay01 ( - - OutSignal => FEETRGRELEASEOUT, OutSignalName => "FEETRGRELEASEOUT", OutTemp => FEETRGRELEASEOUT_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_FEETRGRELEASEOUT, - PathCondition => TRUE)), - GlitchData => FEETRGRELEASEOUT_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_TRG_RELEASE_OUT_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_TRG_RELEASE_OUT_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_TRG_RELEASE_OUT_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_TRG_RELEASE_OUT_MGIOL : ENTITY IS TRUE; - - end FEE_TRG_RELEASE_OUT_MGIOL; - - architecture Structure of FEE_TRG_RELEASE_OUT_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - trb_adapter_inst_FEE_TRG_RELEASE_OUTio: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATAFINISHED_OUTB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATAFINISHED_OUTB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATAFINISHED_OUTB"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_FEEDATAFINISHEDOUT : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; FEEDATAFINISHEDOUT: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATAFINISHED_OUTB : ENTITY IS TRUE; - - end FEE_DATAFINISHED_OUTB; - - architecture Structure of FEE_DATAFINISHED_OUTB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal FEEDATAFINISHEDOUT_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATAFINISHED_OUT_pad: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>FEEDATAFINISHEDOUT_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, FEEDATAFINISHEDOUT_out) - VARIABLE FEEDATAFINISHEDOUT_zd : std_logic := 'X'; - VARIABLE FEEDATAFINISHEDOUT_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAFINISHEDOUT_zd := FEEDATAFINISHEDOUT_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAFINISHEDOUT, OutSignalName => "FEEDATAFINISHEDOUT", OutTemp => FEEDATAFINISHEDOUT_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_FEEDATAFINISHEDOUT, - PathCondition => TRUE)), - GlitchData => FEEDATAFINISHEDOUT_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATAFINISHED_OUT_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATAFINISHED_OUT_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATAFINISHED_OUT_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATAFINISHED_OUT_MGIOL : ENTITY IS TRUE; - - end FEE_DATAFINISHED_OUT_MGIOL; - - architecture Structure of FEE_DATAFINISHED_OUT_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - trb_adapter_inst_FEE_DATAFINISHED_OUTio: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_WRITE_OUTB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_WRITE_OUTB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_WRITE_OUTB"; - - tipd_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_IOLDO_FEEDATAWRITEOUT : VitalDelayType01 := (0 ns, 0 ns)); - - port (IOLDO: in Std_logic; FEEDATAWRITEOUT: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_WRITE_OUTB : ENTITY IS TRUE; - - end FEE_DATA_WRITE_OUTB; - - architecture Structure of FEE_DATA_WRITE_OUTB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_ipd : std_logic := 'X'; - signal FEEDATAWRITEOUT_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_WRITE_OUT_pad: sapiobuf0249 - port map (I=>IOLDO_ipd, PAD=>FEEDATAWRITEOUT_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(IOLDO_ipd, IOLDO, tipd_IOLDO); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_ipd, FEEDATAWRITEOUT_out) - VARIABLE FEEDATAWRITEOUT_zd : std_logic := 'X'; - VARIABLE FEEDATAWRITEOUT_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAWRITEOUT_zd := FEEDATAWRITEOUT_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAWRITEOUT, OutSignalName => "FEEDATAWRITEOUT", OutTemp => FEEDATAWRITEOUT_zd, - Paths => (0 => (InputChangeTime => IOLDO_ipd'last_event, - PathDelay => tpd_IOLDO_FEEDATAWRITEOUT, - PathCondition => TRUE)), - GlitchData => FEEDATAWRITEOUT_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_WRITE_OUT_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_WRITE_OUT_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_WRITE_OUT_MGIOL"; - - tipd_TXDATA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_IOLDO : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_TXDATA0_CLK : VitalDelayType := 0 ns; - tsetup_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_TXDATA0_CLK_noedge_posedge : VitalDelayType := 0 ns; - tisd_LSR_CLK : VitalDelayType := 0 ns; - tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_WRITE_OUT_MGIOL : ENTITY IS TRUE; - - end FEE_DATA_WRITE_OUT_MGIOL; - - architecture Structure of FEE_DATA_WRITE_OUT_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal IOLDO_out : std_logic := 'X'; - signal TXDATA0_ipd : std_logic := 'X'; - signal TXDATA0_dly : std_logic := 'X'; - signal LSR_ipd : std_logic := 'X'; - signal LSR_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - component vcc - port (PWR1: out Std_logic); - end component; - component mfflsre0251 - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - trb_adapter_inst_FEE_DATA_WRITE_OUTio: mfflsre0251 - port map (D0=>TXDATA0_dly, SP=>VCCI, CK=>CLK_dly, LSR=>LSR_dly, - Q=>IOLDO_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(TXDATA0_ipd, TXDATA0, tipd_TXDATA0); - VitalWireDelay(LSR_ipd, LSR, tipd_LSR); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(TXDATA0_dly, TXDATA0_ipd, tisd_TXDATA0_CLK); - VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (IOLDO_out, TXDATA0_dly, LSR_dly, CLK_dly) - VARIABLE IOLDO_zd : std_logic := 'X'; - VARIABLE IOLDO_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_TXDATA0_CLK : x01 := '0'; - VARIABLE TXDATA0_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_LSR_CLK : x01 := '0'; - VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => TXDATA0_dly, - TestSignalName => "TXDATA0", - TestDelay => tisd_TXDATA0_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_TXDATA0_CLK_noedge_posedge, - SetupLow => tsetup_TXDATA0_CLK_noedge_posedge, - HoldHigh => thold_TXDATA0_CLK_noedge_posedge, - HoldLow => thold_TXDATA0_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => TXDATA0_CLK_TimingDatash, - Violation => tviol_TXDATA0_CLK, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => LSR_dly, - TestSignalName => "LSR", - TestDelay => tisd_LSR_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_LSR_CLK_noedge_posedge, - SetupLow => tsetup_LSR_CLK_noedge_posedge, - HoldHigh => thold_LSR_CLK_noedge_posedge, - HoldLow => thold_LSR_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => LSR_CLK_TimingDatash, - Violation => tviol_LSR_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - IOLDO_zd := IOLDO_out; - - VitalPathDelay01 ( - OutSignal => IOLDO, OutSignalName => "IOLDO", OutTemp => IOLDO_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_IOLDO, - PathCondition => TRUE)), - GlitchData => IOLDO_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_31_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_31_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_31_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT31 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT31: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_31_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_31_B; - - architecture Structure of FEE_DATA_OUT_31_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT31_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_31: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT31_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT31_out) - VARIABLE FEEDATAOUT31_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT31_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT31_zd := FEEDATAOUT31_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT31, OutSignalName => "FEEDATAOUT31", OutTemp => FEEDATAOUT31_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT31, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT31_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_30_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_30_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_30_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT30 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT30: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_30_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_30_B; - - architecture Structure of FEE_DATA_OUT_30_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT30_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_30: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT30_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT30_out) - VARIABLE FEEDATAOUT30_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT30_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT30_zd := FEEDATAOUT30_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT30, OutSignalName => "FEEDATAOUT30", OutTemp => FEEDATAOUT30_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT30, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT30_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_29_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_29_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_29_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT29 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT29: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_29_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_29_B; - - architecture Structure of FEE_DATA_OUT_29_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT29_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_29: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT29_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT29_out) - VARIABLE FEEDATAOUT29_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT29_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT29_zd := FEEDATAOUT29_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT29, OutSignalName => "FEEDATAOUT29", OutTemp => FEEDATAOUT29_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT29, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT29_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_28_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_28_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_28_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT28 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT28: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_28_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_28_B; - - architecture Structure of FEE_DATA_OUT_28_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT28_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_28: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT28_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT28_out) - VARIABLE FEEDATAOUT28_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT28_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT28_zd := FEEDATAOUT28_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT28, OutSignalName => "FEEDATAOUT28", OutTemp => FEEDATAOUT28_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT28, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT28_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_27_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_27_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_27_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT27 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT27: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_27_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_27_B; - - architecture Structure of FEE_DATA_OUT_27_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT27_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_27: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT27_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT27_out) - VARIABLE FEEDATAOUT27_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT27_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT27_zd := FEEDATAOUT27_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT27, OutSignalName => "FEEDATAOUT27", OutTemp => FEEDATAOUT27_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT27, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT27_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_26_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_26_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_26_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT26 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT26: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_26_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_26_B; - - architecture Structure of FEE_DATA_OUT_26_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT26_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_26: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT26_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT26_out) - VARIABLE FEEDATAOUT26_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT26_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT26_zd := FEEDATAOUT26_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT26, OutSignalName => "FEEDATAOUT26", OutTemp => FEEDATAOUT26_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT26, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT26_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_25_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_25_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_25_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT25 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT25: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_25_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_25_B; - - architecture Structure of FEE_DATA_OUT_25_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT25_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_25: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT25_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT25_out) - VARIABLE FEEDATAOUT25_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT25_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT25_zd := FEEDATAOUT25_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT25, OutSignalName => "FEEDATAOUT25", OutTemp => FEEDATAOUT25_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT25, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT25_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_24_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_24_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_24_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT24 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT24: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_24_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_24_B; - - architecture Structure of FEE_DATA_OUT_24_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT24_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_24: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT24_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT24_out) - VARIABLE FEEDATAOUT24_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT24_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT24_zd := FEEDATAOUT24_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT24, OutSignalName => "FEEDATAOUT24", OutTemp => FEEDATAOUT24_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT24, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT24_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_23_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_23_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_23_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT23 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT23: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_23_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_23_B; - - architecture Structure of FEE_DATA_OUT_23_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT23_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_23: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT23_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT23_out) - VARIABLE FEEDATAOUT23_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT23_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT23_zd := FEEDATAOUT23_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT23, OutSignalName => "FEEDATAOUT23", OutTemp => FEEDATAOUT23_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT23, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT23_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_22_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_22_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_22_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT22 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT22: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_22_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_22_B; - - architecture Structure of FEE_DATA_OUT_22_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT22_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_22: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT22_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT22_out) - VARIABLE FEEDATAOUT22_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT22_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT22_zd := FEEDATAOUT22_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT22, OutSignalName => "FEEDATAOUT22", OutTemp => FEEDATAOUT22_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT22, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT22_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_21_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_21_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_21_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT21 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT21: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_21_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_21_B; - - architecture Structure of FEE_DATA_OUT_21_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT21_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_21: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT21_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT21_out) - VARIABLE FEEDATAOUT21_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT21_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT21_zd := FEEDATAOUT21_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT21, OutSignalName => "FEEDATAOUT21", OutTemp => FEEDATAOUT21_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT21, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT21_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_20_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_20_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_20_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT20 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT20: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_20_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_20_B; - - architecture Structure of FEE_DATA_OUT_20_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT20_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_20: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT20_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT20_out) - VARIABLE FEEDATAOUT20_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT20_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT20_zd := FEEDATAOUT20_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT20, OutSignalName => "FEEDATAOUT20", OutTemp => FEEDATAOUT20_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT20, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT20_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_19_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_19_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_19_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT19 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT19: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_19_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_19_B; - - architecture Structure of FEE_DATA_OUT_19_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT19_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_19: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT19_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT19_out) - VARIABLE FEEDATAOUT19_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT19_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT19_zd := FEEDATAOUT19_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT19, OutSignalName => "FEEDATAOUT19", OutTemp => FEEDATAOUT19_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT19, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT19_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_18_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_18_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_18_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT18 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT18: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_18_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_18_B; - - architecture Structure of FEE_DATA_OUT_18_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT18_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_18: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT18_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT18_out) - VARIABLE FEEDATAOUT18_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT18_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT18_zd := FEEDATAOUT18_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT18, OutSignalName => "FEEDATAOUT18", OutTemp => FEEDATAOUT18_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT18, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT18_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_17_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_17_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_17_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT17 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT17: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_17_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_17_B; - - architecture Structure of FEE_DATA_OUT_17_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT17_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_17: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT17_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT17_out) - VARIABLE FEEDATAOUT17_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT17_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT17_zd := FEEDATAOUT17_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT17, OutSignalName => "FEEDATAOUT17", OutTemp => FEEDATAOUT17_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT17, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT17_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_16_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_16_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_16_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT16 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT16: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_16_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_16_B; - - architecture Structure of FEE_DATA_OUT_16_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT16_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_16: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT16_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT16_out) - VARIABLE FEEDATAOUT16_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT16_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT16_zd := FEEDATAOUT16_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT16, OutSignalName => "FEEDATAOUT16", OutTemp => FEEDATAOUT16_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT16, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT16_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_15_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_15_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_15_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT15 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT15: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_15_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_15_B; - - architecture Structure of FEE_DATA_OUT_15_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT15_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_15: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT15_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT15_out) - VARIABLE FEEDATAOUT15_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT15_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT15_zd := FEEDATAOUT15_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT15, OutSignalName => "FEEDATAOUT15", OutTemp => FEEDATAOUT15_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT15, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT15_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_14_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_14_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_14_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT14 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT14: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_14_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_14_B; - - architecture Structure of FEE_DATA_OUT_14_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT14_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_14: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT14_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT14_out) - VARIABLE FEEDATAOUT14_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT14_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT14_zd := FEEDATAOUT14_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT14, OutSignalName => "FEEDATAOUT14", OutTemp => FEEDATAOUT14_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT14, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT14_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_13_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_13_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_13_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT13 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT13: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_13_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_13_B; - - architecture Structure of FEE_DATA_OUT_13_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT13_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_13: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT13_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT13_out) - VARIABLE FEEDATAOUT13_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT13_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT13_zd := FEEDATAOUT13_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT13, OutSignalName => "FEEDATAOUT13", OutTemp => FEEDATAOUT13_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT13, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT13_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_12_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_12_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_12_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT12 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT12: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_12_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_12_B; - - architecture Structure of FEE_DATA_OUT_12_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT12_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_12: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT12_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT12_out) - VARIABLE FEEDATAOUT12_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT12_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT12_zd := FEEDATAOUT12_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT12, OutSignalName => "FEEDATAOUT12", OutTemp => FEEDATAOUT12_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT12, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT12_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_11_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_11_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_11_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT11 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT11: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_11_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_11_B; - - architecture Structure of FEE_DATA_OUT_11_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT11_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_11: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT11_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT11_out) - VARIABLE FEEDATAOUT11_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT11_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT11_zd := FEEDATAOUT11_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT11, OutSignalName => "FEEDATAOUT11", OutTemp => FEEDATAOUT11_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT11, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT11_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_10_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_10_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_10_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT10 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT10: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_10_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_10_B; - - architecture Structure of FEE_DATA_OUT_10_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT10_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_10: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT10_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT10_out) - VARIABLE FEEDATAOUT10_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT10_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT10_zd := FEEDATAOUT10_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT10, OutSignalName => "FEEDATAOUT10", OutTemp => FEEDATAOUT10_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT10, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT10_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_9_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_9_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_9_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT9 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT9: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_9_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_9_B; - - architecture Structure of FEE_DATA_OUT_9_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT9_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_9: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT9_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT9_out) - VARIABLE FEEDATAOUT9_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT9_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT9_zd := FEEDATAOUT9_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT9, OutSignalName => "FEEDATAOUT9", OutTemp => FEEDATAOUT9_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT9, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT9_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_8_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_8_B; - - architecture Structure of FEE_DATA_OUT_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT8_out) - VARIABLE FEEDATAOUT8_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT8_zd := FEEDATAOUT8_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT8, OutSignalName => "FEEDATAOUT8", OutTemp => FEEDATAOUT8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT8, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_7_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_7_B; - - architecture Structure of FEE_DATA_OUT_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT7_out) - VARIABLE FEEDATAOUT7_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT7_zd := FEEDATAOUT7_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT7, OutSignalName => "FEEDATAOUT7", OutTemp => FEEDATAOUT7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT7, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_6_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_6_B; - - architecture Structure of FEE_DATA_OUT_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT6_out) - VARIABLE FEEDATAOUT6_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT6_zd := FEEDATAOUT6_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT6, OutSignalName => "FEEDATAOUT6", OutTemp => FEEDATAOUT6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT6, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_5_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_5_B; - - architecture Structure of FEE_DATA_OUT_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT5_out) - VARIABLE FEEDATAOUT5_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT5_zd := FEEDATAOUT5_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT5, OutSignalName => "FEEDATAOUT5", OutTemp => FEEDATAOUT5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT5, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_4_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_4_B; - - architecture Structure of FEE_DATA_OUT_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT4_out) - VARIABLE FEEDATAOUT4_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT4_zd := FEEDATAOUT4_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT4, OutSignalName => "FEEDATAOUT4", OutTemp => FEEDATAOUT4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT4, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_3_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_3_B; - - architecture Structure of FEE_DATA_OUT_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT3_out) - VARIABLE FEEDATAOUT3_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT3_zd := FEEDATAOUT3_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT3, OutSignalName => "FEEDATAOUT3", OutTemp => FEEDATAOUT3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT3, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_2_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_2_B; - - architecture Structure of FEE_DATA_OUT_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT2_out) - VARIABLE FEEDATAOUT2_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT2_zd := FEEDATAOUT2_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT2, OutSignalName => "FEEDATAOUT2", OutTemp => FEEDATAOUT2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT2, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_1_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_1_B; - - architecture Structure of FEE_DATA_OUT_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT1_out) - VARIABLE FEEDATAOUT1_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT1_zd := FEEDATAOUT1_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT1, OutSignalName => "FEEDATAOUT1", OutTemp => FEEDATAOUT1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT1, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity FEE_DATA_OUT_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity FEE_DATA_OUT_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "FEE_DATA_OUT_0_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_FEEDATAOUT0 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; FEEDATAOUT0: out Std_logic); - - ATTRIBUTE Vital_Level0 OF FEE_DATA_OUT_0_B : ENTITY IS TRUE; - - end FEE_DATA_OUT_0_B; - - architecture Structure of FEE_DATA_OUT_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal FEEDATAOUT0_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - FEE_DATA_OUT_pad_0: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>FEEDATAOUT0_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, FEEDATAOUT0_out) - VARIABLE FEEDATAOUT0_zd : std_logic := 'X'; - VARIABLE FEEDATAOUT0_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - FEEDATAOUT0_zd := FEEDATAOUT0_out; - - VitalPathDelay01 ( - - OutSignal => FEEDATAOUT0, OutSignalName => "FEEDATAOUT0", OutTemp => FEEDATAOUT0_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_FEEDATAOUT0, - PathCondition => TRUE)), - GlitchData => FEEDATAOUT0_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LVL1_INVALID_TRG_INB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity LVL1_INVALID_TRG_INB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LVL1_INVALID_TRG_INB"; - - tipd_LVL1INVALIDTRGIN : VitalDelayType01 := (0 ns, 0 ns); - tpd_LVL1INVALIDTRGIN_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LVL1INVALIDTRGIN : VitalDelayType := 0 ns; - tpw_LVL1INVALIDTRGIN_posedge : VitalDelayType := 0 ns; - tpw_LVL1INVALIDTRGIN_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; LVL1INVALIDTRGIN: in Std_logic); - - ATTRIBUTE Vital_Level0 OF LVL1_INVALID_TRG_INB : ENTITY IS TRUE; - - end LVL1_INVALID_TRG_INB; - - architecture Structure of LVL1_INVALID_TRG_INB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal LVL1INVALIDTRGIN_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - LVL1_INVALID_TRG_IN_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>LVL1INVALIDTRGIN_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(LVL1INVALIDTRGIN_ipd, LVL1INVALIDTRGIN, tipd_LVL1INVALIDTRGIN); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, LVL1INVALIDTRGIN_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_LVL1INVALIDTRGIN_LVL1INVALIDTRGIN : x01 := '0'; - VARIABLE periodcheckinfo_LVL1INVALIDTRGIN : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => LVL1INVALIDTRGIN_ipd, - TestSignalName => "LVL1INVALIDTRGIN", - Period => tperiod_LVL1INVALIDTRGIN, - PulseWidthHigh => tpw_LVL1INVALIDTRGIN_posedge, - PulseWidthLow => tpw_LVL1INVALIDTRGIN_negedge, - PeriodData => periodcheckinfo_LVL1INVALIDTRGIN, - Violation => tviol_LVL1INVALIDTRGIN_LVL1INVALIDTRGIN, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => LVL1INVALIDTRGIN_ipd'last_event, - PathDelay => tpd_LVL1INVALIDTRGIN_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LVL1_INVALID_TRG_IN_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity LVL1_INVALID_TRG_IN_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LVL1_INVALID_TRG_IN_MGIOL"; - - tipd_DI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_INFF : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI_CLK : VitalDelayType := 0 ns; - tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - - ATTRIBUTE Vital_Level0 OF LVL1_INVALID_TRG_IN_MGIOL : ENTITY IS TRUE; - - end LVL1_INVALID_TRG_IN_MGIOL; - - architecture Structure of LVL1_INVALID_TRG_IN_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI_ipd : std_logic := 'X'; - signal DI_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal INFF_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component smuxlregsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0: smuxlregsre - port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI_ipd, DI, tipd_DI); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out) - VARIABLE INFF_zd : std_logic := 'X'; - VARIABLE INFF_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI_CLK : x01 := '0'; - VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI_dly, - TestSignalName => "DI", - TestDelay => tisd_DI_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI_CLK_noedge_posedge, - SetupLow => tsetup_DI_CLK_noedge_posedge, - HoldHigh => thold_DI_CLK_noedge_posedge, - HoldLow => thold_DI_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI_CLK_TimingDatash, - Violation => tviol_DI_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - INFF_zd := INFF_out; - - VitalPathDelay01 ( - OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_INFF, - PathCondition => TRUE)), - GlitchData => INFF_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LVL1_TRG_DATA_VALID_INB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity LVL1_TRG_DATA_VALID_INB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LVL1_TRG_DATA_VALID_INB"; - - tipd_LVL1TRGDATAVALIDIN : VitalDelayType01 := (0 ns, 0 ns); - tpd_LVL1TRGDATAVALIDIN_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_LVL1TRGDATAVALIDIN : VitalDelayType := 0 ns; - tpw_LVL1TRGDATAVALIDIN_posedge : VitalDelayType := 0 ns; - tpw_LVL1TRGDATAVALIDIN_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; LVL1TRGDATAVALIDIN: in Std_logic); - - ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALID_INB : ENTITY IS TRUE; - - end LVL1_TRG_DATA_VALID_INB; - - architecture Structure of LVL1_TRG_DATA_VALID_INB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal LVL1TRGDATAVALIDIN_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - LVL1_TRG_DATA_VALID_IN_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>LVL1TRGDATAVALIDIN_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - - VitalWireDelay(LVL1TRGDATAVALIDIN_ipd, LVL1TRGDATAVALIDIN, tipd_LVL1TRGDATAVALIDIN); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, LVL1TRGDATAVALIDIN_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_LVL1TRGDATAVALIDIN_LVL1TRGDATAVALIDIN : x01 := '0'; - VARIABLE periodcheckinfo_LVL1TRGDATAVALIDIN : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => LVL1TRGDATAVALIDIN_ipd, - TestSignalName => "LVL1TRGDATAVALIDIN", - Period => tperiod_LVL1TRGDATAVALIDIN, - PulseWidthHigh => tpw_LVL1TRGDATAVALIDIN_posedge, - PulseWidthLow => tpw_LVL1TRGDATAVALIDIN_negedge, - PeriodData => periodcheckinfo_LVL1TRGDATAVALIDIN, - Violation => tviol_LVL1TRGDATAVALIDIN_LVL1TRGDATAVALIDIN, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => ( - 0 => (InputChangeTime => LVL1TRGDATAVALIDIN_ipd'last_event, - PathDelay => tpd_LVL1TRGDATAVALIDIN_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity LVL1_TRG_DATA_VALID_IN_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity LVL1_TRG_DATA_VALID_IN_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "LVL1_TRG_DATA_VALID_IN_MGIOL"; - - tipd_DI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_INFF : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI_CLK : VitalDelayType := 0 ns; - tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - - ATTRIBUTE Vital_Level0 OF LVL1_TRG_DATA_VALID_IN_MGIOL : ENTITY IS TRUE; - - end LVL1_TRG_DATA_VALID_IN_MGIOL; - - architecture Structure of LVL1_TRG_DATA_VALID_IN_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI_ipd : std_logic := 'X'; - signal DI_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal INFF_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component smuxlregsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0: smuxlregsre - port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI_ipd, DI, tipd_DI); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out) - VARIABLE INFF_zd : std_logic := 'X'; - VARIABLE INFF_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI_CLK : x01 := '0'; - VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI_dly, - TestSignalName => "DI", - TestDelay => tisd_DI_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI_CLK_noedge_posedge, - SetupLow => tsetup_DI_CLK_noedge_posedge, - HoldHigh => thold_DI_CLK_noedge_posedge, - HoldLow => thold_DI_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI_CLK_TimingDatash, - Violation => tviol_DI_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - INFF_zd := INFF_out; - - VitalPathDelay01 ( - OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_INFF, - PathCondition => TRUE)), - GlitchData => INFF_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_empty1B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_empty1B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_empty1B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifoempty1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifoempty1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_empty1B : ENTITY IS TRUE; - - end fifo_empty1B; - - architecture Structure of fifo_empty1B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifoempty1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_empty1_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifoempty1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifoempty1_out) - VARIABLE fifoempty1_zd : std_logic := 'X'; - VARIABLE fifoempty1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifoempty1_zd := fifoempty1_out; - - VitalPathDelay01 ( - - OutSignal => fifoempty1, OutSignalName => "fifoempty1", OutTemp => fifoempty1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifoempty1, - PathCondition => TRUE)), - GlitchData => fifoempty1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_rdenB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_rdenB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_rdenB"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fiforden : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fiforden: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_rdenB : ENTITY IS TRUE; - - end fifo_rdenB; - - architecture Structure of fifo_rdenB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fiforden_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_rden_pad: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fiforden_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fiforden_out) - VARIABLE fiforden_zd : std_logic := 'X'; - VARIABLE fiforden_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fiforden_zd := fiforden_out; - - VitalPathDelay01 ( - OutSignal => fiforden, OutSignalName => "fiforden", OutTemp => fiforden_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fiforden, - PathCondition => TRUE)), - GlitchData => fiforden_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_31_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_31_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_31_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout31 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout31: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_31_B : ENTITY IS TRUE; - - end fifo_data_out_31_B; - - architecture Structure of fifo_data_out_31_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout31_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_31: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout31_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout31_out) - VARIABLE fifodataout31_zd : std_logic := 'X'; - VARIABLE fifodataout31_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout31_zd := fifodataout31_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout31, OutSignalName => "fifodataout31", OutTemp => fifodataout31_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout31, - PathCondition => TRUE)), - GlitchData => fifodataout31_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_30_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_30_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_30_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout30 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout30: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_30_B : ENTITY IS TRUE; - - end fifo_data_out_30_B; - - architecture Structure of fifo_data_out_30_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout30_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_30: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout30_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout30_out) - VARIABLE fifodataout30_zd : std_logic := 'X'; - VARIABLE fifodataout30_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout30_zd := fifodataout30_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout30, OutSignalName => "fifodataout30", OutTemp => fifodataout30_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout30, - PathCondition => TRUE)), - GlitchData => fifodataout30_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_29_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_29_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_29_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout29 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout29: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_29_B : ENTITY IS TRUE; - - end fifo_data_out_29_B; - - architecture Structure of fifo_data_out_29_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout29_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_29: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout29_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout29_out) - VARIABLE fifodataout29_zd : std_logic := 'X'; - VARIABLE fifodataout29_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout29_zd := fifodataout29_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout29, OutSignalName => "fifodataout29", OutTemp => fifodataout29_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout29, - PathCondition => TRUE)), - GlitchData => fifodataout29_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_28_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_28_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_28_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout28 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout28: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_28_B : ENTITY IS TRUE; - - end fifo_data_out_28_B; - - architecture Structure of fifo_data_out_28_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout28_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_28: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout28_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout28_out) - VARIABLE fifodataout28_zd : std_logic := 'X'; - VARIABLE fifodataout28_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout28_zd := fifodataout28_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout28, OutSignalName => "fifodataout28", OutTemp => fifodataout28_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout28, - PathCondition => TRUE)), - GlitchData => fifodataout28_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_27_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_27_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_27_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout27 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout27: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_27_B : ENTITY IS TRUE; - - end fifo_data_out_27_B; - - architecture Structure of fifo_data_out_27_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout27_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_27: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout27_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout27_out) - VARIABLE fifodataout27_zd : std_logic := 'X'; - VARIABLE fifodataout27_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout27_zd := fifodataout27_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout27, OutSignalName => "fifodataout27", OutTemp => fifodataout27_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout27, - PathCondition => TRUE)), - GlitchData => fifodataout27_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_26_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_26_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_26_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout26 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout26: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_26_B : ENTITY IS TRUE; - - end fifo_data_out_26_B; - - architecture Structure of fifo_data_out_26_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout26_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_26: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout26_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout26_out) - VARIABLE fifodataout26_zd : std_logic := 'X'; - VARIABLE fifodataout26_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout26_zd := fifodataout26_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout26, OutSignalName => "fifodataout26", OutTemp => fifodataout26_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout26, - PathCondition => TRUE)), - GlitchData => fifodataout26_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_25_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_25_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_25_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout25 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout25: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_25_B : ENTITY IS TRUE; - - end fifo_data_out_25_B; - - architecture Structure of fifo_data_out_25_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout25_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_25: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout25_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout25_out) - VARIABLE fifodataout25_zd : std_logic := 'X'; - VARIABLE fifodataout25_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout25_zd := fifodataout25_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout25, OutSignalName => "fifodataout25", OutTemp => fifodataout25_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout25, - PathCondition => TRUE)), - GlitchData => fifodataout25_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_24_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_24_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_24_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout24 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout24: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_24_B : ENTITY IS TRUE; - - end fifo_data_out_24_B; - - architecture Structure of fifo_data_out_24_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout24_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_24: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout24_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout24_out) - VARIABLE fifodataout24_zd : std_logic := 'X'; - VARIABLE fifodataout24_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout24_zd := fifodataout24_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout24, OutSignalName => "fifodataout24", OutTemp => fifodataout24_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout24, - PathCondition => TRUE)), - GlitchData => fifodataout24_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_23_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_23_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_23_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout23 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout23: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_23_B : ENTITY IS TRUE; - - end fifo_data_out_23_B; - - architecture Structure of fifo_data_out_23_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout23_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_23: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout23_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout23_out) - VARIABLE fifodataout23_zd : std_logic := 'X'; - VARIABLE fifodataout23_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout23_zd := fifodataout23_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout23, OutSignalName => "fifodataout23", OutTemp => fifodataout23_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout23, - PathCondition => TRUE)), - GlitchData => fifodataout23_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_22_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_22_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_22_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout22 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout22: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_22_B : ENTITY IS TRUE; - - end fifo_data_out_22_B; - - architecture Structure of fifo_data_out_22_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout22_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_22: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout22_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout22_out) - VARIABLE fifodataout22_zd : std_logic := 'X'; - VARIABLE fifodataout22_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout22_zd := fifodataout22_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout22, OutSignalName => "fifodataout22", OutTemp => fifodataout22_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout22, - PathCondition => TRUE)), - GlitchData => fifodataout22_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_21_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_21_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_21_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout21 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout21: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_21_B : ENTITY IS TRUE; - - end fifo_data_out_21_B; - - architecture Structure of fifo_data_out_21_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout21_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_21: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout21_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout21_out) - VARIABLE fifodataout21_zd : std_logic := 'X'; - VARIABLE fifodataout21_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout21_zd := fifodataout21_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout21, OutSignalName => "fifodataout21", OutTemp => fifodataout21_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout21, - PathCondition => TRUE)), - GlitchData => fifodataout21_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_20_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_20_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_20_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout20 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout20: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_20_B : ENTITY IS TRUE; - - end fifo_data_out_20_B; - - architecture Structure of fifo_data_out_20_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout20_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_20: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout20_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout20_out) - VARIABLE fifodataout20_zd : std_logic := 'X'; - VARIABLE fifodataout20_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout20_zd := fifodataout20_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout20, OutSignalName => "fifodataout20", OutTemp => fifodataout20_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout20, - PathCondition => TRUE)), - GlitchData => fifodataout20_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_19_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_19_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_19_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout19 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout19: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_19_B : ENTITY IS TRUE; - - end fifo_data_out_19_B; - - architecture Structure of fifo_data_out_19_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout19_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_19: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout19_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout19_out) - VARIABLE fifodataout19_zd : std_logic := 'X'; - VARIABLE fifodataout19_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout19_zd := fifodataout19_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout19, OutSignalName => "fifodataout19", OutTemp => fifodataout19_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout19, - PathCondition => TRUE)), - GlitchData => fifodataout19_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_18_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_18_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_18_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout18 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout18: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_18_B : ENTITY IS TRUE; - - end fifo_data_out_18_B; - - architecture Structure of fifo_data_out_18_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout18_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_18: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout18_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout18_out) - VARIABLE fifodataout18_zd : std_logic := 'X'; - VARIABLE fifodataout18_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout18_zd := fifodataout18_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout18, OutSignalName => "fifodataout18", OutTemp => fifodataout18_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout18, - PathCondition => TRUE)), - GlitchData => fifodataout18_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_17_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_17_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_17_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout17 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout17: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_17_B : ENTITY IS TRUE; - - end fifo_data_out_17_B; - - architecture Structure of fifo_data_out_17_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout17_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_17: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout17_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout17_out) - VARIABLE fifodataout17_zd : std_logic := 'X'; - VARIABLE fifodataout17_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout17_zd := fifodataout17_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout17, OutSignalName => "fifodataout17", OutTemp => fifodataout17_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout17, - PathCondition => TRUE)), - GlitchData => fifodataout17_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_16_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_16_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_16_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout16 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout16: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_16_B : ENTITY IS TRUE; - - end fifo_data_out_16_B; - - architecture Structure of fifo_data_out_16_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout16_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_16: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout16_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout16_out) - VARIABLE fifodataout16_zd : std_logic := 'X'; - VARIABLE fifodataout16_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout16_zd := fifodataout16_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout16, OutSignalName => "fifodataout16", OutTemp => fifodataout16_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout16, - PathCondition => TRUE)), - GlitchData => fifodataout16_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_15_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_15_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_15_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout15 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout15: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_15_B : ENTITY IS TRUE; - - end fifo_data_out_15_B; - - architecture Structure of fifo_data_out_15_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout15_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_15: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout15_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout15_out) - VARIABLE fifodataout15_zd : std_logic := 'X'; - VARIABLE fifodataout15_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout15_zd := fifodataout15_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout15, OutSignalName => "fifodataout15", OutTemp => fifodataout15_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout15, - PathCondition => TRUE)), - GlitchData => fifodataout15_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_14_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_14_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_14_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout14 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout14: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_14_B : ENTITY IS TRUE; - - end fifo_data_out_14_B; - - architecture Structure of fifo_data_out_14_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout14_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_14: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout14_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout14_out) - VARIABLE fifodataout14_zd : std_logic := 'X'; - VARIABLE fifodataout14_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout14_zd := fifodataout14_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout14, OutSignalName => "fifodataout14", OutTemp => fifodataout14_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout14, - PathCondition => TRUE)), - GlitchData => fifodataout14_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_13_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_13_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_13_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout13 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout13: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_13_B : ENTITY IS TRUE; - - end fifo_data_out_13_B; - - architecture Structure of fifo_data_out_13_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout13_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_13: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout13_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout13_out) - VARIABLE fifodataout13_zd : std_logic := 'X'; - VARIABLE fifodataout13_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout13_zd := fifodataout13_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout13, OutSignalName => "fifodataout13", OutTemp => fifodataout13_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout13, - PathCondition => TRUE)), - GlitchData => fifodataout13_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_12_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_12_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_12_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout12 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout12: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_12_B : ENTITY IS TRUE; - - end fifo_data_out_12_B; - - architecture Structure of fifo_data_out_12_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout12_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_12: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout12_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout12_out) - VARIABLE fifodataout12_zd : std_logic := 'X'; - VARIABLE fifodataout12_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout12_zd := fifodataout12_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout12, OutSignalName => "fifodataout12", OutTemp => fifodataout12_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout12, - PathCondition => TRUE)), - GlitchData => fifodataout12_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_11_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_11_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_11_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout11 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout11: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_11_B : ENTITY IS TRUE; - - end fifo_data_out_11_B; - - architecture Structure of fifo_data_out_11_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout11_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_11: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout11_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout11_out) - VARIABLE fifodataout11_zd : std_logic := 'X'; - VARIABLE fifodataout11_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout11_zd := fifodataout11_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout11, OutSignalName => "fifodataout11", OutTemp => fifodataout11_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout11, - PathCondition => TRUE)), - GlitchData => fifodataout11_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_10_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_10_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_10_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout10 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout10: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_10_B : ENTITY IS TRUE; - - end fifo_data_out_10_B; - - architecture Structure of fifo_data_out_10_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout10_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_10: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout10_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout10_out) - VARIABLE fifodataout10_zd : std_logic := 'X'; - VARIABLE fifodataout10_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout10_zd := fifodataout10_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout10, OutSignalName => "fifodataout10", OutTemp => fifodataout10_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout10, - PathCondition => TRUE)), - GlitchData => fifodataout10_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_9_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_9_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_9_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout9 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout9: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_9_B : ENTITY IS TRUE; - - end fifo_data_out_9_B; - - architecture Structure of fifo_data_out_9_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout9_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_9: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout9_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout9_out) - VARIABLE fifodataout9_zd : std_logic := 'X'; - VARIABLE fifodataout9_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout9_zd := fifodataout9_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout9, OutSignalName => "fifodataout9", OutTemp => fifodataout9_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout9, - PathCondition => TRUE)), - GlitchData => fifodataout9_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_8_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_8_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_8_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout8 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout8: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_8_B : ENTITY IS TRUE; - - end fifo_data_out_8_B; - - architecture Structure of fifo_data_out_8_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout8_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_8: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout8_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout8_out) - VARIABLE fifodataout8_zd : std_logic := 'X'; - VARIABLE fifodataout8_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout8_zd := fifodataout8_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout8, OutSignalName => "fifodataout8", OutTemp => fifodataout8_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout8, - PathCondition => TRUE)), - GlitchData => fifodataout8_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_7_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_7_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_7_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout7 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout7: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_7_B : ENTITY IS TRUE; - - end fifo_data_out_7_B; - - architecture Structure of fifo_data_out_7_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout7_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_7: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout7_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout7_out) - VARIABLE fifodataout7_zd : std_logic := 'X'; - VARIABLE fifodataout7_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout7_zd := fifodataout7_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout7, OutSignalName => "fifodataout7", OutTemp => fifodataout7_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout7, - PathCondition => TRUE)), - GlitchData => fifodataout7_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_6_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_6_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_6_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout6 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout6: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_6_B : ENTITY IS TRUE; - - end fifo_data_out_6_B; - - architecture Structure of fifo_data_out_6_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout6_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_6: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout6_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout6_out) - VARIABLE fifodataout6_zd : std_logic := 'X'; - VARIABLE fifodataout6_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout6_zd := fifodataout6_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout6, OutSignalName => "fifodataout6", OutTemp => fifodataout6_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout6, - PathCondition => TRUE)), - GlitchData => fifodataout6_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_5_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_5_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_5_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout5 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout5: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_5_B : ENTITY IS TRUE; - - end fifo_data_out_5_B; - - architecture Structure of fifo_data_out_5_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout5_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_5: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout5_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout5_out) - VARIABLE fifodataout5_zd : std_logic := 'X'; - VARIABLE fifodataout5_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout5_zd := fifodataout5_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout5, OutSignalName => "fifodataout5", OutTemp => fifodataout5_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout5, - PathCondition => TRUE)), - GlitchData => fifodataout5_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_4_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_4_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_4_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout4 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout4: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_4_B : ENTITY IS TRUE; - - end fifo_data_out_4_B; - - architecture Structure of fifo_data_out_4_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout4_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_4: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout4_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout4_out) - VARIABLE fifodataout4_zd : std_logic := 'X'; - VARIABLE fifodataout4_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout4_zd := fifodataout4_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout4, OutSignalName => "fifodataout4", OutTemp => fifodataout4_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout4, - PathCondition => TRUE)), - GlitchData => fifodataout4_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_3_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_3_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_3_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout3 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout3: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_3_B : ENTITY IS TRUE; - - end fifo_data_out_3_B; - - architecture Structure of fifo_data_out_3_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout3_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_3: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout3_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout3_out) - VARIABLE fifodataout3_zd : std_logic := 'X'; - VARIABLE fifodataout3_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout3_zd := fifodataout3_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout3, OutSignalName => "fifodataout3", OutTemp => fifodataout3_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout3, - PathCondition => TRUE)), - GlitchData => fifodataout3_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_2_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout2 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout2: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_2_B : ENTITY IS TRUE; - - end fifo_data_out_2_B; - - architecture Structure of fifo_data_out_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout2_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_2: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout2_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout2_out) - VARIABLE fifodataout2_zd : std_logic := 'X'; - VARIABLE fifodataout2_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout2_zd := fifodataout2_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout2, OutSignalName => "fifodataout2", OutTemp => fifodataout2_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout2, - PathCondition => TRUE)), - GlitchData => fifodataout2_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity fifo_data_out_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_data_out_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_data_out_1_B"; - - tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); - tpd_PADDO_fifodataout1 : VitalDelayType01 := (0 ns, 0 ns)); - - port (PADDO: in Std_logic; fifodataout1: out Std_logic); - - ATTRIBUTE Vital_Level0 OF fifo_data_out_1_B : ENTITY IS TRUE; - - end fifo_data_out_1_B; - - architecture Structure of fifo_data_out_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDO_ipd : std_logic := 'X'; - signal fifodataout1_out : std_logic := 'X'; - - component sapiobuf0249 - port (I: in Std_logic; PAD: out Std_logic); - end component; - begin - fifo_data_out_pad_1: sapiobuf0249 - port map (I=>PADDO_ipd, PAD=>fifodataout1_out); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); - END BLOCK; - - VitalBehavior : PROCESS (PADDO_ipd, fifodataout1_out) - VARIABLE fifodataout1_zd : std_logic := 'X'; - VARIABLE fifodataout1_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - fifodataout1_zd := fifodataout1_out; - - VitalPathDelay01 ( - - OutSignal => fifodataout1, OutSignalName => "fifodataout1", OutTemp => fifodataout1_zd, - Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, - PathDelay => tpd_PADDO_fifodataout1, - PathCondition => TRUE)), - GlitchData => fifodataout1_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trig_2_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trig_2_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trig_2_B"; - - tipd_trig2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_trig2_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_trig2 : VitalDelayType := 0 ns; - tpw_trig2_posedge : VitalDelayType := 0 ns; - tpw_trig2_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; trig2: in Std_logic); - - ATTRIBUTE Vital_Level0 OF trig_2_B : ENTITY IS TRUE; - - end trig_2_B; - - architecture Structure of trig_2_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal trig2_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - trig_pad_2: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>trig2_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(trig2_ipd, trig2, tipd_trig2); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, trig2_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_trig2_trig2 : x01 := '0'; - VARIABLE periodcheckinfo_trig2 : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => trig2_ipd, - TestSignalName => "trig2", - Period => tperiod_trig2, - PulseWidthHigh => tpw_trig2_posedge, - PulseWidthLow => tpw_trig2_negedge, - PeriodData => periodcheckinfo_trig2, - Violation => tviol_trig2_trig2, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => trig2_ipd'last_event, - PathDelay => tpd_trig2_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trig_1_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trig_1_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trig_1_B"; - - tipd_trig1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_trig1_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_trig1 : VitalDelayType := 0 ns; - tpw_trig1_posedge : VitalDelayType := 0 ns; - tpw_trig1_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; trig1: in Std_logic); - - ATTRIBUTE Vital_Level0 OF trig_1_B : ENTITY IS TRUE; - - end trig_1_B; - - architecture Structure of trig_1_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal trig1_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - trig_pad_1: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>trig1_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(trig1_ipd, trig1, tipd_trig1); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, trig1_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_trig1_trig1 : x01 := '0'; - VARIABLE periodcheckinfo_trig1 : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => trig1_ipd, - TestSignalName => "trig1", - Period => tperiod_trig1, - PulseWidthHigh => tpw_trig1_posedge, - PulseWidthLow => tpw_trig1_negedge, - PeriodData => periodcheckinfo_trig1, - Violation => tviol_trig1_trig1, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => trig1_ipd'last_event, - PathDelay => tpd_trig1_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity trig_0_B - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity trig_0_B is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "trig_0_B"; - - tipd_trig0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_trig0_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_trig0 : VitalDelayType := 0 ns; - tpw_trig0_posedge : VitalDelayType := 0 ns; - tpw_trig0_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; trig0: in Std_logic); - - ATTRIBUTE Vital_Level0 OF trig_0_B : ENTITY IS TRUE; - - end trig_0_B; - - architecture Structure of trig_0_B is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal trig0_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - trig_pad_0: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>trig0_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(trig0_ipd, trig0, tipd_trig0); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, trig0_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_trig0_trig0 : x01 := '0'; - VARIABLE periodcheckinfo_trig0 : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => trig0_ipd, - TestSignalName => "trig0", - Period => tperiod_trig0, - PulseWidthHigh => tpw_trig0_posedge, - PulseWidthLow => tpw_trig0_negedge, - PeriodData => periodcheckinfo_trig0, - Violation => tviol_trig0_trig0, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => trig0_ipd'last_event, - PathDelay => tpd_trig0_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity reset_dcB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity reset_dcB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "reset_dcB"; - - tipd_resetdc : VitalDelayType01 := (0 ns, 0 ns); - tpd_resetdc_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_resetdc : VitalDelayType := 0 ns; - tpw_resetdc_posedge : VitalDelayType := 0 ns; - tpw_resetdc_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; resetdc: in Std_logic); - - ATTRIBUTE Vital_Level0 OF reset_dcB : ENTITY IS TRUE; - - end reset_dcB; - - architecture Structure of reset_dcB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal resetdc_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - reset_dc_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>resetdc_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(resetdc_ipd, resetdc, tipd_resetdc); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, resetdc_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_resetdc_resetdc : x01 := '0'; - VARIABLE periodcheckinfo_resetdc : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => resetdc_ipd, - TestSignalName => "resetdc", - Period => tperiod_resetdc, - PulseWidthHigh => tpw_resetdc_posedge, - PulseWidthLow => tpw_resetdc_negedge, - PeriodData => periodcheckinfo_resetdc, - Violation => tviol_resetdc_resetdc, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => resetdc_ipd'last_event, - PathDelay => tpd_resetdc_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity reset_dc_MGIOL - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity reset_dc_MGIOL is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "reset_dc_MGIOL"; - - tipd_DI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLK_INFF : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLK : VitalDelayType := 0 ns; - tisd_DI_CLK : VitalDelayType := 0 ns; - tsetup_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - thold_DI_CLK_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLK : VitalDelayType := 0 ns; - tpw_CLK_posedge : VitalDelayType := 0 ns; - tpw_CLK_negedge : VitalDelayType := 0 ns); - - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - - ATTRIBUTE Vital_Level0 OF reset_dc_MGIOL : ENTITY IS TRUE; - - end reset_dc_MGIOL; - - architecture Structure of reset_dc_MGIOL is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DI_ipd : std_logic := 'X'; - signal DI_dly : std_logic := 'X'; - signal CLK_ipd : std_logic := 'X'; - signal CLK_dly : std_logic := 'X'; - signal INFF_out : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component smuxlregsre - port (D0: in Std_logic; SP: in Std_logic; CK: in Std_logic; - LSR: in Std_logic; Q: out Std_logic); - end component; - begin - reset_dl_0io_1: smuxlregsre - port map (D0=>DI_dly, SP=>VCCI, CK=>CLK_dly, LSR=>GNDI, Q=>INFF_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DI_ipd, DI, tipd_DI); - VitalWireDelay(CLK_ipd, CLK, tipd_CLK); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DI_dly, DI_ipd, tisd_DI_CLK); - VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); - END BLOCK; - - VitalBehavior : PROCESS (DI_dly, CLK_dly, INFF_out) - VARIABLE INFF_zd : std_logic := 'X'; - VARIABLE INFF_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DI_CLK : x01 := '0'; - VARIABLE DI_CLK_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLK_CLK : x01 := '0'; - VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DI_dly, - TestSignalName => "DI", - TestDelay => tisd_DI_CLK, - RefSignal => CLK_dly, - RefSignalName => "CLK", - RefDelay => ticd_CLK, - SetupHigh => tsetup_DI_CLK_noedge_posedge, - SetupLow => tsetup_DI_CLK_noedge_posedge, - HoldHigh => thold_DI_CLK_noedge_posedge, - HoldLow => thold_DI_CLK_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DI_CLK_TimingDatash, - Violation => tviol_DI_CLK, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLK_ipd, - TestSignalName => "CLK", - Period => tperiod_CLK, - PulseWidthHigh => tpw_CLK_posedge, - PulseWidthLow => tpw_CLK_negedge, - PeriodData => periodcheckinfo_CLK, - Violation => tviol_CLK_CLK, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - INFF_zd := INFF_out; - - VitalPathDelay01 ( - OutSignal => INFF, OutSignalName => "INFF", OutTemp => INFF_zd, - Paths => (0 => (InputChangeTime => CLK_dly'last_event, - PathDelay => tpd_CLK_INFF, - PathCondition => TRUE)), - GlitchData => INFF_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity rd_clkB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity rd_clkB is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "rd_clkB"; - - tipd_rdclk : VitalDelayType01 := (0 ns, 0 ns); - tpd_rdclk_PADDI : VitalDelayType01 := (0 ns, 0 ns); - tperiod_rdclk : VitalDelayType := 0 ns; - tpw_rdclk_posedge : VitalDelayType := 0 ns; - tpw_rdclk_negedge : VitalDelayType := 0 ns); - - port (PADDI: out Std_logic; rdclk: in Std_logic); - - ATTRIBUTE Vital_Level0 OF rd_clkB : ENTITY IS TRUE; - - end rd_clkB; - - architecture Structure of rd_clkB is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal PADDI_out : std_logic := 'X'; - signal rdclk_ipd : std_logic := 'X'; - - component sapiobuf0252 - port (Z: out Std_logic; PAD: in Std_logic); - end component; - begin - rd_clk_pad: sapiobuf0252 - port map (Z=>PADDI_out, PAD=>rdclk_ipd); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(rdclk_ipd, rdclk, tipd_rdclk); - END BLOCK; - - VitalBehavior : PROCESS (PADDI_out, rdclk_ipd) - VARIABLE PADDI_zd : std_logic := 'X'; - VARIABLE PADDI_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_rdclk_rdclk : x01 := '0'; - VARIABLE periodcheckinfo_rdclk : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalPeriodPulseCheck ( - TestSignal => rdclk_ipd, - TestSignalName => "rdclk", - Period => tperiod_rdclk, - PulseWidthHigh => tpw_rdclk_posedge, - PulseWidthLow => tpw_rdclk_negedge, - PeriodData => periodcheckinfo_rdclk, - Violation => tviol_rdclk_rdclk, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - PADDI_zd := PADDI_out; - - VitalPathDelay01 ( - OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, - Paths => (0 => (InputChangeTime => rdclk_ipd'last_event, - PathDelay => tpd_rdclk_PADDI, - PathCondition => TRUE)), - GlitchData => PADDI_GlitchData, - Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity PDPW16KDB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity PDPW16KDB is - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - - ATTRIBUTE Vital_Level0 OF PDPW16KDB : ENTITY IS TRUE; - - end PDPW16KDB; - - architecture Structure of PDPW16KDB is - begin - INST10: PDPW16KD - generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", - CSDECODE_W => "0b001", DATA_WIDTH_R => 36, - DATA_WIDTH_W => 36, GSR => "DISABLED", - INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , INIT_DATA => "STATIC", REGMODE => "NOREG", - RESETMODE => "SYNC") - port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, - DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, - DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, - DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, - DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, - DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, - DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, - ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, - ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, - BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, - CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, - ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, - ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, - ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, - CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, - DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, - DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, - DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, - DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, - DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, - DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, - DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35); - end Structure; - --- entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0" - ; - - tipd_DIA15 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKB : VitalDelayType01 := (0 ns, 0 ns); - tipd_OCEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA17 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA16 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA15 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA14 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA13 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA12 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA11 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA10 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB5 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLKA : VitalDelayType := 0 ns; - tisd_DIA15_CLKA : VitalDelayType := 0 ns; - tsetup_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA13_CLKA : VitalDelayType := 0 ns; - tsetup_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA12_CLKA : VitalDelayType := 0 ns; - tsetup_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA11_CLKA : VitalDelayType := 0 ns; - tsetup_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA9_CLKA : VitalDelayType := 0 ns; - tsetup_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA13_CLKA : VitalDelayType := 0 ns; - tsetup_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA12_CLKA : VitalDelayType := 0 ns; - tsetup_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA11_CLKA : VitalDelayType := 0 ns; - tsetup_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA10_CLKA : VitalDelayType := 0 ns; - tsetup_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA9_CLKA : VitalDelayType := 0 ns; - tsetup_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA8_CLKA : VitalDelayType := 0 ns; - tsetup_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA7_CLKA : VitalDelayType := 0 ns; - tsetup_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA6_CLKA : VitalDelayType := 0 ns; - tsetup_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA5_CLKA : VitalDelayType := 0 ns; - tsetup_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEA_CLKA : VitalDelayType := 0 ns; - tsetup_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - ticd_CLKB : VitalDelayType := 0 ns; - tisd_OCEB_CLKB : VitalDelayType := 0 ns; - tsetup_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEB_CLKB : VitalDelayType := 0 ns; - tsetup_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB5_CLKB : VitalDelayType := 0 ns; - tsetup_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB6_CLKB : VitalDelayType := 0 ns; - tsetup_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB7_CLKB : VitalDelayType := 0 ns; - tsetup_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB8_CLKB : VitalDelayType := 0 ns; - tsetup_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB9_CLKB : VitalDelayType := 0 ns; - tsetup_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB10_CLKB : VitalDelayType := 0 ns; - tsetup_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB11_CLKB : VitalDelayType := 0 ns; - tsetup_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB12_CLKB : VitalDelayType := 0 ns; - tsetup_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB13_CLKB : VitalDelayType := 0 ns; - tsetup_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB6_CLKA : VitalDelayType := 0 ns; - tsetup_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB8_CLKA : VitalDelayType := 0 ns; - tsetup_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB9_CLKA : VitalDelayType := 0 ns; - tsetup_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLKA : VitalDelayType := 0 ns; - tpw_CLKA_posedge : VitalDelayType := 0 ns; - tpw_CLKA_negedge : VitalDelayType := 0 ns; - tperiod_CLKB : VitalDelayType := 0 ns; - tpw_CLKB_posedge : VitalDelayType := 0 ns; - tpw_CLKB_negedge : VitalDelayType := 0 ns); - - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE; - - end genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0; - - - architecture Structure of genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DIA15_ipd : std_logic := 'X'; - signal DIA15_dly : std_logic := 'X'; - signal DIA13_ipd : std_logic := 'X'; - signal DIA13_dly : std_logic := 'X'; - signal DIA12_ipd : std_logic := 'X'; - signal DIA12_dly : std_logic := 'X'; - signal DIA11_ipd : std_logic := 'X'; - signal DIA11_dly : std_logic := 'X'; - signal DIA9_ipd : std_logic := 'X'; - signal DIA9_dly : std_logic := 'X'; - signal ADA13_ipd : std_logic := 'X'; - signal ADA13_dly : std_logic := 'X'; - signal ADA12_ipd : std_logic := 'X'; - signal ADA12_dly : std_logic := 'X'; - signal ADA11_ipd : std_logic := 'X'; - signal ADA11_dly : std_logic := 'X'; - signal ADA10_ipd : std_logic := 'X'; - signal ADA10_dly : std_logic := 'X'; - signal ADA9_ipd : std_logic := 'X'; - signal ADA9_dly : std_logic := 'X'; - signal ADA8_ipd : std_logic := 'X'; - signal ADA8_dly : std_logic := 'X'; - signal ADA7_ipd : std_logic := 'X'; - signal ADA7_dly : std_logic := 'X'; - signal ADA6_ipd : std_logic := 'X'; - signal ADA6_dly : std_logic := 'X'; - signal ADA5_ipd : std_logic := 'X'; - signal ADA5_dly : std_logic := 'X'; - signal DOA17_out : std_logic := 'X'; - signal DOA16_out : std_logic := 'X'; - signal DOA15_out : std_logic := 'X'; - signal DOA14_out : std_logic := 'X'; - signal DOA13_out : std_logic := 'X'; - signal DOA12_out : std_logic := 'X'; - signal DOA11_out : std_logic := 'X'; - signal DOA10_out : std_logic := 'X'; - signal DOA9_out : std_logic := 'X'; - signal DOA8_out : std_logic := 'X'; - signal DOA7_out : std_logic := 'X'; - signal DOA6_out : std_logic := 'X'; - signal DOA5_out : std_logic := 'X'; - signal DOA4_out : std_logic := 'X'; - signal DOA3_out : std_logic := 'X'; - signal DOA2_out : std_logic := 'X'; - signal DOA1_out : std_logic := 'X'; - signal DOA0_out : std_logic := 'X'; - signal CEA_ipd : std_logic := 'X'; - signal CEA_dly : std_logic := 'X'; - signal CLKA_ipd : std_logic := 'X'; - signal CLKA_dly : std_logic := 'X'; - signal CLKB_ipd : std_logic := 'X'; - signal CLKB_dly : std_logic := 'X'; - signal OCEB_ipd : std_logic := 'X'; - signal OCEB_dly : std_logic := 'X'; - signal CEB_ipd : std_logic := 'X'; - signal CEB_dly : std_logic := 'X'; - signal DOB0_out : std_logic := 'X'; - signal DOB1_out : std_logic := 'X'; - signal DOB2_out : std_logic := 'X'; - signal DOB3_out : std_logic := 'X'; - signal DOB4_out : std_logic := 'X'; - signal DOB5_out : std_logic := 'X'; - signal ADB5_ipd : std_logic := 'X'; - signal ADB5_dly : std_logic := 'X'; - signal ADB6_ipd : std_logic := 'X'; - signal ADB6_dly : std_logic := 'X'; - signal ADB7_ipd : std_logic := 'X'; - signal ADB7_dly : std_logic := 'X'; - signal ADB8_ipd : std_logic := 'X'; - signal ADB8_dly : std_logic := 'X'; - signal ADB9_ipd : std_logic := 'X'; - signal ADB9_dly : std_logic := 'X'; - signal ADB10_ipd : std_logic := 'X'; - signal ADB10_dly : std_logic := 'X'; - signal ADB11_ipd : std_logic := 'X'; - signal ADB11_dly : std_logic := 'X'; - signal ADB12_ipd : std_logic := 'X'; - signal ADB12_dly : std_logic := 'X'; - signal ADB13_ipd : std_logic := 'X'; - signal ADB13_dly : std_logic := 'X'; - signal DIB6_ipd : std_logic := 'X'; - signal DIB6_dly : std_logic := 'X'; - signal DIB8_ipd : std_logic := 'X'; - signal DIB8_dly : std_logic := 'X'; - signal DIB9_ipd : std_logic := 'X'; - signal DIB9_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component PDPW16KDB - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KDB - port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, - CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, - CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, - BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, - DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, - DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, - DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, - DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, - DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, - DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, - DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, - DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, - ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, - ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, - ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, - ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, - ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, - ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, - ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, - DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, - DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, - DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, - DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, - DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, - DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, - DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, - DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, - DO34=>DOA16_out, DO35=>DOA17_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15); - VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13); - VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12); - VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11); - VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9); - VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13); - VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12); - VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11); - VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10); - VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9); - VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8); - VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7); - VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6); - VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5); - VitalWireDelay(CEA_ipd, CEA, tipd_CEA); - VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA); - VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB); - VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB); - VitalWireDelay(CEB_ipd, CEB, tipd_CEB); - VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5); - VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6); - VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7); - VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8); - VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9); - VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10); - VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11); - VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12); - VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13); - VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6); - VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8); - VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA); - VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA); - VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA); - VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA); - VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA); - VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA); - VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA); - VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA); - VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA); - VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA); - VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA); - VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA); - VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA); - VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA); - VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA); - VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA); - VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB); - VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB); - VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB); - VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB); - VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB); - VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB); - VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB); - VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB); - VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB); - VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB); - VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB); - VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB); - VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA); - VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA); - VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA); - END BLOCK; - - VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, - DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, - ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, - DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, - DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, - CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, - DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, - ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, - DIB8_dly, DIB9_dly) - VARIABLE DOA17_zd : std_logic := 'X'; - VARIABLE DOA17_GlitchData : VitalGlitchDataType; - VARIABLE DOA16_zd : std_logic := 'X'; - VARIABLE DOA16_GlitchData : VitalGlitchDataType; - VARIABLE DOA15_zd : std_logic := 'X'; - VARIABLE DOA15_GlitchData : VitalGlitchDataType; - VARIABLE DOA14_zd : std_logic := 'X'; - VARIABLE DOA14_GlitchData : VitalGlitchDataType; - VARIABLE DOA13_zd : std_logic := 'X'; - VARIABLE DOA13_GlitchData : VitalGlitchDataType; - VARIABLE DOA12_zd : std_logic := 'X'; - VARIABLE DOA12_GlitchData : VitalGlitchDataType; - VARIABLE DOA11_zd : std_logic := 'X'; - VARIABLE DOA11_GlitchData : VitalGlitchDataType; - VARIABLE DOA10_zd : std_logic := 'X'; - VARIABLE DOA10_GlitchData : VitalGlitchDataType; - VARIABLE DOA9_zd : std_logic := 'X'; - VARIABLE DOA9_GlitchData : VitalGlitchDataType; - VARIABLE DOA8_zd : std_logic := 'X'; - VARIABLE DOA8_GlitchData : VitalGlitchDataType; - VARIABLE DOA7_zd : std_logic := 'X'; - VARIABLE DOA7_GlitchData : VitalGlitchDataType; - VARIABLE DOA6_zd : std_logic := 'X'; - VARIABLE DOA6_GlitchData : VitalGlitchDataType; - VARIABLE DOA5_zd : std_logic := 'X'; - VARIABLE DOA5_GlitchData : VitalGlitchDataType; - VARIABLE DOA4_zd : std_logic := 'X'; - VARIABLE DOA4_GlitchData : VitalGlitchDataType; - VARIABLE DOA3_zd : std_logic := 'X'; - VARIABLE DOA3_GlitchData : VitalGlitchDataType; - VARIABLE DOA2_zd : std_logic := 'X'; - VARIABLE DOA2_GlitchData : VitalGlitchDataType; - VARIABLE DOA1_zd : std_logic := 'X'; - VARIABLE DOA1_GlitchData : VitalGlitchDataType; - VARIABLE DOA0_zd : std_logic := 'X'; - VARIABLE DOA0_GlitchData : VitalGlitchDataType; - VARIABLE DOB0_zd : std_logic := 'X'; - VARIABLE DOB0_GlitchData : VitalGlitchDataType; - VARIABLE DOB1_zd : std_logic := 'X'; - VARIABLE DOB1_GlitchData : VitalGlitchDataType; - VARIABLE DOB2_zd : std_logic := 'X'; - VARIABLE DOB2_GlitchData : VitalGlitchDataType; - VARIABLE DOB3_zd : std_logic := 'X'; - VARIABLE DOB3_GlitchData : VitalGlitchDataType; - VARIABLE DOB4_zd : std_logic := 'X'; - VARIABLE DOB4_GlitchData : VitalGlitchDataType; - VARIABLE DOB5_zd : std_logic := 'X'; - VARIABLE DOB5_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DIA15_CLKA : x01 := '0'; - VARIABLE DIA15_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA13_CLKA : x01 := '0'; - VARIABLE DIA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA12_CLKA : x01 := '0'; - VARIABLE DIA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA11_CLKA : x01 := '0'; - VARIABLE DIA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA9_CLKA : x01 := '0'; - VARIABLE DIA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA13_CLKA : x01 := '0'; - VARIABLE ADA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA12_CLKA : x01 := '0'; - VARIABLE ADA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA11_CLKA : x01 := '0'; - VARIABLE ADA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA10_CLKA : x01 := '0'; - VARIABLE ADA10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA9_CLKA : x01 := '0'; - VARIABLE ADA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA8_CLKA : x01 := '0'; - VARIABLE ADA8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA7_CLKA : x01 := '0'; - VARIABLE ADA7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA6_CLKA : x01 := '0'; - VARIABLE ADA6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA5_CLKA : x01 := '0'; - VARIABLE ADA5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEA_CLKA : x01 := '0'; - VARIABLE CEA_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_OCEB_CLKB : x01 := '0'; - VARIABLE OCEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEB_CLKB : x01 := '0'; - VARIABLE CEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB5_CLKB : x01 := '0'; - VARIABLE ADB5_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB6_CLKB : x01 := '0'; - VARIABLE ADB6_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB7_CLKB : x01 := '0'; - VARIABLE ADB7_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB8_CLKB : x01 := '0'; - VARIABLE ADB8_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB9_CLKB : x01 := '0'; - VARIABLE ADB9_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB10_CLKB : x01 := '0'; - VARIABLE ADB10_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB11_CLKB : x01 := '0'; - VARIABLE ADB11_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB12_CLKB : x01 := '0'; - VARIABLE ADB12_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB13_CLKB : x01 := '0'; - VARIABLE ADB13_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB6_CLKA : x01 := '0'; - VARIABLE DIB6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB8_CLKA : x01 := '0'; - VARIABLE DIB8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB9_CLKA : x01 := '0'; - VARIABLE DIB9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLKA_CLKA : x01 := '0'; - VARIABLE periodcheckinfo_CLKA : VitalPeriodDataType; - VARIABLE tviol_CLKB_CLKB : x01 := '0'; - VARIABLE periodcheckinfo_CLKB : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DIA15_dly, - TestSignalName => "DIA15", - TestDelay => tisd_DIA15_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA15_CLKA_noedge_posedge, - SetupLow => tsetup_DIA15_CLKA_noedge_posedge, - HoldHigh => thold_DIA15_CLKA_noedge_posedge, - HoldLow => thold_DIA15_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA15_CLKA_TimingDatash, - Violation => tviol_DIA15_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA13_dly, - TestSignalName => "DIA13", - TestDelay => tisd_DIA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA13_CLKA_noedge_posedge, - SetupLow => tsetup_DIA13_CLKA_noedge_posedge, - HoldHigh => thold_DIA13_CLKA_noedge_posedge, - HoldLow => thold_DIA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA13_CLKA_TimingDatash, - Violation => tviol_DIA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA12_dly, - TestSignalName => "DIA12", - TestDelay => tisd_DIA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA12_CLKA_noedge_posedge, - SetupLow => tsetup_DIA12_CLKA_noedge_posedge, - HoldHigh => thold_DIA12_CLKA_noedge_posedge, - HoldLow => thold_DIA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA12_CLKA_TimingDatash, - Violation => tviol_DIA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA11_dly, - TestSignalName => "DIA11", - TestDelay => tisd_DIA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA11_CLKA_noedge_posedge, - SetupLow => tsetup_DIA11_CLKA_noedge_posedge, - HoldHigh => thold_DIA11_CLKA_noedge_posedge, - HoldLow => thold_DIA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA11_CLKA_TimingDatash, - Violation => tviol_DIA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA9_dly, - TestSignalName => "DIA9", - TestDelay => tisd_DIA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA9_CLKA_noedge_posedge, - SetupLow => tsetup_DIA9_CLKA_noedge_posedge, - HoldHigh => thold_DIA9_CLKA_noedge_posedge, - HoldLow => thold_DIA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA9_CLKA_TimingDatash, - Violation => tviol_DIA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA13_dly, - TestSignalName => "ADA13", - TestDelay => tisd_ADA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA13_CLKA_noedge_posedge, - SetupLow => tsetup_ADA13_CLKA_noedge_posedge, - HoldHigh => thold_ADA13_CLKA_noedge_posedge, - HoldLow => thold_ADA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA13_CLKA_TimingDatash, - Violation => tviol_ADA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA12_dly, - TestSignalName => "ADA12", - TestDelay => tisd_ADA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA12_CLKA_noedge_posedge, - SetupLow => tsetup_ADA12_CLKA_noedge_posedge, - HoldHigh => thold_ADA12_CLKA_noedge_posedge, - HoldLow => thold_ADA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA12_CLKA_TimingDatash, - Violation => tviol_ADA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA11_dly, - TestSignalName => "ADA11", - TestDelay => tisd_ADA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA11_CLKA_noedge_posedge, - SetupLow => tsetup_ADA11_CLKA_noedge_posedge, - HoldHigh => thold_ADA11_CLKA_noedge_posedge, - HoldLow => thold_ADA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA11_CLKA_TimingDatash, - Violation => tviol_ADA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA10_dly, - TestSignalName => "ADA10", - TestDelay => tisd_ADA10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA10_CLKA_noedge_posedge, - SetupLow => tsetup_ADA10_CLKA_noedge_posedge, - HoldHigh => thold_ADA10_CLKA_noedge_posedge, - HoldLow => thold_ADA10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA10_CLKA_TimingDatash, - Violation => tviol_ADA10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA9_dly, - TestSignalName => "ADA9", - TestDelay => tisd_ADA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA9_CLKA_noedge_posedge, - SetupLow => tsetup_ADA9_CLKA_noedge_posedge, - HoldHigh => thold_ADA9_CLKA_noedge_posedge, - HoldLow => thold_ADA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA9_CLKA_TimingDatash, - Violation => tviol_ADA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA8_dly, - TestSignalName => "ADA8", - TestDelay => tisd_ADA8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA8_CLKA_noedge_posedge, - SetupLow => tsetup_ADA8_CLKA_noedge_posedge, - HoldHigh => thold_ADA8_CLKA_noedge_posedge, - HoldLow => thold_ADA8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA8_CLKA_TimingDatash, - Violation => tviol_ADA8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA7_dly, - TestSignalName => "ADA7", - TestDelay => tisd_ADA7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA7_CLKA_noedge_posedge, - SetupLow => tsetup_ADA7_CLKA_noedge_posedge, - HoldHigh => thold_ADA7_CLKA_noedge_posedge, - HoldLow => thold_ADA7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA7_CLKA_TimingDatash, - Violation => tviol_ADA7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA6_dly, - TestSignalName => "ADA6", - TestDelay => tisd_ADA6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA6_CLKA_noedge_posedge, - SetupLow => tsetup_ADA6_CLKA_noedge_posedge, - HoldHigh => thold_ADA6_CLKA_noedge_posedge, - HoldLow => thold_ADA6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA6_CLKA_TimingDatash, - Violation => tviol_ADA6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA5_dly, - TestSignalName => "ADA5", - TestDelay => tisd_ADA5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA5_CLKA_noedge_posedge, - SetupLow => tsetup_ADA5_CLKA_noedge_posedge, - HoldHigh => thold_ADA5_CLKA_noedge_posedge, - HoldLow => thold_ADA5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA5_CLKA_TimingDatash, - Violation => tviol_ADA5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEA_dly, - TestSignalName => "CEA", - TestDelay => tisd_CEA_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_CEA_CLKA_noedge_posedge, - SetupLow => tsetup_CEA_CLKA_noedge_posedge, - HoldHigh => thold_CEA_CLKA_noedge_posedge, - HoldLow => thold_CEA_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEA_CLKA_TimingDatash, - Violation => tviol_CEA_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => OCEB_dly, - TestSignalName => "OCEB", - TestDelay => tisd_OCEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_OCEB_CLKB_noedge_posedge, - SetupLow => tsetup_OCEB_CLKB_noedge_posedge, - HoldHigh => thold_OCEB_CLKB_noedge_posedge, - HoldLow => thold_OCEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => OCEB_CLKB_TimingDatash, - Violation => tviol_OCEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEB_dly, - TestSignalName => "CEB", - TestDelay => tisd_CEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_CEB_CLKB_noedge_posedge, - SetupLow => tsetup_CEB_CLKB_noedge_posedge, - HoldHigh => thold_CEB_CLKB_noedge_posedge, - HoldLow => thold_CEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEB_CLKB_TimingDatash, - Violation => tviol_CEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB5_dly, - TestSignalName => "ADB5", - TestDelay => tisd_ADB5_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB5_CLKB_noedge_posedge, - SetupLow => tsetup_ADB5_CLKB_noedge_posedge, - HoldHigh => thold_ADB5_CLKB_noedge_posedge, - HoldLow => thold_ADB5_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB5_CLKB_TimingDatash, - Violation => tviol_ADB5_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB6_dly, - TestSignalName => "ADB6", - TestDelay => tisd_ADB6_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB6_CLKB_noedge_posedge, - SetupLow => tsetup_ADB6_CLKB_noedge_posedge, - HoldHigh => thold_ADB6_CLKB_noedge_posedge, - HoldLow => thold_ADB6_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB6_CLKB_TimingDatash, - Violation => tviol_ADB6_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB7_dly, - TestSignalName => "ADB7", - TestDelay => tisd_ADB7_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB7_CLKB_noedge_posedge, - SetupLow => tsetup_ADB7_CLKB_noedge_posedge, - HoldHigh => thold_ADB7_CLKB_noedge_posedge, - HoldLow => thold_ADB7_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB7_CLKB_TimingDatash, - Violation => tviol_ADB7_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB8_dly, - TestSignalName => "ADB8", - TestDelay => tisd_ADB8_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB8_CLKB_noedge_posedge, - SetupLow => tsetup_ADB8_CLKB_noedge_posedge, - HoldHigh => thold_ADB8_CLKB_noedge_posedge, - HoldLow => thold_ADB8_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB8_CLKB_TimingDatash, - Violation => tviol_ADB8_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB9_dly, - TestSignalName => "ADB9", - TestDelay => tisd_ADB9_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB9_CLKB_noedge_posedge, - SetupLow => tsetup_ADB9_CLKB_noedge_posedge, - HoldHigh => thold_ADB9_CLKB_noedge_posedge, - HoldLow => thold_ADB9_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB9_CLKB_TimingDatash, - Violation => tviol_ADB9_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB10_dly, - TestSignalName => "ADB10", - TestDelay => tisd_ADB10_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB10_CLKB_noedge_posedge, - SetupLow => tsetup_ADB10_CLKB_noedge_posedge, - HoldHigh => thold_ADB10_CLKB_noedge_posedge, - HoldLow => thold_ADB10_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB10_CLKB_TimingDatash, - Violation => tviol_ADB10_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB11_dly, - TestSignalName => "ADB11", - TestDelay => tisd_ADB11_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB11_CLKB_noedge_posedge, - SetupLow => tsetup_ADB11_CLKB_noedge_posedge, - HoldHigh => thold_ADB11_CLKB_noedge_posedge, - HoldLow => thold_ADB11_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB11_CLKB_TimingDatash, - Violation => tviol_ADB11_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB12_dly, - TestSignalName => "ADB12", - TestDelay => tisd_ADB12_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB12_CLKB_noedge_posedge, - SetupLow => tsetup_ADB12_CLKB_noedge_posedge, - HoldHigh => thold_ADB12_CLKB_noedge_posedge, - HoldLow => thold_ADB12_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB12_CLKB_TimingDatash, - Violation => tviol_ADB12_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB13_dly, - TestSignalName => "ADB13", - TestDelay => tisd_ADB13_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB13_CLKB_noedge_posedge, - SetupLow => tsetup_ADB13_CLKB_noedge_posedge, - HoldHigh => thold_ADB13_CLKB_noedge_posedge, - HoldLow => thold_ADB13_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB13_CLKB_TimingDatash, - Violation => tviol_ADB13_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB6_dly, - TestSignalName => "DIB6", - TestDelay => tisd_DIB6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB6_CLKA_noedge_posedge, - SetupLow => tsetup_DIB6_CLKA_noedge_posedge, - HoldHigh => thold_DIB6_CLKA_noedge_posedge, - HoldLow => thold_DIB6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB6_CLKA_TimingDatash, - Violation => tviol_DIB6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB8_dly, - TestSignalName => "DIB8", - TestDelay => tisd_DIB8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB8_CLKA_noedge_posedge, - SetupLow => tsetup_DIB8_CLKA_noedge_posedge, - HoldHigh => thold_DIB8_CLKA_noedge_posedge, - HoldLow => thold_DIB8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB8_CLKA_TimingDatash, - Violation => tviol_DIB8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB9_dly, - TestSignalName => "DIB9", - TestDelay => tisd_DIB9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB9_CLKA_noedge_posedge, - SetupLow => tsetup_DIB9_CLKA_noedge_posedge, - HoldHigh => thold_DIB9_CLKA_noedge_posedge, - HoldLow => thold_DIB9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB9_CLKA_TimingDatash, - Violation => tviol_DIB9_CLKA, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKA_ipd, - TestSignalName => "CLKA", - Period => tperiod_CLKA, - PulseWidthHigh => tpw_CLKA_posedge, - PulseWidthLow => tpw_CLKA_negedge, - PeriodData => periodcheckinfo_CLKA, - Violation => tviol_CLKA_CLKA, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKB_ipd, - TestSignalName => "CLKB", - Period => tperiod_CLKB, - PulseWidthHigh => tpw_CLKB_posedge, - PulseWidthLow => tpw_CLKB_negedge, - PeriodData => periodcheckinfo_CLKB, - Violation => tviol_CLKB_CLKB, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - DOA17_zd := DOA17_out; - DOA16_zd := DOA16_out; - DOA15_zd := DOA15_out; - DOA14_zd := DOA14_out; - DOA13_zd := DOA13_out; - DOA12_zd := DOA12_out; - DOA11_zd := DOA11_out; - DOA10_zd := DOA10_out; - DOA9_zd := DOA9_out; - DOA8_zd := DOA8_out; - DOA7_zd := DOA7_out; - DOA6_zd := DOA6_out; - DOA5_zd := DOA5_out; - DOA4_zd := DOA4_out; - DOA3_zd := DOA3_out; - DOA2_zd := DOA2_out; - DOA1_zd := DOA1_out; - DOA0_zd := DOA0_out; - DOB0_zd := DOB0_out; - DOB1_zd := DOB1_out; - DOB2_zd := DOB2_out; - DOB3_zd := DOB3_out; - DOB4_zd := DOB4_out; - DOB5_zd := DOB5_out; - - VitalPathDelay01 ( - OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA17, - PathCondition => TRUE)), - GlitchData => DOA17_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA16, - PathCondition => TRUE)), - GlitchData => DOA16_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA15, - PathCondition => TRUE)), - GlitchData => DOA15_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA14, - PathCondition => TRUE)), - GlitchData => DOA14_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA13, - PathCondition => TRUE)), - GlitchData => DOA13_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA12, - PathCondition => TRUE)), - GlitchData => DOA12_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA11, - PathCondition => TRUE)), - GlitchData => DOA11_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA10, - PathCondition => TRUE)), - GlitchData => DOA10_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA9, - PathCondition => TRUE)), - GlitchData => DOA9_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA8, - PathCondition => TRUE)), - GlitchData => DOA8_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA7, - PathCondition => TRUE)), - GlitchData => DOA7_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA6, - PathCondition => TRUE)), - GlitchData => DOA6_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA5, - PathCondition => TRUE)), - GlitchData => DOA5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA4, - PathCondition => TRUE)), - GlitchData => DOA4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA3, - PathCondition => TRUE)), - GlitchData => DOA3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA2, - PathCondition => TRUE)), - GlitchData => DOA2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA1, - PathCondition => TRUE)), - GlitchData => DOA1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA0, - PathCondition => TRUE)), - GlitchData => DOA0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB0, - PathCondition => TRUE)), - GlitchData => DOB0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB1, - PathCondition => TRUE)), - GlitchData => DOB1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB2, - PathCondition => TRUE)), - GlitchData => DOB2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB3, - PathCondition => TRUE)), - GlitchData => DOB3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB4, - PathCondition => TRUE)), - GlitchData => DOB4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB5, - PathCondition => TRUE)), - GlitchData => DOB5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity PDPW16KD0253 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity PDPW16KD0253 is - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - - ATTRIBUTE Vital_Level0 OF PDPW16KD0253 : ENTITY IS TRUE; - - end PDPW16KD0253; - - architecture Structure of PDPW16KD0253 is - begin - INST10: PDPW16KD - generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", - CSDECODE_W => "0b001", DATA_WIDTH_R => 36, - DATA_WIDTH_W => 36, GSR => "DISABLED", - INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , INIT_DATA => "STATIC", REGMODE => "NOREG", - RESETMODE => "SYNC") - port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, - DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, - DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, - DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, - DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, - DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, - DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, - ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, - ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, - BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, - CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, - ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, - ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, - ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, - CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, - DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, - DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, - DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, - DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, - DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, - DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, - DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35); - end Structure; - --- entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0" - ; - - tipd_DIA15 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKB : VitalDelayType01 := (0 ns, 0 ns); - tipd_OCEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA17 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA16 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA15 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA14 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA13 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA12 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA11 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA10 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB5 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLKA : VitalDelayType := 0 ns; - tisd_DIA15_CLKA : VitalDelayType := 0 ns; - tsetup_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA13_CLKA : VitalDelayType := 0 ns; - tsetup_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA12_CLKA : VitalDelayType := 0 ns; - tsetup_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA11_CLKA : VitalDelayType := 0 ns; - tsetup_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA9_CLKA : VitalDelayType := 0 ns; - tsetup_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA13_CLKA : VitalDelayType := 0 ns; - tsetup_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA12_CLKA : VitalDelayType := 0 ns; - tsetup_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA11_CLKA : VitalDelayType := 0 ns; - tsetup_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA10_CLKA : VitalDelayType := 0 ns; - tsetup_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA9_CLKA : VitalDelayType := 0 ns; - tsetup_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA8_CLKA : VitalDelayType := 0 ns; - tsetup_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA7_CLKA : VitalDelayType := 0 ns; - tsetup_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA6_CLKA : VitalDelayType := 0 ns; - tsetup_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA5_CLKA : VitalDelayType := 0 ns; - tsetup_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEA_CLKA : VitalDelayType := 0 ns; - tsetup_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - ticd_CLKB : VitalDelayType := 0 ns; - tisd_OCEB_CLKB : VitalDelayType := 0 ns; - tsetup_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEB_CLKB : VitalDelayType := 0 ns; - tsetup_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB5_CLKB : VitalDelayType := 0 ns; - tsetup_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB6_CLKB : VitalDelayType := 0 ns; - tsetup_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB7_CLKB : VitalDelayType := 0 ns; - tsetup_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB8_CLKB : VitalDelayType := 0 ns; - tsetup_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB9_CLKB : VitalDelayType := 0 ns; - tsetup_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB10_CLKB : VitalDelayType := 0 ns; - tsetup_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB11_CLKB : VitalDelayType := 0 ns; - tsetup_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB12_CLKB : VitalDelayType := 0 ns; - tsetup_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB13_CLKB : VitalDelayType := 0 ns; - tsetup_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB6_CLKA : VitalDelayType := 0 ns; - tsetup_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB8_CLKA : VitalDelayType := 0 ns; - tsetup_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB9_CLKA : VitalDelayType := 0 ns; - tsetup_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLKA : VitalDelayType := 0 ns; - tpw_CLKA_posedge : VitalDelayType := 0 ns; - tpw_CLKA_negedge : VitalDelayType := 0 ns; - tperiod_CLKB : VitalDelayType := 0 ns; - tpw_CLKB_posedge : VitalDelayType := 0 ns; - tpw_CLKB_negedge : VitalDelayType := 0 ns); - - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE; - - end genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0; - - - architecture Structure of genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DIA15_ipd : std_logic := 'X'; - signal DIA15_dly : std_logic := 'X'; - signal DIA13_ipd : std_logic := 'X'; - signal DIA13_dly : std_logic := 'X'; - signal DIA12_ipd : std_logic := 'X'; - signal DIA12_dly : std_logic := 'X'; - signal DIA11_ipd : std_logic := 'X'; - signal DIA11_dly : std_logic := 'X'; - signal DIA9_ipd : std_logic := 'X'; - signal DIA9_dly : std_logic := 'X'; - signal ADA13_ipd : std_logic := 'X'; - signal ADA13_dly : std_logic := 'X'; - signal ADA12_ipd : std_logic := 'X'; - signal ADA12_dly : std_logic := 'X'; - signal ADA11_ipd : std_logic := 'X'; - signal ADA11_dly : std_logic := 'X'; - signal ADA10_ipd : std_logic := 'X'; - signal ADA10_dly : std_logic := 'X'; - signal ADA9_ipd : std_logic := 'X'; - signal ADA9_dly : std_logic := 'X'; - signal ADA8_ipd : std_logic := 'X'; - signal ADA8_dly : std_logic := 'X'; - signal ADA7_ipd : std_logic := 'X'; - signal ADA7_dly : std_logic := 'X'; - signal ADA6_ipd : std_logic := 'X'; - signal ADA6_dly : std_logic := 'X'; - signal ADA5_ipd : std_logic := 'X'; - signal ADA5_dly : std_logic := 'X'; - signal DOA17_out : std_logic := 'X'; - signal DOA16_out : std_logic := 'X'; - signal DOA15_out : std_logic := 'X'; - signal DOA14_out : std_logic := 'X'; - signal DOA13_out : std_logic := 'X'; - signal DOA12_out : std_logic := 'X'; - signal DOA11_out : std_logic := 'X'; - signal DOA10_out : std_logic := 'X'; - signal DOA9_out : std_logic := 'X'; - signal DOA8_out : std_logic := 'X'; - signal DOA7_out : std_logic := 'X'; - signal DOA6_out : std_logic := 'X'; - signal DOA5_out : std_logic := 'X'; - signal DOA4_out : std_logic := 'X'; - signal DOA3_out : std_logic := 'X'; - signal DOA2_out : std_logic := 'X'; - signal DOA1_out : std_logic := 'X'; - signal DOA0_out : std_logic := 'X'; - signal CEA_ipd : std_logic := 'X'; - signal CEA_dly : std_logic := 'X'; - signal CLKA_ipd : std_logic := 'X'; - signal CLKA_dly : std_logic := 'X'; - signal CLKB_ipd : std_logic := 'X'; - signal CLKB_dly : std_logic := 'X'; - signal OCEB_ipd : std_logic := 'X'; - signal OCEB_dly : std_logic := 'X'; - signal CEB_ipd : std_logic := 'X'; - signal CEB_dly : std_logic := 'X'; - signal DOB0_out : std_logic := 'X'; - signal DOB1_out : std_logic := 'X'; - signal DOB2_out : std_logic := 'X'; - signal DOB3_out : std_logic := 'X'; - signal DOB4_out : std_logic := 'X'; - signal DOB5_out : std_logic := 'X'; - signal ADB5_ipd : std_logic := 'X'; - signal ADB5_dly : std_logic := 'X'; - signal ADB6_ipd : std_logic := 'X'; - signal ADB6_dly : std_logic := 'X'; - signal ADB7_ipd : std_logic := 'X'; - signal ADB7_dly : std_logic := 'X'; - signal ADB8_ipd : std_logic := 'X'; - signal ADB8_dly : std_logic := 'X'; - signal ADB9_ipd : std_logic := 'X'; - signal ADB9_dly : std_logic := 'X'; - signal ADB10_ipd : std_logic := 'X'; - signal ADB10_dly : std_logic := 'X'; - signal ADB11_ipd : std_logic := 'X'; - signal ADB11_dly : std_logic := 'X'; - signal ADB12_ipd : std_logic := 'X'; - signal ADB12_dly : std_logic := 'X'; - signal ADB13_ipd : std_logic := 'X'; - signal ADB13_dly : std_logic := 'X'; - signal DIB6_ipd : std_logic := 'X'; - signal DIB6_dly : std_logic := 'X'; - signal DIB8_ipd : std_logic := 'X'; - signal DIB8_dly : std_logic := 'X'; - signal DIB9_ipd : std_logic := 'X'; - signal DIB9_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component PDPW16KD0253 - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - end component; - begin - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KD0253 - port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, - CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, - CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, - BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, - DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, - DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, - DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, - DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, - DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, - DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, - DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, - DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, - ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, - ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, - ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, - ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, - ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, - ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, - ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, - DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, - DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, - DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, - DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, - DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, - DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, - DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, - DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, - DO34=>DOA16_out, DO35=>DOA17_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15); - VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13); - VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12); - VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11); - VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9); - VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13); - VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12); - VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11); - VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10); - VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9); - VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8); - VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7); - VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6); - VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5); - VitalWireDelay(CEA_ipd, CEA, tipd_CEA); - VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA); - VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB); - VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB); - VitalWireDelay(CEB_ipd, CEB, tipd_CEB); - VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5); - VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6); - VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7); - VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8); - VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9); - VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10); - VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11); - VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12); - VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13); - VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6); - VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8); - VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA); - VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA); - VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA); - VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA); - VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA); - VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA); - VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA); - VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA); - VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA); - VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA); - VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA); - VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA); - VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA); - VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA); - VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA); - VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA); - VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB); - VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB); - VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB); - VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB); - VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB); - VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB); - VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB); - VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB); - VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB); - VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB); - VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB); - VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB); - VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA); - VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA); - VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA); - END BLOCK; - - VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, - DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, - ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, - DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, - DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, - CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, - DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, - ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, - DIB8_dly, DIB9_dly) - VARIABLE DOA17_zd : std_logic := 'X'; - VARIABLE DOA17_GlitchData : VitalGlitchDataType; - VARIABLE DOA16_zd : std_logic := 'X'; - VARIABLE DOA16_GlitchData : VitalGlitchDataType; - VARIABLE DOA15_zd : std_logic := 'X'; - VARIABLE DOA15_GlitchData : VitalGlitchDataType; - VARIABLE DOA14_zd : std_logic := 'X'; - VARIABLE DOA14_GlitchData : VitalGlitchDataType; - VARIABLE DOA13_zd : std_logic := 'X'; - VARIABLE DOA13_GlitchData : VitalGlitchDataType; - VARIABLE DOA12_zd : std_logic := 'X'; - VARIABLE DOA12_GlitchData : VitalGlitchDataType; - VARIABLE DOA11_zd : std_logic := 'X'; - VARIABLE DOA11_GlitchData : VitalGlitchDataType; - VARIABLE DOA10_zd : std_logic := 'X'; - VARIABLE DOA10_GlitchData : VitalGlitchDataType; - VARIABLE DOA9_zd : std_logic := 'X'; - VARIABLE DOA9_GlitchData : VitalGlitchDataType; - VARIABLE DOA8_zd : std_logic := 'X'; - VARIABLE DOA8_GlitchData : VitalGlitchDataType; - VARIABLE DOA7_zd : std_logic := 'X'; - VARIABLE DOA7_GlitchData : VitalGlitchDataType; - VARIABLE DOA6_zd : std_logic := 'X'; - VARIABLE DOA6_GlitchData : VitalGlitchDataType; - VARIABLE DOA5_zd : std_logic := 'X'; - VARIABLE DOA5_GlitchData : VitalGlitchDataType; - VARIABLE DOA4_zd : std_logic := 'X'; - VARIABLE DOA4_GlitchData : VitalGlitchDataType; - VARIABLE DOA3_zd : std_logic := 'X'; - VARIABLE DOA3_GlitchData : VitalGlitchDataType; - VARIABLE DOA2_zd : std_logic := 'X'; - VARIABLE DOA2_GlitchData : VitalGlitchDataType; - VARIABLE DOA1_zd : std_logic := 'X'; - VARIABLE DOA1_GlitchData : VitalGlitchDataType; - VARIABLE DOA0_zd : std_logic := 'X'; - VARIABLE DOA0_GlitchData : VitalGlitchDataType; - VARIABLE DOB0_zd : std_logic := 'X'; - VARIABLE DOB0_GlitchData : VitalGlitchDataType; - VARIABLE DOB1_zd : std_logic := 'X'; - VARIABLE DOB1_GlitchData : VitalGlitchDataType; - VARIABLE DOB2_zd : std_logic := 'X'; - VARIABLE DOB2_GlitchData : VitalGlitchDataType; - VARIABLE DOB3_zd : std_logic := 'X'; - VARIABLE DOB3_GlitchData : VitalGlitchDataType; - VARIABLE DOB4_zd : std_logic := 'X'; - VARIABLE DOB4_GlitchData : VitalGlitchDataType; - VARIABLE DOB5_zd : std_logic := 'X'; - VARIABLE DOB5_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DIA15_CLKA : x01 := '0'; - VARIABLE DIA15_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA13_CLKA : x01 := '0'; - VARIABLE DIA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA12_CLKA : x01 := '0'; - VARIABLE DIA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA11_CLKA : x01 := '0'; - VARIABLE DIA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA9_CLKA : x01 := '0'; - VARIABLE DIA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA13_CLKA : x01 := '0'; - VARIABLE ADA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA12_CLKA : x01 := '0'; - VARIABLE ADA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA11_CLKA : x01 := '0'; - VARIABLE ADA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA10_CLKA : x01 := '0'; - VARIABLE ADA10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA9_CLKA : x01 := '0'; - VARIABLE ADA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA8_CLKA : x01 := '0'; - VARIABLE ADA8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA7_CLKA : x01 := '0'; - VARIABLE ADA7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA6_CLKA : x01 := '0'; - VARIABLE ADA6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA5_CLKA : x01 := '0'; - VARIABLE ADA5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEA_CLKA : x01 := '0'; - VARIABLE CEA_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_OCEB_CLKB : x01 := '0'; - VARIABLE OCEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEB_CLKB : x01 := '0'; - VARIABLE CEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB5_CLKB : x01 := '0'; - VARIABLE ADB5_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB6_CLKB : x01 := '0'; - VARIABLE ADB6_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB7_CLKB : x01 := '0'; - VARIABLE ADB7_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB8_CLKB : x01 := '0'; - VARIABLE ADB8_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB9_CLKB : x01 := '0'; - VARIABLE ADB9_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB10_CLKB : x01 := '0'; - VARIABLE ADB10_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB11_CLKB : x01 := '0'; - VARIABLE ADB11_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB12_CLKB : x01 := '0'; - VARIABLE ADB12_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB13_CLKB : x01 := '0'; - VARIABLE ADB13_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB6_CLKA : x01 := '0'; - VARIABLE DIB6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB8_CLKA : x01 := '0'; - VARIABLE DIB8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB9_CLKA : x01 := '0'; - VARIABLE DIB9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLKA_CLKA : x01 := '0'; - VARIABLE periodcheckinfo_CLKA : VitalPeriodDataType; - VARIABLE tviol_CLKB_CLKB : x01 := '0'; - VARIABLE periodcheckinfo_CLKB : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DIA15_dly, - TestSignalName => "DIA15", - TestDelay => tisd_DIA15_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA15_CLKA_noedge_posedge, - SetupLow => tsetup_DIA15_CLKA_noedge_posedge, - HoldHigh => thold_DIA15_CLKA_noedge_posedge, - HoldLow => thold_DIA15_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA15_CLKA_TimingDatash, - Violation => tviol_DIA15_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA13_dly, - TestSignalName => "DIA13", - TestDelay => tisd_DIA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA13_CLKA_noedge_posedge, - SetupLow => tsetup_DIA13_CLKA_noedge_posedge, - HoldHigh => thold_DIA13_CLKA_noedge_posedge, - HoldLow => thold_DIA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA13_CLKA_TimingDatash, - Violation => tviol_DIA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA12_dly, - TestSignalName => "DIA12", - TestDelay => tisd_DIA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA12_CLKA_noedge_posedge, - SetupLow => tsetup_DIA12_CLKA_noedge_posedge, - HoldHigh => thold_DIA12_CLKA_noedge_posedge, - HoldLow => thold_DIA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA12_CLKA_TimingDatash, - Violation => tviol_DIA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA11_dly, - TestSignalName => "DIA11", - TestDelay => tisd_DIA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA11_CLKA_noedge_posedge, - SetupLow => tsetup_DIA11_CLKA_noedge_posedge, - HoldHigh => thold_DIA11_CLKA_noedge_posedge, - HoldLow => thold_DIA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA11_CLKA_TimingDatash, - Violation => tviol_DIA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA9_dly, - TestSignalName => "DIA9", - TestDelay => tisd_DIA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA9_CLKA_noedge_posedge, - SetupLow => tsetup_DIA9_CLKA_noedge_posedge, - HoldHigh => thold_DIA9_CLKA_noedge_posedge, - HoldLow => thold_DIA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA9_CLKA_TimingDatash, - Violation => tviol_DIA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA13_dly, - TestSignalName => "ADA13", - TestDelay => tisd_ADA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA13_CLKA_noedge_posedge, - SetupLow => tsetup_ADA13_CLKA_noedge_posedge, - HoldHigh => thold_ADA13_CLKA_noedge_posedge, - HoldLow => thold_ADA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA13_CLKA_TimingDatash, - Violation => tviol_ADA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA12_dly, - TestSignalName => "ADA12", - TestDelay => tisd_ADA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA12_CLKA_noedge_posedge, - SetupLow => tsetup_ADA12_CLKA_noedge_posedge, - HoldHigh => thold_ADA12_CLKA_noedge_posedge, - HoldLow => thold_ADA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA12_CLKA_TimingDatash, - Violation => tviol_ADA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA11_dly, - TestSignalName => "ADA11", - TestDelay => tisd_ADA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA11_CLKA_noedge_posedge, - SetupLow => tsetup_ADA11_CLKA_noedge_posedge, - HoldHigh => thold_ADA11_CLKA_noedge_posedge, - HoldLow => thold_ADA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA11_CLKA_TimingDatash, - Violation => tviol_ADA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA10_dly, - TestSignalName => "ADA10", - TestDelay => tisd_ADA10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA10_CLKA_noedge_posedge, - SetupLow => tsetup_ADA10_CLKA_noedge_posedge, - HoldHigh => thold_ADA10_CLKA_noedge_posedge, - HoldLow => thold_ADA10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA10_CLKA_TimingDatash, - Violation => tviol_ADA10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA9_dly, - TestSignalName => "ADA9", - TestDelay => tisd_ADA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA9_CLKA_noedge_posedge, - SetupLow => tsetup_ADA9_CLKA_noedge_posedge, - HoldHigh => thold_ADA9_CLKA_noedge_posedge, - HoldLow => thold_ADA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA9_CLKA_TimingDatash, - Violation => tviol_ADA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA8_dly, - TestSignalName => "ADA8", - TestDelay => tisd_ADA8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA8_CLKA_noedge_posedge, - SetupLow => tsetup_ADA8_CLKA_noedge_posedge, - HoldHigh => thold_ADA8_CLKA_noedge_posedge, - HoldLow => thold_ADA8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA8_CLKA_TimingDatash, - Violation => tviol_ADA8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA7_dly, - TestSignalName => "ADA7", - TestDelay => tisd_ADA7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA7_CLKA_noedge_posedge, - SetupLow => tsetup_ADA7_CLKA_noedge_posedge, - HoldHigh => thold_ADA7_CLKA_noedge_posedge, - HoldLow => thold_ADA7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA7_CLKA_TimingDatash, - Violation => tviol_ADA7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA6_dly, - TestSignalName => "ADA6", - TestDelay => tisd_ADA6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA6_CLKA_noedge_posedge, - SetupLow => tsetup_ADA6_CLKA_noedge_posedge, - HoldHigh => thold_ADA6_CLKA_noedge_posedge, - HoldLow => thold_ADA6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA6_CLKA_TimingDatash, - Violation => tviol_ADA6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA5_dly, - TestSignalName => "ADA5", - TestDelay => tisd_ADA5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA5_CLKA_noedge_posedge, - SetupLow => tsetup_ADA5_CLKA_noedge_posedge, - HoldHigh => thold_ADA5_CLKA_noedge_posedge, - HoldLow => thold_ADA5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA5_CLKA_TimingDatash, - Violation => tviol_ADA5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEA_dly, - TestSignalName => "CEA", - TestDelay => tisd_CEA_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_CEA_CLKA_noedge_posedge, - SetupLow => tsetup_CEA_CLKA_noedge_posedge, - HoldHigh => thold_CEA_CLKA_noedge_posedge, - HoldLow => thold_CEA_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEA_CLKA_TimingDatash, - Violation => tviol_CEA_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => OCEB_dly, - TestSignalName => "OCEB", - TestDelay => tisd_OCEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_OCEB_CLKB_noedge_posedge, - SetupLow => tsetup_OCEB_CLKB_noedge_posedge, - HoldHigh => thold_OCEB_CLKB_noedge_posedge, - HoldLow => thold_OCEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => OCEB_CLKB_TimingDatash, - Violation => tviol_OCEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEB_dly, - TestSignalName => "CEB", - TestDelay => tisd_CEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_CEB_CLKB_noedge_posedge, - SetupLow => tsetup_CEB_CLKB_noedge_posedge, - HoldHigh => thold_CEB_CLKB_noedge_posedge, - HoldLow => thold_CEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEB_CLKB_TimingDatash, - Violation => tviol_CEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB5_dly, - TestSignalName => "ADB5", - TestDelay => tisd_ADB5_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB5_CLKB_noedge_posedge, - SetupLow => tsetup_ADB5_CLKB_noedge_posedge, - HoldHigh => thold_ADB5_CLKB_noedge_posedge, - HoldLow => thold_ADB5_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB5_CLKB_TimingDatash, - Violation => tviol_ADB5_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB6_dly, - TestSignalName => "ADB6", - TestDelay => tisd_ADB6_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB6_CLKB_noedge_posedge, - SetupLow => tsetup_ADB6_CLKB_noedge_posedge, - HoldHigh => thold_ADB6_CLKB_noedge_posedge, - HoldLow => thold_ADB6_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB6_CLKB_TimingDatash, - Violation => tviol_ADB6_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB7_dly, - TestSignalName => "ADB7", - TestDelay => tisd_ADB7_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB7_CLKB_noedge_posedge, - SetupLow => tsetup_ADB7_CLKB_noedge_posedge, - HoldHigh => thold_ADB7_CLKB_noedge_posedge, - HoldLow => thold_ADB7_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB7_CLKB_TimingDatash, - Violation => tviol_ADB7_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB8_dly, - TestSignalName => "ADB8", - TestDelay => tisd_ADB8_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB8_CLKB_noedge_posedge, - SetupLow => tsetup_ADB8_CLKB_noedge_posedge, - HoldHigh => thold_ADB8_CLKB_noedge_posedge, - HoldLow => thold_ADB8_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB8_CLKB_TimingDatash, - Violation => tviol_ADB8_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB9_dly, - TestSignalName => "ADB9", - TestDelay => tisd_ADB9_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB9_CLKB_noedge_posedge, - SetupLow => tsetup_ADB9_CLKB_noedge_posedge, - HoldHigh => thold_ADB9_CLKB_noedge_posedge, - HoldLow => thold_ADB9_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB9_CLKB_TimingDatash, - Violation => tviol_ADB9_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB10_dly, - TestSignalName => "ADB10", - TestDelay => tisd_ADB10_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB10_CLKB_noedge_posedge, - SetupLow => tsetup_ADB10_CLKB_noedge_posedge, - HoldHigh => thold_ADB10_CLKB_noedge_posedge, - HoldLow => thold_ADB10_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB10_CLKB_TimingDatash, - Violation => tviol_ADB10_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB11_dly, - TestSignalName => "ADB11", - TestDelay => tisd_ADB11_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB11_CLKB_noedge_posedge, - SetupLow => tsetup_ADB11_CLKB_noedge_posedge, - HoldHigh => thold_ADB11_CLKB_noedge_posedge, - HoldLow => thold_ADB11_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB11_CLKB_TimingDatash, - Violation => tviol_ADB11_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB12_dly, - TestSignalName => "ADB12", - TestDelay => tisd_ADB12_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB12_CLKB_noedge_posedge, - SetupLow => tsetup_ADB12_CLKB_noedge_posedge, - HoldHigh => thold_ADB12_CLKB_noedge_posedge, - HoldLow => thold_ADB12_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB12_CLKB_TimingDatash, - Violation => tviol_ADB12_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB13_dly, - TestSignalName => "ADB13", - TestDelay => tisd_ADB13_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB13_CLKB_noedge_posedge, - SetupLow => tsetup_ADB13_CLKB_noedge_posedge, - HoldHigh => thold_ADB13_CLKB_noedge_posedge, - HoldLow => thold_ADB13_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB13_CLKB_TimingDatash, - Violation => tviol_ADB13_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB6_dly, - TestSignalName => "DIB6", - TestDelay => tisd_DIB6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB6_CLKA_noedge_posedge, - SetupLow => tsetup_DIB6_CLKA_noedge_posedge, - HoldHigh => thold_DIB6_CLKA_noedge_posedge, - HoldLow => thold_DIB6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB6_CLKA_TimingDatash, - Violation => tviol_DIB6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB8_dly, - TestSignalName => "DIB8", - TestDelay => tisd_DIB8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB8_CLKA_noedge_posedge, - SetupLow => tsetup_DIB8_CLKA_noedge_posedge, - HoldHigh => thold_DIB8_CLKA_noedge_posedge, - HoldLow => thold_DIB8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB8_CLKA_TimingDatash, - Violation => tviol_DIB8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB9_dly, - TestSignalName => "DIB9", - TestDelay => tisd_DIB9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB9_CLKA_noedge_posedge, - SetupLow => tsetup_DIB9_CLKA_noedge_posedge, - HoldHigh => thold_DIB9_CLKA_noedge_posedge, - HoldLow => thold_DIB9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB9_CLKA_TimingDatash, - Violation => tviol_DIB9_CLKA, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKA_ipd, - TestSignalName => "CLKA", - Period => tperiod_CLKA, - PulseWidthHigh => tpw_CLKA_posedge, - PulseWidthLow => tpw_CLKA_negedge, - PeriodData => periodcheckinfo_CLKA, - Violation => tviol_CLKA_CLKA, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKB_ipd, - TestSignalName => "CLKB", - Period => tperiod_CLKB, - PulseWidthHigh => tpw_CLKB_posedge, - PulseWidthLow => tpw_CLKB_negedge, - PeriodData => periodcheckinfo_CLKB, - Violation => tviol_CLKB_CLKB, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - DOA17_zd := DOA17_out; - DOA16_zd := DOA16_out; - DOA15_zd := DOA15_out; - DOA14_zd := DOA14_out; - DOA13_zd := DOA13_out; - DOA12_zd := DOA12_out; - DOA11_zd := DOA11_out; - DOA10_zd := DOA10_out; - DOA9_zd := DOA9_out; - DOA8_zd := DOA8_out; - DOA7_zd := DOA7_out; - DOA6_zd := DOA6_out; - DOA5_zd := DOA5_out; - DOA4_zd := DOA4_out; - DOA3_zd := DOA3_out; - DOA2_zd := DOA2_out; - DOA1_zd := DOA1_out; - DOA0_zd := DOA0_out; - DOB0_zd := DOB0_out; - DOB1_zd := DOB1_out; - DOB2_zd := DOB2_out; - DOB3_zd := DOB3_out; - DOB4_zd := DOB4_out; - DOB5_zd := DOB5_out; - - VitalPathDelay01 ( - OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA17, - PathCondition => TRUE)), - GlitchData => DOA17_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA16, - PathCondition => TRUE)), - GlitchData => DOA16_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA15, - PathCondition => TRUE)), - GlitchData => DOA15_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA14, - PathCondition => TRUE)), - GlitchData => DOA14_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA13, - PathCondition => TRUE)), - GlitchData => DOA13_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA12, - PathCondition => TRUE)), - GlitchData => DOA12_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA11, - PathCondition => TRUE)), - GlitchData => DOA11_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA10, - PathCondition => TRUE)), - GlitchData => DOA10_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA9, - PathCondition => TRUE)), - GlitchData => DOA9_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA8, - PathCondition => TRUE)), - GlitchData => DOA8_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA7, - PathCondition => TRUE)), - GlitchData => DOA7_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA6, - PathCondition => TRUE)), - GlitchData => DOA6_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA5, - PathCondition => TRUE)), - GlitchData => DOA5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA4, - PathCondition => TRUE)), - GlitchData => DOA4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA3, - PathCondition => TRUE)), - GlitchData => DOA3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA2, - PathCondition => TRUE)), - GlitchData => DOA2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA1, - PathCondition => TRUE)), - GlitchData => DOA1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA0, - PathCondition => TRUE)), - GlitchData => DOA0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB0, - PathCondition => TRUE)), - GlitchData => DOB0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB1, - PathCondition => TRUE)), - GlitchData => DOB1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB2, - PathCondition => TRUE)), - GlitchData => DOB2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB3, - PathCondition => TRUE)), - GlitchData => DOB3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB4, - PathCondition => TRUE)), - GlitchData => DOB4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB5, - PathCondition => TRUE)), - GlitchData => DOB5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity PDPW16KD0254 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity PDPW16KD0254 is - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - - ATTRIBUTE Vital_Level0 OF PDPW16KD0254 : ENTITY IS TRUE; - - end PDPW16KD0254; - - architecture Structure of PDPW16KD0254 is - begin - INST10: PDPW16KD - generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", - CSDECODE_W => "0b001", DATA_WIDTH_R => 36, - DATA_WIDTH_W => 36, GSR => "DISABLED", - INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , INIT_DATA => "STATIC", REGMODE => "NOREG", - RESETMODE => "SYNC") - port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, - DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, - DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, - DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, - DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, - DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, - DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, - ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, - ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, - BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, - CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, - ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, - ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, - ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, - CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, - DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, - DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, - DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, - DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, - DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, - DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, - DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35); - end Structure; - --- entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - - InstancePath : string := "genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0" - ; - - tipd_DIA15 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKB : VitalDelayType01 := (0 ns, 0 ns); - tipd_OCEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA17 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA16 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA15 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA14 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA13 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA12 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA11 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA10 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB5 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLKA : VitalDelayType := 0 ns; - tisd_DIA15_CLKA : VitalDelayType := 0 ns; - tsetup_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA13_CLKA : VitalDelayType := 0 ns; - tsetup_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA12_CLKA : VitalDelayType := 0 ns; - tsetup_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA11_CLKA : VitalDelayType := 0 ns; - tsetup_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA9_CLKA : VitalDelayType := 0 ns; - tsetup_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA13_CLKA : VitalDelayType := 0 ns; - tsetup_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA12_CLKA : VitalDelayType := 0 ns; - tsetup_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA11_CLKA : VitalDelayType := 0 ns; - tsetup_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA10_CLKA : VitalDelayType := 0 ns; - tsetup_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA9_CLKA : VitalDelayType := 0 ns; - tsetup_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA8_CLKA : VitalDelayType := 0 ns; - tsetup_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA7_CLKA : VitalDelayType := 0 ns; - tsetup_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA6_CLKA : VitalDelayType := 0 ns; - tsetup_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA5_CLKA : VitalDelayType := 0 ns; - tsetup_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEA_CLKA : VitalDelayType := 0 ns; - tsetup_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - ticd_CLKB : VitalDelayType := 0 ns; - tisd_OCEB_CLKB : VitalDelayType := 0 ns; - tsetup_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEB_CLKB : VitalDelayType := 0 ns; - tsetup_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB5_CLKB : VitalDelayType := 0 ns; - tsetup_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB6_CLKB : VitalDelayType := 0 ns; - tsetup_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB7_CLKB : VitalDelayType := 0 ns; - tsetup_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB8_CLKB : VitalDelayType := 0 ns; - tsetup_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB9_CLKB : VitalDelayType := 0 ns; - tsetup_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB10_CLKB : VitalDelayType := 0 ns; - tsetup_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB11_CLKB : VitalDelayType := 0 ns; - tsetup_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB12_CLKB : VitalDelayType := 0 ns; - tsetup_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB13_CLKB : VitalDelayType := 0 ns; - tsetup_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB6_CLKA : VitalDelayType := 0 ns; - tsetup_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB8_CLKA : VitalDelayType := 0 ns; - tsetup_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB9_CLKA : VitalDelayType := 0 ns; - tsetup_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLKA : VitalDelayType := 0 ns; - tpw_CLKA_posedge : VitalDelayType := 0 ns; - tpw_CLKA_negedge : VitalDelayType := 0 ns; - tperiod_CLKB : VitalDelayType := 0 ns; - tpw_CLKB_posedge : VitalDelayType := 0 ns; - tpw_CLKB_negedge : VitalDelayType := 0 ns); - - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - - - ATTRIBUTE Vital_Level0 OF genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 : ENTITY IS TRUE; - - end genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0; - - - architecture Structure of genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DIA15_ipd : std_logic := 'X'; - signal DIA15_dly : std_logic := 'X'; - signal DIA13_ipd : std_logic := 'X'; - signal DIA13_dly : std_logic := 'X'; - signal DIA12_ipd : std_logic := 'X'; - signal DIA12_dly : std_logic := 'X'; - signal DIA11_ipd : std_logic := 'X'; - signal DIA11_dly : std_logic := 'X'; - signal DIA9_ipd : std_logic := 'X'; - signal DIA9_dly : std_logic := 'X'; - signal ADA13_ipd : std_logic := 'X'; - signal ADA13_dly : std_logic := 'X'; - signal ADA12_ipd : std_logic := 'X'; - signal ADA12_dly : std_logic := 'X'; - signal ADA11_ipd : std_logic := 'X'; - signal ADA11_dly : std_logic := 'X'; - signal ADA10_ipd : std_logic := 'X'; - signal ADA10_dly : std_logic := 'X'; - signal ADA9_ipd : std_logic := 'X'; - signal ADA9_dly : std_logic := 'X'; - signal ADA8_ipd : std_logic := 'X'; - signal ADA8_dly : std_logic := 'X'; - signal ADA7_ipd : std_logic := 'X'; - signal ADA7_dly : std_logic := 'X'; - signal ADA6_ipd : std_logic := 'X'; - signal ADA6_dly : std_logic := 'X'; - signal ADA5_ipd : std_logic := 'X'; - signal ADA5_dly : std_logic := 'X'; - signal DOA17_out : std_logic := 'X'; - signal DOA16_out : std_logic := 'X'; - signal DOA15_out : std_logic := 'X'; - signal DOA14_out : std_logic := 'X'; - signal DOA13_out : std_logic := 'X'; - signal DOA12_out : std_logic := 'X'; - signal DOA11_out : std_logic := 'X'; - signal DOA10_out : std_logic := 'X'; - signal DOA9_out : std_logic := 'X'; - signal DOA8_out : std_logic := 'X'; - signal DOA7_out : std_logic := 'X'; - signal DOA6_out : std_logic := 'X'; - signal DOA5_out : std_logic := 'X'; - signal DOA4_out : std_logic := 'X'; - signal DOA3_out : std_logic := 'X'; - signal DOA2_out : std_logic := 'X'; - signal DOA1_out : std_logic := 'X'; - signal DOA0_out : std_logic := 'X'; - signal CEA_ipd : std_logic := 'X'; - signal CEA_dly : std_logic := 'X'; - signal CLKA_ipd : std_logic := 'X'; - signal CLKA_dly : std_logic := 'X'; - signal CLKB_ipd : std_logic := 'X'; - signal CLKB_dly : std_logic := 'X'; - signal OCEB_ipd : std_logic := 'X'; - signal OCEB_dly : std_logic := 'X'; - signal CEB_ipd : std_logic := 'X'; - signal CEB_dly : std_logic := 'X'; - signal DOB0_out : std_logic := 'X'; - signal DOB1_out : std_logic := 'X'; - signal DOB2_out : std_logic := 'X'; - signal DOB3_out : std_logic := 'X'; - signal DOB4_out : std_logic := 'X'; - signal DOB5_out : std_logic := 'X'; - signal ADB5_ipd : std_logic := 'X'; - signal ADB5_dly : std_logic := 'X'; - signal ADB6_ipd : std_logic := 'X'; - signal ADB6_dly : std_logic := 'X'; - signal ADB7_ipd : std_logic := 'X'; - signal ADB7_dly : std_logic := 'X'; - signal ADB8_ipd : std_logic := 'X'; - signal ADB8_dly : std_logic := 'X'; - signal ADB9_ipd : std_logic := 'X'; - signal ADB9_dly : std_logic := 'X'; - signal ADB10_ipd : std_logic := 'X'; - signal ADB10_dly : std_logic := 'X'; - signal ADB11_ipd : std_logic := 'X'; - signal ADB11_dly : std_logic := 'X'; - signal ADB12_ipd : std_logic := 'X'; - signal ADB12_dly : std_logic := 'X'; - signal ADB13_ipd : std_logic := 'X'; - signal ADB13_dly : std_logic := 'X'; - signal DIB6_ipd : std_logic := 'X'; - signal DIB6_dly : std_logic := 'X'; - signal DIB8_ipd : std_logic := 'X'; - signal DIB8_dly : std_logic := 'X'; - signal DIB9_ipd : std_logic := 'X'; - signal DIB9_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component PDPW16KD0254 - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - end component; - begin - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0_PDPW16KD: PDPW16KD0254 - port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, - CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, - CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, - BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>GNDI, DI1=>GNDI, - DI2=>GNDI, DI3=>GNDI, DI4=>GNDI, DI5=>GNDI, DI6=>GNDI, - DI7=>GNDI, DI8=>GNDI, DI9=>DIA9_dly, DI10=>GNDI, - DI11=>DIA11_dly, DI12=>DIA12_dly, DI13=>DIA13_dly, DI14=>GNDI, - DI15=>DIA15_dly, DI16=>GNDI, DI17=>GNDI, DI18=>GNDI, - DI19=>GNDI, DI20=>GNDI, DI21=>GNDI, DI22=>GNDI, DI23=>GNDI, - DI24=>DIB6_dly, DI25=>GNDI, DI26=>DIB8_dly, DI27=>DIB9_dly, - DI28=>GNDI, DI29=>GNDI, DI30=>GNDI, DI31=>GNDI, DI32=>GNDI, - DI33=>GNDI, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, - ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, - ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, - ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, - ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, - ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, - ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, - ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, - DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>open, - DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, - DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, - DO17=>open, DO18=>DOA0_out, DO19=>DOA1_out, DO20=>DOA2_out, - DO21=>DOA3_out, DO22=>DOA4_out, DO23=>DOA5_out, DO24=>DOA6_out, - DO25=>DOA7_out, DO26=>DOA8_out, DO27=>DOA9_out, - DO28=>DOA10_out, DO29=>DOA11_out, DO30=>DOA12_out, - DO31=>DOA13_out, DO32=>DOA14_out, DO33=>DOA15_out, - DO34=>DOA16_out, DO35=>DOA17_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15); - VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13); - VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12); - VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11); - VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9); - VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13); - VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12); - VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11); - VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10); - VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9); - VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8); - VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7); - VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6); - VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5); - VitalWireDelay(CEA_ipd, CEA, tipd_CEA); - VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA); - VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB); - VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB); - VitalWireDelay(CEB_ipd, CEB, tipd_CEB); - VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5); - VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6); - VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7); - VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8); - VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9); - VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10); - VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11); - VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12); - VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13); - VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6); - VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8); - VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA); - VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA); - VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA); - VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA); - VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA); - VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA); - VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA); - VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA); - VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA); - VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA); - VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA); - VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA); - VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA); - VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA); - VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA); - VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA); - VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB); - VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB); - VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB); - VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB); - VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB); - VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB); - VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB); - VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB); - VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB); - VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB); - VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB); - VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB); - VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA); - VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA); - VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA); - END BLOCK; - - VitalBehavior : PROCESS (DIA15_dly, DIA13_dly, DIA12_dly, DIA11_dly, - DIA9_dly, ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, - ADA7_dly, ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, - DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, - DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, - CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, - DOB2_out, DOB3_out, DOB4_out, DOB5_out, ADB5_dly, ADB6_dly, ADB7_dly, - ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, DIB6_dly, - DIB8_dly, DIB9_dly) - VARIABLE DOA17_zd : std_logic := 'X'; - VARIABLE DOA17_GlitchData : VitalGlitchDataType; - VARIABLE DOA16_zd : std_logic := 'X'; - VARIABLE DOA16_GlitchData : VitalGlitchDataType; - VARIABLE DOA15_zd : std_logic := 'X'; - VARIABLE DOA15_GlitchData : VitalGlitchDataType; - VARIABLE DOA14_zd : std_logic := 'X'; - VARIABLE DOA14_GlitchData : VitalGlitchDataType; - VARIABLE DOA13_zd : std_logic := 'X'; - VARIABLE DOA13_GlitchData : VitalGlitchDataType; - VARIABLE DOA12_zd : std_logic := 'X'; - VARIABLE DOA12_GlitchData : VitalGlitchDataType; - VARIABLE DOA11_zd : std_logic := 'X'; - VARIABLE DOA11_GlitchData : VitalGlitchDataType; - VARIABLE DOA10_zd : std_logic := 'X'; - VARIABLE DOA10_GlitchData : VitalGlitchDataType; - VARIABLE DOA9_zd : std_logic := 'X'; - VARIABLE DOA9_GlitchData : VitalGlitchDataType; - VARIABLE DOA8_zd : std_logic := 'X'; - VARIABLE DOA8_GlitchData : VitalGlitchDataType; - VARIABLE DOA7_zd : std_logic := 'X'; - VARIABLE DOA7_GlitchData : VitalGlitchDataType; - VARIABLE DOA6_zd : std_logic := 'X'; - VARIABLE DOA6_GlitchData : VitalGlitchDataType; - VARIABLE DOA5_zd : std_logic := 'X'; - VARIABLE DOA5_GlitchData : VitalGlitchDataType; - VARIABLE DOA4_zd : std_logic := 'X'; - VARIABLE DOA4_GlitchData : VitalGlitchDataType; - VARIABLE DOA3_zd : std_logic := 'X'; - VARIABLE DOA3_GlitchData : VitalGlitchDataType; - VARIABLE DOA2_zd : std_logic := 'X'; - VARIABLE DOA2_GlitchData : VitalGlitchDataType; - VARIABLE DOA1_zd : std_logic := 'X'; - VARIABLE DOA1_GlitchData : VitalGlitchDataType; - VARIABLE DOA0_zd : std_logic := 'X'; - VARIABLE DOA0_GlitchData : VitalGlitchDataType; - VARIABLE DOB0_zd : std_logic := 'X'; - VARIABLE DOB0_GlitchData : VitalGlitchDataType; - VARIABLE DOB1_zd : std_logic := 'X'; - VARIABLE DOB1_GlitchData : VitalGlitchDataType; - VARIABLE DOB2_zd : std_logic := 'X'; - VARIABLE DOB2_GlitchData : VitalGlitchDataType; - VARIABLE DOB3_zd : std_logic := 'X'; - VARIABLE DOB3_GlitchData : VitalGlitchDataType; - VARIABLE DOB4_zd : std_logic := 'X'; - VARIABLE DOB4_GlitchData : VitalGlitchDataType; - VARIABLE DOB5_zd : std_logic := 'X'; - VARIABLE DOB5_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DIA15_CLKA : x01 := '0'; - VARIABLE DIA15_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA13_CLKA : x01 := '0'; - VARIABLE DIA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA12_CLKA : x01 := '0'; - VARIABLE DIA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA11_CLKA : x01 := '0'; - VARIABLE DIA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA9_CLKA : x01 := '0'; - VARIABLE DIA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA13_CLKA : x01 := '0'; - VARIABLE ADA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA12_CLKA : x01 := '0'; - VARIABLE ADA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA11_CLKA : x01 := '0'; - VARIABLE ADA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA10_CLKA : x01 := '0'; - VARIABLE ADA10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA9_CLKA : x01 := '0'; - VARIABLE ADA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA8_CLKA : x01 := '0'; - VARIABLE ADA8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA7_CLKA : x01 := '0'; - VARIABLE ADA7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA6_CLKA : x01 := '0'; - VARIABLE ADA6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA5_CLKA : x01 := '0'; - VARIABLE ADA5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEA_CLKA : x01 := '0'; - VARIABLE CEA_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_OCEB_CLKB : x01 := '0'; - VARIABLE OCEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEB_CLKB : x01 := '0'; - VARIABLE CEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB5_CLKB : x01 := '0'; - VARIABLE ADB5_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB6_CLKB : x01 := '0'; - VARIABLE ADB6_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB7_CLKB : x01 := '0'; - VARIABLE ADB7_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB8_CLKB : x01 := '0'; - VARIABLE ADB8_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB9_CLKB : x01 := '0'; - VARIABLE ADB9_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB10_CLKB : x01 := '0'; - VARIABLE ADB10_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB11_CLKB : x01 := '0'; - VARIABLE ADB11_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB12_CLKB : x01 := '0'; - VARIABLE ADB12_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB13_CLKB : x01 := '0'; - VARIABLE ADB13_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB6_CLKA : x01 := '0'; - VARIABLE DIB6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB8_CLKA : x01 := '0'; - VARIABLE DIB8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB9_CLKA : x01 := '0'; - VARIABLE DIB9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLKA_CLKA : x01 := '0'; - VARIABLE periodcheckinfo_CLKA : VitalPeriodDataType; - VARIABLE tviol_CLKB_CLKB : x01 := '0'; - VARIABLE periodcheckinfo_CLKB : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DIA15_dly, - TestSignalName => "DIA15", - TestDelay => tisd_DIA15_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA15_CLKA_noedge_posedge, - SetupLow => tsetup_DIA15_CLKA_noedge_posedge, - HoldHigh => thold_DIA15_CLKA_noedge_posedge, - HoldLow => thold_DIA15_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA15_CLKA_TimingDatash, - Violation => tviol_DIA15_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA13_dly, - TestSignalName => "DIA13", - TestDelay => tisd_DIA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA13_CLKA_noedge_posedge, - SetupLow => tsetup_DIA13_CLKA_noedge_posedge, - HoldHigh => thold_DIA13_CLKA_noedge_posedge, - HoldLow => thold_DIA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA13_CLKA_TimingDatash, - Violation => tviol_DIA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA12_dly, - TestSignalName => "DIA12", - TestDelay => tisd_DIA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA12_CLKA_noedge_posedge, - SetupLow => tsetup_DIA12_CLKA_noedge_posedge, - HoldHigh => thold_DIA12_CLKA_noedge_posedge, - HoldLow => thold_DIA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA12_CLKA_TimingDatash, - Violation => tviol_DIA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA11_dly, - TestSignalName => "DIA11", - TestDelay => tisd_DIA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA11_CLKA_noedge_posedge, - SetupLow => tsetup_DIA11_CLKA_noedge_posedge, - HoldHigh => thold_DIA11_CLKA_noedge_posedge, - HoldLow => thold_DIA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA11_CLKA_TimingDatash, - Violation => tviol_DIA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA9_dly, - TestSignalName => "DIA9", - TestDelay => tisd_DIA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA9_CLKA_noedge_posedge, - SetupLow => tsetup_DIA9_CLKA_noedge_posedge, - HoldHigh => thold_DIA9_CLKA_noedge_posedge, - HoldLow => thold_DIA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA9_CLKA_TimingDatash, - Violation => tviol_DIA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA13_dly, - TestSignalName => "ADA13", - TestDelay => tisd_ADA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA13_CLKA_noedge_posedge, - SetupLow => tsetup_ADA13_CLKA_noedge_posedge, - HoldHigh => thold_ADA13_CLKA_noedge_posedge, - HoldLow => thold_ADA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA13_CLKA_TimingDatash, - Violation => tviol_ADA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA12_dly, - TestSignalName => "ADA12", - TestDelay => tisd_ADA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA12_CLKA_noedge_posedge, - SetupLow => tsetup_ADA12_CLKA_noedge_posedge, - HoldHigh => thold_ADA12_CLKA_noedge_posedge, - HoldLow => thold_ADA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA12_CLKA_TimingDatash, - Violation => tviol_ADA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA11_dly, - TestSignalName => "ADA11", - TestDelay => tisd_ADA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA11_CLKA_noedge_posedge, - SetupLow => tsetup_ADA11_CLKA_noedge_posedge, - HoldHigh => thold_ADA11_CLKA_noedge_posedge, - HoldLow => thold_ADA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA11_CLKA_TimingDatash, - Violation => tviol_ADA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA10_dly, - TestSignalName => "ADA10", - TestDelay => tisd_ADA10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA10_CLKA_noedge_posedge, - SetupLow => tsetup_ADA10_CLKA_noedge_posedge, - HoldHigh => thold_ADA10_CLKA_noedge_posedge, - HoldLow => thold_ADA10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA10_CLKA_TimingDatash, - Violation => tviol_ADA10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA9_dly, - TestSignalName => "ADA9", - TestDelay => tisd_ADA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA9_CLKA_noedge_posedge, - SetupLow => tsetup_ADA9_CLKA_noedge_posedge, - HoldHigh => thold_ADA9_CLKA_noedge_posedge, - HoldLow => thold_ADA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA9_CLKA_TimingDatash, - Violation => tviol_ADA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA8_dly, - TestSignalName => "ADA8", - TestDelay => tisd_ADA8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA8_CLKA_noedge_posedge, - SetupLow => tsetup_ADA8_CLKA_noedge_posedge, - HoldHigh => thold_ADA8_CLKA_noedge_posedge, - HoldLow => thold_ADA8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA8_CLKA_TimingDatash, - Violation => tviol_ADA8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA7_dly, - TestSignalName => "ADA7", - TestDelay => tisd_ADA7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA7_CLKA_noedge_posedge, - SetupLow => tsetup_ADA7_CLKA_noedge_posedge, - HoldHigh => thold_ADA7_CLKA_noedge_posedge, - HoldLow => thold_ADA7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA7_CLKA_TimingDatash, - Violation => tviol_ADA7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA6_dly, - TestSignalName => "ADA6", - TestDelay => tisd_ADA6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA6_CLKA_noedge_posedge, - SetupLow => tsetup_ADA6_CLKA_noedge_posedge, - HoldHigh => thold_ADA6_CLKA_noedge_posedge, - HoldLow => thold_ADA6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA6_CLKA_TimingDatash, - Violation => tviol_ADA6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA5_dly, - TestSignalName => "ADA5", - TestDelay => tisd_ADA5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA5_CLKA_noedge_posedge, - SetupLow => tsetup_ADA5_CLKA_noedge_posedge, - HoldHigh => thold_ADA5_CLKA_noedge_posedge, - HoldLow => thold_ADA5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA5_CLKA_TimingDatash, - Violation => tviol_ADA5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEA_dly, - TestSignalName => "CEA", - TestDelay => tisd_CEA_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_CEA_CLKA_noedge_posedge, - SetupLow => tsetup_CEA_CLKA_noedge_posedge, - HoldHigh => thold_CEA_CLKA_noedge_posedge, - HoldLow => thold_CEA_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEA_CLKA_TimingDatash, - Violation => tviol_CEA_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => OCEB_dly, - TestSignalName => "OCEB", - TestDelay => tisd_OCEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_OCEB_CLKB_noedge_posedge, - SetupLow => tsetup_OCEB_CLKB_noedge_posedge, - HoldHigh => thold_OCEB_CLKB_noedge_posedge, - HoldLow => thold_OCEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => OCEB_CLKB_TimingDatash, - Violation => tviol_OCEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEB_dly, - TestSignalName => "CEB", - TestDelay => tisd_CEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_CEB_CLKB_noedge_posedge, - SetupLow => tsetup_CEB_CLKB_noedge_posedge, - HoldHigh => thold_CEB_CLKB_noedge_posedge, - HoldLow => thold_CEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEB_CLKB_TimingDatash, - Violation => tviol_CEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB5_dly, - TestSignalName => "ADB5", - TestDelay => tisd_ADB5_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB5_CLKB_noedge_posedge, - SetupLow => tsetup_ADB5_CLKB_noedge_posedge, - HoldHigh => thold_ADB5_CLKB_noedge_posedge, - HoldLow => thold_ADB5_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB5_CLKB_TimingDatash, - Violation => tviol_ADB5_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB6_dly, - TestSignalName => "ADB6", - TestDelay => tisd_ADB6_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB6_CLKB_noedge_posedge, - SetupLow => tsetup_ADB6_CLKB_noedge_posedge, - HoldHigh => thold_ADB6_CLKB_noedge_posedge, - HoldLow => thold_ADB6_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB6_CLKB_TimingDatash, - Violation => tviol_ADB6_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB7_dly, - TestSignalName => "ADB7", - TestDelay => tisd_ADB7_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB7_CLKB_noedge_posedge, - SetupLow => tsetup_ADB7_CLKB_noedge_posedge, - HoldHigh => thold_ADB7_CLKB_noedge_posedge, - HoldLow => thold_ADB7_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB7_CLKB_TimingDatash, - Violation => tviol_ADB7_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB8_dly, - TestSignalName => "ADB8", - TestDelay => tisd_ADB8_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB8_CLKB_noedge_posedge, - SetupLow => tsetup_ADB8_CLKB_noedge_posedge, - HoldHigh => thold_ADB8_CLKB_noedge_posedge, - HoldLow => thold_ADB8_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB8_CLKB_TimingDatash, - Violation => tviol_ADB8_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB9_dly, - TestSignalName => "ADB9", - TestDelay => tisd_ADB9_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB9_CLKB_noedge_posedge, - SetupLow => tsetup_ADB9_CLKB_noedge_posedge, - HoldHigh => thold_ADB9_CLKB_noedge_posedge, - HoldLow => thold_ADB9_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB9_CLKB_TimingDatash, - Violation => tviol_ADB9_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB10_dly, - TestSignalName => "ADB10", - TestDelay => tisd_ADB10_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB10_CLKB_noedge_posedge, - SetupLow => tsetup_ADB10_CLKB_noedge_posedge, - HoldHigh => thold_ADB10_CLKB_noedge_posedge, - HoldLow => thold_ADB10_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB10_CLKB_TimingDatash, - Violation => tviol_ADB10_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB11_dly, - TestSignalName => "ADB11", - TestDelay => tisd_ADB11_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB11_CLKB_noedge_posedge, - SetupLow => tsetup_ADB11_CLKB_noedge_posedge, - HoldHigh => thold_ADB11_CLKB_noedge_posedge, - HoldLow => thold_ADB11_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB11_CLKB_TimingDatash, - Violation => tviol_ADB11_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB12_dly, - TestSignalName => "ADB12", - TestDelay => tisd_ADB12_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB12_CLKB_noedge_posedge, - SetupLow => tsetup_ADB12_CLKB_noedge_posedge, - HoldHigh => thold_ADB12_CLKB_noedge_posedge, - HoldLow => thold_ADB12_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB12_CLKB_TimingDatash, - Violation => tviol_ADB12_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB13_dly, - TestSignalName => "ADB13", - TestDelay => tisd_ADB13_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB13_CLKB_noedge_posedge, - SetupLow => tsetup_ADB13_CLKB_noedge_posedge, - HoldHigh => thold_ADB13_CLKB_noedge_posedge, - HoldLow => thold_ADB13_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB13_CLKB_TimingDatash, - Violation => tviol_ADB13_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB6_dly, - TestSignalName => "DIB6", - TestDelay => tisd_DIB6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB6_CLKA_noedge_posedge, - SetupLow => tsetup_DIB6_CLKA_noedge_posedge, - HoldHigh => thold_DIB6_CLKA_noedge_posedge, - HoldLow => thold_DIB6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB6_CLKA_TimingDatash, - Violation => tviol_DIB6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB8_dly, - TestSignalName => "DIB8", - TestDelay => tisd_DIB8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB8_CLKA_noedge_posedge, - SetupLow => tsetup_DIB8_CLKA_noedge_posedge, - HoldHigh => thold_DIB8_CLKA_noedge_posedge, - HoldLow => thold_DIB8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB8_CLKA_TimingDatash, - Violation => tviol_DIB8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB9_dly, - TestSignalName => "DIB9", - TestDelay => tisd_DIB9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB9_CLKA_noedge_posedge, - SetupLow => tsetup_DIB9_CLKA_noedge_posedge, - HoldHigh => thold_DIB9_CLKA_noedge_posedge, - HoldLow => thold_DIB9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB9_CLKA_TimingDatash, - Violation => tviol_DIB9_CLKA, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKA_ipd, - TestSignalName => "CLKA", - Period => tperiod_CLKA, - PulseWidthHigh => tpw_CLKA_posedge, - PulseWidthLow => tpw_CLKA_negedge, - PeriodData => periodcheckinfo_CLKA, - Violation => tviol_CLKA_CLKA, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKB_ipd, - TestSignalName => "CLKB", - Period => tperiod_CLKB, - PulseWidthHigh => tpw_CLKB_posedge, - PulseWidthLow => tpw_CLKB_negedge, - PeriodData => periodcheckinfo_CLKB, - Violation => tviol_CLKB_CLKB, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - DOA17_zd := DOA17_out; - DOA16_zd := DOA16_out; - DOA15_zd := DOA15_out; - DOA14_zd := DOA14_out; - DOA13_zd := DOA13_out; - DOA12_zd := DOA12_out; - DOA11_zd := DOA11_out; - DOA10_zd := DOA10_out; - DOA9_zd := DOA9_out; - DOA8_zd := DOA8_out; - DOA7_zd := DOA7_out; - DOA6_zd := DOA6_out; - DOA5_zd := DOA5_out; - DOA4_zd := DOA4_out; - DOA3_zd := DOA3_out; - DOA2_zd := DOA2_out; - DOA1_zd := DOA1_out; - DOA0_zd := DOA0_out; - DOB0_zd := DOB0_out; - DOB1_zd := DOB1_out; - DOB2_zd := DOB2_out; - DOB3_zd := DOB3_out; - DOB4_zd := DOB4_out; - DOB5_zd := DOB5_out; - - VitalPathDelay01 ( - OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA17, - PathCondition => TRUE)), - GlitchData => DOA17_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA16, - PathCondition => TRUE)), - GlitchData => DOA16_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA15, - PathCondition => TRUE)), - GlitchData => DOA15_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA14, - PathCondition => TRUE)), - GlitchData => DOA14_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA13, - PathCondition => TRUE)), - GlitchData => DOA13_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA12, - PathCondition => TRUE)), - GlitchData => DOA12_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA11, - PathCondition => TRUE)), - GlitchData => DOA11_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA10, - PathCondition => TRUE)), - GlitchData => DOA10_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA9, - PathCondition => TRUE)), - GlitchData => DOA9_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA8, - PathCondition => TRUE)), - GlitchData => DOA8_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA7, - PathCondition => TRUE)), - GlitchData => DOA7_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA6, - PathCondition => TRUE)), - GlitchData => DOA6_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA5, - PathCondition => TRUE)), - GlitchData => DOA5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA4, - PathCondition => TRUE)), - GlitchData => DOA4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA3, - PathCondition => TRUE)), - GlitchData => DOA3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA2, - PathCondition => TRUE)), - GlitchData => DOA2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA1, - PathCondition => TRUE)), - GlitchData => DOA1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA0, - PathCondition => TRUE)), - GlitchData => DOA0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB0, - PathCondition => TRUE)), - GlitchData => DOB0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB1, - PathCondition => TRUE)), - GlitchData => DOB1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB2, - PathCondition => TRUE)), - GlitchData => DOB2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB3, - PathCondition => TRUE)), - GlitchData => DOB3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB4, - PathCondition => TRUE)), - GlitchData => DOB4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB5, - PathCondition => TRUE)), - GlitchData => DOB5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity PDPW16KD0255 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity PDPW16KD0255 is - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - - ATTRIBUTE Vital_Level0 OF PDPW16KD0255 : ENTITY IS TRUE; - - end PDPW16KD0255; - - architecture Structure of PDPW16KD0255 is - begin - INST10: PDPW16KD - generic map (ASYNC_RESET_RELEASE => "SYNC", CSDECODE_R => "0b000", - CSDECODE_W => "0b001", DATA_WIDTH_R => 36, - DATA_WIDTH_W => 36, GSR => "DISABLED", - INITVAL_00 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_01 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_02 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_03 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_04 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_05 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_06 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_07 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_08 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_09 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_0F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_10 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_11 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_12 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_13 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_14 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_15 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_16 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_17 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_18 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_19 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_1F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_20 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_21 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_22 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_23 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_24 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_25 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_26 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_27 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_28 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_29 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_2F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_30 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_31 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_32 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_33 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_34 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_35 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_36 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_37 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_38 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_39 => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3A => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3B => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3C => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3D => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3E => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , - INITVAL_3F => "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" - , INIT_DATA => "STATIC", REGMODE => "NOREG", - RESETMODE => "ASYNC") - port map (DI0=>DI0, DI1=>DI1, DI2=>DI2, DI3=>DI3, DI4=>DI4, DI5=>DI5, - DI6=>DI6, DI7=>DI7, DI8=>DI8, DI9=>DI9, DI10=>DI10, DI11=>DI11, - DI12=>DI12, DI13=>DI13, DI14=>DI14, DI15=>DI15, DI16=>DI16, - DI17=>DI17, DI18=>DI18, DI19=>DI19, DI20=>DI20, DI21=>DI21, - DI22=>DI22, DI23=>DI23, DI24=>DI24, DI25=>DI25, DI26=>DI26, - DI27=>DI27, DI28=>DI28, DI29=>DI29, DI30=>DI30, DI31=>DI31, - DI32=>DI32, DI33=>DI33, DI34=>DI34, DI35=>DI35, ADW0=>ADW0, - ADW1=>ADW1, ADW2=>ADW2, ADW3=>ADW3, ADW4=>ADW4, ADW5=>ADW5, - ADW6=>ADW6, ADW7=>ADW7, ADW8=>ADW8, BE0=>BE0, BE1=>BE1, - BE2=>BE2, BE3=>BE3, CEW=>CEW, CLKW=>CLKW, CSW0=>CSW0, - CSW1=>CSW1, CSW2=>CSW2, ADR0=>ADR0, ADR1=>ADR1, ADR2=>ADR2, - ADR3=>ADR3, ADR4=>ADR4, ADR5=>ADR5, ADR6=>ADR6, ADR7=>ADR7, - ADR8=>ADR8, ADR9=>ADR9, ADR10=>ADR10, ADR11=>ADR11, - ADR12=>ADR12, ADR13=>ADR13, CER=>CER, CLKR=>CLKR, CSR0=>CSR0, - CSR1=>CSR1, CSR2=>CSR2, RST=>RST, OCER=>OCER, DO0=>DO0, - DO1=>DO1, DO2=>DO2, DO3=>DO3, DO4=>DO4, DO5=>DO5, DO6=>DO6, - DO7=>DO7, DO8=>DO8, DO9=>DO9, DO10=>DO10, DO11=>DO11, - DO12=>DO12, DO13=>DO13, DO14=>DO14, DO15=>DO15, DO16=>DO16, - DO17=>DO17, DO18=>DO18, DO19=>DO19, DO20=>DO20, DO21=>DO21, - DO22=>DO22, DO23=>DO23, DO24=>DO24, DO25=>DO25, DO26=>DO26, - DO27=>DO27, DO28=>DO28, DO29=>DO29, DO30=>DO30, DO31=>DO31, - DO32=>DO32, DO33=>DO33, DO34=>DO34, DO35=>DO35); - end Structure; - --- entity fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1"; - - tipd_DIA17 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA16 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA15 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA14 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA4 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA3 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA2 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIA0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADA5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKA : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKB : VitalDelayType01 := (0 ns, 0 ns); - tipd_OCEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_CEB : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_ADB13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB0 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB1 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB2 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB3 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB4 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB5 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB6 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB7 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB8 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB9 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB10 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB11 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB12 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB13 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB14 : VitalDelayType01 := (0 ns, 0 ns); - tipd_DIB15 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA17 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA16 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA15 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA14 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA13 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA12 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA11 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA10 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOA0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB0 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB1 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB4 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB5 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB6 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB7 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB8 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB9 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB10 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB11 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB12 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKB_DOB13 : VitalDelayType01 := (0 ns, 0 ns); - ticd_CLKA : VitalDelayType := 0 ns; - tisd_DIA17_CLKA : VitalDelayType := 0 ns; - tsetup_DIA17_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA17_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA16_CLKA : VitalDelayType := 0 ns; - tsetup_DIA16_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA16_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA15_CLKA : VitalDelayType := 0 ns; - tsetup_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA14_CLKA : VitalDelayType := 0 ns; - tsetup_DIA14_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA14_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA13_CLKA : VitalDelayType := 0 ns; - tsetup_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA12_CLKA : VitalDelayType := 0 ns; - tsetup_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA11_CLKA : VitalDelayType := 0 ns; - tsetup_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA10_CLKA : VitalDelayType := 0 ns; - tsetup_DIA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA9_CLKA : VitalDelayType := 0 ns; - tsetup_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA8_CLKA : VitalDelayType := 0 ns; - tsetup_DIA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA7_CLKA : VitalDelayType := 0 ns; - tsetup_DIA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA6_CLKA : VitalDelayType := 0 ns; - tsetup_DIA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA5_CLKA : VitalDelayType := 0 ns; - tsetup_DIA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA4_CLKA : VitalDelayType := 0 ns; - tsetup_DIA4_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA4_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA3_CLKA : VitalDelayType := 0 ns; - tsetup_DIA3_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA3_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA2_CLKA : VitalDelayType := 0 ns; - tsetup_DIA2_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA2_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA1_CLKA : VitalDelayType := 0 ns; - tsetup_DIA1_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA1_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIA0_CLKA : VitalDelayType := 0 ns; - tsetup_DIA0_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIA0_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA13_CLKA : VitalDelayType := 0 ns; - tsetup_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA12_CLKA : VitalDelayType := 0 ns; - tsetup_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA11_CLKA : VitalDelayType := 0 ns; - tsetup_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA10_CLKA : VitalDelayType := 0 ns; - tsetup_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA9_CLKA : VitalDelayType := 0 ns; - tsetup_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA8_CLKA : VitalDelayType := 0 ns; - tsetup_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA7_CLKA : VitalDelayType := 0 ns; - tsetup_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA6_CLKA : VitalDelayType := 0 ns; - tsetup_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADA5_CLKA : VitalDelayType := 0 ns; - tsetup_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_ADA5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEA_CLKA : VitalDelayType := 0 ns; - tsetup_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_CEA_CLKA_noedge_posedge : VitalDelayType := 0 ns; - ticd_CLKB : VitalDelayType := 0 ns; - tisd_OCEB_CLKB : VitalDelayType := 0 ns; - tsetup_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_OCEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_CEB_CLKB : VitalDelayType := 0 ns; - tsetup_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_CEB_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB5_CLKB : VitalDelayType := 0 ns; - tsetup_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB5_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB6_CLKB : VitalDelayType := 0 ns; - tsetup_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB6_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB7_CLKB : VitalDelayType := 0 ns; - tsetup_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB7_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB8_CLKB : VitalDelayType := 0 ns; - tsetup_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB8_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB9_CLKB : VitalDelayType := 0 ns; - tsetup_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB9_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB10_CLKB : VitalDelayType := 0 ns; - tsetup_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB10_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB11_CLKB : VitalDelayType := 0 ns; - tsetup_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB11_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB12_CLKB : VitalDelayType := 0 ns; - tsetup_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB12_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_ADB13_CLKB : VitalDelayType := 0 ns; - tsetup_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - thold_ADB13_CLKB_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB0_CLKA : VitalDelayType := 0 ns; - tsetup_DIB0_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB0_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB1_CLKA : VitalDelayType := 0 ns; - tsetup_DIB1_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB1_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB2_CLKA : VitalDelayType := 0 ns; - tsetup_DIB2_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB2_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB3_CLKA : VitalDelayType := 0 ns; - tsetup_DIB3_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB3_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB4_CLKA : VitalDelayType := 0 ns; - tsetup_DIB4_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB4_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB5_CLKA : VitalDelayType := 0 ns; - tsetup_DIB5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB5_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB6_CLKA : VitalDelayType := 0 ns; - tsetup_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB6_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB7_CLKA : VitalDelayType := 0 ns; - tsetup_DIB7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB7_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB8_CLKA : VitalDelayType := 0 ns; - tsetup_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB8_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB9_CLKA : VitalDelayType := 0 ns; - tsetup_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB9_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB10_CLKA : VitalDelayType := 0 ns; - tsetup_DIB10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB10_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB11_CLKA : VitalDelayType := 0 ns; - tsetup_DIB11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB11_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB12_CLKA : VitalDelayType := 0 ns; - tsetup_DIB12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB12_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB13_CLKA : VitalDelayType := 0 ns; - tsetup_DIB13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB13_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB14_CLKA : VitalDelayType := 0 ns; - tsetup_DIB14_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB14_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tisd_DIB15_CLKA : VitalDelayType := 0 ns; - tsetup_DIB15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - thold_DIB15_CLKA_noedge_posedge : VitalDelayType := 0 ns; - tperiod_CLKA : VitalDelayType := 0 ns; - tpw_CLKA_posedge : VitalDelayType := 0 ns; - tpw_CLKA_negedge : VitalDelayType := 0 ns; - tperiod_CLKB : VitalDelayType := 0 ns; - tpw_CLKB_posedge : VitalDelayType := 0 ns; - tpw_CLKB_negedge : VitalDelayType := 0 ns); - - port (DIA17: in Std_logic; DIA16: in Std_logic; DIA15: in Std_logic; - DIA14: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA10: in Std_logic; DIA9: in Std_logic; - DIA8: in Std_logic; DIA7: in Std_logic; DIA6: in Std_logic; - DIA5: in Std_logic; DIA4: in Std_logic; DIA3: in Std_logic; - DIA2: in Std_logic; DIA1: in Std_logic; DIA0: in Std_logic; - ADA13: in Std_logic; ADA12: in Std_logic; ADA11: in Std_logic; - ADA10: in Std_logic; ADA9: in Std_logic; ADA8: in Std_logic; - ADA7: in Std_logic; ADA6: in Std_logic; ADA5: in Std_logic; - DOA17: out Std_logic; DOA16: out Std_logic; DOA15: out Std_logic; - DOA14: out Std_logic; DOA13: out Std_logic; DOA12: out Std_logic; - DOA11: out Std_logic; DOA10: out Std_logic; DOA9: out Std_logic; - DOA8: out Std_logic; DOA7: out Std_logic; DOA6: out Std_logic; - DOA5: out Std_logic; DOA4: out Std_logic; DOA3: out Std_logic; - DOA2: out Std_logic; DOA1: out Std_logic; DOA0: out Std_logic; - CEA: in Std_logic; CLKA: in Std_logic; CLKB: in Std_logic; - OCEB: in Std_logic; CEB: in Std_logic; DOB0: out Std_logic; - DOB1: out Std_logic; DOB2: out Std_logic; DOB3: out Std_logic; - DOB4: out Std_logic; DOB5: out Std_logic; DOB6: out Std_logic; - DOB7: out Std_logic; DOB8: out Std_logic; DOB9: out Std_logic; - DOB10: out Std_logic; DOB11: out Std_logic; DOB12: out Std_logic; - DOB13: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB0: in Std_logic; DIB1: in Std_logic; - DIB2: in Std_logic; DIB3: in Std_logic; DIB4: in Std_logic; - DIB5: in Std_logic; DIB6: in Std_logic; DIB7: in Std_logic; - DIB8: in Std_logic; DIB9: in Std_logic; DIB10: in Std_logic; - DIB11: in Std_logic; DIB12: in Std_logic; DIB13: in Std_logic; - DIB14: in Std_logic; DIB15: in Std_logic); - - - ATTRIBUTE Vital_Level0 OF fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 : ENTITY IS TRUE; - - end fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1; - - architecture Structure of fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 is - ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; - - signal DIA17_ipd : std_logic := 'X'; - signal DIA17_dly : std_logic := 'X'; - signal DIA16_ipd : std_logic := 'X'; - signal DIA16_dly : std_logic := 'X'; - signal DIA15_ipd : std_logic := 'X'; - signal DIA15_dly : std_logic := 'X'; - signal DIA14_ipd : std_logic := 'X'; - signal DIA14_dly : std_logic := 'X'; - signal DIA13_ipd : std_logic := 'X'; - signal DIA13_dly : std_logic := 'X'; - signal DIA12_ipd : std_logic := 'X'; - signal DIA12_dly : std_logic := 'X'; - signal DIA11_ipd : std_logic := 'X'; - signal DIA11_dly : std_logic := 'X'; - signal DIA10_ipd : std_logic := 'X'; - signal DIA10_dly : std_logic := 'X'; - signal DIA9_ipd : std_logic := 'X'; - signal DIA9_dly : std_logic := 'X'; - signal DIA8_ipd : std_logic := 'X'; - signal DIA8_dly : std_logic := 'X'; - signal DIA7_ipd : std_logic := 'X'; - signal DIA7_dly : std_logic := 'X'; - signal DIA6_ipd : std_logic := 'X'; - signal DIA6_dly : std_logic := 'X'; - signal DIA5_ipd : std_logic := 'X'; - signal DIA5_dly : std_logic := 'X'; - signal DIA4_ipd : std_logic := 'X'; - signal DIA4_dly : std_logic := 'X'; - signal DIA3_ipd : std_logic := 'X'; - signal DIA3_dly : std_logic := 'X'; - signal DIA2_ipd : std_logic := 'X'; - signal DIA2_dly : std_logic := 'X'; - signal DIA1_ipd : std_logic := 'X'; - signal DIA1_dly : std_logic := 'X'; - signal DIA0_ipd : std_logic := 'X'; - signal DIA0_dly : std_logic := 'X'; - signal ADA13_ipd : std_logic := 'X'; - signal ADA13_dly : std_logic := 'X'; - signal ADA12_ipd : std_logic := 'X'; - signal ADA12_dly : std_logic := 'X'; - signal ADA11_ipd : std_logic := 'X'; - signal ADA11_dly : std_logic := 'X'; - signal ADA10_ipd : std_logic := 'X'; - signal ADA10_dly : std_logic := 'X'; - signal ADA9_ipd : std_logic := 'X'; - signal ADA9_dly : std_logic := 'X'; - signal ADA8_ipd : std_logic := 'X'; - signal ADA8_dly : std_logic := 'X'; - signal ADA7_ipd : std_logic := 'X'; - signal ADA7_dly : std_logic := 'X'; - signal ADA6_ipd : std_logic := 'X'; - signal ADA6_dly : std_logic := 'X'; - signal ADA5_ipd : std_logic := 'X'; - signal ADA5_dly : std_logic := 'X'; - signal DOA17_out : std_logic := 'X'; - signal DOA16_out : std_logic := 'X'; - signal DOA15_out : std_logic := 'X'; - signal DOA14_out : std_logic := 'X'; - signal DOA13_out : std_logic := 'X'; - signal DOA12_out : std_logic := 'X'; - signal DOA11_out : std_logic := 'X'; - signal DOA10_out : std_logic := 'X'; - signal DOA9_out : std_logic := 'X'; - signal DOA8_out : std_logic := 'X'; - signal DOA7_out : std_logic := 'X'; - signal DOA6_out : std_logic := 'X'; - signal DOA5_out : std_logic := 'X'; - signal DOA4_out : std_logic := 'X'; - signal DOA3_out : std_logic := 'X'; - signal DOA2_out : std_logic := 'X'; - signal DOA1_out : std_logic := 'X'; - signal DOA0_out : std_logic := 'X'; - signal CEA_ipd : std_logic := 'X'; - signal CEA_dly : std_logic := 'X'; - signal CLKA_ipd : std_logic := 'X'; - signal CLKA_dly : std_logic := 'X'; - signal CLKB_ipd : std_logic := 'X'; - signal CLKB_dly : std_logic := 'X'; - signal OCEB_ipd : std_logic := 'X'; - signal OCEB_dly : std_logic := 'X'; - signal CEB_ipd : std_logic := 'X'; - signal CEB_dly : std_logic := 'X'; - signal DOB0_out : std_logic := 'X'; - signal DOB1_out : std_logic := 'X'; - signal DOB2_out : std_logic := 'X'; - signal DOB3_out : std_logic := 'X'; - signal DOB4_out : std_logic := 'X'; - signal DOB5_out : std_logic := 'X'; - signal DOB6_out : std_logic := 'X'; - signal DOB7_out : std_logic := 'X'; - signal DOB8_out : std_logic := 'X'; - signal DOB9_out : std_logic := 'X'; - signal DOB10_out : std_logic := 'X'; - signal DOB11_out : std_logic := 'X'; - signal DOB12_out : std_logic := 'X'; - signal DOB13_out : std_logic := 'X'; - signal ADB5_ipd : std_logic := 'X'; - signal ADB5_dly : std_logic := 'X'; - signal ADB6_ipd : std_logic := 'X'; - signal ADB6_dly : std_logic := 'X'; - signal ADB7_ipd : std_logic := 'X'; - signal ADB7_dly : std_logic := 'X'; - signal ADB8_ipd : std_logic := 'X'; - signal ADB8_dly : std_logic := 'X'; - signal ADB9_ipd : std_logic := 'X'; - signal ADB9_dly : std_logic := 'X'; - signal ADB10_ipd : std_logic := 'X'; - signal ADB10_dly : std_logic := 'X'; - signal ADB11_ipd : std_logic := 'X'; - signal ADB11_dly : std_logic := 'X'; - signal ADB12_ipd : std_logic := 'X'; - signal ADB12_dly : std_logic := 'X'; - signal ADB13_ipd : std_logic := 'X'; - signal ADB13_dly : std_logic := 'X'; - signal DIB0_ipd : std_logic := 'X'; - signal DIB0_dly : std_logic := 'X'; - signal DIB1_ipd : std_logic := 'X'; - signal DIB1_dly : std_logic := 'X'; - signal DIB2_ipd : std_logic := 'X'; - signal DIB2_dly : std_logic := 'X'; - signal DIB3_ipd : std_logic := 'X'; - signal DIB3_dly : std_logic := 'X'; - signal DIB4_ipd : std_logic := 'X'; - signal DIB4_dly : std_logic := 'X'; - signal DIB5_ipd : std_logic := 'X'; - signal DIB5_dly : std_logic := 'X'; - signal DIB6_ipd : std_logic := 'X'; - signal DIB6_dly : std_logic := 'X'; - signal DIB7_ipd : std_logic := 'X'; - signal DIB7_dly : std_logic := 'X'; - signal DIB8_ipd : std_logic := 'X'; - signal DIB8_dly : std_logic := 'X'; - signal DIB9_ipd : std_logic := 'X'; - signal DIB9_dly : std_logic := 'X'; - signal DIB10_ipd : std_logic := 'X'; - signal DIB10_dly : std_logic := 'X'; - signal DIB11_ipd : std_logic := 'X'; - signal DIB11_dly : std_logic := 'X'; - signal DIB12_ipd : std_logic := 'X'; - signal DIB12_dly : std_logic := 'X'; - signal DIB13_ipd : std_logic := 'X'; - signal DIB13_dly : std_logic := 'X'; - signal DIB14_ipd : std_logic := 'X'; - signal DIB14_dly : std_logic := 'X'; - signal DIB15_ipd : std_logic := 'X'; - signal DIB15_dly : std_logic := 'X'; - - signal VCCI: Std_logic; - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component vcc - port (PWR1: out Std_logic); - end component; - component PDPW16KD0255 - port (CEW: in Std_logic; CLKW: in Std_logic; CSW0: in Std_logic; - CSW1: in Std_logic; CSW2: in Std_logic; CER: in Std_logic; - OCER: in Std_logic; CLKR: in Std_logic; CSR0: in Std_logic; - CSR1: in Std_logic; CSR2: in Std_logic; RST: in Std_logic; - BE0: in Std_logic; BE1: in Std_logic; BE2: in Std_logic; - BE3: in Std_logic; DI0: in Std_logic; DI1: in Std_logic; - DI2: in Std_logic; DI3: in Std_logic; DI4: in Std_logic; - DI5: in Std_logic; DI6: in Std_logic; DI7: in Std_logic; - DI8: in Std_logic; DI9: in Std_logic; DI10: in Std_logic; - DI11: in Std_logic; DI12: in Std_logic; DI13: in Std_logic; - DI14: in Std_logic; DI15: in Std_logic; DI16: in Std_logic; - DI17: in Std_logic; DI18: in Std_logic; DI19: in Std_logic; - DI20: in Std_logic; DI21: in Std_logic; DI22: in Std_logic; - DI23: in Std_logic; DI24: in Std_logic; DI25: in Std_logic; - DI26: in Std_logic; DI27: in Std_logic; DI28: in Std_logic; - DI29: in Std_logic; DI30: in Std_logic; DI31: in Std_logic; - DI32: in Std_logic; DI33: in Std_logic; DI34: in Std_logic; - DI35: in Std_logic; ADW0: in Std_logic; ADW1: in Std_logic; - ADW2: in Std_logic; ADW3: in Std_logic; ADW4: in Std_logic; - ADW5: in Std_logic; ADW6: in Std_logic; ADW7: in Std_logic; - ADW8: in Std_logic; ADR0: in Std_logic; ADR1: in Std_logic; - ADR2: in Std_logic; ADR3: in Std_logic; ADR4: in Std_logic; - ADR5: in Std_logic; ADR6: in Std_logic; ADR7: in Std_logic; - ADR8: in Std_logic; ADR9: in Std_logic; ADR10: in Std_logic; - ADR11: in Std_logic; ADR12: in Std_logic; ADR13: in Std_logic; - DO0: out Std_logic; DO1: out Std_logic; DO2: out Std_logic; - DO3: out Std_logic; DO4: out Std_logic; DO5: out Std_logic; - DO6: out Std_logic; DO7: out Std_logic; DO8: out Std_logic; - DO9: out Std_logic; DO10: out Std_logic; DO11: out Std_logic; - DO12: out Std_logic; DO13: out Std_logic; DO14: out Std_logic; - DO15: out Std_logic; DO16: out Std_logic; DO17: out Std_logic; - DO18: out Std_logic; DO19: out Std_logic; DO20: out Std_logic; - DO21: out Std_logic; DO22: out Std_logic; DO23: out Std_logic; - DO24: out Std_logic; DO25: out Std_logic; DO26: out Std_logic; - DO27: out Std_logic; DO28: out Std_logic; DO29: out Std_logic; - DO30: out Std_logic; DO31: out Std_logic; DO32: out Std_logic; - DO33: out Std_logic; DO34: out Std_logic; DO35: out Std_logic); - end component; - begin - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1_PDPW16KD: PDPW16KD0255 - port map (CEW=>CEA_dly, CLKW=>CLKA_dly, CSW0=>VCCI, CSW1=>GNDI, - CSW2=>GNDI, CER=>CEB_dly, OCER=>OCEB_dly, CLKR=>CLKB_dly, - CSR0=>GNDI, CSR1=>GNDI, CSR2=>GNDI, RST=>GNDI, BE0=>VCCI, - BE1=>VCCI, BE2=>VCCI, BE3=>VCCI, DI0=>DIA0_dly, DI1=>DIA1_dly, - DI2=>DIA2_dly, DI3=>DIA3_dly, DI4=>DIA4_dly, DI5=>DIA5_dly, - DI6=>DIA6_dly, DI7=>DIA7_dly, DI8=>DIA8_dly, DI9=>DIA9_dly, - DI10=>DIA10_dly, DI11=>DIA11_dly, DI12=>DIA12_dly, - DI13=>DIA13_dly, DI14=>DIA14_dly, DI15=>DIA15_dly, - DI16=>DIA16_dly, DI17=>DIA17_dly, DI18=>DIB0_dly, - DI19=>DIB1_dly, DI20=>DIB2_dly, DI21=>DIB3_dly, DI22=>DIB4_dly, - DI23=>DIB5_dly, DI24=>DIB6_dly, DI25=>DIB7_dly, DI26=>DIB8_dly, - DI27=>DIB9_dly, DI28=>DIB10_dly, DI29=>DIB11_dly, - DI30=>DIB12_dly, DI31=>DIB13_dly, DI32=>DIB14_dly, - DI33=>DIB15_dly, DI34=>GNDI, DI35=>GNDI, ADW0=>ADA5_dly, - ADW1=>ADA6_dly, ADW2=>ADA7_dly, ADW3=>ADA8_dly, ADW4=>ADA9_dly, - ADW5=>ADA10_dly, ADW6=>ADA11_dly, ADW7=>ADA12_dly, - ADW8=>ADA13_dly, ADR0=>GNDI, ADR1=>GNDI, ADR2=>GNDI, - ADR3=>GNDI, ADR4=>GNDI, ADR5=>ADB5_dly, ADR6=>ADB6_dly, - ADR7=>ADB7_dly, ADR8=>ADB8_dly, ADR9=>ADB9_dly, - ADR10=>ADB10_dly, ADR11=>ADB11_dly, ADR12=>ADB12_dly, - ADR13=>ADB13_dly, DO0=>DOB0_out, DO1=>DOB1_out, DO2=>DOB2_out, - DO3=>DOB3_out, DO4=>DOB4_out, DO5=>DOB5_out, DO6=>DOB6_out, - DO7=>DOB7_out, DO8=>DOB8_out, DO9=>DOB9_out, DO10=>DOB10_out, - DO11=>DOB11_out, DO12=>DOB12_out, DO13=>DOB13_out, DO14=>open, - DO15=>open, DO16=>open, DO17=>open, DO18=>DOA0_out, - DO19=>DOA1_out, DO20=>DOA2_out, DO21=>DOA3_out, DO22=>DOA4_out, - DO23=>DOA5_out, DO24=>DOA6_out, DO25=>DOA7_out, DO26=>DOA8_out, - DO27=>DOA9_out, DO28=>DOA10_out, DO29=>DOA11_out, - DO30=>DOA12_out, DO31=>DOA13_out, DO32=>DOA14_out, - DO33=>DOA15_out, DO34=>DOA16_out, DO35=>DOA17_out); - DRIVEVCC: vcc - port map (PWR1=>VCCI); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(DIA17_ipd, DIA17, tipd_DIA17); - VitalWireDelay(DIA16_ipd, DIA16, tipd_DIA16); - VitalWireDelay(DIA15_ipd, DIA15, tipd_DIA15); - VitalWireDelay(DIA14_ipd, DIA14, tipd_DIA14); - VitalWireDelay(DIA13_ipd, DIA13, tipd_DIA13); - VitalWireDelay(DIA12_ipd, DIA12, tipd_DIA12); - VitalWireDelay(DIA11_ipd, DIA11, tipd_DIA11); - VitalWireDelay(DIA10_ipd, DIA10, tipd_DIA10); - VitalWireDelay(DIA9_ipd, DIA9, tipd_DIA9); - VitalWireDelay(DIA8_ipd, DIA8, tipd_DIA8); - VitalWireDelay(DIA7_ipd, DIA7, tipd_DIA7); - VitalWireDelay(DIA6_ipd, DIA6, tipd_DIA6); - VitalWireDelay(DIA5_ipd, DIA5, tipd_DIA5); - VitalWireDelay(DIA4_ipd, DIA4, tipd_DIA4); - VitalWireDelay(DIA3_ipd, DIA3, tipd_DIA3); - VitalWireDelay(DIA2_ipd, DIA2, tipd_DIA2); - VitalWireDelay(DIA1_ipd, DIA1, tipd_DIA1); - VitalWireDelay(DIA0_ipd, DIA0, tipd_DIA0); - VitalWireDelay(ADA13_ipd, ADA13, tipd_ADA13); - VitalWireDelay(ADA12_ipd, ADA12, tipd_ADA12); - VitalWireDelay(ADA11_ipd, ADA11, tipd_ADA11); - VitalWireDelay(ADA10_ipd, ADA10, tipd_ADA10); - VitalWireDelay(ADA9_ipd, ADA9, tipd_ADA9); - VitalWireDelay(ADA8_ipd, ADA8, tipd_ADA8); - VitalWireDelay(ADA7_ipd, ADA7, tipd_ADA7); - VitalWireDelay(ADA6_ipd, ADA6, tipd_ADA6); - VitalWireDelay(ADA5_ipd, ADA5, tipd_ADA5); - VitalWireDelay(CEA_ipd, CEA, tipd_CEA); - VitalWireDelay(CLKA_ipd, CLKA, tipd_CLKA); - VitalWireDelay(CLKB_ipd, CLKB, tipd_CLKB); - VitalWireDelay(OCEB_ipd, OCEB, tipd_OCEB); - VitalWireDelay(CEB_ipd, CEB, tipd_CEB); - VitalWireDelay(ADB5_ipd, ADB5, tipd_ADB5); - VitalWireDelay(ADB6_ipd, ADB6, tipd_ADB6); - VitalWireDelay(ADB7_ipd, ADB7, tipd_ADB7); - VitalWireDelay(ADB8_ipd, ADB8, tipd_ADB8); - VitalWireDelay(ADB9_ipd, ADB9, tipd_ADB9); - VitalWireDelay(ADB10_ipd, ADB10, tipd_ADB10); - VitalWireDelay(ADB11_ipd, ADB11, tipd_ADB11); - VitalWireDelay(ADB12_ipd, ADB12, tipd_ADB12); - VitalWireDelay(ADB13_ipd, ADB13, tipd_ADB13); - VitalWireDelay(DIB0_ipd, DIB0, tipd_DIB0); - VitalWireDelay(DIB1_ipd, DIB1, tipd_DIB1); - VitalWireDelay(DIB2_ipd, DIB2, tipd_DIB2); - VitalWireDelay(DIB3_ipd, DIB3, tipd_DIB3); - VitalWireDelay(DIB4_ipd, DIB4, tipd_DIB4); - VitalWireDelay(DIB5_ipd, DIB5, tipd_DIB5); - VitalWireDelay(DIB6_ipd, DIB6, tipd_DIB6); - VitalWireDelay(DIB7_ipd, DIB7, tipd_DIB7); - VitalWireDelay(DIB8_ipd, DIB8, tipd_DIB8); - VitalWireDelay(DIB9_ipd, DIB9, tipd_DIB9); - VitalWireDelay(DIB10_ipd, DIB10, tipd_DIB10); - VitalWireDelay(DIB11_ipd, DIB11, tipd_DIB11); - VitalWireDelay(DIB12_ipd, DIB12, tipd_DIB12); - VitalWireDelay(DIB13_ipd, DIB13, tipd_DIB13); - VitalWireDelay(DIB14_ipd, DIB14, tipd_DIB14); - VitalWireDelay(DIB15_ipd, DIB15, tipd_DIB15); - END BLOCK; - - -- Setup and Hold DELAYs - SignalDelay : BLOCK - BEGIN - VitalSignalDelay(DIA17_dly, DIA17_ipd, tisd_DIA17_CLKA); - VitalSignalDelay(DIA16_dly, DIA16_ipd, tisd_DIA16_CLKA); - VitalSignalDelay(DIA15_dly, DIA15_ipd, tisd_DIA15_CLKA); - VitalSignalDelay(DIA14_dly, DIA14_ipd, tisd_DIA14_CLKA); - VitalSignalDelay(DIA13_dly, DIA13_ipd, tisd_DIA13_CLKA); - VitalSignalDelay(DIA12_dly, DIA12_ipd, tisd_DIA12_CLKA); - VitalSignalDelay(DIA11_dly, DIA11_ipd, tisd_DIA11_CLKA); - VitalSignalDelay(DIA10_dly, DIA10_ipd, tisd_DIA10_CLKA); - VitalSignalDelay(DIA9_dly, DIA9_ipd, tisd_DIA9_CLKA); - VitalSignalDelay(DIA8_dly, DIA8_ipd, tisd_DIA8_CLKA); - VitalSignalDelay(DIA7_dly, DIA7_ipd, tisd_DIA7_CLKA); - VitalSignalDelay(DIA6_dly, DIA6_ipd, tisd_DIA6_CLKA); - VitalSignalDelay(DIA5_dly, DIA5_ipd, tisd_DIA5_CLKA); - VitalSignalDelay(DIA4_dly, DIA4_ipd, tisd_DIA4_CLKA); - VitalSignalDelay(DIA3_dly, DIA3_ipd, tisd_DIA3_CLKA); - VitalSignalDelay(DIA2_dly, DIA2_ipd, tisd_DIA2_CLKA); - VitalSignalDelay(DIA1_dly, DIA1_ipd, tisd_DIA1_CLKA); - VitalSignalDelay(DIA0_dly, DIA0_ipd, tisd_DIA0_CLKA); - VitalSignalDelay(ADA13_dly, ADA13_ipd, tisd_ADA13_CLKA); - VitalSignalDelay(ADA12_dly, ADA12_ipd, tisd_ADA12_CLKA); - VitalSignalDelay(ADA11_dly, ADA11_ipd, tisd_ADA11_CLKA); - VitalSignalDelay(ADA10_dly, ADA10_ipd, tisd_ADA10_CLKA); - VitalSignalDelay(ADA9_dly, ADA9_ipd, tisd_ADA9_CLKA); - VitalSignalDelay(ADA8_dly, ADA8_ipd, tisd_ADA8_CLKA); - VitalSignalDelay(ADA7_dly, ADA7_ipd, tisd_ADA7_CLKA); - VitalSignalDelay(ADA6_dly, ADA6_ipd, tisd_ADA6_CLKA); - VitalSignalDelay(ADA5_dly, ADA5_ipd, tisd_ADA5_CLKA); - VitalSignalDelay(CEA_dly, CEA_ipd, tisd_CEA_CLKA); - VitalSignalDelay(CLKA_dly, CLKA_ipd, ticd_CLKA); - VitalSignalDelay(CLKB_dly, CLKB_ipd, ticd_CLKB); - VitalSignalDelay(OCEB_dly, OCEB_ipd, tisd_OCEB_CLKB); - VitalSignalDelay(CEB_dly, CEB_ipd, tisd_CEB_CLKB); - VitalSignalDelay(ADB5_dly, ADB5_ipd, tisd_ADB5_CLKB); - VitalSignalDelay(ADB6_dly, ADB6_ipd, tisd_ADB6_CLKB); - VitalSignalDelay(ADB7_dly, ADB7_ipd, tisd_ADB7_CLKB); - VitalSignalDelay(ADB8_dly, ADB8_ipd, tisd_ADB8_CLKB); - VitalSignalDelay(ADB9_dly, ADB9_ipd, tisd_ADB9_CLKB); - VitalSignalDelay(ADB10_dly, ADB10_ipd, tisd_ADB10_CLKB); - VitalSignalDelay(ADB11_dly, ADB11_ipd, tisd_ADB11_CLKB); - VitalSignalDelay(ADB12_dly, ADB12_ipd, tisd_ADB12_CLKB); - VitalSignalDelay(ADB13_dly, ADB13_ipd, tisd_ADB13_CLKB); - VitalSignalDelay(DIB0_dly, DIB0_ipd, tisd_DIB0_CLKA); - VitalSignalDelay(DIB1_dly, DIB1_ipd, tisd_DIB1_CLKA); - VitalSignalDelay(DIB2_dly, DIB2_ipd, tisd_DIB2_CLKA); - VitalSignalDelay(DIB3_dly, DIB3_ipd, tisd_DIB3_CLKA); - VitalSignalDelay(DIB4_dly, DIB4_ipd, tisd_DIB4_CLKA); - VitalSignalDelay(DIB5_dly, DIB5_ipd, tisd_DIB5_CLKA); - VitalSignalDelay(DIB6_dly, DIB6_ipd, tisd_DIB6_CLKA); - VitalSignalDelay(DIB7_dly, DIB7_ipd, tisd_DIB7_CLKA); - VitalSignalDelay(DIB8_dly, DIB8_ipd, tisd_DIB8_CLKA); - VitalSignalDelay(DIB9_dly, DIB9_ipd, tisd_DIB9_CLKA); - VitalSignalDelay(DIB10_dly, DIB10_ipd, tisd_DIB10_CLKA); - VitalSignalDelay(DIB11_dly, DIB11_ipd, tisd_DIB11_CLKA); - VitalSignalDelay(DIB12_dly, DIB12_ipd, tisd_DIB12_CLKA); - VitalSignalDelay(DIB13_dly, DIB13_ipd, tisd_DIB13_CLKA); - VitalSignalDelay(DIB14_dly, DIB14_ipd, tisd_DIB14_CLKA); - VitalSignalDelay(DIB15_dly, DIB15_ipd, tisd_DIB15_CLKA); - END BLOCK; - - VitalBehavior : PROCESS (DIA17_dly, DIA16_dly, DIA15_dly, DIA14_dly, - DIA13_dly, DIA12_dly, DIA11_dly, DIA10_dly, DIA9_dly, DIA8_dly, DIA7_dly, - DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, - ADA13_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, - ADA6_dly, ADA5_dly, DOA17_out, DOA16_out, DOA15_out, DOA14_out, - DOA13_out, DOA12_out, DOA11_out, DOA10_out, DOA9_out, DOA8_out, DOA7_out, - DOA6_out, DOA5_out, DOA4_out, DOA3_out, DOA2_out, DOA1_out, DOA0_out, - CEA_dly, CLKA_dly, CLKB_dly, OCEB_dly, CEB_dly, DOB0_out, DOB1_out, - DOB2_out, DOB3_out, DOB4_out, DOB5_out, DOB6_out, DOB7_out, DOB8_out, - DOB9_out, DOB10_out, DOB11_out, DOB12_out, DOB13_out, ADB5_dly, ADB6_dly, - ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly, ADB13_dly, - DIB0_dly, DIB1_dly, DIB2_dly, DIB3_dly, DIB4_dly, DIB5_dly, DIB6_dly, - DIB7_dly, DIB8_dly, DIB9_dly, DIB10_dly, DIB11_dly, DIB12_dly, DIB13_dly, - DIB14_dly, DIB15_dly) - VARIABLE DOA17_zd : std_logic := 'X'; - VARIABLE DOA17_GlitchData : VitalGlitchDataType; - VARIABLE DOA16_zd : std_logic := 'X'; - VARIABLE DOA16_GlitchData : VitalGlitchDataType; - VARIABLE DOA15_zd : std_logic := 'X'; - VARIABLE DOA15_GlitchData : VitalGlitchDataType; - VARIABLE DOA14_zd : std_logic := 'X'; - VARIABLE DOA14_GlitchData : VitalGlitchDataType; - VARIABLE DOA13_zd : std_logic := 'X'; - VARIABLE DOA13_GlitchData : VitalGlitchDataType; - VARIABLE DOA12_zd : std_logic := 'X'; - VARIABLE DOA12_GlitchData : VitalGlitchDataType; - VARIABLE DOA11_zd : std_logic := 'X'; - VARIABLE DOA11_GlitchData : VitalGlitchDataType; - VARIABLE DOA10_zd : std_logic := 'X'; - VARIABLE DOA10_GlitchData : VitalGlitchDataType; - VARIABLE DOA9_zd : std_logic := 'X'; - VARIABLE DOA9_GlitchData : VitalGlitchDataType; - VARIABLE DOA8_zd : std_logic := 'X'; - VARIABLE DOA8_GlitchData : VitalGlitchDataType; - VARIABLE DOA7_zd : std_logic := 'X'; - VARIABLE DOA7_GlitchData : VitalGlitchDataType; - VARIABLE DOA6_zd : std_logic := 'X'; - VARIABLE DOA6_GlitchData : VitalGlitchDataType; - VARIABLE DOA5_zd : std_logic := 'X'; - VARIABLE DOA5_GlitchData : VitalGlitchDataType; - VARIABLE DOA4_zd : std_logic := 'X'; - VARIABLE DOA4_GlitchData : VitalGlitchDataType; - VARIABLE DOA3_zd : std_logic := 'X'; - VARIABLE DOA3_GlitchData : VitalGlitchDataType; - VARIABLE DOA2_zd : std_logic := 'X'; - VARIABLE DOA2_GlitchData : VitalGlitchDataType; - VARIABLE DOA1_zd : std_logic := 'X'; - VARIABLE DOA1_GlitchData : VitalGlitchDataType; - VARIABLE DOA0_zd : std_logic := 'X'; - VARIABLE DOA0_GlitchData : VitalGlitchDataType; - VARIABLE DOB0_zd : std_logic := 'X'; - VARIABLE DOB0_GlitchData : VitalGlitchDataType; - VARIABLE DOB1_zd : std_logic := 'X'; - VARIABLE DOB1_GlitchData : VitalGlitchDataType; - VARIABLE DOB2_zd : std_logic := 'X'; - VARIABLE DOB2_GlitchData : VitalGlitchDataType; - VARIABLE DOB3_zd : std_logic := 'X'; - VARIABLE DOB3_GlitchData : VitalGlitchDataType; - VARIABLE DOB4_zd : std_logic := 'X'; - VARIABLE DOB4_GlitchData : VitalGlitchDataType; - VARIABLE DOB5_zd : std_logic := 'X'; - VARIABLE DOB5_GlitchData : VitalGlitchDataType; - VARIABLE DOB6_zd : std_logic := 'X'; - VARIABLE DOB6_GlitchData : VitalGlitchDataType; - VARIABLE DOB7_zd : std_logic := 'X'; - VARIABLE DOB7_GlitchData : VitalGlitchDataType; - VARIABLE DOB8_zd : std_logic := 'X'; - VARIABLE DOB8_GlitchData : VitalGlitchDataType; - VARIABLE DOB9_zd : std_logic := 'X'; - VARIABLE DOB9_GlitchData : VitalGlitchDataType; - VARIABLE DOB10_zd : std_logic := 'X'; - VARIABLE DOB10_GlitchData : VitalGlitchDataType; - VARIABLE DOB11_zd : std_logic := 'X'; - VARIABLE DOB11_GlitchData : VitalGlitchDataType; - VARIABLE DOB12_zd : std_logic := 'X'; - VARIABLE DOB12_GlitchData : VitalGlitchDataType; - VARIABLE DOB13_zd : std_logic := 'X'; - VARIABLE DOB13_GlitchData : VitalGlitchDataType; - - VARIABLE tviol_DIA17_CLKA : x01 := '0'; - VARIABLE DIA17_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA16_CLKA : x01 := '0'; - VARIABLE DIA16_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA15_CLKA : x01 := '0'; - VARIABLE DIA15_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA14_CLKA : x01 := '0'; - VARIABLE DIA14_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA13_CLKA : x01 := '0'; - VARIABLE DIA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA12_CLKA : x01 := '0'; - VARIABLE DIA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA11_CLKA : x01 := '0'; - VARIABLE DIA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA10_CLKA : x01 := '0'; - VARIABLE DIA10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA9_CLKA : x01 := '0'; - VARIABLE DIA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA8_CLKA : x01 := '0'; - VARIABLE DIA8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA7_CLKA : x01 := '0'; - VARIABLE DIA7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA6_CLKA : x01 := '0'; - VARIABLE DIA6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA5_CLKA : x01 := '0'; - VARIABLE DIA5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA4_CLKA : x01 := '0'; - VARIABLE DIA4_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA3_CLKA : x01 := '0'; - VARIABLE DIA3_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA2_CLKA : x01 := '0'; - VARIABLE DIA2_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA1_CLKA : x01 := '0'; - VARIABLE DIA1_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIA0_CLKA : x01 := '0'; - VARIABLE DIA0_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA13_CLKA : x01 := '0'; - VARIABLE ADA13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA12_CLKA : x01 := '0'; - VARIABLE ADA12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA11_CLKA : x01 := '0'; - VARIABLE ADA11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA10_CLKA : x01 := '0'; - VARIABLE ADA10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA9_CLKA : x01 := '0'; - VARIABLE ADA9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA8_CLKA : x01 := '0'; - VARIABLE ADA8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA7_CLKA : x01 := '0'; - VARIABLE ADA7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA6_CLKA : x01 := '0'; - VARIABLE ADA6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADA5_CLKA : x01 := '0'; - VARIABLE ADA5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEA_CLKA : x01 := '0'; - VARIABLE CEA_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_OCEB_CLKB : x01 := '0'; - VARIABLE OCEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CEB_CLKB : x01 := '0'; - VARIABLE CEB_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB5_CLKB : x01 := '0'; - VARIABLE ADB5_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB6_CLKB : x01 := '0'; - VARIABLE ADB6_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB7_CLKB : x01 := '0'; - VARIABLE ADB7_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB8_CLKB : x01 := '0'; - VARIABLE ADB8_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB9_CLKB : x01 := '0'; - VARIABLE ADB9_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB10_CLKB : x01 := '0'; - VARIABLE ADB10_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB11_CLKB : x01 := '0'; - VARIABLE ADB11_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB12_CLKB : x01 := '0'; - VARIABLE ADB12_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_ADB13_CLKB : x01 := '0'; - VARIABLE ADB13_CLKB_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB0_CLKA : x01 := '0'; - VARIABLE DIB0_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB1_CLKA : x01 := '0'; - VARIABLE DIB1_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB2_CLKA : x01 := '0'; - VARIABLE DIB2_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB3_CLKA : x01 := '0'; - VARIABLE DIB3_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB4_CLKA : x01 := '0'; - VARIABLE DIB4_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB5_CLKA : x01 := '0'; - VARIABLE DIB5_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB6_CLKA : x01 := '0'; - VARIABLE DIB6_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB7_CLKA : x01 := '0'; - VARIABLE DIB7_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB8_CLKA : x01 := '0'; - VARIABLE DIB8_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB9_CLKA : x01 := '0'; - VARIABLE DIB9_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB10_CLKA : x01 := '0'; - VARIABLE DIB10_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB11_CLKA : x01 := '0'; - VARIABLE DIB11_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB12_CLKA : x01 := '0'; - VARIABLE DIB12_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB13_CLKA : x01 := '0'; - VARIABLE DIB13_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB14_CLKA : x01 := '0'; - VARIABLE DIB14_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_DIB15_CLKA : x01 := '0'; - VARIABLE DIB15_CLKA_TimingDatash : VitalTimingDataType; - VARIABLE tviol_CLKA_CLKA : x01 := '0'; - VARIABLE periodcheckinfo_CLKA : VitalPeriodDataType; - VARIABLE tviol_CLKB_CLKB : x01 := '0'; - VARIABLE periodcheckinfo_CLKB : VitalPeriodDataType; - - BEGIN - - IF (TimingChecksOn) THEN - VitalSetupHoldCheck ( - TestSignal => DIA17_dly, - TestSignalName => "DIA17", - TestDelay => tisd_DIA17_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA17_CLKA_noedge_posedge, - SetupLow => tsetup_DIA17_CLKA_noedge_posedge, - HoldHigh => thold_DIA17_CLKA_noedge_posedge, - HoldLow => thold_DIA17_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA17_CLKA_TimingDatash, - Violation => tviol_DIA17_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA16_dly, - TestSignalName => "DIA16", - TestDelay => tisd_DIA16_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA16_CLKA_noedge_posedge, - SetupLow => tsetup_DIA16_CLKA_noedge_posedge, - HoldHigh => thold_DIA16_CLKA_noedge_posedge, - HoldLow => thold_DIA16_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA16_CLKA_TimingDatash, - Violation => tviol_DIA16_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA15_dly, - TestSignalName => "DIA15", - TestDelay => tisd_DIA15_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA15_CLKA_noedge_posedge, - SetupLow => tsetup_DIA15_CLKA_noedge_posedge, - HoldHigh => thold_DIA15_CLKA_noedge_posedge, - HoldLow => thold_DIA15_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA15_CLKA_TimingDatash, - Violation => tviol_DIA15_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA14_dly, - TestSignalName => "DIA14", - TestDelay => tisd_DIA14_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA14_CLKA_noedge_posedge, - SetupLow => tsetup_DIA14_CLKA_noedge_posedge, - HoldHigh => thold_DIA14_CLKA_noedge_posedge, - HoldLow => thold_DIA14_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA14_CLKA_TimingDatash, - Violation => tviol_DIA14_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA13_dly, - TestSignalName => "DIA13", - TestDelay => tisd_DIA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA13_CLKA_noedge_posedge, - SetupLow => tsetup_DIA13_CLKA_noedge_posedge, - HoldHigh => thold_DIA13_CLKA_noedge_posedge, - HoldLow => thold_DIA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA13_CLKA_TimingDatash, - Violation => tviol_DIA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA12_dly, - TestSignalName => "DIA12", - TestDelay => tisd_DIA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA12_CLKA_noedge_posedge, - SetupLow => tsetup_DIA12_CLKA_noedge_posedge, - HoldHigh => thold_DIA12_CLKA_noedge_posedge, - HoldLow => thold_DIA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA12_CLKA_TimingDatash, - Violation => tviol_DIA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA11_dly, - TestSignalName => "DIA11", - TestDelay => tisd_DIA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA11_CLKA_noedge_posedge, - SetupLow => tsetup_DIA11_CLKA_noedge_posedge, - HoldHigh => thold_DIA11_CLKA_noedge_posedge, - HoldLow => thold_DIA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA11_CLKA_TimingDatash, - Violation => tviol_DIA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA10_dly, - TestSignalName => "DIA10", - TestDelay => tisd_DIA10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA10_CLKA_noedge_posedge, - SetupLow => tsetup_DIA10_CLKA_noedge_posedge, - HoldHigh => thold_DIA10_CLKA_noedge_posedge, - HoldLow => thold_DIA10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA10_CLKA_TimingDatash, - Violation => tviol_DIA10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA9_dly, - TestSignalName => "DIA9", - TestDelay => tisd_DIA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA9_CLKA_noedge_posedge, - SetupLow => tsetup_DIA9_CLKA_noedge_posedge, - HoldHigh => thold_DIA9_CLKA_noedge_posedge, - HoldLow => thold_DIA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA9_CLKA_TimingDatash, - Violation => tviol_DIA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA8_dly, - TestSignalName => "DIA8", - TestDelay => tisd_DIA8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA8_CLKA_noedge_posedge, - SetupLow => tsetup_DIA8_CLKA_noedge_posedge, - HoldHigh => thold_DIA8_CLKA_noedge_posedge, - HoldLow => thold_DIA8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA8_CLKA_TimingDatash, - Violation => tviol_DIA8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA7_dly, - TestSignalName => "DIA7", - TestDelay => tisd_DIA7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA7_CLKA_noedge_posedge, - SetupLow => tsetup_DIA7_CLKA_noedge_posedge, - HoldHigh => thold_DIA7_CLKA_noedge_posedge, - HoldLow => thold_DIA7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA7_CLKA_TimingDatash, - Violation => tviol_DIA7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA6_dly, - TestSignalName => "DIA6", - TestDelay => tisd_DIA6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA6_CLKA_noedge_posedge, - SetupLow => tsetup_DIA6_CLKA_noedge_posedge, - HoldHigh => thold_DIA6_CLKA_noedge_posedge, - HoldLow => thold_DIA6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA6_CLKA_TimingDatash, - Violation => tviol_DIA6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA5_dly, - TestSignalName => "DIA5", - TestDelay => tisd_DIA5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA5_CLKA_noedge_posedge, - SetupLow => tsetup_DIA5_CLKA_noedge_posedge, - HoldHigh => thold_DIA5_CLKA_noedge_posedge, - HoldLow => thold_DIA5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA5_CLKA_TimingDatash, - Violation => tviol_DIA5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA4_dly, - TestSignalName => "DIA4", - TestDelay => tisd_DIA4_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA4_CLKA_noedge_posedge, - SetupLow => tsetup_DIA4_CLKA_noedge_posedge, - HoldHigh => thold_DIA4_CLKA_noedge_posedge, - HoldLow => thold_DIA4_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA4_CLKA_TimingDatash, - Violation => tviol_DIA4_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA3_dly, - TestSignalName => "DIA3", - TestDelay => tisd_DIA3_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA3_CLKA_noedge_posedge, - SetupLow => tsetup_DIA3_CLKA_noedge_posedge, - HoldHigh => thold_DIA3_CLKA_noedge_posedge, - HoldLow => thold_DIA3_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA3_CLKA_TimingDatash, - Violation => tviol_DIA3_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA2_dly, - TestSignalName => "DIA2", - TestDelay => tisd_DIA2_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA2_CLKA_noedge_posedge, - SetupLow => tsetup_DIA2_CLKA_noedge_posedge, - HoldHigh => thold_DIA2_CLKA_noedge_posedge, - HoldLow => thold_DIA2_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA2_CLKA_TimingDatash, - Violation => tviol_DIA2_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA1_dly, - TestSignalName => "DIA1", - TestDelay => tisd_DIA1_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA1_CLKA_noedge_posedge, - SetupLow => tsetup_DIA1_CLKA_noedge_posedge, - HoldHigh => thold_DIA1_CLKA_noedge_posedge, - HoldLow => thold_DIA1_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA1_CLKA_TimingDatash, - Violation => tviol_DIA1_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIA0_dly, - TestSignalName => "DIA0", - TestDelay => tisd_DIA0_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIA0_CLKA_noedge_posedge, - SetupLow => tsetup_DIA0_CLKA_noedge_posedge, - HoldHigh => thold_DIA0_CLKA_noedge_posedge, - HoldLow => thold_DIA0_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIA0_CLKA_TimingDatash, - Violation => tviol_DIA0_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA13_dly, - TestSignalName => "ADA13", - TestDelay => tisd_ADA13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA13_CLKA_noedge_posedge, - SetupLow => tsetup_ADA13_CLKA_noedge_posedge, - HoldHigh => thold_ADA13_CLKA_noedge_posedge, - HoldLow => thold_ADA13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA13_CLKA_TimingDatash, - Violation => tviol_ADA13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA12_dly, - TestSignalName => "ADA12", - TestDelay => tisd_ADA12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA12_CLKA_noedge_posedge, - SetupLow => tsetup_ADA12_CLKA_noedge_posedge, - HoldHigh => thold_ADA12_CLKA_noedge_posedge, - HoldLow => thold_ADA12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA12_CLKA_TimingDatash, - Violation => tviol_ADA12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA11_dly, - TestSignalName => "ADA11", - TestDelay => tisd_ADA11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA11_CLKA_noedge_posedge, - SetupLow => tsetup_ADA11_CLKA_noedge_posedge, - HoldHigh => thold_ADA11_CLKA_noedge_posedge, - HoldLow => thold_ADA11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA11_CLKA_TimingDatash, - Violation => tviol_ADA11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA10_dly, - TestSignalName => "ADA10", - TestDelay => tisd_ADA10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA10_CLKA_noedge_posedge, - SetupLow => tsetup_ADA10_CLKA_noedge_posedge, - HoldHigh => thold_ADA10_CLKA_noedge_posedge, - HoldLow => thold_ADA10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA10_CLKA_TimingDatash, - Violation => tviol_ADA10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA9_dly, - TestSignalName => "ADA9", - TestDelay => tisd_ADA9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA9_CLKA_noedge_posedge, - SetupLow => tsetup_ADA9_CLKA_noedge_posedge, - HoldHigh => thold_ADA9_CLKA_noedge_posedge, - HoldLow => thold_ADA9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA9_CLKA_TimingDatash, - Violation => tviol_ADA9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA8_dly, - TestSignalName => "ADA8", - TestDelay => tisd_ADA8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA8_CLKA_noedge_posedge, - SetupLow => tsetup_ADA8_CLKA_noedge_posedge, - HoldHigh => thold_ADA8_CLKA_noedge_posedge, - HoldLow => thold_ADA8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA8_CLKA_TimingDatash, - Violation => tviol_ADA8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA7_dly, - TestSignalName => "ADA7", - TestDelay => tisd_ADA7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA7_CLKA_noedge_posedge, - SetupLow => tsetup_ADA7_CLKA_noedge_posedge, - HoldHigh => thold_ADA7_CLKA_noedge_posedge, - HoldLow => thold_ADA7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA7_CLKA_TimingDatash, - Violation => tviol_ADA7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA6_dly, - TestSignalName => "ADA6", - TestDelay => tisd_ADA6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA6_CLKA_noedge_posedge, - SetupLow => tsetup_ADA6_CLKA_noedge_posedge, - HoldHigh => thold_ADA6_CLKA_noedge_posedge, - HoldLow => thold_ADA6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA6_CLKA_TimingDatash, - Violation => tviol_ADA6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADA5_dly, - TestSignalName => "ADA5", - TestDelay => tisd_ADA5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_ADA5_CLKA_noedge_posedge, - SetupLow => tsetup_ADA5_CLKA_noedge_posedge, - HoldHigh => thold_ADA5_CLKA_noedge_posedge, - HoldLow => thold_ADA5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADA5_CLKA_TimingDatash, - Violation => tviol_ADA5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEA_dly, - TestSignalName => "CEA", - TestDelay => tisd_CEA_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_CEA_CLKA_noedge_posedge, - SetupLow => tsetup_CEA_CLKA_noedge_posedge, - HoldHigh => thold_CEA_CLKA_noedge_posedge, - HoldLow => thold_CEA_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEA_CLKA_TimingDatash, - Violation => tviol_CEA_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => OCEB_dly, - TestSignalName => "OCEB", - TestDelay => tisd_OCEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_OCEB_CLKB_noedge_posedge, - SetupLow => tsetup_OCEB_CLKB_noedge_posedge, - HoldHigh => thold_OCEB_CLKB_noedge_posedge, - HoldLow => thold_OCEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => OCEB_CLKB_TimingDatash, - Violation => tviol_OCEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => CEB_dly, - TestSignalName => "CEB", - TestDelay => tisd_CEB_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_CEB_CLKB_noedge_posedge, - SetupLow => tsetup_CEB_CLKB_noedge_posedge, - HoldHigh => thold_CEB_CLKB_noedge_posedge, - HoldLow => thold_CEB_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => CEB_CLKB_TimingDatash, - Violation => tviol_CEB_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB5_dly, - TestSignalName => "ADB5", - TestDelay => tisd_ADB5_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB5_CLKB_noedge_posedge, - SetupLow => tsetup_ADB5_CLKB_noedge_posedge, - HoldHigh => thold_ADB5_CLKB_noedge_posedge, - HoldLow => thold_ADB5_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB5_CLKB_TimingDatash, - Violation => tviol_ADB5_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB6_dly, - TestSignalName => "ADB6", - TestDelay => tisd_ADB6_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB6_CLKB_noedge_posedge, - SetupLow => tsetup_ADB6_CLKB_noedge_posedge, - HoldHigh => thold_ADB6_CLKB_noedge_posedge, - HoldLow => thold_ADB6_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB6_CLKB_TimingDatash, - Violation => tviol_ADB6_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB7_dly, - TestSignalName => "ADB7", - TestDelay => tisd_ADB7_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB7_CLKB_noedge_posedge, - SetupLow => tsetup_ADB7_CLKB_noedge_posedge, - HoldHigh => thold_ADB7_CLKB_noedge_posedge, - HoldLow => thold_ADB7_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB7_CLKB_TimingDatash, - Violation => tviol_ADB7_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB8_dly, - TestSignalName => "ADB8", - TestDelay => tisd_ADB8_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB8_CLKB_noedge_posedge, - SetupLow => tsetup_ADB8_CLKB_noedge_posedge, - HoldHigh => thold_ADB8_CLKB_noedge_posedge, - HoldLow => thold_ADB8_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB8_CLKB_TimingDatash, - Violation => tviol_ADB8_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB9_dly, - TestSignalName => "ADB9", - TestDelay => tisd_ADB9_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB9_CLKB_noedge_posedge, - SetupLow => tsetup_ADB9_CLKB_noedge_posedge, - HoldHigh => thold_ADB9_CLKB_noedge_posedge, - HoldLow => thold_ADB9_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB9_CLKB_TimingDatash, - Violation => tviol_ADB9_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB10_dly, - TestSignalName => "ADB10", - TestDelay => tisd_ADB10_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB10_CLKB_noedge_posedge, - SetupLow => tsetup_ADB10_CLKB_noedge_posedge, - HoldHigh => thold_ADB10_CLKB_noedge_posedge, - HoldLow => thold_ADB10_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB10_CLKB_TimingDatash, - Violation => tviol_ADB10_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB11_dly, - TestSignalName => "ADB11", - TestDelay => tisd_ADB11_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB11_CLKB_noedge_posedge, - SetupLow => tsetup_ADB11_CLKB_noedge_posedge, - HoldHigh => thold_ADB11_CLKB_noedge_posedge, - HoldLow => thold_ADB11_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB11_CLKB_TimingDatash, - Violation => tviol_ADB11_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB12_dly, - TestSignalName => "ADB12", - TestDelay => tisd_ADB12_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB12_CLKB_noedge_posedge, - SetupLow => tsetup_ADB12_CLKB_noedge_posedge, - HoldHigh => thold_ADB12_CLKB_noedge_posedge, - HoldLow => thold_ADB12_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB12_CLKB_TimingDatash, - Violation => tviol_ADB12_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => ADB13_dly, - TestSignalName => "ADB13", - TestDelay => tisd_ADB13_CLKB, - RefSignal => CLKB_dly, - RefSignalName => "CLKB", - RefDelay => ticd_CLKB, - SetupHigh => tsetup_ADB13_CLKB_noedge_posedge, - SetupLow => tsetup_ADB13_CLKB_noedge_posedge, - HoldHigh => thold_ADB13_CLKB_noedge_posedge, - HoldLow => thold_ADB13_CLKB_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => ADB13_CLKB_TimingDatash, - Violation => tviol_ADB13_CLKB, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB0_dly, - TestSignalName => "DIB0", - TestDelay => tisd_DIB0_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB0_CLKA_noedge_posedge, - SetupLow => tsetup_DIB0_CLKA_noedge_posedge, - HoldHigh => thold_DIB0_CLKA_noedge_posedge, - HoldLow => thold_DIB0_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB0_CLKA_TimingDatash, - Violation => tviol_DIB0_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB1_dly, - TestSignalName => "DIB1", - TestDelay => tisd_DIB1_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB1_CLKA_noedge_posedge, - SetupLow => tsetup_DIB1_CLKA_noedge_posedge, - HoldHigh => thold_DIB1_CLKA_noedge_posedge, - HoldLow => thold_DIB1_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB1_CLKA_TimingDatash, - Violation => tviol_DIB1_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB2_dly, - TestSignalName => "DIB2", - TestDelay => tisd_DIB2_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB2_CLKA_noedge_posedge, - SetupLow => tsetup_DIB2_CLKA_noedge_posedge, - HoldHigh => thold_DIB2_CLKA_noedge_posedge, - HoldLow => thold_DIB2_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB2_CLKA_TimingDatash, - Violation => tviol_DIB2_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB3_dly, - TestSignalName => "DIB3", - TestDelay => tisd_DIB3_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB3_CLKA_noedge_posedge, - SetupLow => tsetup_DIB3_CLKA_noedge_posedge, - HoldHigh => thold_DIB3_CLKA_noedge_posedge, - HoldLow => thold_DIB3_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB3_CLKA_TimingDatash, - Violation => tviol_DIB3_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB4_dly, - TestSignalName => "DIB4", - TestDelay => tisd_DIB4_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB4_CLKA_noedge_posedge, - SetupLow => tsetup_DIB4_CLKA_noedge_posedge, - HoldHigh => thold_DIB4_CLKA_noedge_posedge, - HoldLow => thold_DIB4_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB4_CLKA_TimingDatash, - Violation => tviol_DIB4_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB5_dly, - TestSignalName => "DIB5", - TestDelay => tisd_DIB5_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB5_CLKA_noedge_posedge, - SetupLow => tsetup_DIB5_CLKA_noedge_posedge, - HoldHigh => thold_DIB5_CLKA_noedge_posedge, - HoldLow => thold_DIB5_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB5_CLKA_TimingDatash, - Violation => tviol_DIB5_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB6_dly, - TestSignalName => "DIB6", - TestDelay => tisd_DIB6_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB6_CLKA_noedge_posedge, - SetupLow => tsetup_DIB6_CLKA_noedge_posedge, - HoldHigh => thold_DIB6_CLKA_noedge_posedge, - HoldLow => thold_DIB6_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB6_CLKA_TimingDatash, - Violation => tviol_DIB6_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB7_dly, - TestSignalName => "DIB7", - TestDelay => tisd_DIB7_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB7_CLKA_noedge_posedge, - SetupLow => tsetup_DIB7_CLKA_noedge_posedge, - HoldHigh => thold_DIB7_CLKA_noedge_posedge, - HoldLow => thold_DIB7_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB7_CLKA_TimingDatash, - Violation => tviol_DIB7_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB8_dly, - TestSignalName => "DIB8", - TestDelay => tisd_DIB8_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB8_CLKA_noedge_posedge, - SetupLow => tsetup_DIB8_CLKA_noedge_posedge, - HoldHigh => thold_DIB8_CLKA_noedge_posedge, - HoldLow => thold_DIB8_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB8_CLKA_TimingDatash, - Violation => tviol_DIB8_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB9_dly, - TestSignalName => "DIB9", - TestDelay => tisd_DIB9_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB9_CLKA_noedge_posedge, - SetupLow => tsetup_DIB9_CLKA_noedge_posedge, - HoldHigh => thold_DIB9_CLKA_noedge_posedge, - HoldLow => thold_DIB9_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB9_CLKA_TimingDatash, - Violation => tviol_DIB9_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB10_dly, - TestSignalName => "DIB10", - TestDelay => tisd_DIB10_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB10_CLKA_noedge_posedge, - SetupLow => tsetup_DIB10_CLKA_noedge_posedge, - HoldHigh => thold_DIB10_CLKA_noedge_posedge, - HoldLow => thold_DIB10_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB10_CLKA_TimingDatash, - Violation => tviol_DIB10_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB11_dly, - TestSignalName => "DIB11", - TestDelay => tisd_DIB11_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB11_CLKA_noedge_posedge, - SetupLow => tsetup_DIB11_CLKA_noedge_posedge, - HoldHigh => thold_DIB11_CLKA_noedge_posedge, - HoldLow => thold_DIB11_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB11_CLKA_TimingDatash, - Violation => tviol_DIB11_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB12_dly, - TestSignalName => "DIB12", - TestDelay => tisd_DIB12_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB12_CLKA_noedge_posedge, - SetupLow => tsetup_DIB12_CLKA_noedge_posedge, - HoldHigh => thold_DIB12_CLKA_noedge_posedge, - HoldLow => thold_DIB12_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB12_CLKA_TimingDatash, - Violation => tviol_DIB12_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB13_dly, - TestSignalName => "DIB13", - TestDelay => tisd_DIB13_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB13_CLKA_noedge_posedge, - SetupLow => tsetup_DIB13_CLKA_noedge_posedge, - HoldHigh => thold_DIB13_CLKA_noedge_posedge, - HoldLow => thold_DIB13_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB13_CLKA_TimingDatash, - Violation => tviol_DIB13_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB14_dly, - TestSignalName => "DIB14", - TestDelay => tisd_DIB14_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB14_CLKA_noedge_posedge, - SetupLow => tsetup_DIB14_CLKA_noedge_posedge, - HoldHigh => thold_DIB14_CLKA_noedge_posedge, - HoldLow => thold_DIB14_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB14_CLKA_TimingDatash, - Violation => tviol_DIB14_CLKA, - MsgSeverity => warning); - VitalSetupHoldCheck ( - TestSignal => DIB15_dly, - TestSignalName => "DIB15", - TestDelay => tisd_DIB15_CLKA, - RefSignal => CLKA_dly, - RefSignalName => "CLKA", - RefDelay => ticd_CLKA, - SetupHigh => tsetup_DIB15_CLKA_noedge_posedge, - SetupLow => tsetup_DIB15_CLKA_noedge_posedge, - HoldHigh => thold_DIB15_CLKA_noedge_posedge, - HoldLow => thold_DIB15_CLKA_noedge_posedge, - CheckEnabled => TRUE, - RefTransition => '/', - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - TimingData => DIB15_CLKA_TimingDatash, - Violation => tviol_DIB15_CLKA, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKA_ipd, - TestSignalName => "CLKA", - Period => tperiod_CLKA, - PulseWidthHigh => tpw_CLKA_posedge, - PulseWidthLow => tpw_CLKA_negedge, - PeriodData => periodcheckinfo_CLKA, - Violation => tviol_CLKA_CLKA, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - VitalPeriodPulseCheck ( - TestSignal => CLKB_ipd, - TestSignalName => "CLKB", - Period => tperiod_CLKB, - PulseWidthHigh => tpw_CLKB_posedge, - PulseWidthLow => tpw_CLKB_negedge, - PeriodData => periodcheckinfo_CLKB, - Violation => tviol_CLKB_CLKB, - MsgOn => MsgOn, XOn => XOn, - HeaderMsg => InstancePath, - CheckEnabled => TRUE, - MsgSeverity => warning); - - END IF; - - DOA17_zd := DOA17_out; - DOA16_zd := DOA16_out; - DOA15_zd := DOA15_out; - DOA14_zd := DOA14_out; - DOA13_zd := DOA13_out; - DOA12_zd := DOA12_out; - DOA11_zd := DOA11_out; - DOA10_zd := DOA10_out; - DOA9_zd := DOA9_out; - DOA8_zd := DOA8_out; - DOA7_zd := DOA7_out; - DOA6_zd := DOA6_out; - DOA5_zd := DOA5_out; - DOA4_zd := DOA4_out; - DOA3_zd := DOA3_out; - DOA2_zd := DOA2_out; - DOA1_zd := DOA1_out; - DOA0_zd := DOA0_out; - DOB0_zd := DOB0_out; - DOB1_zd := DOB1_out; - DOB2_zd := DOB2_out; - DOB3_zd := DOB3_out; - DOB4_zd := DOB4_out; - DOB5_zd := DOB5_out; - DOB6_zd := DOB6_out; - DOB7_zd := DOB7_out; - DOB8_zd := DOB8_out; - DOB9_zd := DOB9_out; - DOB10_zd := DOB10_out; - DOB11_zd := DOB11_out; - DOB12_zd := DOB12_out; - DOB13_zd := DOB13_out; - - VitalPathDelay01 ( - OutSignal => DOA17, OutSignalName => "DOA17", OutTemp => DOA17_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA17, - PathCondition => TRUE)), - GlitchData => DOA17_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA16, OutSignalName => "DOA16", OutTemp => DOA16_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA16, - PathCondition => TRUE)), - GlitchData => DOA16_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA15, OutSignalName => "DOA15", OutTemp => DOA15_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA15, - PathCondition => TRUE)), - GlitchData => DOA15_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA14, OutSignalName => "DOA14", OutTemp => DOA14_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA14, - PathCondition => TRUE)), - GlitchData => DOA14_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA13, OutSignalName => "DOA13", OutTemp => DOA13_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA13, - PathCondition => TRUE)), - GlitchData => DOA13_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA12, OutSignalName => "DOA12", OutTemp => DOA12_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA12, - PathCondition => TRUE)), - GlitchData => DOA12_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA11, OutSignalName => "DOA11", OutTemp => DOA11_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA11, - PathCondition => TRUE)), - GlitchData => DOA11_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA10, OutSignalName => "DOA10", OutTemp => DOA10_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA10, - PathCondition => TRUE)), - GlitchData => DOA10_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA9, OutSignalName => "DOA9", OutTemp => DOA9_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA9, - PathCondition => TRUE)), - GlitchData => DOA9_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA8, OutSignalName => "DOA8", OutTemp => DOA8_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA8, - PathCondition => TRUE)), - GlitchData => DOA8_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA7, OutSignalName => "DOA7", OutTemp => DOA7_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA7, - PathCondition => TRUE)), - GlitchData => DOA7_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA6, OutSignalName => "DOA6", OutTemp => DOA6_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA6, - PathCondition => TRUE)), - GlitchData => DOA6_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA5, OutSignalName => "DOA5", OutTemp => DOA5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA5, - PathCondition => TRUE)), - GlitchData => DOA5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA4, OutSignalName => "DOA4", OutTemp => DOA4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA4, - PathCondition => TRUE)), - GlitchData => DOA4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA3, OutSignalName => "DOA3", OutTemp => DOA3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA3, - PathCondition => TRUE)), - GlitchData => DOA3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA2, OutSignalName => "DOA2", OutTemp => DOA2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA2, - PathCondition => TRUE)), - GlitchData => DOA2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA1, OutSignalName => "DOA1", OutTemp => DOA1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA1, - PathCondition => TRUE)), - GlitchData => DOA1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOA0, OutSignalName => "DOA0", OutTemp => DOA0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOA0, - PathCondition => TRUE)), - GlitchData => DOA0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB0, OutSignalName => "DOB0", OutTemp => DOB0_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB0, - PathCondition => TRUE)), - GlitchData => DOB0_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB1, OutSignalName => "DOB1", OutTemp => DOB1_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB1, - PathCondition => TRUE)), - GlitchData => DOB1_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB2, OutSignalName => "DOB2", OutTemp => DOB2_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB2, - PathCondition => TRUE)), - GlitchData => DOB2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB3, OutSignalName => "DOB3", OutTemp => DOB3_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB3, - PathCondition => TRUE)), - GlitchData => DOB3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB4, OutSignalName => "DOB4", OutTemp => DOB4_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB4, - PathCondition => TRUE)), - GlitchData => DOB4_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB5, OutSignalName => "DOB5", OutTemp => DOB5_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB5, - PathCondition => TRUE)), - GlitchData => DOB5_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB6, OutSignalName => "DOB6", OutTemp => DOB6_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB6, - PathCondition => TRUE)), - GlitchData => DOB6_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB7, OutSignalName => "DOB7", OutTemp => DOB7_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB7, - PathCondition => TRUE)), - GlitchData => DOB7_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB8, OutSignalName => "DOB8", OutTemp => DOB8_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB8, - PathCondition => TRUE)), - GlitchData => DOB8_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB9, OutSignalName => "DOB9", OutTemp => DOB9_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB9, - PathCondition => TRUE)), - GlitchData => DOB9_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB10, OutSignalName => "DOB10", OutTemp => DOB10_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB10, - PathCondition => TRUE)), - GlitchData => DOB10_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB11, OutSignalName => "DOB11", OutTemp => DOB11_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB11, - PathCondition => TRUE)), - GlitchData => DOB11_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB12, OutSignalName => "DOB12", OutTemp => DOB12_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB12, - PathCondition => TRUE)), - GlitchData => DOB12_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => DOB13, OutSignalName => "DOB13", OutTemp => DOB13_zd, - Paths => (0 => (InputChangeTime => CLKB_dly'last_event, - PathDelay => tpd_CLKB_DOB13, - PathCondition => TRUE)), - GlitchData => DOB13_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity EHXPLLLB - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity EHXPLLLB is - port (CLKI: in Std_logic; CLKFB: in Std_logic; PHASESEL1: in Std_logic; - PHASESEL0: in Std_logic; PHASEDIR: in Std_logic; - PHASESTEP: in Std_logic; PHASELOADREG: in Std_logic; - STDBY: in Std_logic; PLLWAKESYNC: in Std_logic; RST: in Std_logic; - ENCLKOP: in Std_logic; ENCLKOS: in Std_logic; ENCLKOS2: in Std_logic; - ENCLKOS3: in Std_logic; CLKOP: out Std_logic; CLKOS: out Std_logic; - CLKOS2: out Std_logic; CLKOS3: out Std_logic; LOCK: out Std_logic; - INTLOCK: out Std_logic; REFCLK: out Std_logic; - CLKINTFB: out Std_logic); - - - - end EHXPLLLB; - - architecture Structure of EHXPLLLB is - begin - INST10: EHXPLLL - generic map (CLKFB_DIV => 3, CLKI_DIV => 1, CLKOP_CPHASE => 1, - CLKOP_DIV => 2, CLKOP_ENABLE => "ENABLED", - CLKOP_FPHASE => 0, CLKOP_TRIM_DELAY => 0, - CLKOP_TRIM_POL => "FALLING", CLKOS2_CPHASE => 1, - CLKOS2_DIV => 2, CLKOS2_ENABLE => "ENABLED", - CLKOS2_FPHASE => 4, CLKOS3_CPHASE => 1, CLKOS3_DIV => 2, - CLKOS3_ENABLE => "ENABLED", CLKOS3_FPHASE => 6, - CLKOS_CPHASE => 1, CLKOS_DIV => 2, - CLKOS_ENABLE => "ENABLED", CLKOS_FPHASE => 2, - CLKOS_TRIM_DELAY => 0, CLKOS_TRIM_POL => "FALLING", - DPHASE_SOURCE => "DISABLED", FEEDBK_PATH => "CLKOP", - INTFB_WAKE => "DISABLED", INT_LOCK_STICKY => "ENABLED", - OUTDIVIDER_MUXA => "DIVA", OUTDIVIDER_MUXB => "DIVB", - OUTDIVIDER_MUXC => "DIVC", OUTDIVIDER_MUXD => "DIVD", - PLLRST_ENA => "DISABLED", PLL_LOCK_DELAY => 200, - PLL_LOCK_MODE => 0, REFIN_RESET => "DISABLED", - STDBY_ENABLE => "DISABLED", SYNC_ENABLE => "DISABLED") - port map (CLKI=>CLKI, CLKFB=>CLKFB, PHASESEL1=>PHASESEL1, - PHASESEL0=>PHASESEL0, PHASEDIR=>PHASEDIR, PHASESTEP=>PHASESTEP, - PHASELOADREG=>PHASELOADREG, STDBY=>STDBY, - PLLWAKESYNC=>PLLWAKESYNC, RST=>RST, ENCLKOP=>ENCLKOP, - ENCLKOS=>ENCLKOS, ENCLKOS2=>ENCLKOS2, ENCLKOS3=>ENCLKOS3, - CLKOP=>CLKOP, CLKOS=>CLKOS, CLKOS2=>CLKOS2, CLKOS3=>CLKOS3, - LOCK=>LOCK, INTLOCK=>INTLOCK, REFCLK=>REFCLK, - CLKINTFB=>CLKINTFB); - end Structure; - --- entity pll0inst_PLLInst_0 - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity pll0inst_PLLInst_0 is - -- miscellaneous vital GENERICs - GENERIC ( - TimingChecksOn : boolean := TRUE; - XOn : boolean := FALSE; - MsgOn : boolean := TRUE; - InstancePath : string := "pll0inst_PLLInst_0"; - - tipd_CLKI : VitalDelayType01 := (0 ns, 0 ns); - tipd_CLKFB : VitalDelayType01 := (0 ns, 0 ns); - tipd_STDBY : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKI_CLKOS3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKI_CLKOS2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKI_CLKOS : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKI_CLKOP : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKFB_CLKOS3 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKFB_CLKOS2 : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKFB_CLKOS : VitalDelayType01 := (0 ns, 0 ns); - tpd_CLKFB_CLKOP : VitalDelayType01 := (0 ns, 0 ns)); - - port (CLKI: in Std_logic; CLKFB: in Std_logic; STDBY: in Std_logic; - CLKOS3: out Std_logic; CLKOS2: out Std_logic; CLKOS: out Std_logic; - CLKOP: out Std_logic); - - - - end pll0inst_PLLInst_0; - - architecture Structure of pll0inst_PLLInst_0 is - signal CLKI_ipd : std_logic := 'X'; - signal CLKFB_ipd : std_logic := 'X'; - signal STDBY_ipd : std_logic := 'X'; - signal CLKOS3_out : std_logic := 'X'; - signal CLKOS2_out : std_logic := 'X'; - signal CLKOS_out : std_logic := 'X'; - signal CLKOP_out : std_logic := 'X'; - - signal GNDI: Std_logic; - component gnd - port (PWR0: out Std_logic); - end component; - component EHXPLLLB - port (CLKI: in Std_logic; CLKFB: in Std_logic; PHASESEL1: in Std_logic; - PHASESEL0: in Std_logic; PHASEDIR: in Std_logic; - PHASESTEP: in Std_logic; PHASELOADREG: in Std_logic; - STDBY: in Std_logic; PLLWAKESYNC: in Std_logic; RST: in Std_logic; - ENCLKOP: in Std_logic; ENCLKOS: in Std_logic; - ENCLKOS2: in Std_logic; ENCLKOS3: in Std_logic; - CLKOP: out Std_logic; CLKOS: out Std_logic; CLKOS2: out Std_logic; - CLKOS3: out Std_logic; LOCK: out Std_logic; INTLOCK: out Std_logic; - REFCLK: out Std_logic; CLKINTFB: out Std_logic); - end component; - begin - pll0inst_PLLInst_0_EHXPLLL: EHXPLLLB - port map (CLKI=>CLKI_ipd, CLKFB=>CLKFB_ipd, PHASESEL1=>GNDI, - PHASESEL0=>GNDI, PHASEDIR=>GNDI, PHASESTEP=>GNDI, - PHASELOADREG=>GNDI, STDBY=>STDBY_ipd, PLLWAKESYNC=>GNDI, - RST=>GNDI, ENCLKOP=>GNDI, ENCLKOS=>GNDI, ENCLKOS2=>GNDI, - ENCLKOS3=>GNDI, CLKOP=>CLKOP_out, CLKOS=>CLKOS_out, - CLKOS2=>CLKOS2_out, CLKOS3=>CLKOS3_out, LOCK=>open, - INTLOCK=>open, REFCLK=>open, CLKINTFB=>open); - DRIVEGND: gnd - port map (PWR0=>GNDI); - - -- INPUT PATH DELAYs - WireDelay : BLOCK - BEGIN - VitalWireDelay(CLKI_ipd, CLKI, tipd_CLKI); - VitalWireDelay(CLKFB_ipd, CLKFB, tipd_CLKFB); - VitalWireDelay(STDBY_ipd, STDBY, tipd_STDBY); - END BLOCK; - - VitalBehavior : PROCESS (CLKI_ipd, CLKFB_ipd, STDBY_ipd, CLKOS3_out, - CLKOS2_out, CLKOS_out, CLKOP_out) - VARIABLE CLKOS3_zd : std_logic := 'X'; - VARIABLE CLKOS3_GlitchData : VitalGlitchDataType; - VARIABLE CLKOS2_zd : std_logic := 'X'; - VARIABLE CLKOS2_GlitchData : VitalGlitchDataType; - VARIABLE CLKOS_zd : std_logic := 'X'; - VARIABLE CLKOS_GlitchData : VitalGlitchDataType; - VARIABLE CLKOP_zd : std_logic := 'X'; - VARIABLE CLKOP_GlitchData : VitalGlitchDataType; - - - BEGIN - - IF (TimingChecksOn) THEN - - END IF; - - CLKOS3_zd := CLKOS3_out; - CLKOS2_zd := CLKOS2_out; - CLKOS_zd := CLKOS_out; - CLKOP_zd := CLKOP_out; - - VitalPathDelay01 ( - OutSignal => CLKOS3, OutSignalName => "CLKOS3", OutTemp => CLKOS3_zd, - Paths => (0 => (InputChangeTime => CLKI_ipd'last_event, - PathDelay => tpd_CLKI_CLKOS3, - PathCondition => TRUE), - 1 => (InputChangeTime => CLKFB_ipd'last_event, - PathDelay => tpd_CLKFB_CLKOS3, - PathCondition => TRUE)), - GlitchData => CLKOS3_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => CLKOS2, OutSignalName => "CLKOS2", OutTemp => CLKOS2_zd, - Paths => (0 => (InputChangeTime => CLKI_ipd'last_event, - PathDelay => tpd_CLKI_CLKOS2, - PathCondition => TRUE), - 1 => (InputChangeTime => CLKFB_ipd'last_event, - PathDelay => tpd_CLKFB_CLKOS2, - PathCondition => TRUE)), - GlitchData => CLKOS2_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => CLKOS, OutSignalName => "CLKOS", OutTemp => CLKOS_zd, - Paths => (0 => (InputChangeTime => CLKI_ipd'last_event, - PathDelay => tpd_CLKI_CLKOS, - PathCondition => TRUE), - 1 => (InputChangeTime => CLKFB_ipd'last_event, - PathDelay => tpd_CLKFB_CLKOS, - PathCondition => TRUE)), - GlitchData => CLKOS_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - VitalPathDelay01 ( - OutSignal => CLKOP, OutSignalName => "CLKOP", OutTemp => CLKOP_zd, - Paths => (0 => (InputChangeTime => CLKI_ipd'last_event, - PathDelay => tpd_CLKI_CLKOP, - PathCondition => TRUE), - 1 => (InputChangeTime => CLKFB_ipd'last_event, - PathDelay => tpd_CLKFB_CLKOP, - PathCondition => TRUE)), - GlitchData => CLKOP_GlitchData, - Mode => ondetect, XOn => XOn, MsgOn => MsgOn); - - END PROCESS; - - end Structure; - --- entity top_tf - library IEEE, vital2000, ECP5UM; - use IEEE.STD_LOGIC_1164.all; - use vital2000.vital_timing.all; - use ECP5UM.COMPONENTS.ALL; - - entity top_tf is - port (clk: in Std_logic; rd_clk: in Std_logic; reset_dc: in Std_logic; - trig: in Std_logic_vector (2 downto 0); - fifo_data_out: out Std_logic_vector (31 downto 0); - fifo_rden: out Std_logic; fifo_empty1: out Std_logic; - LVL1_TRG_DATA_VALID_IN: in Std_logic; - LVL1_INVALID_TRG_IN: in Std_logic; - FEE_DATA_OUT: out Std_logic_vector (31 downto 0); - FEE_DATA_WRITE_OUT: out Std_logic; - FEE_DATAFINISHED_OUT: out Std_logic; - FEE_TRG_RELEASE_OUT: out Std_logic; - LVL1_TRG_DATA_VALI_IN_rising: out Std_logic; burst: out Std_logic; - discard: out Std_logic; last_buf_empty: out Std_logic; - finished: out Std_logic; release_out: out Std_logic; - hades_trig: in Std_logic; hades_raw_out_valid: out Std_logic; - hades_raw_valid_vect: out Std_logic_vector (1 downto 0); - hades_lvl1: in Std_logic; hades_lvl1_invalid: in Std_logic; - hades_offset: out Std_logic_vector (8 downto 0); - hades_offset_valid: out Std_logic; hades_window_end: out Std_logic; - hades_buf_out_valid: out Std_logic; hades_buf_release: out Std_logic; - hades_buf_finished: out Std_logic; - hades_hit_out_i: out Std_logic_vector (3 downto 0); - hades_hit_valid: out Std_logic_vector (3 downto 0); - hades_discard: out Std_logic; - hades_invalid_dl: out Std_logic_vector (3 downto 0); - hades_buf_drop: out Std_logic_vector (3 downto 0); - hades_dbg2_out: out Std_logic_vector (31 downto 0); - hades_dbg2_coarse: out Std_logic_vector (8 downto 0); - hades_drop_cmp_buf: out Std_logic_vector (11 downto 0); - hades_drop_cmp_buf_coarse: out Std_logic_vector (11 downto 0); - hades_drop_cmp_buf_valid: out Std_logic); - - - - end top_tf; - - architecture Structure of top_tf is - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic; - signal pll_clks_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic; - signal fifo_empty_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic; - signal fifo_empty_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d: Std_logic; - signal fifo_empty1_c: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gctr_ci: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_wren_i: Std_logic; - signal fifo_colector_inst_fifo40_inst_co0: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_co1: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_co2: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_co3: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_iwcount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gctr_ci: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_rden_i: Std_logic; - signal rd_clk_c: Std_logic; - signal fifo_colector_inst_fifo40_inst_co0_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_co1_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_co2_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_co3_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_ircount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_cmp_ci: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r1: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r0: Std_logic; - signal fifo_colector_inst_fifo40_inst_co0_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r3: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r2: Std_logic; - signal fifo_colector_inst_fifo40_inst_co1_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r5: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r4: Std_logic; - signal fifo_colector_inst_fifo40_inst_co2_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r7: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_co3_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_empty_cmp_set: Std_logic; - signal fifo_colector_inst_fifo40_inst_empty_cmp_clr: Std_logic; - signal fifo_colector_inst_fifo40_inst_wcount_r8: Std_logic; - signal fifo_colector_inst_fifo40_inst_empty_d_c: Std_logic; - signal fifo_colector_inst_fifo40_inst_empty_d: Std_logic; - signal last_buf_empty_c: Std_logic; - signal fifo_colector_inst_fifo40_inst_cmp_ci_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w0: Std_logic; - signal fifo_colector_inst_fifo40_inst_co0_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w2: Std_logic; - signal fifo_colector_inst_fifo40_inst_co1_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w5: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w4: Std_logic; - signal fifo_colector_inst_fifo40_inst_co2_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w7: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_co3_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_full_cmp_clr: Std_logic; - signal fifo_colector_inst_fifo40_inst_full_cmp_set: Std_logic; - signal fifo_colector_inst_fifo40_inst_rcount_w8: Std_logic; - signal fifo_colector_inst_fifo40_inst_full_d_c: Std_logic; - signal fifo_colector_inst_fifo40_inst_full_d: Std_logic; - signal fifo_colector_inst_fifo40_inst_Full: Std_logic; - signal hades_tdc_bundle_inst_hit_valid25_0_I_27_cry: Std_logic; - signal hades_tdc_bundle_inst_hit_valid25: Std_logic; - signal hades_dbg2_coarse_c_1: Std_logic; - signal hades_dbg2_coarse_c_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14: Std_logic; - signal hades_dbg2_coarse_c_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3: Std_logic; - signal hades_dbg2_coarse_c_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0: Std_logic; - signal hades_dbg2_coarse_c_8: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4: Std_logic; - signal hades_dbg2_coarse_c_7: Std_logic; - signal hades_dbg2_coarse_c_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0: Std_logic; - signal hades_drop_cmp_buf_c_0: Std_logic; - signal hades_drop_cmp_buf_coarse_c_0: Std_logic; - signal hades_drop_cmp_buf_coarse_c_1: Std_logic; - signal hades_drop_cmp_buf_c_1: Std_logic; - signal hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0: Std_logic; - signal hades_drop_cmp_buf_coarse_c_5: Std_logic; - signal hades_drop_cmp_buf_c_5: Std_logic; - signal hades_drop_cmp_buf_coarse_c_4: Std_logic; - signal hades_drop_cmp_buf_c_4: Std_logic; - signal hades_drop_cmp_buf_coarse_c_3: Std_logic; - signal hades_drop_cmp_buf_c_2: Std_logic; - signal hades_drop_cmp_buf_coarse_c_2: Std_logic; - signal hades_drop_cmp_buf_c_3: Std_logic; - signal hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2: Std_logic; - signal hades_drop_cmp_buf_c_8: Std_logic; - signal hades_drop_cmp_buf_coarse_c_9: Std_logic; - signal hades_drop_cmp_buf_coarse_c_8: Std_logic; - signal hades_drop_cmp_buf_coarse_c_7: Std_logic; - signal hades_drop_cmp_buf_coarse_c_6: Std_logic; - signal hades_drop_cmp_buf_c_6: Std_logic; - signal hades_drop_cmp_buf_c_7: Std_logic; - signal ANB1: Std_logic; - signal ANB2: Std_logic; - signal ANB0: Std_logic; - signal ANB3: Std_logic; - signal hades_tdc_bundle_inst_N_247_i: Std_logic; - signal hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0: Std_logic; - signal reset_dl_2: Std_logic; - signal hades_tdc_bundle_inst_N_50_i_i: Std_logic; - signal hades_tdc_bundle_inst_N_46_i: Std_logic; - signal hades_discard_c: Std_logic; - signal hades_tdc_bundle_inst_hit_out_i_6_2: Std_logic; - signal trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0: Std_logic; - signal discard_c: Std_logic; - signal fifo_colector_inst_iterator_0: Std_logic; - signal fifo_colector_inst_in_empty_pmux_i: Std_logic; - signal fifo_colector_inst_iterator_1: Std_logic; - signal fifo_colector_inst_buffer_wr_enable: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_8: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_0: Std_logic; - signal fifo_colector_inst_data_buffer_3_0: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_16: Std_logic; - signal fifo_colector_inst_data_buffer_0: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_9: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_1: Std_logic; - signal fifo_colector_inst_data_buffer_3_1: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_17: Std_logic; - signal fifo_colector_inst_data_buffer_1: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_2: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_10: Std_logic; - signal fifo_colector_inst_data_buffer_3_2: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_18: Std_logic; - signal fifo_colector_inst_data_buffer_2: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_3: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_11: Std_logic; - signal fifo_colector_inst_data_buffer_3_3: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_19: Std_logic; - signal fifo_colector_inst_data_buffer_3: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_4: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_12: Std_logic; - signal fifo_colector_inst_data_buffer_3_4: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_20: Std_logic; - signal fifo_colector_inst_data_buffer_4: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_13: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_5: Std_logic; - signal fifo_colector_inst_data_buffer_3_5: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_21: Std_logic; - signal fifo_colector_inst_data_buffer_5: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_14: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_6: Std_logic; - signal fifo_colector_inst_data_buffer_3_6: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_22: Std_logic; - signal fifo_colector_inst_data_buffer_6: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_7: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_15: Std_logic; - signal fifo_colector_inst_data_buffer_3_7: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_23: Std_logic; - signal fifo_colector_inst_data_buffer_7: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_9: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_17: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_16: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_8: Std_logic; - signal fifo_colector_inst_data_buffer_3_9: Std_logic; - signal fifo_colector_inst_data_buffer_3_8: Std_logic; - signal fifo_colector_inst_iterator_RNI7U5I_1: Std_logic; - signal fifo_colector_inst_data_buffer_8: Std_logic; - signal fifo_colector_inst_data_buffer_9: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_19: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_11: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_10: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_18: Std_logic; - signal fifo_colector_inst_data_buffer_3_11: Std_logic; - signal fifo_colector_inst_data_buffer_3_10: Std_logic; - signal fifo_colector_inst_data_buffer_10: Std_logic; - signal fifo_colector_inst_data_buffer_11: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_21: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_13: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_20: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_12: Std_logic; - signal fifo_colector_inst_data_buffer_3_13: Std_logic; - signal fifo_colector_inst_data_buffer_3_12: Std_logic; - signal fifo_colector_inst_data_buffer_12: Std_logic; - signal fifo_colector_inst_data_buffer_13: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_23: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_15: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_22: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_14: Std_logic; - signal fifo_colector_inst_data_buffer_3_15: Std_logic; - signal fifo_colector_inst_data_buffer_3_14: Std_logic; - signal fifo_colector_inst_data_buffer_14: Std_logic; - signal fifo_colector_inst_data_buffer_15: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_1: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_17: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_16: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_0: Std_logic; - signal fifo_colector_inst_data_buffer_3_17: Std_logic; - signal fifo_colector_inst_data_buffer_3_16: Std_logic; - signal fifo_colector_inst_data_buffer_16: Std_logic; - signal fifo_colector_inst_data_buffer_17: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_3: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_19: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_18: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_2: Std_logic; - signal fifo_colector_inst_data_buffer_3_19: Std_logic; - signal fifo_colector_inst_data_buffer_3_18: Std_logic; - signal fifo_colector_inst_data_buffer_18: Std_logic; - signal fifo_colector_inst_data_buffer_19: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_5: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_21: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_20: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_4: Std_logic; - signal fifo_colector_inst_data_buffer_3_21: Std_logic; - signal fifo_colector_inst_data_buffer_3_20: Std_logic; - signal fifo_colector_inst_data_buffer_20: Std_logic; - signal fifo_colector_inst_data_buffer_21: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_7: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_23: Std_logic; - signal genblk1_0_un1_tdc_channel_fifo_out_inst_22: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_6: Std_logic; - signal fifo_colector_inst_data_buffer_3_23: Std_logic; - signal fifo_colector_inst_data_buffer_3_22: Std_logic; - signal fifo_colector_inst_data_buffer_22: Std_logic; - signal fifo_colector_inst_data_buffer_23: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_9: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_1: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_8: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_0: Std_logic; - signal fifo_colector_inst_data_buffer_3_25: Std_logic; - signal fifo_colector_inst_data_buffer_3_24: Std_logic; - signal fifo_colector_inst_data_buffer_24: Std_logic; - signal fifo_colector_inst_data_buffer_25: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_11: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_3: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_2: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_10: Std_logic; - signal fifo_colector_inst_data_buffer_3_27: Std_logic; - signal fifo_colector_inst_data_buffer_3_26: Std_logic; - signal fifo_colector_inst_data_buffer_26: Std_logic; - signal fifo_colector_inst_data_buffer_27: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_13: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_5: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_4: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_12: Std_logic; - signal fifo_colector_inst_data_buffer_3_29: Std_logic; - signal fifo_colector_inst_data_buffer_3_28: Std_logic; - signal fifo_colector_inst_data_buffer_28: Std_logic; - signal fifo_colector_inst_data_buffer_29: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_15: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_7: Std_logic; - signal genblk1_1_un1_tdc_channel_fifo_out_inst_6: Std_logic; - signal genblk1_2_un1_tdc_channel_fifo_out_inst_14: Std_logic; - signal fifo_colector_inst_data_buffer_3_31: Std_logic; - signal fifo_colector_inst_data_buffer_3_30: Std_logic; - signal fifo_colector_inst_data_buffer_30: Std_logic; - signal fifo_colector_inst_data_buffer_31: Std_logic; - signal fifo_colector_inst_data_buffer_32: Std_logic; - signal fifo_colector_inst_data_buffer_33: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gdata_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w0: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w1: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w2: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w3: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w4: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w5: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w6: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w7: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w8: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w9: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w20: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w21: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w22: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w23: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w24: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w25: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w26: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w27: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w28: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_gcount_w29: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_rptr_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gdata_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_9: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r0: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r1: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r2: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r3: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r4: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r5: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r6: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r7: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r8: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r9: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r20: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r21: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r22: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r23: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r24: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r25: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r26: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r27: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r28: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_gcount_r29: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_2: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_3: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_4: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_5: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_6: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_7: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_8: Std_logic; - signal fifo_colector_inst_fifo40_inst_wptr_9: Std_logic; - signal fifo_colector_inst_un5_in_read_enable: Std_logic; - signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1: Std_logic; - signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2: Std_logic; - signal fifo_rden_c: Std_logic; - signal burst_c: Std_logic; - signal trb_adapter_inst_buf_rden4: Std_logic; - signal fifo_read_1: Std_logic; - signal fifo_read_0: Std_logic; - signal fifo_colector_inst_fb_0_1: Std_logic; - signal fifo_colector_inst_fb_0: Std_logic; - signal fifo_colector_inst_in_empty_pmux: Std_logic; - signal fifo_read_2: Std_logic; - signal fifo_colector_inst_fb_0_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_decoder_valid: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fb_0: Std_logic; - signal trig_c_i_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic; - signal pll_clks_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic; - signal pll_clks_1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic; - signal pll_clks_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_decoder_valid: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fb_0: Std_logic; - signal trig_c_i_1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_decoder_valid: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fb_0: Std_logic; - signal trig_c_i_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7: Std_logic; - signal hades_tdc_bundle_inst_buf_finished5: Std_logic; - signal hades_buf_finished_c: Std_logic; - signal hades_tdc_bundle_inst_N_80: Std_logic; - signal hades_buf_release_c: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1: Std_logic; - signal hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0: Std_logic; - signal hades_dbg2_coarse_c_2: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2: Std_logic; - signal hades_dbg2_coarse_c_4: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_4: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_3: Std_logic; - signal un1_hit_i_2_0_a2: Std_logic; - signal hades_dbg2_out_c_4: Std_logic; - signal hades_dbg2_out_c_5: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_6: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_5: Std_logic; - signal hades_dbg2_out_c_6: Std_logic; - signal hades_dbg2_out_c_7: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_8: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_7: Std_logic; - signal hades_dbg2_out_c_8: Std_logic; - signal hades_dbg2_out_c_9: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_10: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_9: Std_logic; - signal hades_dbg2_out_c_10: Std_logic; - signal hades_dbg2_out_c_11: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_11: Std_logic; - signal hades_dbg2_out_c_12: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97: Std_logic; - signal hades_invalid_dl_c_3: Std_logic; - signal hades_invalid_dl_c_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9: Std_logic; - signal hades_hit_valid_c_1: Std_logic; - signal hades_drop_cmp_buf_valid_c: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i: Std_logic; - signal hades_hit_valid_c_0: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_valid: Std_logic; - signal hades_tdc_bundle_inst_hit_i_0: Std_logic; - signal hades_tdc_bundle_inst_N_246_i: Std_logic; - signal hades_tdc_bundle_inst_hit_i_1: Std_logic; - signal hades_tdc_bundle_inst_N_44: Std_logic; - signal hades_tdc_bundle_inst_N_243_i: Std_logic; - signal hades_hit_valid_c_2: Std_logic; - signal hades_tdc_bundle_inst_N_245_i: Std_logic; - signal hades_hit_valid_c_3: Std_logic; - signal hades_tdc_bundle_inst_N_244_i: Std_logic; - signal hades_invalid_dl_c_1: Std_logic; - signal hades_invalid_dl_c_0: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0: Std_logic; - signal hades_offset_valid_c: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_0: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_2: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_12: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_13: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_14: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_15: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_16: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_17: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_18: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_19: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_20: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_21: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_22: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11: Std_logic; - signal hades_tdc_bundle_inst_hades_raw_out_23: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal: Std_logic; - signal hades_lvl1_c_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0: Std_logic; - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid: Std_logic; - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal: Std_logic; - signal hades_trig_c_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7: Std_logic; - signal hades_trig_c: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7: Std_logic; - - signal hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7: Std_logic; - signal hades_tdc_bundle_inst_SUM1_0_0: Std_logic; - signal hades_tdc_bundle_inst_N_59_i: Std_logic; - - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5: Std_logic; - signal hades_window_end_c: Std_logic; - signal trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0: Std_logic; - signal trb_adapter_inst_buf_rden_prev: Std_logic; - signal finished_c: Std_logic; - signal trb_adapter_inst_finished_prev: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic; - - signal genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic; - - signal genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1: Std_logic; - - signal genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1: Std_logic; - signal fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1: Std_logic; - signal N_248_i: Std_logic; - signal hades_tdc_bundle_inst_N_45: Std_logic; - signal hades_tdc_bundle_inst_N_66: Std_logic; - signal hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0: Std_logic; - signal fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1: Std_logic; - signal fifo_colector_inst_in_empty_pmux_0: Std_logic; - signal hades_tdc_bundle_inst_N_90: Std_logic; - signal hades_tdc_bundle_inst_buf_out12: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0: Std_logic; - signal hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa: Std_logic; - signal genblk1_2_tdc_channel_fifo_out_inst_fifo_wren: Std_logic; - signal genblk1_1_tdc_channel_fifo_out_inst_fifo_wren: Std_logic; - signal genblk1_0_tdc_channel_fifo_out_inst_fifo_wren: Std_logic; - signal LVL1_TRG_DATA_VALI_IN_rising_c: Std_logic; - signal release_out_c: Std_logic; - signal valid_fast_RNI999V: Std_logic; - signal hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0: Std_logic; - signal reset_dl_1: Std_logic; - signal pll0inst_GND: Std_logic; - signal hades_lvl1_c: Std_logic; - signal trig_c_0: Std_logic; - signal trig_c_1: Std_logic; - signal trig_c_2: Std_logic; - signal FEE_DATA_OUT_c_0: Std_logic; - signal clk_c: Std_logic; - signal hades_dbg2_out_c_28: Std_logic; - signal hades_dbg2_out_c_27: Std_logic; - signal hades_dbg2_out_c_26: Std_logic; - signal hades_dbg2_out_c_25: Std_logic; - signal hades_dbg2_out_c_24: Std_logic; - signal hades_dbg2_out_c_23: Std_logic; - signal hades_dbg2_out_c_22: Std_logic; - signal hades_dbg2_out_c_21: Std_logic; - signal hades_dbg2_out_c_20: Std_logic; - signal hades_dbg2_out_c_18: Std_logic; - signal hades_dbg2_out_c_17: Std_logic; - signal hades_dbg2_out_c_16: Std_logic; - signal hades_dbg2_out_c_2: Std_logic; - signal hades_dbg2_out_c_1: Std_logic; - signal hades_dbg2_out_c_0: Std_logic; - signal hades_buf_drop_c_1: Std_logic; - signal hades_buf_out_valid_c: Std_logic; - signal hades_offset_c_8: Std_logic; - signal hades_offset_c_7: Std_logic; - signal hades_offset_c_6: Std_logic; - signal hades_offset_c_5: Std_logic; - signal hades_offset_c_4: Std_logic; - signal hades_offset_c_3: Std_logic; - signal hades_offset_c_2: Std_logic; - signal hades_offset_c_1: Std_logic; - signal hades_offset_c_0: Std_logic; - signal hades_lvl1_invalid_c: Std_logic; - signal hades_raw_out_valid_c: Std_logic; - signal FEE_TRG_RELEASE_OUT_c: Std_logic; - signal FEE_DATAFINISHED_OUT_c: Std_logic; - signal FEE_DATA_WRITE_OUT_c: Std_logic; - signal FEE_DATA_OUT_c_31: Std_logic; - signal FEE_DATA_OUT_c_30: Std_logic; - signal FEE_DATA_OUT_c_29: Std_logic; - signal FEE_DATA_OUT_c_28: Std_logic; - signal FEE_DATA_OUT_c_27: Std_logic; - signal FEE_DATA_OUT_c_26: Std_logic; - signal FEE_DATA_OUT_c_25: Std_logic; - signal FEE_DATA_OUT_c_24: Std_logic; - signal FEE_DATA_OUT_c_23: Std_logic; - signal FEE_DATA_OUT_c_22: Std_logic; - signal FEE_DATA_OUT_c_21: Std_logic; - signal FEE_DATA_OUT_c_20: Std_logic; - signal FEE_DATA_OUT_c_19: Std_logic; - signal FEE_DATA_OUT_c_18: Std_logic; - signal FEE_DATA_OUT_c_17: Std_logic; - signal FEE_DATA_OUT_c_16: Std_logic; - signal FEE_DATA_OUT_c_15: Std_logic; - signal FEE_DATA_OUT_c_14: Std_logic; - signal FEE_DATA_OUT_c_13: Std_logic; - signal FEE_DATA_OUT_c_12: Std_logic; - signal FEE_DATA_OUT_c_11: Std_logic; - signal FEE_DATA_OUT_c_10: Std_logic; - signal FEE_DATA_OUT_c_9: Std_logic; - signal FEE_DATA_OUT_c_8: Std_logic; - signal FEE_DATA_OUT_c_7: Std_logic; - signal FEE_DATA_OUT_c_6: Std_logic; - signal FEE_DATA_OUT_c_5: Std_logic; - signal FEE_DATA_OUT_c_4: Std_logic; - signal FEE_DATA_OUT_c_3: Std_logic; - signal FEE_DATA_OUT_c_2: Std_logic; - signal FEE_DATA_OUT_c_1: Std_logic; - signal LVL1_INVALID_TRG_IN_c: Std_logic; - signal LVL1_TRG_DATA_VALID_IN_c: Std_logic; - signal reset_dc_c: Std_logic; - signal VCCI: Std_logic; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 - port (FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 - port (FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 - port (FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 - port (FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 - port (FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 - port (FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_78 - port (FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_79 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_80 - port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_81 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_82 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_83 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_84 - port (FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_85 - port (B1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_86 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_87 - port (A1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_88 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_89 - port (B1: in Std_logic; B0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_90 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_91 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_92 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_93 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_94 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_95 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_96 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_97 - port (B1: in Std_logic; A1: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_98 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_99 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_100 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_101 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_102 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_103 - port (DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_104 - port (FCI: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 - port (FCI: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 - port (FCI: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - FCI: in Std_logic; F0: out Std_logic; F1: out Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 - port (B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_118 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_119 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; FCI: in Std_logic; - FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_120 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; FCI: in Std_logic; FCO: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_121 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_122 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_123 - port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component trb_adapter_inst_SLICE_124 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_125 - port (B1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_126 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_127 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_128 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_129 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_130 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_131 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_132 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_133 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - OFX0: out Std_logic; Q0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_134 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_135 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_136 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_137 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_138 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_139 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_140 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_141 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_142 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_143 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_144 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_145 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_146 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_147 - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_148 - port (D1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_149 - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_150 - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_151 - port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_152 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_153 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_154 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_155 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_156 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_157 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_158 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_159 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_160 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_161 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_162 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_163 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_164 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_165 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_166 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_167 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_168 - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_169 - port (D1: in Std_logic; C1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_170 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_171 - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_172 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_173 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_174 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_175 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_176 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_177 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_178 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_179 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_180 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_181 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_182 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_183 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_184 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_185 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_186 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_187 - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component trb_adapter_inst_SLICE_188 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_189 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_190 - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 - port (D1: in Std_logic; B1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 - port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 - port (C0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 - port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 - port (C1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 - port (D0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 - port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 - port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 - port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 - port (D1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 - port (C1: in Std_logic; A1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 - port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - B0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - M1: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 - port (C0: in Std_logic; B0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_432 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_433 - port (M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_434 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - DI1: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; - F1: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_435 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_436 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_437 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_438 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_439 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_440 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_441 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_442 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_443 - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_445 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_446 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_447 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_448 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_449 - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_450 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_451 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_452 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_453 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_454 - port (M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_455 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_456 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_457 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_458 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_459 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_460 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 - port (D0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 - port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - DI0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; Q0: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 - port (M0: in Std_logic; CE: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 - port (D0: in Std_logic; C0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 - port (M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI1: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic; F1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_628 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; A0: in Std_logic; DI1: in Std_logic; - DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; - Q1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; DI0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); - end component; - component trb_adapter_inst_SLICE_631 - port (M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - Q0: out Std_logic; Q1: out Std_logic); - end component; - component trb_adapter_inst_SLICE_632 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component trb_adapter_inst_SLICE_633 - port (M0: in Std_logic; CLK: in Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - M0: in Std_logic; OFX0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_648 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_649 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - OFX0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_653 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_654 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_673 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_674 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_675 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_676 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_677 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_678 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_679 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_SLICE_680 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_681 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_683 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_691 - port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_692 - port (D1: in Std_logic; C1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_693 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_698 - port (D1: in Std_logic; B1: in Std_logic; A1: in Std_logic; - D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_701 - port (D1: in Std_logic; B1: in Std_logic; C0: in Std_logic; - A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_702 - port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; - A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_703 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 - port (D1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 - port (D1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 - port (C1: in Std_logic; A1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 - port (C1: in Std_logic; B1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic; F1: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_710 - port (D1: in Std_logic; C1: in Std_logic; D0: in Std_logic; - C0: in Std_logic; B0: in Std_logic; F0: out Std_logic; - F1: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 - port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 - port (B0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 - port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_720 - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_SLICE_721 - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - end component; - component fifo_colector_inst_SLICE_722 - port (D0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component trb_adapter_inst_SLICE_723 - port (D0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - end component; - component trb_adapter_inst_SLICE_724 - port (B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 - port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; - Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 - port (D0: in Std_logic; C0: in Std_logic; F0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 - port (D0: in Std_logic; C0: in Std_logic; A0: in Std_logic; - F0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - - component hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 - port (C0: in Std_logic; B0: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; M0: in Std_logic; CLK: in Std_logic; - F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 - port (D0: in Std_logic; B0: in Std_logic; A0: in Std_logic; - F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - component hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 - port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; - A0: in Std_logic; F0: out Std_logic); - end component; - component SLICE_740 - port (D0: in Std_logic; C0: in Std_logic; M0: in Std_logic; - CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic); - end component; - component hades_tdc_bundle_inst_SLICE_741 - port (C0: in Std_logic; A0: in Std_logic; F0: out Std_logic); - end component; - component pll0inst_SLICE_742 - port (F0: out Std_logic); - end component; - component SLICE_743 - port (D0: in Std_logic; F0: out Std_logic); - end component; - component SLICE_744 - port (D0: in Std_logic; F0: out Std_logic); - end component; - component SLICE_745 - port (D0: in Std_logic; F0: out Std_logic); - end component; - component SLICE_746 - port (D0: in Std_logic; F0: out Std_logic); - end component; - component SLICE_747 - port (A0: in Std_logic; F0: out Std_logic); - end component; - component hades_raw_valid_vect_0_B - port (hadesrawvalidvect0: out Std_logic); - end component; - component fifo_data_out_0_B - port (PADDO: in Std_logic; fifodataout0: out Std_logic); - end component; - component clkB - port (PADDI: out Std_logic; clkS: in Std_logic); - end component; - component hades_drop_cmp_buf_validB - port (PADDO: in Std_logic; hadesdropcmpbufvalid: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_11_B - port (hadesdropcmpbufcoarse11: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_10_B - port (hadesdropcmpbufcoarse10: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_9_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse9: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_8_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse8: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_7_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse7: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_6_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse6: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_5_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse5: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_4_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse4: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_3_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse3: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_2_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse2: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_1_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse1: out Std_logic); - end component; - component hades_drop_cmp_buf_coarse_0_B - port (PADDO: in Std_logic; hadesdropcmpbufcoarse0: out Std_logic); - end component; - component hades_drop_cmp_buf_11_B - port (hadesdropcmpbuf11: out Std_logic); - end component; - component hades_drop_cmp_buf_10_B - port (hadesdropcmpbuf10: out Std_logic); - end component; - component hades_drop_cmp_buf_9_B - port (hadesdropcmpbuf9: out Std_logic); - end component; - component hades_drop_cmp_buf_8_B - port (PADDO: in Std_logic; hadesdropcmpbuf8: out Std_logic); - end component; - component hades_drop_cmp_buf_7_B - port (PADDO: in Std_logic; hadesdropcmpbuf7: out Std_logic); - end component; - component hades_drop_cmp_buf_6_B - port (PADDO: in Std_logic; hadesdropcmpbuf6: out Std_logic); - end component; - component hades_drop_cmp_buf_5_B - port (PADDO: in Std_logic; hadesdropcmpbuf5: out Std_logic); - end component; - component hades_drop_cmp_buf_4_B - port (PADDO: in Std_logic; hadesdropcmpbuf4: out Std_logic); - end component; - component hades_drop_cmp_buf_3_B - port (PADDO: in Std_logic; hadesdropcmpbuf3: out Std_logic); - end component; - component hades_drop_cmp_buf_2_B - port (PADDO: in Std_logic; hadesdropcmpbuf2: out Std_logic); - end component; - component hades_drop_cmp_buf_1_B - port (PADDO: in Std_logic; hadesdropcmpbuf1: out Std_logic); - end component; - component hades_drop_cmp_buf_0_B - port (PADDO: in Std_logic; hadesdropcmpbuf0: out Std_logic); - end component; - component hades_dbg2_coarse_8_B - port (PADDO: in Std_logic; hadesdbg2coarse8: out Std_logic); - end component; - component hades_dbg2_coarse_7_B - port (PADDO: in Std_logic; hadesdbg2coarse7: out Std_logic); - end component; - component hades_dbg2_coarse_6_B - port (PADDO: in Std_logic; hadesdbg2coarse6: out Std_logic); - end component; - component hades_dbg2_coarse_5_B - port (PADDO: in Std_logic; hadesdbg2coarse5: out Std_logic); - end component; - component hades_dbg2_coarse_4_B - port (PADDO: in Std_logic; hadesdbg2coarse4: out Std_logic); - end component; - component hades_dbg2_coarse_3_B - port (PADDO: in Std_logic; hadesdbg2coarse3: out Std_logic); - end component; - component hades_dbg2_coarse_2_B - port (PADDO: in Std_logic; hadesdbg2coarse2: out Std_logic); - end component; - component hades_dbg2_coarse_1_B - port (PADDO: in Std_logic; hadesdbg2coarse1: out Std_logic); - end component; - component hades_dbg2_coarse_0_B - port (PADDO: in Std_logic; hadesdbg2coarse0: out Std_logic); - end component; - component hades_dbg2_out_31_B - port (hadesdbg2out31: out Std_logic); - end component; - component hades_dbg2_out_30_B - port (hadesdbg2out30: out Std_logic); - end component; - component hades_dbg2_out_29_B - port (hadesdbg2out29: out Std_logic); - end component; - component hades_dbg2_out_28_B - port (IOLDO: in Std_logic; hadesdbg2out28: out Std_logic); - end component; - component hades_dbg2_out_28_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_27_B - port (IOLDO: in Std_logic; hadesdbg2out27: out Std_logic); - end component; - component hades_dbg2_out_27_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_26_B - port (IOLDO: in Std_logic; hadesdbg2out26: out Std_logic); - end component; - component hades_dbg2_out_26_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_25_B - port (IOLDO: in Std_logic; hadesdbg2out25: out Std_logic); - end component; - component hades_dbg2_out_25_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_24_B - port (IOLDO: in Std_logic; hadesdbg2out24: out Std_logic); - end component; - component hades_dbg2_out_24_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_23_B - port (IOLDO: in Std_logic; hadesdbg2out23: out Std_logic); - end component; - component hades_dbg2_out_23_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_22_B - port (IOLDO: in Std_logic; hadesdbg2out22: out Std_logic); - end component; - component hades_dbg2_out_22_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_21_B - port (IOLDO: in Std_logic; hadesdbg2out21: out Std_logic); - end component; - component hades_dbg2_out_21_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_20_B - port (IOLDO: in Std_logic; hadesdbg2out20: out Std_logic); - end component; - component hades_dbg2_out_20_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_19_B - port (hadesdbg2out19: out Std_logic); - end component; - component hades_dbg2_out_18_B - port (IOLDO: in Std_logic; hadesdbg2out18: out Std_logic); - end component; - component hades_dbg2_out_18_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_17_B - port (IOLDO: in Std_logic; hadesdbg2out17: out Std_logic); - end component; - component hades_dbg2_out_17_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_16_B - port (IOLDO: in Std_logic; hadesdbg2out16: out Std_logic); - end component; - component hades_dbg2_out_16_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_15_B - port (hadesdbg2out15: out Std_logic); - end component; - component hades_dbg2_out_14_B - port (hadesdbg2out14: out Std_logic); - end component; - component hades_dbg2_out_13_B - port (hadesdbg2out13: out Std_logic); - end component; - component hades_dbg2_out_12_B - port (PADDO: in Std_logic; hadesdbg2out12: out Std_logic); - end component; - component hades_dbg2_out_11_B - port (PADDO: in Std_logic; hadesdbg2out11: out Std_logic); - end component; - component hades_dbg2_out_10_B - port (PADDO: in Std_logic; hadesdbg2out10: out Std_logic); - end component; - component hades_dbg2_out_9_B - port (PADDO: in Std_logic; hadesdbg2out9: out Std_logic); - end component; - component hades_dbg2_out_8_B - port (PADDO: in Std_logic; hadesdbg2out8: out Std_logic); - end component; - component hades_dbg2_out_7_B - port (PADDO: in Std_logic; hadesdbg2out7: out Std_logic); - end component; - component hades_dbg2_out_6_B - port (PADDO: in Std_logic; hadesdbg2out6: out Std_logic); - end component; - component hades_dbg2_out_5_B - port (PADDO: in Std_logic; hadesdbg2out5: out Std_logic); - end component; - component hades_dbg2_out_4_B - port (PADDO: in Std_logic; hadesdbg2out4: out Std_logic); - end component; - component hades_dbg2_out_3_B - port (hadesdbg2out3: out Std_logic); - end component; - component hades_dbg2_out_2_B - port (IOLDO: in Std_logic; hadesdbg2out2: out Std_logic); - end component; - component hades_dbg2_out_2_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_1_B - port (IOLDO: in Std_logic; hadesdbg2out1: out Std_logic); - end component; - component hades_dbg2_out_1_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_dbg2_out_0_B - port (IOLDO: in Std_logic; hadesdbg2out0: out Std_logic); - end component; - component hades_dbg2_out_0_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_buf_drop_3_B - port (hadesbufdrop3: out Std_logic); - end component; - component hades_buf_drop_2_B - port (hadesbufdrop2: out Std_logic); - end component; - component hades_buf_drop_1_B - port (IOLDO: in Std_logic; hadesbufdrop1: out Std_logic); - end component; - component hades_buf_drop_1_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - end component; - component hades_buf_drop_0_B - port (hadesbufdrop0: out Std_logic); - end component; - component hades_invalid_dl_3_B - port (PADDO: in Std_logic; hadesinvaliddl3: out Std_logic); - end component; - component hades_invalid_dl_2_B - port (PADDO: in Std_logic; hadesinvaliddl2: out Std_logic); - end component; - component hades_invalid_dl_1_B - port (PADDO: in Std_logic; hadesinvaliddl1: out Std_logic); - end component; - component hades_invalid_dl_0_B - port (PADDO: in Std_logic; hadesinvaliddl0: out Std_logic); - end component; - component hades_discardB - port (PADDO: in Std_logic; hadesdiscard: out Std_logic); - end component; - component hades_hit_valid_3_B - port (PADDO: in Std_logic; hadeshitvalid3: out Std_logic); - end component; - component hades_hit_valid_2_B - port (PADDO: in Std_logic; hadeshitvalid2: out Std_logic); - end component; - component hades_hit_valid_1_B - port (PADDO: in Std_logic; hadeshitvalid1: out Std_logic); - end component; - component hades_hit_valid_0_B - port (PADDO: in Std_logic; hadeshitvalid0: out Std_logic); - end component; - component hades_hit_out_i_3_B - port (PADDO: in Std_logic; hadeshitouti3: out Std_logic); - end component; - component hades_hit_out_i_2_B - port (PADDO: in Std_logic; hadeshitouti2: out Std_logic); - end component; - component hades_hit_out_i_1_B - port (PADDO: in Std_logic; hadeshitouti1: out Std_logic); - end component; - component hades_hit_out_i_0_B - port (PADDO: in Std_logic; hadeshitouti0: out Std_logic); - end component; - component hades_buf_finishedB - port (PADDO: in Std_logic; hadesbuffinished: out Std_logic); - end component; - component hades_buf_releaseB - port (PADDO: in Std_logic; hadesbufrelease: out Std_logic); - end component; - component hades_buf_out_validB - port (IOLDO: in Std_logic; hadesbufoutvalid: out Std_logic); - end component; - component hades_buf_out_valid_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - CLK: in Std_logic); - end component; - component hades_window_endB - port (PADDO: in Std_logic; hadeswindowend: out Std_logic); - end component; - component hades_offset_validB - port (PADDO: in Std_logic; hadesoffsetvalid: out Std_logic); - end component; - component hades_offset_8_B - port (IOLDO: in Std_logic; hadesoffset8: out Std_logic); - end component; - component hades_offset_8_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_7_B - port (IOLDO: in Std_logic; hadesoffset7: out Std_logic); - end component; - component hades_offset_7_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_6_B - port (IOLDO: in Std_logic; hadesoffset6: out Std_logic); - end component; - component hades_offset_6_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_5_B - port (IOLDO: in Std_logic; hadesoffset5: out Std_logic); - end component; - component hades_offset_5_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_4_B - port (IOLDO: in Std_logic; hadesoffset4: out Std_logic); - end component; - component hades_offset_4_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_3_B - port (IOLDO: in Std_logic; hadesoffset3: out Std_logic); - end component; - component hades_offset_3_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_2_B - port (IOLDO: in Std_logic; hadesoffset2: out Std_logic); - end component; - component hades_offset_2_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_1_B - port (IOLDO: in Std_logic; hadesoffset1: out Std_logic); - end component; - component hades_offset_1_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_offset_0_B - port (IOLDO: in Std_logic; hadesoffset0: out Std_logic); - end component; - component hades_offset_0_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CE: in Std_logic; - LSR: in Std_logic; CLK: in Std_logic); - end component; - component hades_lvl1_invalidB - port (PADDI: out Std_logic; hadeslvl1invalid: in Std_logic); - end component; - component hades_lvl1_invalid_MGIOL - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - end component; - component hades_lvl1B - port (PADDI: out Std_logic; hadeslvl1: in Std_logic); - end component; - component hades_lvl1_MGIOL - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - end component; - component hades_raw_valid_vect_1_B - port (hadesrawvalidvect1: out Std_logic); - end component; - component hades_raw_out_validB - port (IOLDO: in Std_logic; hadesrawoutvalid: out Std_logic); - end component; - component hades_raw_out_valid_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; CLK: in Std_logic); - end component; - component hades_trigB - port (PADDI: out Std_logic; hadestrig: in Std_logic); - end component; - component release_outB - port (PADDO: in Std_logic; releaseout: out Std_logic); - end component; - component finishedB - port (PADDO: in Std_logic; finishedS: out Std_logic); - end component; - component last_buf_emptyB - port (PADDO: in Std_logic; lastbufempty: out Std_logic); - end component; - component discardB - port (PADDO: in Std_logic; discardS: out Std_logic); - end component; - component burstB - port (PADDO: in Std_logic; burstS: out Std_logic); - end component; - component LVL1_TRG_DATA_VALI_IN_risingB - port (PADDO: in Std_logic; LVL1TRGDATAVALIINrising: out Std_logic); - end component; - component FEE_TRG_RELEASE_OUTB - port (IOLDO: in Std_logic; FEETRGRELEASEOUT: out Std_logic); - end component; - component FEE_TRG_RELEASE_OUT_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - end component; - component FEE_DATAFINISHED_OUTB - port (IOLDO: in Std_logic; FEEDATAFINISHEDOUT: out Std_logic); - end component; - component FEE_DATAFINISHED_OUT_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - end component; - component FEE_DATA_WRITE_OUTB - port (IOLDO: in Std_logic; FEEDATAWRITEOUT: out Std_logic); - end component; - component FEE_DATA_WRITE_OUT_MGIOL - port (IOLDO: out Std_logic; TXDATA0: in Std_logic; LSR: in Std_logic; - CLK: in Std_logic); - end component; - component FEE_DATA_OUT_31_B - port (PADDO: in Std_logic; FEEDATAOUT31: out Std_logic); - end component; - component FEE_DATA_OUT_30_B - port (PADDO: in Std_logic; FEEDATAOUT30: out Std_logic); - end component; - component FEE_DATA_OUT_29_B - port (PADDO: in Std_logic; FEEDATAOUT29: out Std_logic); - end component; - component FEE_DATA_OUT_28_B - port (PADDO: in Std_logic; FEEDATAOUT28: out Std_logic); - end component; - component FEE_DATA_OUT_27_B - port (PADDO: in Std_logic; FEEDATAOUT27: out Std_logic); - end component; - component FEE_DATA_OUT_26_B - port (PADDO: in Std_logic; FEEDATAOUT26: out Std_logic); - end component; - component FEE_DATA_OUT_25_B - port (PADDO: in Std_logic; FEEDATAOUT25: out Std_logic); - end component; - component FEE_DATA_OUT_24_B - port (PADDO: in Std_logic; FEEDATAOUT24: out Std_logic); - end component; - component FEE_DATA_OUT_23_B - port (PADDO: in Std_logic; FEEDATAOUT23: out Std_logic); - end component; - component FEE_DATA_OUT_22_B - port (PADDO: in Std_logic; FEEDATAOUT22: out Std_logic); - end component; - component FEE_DATA_OUT_21_B - port (PADDO: in Std_logic; FEEDATAOUT21: out Std_logic); - end component; - component FEE_DATA_OUT_20_B - port (PADDO: in Std_logic; FEEDATAOUT20: out Std_logic); - end component; - component FEE_DATA_OUT_19_B - port (PADDO: in Std_logic; FEEDATAOUT19: out Std_logic); - end component; - component FEE_DATA_OUT_18_B - port (PADDO: in Std_logic; FEEDATAOUT18: out Std_logic); - end component; - component FEE_DATA_OUT_17_B - port (PADDO: in Std_logic; FEEDATAOUT17: out Std_logic); - end component; - component FEE_DATA_OUT_16_B - port (PADDO: in Std_logic; FEEDATAOUT16: out Std_logic); - end component; - component FEE_DATA_OUT_15_B - port (PADDO: in Std_logic; FEEDATAOUT15: out Std_logic); - end component; - component FEE_DATA_OUT_14_B - port (PADDO: in Std_logic; FEEDATAOUT14: out Std_logic); - end component; - component FEE_DATA_OUT_13_B - port (PADDO: in Std_logic; FEEDATAOUT13: out Std_logic); - end component; - component FEE_DATA_OUT_12_B - port (PADDO: in Std_logic; FEEDATAOUT12: out Std_logic); - end component; - component FEE_DATA_OUT_11_B - port (PADDO: in Std_logic; FEEDATAOUT11: out Std_logic); - end component; - component FEE_DATA_OUT_10_B - port (PADDO: in Std_logic; FEEDATAOUT10: out Std_logic); - end component; - component FEE_DATA_OUT_9_B - port (PADDO: in Std_logic; FEEDATAOUT9: out Std_logic); - end component; - component FEE_DATA_OUT_8_B - port (PADDO: in Std_logic; FEEDATAOUT8: out Std_logic); - end component; - component FEE_DATA_OUT_7_B - port (PADDO: in Std_logic; FEEDATAOUT7: out Std_logic); - end component; - component FEE_DATA_OUT_6_B - port (PADDO: in Std_logic; FEEDATAOUT6: out Std_logic); - end component; - component FEE_DATA_OUT_5_B - port (PADDO: in Std_logic; FEEDATAOUT5: out Std_logic); - end component; - component FEE_DATA_OUT_4_B - port (PADDO: in Std_logic; FEEDATAOUT4: out Std_logic); - end component; - component FEE_DATA_OUT_3_B - port (PADDO: in Std_logic; FEEDATAOUT3: out Std_logic); - end component; - component FEE_DATA_OUT_2_B - port (PADDO: in Std_logic; FEEDATAOUT2: out Std_logic); - end component; - component FEE_DATA_OUT_1_B - port (PADDO: in Std_logic; FEEDATAOUT1: out Std_logic); - end component; - component FEE_DATA_OUT_0_B - port (PADDO: in Std_logic; FEEDATAOUT0: out Std_logic); - end component; - component LVL1_INVALID_TRG_INB - port (PADDI: out Std_logic; LVL1INVALIDTRGIN: in Std_logic); - end component; - component LVL1_INVALID_TRG_IN_MGIOL - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - end component; - component LVL1_TRG_DATA_VALID_INB - port (PADDI: out Std_logic; LVL1TRGDATAVALIDIN: in Std_logic); - end component; - component LVL1_TRG_DATA_VALID_IN_MGIOL - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - end component; - component fifo_empty1B - port (PADDO: in Std_logic; fifoempty1: out Std_logic); - end component; - component fifo_rdenB - port (PADDO: in Std_logic; fiforden: out Std_logic); - end component; - component fifo_data_out_31_B - port (PADDO: in Std_logic; fifodataout31: out Std_logic); - end component; - component fifo_data_out_30_B - port (PADDO: in Std_logic; fifodataout30: out Std_logic); - end component; - component fifo_data_out_29_B - port (PADDO: in Std_logic; fifodataout29: out Std_logic); - end component; - component fifo_data_out_28_B - port (PADDO: in Std_logic; fifodataout28: out Std_logic); - end component; - component fifo_data_out_27_B - port (PADDO: in Std_logic; fifodataout27: out Std_logic); - end component; - component fifo_data_out_26_B - port (PADDO: in Std_logic; fifodataout26: out Std_logic); - end component; - component fifo_data_out_25_B - port (PADDO: in Std_logic; fifodataout25: out Std_logic); - end component; - component fifo_data_out_24_B - port (PADDO: in Std_logic; fifodataout24: out Std_logic); - end component; - component fifo_data_out_23_B - port (PADDO: in Std_logic; fifodataout23: out Std_logic); - end component; - component fifo_data_out_22_B - port (PADDO: in Std_logic; fifodataout22: out Std_logic); - end component; - component fifo_data_out_21_B - port (PADDO: in Std_logic; fifodataout21: out Std_logic); - end component; - component fifo_data_out_20_B - port (PADDO: in Std_logic; fifodataout20: out Std_logic); - end component; - component fifo_data_out_19_B - port (PADDO: in Std_logic; fifodataout19: out Std_logic); - end component; - component fifo_data_out_18_B - port (PADDO: in Std_logic; fifodataout18: out Std_logic); - end component; - component fifo_data_out_17_B - port (PADDO: in Std_logic; fifodataout17: out Std_logic); - end component; - component fifo_data_out_16_B - port (PADDO: in Std_logic; fifodataout16: out Std_logic); - end component; - component fifo_data_out_15_B - port (PADDO: in Std_logic; fifodataout15: out Std_logic); - end component; - component fifo_data_out_14_B - port (PADDO: in Std_logic; fifodataout14: out Std_logic); - end component; - component fifo_data_out_13_B - port (PADDO: in Std_logic; fifodataout13: out Std_logic); - end component; - component fifo_data_out_12_B - port (PADDO: in Std_logic; fifodataout12: out Std_logic); - end component; - component fifo_data_out_11_B - port (PADDO: in Std_logic; fifodataout11: out Std_logic); - end component; - component fifo_data_out_10_B - port (PADDO: in Std_logic; fifodataout10: out Std_logic); - end component; - component fifo_data_out_9_B - port (PADDO: in Std_logic; fifodataout9: out Std_logic); - end component; - component fifo_data_out_8_B - port (PADDO: in Std_logic; fifodataout8: out Std_logic); - end component; - component fifo_data_out_7_B - port (PADDO: in Std_logic; fifodataout7: out Std_logic); - end component; - component fifo_data_out_6_B - port (PADDO: in Std_logic; fifodataout6: out Std_logic); - end component; - component fifo_data_out_5_B - port (PADDO: in Std_logic; fifodataout5: out Std_logic); - end component; - component fifo_data_out_4_B - port (PADDO: in Std_logic; fifodataout4: out Std_logic); - end component; - component fifo_data_out_3_B - port (PADDO: in Std_logic; fifodataout3: out Std_logic); - end component; - component fifo_data_out_2_B - port (PADDO: in Std_logic; fifodataout2: out Std_logic); - end component; - component fifo_data_out_1_B - port (PADDO: in Std_logic; fifodataout1: out Std_logic); - end component; - component trig_2_B - port (PADDI: out Std_logic; trig2: in Std_logic); - end component; - component trig_1_B - port (PADDI: out Std_logic; trig1: in Std_logic); - end component; - component trig_0_B - port (PADDI: out Std_logic; trig0: in Std_logic); - end component; - component reset_dcB - port (PADDI: out Std_logic; resetdc: in Std_logic); - end component; - component reset_dc_MGIOL - port (DI: in Std_logic; CLK: in Std_logic; INFF: out Std_logic); - end component; - component rd_clkB - port (PADDI: out Std_logic; rdclk: in Std_logic); - end component; - component genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - end component; - component genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - end component; - component genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port (DIA15: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA9: in Std_logic; ADA13: in Std_logic; - ADA12: in Std_logic; ADA11: in Std_logic; ADA10: in Std_logic; - ADA9: in Std_logic; ADA8: in Std_logic; ADA7: in Std_logic; - ADA6: in Std_logic; ADA5: in Std_logic; DOA17: out Std_logic; - DOA16: out Std_logic; DOA15: out Std_logic; DOA14: out Std_logic; - DOA13: out Std_logic; DOA12: out Std_logic; DOA11: out Std_logic; - DOA10: out Std_logic; DOA9: out Std_logic; DOA8: out Std_logic; - DOA7: out Std_logic; DOA6: out Std_logic; DOA5: out Std_logic; - DOA4: out Std_logic; DOA3: out Std_logic; DOA2: out Std_logic; - DOA1: out Std_logic; DOA0: out Std_logic; CEA: in Std_logic; - CLKA: in Std_logic; CLKB: in Std_logic; OCEB: in Std_logic; - CEB: in Std_logic; DOB0: out Std_logic; DOB1: out Std_logic; - DOB2: out Std_logic; DOB3: out Std_logic; DOB4: out Std_logic; - DOB5: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB6: in Std_logic; DIB8: in Std_logic; - DIB9: in Std_logic); - end component; - component fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 - port (DIA17: in Std_logic; DIA16: in Std_logic; DIA15: in Std_logic; - DIA14: in Std_logic; DIA13: in Std_logic; DIA12: in Std_logic; - DIA11: in Std_logic; DIA10: in Std_logic; DIA9: in Std_logic; - DIA8: in Std_logic; DIA7: in Std_logic; DIA6: in Std_logic; - DIA5: in Std_logic; DIA4: in Std_logic; DIA3: in Std_logic; - DIA2: in Std_logic; DIA1: in Std_logic; DIA0: in Std_logic; - ADA13: in Std_logic; ADA12: in Std_logic; ADA11: in Std_logic; - ADA10: in Std_logic; ADA9: in Std_logic; ADA8: in Std_logic; - ADA7: in Std_logic; ADA6: in Std_logic; ADA5: in Std_logic; - DOA17: out Std_logic; DOA16: out Std_logic; DOA15: out Std_logic; - DOA14: out Std_logic; DOA13: out Std_logic; DOA12: out Std_logic; - DOA11: out Std_logic; DOA10: out Std_logic; DOA9: out Std_logic; - DOA8: out Std_logic; DOA7: out Std_logic; DOA6: out Std_logic; - DOA5: out Std_logic; DOA4: out Std_logic; DOA3: out Std_logic; - DOA2: out Std_logic; DOA1: out Std_logic; DOA0: out Std_logic; - CEA: in Std_logic; CLKA: in Std_logic; CLKB: in Std_logic; - OCEB: in Std_logic; CEB: in Std_logic; DOB0: out Std_logic; - DOB1: out Std_logic; DOB2: out Std_logic; DOB3: out Std_logic; - DOB4: out Std_logic; DOB5: out Std_logic; DOB6: out Std_logic; - DOB7: out Std_logic; DOB8: out Std_logic; DOB9: out Std_logic; - DOB10: out Std_logic; DOB11: out Std_logic; DOB12: out Std_logic; - DOB13: out Std_logic; ADB5: in Std_logic; ADB6: in Std_logic; - ADB7: in Std_logic; ADB8: in Std_logic; ADB9: in Std_logic; - ADB10: in Std_logic; ADB11: in Std_logic; ADB12: in Std_logic; - ADB13: in Std_logic; DIB0: in Std_logic; DIB1: in Std_logic; - DIB2: in Std_logic; DIB3: in Std_logic; DIB4: in Std_logic; - DIB5: in Std_logic; DIB6: in Std_logic; DIB7: in Std_logic; - DIB8: in Std_logic; DIB9: in Std_logic; DIB10: in Std_logic; - DIB11: in Std_logic; DIB12: in Std_logic; DIB13: in Std_logic; - DIB14: in Std_logic; DIB15: in Std_logic); - end component; - component pll0inst_PLLInst_0 - port (CLKI: in Std_logic; CLKFB: in Std_logic; STDBY: in Std_logic; - CLKOS3: out Std_logic; CLKOS2: out Std_logic; CLKOS: out Std_logic; - CLKOP: out Std_logic); - end component; - begin - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_0 - port map ( - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_1 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_2 - port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_3 - port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_4 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_5 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_6 - port map ( - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_7 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_8 - port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_9 - port map (A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_10 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_11 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_12 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_13 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_14 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_15 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_16 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_17 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_18 - port map (DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - Q0=>fifo_empty_2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_19 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_20 - port map (B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_21 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_22 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_23 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_24 - port map ( - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, - FCO=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_25 - port map (DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - CLK=>pll_clks_3, - FCI=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_26 - port map ( - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_27 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_28 - port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_29 - port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_30 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_31 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_32 - port map ( - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_33 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_34 - port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_35 - port map (A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_36 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_37 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_38 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_39 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_40 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_41 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_42 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_43 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_44 - port map (DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - Q0=>fifo_empty_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_45 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_46 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_47 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_48 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_49 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_50 - port map ( - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, - FCO=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_51 - port map (DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - CLK=>pll_clks_3, - FCI=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_52 - port map ( - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_53 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gctr_ci, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_1, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_54 - port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_3, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_55 - port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_4, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_5, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_56 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_6, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_7, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_57 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_8, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_iwcount_9, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_58 - port map ( - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_59 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gctr_ci, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_1, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_60 - port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_1, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_3, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_61 - port map (A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_1, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_4, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_5, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_62 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_1, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_6, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_7, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_63 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_1, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_8, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_ircount_9, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_64 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_65 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_66 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_2, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_67 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_2, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_68 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_2, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_69 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_2, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_70 - port map (DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d_c, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_d, - Q0=>fifo_empty1_c); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_71 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_72 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_cmp_ci_1, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_73 - port map (B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co0_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_74 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co1_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_75 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co2_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_76 - port map ( - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_co3_3, - FCO=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_77 - port map (DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - CLK=>pll_clks_3, - FCI=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d_c, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_d, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full); - - fifo_colector_inst_fifo40_inst_SLICE_78I: fifo_colector_inst_fifo40_inst_SLICE_78 - port map (FCO=>fifo_colector_inst_fifo40_inst_w_gctr_ci); - - fifo_colector_inst_fifo40_inst_SLICE_79I: fifo_colector_inst_fifo40_inst_SLICE_79 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_1, - B0=>fifo_colector_inst_fifo40_inst_wcount_0, - DI1=>fifo_colector_inst_fifo40_inst_iwcount_1, - DI0=>fifo_colector_inst_fifo40_inst_iwcount_0, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_w_gctr_ci, - F0=>fifo_colector_inst_fifo40_inst_iwcount_0, - Q0=>fifo_colector_inst_fifo40_inst_wcount_0, - F1=>fifo_colector_inst_fifo40_inst_iwcount_1, - Q1=>fifo_colector_inst_fifo40_inst_wcount_1, - FCO=>fifo_colector_inst_fifo40_inst_co0); - - fifo_colector_inst_fifo40_inst_SLICE_80I: fifo_colector_inst_fifo40_inst_SLICE_80 - port map (A1=>fifo_colector_inst_fifo40_inst_wcount_3, - A0=>fifo_colector_inst_fifo40_inst_wcount_2, - DI1=>fifo_colector_inst_fifo40_inst_iwcount_3, - DI0=>fifo_colector_inst_fifo40_inst_iwcount_2, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_co0, - F0=>fifo_colector_inst_fifo40_inst_iwcount_2, - Q0=>fifo_colector_inst_fifo40_inst_wcount_2, - F1=>fifo_colector_inst_fifo40_inst_iwcount_3, - Q1=>fifo_colector_inst_fifo40_inst_wcount_3, - FCO=>fifo_colector_inst_fifo40_inst_co1); - - fifo_colector_inst_fifo40_inst_SLICE_81I: fifo_colector_inst_fifo40_inst_SLICE_81 - port map (A1=>fifo_colector_inst_fifo40_inst_wcount_5, - B0=>fifo_colector_inst_fifo40_inst_wcount_4, - DI1=>fifo_colector_inst_fifo40_inst_iwcount_5, - DI0=>fifo_colector_inst_fifo40_inst_iwcount_4, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_co1, - F0=>fifo_colector_inst_fifo40_inst_iwcount_4, - Q0=>fifo_colector_inst_fifo40_inst_wcount_4, - F1=>fifo_colector_inst_fifo40_inst_iwcount_5, - Q1=>fifo_colector_inst_fifo40_inst_wcount_5, - FCO=>fifo_colector_inst_fifo40_inst_co2); - - fifo_colector_inst_fifo40_inst_SLICE_82I: fifo_colector_inst_fifo40_inst_SLICE_82 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_7, - B0=>fifo_colector_inst_fifo40_inst_wcount_6, - DI1=>fifo_colector_inst_fifo40_inst_iwcount_7, - DI0=>fifo_colector_inst_fifo40_inst_iwcount_6, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_co2, - F0=>fifo_colector_inst_fifo40_inst_iwcount_6, - Q0=>fifo_colector_inst_fifo40_inst_wcount_6, - F1=>fifo_colector_inst_fifo40_inst_iwcount_7, - Q1=>fifo_colector_inst_fifo40_inst_wcount_7, - FCO=>fifo_colector_inst_fifo40_inst_co3); - - fifo_colector_inst_fifo40_inst_SLICE_83I: fifo_colector_inst_fifo40_inst_SLICE_83 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_9, - B0=>fifo_colector_inst_fifo40_inst_wcount_8, - DI1=>fifo_colector_inst_fifo40_inst_iwcount_9, - DI0=>fifo_colector_inst_fifo40_inst_iwcount_8, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_co3, - F0=>fifo_colector_inst_fifo40_inst_iwcount_8, - Q0=>fifo_colector_inst_fifo40_inst_wcount_8, - F1=>fifo_colector_inst_fifo40_inst_iwcount_9, - Q1=>fifo_colector_inst_fifo40_inst_wcount_9); - - fifo_colector_inst_fifo40_inst_SLICE_84I: fifo_colector_inst_fifo40_inst_SLICE_84 - port map (FCO=>fifo_colector_inst_fifo40_inst_r_gctr_ci); - - fifo_colector_inst_fifo40_inst_SLICE_85I: fifo_colector_inst_fifo40_inst_SLICE_85 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_1, - A0=>fifo_colector_inst_fifo40_inst_rcount_0, - DI1=>fifo_colector_inst_fifo40_inst_ircount_1, - DI0=>fifo_colector_inst_fifo40_inst_ircount_0, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_r_gctr_ci, - F0=>fifo_colector_inst_fifo40_inst_ircount_0, - Q0=>fifo_colector_inst_fifo40_inst_rcount_0, - F1=>fifo_colector_inst_fifo40_inst_ircount_1, - Q1=>fifo_colector_inst_fifo40_inst_rcount_1, - FCO=>fifo_colector_inst_fifo40_inst_co0_1); - - fifo_colector_inst_fifo40_inst_SLICE_86I: fifo_colector_inst_fifo40_inst_SLICE_86 - port map (A1=>fifo_colector_inst_fifo40_inst_rcount_3, - B0=>fifo_colector_inst_fifo40_inst_rcount_2, - DI1=>fifo_colector_inst_fifo40_inst_ircount_3, - DI0=>fifo_colector_inst_fifo40_inst_ircount_2, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_co0_1, - F0=>fifo_colector_inst_fifo40_inst_ircount_2, - Q0=>fifo_colector_inst_fifo40_inst_rcount_2, - F1=>fifo_colector_inst_fifo40_inst_ircount_3, - Q1=>fifo_colector_inst_fifo40_inst_rcount_3, - FCO=>fifo_colector_inst_fifo40_inst_co1_1); - - fifo_colector_inst_fifo40_inst_SLICE_87I: fifo_colector_inst_fifo40_inst_SLICE_87 - port map (A1=>fifo_colector_inst_fifo40_inst_rcount_5, - B0=>fifo_colector_inst_fifo40_inst_rcount_4, - DI1=>fifo_colector_inst_fifo40_inst_ircount_5, - DI0=>fifo_colector_inst_fifo40_inst_ircount_4, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_co1_1, - F0=>fifo_colector_inst_fifo40_inst_ircount_4, - Q0=>fifo_colector_inst_fifo40_inst_rcount_4, - F1=>fifo_colector_inst_fifo40_inst_ircount_5, - Q1=>fifo_colector_inst_fifo40_inst_rcount_5, - FCO=>fifo_colector_inst_fifo40_inst_co2_1); - - fifo_colector_inst_fifo40_inst_SLICE_88I: fifo_colector_inst_fifo40_inst_SLICE_88 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_7, - B0=>fifo_colector_inst_fifo40_inst_rcount_6, - DI1=>fifo_colector_inst_fifo40_inst_ircount_7, - DI0=>fifo_colector_inst_fifo40_inst_ircount_6, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_co2_1, - F0=>fifo_colector_inst_fifo40_inst_ircount_6, - Q0=>fifo_colector_inst_fifo40_inst_rcount_6, - F1=>fifo_colector_inst_fifo40_inst_ircount_7, - Q1=>fifo_colector_inst_fifo40_inst_rcount_7, - FCO=>fifo_colector_inst_fifo40_inst_co3_1); - - fifo_colector_inst_fifo40_inst_SLICE_89I: fifo_colector_inst_fifo40_inst_SLICE_89 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_9, - B0=>fifo_colector_inst_fifo40_inst_rcount_8, - DI1=>fifo_colector_inst_fifo40_inst_ircount_9, - DI0=>fifo_colector_inst_fifo40_inst_ircount_8, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_co3_1, - F0=>fifo_colector_inst_fifo40_inst_ircount_8, - Q0=>fifo_colector_inst_fifo40_inst_rcount_8, - F1=>fifo_colector_inst_fifo40_inst_ircount_9, - Q1=>fifo_colector_inst_fifo40_inst_rcount_9); - - fifo_colector_inst_fifo40_inst_SLICE_90I: fifo_colector_inst_fifo40_inst_SLICE_90 - port map (B1=>fifo_colector_inst_fifo40_inst_rden_i, - A1=>fifo_colector_inst_fifo40_inst_rden_i, - FCO=>fifo_colector_inst_fifo40_inst_cmp_ci); - - fifo_colector_inst_fifo40_inst_SLICE_91I: fifo_colector_inst_fifo40_inst_SLICE_91 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_1, - A1=>fifo_colector_inst_fifo40_inst_wcount_r1, - B0=>fifo_colector_inst_fifo40_inst_rcount_0, - A0=>fifo_colector_inst_fifo40_inst_wcount_r0, - FCI=>fifo_colector_inst_fifo40_inst_cmp_ci, - FCO=>fifo_colector_inst_fifo40_inst_co0_2); - - fifo_colector_inst_fifo40_inst_SLICE_92I: fifo_colector_inst_fifo40_inst_SLICE_92 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_3, - A1=>fifo_colector_inst_fifo40_inst_wcount_r3, - B0=>fifo_colector_inst_fifo40_inst_wcount_r2, - A0=>fifo_colector_inst_fifo40_inst_rcount_2, - FCI=>fifo_colector_inst_fifo40_inst_co0_2, - FCO=>fifo_colector_inst_fifo40_inst_co1_2); - - fifo_colector_inst_fifo40_inst_SLICE_93I: fifo_colector_inst_fifo40_inst_SLICE_93 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_r5, - A1=>fifo_colector_inst_fifo40_inst_rcount_5, - B0=>fifo_colector_inst_fifo40_inst_wcount_r4, - A0=>fifo_colector_inst_fifo40_inst_rcount_4, - FCI=>fifo_colector_inst_fifo40_inst_co1_2, - FCO=>fifo_colector_inst_fifo40_inst_co2_2); - - fifo_colector_inst_fifo40_inst_SLICE_94I: fifo_colector_inst_fifo40_inst_SLICE_94 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_7, - A1=>fifo_colector_inst_fifo40_inst_wcount_r7, - B0=>fifo_colector_inst_fifo40_inst_rcount_6, - A0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - FCI=>fifo_colector_inst_fifo40_inst_co2_2, - FCO=>fifo_colector_inst_fifo40_inst_co3_2); - - fifo_colector_inst_fifo40_inst_SLICE_95I: fifo_colector_inst_fifo40_inst_SLICE_95 - port map (B1=>fifo_colector_inst_fifo40_inst_empty_cmp_set, - A1=>fifo_colector_inst_fifo40_inst_empty_cmp_clr, - B0=>fifo_colector_inst_fifo40_inst_rcount_8, - A0=>fifo_colector_inst_fifo40_inst_wcount_r8, - FCI=>fifo_colector_inst_fifo40_inst_co3_2, - FCO=>fifo_colector_inst_fifo40_inst_empty_d_c); - - fifo_colector_inst_fifo40_inst_SLICE_96I: fifo_colector_inst_fifo40_inst_SLICE_96 - port map (DI0=>fifo_colector_inst_fifo40_inst_empty_d, CLK=>rd_clk_c, - FCI=>fifo_colector_inst_fifo40_inst_empty_d_c, - F0=>fifo_colector_inst_fifo40_inst_empty_d, - Q0=>last_buf_empty_c); - - fifo_colector_inst_fifo40_inst_SLICE_97I: fifo_colector_inst_fifo40_inst_SLICE_97 - port map (B1=>fifo_colector_inst_fifo40_inst_wren_i, - A1=>fifo_colector_inst_fifo40_inst_wren_i, - FCO=>fifo_colector_inst_fifo40_inst_cmp_ci_1); - - fifo_colector_inst_fifo40_inst_SLICE_98I: fifo_colector_inst_fifo40_inst_SLICE_98 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_1, - A1=>fifo_colector_inst_fifo40_inst_rcount_w1, - B0=>fifo_colector_inst_fifo40_inst_rcount_w0, - A0=>fifo_colector_inst_fifo40_inst_wcount_0, - FCI=>fifo_colector_inst_fifo40_inst_cmp_ci_1, - FCO=>fifo_colector_inst_fifo40_inst_co0_3); - - fifo_colector_inst_fifo40_inst_SLICE_99I: fifo_colector_inst_fifo40_inst_SLICE_99 - port map (B1=>fifo_colector_inst_fifo40_inst_wcount_3, - A1=>fifo_colector_inst_fifo40_inst_rcount_w3, - B0=>fifo_colector_inst_fifo40_inst_rcount_w2, - A0=>fifo_colector_inst_fifo40_inst_wcount_2, - FCI=>fifo_colector_inst_fifo40_inst_co0_3, - FCO=>fifo_colector_inst_fifo40_inst_co1_3); - - fifo_colector_inst_fifo40_inst_SLICE_100I: fifo_colector_inst_fifo40_inst_SLICE_100 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_w5, - A1=>fifo_colector_inst_fifo40_inst_wcount_5, - B0=>fifo_colector_inst_fifo40_inst_wcount_4, - A0=>fifo_colector_inst_fifo40_inst_rcount_w4, - FCI=>fifo_colector_inst_fifo40_inst_co1_3, - FCO=>fifo_colector_inst_fifo40_inst_co2_3); - - fifo_colector_inst_fifo40_inst_SLICE_101I: fifo_colector_inst_fifo40_inst_SLICE_101 - port map (B1=>fifo_colector_inst_fifo40_inst_rcount_w7, - A1=>fifo_colector_inst_fifo40_inst_wcount_7, - B0=>fifo_colector_inst_fifo40_inst_wcount_6, - A0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, - FCI=>fifo_colector_inst_fifo40_inst_co2_3, - FCO=>fifo_colector_inst_fifo40_inst_co3_3); - - fifo_colector_inst_fifo40_inst_SLICE_102I: fifo_colector_inst_fifo40_inst_SLICE_102 - port map (B1=>fifo_colector_inst_fifo40_inst_full_cmp_clr, - A1=>fifo_colector_inst_fifo40_inst_full_cmp_set, - B0=>fifo_colector_inst_fifo40_inst_wcount_8, - A0=>fifo_colector_inst_fifo40_inst_rcount_w8, - FCI=>fifo_colector_inst_fifo40_inst_co3_3, - FCO=>fifo_colector_inst_fifo40_inst_full_d_c); - - fifo_colector_inst_fifo40_inst_SLICE_103I: fifo_colector_inst_fifo40_inst_SLICE_103 - port map (DI0=>fifo_colector_inst_fifo40_inst_full_d, CLK=>pll_clks_3, - FCI=>fifo_colector_inst_fifo40_inst_full_d_c, - F0=>fifo_colector_inst_fifo40_inst_full_d, - Q0=>fifo_colector_inst_fifo40_inst_Full); - hades_tdc_bundle_inst_SLICE_104I: hades_tdc_bundle_inst_SLICE_104 - port map (FCI=>hades_tdc_bundle_inst_hit_valid25_0_I_27_cry, - F0=>hades_tdc_bundle_inst_hit_valid25); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_105 - port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_0, - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_106 - port map (D1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5, - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14 - , B1=>hades_dbg2_coarse_c_5, - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6 - , B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_dbg2_coarse_c_3, - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_0 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_107 - port map (D1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, - C1=>hades_dbg2_coarse_c_8, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - D0=>hades_dbg2_coarse_c_7, C0=>hades_dbg2_coarse_c_6, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_data_tmp_2 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_108 - port map ( - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_I_27_cry - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_109 - port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_0, - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_110 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8 - , B1=>hades_dbg2_coarse_c_5, - A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5, - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6 - , B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_dbg2_coarse_c_3, - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_0 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_111 - port map (D1=>hades_dbg2_coarse_c_8, - C1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - D0=>hades_dbg2_coarse_c_6, C0=>hades_dbg2_coarse_c_7, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_data_tmp_2 - , - FCO=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_112 - port map ( - FCI=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_I_27_cry - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_113 - port map ( - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , - FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_114 - port map ( - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_0 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1 - , - FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_115 - port map ( - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, - FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_2 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1 - , - FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_116 - port map ( - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , - FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_4 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1 - , - FCO=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_117 - port map ( - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2 - , A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, - FCI=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_6 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0 - ); - hades_tdc_bundle_inst_SLICE_118I: hades_tdc_bundle_inst_SLICE_118 - port map (D1=>hades_drop_cmp_buf_c_0, C1=>hades_drop_cmp_buf_coarse_c_0, - B1=>hades_drop_cmp_buf_coarse_c_1, A1=>hades_drop_cmp_buf_c_1, - FCO=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0); - hades_tdc_bundle_inst_SLICE_119I: hades_tdc_bundle_inst_SLICE_119 - port map (D1=>hades_drop_cmp_buf_coarse_c_5, C1=>hades_drop_cmp_buf_c_5, - B1=>hades_drop_cmp_buf_coarse_c_4, A1=>hades_drop_cmp_buf_c_4, - D0=>hades_drop_cmp_buf_coarse_c_3, C0=>hades_drop_cmp_buf_c_2, - B0=>hades_drop_cmp_buf_coarse_c_2, A0=>hades_drop_cmp_buf_c_3, - FCI=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_0, - FCO=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2); - hades_tdc_bundle_inst_SLICE_120I: hades_tdc_bundle_inst_SLICE_120 - port map (D1=>hades_drop_cmp_buf_c_8, C1=>hades_drop_cmp_buf_coarse_c_9, - B1=>hades_drop_cmp_buf_coarse_c_8, - D0=>hades_drop_cmp_buf_coarse_c_7, - C0=>hades_drop_cmp_buf_coarse_c_6, B0=>hades_drop_cmp_buf_c_6, - A0=>hades_drop_cmp_buf_c_7, - FCI=>hades_tdc_bundle_inst_hit_valid25_0_data_tmp_2, - FCO=>hades_tdc_bundle_inst_hit_valid25_0_I_27_cry); - hades_tdc_bundle_inst_SLICE_121I: hades_tdc_bundle_inst_SLICE_121 - port map (D1=>ANB1, C1=>ANB2, B1=>ANB0, A1=>ANB3, D0=>ANB0, - DI0=>hades_tdc_bundle_inst_N_247_i, - M0=>hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0, - LSR=>reset_dl_2, CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_N_247_i, Q0=>ANB0); - hades_tdc_bundle_inst_SLICE_122I: hades_tdc_bundle_inst_SLICE_122 - port map (D1=>ANB1, C1=>ANB0, B1=>ANB2, A1=>ANB3, C0=>ANB0, B0=>ANB1, - DI1=>hades_tdc_bundle_inst_N_50_i_i, - DI0=>hades_tdc_bundle_inst_N_46_i, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_N_46_i, Q0=>ANB1, - F1=>hades_tdc_bundle_inst_N_50_i_i, Q1=>ANB3); - hades_tdc_bundle_inst_SLICE_123I: hades_tdc_bundle_inst_SLICE_123 - port map (B1=>ANB2, A1=>ANB1, D0=>hades_discard_c, C0=>ANB1, B0=>ANB2, - A0=>ANB3, DI0=>hades_tdc_bundle_inst_hit_out_i_6_2, M0=>ANB0, - LSR=>reset_dl_2, CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hit_out_i_6_2, Q0=>ANB2); - trb_adapter_inst_SLICE_124I: trb_adapter_inst_SLICE_124 - port map (M0=>trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0, CLK=>rd_clk_c, - Q0=>discard_c); - fifo_colector_inst_SLICE_125I: fifo_colector_inst_SLICE_125 - port map (B1=>fifo_empty_2, D0=>fifo_empty_1, - C0=>fifo_colector_inst_iterator_0, A0=>fifo_empty1_c, - DI0=>fifo_colector_inst_in_empty_pmux_i, - M0=>fifo_colector_inst_iterator_1, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_in_empty_pmux_i, - Q0=>fifo_colector_inst_buffer_wr_enable); - fifo_colector_inst_SLICE_126I: fifo_colector_inst_SLICE_126 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, - A1=>fifo_colector_inst_iterator_1, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, - B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_0, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_16, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_0, - Q0=>fifo_colector_inst_data_buffer_0); - fifo_colector_inst_SLICE_127I: fifo_colector_inst_SLICE_127 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, - A1=>fifo_colector_inst_iterator_1, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, - B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_1, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_17, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_1, - Q0=>fifo_colector_inst_data_buffer_1); - fifo_colector_inst_SLICE_128I: fifo_colector_inst_SLICE_128 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, - A1=>fifo_colector_inst_iterator_1, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, - B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_2, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_18, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_2, - Q0=>fifo_colector_inst_data_buffer_2); - fifo_colector_inst_SLICE_129I: fifo_colector_inst_SLICE_129 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, - A1=>fifo_colector_inst_iterator_1, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, - B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_3, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_19, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_3, - Q0=>fifo_colector_inst_data_buffer_3); - fifo_colector_inst_SLICE_130I: fifo_colector_inst_SLICE_130 - port map (D1=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, - C1=>fifo_colector_inst_iterator_0, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, - A1=>fifo_colector_inst_iterator_1, - D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, - C0=>fifo_colector_inst_iterator_0, - B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_4, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_20, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_4, - Q0=>fifo_colector_inst_data_buffer_4); - fifo_colector_inst_SLICE_131I: fifo_colector_inst_SLICE_131 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, - A1=>fifo_colector_inst_iterator_1, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, - B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_5, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_21, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_5, - Q0=>fifo_colector_inst_data_buffer_5); - fifo_colector_inst_SLICE_132I: fifo_colector_inst_SLICE_132 - port map (D1=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, - C1=>fifo_colector_inst_iterator_0, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, - A1=>fifo_colector_inst_iterator_1, - D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, - C0=>fifo_colector_inst_iterator_0, - B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_6, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_22, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_6, - Q0=>fifo_colector_inst_data_buffer_6); - fifo_colector_inst_SLICE_133I: fifo_colector_inst_SLICE_133 - port map (D1=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, - B1=>fifo_colector_inst_iterator_0, - A1=>fifo_colector_inst_iterator_1, - D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, - B0=>fifo_colector_inst_iterator_0, - A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_data_buffer_3_7, - M0=>genblk1_2_un1_tdc_channel_fifo_out_inst_23, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - OFX0=>fifo_colector_inst_data_buffer_3_7, - Q0=>fifo_colector_inst_data_buffer_7); - fifo_colector_inst_SLICE_134I: fifo_colector_inst_SLICE_134 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_0_un1_tdc_channel_fifo_out_inst_9, - A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_17, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_16, - B0=>genblk1_0_un1_tdc_channel_fifo_out_inst_8, - DI1=>fifo_colector_inst_data_buffer_3_9, - DI0=>fifo_colector_inst_data_buffer_3_8, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_8, - Q0=>fifo_colector_inst_data_buffer_8, - F1=>fifo_colector_inst_data_buffer_3_9, - Q1=>fifo_colector_inst_data_buffer_9); - fifo_colector_inst_SLICE_135I: fifo_colector_inst_SLICE_135 - port map (D1=>fifo_colector_inst_iterator_0, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_19, - A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_11, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_10, - B0=>genblk1_1_un1_tdc_channel_fifo_out_inst_18, - DI1=>fifo_colector_inst_data_buffer_3_11, - DI0=>fifo_colector_inst_data_buffer_3_10, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_10, - Q0=>fifo_colector_inst_data_buffer_10, - F1=>fifo_colector_inst_data_buffer_3_11, - Q1=>fifo_colector_inst_data_buffer_11); - fifo_colector_inst_SLICE_136I: fifo_colector_inst_SLICE_136 - port map (D1=>fifo_colector_inst_iterator_0, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_21, - A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_13, - D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_20, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_12, - A0=>fifo_colector_inst_iterator_0, - DI1=>fifo_colector_inst_data_buffer_3_13, - DI0=>fifo_colector_inst_data_buffer_3_12, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_12, - Q0=>fifo_colector_inst_data_buffer_12, - F1=>fifo_colector_inst_data_buffer_3_13, - Q1=>fifo_colector_inst_data_buffer_13); - fifo_colector_inst_SLICE_137I: fifo_colector_inst_SLICE_137 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_23, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_15, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_22, - A0=>genblk1_0_un1_tdc_channel_fifo_out_inst_14, - DI1=>fifo_colector_inst_data_buffer_3_15, - DI0=>fifo_colector_inst_data_buffer_3_14, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_14, - Q0=>fifo_colector_inst_data_buffer_14, - F1=>fifo_colector_inst_data_buffer_3_15, - Q1=>fifo_colector_inst_data_buffer_15); - fifo_colector_inst_SLICE_138I: fifo_colector_inst_SLICE_138 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_1, - B1=>genblk1_0_un1_tdc_channel_fifo_out_inst_17, - D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_16, - C0=>genblk1_2_un1_tdc_channel_fifo_out_inst_0, - B0=>fifo_colector_inst_iterator_0, - DI1=>fifo_colector_inst_data_buffer_3_17, - DI0=>fifo_colector_inst_data_buffer_3_16, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_16, - Q0=>fifo_colector_inst_data_buffer_16, - F1=>fifo_colector_inst_data_buffer_3_17, - Q1=>fifo_colector_inst_data_buffer_17); - fifo_colector_inst_SLICE_139I: fifo_colector_inst_SLICE_139 - port map (D1=>fifo_colector_inst_iterator_0, - B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_3, - A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_19, - D0=>genblk1_0_un1_tdc_channel_fifo_out_inst_18, - B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_2, - A0=>fifo_colector_inst_iterator_0, - DI1=>fifo_colector_inst_data_buffer_3_19, - DI0=>fifo_colector_inst_data_buffer_3_18, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_18, - Q0=>fifo_colector_inst_data_buffer_18, - F1=>fifo_colector_inst_data_buffer_3_19, - Q1=>fifo_colector_inst_data_buffer_19); - fifo_colector_inst_SLICE_140I: fifo_colector_inst_SLICE_140 - port map (D1=>fifo_colector_inst_iterator_0, - B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_5, - A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_21, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_20, - B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_4, - DI1=>fifo_colector_inst_data_buffer_3_21, - DI0=>fifo_colector_inst_data_buffer_3_20, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_20, - Q0=>fifo_colector_inst_data_buffer_20, - F1=>fifo_colector_inst_data_buffer_3_21, - Q1=>fifo_colector_inst_data_buffer_21); - fifo_colector_inst_SLICE_141I: fifo_colector_inst_SLICE_141 - port map (D1=>fifo_colector_inst_iterator_0, - B1=>genblk1_2_un1_tdc_channel_fifo_out_inst_7, - A1=>genblk1_0_un1_tdc_channel_fifo_out_inst_23, - D0=>fifo_colector_inst_iterator_0, - C0=>genblk1_0_un1_tdc_channel_fifo_out_inst_22, - A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_6, - DI1=>fifo_colector_inst_data_buffer_3_23, - DI0=>fifo_colector_inst_data_buffer_3_22, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_22, - Q0=>fifo_colector_inst_data_buffer_22, - F1=>fifo_colector_inst_data_buffer_3_23, - Q1=>fifo_colector_inst_data_buffer_23); - fifo_colector_inst_SLICE_142I: fifo_colector_inst_SLICE_142 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_9, - A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_1, - C0=>fifo_colector_inst_iterator_0, - B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_8, - A0=>genblk1_1_un1_tdc_channel_fifo_out_inst_0, - DI1=>fifo_colector_inst_data_buffer_3_25, - DI0=>fifo_colector_inst_data_buffer_3_24, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_24, - Q0=>fifo_colector_inst_data_buffer_24, - F1=>fifo_colector_inst_data_buffer_3_25, - Q1=>fifo_colector_inst_data_buffer_25); - fifo_colector_inst_SLICE_143I: fifo_colector_inst_SLICE_143 - port map (D1=>fifo_colector_inst_iterator_0, - C1=>genblk1_2_un1_tdc_channel_fifo_out_inst_11, - B1=>genblk1_1_un1_tdc_channel_fifo_out_inst_3, - D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_2, - B0=>fifo_colector_inst_iterator_0, - A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_10, - DI1=>fifo_colector_inst_data_buffer_3_27, - DI0=>fifo_colector_inst_data_buffer_3_26, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_26, - Q0=>fifo_colector_inst_data_buffer_26, - F1=>fifo_colector_inst_data_buffer_3_27, - Q1=>fifo_colector_inst_data_buffer_27); - fifo_colector_inst_SLICE_144I: fifo_colector_inst_SLICE_144 - port map (D1=>genblk1_2_un1_tdc_channel_fifo_out_inst_13, - B1=>fifo_colector_inst_iterator_0, - A1=>genblk1_1_un1_tdc_channel_fifo_out_inst_5, - C0=>genblk1_1_un1_tdc_channel_fifo_out_inst_4, - B0=>fifo_colector_inst_iterator_0, - A0=>genblk1_2_un1_tdc_channel_fifo_out_inst_12, - DI1=>fifo_colector_inst_data_buffer_3_29, - DI0=>fifo_colector_inst_data_buffer_3_28, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_28, - Q0=>fifo_colector_inst_data_buffer_28, - F1=>fifo_colector_inst_data_buffer_3_29, - Q1=>fifo_colector_inst_data_buffer_29); - fifo_colector_inst_SLICE_145I: fifo_colector_inst_SLICE_145 - port map (D1=>genblk1_2_un1_tdc_channel_fifo_out_inst_15, - C1=>genblk1_1_un1_tdc_channel_fifo_out_inst_7, - B1=>fifo_colector_inst_iterator_0, - D0=>genblk1_1_un1_tdc_channel_fifo_out_inst_6, - C0=>fifo_colector_inst_iterator_0, - B0=>genblk1_2_un1_tdc_channel_fifo_out_inst_14, - DI1=>fifo_colector_inst_data_buffer_3_31, - DI0=>fifo_colector_inst_data_buffer_3_30, - CE=>fifo_colector_inst_in_empty_pmux_i, - LSR=>fifo_colector_inst_iterator_RNI7U5I_1, CLK=>pll_clks_3, - F0=>fifo_colector_inst_data_buffer_3_30, - Q0=>fifo_colector_inst_data_buffer_30, - F1=>fifo_colector_inst_data_buffer_3_31, - Q1=>fifo_colector_inst_data_buffer_31); - fifo_colector_inst_SLICE_146I: fifo_colector_inst_SLICE_146 - port map (M1=>fifo_colector_inst_iterator_1, - M0=>fifo_colector_inst_iterator_0, - CE=>fifo_colector_inst_in_empty_pmux_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_data_buffer_32, - Q1=>fifo_colector_inst_data_buffer_33); - - fifo_colector_inst_fifo40_inst_SLICE_147I: fifo_colector_inst_fifo40_inst_SLICE_147 - port map (C1=>fifo_colector_inst_fifo40_inst_rcount_1, - A1=>fifo_colector_inst_fifo40_inst_rcount_2, - D0=>fifo_colector_inst_fifo40_inst_rcount_0, - C0=>fifo_colector_inst_fifo40_inst_rcount_1, - DI1=>fifo_colector_inst_fifo40_inst_r_gdata_1, - DI0=>fifo_colector_inst_fifo40_inst_r_gdata_0, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - F0=>fifo_colector_inst_fifo40_inst_r_gdata_0, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_0, - F1=>fifo_colector_inst_fifo40_inst_r_gdata_1, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_1); - - fifo_colector_inst_fifo40_inst_SLICE_148I: fifo_colector_inst_fifo40_inst_SLICE_148 - port map (D1=>fifo_colector_inst_fifo40_inst_rcount_4, - A1=>fifo_colector_inst_fifo40_inst_rcount_3, - B0=>fifo_colector_inst_fifo40_inst_rcount_2, - A0=>fifo_colector_inst_fifo40_inst_rcount_3, - DI1=>fifo_colector_inst_fifo40_inst_r_gdata_3, - DI0=>fifo_colector_inst_fifo40_inst_r_gdata_2, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - F0=>fifo_colector_inst_fifo40_inst_r_gdata_2, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_2, - F1=>fifo_colector_inst_fifo40_inst_r_gdata_3, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_3); - - fifo_colector_inst_fifo40_inst_SLICE_149I: fifo_colector_inst_fifo40_inst_SLICE_149 - port map (C1=>fifo_colector_inst_fifo40_inst_rcount_6, - A1=>fifo_colector_inst_fifo40_inst_rcount_5, - D0=>fifo_colector_inst_fifo40_inst_rcount_4, - A0=>fifo_colector_inst_fifo40_inst_rcount_5, - DI1=>fifo_colector_inst_fifo40_inst_r_gdata_5, - DI0=>fifo_colector_inst_fifo40_inst_r_gdata_4, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - F0=>fifo_colector_inst_fifo40_inst_r_gdata_4, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_4, - F1=>fifo_colector_inst_fifo40_inst_r_gdata_5, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_5); - - fifo_colector_inst_fifo40_inst_SLICE_150I: fifo_colector_inst_fifo40_inst_SLICE_150 - port map (D1=>fifo_colector_inst_fifo40_inst_rcount_7, - C1=>fifo_colector_inst_fifo40_inst_rcount_8, - D0=>fifo_colector_inst_fifo40_inst_rcount_7, - C0=>fifo_colector_inst_fifo40_inst_rcount_6, - DI1=>fifo_colector_inst_fifo40_inst_r_gdata_7, - DI0=>fifo_colector_inst_fifo40_inst_r_gdata_6, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - F0=>fifo_colector_inst_fifo40_inst_r_gdata_6, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_6, - F1=>fifo_colector_inst_fifo40_inst_r_gdata_7, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_7); - - fifo_colector_inst_fifo40_inst_SLICE_151I: fifo_colector_inst_fifo40_inst_SLICE_151 - port map (D0=>fifo_colector_inst_fifo40_inst_rcount_9, - B0=>fifo_colector_inst_fifo40_inst_rcount_8, - DI0=>fifo_colector_inst_fifo40_inst_r_gdata_8, - M1=>fifo_colector_inst_fifo40_inst_rcount_9, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - F0=>fifo_colector_inst_fifo40_inst_r_gdata_8, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_8, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_9); - - fifo_colector_inst_fifo40_inst_SLICE_152I: fifo_colector_inst_fifo40_inst_SLICE_152 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_1, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_0, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w0, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w1); - - fifo_colector_inst_fifo40_inst_SLICE_153I: fifo_colector_inst_fifo40_inst_SLICE_153 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_3, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_2, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w2, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w3); - - fifo_colector_inst_fifo40_inst_SLICE_154I: fifo_colector_inst_fifo40_inst_SLICE_154 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_5, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_4, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w4, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w5); - - fifo_colector_inst_fifo40_inst_SLICE_155I: fifo_colector_inst_fifo40_inst_SLICE_155 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_7, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_6, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w6, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w7); - - fifo_colector_inst_fifo40_inst_SLICE_156I: fifo_colector_inst_fifo40_inst_SLICE_156 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_9, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_8, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w8, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w9); - - fifo_colector_inst_fifo40_inst_SLICE_157I: fifo_colector_inst_fifo40_inst_SLICE_157 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w1, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w0, - CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w20, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w21); - - fifo_colector_inst_fifo40_inst_SLICE_158I: fifo_colector_inst_fifo40_inst_SLICE_158 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w3, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w2, - CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w22, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w23); - - fifo_colector_inst_fifo40_inst_SLICE_159I: fifo_colector_inst_fifo40_inst_SLICE_159 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w5, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w4, - CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w25); - - fifo_colector_inst_fifo40_inst_SLICE_160I: fifo_colector_inst_fifo40_inst_SLICE_160 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w7, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w6, - CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w27); - - fifo_colector_inst_fifo40_inst_SLICE_161I: fifo_colector_inst_fifo40_inst_SLICE_161 - port map (M1=>fifo_colector_inst_fifo40_inst_r_gcount_w9, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w8, - CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - Q1=>fifo_colector_inst_fifo40_inst_r_gcount_w29); - - fifo_colector_inst_fifo40_inst_SLICE_162I: fifo_colector_inst_fifo40_inst_SLICE_162 - port map (M1=>fifo_colector_inst_fifo40_inst_rcount_1, - M0=>fifo_colector_inst_fifo40_inst_rcount_0, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_rptr_0, - Q1=>fifo_colector_inst_fifo40_inst_rptr_1); - - fifo_colector_inst_fifo40_inst_SLICE_163I: fifo_colector_inst_fifo40_inst_SLICE_163 - port map (M1=>fifo_colector_inst_fifo40_inst_rcount_3, - M0=>fifo_colector_inst_fifo40_inst_rcount_2, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_rptr_2, - Q1=>fifo_colector_inst_fifo40_inst_rptr_3); - - fifo_colector_inst_fifo40_inst_SLICE_164I: fifo_colector_inst_fifo40_inst_SLICE_164 - port map (M1=>fifo_colector_inst_fifo40_inst_rcount_5, - M0=>fifo_colector_inst_fifo40_inst_rcount_4, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_rptr_4, - Q1=>fifo_colector_inst_fifo40_inst_rptr_5); - - fifo_colector_inst_fifo40_inst_SLICE_165I: fifo_colector_inst_fifo40_inst_SLICE_165 - port map (M1=>fifo_colector_inst_fifo40_inst_rcount_7, - M0=>fifo_colector_inst_fifo40_inst_rcount_6, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_rptr_6, - Q1=>fifo_colector_inst_fifo40_inst_rptr_7); - - fifo_colector_inst_fifo40_inst_SLICE_166I: fifo_colector_inst_fifo40_inst_SLICE_166 - port map (M1=>fifo_colector_inst_fifo40_inst_rcount_9, - M0=>fifo_colector_inst_fifo40_inst_rcount_8, - CE=>fifo_colector_inst_fifo40_inst_rden_i, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_rptr_8, - Q1=>fifo_colector_inst_fifo40_inst_rptr_9); - - fifo_colector_inst_fifo40_inst_SLICE_167I: fifo_colector_inst_fifo40_inst_SLICE_167 - port map (C1=>fifo_colector_inst_fifo40_inst_wcount_2, - B1=>fifo_colector_inst_fifo40_inst_wcount_1, - D0=>fifo_colector_inst_fifo40_inst_wcount_0, - B0=>fifo_colector_inst_fifo40_inst_wcount_1, - DI1=>fifo_colector_inst_fifo40_inst_w_gdata_1, - DI0=>fifo_colector_inst_fifo40_inst_w_gdata_0, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fifo40_inst_w_gdata_0, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_0, - F1=>fifo_colector_inst_fifo40_inst_w_gdata_1, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_1); - - fifo_colector_inst_fifo40_inst_SLICE_168I: fifo_colector_inst_fifo40_inst_SLICE_168 - port map (D1=>fifo_colector_inst_fifo40_inst_wcount_3, - C1=>fifo_colector_inst_fifo40_inst_wcount_4, - D0=>fifo_colector_inst_fifo40_inst_wcount_3, - C0=>fifo_colector_inst_fifo40_inst_wcount_2, - DI1=>fifo_colector_inst_fifo40_inst_w_gdata_3, - DI0=>fifo_colector_inst_fifo40_inst_w_gdata_2, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fifo40_inst_w_gdata_2, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_2, - F1=>fifo_colector_inst_fifo40_inst_w_gdata_3, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_3); - - fifo_colector_inst_fifo40_inst_SLICE_169I: fifo_colector_inst_fifo40_inst_SLICE_169 - port map (D1=>fifo_colector_inst_fifo40_inst_wcount_6, - C1=>fifo_colector_inst_fifo40_inst_wcount_5, - C0=>fifo_colector_inst_fifo40_inst_wcount_5, - A0=>fifo_colector_inst_fifo40_inst_wcount_4, - DI1=>fifo_colector_inst_fifo40_inst_w_gdata_5, - DI0=>fifo_colector_inst_fifo40_inst_w_gdata_4, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fifo40_inst_w_gdata_4, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_4, - F1=>fifo_colector_inst_fifo40_inst_w_gdata_5, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_5); - - fifo_colector_inst_fifo40_inst_SLICE_170I: fifo_colector_inst_fifo40_inst_SLICE_170 - port map (D1=>fifo_colector_inst_fifo40_inst_wcount_8, - B1=>fifo_colector_inst_fifo40_inst_wcount_7, - D0=>fifo_colector_inst_fifo40_inst_wcount_6, - B0=>fifo_colector_inst_fifo40_inst_wcount_7, - DI1=>fifo_colector_inst_fifo40_inst_w_gdata_7, - DI0=>fifo_colector_inst_fifo40_inst_w_gdata_6, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fifo40_inst_w_gdata_6, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_6, - F1=>fifo_colector_inst_fifo40_inst_w_gdata_7, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_7); - - fifo_colector_inst_fifo40_inst_SLICE_171I: fifo_colector_inst_fifo40_inst_SLICE_171 - port map (D0=>fifo_colector_inst_fifo40_inst_wcount_9, - C0=>fifo_colector_inst_fifo40_inst_wcount_8, - DI0=>fifo_colector_inst_fifo40_inst_w_gdata_8, - M1=>fifo_colector_inst_fifo40_inst_wcount_9, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fifo40_inst_w_gdata_8, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_8, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_9); - - fifo_colector_inst_fifo40_inst_SLICE_172I: fifo_colector_inst_fifo40_inst_SLICE_172 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_1, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_0, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r0, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r1); - - fifo_colector_inst_fifo40_inst_SLICE_173I: fifo_colector_inst_fifo40_inst_SLICE_173 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_3, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_2, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r2, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r3); - - fifo_colector_inst_fifo40_inst_SLICE_174I: fifo_colector_inst_fifo40_inst_SLICE_174 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_5, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_4, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r4, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r5); - - fifo_colector_inst_fifo40_inst_SLICE_175I: fifo_colector_inst_fifo40_inst_SLICE_175 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_7, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_6, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r6, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r7); - - fifo_colector_inst_fifo40_inst_SLICE_176I: fifo_colector_inst_fifo40_inst_SLICE_176 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_9, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_8, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r8, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r9); - - fifo_colector_inst_fifo40_inst_SLICE_177I: fifo_colector_inst_fifo40_inst_SLICE_177 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r1, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_r0, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r20, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r21); - - fifo_colector_inst_fifo40_inst_SLICE_178I: fifo_colector_inst_fifo40_inst_SLICE_178 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r3, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_r2, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r22, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r23); - - fifo_colector_inst_fifo40_inst_SLICE_179I: fifo_colector_inst_fifo40_inst_SLICE_179 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r5, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_r4, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r24, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r25); - - fifo_colector_inst_fifo40_inst_SLICE_180I: fifo_colector_inst_fifo40_inst_SLICE_180 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r7, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_r6, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r26, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r27); - - fifo_colector_inst_fifo40_inst_SLICE_181I: fifo_colector_inst_fifo40_inst_SLICE_181 - port map (M1=>fifo_colector_inst_fifo40_inst_w_gcount_r9, - M0=>fifo_colector_inst_fifo40_inst_w_gcount_r8, CLK=>rd_clk_c, - Q0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, - Q1=>fifo_colector_inst_fifo40_inst_w_gcount_r29); - - fifo_colector_inst_fifo40_inst_SLICE_182I: fifo_colector_inst_fifo40_inst_SLICE_182 - port map (M1=>fifo_colector_inst_fifo40_inst_wcount_1, - M0=>fifo_colector_inst_fifo40_inst_wcount_0, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_wptr_0, - Q1=>fifo_colector_inst_fifo40_inst_wptr_1); - - fifo_colector_inst_fifo40_inst_SLICE_183I: fifo_colector_inst_fifo40_inst_SLICE_183 - port map (M1=>fifo_colector_inst_fifo40_inst_wcount_3, - M0=>fifo_colector_inst_fifo40_inst_wcount_2, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_wptr_2, - Q1=>fifo_colector_inst_fifo40_inst_wptr_3); - - fifo_colector_inst_fifo40_inst_SLICE_184I: fifo_colector_inst_fifo40_inst_SLICE_184 - port map (M1=>fifo_colector_inst_fifo40_inst_wcount_5, - M0=>fifo_colector_inst_fifo40_inst_wcount_4, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_wptr_4, - Q1=>fifo_colector_inst_fifo40_inst_wptr_5); - - fifo_colector_inst_fifo40_inst_SLICE_185I: fifo_colector_inst_fifo40_inst_SLICE_185 - port map (M1=>fifo_colector_inst_fifo40_inst_wcount_7, - M0=>fifo_colector_inst_fifo40_inst_wcount_6, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_wptr_6, - Q1=>fifo_colector_inst_fifo40_inst_wptr_7); - - fifo_colector_inst_fifo40_inst_SLICE_186I: fifo_colector_inst_fifo40_inst_SLICE_186 - port map (M1=>fifo_colector_inst_fifo40_inst_wcount_9, - M0=>fifo_colector_inst_fifo40_inst_wcount_8, - CE=>fifo_colector_inst_fifo40_inst_wren_i, CLK=>pll_clks_3, - Q0=>fifo_colector_inst_fifo40_inst_wptr_8, - Q1=>fifo_colector_inst_fifo40_inst_wptr_9); - fifo_colector_inst_SLICE_187I: fifo_colector_inst_SLICE_187 - port map (C0=>fifo_colector_inst_iterator_0, - B0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_un5_in_read_enable, - M1=>fifo_colector_inst_iterator_0, CLK=>pll_clks_3, - F0=>fifo_colector_inst_un5_in_read_enable, - Q0=>fifo_colector_inst_iterator_0, - Q1=>fifo_colector_inst_iterator_1); - trb_adapter_inst_SLICE_188I: trb_adapter_inst_SLICE_188 - port map (C1=>discard_c, - B1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, - A1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2, - D0=>fifo_rden_c, C0=>last_buf_empty_c, B0=>burst_c, - DI0=>trb_adapter_inst_buf_rden4, CLK=>rd_clk_c, - F0=>trb_adapter_inst_buf_rden4, Q0=>fifo_rden_c, F1=>burst_c); - fifo_colector_inst_SLICE_189I: fifo_colector_inst_SLICE_189 - port map (C1=>fifo_colector_inst_iterator_0, B1=>fifo_read_1, - D0=>fifo_read_0, C0=>fifo_colector_inst_iterator_0, - A0=>fifo_colector_inst_iterator_1, - DI1=>fifo_colector_inst_fb_0_1, DI0=>fifo_colector_inst_fb_0, - LSR=>fifo_colector_inst_in_empty_pmux, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fb_0, Q0=>fifo_read_0, - F1=>fifo_colector_inst_fb_0_1, Q1=>fifo_read_1); - fifo_colector_inst_SLICE_190I: fifo_colector_inst_SLICE_190 - port map (D0=>fifo_read_2, A0=>fifo_colector_inst_iterator_1, - DI0=>fifo_colector_inst_fb_0_0, - LSR=>fifo_colector_inst_in_empty_pmux, CLK=>pll_clks_3, - F0=>fifo_colector_inst_fb_0_0, Q0=>fifo_read_2); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_192 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_193 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_194 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_195 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_196 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_197 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_198 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_199 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_200 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_201 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_202 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_203 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_204 - port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - , B0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i, - LSR=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_N_352_i, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_205 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_valid_internal, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_206 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_207 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_208 - port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_209 - port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_210 - port map (C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_211 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_212 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_213 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_214 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_215 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_216 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_217 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_218 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_219 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_220 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_221 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_222 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_223 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_224 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_225 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_226 - port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_227 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_228 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_229 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - DI1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_230 - port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_231 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_232 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_233 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_234 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_235 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_236 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_237 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_238 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_239 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_240 - port map ( - M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_241 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_242 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_243 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_244 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_245 - port map (M1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - CE=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9); - - genblk1_0_tdc_channel_fifo_out_inst_SLICE_246I: genblk1_0_tdc_channel_fifo_out_inst_SLICE_246 - port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - B0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid, - DI0=>genblk1_0_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>genblk1_0_tdc_channel_fifo_out_inst_fb_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_256 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, - CLK=>pll_clks_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_257 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, - CLK=>pll_clks_1, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_258 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, - CLK=>pll_clks_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_259 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_260 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, - CLK=>pll_clks_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_261 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, - CLK=>pll_clks_1, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_262 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, - CLK=>pll_clks_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_263 - port map (M1=>trig_c_i_0, - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - Q1=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_264 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - CLK=>pll_clks_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_0); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_265 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - CLK=>pll_clks_1, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_1); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_266 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - CLK=>pll_clks_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_2); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_267 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_3); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_268 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - CLK=>pll_clks_0, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_4); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_269 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - CLK=>pll_clks_1, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_5); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_270 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - CLK=>pll_clks_2, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_6); - - genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271I: genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_SLICE_271 - port map ( - M0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - CLK=>pll_clks_3, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_tdc_out_7); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_272 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_273 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_274 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_275 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_276 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_277 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_278 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_279 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_280 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_281 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_282 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_283 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_284 - port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - C0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - , B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, - A0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i, - LSR=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_N_351_i, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_285 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_valid_internal, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_286 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_287 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_288 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_289 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_290 - port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_291 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_292 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_293 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_294 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_295 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_296 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_297 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_298 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_299 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_300 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_301 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_302 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_303 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_304 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_305 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_306 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_307 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_308 - port map (B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_309 - port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - DI1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_310 - port map (B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_311 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_312 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_313 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_314 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_315 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_316 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_317 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_318 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_319 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_320 - port map ( - M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_321 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_322 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_323 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_324 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_325 - port map (M1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - CE=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9); - - genblk1_1_tdc_channel_fifo_out_inst_SLICE_326I: genblk1_1_tdc_channel_fifo_out_inst_SLICE_326 - port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - A0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid, - DI0=>genblk1_1_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>genblk1_1_tdc_channel_fifo_out_inst_fb_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_336 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, - CLK=>pll_clks_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_337 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, - CLK=>pll_clks_1, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_338 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, - CLK=>pll_clks_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_339 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_340 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, - CLK=>pll_clks_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_341 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, - CLK=>pll_clks_1, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_342 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, - CLK=>pll_clks_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_343 - port map (M1=>trig_c_i_1, - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - Q1=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_344 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - CLK=>pll_clks_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_0); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_345 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - CLK=>pll_clks_1, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_1); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_346 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - CLK=>pll_clks_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_2); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_347 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_3); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_348 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - CLK=>pll_clks_0, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_4); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_349 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - CLK=>pll_clks_1, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_5); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_350 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - CLK=>pll_clks_2, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_6); - - genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351I: genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_SLICE_351 - port map ( - M0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - CLK=>pll_clks_3, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_tdc_out_7); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_352 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_353 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_354 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_355 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_356 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_357 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_358 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_359 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_0_6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_360 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_361 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_362 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_363 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_364 - port map ( - D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - , C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - B0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_0, - A0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_1, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i, - LSR=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_N_350_i, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_365 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_valid_internal, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_366 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_1, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_367 - port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_3, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_368 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_4, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_5, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_369 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_6, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_7, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_370 - port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gdata_8, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_371 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_372 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_373 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_374 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_375 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_376 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_377 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_378 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_379 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_380 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w8, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_381 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_382 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_383 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_384 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_385 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_8, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_386 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_1, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_387 - port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_3, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_388 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_4, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_5, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_389 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - DI1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_6, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_7, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_390 - port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gdata_8, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_391 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_392 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_393 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_394 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_395 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_8, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_396 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r0, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_397 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r2, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_398 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r4, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_399 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r6, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_400 - port map ( - M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r8, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_401 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_1, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_0, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_402 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_2, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_403 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_5, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_4, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_404 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_7, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_6, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_405 - port map (M1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_8, - CE=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9); - - genblk1_2_tdc_channel_fifo_out_inst_SLICE_406I: genblk1_2_tdc_channel_fifo_out_inst_SLICE_406 - port map (C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid, - DI0=>genblk1_2_tdc_channel_fifo_out_inst_fb_0, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>genblk1_2_tdc_channel_fifo_out_inst_fb_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_416 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0, - CLK=>pll_clks_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_0); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_417 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1, - CLK=>pll_clks_1, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_1); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_418 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2, - CLK=>pll_clks_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_2); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_419 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_3); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_420 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4, - CLK=>pll_clks_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_4); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_421 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5, - CLK=>pll_clks_1, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_5); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_422 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6, - CLK=>pll_clks_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_6); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_423 - port map (M1=>trig_c_i_2, - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - Q1=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_in_clk_synced_7); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_424 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_0, - CLK=>pll_clks_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_0); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_425 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_1, - CLK=>pll_clks_1, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_1); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_426 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_2, - CLK=>pll_clks_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_2); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_427 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_3, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_3); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_428 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_4, - CLK=>pll_clks_0, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_4); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_429 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_5, - CLK=>pll_clks_1, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_5); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_430 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_6, - CLK=>pll_clks_2, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_6); - - genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431I: genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_SLICE_431 - port map ( - M0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_inst_out_buffered1_7, - CLK=>pll_clks_3, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_tdc_out_7); - hades_tdc_bundle_inst_SLICE_432I: hades_tdc_bundle_inst_SLICE_432 - port map (D1=>ANB1, B1=>ANB3, D0=>ANB0, C0=>ANB1, B0=>ANB3, A0=>ANB2, - DI0=>hades_tdc_bundle_inst_buf_finished5, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_buf_finished5, - Q0=>hades_buf_finished_c, F1=>hades_tdc_bundle_inst_N_80); - hades_tdc_bundle_inst_SLICE_433I: hades_tdc_bundle_inst_SLICE_433 - port map (M0=>hades_buf_finished_c, LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_buf_release_c); - hades_tdc_bundle_inst_SLICE_434I: hades_tdc_bundle_inst_SLICE_434 - port map (C1=>hades_dbg2_coarse_c_0, B1=>hades_dbg2_coarse_c_1, - D0=>hades_dbg2_coarse_c_0, - DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, - DI0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, - Q0=>hades_dbg2_coarse_c_0, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, - Q1=>hades_dbg2_coarse_c_1); - hades_tdc_bundle_inst_SLICE_435I: hades_tdc_bundle_inst_SLICE_435 - port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_3, - B1=>hades_dbg2_coarse_c_2, A1=>hades_dbg2_coarse_c_0, - D0=>hades_dbg2_coarse_c_1, C0=>hades_dbg2_coarse_c_2, - A0=>hades_dbg2_coarse_c_0, - DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, - Q0=>hades_dbg2_coarse_c_2, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, - Q1=>hades_dbg2_coarse_c_3); - hades_tdc_bundle_inst_SLICE_436I: hades_tdc_bundle_inst_SLICE_436 - port map (D1=>hades_dbg2_coarse_c_5, C1=>hades_dbg2_coarse_c_4, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A1=>hades_dbg2_coarse_c_3, D0=>hades_dbg2_coarse_c_4, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_dbg2_coarse_c_3, - DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, - Q0=>hades_dbg2_coarse_c_4, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, - Q1=>hades_dbg2_coarse_c_5); - hades_tdc_bundle_inst_SLICE_437I: hades_tdc_bundle_inst_SLICE_437 - port map (D1=>hades_dbg2_coarse_c_7, C1=>hades_dbg2_coarse_c_6, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - A1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - D0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - C0=>hades_dbg2_coarse_c_6, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_dbg2_coarse_c_3, - DI1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, - Q0=>hades_dbg2_coarse_c_6, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, - Q1=>hades_dbg2_coarse_c_7); - hades_tdc_bundle_inst_SLICE_438I: hades_tdc_bundle_inst_SLICE_438 - port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_3, - B1=>hades_dbg2_coarse_c_0, A1=>hades_dbg2_coarse_c_2, - D0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, - C0=>hades_dbg2_coarse_c_8, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - A0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, - Q0=>hades_dbg2_coarse_c_8, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4); - hades_tdc_bundle_inst_SLICE_439I: hades_tdc_bundle_inst_SLICE_439 - port map (M1=>hades_tdc_bundle_inst_hades_raw_out_4, - M0=>hades_tdc_bundle_inst_hades_raw_out_3, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_4, - Q1=>hades_dbg2_out_c_5); - hades_tdc_bundle_inst_SLICE_440I: hades_tdc_bundle_inst_SLICE_440 - port map (M1=>hades_tdc_bundle_inst_hades_raw_out_6, - M0=>hades_tdc_bundle_inst_hades_raw_out_5, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_6, - Q1=>hades_dbg2_out_c_7); - hades_tdc_bundle_inst_SLICE_441I: hades_tdc_bundle_inst_SLICE_441 - port map (M1=>hades_tdc_bundle_inst_hades_raw_out_8, - M0=>hades_tdc_bundle_inst_hades_raw_out_7, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_8, - Q1=>hades_dbg2_out_c_9); - hades_tdc_bundle_inst_SLICE_442I: hades_tdc_bundle_inst_SLICE_442 - port map (M1=>hades_tdc_bundle_inst_hades_raw_out_10, - M0=>hades_tdc_bundle_inst_hades_raw_out_9, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_10, - Q1=>hades_dbg2_out_c_11); - hades_tdc_bundle_inst_SLICE_443I: hades_tdc_bundle_inst_SLICE_443 - port map (M0=>hades_tdc_bundle_inst_hades_raw_out_11, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3, Q0=>hades_dbg2_out_c_12); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_444 - port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa, - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, - D0=>hades_invalid_dl_c_3, C0=>hades_invalid_dl_c_2, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa - , CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxa, - Q0=>hades_discard_c, - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard_en); - hades_tdc_bundle_inst_SLICE_445I: hades_tdc_bundle_inst_SLICE_445 - port map (M1=>hades_dbg2_out_c_5, M0=>hades_dbg2_out_c_4, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_0, - Q1=>hades_drop_cmp_buf_c_1); - hades_tdc_bundle_inst_SLICE_446I: hades_tdc_bundle_inst_SLICE_446 - port map (M1=>hades_dbg2_out_c_7, M0=>hades_dbg2_out_c_6, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_2, - Q1=>hades_drop_cmp_buf_c_3); - hades_tdc_bundle_inst_SLICE_447I: hades_tdc_bundle_inst_SLICE_447 - port map (M1=>hades_dbg2_out_c_9, M0=>hades_dbg2_out_c_8, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_4, - Q1=>hades_drop_cmp_buf_c_5); - hades_tdc_bundle_inst_SLICE_448I: hades_tdc_bundle_inst_SLICE_448 - port map (M1=>hades_dbg2_out_c_11, M0=>hades_dbg2_out_c_10, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_6, - Q1=>hades_drop_cmp_buf_c_7); - hades_tdc_bundle_inst_SLICE_449I: hades_tdc_bundle_inst_SLICE_449 - port map (M0=>hades_dbg2_out_c_12, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_c_8); - hades_tdc_bundle_inst_SLICE_450I: hades_tdc_bundle_inst_SLICE_450 - port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_1, - M0=>hades_tdc_bundle_inst_hades_dbg2_coarse_c_i_0, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_0, - Q1=>hades_drop_cmp_buf_coarse_c_1); - hades_tdc_bundle_inst_SLICE_451I: hades_tdc_bundle_inst_SLICE_451 - port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_3, - M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_2, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_2, - Q1=>hades_drop_cmp_buf_coarse_c_3); - hades_tdc_bundle_inst_SLICE_452I: hades_tdc_bundle_inst_SLICE_452 - port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_5, - M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_4, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_4, - Q1=>hades_drop_cmp_buf_coarse_c_5); - hades_tdc_bundle_inst_SLICE_453I: hades_tdc_bundle_inst_SLICE_453 - port map (M1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_7, - M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_6, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_6, - Q1=>hades_drop_cmp_buf_coarse_c_7); - hades_tdc_bundle_inst_SLICE_454I: hades_tdc_bundle_inst_SLICE_454 - port map (M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_8, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, Q0=>hades_drop_cmp_buf_coarse_c_8); - hades_tdc_bundle_inst_SLICE_455I: hades_tdc_bundle_inst_SLICE_455 - port map (D1=>hades_dbg2_coarse_c_4, C1=>hades_dbg2_coarse_c_8, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, - A1=>hades_dbg2_coarse_c_5, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9, - M0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c4, - CE=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_9, - Q0=>hades_drop_cmp_buf_coarse_c_9); - hades_tdc_bundle_inst_SLICE_456I: hades_tdc_bundle_inst_SLICE_456 - port map (D0=>hades_hit_valid_c_1, C0=>hades_drop_cmp_buf_valid_c, - B0=>hades_tdc_bundle_inst_hit_valid25, - DI0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i, - CE=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_4_iv_i, - Q0=>hades_drop_cmp_buf_valid_c); - hades_tdc_bundle_inst_SLICE_457I: hades_tdc_bundle_inst_SLICE_457 - port map (D1=>hades_hit_valid_c_0, B1=>hades_buf_release_c, - D0=>hades_buf_release_c, C0=>hades_hit_valid_c_0, - B0=>hades_tdc_bundle_inst_hades_raw_out_valid, - A0=>hades_tdc_bundle_inst_hit_i_0, - DI0=>hades_tdc_bundle_inst_N_246_i, - M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, - CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_246_i, - Q0=>hades_hit_valid_c_0); - hades_tdc_bundle_inst_SLICE_458I: hades_tdc_bundle_inst_SLICE_458 - port map (D1=>hades_buf_release_c, C1=>hades_tdc_bundle_inst_hit_valid25, - B1=>hades_drop_cmp_buf_valid_c, D0=>hades_buf_release_c, - C0=>hades_tdc_bundle_inst_hit_valid25, - B0=>hades_drop_cmp_buf_valid_c, A0=>hades_tdc_bundle_inst_N_44, - DI0=>hades_tdc_bundle_inst_N_243_i, M0=>hades_hit_valid_c_1, - CE=>reset_dl_2, CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_N_243_i, Q0=>hades_hit_valid_c_1); - hades_tdc_bundle_inst_SLICE_459I: hades_tdc_bundle_inst_SLICE_459 - port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, - C1=>hades_buf_release_c, B1=>hades_tdc_bundle_inst_hit_i_0, - A1=>hades_hit_valid_c_2, D0=>hades_hit_valid_c_2, - C0=>hades_buf_release_c, DI0=>hades_tdc_bundle_inst_N_245_i, - M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, - CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_245_i, - Q0=>hades_hit_valid_c_2); - hades_tdc_bundle_inst_SLICE_460I: hades_tdc_bundle_inst_SLICE_460 - port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, - C1=>hades_hit_valid_c_3, B1=>hades_buf_release_c, - A1=>hades_tdc_bundle_inst_hit_i_0, D0=>hades_hit_valid_c_3, - C0=>hades_buf_release_c, DI0=>hades_tdc_bundle_inst_N_244_i, - M0=>hades_tdc_bundle_inst_hit_i_1, CE=>reset_dl_2, - CLK=>pll_clks_3, OFX0=>hades_tdc_bundle_inst_N_244_i, - Q0=>hades_hit_valid_c_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_461 - port map (M1=>hades_invalid_dl_c_1, M0=>hades_invalid_dl_c_0, - CLK=>pll_clks_3, Q0=>hades_invalid_dl_c_1, - Q1=>hades_invalid_dl_c_2); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_462 - port map (M0=>hades_invalid_dl_c_2, CLK=>pll_clks_3, - Q0=>hades_invalid_dl_c_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_463 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - A0=>hades_discard_c, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_39_i, - Q0=>hades_offset_valid_c); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_464 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1 - , - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_465 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_466 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_0, - Q1=>hades_tdc_bundle_inst_hades_raw_out_1); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_467 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_2, - Q1=>hades_tdc_bundle_inst_hades_raw_out_12); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_468 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_13, - Q1=>hades_tdc_bundle_inst_hades_raw_out_14); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_469 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_15, - Q1=>hades_tdc_bundle_inst_hades_raw_out_16); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_470 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_17, - Q1=>hades_tdc_bundle_inst_hades_raw_out_18); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_471 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_19, - Q1=>hades_tdc_bundle_inst_hades_raw_out_20); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_472 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_21, - Q1=>hades_tdc_bundle_inst_hades_raw_out_22); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_473 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_23); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_474 - port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_475 - port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_476 - port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_477 - port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_478 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_1, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_0, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_479 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_3, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_2, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_480 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_5, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_4, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_481 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_7, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_0_6, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_482 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_1, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_0, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_483 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_3, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_2, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_484 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_5, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_4, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_485 - port map ( - M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_6, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_486 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - , - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1 - , - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0 - , - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_0 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_487 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3 - , - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i - , - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_1 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_488 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290, - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - , - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0 - , - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6 - , - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal31_1_i_0 - , - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_out_internal_2 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_489 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_291, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0 - , - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i - , - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0 - , - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_i - , - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_490 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_499 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_500 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_1 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_501 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_2 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_502 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_3 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_503 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_4 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_504 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_5 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_505 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_6 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_506 - port map (M1=>hades_lvl1_c_i, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7 - , - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_in_clk_synced_7 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_507 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_0); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_508 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_1); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_509 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_2); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_510 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_511 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_4); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_512 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_5); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_513 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_6); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_SLICE_514 - port map ( - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_inst_out_buffered1_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_tdc_out_7); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_515 - port map (M1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_1, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_516 - port map (M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_518 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0, - M0=>hades_discard_c, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_0, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_519 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S0 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - B1=>hades_discard_c, A1=>reset_dl_2, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S0 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - B0=>hades_discard_c, A0=>reset_dl_2, - DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_1, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_3, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_520 - port map (D0=>hades_invalid_dl_c_2, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_3, - B0=>hades_invalid_dl_c_3, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_2, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , M0=>reset_dl_2, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2, - CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_521 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S0 - , C1=>reset_dl_2, - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - A1=>hades_discard_c, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_3_0_S1 - , C0=>reset_dl_2, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - A0=>hades_discard_c, - DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_4, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_5, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_522 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_s_7_0_S0 - , C1=>reset_dl_2, B1=>hades_discard_c, - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_5_0_S1 - , C0=>reset_dl_2, B0=>hades_discard_c, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - DI1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6, - LSR=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0_sqmuxadup - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_6, - Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_7, - Q1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_523 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_3, - Q1=>hades_tdc_bundle_inst_hades_raw_out_4); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_524 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_5, - Q1=>hades_tdc_bundle_inst_hades_raw_out_6); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_525 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_7, - Q1=>hades_tdc_bundle_inst_hades_raw_out_8); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_526 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_9, - Q1=>hades_tdc_bundle_inst_hades_raw_out_10); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_527 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_raw_out_11); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_528 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_249_i, - Q0=>hades_tdc_bundle_inst_hades_raw_out_valid); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_529 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_530 - port map (M1=>hades_dbg2_coarse_c_0, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_531 - port map (M1=>hades_dbg2_coarse_c_2, M0=>hades_dbg2_coarse_c_1, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_532 - port map (M1=>hades_dbg2_coarse_c_4, M0=>hades_dbg2_coarse_c_3, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_533 - port map (M1=>hades_dbg2_coarse_c_6, M0=>hades_dbg2_coarse_c_5, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_8 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_9 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_534 - port map (M1=>hades_dbg2_coarse_c_8, M0=>hades_dbg2_coarse_c_7, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_10 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_11 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_535 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_i - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4 - , CE=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready_4 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_536 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_537 - port map (M1=>hades_dbg2_coarse_c_0, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2 - , - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_538 - port map (M1=>hades_dbg2_coarse_c_2, M0=>hades_dbg2_coarse_c_1, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_539 - port map (M1=>hades_dbg2_coarse_c_4, M0=>hades_dbg2_coarse_c_3, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_540 - port map (M1=>hades_dbg2_coarse_c_6, M0=>hades_dbg2_coarse_c_5, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_8 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_9 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_541 - port map (M1=>hades_dbg2_coarse_c_8, M0=>hades_dbg2_coarse_c_7, - CE=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_10 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_11 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_542 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_i - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_ready - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7, - CE=>reset_dl_2, CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_7, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_543 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_544 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_545 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_546 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_547 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_548 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_549 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_550 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_0_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_551 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_552 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_553 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_554 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_555 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_0 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_556 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_0 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_557 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal31_1_i_0_0 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_558 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_269 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_i - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_559 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_560 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_561 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_562 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_563 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_564 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_565 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_566 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_0_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_567 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_568 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_3 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_569 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_5 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_4 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_570 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_6 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_571 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3 - , - DI1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_1 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_572 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_N_5 - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal31_1_i_0_o5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_573 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5 - , - DI0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0 - , - LSR=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i - , CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_i - , - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_574 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_575 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_out_internal_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_576 - port map ( - M1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_1 - , - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_0 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_577 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_out_internal_2 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_out_neg_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_588 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_589 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_590 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_591 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_592 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_4 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_593 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_594 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_6 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_595 - port map (M1=>hades_trig_c_i, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_in_clk_synced_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_604 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_605 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_606 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_607 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_608 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_4 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_609 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_610 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_6 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_611 - port map (M1=>hades_trig_c, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7 - , - Q1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_in_clk_synced_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_612 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_613 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_614 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_615 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_616 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_4 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_617 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_618 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_6 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_SLICE_619 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_inst_out_buffered1_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_7 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_620 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_0 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_621 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_1 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_622 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_2 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_2 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_623 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_3 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_624 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_4 - , CLK=>pll_clks_0, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_4 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_625 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_5 - , CLK=>pll_clks_1, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_5 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_626 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_6 - , CLK=>pll_clks_2, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_6 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_SLICE_627 - port map ( - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_neg_inst_out_buffered1_7 - , CLK=>pll_clks_3, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_tdc_out_neg_7 - ); - hades_tdc_bundle_inst_SLICE_628I: hades_tdc_bundle_inst_SLICE_628 - port map (D1=>hades_tdc_bundle_inst_hit_i_0, - C1=>hades_tdc_bundle_inst_hades_raw_out_valid, - A1=>hades_tdc_bundle_inst_hit_i_1, - C0=>hades_tdc_bundle_inst_hades_raw_out_valid, - A0=>hades_tdc_bundle_inst_hit_i_0, - DI1=>hades_tdc_bundle_inst_SUM1_0_0, - DI0=>hades_tdc_bundle_inst_N_59_i, LSR=>reset_dl_2, - CLK=>pll_clks_3, F0=>hades_tdc_bundle_inst_N_59_i, - Q0=>hades_tdc_bundle_inst_hit_i_0, - F1=>hades_tdc_bundle_inst_SUM1_0_0, - Q1=>hades_tdc_bundle_inst_hit_i_1); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_629 - port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3 - , A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - DI0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - CLK=>pll_clks_3, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_end5, - Q0=>hades_window_end_c); - trb_adapter_inst_SLICE_631I: trb_adapter_inst_SLICE_631 - port map (M1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, - M0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0, - CLK=>rd_clk_c, - Q0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, - Q1=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2); - trb_adapter_inst_SLICE_632I: trb_adapter_inst_SLICE_632 - port map (M0=>fifo_rden_c, CLK=>rd_clk_c, - Q0=>trb_adapter_inst_buf_rden_prev); - trb_adapter_inst_SLICE_633I: trb_adapter_inst_SLICE_633 - port map (M0=>finished_c, CLK=>rd_clk_c, - Q0=>trb_adapter_inst_finished_prev); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_634 - port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, - C1=>hades_discard_c, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - A0=>hades_discard_c, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_635 - port map (D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3 - , M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - OFX0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1 - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_636 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_637 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_638 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_639 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - M0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - OFX0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_640 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_641 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_642 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_643 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - M0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - OFX0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_644 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_645 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r5); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_646 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w2); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_647 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - M0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - OFX0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w5); - - fifo_colector_inst_fifo40_inst_SLICE_648I: fifo_colector_inst_fifo40_inst_SLICE_648 - port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - C1=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - A1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - M0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, - OFX0=>fifo_colector_inst_fifo40_inst_rcount_w2); - - fifo_colector_inst_fifo40_inst_SLICE_649I: fifo_colector_inst_fifo40_inst_SLICE_649 - port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - C1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - A1=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - M0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, - OFX0=>fifo_colector_inst_fifo40_inst_rcount_w5); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_650 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - C1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - B1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - A1=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - B0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - A0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - M0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - OFX0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - ); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_651 - port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - C1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - B1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - A1=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - C0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - A0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - M0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - OFX0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - ); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_652 - port map (D1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - C1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - B1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - A1=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - D0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_6, - C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_3, - B0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_4, - A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_5, - M0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_2, - OFX0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_un1_out_internal35_1_0_0 - ); - hades_tdc_bundle_inst_SLICE_653I: hades_tdc_bundle_inst_SLICE_653 - port map (D0=>ANB3, C0=>ANB0, B0=>ANB2, A0=>ANB1, M0=>reset_dl_2, - OFX0=>N_248_i); - hades_tdc_bundle_inst_SLICE_654I: hades_tdc_bundle_inst_SLICE_654 - port map (D1=>hades_tdc_bundle_inst_N_45, C1=>ANB1, B1=>ANB2, A1=>ANB3, - D0=>hades_tdc_bundle_inst_N_66, C0=>hades_hit_valid_c_0, - B0=>ANB2, A0=>hades_tdc_bundle_inst_N_80, - F0=>hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0, - F1=>hades_tdc_bundle_inst_N_66); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_655 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_656 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_657 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_658 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_659 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_660 - port map ( - D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_661 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_662 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_663 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_664 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_665 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_666 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_667 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r20 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r0); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_668 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r21 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r22 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_1 - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_669 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r26 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r27 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r7, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r4); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_670 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w20 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w0); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_671 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w21 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w22 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_1 - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w1); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_672 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w26 - , - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w27 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w7, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w4); - - fifo_colector_inst_fifo40_inst_SLICE_673I: fifo_colector_inst_fifo40_inst_SLICE_673 - port map (D1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - C1=>fifo_colector_inst_fifo40_inst_w_gcount_r20, - B1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, - A1=>fifo_colector_inst_fifo40_inst_w_gcount_r21, - D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, - C0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, - B0=>fifo_colector_inst_fifo40_inst_w_gcount_r27, - A0=>fifo_colector_inst_fifo40_inst_w_gcount_r26, - F0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - F1=>fifo_colector_inst_fifo40_inst_wcount_r0); - - fifo_colector_inst_fifo40_inst_SLICE_674I: fifo_colector_inst_fifo40_inst_SLICE_674 - port map (D1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - C1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, - B1=>fifo_colector_inst_fifo40_inst_w_gcount_r21, - D0=>fifo_colector_inst_fifo40_inst_w_gcount_r22, - C0=>fifo_colector_inst_fifo40_inst_w_gcount_r25, - B0=>fifo_colector_inst_fifo40_inst_w_gcount_r23, - A0=>fifo_colector_inst_fifo40_inst_w_gcount_r24, - F0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, - F1=>fifo_colector_inst_fifo40_inst_wcount_r1); - - fifo_colector_inst_fifo40_inst_SLICE_675I: fifo_colector_inst_fifo40_inst_SLICE_675 - port map (D1=>fifo_colector_inst_fifo40_inst_wcount_r8, - C1=>fifo_colector_inst_fifo40_inst_w_gcount_r27, - B1=>fifo_colector_inst_fifo40_inst_w_gcount_r26, - A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, - D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, - B0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, - F0=>fifo_colector_inst_fifo40_inst_wcount_r8, - F1=>fifo_colector_inst_fifo40_inst_wcount_r5); - - fifo_colector_inst_fifo40_inst_SLICE_676I: fifo_colector_inst_fifo40_inst_SLICE_676 - port map (D1=>fifo_colector_inst_fifo40_inst_wcount_r7, - C1=>fifo_colector_inst_fifo40_inst_w_gcount_r26, - B1=>fifo_colector_inst_fifo40_inst_w_gcount_r24, - A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, - D0=>fifo_colector_inst_fifo40_inst_w_gcount_r28, - B0=>fifo_colector_inst_fifo40_inst_w_gcount_r27, - A0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, - F0=>fifo_colector_inst_fifo40_inst_wcount_r7, - F1=>fifo_colector_inst_fifo40_inst_wcount_r4); - - fifo_colector_inst_fifo40_inst_SLICE_677I: fifo_colector_inst_fifo40_inst_SLICE_677 - port map (D1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, - C1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w20, - A1=>fifo_colector_inst_fifo40_inst_r_gcount_w21, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - F0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, - F1=>fifo_colector_inst_fifo40_inst_rcount_w0); - - fifo_colector_inst_fifo40_inst_SLICE_678I: fifo_colector_inst_fifo40_inst_SLICE_678 - port map (D1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, - C1=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w21, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w23, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, - B0=>fifo_colector_inst_fifo40_inst_r_gcount_w22, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, - F0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_1, - F1=>fifo_colector_inst_fifo40_inst_rcount_w1); - - fifo_colector_inst_fifo40_inst_SLICE_679I: fifo_colector_inst_fifo40_inst_SLICE_679 - port map (D1=>fifo_colector_inst_fifo40_inst_rcount_w7, - C1=>fifo_colector_inst_fifo40_inst_r_gcount_w24, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w26, - A1=>fifo_colector_inst_fifo40_inst_r_gcount_w25, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w27, - B0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - F0=>fifo_colector_inst_fifo40_inst_rcount_w7, - F1=>fifo_colector_inst_fifo40_inst_rcount_w4); - fifo_colector_inst_SLICE_680I: fifo_colector_inst_SLICE_680 - port map (D1=>fifo_colector_inst_iterator_0, C1=>fifo_empty1_c, - A1=>fifo_empty_1, D0=>fifo_empty_2, - B0=>fifo_colector_inst_iterator_1, - A0=>fifo_colector_inst_in_empty_pmux_0, - F0=>fifo_colector_inst_in_empty_pmux, - F1=>fifo_colector_inst_in_empty_pmux_0); - hades_tdc_bundle_inst_SLICE_681I: hades_tdc_bundle_inst_SLICE_681 - port map (D1=>hades_dbg2_coarse_c_1, C1=>hades_dbg2_coarse_c_2, - B1=>hades_dbg2_coarse_c_0, - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_7 - , C0=>hades_dbg2_coarse_c_4, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_dbg2_coarse_c_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_14 - , F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_682 - port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3 - , B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - A0=>hades_discard_c, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_c - , F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_N_97); - hades_tdc_bundle_inst_SLICE_683I: hades_tdc_bundle_inst_SLICE_683 - port map (D1=>ANB0, C1=>ANB1, A1=>ANB3, - D0=>hades_tdc_bundle_inst_hit_valid_pmux_iv_0_0, - B0=>hades_tdc_bundle_inst_N_90, A0=>hades_hit_valid_c_3, - F0=>hades_tdc_bundle_inst_buf_out12, - F1=>hades_tdc_bundle_inst_N_90); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_684 - port map (D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_2, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_5, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_7, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_discard4_0_a2_0_3 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_685 - port map (C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - ); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_686 - port map (D1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_687 - port map (D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - ); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_688 - port map (C1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_689 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_9, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_9, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_set - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_empty_cmp_clr - ); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_690 - port map (C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_9, - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_9, - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_set - , - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_full_cmp_clr - ); - - fifo_colector_inst_fifo40_inst_SLICE_691I: fifo_colector_inst_fifo40_inst_SLICE_691 - port map (C1=>fifo_colector_inst_fifo40_inst_wcount_9, - B1=>fifo_colector_inst_fifo40_inst_wptr_9, - A1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - C0=>fifo_colector_inst_fifo40_inst_wcount_9, - B0=>fifo_colector_inst_fifo40_inst_wptr_9, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - F0=>fifo_colector_inst_fifo40_inst_full_cmp_clr, - F1=>fifo_colector_inst_fifo40_inst_full_cmp_set); - - fifo_colector_inst_fifo40_inst_SLICE_692I: fifo_colector_inst_fifo40_inst_SLICE_692 - port map (D1=>fifo_colector_inst_fifo40_inst_rcount_9, - C1=>fifo_colector_inst_fifo40_inst_rptr_9, - A1=>fifo_colector_inst_fifo40_inst_w_gcount_r29, - D0=>fifo_colector_inst_fifo40_inst_rcount_9, - C0=>fifo_colector_inst_fifo40_inst_rptr_9, - A0=>fifo_colector_inst_fifo40_inst_w_gcount_r29, - F0=>fifo_colector_inst_fifo40_inst_empty_cmp_set, - F1=>fifo_colector_inst_fifo40_inst_empty_cmp_clr); - hades_tdc_bundle_inst_SLICE_693I: hades_tdc_bundle_inst_SLICE_693 - port map (D1=>hades_tdc_bundle_inst_hades_raw_out_valid, - C1=>hades_tdc_bundle_inst_hit_i_1, - B1=>hades_tdc_bundle_inst_hit_i_0, - D0=>hades_tdc_bundle_inst_hades_raw_out_valid, - C0=>hades_tdc_bundle_inst_hit_i_1, - B0=>hades_tdc_bundle_inst_hit_i_0, A0=>reset_dl_2, - F0=>un1_hit_i_2_0_a2, F1=>hades_tdc_bundle_inst_N_44); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_694 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_o5 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m15_i_1_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_695 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m15_i_3 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_696 - port map ( - D1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - C1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0 - , - B1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1 - , - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_2 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_1 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_0 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_N_268 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_m11_i_1_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_SLICE_697 - port map (D1=>hades_dbg2_coarse_c_0, C1=>hades_dbg2_coarse_c_2, - B1=>hades_dbg2_coarse_c_1, - A1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_5 - , D0=>hades_dbg2_coarse_c_0, - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_5 - , B0=>hades_dbg2_coarse_c_1, A0=>hades_dbg2_coarse_c_2, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_19 - , - F1=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_buf_positive_0_N_19 - ); - hades_tdc_bundle_inst_SLICE_698I: hades_tdc_bundle_inst_SLICE_698 - port map (D1=>hades_dbg2_coarse_c_4, - B1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A1=>hades_dbg2_coarse_c_3, D0=>hades_dbg2_coarse_c_4, - C0=>hades_dbg2_coarse_c_3, - B0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c3, - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_negative_7 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_un1_coarse_1_0_N_14 - , F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_c5); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_699 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m15_i_3 - , - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_700 - port map ( - D1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1 - , - C1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - B1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - A1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0 - , - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_1 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_2 - , - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_0 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_N_290, - F1=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_m11_i_1_0 - ); - hades_tdc_bundle_inst_SLICE_701I: hades_tdc_bundle_inst_SLICE_701 - port map (D1=>hades_dbg2_coarse_c_4, B1=>hades_dbg2_coarse_c_5, - C0=>hades_dbg2_coarse_c_6, A0=>hades_dbg2_coarse_c_7, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_13_0, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_coarse_2_ac0_9_0); - - fifo_colector_inst_fifo40_inst_SLICE_702I: fifo_colector_inst_fifo40_inst_SLICE_702 - port map (D1=>fifo_colector_inst_fifo40_inst_w_gcount_r24, - C1=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - B1=>fifo_colector_inst_fifo40_inst_w_gcount_r23, - A1=>fifo_colector_inst_fifo40_inst_w_gcount_r25, - D0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_0, - C0=>fifo_colector_inst_fifo40_inst_w_g2b_xor_cluster_1, - F0=>fifo_colector_inst_fifo40_inst_wcount_r2, - F1=>fifo_colector_inst_fifo40_inst_wcount_r3); - - fifo_colector_inst_fifo40_inst_SLICE_703I: fifo_colector_inst_fifo40_inst_SLICE_703 - port map (D1=>fifo_colector_inst_fifo40_inst_r_gcount_w28, - B1=>fifo_colector_inst_fifo40_inst_r_gcount_w29, - D0=>fifo_colector_inst_fifo40_inst_r_gcount_w23, - C0=>fifo_colector_inst_fifo40_inst_r_gcount_w24, - B0=>fifo_colector_inst_fifo40_inst_r_g2b_xor_cluster_0, - A0=>fifo_colector_inst_fifo40_inst_r_gcount_w25, - F0=>fifo_colector_inst_fifo40_inst_rcount_w3, - F1=>fifo_colector_inst_fifo40_inst_rcount_w8); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_704 - port map ( - C1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_705 - port map ( - D1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - B0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - A0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - F1=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_706 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - A1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_707 - port map ( - D1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - B0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - A0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - F1=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_708 - port map ( - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w28 - , - A1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_g2b_xor_cluster_0 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w24 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w23 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_r_gcount_w25 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w3, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rcount_w8); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_709 - port map ( - C1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r28 - , - B1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r29 - , - D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_g2b_xor_cluster_0 - , - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r23 - , - B0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r25 - , - A0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_w_gcount_r24 - , - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r3, - F1=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wcount_r8); - hades_tdc_bundle_inst_SLICE_710I: hades_tdc_bundle_inst_SLICE_710 - port map (D1=>hades_drop_cmp_buf_valid_c, - C1=>hades_tdc_bundle_inst_hit_valid25, D0=>ANB0, - C0=>hades_hit_valid_c_1, B0=>hades_hit_valid_c_2, - F0=>hades_tdc_bundle_inst_N_45, - F1=>hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa); - - genblk1_2_tdc_channel_fifo_out_inst_SLICE_711I: genblk1_2_tdc_channel_fifo_out_inst_SLICE_711 - port map (D0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_wren, - C0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, - M0=>genblk1_2_tdc_channel_fifo_out_inst_decoder_valid, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - Q0=>genblk1_2_tdc_channel_fifo_out_inst_fifo_wren); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_712 - port map (D0=>fifo_read_2, A0=>fifo_empty_2, - F0=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i); - - genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713I: genblk1_2_tdc_channel_fifo_out_inst_dec_inst_SLICE_713 - port map (D0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, - C0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - F0=>genblk1_2_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - ); - - genblk1_1_tdc_channel_fifo_out_inst_SLICE_714I: genblk1_1_tdc_channel_fifo_out_inst_SLICE_714 - port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_wren, - C0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, - M0=>genblk1_1_tdc_channel_fifo_out_inst_decoder_valid, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - Q0=>genblk1_1_tdc_channel_fifo_out_inst_fifo_wren); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_715 - port map (D0=>fifo_read_1, A0=>fifo_empty_1, - F0=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i); - - genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716I: genblk1_1_tdc_channel_fifo_out_inst_dec_inst_SLICE_716 - port map (D0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, - B0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - F0=>genblk1_1_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - ); - - genblk1_0_tdc_channel_fifo_out_inst_SLICE_717I: genblk1_0_tdc_channel_fifo_out_inst_SLICE_717 - port map (D0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_wren, - C0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_Full, - M0=>genblk1_0_tdc_channel_fifo_out_inst_decoder_valid, - LSR=>reset_dl_2, CLK=>pll_clks_3, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - Q0=>genblk1_0_tdc_channel_fifo_out_inst_fifo_wren); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_SLICE_718 - port map (B0=>fifo_read_0, A0=>fifo_empty1_c, - F0=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i); - - genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719I: genblk1_0_tdc_channel_fifo_out_inst_dec_inst_SLICE_719 - port map (C0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced_7, - A0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_dl_1_7, - F0=>genblk1_0_tdc_channel_fifo_out_inst_dec_inst_in_synced7_rising_i - ); - - fifo_colector_inst_fifo40_inst_SLICE_720I: fifo_colector_inst_fifo40_inst_SLICE_720 - port map (D0=>last_buf_empty_c, C0=>fifo_rden_c, - F0=>fifo_colector_inst_fifo40_inst_rden_i); - - fifo_colector_inst_fifo40_inst_SLICE_721I: fifo_colector_inst_fifo40_inst_SLICE_721 - port map (C0=>fifo_colector_inst_fifo40_inst_Full, - B0=>fifo_colector_inst_buffer_wr_enable, - F0=>fifo_colector_inst_fifo40_inst_wren_i); - fifo_colector_inst_SLICE_722I: fifo_colector_inst_SLICE_722 - port map (D0=>fifo_colector_inst_iterator_1, A0=>fifo_empty_2, - F0=>fifo_colector_inst_iterator_RNI7U5I_1); - trb_adapter_inst_SLICE_723I: trb_adapter_inst_SLICE_723 - port map (D0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_2, - B0=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_1, - F0=>LVL1_TRG_DATA_VALI_IN_rising_c); - trb_adapter_inst_SLICE_724I: trb_adapter_inst_SLICE_724 - port map (B0=>trb_adapter_inst_finished_prev, A0=>finished_c, - M0=>trb_adapter_inst_buf_rden_prev, LSR=>fifo_rden_c, - CLK=>rd_clk_c, F0=>release_out_c, Q0=>finished_c); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_725 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_buf_positive_ready - , A0=>reset_dl_2, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_valid_internal - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_11_i, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid_neg - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_726 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_7 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_dl_1_7 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced7_rising_i - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_727 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_6 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_un1_out_internal35_1_0_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_728 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_0 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_4 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_1 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_0 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_SLICE_729 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_5 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_3 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_in_synced_2 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_neg_inst_m11_i_m3 - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_730 - port map ( - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_dl_1_7 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_7 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced7_rising_i - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_731 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid - , C0=>reset_dl_2, - M0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_valid_internal - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_N_251_i, - Q0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_decoder_valid - ); - - hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732I: hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_SLICE_732 - port map ( - D0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_6 - , - C0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_3 - , - B0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_5 - , - A0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_in_synced_4 - , - F0=>hades_tdc_bundle_inst_hades_tdc_channel_raw_out_inst_dec_inst_un1_out_internal35_1_0_0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_733 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, - B0=>reset_dl_2, A0=>hades_discard_c, F0=>valid_fast_RNI999V); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_734 - port map ( - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_7 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_dl_1_7, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced7_rising_i - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_735 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_3 - , - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_6 - , - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_5 - , - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_in_synced_4 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_un1_out_internal35_1_0_0 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_SLICE_736 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_4_0, - A0=>reset_dl_2, - M0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_dec_inst_valid_internal - , CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , Q0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_valid_fast); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_737 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2_0 - , B0=>hades_discard_c, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_1 - , - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_reset_0_a2_2 - ); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_738 - port map ( - D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_un1_window_8_cry_1_0_S1 - , C0=>reset_dl_2, B0=>hades_discard_c, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_decoder_valid, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_6_2); - - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739I: hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_SLICE_739 - port map (D0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_0, - C0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_3, - B0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_4, - A0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_window_1, - F0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_G_25_0_a3_5_0); - SLICE_740I: SLICE_740 - port map (D0=>reset_dl_2, C0=>hades_hit_valid_c_1, M0=>reset_dl_1, - CLK=>pll_clks_3, - F0=>hades_tdc_bundle_inst_drop_cmp_buf_0_sqmuxa, - Q0=>reset_dl_2); - hades_tdc_bundle_inst_SLICE_741I: hades_tdc_bundle_inst_SLICE_741 - port map (C0=>hades_window_end_c, A0=>hades_discard_c, - F0=>hades_tdc_bundle_inst_hit_out_i_6_i_a2_0_0); - pll0inst_SLICE_742I: pll0inst_SLICE_742 - port map (F0=>pll0inst_GND); - SLICE_743I: SLICE_743 - port map (D0=>hades_lvl1_c, F0=>hades_lvl1_c_i); - SLICE_744I: SLICE_744 - port map (D0=>trig_c_0, F0=>trig_c_i_0); - SLICE_745I: SLICE_745 - port map (D0=>trig_c_1, F0=>trig_c_i_1); - SLICE_746I: SLICE_746 - port map (D0=>trig_c_2, F0=>trig_c_i_2); - SLICE_747I: SLICE_747 - port map (A0=>hades_trig_c, F0=>hades_trig_c_i); - hades_raw_valid_vect_0_I: hades_raw_valid_vect_0_B - port map (hadesrawvalidvect0=>hades_raw_valid_vect(0)); - fifo_data_out_0_I: fifo_data_out_0_B - port map (PADDO=>FEE_DATA_OUT_c_0, fifodataout0=>fifo_data_out(0)); - clkI: clkB - port map (PADDI=>clk_c, clkS=>clk); - hades_drop_cmp_buf_validI: hades_drop_cmp_buf_validB - port map (PADDO=>hades_drop_cmp_buf_valid_c, - hadesdropcmpbufvalid=>hades_drop_cmp_buf_valid); - hades_drop_cmp_buf_coarse_11_I: hades_drop_cmp_buf_coarse_11_B - port map (hadesdropcmpbufcoarse11=>hades_drop_cmp_buf_coarse(11)); - hades_drop_cmp_buf_coarse_10_I: hades_drop_cmp_buf_coarse_10_B - port map (hadesdropcmpbufcoarse10=>hades_drop_cmp_buf_coarse(10)); - hades_drop_cmp_buf_coarse_9_I: hades_drop_cmp_buf_coarse_9_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_9, - hadesdropcmpbufcoarse9=>hades_drop_cmp_buf_coarse(9)); - hades_drop_cmp_buf_coarse_8_I: hades_drop_cmp_buf_coarse_8_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_8, - hadesdropcmpbufcoarse8=>hades_drop_cmp_buf_coarse(8)); - hades_drop_cmp_buf_coarse_7_I: hades_drop_cmp_buf_coarse_7_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_7, - hadesdropcmpbufcoarse7=>hades_drop_cmp_buf_coarse(7)); - hades_drop_cmp_buf_coarse_6_I: hades_drop_cmp_buf_coarse_6_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_6, - hadesdropcmpbufcoarse6=>hades_drop_cmp_buf_coarse(6)); - hades_drop_cmp_buf_coarse_5_I: hades_drop_cmp_buf_coarse_5_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_5, - hadesdropcmpbufcoarse5=>hades_drop_cmp_buf_coarse(5)); - hades_drop_cmp_buf_coarse_4_I: hades_drop_cmp_buf_coarse_4_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_4, - hadesdropcmpbufcoarse4=>hades_drop_cmp_buf_coarse(4)); - hades_drop_cmp_buf_coarse_3_I: hades_drop_cmp_buf_coarse_3_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_3, - hadesdropcmpbufcoarse3=>hades_drop_cmp_buf_coarse(3)); - hades_drop_cmp_buf_coarse_2_I: hades_drop_cmp_buf_coarse_2_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_2, - hadesdropcmpbufcoarse2=>hades_drop_cmp_buf_coarse(2)); - hades_drop_cmp_buf_coarse_1_I: hades_drop_cmp_buf_coarse_1_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_1, - hadesdropcmpbufcoarse1=>hades_drop_cmp_buf_coarse(1)); - hades_drop_cmp_buf_coarse_0_I: hades_drop_cmp_buf_coarse_0_B - port map (PADDO=>hades_drop_cmp_buf_coarse_c_0, - hadesdropcmpbufcoarse0=>hades_drop_cmp_buf_coarse(0)); - hades_drop_cmp_buf_11_I: hades_drop_cmp_buf_11_B - port map (hadesdropcmpbuf11=>hades_drop_cmp_buf(11)); - hades_drop_cmp_buf_10_I: hades_drop_cmp_buf_10_B - port map (hadesdropcmpbuf10=>hades_drop_cmp_buf(10)); - hades_drop_cmp_buf_9_I: hades_drop_cmp_buf_9_B - port map (hadesdropcmpbuf9=>hades_drop_cmp_buf(9)); - hades_drop_cmp_buf_8_I: hades_drop_cmp_buf_8_B - port map (PADDO=>hades_drop_cmp_buf_c_8, - hadesdropcmpbuf8=>hades_drop_cmp_buf(8)); - hades_drop_cmp_buf_7_I: hades_drop_cmp_buf_7_B - port map (PADDO=>hades_drop_cmp_buf_c_7, - hadesdropcmpbuf7=>hades_drop_cmp_buf(7)); - hades_drop_cmp_buf_6_I: hades_drop_cmp_buf_6_B - port map (PADDO=>hades_drop_cmp_buf_c_6, - hadesdropcmpbuf6=>hades_drop_cmp_buf(6)); - hades_drop_cmp_buf_5_I: hades_drop_cmp_buf_5_B - port map (PADDO=>hades_drop_cmp_buf_c_5, - hadesdropcmpbuf5=>hades_drop_cmp_buf(5)); - hades_drop_cmp_buf_4_I: hades_drop_cmp_buf_4_B - port map (PADDO=>hades_drop_cmp_buf_c_4, - hadesdropcmpbuf4=>hades_drop_cmp_buf(4)); - hades_drop_cmp_buf_3_I: hades_drop_cmp_buf_3_B - port map (PADDO=>hades_drop_cmp_buf_c_3, - hadesdropcmpbuf3=>hades_drop_cmp_buf(3)); - hades_drop_cmp_buf_2_I: hades_drop_cmp_buf_2_B - port map (PADDO=>hades_drop_cmp_buf_c_2, - hadesdropcmpbuf2=>hades_drop_cmp_buf(2)); - hades_drop_cmp_buf_1_I: hades_drop_cmp_buf_1_B - port map (PADDO=>hades_drop_cmp_buf_c_1, - hadesdropcmpbuf1=>hades_drop_cmp_buf(1)); - hades_drop_cmp_buf_0_I: hades_drop_cmp_buf_0_B - port map (PADDO=>hades_drop_cmp_buf_c_0, - hadesdropcmpbuf0=>hades_drop_cmp_buf(0)); - hades_dbg2_coarse_8_I: hades_dbg2_coarse_8_B - port map (PADDO=>hades_dbg2_coarse_c_8, - hadesdbg2coarse8=>hades_dbg2_coarse(8)); - hades_dbg2_coarse_7_I: hades_dbg2_coarse_7_B - port map (PADDO=>hades_dbg2_coarse_c_7, - hadesdbg2coarse7=>hades_dbg2_coarse(7)); - hades_dbg2_coarse_6_I: hades_dbg2_coarse_6_B - port map (PADDO=>hades_dbg2_coarse_c_6, - hadesdbg2coarse6=>hades_dbg2_coarse(6)); - hades_dbg2_coarse_5_I: hades_dbg2_coarse_5_B - port map (PADDO=>hades_dbg2_coarse_c_5, - hadesdbg2coarse5=>hades_dbg2_coarse(5)); - hades_dbg2_coarse_4_I: hades_dbg2_coarse_4_B - port map (PADDO=>hades_dbg2_coarse_c_4, - hadesdbg2coarse4=>hades_dbg2_coarse(4)); - hades_dbg2_coarse_3_I: hades_dbg2_coarse_3_B - port map (PADDO=>hades_dbg2_coarse_c_3, - hadesdbg2coarse3=>hades_dbg2_coarse(3)); - hades_dbg2_coarse_2_I: hades_dbg2_coarse_2_B - port map (PADDO=>hades_dbg2_coarse_c_2, - hadesdbg2coarse2=>hades_dbg2_coarse(2)); - hades_dbg2_coarse_1_I: hades_dbg2_coarse_1_B - port map (PADDO=>hades_dbg2_coarse_c_1, - hadesdbg2coarse1=>hades_dbg2_coarse(1)); - hades_dbg2_coarse_0_I: hades_dbg2_coarse_0_B - port map (PADDO=>hades_dbg2_coarse_c_0, - hadesdbg2coarse0=>hades_dbg2_coarse(0)); - hades_dbg2_out_31_I: hades_dbg2_out_31_B - port map (hadesdbg2out31=>hades_dbg2_out(31)); - hades_dbg2_out_30_I: hades_dbg2_out_30_B - port map (hadesdbg2out30=>hades_dbg2_out(30)); - hades_dbg2_out_29_I: hades_dbg2_out_29_B - port map (hadesdbg2out29=>hades_dbg2_out(29)); - hades_dbg2_out_28_I: hades_dbg2_out_28_B - port map (IOLDO=>hades_dbg2_out_c_28, hadesdbg2out28=>hades_dbg2_out(28)); - hades_dbg2_out_28_MGIOLI: hades_dbg2_out_28_MGIOL - port map (IOLDO=>hades_dbg2_out_c_28, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_23, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_27_I: hades_dbg2_out_27_B - port map (IOLDO=>hades_dbg2_out_c_27, hadesdbg2out27=>hades_dbg2_out(27)); - hades_dbg2_out_27_MGIOLI: hades_dbg2_out_27_MGIOL - port map (IOLDO=>hades_dbg2_out_c_27, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_22, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_26_I: hades_dbg2_out_26_B - port map (IOLDO=>hades_dbg2_out_c_26, hadesdbg2out26=>hades_dbg2_out(26)); - hades_dbg2_out_26_MGIOLI: hades_dbg2_out_26_MGIOL - port map (IOLDO=>hades_dbg2_out_c_26, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_21, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_25_I: hades_dbg2_out_25_B - port map (IOLDO=>hades_dbg2_out_c_25, hadesdbg2out25=>hades_dbg2_out(25)); - hades_dbg2_out_25_MGIOLI: hades_dbg2_out_25_MGIOL - port map (IOLDO=>hades_dbg2_out_c_25, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_20, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_24_I: hades_dbg2_out_24_B - port map (IOLDO=>hades_dbg2_out_c_24, hadesdbg2out24=>hades_dbg2_out(24)); - hades_dbg2_out_24_MGIOLI: hades_dbg2_out_24_MGIOL - port map (IOLDO=>hades_dbg2_out_c_24, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_19, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_23_I: hades_dbg2_out_23_B - port map (IOLDO=>hades_dbg2_out_c_23, hadesdbg2out23=>hades_dbg2_out(23)); - hades_dbg2_out_23_MGIOLI: hades_dbg2_out_23_MGIOL - port map (IOLDO=>hades_dbg2_out_c_23, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_18, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_22_I: hades_dbg2_out_22_B - port map (IOLDO=>hades_dbg2_out_c_22, hadesdbg2out22=>hades_dbg2_out(22)); - hades_dbg2_out_22_MGIOLI: hades_dbg2_out_22_MGIOL - port map (IOLDO=>hades_dbg2_out_c_22, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_17, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_21_I: hades_dbg2_out_21_B - port map (IOLDO=>hades_dbg2_out_c_21, hadesdbg2out21=>hades_dbg2_out(21)); - hades_dbg2_out_21_MGIOLI: hades_dbg2_out_21_MGIOL - port map (IOLDO=>hades_dbg2_out_c_21, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_16, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_20_I: hades_dbg2_out_20_B - port map (IOLDO=>hades_dbg2_out_c_20, hadesdbg2out20=>hades_dbg2_out(20)); - hades_dbg2_out_20_MGIOLI: hades_dbg2_out_20_MGIOL - port map (IOLDO=>hades_dbg2_out_c_20, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_15, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_19_I: hades_dbg2_out_19_B - port map (hadesdbg2out19=>hades_dbg2_out(19)); - hades_dbg2_out_18_I: hades_dbg2_out_18_B - port map (IOLDO=>hades_dbg2_out_c_18, hadesdbg2out18=>hades_dbg2_out(18)); - hades_dbg2_out_18_MGIOLI: hades_dbg2_out_18_MGIOL - port map (IOLDO=>hades_dbg2_out_c_18, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_14, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_17_I: hades_dbg2_out_17_B - port map (IOLDO=>hades_dbg2_out_c_17, hadesdbg2out17=>hades_dbg2_out(17)); - hades_dbg2_out_17_MGIOLI: hades_dbg2_out_17_MGIOL - port map (IOLDO=>hades_dbg2_out_c_17, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_13, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_16_I: hades_dbg2_out_16_B - port map (IOLDO=>hades_dbg2_out_c_16, hadesdbg2out16=>hades_dbg2_out(16)); - hades_dbg2_out_16_MGIOLI: hades_dbg2_out_16_MGIOL - port map (IOLDO=>hades_dbg2_out_c_16, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_12, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_15_I: hades_dbg2_out_15_B - port map (hadesdbg2out15=>hades_dbg2_out(15)); - hades_dbg2_out_14_I: hades_dbg2_out_14_B - port map (hadesdbg2out14=>hades_dbg2_out(14)); - hades_dbg2_out_13_I: hades_dbg2_out_13_B - port map (hadesdbg2out13=>hades_dbg2_out(13)); - hades_dbg2_out_12_I: hades_dbg2_out_12_B - port map (PADDO=>hades_dbg2_out_c_12, hadesdbg2out12=>hades_dbg2_out(12)); - hades_dbg2_out_11_I: hades_dbg2_out_11_B - port map (PADDO=>hades_dbg2_out_c_11, hadesdbg2out11=>hades_dbg2_out(11)); - hades_dbg2_out_10_I: hades_dbg2_out_10_B - port map (PADDO=>hades_dbg2_out_c_10, hadesdbg2out10=>hades_dbg2_out(10)); - hades_dbg2_out_9_I: hades_dbg2_out_9_B - port map (PADDO=>hades_dbg2_out_c_9, hadesdbg2out9=>hades_dbg2_out(9)); - hades_dbg2_out_8_I: hades_dbg2_out_8_B - port map (PADDO=>hades_dbg2_out_c_8, hadesdbg2out8=>hades_dbg2_out(8)); - hades_dbg2_out_7_I: hades_dbg2_out_7_B - port map (PADDO=>hades_dbg2_out_c_7, hadesdbg2out7=>hades_dbg2_out(7)); - hades_dbg2_out_6_I: hades_dbg2_out_6_B - port map (PADDO=>hades_dbg2_out_c_6, hadesdbg2out6=>hades_dbg2_out(6)); - hades_dbg2_out_5_I: hades_dbg2_out_5_B - port map (PADDO=>hades_dbg2_out_c_5, hadesdbg2out5=>hades_dbg2_out(5)); - hades_dbg2_out_4_I: hades_dbg2_out_4_B - port map (PADDO=>hades_dbg2_out_c_4, hadesdbg2out4=>hades_dbg2_out(4)); - hades_dbg2_out_3_I: hades_dbg2_out_3_B - port map (hadesdbg2out3=>hades_dbg2_out(3)); - hades_dbg2_out_2_I: hades_dbg2_out_2_B - port map (IOLDO=>hades_dbg2_out_c_2, hadesdbg2out2=>hades_dbg2_out(2)); - hades_dbg2_out_2_MGIOLI: hades_dbg2_out_2_MGIOL - port map (IOLDO=>hades_dbg2_out_c_2, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_2, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_1_I: hades_dbg2_out_1_B - port map (IOLDO=>hades_dbg2_out_c_1, hadesdbg2out1=>hades_dbg2_out(1)); - hades_dbg2_out_1_MGIOLI: hades_dbg2_out_1_MGIOL - port map (IOLDO=>hades_dbg2_out_c_1, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_1, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_dbg2_out_0_I: hades_dbg2_out_0_B - port map (IOLDO=>hades_dbg2_out_c_0, hadesdbg2out0=>hades_dbg2_out(0)); - hades_dbg2_out_0_MGIOLI: hades_dbg2_out_0_MGIOL - port map (IOLDO=>hades_dbg2_out_c_0, - TXDATA0=>hades_tdc_bundle_inst_hades_raw_out_0, - CE=>un1_hit_i_2_0_a2, CLK=>pll_clks_3); - hades_buf_drop_3_I: hades_buf_drop_3_B - port map (hadesbufdrop3=>hades_buf_drop(3)); - hades_buf_drop_2_I: hades_buf_drop_2_B - port map (hadesbufdrop2=>hades_buf_drop(2)); - hades_buf_drop_1_I: hades_buf_drop_1_B - port map (IOLDO=>hades_buf_drop_c_1, hadesbufdrop1=>hades_buf_drop(1)); - hades_buf_drop_1_MGIOLI: hades_buf_drop_1_MGIOL - port map (IOLDO=>hades_buf_drop_c_1, - TXDATA0=>hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa, - LSR=>reset_dl_2, CLK=>pll_clks_3); - hades_buf_drop_0_I: hades_buf_drop_0_B - port map (hadesbufdrop0=>hades_buf_drop(0)); - hades_invalid_dl_3_I: hades_invalid_dl_3_B - port map (PADDO=>hades_invalid_dl_c_3, - hadesinvaliddl3=>hades_invalid_dl(3)); - hades_invalid_dl_2_I: hades_invalid_dl_2_B - port map (PADDO=>hades_invalid_dl_c_2, - hadesinvaliddl2=>hades_invalid_dl(2)); - hades_invalid_dl_1_I: hades_invalid_dl_1_B - port map (PADDO=>hades_invalid_dl_c_1, - hadesinvaliddl1=>hades_invalid_dl(1)); - hades_invalid_dl_0_I: hades_invalid_dl_0_B - port map (PADDO=>hades_invalid_dl_c_0, - hadesinvaliddl0=>hades_invalid_dl(0)); - hades_discardI: hades_discardB - port map (PADDO=>hades_discard_c, hadesdiscard=>hades_discard); - hades_hit_valid_3_I: hades_hit_valid_3_B - port map (PADDO=>hades_hit_valid_c_3, hadeshitvalid3=>hades_hit_valid(3)); - hades_hit_valid_2_I: hades_hit_valid_2_B - port map (PADDO=>hades_hit_valid_c_2, hadeshitvalid2=>hades_hit_valid(2)); - hades_hit_valid_1_I: hades_hit_valid_1_B - port map (PADDO=>hades_hit_valid_c_1, hadeshitvalid1=>hades_hit_valid(1)); - hades_hit_valid_0_I: hades_hit_valid_0_B - port map (PADDO=>hades_hit_valid_c_0, hadeshitvalid0=>hades_hit_valid(0)); - hades_hit_out_i_3_I: hades_hit_out_i_3_B - port map (PADDO=>ANB3, hadeshitouti3=>hades_hit_out_i(3)); - hades_hit_out_i_2_I: hades_hit_out_i_2_B - port map (PADDO=>ANB2, hadeshitouti2=>hades_hit_out_i(2)); - hades_hit_out_i_1_I: hades_hit_out_i_1_B - port map (PADDO=>ANB1, hadeshitouti1=>hades_hit_out_i(1)); - hades_hit_out_i_0_I: hades_hit_out_i_0_B - port map (PADDO=>ANB0, hadeshitouti0=>hades_hit_out_i(0)); - hades_buf_finishedI: hades_buf_finishedB - port map (PADDO=>hades_buf_finished_c, - hadesbuffinished=>hades_buf_finished); - hades_buf_releaseI: hades_buf_releaseB - port map (PADDO=>hades_buf_release_c, hadesbufrelease=>hades_buf_release); - hades_buf_out_validI: hades_buf_out_validB - port map (IOLDO=>hades_buf_out_valid_c, - hadesbufoutvalid=>hades_buf_out_valid); - hades_buf_out_valid_MGIOLI: hades_buf_out_valid_MGIOL - port map (IOLDO=>hades_buf_out_valid_c, - TXDATA0=>hades_tdc_bundle_inst_buf_out12, CE=>N_248_i, - CLK=>pll_clks_3); - hades_window_endI: hades_window_endB - port map (PADDO=>hades_window_end_c, hadeswindowend=>hades_window_end); - hades_offset_validI: hades_offset_validB - port map (PADDO=>hades_offset_valid_c, - hadesoffsetvalid=>hades_offset_valid); - hades_offset_8_I: hades_offset_8_B - port map (IOLDO=>hades_offset_c_8, hadesoffset8=>hades_offset(8)); - hades_offset_8_MGIOLI: hades_offset_8_MGIOL - port map (IOLDO=>hades_offset_c_8, TXDATA0=>hades_dbg2_coarse_c_5, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_7_I: hades_offset_7_B - port map (IOLDO=>hades_offset_c_7, hadesoffset7=>hades_offset(7)); - hades_offset_7_MGIOLI: hades_offset_7_MGIOL - port map (IOLDO=>hades_offset_c_7, TXDATA0=>hades_dbg2_coarse_c_4, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_6_I: hades_offset_6_B - port map (IOLDO=>hades_offset_c_6, hadesoffset6=>hades_offset(6)); - hades_offset_6_MGIOLI: hades_offset_6_MGIOL - port map (IOLDO=>hades_offset_c_6, TXDATA0=>hades_dbg2_coarse_c_3, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_5_I: hades_offset_5_B - port map (IOLDO=>hades_offset_c_5, hadesoffset5=>hades_offset(5)); - hades_offset_5_MGIOLI: hades_offset_5_MGIOL - port map (IOLDO=>hades_offset_c_5, TXDATA0=>hades_dbg2_coarse_c_2, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_4_I: hades_offset_4_B - port map (IOLDO=>hades_offset_c_4, hadesoffset4=>hades_offset(4)); - hades_offset_4_MGIOLI: hades_offset_4_MGIOL - port map (IOLDO=>hades_offset_c_4, TXDATA0=>hades_dbg2_coarse_c_1, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_3_I: hades_offset_3_B - port map (IOLDO=>hades_offset_c_3, hadesoffset3=>hades_offset(3)); - hades_offset_3_MGIOLI: hades_offset_3_MGIOL - port map (IOLDO=>hades_offset_c_3, TXDATA0=>hades_dbg2_coarse_c_0, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_2_I: hades_offset_2_B - port map (IOLDO=>hades_offset_c_2, hadesoffset2=>hades_offset(2)); - hades_offset_2_MGIOLI: hades_offset_2_MGIOL - port map (IOLDO=>hades_offset_c_2, - TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_1_I: hades_offset_1_B - port map (IOLDO=>hades_offset_c_1, hadesoffset1=>hades_offset(1)); - hades_offset_1_MGIOLI: hades_offset_1_MGIOL - port map (IOLDO=>hades_offset_c_1, - TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_offset_0_I: hades_offset_0_B - port map (IOLDO=>hades_offset_c_0, hadesoffset0=>hades_offset(0)); - hades_offset_0_MGIOLI: hades_offset_0_MGIOL - port map (IOLDO=>hades_offset_c_0, - TXDATA0=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0, - CE=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 - , LSR=>valid_fast_RNI999V, CLK=>pll_clks_3); - hades_lvl1_invalidI: hades_lvl1_invalidB - port map (PADDI=>hades_lvl1_invalid_c, - hadeslvl1invalid=>hades_lvl1_invalid); - hades_lvl1_invalid_MGIOLI: hades_lvl1_invalid_MGIOL - port map (DI=>hades_lvl1_invalid_c, CLK=>pll_clks_3, - INFF=>hades_invalid_dl_c_0); - hades_lvl1I: hades_lvl1B - port map (PADDI=>hades_lvl1_c, hadeslvl1=>hades_lvl1); - hades_lvl1_MGIOLI: hades_lvl1_MGIOL - port map (DI=>hades_lvl1_c, CLK=>pll_clks_3, - INFF=>hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0); - hades_raw_valid_vect_1_I: hades_raw_valid_vect_1_B - port map (hadesrawvalidvect1=>hades_raw_valid_vect(1)); - hades_raw_out_validI: hades_raw_out_validB - port map (IOLDO=>hades_raw_out_valid_c, - hadesrawoutvalid=>hades_raw_out_valid); - hades_raw_out_valid_MGIOLI: hades_raw_out_valid_MGIOL - port map (IOLDO=>hades_raw_out_valid_c, TXDATA0=>hades_offset_valid_c, - CLK=>pll_clks_3); - hades_trigI: hades_trigB - port map (PADDI=>hades_trig_c, hadestrig=>hades_trig); - release_outI: release_outB - port map (PADDO=>release_out_c, releaseout=>release_out); - finishedI: finishedB - port map (PADDO=>finished_c, finishedS=>finished); - last_buf_emptyI: last_buf_emptyB - port map (PADDO=>last_buf_empty_c, lastbufempty=>last_buf_empty); - discardI: discardB - port map (PADDO=>discard_c, discardS=>discard); - burstI: burstB - port map (PADDO=>burst_c, burstS=>burst); - LVL1_TRG_DATA_VALI_IN_risingI: LVL1_TRG_DATA_VALI_IN_risingB - port map (PADDO=>LVL1_TRG_DATA_VALI_IN_rising_c, - LVL1TRGDATAVALIINrising=>LVL1_TRG_DATA_VALI_IN_rising); - FEE_TRG_RELEASE_OUTI: FEE_TRG_RELEASE_OUTB - port map (IOLDO=>FEE_TRG_RELEASE_OUT_c, - FEETRGRELEASEOUT=>FEE_TRG_RELEASE_OUT); - FEE_TRG_RELEASE_OUT_MGIOLI: FEE_TRG_RELEASE_OUT_MGIOL - port map (IOLDO=>FEE_TRG_RELEASE_OUT_c, TXDATA0=>release_out_c, - LSR=>reset_dl_2, CLK=>rd_clk_c); - FEE_DATAFINISHED_OUTI: FEE_DATAFINISHED_OUTB - port map (IOLDO=>FEE_DATAFINISHED_OUT_c, - FEEDATAFINISHEDOUT=>FEE_DATAFINISHED_OUT); - FEE_DATAFINISHED_OUT_MGIOLI: FEE_DATAFINISHED_OUT_MGIOL - port map (IOLDO=>FEE_DATAFINISHED_OUT_c, TXDATA0=>finished_c, - LSR=>reset_dl_2, CLK=>rd_clk_c); - FEE_DATA_WRITE_OUTI: FEE_DATA_WRITE_OUTB - port map (IOLDO=>FEE_DATA_WRITE_OUT_c, - FEEDATAWRITEOUT=>FEE_DATA_WRITE_OUT); - FEE_DATA_WRITE_OUT_MGIOLI: FEE_DATA_WRITE_OUT_MGIOL - port map (IOLDO=>FEE_DATA_WRITE_OUT_c, TXDATA0=>fifo_rden_c, - LSR=>reset_dl_2, CLK=>rd_clk_c); - FEE_DATA_OUT_31_I: FEE_DATA_OUT_31_B - port map (PADDO=>FEE_DATA_OUT_c_31, FEEDATAOUT31=>FEE_DATA_OUT(31)); - FEE_DATA_OUT_30_I: FEE_DATA_OUT_30_B - port map (PADDO=>FEE_DATA_OUT_c_30, FEEDATAOUT30=>FEE_DATA_OUT(30)); - FEE_DATA_OUT_29_I: FEE_DATA_OUT_29_B - port map (PADDO=>FEE_DATA_OUT_c_29, FEEDATAOUT29=>FEE_DATA_OUT(29)); - FEE_DATA_OUT_28_I: FEE_DATA_OUT_28_B - port map (PADDO=>FEE_DATA_OUT_c_28, FEEDATAOUT28=>FEE_DATA_OUT(28)); - FEE_DATA_OUT_27_I: FEE_DATA_OUT_27_B - port map (PADDO=>FEE_DATA_OUT_c_27, FEEDATAOUT27=>FEE_DATA_OUT(27)); - FEE_DATA_OUT_26_I: FEE_DATA_OUT_26_B - port map (PADDO=>FEE_DATA_OUT_c_26, FEEDATAOUT26=>FEE_DATA_OUT(26)); - FEE_DATA_OUT_25_I: FEE_DATA_OUT_25_B - port map (PADDO=>FEE_DATA_OUT_c_25, FEEDATAOUT25=>FEE_DATA_OUT(25)); - FEE_DATA_OUT_24_I: FEE_DATA_OUT_24_B - port map (PADDO=>FEE_DATA_OUT_c_24, FEEDATAOUT24=>FEE_DATA_OUT(24)); - FEE_DATA_OUT_23_I: FEE_DATA_OUT_23_B - port map (PADDO=>FEE_DATA_OUT_c_23, FEEDATAOUT23=>FEE_DATA_OUT(23)); - FEE_DATA_OUT_22_I: FEE_DATA_OUT_22_B - port map (PADDO=>FEE_DATA_OUT_c_22, FEEDATAOUT22=>FEE_DATA_OUT(22)); - FEE_DATA_OUT_21_I: FEE_DATA_OUT_21_B - port map (PADDO=>FEE_DATA_OUT_c_21, FEEDATAOUT21=>FEE_DATA_OUT(21)); - FEE_DATA_OUT_20_I: FEE_DATA_OUT_20_B - port map (PADDO=>FEE_DATA_OUT_c_20, FEEDATAOUT20=>FEE_DATA_OUT(20)); - FEE_DATA_OUT_19_I: FEE_DATA_OUT_19_B - port map (PADDO=>FEE_DATA_OUT_c_19, FEEDATAOUT19=>FEE_DATA_OUT(19)); - FEE_DATA_OUT_18_I: FEE_DATA_OUT_18_B - port map (PADDO=>FEE_DATA_OUT_c_18, FEEDATAOUT18=>FEE_DATA_OUT(18)); - FEE_DATA_OUT_17_I: FEE_DATA_OUT_17_B - port map (PADDO=>FEE_DATA_OUT_c_17, FEEDATAOUT17=>FEE_DATA_OUT(17)); - FEE_DATA_OUT_16_I: FEE_DATA_OUT_16_B - port map (PADDO=>FEE_DATA_OUT_c_16, FEEDATAOUT16=>FEE_DATA_OUT(16)); - FEE_DATA_OUT_15_I: FEE_DATA_OUT_15_B - port map (PADDO=>FEE_DATA_OUT_c_15, FEEDATAOUT15=>FEE_DATA_OUT(15)); - FEE_DATA_OUT_14_I: FEE_DATA_OUT_14_B - port map (PADDO=>FEE_DATA_OUT_c_14, FEEDATAOUT14=>FEE_DATA_OUT(14)); - FEE_DATA_OUT_13_I: FEE_DATA_OUT_13_B - port map (PADDO=>FEE_DATA_OUT_c_13, FEEDATAOUT13=>FEE_DATA_OUT(13)); - FEE_DATA_OUT_12_I: FEE_DATA_OUT_12_B - port map (PADDO=>FEE_DATA_OUT_c_12, FEEDATAOUT12=>FEE_DATA_OUT(12)); - FEE_DATA_OUT_11_I: FEE_DATA_OUT_11_B - port map (PADDO=>FEE_DATA_OUT_c_11, FEEDATAOUT11=>FEE_DATA_OUT(11)); - FEE_DATA_OUT_10_I: FEE_DATA_OUT_10_B - port map (PADDO=>FEE_DATA_OUT_c_10, FEEDATAOUT10=>FEE_DATA_OUT(10)); - FEE_DATA_OUT_9_I: FEE_DATA_OUT_9_B - port map (PADDO=>FEE_DATA_OUT_c_9, FEEDATAOUT9=>FEE_DATA_OUT(9)); - FEE_DATA_OUT_8_I: FEE_DATA_OUT_8_B - port map (PADDO=>FEE_DATA_OUT_c_8, FEEDATAOUT8=>FEE_DATA_OUT(8)); - FEE_DATA_OUT_7_I: FEE_DATA_OUT_7_B - port map (PADDO=>FEE_DATA_OUT_c_7, FEEDATAOUT7=>FEE_DATA_OUT(7)); - FEE_DATA_OUT_6_I: FEE_DATA_OUT_6_B - port map (PADDO=>FEE_DATA_OUT_c_6, FEEDATAOUT6=>FEE_DATA_OUT(6)); - FEE_DATA_OUT_5_I: FEE_DATA_OUT_5_B - port map (PADDO=>FEE_DATA_OUT_c_5, FEEDATAOUT5=>FEE_DATA_OUT(5)); - FEE_DATA_OUT_4_I: FEE_DATA_OUT_4_B - port map (PADDO=>FEE_DATA_OUT_c_4, FEEDATAOUT4=>FEE_DATA_OUT(4)); - FEE_DATA_OUT_3_I: FEE_DATA_OUT_3_B - port map (PADDO=>FEE_DATA_OUT_c_3, FEEDATAOUT3=>FEE_DATA_OUT(3)); - FEE_DATA_OUT_2_I: FEE_DATA_OUT_2_B - port map (PADDO=>FEE_DATA_OUT_c_2, FEEDATAOUT2=>FEE_DATA_OUT(2)); - FEE_DATA_OUT_1_I: FEE_DATA_OUT_1_B - port map (PADDO=>FEE_DATA_OUT_c_1, FEEDATAOUT1=>FEE_DATA_OUT(1)); - FEE_DATA_OUT_0_I: FEE_DATA_OUT_0_B - port map (PADDO=>FEE_DATA_OUT_c_0, FEEDATAOUT0=>FEE_DATA_OUT(0)); - LVL1_INVALID_TRG_INI: LVL1_INVALID_TRG_INB - port map (PADDI=>LVL1_INVALID_TRG_IN_c, - LVL1INVALIDTRGIN=>LVL1_INVALID_TRG_IN); - LVL1_INVALID_TRG_IN_MGIOLI: LVL1_INVALID_TRG_IN_MGIOL - port map (DI=>LVL1_INVALID_TRG_IN_c, CLK=>rd_clk_c, - INFF=>trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0); - LVL1_TRG_DATA_VALID_INI: LVL1_TRG_DATA_VALID_INB - port map (PADDI=>LVL1_TRG_DATA_VALID_IN_c, - LVL1TRGDATAVALIDIN=>LVL1_TRG_DATA_VALID_IN); - LVL1_TRG_DATA_VALID_IN_MGIOLI: LVL1_TRG_DATA_VALID_IN_MGIOL - port map (DI=>LVL1_TRG_DATA_VALID_IN_c, CLK=>rd_clk_c, - INFF=>trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0); - fifo_empty1I: fifo_empty1B - port map (PADDO=>fifo_empty1_c, fifoempty1=>fifo_empty1); - fifo_rdenI: fifo_rdenB - port map (PADDO=>fifo_rden_c, fiforden=>fifo_rden); - fifo_data_out_31_I: fifo_data_out_31_B - port map (PADDO=>FEE_DATA_OUT_c_31, fifodataout31=>fifo_data_out(31)); - fifo_data_out_30_I: fifo_data_out_30_B - port map (PADDO=>FEE_DATA_OUT_c_30, fifodataout30=>fifo_data_out(30)); - fifo_data_out_29_I: fifo_data_out_29_B - port map (PADDO=>FEE_DATA_OUT_c_29, fifodataout29=>fifo_data_out(29)); - fifo_data_out_28_I: fifo_data_out_28_B - port map (PADDO=>FEE_DATA_OUT_c_28, fifodataout28=>fifo_data_out(28)); - fifo_data_out_27_I: fifo_data_out_27_B - port map (PADDO=>FEE_DATA_OUT_c_27, fifodataout27=>fifo_data_out(27)); - fifo_data_out_26_I: fifo_data_out_26_B - port map (PADDO=>FEE_DATA_OUT_c_26, fifodataout26=>fifo_data_out(26)); - fifo_data_out_25_I: fifo_data_out_25_B - port map (PADDO=>FEE_DATA_OUT_c_25, fifodataout25=>fifo_data_out(25)); - fifo_data_out_24_I: fifo_data_out_24_B - port map (PADDO=>FEE_DATA_OUT_c_24, fifodataout24=>fifo_data_out(24)); - fifo_data_out_23_I: fifo_data_out_23_B - port map (PADDO=>FEE_DATA_OUT_c_23, fifodataout23=>fifo_data_out(23)); - fifo_data_out_22_I: fifo_data_out_22_B - port map (PADDO=>FEE_DATA_OUT_c_22, fifodataout22=>fifo_data_out(22)); - fifo_data_out_21_I: fifo_data_out_21_B - port map (PADDO=>FEE_DATA_OUT_c_21, fifodataout21=>fifo_data_out(21)); - fifo_data_out_20_I: fifo_data_out_20_B - port map (PADDO=>FEE_DATA_OUT_c_20, fifodataout20=>fifo_data_out(20)); - fifo_data_out_19_I: fifo_data_out_19_B - port map (PADDO=>FEE_DATA_OUT_c_19, fifodataout19=>fifo_data_out(19)); - fifo_data_out_18_I: fifo_data_out_18_B - port map (PADDO=>FEE_DATA_OUT_c_18, fifodataout18=>fifo_data_out(18)); - fifo_data_out_17_I: fifo_data_out_17_B - port map (PADDO=>FEE_DATA_OUT_c_17, fifodataout17=>fifo_data_out(17)); - fifo_data_out_16_I: fifo_data_out_16_B - port map (PADDO=>FEE_DATA_OUT_c_16, fifodataout16=>fifo_data_out(16)); - fifo_data_out_15_I: fifo_data_out_15_B - port map (PADDO=>FEE_DATA_OUT_c_15, fifodataout15=>fifo_data_out(15)); - fifo_data_out_14_I: fifo_data_out_14_B - port map (PADDO=>FEE_DATA_OUT_c_14, fifodataout14=>fifo_data_out(14)); - fifo_data_out_13_I: fifo_data_out_13_B - port map (PADDO=>FEE_DATA_OUT_c_13, fifodataout13=>fifo_data_out(13)); - fifo_data_out_12_I: fifo_data_out_12_B - port map (PADDO=>FEE_DATA_OUT_c_12, fifodataout12=>fifo_data_out(12)); - fifo_data_out_11_I: fifo_data_out_11_B - port map (PADDO=>FEE_DATA_OUT_c_11, fifodataout11=>fifo_data_out(11)); - fifo_data_out_10_I: fifo_data_out_10_B - port map (PADDO=>FEE_DATA_OUT_c_10, fifodataout10=>fifo_data_out(10)); - fifo_data_out_9_I: fifo_data_out_9_B - port map (PADDO=>FEE_DATA_OUT_c_9, fifodataout9=>fifo_data_out(9)); - fifo_data_out_8_I: fifo_data_out_8_B - port map (PADDO=>FEE_DATA_OUT_c_8, fifodataout8=>fifo_data_out(8)); - fifo_data_out_7_I: fifo_data_out_7_B - port map (PADDO=>FEE_DATA_OUT_c_7, fifodataout7=>fifo_data_out(7)); - fifo_data_out_6_I: fifo_data_out_6_B - port map (PADDO=>FEE_DATA_OUT_c_6, fifodataout6=>fifo_data_out(6)); - fifo_data_out_5_I: fifo_data_out_5_B - port map (PADDO=>FEE_DATA_OUT_c_5, fifodataout5=>fifo_data_out(5)); - fifo_data_out_4_I: fifo_data_out_4_B - port map (PADDO=>FEE_DATA_OUT_c_4, fifodataout4=>fifo_data_out(4)); - fifo_data_out_3_I: fifo_data_out_3_B - port map (PADDO=>FEE_DATA_OUT_c_3, fifodataout3=>fifo_data_out(3)); - fifo_data_out_2_I: fifo_data_out_2_B - port map (PADDO=>FEE_DATA_OUT_c_2, fifodataout2=>fifo_data_out(2)); - fifo_data_out_1_I: fifo_data_out_1_B - port map (PADDO=>FEE_DATA_OUT_c_1, fifodataout1=>fifo_data_out(1)); - trig_2_I: trig_2_B - port map (PADDI=>trig_c_2, trig2=>trig(2)); - trig_1_I: trig_1_B - port map (PADDI=>trig_c_1, trig1=>trig(1)); - trig_0_I: trig_0_B - port map (PADDI=>trig_c_0, trig0=>trig(0)); - reset_dcI: reset_dcB - port map (PADDI=>reset_dc_c, resetdc=>reset_dc); - reset_dc_MGIOLI: reset_dc_MGIOL - port map (DI=>reset_dc_c, CLK=>pll_clks_3, INFF=>reset_dl_1); - rd_clkI: rd_clkB - port map (PADDI=>rd_clk_c, rdclk=>rd_clk); - - genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port map (DIA15=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA13=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA12=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA11=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA9=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - ADA13=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - ADA12=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, - ADA11=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - ADA10=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, - ADA9=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - ADA8=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, - ADA7=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - ADA6=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, - ADA5=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - DOA17=>genblk1_2_un1_tdc_channel_fifo_out_inst_17, - DOA16=>genblk1_2_un1_tdc_channel_fifo_out_inst_16, - DOA15=>genblk1_2_un1_tdc_channel_fifo_out_inst_15, - DOA14=>genblk1_2_un1_tdc_channel_fifo_out_inst_14, - DOA13=>genblk1_2_un1_tdc_channel_fifo_out_inst_13, - DOA12=>genblk1_2_un1_tdc_channel_fifo_out_inst_12, - DOA11=>genblk1_2_un1_tdc_channel_fifo_out_inst_11, - DOA10=>genblk1_2_un1_tdc_channel_fifo_out_inst_10, - DOA9=>genblk1_2_un1_tdc_channel_fifo_out_inst_9, - DOA8=>genblk1_2_un1_tdc_channel_fifo_out_inst_8, - DOA7=>genblk1_2_un1_tdc_channel_fifo_out_inst_7, - DOA6=>genblk1_2_un1_tdc_channel_fifo_out_inst_6, - DOA5=>genblk1_2_un1_tdc_channel_fifo_out_inst_5, - DOA4=>genblk1_2_un1_tdc_channel_fifo_out_inst_4, - DOA3=>genblk1_2_un1_tdc_channel_fifo_out_inst_3, - DOA2=>genblk1_2_un1_tdc_channel_fifo_out_inst_2, - DOA1=>genblk1_2_un1_tdc_channel_fifo_out_inst_1, - DOA0=>genblk1_2_un1_tdc_channel_fifo_out_inst_0, - CEA=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLKA=>pll_clks_3, CLKB=>pll_clks_3, - OCEB=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CEB=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - DOB0=>genblk1_2_un1_tdc_channel_fifo_out_inst_18, - DOB1=>genblk1_2_un1_tdc_channel_fifo_out_inst_19, - DOB2=>genblk1_2_un1_tdc_channel_fifo_out_inst_20, - DOB3=>genblk1_2_un1_tdc_channel_fifo_out_inst_21, - DOB4=>genblk1_2_un1_tdc_channel_fifo_out_inst_22, - DOB5=>genblk1_2_un1_tdc_channel_fifo_out_inst_23, - ADB5=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - ADB6=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, - ADB7=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - ADB8=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, - ADB9=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - ADB10=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, - ADB11=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - ADB12=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, - ADB13=>genblk1_2_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - DIB6=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB8=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB9=>genblk1_2_tdc_channel_fifo_out_inst_fifo_in_data_9); - - genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port map (DIA15=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA13=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA12=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA11=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA9=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - ADA13=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - ADA12=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, - ADA11=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - ADA10=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, - ADA9=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - ADA8=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, - ADA7=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - ADA6=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, - ADA5=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - DOA17=>genblk1_1_un1_tdc_channel_fifo_out_inst_17, - DOA16=>genblk1_1_un1_tdc_channel_fifo_out_inst_16, - DOA15=>genblk1_1_un1_tdc_channel_fifo_out_inst_15, - DOA14=>genblk1_1_un1_tdc_channel_fifo_out_inst_14, - DOA13=>genblk1_1_un1_tdc_channel_fifo_out_inst_13, - DOA12=>genblk1_1_un1_tdc_channel_fifo_out_inst_12, - DOA11=>genblk1_1_un1_tdc_channel_fifo_out_inst_11, - DOA10=>genblk1_1_un1_tdc_channel_fifo_out_inst_10, - DOA9=>genblk1_1_un1_tdc_channel_fifo_out_inst_9, - DOA8=>genblk1_1_un1_tdc_channel_fifo_out_inst_8, - DOA7=>genblk1_1_un1_tdc_channel_fifo_out_inst_7, - DOA6=>genblk1_1_un1_tdc_channel_fifo_out_inst_6, - DOA5=>genblk1_1_un1_tdc_channel_fifo_out_inst_5, - DOA4=>genblk1_1_un1_tdc_channel_fifo_out_inst_4, - DOA3=>genblk1_1_un1_tdc_channel_fifo_out_inst_3, - DOA2=>genblk1_1_un1_tdc_channel_fifo_out_inst_2, - DOA1=>genblk1_1_un1_tdc_channel_fifo_out_inst_1, - DOA0=>genblk1_1_un1_tdc_channel_fifo_out_inst_0, - CEA=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLKA=>pll_clks_3, CLKB=>pll_clks_3, - OCEB=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CEB=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - DOB0=>genblk1_1_un1_tdc_channel_fifo_out_inst_18, - DOB1=>genblk1_1_un1_tdc_channel_fifo_out_inst_19, - DOB2=>genblk1_1_un1_tdc_channel_fifo_out_inst_20, - DOB3=>genblk1_1_un1_tdc_channel_fifo_out_inst_21, - DOB4=>genblk1_1_un1_tdc_channel_fifo_out_inst_22, - DOB5=>genblk1_1_un1_tdc_channel_fifo_out_inst_23, - ADB5=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - ADB6=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, - ADB7=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - ADB8=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, - ADB9=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - ADB10=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, - ADB11=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - ADB12=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, - ADB13=>genblk1_1_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - DIB6=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB8=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB9=>genblk1_1_tdc_channel_fifo_out_inst_fifo_in_data_9); - - genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0I: genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_pdp_ram_0_0_0 - port map (DIA15=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA13=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA12=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA11=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIA9=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - ADA13=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_8, - ADA12=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_7, - ADA11=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_6, - ADA10=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_5, - ADA9=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_4, - ADA8=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_3, - ADA7=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_2, - ADA6=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_1, - ADA5=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wptr_0, - DOA17=>genblk1_0_un1_tdc_channel_fifo_out_inst_17, - DOA16=>genblk1_0_un1_tdc_channel_fifo_out_inst_16, - DOA15=>genblk1_0_un1_tdc_channel_fifo_out_inst_15, - DOA14=>genblk1_0_un1_tdc_channel_fifo_out_inst_14, - DOA13=>genblk1_0_un1_tdc_channel_fifo_out_inst_13, - DOA12=>genblk1_0_un1_tdc_channel_fifo_out_inst_12, - DOA11=>genblk1_0_un1_tdc_channel_fifo_out_inst_11, - DOA10=>genblk1_0_un1_tdc_channel_fifo_out_inst_10, - DOA9=>genblk1_0_un1_tdc_channel_fifo_out_inst_9, - DOA8=>genblk1_0_un1_tdc_channel_fifo_out_inst_8, - DOA7=>genblk1_0_un1_tdc_channel_fifo_out_inst_7, - DOA6=>genblk1_0_un1_tdc_channel_fifo_out_inst_6, - DOA5=>genblk1_0_un1_tdc_channel_fifo_out_inst_5, - DOA4=>genblk1_0_un1_tdc_channel_fifo_out_inst_4, - DOA3=>genblk1_0_un1_tdc_channel_fifo_out_inst_3, - DOA2=>genblk1_0_un1_tdc_channel_fifo_out_inst_2, - DOA1=>genblk1_0_un1_tdc_channel_fifo_out_inst_1, - DOA0=>genblk1_0_un1_tdc_channel_fifo_out_inst_0, - CEA=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_wren_i, - CLKA=>pll_clks_3, CLKB=>pll_clks_3, - OCEB=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - CEB=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rden_i, - DOB0=>genblk1_0_un1_tdc_channel_fifo_out_inst_18, - DOB1=>genblk1_0_un1_tdc_channel_fifo_out_inst_19, - DOB2=>genblk1_0_un1_tdc_channel_fifo_out_inst_20, - DOB3=>genblk1_0_un1_tdc_channel_fifo_out_inst_21, - DOB4=>genblk1_0_un1_tdc_channel_fifo_out_inst_22, - DOB5=>genblk1_0_un1_tdc_channel_fifo_out_inst_23, - ADB5=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_0, - ADB6=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_1, - ADB7=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_2, - ADB8=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_3, - ADB9=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_4, - ADB10=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_5, - ADB11=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_6, - ADB12=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_7, - ADB13=>genblk1_0_tdc_channel_fifo_out_inst_fifo32dc_inst_rptr_8, - DIB6=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB8=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9, - DIB9=>genblk1_0_tdc_channel_fifo_out_inst_fifo_in_data_9); - - fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1I: fifo_colector_inst_fifo40_inst_pdp_ram_0_0_1 - port map (DIA17=>fifo_colector_inst_data_buffer_17, - DIA16=>fifo_colector_inst_data_buffer_16, - DIA15=>fifo_colector_inst_data_buffer_15, - DIA14=>fifo_colector_inst_data_buffer_14, - DIA13=>fifo_colector_inst_data_buffer_13, - DIA12=>fifo_colector_inst_data_buffer_12, - DIA11=>fifo_colector_inst_data_buffer_11, - DIA10=>fifo_colector_inst_data_buffer_10, - DIA9=>fifo_colector_inst_data_buffer_9, - DIA8=>fifo_colector_inst_data_buffer_8, - DIA7=>fifo_colector_inst_data_buffer_7, - DIA6=>fifo_colector_inst_data_buffer_6, - DIA5=>fifo_colector_inst_data_buffer_5, - DIA4=>fifo_colector_inst_data_buffer_4, - DIA3=>fifo_colector_inst_data_buffer_3, - DIA2=>fifo_colector_inst_data_buffer_2, - DIA1=>fifo_colector_inst_data_buffer_1, - DIA0=>fifo_colector_inst_data_buffer_0, - ADA13=>fifo_colector_inst_fifo40_inst_wptr_8, - ADA12=>fifo_colector_inst_fifo40_inst_wptr_7, - ADA11=>fifo_colector_inst_fifo40_inst_wptr_6, - ADA10=>fifo_colector_inst_fifo40_inst_wptr_5, - ADA9=>fifo_colector_inst_fifo40_inst_wptr_4, - ADA8=>fifo_colector_inst_fifo40_inst_wptr_3, - ADA7=>fifo_colector_inst_fifo40_inst_wptr_2, - ADA6=>fifo_colector_inst_fifo40_inst_wptr_1, - ADA5=>fifo_colector_inst_fifo40_inst_wptr_0, - DOA17=>FEE_DATA_OUT_c_17, DOA16=>FEE_DATA_OUT_c_16, - DOA15=>FEE_DATA_OUT_c_15, DOA14=>FEE_DATA_OUT_c_14, - DOA13=>FEE_DATA_OUT_c_13, DOA12=>FEE_DATA_OUT_c_12, - DOA11=>FEE_DATA_OUT_c_11, DOA10=>FEE_DATA_OUT_c_10, - DOA9=>FEE_DATA_OUT_c_9, DOA8=>FEE_DATA_OUT_c_8, - DOA7=>FEE_DATA_OUT_c_7, DOA6=>FEE_DATA_OUT_c_6, - DOA5=>FEE_DATA_OUT_c_5, DOA4=>FEE_DATA_OUT_c_4, - DOA3=>FEE_DATA_OUT_c_3, DOA2=>FEE_DATA_OUT_c_2, - DOA1=>FEE_DATA_OUT_c_1, DOA0=>FEE_DATA_OUT_c_0, - CEA=>fifo_colector_inst_fifo40_inst_wren_i, CLKA=>pll_clks_3, - CLKB=>rd_clk_c, OCEB=>fifo_colector_inst_fifo40_inst_rden_i, - CEB=>fifo_colector_inst_fifo40_inst_rden_i, - DOB0=>FEE_DATA_OUT_c_18, DOB1=>FEE_DATA_OUT_c_19, - DOB2=>FEE_DATA_OUT_c_20, DOB3=>FEE_DATA_OUT_c_21, - DOB4=>FEE_DATA_OUT_c_22, DOB5=>FEE_DATA_OUT_c_23, - DOB6=>FEE_DATA_OUT_c_24, DOB7=>FEE_DATA_OUT_c_25, - DOB8=>FEE_DATA_OUT_c_26, DOB9=>FEE_DATA_OUT_c_27, - DOB10=>FEE_DATA_OUT_c_28, DOB11=>FEE_DATA_OUT_c_29, - DOB12=>FEE_DATA_OUT_c_30, DOB13=>FEE_DATA_OUT_c_31, - ADB5=>fifo_colector_inst_fifo40_inst_rptr_0, - ADB6=>fifo_colector_inst_fifo40_inst_rptr_1, - ADB7=>fifo_colector_inst_fifo40_inst_rptr_2, - ADB8=>fifo_colector_inst_fifo40_inst_rptr_3, - ADB9=>fifo_colector_inst_fifo40_inst_rptr_4, - ADB10=>fifo_colector_inst_fifo40_inst_rptr_5, - ADB11=>fifo_colector_inst_fifo40_inst_rptr_6, - ADB12=>fifo_colector_inst_fifo40_inst_rptr_7, - ADB13=>fifo_colector_inst_fifo40_inst_rptr_8, - DIB0=>fifo_colector_inst_data_buffer_18, - DIB1=>fifo_colector_inst_data_buffer_19, - DIB2=>fifo_colector_inst_data_buffer_20, - DIB3=>fifo_colector_inst_data_buffer_21, - DIB4=>fifo_colector_inst_data_buffer_22, - DIB5=>fifo_colector_inst_data_buffer_23, - DIB6=>fifo_colector_inst_data_buffer_24, - DIB7=>fifo_colector_inst_data_buffer_25, - DIB8=>fifo_colector_inst_data_buffer_26, - DIB9=>fifo_colector_inst_data_buffer_27, - DIB10=>fifo_colector_inst_data_buffer_28, - DIB11=>fifo_colector_inst_data_buffer_29, - DIB12=>fifo_colector_inst_data_buffer_30, - DIB13=>fifo_colector_inst_data_buffer_31, - DIB14=>fifo_colector_inst_data_buffer_32, - DIB15=>fifo_colector_inst_data_buffer_33); - pll0inst_PLLInst_0I: pll0inst_PLLInst_0 - port map (CLKI=>clk_c, CLKFB=>pll_clks_0, STDBY=>pll0inst_GND, - CLKOS3=>pll_clks_3, CLKOS2=>pll_clks_2, CLKOS=>pll_clks_1, - CLKOP=>pll_clks_0); - VHI_INST: VHI - port map (Z=>VCCI); - PUR_INST: PUR - port map (PUR=>VCCI); - GSR_INST: GSR - port map (GSR=>VCCI); - end Structure; - - - - library IEEE, vital2000, ECP5UM; - configuration Structure_CON of top_tf is - for Structure - end for; - end Structure_CON; - - diff --git a/impl1/s1_impl1_vo.sdf b/impl1/s1_impl1_vo.sdf deleted file mode 100644 index 4989c4b..0000000 --- a/impl1/s1_impl1_vo.sdf +++ /dev/null @@ -1,678 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "top") - (DATE "Fri Jul 17 09:09:56 2020") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.11.2.446") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_0) - (DELAY - (ABSOLUTE - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (-167:-165:-164)(167:174:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_1) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_2) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_3) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_4) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_5) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_6) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_7) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_8) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH A0 F0 (119:130:141)(119:130:141)) - (IOPATH A0 F1 (352:372:392)(352:372:392)) - (IOPATH A0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_9) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_10) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_11) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_12) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_13) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_14) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (119:130:141)(119:130:141)) - (IOPATH A1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_15) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH B0 F0 (119:130:141)(119:130:141)) - (IOPATH B0 F1 (352:372:392)(352:372:392)) - (IOPATH B0 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q0 (257:283:309)(257:283:309)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - (IOPATH FCI F0 (140:198:257)(140:198:257)) - (IOPATH FCI F1 (201:237:273)(201:237:273)) - (IOPATH FCI FCO (39:41:43)(39:41:43)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD DI0 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:225)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "SCCU2C") - (INSTANCE SLICE_16) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (119:130:141)(119:130:141)) - (IOPATH B1 FCO (112:195:278)(112:195:278)) - (IOPATH CLK Q1 (257:282:308)(257:282:308)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (-166:-166:-166)(166:173:181)) - (SETUPHOLD LSR (posedge CLK) (146:185:224)(-146:-132:-119)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (444:444:444)) - (WIDTH (negedge LSR) (444:444:444)) - (WIDTH (posedge CLK) (889:889:889)) - (WIDTH (negedge CLK) (889:889:889)) - ) - ) - (CELL - (CELLTYPE "pwm") - (INSTANCE pwm_I) - (DELAY - (ABSOLUTE - (IOPATH PADDO pwm (1736:1751:1766)(1736:1751:1766)) - ) - ) - ) - (CELL - (CELLTYPE "clk") - (INSTANCE clk_I) - (DELAY - (ABSOLUTE - (IOPATH clk PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge clk) (2500:2500:2500)) - (WIDTH (negedge clk) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "reset") - (INSTANCE reset_I) - (DELAY - (ABSOLUTE - (IOPATH reset PADDI (826:851:876)(826:851:876)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge reset) (2500:2500:2500)) - (WIDTH (negedge reset) (2500:2500:2500)) - ) - ) - (CELL - (CELLTYPE "top") - (INSTANCE ) - (DELAY - (ABSOLUTE - (INTERCONNECT SLICE_0/Q0 SLICE_0/B0 (378:438:499)(378:438:499)) - (INTERCONNECT SLICE_0/Q0 pwm_I/PADDO (440:497:555)(440:497:555)) - (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT reset_I/PADDI SLICE_0/LSR (605:671:737)(605:671:737)) - (INTERCONNECT reset_I/PADDI SLICE_1/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_1/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_2/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_2/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_3/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_3/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_4/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_4/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_5/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_5/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_6/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_6/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_7/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_7/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_8/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_8/LSR (745:828:911)(745:828:911)) - (INTERCONNECT reset_I/PADDI SLICE_9/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_9/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_10/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_10/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_11/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_11/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_12/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_12/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_13/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_13/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_14/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_14/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_15/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_15/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT reset_I/PADDI SLICE_16/LSR (880:977:1075)(880:977:1075)) - (INTERCONNECT clk_I/PADDI SLICE_0/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_1/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_1/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_2/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_2/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_3/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_3/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_4/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_4/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_5/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_5/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_6/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_6/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_7/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_7/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_8/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_8/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_9/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_9/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_10/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_10/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_11/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_11/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_12/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_12/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_13/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_13/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_14/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_14/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_15/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_15/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT clk_I/PADDI SLICE_16/CLK (1588:1665:1742)(1588:1665:1742)) - (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_1/Q0 SLICE_1/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_3/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_3/Q0 SLICE_3/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (380:457:535)(380:457:535)) - (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_5/Q0 SLICE_5/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_6/Q0 SLICE_6/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_7/Q1 SLICE_7/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_7/Q0 SLICE_7/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_7/F1 SLICE_7/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_8/FCO SLICE_7/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_8/Q1 SLICE_8/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (380:457:535)(380:457:535)) - (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_9/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_9/Q0 SLICE_9/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_10/FCO SLICE_9/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_10/Q1 SLICE_10/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_10/Q0 SLICE_10/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_10/F1 SLICE_10/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_11/FCO SLICE_10/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_11/Q1 SLICE_11/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_11/F1 SLICE_11/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/FCO SLICE_11/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/Q1 SLICE_12/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_12/Q0 SLICE_12/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_13/FCO SLICE_12/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_13/Q1 SLICE_13/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_13/Q0 SLICE_13/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_13/F1 SLICE_13/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_14/FCO SLICE_13/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_14/Q1 SLICE_14/A1 (258:314:370)(258:314:370)) - (INTERCONNECT SLICE_14/Q0 SLICE_14/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_14/F1 SLICE_14/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_15/FCO SLICE_14/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_15/Q1 SLICE_15/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_15/Q0 SLICE_15/B0 (374:431:489)(374:431:489)) - (INTERCONNECT SLICE_15/F1 SLICE_15/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/FCO SLICE_15/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q1 SLICE_16/B1 (272:320:369)(272:320:369)) - (INTERCONNECT SLICE_16/F1 SLICE_16/DI1 (0:0:0)(0:0:0)) - ) - ) - ) -) diff --git a/impl1/s1_impl1_vo.vo b/impl1/s1_impl1_vo.vo deleted file mode 100644 index 1501258..0000000 --- a/impl1/s1_impl1_vo.vo +++ /dev/null @@ -1,207 +0,0 @@ - -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.11.2.446 -// ldbanno -n Verilog -o s1_impl1_vo.vo -w -neg -gui s1_impl1.ncd -// Netlist created on Fri Jul 17 09:08:55 2020 -// Netlist written on Fri Jul 17 09:09:56 2020 -// Design is for device LFE5UM5G-45F -// Design is for package CABGA381 -// Design is for performance grade 8 - -`timescale 1 ns / 1 ps - -module top ( clk, reset, pwm ); - input clk, reset; - output pwm; - wire pwm_c_31, n134, reset_c, clk_c, n216, n2, n3, n135, n136, n215, n4, - n5, n137, n138, n214, n6, n7, n139, n140, n213, n8, n9, n141, n142, - n212, n10, n11, n143, n144, n211, n12, n13, n145, n146, n210, n14, - n15, n147, n148, n209, n16, n17, n149, n150, n208, n18, n19, n151, - n152, n207, n20, n21, n153, n154, n206, n22, n23, n155, n156, n205, - n24, n25, n157, n158, n204, n26, n27, n159, n160, n203, n28, n29, - n161, n162, n202, n30, n31, n163, n164, n201, n32, n165, VCCI; - - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'h0000), .REG0_SD("VHI"), - .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) SLICE_0( .M1(1'bX), .A1(1'bX), - .B1(1'bX), .C1(1'bX), .D1(1'bX), .DI1(1'bX), .DI0(n134), .A0(1'bX), - .B0(pwm_c_31), .C0(1'bX), .D0(1'b1), .FCI(n216), .M0(1'bX), .CE(1'bX), - .CLK(clk_c), .LSR(reset_c), .FCO(), .F1(), .Q1(), .F0(n134), .Q0(pwm_c_31)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_1( .M1(1'bX), .A1(n2), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n135), - .DI0(n136), .A0(1'bX), .B0(n3), .C0(1'bX), .D0(1'b1), .FCI(n215), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n216), .F1(n135), - .Q1(n2), .F0(n136), .Q0(n3)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_2( .M1(1'bX), .A1(n4), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n137), - .DI0(n138), .A0(1'bX), .B0(n5), .C0(1'bX), .D0(1'b1), .FCI(n214), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n215), .F1(n137), - .Q1(n4), .F0(n138), .Q0(n5)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_3( .M1(1'bX), .A1(1'bX), .B1(n6), .C1(1'bX), .D1(1'b1), .DI1(n139), - .DI0(n140), .A0(1'bX), .B0(n7), .C0(1'bX), .D0(1'b1), .FCI(n213), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n214), .F1(n139), - .Q1(n6), .F0(n140), .Q0(n7)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hAA00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_4( .M1(1'bX), .A1(1'bX), .B1(n8), .C1(1'bX), .D1(1'b1), .DI1(n141), - .DI0(n142), .A0(n9), .B0(1'bX), .C0(1'bX), .D0(1'b1), .FCI(n212), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n213), .F1(n141), - .Q1(n8), .F0(n142), .Q0(n9)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_5( .M1(1'bX), .A1(n10), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n143), - .DI0(n144), .A0(1'bX), .B0(n11), .C0(1'bX), .D0(1'b1), .FCI(n211), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n212), .F1(n143), - .Q1(n10), .F0(n144), .Q0(n11)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_6( .M1(1'bX), .A1(n12), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n145), - .DI0(n146), .A0(1'bX), .B0(n13), .C0(1'bX), .D0(1'b1), .FCI(n210), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n211), .F1(n145), - .Q1(n12), .F0(n146), .Q0(n13)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_7( .M1(1'bX), .A1(1'bX), .B1(n14), .C1(1'bX), .D1(1'b1), .DI1(n147), - .DI0(n148), .A0(1'bX), .B0(n15), .C0(1'bX), .D0(1'b1), .FCI(n209), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n210), .F1(n147), - .Q1(n14), .F0(n148), .Q0(n15)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hAA00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_8( .M1(1'bX), .A1(1'bX), .B1(n16), .C1(1'bX), .D1(1'b1), .DI1(n149), - .DI0(n150), .A0(n17), .B0(1'bX), .C0(1'bX), .D0(1'b1), .FCI(n208), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n209), .F1(n149), - .Q1(n16), .F0(n150), .Q0(n17)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_9( .M1(1'bX), .A1(n18), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n151), - .DI0(n152), .A0(1'bX), .B0(n19), .C0(1'bX), .D0(1'b1), .FCI(n207), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n208), .F1(n151), - .Q1(n18), .F0(n152), .Q0(n19)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_10( .M1(1'bX), .A1(n20), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n153), - .DI0(n154), .A0(1'bX), .B0(n21), .C0(1'bX), .D0(1'b1), .FCI(n206), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n207), .F1(n153), - .Q1(n20), .F0(n154), .Q0(n21)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_11( .M1(1'bX), .A1(1'bX), .B1(n22), .C1(1'bX), .D1(1'b1), .DI1(n155), - .DI0(n156), .A0(1'bX), .B0(n23), .C0(1'bX), .D0(1'b1), .FCI(n205), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n206), .F1(n155), - .Q1(n22), .F0(n156), .Q0(n23)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_12( .M1(1'bX), .A1(1'bX), .B1(n24), .C1(1'bX), .D1(1'b1), .DI1(n157), - .DI0(n158), .A0(1'bX), .B0(n25), .C0(1'bX), .D0(1'b1), .FCI(n204), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n205), .F1(n157), - .Q1(n24), .F0(n158), .Q0(n25)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_13( .M1(1'bX), .A1(n26), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n159), - .DI0(n160), .A0(1'bX), .B0(n27), .C0(1'bX), .D0(1'b1), .FCI(n203), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n204), .F1(n159), - .Q1(n26), .F0(n160), .Q0(n27)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hAA00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_14( .M1(1'bX), .A1(n28), .B1(1'bX), .C1(1'bX), .D1(1'b1), .DI1(n161), - .DI0(n162), .A0(1'bX), .B0(n29), .C0(1'bX), .D0(1'b1), .FCI(n202), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n203), .F1(n161), - .Q1(n28), .F0(n162), .Q0(n29)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'hCC00), .INIT1_INITVAL(16'hCC00), .REG1_SD("VHI"), - .REG0_SD("VHI"), .CHECK_DI1(1'b1), .CHECK_DI0(1'b1), .CHECK_LSR(1'b1)) - SLICE_15( .M1(1'bX), .A1(1'bX), .B1(n30), .C1(1'bX), .D1(1'b1), .DI1(n163), - .DI0(n164), .A0(1'bX), .B0(n31), .C0(1'bX), .D0(1'b1), .FCI(n201), - .M0(1'bX), .CE(1'bX), .CLK(clk_c), .LSR(reset_c), .FCO(n202), .F1(n163), - .Q1(n30), .F0(n164), .Q0(n31)); - SCCU2C #(.CLKMUX("SIG"), .CEMUX("VHI"), .LSRMUX("SIG"), - .CCU2_INJECT1_0("NO"), .CCU2_INJECT1_1("NO"), .GSR("DISABLED"), - .INIT0_INITVAL(16'h0000), .INIT1_INITVAL(16'h33FF), .REG1_SD("VHI"), - .CHECK_DI1(1'b1), .CHECK_LSR(1'b1)) SLICE_16( .M1(1'bX), .A1(1'bX), - .B1(n32), .C1(1'bX), .D1(1'b1), .DI1(n165), .DI0(1'bX), .A0(1'bX), - .B0(1'bX), .C0(1'bX), .D0(1'bX), .FCI(1'bX), .M0(1'bX), .CE(1'bX), - .CLK(clk_c), .LSR(reset_c), .FCO(n201), .F1(n165), .Q1(n32), .F0(), .Q0()); - pwm pwm_I( .PADDO(pwm_c_31), .pwm(pwm)); - clk clk_I( .PADDI(clk_c), .clk(clk)); - reset reset_I( .PADDI(reset_c), .reset(reset)); - VHI VHI_INST( .Z(VCCI)); - PUR PUR_INST( .PUR(VCCI)); - GSR GSR_INST( .GSR(VCCI)); -endmodule - -module pwm ( input PADDO, output pwm ); - - sapiobuf pwm_pad( .I(PADDO), .PAD(pwm)); - - specify - (PADDO => pwm) = (0:0:0,0:0:0); - endspecify - -endmodule - -module sapiobuf ( input I, output PAD ); - - OB INST5( .I(I), .O(PAD)); -endmodule - -module clk ( output PADDI, input clk ); - - sapiobuf0001 clk_pad( .Z(PADDI), .PAD(clk)); - - specify - (clk => PADDI) = (0:0:0,0:0:0); - $width (posedge clk, 0:0:0); - $width (negedge clk, 0:0:0); - endspecify - -endmodule - -module sapiobuf0001 ( output Z, input PAD ); - - IBPD INST1( .I(PAD), .O(Z)); -endmodule - -module reset ( output PADDI, input reset ); - - sapiobuf0001 reset_pad( .Z(PADDI), .PAD(reset)); - - specify - (reset => PADDI) = (0:0:0,0:0:0); - $width (posedge reset, 0:0:0); - $width (negedge reset, 0:0:0); - endspecify - -endmodule diff --git a/impl1/scratchproject.prs b/impl1/scratchproject.prs deleted file mode 100644 index b6e5d18..0000000 --- a/impl1/scratchproject.prs +++ /dev/null @@ -1,99 +0,0 @@ -#-- Synopsys, Inc. -#-- Version O-2018.09-SP1 -#-- Project file /home/hadaq/mmichalek/lattice/simplified/impl1/scratchproject.prs - -#project files -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/modules2.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/top2.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" -add_file -verilog "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" -add_file -vhdl -lib work "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd" - - - -#implementation: "impl1" -impl -add /home/hadaq/mmichalek/lattice/simplified/impl1 -type fpga - -# -#implementation attributes - -set_option -vlog_std v2001 -set_option -num_critical_paths 3 -set_option -project_relative_includes 1 -set_option -hdl_define -set SBP_SYNTHESIS -set_option -include_path {/home/hadaq/mmichalek/lattice/simplified/impl1/} -set_option -include_path {/home/hadaq/mmichalek/lattice/simplified} - -#device options -set_option -technology ECP5UM5G -set_option -part LFE5UM5G_45F -set_option -package BG381C -set_option -speed_grade -8 -set_option -part_companion "" - -#compilation/mapping options -set_option -top_module "top_tf" - -# hdl_compiler_options -set_option -distributed_compile 1 - -# mapper_without_write_options -set_option -frequency 200 -set_option -srs_instrumentation 1 - -# mapper_options -set_option -write_verilog 0 -set_option -write_vhdl 0 - -# Lattice XP -set_option -maxfan 1000 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 1 -set_option -forcegsr auto -set_option -fix_gated_and_generated_clocks 1 -set_option -rw_check_on_ram 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 -set_option -Write_declared_clocks_only 1 - -# NFilter -set_option -no_sequential_opt 0 - -# sequential_optimization_options -set_option -symbolic_fsm_compiler 1 - -# Compiler Options -set_option -compiler_compatible 0 -set_option -resource_sharing 0 -set_option -multi_file_compilation_unit 1 - -# Compiler Options -set_option -auto_infer_blackbox 0 - -#automatic place and route (vendor) options -set_option -write_apr_constraint 1 - -#set result format/file last -project -result_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi" - -#set log file -set_option log_file "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf" - -#design plan options -impl -active "impl1" diff --git a/impl1/stdout.log b/impl1/stdout.log deleted file mode 100644 index 9ecd1a8..0000000 --- a/impl1/stdout.log +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Wed Jun 16 09:19:12 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Wed Jun 16 09:19:12 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Wed Jun 16 09:19:13 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Wed Jun 16 09:19:17 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Wed Jun 16 09:19:17 2021 - -multi_srs_gen completed -# Wed Jun 16 09:19:17 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Wed Jun 16 09:19:17 2021 - -premap completed with warnings -# Wed Jun 16 09:19:18 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Wed Jun 16 09:19:18 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Wed Jun 16 09:19:18 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Wed Jun 16 09:19:25 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak b/impl1/stdout.log.bak deleted file mode 100644 index b7798bc..0000000 --- a/impl1/stdout.log.bak +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Wed Jun 16 07:57:05 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Wed Jun 16 07:57:05 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Wed Jun 16 07:57:06 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Wed Jun 16 07:57:06 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Wed Jun 16 07:57:06 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Wed Jun 16 07:57:10 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Wed Jun 16 07:57:10 2021 - -multi_srs_gen completed -# Wed Jun 16 07:57:10 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Wed Jun 16 07:57:10 2021 - -premap completed with warnings -# Wed Jun 16 07:57:11 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Wed Jun 16 07:57:11 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Wed Jun 16 07:57:11 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Wed Jun 16 07:57:18 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak.1 b/impl1/stdout.log.bak.1 deleted file mode 100644 index df11321..0000000 --- a/impl1/stdout.log.bak.1 +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Wed Jun 16 07:45:06 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Wed Jun 16 07:45:06 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Wed Jun 16 07:45:07 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Wed Jun 16 07:45:07 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Wed Jun 16 07:45:07 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Wed Jun 16 07:45:11 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Wed Jun 16 07:45:11 2021 - -multi_srs_gen completed -# Wed Jun 16 07:45:11 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Wed Jun 16 07:45:11 2021 - -premap completed with warnings -# Wed Jun 16 07:45:12 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Wed Jun 16 07:45:12 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Wed Jun 16 07:45:12 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Wed Jun 16 07:45:19 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak.2 b/impl1/stdout.log.bak.2 deleted file mode 100644 index 9ea0606..0000000 --- a/impl1/stdout.log.bak.2 +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Tue Jun 15 17:59:30 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Tue Jun 15 17:59:31 2021 - -Return Code: 0 -Run Time:00h:00m:01s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Tue Jun 15 17:59:31 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Tue Jun 15 17:59:31 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Tue Jun 15 17:59:31 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Tue Jun 15 17:59:35 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Tue Jun 15 17:59:35 2021 - -multi_srs_gen completed -# Tue Jun 15 17:59:35 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Tue Jun 15 17:59:35 2021 - -premap completed with warnings -# Tue Jun 15 17:59:36 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Tue Jun 15 17:59:36 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Tue Jun 15 17:59:36 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Tue Jun 15 17:59:43 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak.3 b/impl1/stdout.log.bak.3 deleted file mode 100644 index 5827931..0000000 --- a/impl1/stdout.log.bak.3 +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Tue Jun 15 17:47:11 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Tue Jun 15 17:47:11 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Tue Jun 15 17:47:11 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Tue Jun 15 17:47:11 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Tue Jun 15 17:47:11 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Tue Jun 15 17:47:15 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Tue Jun 15 17:47:15 2021 - -multi_srs_gen completed -# Tue Jun 15 17:47:15 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Tue Jun 15 17:47:15 2021 - -premap completed with warnings -# Tue Jun 15 17:47:17 2021 - -Return Code: 1 -Run Time:00h:00m:02s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Tue Jun 15 17:47:17 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Tue Jun 15 17:47:17 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Tue Jun 15 17:47:23 2021 - -Return Code: 1 -Run Time:00h:00m:06s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak.4 b/impl1/stdout.log.bak.4 deleted file mode 100644 index 57cc079..0000000 --- a/impl1/stdout.log.bak.4 +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Tue Jun 15 11:40:10 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Tue Jun 15 11:40:10 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Tue Jun 15 11:40:10 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Tue Jun 15 11:40:10 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Tue Jun 15 11:40:10 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Tue Jun 15 11:40:14 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Tue Jun 15 11:40:14 2021 - -multi_srs_gen completed -# Tue Jun 15 11:40:14 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Tue Jun 15 11:40:14 2021 - -premap completed with warnings -# Tue Jun 15 11:40:15 2021 - -Return Code: 1 -Run Time:00h:00m:01s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Tue Jun 15 11:40:15 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Tue Jun 15 11:40:15 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Tue Jun 15 11:40:24 2021 - -Return Code: 1 -Run Time:00h:00m:09s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/stdout.log.bak.5 b/impl1/stdout.log.bak.5 deleted file mode 100644 index 90ffa6b..0000000 --- a/impl1/stdout.log.bak.5 +++ /dev/null @@ -1,105 +0,0 @@ - - Synplify (R) Premier - - Version O-2018.09-SP1 for RHEL64 - Nov 27, 2018 - - Copyright (c) 1988 - 2018 Synopsys, Inc. - This software and the associated documentation are proprietary to Synopsys, - Inc. This software may only be used in accordance with the terms and conditions - of a written license agreement with Synopsys, Inc. All other use, reproduction, - or distribution of this software is strictly prohibited. - -Starting: synbatch_orig -Install: /opt/synplicity/O-2018.09-SP1 -Hostname: lxhadeb07 -Date: Tue Jun 15 11:16:34 2021 -Version: O-2018.09-SP1 - -Arguments: -product synplify_premier -batch s1_impl1_synplify.tcl -ProductType: synplify_premier - -License checkout: synplifypremier -License: synplifypremier from server lxcad03.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: hdl_info_gen in foreground - -License granted for 4 parallel jobs -Generating HDL info... -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf - -hdl_info_gen completed -# Tue Jun 15 11:16:34 2021 - -Return Code: 0 -Run Time:00h:00m:00s -log file: "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr" -Running: impl1 in foreground - -Running proj_1|impl1 - -Running Flow: compile (Compile) on proj_1|impl1 -# Tue Jun 15 11:16:34 2021 - -Running Flow: compile_flow (Compile Process) on proj_1|impl1 -# Tue Jun 15 11:16:34 2021 -License granted for 4 parallel jobs - -Running: compiler (Compile Input) on proj_1|impl1 -# Tue Jun 15 11:16:34 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs - -compiler completed -# Tue Jun 15 11:16:38 2021 - -Return Code: 0 -Run Time:00h:00m:04s - -Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1 -# Tue Jun 15 11:16:38 2021 - -multi_srs_gen completed -# Tue Jun 15 11:16:38 2021 - -Return Code: 0 -Run Time:00h:00m:00s -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_mult.srs to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srs -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Compile Process on proj_1|impl1 - -Running: premap (Premap) on proj_1|impl1 -# Tue Jun 15 11:16:38 2021 - -premap completed with warnings -# Tue Jun 15 11:16:40 2021 - -Return Code: 1 -Run Time:00h:00m:02s -Complete: Compile on proj_1|impl1 - -Running Flow: map (Map) on proj_1|impl1 -# Tue Jun 15 11:16:40 2021 -License granted for 4 parallel jobs - -Running: fpga_mapper (Map & Optimize) on proj_1|impl1 -# Tue Jun 15 11:16:40 2021 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srm - -fpga_mapper completed with warnings -# Tue Jun 15 11:16:47 2021 - -Return Code: 1 -Run Time:00h:00m:07s -Complete: Map on proj_1|impl1 -Copied /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srr to /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.srf -Complete: Logic Synthesis on proj_1|impl1 -TCL script complete: "s1_impl1_synplify.tcl" -exit status=0 -exit status=0 -Save changes for project: -/home/hadaq/mmichalek/lattice/simplified/impl1/proj_1.prj -batch mode default:no -License checkin: synplifypremier diff --git a/impl1/synlog.tcl b/impl1/synlog.tcl deleted file mode 100644 index 6874eb2..0000000 --- a/impl1/synlog.tcl +++ /dev/null @@ -1 +0,0 @@ -run_tcl -fg s1_impl1_synplify.tcl diff --git a/impl1/synlog/distcomp0.tlg.rptmap b/impl1/synlog/distcomp0.tlg.rptmap deleted file mode 100644 index ba28008..0000000 --- a/impl1/synlog/distcomp0.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork//distcomp/distcomp0/distcomp0.tlg,distcomp0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/impl1/synlog/distcomp1.tlg.rptmap b/impl1/synlog/distcomp1.tlg.rptmap deleted file mode 100644 index ae29ab6..0000000 --- a/impl1/synlog/distcomp1.tlg.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork//distcomp/distcomp1/distcomp1.tlg,distcomp1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages. diff --git a/impl1/synlog/incr_compile.rpt.rptmap b/impl1/synlog/incr_compile.rpt.rptmap deleted file mode 100644 index dbb7528..0000000 --- a/impl1/synlog/incr_compile.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report diff --git a/impl1/synlog/linker.rpt.rptmap b/impl1/synlog/linker.rpt.rptmap deleted file mode 100644 index 74ed6b7..0000000 --- a/impl1/synlog/linker.rpt.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synwork/s1_impl1_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind diff --git a/impl1/synlog/report/metrics.db b/impl1/synlog/report/metrics.db deleted file mode 100644 index 1701ec64be7e9de55993dee36b4e578db0d7a9d3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 40960 zcmeI5U2NOd6@aD0wk{=6jFUL7>bjxfq>h_fAtlQ{YZ}jW+$=v{ySiO}1D2L3o3SLS zB$dEzior&KJuJh323Ub&F9VEWYhSvDWgEJOzU^@XiflvovSPr1VJ~|v&<;B!Ws$rT zB_(d_{v0K?N%5R>&-r-nCGX|c)$;c)siwl0G`%95d@gbz5{*W_&GV7S^Y2C?kvRP9 zycpQ%+1Y`=QO|bBCfLXv{)mO640AogJ(v1Lim*>7ZzlecI30fx-oh6WKmter2_OL^ zfCRo#1U4@-vBCNI=+>esuap&2t*F&isZiDm>yoaNWmDCv#+q6)!jHrko?M)NYLS0x z{?SW|{8+f)*a>aric&E7tFm5Lll6!Aiel<&!QHFCz5=lnUbkXC;0iH|~GY;bfmx;19|Sb&T&by=;NhG#S8_ttY{Ph6hsjSWsrM7Ko8 zWxGCrPgfP)fEwY{4|l(ha-I_3lL&+!FZ7~fsH;^;t(G*;X0P9G&yhWGd1!xZa9|+1 zmA0W*RHI=1^!S~$-r5uIgneG1YsInzZBR`uE1u2$eqTLD_Qd65(b(Y7P;~344OFjJ zp=D4SfA;xZZM?e|ZnCM{krexSUuq(?pL>N{V*i$UhkciOAoU6NtJGHN1?~g(^>5Tg z8G}UvNB{{S0VIF~kN^@u0!RP}d|m_|I=MZ*eTA??!$YGiQ>fLgZsK%C$WIA^U??!o zQ8Y@mRavUYH5m6gzFi>f@bFNYWpqU@Tf$-nBwgXMT3uK46Wg*acQjP4(Sg>5v73kO z;z6`gJY{i5Qao|Oi_c10`JL0_B+({BjO?<4F4 z#||$s@P=Aam7>%*(n*tVST3H65_TL+Ty{;^E{S19Q?54++5La66ybi)y}^CRmAE&) zW+xfLK>|ns2_OL^fCP{L5oUcjP%14ftn((SCopTZ-|q*j3CYm zGvd;t_N0UH@gG889mL>Sx>qcpnVJ>_F}L)nXKDubVdNY;!m*>zG0+QNk;E$I`AkmCirJ}#XSMrp#0WcZoV5awb@S3=i}|OQ^5>+< z{A131iP0O3EnvA$33!~g`u|bxFA?~UFC>5jkN^@u0!RP}AOR$R1dsp{KmthMD@EW0 zOb?jjtg!)S@`9w5tj`@Nx(;&<>;*K8yfaE*_5TktYZ2~`T%CJ3^=ay6>M;8zJCb}e z`CPImp(KvPe;vOPPcrX=5WbKA5g^ckOV`_LrqXB#tx6gb%rPWCeeYn4HdlT!gZEq$zN)d{Bnd#jbN zORVGTs;>;&SCRI$3v-+IB^mZS#J;H#Sk|$yR+Cj-s#n*m+O?`=)6=EenrtY6Gp5z7 z1qENR)`#S6Ro>DycykSw>%OMw3J+Pt!w0FgtAKk&Dadt0ful+Ty3HB+T*Xu z25%_lt1*TZt%RBLlv-2`D-VjFQK37`tYt>+a(C>%*2mcS;49p&N>WWW*FK}-Ax9hV zp?JBGu9p3^UWQ$?V(<0DE|;-@gHS5^&poDJ<_m>d2?@>CSZ1n)6nP5(a*B|Xll zg;iK`)r5sHTi`vvaL&n1f6~vu^#4)NK2Jc~kYI7Y)fUPH*(k_Ga0;v}!=kH}&=WAJ zU<@?tmL{xZXf16Ctz{r0Z^2C|-qd)*)O2}OfqK8H8c>amY3T4eV6)Bf}8j&KH32g*BzH?)3j}N4VQxsP9-954@w0u4j#n zNF@2QkuP?Q{vy!9nAlt$uTqdCiKQ>$Hvu(EkiwCCMV6FKopd0!Zbw?~Fs z=vqPVd=SYm|B4fKvn)GuF_X`Wv{z3!aWp0A;B%SD$yr)yh*Ih%{&*w)TDd%Pec{r@ z$Cs%OQMKif^~D!|%i+<%Rw$qN^A4X-{RXdKro?$C^ia(pzhLq(fA3(V8=lNhoqPgM zggfV%^YLUZGelkbrJ*7!A3^pYT2Ra(*%=02g=4qaE4Q!imf+ykT zQe>V6+S*tM(QmP2elTq>xz@Z;&<1RzPLIadvYt(nd73G$OGBN? z0VIF~zUl-XxtHWmTK6cVIk+=%rn#xBh9cR&?5k?4u_0zM--Wt62d>qq7x}N_Lilac z#F_A8CAkb=BV_#wx%5XOhzkQ`u?fu8 z3pLXYoOGCMe6HY%hsee*!8OiI+b|C9E)0r!Z~&>;zq>Hp0@{Uf`2eZYXM?&;_9hv1 zsACeZaHLM33(7`U=G%sl+D!;9rjUBL!tN#n*L>R$l7SHDJ9G~w`cUVykO+i8+vv)C z+YsWr3Bkn_b{3f3gy5QQ7s5*fsSJoP|E>I*hacT$QSf_rHaGvajCH|$aD-CY=N0d2$R*iDzzrjKqaf|uT^Mfe+F2!JMCyrMF}k}j+ydH#@qdpHNCp4^ diff --git a/impl1/synlog/report/s1_impl1_compiler_errors.txt b/impl1/synlog/report/s1_impl1_compiler_errors.txt deleted file mode 100644 index 9b24368..0000000 --- a/impl1/synlog/report/s1_impl1_compiler_errors.txt +++ /dev/null @@ -1,2 +0,0 @@ -@E: CH103 : | One or more distribution nodes failed to compile. - diff --git a/impl1/synlog/report/s1_impl1_compiler_notes.txt b/impl1/synlog/report/s1_impl1_compiler_notes.txt deleted file mode 100644 index c162548..0000000 --- a/impl1/synlog/report/s1_impl1_compiler_notes.txt +++ /dev/null @@ -1,34 +0,0 @@ -@N|Running in 64-bit mode -@N|Running in 64-bit mode -@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb. -@N|Running in 64-bit mode -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -@N|Running in 64-bit mode -@N|Running in 64-bit mode - diff --git a/impl1/synlog/report/s1_impl1_compiler_runstatus.xml b/impl1/synlog/report/s1_impl1_compiler_runstatus.xml deleted file mode 100644 index 6a28a3b..0000000 --- a/impl1/synlog/report/s1_impl1_compiler_runstatus.xml +++ /dev/null @@ -1,41 +0,0 @@ - - - - - - /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_compiler.srr - Synopsys HDL Compiler - - - Completed - - - - 33 - /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_notes.txt - - - 8 - /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_warnings.txt - - - 0 - /home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_compiler_errors.txt - - - - - - - 00h:00m:03s - - - - - - - 1623827956 - - - \ No newline at end of file diff --git a/impl1/synlog/report/s1_impl1_compiler_warnings.txt b/impl1/synlog/report/s1_impl1_compiler_warnings.txt deleted file mode 100644 index 187dc16..0000000 --- a/impl1/synlog/report/s1_impl1_compiler_warnings.txt +++ /dev/null @@ -1,9 +0,0 @@ -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg - diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml deleted file mode 100644 index b466386..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_area_report.xml +++ /dev/null @@ -1,26 +0,0 @@ - - - - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt -Resource Usage - - -934 - - -186 - - -4 - - -0 - - -180 - - diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt deleted file mode 100644 index 085063d..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt +++ /dev/null @@ -1,21 +0,0 @@ -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MF284 |Setting synthesis effort to medium for the design -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog)) -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing. -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml deleted file mode 100644 index a357e2a..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_opt_report.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt b/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt deleted file mode 100644 index d7cf118..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_resourceusage.rpt +++ /dev/null @@ -1,36 +0,0 @@ -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 - -Details: -AND2: 8 -CCU2C: 121 -EHXPLLL: 1 -FD1P3AX: 69 -FD1P3BX: 8 -FD1P3DX: 232 -FD1P3IX: 50 -FD1S3AX: 321 -FD1S3BX: 4 -FD1S3DX: 164 -FD1S3IX: 41 -FD1S3JX: 10 -GSR: 1 -IB: 11 -IFS1P3DX: 5 -INV: 20 -OB: 173 -OBZ: 2 -OFS1P3DX: 17 -OFS1P3IX: 13 -OR2: 4 -ORCALUT4: 180 -PDPW16KD: 4 -PUR: 1 -ROM16X1A: 96 -VHI: 25 -VLO: 6 -XOR2: 72 diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml deleted file mode 100644 index edd26c1..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_fpga_mapper.srr - - - -Completed - - - -21 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_notes.txt - - - -13 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt - - - -0 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_fpga_mapper_errors.txt - - - -0h:00m:07s - - -0h:00m:07s - - -153MB - - -1623827965 - - - diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml b/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml deleted file mode 100644 index 41bed49..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_timing_report.xml +++ /dev/null @@ -1,53 +0,0 @@ - - - - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_fpga_mapper.srr -START OF TIMING REPORT - - -Clock Name -Req Freq -Est Freq -Slack - - -pll0|CLKOP_inferred_clock -200.0 MHz -1037.3 MHz -4.036 - - -pll0|CLKOS2_inferred_clock -200.0 MHz -1037.3 MHz -4.036 - - -pll0|CLKOS3_inferred_clock -200.0 MHz -158.6 MHz --0.652 - - -pll0|CLKOS_inferred_clock -200.0 MHz -1037.3 MHz -4.036 - - -top_tf|rd_clk -200.0 MHz -256.6 MHz -1.103 - - -System -200.0 MHz -527.3 MHz -3.103 - - diff --git a/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt b/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt deleted file mode 100644 index 81a1838..0000000 --- a/impl1/synlog/report/s1_impl1_fpga_mapper_warnings.txt +++ /dev/null @@ -1,13 +0,0 @@ -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. -@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. -@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. -@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. -@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. diff --git a/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml b/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml deleted file mode 100644 index 18b0dca..0000000 --- a/impl1/synlog/report/s1_impl1_hdl_info_gen_runstatus.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - Running - - - - - - - 0 - 0 - - 0 - - - - - - - - - - - \ No newline at end of file diff --git a/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt b/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt deleted file mode 100644 index 0af1174..0000000 --- a/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt +++ /dev/null @@ -1,29 +0,0 @@ - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s) -4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s) -0 instances converted, 895 sequential instances remain driven by gated/generated clocks - -===================================== Non-Gated/Non-Generated Clocks ====================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------ -@KP:ckid0_8 rd_clk Unconstrained_port 64 trb_adapter_inst.FEE_DATA_WRITE_OUT -=========================================================================================================== -======================================================================================== Gated/Generated Clocks ======================================================================================== -Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -@KP:ckid0_1 pll0inst.PLLInst_0.CLKOS3 EHXPLLL 787 reset_dl[2:1] Black box on clock path -@KP:ckid0_3 pll0inst.PLLInst_0.CLKOS2 EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2] Black box on clock path -@KP:ckid0_5 pll0inst.PLLInst_0.CLKOS EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1] Black box on clock path -@KP:ckid0_7 pll0inst.PLLInst_0.CLKOP EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0] Black box on clock path -======================================================================================================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - diff --git a/impl1/synlog/report/s1_impl1_premap_errors.txt b/impl1/synlog/report/s1_impl1_premap_errors.txt deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synlog/report/s1_impl1_premap_notes.txt b/impl1/synlog/report/s1_impl1_premap_notes.txt deleted file mode 100644 index 26ac484..0000000 --- a/impl1/synlog/report/s1_impl1_premap_notes.txt +++ /dev/null @@ -1,25 +0,0 @@ -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -@N: MF284 |Setting synthesis effort to medium for the design -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. diff --git a/impl1/synlog/report/s1_impl1_premap_opt_report.xml b/impl1/synlog/report/s1_impl1_premap_opt_report.xml deleted file mode 100644 index 35403c5..0000000 --- a/impl1/synlog/report/s1_impl1_premap_opt_report.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - -1 / 4 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_combined_clk.rpt -START OF CLOCK OPTIMIZATION REPORT - - - diff --git a/impl1/synlog/report/s1_impl1_premap_runstatus.xml b/impl1/synlog/report/s1_impl1_premap_runstatus.xml deleted file mode 100644 index e28a1f7..0000000 --- a/impl1/synlog/report/s1_impl1_premap_runstatus.xml +++ /dev/null @@ -1,46 +0,0 @@ - - - - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/s1_impl1_premap.srr - - - -Completed - - - -25 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_notes.txt - - - -8 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_warnings.txt - - - -0 - -/home/hadaq/mmichalek/lattice/simplified/impl1/synlog/report/s1_impl1_premap_errors.txt - - - -0h:00m:01s - - -0h:00m:00s - - -145MB - - -1623827958 - - - diff --git a/impl1/synlog/report/s1_impl1_premap_warnings.txt b/impl1/synlog/report/s1_impl1_premap_warnings.txt deleted file mode 100644 index e5084c9..0000000 --- a/impl1/synlog/report/s1_impl1_premap_warnings.txt +++ /dev/null @@ -1,8 +0,0 @@ -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. diff --git a/impl1/synlog/s1_impl1_compiler.srr b/impl1/synlog/s1_impl1_compiler.srr deleted file mode 100644 index f964ee1..0000000 --- a/impl1/synlog/s1_impl1_compiler.srr +++ /dev/null @@ -1,279 +0,0 @@ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! -File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -Running optimization stage 1 on fifo_colector ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -Running optimization stage 1 on tdc_channel_fifo_out ....... -Running optimization stage 1 on top_tf ....... - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] - -Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Divided design in to 1 groups -@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog " -Compiling work_top_tf_verilog as a separate process -Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s - -Distributed Compiler Report -*************************** - -DP Name Status Start time End Time Total Real Time Log File ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -work.top_tf.verilog Success 0h:00m:00s 0h:00m:01s 0h:00m:01s /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log -============================================================================================================================================================================== -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB) - -Process took 0h:00m:02s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] diff --git a/impl1/synlog/s1_impl1_compiler.srr.db b/impl1/synlog/s1_impl1_compiler.srr.db deleted file mode 100644 index f9b8e7719e8d30eea58f5d8da5f7ff8df79372c3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 zcmeI2&vV;E6vzD|j*~dHQ`!*Pl2#2D7--~`{38w*(j=q>(}bj?nc;^}thJ+wEV#AQJ#=7(0|)+ta^O8Vb{x=#cpRpk>3WitY|DOMfA;O$eXFv^dD4hKBdFMUeF&>${@LL+*jb^`#z@K;s z0)l`bAP5Kof`A|(2nYg#fFK|U2m&uT0TxY8O;1PtcbUFz(FXNAy-vN(F}AqAyl`h( zy0dVjvMhC8ebY3g`?_1*(cO0>%d~foo*iCt^un%b_gvhBPntG+D*@D_*=NXpDEln^ zB)vZVczh-GL#jCT)0i^)t4eJq z(`vKOY82|T_h;ry#rYC8gdA+_+iZt==0nr2OAW_pSyWnF{6tv<&G0+7UEST6_8fP2 z)^-?W%YJkk?4PFt*(b#u2*8%8p$gt#A{*+BEv|;w&qBjopkeMr4NH6tm(M^0DWe8x z`5e~N6Es{p3k^YEkdyji?S#IFT|^D_f&8IdKn~cFe5gOHEv?-p#SfQw4iS58a1kXy z0HXpygo{{T{fHE|$O1>i*HfrL8wkW)paENw3k9*Yx~_2SAG`|o&wW0S{bB(l1GeQ* z^CwuJ9NfBE1pf2bhFiaNdz1IuFM##zVC9;Ke&O~KkGvl}59U*iF8Up(LFFCY z(C^8Oh6!_qMR#ROXUwcp*)tmutZODUWacy#jK_+Ku7@otg>q-^wgz9FP)mkhX1VX|BGfIW5K$7n=Z7Jt6C~-E{~lP^IPx`YN=XXu({wu9^0Io`_5qL`*$8 z13*f zb$?Skty|LJ5WzU6*|ff=yEZJ*VF5m#L`n2)B*Bb>l5!aD`;pX@^Kcl{r0xc4RJC+^ zK;5|yjF;yXl#oBTO_{Xas%fr4ZLOwTkZ9E<(~}_gKp?=28na#7ejg zW6#Y?h@XIT|M_|er0wx5cyIm+r104XnZGg(k^hVQKgj$={y!6B{v!X!m7>W1MgAYM zBP;TMk^dj=8T~u45cz+1L#=l&LgfF!y`CWP7x}-)|8Yb5Xs7pZOG4!TBL6>rPvZaZ zl9xUI$BjFJ`F|pPH8DZtnSnbxSEDLG`PADx)&VZQdqiWdGmW$x`s)|vSJ10GLL*a#8 zoeMdYD-W)Lka)FkDxIj!f6iW9q95H_b)*`Jo diff --git a/impl1/synlog/s1_impl1_compiler.srr.rptmap b/impl1/synlog/s1_impl1_compiler.srr.rptmap deleted file mode 100644 index 6d8e7e9..0000000 --- a/impl1/synlog/s1_impl1_compiler.srr.rptmap +++ /dev/null @@ -1 +0,0 @@ -./synlog/s1_impl1_compiler.srr,s1_impl1_compiler.srr,Compile Log diff --git a/impl1/synlog/s1_impl1_fpga_mapper.srr b/impl1/synlog/s1_impl1_fpga_mapper.srr deleted file mode 100644 index ca796af..0000000 --- a/impl1/synlog/s1_impl1_fpga_mapper.srr +++ /dev/null @@ -1,1241 +0,0 @@ -# Wed Jun 16 09:19:18 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog)) -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:02s -0.86ns 187 / 525 - 2 0h:00m:02s -0.86ns 184 / 525 -@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing. -Timing driven replication report -Added 1 Registers via timing driven replication -Added 0 LUTs via timing driven replication - - 3 0h:00m:04s -0.74ns 186 / 526 - - - 4 0h:00m:04s -0.74ns 186 / 526 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB) - -Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - -@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. -@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. -@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. -@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. -@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Wed Jun 16 09:19:25 2021 -# - - -Top view: top_tf -Requested Frequency: 200.0 MHz -Wire load mode: top -Paths requested: 3 -Constraint File(s): -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: -0.652 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------ -pll0|CLKOP_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_1 -pll0|CLKOS2_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_3 -pll0|CLKOS3_inferred_clock 200.0 MHz 158.6 MHz 5.000 6.305 -0.652 inferred Inferred_clkgroup_0 -pll0|CLKOS_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_2 -top_tf|rd_clk 200.0 MHz 256.6 MHz 5.000 3.897 1.103 inferred Inferred_clkgroup_4 -System 200.0 MHz 527.3 MHz 5.000 1.897 3.103 system system_clkgroup -=================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------ -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------ -System pll0|CLKOS3_inferred_clock | 5.000 3.104 | No paths - | No paths - | No paths - -System top_tf|rd_clk | 5.000 3.104 | No paths - | No paths - | No paths - -pll0|CLKOS3_inferred_clock System | 5.000 3.782 | No paths - | No paths - | 5.000 4.247 -pll0|CLKOS3_inferred_clock pll0|CLKOS3_inferred_clock | 5.000 0.197 | 5.000 2.602 | 2.500 1.172 | 2.500 -0.653 -pll0|CLKOS3_inferred_clock top_tf|rd_clk | Diff grp - | No paths - | No paths - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOP_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS2_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -top_tf|rd_clk System | 5.000 3.807 | No paths - | No paths - | No paths - -top_tf|rd_clk pll0|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -top_tf|rd_clk top_tf|rd_clk | 5.000 1.104 | No paths - | No paths - | No paths - -=============================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: pll0|CLKOP_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS2_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -============================================================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -=============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS3_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast pll0|CLKOS3_inferred_clock FD1S3AX Q valid_fast 0.863 -0.652 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX Q window[2] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX Q window[5] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX Q window[6] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX Q window[7] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX Q window[3] 0.838 0.720 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX Q window[4] 0.838 0.720 -=============================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[7] 2.289 -0.652 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[5] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[6] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX PD window_6[2] 2.183 -0.581 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[3] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[4] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[1] 2.289 -0.475 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -============================================================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.942 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -0.652 - - Number of logic level(s): 7 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.992 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.992 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.599 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.599 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.942 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.942 - -============================================================================================================================================= - - -Path information for path number 2: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - -Path information for path number 3: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B0 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: top_tf|rd_clk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------ -fifo_colector_inst.fifo40_inst.FF_12 top_tf|rd_clk FD1S3DX Q w_gcount_r29 0.883 1.103 -fifo_colector_inst.fifo40_inst.FF_13 top_tf|rd_clk FD1S3DX Q w_gcount_r28 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_14 top_tf|rd_clk FD1S3DX Q w_gcount_r27 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_15 top_tf|rd_clk FD1S3DX Q w_gcount_r26 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_16 top_tf|rd_clk FD1S3DX Q w_gcount_r25 0.863 1.169 -fifo_colector_inst.fifo40_inst.FF_17 top_tf|rd_clk FD1S3DX Q w_gcount_r24 0.838 1.194 -fifo_colector_inst.fifo40_inst.FF_18 top_tf|rd_clk FD1S3DX Q w_gcount_r23 0.798 1.234 -fifo_colector_inst.fifo40_inst.FF_19 top_tf|rd_clk FD1S3DX Q w_gcount_r22 0.753 1.278 -fifo_colector_inst.fifo40_inst.FF_20 top_tf|rd_clk FD1S3DX Q w_gcount_r21 0.798 1.841 -fifo_colector_inst.fifo40_inst.FF_21 top_tf|rd_clk FD1S3DX Q w_gcount_r20 0.753 1.887 -================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_1 top_tf|rd_clk FD1S3BX D empty_d 4.789 1.103 -fifo_colector_inst.fifo40_inst.FF_62 top_tf|rd_clk FD1P3DX D ircount_9 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_63 top_tf|rd_clk FD1P3DX D ircount_8 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_64 top_tf|rd_clk FD1P3DX D ircount_7 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_65 top_tf|rd_clk FD1P3DX D ircount_6 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_66 top_tf|rd_clk FD1P3DX D ircount_5 4.789 2.457 -fifo_colector_inst.fifo40_inst.FF_67 top_tf|rd_clk FD1P3DX D ircount_4 4.789 2.457 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR5 rptr_0 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR6 rptr_1 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR7 rptr_2 3.223 2.470 -========================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r1 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B1 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.640 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.148 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_13 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_13 FD1S3DX Q Out 0.838 0.838 - -w_gcount_r28 Net - - - - 3 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD1 In 0.000 0.838 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.491 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.491 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.014 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.014 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.798 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.798 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.857 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.857 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.916 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.916 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 2.975 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 2.975 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.034 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.034 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.640 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.640 - -============================================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 -Block Rams : 4 of 108 (3%) - - -Details: -AND2: 8 -CCU2C: 121 -EHXPLLL: 1 -FD1P3AX: 69 -FD1P3BX: 8 -FD1P3DX: 232 -FD1P3IX: 50 -FD1S3AX: 321 -FD1S3BX: 4 -FD1S3DX: 164 -FD1S3IX: 41 -FD1S3JX: 10 -GSR: 1 -IB: 11 -IFS1P3DX: 5 -INV: 20 -OB: 173 -OBZ: 2 -OFS1P3DX: 17 -OFS1P3IX: 13 -OR2: 4 -ORCALUT4: 180 -PDPW16KD: 4 -PUR: 1 -ROM16X1A: 96 -VHI: 25 -VLO: 6 -XOR2: 72 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB) - -Process took 0h:00m:07s realtime, 0h:00m:07s cputime -# Wed Jun 16 09:19:25 2021 - -###########################################################] diff --git a/impl1/synlog/s1_impl1_fpga_mapper.srr.db b/impl1/synlog/s1_impl1_fpga_mapper.srr.db deleted file mode 100644 index 3d740d388d07e89b4be29f3888159bd85eb74f51..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeHOL2w&M6_sT>ik-;LZZ_);A*451hz+r<8OciGB?Y!OPN;P@*~Da*q*6m`re*hP zG^5On_DD0D z>Hht?`}hC--@o=l@JZJ@9r0M| zt-mMn)WG;JWB7}X2!RNJ2!RNJ2!RNJ2!RNJ2!RNJ2!RNJ2!YoefnXppaq{Fq?frn~ zZBY`w&sT-t{ERQ&yga{hnXSw(EMI2LyOYvlRqmN<+&jl?=@d7w8joz=C`xC`!)3fF zonVR_{P_5ng#GaNf5*QZ`*renhyQr!$)VAaCnKYYCy7JD{~YE+{}}vj{LaAJuS*xz z=Z_wosEt43C*lhqX&L?W%$i#gGi%)9_h(8a3BYYpoUwTjNK?%CvQ)NZK?-Z8Odl>4u?qQhe28M6+Acp6= zh9SD=rH{iOA4yCkYv!@|wI%KR#U-}_HK?UoenXuxkuZz6ErSi_mW9Uy*JG1sFI_r2 z#VU?wm@fBxVQ6epI;<+i`W#z#ys3k6>UcQ4+1zM#vumo=jeCDLPMZWe`Fk6gx~YoJZV17-@_R-?g^J}rrx718t1 zG3OYnQ~HSX)}}6Ua5pc4bs<9C)Dn=R>q)ykT?4nOP~zyR?NfcYvdefHTEBXG+`P-t6A?R*<$x zHB7$AL5Tmp5QOjKq>u$BvAdf2$s~eZ{ zoLs)d3KRVJA%@f7QHsqUg=0Vd#rRLgSH}Jt`TqbU7Ww~?|G$UrnV0Un z*5@PtUu~DYz&=#u|38lW|8RpM^8dTP`_rj6+dJDok^lc}Fk_p2t^d3Gr?oo(VKF_w z{dYU^|DOqFJ=On_|4;k=ZO-g=zHsFKKNqsd|9{o~|K>Ic`Txm*vDnxb$p?qCqyHX_ zjr`)^&l5jAFgNtC!9T=*fS+EYqkfgq9`GaC-B3xWS1EY-)OM%}DQ;aR!)?+qtY&15 zR3X3Pc4W_(Q}wH-dKSvreuMIBJqu;7-=I9%vrwMzHz>c_vrt~>FDPpdPXNk9ok$}4 z6W4OVD+vtENP*+Bn=sXOR&Kk)*JdQ|Xz|q^e&v-QkbWr$ybL?Pa-8B-w~ob^KGkyB z6|htqu_#0XiSN>4zaU;1hMvB6eL;l}iT{x&u8Ut5reYzc*bQ4y%&5ta0cB9aj9}m^ zdNN-LM2aC0Dipw9jaJA-$6)qD=A3N>2nCH;yim(fC_1H6|!rx2piGS-5NZW zFhk2n1!8wJdDdmHMqDo2d(8=fH}=H3D!=GR*u0wRb<5o$1{(J7+s& z)OAp__VO8Z_4&8=3&RfBv7KVrLD5~o@YsG~2m9*B+z zf&E0lOOrix4HofAM%P>XokkV{89}C9v0x=RNKa@oe5V6sB6k7r#sURJc-+JG#*nxkJQT7ILke6;;nP*kuSa|Z;GQ!FlLOo0o z5XeNiwvyG;A?r>$1>t#Ul9C?A4zcAv_lTcV44VlmyL2r!n@Xo0zhw`?va-1caY+ns z+7ghlRSIl;)yA-x%|wpc@o7Tk*me?>Z9Dz>;_`>rZ|N}ILg7NP)QgBi#5yWj<-*_# zHP5GvnO2fX?VWQZ+tJ<0)^*XKptp$jt=)@uqwAuTlFD)TMehw|llKjg%QWQKTxDp3`(X>*)o|&|=ZS4(6h)764@d!&_y+tJ_z@gLPjCW>Xb%P=k^V4a8q=F&s&5cCkrV+rZYB96 zJc_I-Hu-Tgy`;cy3Z(_6TCKe^iH@k91m*k_EuFiy;gIu0xhRX930F&?7BZ8=36x># zSj8d6Xhk&uQo!Cu?VwN12|@ec~aB1WmsD!IEMt&aqu5 zwNZMTHsfoC`jP_avXNP^^bPdY#3Rv5+vUg>F}Y{;*Jk;LUspi7y#!<|XX4l&5r zFfec6jZ%tgD+6x)8{Py-n6$opu2DK|84-ll6%T))C)%xaP$~=U=7~6#435^@2j?s< z+JrkNJBB!Lmt2zsf#;oO?yq(Ga-Yp_n@|^PvaJ>E*xzl^=Pv*N0RR8&y?b+_*w#4w zcl;F8V7(L0uT^MirG2KSMmExsBKokRv@C1*sWNOCwsoYDil|v4G3?5aH@vQ97!{%z z+R&4S1zRySgXkYB9xqmkn&}y$Z4^tDu-pmcYALvuDyggu4D%yn)@azPFmp`U@_m#q ziJC?~^Wx2PT=J-=B)Uk79yR$Q!YL-qBV=eKgqF;rop>dYdNk2XW-?Hyk-!3VVpUp7 z#ria~henH7+L2Y!L|Zh7QQ?P%r*##BR6Jv-m1OFPRzkUGR;$gYlN#&IJX*3W`)J%G zbRzdV>X?=iVkwlCI;D?8t4l3Y4uXIhCC@7nY7n!V5XOHpq*fQ!(j6NgEkz`@t?5TH zPvLXjkFY-?CKk~YTj%W~3UGzinMy+Y$Q%k5em`J5flru2gD_KJ#E`p`CZ#ijiA2$e zZ7Bdnw>6s`@p{qJ@NY=lv@}4SZP?62ym&*44odtm8CpfHYmgSL=#?RXlT$toD?`Jw zTUv!2X`&?>6`Syg1Hf^a#^V8PSFVUC~5BbE zdce$~#XOO=_`Xg{1P+JlmDaFD-~<(`Vho42)&kreRV+gkZJtz+&J5Bulwrm2Dw@n2 zGQ;&(4Wa7n0FJ%?B+oym z?C*xAMH1@i@_!i6i#C2CjjqQ;E$v zj`?Q}oBAB9M^b#jnrLtLNO)lfPAG#r%39x4&;!?*|WA4!KB9`HJ%7yg@`^y2JSMw2bnG^Xj zXoJ}2qKV@_KxgSgxz{Vd>0Otu_lH+|61;L*e$x+1qc^2d|GII#mmX9{?20*aH$pua zJJaZrr5C9bx*JG_maaQ{!>heAy!-o0S>2(Ivxy}RvcE&aTkQ`-sZ@7a>VVpqHRqe* z(Oz!*do6h1_U8+L%Ln{$sPlU*c&q)Lp+(5*EDHULt?+U@zt@7d+Mmxt?ooKXa&G&3 z61*JG4`HEQKLG`NALciF2D$C;wc&wH=nJa5(Fi>RK3@r5<_CgvJMo2h;ydvsaJl-O zYp_^-4&S<*6s>Hfd+@+!sy0UX!ILf>_aYQnEU6LYw!qtaf0q(>DKv$s&I##Vy?zLM z&e=3_fZZ=|q%aiRx#T|dCGG?&=zj1bCOP0FT{^MgN0V9Tq|KO0TjA}!zm&!4xez+; zGzLe0TBjRar91G-`|)3#Mk>d#tE)J2qF8N8u@uvb9q@wv;Rzh$uCBP4i+ra!xeTcw zZHKoXJ~MbJ#{@1^rASieoa72S&o77lflnO)WpaWr<2dfO-RGABJPd3_aTB~j=P~{Z z_T>lE4+xWT+kMeP%^S9(ca)XxwXPj-dVe*H!h}VN{9|C*K!q}fbz-7Mh zxTYURVB24^3n`S+E%sr4@TN{!pK%wgPMz7|@i|jdUvS)Jottmc5%=Nkn{P?aQ^9q7 zRgJ=%@XCpt*bV7J)tg^_XQs}C8sh}Xol|wYZJ!rDClMDj^R^MF7aY%TZY5;PCSL4o^Byg?@e8@Rh zjMW{1n@1asnSJ3+V}VUwJi|#yx5=^t!DFc#$HIa25fG+u?g9_G@w8r_)AQZ?+grZG z(Ix2F=$K>9+{eP0Xfsmtf>#fL10&x#k8Y-1I_J)})KugI&-H~Ub?bt|xzmZ`FX?pd za&uwo&d)>0~}t=d=|0r zY)a$9)@va=E)`ffi_T&;-L8;w+8^lI_}q0K-($}39^GS(=cm@WFr21X(-hI0-T2&F zKP>n6D9pU-ndTCk`OSEzt&}4^0Ur25&Q4Hy!b_(&(KKdrCj#qi?r!!Sa>OV4nrN4W zEN0Pk7SqWVgDI!|HPt%15;zVF-mFpt^zK7jBFFtLbvx*U_$I=7UiGG)&JU-Lmhe=t zBiuUpfX+1b1(t?F%DIyBF!`7hyn5mcQ zX~ew>JcpZv0v1)w-KIMy!n(d#}`6S6u#?h4c6xbFY~D#mii9M?50DXpFiWy zA{w4;rj<2#Iq^HV?-2(!_N`qQOYU7?FlT-T8#iXa^Nus!7|YHZ9>ynp=FC8l`b_0g z>GB@W=Y-Gr^BhAHtUf!#;>^%>W6ovL#Wwys1iT0npZEQ;oZtaVb4-ZOkWv7juFnav z8nNgmR1f0cF5#(uICskc3-gZdlye^Rf8-3$8@?@VHf>URmR zwkJGCjXqjpw#MPReRT1Qv5)%uv_D_l_f79f)33FhIGizvL1O7Xak$jQ8xz z@0iPBp)mI)j*HIHSW-9F7Ui|SCA>*93S&QFTm;k--N$8)`{TecV=gz5F2n7yx*Yd6 zox$XYH@I@BZ$>dvt$2I@(YFfjJRf#I)?QGWJ>M zbHIjv3?fZ{Z69QRi~M_5b2H-@Y|FhA94@{T)Qe56j<`8jo8DR{iolyf90ocTbg zsw=GEjdG$-Hxw8cgb(<1<&#)A?3#-|)GgeZ7Kr2IuDrQXEFn8Ra${ z;4Qpd@Hum1sY&ODug6@%%koEV)(iVn?(uj}KJc70Y{rgy zvpIK^ik)2o!JXM=^M3QFy5Rq5pTmBtMJU&9=zS9QTLtX6$owYu(EM;4R~; z!UZS!oO>xzXMOX`xXU&L4o7KX@^V=VvS&q?nGkfs0;LUs&EWywI)_vv(59dow)eS!1 z0pJN!PQ925Sx%0N)My4CwF=$~__^w)d`DjJ)HJ@CvB&MDyy98TT$rgB;Ai?SFa~qt zi63o(w|D+FnqyA$)%>F+yjSyAR`6cSUs=I>Eq`SN@3s7u6};E-SC;Ua(fkpComc(D za)0hTa=0{7>(NbClerCEPW<{lzUcZCSJ^Nt+-lM#} z25(<}2YBb872HcsO{apx;+dd2O#1CX&N!!h9PaN?*>dOn_Q&U=vL#=5kIR-dcscOj z z&6h4*>5_A{)o1NpU$BIC4m!aJ-6?#3wOjw?1`l)7Psrcy#}8}p0Gn6QWBsuE%Cj|i zS-;_9``g!kS%Y^bfgFwED6F4tuUFhxzO3Ly&3SZxKG^2-%LkuMD)^4OrB**jczqnr z7tNW}jJau@#ZH>;tY^PQ$|ia0l9!t}uWF0uM7WKliqx7anGVefvf6vQ={ zo;bs9W1myr`}-VCn4@Mib0N9Wl-qKKdBr0IE{lUKXJBuhm5?JoSMWGiZ?gGhA=6$D zURH}4=BsG-Y%7ynHZx0=rFFoJv&KGG{+$ zcv2d=Sc@{9x@OXdofoP={#{gA11 z&VM-DF}HfYS@f##+}Q2CGQ9q4!b5r~bLSZUY+_GWG~Lo9kXL>3gyUQx=D?_T&Sy-3 z1KkKNXMVsLOj9;L&tweURLPr{{JhuuFlAB}A9+xhk`q3qx+7hM5#Uprv6;&WGwe$^ z-1)8S2`oIrt|y$dzmaD0&G*md=hJPIN)7=JXS?|lcjj^zhrR!02~Y6jDd(PT=xaO- zJe6Y;AI@*%oW29Vt4H&gg=(Z8d>+I%d@?4SJvtmWFL>ZTxI)O{`!ihghBpNu*$o15 zU66K#2y=$#*5ep#!mHPSx0>bQ;+b7^CQ zcjhhTYfoUk+h)CYnEl1rHXSx2Rk+zAV;1n_Ua((0YgXsDiNLU{f4eL@%=u+KzrgS_ zZYH@Z^JfQyhq;b<9n4i6m73a=|%1?u5k? zN#G=IT^;6IU+3UGYd)LL>k`M*%lM(ylrO#1V{V3{`64!Vv$#3d_NiBD?(pIZZUTHz z7iKdFcmn;0gYv@?UU~yQ8Jo?r{eAY?j5cpJ!rQ-o5S-h^J&w$cXWU$1{@nTO(Ann8 zJaVF!JNz(pL3ST#p2yUWVnJm%fPQy{>jB`YEZ%-gZI19Hm8nkbZ;K@73ol;mFPgA) zI%RXZWjtoi`^)&c&?9{4!=&U}`%l=p}a=uJM14`>VtGNfC2z<|_6V9~_^Y zy3j)|>Y;SEKfQ1K8u8f#d|rlbb`L}-T}Hd=KSz7!-`Dq7ci9Ebki>8=7-~(lXVg`H zUcUN0n-3w4A>bgH0bs_3iawIn)!W66T8II>xXLj?ZPiRCafObk0(T zQ{zo{$>j!5aIrRInL|B1y)5CWY?|(dnO8ns4X<1dXV7C23<$RL{$QJY;jQZVQh`H5 z+m(P9-FV04it>K*knY37iHE!FGuq!Te!c21X7lsx?xPuwxQR9t4(FtA(|8(PI5XzY zVzA!bd7ReWL(W@U)oWmlWEkzZ10w(YrUX9V;qx6+4y+aS8S};2J;n#VKgXH-pJ#LD z0_z7qGj7h}2zC77=6S&WK(z|4BgLEUOwJqLk{>c&n7d4Jz(Bm%G)6M7{hcrJ#q&!J z_xNzGaNhfy&fSzfVSrCw@YJ-v$^$I>?svjNfcwH*+>bD=gB}0q{^*|mt?T0@FYe}< zpBv!qJ#TaY5A%OmqqUlKda(0b!n>WRinARz&J0?@>+cC~{cb0^D@K@qJ?(Uc_Yb`e zJU@)wwCS?>MYNkA_Ri-ld=y`ZW?9@$IFHo_vmr%QBDZ*t%FQDtVb`eRNK@=A5rp_*R3xwc)w#HS!6ceKt^PW%c{6UD zh9F6&bXy83UwCOWkMQ<~ESGx7eDP}D8mJ_Ph0U21Zz&+m%U=N>I(4Q37hcsJHUoEw z+uV1U@BUV^SQz;8b;g0qn{stJPjiQd4iRn&a}Qj&t+_Zyc))*B1PVSCBvAA-mdbT` zmc}#i1n<~RdG#Z}$#KyYYeo)J)r*KZYMle;)30+I>tFJ!cauWj#k-T;a~5X(RR_W+ zYsU3C*PNie^pto(4)=4hIyhp{mTMUDhKKjjN|zVA?@rAVpEEVP!)7Ng^W5LLFku`R zFf(CJpWq+mfln5x^_Yt;P>3EHpDTY%4F!(Q9>4!KkN#=QD>{*z)nBt4DNTh9W?_Et zu=a(EeF;VB1qX5zd&QZ0Bc0tmynif*cpYPI9qrxiy?;5vTk}_%QoRoLS^BWHCr5aA zKOVNFf-cJHqUp9V^f|&?&hlrG#9?kAoAq`udO259SKtIG_Om)nVYcP2!+iPAmBN&% z+YJ3qe}y*^SMNz_htdYZsF-}wvtbn#u^0xWvK(}( z*J(+Tjf&RxD!PbpKf)@0F8tKcscnwCMkA!EFI-`7klMlj9?agpzv)cOy&PUdCt=i# zGd%@X%_ZGx*W?3FqIgH%%y+{%^VRSvL5scMsWg6C4tWW0Xj&u>c#r0gbAxxzurF7g za*t@?wII-5@Mdh8*NsEh@qsP3%zex2{ASFbg0IWcSWur}wB@kBt8;bt{oXmkLw*3- zJi|L7Kz(q`akkvkmk+#<3fWx(Of6%*E8b;r(EV}LKLZ6HrBN(RIJP6Moe#VS_)ne2 zS^vd+XY4mOcv-LGs`oKw)7?RYJ>h}lH^rDQ$LhfKSM}|)cJk5>i~WI)h&dmu3?`&% zwBY?iz;p5ZzTMZX()osd{~Ym&{J!dw#j}$(*}pl$n^7O{^}e0q9J9+UeUJIzGo=&I zL^mnNu6zMZ;TUT*x#`0@U~;x6gc*1gTndNDNscO{jyt=TFaJOZO*EeDr~e|Fa?vDq z*l!&6U2QqL{Las(Szd=pPI$rj;IwRY)AEupQVQ~OiZLJ`oKUbS+$Pq7KG#GCxX z{LXJ7udjsAiLj0Xcrm)74{DrpwI|#~Z6WhPUaR#@IqMwtE#|GW{!#E-7+0UAQFt(T zK6O-AV9spHoQ=7boZ$&H25TY}T+C&Kz5p@}_#)=O(U*MJ$>vDkgSQty?1C4&(}zLr z9N;Zy_}tdv0D*>6$&K&Iw!^}6B-aPyF#1+6mYe-@3+D{1Yvx{FIk6B&P0U|!2x{j* zFDb(*$}Z-3nD2+#zc_RJuFk!MSI%pHSg$qTI=Anz^a&O){HMYyoMp}5;rRjY=md8O zT<+-L@GhA;Xa0>OxbdAPjDXe-2``%s?4%J#g$2AS4QhGwAI@P5&!hNm?cD<2adwU5 ze)Q@3Tm+&ro7<<>+2zgLXTM4J`~UOjcTCq|Z)b!f+l5%YZ+~XMdcofCuogye7kyA@ zOGG{cL%S|<&TpIcw^w`+;WeXgd)%IT$q%30r6a8TzU_IJ{P=GUyUXe()zFQEkWIi) zlj5!RQf~Az0ZCEIdWL%#6|jNPLhio6egbx5TxLjw1P z2R8L2<`%FPc6NQ9ZlIg|^ey^D(HWah-7WR>Il{Z3l8*}hYQnfsXi87uzrEl&^h!8) zxf6a=73EhbWsO_jPdb~c>18MDX;j_Im5X(v)OTHsduqgwajGEoluLK8M zgj66>#;KR;)eURXdOde|;DklzcpvUn4QmgaNX>d_vboqe1_wOC^97IOhfj=Ql{pr$ zAdsl=XufJMc;`43Gzz)9_e*VW66)_ApU--mow|>8a9g&P%hE}=AJpLY*Y z&k^1ntfq7K`ufoDP@YLFc6{tpcOwbtu^u{`hQ;Rx4=B``N}yx6>Z1JMfxcxfCpqpk zM*qR}L9l_aS@dL?}{2lr{(1-wGZY^fSkITpxQ%1xX0! zD%fnHB(RIf2Xkt6k^WllZ zF50Hpt$zGTEc|RYsBW0uvD%=Zf50rfV15)g!JfICNSE2Yylm>$AMO<41uuu^Hz>}Y z%I3dek7w#$Y$TvN@b=hW+@KNYTCN!b&77BKXB)0s%oASJpt0k+D%zj!+~>{&=7jF$ zJaXBc``_}yC!QYz&sr5?%$G$hzKG}be@o{s+qgg2TJ;d{E;hppf@*NwsO1mu66|1x zBN8tK3G3hQ;ByanQiB2~q*EqMviud@-R?{+cz=Vu99|Rm=f>IHEGe7M=4k(>4|BSC z(F@n0+3W@tWZF%rVh-!pH}suwGrT?cVFLUYhs|itnloX>ZJklE22XB`UJmcFfyvby zHxAhqC_z@AoiRW5L)VQR8v2{y*?kX?(oHnR52j3HGCu6_qGW8O3b82+yY>3?L5AVD|!J3}} z!_PMNwHyE**oEgzz1UfQlOsIGkDPOrfyE|W`o14x@9aVM2LeqH{P?2I@a`gE<397G zmuU*Rzz-)>eRMq90^WZ7aDl@t1@K?o=A4_3lHqGIdj9hT-SzGSr<# zETZ8

    {_f(f#PN4vHN_%mmz)6s-GLaOV$ZaO6cV+u)_(Akwuv`~Y4>=e3hcm+xBM znAwJ@n?qyVuJB`>wT7pp!V_yqhDk-UDvH>!UcM$5bTWtIrPJ8VLq$@tk0r&?q)R*+Y1h9NI$IC zYCox#J2@qQ1bstqQHDo0_2<=;3}(=Hfpi(mbW z=c#_u6)l<&i<*i>HOCId9O^cMJROka4JEKPMI6}18+e~G z)D639Sh@%d^M)n{Rd_>8+QvZC;n&?36-lx100+95(3S=3wt3wkmI!N9Y%&-E1}uZ> zrU9Q7ZP-8T&ub;RA+`-tP^zw`>kY&y@Id!nkqYTsfJug=nG^x@3;q@U9fbAu32DAyst@LWgJ)!xA4n#wvr@ju-NP28SVwevecdd)E&S5>#i!-ztn;-;B@vF2nqyupnk|FC`YGv(ddA~JgD8XUkY>E0 z5K6`%SAQw|;)4#Gjjmz`$yH2@B z2VVu#G>x$d+boTGZEApM(3R@#yGJ9ceN{nB9NDM3nb8d~si|3QLY3;fp{frRkSpW| zUi6rrt-&aDKU!=oGNM?_RK|pu3G%VVY@N4{z)JYR5KY>GBL=$vkKGliQPs%XdZCc* z3*?vwRQM|A5Xix_(0p643R9G-)No8uGl0DQ$Yjl{u0bqFApb;7(JiC{(J+Rfq2c5- zk~@5v$}*icy(3~}U%#C;3r1mvyaBvm>OXerqxv0wI21`0nE1!8W*I;ajVJTt98j>Jgl*9 zuT~N}RlxV-dn*(RGs7@>rA0v8>&n3gM8N30q{{>P&E6#7y%eE@ce2?D!ox(YSWAJFMkp+t)kqYZpq zd;VKF34Q$g2(Ym$TU^uR^UbhP8@L8N&&Tc`G@LhqfzbvS{t3~M)|AZCOp{vAa4}|d^@Uu{g?2}Iz3^Q zq8ZFS1?9}-cR;Z#!ykGbgL=2gk zAZx&X;CL0>6k>xTU=KaZL;6O4?#MGd(gw*huq`k!fidZj7l)ROIyLbuvHL+I!`h(M z8?)N1o4qId8}R#7%FTG&Bj{^VZ)kZ)|6n!o-jM;ejMBD<4eU+yAwae8)_1!F{NN>; z_~F*JDAc;Qdd8(f1j|SJ>kss;z^Hx)x=k~v3)UCacp&ybp$n#I1iboxG;jaQ9Mb8C_AoH31=gWKJc^PQ;nr zLVLK8fMbh3g-!Xyw!}=90v$e`|G-z~@A7{P)epCH>=N?`c&|m7>O*eR*`u$=64PoBB`m=Z0ol1DmwQ z=C6%H`r)kptatw^7wiv1Wv5PWgHE^23R6y7nn+9hXN_u8{zjx@ucQohuu#pCM?NNW z3`Qy~StZb8U}MnM4;8&KBrVHQJ`F3NyzG`%Ax9dxoD2${_*t^v54)#_NN~G7Y=N(T2 z`u4H7YTINL8~04X;?gwwnHO)S`)}2VU)e>#AXL)chiKr36D-=9RE3-w>?|;d;jXl^cP!;n1>A?Hr zjhejpJ;)dM9<|@Oe#4!<=sg+;i{W_jo{Nt+|9*4%$BW*xfgUqHGG-RYegy-?84kft ze-VwMyaHN4{+Exgxtngis{Ba2U9m%yr!$NXpp69fPZld`{g{s&)2sZCKrdT;6aSZA zz;|i(>8RXzD$OIMqFo4bcmVXZutAT(0%;sKgwa=WI@B|tV?aI;P}df?TBgN|Ca7DT z?{RBU)nUZ^v(u*S#alhBKq!TlM@ph2>gEacj%jA z9_$`H{VBYCEq-}_-zG=;iFgLbEho%6(ccZkTl<{Qw#{2WI3SvcqVpI_Lf;ksJj)3J zx_JO&gC9|d7yBvGYdM$wG)G_2&%qc~VvsQp0-1L8F8_sy*MG;ep3$jHkFOj0*VzF0 zAAPGL`dMPzpm1ImFlQ0tPyk(jm(U-7{P5weNe43cR$ZNWJjOxak&XKnnPS^!%Ys#E z56ec!^Rr<^oE`ooo zk5wz0eW};`e4%o|o<7zZ9V~n-FF1)EP2bDMstvvVMXz@;>4?G(A4~o#`dEFl*8AL( z)PTF#%g3r6jr%9P-g)`No34DU_{7tG(4D<}tiD(4UGy$Gf;idR$HI4wdlPc@$I;*3 z$3nh8IXU;4{ z<-ej{?wE3~S^fkh6z&`Q?0CKM#eXcbz0%A5q}2C=#4nuPcOrJyl&8b!)bfz#0`?dVIj z{C-_ecXgwS@q=Y9v)eUvW?D=U%hs3U_WN(KPM&7AfuWsRgqos=rJ2iE%eYNU?F)!n z@qHEE%vvVK+cajduCB9zh-=8+Y{HL3#j-|U%J1DO;`oS&9&N$Dfc2rw;JacK_i896v%ZK{nU3DCa`c8FQvMU5 z(K1dokZ)M)^5Qd*tuKB0zUm$UZ&2c`$GI+bc6npbGKJdpN_jc&kBp`ss9FSf)lqor?RMi3~WV)YXr?WejWeF6#~Tik^mj z6}%;aI50(?VgCVOjwGiabeWnM<67;jKrqgGM&+j8Z#<9$jW#|FPT>rJQ-NdlIukjI8Dgw|9S@Yeu{6&sV!uVgqhvA{ zIRP)>Pf0>nd4UygS8bAaJxIZl#002)Y|$=w6Pdi*TGt})u4|E>Ti3$Z4gOTu)@3Y@ z^?R6C&>JU-epDR{L{B8Z*eL1y9mYOzB^B+33&Krw*qS>;= z!Uq}kU!6C2__J^H$lF=XV^*JqzTTj!i=sDRwnFqoA)R+DSowIg+s3+V(gpI+|45d7 zGN5hC;)fdTz42O>Xn!!pGWvoBt@9eM-;uRCk9AU~%7Q zeL6kuJWiw6ALLsa?LPrdt8t|eZDO_~qnfHy#<?K|%Vax1fz7|uY@!jSoxUa7 zRyyj5ANuS2GYT`a1+uQIEY^s4-O*Pd@9Zm(H}@6v@Dk`{Ujcsovc7_cHO16?ybfP2 z7C_c%S?j%4U{fYT(D7@p>X^i=MiymyuwvqG6*r!Ja3r!~?-r`{qylw>21aW;Ost zIz3A$FY{RCujQR*Ti$iH9UViY$>NXzkp{*#mbKhx9IjZ?HT|1fRTH8ve*w^kg0$MHe zJh5~4YgTpp35E0a7QK^0om%faDrf+Do7_sNI^X2`l)?9z{vSXb>P76&wiRq{Pe2(q zm<&H_6B~OE=K{QY{ied~B)Kdeo&4VZ# z7zN$DgEKLT$Z)>WOQHf+nBCIHnqCCVJl+#@aM?fFXsaB9t-`0E8-M*3 z^&#-#@K^oUOb1J-gQH)69e{MH5GssC*jFLpOM5&8oLv(9`s?la16*37G#FJo=CAy( z^jPjtT3O79sMX5&`SPyM_wIc@I#*d!noF+h;9aGSKA5q*v*0O(U&L+|pffWu#vlON z1`l`|i2Au%Q1Q-Rw!NlpS#pLHCFSdl+(l@iAf38s$#CSU>5LBl3!cD zu3|X7U+J%SiB73%9``VgA=A!i8M&afLU~l61^9#Bud5tI591p+D)Ts~_I@?_Uptt8 zSOz=Fv^FAzW|re!-`9?uM{j4&qxYnoM+b8rm>1HhJ-}Wozd;9N*v5WOx}pPs>8x_C z0nq;`rKFn}s;Lh|oRr%w#Mm=!P)ZEz zRP?Zt(Xtcl9YitN9@7Eqj=Q>L4gfzbIGdKDYuVoh{UF$myZ&;%ODI35e^#%E9_GtB zjdG(Q2jz07ah-g14S*pkB5>ZBs@E{b&-K!@3LyZ24771(K$l;TWVs$ zXVbfa4SlBfXTQMT!7&EZL@*i?#dzqg)qQ;&i#JqtTyAcyVfh7O<)o?z3U5= z-#<3L3F+Iwrg5Cti8=%8dnY>e3-wp&ncg_JXG0Hd_VaEv>l0_y4(q;a@1}{rLa*&> z^dV!##Tm;up9@$y%Zqpk1=V+C((xO#@~~DDYdUZ1G?7OMZHwfDEWcm;ot3~Z zK-YnZr{kPq`y(Y)O{1?dqv4r0TGqQh0t~jR-N$+JuQ10UZZxm`XWFb7;4KB%iJ zmch3{%iZz=ejaq~8$$UkFHhJJk-giTJj%*8U=J{tegBP*tW1pFq47eM{&i(w@4F1# zPX_kC%fLNkVEMZY+*bz5-(}#QGBEfq1NV`E=qpqW# z{SoJ`_diznj#nxTMFVG}KWT>bK-B?tIM54zXDTknlBVNqKJSxf!*7~1UMQMtv)L1V z*;CYlja#k6F7B)=>+Py5>us+qJ6@|R>n!TU?FMZf5u2xjA)qo5Pj$~*>k+x5|LFK_ zqeg4T*Ya_>5FBScQD@}@h~L%z1cmOT`9e~BjAoyGPe;`* zqb&Y*2gxJ%aQqYcvHl5rND60IsXwk$&hcjpez3$WUvt~XfO8iLgkRCjWZBEJ_uVR0 z!+sXctoUY|tbc(nDL<2M{t5QdKVc86oLxX`qpvF)X2#Vs-l;U6XS=Ly79v*_&M4HW zGdmISZa-pXJ$lAFykknjRs~?_GG-S?6fCInHLZaOwdr2J#rm3O!PgO$R`jSA*Li9N zCOA4w7J9Vy07DuGYrx}-8#3rx+Np?YW`KRpGWBK;^cOd#xK>}o93b{un96Mr4dVQf zJG(|Z_1S2%KC4kVSm`tPy8m6Deb;Ayr9CWri1EFas4Z$;z`L<{t!TXCclBb8w)SF; zcJ*S_f^WT8wf^!x#WPx-x;@~qC&$IKil=!&MXPGT>F9?>P;SVL#waK^gRj_A+@|_R zF1!&u&*HB_pwL%iP=c3ZS)3p*d_*d!LxY<7ne zv9p)~%4B$tS+v0CGIqib4#ft-t|K)8qhh|!Kd%=um@e!uj&m8(?hQ(c;0%XL$61E&U(tB#BR@$WoMb`z{CSlrz^Ff8km${ z)VbiDUzV*UxFV!OQc}R5GgmZ_RUmjG)eJ4b{D8+a&E^+@@7jbB-!z~WxM1`h*^iI~_5(+Wq`!hZ|@{V)CReU|kj_ zqb$≻A(Va?H-|e+E~40ADCzfmCPUpLcP7!Rqe;%L85$-=HkSm~2XClhYVXO8C3` z@4%b0L_Mjl?qe&v{jy2{!zn!0zh*SIn%~4@>=WKk20)Cud7D2GlafwK-|}a;f8OGC z%SPKw$!G#VwXhlyw6UTMtc(}%oYO*qz_Jr_XxS2>18X=;{#7je>;6;tSD}!c={zqk zW;cKY1ueycL~N8sLA6%M+AOy}0+1c~G~luRG&?H}thgaiqq6ulo-^Ua>^q)v8LlZ& z?z}^#3m#m3i}b(#dsxBkoqD>e+4RnDDV@<a;F^wlt8aV#YB0ht40Gsl4eV|zlKqt2DR0<8O`Gh9$!Q7?JT4}>nzGyTs`T2MO}4| zD;}<4RNjS$eurKkufCPRIp{xa4LwOLf;=AHhrW3Y$F*`5B=VLu$m?t9uhzf=Z-NY2 zLEsUdJ!D#P1g74=L*D%GXFmn_KRzg*gd?ow&t|)T((xV&T@brkL0#O#{p{x}#Y$WX zD977;_{1RD58=_kXGUGw1p|p<{_Ngo@%Q&XyZSu}m%q}3_i*D(Av%7D0h4l>FS-ps zYjY7nX=XCvD_Z-j*aJ_Oy6zdD{j1@pSdj1*&5am98(0m#M$%2#H`&V0WlJ6V6~tXN zpi8ckLDG53{AY-fLQILHW#Ot@u%GG0B zJN`bX1*;{(>qh-u>v`%jQgwVnsRI~0EO!gij1jy&w3 zd_LZv-*>I&vGY2F{MoghXX!6FAN_>}k;h2Uy>w5Hp)yh3`(Ng){wVS24OEfJ|Fld`=%HgQ~}) zsSdu3nAlzXoYNiZN!F|PFS^NG|5rgTz$rQ5dVUGxzWAP}psyg-NmlzosDSYxnsoJL zETgg2r+*3!6u|9R*~;k{FHARioQ-+bLY(u|k~I5YM;rIF76ba%?jTQ2&uUKSCY$~_ zPZB3M%kcJlhZa`z4EJ2&&PO1mo7lwM2&70|k1l^>&@^*S2=&GLpL1!Ji_E^37QV%+ z;9jHZQvc@rl;~f~F?!xpSk7_${r4~B_u}u{XJBFtJJwi}>SCs3@cWnFtM7j|Y?EpH z5i1gqSlE}i8TY&FMLLt}a-YWM`1R-IpKN^ZF~+9)iw~e(Fdh}Mxu;*`-{s$bf4_Cc zr6^Vv!_ImXvU#7sAIV?d2fzPrRt=2fFq1FZUx*UW_ZyeLGv-*QGdY&}=ZlXnmJf3G z!Fyo`)&B7!&bG8))^H#E?Qq{36}I*^V6F6OFNt=iM+AFGOh&TVuGRJZ8^2dgjNug- zk6QH$4c;FV_q%Gk*Xd}zzW`_J;^)R}LeI+lX zpI4y!JY-Jq{&Tqf#r?r$PA?akvlaLI`XGPigLbyUW&TBK z>V|m2XLSn8dG?Z3u#X zcB%AD2b6#ReaDP`lvNMpl>U2l&=%Q%bi0X6l$CAt;MrE=ggN0Eh_1dY#q=Cy*y6$5 z<_4Rq*Qp*~uikl2=LIj(d3gU2-VqP7lzdU-9PI4H4mQ~vC~L2eJF9nQxnxpU=rDPq z!?w<=-)7(8@4M{*#!-|&{<3lP9-#lL7N}u#lRk{uQ7X^s(s@5#Uq0PrH&$uyn06NE z-`7?p%p5;;KhMzFx8$?YR_#?gbV)t1m!Qxe?dsuuaR2Zl_6PpH-G!wCZOiL6>!D~r zCtG{#x?hX-%Q?_~??ANQ`;%zDmmBT(w$c7KIVk5K_j?DD`@Pqs{Rck7zO>)lM*DxY z9KtgnjIC$(wMA3WX<;3bKE(Nn|1vknv$2*@OtX5(+jzcCyUF4%y~QlT29@d37QC%Z zT-F3O?jH<3%e-6m7g7o9c?USx@wPT~(^I8Exgg8<<^Nm8T@{OHMUh&o9EFEI#QHme zpc=djs9`BYqi+lJ1N;o@Wr+bxqvDW~tpFEvTPS3?BRx$#%Nl3%9(SxWs8x^q3p|vv zdP}@Jm|8_J@#*RgvO8-Gmib5Jok8AO+5#UR7PT?@JJU=`Hr{S!QSI#mh)Y?J{mtqg z8Ldlodu&j=3z65}y}iHA!Xlw|TlZ;rI`$iE#d+Rw+|QK-c9uThgY&xotnM1hL(eR1 zl1d#{(4uaZ>!OL6tpVLmlx;Y3g0_pd@OSAT<4eK=4&P(_w&@wPpx)r0;H*bNu|bV` zSpQ_$eCEH9wnB^Rd)p>ozZ_wo5pUA*d#p1zRFmE~gp%7IEZ*{6FwJ|2yD574(SH~c8u#p;WF zakS9}-een^)XDw@90hby^RW>}ALw6B!DHWnMa7n(gPg!FDyn0fZIaEr9h#Z!FBg__ zlu+Rlk5~H+EmR5(UG<8>5{fn%mcj^j}!ef9bxBfU{;XhWB8N z8*Bv3@4q{uW(n`p1!=6=)?4~eQ7vl9!A1ZcxSh#7)^zwh#XEslJu`Q3i1=IO?7c;8 z!B!k#D_)+t$O^Li=K|&E=JVRLgj{`%;C-dAU`W)H*=*=M_2f#on~TEwJav0vHB%mJ z2%nPNRWLPEBl~w1gI#-KBS}taR%Q;QrdPrI#xFo7?B>^JKkNNEKGwT0-e0Firh@Cp zON%wS!&S`KqB9fq&)awWUrqs!OZn&W*L~m5-%uCQK}Hj|I%Q24(>3){*p}Db=Mnui zIw;-$;=vE_xmCbpx*v`<#bGza2PmdH7L*;V`ct;y=+9QT_n)jD>`@=M|J?`vNBh9} z)YH7w2M)gbz~6n~zqJpXUp?AC*9U$Pj{YZn;HMUalR_QaM6>xmIA;O%H0sI*_RwsZ zM^Uhkp1Ou_dLu=>!7pY=oawx@==I-S6b=vS(^q(I*SY7j?t5g9SyKU}W+`m)-yY;H%h`+9W#hgzALaWs zz2z;w-0x@d4|ojGCBzDkG9kP9&y+WcpvSq z`FJ_)k2cc&UbTJ?<^Jeka)0!E+DCb`I*aw0{kRu6Sz?Tzwx1kmfAr6+5&uvy3yaw# zFR{7*Zhe@Tze@(jYStG%Yq^KRJpecB>D^X~z8;rYXB>jkqnONBmo46}-oE z;rA1zy`C}OC8NIAto`F^)^f{{adD zXH5s^Q8V&S*TFBs(f^7L{_up-argxAh=}(OQ%}h5vcn$hOc!~LHCfjGd(RV>=&e58 z>pkl|G0P{HI+eU?zt`m)&XNS1Cl~zv56>ffRvuabdtxbbP7O;_EY{_*N9K-Q(0^K; zn*~-GGnB4q@wdnV`P0E`=I{wtBpPUE(^VhfAX8p6)_Z<2=5v#CB<>Y?7%v09)?+5EUF;5iz zPQ7wQfBnwtYnfiZbbYmFukRuLmg}n>Vtu3h);BuD`i}Ek-|->V*UxW#{jKXersd#; z>+9vWzTWQjYq?OWKhZ1;e*zxe#6?XqX~<(w#nsUM%* z`mQ_g{9XEj4qb5j${oz!F*;#)YK80Gu70vezKZVD!x`1PI&AlSYO8uNhpsPf zDJR)zbT@WTE`OWxineU8cD*YgpcXa7Pn(M!i=H&fpPJV>uYQ1gt4cka_y2!eu%ZpzO zJ$TT+w1MVkG?e;snw_hDG-?c=a3C{KP_0=Ytt5t*RO*F^0&>Z|+=eu2^ zi^d9fJ83S2<)zZ?xvERl-TJM9$oy+q9lcu6Twnf1a{y0$Ww$L27QeEC4qJF>U zbPLUe@=Qu^&sAM4PCK=XuEH$Xt8nc**K~n8pgH;0-~^fr3bpG$+pgO6{3U8jmv{O8 zm2+wfS@OJ`TDb?(F|V9j@@{)RZSl8@7!1N2P=A=T3EoMm8TuG3PVMv^(Rh0APmh4{IyX+4nb z)|ajZyUinC_Tb&GoiF>db7kxCo|YTCHNaYQZ`?3P@N38Q&zX=HXsFKP$VCY1H+Y-!VjFR@Z|odx zkh)X*OpmkWgt4GTy}7%1`)`YX)@ESIbd=dBa=#kL_ZKsu1ruZ?tcNfwU}eV2n=g8N z;$>du|vKI=0uV`Ht$@P;WYQ*VK&qDw&7jtSNr+rXU?~O-Z)h%5L1kYl1k9_-l$@pPYkdQ2(gf>zZ1}@6x%%n8a;AzHI9F zkbl@j-h71FCfm<}X|S$C|3C9EH-I)>zY^_pO%>&Q8RExh^J|JLn>W_?bSHB^I`Uhe z`ytEK=YGf*vVzySkGUT-&oDzy@Q4q$^M$7SFxFx42t#wAX+!C1sLuxWZlH^bbwF4(swq3sCU)|y!tg^zee7q70eXrB8or0mb8Gs;9i6~X#l3K zk#}(dx9qJ7WAT4{fbqZ>41c27M14dwb94p2hu5YZ#c5Bh2G`zePw_XuN!`~;5i zlVkkk7(Y42Pmb}E^lgsu6FA0C{$t`N+nl*;FV9l`a`hK>zTIKECigLSBnMa)z+DLiFY#d66a@LV*X)Mv_A>YjKt-$f@}2Od<(MQ z+N@p7?PrR2D*L+gI&(b|ajuUfj%}6$$vzjmuB$)0*86SjIh`HpeP>^LPG?7ZPG|Rf z&H-e<<2|RdQ`w930e!3VpEhGR?zs^E{|{_q2RT>RPHWRmbQSk<**2ZNsZ?2Isy&|& zbLSIcu8f!-4x47P$32s{Hdkx9?)#HF^W^Ghp8kL8{8q8&+IZ|^t=HJjP9C0bZ-lc2 zBBHb9uf5_}8;$G4@4_FXdV^HuCCQ5q&o=d}4LQinW)JK}IuCNzO43=WGrPvD9Gvab zkMS1HY|d;;yvy0NIM;_9XXAo9)ctMS9Ne|ME8Tze8q7h<%e_+&k8P^^olUx5*Is3H zzq2FV@9bbMFke?X`G?<%?spEP`_=62Lf!B1b^o*X0~_3*!{9o#uU8agr(EB~7)7Ly z3T{CQsXbVysSJ5PG)dNlUhrI% zT4n#RoWem=n#5X6!c`SO>B=e z1H$Wf>DKHAKf|>|XmLMG?mT)S+t6};fu!?8`(ruUMIMAVr(#LB043ZbomO=2276H? zq$tyi3hdK{#9|iK$?i-hoSOwF)Ko@1KZIu+-a&|3h%xSz3S@NXBRWUq$X?Of0kTi% zhQA2H#u*+nj&^?j3erNjmae#U1C zdls{2-w5&Zx=kou19O_XCwp(+A&eUCF$J+pUVMNY!fW6l6;P3k-dawJ=BYOMz|PSJ z4*%wz`oP=6)718XtIygz`oLA_=mYP7c7aEGuRicL@)7UY2Sy@xLH9G#h6*_>v|d}+ zCjOZC7gv68R`#jKOr-gj?e|PH_#k@Q_3ZT;7!^u%euf~`n#IQMPZ0^v#3i->)f;v` z8|wqadtz=L1H1oJ#DZ)K&#`xJV|!1NV8nw2yjyZSWv{Y8DT0SDz3imgu+ zfBY9c&ysv)H?wEiaPv4f^^vdGGR=_%dzTgFDseFH$3^sv*KKp4Xr?~&gY%v43Dcn) z{QiPp>|ph>x=pl_eiYi^-ISklW7?0zAQ;(}AC`ewuIj{vjd=9x@z{yqqsQ>*iSXE}!{e0C<7_+?;nAwcW8~jjQEHU(IF%g{ z9%prUlp`M5vr5KlYitSd7><~z&LhtAh^@`KD!Xg=hohx;l0lzty{yi z4LoHQ8_D7!f$<60m>(Pef|~V4+o~NpWUbJUtOir3unLW=FF%>lZBO0ccl+ffWn3%N zADr0Z-d{eAfd!w1IGD@m8=;*_B)d47C^kfIHjN>{7`aYh7Y~TLs++`*CpPg|QHRs9 z?$Y016!k^6GxMX#{_vMF_9+HujR9G8GxHw79Qwg}r1#5Uhh&HB>H<7_i9KD+^Xi)u z-!h(;2tM6=EW&o4XR^6E)<&MEO?htRd7cq(N{D9$MpTt&uZZVaYa`EIQ=U6{o;&JP zjAy1Cw<^z5KF?FsDd%~js6BsT8}5R36|uQI)7h$c_0@ylgL^)8y6x~8{fQsfzdO`M zk&{*(a!VzQZQyw_>Dde4uwB=->4C`Od9~_({T+MVkmIK|c(k?@Cbr@ydjVNUa=b57&z@)PEe}lWZMSk? zIjd40Sm3Sp%@ z&YVa3wfitj+XEVZ2V%CHQt+O%+a4PsPOtNA_k!C)ueTqmmz#+H#`bn%{TY5Qw$RUa zEl$6&8$h=HXwL1C;=_7ebs^R3w~-hnn|PyrMToDM7;bI6eD`>iAg@dR*Nr|-`Z{^h{7X!HLoa(f^mt>-zub~_?Arrn zE@`fBmx;1YkC{Y}BD~@0y0H|?Tfkn(HLoudmp7sJhLhW+-&=PX{A6^p6TM?O?v({; zois=KTybr`OnwP9?E$laH%(bgP8PN~iEOsae92Hrcs*Wtylr}K3soaF+KFi|CgIJ5 z=SRv`)OUxy9dgOR0^*(E8udM@z#Hc9R?;hs&ztyr3vVab3yhdm`Pon=AYI0#>p4aH z(@8nUTS+f3E^igyTX-|!{&(a+@$!8W<+rJm4u`igo#gT+{@%jd3F@RHtI1s1v`#v2 zQ75N4-b!?m%Ugx_7T!!)Cmk1B`5tK#ZK3o|h(9eB3f!qqx~h@7nYd2!dE4;bj7*=r z^!auc{v)H49&Oz~$gzlbm%W)rOmjA7xQTYGlhjsbZx`CimmB-Dae3Qwf3}^>|Dy}x zZTGLAwyO89cRUp4`S#Jj9=j^hA%y5MoNJ3)pZcVa1D$*yw80ncqA#6i|Hh*7i~Cn> z!h4U2Ybuc6u8biUSu0g>;hFqeQ!IEYKe%oD_pY(snVi*|#%+^Z3B|HvifVP^_^9>!`r5K{r&gXsl$Y9p4&@|y>G$ImeI{pxH&Imq=QulGN%yX?MAjAZ*}_@pRAF& zM%HLqPxed?86iv@TZt~hTZhpTmbWfE1rp}r-3oXUd2cv=z|4E=!ZN&etdku#%x}mv zcJ1cz?IyYjb5DLMJz7Y$baIXFFXc^B)WB|Xd_1G;Q4#_UP*9B>RR$dBYsu?%?Vn z{F&Fu0^Y>m8_vDAtNZ0^@Jp)X7-yXR_)+#uX2BQhswf=~UFo0^Y>mnh>_TKPbkW;Yn=omZ8wPOWC3rb@6Axu)Xg&QE$P)C>!e5DTPw*S z=lEQpApRp5W!SAwQd=4Fw(?~b>%!AX9&h`^LL6)A#B1t2hu8=1eroC{&eg)xN;P#> z#hN-1+`%Vm5B-YZBk*HA91>Y8pHR3gDE=UjT~qu)jE$hWLciV+8^P3Ve9F~aY@)bs zEsi%Z^fdJSFJJ_4h6m79od$az02xpogG&)xoAyA<)55>)!Z65}c4_P@y#M`TUBmV= zqA}d_3u&)l2C-U=HBghqga5i_If>&tsuj&Eb1iUUtY9h!ALNc@+qYmd)rsRL58DJ^ z5ai&)BZCvi=kwMGJCV=9dr|*oJX5E+L>9$`+&&U1{-WD+b3oRpW|z&=*$XbD0AJt~ z<3hN+HNj5sa3QkViEtsZyMD&?d(&?sd`*e`7}{69GlwrIpMl5ctqFFbWX7F5Q(L(O z5ac`Ex0vtD;|t1i@I2lcVkgRS@D_Ah+1nxfHgoVid_g%bgu`1C>_izZ1go=LPB73( z`7P>X9$!$VlRVxUVkgRRA+6k)M&!Iro#f#Q%5fna-kM-1%5Wi$>gG1(I0sK`Wg$WC zSSL&I1!cGp9&b&s6XkOS9S^2C7)p!_$qS87JJre1R$l)hwUsX;TX`L1;Nn8KyzMW_ zK;sN3_;2&~J`?{%84`yXCT&dzU!jNRk> z{}uyT67Ka)_rjhd2mL{w6!pRG$_nv90&yxQk_Hi+-~ou!BClt16VJV8Yony$O&lYn zgvmzu=!o@tr?D1itjlqauh!}RI2ePfWLNd7Vcc%wikb$5c z$YuU^QyFZqdA`ZZwhckGxeq*|JQk_DLzCt;(dl*KbND zJ#{iMY=2?fBmF%+1rg-%lp#p%bP zq%1T;>CrlZY`sTRv(P_{V_+3<7qNX`1$WV^*~_@%-b{TId!}Ictzv(Pn)j+b>dVJt$p&fTg+lslbVd!FJ*)3J>+Y{ zk$7INh*%7!Xl`T;B8OV>A{OIno5SFxvw4gFhyVrHOeRjiU^8pk8%z$&G=_QnYf1h- z=}W*0#w1I{oY?86-t}lJeV!}shgmE`3d35S6HMg7K2>Agh~G1-8)cYe%WYn}QAVjf zxMJ?>5$f$5*;)@s=NAj{;9)J-H1|NwbpuB?PU%KTE}Z;K#9teqQAm55Nm8_LBpk5& zMoG@s<@Kj%svB~FZWPr)1a@=;hse}H$W`hfim1++!sgo>?;Ft`!0sERH7G8(2BoQP zB!}dNGbP44;BEB4D4_$NDdAouex_hI%B8?o&y?tx5dKp2fwzJg}vDIbrO%mq#HTXG)6o z5~XXa)4Z4HsRSPtW4NGwQcSj&iKMJ&FwxkPdg{h96z@Ok)aXCjsyTBYmkqHJf7H`#*g}+|hVA0S_7`KjRKoehK2H#5vBS_2W4k;R^^quw zqt(n0C3fx5Hf=CA`@`!#mi$;rV4IrFU&_{OmkRq~w&sSCs6Wh$qcznHw}wB=ishTST~|e ziu%I^v64!?NXlqS{&1~*!>JKt<;BsO>xL8ESTx4UkCjxcH!7q9pD9V5s^FQzjiWWy zjcLU*r6^XC^!2ctg^mt!reu4ZP!c^;3gT$BbR$~>MTymolAf;ISV`5Mt|fGcGbM*< zWBap|*G=)`Xorp&Q9AZ*Ibx3J&u!07-!|r`;{A@8qa)_1GBKE=O0_WWA9EyLpS4rW zQ3c%hd&eAA+z)q%IjW}{?-X-XY2Vlt=BU1Iyi?3ky?tZbn4?;{@qRH!HTR8eV~*e-irmCp;{>@Nx(D&;KU+ zwQ7G{Li?Wn)1T-kbUz#}M%p9%GBGuZOOmdEIKIRe@689GjEEn4s~LmIWQerhgQkzr z5WS49$mL-hImN6`F&tOcn55e!w^Z6+f15&h!zdD!51x@YsQ8F|Q+7m_hk-svOK_A9* zt+TK@kJHo6*lHuBNsmK?aB(XQmA(VBDUAVGQ)hZ%fsFokzJj}}@1~(#$MKju7kx69 zph<&49HGI;@-Asi!+`dpFA=+93S*b3sRI{(L+1!7UCoe&gZ=}e*ok#u2Z0stL+g() zlJUpYKfitNfB&9*)%<0lfQhiP&5NR{D|x-&Wjv;b{Buvp{+{k zwa(VplEDeCf607?U>elj_T&0&`dnW0*yzg~|GIlfeF@3#GW&O^KT?O?pGRq$AcNV``14+&))f0|ND~t z$Xg=XgJk_R8Cq!aY)pvmN#@+t#*#Egga1PCq&!cE;(zqv7Z@rRMq3-uUc*F@2NL<* z?Ln}xT76f#`WaUDuZ3&=S=Sc+`~>Ldra$*J8pC{cT9+D34EWH;&mHHI=;zAxbqyp* z`Jn5`x`meH4>Sr;T>Q^^y|!R(26#vG^-s|L(Stc2fkzykejm?dxdSfI-(df%Nk3`m z(!cb(ZE|nApY-XzFS~L_@<1DzdJjnm{XYNz0RR8ua!}v`00030{{sLEt)&-pyaE91 C-z7@` diff --git a/impl1/synlog/s1_impl1_multi_srs_gen.srr b/impl1/synlog/s1_impl1_multi_srs_gen.srr deleted file mode 100644 index 2dbe59d..0000000 --- a/impl1/synlog/s1_impl1_multi_srs_gen.srr +++ /dev/null @@ -1,31 +0,0 @@ -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:17 2021 - -###########################################################] diff --git a/impl1/synlog/s1_impl1_multi_srs_gen.srr.db b/impl1/synlog/s1_impl1_multi_srs_gen.srr.db deleted file mode 100644 index 33612a25abcc09ccda948d7859cc45d1eae869ad..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI#y$ZrW3Y@Gy=5 diff --git a/impl1/synlog/s1_impl1_premap.srr b/impl1/synlog/s1_impl1_premap.srr deleted file mode 100644 index 60ab429..0000000 --- a/impl1/synlog/s1_impl1_premap.srr +++ /dev/null @@ -1,183 +0,0 @@ -# Wed Jun 16 09:19:17 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@A: MF827 |No constraint file specified. -@N: MF284 |Setting synthesis effort to medium for the design -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt -Printing clock summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - -syn_allowed_resources : blockrams=108 set on top level netlist top_tf - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------- -0 - System 200.0 MHz 5.000 system system_clkgroup 0 - -0 - pll0|CLKOS3_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_0 787 - -0 - top_tf|rd_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_4 64 - -0 - pll0|CLKOP_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_1 36 - -0 - pll0|CLKOS2_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_3 36 - -0 - pll0|CLKOS_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_2 36 -=============================================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System 0 - - - - - -pll0|CLKOS3_inferred_clock 787 pll0inst.PLLInst_0.CLKOS3(EHXPLLL) reset_dl[2:1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv) - -top_tf|rd_clk 64 rd_clk(port) fifo_colector_inst.fifo40_inst.FF_1.CK - - - -pll0|CLKOP_inferred_clock 36 pll0inst.PLLInst_0.CLKOP(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv) - -pll0|CLKOS2_inferred_clock 36 pll0inst.PLLInst_0.CLKOS2(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv) - -pll0|CLKOS_inferred_clock 36 pll0inst.PLLInst_0.CLKOS(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv) -============================================================================================================================================================================================================================================================= - -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s) -4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s) -0 instances converted, 895 sequential instances remain driven by gated/generated clocks - -===================================== Non-Gated/Non-Generated Clocks ====================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------ -@KP:ckid0_8 rd_clk Unconstrained_port 64 trb_adapter_inst.FEE_DATA_WRITE_OUT -=========================================================================================================== -======================================================================================== Gated/Generated Clocks ======================================================================================== -Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -@KP:ckid0_1 pll0inst.PLLInst_0.CLKOS3 EHXPLLL 787 reset_dl[2:1] Black box on clock path -@KP:ckid0_3 pll0inst.PLLInst_0.CLKOS2 EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2] Black box on clock path -@KP:ckid0_5 pll0inst.PLLInst_0.CLKOS EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1] Black box on clock path -@KP:ckid0_7 pll0inst.PLLInst_0.CLKOP EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0] Black box on clock path -======================================================================================================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jun 16 09:19:18 2021 - -###########################################################] diff --git a/impl1/synlog/s1_impl1_premap.srr.db b/impl1/synlog/s1_impl1_premap.srr.db deleted file mode 100644 index ab7def4b98fbadbdaac2e64e023c2f7b885262df..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16384 zcmeHOTW=dh6t>+o?#*=z4Iz}mGzgJMt>fKwY{#XDG;!Lh&ZUXVMQ*gLcgOMIy=8ao zG;Jkhb9n%XR|G!*UXkbz;DI*;{{emmyl`eWzF@ma9H*%fYc=DwcXzzsIcMga^PSVR zyBR_;Dj1d~Q6%`z`TTz0y9oJwz5x6U!C(F5hlBRd^>a^q5BMS%{s_TYfA~uu{PSL( z1Uw0N67VG8Nx+kUCjn0ao&-DzcoOg=;7Qr@YNXXo?g#5xlLXJK|$eZT@aH`rhKIfQXF@ zUEM}@*)$D{f{=i!Mz>~H)~+U_JCcf>J;+_PJ0Z4=J}qAacfkogxQo`!k`utNQf!Rx zx>;^uJ+GFy9KRl6t^j5rxas|Gc&)}MfMrHgF!DmfI2(3DEwTY- zS8+_QbLn?6($>wdHF9ynoceT)i(0LBf6>e4sl&jWa4;wK#@xBZKM%|&4*_#bV3=Xt zQ_n)j7XKVD(-RKn#lCDiJ_GT23P!%U@iuK6Q0bVNw@v#;tjIA%u|&HF4yX_Ft^^&} zcl&}p6HRf66pVbbb4f$UeR#0j!uW#&zcCE%*#M`$z$asC7_u*xO>OJod2Hs^3gFQl zm!@Hblr_h}Gp__W8QIX?%x3#|a5PlSu}R|b_?&9UCFZ3dm9h!=BsYjsB4}dH&@>4W z-EkXJ(J(1Hd$m9wh#L^`DI%N_!C_*{`6RP>Y{ZR&2Xy?JX&E0w^oI&W#gR$(rzeKs z@vk|LA4{&5b>{Eb_3_x%JS1kY-{PG(BT3U74+evOHe?e*~OIXA;m0=i%l5yD`PRXX#%4|MY#hcWHY0 z|4tdBnIn1me_N%d8!^{Nd)lfshsJq$`TxPVEieD~@_#S?Z=*?i%KxDVPM@&+Kjiz- z7Y?3189IF?bo%_M3n#Axzc~Kq&^v)|{c$)oP_OE-@!(jfs*MB|KH#{RuvQ|b$ru^Q zW^55Vy1kT5uP)7I#P?Ry3r?xT$V+<3zS3Z%8N1|kS+EMc1~m_MTfs6k1V_y~7)b-% z43Is9mHo*>tn4s7wT~_Xmlyo(t&4%h>@+{K|1GRuj})TQ&|$#F#DW2R0q`TxN?<{K z%OR!UAy~Qbv89NzT0&bz=w4uK4z&!`2I{G`8v(O!5gkg2M3>dF!mv;)FGAacNwMWt zmKM@!aeg*CE55&aJDV1l?`5F^R0MqPud!mJZZzp3C`W2+o|Zz8`v{t}ji4MQxdb0FvE}^t6KJD|phiLI({aS; z($C-MS;Vas5H883fEiu_C60+@b0&n z_cENwD$I>iAB#0uC>GfXW$)+s`|I~3?0miq9Ux!{xi~A+4YralzwRjM@)0TNdFzPl z(2-M09dI4Jc9c3=dEPpTcIYTJ`0MD6OOB4-Jfd|Z?4hJYGVzReJE22MiGkNr6~78v z3f2-mx7XFZKF>#4YaNWcx7Nvq1fDX-&2(w6>*%WK+C^wX8=-Yjw)Npfz&Xact@>`H zZ^n2En`a?fD*y#6cFYOC`P;lEKjh_vD<# zN0;#6?KVEC{^Q#QIvcFY9D~+t!Bc>QUcqFy}7-00960?0tQ6n@HC0-_ob( zJE&^RQ;`G~HblGGifDw%tO3(^EX%W_>H^zkjKG2*V3x{` zW6Sz+PM_C4r%!)rHgzR!7~S;K5bI%A8Cq8OOE(-Ew$;#ZSI{g08+JG33~!_vMi(oF z7J5?Hv=vh`u>Ps*aYDDHnVuooMyuV8I_H7ZYX`StH-N2 zf~JvQIpHp!wLRh~sV?A_M@+88a9Sz#Fb<6rleXEiQ?D%$kED9rOs5JlQg}ceTiv13 zwSEch&=_J%Ygk=PumuAfT`n{{ZKN2u>lvZemWU@ZBK zE?u9iGty46r4Z6SZ=ZzLh*+i+1OYMHp4Z02z~(5$l>5aHha-5F(abop6am||rZ*&x z!23ogKpz%T3u}t4b9RFOEsrDwO-;rZFSN+C&4p=bwX~6ehoq}_LkugY{1SFU!?K53 z7dJG)5{#~mImQFS7-2){hLWdsfyY``pQSqXQdm1Fq=rW|$qRu4CtfdXYb2cE6r0ol zqEl=uRBPxqP#Ls6L8oULER9BWO_^ey2;PVa#A*vPG^bSXtl>4h6Ss9(r_rBUCr)~J zmYybIq8M${)@?d$cpf|#;kY0AETGHo*^Lw=pp8fAF9GQUK`#h?fM;JCdfKI&RLTF8 z0*25_+Z-8v(R2c=^f-$nc6(;CHR3#r(+T`ERsQUAw{-JM$~B&?OHbia;Hh#3x}y=} zv@7TydnV6jIw`cGpxu#z^WJUN7A2#rold)&Enu_jVf*-a8qP@XtbL|nL$d+$l;~Yg z;5-m8!?1;@)on|i;QY21v?Vd?o@&4XZHl|5;L*@fdU$jOv}m3_v%=JZUmk`-4AdxA z*9b#f8-mO?x|SgbHix^6KL#EdO4v2Lt|oCp%M3a1acw=K&Dt%UGk0Bsiq9defx_&^ zzrco(KV`$(UE-PPzbq1B?_a4-LDw{*&wgONw3*c9DEqf3QPA(uOM6_(f$ai$tJdXT zq^(=0X6Rv3{T%F%M+~KNaC?8-B+Y+ga-mGgKh1k0k$!M1Nw@t2_}xxZYW|)4qi>IN z(;%}xazr;riAzz!Ck`#fITaHc$FhUOIq^lZczq&|FR8DS?KZk=oN_6wp|04bFzTKB zU1 z`r`pF%Xc>*EEU7{NZ$&c^nQ3$En?{=epkHCp7G>?%$IkdfQW($$Z8hlTk&?)2YPcX zMXdHG{9xkb@q}iVnHafiM256)&v(WVrI`b6 zqZpLy@yJze^t~6}clvxDc)6kv`&z&E!dudJ!6HH`(>U@kH{#W}e(#01q|c`jdKK@g zQyYD6!mDxp7#54`=iq=}Vt(gmP#b;kjR!HI&#Ug*Aao!6d?&mr4}|1)?(@mqcan8* zwdS2qu&7+ZKV2lo%UJ0J9>h$&{(XIT;>2+;Bc3Lr8WXeuZ)f@@BAW06K9&)mJ@@PT z;Actm*a3B)+=)@dyQS!^<`T~~D#&hlF%=z1k|s{V`|-SpoNSN~aU3#(d;-iE|WE>(lflyZu*yGv5FAAxk+LtPSk;zhzYsef*0(L$0LevZcu_^-x|;Z`;?e20XU06(s-GHBz#o8i|@;|q}9#OiawR?q4{#Pe?ZodStort6{(*)jtZ8>O;m^8 zAP3xhM%?}5&67BCd1pdiZ2i<}Uk;eO6!8s>c;G4W$(AjOpxp^})rTi|zeR|r#Gh|m zziarfM*0?bs{->qK9lOii~RvzCGHtsAob68#>-<`B>YW8`QK19r>lDuOS~(_&+B^e z_$_!qUmg5>#G~=RCu=ym#5*RWvunKj3@?ke;vF!4?y!CZ;AL(kLX70nIe#OHbgj{@ z+aD!hu`?C9FPRY zA4|c9PWv{Hf@^8V{Z|M-6aEtNPB%^*`VdFuK6x2t)V9BzRPlsJomftMdf{)Vfz*bV zfo5E6jA81>d)Tjs*ggXFD5AtKS9n=39vb*b46*%$UW$>JZHN!+!^@pWF3=^FiBs&K zpM{$FyyFgJRIc+8FY$J*w`AjtcO73<#Oe+YQY~<#EWi8)XlMd zUHqKKD52`*_F8<6^gXTTvOOnt!`^bu^a=XZw=G6Y#U~0isUnv&NWsJyYw#lOxc;*muV9U5>I6jW_gE z)P(2ye4M#5?;tmyJN`mWOBa=V?v~?-6h*!3=f`su`QRO%?@jDWUYLAdByj@1y|`f2 z$9(->eO>%yc)-KU!lyBfE^?CWw_l6lp^T?d5nm)U-|UcTq7VFRGIpKUX{;IVRT^tt zKUGFilxM7`DJFN@`MI-ySkU(>W?lVErAP~ZkZg^WYUC&2K`!KMg{l)T%kSbmp`{Z; zbXL0SbB7xF$#P8=mqj$8ab6^3z9C?$iN1j<(;FTk2zaYb5%9aKu|$pZEqpupgyb$} z{k-a(oR$0YM+-a^;s{rU9MH)VpQl;GXUG+u)#77Kcyi{5F-~a=wiLBJi)6;-ywaE5yaS!abY65&vU_=^&Mi|go4gHPQG?8yKX$T zKjBlS07L3i6=mY&h0fQ+&*ayVZB0aYI$tt@ zzy*NZt@}N@>N~6D(156iw|EKgSjQ>EEg9L;yHO{7E*kT0qEgxM9Tj|% zPf>yf``NF{+{k6;$XKj2Pc{{Ep768N+ZhjX=rP!8k+@p~W{Gzk?6|)avsfYl4_kHI zy^1I8i1%QxeHHS*B#tw%GntrF*v_+D@X=m(cEXEzl!1xM0{)q$9xxc^NtzTnYK*l~#kSedqQP$A6bA1KqllUZX?jW`n zS>P+@G`|F&B<~Fm_?d~2vxAvQARyg4eSnulzVEWL|FC`ziT1Z2vcQ`owxey)7`|cbvO`1d`Sv{{>Q-6WzPZFO- zJ_0rL6EJB!ki8fB9_sH^&rN|SkmXKz2PG3;y8LmnB}DjM=`@tMSXO`nSY$lCke*2QtrPWbAeaYk60~Y@A>8vJXG+%t~=Mf4?NZ{?C0q9{hoU8oGcn7j(WGgc2wi~ zE$nq(NHhk=oB449*;yRzi$0eBT~g7n_UwucwzEe17+yht9c=7-*#q8Uf0e&PqL18( zNSrlht={-7cA~i&QI`((>~9x%BA+L&NDD~dk?KV9s+`uyPbMp_A2|?{Me@4Z!xOw+ z{of;AmQ3DKf7sRkE%9z3dLe7tUS8tu>i?E_nX};>!U{ik-(O;Q{6!?jOn9P;t;0li z^?wYnq=T5m>)pcY`t8oos>bNMRXq4!c!lpmB>1bpkU%W$d6VR^|Av z>dD-MSCc-xTYd!A@^xLWkv_nCUDuz<%kFru>iRQ&?sy&+@LtvRCwRN+JK&AME4UM+ zW;yTBq~KMDiodPYjBBdLG5TJ$Ezj0(cYeNVTk6Go-L^czt3m%>*Y!H_+{8hC!N*jM zM0HD&TbI7OiA+(U()dm!?)HAZ77@8nz`ND^GalkU&;#TTc(7`|caX0kp*NAt`M)Sob6$c5*WtuoywzZ$V zru|5sM!6%h&7~N*5#{qe>$^zhBBHTeowwLFpJC_oTp5^a2tC;hyS3+>>Zb44cupO) zl9@}m2eu}aq-b69*Q!HrVBEDef685)#%Xoq{p0QI;Y|{Q(nW?wl zUzFo~)1;Dp;IY|mzKAYdbh+RAUlw@0pXA8BSaYs%KX@vlb05}k?VP?n;K^~B&`6Ed zz0ZUA&QD7Di&ux^)`bW8gUd%Wc{#(iZoC{osv86nnHRTh5!Q_7%1Ht-;mv#CEoXVS z>`pK`hY#@n`fYf- z`o9YwRr9QnKllB)^XhrLn&@NaVQ=DzOxb!aVvOk7yv2Is3D)nn-tX;)zJwi{js~&H z-)*ol4|vj5u-krCAtN;BDLd7_*_Q2R{i-v+pzsAML|3JLu}3^s>nLRid)YZ$6p570 z$bGh-R#SfDxV-4Ah@Ceq*oi#kY_C7mRPVo>qXa>CHcnh#6 z-2nVtXcAYlnOD~z z(aSj)wY75-YNYQ51f}Hj_$~dWJI~j6;ODCU+3)%Rg?{ud^E?*%=dii#iA#A0^(ZF^y@62M z$-pnUdGtj8Yot$x^%G<2-jymlU%YpIBK5%!xy%n`+wh0*$hdx-3x)*fWmyc2MYwi+tO)p_h`ARZ~ z)xjN&vN7eUlV406x7rU;d1o!&&hipv&TqMcSj@}n#nHN2RgHMDm^t8vR?pY(36J%G zQCK!{?9fasAu-y%UtU-J$QLhFP((KCZT&2}y7oh4hs~)J)k~i)Xk{};MIJOV%aiP} z?q3rgn@v<8>c(h;U$2=y)$w_DpG?e7hl`gqE}Yd_Yc=ADe(aPv6&LfD5{T)eSl-+Z zRzp9LDzaK}BC|cLz4LR?FIC+gAdYF~AT?Qcmt1Xlyvuq+7B$rU%gX{!rFpg;v#xr$ z8r`^v&7fyZFkslSmxFEU#as6CWjtbmwkv`zy2+Ny6{X$gA-%+76A!n=XXJXf{p;oV zVp@)?yN?Ps;wE0xI9!vz&5}I6bPDPh2}JL1nPjrN&v|Rheht%-3VoQE96=i{Q&jOkht8awN70S!&;rsWwEo;-z4R?-u~5k8Wr`r>&5%sWtadz>5HX@y?Eyub z4j0#m2l^+*;NUY}1V>-cOp>J{OA5#YpT$mfokxI`L-7qA#12)}%a}T=)E>dGwM-F)`1 zM!YBa%0QH5h|jXs-kuuq*!_6ySSt9UsxO*s8beW2)mzxfX$lCQ+HS*VP4vdje1KkLKU|IQXF!^J$Mn}tGfiK+F|{!>@I`7(uatD0S-RS z;zXPyx@BLx9=sUzPtB9+{6)ES@3%I*>a64P>|;Xn?VAWY;z8nVv&j<#jdd8vQM+ zTUX~tA#b5bF0we<8=g-b)#a&ETfo4{JGD4#Ou^WAM4jDH_q+buY5uT41ZL3 z3TM&tw|{+LcXUF!1SxmCcf1KzOX}Z=yqi2bgb|SAed1NKft@Tygnz*6k>I#){bO_3 zqH&x&@4b7#JE*Ra+)X}RAH`rQtGRuuOec4xPk$3%p8v03-&whio$ZX-$aX$aU&fym z*j2DI9_xkS-G_5fES89U3W2sPBImbt^zF1i$nXa7cN#a>Uh3l~nmGJ2@7r8=sZak( zpswnhR3kU$BRYpbO-we%OSQ>MfoK6sw_$c>ZS)~Id6+HW&66 z%5)#{>WGLNh6L`62Ql?LK@V6DakgA$YviUrf6MZs_=1+XyP==HM!ZWR`pm)K%qfca zf%pdf+X>GhH~iQ|$Bdscq~3g5PJ9Y^<{Txi zyr>DPH<6DVUR>m6HQKWhxXDK@^MPPve0E1XS!rvkYkz4>+1#6=I5=PUUDi9Yc?iai zcoV{Q&Fm7AR5ph5DEWky=o`CF`Eh+N9g(eQkxG6UGKaft!$ITO#Ke#>^HZV4ec}Y+A4C=$1FIgI8|I`|Kua|N&Oz%^Z}iHcB{*ohNsyrL+Ey*cF>c~ z1M#+exn!EBU zr3^3laXi0I*zBol{u?{vnYov11?U;x4)i5`5`(Wrg9Kz|+$k>BT(wvyUfd^%K{Iw<%8ZJbf@1W)SU z|2W>H&x)&eZW7TOaDr4WE~uaQk?ST7iTrhVwb;-6k|rq2c%EK3%vllnd5OF(JfP3v z=M%*I5tEZm_fgb^2l_C%bNmGPqQ9+nRhN9`eIk~Sd$Qii#2>g+ov_-R8c&=xJ9oR| zjr#1VFiRft7k5yixlGk{XFO}hgNXhrBE{zWGV9{! z4cM~+VwP+SJmp;9SJdk?3@F43GzKmq`hSe(`_tw_R@UtB4Ejb+So~1fxn5#X2auFw`TlGL}Za5?n z`Si3``%S&v=@|wl=xfdvReYqmUk+C0<2-q_KSdQ!+rh0!G6|l!>v2N2rJ0@~*hZ_} z{r>ZACTU&c^o+x)(bG+#c_K9Rrs^53bVi245m67NtJ~Y^8Cyg&Io)d!?t{}a?WW-l zx#jmbj_6-Tf<;nn5mT{ex{G$ z6TcXkK@rX7u!(2HN<)ls(-gi84S|?qOK$<1^8r5J?j`W7Iu?d0N2WOaKrlR;B1~=L z1ALwm>V`csEL{MF`9M;GD4Zdrr^Zy!;m4yP5pb)y!UJ7M$aDm_=z^*-Y%=)mZxMfmIxFmZ?nX>+O=TE9)cuU#{f z9KqzQzNT%}ok(hmav#`!YM4Hmmqs@>$@JuwBS(UeV!Js!oCrE+g8uhUh&IHQa@q_I zLSmhq2}U|4mKN$@8Az)?HB2qUhM=61qZTLNL#r8{Fur*yquS;;4uiRtt~=7zIs2JF zIE&Z~4jX^;ugUp&aDIQj{M}}=>1d&c%@Bi_2znou&oe?zl$tHi)H%}PV!;v&Vq!$6xFf=>Li19l4?$ge~? z{l0W{-0U<94DW-5Hb+D!`p>WG$H>-G4FA)6DaVbl@v}unhN5B6EuYxjbZC$f2vH>; zseo<0nYNx`41ezG-4G8gOZg@2hK6MiwJvUGjJ~doIYzf(z$Yu+Q1Y~HI@0YFgMjO4 z&*1QA^fR&G^AsQK#}vd01P{a;>q<%tc%#tL)27wTnN|@?6jD!^l2Fw>LBp6QNAOL} z#Re=X);xv7;8TY|KL~@r1so~WjD)U%;b|@GamtVc{V)jnToC*XlRSjaCV0vzQ(~tk zVBPk~ImriJ16%!Da+@~?ht1^k=YB!*bJ98ZMtl$iuq8%nnIoZkPR{nQfq`Y8d(F?p z@8{=5=Sn2sK$Jj&XQVYW14wZsW3B40ybL! z`LyjJZZO_=F<1mW>?*+F@Rx2lG;FJ(;jW-r0ygY!$Qj;<*?0^R5_*!<>#o3k5U zFBLMh$(GS9 z%pnNJ7X{?b5KMbU0DwzPc-kQ-4d@+vU(c;8%g;0_DJB3$xSK zCyRiVVvd-abqeh6Eq|{=uFk)i{M2N8Cx&@{det^Uf#^L2FW+-d?(e_ps%F~_qGR*H zXPQi&PBrDIN7PUcnP2!x;4lTB%buZqGBT(zv%uU?bEZ(7f(23pOm$ncNdt)fiI{Bd zQ{w6NzraSoIv?U*6E|fh3&eBGsS3}*YzVyV$l|eP5Eo26(KyS)fkGaHydQAt-yka~ zf%))LPqUam34&oi2tqJd+~0C$-=?j~&)DfS#eGvC5DDbofZ)E>AlL9Ulk=sH8ICDv z1~B@M%ATv99)hL`1RwF1t8K(lNmg#u!!XAn`>iSaeriv_j+o4rc9y!v?CN1YXo}4y zxRDf8T36Vbgo453jjc6Tx2{7lEDf%60_<#5Uti^iMYCDi9uxQg{`TkB;x^&5YxKaz z|7-(eMwZsc5D>i4Zoa`b&oDOAu3>A(BRrjj$8>ac+ykCG+Gq&QHrhil?kXHycEX5qpz*=d>NlG$900eS|*KUJs^}zqUNxr74u9+Ybl^-+}*Dyje2Rp4Pn4HE&%HrSG^ydWh zhta`xuL1pB=ow+f?>|Wc_`$HJ3HH0`h0znjW!yp_59f3OW@T9UE~2LjHc~qk^cJie z(-V(iQ~!BH-jI{cOarI(sH@@dczS#_qsQl?_M3J7(XX9feG^3d7*BA+%KwcZ_JX)k zfY={Ib{YbEQvx;8^k}nk))UnkaDiAS*c4$ECtTn7IaGA+_mkU`O z55L%jJYvdexbsu*tlz&4q}zjjaNh5H3wdDinK1(`;7q}?K`gLoQ*6wrNjS*A4D$@K z8Hh8#q(Y;o*ft%SmWf9iHRwp!kEX&I@IpJ(XNOD3sblbm&xcm6N17F~8d}!!r%zc{{2jP&71*+I4#WRRtAow^k2tG65@d!dd>O@;14L6 zJ__Fi%xi-jnQXntm;UnkDa3=OW@0)T8Typ!5ZORHWoR>Uc&G~_(jp$NWFq~dH_{$B ze~^{4v;PpS*9X#d&_8$st)2h>X_XkQ(i>=%{^PV>^at0z)cH|b&w)xw>R;cV_aA8m ztMH3C#Vqc9v=5lf%*LrEef-*4OQT5*ZUi0+Y?Yyy)cPt|kWYMkq{R^6Lm}d{j57`5 zUADKgqys_}d@5;;uf5L4b#{QVXE1sUiJBHw1j+h(Og{G925^U9kJ;?yXMOM>f+bq( zF)!r=((+6SDK?jWI>VC5SPEIwlCHlv4{uLD0@G}ZGr(SR;NqtE7ehO8d&fMgBoZZK)l$wzW+0{hErY9I+&~I?caBT`+leM zt$)lzZhyvNyk9sx1sh{Pe*9=-z>a(kI{lUBh3|WyABqmy)HzORa7{PG9W1|zd&a49 zG#YvE^&v#|HfMp7gI;1qhp^WaQlhYrulAXjKBI@ZDi-z0;F{cb`fuGA3Y9M84^!OZ zI%l1q`uFhsKwuT!D(u^+sQv7W_k_A^M;;?q%28Kp;_ zLBc;DYux+Sf6jLR4?>PsYkS7^emZ8MM!y4b_w~UxdQ7cSz z_pjM1Di|iVQd8@H?F2_3pWEnZPZtDlN+F44*)>S_b+9SMWP2{BF+@+CGV-|h*X4ss zmnBB~)-`6jYzWk3o1tGVtrq*mo%R&&zi+KO`&;Xahy4HQ?Q3mxN25T$qFu#i@%oh# zP@BcX2ap(pS-a{72c0MW>XB~GQ)rl4R0=3P3ZB!F?4){c zj7rtd+@36D7xzbZGV4G7PuMUCmKg+GdVQ^j#_4D}!kx4hJC;gT_+GO87+>}~LBRg+ zwRj6OI{nIFDY#vYxn9PIn{+q*0o`5HOdjiU9yo7s@PDwnvu8rq!b&wY*KV$ebhWJA zz}LsDcEf5XoM{YMo#{XM9NYK-%23rRhpcYE)n8Y;lCB=>YRB+3tE(;d?rnu=4V~FP z&-f#J=(_+)Kr~Xw;D_81-b0P#>iBz&1io$_HaXfdEnU;TfLBR%4B>QYgR$(NGG2jw z;(|}oIeY`_0s+e@cmM~vlxAwIOvwoX)jgp(YChIP1QTn5!4WRS0x&`_rm1-}+XpRI zFKKCNO;sm$Lky=Ot9|^>%UAP%nvcCh0ue2e3LATie&Lx;gK#N?waPPp&9S_ky;%L1 zG#=ikkqUF=_u2QGb|c34OxyOpaPD1^nrYKYL?IIzZiXWuV3d0eV^X*)r9|4a9eDRtXNm3L=4l=YJsC# z`y$QlEAYg}h^aoc$!2q0y;SlLgP57|qf4~*W%_!X^)_V<)(b#bo3d`3?Om~&PyOzi zSFGq(^@Tw)^DQ6vi-?JZPC^Lie)O4EULyEz^b0xhtWaC>KUDS86N0R&f9nTdZPI*K z-~JbSH97HnjIibvJmu6I8Cv^m?MK#v^WK*CFZF6_o)*O4)Vu3QTxa_a$oWC_M&={T zz~C~W7n`xe1p@8esd029UZZR>jt>`iSV3+A89inDO_KVtSIa}LTjoVw_xInwc0LNf zZ>~#9Qx zrmLS{!|GSBO?r>Aqe(o@ViF%#?|Z90vf2^b7skDZeud!oufO*`{%+Wyrd)%zSpDha z*PzD&s9p4aiDUMr64AJcoW9=(^=uDw+I+DlK?{?lReU31XC*sJ-u`S~L6 z6ZiJG^P{y#i8Z91_a*6D|GY5usbZ4le#k?sZFPvsbJQ_HWVIu5aReoV*N(T-Znw#DTZCe8CAd9?+xke z$LrsJXEn|#Jsq*$h6Cj*>q{FFgRANltba&{BpP#`&FXK0LJW4EnLT65vFaR9_ho2@ zLt=R?0+H>RX$#-aCb8NQJA0%u=A%@izw_YZVPMdT%tulKv@sC zXR>|hQEG;kO>nPy@%eM#CHXPw-2PAxkMvXj{95Y6%AEI$^KZH`H6Qn8G*a>33pDK; z(_tf{Ch#Mri)S5@F9xxPwx9#qI^^ru_m90l@Yov0p-BYJ&`f*E&Ri_|wOBvpDd1=Z zuJ~Tn7;j)@Qi)pn7h2Wad#sM3*p+U6*Wuu!{(EnFD$pq&jnc1Jxnez++|VG*77ZK3 zVs$u=aCihO13YDQr59(@s%H*~)$-0@Wr!)*XS#_Epn#n>u*i(9g+5Ek@=O?6oC#xR z$k^{$SUF=CEwn;ncmgZ~$dv)h=mBeVD-F$_jmdlJ%uAd6r9p;(!Om_A8b}=5M|)Ba z#q6{gX9~n-Cp+L{hcoi5KZj~nA7zi}QOr?T8j1DTy=Ify&#PK8Jjd7G@kheWXfI?4 zG=VcgX*>hltlwyPZtSrq_KWcF%q6HJ>c!bxlNLKcogdCLtiMVdTaBJdwlz&y|qkNr0f3qxzztQ zEp*dRNTnA`9p1L@%j|+Z1S(8HCmMGRi?d%_)_HEr?*GednEaqQ_)eQaVDOft)84*>R6Kg2gphAT8#(?_tgK5(b)6?p#r9;%Y zW?NuFANmhd_E~+b{NHBKY>J;h6YX2I*ByaX3@zi2YTiO9PQ#X!HsSSec#%YO`N$;& zPcoF{31RnSMt3A*cbmJvRdcg=ND}#fyM(>}tJG`~)70CH7bdLr%xpii%R+;sM_|qr zHmkrmGw)~QYU#I*3@|x|Wc0M}9b+v7+j7+84zHN42b=rMo-jE9bv+{7A?vSXHtL+* z9#?!fh-V%iaf}x$vcd^Rhol)i_F-1*e1?S&SRu#fx9j>*SeHZyK55YlZJy3rm5r;; zvk73X7IvQd)O=I?S?%!)a|`>xr}Rs@{+4b$_*di$K#;%Tp|YKJ?x8P=Tl`C&^+SThuJwodWJZ^V(x(LYOSg zmF^G8(GR?;T9OO;3`**-nSJnIrPFA(w8zioXM+ruy7{1cU@!laJpS3&2|=EzSyi9V zGr9gRDGNQJv z#al{Gu!qzJ8xQd{9aXywn{%4Z%bcb|fE5E)2L>@cIn~+OrbSHQ37>~g*W|bY-@GQ( zkJqlrH6d#WS)K=5?6GY;`^IQwanMZYVa+^ke3gEee*gU=JG(+hr;r5Tl{>3$E1+1r7P0-CK_xuk~JgT41|Qm4D44D-j8{DgMKqotRiS5j)jW|fh3FZ+WM?uh{nRuXr0Sc7sM%n-5;p!&_+GP`wJ@Jmxw?_r%wIr= zVw}BszQOFY@^8k>e)yZSd#%EJ?2}#2s~EEx4B5%b=Qm%QH}PlZS#%7W&3Aa5)q%%f*;F%>mQwk)v)cJka|tXg|OcA%_jcd2mPPoJp z7vz%hdGvp#T2p8y#LF!Yo&yOd#*g>jOY3{@Z^`k>v*=m1&L9MA|908$EfFhaiLrr$ z4-fQ9K)*-qDf=F2{`&%+<)36~O2Iw3z3sDUOy{5!oyuSQ=xgw?iRCmMur*+P=s}!Y@Gy=5 diff --git a/impl1/synthesis.log b/impl1/synthesis.log deleted file mode 100644 index f5c31f3..0000000 --- a/impl1/synthesis.log +++ /dev/null @@ -1,154 +0,0 @@ -synthesis: version Diamond (64-bit) 3.11.2.446 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Fri Jul 24 14:34:04 2020 - - -Command Line: synthesis -f s1_impl1_lattice.synproj -gui - -Synthesis options: -The -a option is ECP5UM5G. -The -s option is 8. -The -t option is CABGA381. -The -d option is LFE5UM5G-45F. -Using package CABGA381. -Using performance grade 8. - - -########################################################## - -### Lattice Family : ECP5UM5G - -### Device : LFE5UM5G-45F - -### Package : CABGA381 - -### Speed : 8 - -########################################################## - - - -INFO - synthesis: User-Selected Strategy Settings -Optimization goal = Timing -Top-level module name = top. -Target frequency = 200.000000 MHz. -Maximum fanout = 1000. -Timing path count = 3 -BRAM utilization = 100.000000 % -DSP usage = true -DSP utilization = 100.000000 % -fsm_encoding_style = auto -resolve_mixed_drivers = 0 -fix_gated_clocks = 1 - -Mux style = Auto -Use Carry Chain = true -carry_chain_length = 0 -Loop Limit = 1950. -Use IO Insertion = TRUE -Use IO Reg = AUTO - -Resource Sharing = FALSE -Propagate Constants = TRUE -Remove Duplicate Registers = TRUE -force_gsr = auto -ROM style = auto -RAM style = auto -The -comp option is FALSE. -The -syn option is FALSE. --p /home/hadaq/mmichalek/lattice/simplified (searchpath added) --p /home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data (searchpath added) --p /home/hadaq/mmichalek/lattice/simplified/impl1 (searchpath added) --p /home/hadaq/mmichalek/lattice/simplified (searchpath added) -Verilog design file = /home/hadaq/mmichalek/lattice/simplified/top.v -NGD file = s1_impl1.ngd --sdc option: SDC file input not used. --lpf option: Output file option is ON. ---------- Intermediate File Dump will be done ----------- - -Hardtimer checking is enabled (default). The -dt option is not used. -The -r option is OFF. [ Remove LOC Properties is OFF. ] -Technology check ok... - -Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482 -Compile design. -Compile Design Begin -Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top.v. VERI-1482 -Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482 -Top module name (Verilog): top -INFO - synthesis: /home/hadaq/mmichalek/lattice/simplified/top.v(1): compiling module top. VERI-1018 -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'... -Loading device for application map from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Top-level module name = top. -GSR will not be inferred because no asynchronous signal was found in the netlist. -Applying 200.000000 MHz constraint to all clocks - -WARNING - synthesis: No user .sdc file. -Results of NGD DRC are available in top_drc.log. -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'... -Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'... -WARNING - synthesis: logical net 'GND_net' has no load. -WARNING - synthesis: DRC complete with 1 warnings. -All blocks are expanded and NGD expansion is successful. -Writing NGD file s1_impl1.ngd. - -################### Begin Area Report (top)###################### -Number of register bits => 2 of 44457 (0 % ) -FD1S3IX => 2 -GSR => 1 -IB => 2 -LUT4 => 2 -OB => 2 -################### End Area Report ################## - -################### Begin Clock Report ###################### -Clock Nets -Number of Clocks: 1 - Net : clk_c, loads : 2 -Clock Enable Nets -Number of Clock Enables: 0 -Top 0 highest fanout Clock Enables: -Highest fanout non-clock nets -Top 10 highest fanout non-clock nets: - Net : cnt_c_0, loads : 3 - Net : reset_c, loads : 2 - Net : cnt_c_1, loads : 2 - Net : n14, loads : 1 - Net : n15, loads : 1 - Net : cnt[1], loads : 0 - Net : cnt[0], loads : 0 -################### End Clock Report ################## - -Timing Report Summary --------------- --------------------------------------------------------------------------------- -Constraint | Constraint| Actual|Levels --------------------------------------------------------------------------------- - | | | -create_clock -period 5.000000 -name | | | -clk0 [get_nets clk_c] | 200.000 MHz| 388.500 MHz| 2 - | | | --------------------------------------------------------------------------------- - - -All constraints were met. - - -Peak Memory Usage: 245.766 MB - --------------------------------------------------------------- -Elapsed CPU time for LSE flow : 0.976 secs --------------------------------------------------------------- diff --git a/impl1/synthesis_lse.html b/impl1/synthesis_lse.html deleted file mode 100644 index 767f468..0000000 --- a/impl1/synthesis_lse.html +++ /dev/null @@ -1,219 +0,0 @@ - -Synthesis and Ngdbuild Report - - -

    Synthesis and Ngdbuild  Report
-synthesis:  version Diamond (64-bit) 3.11.2.446
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.
-Fri Jul 24 14:34:04 2020
-
-
-Command Line:  synthesis -f s1_impl1_lattice.synproj -gui 
-
-Synthesis options:
-The -a option is ECP5UM5G.
-The -s option is 8.
-The -t option is CABGA381.
-The -d option is LFE5UM5G-45F.
-Using package CABGA381.
-Using performance grade 8.
-                                                          
-
-##########################################################
-
-### Lattice Family : ECP5UM5G
-
-### Device  : LFE5UM5G-45F
-
-### Package : CABGA381
-
-### Speed   : 8
-
-##########################################################
-
-                                                          
-
-INFO - synthesis: User-Selected Strategy Settings
-Optimization goal = Timing
-Top-level module name = top.
-Target frequency = 200.000000 MHz.
-Maximum fanout = 1000.
-Timing path count = 3
-BRAM utilization = 100.000000 %
-DSP usage = true
-DSP utilization = 100.000000 %
-fsm_encoding_style = auto
-resolve_mixed_drivers = 0
-fix_gated_clocks = 1
-
-Mux style = Auto
-Use Carry Chain = true
-carry_chain_length = 0
-Loop Limit = 1950.
-Use IO Insertion = TRUE
-Use IO Reg = AUTO
-
-Resource Sharing = FALSE
-Propagate Constants = TRUE
-Remove Duplicate Registers = TRUE
-force_gsr = auto
-ROM style = auto
-RAM style = auto
-The -comp option is FALSE.
-The -syn option is FALSE.
--p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
--p /home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00g/data (searchpath added)
--p /home/hadaq/mmichalek/lattice/simplified/impl1 (searchpath added)
--p /home/hadaq/mmichalek/lattice/simplified (searchpath added)
-Verilog design file = /home/hadaq/mmichalek/lattice/simplified/top.v
-NGD file = s1_impl1.ngd
--sdc option: SDC file input not used.
--lpf option: Output file option is ON.
---------- Intermediate File Dump will be done -----------
-
-Hardtimer checking is enabled (default). The -dt option is not used.
-The -r option is OFF. [ Remove LOC Properties is OFF. ]
-Technology check ok...
-
-Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
-Compile design.
-Compile Design Begin
-Analyzing Verilog file /home/hadaq/mmichalek/lattice/simplified/top.v. VERI-1482
-Analyzing Verilog file /home/soft/lattice/diamond/3.11_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/ecp5um.v. VERI-1482
-Top module name (Verilog): top
-INFO - synthesis: /home/hadaq/mmichalek/lattice/simplified/top.v(1): compiling module top. VERI-1018
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
-Loading device for application map from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga.
-Package Status:                     Final          Version 1.38.
-Top-level module name = top.
-GSR will not be inferred because no asynchronous signal was found in the netlist.
-Applying 200.000000 MHz constraint to all clocks
-
-WARNING - synthesis: No user .sdc file.
-Results of NGD DRC are available in top_drc.log.
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00m/data/sa5mlib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
-Loading NGL library '/home/soft/lattice/diamond/3.11_x64/ispfpga/or5g00/data/orc5glib.ngl'...
-WARNING - synthesis: logical net 'GND_net' has no load.
-WARNING - synthesis: DRC complete with 1 warnings.
-All blocks are expanded and NGD expansion is successful.
-Writing NGD file s1_impl1.ngd.
-
-################### Begin Area Report (top)######################
-Number of register bits => 2 of 44457 (0 % )
-FD1S3IX => 2
-GSR => 1
-IB => 2
-LUT4 => 2
-OB => 2
-################### End Area Report ##################
-
-################### Begin Clock Report ######################
-Clock Nets
-Number of Clocks: 1
-  Net : clk_c, loads : 2
-Clock Enable Nets
-Number of Clock Enables: 0
-Top 0 highest fanout Clock Enables:
-Highest fanout non-clock nets
-Top 10 highest fanout non-clock nets:
-  Net : cnt_c_0, loads : 3
-  Net : reset_c, loads : 2
-  Net : cnt_c_1, loads : 2
-  Net : n14, loads : 1
-  Net : n15, loads : 1
-  Net : cnt[1], loads : 0
-  Net : cnt[0], loads : 0
-################### End Clock Report ##################
-
-Timing Report Summary
---------------
---------------------------------------------------------------------------------
-Constraint                              |   Constraint|       Actual|Levels
---------------------------------------------------------------------------------
-                                        |             |             |
-create_clock -period 5.000000 -name     |             |             |
-clk0 [get_nets clk_c]                   |  200.000 MHz|  388.500 MHz|     2  
-                                        |             |             |
---------------------------------------------------------------------------------
-
-
-All constraints were met.
-
-
-Peak Memory Usage: 245.766  MB
-
---------------------------------------------------------------
-Elapsed CPU time for LSE flow : 0.976  secs
---------------------------------------------------------------
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    - - diff --git a/impl1/syntmp/closed.png b/impl1/syntmp/closed.png deleted file mode 100644 index 0d78634f322a904e7bd0c9466498c0a42777589f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3672 zcmeH}={wX77sr2=$PzQiz6{y-jN4KYF_wtIP-F`kBBt#7AfeD8`@T=sp)7-;LX(KG zMk;%mvP`%|gL&rp8=kk%xjyH6uJhu1o$H)eClzjGdX8O~9RPrH=4QsW^a`dY=UFDY zzNFTs(+e}w@P;7(v}Qz8ZL;Y-#M8|71^^^;13(%*Pw1w20|1DL008n+0MJ_p0HM(! zy`(SzVAu6EGJ?Z>0)qpCd;(Drb0Z@N>S3U_um4>DFe8@ah9MB2_>;#8VUZOd)fsIc zf9rV-Oh#q9!tUe?xyv(gK{Z zpEfu4{@LB7t~Lg4z5IixZW6|w1c0nMwY)qQ3kJ*wUP_`~F&Ug`6TAta8N}Vu3V@}9 zNw*s=>MUq@X`W(G>+tzJgd6bXv9Vx^T;JCdX0H}U~+(Mw$+Ww1bsj*JCH zwPXBAzHpwhx1fx7pS&S>BvtoL<~e<;a$8mY{0qH~lp)=^mv-|W+vk6GSW21>rnIDR zK=H-O;6(FfPc%`Wc)i|k#(?a$FuYXy9MG76_k)S5p)2)`{NnyZ!H1*!gy{9V8?C3ES;Qd#s z$CM6$uEqw6ed_P#zM-d<%4pb~-ul47As3uCpur=s&wXN@++Weshm_Xeezr?;(fw_C z=LuT1Swu-i=EnOvWHr=Lw0pTM`A~xOG(?=musEEnY=9T`D77|i!~)b_MEuU)<*Roo z?@w9bA@{&(^$?yvb@C7l_e?`ihbS7vZn4UIlXpCnUD)47;oTr?D!HiK6!}`HMYy&WIXK6&MpqK+*iyS6`Kx__7 z{ASEA(A;eX;&aUGh8O494$$}Dtipy+pEE>5Ih`|Oi55%3T?_$f zYT^$N8Uz-ud?F~tIe6x`X(cB7(X&R=Cm8l>247frrv93&#*A!%)$KKAeZ=nYn@eUm4Q`q zq?U_)DX%w547#U>8CCw>r+H5** zf@8(&_N78R)ugO&8pfV|FN|u>)J-8_~-dOd)h1RU_wD1BQlW2=9NphyM*@U#D zFDn^D7A32aWeO~3r7mYxy=UCzdI&vYJOUr3GsE7Ry|qYCX*H}gsWkF1Tfs}a+S*N; zKWz7E_DWh~8~&9AwGCHLQ4mn5osN7V{36@-f^EoiN?Vi{P{``U$&H$#2(R#RW&+z3Y`X{CL=VWcGb& zu2_wvrb?lJN|M9%%T^+_gxi&`27TF(!v``=7LRjBM^tixp0B48R2z6(bek!miG~4T8=UQ~?svFlT zo;M?Ef(?C53Tij8#nsNu(Iyd2NtGTgZ|xOs>Ne~?SG5SMtRpFr3Hy%rFneqJihG2g z=${FN9Zp!MKBuD3Mj;88jIOv6oC&5e4o0v6>kHOZu+>so*X)V{EdJ(8>mXN)+e*%U z4Gwj)&pV1c@x-0l{1c^uHTt^ZXd5?7k!TIrhpEhOgFqHS42 zzjYi5xbJ@dHPlC4@S?QPB_VI&4#5neiL~hS-SkW8r6PWUrb0U!+t5=Vk2_f&lRgg@ z5$~oKG#6hj?1w?GKyw|_=T(B*@I6N?d#ZZ^Bl~#|a<|+m+q|w^3zrFPpcuutQ=;JI&YyKc*Yx?2VdhvSt z2yttAGe7j-(5i!A>MbhMK^0d$mt`_bGBM+4hCfl3XfEecCtX)%HC}R~_-JfvY)@57 z^_TM)UaDEV8P?1cpb=0JFca|X%gh(vFSoxSuPE!yMi%cGNBs@o-WC0AyXz70Pt?cA z+Yv2$+y6=)F;fv#y@Q#(b!sT}P3*VWo)hs#lJlF}6J+jV!f_b&Dkq8S7B9sUBC8I; z$x_TQzHnE#o4SmS?4cRu7w89O5<{)HRPmNnsy>X{zq|Qs> zGhJ-vusCcj7M~NK^rx{nr6WZ(P29DHpcpliGsE6s=TMfBnRe%0aSDw1m?)kaGro`1 zQvb2iyK-;U+flWV(1`Rm4b_b*^du^*TE1Ht${VtlnUmSH%C`zOYcwlf?nX7>)w1-m ze`bBpKFQ{miM!5b?Q1bq^RBjZZJ3f3LGb?2tvi1P^T5G!_e(U=}Lr0vlhk%QUmO`_9tlL{f{NHr4cFtn-XK=q~`E*+_&1%%@ z+t{)TR}WX7dER<%`p&_^R~sueHO07gIq&hDCwI?>M6pFBMVTtaDD~89)`vO}TC5uT zTvnZ@92#!*5JF=mq83T9#FM6w>mfrSJ6tI4FE9RJcYH|qusSKa`4JRz&s(00ooRtZ zMSO)%iu6TS#DuSi26uJN*W-^;Rx&5~yI^w~F`9oj(s!Kuf8G1XzbUY){k#Md@e#2! zR)Ts$c~G``MNUx8DUNhp(NQw#I?WKW7Cag%8=4Uc3q4o5uRlL^f8pzC)x@)8s~4s9 zx++oK`<%;`ZwjoDLE~d37FV@{^p}srtu4n-IKTn{|FRr#Iq&1ckFuyW95GfgNVNqQ z{g9#WABG#!8cIGXw}kB9-tVM&{kEf`*A0jv4ZmEp8v}#6RVDPGYwE$LwZA@EboK_g z^bl4KmQWj%lFW_FiOZXp?ZWJ~`?~TX0+&zUv2L)!xNF26^lYQ2DKEFj?^oqk)e)VE zeJ}|rKlJPE-bt4zu(kNTbG@lVane-?jGEj0stleZi#?FKp+SNq%IFJ&{2mQ7{K8M?r^xf zI~+v^<&Hr?%EKXOlsh^cg+qe~&p|je1e1b#odP0ZK(F&5Bs%4grF_T|UCY&%udXL*$JVq7utpfAW!Cq~)vfZav1e=9J4)LuwIo$SQ2?#O z>5TN-e>7d4wWND_fn=Z>!aCPx#1ZP1_K>z@;j|==^1poj5AY({UO#lFTCIA3{ga82g0001h=l}q9FaQARU;qF* zm;eA5aGbhPJOBUzLPZp>)DD*xuJrLE&vMd$CAS~p-?-;7v0}#6W zK!*&q^nLraG8##gHcA0$>IMWyA3F6832+TiX>f2vout6F5+Ar6F)sEtHPYQAm=&QB zzRsNDFORoz&Rd@j_9k}3P_@Yj@S4LDdw+c%F*c^MW@FMmL^UFq*q*9=#Vw}!jD6ML zTLufTX7?w3b>Dtd?Gz(`Oz!9Ne%vt|je?%YYT1@aFN29GQVmgR!B8?Xp%fDaA%{f{ uQpjB7cbS-F*)`{!amLtrN{glG@TUKEuz}n1Y}Ahc0000 - - - - - - - - - - - - - - - - diff --git a/impl1/syntmp/s1_impl1.plg b/impl1/syntmp/s1_impl1.plg deleted file mode 100644 index aa50bf5..0000000 --- a/impl1/syntmp/s1_impl1.plg +++ /dev/null @@ -1,59 +0,0 @@ -@P: Worst Slack : -0.652 -@P: pll0|CLKOP_inferred_clock - Estimated Frequency : 1037.3 MHz -@P: pll0|CLKOP_inferred_clock - Requested Frequency : 200.0 MHz -@P: pll0|CLKOP_inferred_clock - Estimated Period : 0.964 -@P: pll0|CLKOP_inferred_clock - Requested Period : 5.000 -@P: pll0|CLKOP_inferred_clock - Slack : 4.036 -@P: pll0|CLKOS2_inferred_clock - Estimated Frequency : 1037.3 MHz -@P: pll0|CLKOS2_inferred_clock - Requested Frequency : 200.0 MHz -@P: pll0|CLKOS2_inferred_clock - Estimated Period : 0.964 -@P: pll0|CLKOS2_inferred_clock - Requested Period : 5.000 -@P: pll0|CLKOS2_inferred_clock - Slack : 4.036 -@P: pll0|CLKOS3_inferred_clock - Estimated Frequency : 158.6 MHz -@P: pll0|CLKOS3_inferred_clock - Requested Frequency : 200.0 MHz -@P: pll0|CLKOS3_inferred_clock - Estimated Period : 6.305 -@P: pll0|CLKOS3_inferred_clock - Requested Period : 5.000 -@P: pll0|CLKOS3_inferred_clock - Slack : -0.652 -@P: pll0|CLKOS_inferred_clock - Estimated Frequency : 1037.3 MHz -@P: pll0|CLKOS_inferred_clock - Requested Frequency : 200.0 MHz -@P: pll0|CLKOS_inferred_clock - Estimated Period : 0.964 -@P: pll0|CLKOS_inferred_clock - Requested Period : 5.000 -@P: pll0|CLKOS_inferred_clock - Slack : 4.036 -@P: top_tf|rd_clk - Estimated Frequency : 256.6 MHz -@P: top_tf|rd_clk - Requested Frequency : 200.0 MHz -@P: top_tf|rd_clk - Estimated Period : 3.897 -@P: top_tf|rd_clk - Requested Period : 5.000 -@P: top_tf|rd_clk - Slack : 1.103 -@P: System - Estimated Frequency : 527.3 MHz -@P: System - Requested Frequency : 200.0 MHz -@P: System - Estimated Period : 1.897 -@P: System - Requested Period : 5.000 -@P: System - Slack : 3.103 -@P: Total Area : 200.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: Total Area : 0.0 -@P: CPU Time : 0h:00m:06s diff --git a/impl1/syntmp/s1_impl1_srr.htm b/impl1/syntmp/s1_impl1_srr.htm deleted file mode 100644 index 3352fe1..0000000 --- a/impl1/syntmp/s1_impl1_srr.htm +++ /dev/null @@ -1,1777 +0,0 @@ -
    -
-#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018
-#install: /opt/synplicity/O-2018.09-SP1
-#OS: Linux 
-#Hostname: lxhadeb07
-
-# Wed Jun 16 09:19:13 2021
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-@N: : trb5_tb.vhd(8) | Top entity is set to trb5_tb.
-VHDL syntax check successful!
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
-@W:CG921 : top2.v(181) | fifo_data_out is already declared in this scope.
-@W:CG1337 : top2.v(270) | Net buf_rden_falling is not declared.
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
-@W:CG1249 : hades_modules2.v(170) | Redeclaration of implicit signal decoder_out
-@W:CG1249 : hades_modules2.v(171) | Redeclaration of implicit signal decoder_out_neg
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work)
-@W:CG921 : top2.v(181) | fifo_data_out is already declared in this scope.
-@W:CG1337 : top2.v(270) | Net buf_rden_falling is not declared.
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work)
-@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work)
-@W:CG1249 : hades_modules2.v(170) | Redeclaration of implicit signal decoder_out
-@W:CG1249 : hades_modules2.v(171) | Redeclaration of implicit signal decoder_out_neg
-Verilog syntax check successful!
-File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling
-@N:CG364 : ecp5um5g.v(757) | Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-@N:CG364 : ecp5um5g.v(761) | Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-@N:CG364 : ecp5um5g.v(1696) | Synthesizing module EHXPLLL in library work.
-Running optimization stage 1 on EHXPLLL .......
-@N:CG364 : pll0.v(8) | Synthesizing module pll0 in library work.
-Running optimization stage 1 on pll0 .......
-@N:CG364 : modules2.v(160) | Synthesizing module tdc4ddr_short in library work.
-Running optimization stage 1 on tdc4ddr_short .......
-@N:CG364 : modules2.v(236) | Synthesizing module output_decoder8 in library work.
-Running optimization stage 1 on output_decoder8 .......
-@N:CG364 : hades_modules2.v(2) | Synthesizing module hades_LVL1_raw_out in library work.
-Running optimization stage 1 on hades_LVL1_raw_out .......
-@N:CG364 : modules2.v(341) | Synthesizing module trig_inv in library work.
-Running optimization stage 1 on trig_inv .......
-@N:CG364 : hades_modules2.v(110) | Synthesizing module hades_tdc_channel_raw_out in library work.
-Running optimization stage 1 on hades_tdc_channel_raw_out .......
-@N:CG364 : hades_modules.v(2) | Synthesizing module hades_tdc_bundle in library work.
-Running optimization stage 1 on hades_tdc_bundle .......
-@N:CG364 : top2.v(230) | Synthesizing module trb_adapter in library work.
-Running optimization stage 1 on trb_adapter .......
-@N:CG364 : ecp5um5g.v(25) | Synthesizing module AND2 in library work.
-Running optimization stage 1 on AND2 .......
-@N:CG364 : ecp5um5g.v(367) | Synthesizing module INV in library work.
-Running optimization stage 1 on INV .......
-@N:CG364 : ecp5um5g.v(656) | Synthesizing module OR2 in library work.
-Running optimization stage 1 on OR2 .......
-@N:CG364 : ecp5um5g.v(810) | Synthesizing module XOR2 in library work.
-Running optimization stage 1 on XOR2 .......
-@N:CG364 : ecp5um5g.v(710) | Synthesizing module ROM16X1A in library work.
-Running optimization stage 1 on ROM16X1A .......
-@N:CG364 : ecp5um5g.v(959) | Synthesizing module PDPW16KD in library work.
-Running optimization stage 1 on PDPW16KD .......
-@N:CG364 : ecp5um5g.v(110) | Synthesizing module FD1P3BX in library work.
-Running optimization stage 1 on FD1P3BX .......
-@N:CG364 : ecp5um5g.v(119) | Synthesizing module FD1P3DX in library work.
-Running optimization stage 1 on FD1P3DX .......
-@N:CG364 : ecp5um5g.v(168) | Synthesizing module FD1S3DX in library work.
-Running optimization stage 1 on FD1S3DX .......
-@N:CG364 : ecp5um5g.v(160) | Synthesizing module FD1S3BX in library work.
-Running optimization stage 1 on FD1S3BX .......
-@N:CG364 : ecp5um5g.v(76) | Synthesizing module CCU2C in library work.
-Running optimization stage 1 on CCU2C .......
-@N:CG364 : fifo40_dc.v(8) | Synthesizing module fifo40_dc in library work.
-Running optimization stage 1 on fifo40_dc .......
-@N:CG364 : fifo_colector.v(3) | Synthesizing module fifo_colector in library work.
-Running optimization stage 1 on fifo_colector .......
-@N:CG364 : top2.v(1) | Synthesizing module top_tf in library work.
-@N:CG364 : fifo32dc.v(8) | Synthesizing module fifo32dc in library work.
-Running optimization stage 1 on fifo32dc .......
-@N:CG364 : modules2.v(3) | Synthesizing module tdc_channel_fifo_out in library work.
-Running optimization stage 1 on tdc_channel_fifo_out .......
-Running optimization stage 1 on top_tf .......
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB)
-
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:13 2021
-
-###########################################################]
-
-Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Divided design in to 1 groups
-Log file for distribution node work.top_tf.verilog  distcomp0.log
-Compiling work_top_tf_verilog as a separate process
-Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s
-
-Distributed Compiler Report
-***************************
-
-DP Name                 Status      Start time     End Time       Total Real Time     Log File                                                                                
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-work.top_tf.verilog     Success     0h:00m:00s     0h:00m:01s     0h:00m:01s          /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log
-==============================================================================================================================================================================
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:16 2021
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:16 2021
-
-###########################################################]
-
-
     -
    -
-###########################################################[
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49
-
-@N: :  | Running in 64-bit mode 
-File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Wed Jun 16 09:19:17 2021
-
-###########################################################]
-
-
     -
    -
-Premap Report
-
-
-
     -
    -
-# Wed Jun 16 09:19:17 2021
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
-
-@A:MF827 :  | No constraint file specified. 
-@N:MF284 :  | Setting synthesis effort to medium for the design 
-Linked File:  s1_impl1_scck.rpt
-Printing clock  summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file 
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-@N:MF284 :  | Setting synthesis effort to medium for the design 
-@N:BN115 : modules2.v(90) | Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances.
-@N:BN115 : modules2.v(69) | Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances.
-@N:BN115 : modules2.v(43) | Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@N:BN115 : modules2.v(37) | Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@N:BN115 : modules2.v(31) | Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances.
-@W:BN132 : modules2.v(138) | Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@N:MH105 :  | UMR3 is only supported for HAPS-80. 
-@N:MH105 :  | UMR3 is only supported for HAPS-80. 
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N:BN362 : modules2.v(262) | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N:BN362 : modules2.v(262) | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N:BN362 : modules2.v(262) | Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
-@N:BN362 : hades_modules.v(153) | Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
-@N:BN362 : hades_modules.v(96) | Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
-@N:BN362 : modules2.v(272) | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@N:BN362 : modules2.v(272) | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@N:BN362 : modules2.v(272) | Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances.
-@W:BN114 : fifo40_dc.v(407) | Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances.
-@N:BN362 : hades_modules.v(122) | Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
-@N:BN362 : top2.v(220) | Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-syn_allowed_resources : blockrams=108  set on top level netlist top_tf
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-
-Clock Summary
-******************
-
-          Start                          Requested     Requested     Clock        Clock                   Clock
-Level     Clock                          Frequency     Period        Type         Group                   Load 
----------------------------------------------------------------------------------------------------------------
-0 -       System                         200.0 MHz     5.000         system       system_clkgroup         0    
-                                                                                                               
-0 -       pll0|CLKOS3_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_0     787  
-                                                                                                               
-0 -       top_tf|rd_clk                  200.0 MHz     5.000         inferred     Inferred_clkgroup_4     64   
-                                                                                                               
-0 -       pll0|CLKOP_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_1     36   
-                                                                                                               
-0 -       pll0|CLKOS2_inferred_clock     200.0 MHz     5.000         inferred     Inferred_clkgroup_3     36   
-                                                                                                               
-0 -       pll0|CLKOS_inferred_clock      200.0 MHz     5.000         inferred     Inferred_clkgroup_2     36   
-===============================================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-                               Clock     Source                                 Clock Pin                                                                             Non-clock Pin     Non-clock Pin                                                        
-Clock                          Load      Pin                                    Seq Example                                                                           Seq Example       Comb Example                                                         
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-System                         0         -                                      -                                                                                     -                 -                                                                    
-                                                                                                                                                                                                                                                             
-pll0|CLKOS3_inferred_clock     787       pll0inst.PLLInst_0.CLKOS3(EHXPLLL)     reset_dl[2:1].C                                                                       -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv)       
-                                                                                                                                                                                                                                                             
-top_tf|rd_clk                  64        rd_clk(port)                           fifo_colector_inst.fifo40_inst.FF_1.CK                                                -                 -                                                                    
-                                                                                                                                                                                                                                                             
-pll0|CLKOP_inferred_clock      36        pll0inst.PLLInst_0.CLKOP(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv)  
-                                                                                                                                                                                                                                                             
-pll0|CLKOS2_inferred_clock     36        pll0inst.PLLInst_0.CLKOS2(EHXPLLL)     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv)
-                                                                                                                                                                                                                                                             
-pll0|CLKOS_inferred_clock      36        pll0inst.PLLInst_0.CLKOS(EHXPLLL)      genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C     -                 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv)
-=============================================================================================================================================================================================================================================================
-
-@W:MT529 : modules2.v(181) | Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W:MT529 : modules2.v(181) | Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W:MT529 : modules2.v(181) | Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W:MT529 : modules2.v(181) | Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-@W:MT529 : top2.v(305) | Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s)
-4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s)
-0 instances converted, 895 sequential instances remain driven by gated/generated clocks
-
-===================================== Non-Gated/Non-Generated Clocks ======================================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                    
------------------------------------------------------------------------------------------------------------
-ClockId_0_8       rd_clk              Unconstrained_port     64         trb_adapter_inst.FEE_DATA_WRITE_OUT
-===========================================================================================================
-======================================================================================== Gated/Generated Clocks ========================================================================================
-Clock Tree ID     Driving Element               Drive Element Type     Unconverted Fanout     Sample Instance                                                                    Explanation            
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-ClockId_0_1       pll0inst.PLLInst_0.CLKOS3     EHXPLLL                787                    reset_dl[2:1]                                                                      Black box on clock path
-ClockId_0_3       pll0inst.PLLInst_0.CLKOS2     EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2]     Black box on clock path
-ClockId_0_5       pll0inst.PLLInst_0.CLKOS      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1]     Black box on clock path
-ClockId_0_7       pll0inst.PLLInst_0.CLKOP      EHXPLLL                36                     genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0]     Black box on clock path
-========================================================================================================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Jun 16 09:19:18 2021
-
-###########################################################]
-
-
     -
    -
-Map & Optimize Report
-
-
-
     -
    -
-# Wed Jun 16 09:19:18 2021
-
-
-Copyright (C) 1994-2018 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify (R) Premier
-Build: O-2018.09-SP1
-Install: /opt/synplicity/O-2018.09-SP1
-OS: Debian GNU/Linux 9 (stretch)
-Hostname: lxhadeb07
-max virtual memory: unlimited (bytes)
-max user processes: 1031428
-max stack size: 8388608 (bytes)
-
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
-
-@N:MF284 :  | Setting synthesis effort to medium for the design 
-@N:MF916 :  | Option synthesis_strategy=base is enabled.  
-@N:MF248 :  | Running in 64-bit mode. 
-@N:MF666 :  | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-@N:MF284 :  | Setting synthesis effort to medium for the design 
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-@N:MF179 : hades_modules.v(140) | Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog))
-@N:BN362 : hades_modules2.v(74) | Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A:BN291 : hades_modules2.v(74) | Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N:BN362 : hades_modules2.v(74) | Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A:BN291 : hades_modules2.v(74) | Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N:BN362 : hades_modules2.v(74) | Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances.
-@A:BN291 : hades_modules2.v(74) | Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@N:MF179 :  | Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) 
-@N:MF179 :  | Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) 
-@W:BN132 : modules2.v(138) | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-
-Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-@W:BN132 : modules2.v(138) | Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W:BN132 : modules2.v(138) | Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
-
-Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:02s		    -0.86ns		 187 /       525
-   2		0h:00m:02s		    -0.86ns		 184 /       525
-@N:FX271 : modules2.v(262) | Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing.
-Timing driven replication report
-Added 1 Registers via timing driven replication
-Added 0 LUTs via timing driven replication
-
-   3		0h:00m:04s		    -0.74ns		 186 /       526
-
-
-   4		0h:00m:04s		    -0.74ns		 186 /       526
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB)
-
-@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@N:MO111 : top2.v(28) | Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND.
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A:BN291 : hades_modules2.v(74) | Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB)
-
-Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB)
-
-Writing EDIF Netlist and constraint files
-@N:FX1056 :  | Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi 
-@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB)
-
-@W:MT246 : pll0.v(60) | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W:MT420 :  | Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. 
-@W:MT420 :  | Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. 
-@W:MT420 :  | Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. 
-@W:MT420 :  | Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. 
-@W:MT420 :  | Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. 
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Wed Jun 16 09:19:25 2021
-#
-
-
-Top view:               top_tf
-Requested Frequency:    200.0 MHz
-Wire load mode:         top
-Paths requested:        3
-Constraint File(s):    
-@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
-
-@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: -0.652
-
-                               Requested     Estimated      Requested     Estimated                Clock        Clock              
-Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type         Group              
------------------------------------------------------------------------------------------------------------------------------------
-pll0|CLKOP_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_1
-pll0|CLKOS2_inferred_clock     200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_3
-pll0|CLKOS3_inferred_clock     200.0 MHz     158.6 MHz      5.000         6.305         -0.652     inferred     Inferred_clkgroup_0
-pll0|CLKOS_inferred_clock      200.0 MHz     1037.3 MHz     5.000         0.964         4.036      inferred     Inferred_clkgroup_2
-top_tf|rd_clk                  200.0 MHz     256.6 MHz      5.000         3.897         1.103      inferred     Inferred_clkgroup_4
-System                         200.0 MHz     527.3 MHz      5.000         1.897         3.103      system       system_clkgroup    
-===================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
------------------------------------------------------------------------------------------------------------------------------------------------
-Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
------------------------------------------------------------------------------------------------------------------------------------------------
-System                      pll0|CLKOS3_inferred_clock  |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
-System                      top_tf|rd_clk               |  5.000       3.104  |  No paths    -      |  No paths    -      |  No paths    -     
-pll0|CLKOS3_inferred_clock  System                      |  5.000       3.782  |  No paths    -      |  No paths    -      |  5.000       4.247 
-pll0|CLKOS3_inferred_clock  pll0|CLKOS3_inferred_clock  |  5.000       0.197  |  5.000       2.602  |  2.500       1.172  |  2.500       -0.653
-pll0|CLKOS3_inferred_clock  top_tf|rd_clk               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
-pll0|CLKOP_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOP_inferred_clock   pll0|CLKOP_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-pll0|CLKOS_inferred_clock   pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOS_inferred_clock   pll0|CLKOS_inferred_clock   |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-pll0|CLKOS2_inferred_clock  pll0|CLKOS3_inferred_clock  |  No paths    -      |  Diff grp    -      |  Diff grp    -      |  No paths    -     
-pll0|CLKOS2_inferred_clock  pll0|CLKOS2_inferred_clock  |  5.000       4.036  |  5.000       4.036  |  No paths    -      |  No paths    -     
-top_tf|rd_clk               System                      |  5.000       3.807  |  No paths    -      |  No paths    -      |  No paths    -     
-top_tf|rd_clk               pll0|CLKOS3_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -     
-top_tf|rd_clk               top_tf|rd_clk               |  5.000       1.104  |  No paths    -      |  No paths    -      |  No paths    -     
-===============================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOP_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                               Arrival          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]         pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]                pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[0]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4]     pll0|CLKOP_inferred_clock     FD1S3AX     Q       in_clk_synced[4]     0.753       4.036
-=============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                               Required          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]         pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[0]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4]     pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                      pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4]                pll0|CLKOP_inferred_clock     FD1S3AX     D       in_clk_synced[4]     4.789        4.036
-==============================================================================================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D
-    The start point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOP_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[0]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS2_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                                Arrival          
-Instance                                                                                             Reference                      Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[2]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6]     pll0|CLKOS2_inferred_clock     FD1S3AX     Q       in_clk_synced[6]     0.753       4.036
-==============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                                Required          
-Instance                                                                                             Reference                      Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                     
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2]     pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]                pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[2]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]         pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6]                      pll0|CLKOS2_inferred_clock     FD1S3AX     D       in_clk_synced[6]     4.789        4.036
-===============================================================================================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D
-    The start point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS2_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[2]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS3_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                      Starting                                                               Arrival           
-Instance                                                              Reference                      Type        Pin     Net                 Time        Slack 
-                                                                      Clock                                                                                    
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast     pll0|CLKOS3_inferred_clock     FD1S3AX     Q       valid_fast          0.863       -0.652
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11]              pll0|CLKOS3_inferred_clock     FD1S3IX     Q       fifo_in_data[9]     0.913       0.007 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]               pll0|CLKOS3_inferred_clock     FD1S3JX     Q       window[2]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[5]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[6]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[7]           0.838       0.197 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[3]           0.838       0.720 
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]               pll0|CLKOS3_inferred_clock     FD1S3IX     Q       window[4]           0.838       0.720 
-===============================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                              Starting                                                                   Required           
-Instance                                                      Reference                      Type         Pin     Net                    Time         Slack 
-                                                              Clock                                                                                         
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[7]            2.289        -0.652
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[5]            2.289        -0.594
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[6]            2.289        -0.594
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2]       pll0|CLKOS3_inferred_clock     FD1S3JX      PD      window_6[2]            2.183        -0.581
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[3]            2.289        -0.534
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[4]            2.289        -0.534
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1]       pll0|CLKOS3_inferred_clock     FD1S3IX      D       window_6[1]            2.289        -0.475
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]     pll0|CLKOS3_inferred_clock     OFS1P3IX     CD      valid_fast_RNI999V     2.183        -0.059
-============================================================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.942
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     -0.652
-
-    Number of logic level(s):                7
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        B1       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_0                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.992       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.992       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.599       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.599       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.942       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.942       -         
-=============================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.882
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.593
-
-    Number of logic level(s):                6
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B1       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
-=============================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      2.500
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         2.289
-
-    - Propagation time:                      2.882
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 -0.593
-
-    Number of logic level(s):                6
-    Starting point:                          hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q
-    Ending point:                            hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D
-    The start point is clocked by            pll0|CLKOS3_inferred_clock [falling] on pin CK
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                              Pin      Pin               Arrival     No. of    
-Name                                                                           Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast              FD1S3AX      Q        Out     0.863     0.863       -         
-valid_fast                                                                     Net          -        -       -         -           4         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     C        In      0.000     0.863       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71     ORCALUT4     Z        Out     0.168     1.031       -         
-un1_reset_0_a2_2_0                                                             Net          -        -       -         -           8         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        B0       In      0.000     1.031       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0             CCU2C        COUT     Out     0.784     1.815       -         
-un1_window_8_cry_2                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        CIN      In      0.000     1.815       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0             CCU2C        COUT     Out     0.059     1.874       -         
-un1_window_8_cry_4                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        CIN      In      0.000     1.874       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0             CCU2C        COUT     Out     0.059     1.933       -         
-un1_window_8_cry_6                                                             Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        CIN      In      0.000     1.933       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0               CCU2C        S0       Out     0.607     2.539       -         
-un1_window_8_s_7_0_S0                                                          Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     C        In      0.000     2.539       -         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7]                      ORCALUT4     Z        Out     0.343     2.882       -         
-window_6[7]                                                                    Net          -        -       -         -           1         
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7]                        FD1S3IX      D        In      0.000     2.882       -         
-=============================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: pll0|CLKOS_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                                                     Starting                                                               Arrival          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time        Slack
-                                                                                                     Clock                                                                                   
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]         pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]                pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[1]     0.753       4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5]     pll0|CLKOS_inferred_clock     FD1S3AX     Q       in_clk_synced[5]     0.753       4.036
-=============================================================================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                                                     Starting                                                               Required          
-Instance                                                                                             Reference                     Type        Pin     Net                  Time         Slack
-                                                                                                     Clock                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]         pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]                pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[1]     4.789        4.036
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5]                      pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5]     pll0|CLKOS_inferred_clock     FD1S3AX     D       in_clk_synced[5]     4.789        4.036
-==============================================================================================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      0.753
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 4.036
-
-    Number of logic level(s):                0
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D
-    The start point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-    The end   point is clocked by            pll0|CLKOS_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                                  Pin      Pin               Arrival     No. of    
-Name                                                                                Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1]     FD1S3AX     Q        Out     0.753     0.753       -         
-in_clk_synced[1]                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1]     FD1S3AX     D        In      0.000     0.753       -         
-=================================================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: top_tf|rd_clk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                         Starting                                               Arrival          
-Instance                                 Reference         Type        Pin     Net              Time        Slack
-                                         Clock                                                                   
------------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r29     0.883       1.103
-fifo_colector_inst.fifo40_inst.FF_13     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r28     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_14     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r27     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_15     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r26     0.838       1.149
-fifo_colector_inst.fifo40_inst.FF_16     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r25     0.863       1.169
-fifo_colector_inst.fifo40_inst.FF_17     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r24     0.838       1.194
-fifo_colector_inst.fifo40_inst.FF_18     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r23     0.798       1.234
-fifo_colector_inst.fifo40_inst.FF_19     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r22     0.753       1.278
-fifo_colector_inst.fifo40_inst.FF_20     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r21     0.798       1.841
-fifo_colector_inst.fifo40_inst.FF_21     top_tf|rd_clk     FD1S3DX     Q       w_gcount_r20     0.753       1.887
-=================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                 Starting                                              Required          
-Instance                                         Reference         Type         Pin      Net           Time         Slack
-                                                 Clock                                                                   
--------------------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_1              top_tf|rd_clk     FD1S3BX      D        empty_d       4.789        1.103
-fifo_colector_inst.fifo40_inst.FF_62             top_tf|rd_clk     FD1P3DX      D        ircount_9     4.789        2.338
-fifo_colector_inst.fifo40_inst.FF_63             top_tf|rd_clk     FD1P3DX      D        ircount_8     4.789        2.338
-fifo_colector_inst.fifo40_inst.FF_64             top_tf|rd_clk     FD1P3DX      D        ircount_7     4.789        2.397
-fifo_colector_inst.fifo40_inst.FF_65             top_tf|rd_clk     FD1P3DX      D        ircount_6     4.789        2.397
-fifo_colector_inst.fifo40_inst.FF_66             top_tf|rd_clk     FD1P3DX      D        ircount_5     4.789        2.457
-fifo_colector_inst.fifo40_inst.FF_67             top_tf|rd_clk     FD1P3DX      D        ircount_4     4.789        2.457
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR5     rptr_0        3.223        2.470
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR6     rptr_1        3.223        2.470
-fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1     top_tf|rd_clk     PDPW16KD     ADR7     rptr_2        3.223        2.470
-=========================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.686
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.103
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
-w_gcount_r29                                   Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.536       -         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.059       -         
-wcount_r0                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.059       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
-=============================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.686
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.103
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_12 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_12           FD1S3DX      Q        Out     0.883     0.883       -         
-w_gcount_r29                                   Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD0      In      0.000     0.883       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.536       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     AD3      In      0.000     1.536       -         
-fifo_colector_inst.fifo40_inst.LUT4_15         ROM16X1A     DO0      Out     0.523     2.059       -         
-wcount_r1                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B1       In      0.000     2.059       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.843       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.843       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.902       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.902       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.961       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.961       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     3.020       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     3.020       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.079       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.079       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.686       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.686       -         
-=============================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      3.640
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (non-critical) :                 1.148
-
-    Number of logic level(s):                8
-    Starting point:                          fifo_colector_inst.fifo40_inst.FF_13 / Q
-    Ending point:                            fifo_colector_inst.fifo40_inst.FF_1 / D
-    The start point is clocked by            top_tf|rd_clk [rising] on pin CK
-    The end   point is clocked by            top_tf|rd_clk [rising] on pin CK
-
-Instance / Net                                              Pin      Pin               Arrival     No. of    
-Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------
-fifo_colector_inst.fifo40_inst.FF_13           FD1S3DX      Q        Out     0.838     0.838       -         
-w_gcount_r28                                   Net          -        -       -         -           3         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     AD1      In      0.000     0.838       -         
-fifo_colector_inst.fifo40_inst.LUT4_23         ROM16X1A     DO0      Out     0.653     1.491       -         
-w_g2b_xor_cluster_0                            Net          -        -       -         -           5         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     AD3      In      0.000     1.491       -         
-fifo_colector_inst.fifo40_inst.LUT4_14         ROM16X1A     DO0      Out     0.523     2.014       -         
-wcount_r0                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        B0       In      0.000     2.014       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_0     CCU2C        COUT     Out     0.784     2.798       -         
-co0_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        CIN      In      0.000     2.798       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_1     CCU2C        COUT     Out     0.059     2.857       -         
-co1_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        CIN      In      0.000     2.857       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_2     CCU2C        COUT     Out     0.059     2.916       -         
-co2_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        CIN      In      0.000     2.916       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_3     CCU2C        COUT     Out     0.059     2.975       -         
-co3_2                                          Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        CIN      In      0.000     2.975       -         
-fifo_colector_inst.fifo40_inst.empty_cmp_4     CCU2C        COUT     Out     0.059     3.034       -         
-empty_d_c                                      Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        CIN      In      0.000     3.034       -         
-fifo_colector_inst.fifo40_inst.a0              CCU2C        S0       Out     0.607     3.640       -         
-empty_d                                        Net          -        -       -         -           1         
-fifo_colector_inst.fifo40_inst.FF_1            FD1S3BX      D        In      0.000     3.640       -         
-=============================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                                                                   Starting                                     Arrival          
-Instance                                                           Reference     Type     Pin     Net           Time        Slack
-                                                                   Clock                                                         
----------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19     System        AND2     Z       rden_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.AND2_t19                            System        AND2     Z       rden_i        0.000       3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20     System        AND2     Z       wren_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.AND2_t20                            System        AND2     Z       wren_i        0.000       3.103
-fifo_colector_inst.fifo40_inst.XOR2_t0                             System        XOR2     Z       r_gdata_8     0.000       4.789
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0      System        XOR2     Z       r_gdata_8     0.000       4.789
-=================================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                                                                        Starting                                       Required          
-Instance                                                                Reference     Type         Pin     Net         Time         Slack
-                                                                        Clock                                                            
------------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0              System        FD1S3DX      D       full_d      4.789        3.103
-fifo_colector_inst.fifo40_inst.FF_0                                     System        FD1S3DX      D       full_d      4.789        3.103
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1              System        FD1S3BX      D       empty_d     4.789        3.103
-fifo_colector_inst.fifo40_inst.FF_1                                     System        FD1S3BX      D       empty_d     4.789        3.103
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0     System        PDPW16KD     CER     rden_i      3.228        3.228
-=========================================================================================================================================
-
-
-
-Worst Path Information
-View Worst Path in Analyst
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-Path information for path number 2: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-Path information for path number 3: 
-      Requested Period:                      5.000
-    - Setup time:                            0.211
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         4.789
-
-    - Propagation time:                      1.685
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 3.103
-
-    Number of logic level(s):                7
-    Starting point:                          genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z
-    Ending point:                            genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            pll0|CLKOS3_inferred_clock [rising] on pin CK
-
-Instance / Net                                                                       Pin      Pin               Arrival     No. of    
-Name                                                                     Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19           AND2        Z        Out     0.000     0.000       -         
-rden_i                                                                   Net         -        -       -         -           34        
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       A1       In      0.000     0.000       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a     CCU2C       COUT     Out     0.784     0.784       -         
-cmp_ci                                                                   Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       CIN      In      0.000     0.784       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0        CCU2C       COUT     Out     0.059     0.843       -         
-co0_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       CIN      In      0.000     0.843       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1        CCU2C       COUT     Out     0.059     0.902       -         
-co1_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       CIN      In      0.000     0.902       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2        CCU2C       COUT     Out     0.059     0.961       -         
-co2_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       CIN      In      0.000     0.961       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3        CCU2C       COUT     Out     0.059     1.020       -         
-co3_2                                                                    Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       CIN      In      0.000     1.020       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4        CCU2C       COUT     Out     0.059     1.079       -         
-empty_d_c                                                                Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       CIN      In      0.000     1.079       -         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0                 CCU2C       S0       Out     0.607     1.685       -         
-empty_d                                                                  Net         -        -       -         -           1         
-genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1               FD1S3BX     D        In      0.000     1.685       -         
-======================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um5g_45f-8
-
-Register bits: 934 of 43848 (2%)
-PIC Latch:       0
-I/O cells:       186
-Block Rams : 4 of 108 (3%)
-
-
-Details:
-AND2:           8
-CCU2C:          121
-EHXPLLL:        1
-FD1P3AX:        69
-FD1P3BX:        8
-FD1P3DX:        232
-FD1P3IX:        50
-FD1S3AX:        321
-FD1S3BX:        4
-FD1S3DX:        164
-FD1S3IX:        41
-FD1S3JX:        10
-GSR:            1
-IB:             11
-IFS1P3DX:       5
-INV:            20
-OB:             173
-OBZ:            2
-OFS1P3DX:       17
-OFS1P3IX:       13
-OR2:            4
-ORCALUT4:       180
-PDPW16KD:       4
-PUR:            1
-ROM16X1A:       96
-VHI:            25
-VLO:            6
-XOR2:           72
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB)
-
-Process took 0h:00m:07s realtime, 0h:00m:07s cputime
-# Wed Jun 16 09:19:25 2021
-
-###########################################################]
-
-
     diff --git a/impl1/syntmp/s1_impl1_toc.htm b/impl1/syntmp/s1_impl1_toc.htm deleted file mode 100644 index 6b60a7d..0000000 --- a/impl1/syntmp/s1_impl1_toc.htm +++ /dev/null @@ -1,73 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/impl1/syntmp/statusReport.html b/impl1/syntmp/statusReport.html deleted file mode 100644 index c31e077..0000000 --- a/impl1/syntmp/statusReport.html +++ /dev/null @@ -1,117 +0,0 @@ - - - Project Status Summary Page - - - - - - -
    - - - - - - - - - - -
    Project Settings
    Project Name proj_1 Device Name impl1: Lattice ECP5UM5G : LFE5UM5G_45F
    Implementation Name impl1 Top Module top_tf
    Pipelining 1 Retiming 0
    Resource Sharing 0 Fanout Guide 1000
    Disable I/O Insertion 0 Disable Sequential Optimizations 0
    Clock Conversion 1 FSM Compiler 1

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Run Status
    Job NameStatusCPU TimeReal TimeMemoryDate/Time
    (compiler)Complete3380-00m:03s-6/16/21
    9:19 AM
    (premap)Complete25800m:01s0m:00s145MB6/16/21
    9:19 AM
    (fpga_mapper)Complete211300m:07s0m:07s153MB6/16/21
    9:19 AM
    Multi-srs GeneratorComplete6/16/21
    9:19 AM
    -
    - - - - - - - - - - - - - - - - -
    Area Summary
    Register bits 934I/O cells 186
    Block RAMs -(v_ram) 4DSPs -(dsp_used) 0
    ORCA LUTs -(total_luts) 180

    - - - - - - - - - - - - - -
    Timing Summary
    Clock NameReq FreqEst FreqSlack
    pll0|CLKOP_inferred_clock200.0 MHz1037.3 MHz4.036
    pll0|CLKOS2_inferred_clock200.0 MHz1037.3 MHz4.036
    pll0|CLKOS3_inferred_clock200.0 MHz158.6 MHz-0.652
    pll0|CLKOS_inferred_clock200.0 MHz1037.3 MHz4.036
    top_tf|rd_clk200.0 MHz256.6 MHz1.103
    System200.0 MHz527.3 MHz3.103
    -
    - - - - - - -
    Optimizations Summary
    Combined Clock Conversion 1 / 4

    -
    -
    - \ No newline at end of file diff --git a/impl1/syntmp/traplog.tlg b/impl1/syntmp/traplog.tlg deleted file mode 100644 index 49bcb5d..0000000 --- a/impl1/syntmp/traplog.tlg +++ /dev/null @@ -1,23 +0,0 @@ -@N: CD630 :"/home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/gentmp1842Qm2Ltg":4:7:4:9|Synthesizing work.top.gen. -@N: CD630 :"syng0rf3Y85":71:7:71:12|Synthesizing work.cmp_eq.cell_level. -@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 5 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. -@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 6 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. -@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 7 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. -@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 8 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. -@W: CD796 :"syng0rf3Y85":94:11:94:18|Bit 9 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. -@W: CD638 :"syng0rf3Y85":105:8:105:9|Signal t1 is undriven. Either assign the signal a value or remove the signal declaration. -@N: CD630 :"syng0rf3Y85":8:7:8:16|Synthesizing work.eq_element.eqn. -@W: CD280 :"syng0rf3Y85":17:11:17:17|Unbound component MUXCY_L mapped to black box -@N: CD630 :"syng0rf3Y85":17:11:17:17|Synthesizing work.muxcy_l.syn_black_box. -Post processing for work.muxcy_l.syn_black_box -Running optimization stage 1 on MUXCY_L ....... -Post processing for work.eq_element.eqn -Running optimization stage 1 on eq_element ....... -Post processing for work.cmp_eq.cell_level -Running optimization stage 1 on CMP_EQ ....... -Post processing for work.top.gen -Running optimization stage 1 on top ....... -Running optimization stage 2 on MUXCY_L ....... -Running optimization stage 2 on eq_element ....... -Running optimization stage 2 on CMP_EQ ....... -Running optimization stage 2 on top ....... diff --git a/impl1/syntmp/traplog.tlg.db b/impl1/syntmp/traplog.tlg.db deleted file mode 100644 index 83dfd3cc03d2d6d98a0b5e41ed7fde5d2ee2435b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8192 zcmeI1&u-c<9LED|p{47(!zK<>C99`Rs*(mM1bXOb$6*rN+R;j@swpyw0Sm_ti9^fO z9oTU%uvgeC>{)i&o9q`9`e#EcS2SB-JC5`7_xnNm#TKpOCY1zrMBrhGirQl>mC{}! zq-k0@`9d=(DX5o{e%!>@_m#A!Kl!x|vr-#hHTbBa2q*%IfFhs>C<2OrBA^H;0*Zhl zpa}fu1Y|0k-`q@%_atsJ;*l`KT@p^)^x^wP{iK0T>IcmRnvOoFE*j#%>EU1-G0OWl zSILx{fj;H8Cj0Ot9KoL*` z6ahs*5xAc~Yb}$ne|(xgd{r*)Y=tA<-3dCyGi!INW>#vZIjJjGtr3?!64FnUchQ9i z`nnfgIwPCu@QB@J*y-DCajA15Nt8X$LD23q2wJfI5%iR|MFjgiM|i&AgiG}1^uytq z-9#Stec~c1&?Gd1&=)x1uy~Yxy_(7Iy_>1ns#R)M%`DH5O9nQHH>zCfWWW=hHHYbf!zWSYlgx z{#|890yM$S9AsiRx&GV{B$7SG-C{O&4?=Wc0!cjd)%_h5c^yNl-T zZ90?RKb@H?D<&jMsLaBQZ0UHuO$NF{7_%7}5|$*)&v5J?8}(^GqbEFK^stKuhUZZ@ z*)!5NAl*pn5CifBWQGnUt`YZ416~!7sEjToVb3?MQsLMuG-Y?IRst!dIL-d`mXX5O IVScjwZ^}G+tN;K2 diff --git a/impl1/synwork/.cckTransfer b/impl1/synwork/.cckTransfer deleted file mode 100644 index 32050b5a12b29f85269561de655eca8f37e5b3a2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 459 zcmV;+0W|&}iwFP!0000015#C0RVXORFG)=pmWx%`l4>)zFk$xvCUk;NPs5xNc>s`uLliqd9inlM{IdtgIj@&v1+ z*D=RspW*9s-}|2PoIlQ7_qDEduf5h@pY_>m-xs%SXrrDz`R9ZBB|+J4UYwxk@cKn?OcuI) zH3KBV*Op5p7gMPFtw8Fz?F-y^kEy>Z20>!JR)2fLk^;p8E?Sm`n#b&UgBNwAhMhc1 z@c@6w6m#C%$LpQoFi8(tw^MlaK5xaxs3u_>aA(v)xq1!#*g~tgl)y;Sam!t2Za6l) z!vA@&qxDbQt2Pp8kK}L*vzxIo`K}|IQ}XI+{oWPk-}Z;nVqw4>VlUf1qqd-WKxUHU z=lrKrb-$bIQrTCUS4XZv7f+rR#A1rwa# zeurw%x3mxKM!<4jIeU8(vgVU8m!TH$*Qv3o^sP?P@jab_=W5 zE55<(hQZ{LRosagya_3d9jiI_T*|3cyEzuievb1=tTx8d@uMX4nf}ICWMl7$4x2f( zz^|MJ(_UYn?BgRB@8O|a&%r5826k`%@ErR!Nx)WM&oj2qd2_~c9=J0(J^cr6T799< zl4lsg1!pf{VsIQ@4jZjGdyP4K4PjAI*w0g5tE1>jlj_wybLHka^t#=FfhjJay!FfC z?d|<8*Wy`cGhsCO~R-T-Te&V;=g-cR~IA(i+FdnY(c5b#`6G=Vc`XP)g>ACv9i!Fb&P zs#8He=%f_S>In+;%g=xR_5IHI4TlG2$(PBZ2Gg%s zJ&O&~afF!;DLYY-T1s~|y=a0j6hvQwR|o#cr3v7ll}2g!bbSA#md`jC+Syk5=Uqkm z4dxX=QhdM+xEM^7a${k}^jmQ5v&yF>M1CHp#ZOsuQO06N^>Q{uhsR8uW+U1UEfy^y z*0lGDxO|;T9!ab^XA8fm^}&$}ASdqcp|cEr!0MvCNck&UIJo-Hvjy?{c~$*mLxVav z^~0HW6u#@SZrIjCdfpohIT6o&CaB+^B!^jV0{ozj#xchN-E8L4m&s(%wg?xO^9nOx zx;~I^<;zyFyZu+R`eNEM)qqM8BbSYKBF_U9w(2Smwb70dkDm^((;xoMi=bwHHn!OZ zhn>NL6@nS;rE1LTLl(JLy47})fjX3)wu3@IX$!qSHiJtm_*XZT&TK}83PE=SR0|;+ z^QcC3-^E?tX}!c>jvAi)vp(GGo{xp4e;LK!|AnO1RroH8%1C=eBID}@ep`^B<1)Uz zyr#WT)vM0^t`^f^qE=s{54f&hZ^l{HE7qDE&KFKrdh0!!PRJaT%Y3Bo_TbxJ2>$-X zIPFS3_(0idViiVxKwIMdkSbK|;0%WE;Z+;V#UFZ2NJ`_6N6~}9bcyc{9rx3qm2qhDC_FHHy^N64~SFSDx7_3G$ehgfUT9U{t+WHt) z@LStDys7xaOb66tehf!Mz=c`GItkKN{n7-iat_& ztC`Un7j~r+Nv0V5O4qB^>iD(=bf7g*uYE$jmqYgVQ|ybzSUc$!t;_U9euDA6!JWB3 z?c)>XV$G~G6I+Vj`#8StTrq4aD7_nJi#1x)^}@&4G=+9Q^EAPoiz&0I2mn8<*WC=)uEEy91+Txm&d-p=NqKJjiT z(7Tm(8!))nBj&s5({u5q#R4q;kleBz`Anxb^Z3R`Ec?^}4SJA@RkRdoRe`_m-JlVM(W4a^W>)CMHfG(Z6S}0iqp@Hb#Qh+k4m(&{vNy^ z0UBRpxob%$w@QGO)8j13q)i7ewMOa6Bw`X**)sA+7-q0us=c-!R&tLcXfp{peF_QI zuUoKLf7=8k^lj!v%uGn22j9u8vvWD}V{Cpi!&G6T|5RJaJL%y{KhKK!16za+T2yf= zpfk(?X2Mx&+Ve{xk1)xlQ^aYsJZ-VdFcXZPn0ZE*U-Q&9=O&{CdQ>Bk7}qP6UPXQu zdjMSX3(d@v<4yN8$HJAhkBi>^V_!^uWFPaAKo2)rs;hg{H2A%n6o-#Zg2a{QX(he< z2V3jzS3{E$(<{~9y%uhQS!`~$v+1E#@phLBvhFT-1^ z9N^HM^vXf_@ph>;IT*iuHG z%lNihRIAEc=aFBuk%}q1dA-j`9|(^^B)I$guQ^ zr9w?HwoM+JMcGf$*A|UFvXTx&TC-@Bc4P?X&auaK4W2p=smd*By&ePoxPMQ^e9IiW3=TOwwDDt@fLSxqF0Z z{}1`{iKq5D2c>}Z3!4>IWn!!6yL}*m4^u|9K>qsZQP|9Uw`1>vKPZ#_n)T$wzDp(SUG;uW*x}d$}05gz}cT<)VMuAz5qQbf|s5f~|6sY!4!uh7=5_TiKzY>Rey?ukmW+$C)-_h;wwK{yJkSjO4ZyS3fpqoDbPYEkAl=C^NXc`*yl zP=%_6=UXRZCh{DO)0?%Mgn<3>21m3P!kbEEjbD$y{h3qARwPklx}#Dnwz|Q8^AS%d z{Ao8fJhc+KMo4@S+hcFO^MN{X8PgD(dZm#EbL#T@zTU)mPs{F`fppEeF(935JH@*8=bdY7H*c5OJE zr7f%)oI7bO*%HY_MmO5_L7Y&qf2Js+K9>vs+xwK;YFC0!H(h4y2xeNIH?%7 zi77|`X2na6-D52_K`SlxC%HS7m_HsBFRW2L8Yjqq$w*o2GE#qGbM{6;oKAj-dT` za&%()`cvYIhqYra0YG&X%Aau4;Z%GvjVer6idd22F}3N*{Pgi+-mzwbG*wCYEJ?YE zOZ_yZ&uLrRj8>UvS{IT9YW|X920LB5t3|iM>P+AotyE6vvUGnVn1 zYCZcrW&dz`{xvZAQYgX{h>*#NK7`XAMuuCUEom)$>M^TRvYowrUE*$jDy3O$(G_Js z7ypi8R_C2iTi*`#tP1^&e*ZYAwKhKQPwQDW$Ntv*k6}ukq8|?1^FRLan;)-#CuD05 zy-onN=ElGI)4HC`vHgGdVx;y+Ykxyd(}=+u=i!iG&axM9)|8QK_b#${}w@ z8vX;l8 z+%4j4E#kZ`;w&TL{7u9;SH$@RGKJ4_3Zgv=(ayCKv)COINQJP5 zr;r#6z6x4z`1OOsJ!=;@ogcAyMMXRl=Kq?~-9KZS#=f{>^nW*QFRWL1XTY*pC zv?bB$($>UK-?1^FscG;l#%<&9Zz&(41d_H23FKI&uJjT(`^E_`xT=&05~ou5xp}(3 zNezX!DhZLryq20UYmck!wf;#*hjITgT0PUILnr^X?}-lgFPzgsfubZ^jEyC3ik-RC zT6@W390jF9LN|p4V}@Y$6o!dJc1BrZVFQbGDoF|jTLuzFM!|j4RrRh!EvY^(o#3oc zO_N$}Wms*@m}-BYo2_|ZR##>3vcRtwe>N|2RUIhh8boBDwdP+7w#|e(w`GZ7tz6{l zuGw|&W3ej}5PNdUenpl+n8?%0h@ngQo6A%Nlh{llJ_Yh3FJ|dk>{}vA3e##lsjigQ zsTtMhoMrHz>Zb~YN+!)e1Bimfh!3Fpe6X@BCVdWPToZ7s;S^g{-K-48fJX&C$mH^s=ZYp4gF(S(})*&1S0J@=Pq{TbeXKUF)!eP3OiTdux66XWDMij^9R~TUr|lWyh1~0r7*Bn z<1ubb(G&|(Lg!r)SFher>ZaDLS@V}?qT5Q2t={(gE<^+;IX~n|Jr|{}UwxwgOFiXd zF#pyOlX0-H67B$(BGnT=eUnvRd!@QteTF#sw;5eZ$BvX^f6QD3>VK_*o%--2ETz1@ zjRsM4A3l|-?3JJ{;ry(W$R65WiDu{6%az+9K2^;5x!#&IxTF#d{j0OWv@y@6jr@I)S7Xs2~#fmD_#jaz|XW?u199PqSOHUM3&3->&`p1?VyuzI~1m zJ;n`gF>Tki67Ix9kZk35gX)VQj zML1--2V5E4_{T6clvkA6FRV4NZkFlyknRPv+FiRUpVx2cvJ>-z<_=vG0SL+$Mk`iV z=po=pc=_Vh#s0>PkqhWvMWsz@J|#u=!IKlTbGiLv^NYq8sHl8$4U{Ou3IlUnmOEql zy&pN#Fn>lsImCt=B%&&kaqQLW!tCq?W`g*n9(!$C{g!NoV$Mgf31tSgQdiPbCTjf( z5Pe>6me_p1=Y|avKrHw#R)ojveG-u}%YLT5 zoCzm0CS5uj6UJ!J0ZLgJAUx88H# z*z@Zl{Rt;Pr^Al>8prS1Qr>O(gwd1%6YdRvA57kW9m5{K?6hR(#E|*yK{Z*gLCL^T z>`-gnKCAFXCah7RdU4m4>ocPGUeRE);@6SEQv_3K2bzyGD$us5sK4?}4;5pj$ud~b zSB&Cb?4Or-a;&n${Z*T;&glQ#?in~Z&GS#+E!;luddtZZ`NlpeuJJh%JZ*&UNVqB$5-34Z?yA z+Ao~&cQ1NS1a(_mm|v2HZS0vhrQ~pg9GKmBv}*f<1IR`qORiQUo7Xn3I*zOb+L-G$ zRtHUeJ+xn*maI%onHmz^A8h%0eP-iWWZ#_UpjCQlRkI<=*3vppQ$EtWRSsjn+PrI;|A7_I+G&FZ`401!V+K$r>y31f;n?(*US z>N(#PjKC{>{Vtrn8s0&|YS06;&Jox9E3?_c0`sk@??Mls5A@&|jLjOMJ^6MQ@_XaT zNc7f1c1%c0AYDbY>1kKbm_*QGn{qV{J=++|E4k#s<2LRAuWOj;)!}i1>yNuB8%(bF zedadNStYnMyaI2LgQe7l@u7w*TS$C@XN8U$B-c;YrIw%k@7Fj2Z3F!exl z+(y%!x$B_wgHY4li_^aW_}3mnAn7XfF+*82v#+^MkfYt)jRBF0(mj?|s-3+g0FB(= zzMZN~@n>B=Gv%7kcyY=xDF20XSPL=X>R#c$WbZYi0v29QhIo4qox|0d*oOy`wDv!P zCIxfnvx$Yrcn}s$fa6HrX%n<(7RSMkrtdS6^U(Uk z=M@7dM14=TFe@J9z{3Vu@yuN&??FwPo{TVp!c#CP*5yZ7C zsTGE${S4MMtw};&X%&M`^>u$y1axWGpGT+)Jowg&NY;FS9Uqq5prkJTNT@(a+YJ{? zE#DtboV+}~F>T=W{RA)?)ubB|@^t^NZT)z0`%(5ymrfDj5l^qkIFeiD!#E zp?v4Z`CQFKv3xNrihj*DI8Hljie_GFv`&rKPS>xGUxr)g%NSrCg&KHuJzL}qfIi~SQim+J)$7y{n#?*_R*6BqT z<&{?s*1V=`JA!z zZs7F9)yD5@nTB_(wj&<90F=*Sbh_*Qwp^boX>ibYpg^nniy5Ud;l5+f>o9 zv*%ZS)AwDwZrP{l-~4>iIsI6isz(Zz${kz$jdHb6qBRZUDJuFrfu9b%J{fv{I`H|w z%0;hF_a9nbn^hKzB`wCZ^&eQ`ubsl?jP|IKl_*Pk@Hh6#soJJ#hN5Nb4PwR=eu;g) z6=RN|iRCsFZEmFm`m=1w$9}4>pn&}5;Q5vHnSc*Qc+RCWUGo0wjIzmsl8&^#P>d;}j#awbvS?kQ#D~r4322WN^_tpN z6$;1E)JPavudV3bl>FxCCv2%xFW+Xr&;c_OX656gQkyH=KeOCcwR}>6x&VnXs`(j|U4M z_VP`0{gHlMGg?2$jC561?3@|xpI*`D5Yb4G-z3dVA>cxV|3c-Cv?pPtj6YGMFqT98w~3pI_X8bQ>wDEQDCR~g>KcaE-?HjVo zl!NBv4`z|3DcMidUKmF{RZt0h`<(L=Nn2HPxrh^IS_^y zacyuZcn7}4=iETa7j93&OgVX?Mq@mH`fuYSF#YR-t`{~6=YQmbi_(b?(xsC>X~b?^ zWrvjLYC$sr7w~yklg$x-N)acId9TZ2-gDpCLr6!VZ4SKOUrZv+$A7QxxKh(0-Mh*G z@d4hgKAdSS5+JyrL7Z6!?=I*_pJ9jb&u{qP%x_SbSpj2$Yg*d$V@<4p0brW05!XsT z?oef;lXSA;E8)rpJrOP&JN1P{C+3J*DJ|xZ?jv@Sn;2CjmHB?D(2$!UmCkS&K}9yV>nA3;917 z{D)R)PQM^G(>Qa5;dpI~vpa)=B>NT=9dQx|M5j65AitJwk*lPzu z1i_z~NOv}?&G5k7q}gtCitOeA?70IW{9pnm($&rCuAIFg^lkmmiSpHA$+-h>TwG<- z^@;eBbG6u?uHZ!O{A?2>tr8#XwF` zzkvda7Jos-Q$Z~T)}-BY5dgmm1)E*BVvMnL%x^7vYdf?%3JEp(nHs4lam7+-Jb-L! zKz5zfWC@|W-N!VF^9i%;vlJN-UchT=z-z;p@G`<=IufiQ@bQD zfZPJb8^xGw8*Ys`g*@IgiU<$|R)tjOw9F-dC|@euDuzhBgkmhWh;XZruoCdpFeXrs zesr=hQ%NmvqFQQn@|ox4Ga#U|PHLutkQdM?V%Pno)D}%gjec5%-qNnSnS!fcsR@XQp!BfjwbiOw34qmt={p zT+>A%f}XlREn|DJZgX<0zH>g}t;6i5sFuhoeEDZ6U}|^DJp|UXGTSWNBsA}zK}{lK zuzQ)45*?b>ap!W)PnL>!-hYrgS5-bOVGtT&)&iHxrfmpQ*!HtUm1kp?^@H6v4(W!kZ@IB*Sh{!p3h32~pa^59W zh73%ZQcM{ipC^Tzj-x-D;_(g$V}aeSv6l<GsGn(ZzT@51&-p!TaUpe!aLAru%f z*wXFFaSTo-J9r}kmPRXX2$Sg&8S4-+0W%37U?o2i=e0n5*AUjQn!%&?1Nb`_*zSyf zxqwQ8&|iuR3^d?Ly zO!kh8L{>ZZuWA#J)qXn!e1ikNol|7T!esWYvbv8cvb*fULxG*=6rC-w4y5$L9hyzl|oP?7-`;o}w4z37w_*K4;2&p2v;``{w`Yb~R4VRr*yZm91P zJGew~;O>QsLh%^TVA!>mu?DzyQD(?q%^<)6g;drQRtQhMQzPT2J| zhp*Dern|AdYA|}gPE%=!>Sc)9V2C<%!xRJuh>KOkGms#Nb^+pHuqVBCPnPVSK<%Eu z9w+*p43nAsrtTU`R)HeejB(VAQMrKH3VV_PdopboC~7EaQP7OhPXs~MNpt+KI=k0s zsvhesq#~ZPV*o+XsSQz)l;~HWAg=`=9(Bc7ERZ3K1i@_c$m)|dK;R)D5Dp0ZH>(jR zOA&&Q&Uc6lAKYbcBysI)8M}Zd)(x;OJBAC`0hLGz z45(QHI4f6lupYR~I6Jk$+I#Jcm+Xw8cE&KfhDSESPnJGj>Dz;mt%9`vyH!w`9$N)B z!TRByAG=F)??2C>a@bMBomw}J-u-E9vK{ZWRMg26zZ}g03M>bG-K=@QIxLGxV2!oWokIL zU~n4-pPx~@uNbf+fWWIkyA(q{xSQU%n@A}tzv6{E4Yecq?1Had(Salw>3n4v>}?nf zHVg(Vn6)%xsNAQC`xymq(jccDI;D8r!v8qvRCHW>;hJWS(ScwyP?6O~jL4@9M8p&f z8?=*QRrkhSz0{vx0cejqBZr0_N2wm$;~TOcQ-N68VKC!fJI*CLPN*H{|4$^^j+G70 zV|ySW{<}TM{%Mc6k2g*_!mC~}caIMm{fZSAeBeUY4`54k=upWCMK?G(5XofkBa=w* z|7H@OSl1<1t^%dlisAVPVv~tvd|LU=@kj#-0{ct)ZHj7Hf~a>8qR?|9_u-5}yNjJI zlT3FzAZRT#SkUm)p4>B*)>R&%V{|?{p*Ad;izuUDD)cYEZaNfrV|$<=+l#W^pSE{! zU~pAwAm^t3qdXw7qg;$GJ~g$K_2A&g#zj^ViP~Xy-ZqQQ#@iP80nhm+*Zy;+onM%5 z6=hpl-hx?|{yGe91n-f%2uy1VaxrqdtOzrbAjUPdMZ5sxR+?^)g_i_5b| z*W)^RzR78@!WpWMX^!KCsmo=|VvfW7nk#`PqWhHw4iWOq2o6OAiUtl@M3Cx>h>j96 z;pm`ol0>diYP%lsw?DWD93kSb&{-!V=`@*>?;>QPKSHd{Ks=kwUjdo3&q_Ex8 zO+c?x=wk$I%`&QeNoJkcZfsU?$2Hgkbg$M~WVC za)?%AKpL5n{pyce7IXQB`Cy(iPML;|<$SM{2kn;6+u|W1x4QNpeW*8UWXE^)FOol+ z5>N+!H2q8xEM?k`8{I9gfrEtXj&lGZ)2Eq`@K?|?gL}mdW>!9|`38apQBF<-L>s86 zPJKrYfIcF91u&DP%=}nb?1{0v=YD-=--Q}86Dv&A@q+EeA6?X6=qY-#>@0Y#?$^n7BT{(`b}1}!PI^OK8L1@Y?xTfCVIf3Npp zJ2T(ccM}-1XiDAWRI43nX}5K$X<=nmbg+&;f}))=IJu_3WpFZ1WN_*RRZv`y1q zWgvqF64ZS0-oW3~sFCWW^N{k~$gy#1FldX6fhf3`jE6{)Mv$KCGf7UKkSjHe%Zn8w z0TSyTp)G{b`PQ&L*1#A!h25yAM_G?9b<;%)xm?nO zL-C!>)bvI*wfgl4y%ExB!sejp`8lijafoxIPU2OZy zdzpe=2^COidcd-@ejBEZU`p;phv2&~Scq=SBrv-3s(#M@HPCR$UokA$)J^OPqW*{S zU1Y~Ke#?PjeRk>r4Jh@v@x?{V|mx?if3x~WmgHSDAUHg zC!DFP>2$N1L<3&NJp2S9jH#7@>X!^(-VstY&5(384TCQ;Zwja@Y=B>9bah*M<5A{p z2<(sr!8y5JXGlWAy+MLf-EJvlt^XMQ%R>QY327vRW|?&hOHUU zL;jIYYS2xc>jPA!9$zHvKh9-njcXZSUfk(q-wYkzLBjDNdX;Z6|epEqPVXTmI~d z#eL5=*P;ez z+qc8-lLkk1q+H1b2KCw9Jas^Cu5yxNyN z50<+~s+{h#Fyh)YVxDC*Tz&~urP07g_0CbL@b%=zWmbA%l6v}QXpx>$9J^9nATh%- z8Wz9A(?_-GfCS4uyZGt&;gFPA3h~Zed^N!fp>&x>fq1lZnWst&C`<`~#Io%X>o@#C zdnG+nOJYgH-^L?}cUpZ0vBr9^2%SHmr4yhqeQZanrZB(60CuK^O*Bt_ltuxRr%Hi= z#IKgop7B4b4+2b+l=wVMzn%Gmn)riIm6ijE`Iph~9@V|Z3OIEAn~&HNjR&E0 z^N_`7SnL_#H0iBW^RUuPynihk+Oul!>snR2G#_LexrI^#7h2riKcOQkrH^uBkV!Qsrrl zdPF`f2|V0#*gnf`9w#_wlP{xNZ{qppMe$*df@nk{{#sPjNHV;Du4yso-pcmb;44jv zuXJvJTsNB3S^$HMjSP`(xEQJ897V!y1prMGy8Bs&bk!z&YckGRG?M*OAzkML!Ps=1 zvr?popEM-1kdD)gN}_lPwqpHkYnp%n8O(w1fQ#}D7bPq77R^nqFhe#$?ftoeY8l;S z6Av1Y;_EyThw|7PJOJ{hdiM?ykRQ5?^C6Fpz*I|85MEeXMpv3g$2Lh2kTEbv(dqvb zR|RUI^6Jmj7{S)!A@u}-^=8%xxWblZ$NJfNMyUGXtrO43bHa>=Id`MG%woDgW?Yp+ z0~;Q+>=C!1Dd9a=1(q0gkax34ush+0P+rOdQl3uyS9MXLXh{Vk>A zfM8y2Sk|zY)Il(luZCT~?9$F`?(1eh1Jvh}q}MKL?(p!&&AHFj=~NM*B7YTuy5{Ei zW;Ur&XH|qJr__5}!)XT#JP5=cZ!2eD#q7J}-cP@qR%>wAj)k$zy^P=J-AglsZpZM} zQ_VT&)4ak9*^|a0K6kv&Qf01zf?=_=yHwfmhcfmzJHV#j_jt{e8QcDUJv&S8qoqoy z%mX5gu7>l=Sw;BSPuB!7S#mT5MqQ~W)iCBiVhj_dG|VLU%@EP*t(wT|+s{Ks_@Kga z=$bRdhpWX^ih@;&Y;_T_4yz`V-i(W_YKz8E`u08k_90Pal{3$2k#E`cqTZP(i1-|u zU|*PG3)=@py{nx0dN)JFm`5$XY8r(wiSo0r3VY{K5h~LJ3432EA_eI3Hq`EO zPbfP~T-u(X*P|BaTNOQ2lTSZ*2V3sVa#D8wyUl`Jg)We=jJoEY=34MduLf7z>_^3#F3X>Qy( zjR7V0s!&w(?^U5;PF@}yci$H{HoIqXH&be_RJWkt5$Z1E!!2{l`Cok8^yi?Htv{g` z5Gk^qLBXwIxn8NZ?=J_ZN>=Yz>sb!udcSAdP#wzu$&`V7z5yGh#jRo&UsVSoiYBLe z_3X`~U;pvt%7nS_7Nv4erSAD&9OqoI<@W~%BQPH@AOFqne>?AW9}Cp8}R#-dY@+_=2e&Zr_Z_F9a z4baQdC+uoSeBEjaU9YzTmK#`B^Z2juh=H6nf>byvdn#w({3|HfKC)pQ*oEw-0L@9=VY0-eq-=gD&<>- zsn9-PU0b?^7R`!YgN)!eHP3U;E;z67uf;^0`*39<`^0UAbpLxRFR_vr2iF4@9qPfR zm#ftsBBHC2c}k|nz}SGwv5xrqr^}LeG7p3k!H5^m%*)2L={5$>>E%Y+pTWFuig3M9 ztLfTh+%&x`rbp}%=kPFc8wTgsC=`R0M*XENu)yeOyJse$PX;FaGrp5bRhusR+Vhw1 z>r(Hi!I|Brk7FT*pxT2IgMlQKQm+=5>5V(1J?tg{ zRSMee+vulBvRRt-W??8U2kz8P=LX4J?md*dci|3f>|Pfdc2bx}`X}Y|AU>{`w^H$( zR+n?!YkQ~q$Ba8iD(RZcBySDk7Vjch=dNal&6XlKLQEoCT%r313*Tc{<;(KMj0E$m z$2+eR653GSsouONz-!9j`L3w-=EAS6;_`ca=qr`yjK7__kr*nG$+#jRs0~0@xPt7*D*>3O}pRMMGoCs`DIbCa_B7^5rD21D6{#|a2zh# z&yw)I&`g}8$?zd??|Xg;fVmWnT2B*ls0P#QVvd{*?i=TNx1x?okUMY8E!;6?3s9v46 z{`5M%YE^s_8~vof$gTCn!R)gR!HImUR9j8*W{S(;piB-6ah!0q#%XBE8!ZJtw_hqJ3B+b5g2<%8hmMl* zxtFesC5{;x=i3%5^`>9WrTCB0TQsN%?@}fE=Cssgm@u=@@%zNITAKB*G{Sgu^HJH= zK<~>Jsfd_ByZizF=^UoIYDe)rCxI};NQI5oH)7WG`15*{2}zbXLlgFhhVf1O>$G*k zG5-J(CgCkZ2F;wGI+l9!W$SKl;CcdsJG~a4Qk7H=t#ypi&ax%nnTin9bK*K~ z<5^xS3FI$IrsgwlzQgDMJzVC{%5p~&M4)<@y5h66`tK;57RKnofRM69(VrZ91KMZp zqiDygthSahTD%9N>tDS9OJAEB{ow2tGs>sn`6j;<{x*RxFuHKJ?`e$mi*;@Tf09m8 z-?Mu|WG$L{YbP1;1dK4>hJB%ZbMDiOa-m3F>7~aiF-1jnL zHmNqC(9Jt8sJW_?m5pTudZH4#cT{%T!Rmbzr%|nwx9?7qwA)Qco0Sw+YrzC3G4_0M z7~sfrR<^`D8_PEJAJ6CN$4f-5apHtPhby$RX+L8*DLqBGes`#@)fr*?6FH9VMzuXI(OKncCbzf)V-QeO&(+VgN>9+^V?EVGSCF6)u ztvW6Bi*4TI@hJ~uaIEa@Dq%dusTS)`oA~jy1V!kC$UihTmhCGa#JQ&7BGXM-u>|ri zcyQ$dxi!Jr$v1$)O8|jVVp~T-`0iODW1hzRnQ>qpe^y@Vgl?uFo&8_5SOUU6#;a8a zJ7-?&WIl8GelvG}VA^&gWyN%E#QJeyiIH?&EuYk!%hFLo!>+`;J<2lc(H7I z4?4cAbE_QxX$RY@NDQWn8ptFG95;*nBmDg5$oq2a0`!Gb~h33Kk@dlq`zE%V$Q^>(Z zS@5R&|KsZ|fZ}MjhT$iIJA~jC2reNwED{JVOK=D-!7aEf1a}W^A-KD{2X}W}WYGl{ zSmfW_``)+etMC3_)z&b5rjMVVVNQ3Sk>4p+V!iwR-AyeTtwX3UyQ9>1snWzAEx(F? zpj%Uq0`0^6W3G=t?;Aa&#kk6x=tZ|`*lxxJ=bFLP?+DD$xx0{qm$|PJiIyc|zdLi{ zeTo+wJ_h_yv(VTjj5P##ELmum?1e&cw7Q2ae&8(x?Uo&w3D`R*57fO>e*LB*S=2j! z2`P4DI-0Q8EG1-R@Ty6KY6dQ-Yu^a=0zOFMfxO0v@`Lrr8mE0)iql|QU^AF%?F#He z-?SO+)KDkVK>X_nW2ltr{j_}W^BFQ}u`1@z9|MIwYR@bxM5yS;W`$~pg#@3Xj z;?FRD3|1Zz_mgpDpo6P@Ca8rOn_Kf5bHKnGanLE(Gv3(63kxY}^KlXmR`$;gL!alB zc7XJxvrU+Ls1!TXnqBRsa;0TgBb$H&Yza2SN@slr>}wmc*=`SYS(hrMB>pE>d&p%T zFTV-cTcKuk%!-=_s)CeTOBs@8R1kIiEE4%XY1(l>SS`OYqfSGBDk*azHqxok8gu;$ znH5^pXreEOHVQ4d%y-d1-pka#XAg1ougLo1O64OEg2MZBce^vcvF7dN;py(vl|0Ds zd}8!)34lC{B<&b*!umx4Sa#%}d{_wTfwchcY8@qn*Zg4ia20mUV5jyhbkM?C;j?MnvP-m_L|a zg#cTjJ-Qj(^%4G?teC+_6e9F@BqlRLnKfNByM*%_~oT#G18zVA_UHQk|(X zns$CvGQz6xp-4r6Je@Zc{LL?dbwxQ*sxNR~-}Hc)B3i+2``!(=Atgp-Hw)CCEA*SoVrmyT9dJv8YchlG7Wbh5D84BU7vt3sQ z)Yq%|1RcI4$H4|@u@WAwusqPRZAR2>_l#0S#x;9Mi4Y+O?2mjhClR|31! zn%EDHS(b|#p1DlA>8!~FIH5h*ck4G_%;VDYGAk`b$XC=xTg7|f?w--5%c*HZ(Jau; z7J>sQ)|53uVvT4(zEdF1xv z$>GQ=TlzmX=RzbYWn5u-2_FvfXz)TKr4B&}1#pgc#!>uVAJ~)FqUJyRW}b9Bk57>1 zw6VJM7hjVer`-tC(WF&Z%ME?MttDYxaKjkxYRB)=ueMG}(pO8rCTPWGd)-ECm1SZX z+3Zq|-a8@eTiRcit=xMX&Wb-_kFhh9Jo~BQU@PR_?r}g7Vvs_l#MaJ|6QAL$l}?tH zIkh2F8UV4$INO5M3xm#Jbak3>K7MNF5&9PXu`REg#bSQD-DZVMb8Vxsw{`vVnAcBN z*8QggCx>5e=b_~)VqAlhM^NhQ^V4?gW(|&!&H8N`w)YF~P+wQ%K};prc@!q?E}d^% zkmg5A*Uv%;X45}0i20we7k^tM(^AB)2f)QXTWSQ8D*5 z)rRgrcK%Kd7ND@^JA3>ne7A=WSE$^wjm|LtEa9Hcjr!pNQgFj-;&3exsdT1ZcU_MH z`q07a+SM?QZ({T5{yA3Ef$ZYp<^h<&9-mHkhbW`-f4$y2tLa%EBVO+jH?Atgjcc~( zGhIz2jas?qIV$2%6G!}b%s`9+zmsf<(suH52aCfbp}Y9p1} z*L0(gWhlsB>?XjP#%0-OWqssw9Etp?tjsLLvO6&U6>;Jm7-t9x-a}a2WvO}0zIZB6&z4$9_eA^%0!?s5O zNe=GroyQwj_T`-%;Pe~c7o{gw->X)fo@xKY+W5(e3W>Ff<#brc{*E>8#c3uE$Grnt{23u3?U^7XW-*(owO+nH0r61OvV#v>3-*5O5ar)`|BFk4d zwRw)L^bM`9XQFkw3Fj?7n+IpdVL21nkLfN`*zM`*;YL<1n$%0D<{d%Vrk0FF31 ziURP(lLpOxluBUDy(!4k{x}e7Z6)=O$2hHb;)14!Fy{Aayar9wKK7`UJZf~K{``=% zpUs%>c=VLeXifHs$r6k)@ku6@%nrk^7DVJKn+91@)2a>FgmzpAv^rnOWPLg7Z6{ z;ptdLJM-T%0?8Mt6jNq?pS&{k6B)n zA_>5HRoSdgO89CFsUFz5;|7cPfRuR=K~^)n>tk2e)s`|HnG|h}1HO`8|y9ODT#J z=P|iT{<4}DbHFq&u9wb#nqcjsTTOYtgb}?ak^y>X?}8CtYwmjXt;W_(-Q^MP;=(gQ z>BTE6&pDR#I|bcoQC`H`u){`~xD?qvH?!MD(9zNkmSGZbm!Kr#bhEi)lDcEQHEFdHR_5WSE@V`P8BmBA(1g zm>Krh?hU@97#rqZ%_M;**)JX@wVSGzWeXl-skIJhYQ-t8s6I7mRc&&SXRMf`q3fZS zBgxm5u{n~U68Y7ktsK%@-?tCsjrD8}PDB727t&VU9iMr?-BcO^F}DE2h;zU#AYgW0 zqFC!{F?>a<5vj+J*6c)a+2lCl@shTvLvTf?`K;tpRB^Z``$TM!jO|{or%b`hdch;V zHb#(WxLwrXE&$19Ij8Q>+;Ucp-NPO7Ckwq}82ZQinv`o5SUGYO@x){Iz!z-p@C1GjqUw$_rC z7$$@$TY12J)M7Yk7Y zJU{MGS~pFUn;XYhkfeW0F2WlDo^sj&wgengF=MjMz;`Ac&a;%XQRbQ%D-t%pN4qmR zYPr?Xc7DN&b=JMB}98l~Cd+H2D?$O2}pVzG3T%G!h_+K{n|tZtQeY zLv)6ujd`?oLlZc24*bNjftCeLWu76Z7(68K3i-)@X(JWp`OfV=tY`0MZ#%j7MYY#O z^$G=(4S2M|r)tRprKDCURj$uO_k!w;-PzHvNDZPVG|D%%AE>3eLUV8OLEY-ME(q;6%(~ z8~S~#L8)4DOa`4SekrM{bdr(P<{eFD3gSXMuIT8Otq1XUM46MCPuz8$=<(Y%9=lUH^X!vUWm6hzlyCD4g29pbjz8g70qLc3Ew-Y zOE>y_YPz87I%bwDq1Q0YcI)(wf9E|!T7EGK&$K36_4_-Qm5W%TvMEa>6CH5&C^KaD zC7HEtv49SwE~?oVeWaLdgzh}+-<(#We>pu z;hbwAJ@*?ul;ylx|1EJuR`cS>{m;(sRut+TMhsUH*PXg8wOqB#jT1@HJ;VC@#T%^# zs?SO%Pty%X44ZF9O!lTz>3=uaOx&0tkEsMkIiB8LzKO9H^}+89xdMJyWiQ+o z-f)|HIOy$!ha*-?KL%fvL^qf37Za8OL72Rd;G=Bkx+d)E3Clv}RgO;Ii#weA&!8gH z(q-3#%*9Po-$>zMbOH1P&UsGC^wxUO6=0t*bt_~F+O@>y6r=3gKZnlo55Y)|hgP}9 z6q05!W}E9g$cX-3$@<1ci}sS-5}lhaT+5j4{n=qAmd6fZwH*Axt`t%}@+`V|Hyp#$ zZPN#=tgl@McYZ2(S8yPfmavk_Kg0~S+^syAsLl@XdeH0$F6&Uzjmd8J5$NILv>es9 zhebhWv!_xKWeAdq&z&YtG6lGNqCY=vs?i>G)^e7qoB@N%T7HB9k)r z;^_X8pD#8!rgLfGTG;OsZ4FXI1vKXoH0p6;+%e*X&f%6MwEtz>NG~!wyIP6@SAp%p z*Y+cR*nO?x^jDp{Lqgg`79*i+w+fY*JKilQ$uYlAMnvaUriG$oT7kCo4PBs z_;s~?d475JT#UErk_Y`AkF+l^gBNpAMG?8~Bb9Gs{UQbj%ZXW|OAM}8XDYuMMYnd? zhB`)34EE5R%pO$Rn&pd&5)nAk`oi4saL2~#e_{I-znDi!}P^| z&4QO7$)Ue%H}#5dNf9J6!OkhB&{S7)?1vz&Vx$%Hw@%e6(7C;Pc`c;2aXw;s1r}tinVTsn*jV~ zryFqXURg(9+pDgqf(54NWXdKQ`fMpJ_#S>m*-nZBbeA$a410J3&M{Z0mN-6M!$d_| z^lor$jeTC~6D0bm38{keM+?_+)@kLNX9**XvL(a2iYr!chn>`>!tv8J*DIamn>RaV zhb|b7%;@y45znUOHQi4j@?(%j{3kTt)bt3+38a z#IU`5=WbDC#M65v&&0y}HXr?Kk4_&Am$sb!q8)arYmfJ;>w^y!4Z?1_wZgWS>p3lj z#m^}VowX1^tTZ>3y4&+v#|t)dij{hkO4?G%*aF7lfxV8lkZvFIzD`MvjW>5`;S=26 zI(M5fkZS0M`_@?~#j}2rQ z*aKAawq^)nDfm%U4iz}37WCR-aZIJ#(rMq8HPT?b8e_<6(IRDW?`^C#m+E8H`~Lh< zljECjNPgoYa8a_AJ8Mi9Jrb-DF}7SbFdwXU&(YRfd8ICEFn1VtJ5OMuWrEoehSy~- zf|p|dhL7|pX1Kb4LWX0i&ntUkOw0T0R<3b5yIZa5{?9YFt_=N~_SyQZw{vE+_<93Z zUGZ75NW z6H!N|W6wR7o91yTz1Vs|OX@krcbIDh5VmRWf!@2V!1pdIeEFgZ`(tiT>$N(R&Zyc# zR<2}k-(njvPMrZ&!=C5gvr_%Q$2{3Oxtcp&8JJZfX}bHhJN$uvcbKo{qfI{ zedt6s$p_crJ?#N?`q81VtHh7vrq~C0%B#V9wEIm0wo>NW6$<-BHDw~kO8wxs;%|3A z!|$Z(dh&+7dyt4|LI_vWG()wE41aP(g|1E+zjHzDxnJEPY{1>RXISg|)HWxn(NpOn z-^ZNu#C{!gqEh)``;3Y=J}fA6YLxW7`}`cCd$wXtQ>20tAS==d5s1~`{o{csnqjL0^hHs7F&w2zOXDYTJDnM z4aH9lRlZ0RCbYVu4?i-j4*rwyNb+%$b&5?V2QxIBO(SaZpHh{ExyplVUCAFT#!(*- zQ}(i5Jg`GiQL6hV!_Lt03NDvT`xj2(gD~|DR{o5Z_|e;3@_*eH#C3;Wgn>;t%vJ*Le(9 zQv2qwUz*$r8?}dg)HV`#jy!syX8LCj>4@z zr~sR^NF+a+#}*%Cv;svmKAusDgfDggj1PG#HOc8$`sx=Te?I_Jl2*E7-?6D%56utK@>HDE4W%2#+ww)$T5tv znkWVz1j<(UgkLYgE)pz}9osqelv_aup*_uA;3mF`+X2GoK#o)6fH8@w9uG;6-{U#gz-et% zU3* z+A9|wT0U8NNrxckY``O1xRhk)=grW2dcGVSRCY*rPO&;!(tl*H{%1rv;_7)KL7=^6 zZk+DxN-T6-LqT|>-V4sDFFI)mQ56_;*^eizy5vr7s&Ze0OgzPJeRQeb2io)PMP_^d&YGv&@$#M3JEXD`UC(uaZG6kGjw3 zy(ET~Z{!ylKe-U1T4X3}8j~?-1j{xo2F1p5IWMI|EzEqIGVqlh&ZCs8QP&$K6XZG! zd?Ohi5;7r>XLd6t`4l|FZN{kR)B`#ls{Yy*ld;t_|tD_SJ7~TTJ&BxH0+|rY~2gr=067t>lkvgYnOIo(w#3dAH>Ii5O zoG`G}gaV_yCMqv&IiI<+b;$|u?iAbCp}>{9rT&M^)(Mdf_GgImMK5o5r$)mm6;xBy zhDs^9AbLWSo!+1TT*(2Ppt^)k?QRvMw6$ckvA<0g)z8q&c-!z4(|@- z*xA0$xAiqWzUMJ`zw<8DHk?ECl18+Hl=X6`GHbJ!|a_ zeP(@hW#B#jVqDUwpVPWv_C=+&npeXb{SGM>g_u zJap>?xRGeZs0bw=kk85!BSMMIF0O4wD&rJBP*^BUV9?0BH_9VCe+Q;@GW#GPvXQuu zWZs-48uuK|t@-TmEUNKL+$O+>G|DqHYD?(D%y`z_&HC{f~KVCI5zg=D28PCO818S$`}k^^OU0wj^cywuG7? zz&gJs;iG-QH(m}$kD&_kCDu?DX&FZ8f3;h`tMb&tl=RkT_duEDXA4V^Bw(RFv zD!mLMA{?TXn8Ll)6poNm-|=uSag93*+q(4jHc%cc*Q4+b5iY{{vX zUd7Nvopp2C-!WhzC8h9wQ!l5d6b|}=*`udu(`I<*u++*Lv8t@OIP#6lM>+z4<)19@9V9w!VG|ex6-{JBrxXfiJP^8QAc`K9(hX9!Wl28XK$~+`gpY zKospfGTvp)28~^e4mPIO#+di_?wL4_q14(mrxA`2j;`3K6^Oj$GpF|vxePJ>RROHo z{wxU_BQ=XJlTp*f8A4^1&=sbuDEu-oPmq|ZWNjOFY^kBJ<9WJZz%^o~JbtmeeGsy} zwe9V7fANkgHoTQ?|5WrWge#uNid(0A4U{BJ8=ug5=u5_%{Os9qFJO3^a*TJ!clVWX zyCNpk%Hhg_GZp+SM#T*IddkxMPa z3E#!@YJ3Z(&shx5BZ``?U3hynYgKUUMfRv7YHLTfFFuVTFN`cPe_byNk8N~xG*xw9 z$3%C`%q&VEQ}04N{k3)Jzo4-qs(kASC+1O|Z2oRbiZHWpL;tRe5Nb?MUm#0g8<%Wcvms^VfLA_{DEN zzUQ!aKH}_Retr)sy@Yzhjf2e%%nLmZ%|-U#KUb$Rj2tgnrH*O%C>inr`LwHFK;Pgf zDRn(CkBrtBzfF{l*CE+HqHz>9WKTA;`RgSOspe+#dY;Vr;j&6al(Slwi))deWScwv zQvkkPy$oOPMg7%rE%PhKO?2UFhn=htIwg{TVS_T@cwnrgn4>n`XGj=?+Ad;p2(*o$-^#-ee;3) zu5+m^(5b>!zofH0V*lifpCh$eGq6}KjVJvh^b&FNKbIIJW&TO>1~57lGBY@|hvOr> z>#dA@U}HiWSzJ9Z^-0xll4EsiY)Z&d!xp-?B;`nLTn>-o(!J zeB^S+8FCGZAypu$b&AQ4G%nXKpk#6Ea`OAwZSpFkCk;JmWeoVE)uDrBJAe`7TF%~B z;qP*??@-SEF=9aZr#{*I-hzgso?Vu-i^sEzr@&tvN! zLKko*N;egca~(ZXf+!lMg++wES?FcfgWNh{nCQ{(%}8lmiQN;MgM!6X&l&YftpWs#(&9di?Xl?5y{W+u_U1ioaxuOl zP1Cb~w%kF=t-E;nW!a)TsS7?N`;+&HLyqh*W}5y<`a1Ovr_yVpv7G}Njq&u=(&t!^ z)aog#{`M^A&Y!w9dmLA8Xrx?8&j2b8Nr&2v_BUMKNmlcu5*$~q0Z=Rpq0}e)yfQ-e zRBQJ87S6sIu1@?dqDrkEWck)Gc=Hj|hXtq89$Oq|gEz)ETiEG%LxwqZjZ3;kW~AfE ze?@rpMzv!HfKA$w-ndw~;=K%a&A#avD{Qw5fUoIbt)8_BHf?zDICRcfW#1fg#kxL` zuTnjvPQck=y`x%!pn*V(tB-5fiIA@egm=-XUgR>XSOYJU0={ zyv%j~y02b-bu(JZ*--t>mYKO&=^O4yvi8Q+jR*NYLBua(`XDtKxH8~plS8vB;R7XC}d9NjgInO2eIq}ZEs;g#I z9a~WbmSbkLwtkEoSpIl@XFY=Tb|ZUy_)Vghnarv4jcsvlo1Xawa%TC>plCbWqvPa~ zp5OswWiwkob1gq$TmzOY_;tc!mYcs~QlKH3Qv9GbNf@IUJ0{_$0L^LsuoSX=C-4I~ItoydJ zFXm%f_{Q`lcQc1&$1Eawwe|sx&Vq2>16Ef-xQ1Wd)DokuGp`(3X4JHl`3Anbs6ZIv zB=>*dB@+j%ZKp0bwv$U6Hre+axwZ7G@8HcoL zvFnG{GH3H;H0?7Q2oH-o_-3q^Ya^C|2Et*Ab+STc#%&8p~hjMN_=n~7|+WiT*XT*(9j9kHsv-uj83sFGVdanwA$2qyA) z_lLW=g#~;DEqquSU+WXo0f?>$Tx=cWI@Rjg&^5U1R(Icg zLGBO+_DT_15w3y= zFlEV$o*UgfbU$Z}dOrb01y*lPTprVagSlf4F7W`YQeisNP9ncJkgEPna&a@&{W926 z{BzdoUGpugZgxW7&C*G`&mWP%jf7F~vzn>sQcZcrlS>v*ddJ(nW*HC_EZa}m&8qp@ z=)I;pgJu&L9YuHR2TR+w99-m)vI4dC+hETDu%D3B@qMvVP?B!W50+WS{wMu?l!{4v zaJUDuO|ySoQPXdn?~-W&aj@KM*WH-)_ua&AD(Id_cjQM~yNV*3=+3 zj){u)P=7~BMc@`j#gecQ!x#8<9k)l-*2CneCxqXo5`Gsr#`Okxz$9d&wWT_7n`prSDF@x%k66moLpb zLC7C?VT5f25eQTSRPYC~WJhAT`bji_sBCaTAo?^79DN?xVK1q6V;yWy_yZ*oEMVjx z7ttnY5Jr{=)yAgTNfr)qM+s>HbFf6UoKvwsB83ak0pMNTSBf=%NSA^@gaO<!6bHd(-`)JZ_EMev2qE10>`R9t1XB%1R8OlH!aTdm z96;L%-7Z9r5CMd;pMVsOsP0Eua~V_mcqJ%&vM_t*@x=#7pqITdi*u zH^XKTK)~fJ0MQ&&-PtVee!{KvIGW(WzSt~ohTF}8Ax?Lgb0XZli+2}X6H$-1sSiFo z<{Kt;UY>N326aS_%>q6>G1(s`&X+*rmrHxni`~TIl0kYg#7g3r4F3qN`{~t-o{WRh z7B7BK#8hLz=h`@219c#wVaJq0%YGEsi&Mlxq(&$p{z5`mVQ+pk5pv@~p{f}|S5jlm z6U$>_p_A$vP_^o`abYAMY%vEL5<7_9znFt6L<|!ssXE4ksfWT1MWbu6AzDEc0gKf? zC?cvcyf(`CTz~f|y@r^gxK5iem_SSeDXva+H5RYWPnq4_eo&}~ROfcLs=|bQV<^;L z2&pUIHY?o%rgvf8(FOQ;RF^$UxWxT-@7s!x+$|*$BiLI=0wHyX1X(-%atSiAV8bD>nIPFz|i=asAA zJUWGC5VlSZ+yV(p=hF)Wj~vIpJh1-F!vLZdmWjTI08m&;24;p<1?c1;BA~LJrjpRm zUdGKLX#cN~xc_Y=;p!bFmY$Bt)5(8zr-=I7-4fB=&7@7^hcMn+4xx_b;-~USWtMl4 z9~xJEO8n)x`Yg^N8V526h;kr;PZTr6^Mt{p{Kuk;MbNkZgLtnJOVt88f{5UM)D<5= zsC%~LUj7f9u}FeNc@q7NC6d36-%D4R!ao-M z;0a2hH+3(sr_k~1UP6$5VV8?F{q=)!P!eMU$u_PeKIp;bVi zrOWfJiv`m5U%7DqqqHhQX)n&d{Qri=za0JhZ)k`Yw9TSp&(|WZ#8x0o;r9#S))(am zK@`CE467C99$lxuG=BZB=79*!+b4SE%R{S-wWT%Ec&j z{N5ohC*UF2$Cgzc=Mat(GZqq(Ly)Sl%MCxVXyp-NS|MR9R?Dzxi9&E|7lYhnv<6%J zC3U)Ay0Xrrzb$9cnna(MW>FrNFW)p29uchb-$F;k8K#wFAjM>O$6_(Q5MdPp!1~w3 zh(NCQ4?}OI)X7;Z1W2*)YfaQ3`1~u(1O5}{q+cO*3+VGX|3*O!_j>=SzbKyqG=5yO zA~Y#rL1^;fKblBqY6QaAv_dqh{#Wr}gyMh0??pADw?=z9l_k>uQeU-1LTs2uh$)HS z$3Xj+lD5%;1dID5dKD2hB8-vCW8*YriU{$28vn5ff`nu`=+Lxj{K5VU{_`U3c2U`7D>}px1u(8R9l6>N{Sr2NQZTi}7;9_xr*FOl-K5>}+Kn@ntA4 zqEVkS@eg%g(xbB=2afO*yB}w3%x*W`c9CP5=dE1mr_xK-Pr|%4a1kh9bZwQ0{vwA? z(#97bMtxD6i2ht=bfgU`xOciYeb|$7rv1}-i~B0OLUB(PM*3v_pU*XUl@TE!lGUI( z*vc7KI-p|||Dr2mVI{;kXO+ZEqyou~Zs9=`1T(V9i;) zVwkS;GpofK#c$|~;+@1d=hy!2Nk$J$=RFUwvkX|~wU8$RY_Zvf)?iIdBfHveCh>;a z2GrH%;LlA5>&8dY$!pv9?sCo`dl*LX%J?ggz2;e=7Mzlwwg^bFR5J=2B)DdPg5-N3u;Nyj3uF?t#b) zy#(=CR5A~M-eUruQ6*BBjq%{ryW$1mR?vMcC`EXUcLaFBoxV0dXyYl|nzW}!XHJ}6wPIPLB@A$G-9uoROD!KYGeAb;hJaP zf5_y91d$SKsQvWqVW3FB$E1B~sA&qBZN*{~En!fPtSukQXvN}2lxznJVf>%Ab=P{$ zylS9T^Bp5zvV{?xh1v_&uQ*f#j(3IDv`;&b;@b~)(L2Nw=XDnfTpxKRxYK#FEqT?0 zS)$C-^kdEx&0vZrIy3ci?4-#CUqQP|Ex2uzqVuUArkm}KX!XB>baxQ$wEpW(8?urm zo`{xNLFfZ32G1E>B<1U(jfsZ^_3xTDFK5aQs&&EOOd6_>J(A znkWtbD=1b|682NbD(mbH`M9pR2gu$Zk3Mko*q0|5uaR5t#Lcrk?iHL4@RN1uP&Up+ zDXxui@~&H~O#{u25Z?gmA}Jl&?O5D}rB8kH^cB?^&j@*1_|`%?5x({4tObY)>D~I4 z_H50qM=`M~AXdA@or<*}Yvf(8ayDEW{B6K|B7UnyCb*HAYN>O|aJE6}11z1i5H^&2 z?T{Ap#G{jFo2Fu*ka^RVdtq@~I?@W{O*eB)e*=3aIo6$p+JW>}NTkm7Gr|r;66}N% zY`El3?fLpIMUmeSc;TvzUz%wxLgSM9Yqf#96AptA+w zg}Q-Z)Z-(nxVWGh`i)}-URX)~1R_25e%On)_+HPnU>kB{ zIo+3sCPSv@tzx!((RaRH2=h)h6KPH{*o)xub=A6>;9TSa~=jyfr7lzC(1U<4fZvuylL9Meyu-Hom}>2d8U=36Eaq{_5G2r3mn-OW*M)KI59Y%%F+7Z7 zwG=AGAG94`KQ4#RIU;o!;uXiwl;HXm2-=>%8pTeqE8ovn9fZSMWZVh8A>KBc8_zpy+`{|SU^HOn`iQjLP|`sciBh%--~va%@td5Qsn zsmGyltuYz(*_MZu8=30hU8C+1VxvwX664or;dpItY2DeR&UGR;>xmKHD>UAKJs)$v zBj>Pq7IGLcKO?45>9&b96b~f+)cIa&QYZ3PJ@F@NPXBr1*X8}8!d^Y~#9y+C!3Sc0 za-6Q8s5pB%q%D+j$@@^(C}^G8qz-fFp4ZLU za~HAE#@(B~J_YT5)Rz+@w&`R8PIK+~!Wis5Jy|FyJAvQ9)auaQ`7b+2Bt@P7P_Axu z(*k4|DD(VKig!M}1IQ5IOn2?9c<-M@gnV}|Ld97PL$TZRJ9h8WC*Zs2!UCLUM~6Jx z0EuOs1EoVYxIuVWfX@^-cw01S?xDz(ULv*65*Jk z$Zk7_%>4i%=Mctlx?Gp?zf}F)2KM}VbW^} z%Usmf?p26JU+$^=(2qx?^DgWd{;Xjofaxn7?Li4C_doQMHGYHH5MZ_QSt`bxLDkhg zpyN#TcCcu_i*GnBzyWbCx|01@oB(Ne=Udg)tHP!&pyOIL?|Bh?rXB3`l;h4A5)yuX za9-GS2z2bt-fj`K-TVS8yq&lyyy?;*1GD5$*SF5UqEY zi6eC@S<}8ntRVw*Pmvh7xeH^%4R%_2H2O_r_3U|%f3tdhY#KjR3U}cgARv%fCtC9I z0y+XLec0cQ6Vyq&FI7{YK7P;?$;Pdk_|DhSvqw3yR@hdyGCKHfrKu(Wtyx512ptaS z6P|#>TER57UJR`rDoitK#^~^HoNK~CQ2!SLPKdQrwrGa-x8>eFl7wHC+YSaukWy3- zp`$^6cgHk$zN5iiPRC_aCE$o91Z0~PK|D@+4I-?nymByLg0NtL5FHM?J6dQrayyPB zKy!`;F0-0g@a5HXEHH_&9eg+}5F{A_4>vUUa=;P}568Yrl>bSpot%vLo$sw&xe6F1ftuX&ceYOnA3ZL_=e8$|{hOX+V$ zFA@l-$PB$dE-c@qyKRtl_aRn)yEPpoAF_|fO7O27lSP~q^v$1|`w>g7uUMarSPur0 zZzc+9=|RSooF>8<=9Z4!I4)g827ET=3_?t7VDU=fkk`7U+a~GAXCf#c#z{&3R12ZN zlnPI^oxbyHEP+zT=&w}8e3q=wHZ&KoBkLJ=5<>^m+#-1@2htV>N&8rR49nKy(p}4f zewZi<4Wtd2C~j%ZxR)KipjeIKDIU;qi>$ARsjnE&Sr}|F6Q&vg61w6>&LFWkhP40!1NglU&8oJG`hvK`Nqbl%ty zc=f#YXr4Wkd(;JGReQ%(R`{^PTONL{SYz*~S3fLu2${mKq2JZ(%I!<;gW$c}&79X{ z1{UXK#=FcLbd(cOmc9Co)=DdtrnNPoxVIByvUn9su8;Kr?t+iC?#AtM$)dfTA=Zf; zzBkZ;Cy@_7t8JH`h=FF{KQ&s9-hcSwruh;#n6&fL`#fogLr%CfY=17eIl2dEhK1EH zMlF?~F4(j_>8z}Ja}i@B|JO1(ff`?|cldFA5c}wgFE>@J_CpU48-S}+0@346RC$-A z{Y-d6$c;l6S2}%Zc`OrL&&DT9WYS2+_%^&}f~ql;;91Z%(aRoYIKH8=_DoZLanzz* z;hF}MkQidoXg(>|*T&i^brj7JDRj%vpehJuTE4ZFQRL@Wbq*3}utU4ju-H#5g3C2y zR`TDLgES7lFsDz|WYud#eR{qY_1UJ7uJbEbeI@~xeyGS(I#YphZ?+CKfwbBbefA!|n-=GqrYnu{_DMUCb;;ufRa;prkT+S+vz!7*3(-VyV3BRP)olwzN_exulpU)lE9 zZ2)KxOVPbK2`c1dKaLpSSDcRp6OI(#VZgUE=%zZkZ?uGw^S(QMKL~h+< zA*Cg0vO3k|d?Fp@$I5G|XY{L}8ZJmhi&s$+g?w^eZ}zWhErcd-avYwDj-X<4Y0$ zUe?i!&7uyi9_2nK|FESy4rY_=X{cDQZtWoB`7CL)L6(c}b zt69;ug>O!V&M0xG=Z|jxNKwDtBhj@^cFjnw2A->yFCTBh^EvuL#&Sr%E2uQBnOGij ztFcS1gw-S*)0~)^rDOb)D--P%Iz{{LEM8e1>dDtm^6HL>YJ=$3cN|p)n+Y1-(LAHo zVmRpZl?V=p+x6g-7-{j))09?*J=*x&+Ql9XmCdz{lgt-WL6 zh;p<#@XzV_tr4PGzJBfamPRx}`j3Z$XCJ+#N!!!?m}64oa@$rVO`nMMPCD1YLL#rl zjva)y0=*>kVC?DaTsLsx+1f#hW>?sk^&a3bSsmQsQb6r67PdQ)cJrGn8J3^1AX!jf zjHv{%hUdMnrV@cXm)_7Ya*r#{F26gYx^o$S%h(aTa{im%u|Ue#7QS5jVfonG5>j3y z+?X=8m|Lu|0DnITe5_%tZN=>TuT^IHv~BH|<=#G#`yln)Z5|xy1XLM*sCnapd}eAE zV}yH}{FyegHYeElylzEZ6TSf>Cu5)!OY^GK_*#qv0A~o;Po$c!uE?x;p3YwbR$Ks@ zNJrzbEQGOY3<`=0)b2FW<+8s${kX}-ok!ot@KO|nVyk?V6J&eOkkk>a!cz4bL*UD& zqupSybcFj!PN59-st zy;|+EZoTIMq^J7xKrJ4e)^a5GlUF*bHLrZdm}Ei-#!dbOp*8#YyKXjc)Lt+4pBK}? zgX3pvum=O}ZskMv;5#E##nFqbYfU6cHi3~HqCTx2_N#7t=MM%i`pO^dZw7<5?sl8s zmEVEt87>MT!z$l*SAluXfw^WPr*%Bny>U8aCi-p>`A;$qV%iN<$~q|tbcZCB4Cz@L zLAb@pW+T^Dku%kE`rG9wb1OeL79kcFWJ3h&sT}?+^H%nFY9wyet($E<&vWyv5B;wVjYs^dbt@`dEOQTZmY&U& zfzBng71uibTBo0Zjv%J+N+%~nWlB*vLobK@f_lF#?zeRkM+uz-R7#>rur9sK&6DBj zv(|7FpnbcxZ_mMgl8At6!&*_j_EfJu<(^ZmZ8S?=a{U~m=Vq>(gEcQxyWOLEqZi-y zda!uh>-}Ii)uZXEiO+@D@+HKmocYdu-08>Zs*?G(xT)oWgIwRs`<0ygL$})%-WFef zRzCk2sy1{l_Vd^B=OW8pZy1bP%DuhaZawrTcb%dYopKh z6U5a1(bkC3)sN}4-F+DR)L$2ky?JAA?#C|Vk*tinuBXj27X&y zlC=&KtjCC4H@S1%%*$cjQ?8u|5m|K1j`WwPzrw(aFM+IHq+CaER0xm)XiNIl^rL0{zNUOunno}T4UMhiM2EH1HTQjMu*0Cagb z5t37;C$URPZKME-d!8rDrZ!8cjZ^P^(#uO22O!ksO;|8yCsI(VIocWzYrTnxa8F%Q{@TB#gZdQ~ zP(QTvnkL$mL5gzco*n6CsGBvq)Y73YoS zGGkRebgVDqz?2r7zuv!(`}gga{SEMuSZ~s>Tqo|a4{(O*G~VbW1V7wYer#($wpml( zfSPop;}rX$@dtI9TwYo~vT4^g?QEQ#>OAAz9C+Lu<|y=8hRyifJPAaic^t4HCI)b5 z{e!4nc{y^4>g<3$Ip9B-7*+AIq^QoMm<2pGz#ou<-L+-fs}cls*k`dCjG9knbn z!*kQ;S0;vDNv`yX4bz&z>|(wJ$VtfQx@gTJsVRAqWgqI|YY|oF;@iDSi#)+WG(>rv zvn9E94)Q>4(rYlB#DNZC&VWxEK_aNXQ_C}Lps>)>GGusOi=qGO*(KeeHCt1_SxICD z!*96ualTRl$v=tXsm#1qKAa(@Q??<&wZ8^yo9py67R(#UNy8}2CIAQb-~2wSbHJ^C z_&h6fXQY-a3VqISp0hBLJYlE)0?!i2vjQEZky$h3SkJxGw~-(89ou_?ULx9rGNn)y zR^>){|H$*heZj~O5(2cY=_69SJZpS{-tn=2LIN&HfDvIQy+L4?w|eI|j6YpfdN7@^faEo z5zN82G70QuMPlqT+VHHiy(T#j2d3AC_|MRce2#vxt9&4lSlSp?AGDRUQG9nOvC^$DvnGA`yk8BaORVhhjZbm(({6+Eyi{y;T};cSQ)i)UW#o!3*k60+=62U_h`Of${X5@098OQ zDatq8_L6-ud&Ob>hUdb^+4^D}W5Dk*pB4U?9PTLZ^)-!!C4HDM_z67ZtSp}Y$6OZA z{^s|E+@jxAo{XkJmX=t5tWCxL&ebl1`wP|{xhKZ%0v7R_Fk$Ylz6xv6=%y@flN?fvFvbMB=)%3pI>n1gxq zo|3D29WeB1y8GgP`LvsI{qpSV?#uU`|LKeV`aR7#uljU1`}D>C+Qqf*8`dk#p3i2@@8axWHh%g7fQQe`Kp&(gAS0Q(u`|`dwyhj|w z(O3di=amd%yx}2`m-;>eUa+9%G#{-4o#E^XV7}Qo86t>2?!SF_U-Oo`AkR0dM*^-* zBnqiEtaHi6h~T?x(Sx~LXh=3;7VA*B7<5LmCzL2)3Z#*invC;8bt=CcC=sli=3N^6 z&2rD#+TPN;w9he)&&f2nW~$D+`-{9E-y@Fl<-V6Mz;x5+RsV9o#z0|xOuw1=huP`m zHryBe>K=boZ}(l?c#hrhGauh2H+}Z2cn^K{=AE*C{OsdCWYu}_-0Rr4*#A)f7Yw?; z#vtCweR5sdK~7&>f4B}9C-NSg0Y1w85&tpo=kBuD$J`Jt0#j@vID1s*k`4U76(Lj) z-yVT?aDRXf>~!3bXh}tT0)5dWm1Cvz&cUy;;|~A#vp)Ybvp)Zev;JNEkIee~PtW>a z#QO(k{kuMVWY*_@dDg#QhhNP4cm4l=&HB8a^{xK`00960;&M>n0ssI2|NjF3nVZ%N Hv<(6P7{8?_ diff --git a/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl b/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl deleted file mode 100644 index 0352194..0000000 --- a/impl1/synwork/distcomp/distcomp0/_info_mixed_hdl +++ /dev/null @@ -1,3 +0,0 @@ -work.trig_inv -work.trig_inv -work.trig_inv diff --git a/impl1/synwork/distcomp/distcomp0/_slc_mhdlc b/impl1/synwork/distcomp/distcomp0/_slc_mhdlc deleted file mode 100644 index 8ee23fe..0000000 --- a/impl1/synwork/distcomp/distcomp0/_slc_mhdlc +++ /dev/null @@ -1,8 +0,0 @@ -pll0 -tdc4ddr_short -output_decoder8 -trig_inv -trb_adapter -fifo40_dc -fifo32dc -tdc_channel_fifo_out diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo b/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo1 b/impl1/synwork/distcomp/distcomp0/distcomp0.SideInfo1 deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.cdc b/impl1/synwork/distcomp/distcomp0/distcomp0.cdc deleted file mode 100644 index bf7c90d..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.cdc +++ /dev/null @@ -1,27 +0,0 @@ -define_directive {v:work.top_tf} {.noprune} {1} -define_directive {v:work.top_tf} {.distcompnoprune} {1} -define_directive {v:work.fifo_colector} {.noprune} {1} -define_directive {v:work.fifo_colector} {.distcompnoprune} {1} -define_directive {v:work.fifo40_dc} {.noprune} {1} -define_directive {v:work.fifo40_dc} {.distcompnoprune} {1} -define_directive {v:work.trb_adapter} {.noprune} {1} -define_directive {v:work.trb_adapter} {.distcompnoprune} {1} -define_directive {v:work.hades_tdc_bundle} {.noprune} {1} -define_directive {v:work.hades_tdc_bundle} {.distcompnoprune} {1} -define_directive {v:work.hades_tdc_channel_raw_out} {.noprune} {1} -define_directive {v:work.hades_tdc_channel_raw_out} {.distcompnoprune} {1} -define_directive {v:work.output_decoder8} {.noprune} {1} -define_directive {v:work.output_decoder8} {.distcompnoprune} {1} -define_directive {v:work.hades_LVL1_raw_out} {.noprune} {1} -define_directive {v:work.hades_LVL1_raw_out} {.distcompnoprune} {1} -define_directive {v:work.tdc4ddr_short} {.noprune} {1} -define_directive {v:work.tdc4ddr_short} {.distcompnoprune} {1} -define_directive {v:work.pll0} {.noprune} {1} -define_directive {v:work.pll0} {.distcompnoprune} {1} -define_directive {v:work.tdc_channel_fifo_out} {.noprune} {1} -define_directive {v:work.tdc_channel_fifo_out} {.distcompnoprune} {1} -define_directive {v:work.trig_inv} {.noprune} {1} -define_directive {v:work.trig_inv} {.distcompnoprune} {1} -define_directive {v:work.fifo32dc} {.noprune} {1} -define_directive {v:work.fifo32dc} {.distcompnoprune} {1} -define_directive {v:work.top_tf} {.distcompmodetop} {1} diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.fdep b/impl1/synwork/distcomp/distcomp0/distcomp0.fdep deleted file mode 100644 index 3dd41e2..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.fdep +++ /dev/null @@ -1,54 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-distcompsynthmode|-cdc|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc|-mixedhdl|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-top|work.Uart_top.uart_top_a|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc":1600097169 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075 -0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl -1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl -2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl -4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 -1 -1 -2 -1 -3 -1 -4 0 1 2 3 - -# Dependency Lists (Users Of) -0 4 -1 4 -2 4 -3 4 -4 -1 - -# Design Unit to File Association -arch work intface intface_a 0 -module work intface 0 -arch work modem modem_a 1 -module work modem 1 -arch work rxcver rxcver_a 2 -module work rxcver 2 -arch work txmitt txmitt_a 3 -module work txmitt 3 -arch work uart_top uart_top_a 4 -module work uart_top 4 - -# Unbound Instances to File Association - - -# Configuration files used diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig b/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig deleted file mode 100644 index 93040c2..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.fdeporig +++ /dev/null @@ -1,51 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-distcompsynthmode|-cdc|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc|-mixedhdl|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-top|work.Uart_top.uart_top_a|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc":1600097169 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075 -0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl -1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl -2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl -4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 -1 -1 -2 -1 -3 -1 -4 0 1 2 3 - -# Dependency Lists (Users Of) -0 4 -1 4 -2 4 -3 4 -4 -1 - -# Design Unit to File Association -arch work intface intface_a 0 -module work intface 0 -arch work modem modem_a 1 -module work modem 1 -arch work rxcver rxcver_a 2 -module work rxcver 2 -arch work txmitt txmitt_a 3 -module work txmitt 3 -arch work uart_top uart_top_a 4 -module work uart_top 4 - -# Unbound Instances to File Association diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.log b/impl1/synwork/distcomp/distcomp0/distcomp0.log deleted file mode 100644 index 86ee22a..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.log +++ /dev/null @@ -1,273 +0,0 @@ -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":28:40:28:51|Ignoring property syn_preserve -@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":34:16:34:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name. -@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":40:16:40:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name. -@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":46:16:46:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name. -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":177:44:177:55|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":178:53:178:64|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":179:52:179:63|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":182:46:182:57|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":183:57:183:68|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":184:56:184:67|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":220:44:220:55|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":221:53:221:64|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":222:52:222:63|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":227:46:227:57|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":228:57:228:68|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":229:56:229:67|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":345:31:345:38|Ignoring property syn_keep -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CS141 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":141:16:141:28|Unrecognized synthesis directive syn_black_box. Verify the correct directive name. -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! -File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling -@N:: Applying property .distcompmodetop with value 1 on module top_tf in library work -@N:: Applying property .distcompnoprune with value 1 on module top_tf in library work -@N:: Applying property .noprune with value 1 on module top_tf in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo_colector in library work -@N:: Applying property .noprune with value 1 on module fifo_colector in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo40_dc in library work -@N:: Applying property .noprune with value 1 on module fifo40_dc in library work -@N:: Applying property .distcompnoprune with value 1 on module trb_adapter in library work -@N:: Applying property .noprune with value 1 on module trb_adapter in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_bundle in library work -@N:: Applying property .noprune with value 1 on module hades_tdc_bundle in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_channel_raw_out in library work -@N:: Applying property .noprune with value 1 on module hades_tdc_channel_raw_out in library work -@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work -@N:: Applying property .noprune with value 1 on module output_decoder8 in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_LVL1_raw_out in library work -@N:: Applying property .noprune with value 1 on module hades_LVL1_raw_out in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr_short in library work -@N:: Applying property .noprune with value 1 on module tdc4ddr_short in library work -@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work -@N:: Applying property .noprune with value 1 on module pll0 in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc_channel_fifo_out in library work -@N:: Applying property .noprune with value 1 on module tdc_channel_fifo_out in library work -@N:: Applying property .distcompnoprune with value 1 on module trig_inv in library work -@N:: Applying property .noprune with value 1 on module trig_inv in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work -@N:: Applying property .noprune with value 1 on module fifo32dc in library work -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":168:12:168:23|Object fifo_in_data is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":169:7:169:19|Removing wire fifo_in_valid, as there is no assignment to it. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -@W: CG1340 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":108:51:108:62|Index into variable hit_valid could be out of range ; a simulation mismatch is possible. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":187:37:187:56|Port-width mismatch for port raw_valid_vect. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CL134 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Found RAM hitbuffer, depth=4, width=24 -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_0_[23:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_2_[23:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_3_[23:0]. Make sure that there are no unused intermediate registers. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[9] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[11] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[2] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[3] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 3 to 2 of buf_drop[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bit 0 of buf_drop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 9 of drop_cmp_buf[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@W: CL265 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":273:2:273:7|Removing unused bit 2 of LVL1_INVALID_TRG_IN_dl[2:0]. Either assign all bits or reduce the width of the signal. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":795:12:795:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":843:12:843:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":891:12:891:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":947:12:947:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":47:14:47:14|Port-width mismatch for port Reset. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Input RPReset on instance fifo40_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 34 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 35 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 36 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 37 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 38 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 39 of data_buffer -Running optimization stage 1 on fifo_colector ....... -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":54:1:54:6|Pruning unused register test_cnt[31:0]. Make sure that there are no unused intermediate registers. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 34 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 35 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 36 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 37 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 38 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 39 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":51:7:51:19|Removing wire fifo_in_valid, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":52:13:52:25|Removing wire fifo_out_data, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":54:7:54:19|Removing wire fifo_out_rden, as there is no assignment to it. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":59:12:59:23|Object buf_positive is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":60:12:60:23|Object buf_negative is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":61:6:61:23|Object buf_positive_ready is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":62:6:62:23|Object buf_negative_ready is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on tdc_channel_fifo_out ....... -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":137:23:137:34|Port-width mismatch for port LVL1_offset. The port definition is 12 bits, but the actual port connection bit width is 9. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":199:19:199:19|Input raw_enable on instance fifo_colector_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":194:18:194:30|Port-width mismatch for port out_data. The port definition is 40 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Removing wire hades_raw_valid_vect, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":66:22:66:29|Removing wire tdc_out1, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":67:11:67:18|Removing wire tdc_out2, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":178:13:178:26|Removing wire fifo_data_out1, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":179:13:179:26|Removing wire fifo_data_out2, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":182:21:182:28|Removing wire in_empty, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":183:21:183:27|Removing wire in_data, as there is no assignment to it. -Running optimization stage 1 on top_tf ....... -@W: CL318 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|*Output hades_raw_valid_vect has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. -Running optimization stage 2 on tdc_channel_fifo_out ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[1] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[2] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[3] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[4] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[5] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[6] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[7] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[8] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[14] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[16] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[17] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[18] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[19] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[20] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[21] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[22] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[23] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[25] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[28] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[29] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[30] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[31] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 31 to 28 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 25 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 23 to 16 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 14 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 10 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 8 to 0 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":6:10:6:15|Input coarse is unused. -Running optimization stage 2 on fifo32dc ....... -Running optimization stage 2 on top_tf ....... -@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":185:48:185:56|*Input fifo_data[95:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. -Running optimization stage 2 on fifo_colector ....... -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":5:8:5:12|Input reset is unused. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":12:8:12:14|Input discard is unused. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":14:8:14:17|Input raw_enable is unused. -Running optimization stage 2 on fifo40_dc ....... -Running optimization stage 2 on CCU2C ....... -Running optimization stage 2 on FD1S3BX ....... -Running optimization stage 2 on FD1S3DX ....... -Running optimization stage 2 on FD1P3DX ....... -Running optimization stage 2 on FD1P3BX ....... -Running optimization stage 2 on PDPW16KD ....... -Running optimization stage 2 on ROM16X1A ....... -Running optimization stage 2 on XOR2 ....... -Running optimization stage 2 on OR2 ....... -Running optimization stage 2 on INV ....... -Running optimization stage 2 on AND2 ....... -Running optimization stage 2 on trb_adapter ....... -@W: CL138 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Removing register 'FEE_DATA_OUT' because it is only assigned 0 or its original value. -Running optimization stage 2 on hades_tdc_bundle ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[11] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 10 of drop_cmp_buf_coarse[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -Running optimization stage 2 on hades_tdc_channel_raw_out ....... -Running optimization stage 2 on trig_inv ....... -Running optimization stage 2 on hades_LVL1_raw_out ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Register bit window[8] is always 0. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Pruning register bit 8 of window[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -Running optimization stage 2 on output_decoder8 ....... -@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible. -Running optimization stage 2 on tdc4ddr_short ....... -Running optimization stage 2 on pll0 ....... -Running optimization stage 2 on EHXPLLL ....... -Running optimization stage 2 on VLO ....... -Running optimization stage 2 on VHI ....... - -For a summary of runtime and memory usage per design unit, please see file: -========================================================== -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.rt.csv - - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 88MB) - - -Process completed successfully. -# Wed Jun 16 09:19:14 2021 - -###########################################################] diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.log.db b/impl1/synwork/distcomp/distcomp0/distcomp0.log.db deleted file mode 100644 index 843fb07176699dd31e1b99bf16cdd8da08fcf988..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 36864 zcmeHQTWlNYbtXmKs2i==iXvaK<)`0J)7+M< zr#58$3YSr}&D#IUZ>jxYQ`PF;oX00s&3K~+TJH^gLAnoy{wMTbq5lm1Ec7p-F9u&9 z_>%!K_-DbH{=e>D?EAYux%cmTANBlE&qVk4y88p)4|I3^n*SI6C%(_yK5XW-3;pBf zn7MeaYxWi|imy&>$Q`ua)m{AJC zEr8X33r@*C^R7TeE{o|s+X*q+F3k7vuQ__>% zoN8<+die*O3^iwp3YXJ4UCHLQ6b`>Fe_S@yoHn^F>zb;q8=4tB-#2caE{=hDF&1f( zc`+u%B>`7~-(A_!K&_yDg1^sMB67K+kuMra2#`xFdICcY^LVVw`VP09(>Es}i~?Tz z&Jiz9TH=L|g~1D5`Dt5TjC3lJPV33SMou>zIC*v!j0`7TGm_6_!c%miAx(gfgv5t! zxu7>W5H|x8pgyitsps;>RAEPh*`!osXKL}P5att;;pwX@OZ*h{IF%`;6wR1YQu$~x z8(k;jd~BM=gxz@2mW8?Z9xg2`EI4qn`xP)T`lux);xQgP(A9n@?k_AlQ6Kk!dK9#! zIIa%V-_9V%GY)KB2(VD-$G!1t;6v7y41;b+Om89B9?e4Kka$=z3Ub!~?^ zxKvK3H`TpYle0?A*L`vtDja-J_S5mkc{Xx+%Sl6H(~>}Xi|pP}3^?Moq@Gr^heqGDyBzs;5CEeIzBeba~`Kq;S zpCY33EfE!jX(@^Y2Dez;foNV=3W~m^)Ch;XAe@lkLj)lq#hj!)OnAf#!f`1=630Qm zVTp&mAS_7OjtGJv#l(gQ4|zeDm!cvF^HMC*FyTQj2#2Le1cbv;XooF3d(o|BGv{i2OV8KexYDa$NEM z{wl$tiB9qVxG(DqfjFtesv%ayw+dn`{TZ^_x`Z=Y|m#sXS+WO z{J86L|DXCryuG=XIU7MjCTMP=FtH%SqRkY9kgY~RNR;BJqoLAHb&#S~EKrdiMLmH^ zd<*v%_~iVZ`!fskH!#Yngco|ty3-0`X!(V1#TM%3W7~A2n)ayg)1}&s>Xh~rsuNk z&CnT_QMQy!o&GhR$v$OSQMhp{+83EMB0Co*p{eLdg0G6r%j+PntXUFsM+#gBGl8eu zG1wxFHJe6Wh~2_4KcB)ZJNE#yY=KXBW#G$ohFv$VkF1LBw!Bl|!ewyG^U1c+7i{TY zZ5#ct9ep!!g&2^JaR3f@6MHV+Y%dq~y6C!0To69#xQub1E~af&G4}@Cz$@lQtx#>G20eh01}T}P2bHG z0XJQqxy@Cr2zvk}Z){wTT)|?9{nd3LV!;qg6R(pZzw3u#uLv<0fX>4#B;t}tRd!Th zv7G_n@T#?!%c=z&a7}H{NmnjUKt#fNvh7E53mB$J?k@H%>=$WeP1RIFZPKbBuszTf z1_7nri<~lwfQ_+trgEA_ASt|)HlG$He1@OoX3`%Q3kIiHFj4wo-Jb;u^b=Jp7_w$y zp3q-lyG?wU{&L-9Nqnt;0+aqabOW$!q@~?X7>PA(^>B*`yYtwfJ*AymjxfS1fsSdc zES+$vTror2H$svUYr3qhE8I08U4f@90wYT-SCz`x1~wLdqmK2#*I-y<+b}G5NY_K7 zD$sTrU=iERvh{9&OtB}`(h$O7$9(=(He35hkz%Y_Ju+AtoG&<{Dfiin=?by`E5(qLX(B=wb zgkdAQt{~=^Vbi|d3vBaQj_Ekq+K^j9@C;Urt7s2#u8lkDl$eK^B+Y1s&a($QcfA60 zJiYFkw|ba`2+Slr3;`%3w$^Cq>UvVuww$bR+GoCBO zX?nyHF5t+ArUxZY0iFbSDvUK8*%EGfX&EqFEYp-spe+TmSoE<-7@i255O{m6jFf-T zuz<58ER^KI3KX8?xD}iAJfABs<_FHXSi2UY>3q_KtIoz!=v^lC6A0~YUw2q&EVmIU zLf4~rbxaeEn>oIT&73HBxSQ*rgDsA^KX7wMAxMBqfH>M8wAlAzN(uXNE$#x+x#V*aAStfeaE723vlt7iN zn}g^|HgD{l0NIN-nCw?QlRW}6gzW6*AiJJiPZ@eLrM|>5FV1)?cYHcZa$7eCxwlV% z+yn2x<6Kl-Z#b)Sd;csipRtSDZhotuaqu~NZ-bW*WfZM|u$gmqaXMv(3vVA4%+B5u zW*x|z{dDePx-xjlV1^UJapvYx)(gqFi?EwaMF9j?*kO;-eJEV`JcBxw8i&CO)_&W1#FVsbeM9Ri{mO&m^ zg(DgKw7R=$6qZsyh*nsMbMtmhB`C*U$+fZ&^N3{Y*0-ReOHD?XqEHSl=^GYX0&0Sp zG0koco9(re5nFD5!~}0Hwmc+wBFdr+>*gT%Nr@~A51Hi6MV5yp53_Vag54Y>KM8SV z;enS@$E_v6x;aRF5~9k!`|vdvYCGpfeGR#d!$S>Eh)~A9l2Q4D!|v(nJunhTxpsOL zEFO7b@-6lb4`4R~Eko?PiQ7v#VC>(c_>UAi< zz9_Rh$+aDa_k88p6u^orCtm@}$EE;Q*g5$M`0&^iz=}#IUja+UrT|vZI{6A%JT?We zV%mvU!1X&&z&MLq-GTBBtpXG~Q2>h@nxsH3Qy9ac0 zVLhU7t2>aukU#(dxeY9bpAb8HEwFdO>H6{lFx!!vY0Yfo>kQJ!}S>X9xgO zMBjunWxd$S2R3R*Dbf&Ob_7>!j*O$;B6PN-y?903ZE@XJOh6hCI__<%;r6;P$74$OJ_qJQNO zmPSX>7{v4-NF`YbgkCaMWkh9i)AVi941hZZNS?<{d;v&>;qr28YXI#yS_0n;@Oaug zs7h&cgB0@JK+_5l;LT8zpc~-EOGja`*_e)AP3O;r2(a5AeBznrO|Z9Kn@v5s$(D( z12Nxz3}uAON3_>yx{-SfyHqSN2WqC3f^X95(tBKG-?wEiB)|eGp=Y;!)%SQMp!ols z|Ee!^e&lyYzB>GS!`#r1hF%@~gTb#2{AA$u;7@|D_y4&6wZ7l)yNEsjuk`$&=R)`I zbe{`+7MSSb@UdU6mzgt%G2Wx4Yp_@}FmQ2*sJ_U`<7@+>bX;qxp2|5%c92Y9xj(ik zDrXTY8K0(d{4Je5FPcM4Gg+rxnEq37o&wLNYN1A^^==jSH1KW+~L3Hu?SHc0JZAZpJ5wL@+X z1EM_x)E2ot4A^%;FuU8v0B^5>K-(B_n1)^LVt{v;hO9MlJ3JxpFb#ce(?HzT20m>Y z{g^HN=WU}Ov8BJ)Hu|vl}JfY2vcx<(_X2C z)K{%8FS2K{ad!18{IGULm*sWq59(G9NwQzivE57Gy7a<>yEE*ZFCJ4=X>eyXvqJ?6 z$9HQ@Iw<}>)m`+3`bN$SUmUtT_~!$EHSjR_&%s>(U-n1({;>B)y|48|@P^K-qk)bF zIvVgo1Lif;dW7eP6V%Eq>Z03C{g!V3BRntP(<&`&EJw+@7FD0;xf%y#ighZ}6|^){ z&?F(v$>>pK;K`t@7Xo+ns%>+lYBK~my@dyg;<1^V=6Ng(6Qws@rvVSQafuV^3m1n} zAj^ksVtN>%(Li0P;v!*8OzHC@UKD*eX04Tqhv+ zDZ7z&pXl7hvXDG$`&r+S4=4qy#=f+crvoNEqV!y@wJ|uTgMEWwFRtB?m;)v~tF-;x z*zeNbFvn?|W>RmJ1!UFTZ_~suUCL-0`!YDxU zcw!whB+J!VU4!b32r3?hibqSct{rhbwHFn?3S7ckjZa7&2sOV`OzdN>`B`hufx6Jk mS@0ops4XHhg#XD9xoD0sk&nB~DX{+9JUiXundB{$IsXr2v|~E} diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv b/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv deleted file mode 100644 index 3f23062..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.rt.csv +++ /dev/null @@ -1 +0,0 @@ -Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2 diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.srs b/impl1/synwork/distcomp/distcomp0/distcomp0.srs deleted file mode 100644 index 483b394d999304a210b3e7f8be312632c35d7f56..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 64552 zcmb??byU^g^0r8KcZeX3bax065(0vBcXxwyr*tFT96F@CySuyN(7Z?e*1gyJTW|3X zti_t=Gkf;T-ZRh4eiZ`q;^z;z+^0{UC@K5t#ii)H#tNv;j1xHv)R0Pl{PX#F-9~ox z<c5JiQy3?ocDJY1P+(E3SlG+NC3AGX*TG+)8lv`m2%C_b zjX*b7YJ`qG;M!Pmb23Olx68z>rhOlRHKdYBtx>g0pX*F^G8QmEWB1y$izat0+PEV} z0GHMmOqxj7PiCyqUx^dW`vwbBWg1_!+uSvnoCKdB^@U({(n>tmqr(|@yD^@tMGJat zf0e=8z-==21y(&h?eu(uz+i&0LZL~V#Ixl|H3O+3-<;{W4d0kJ30s2#i>O%5uY})n z-$s8k8S~EUe({cVo<-p^g{7oF?L_sS2s4$<@hDW^%a51Y_0=DUtwLbIv6f7`Q#>v^ z&2OtKY|B5rl;vj46JsuaYsu8ZEmA$`+{WDSM8?`*4@jaFoYqt zLi(zFiaZ(X)+X57MfACR;!7)QB_`#93-|&b*zSlZF^`a-i~kyW76Z)LSkQe-;xGmK zOl9T9@K-ChPNRw2oZ>{y@f5y0`=QEc#lyC;{Av{ZmDBkxWW)LsgIV?xr|7#j_Jm9L z&aL5AFP`3peu*h(x|bGn9Fnj3iZ3d7xD~!Whb~Ba$IrETH6@jO*4V}z)YGuhMxGXl zJK%a9E+-IWm&R?jKs}u(^%gZpc_Ic}ERWBMps0KAXyrR{iI$P$pv{$7DL82sEy$Ucs26&gF6azTa`mo(R}UTc zb9yyHjDn`qZR`L)_$;+nZ1dtb2RHQ8NxZb1h43z+kg^?1j9agX@6f3Vw%41#LLL?u zA`u`@!+^`s_w_Uu-Rikqr9Ciut*viw*xA@02L~*w%WP*~sD0zdUsbc;yWk(p9!})r z-s>*(MJj%Fb88~Kv{F|(*aDHiFg6$_ClzdR-jxGXCi zDZ$1^l!uH$OBXNQ4UWzZZEr_}TSvG}&SQ?CEO)8}E>4&V2*U?7l|=t*T@7Mw4vA|Y zmTGd`Pv13!zZoG|!}@azufA6DNMt0M5k+6<4E6bB+0rMe=c5A$oquB-aKCM;0Q3SQxld@?q z^*K#@*CD52@^6tXDzBb|)>?j^C{>eEG9AP?(5Lr&BJv|N=Cylq>X)m|A=12PqT22l zP%q7y_?xonRN@k1vKvu^U|aaUKR8E|?fZ*jV?@+odkPA%KuPhg}mlAmmi+R1iJ zpu&$kMKKhr5PL+kH7h}inETG>kfst9^BI+;kP7^A3;!U=U3SdvFql^V$!_u~^&_@e z$blFhOJ$<@0sr2$P{mP;T*(_@)`DJ&Xfz`!hniK$JlhO8Q-BryBl;*i%c@#1|pGQ8;F4 z8y93pE?~H*l)~b9c69;qADO(@@)$x!D6q7YdcVGam&8w?21cy>+u<%jBRHFh=-x1{6`l3ud%{P(Q2y15~;c)M)0Wwvt5!jJJAq&&WC-QF>0!oK^s*WBlDd zz>VEUZJrezWk>iCd8rIWE#?o^C#w+IWKcvkB}!_3>tsT-0yHBIiJ^#-O46%^I>AQ= z5;m$K07Q%rBF9&0cxP}9DhBrk{RwhkNlJxXx4MSq^ZlJx8rL^rm6?;Z54h*zDXCgo zJeA+WrJ|$tpLsXB-90?tZ-exGe)bJ#g!f^<@C5>Cf~~Cp5D0P_ajlinZF(G|Z6a15 z;0P95g`1m@q(25o2mfFY+bdfaS z?WVoGX;mcn5*y^T7u!ih$TzhdB*lhPJEs`@$qGeK^kognZyla$oGo1Z#pwy?zmb)V zP65liifb~you4DH^E&Hm=eyTFzuTm{1pA@m|778CKLZo2wRYUsoE?az?3f~|^8YY! z=4obQ#K>?&)=ApNUVm>xvXi>W%P_EH?LuMX_rz}*%U5bNtgwQ2U;r)2NIoV*5AI7GbDy8cA7nVWF@b( zwI!Y$KOn4NFBflDSeL=87SpI@Krq)7Y;k7u@^Q6Eq&B+Vw3{9EG_)y@8s+O`Px)|0 zP!Ds`jc@wn9W9{-1EDkD>Z(MmK!}su>qT4cSSH)IFq%29UyyLZ!EM~)*%ng2k5!1| z)fjwB2`$-SdP70t`HlUj&;FZ%-4vxF);UmkWjy>ax6A9_eGbzrKppQS_K!`nQwt#C z$dIcN{92yctvKBmtl3g?A=rL-Nag%#tFXUF$=}lTrlyX^ljr&2W@E$o%=YXo#e8if z*v;!Jk5Qu7XUoE+=|;MZJc#LolM9o|h&EM@hwJ8&^%=xcV6qg#iRrU|w2H)Dk0kwE z+eER%bmM`+LeEJwZi8D04J|so|Gsf!NZD;;3)D9m=sn53!$x!ar45Uk)D3*Fm8*)F zW@zj4s+GC1y~0-5RcGoe+*UGeo_!+Ai7hcGqXvj*9aaaubl zyonG%!m%n1$*8<60-HV%7uhXE8X#Tzk*qPtI~B43{Ck@q z@9Hkt1@s_GQX3Z8d&T%%nYWTLDVSp6a$s4;@50||LU==o5TOW7kdCIDPN(^Z9pS2I zsla$lw$cVTW$C|2*%gqGkQ?;#=8?ds^`Kn89Y~-c2B0{E!xt5e6<31A&##|`??Eio zrzF0hH@mpP`z&O{x>Yw6MTsWf>kia&KZ>GryVu+19KPq)yyoYdps!W=9O;1E&85=* z?Ih^@6kYW?WM~&)?Q%&6OyfqB;@CCw40Am+do?YZ@ftFOVQRm#tria-m@@4pP#`Jm zL266&w8!Z(x~|U>u#%RUo>DKEn8X?M1(j!#y{i@bNtrWz{M>-Y(Em+-)&iKXFz1~{mr4_b^TdcSG&sFvUEXlx_AJ^yIWudz$Ic#sCzsXR`80bn*?)+E zyx@$7q!j5VZR?=a{%PATn1x{dj(6W(t#+P(AyvnAdXJCPe5kmQUMU8_zJ$p2gJ+j^ z-c@ETdGfRvD-@-PfyKmzR+fD7BwE;qlU*cYM6a$Xxe>Q%mzI9$Ru7+lnr$W>4VR;g&tR=k3$@ z6MX_1Ll7`74fyJ3h})dP*f8`}^jAvEjP_PCiL;ND_fx~z^xMH9P?rxQY{H#iFgQ@L z1p=*ThDXk>Y#rd_sAc;RsNb=tSi7_&IjppqAf>Qn`l=A-orTkkcwlSYSp|%CRl5+e3esD?KUeiQs z9)eKaU36V%7DOJm&72a$f()Ewbf$E4|FJFx<}vUI=N#o<`s4(`{ajiQoIjje&VSP< zNCGbBclz`)i-S$z<@Ei;g50k6OA>@5`>B*4Wc@Z-65Q_;>phoHn^sf%cg2vWe(pGI zHIq036AQ9UD2v?(mWa#B?Q=>bCN?YEAo}a8ULbtGwIUPy2fM0ph4o)$>)%_B%*rSZ zHQ@qM2htC6EinqtA2&xDhAsYUbvod^to3)V5LFLAKv|`xw5*q$v7mudrjWmOHhO$C zD>g`(e>#uM%nw~;WNP6gCRre~O_AwZh`~2>;@6$nkz3qW2*`GbrN}zonbHye`zmDE z89`eFmnnz~a=CiA9F(M@$@!64(tM8P)~>fLvmG;Y^c0}ft&OUdxH3kvFA4rXKFthr z7dX5>0Q^ys21frIz(nNl0A#$z{uCGVcY%Y%l}>c2_y65a{1+FIk@5cr0@Y6hs{b7X zEBGJLJ6_)3KR#N{)c3MN3eG!)$;U=A)drqP^0By{C)g(xaZznO#GUv2(c2~^mMIm^ zrbIHf?hiBm4Z!qg^!g`)PHd1V)%^d{Ie$hkNU^`7_h00pCtRdKt^fjXffW3&Hju7| zO!S|2k@(Xe|ArW6?gO8ok|zHNLG=UTzZl^c1l4aKBz~*{(pj(`Bn+8YFa5hsAh!Nz zoc{fJ2}W4Ri9WABLEQQvNNKM`lq8yo-#7vl!&m_^``5o6;V%THu^*ej#0VIdhZ(0G zv7?5eo>8!>pzHmQV{{rpPL7h&v42ypV*6K6#mGsSZZM!U9Vq!qBOPb9w+X|JivXfC ze8_rRw@spP@CNM78M=;J%8FT*c#kZ0&LMQtmIEf!FkGTwA_7NHoreorrUTH!k{?EA zW`>Mo{5d5mwYg(lH@NQaGWI-xR&k-<+RhxNr)<&E_&qeBl?z*4YC^T_rLEiV=YhKIyyCrdhFBMzEaiw14 z-r!l>jneSo(UAogOR5Y?OI8wr``;}uFt3Ul!kXi7KPw%##)UDzSeoB|`9T6MH+e+u2(k)-@^UlEU6D>OCf5S-PWAyHN-cEvdYr1~F8R z9o8MymnTS@<=8zVV< zj;vZBW&Y9JP-3t|>YDi)hB}G zWpljpx0+85uqv!qZ2xf``6{YMBy*v-mwNg^x_>4LF30LagQ4P}`Zn$#7I5SsPgSvt zrcSJH`i}5;sI0}`*EgFc7Mo||_B@e!RT-kP%rR}JsX=q)yAow$vDapC9GPH!`eM&0 zoFVF?$;KAXE$q0Kz6N^M73$)UL7HKUhx?TovKeq7ARn@MNuV*Qrv(f3aIh!f6A51r z;4{gD_|Qq4ZiOq#*?uK*eyVdNw<^UHpnx}xnLXnV$898MpFyp93zpyuYOG+f1ntz?JZ@`qgthsAytTX zq^gS8wS5x8Ckcz#es!zHRcp3cYZE4}T@gYkUSgKyvnEtnkv1KmpE)A?)s{AN{M(7T zz@ekvt@6yqXwUvtfsk;zeyfDS*UL@*UAgm^a3`GWUI*xs(+EIk-Md>}!0~_JbqEdgV&|)aiN5KjAG>;Zsc;J$lG*b_ z9v595X;w!1vTN#%M@?;ABnJD`T{J0aJDOWrMx6g4-fc2=ch~!-ldNSRr$DMX)ectI zy1r)yZ*F&7+9O1t_2)~Rjy?CqfqkFrc{#5VUheNN*mtK5yPXWYk8~p#a5@(9Iy9t^ zar0EefpHwIlKJvy`%Fjfuj`F&;#Q@Hkz^TT1e=Z}sx+cFqXR|_n z*=vXmd}Z|k_1S@2N_o0E*I*!sY|oZSx#qkxCYMHd9u7k{0H?Phn3WHQgxDD*8a7Vn zKo#&vVKsQ=tP6cBYxurY-+|O|-@udPpdRhfY+6UA2QOExeT~+Rx0==4 zYXToAypSgZ-hlUw(s8e`?OY4}(x-(_KGZ!Y(E6csj+9(5<31C1xEb^8BJ$aBc`BXj zd8Tj&`_PyXXG}Q5<1`J=g5#?#g5sp^3)Kt+pe(y`&j3Nganx zhmx(AY(?*poV0eW#D${@3_4nO5AZMH^aA`un50cQyt!A1I0hl*2f04q;V0rg@%xmz zR-6hxBTuX43pqBhaMS^(&d!Q}<{65ju}VIPnL{p5>%%V8NC^eitHmh1^qEZO`$nG- z?Ufre9_%O~RB75mz~DRlA1rU}WXg0NM;-knRxs5bi)z%79i+J}+vYfJjUJc2M_9M8 z@CWbcPx1}!a67`@d7KKbAX6W$HLT8!7*r%soPK{{%UAq-F_zcDTPXuW`uKqSo2%hn zcoSSZ1BR&KJx-91E-^0MkX+p!8Pe?sXDVHvw)BVt0#HnCc%-XCD8$A)w_D%?B}vX7|8j*w=5 zC&uK$B5LHkAle)cEatpMd`%K6x`R#Fi^`N`{+_*GwT0iMm_mwF6ivf_ccuhua$ZYu z;jQUNrOJ@)?X>OE(N6ocEjP1-M2kS%ciLC)1jTRtn_^vaV`Ch=0?_rnQB+rHyySIA zvZ=~+U$8^n)`pMS!)2H8X35SadX35(C?uw8>)T!99OY~C5|@0@A1v1{^l7p`ZW>PA zUu?2}(CEqIdipq%V?#?Et{w;gLZI$m5eY_Jc6L^r7PxC64s}IE5>b*HrHykO=|R5e zw$P2or2_PglFvL_wsZx(4%Fqel$K@3VS|7+Az*= zlK}l349WhOxI=V8w`Y1~P;YeBalg_vJT-rCD(>w%6_u3BU@fcc@1)fjMZO4yRY4$Y zMh(HN(n-`-f|iILO`0yB^GY+DvnJ6P^WBWmfos(bko10$!ch#s#dAxjz2!m)9}7dS za?_H2;YR_*h>~I;;t`Kw5R^vG)OP-jU^iLhG}9vKJ!c+0?L&&Z3FbsG<6L|{$(nsw z!TZfOhe{-3-deeN$R*ru)yOzAui1vI-msV=;*i#w7d+PwH>MrC9Y>GEx>3SznqlbS zbebRMK4Mbl)HbzvT%%cB?|xy!JbdRXrQ!8`1V?7A0Vw}!pSYXc%z(K)7FUqS{oL9w zB8vc9h6JHYfZA)0(msP5+U_3zjy{=po{PB@FJC(VYIp&UgWqU1_uwQw6R(t@AHl1l zr_IbCBMc%0_uFhoCp6o=D?%X>ohnydF+-i_SHVQ^=gzbyLGudR`=|P^>Fd)uWacY+qO*V7m?|JC)U<}A(r~O&8zDwbWd$vE$OC5p|V%@%i}Z7 z@y)})#i9YQiz_r)TY>Ot-ml=W?6$2jhWbePrk}T8IQ3rJq@wy5NqV-$fI}@_7f>u; zGV{u_<~mKdMbJ00IMf4awM(PZ?Rk~A4W%?^&TWUvYJFW2(=iD-PZQJmSuV?a&XHV( zMv`wwf{q;tzaE@84y4iAq>j&2s{uDHm^BSM=~Sk)u}$o2v{sIEW$v#iK4j>6+lL9} zUzI~nSRmhHkt_9ViWbe=3YXMieQ10$+WF%q45cO;;ZX8>4dYo z%#OOt{E6zw@HNE=^7JtOl552$ndIY7Tq8*{(5GZ0cX1lVtoF(?llt+w*Y{KX>gsDx zF5RmG9+beMu6wzzqL|Qg$g=S!;W2Cai>?z-PyYJ^gS&{^Uu4$5@zn~TQ@Vo~Lv&}G zu}V0Pc$e6kO09mj?G@ddB4S)Pf4#aBWb^TYi=NwIXHgev1HwFe&*F)?WaBp;YbEH^ zQ!YbTk#7eD{1|UY>oaMy8PB#e4bt5fAy8^c8$My0iK6f{GQElBig|Gei)?G-Rponk zZ>q;Sj)>M?6F^^z0H?+QZwkoS1Xi^}i{=kmdPNq(IJ|m4v7eGc>p@38C z-(<}qpd=XsgbULL^PhP9+1dEPuz-%)u}XV+aIM4$FItxj zXNTpCDABM5qiFpjkzuM=<#r>Vg->iILQf%5;9su#`e7F-p`0hqK-gS$1i2s#ARwg%t6ICd@%6z)3wr>y#pW+2%sMC zJugQ%{}iNjU480E*FRqV+gnL!x+6z#=vR*}MM==~0@UD`Y0(L?J$;?dpn#*?43T|h zqMeiAb%TM@>HkHYpj`U?L`g!Yry}+8;Cj?oG0FL2d&tNjy(4WMZwx|va&9Hi0d8#gcqmg-{z1h)Rg3J)+TLYy3(d zB?WjzB=1Wi!6?ciB&HQ<4tD;9)sp`>Jpg&N?Y+Zt2T|61S|Mf0Az{?w2wd@&Vn8&( z=M_7a)VpKcJ-PWW!uGQg(@|*#Qh0|W)1NmM{mm+1%__G{=b zLj-q3vXtI?vlEm9uuT&E=DLZx2We5|?Ml`>W?`7A>i(`SD;7fJ{G|%2sj&`u)Orur z`K$?P++aTGds0WlJ#{{)AuTa*6o$J!upIQG>5ZoTmiWL+XNrUIJaY1C(-CaCosw$+ z$J6@vDFDrTQqBzB(uL0qxcGFKaN)X$c8csZC|nX~lp?p6x1&>Eb_zJ%?i5XhKj6+m zWW39-Jtvq)YW={tyK>8?7&!kxNVU43%m3=4tAmyf9qBAa7~{($uG=(U#8k|Cv0NaR z%mAIGk440!cSWifQN-s@#9kQkwD!w9)v`3pA09FbS~8>wtAa*MIuma=8riPyBT8V) zUgh!g!wR^1}&bZA2FsfQpLPko%98fw5gm>+1#*R*k%SaLblzvOLT3nx2v zp5S2i9SB=X=0^lEx{sy&-`yn*9mjZ{oCytC@63<)->0oismMP2Hk$M;6=QjHs#gSh zmQLJ$w>s#9Iu|L9Gi-{3A8nRt1>0QRapg00a?2X{dXitXIIwzGveC2A4Xg|%o0zTC zr@7|1Ja*>kbKwcPs$4~lb`2XER&2?GuBr-9I$~{Mh9A1c)3I|q6M_{yzOLF57Hq2~ zKH-pb8%C+277%DGf0L8A1U&Rv_mfTGxylTv2TtG5Y)`E=)R;Q+u~`r;2vLUdF{4+! zWKNi@O};Znd<}=Sf+!@cL?HGj6Zy-^sc zdM}m6H^Q-W2Ux5p+o{J+cmm> zXt9(Jtad3cANg1jss3_$j6?~%Q*^&xPDGeCe~3{rt81UQXzX)6w23kuqpzd^<1{$6 zw2?MDqETN`z8x!eBx?B(6su`fC}uuqC8RNinNFD@d{*}Da)0Zo_v;WNQxWLq)2iUg zdV1>cp6Bwyxg;gi4Kdu9qP+$O*c#A)mWx+=^|Jk_bW>fe@X8X;V@G<%ck-gE_2*r! zHTU6ke!CMDudnd6*+64xnN8z0#s{6lC|mpY=j^%quy!h%O5!2Xhi;D7R4__(xDHm* zsYdry93R{~55|{p`D~u;chd2NzR>d@V5yyS`nro*I6juVXn2?;z+hgq39>HrGSNT3 zJ1E1Z^k}}P$ofWr5NWoyrB>M?9!6d`@j}!fn|SkA+x}Pf04vp3!31Cu2S_*|Q7amcBt72bznN9(iysmikvw+Y($ zmrCysMAm^Hh>Vp?w(#dbTRKI$ez@w2cLw*$w$2#PxcGJTo!Iv-oA;1g95lDLjhHl4 z+^V)<|Dw~-PlUco2`VI}Q-)q->YD4`oqumovcbqvE1vh({!4?hoC$WS_s8c!-OUTc zbC}apTfmnwk7+fcF2Qan3%aweW};gULC#?bFrsD;EIOip_RD@I8n9C0Y=D>FFp4rZ z?bx@<84S^VNYEvViZd8$8Ma6a!N1a?(@650(nYKj>w>e#-{@#YxV2;u7?MSPkFNA$ z#YO>TLVsl~uu_a;mE#kY5&*byNo#o|cv~cfKwzcS84R2)ynMJL+fN05w^c%MJAYNs zzcL^YmN;Ns67U0y`K;>n)ZX?w6nIqyb8dA}eR>(@So1ra^Q+79K*tLRCfefqFaM^R zc+I$E4G4}2w)zw(dks%r^I~GU3rkJVgQ%OX3+jx>qU)Bk*<%<>P=d&#|EX&l>(2zT zSg9@epbkyFwq+f4#Sa^o)JR*;&;JXH$t_c~FzdA<3O<5^RjW!n zRfQ`1`3$P#%WxpB9FyQ-!OQLvj7_)?aiSuOcQ%GAC%t)Wa+*vj;(W54I9|Ikw7}do zjdou$vu5s`TdKQp-+_DAh#u@9z2ZUST#57ewKbkAMy->82wYO;`=jgg_FevueP~Q$ z5qz&g+dIqUNH7CdQY--<=htiUFsw)gQ{So06pP@PeC$ccjPnXZMiA+-?FIFST9KgQ zX9l02!b>3ElqqF_F+Lv?lOj?-Y0u7eQy9#Fo!WFKaB`@#0SE*UDP$oX3Y4;Y^N3C} zLaE;*z8k~lq&-1KNsX8q+iEfCiBlY28D2Trpbk`ciEZG`Ib2ORZO*u~aphVRRYTZi z6}|6~jw;g7>M~Gle8?mZ(XbG%#vW#7$3s!Nx9DU9BR}WTw0*hvd8mb*@B~VRIlJ1+q za3xJu_ue)~gQDhFm$MMBj)99f%u)uo=3C$K}%L z>2@o;;O}P|_IFUVC~rowyVcgyg)a+u7qw+{#S?f(8@Hxm3d;5?bT1saB{hu2dwqK5 z7%qM9r?2sBd#GGXin@%uJ8=k*`RUU?C!0%$wc1L79Sai#e7n!Ve(PS%_WFdpdwXX` zf3$3Qsm{8#r9-LwR)a@-Mbo=kiv{${;>@7-WZ3_LY1>kM66&ZTv}<>2sq8L=-?V2G z{2;q+Io=6E=YUJ&VRXAwFnYBIcE~+ohKsKfI^OKKg0ON`b7y-rr_$@_yga`K+%bRAvknX6thwJahGlG|Ez+?mfT{o>iZ`!xW*z%N-AH z{4SB&c8)3=t!FO|5%7-gPTQK2Q=2CMOPqnk{UUdIP#ps1G!gVkp zyx6(JwGIdebEUjSi$vWges9!kBF2P)cAD`lY~1a@cWj}PDz^x%>gtKRuFJ{4ZcpA5 zo5T;H#2~ffogr>WF|wyatcxk6KwweX5ncBWL3d)z9id^A;PXG(7Eq?d#wgwg z9;JxaEJ!3cP1O7!S00g|M6;U2v`0UYAazRf*|6ZSIQid`HNKIIrkxB3emfUsl=1it zY78m8TJ%tm8?TwR5H%2`Gpy*2Rtuh+t>@`-tX_Jd$fT!j@}y*%Gt-P+n@mR`d~#Z1 zR>8!xm>;PZzX^2OsJy;fyvIgpzwK1e$_!>cmhMJr3r$iLnF_(yly*nE~)FClqh$n1d5h5sQntqndN4-F#mrMN%hHwZr~M-`nE4E^F5$IsT-QJ7kj7ayVT;o{J?2xVt7MBOoacdNv{JZJ?^_mMKI-s2z6 z2FnUy0`sOtF^)YXP$(wYG?P6%EH+y;9NPLwpl7zajiz~c5Osnbvr(Ll5CdS7{iD?l z(FTC~LW}`9s?0AOPY&x6G9t2zMn}bCgw-kTE%5w`i-J7p12QA$x3+iT>|)?1AD5)# z)>I*b{gSdOM+Ec8dOR{qx!skQCo(b%UlvJ?^8ZRof3l4~R1#+dHFZFPK!E@IB>e{p z+b@)w|HDN6SE3C9U}XLYz*yN|3Bz_&p5?%KTprsQz8Z z{0Rpd31R~k4UEiy@e6qB>p>8l7}a1P`q_%AK1bK2_=cB=u!zlRMF zI{)G_Z(hJo3fiIK2@&AE8RZmiRQ|zbx^~!)Yg{BAq}oV77ifIri$e{RQlPV7>c#qi zMLYho(L%t;ElPHNwQB8hM6+ zB?=5>h|~~vvgPU5E0)#Woo|K*mk4`9jjQ>jQ@K9b2ClUlOCJSHr`&OtVI(-_REkN) zp+;S^ZfS$}*cQVpNkrpjc8LOxZfAGtP^n4fV9Y1O%?V`BmGlDR0DFAsWC+Edu1hgP zvZa{?Q?7;yRt2c;+GNx-H-hhX88vW;T2?V$QwoD{hyX zxS*L6HE>@@*X|x8%C)a#fq6b}EX}yqr1aHlWL<%sXz#WZDb=T5N0}rJj2?A>&EHX2 zvGubG)6DM58#XPb*Nv3^F$^K;4*EiYwoIvq5R9(LwiFluV9IVxDRu46Jr}JVMvg_* zK57+%gS3w(Pc3I>!)tMRF64~`@%Mu37FCp?$*`mj0w(}S%p4-*hv0a&8Yf68VK|b} zz`(@5b5z%9ugC&vg80t_*B?=hL*CCSN!vubADu-WiO=t%hRE-Bx(mBqw#Xy~BBJ9R zOw8~hGw#Jly9B6pQ$ejIe5TvFwHYnHN)zwL$F@Gm*C;nUl*2ZSeZW?u9L8) ztVh10v;=6^MOc0+p$8WegF;8v-e)9fJ=6oHuDq!K1exLjcAa`<%G&-`$C!2fvygns z7-ykaB5cA%o3>9_lJ4Nm8Nep&3ObCqodrCPy=C#ubRRC2yDxbrTj^#ow3%cd~D5p9|RYO+l|@o@tD7IsS&L3s^@ z+RM%@u*y}iO8khIuTYJh)uGt<65no$MLaz&!OCPjp;@puV!y$fo-+mb8pfx#!5o$X z1#OFoq`#NCqze-cn_u1NxFgiEr`&yz<(_yk7M>AE!fRv}XlDzc!P+Q)AZ_`eXGi-f z-mUaZ`@nN4atmipdC-s?lUL-?DIfl*AdHn2U}HOWVNNJ*pIBwL+VQ~^`(Qsm^^S~@ z2(2qM>T{-y(X`_VH=y}qXT7#&m?P~=!Dc2OtIC5NKc163GEQCflheJ~r0*Hy^VfMA z0&>z76PrqIEq@o6jlFD1NuESI$Q`34op|MY$wyPyce?yT_0L^Rs-C=8-}r$o=v##J zmihaTP9f4G@(;o*ADm{@Vc)p+nJd=P-!jj&HyMpnBkP;2qM5EC7y??ixS!DDt-q~R z_%XlP$(#+ZTGjB1>%pKxr|=Au4uJCLDJLJ!>p2e`Lo>(uZU(~eRMz2?CqTU6eYW0TV?;M)V$a) zbP248`jzYAe8?4MIy~|Yr&=BV7I6}?m|USQb}|u5Q&$8$^eFilb(qviaLCby^|aYh z@!W9P&f>be2Ira?6rz0-f|C?M+JV~uTZrK_@L_Sgsyt%l^s>x7;U0*4R$SY2eN}Ay z>fCco(6BNg#P?0|1|JVR{z=5JL$bp@Yf7evsVUm&Lk;)f{bb|%#RRU-b-wsihIr%} zABXlWPYA_u(;)R-@K@o2*r-=Fu+)wCU(_q54C<>`ln>;P-bF4hNDLhrkerQQx( zTl2M?;)!x2e}2Ud@184(zjNeio!_nDC~MSweNE6Ef4Zfy*Rncd9^nmMP;5+KE7 zE&+CN`Fzur$VQbT5_!pG;&kFY57G3di*21~Diji1KAH;aeG_sx6p5x}g%dzIvM#WTX(+^sgEaR$$K4f#jq3LasSd^Km`ZP(9#{UEOpb~DKakI3V*kI%=P`yq$mgFKX>UJ$ zh3`-Hw_mWE+N1fbi@M809Ll0gQ0+HQO}ZqYh^BA$;x_tHDNp3nAIqv})=g*)H`yUMX&t!K@OnSJYf1pC5298OR-oXKh z=GyVv-k~yZ1k}2h095tE!GQf`U~=X_Sa`wapAx=6mCt^98a{SS0D z&}2I^0E8~VNcB(jzu4=)(Yp-sA)IdNKi~WYU0c5Aua^5S5_^o{$1qtx$P#c&;=un0 z5*wj66YdKG3e@VcZkF6yCf4Kki{XM>F=u=;sp>l_1Zaac-<hD-qpW7P2xAMzhX1nCTeH!0jSi)dc8Str#r#gnomC`l9ch5uf zH9pW}Yd>j{v7j4ZfetM+*V`C3hINJcBX0iOLAJ_%=E@&CIB^j)f@J$=c`}G}4mGHcFjB8lAeh2uF5zrvUU&Z2Ir3!~VS|;HeIw3N>azUm#1FH`JpXY#O%$S!mjAfA8 zZ4j`P1&9hEsdeOE**-8nxQ7t95B=w)q zPe3ss#s*tG4qyEPO7aY}X!wiM(@!;4_DFCSec?dJ^ORWiw-3L0%M!U&A5&ZpQVMj> z{A0+3gELk@gn>@Tv{x>`jo3$8g>v^f(=qW)mSY>c9U^!?YA{ozw3eEC4CRN6uYxnX zIHpYBw;&qq`5!(x)5H5=8ky*r{#q(e-yfU4WN2qYDaR1QM(16k#~1@bO?`*4|13zc zR+Frhi0YzA|KJouSP@OrNu^cvK3u4aD&U<;W+vhKvlN(3)$^-S5*b2XrUur%%CR9E zx^De(g@jzK2GAp@KL=Sr5g=aMFH!p=0{SZd5Bn~E1kosH2nG~Hpwbo;L_dy>AYgg9 zm^Iap$;@|as)ouokhjh_jTrcyu639@J2!Wnt`JnW4G=eApE?_@sFeR0*ZDIfnL*JG z8a%25ZOS!hQ!2%%9cX^ecEZEij(v1MlE1dK9-cmfr3tUKVipgkA7=zWgxvln-u-U% zdK#56D6Iebgj>ijIuOW1s?3C=olgm%`VP%n5gPDB}h~vp%CnTu#t3Vz8 zB0zy6+ve~4r&BsK0=ok`LR+nLzH z&-TWaBe7z~$bqIH*yjDH=)swVh2JGw_l{pFP9!=76*V< z2r}UKK*i`qUj*>Nk%msr0jU~vbPDOHx?0^r;^JU8V)QgR-)!A)Q*uJLP5n!w@)ypJ zaV=Ix(7U=ZkWk2c=Hu_y-00aSl9YV`(x*|2qKBrqNc z7j7z&Qc^%vPfQkO^(dseNO7*B1guDZZ+9savOPFSHqSLsGj*8Mo z-4blvQ)~-uG?{PlCcboM=frgSR#`Jk#HCv9do&ar%N2T)2^pAuUz)m|E|6Ewm$bnc z{OWg;7Mh7RcjG()KfGz7Fn3gZT>EvuKZFu(`zU;)$SsE@&{eLhD#G|vPb|SorKR78 z#PuioyNh_2SMZnysRZ~JvEQA+HxF>qXdBi3PPq|+kx)&P` zlJK|mAnZDlw2_>wwO#KKUh;Ui>^unf+#hh06Ltug5q(8M!0*}oaEB?!>au>ZL1ME= znsO^{OIEd%2>f_Hj=U#u=4`H;82i*JJU`CCG&6=x?>%=A9B_B*cp|LF={kaGxW2{f zX_%8>pe^=^AyVDUfu7*I5O-?sL#03%KBvfp_}! z&7F+9+$$nzkWXHNA-&)wRf`@AIX1RdY*ZuBQX5M43rl^(K&Dz}wR#RQ`RRyw> z$7R4ZoU5mDxbTUt8*2L64kgs(5vLwbPbT6zrRSbeX4(Qrk36JZa38_*YjXQ!QF_0T zI-3zeo*~=$maY&DM|+D)zTknzVI}+KQwAcV1uuU2!b=w;Rcq;sH?^iTnwxigpp)fM z4ceMuqQ+k#HWIsn!;tifb0~Y6nGjTljzo+%HbIqP9Gg@6CGG9pcPQ-I(+Dc{@Sz(j zh7Q=y(t7rx7XL_;jeRxcgAD8V6lJ%O^pMkyFp5{V#10Gw$Ex>pO9 zq~oTZv`hECuQ_P#60C{3NSmLZXeD0<&$M13fQWK-jJn;+Xed@7M1+RpBt|Y*bl%TR zXf5>=K|5f+7>FJL&R&(iAZO%#QL0v8lzS!jvI}$nCWElt(7R@LHnYTt;`qwp@{PMY z;yw;Gm|3BCm}xe)aax{nB|$pgTv*P!Nc-yuiWPyT$#Ma;39h&*!B>?F2?Yzc;jS=h zp-o_%f>PCmG^$%8Ee*c9ze9WZ8<57t`Np=A%PjRhZc1@TK?V@WeR)5$8e z&u{EvoZ+J%>yM4J5_l+$eCzAg&GF3XIXg7WH(W-Zq&ct9(YJ3=X1z8X^K) zFw7ajUQp!l>0^-R+{oS1Vy{dKJ+I}3k%b7iol)-WW#Q3#82x?(PL$om7}?FVy+5Y+ ze7Dwx_KUw;rK;5&TYGTgfwuiWNQl>b^;8PVe^@i6bya(%JaqD7`7tlYp|VkS>dEq$ zP>hSS_xF{nkBh^Xv_ksYLs{<)-*lWg}YL{m>JKr*uKqTj-ZicOp;=K z?7Bar(3Y9i#ksf_cUO<3xZgC3ZiL7Ld7CeUO7~r$rE^i4mA%b0!Gx*$O_6PRfo4nf)m|?pXQ2GdOJaHU88#^w)BWzjyv7M! zM&O*h1tR6wD6EBs8=9r}5(Fwf*OR?Hy`$qHh$>1DSFd2sZ-Bw5EM4SV=7aC&k|dzr z7u~pklfs-ZAWgAuNlqN5(_n?%6iMH1Po6ePA2Q{cx;E{eR=nIgS5D^muwuu&m0O(r zoOV6Qf)*o0`0i_|v4!Y*4fKlkwaz@he&fQ*G_9H&-!)7%d=GBmp9j)qPu*zA_-fcI zlGvo?8_?z!zNO@Dzom$(G?%_n_QE$tJftAOmGH%V<5QJ;+zf5&&%?hk;3arhZpR&S z89BA5zZbu=hN5;IWw&&X)%sNGZ3U}n8fI+R!x!G^-LJG*L{(wP6;{d{N}Sxmq8J%vp+L zxG;v+;;Y3c9AD{KNPp_LY#Ge8rn1s|b5H)Pv-v@?$NIeh#M@r6raAV#?KhV)>m~)l zTPNn9^&N|mt`=#54&?=+D)uT!u0*+KyvZP zm+c;_J4`BA?3oj&K$Vkw!Rw*laKHx(;=603Mv(~uh%J{P|9H_%ISPSUKO3C5$iuxUnRw*KB}OJI657dd=B}Dsik7%p;Tmj zDrn;`ctcpZIeV@(Y;9VRap1+GU_JdB9w*nIVR8%6do871vtKq_=62hf3rpq` zraH=-A9C+KW7dhC6RJur;nTw z?{Iz_(XcrEs$?aeBt!(Qz}+ zn##2gv9>w}-U#B|-bqjQR0Uh^er=r7yT5pHEGg86iq!aQxn?pn6Q3Y75wWHr{Jyry z{wp;vrbIG6Cxp{)DQjm%Jmj)>&9QTqrqHDx>OQtIeC_ak<@v_poq0OsulTkzRBtg^ zR<7V=t)7bP(w7t*Y|B7;L}cdN_sU!BY4}Qxs8zt>6Bc9l)6W_1KFEBhU zfC!g1e%y>#qxUgd9yQCUhjbO$3YHzSI(9|i>wu`4YxZnxu$bcff}z}e6ZA!; zMvKntCM~CGg1t;5>KMbxJQJga7{Mc2EeqBN#ccZzvRB8KUDD|2HJ0x5RbSn4L8pCG zM(u{w$gy~Lw#c^do~4szy73fN#Jp7vU(DGDU#u~Q@Cq@;Ria(8WwM6299@5>L|4pv zqg-yhaSZzE?dlrV%-;*5t{i;7I^Q%t<6M*HGT>O|#wVe|E$z)6qZb^M8dc_=`hg)x zq*$FTcq-<}2Wv~a9~^kG@svbMO4{-&vKcRW=C!g+dpqdkJ2O`%G*&e<^|HP!m9lP= zxe%+Y1Tfm~S6P8oTx;g01U2|cQ(Ph^rwbH!B<}G^m8NrMqGa)wOfIw8@74_SQ*gRF zn#V-squ(U0DRdbC-#0-RQ)qWuy3bOY{nDK=qVVo>F0QT4Gc@;+J>0c`(Vfh5re-c5 z7FI&9NeU)@bAvktEGwOv2xW;0b6Xh%2=NqshacBmo6cj{MQ6GwqK$c`by;arjL(iK z@*vS4O*)#ai$y$fouWp&SGj)F z(w(b}v+@TB`Xe0~438IYk}V&E+~DRbH?rI{C6=#Xoy|7SdFy7>wlAU04(XSZ6FJtF zi!MB6&R*Xtj($#XY@j_hHryGGeJf{-Af?LJVqFzntFacJ9oo#iw94JLk8tQ%yLOV5 zVrdf<#ll?(>NFYrzQaEl@ixlV6O{Zc`I@fnBYPZG2K!1;Q z^!fh663adj9$vz1y~(QKcH!YMhHXNYF{3u4HOnMJ!op1K1SzhqYyyi~f>%yp-1doN zP5nkv8B)2xdDTGb+|jxnaTn?)(GbMr?8ujRJ*P&i%H!pP2W%DgpPZ4WT@0r6^f#|h zm7U$;R|9z?qL^foS$&tS(VD6b!~5*0X|?-sbKwi9JlYR>6X>Xlabman*B@Eq zE>8;IqN=RjaZH`xm)|7@b*BS9v&y^b%bqw*pz>?#}NEbM*|jMkVgm93n1y{diQv9OE?*h$xSwi#8f9^ zzUprxBytMkRJSG*3|uR-inC_d1v{+E7REbROmsASPp#Un|UGL`B-n44J zjd};s`j%Qls=!3ZrcJGwWPAOC_c`nA?O!GC);y4UjxG`%^j^A$+^0o%BLrnIyZ2gv z0TJ12`FZKI<2~0&EVJd)3ZCPPMG`rk#5+gS_di-hj$b$gCIvv>TLO6Rt07O6ol*IJ zpn7l4`FVQ(AjtFdK`ooxRQln^k2;6C>HWjc+tY`@Gj9`hu53`r?^5Q`4}Nj{rLeEJ zv;Li~3wu5b)GrcZ#UMGrFWrD6OX1F z&?j6R1Oqb6QRIs^HcB?AFfTK3#-Cb45}vri6-FKAe|kz?`dd-Fkouty9+UuHtq;)X zQJ{jPj7=BAh8#+p1ExP%P7IU_XB=)pm0Ok;G5P7suL+W1h4EOTq^%9mbPL|nIqYp> zw9#Vvm*hI^{rIoc59qoG?N8W`fAjaZ$J*LKz=PWQ+Vk7CkWshocV!(g3y`;D_jav{ z9EvaP8DOHp9;E(zWCeUw4^9@p*__}j!>>a`KTIb1IYn|?w>Mz=5tBIC9*;StlOIy$ zw?aR5_alW>Z++S>BBFp^2hH={jA>+_*i~1a^_;n}^&Ga>&(I!#@LtOeoDz{KBh?lJ zF$aa1(Xj?y;Rs~3YivpPLe3nvVtp~T?HCJ=0z1Y>gpp*Rv_wzeHdWSHr#Fg5Sk@2C zVGvQFKxuLF4jC|0ok?1F&VO!Xr8>`^jorV-^8vS80U{xs=8JTrF~8P8cK+=l$IeVi zgzAf{gqV(;YcgrEn@<|AY_ku?U@0qQTegmV@AcifKa#V>8NsO62b)!&vwP&}?d9@>&zaCg&m%R%(UB%C zYo<-qRD>CsTQ=QGoC;m8W%y}dswpv3*HezNSkLz}kKNhk36`&feweU)K`w7q?ii;Y zCsDnikcwNmqHsGKAvM@&RJfp-OPd$Nee{``j1KW?fiz@i(EW&;ZMwMh2OH)CB%AcB zPp97HY#q0K?(3QG(oJ-x<+`4v7P5urQ&l^yv8_MRkI2Yr`Fy2jW2>TUO8L-+C@#3b z`;Y_+g1^nGJV?jO(`mr-%^rQmmpcD82DtXIFiof%65;gNHeRE&2pU?7ccT*8{#>Bo zq0N3K;c@eJh=KiKO17eM0wYe z9b^9z*!AGW;P&-F)ziaFS0Iqj^+v}`2O+u z^HbTKX?n?2)8`1i0rBJN%eNgK#NMJuT&)~5T#q?g{b+QR8Obr1&S%I$u8@z5KG!jCDEGGsao%${ihP$@D&(fiue(_2DI@^m*WRB+zi>1a(6kOrb`(0suBqKNv zWp4N3{%FEGk8aCURF=P{pv5QNgG$G+7yMrDBYVqZZsO@|JUZ~&2GN-mvLiMy{eahd zf0Q2%@^<)H9Jh~9!!i%QFmn2g_pK2By_)73H{TB5WjAMsaVC4nyj?j%{+dCygkNH< z9;2lG!Zh+Hb|<2eEIbYGI(EJmJ}MPXx+dqls3KNE3_g4IWaU|nL&961NwC!PNVRHd zZHp{F2QaX-es?a!i#OMFWoS6A)u+G`jUEb6pKRs1;kS5t+U_jB5cggd)o?6zX8wGV z^`BZ+Kng*d1XfW#s#I$Mr6d;Wcgo9ktmNe>|0zZJubRb52nLVoB&JkbbwFcNQxD&g zJZi*L9r2j_U9~y~GC;_Q=lLA+{7fcbn)%n9-8ampUE+=b>2EMZolneqev2Rw}z) znoNca<}Y6=x$2Z;v{dm;v^sfjm7!I^Te1Q%(iB=U&U6yYR`!08Rk%<0KydTGgSu+1YRx_-EMv$zbKt@p~ zR_pNH<2kI)#rf7R1Kx~ozQos#dx(_tDek(U8nv((^suM&Xc3K=tL1Sn{MyX6tHOdc`!zgnVER17gw%50#dZjjuS4n@`13243vlv zW6c9Pk~!~x8fMVw3Ijn3fSLj`uK%U9d1MN_jbJX~n4Q7e4LSDEgVdw#Fgx1%%@Rlkc zp*lv0B1<7Dm<`F1P2JK>?`UonB;R!lO=1C!o%=CX3 zD75JEpb}}hKeC!&NSVBR@t$8u2vs2qWCkvBP~j4?IA4757m^jQ$qL^l%O#tv1^J-g zZwsa@WC4GNYqLxKr_JAAjFWf0Y^9H{5ujub1AcxE z(ha*4pa;97qk|d9eIJvkQ-b%cIMI%_!>Rk1hVJhoB9;h?3$qBJN-FE>%_l`rz5#WG z=%eC(8bcLXl%faIB%|N0zqd=Ba59=1<#2Rn>?smVv+E#%+T+Nt;$PiFHkY_Q;wwf= zB;42cbuK|8MS7_lULIv-l$2=(AC3>CGY7xWznmZpoj~+)A>|-it0LB;ULk@<*pgL; zcg;qQw{t$TNn4bZP`sEqSU489amC%vedYT#UV828V&PYE1)XJWRx!kRM!Jb1Pm%Y` zVt0uf&BBD}-Azu6u0Avv-$ZTlGjgzgl%RKu&O!RxyjKDNZzcQqAx@J;sL&#Vv`&M8 zZY+Ov8R%UM({qtXebTF)Y+{Yp$EzbqAxzwD-gc)As+tM@&#AloQ-+x9eoPsuE+uyy zQnh%QYKm*krtVYLx?oL>lM=rGKiEJXjv&^+My`vzwP#re<;g3KOz?A>Kj)X zfwfyGFRN)}2x*eCw{2o9Kk*E(zg{J$vv&)z8@*jV78{mHgM6+gAmDGPX%6FTku!&;rmA-vGRI=}|x5~9^T6^Qk{x`n@ z46V8kjMyBFfzdd0VI(Y5@dn|-uT*^C;z7( z|E-h%(=X}f$^YT!K17^9t9D~5tc;e$^|ty5l$yTdMt`}wl5UiK^Y z>#OZN?W;qY2l5AJ6stg*xa@S-@+1cw)q(09@}U8 zSCMK_010GQfq<$=VALWIiZ}z7Bqk6Mr^SmeRVYPO1j*z{EB_JJplCp*0TR2!!Q#ce zXizi?44wBE^q-;aC%U%ok0#vF2SS+E1@t1-+K+KomrL-62&fa5)7Jpo&zc z;P3R+UsQoklb}KaKotlw6AECyA70fBxK!yWfKmm522cgSbpQ@$oo<8caMrx8OH={& z7l5vUNB~p;&`_eWPQxb}Yu;s|^%X#=0s%6{p|+t!16&4|Xn@Q9OEd|fm!YA{u}Or~(1xbxf$gU~dkeXsmgci8lDlYcMpFXh6IFV*3)&7=L>WMinU0 z0H4E+Xn@auO%{I-?w?+hC;_2~vtq%&tiU$)o87;P^1)&ubW#ipDGUr)sOZcknCO@E zeikfw)WXY=3^<(LRUj_Y3T$rl(*M;aAI2q{KuRmr&oV$VFIpSpUy9TTi%Up}-|d8bss8F)9Jt7zHld;CZ%97w%Sh>8?SygZuSjgT z$P1ewv^LORZGNM^jFbTuInuC*L50qYg@sDTgthy>eq4Z^K48qrU;+^Xz(MG-DADJ8 zbNBvR;~k_ziC!}J>omYG_V!5>LnDTaG!QWWG?)>Jh7)gK=*#g22sA*%km&*<27qRT zq2a_E82VDY0rn`N5km%GG88St0<{e%-oVh8;|+j@dV3Iv7*I3=41IabU!X6=8|hzO zgP|d?H-{5%VCYNnhVi%8Kv1u-!feBdHy7>xuWbMg^BNN9bsbt~LC0&<`m+4X^N@~@ zsP$O|m**kCsuuQfVX#J*7qu=_7QM6{c0iYx&%G348G)@(=qv=faoKCDcm;0tP!Y20 zmxn|jBkZ%nDgguykoDh@mxly^Y=hcF0}gbw+58ph4QEJz3lOmR$;qYpQKzK`QKv6$ zflKp?qYh60c@PUWLj(u~@CgiUByjTpG9B#3gUj>FiyIIAJHPB}FK7d1#b9VdQ5`}3 zjOaF~^YB=qXoFgEi4{;Z&{(iU2@K7|07b)N1r&YhDf4<-yx20W9>-{Ii$+bKV1NiNj_9-9WMj>Kel(>@?i z1=a%K2~ac^GZYPHeE~yX`YJ=wKtzIc7XYghYFH%hpM@WZ`wK5cVn%?nQ2!$r!O+l1 z+&>FH689Hgip1>z8an$DEpCJP9)^Y=i2+{xciwohuX6GIkz|3OLp`_mzkYuJ6(4wS zEU6M8tN=JD^Jd}9`z}2G-&oiO9Ekzm8>_Pb#u;cF27GpTz6(QN9&rE~@Ho~0ba?{s z1!f!Gh=ca_4x3u0tXF?aF=XD(LkGlo3#Lc+rc7SFI;~s+VmD)^0$Oo2{cB@utNQ92ZBbp-dTA5 zhN3U~TdV}N6N=6QMwcBd!u8I=k8r((m;Eh$;WePYG5^O)!GN4A;G58U1<-ixFfKHn zF{s9)@&DC$ejm`>FAOrMfWSYdmdA|I&DVqJceUpu*%YjR!2%3PWF>ptcgw3Alt?<8g zuvsb&HGLuRfSF;Y;dB(t^gkW-2O0vPFC-ptXB+gz;dB%X{ZB{zLIV=dh0}m;W&}%t zF`$aWts^gnL^faE!#3n-&9} z(`>m-F)ld`Ch-8<{ZNUgeE@2{^ZzUH{4xwkJV2v=N<3iZcIa!viNCPd{wMzaM0W#X z1<>f95)X`La3!7#m;GLO|APjud;2Bvz<35%;<-TomuI4YNCUMEL}5VU0T00598Ls= zq5p{pKW#(N09AfUJTRicm3S`NeaSW;@mzQfMinU0;7U9&^d+Lv|MnVm-3}ufT!{xj z|0(hO>M=m#x$s&W6b&UB>ok0#vF2SOnkY=;x!?+g{Zr!s zcLE-VtMS0z`=2lUuiggK3ZTD!YCJHe!PR(R=*vt4)C!>0KQ$g0)8J}67e4zh(?kK4 z25KAl20&X3jc9N+o(uG)-UiSBSAJ?dFs8A>Q>|g>%S;0_o(r#u0}2t0X>c{3i+2Cl zHvMm}!MFlt8eEMBhQ7?SpI*Drc)-`;E}d*s$NtcGevJ>9#slREpz*X}Fqd>;z|(lz ziY_sX9?(933FS|X=dU(3{?K@S@e4o#e*UTP{1rL&hsN`ZTY$!MVH2wH{1vJ3hsN^< z^1>!m<^9Smxq406RPq29r=gG^9S;$P3VW_Z@r@N$Ab1363}=q+6m**Uy=VT zXv4zuz5@3#3b}YRZiUr#5~34)B4I_Mz{1P(znaGU6u~p!<{i^Sjdozzi;|H6H2hv8 z*WmdvwsAcBuH}(ut0t?|CSqFGt4ETezYOyR1^+OOT$=$0$M=hD&?rHq9f^vBA7MzH zm-b}6+`%%jP@0rJ_H4)}Y;K06*6hybk!6+xDG-Oil}?H2yr>*nj0WH9H4V5o@f5R2jwEv69!cKH zo^EV-D1O8!6S6gLz^N)ahSHE0=Mq;!=!g+9;`^u)KGd+3Zm$fZyL%}^G~byTucVav zKj+%_^}Oo|DSkLxv7hkV{TBANHV1B(Eon8mcBxXC0|{=D=37(Dh9hkY~^!g-061WW|StS zYCQLvhRN(o#{9~cxybwT$t$kX5&;CV7Cy*IR$M7Islz>N1e|Z2=c*1@GU>+EsqYt% z8g1L*&aC;z31t9AOdW8CR397qMiZ>y65`pa$IA`tI#}V4*W>f#$8=bT56`T7zVJCL za-6D)C@}4G6P&GXJkEY{tQLL0*D~0f_38_fuE|okw zWy1J8o=J?#^{pUv9fM;7mJh>WjDosI2H_u6-Tes|86O#}?W?V{#<062FSTe?&(EJH z%?}^&q|bRIoMyVaovm-DEPb7Xm&KwHl=lueLIYf3N#zyxy_emnR)?A4_B+f^fkO{V z6=ohDpqJ+|oSnW3{a$M0)7-&H!BO8|3+cDV<`bcJU+2QkTm=PiTNfvBSmp!AoJJqD zBL@|)>;{epG-_tWV2^x!!CBWE!;e~*X)8Nuy&*eU*_-6LC;Ey%u2luo(Vwx%#@n6X z#siEaNeuxEDS7V`DR+%WcR$=W){t+ElH(SO@3200?p=ILeC#rLw#F*`f#>8?a`F!& zWR`?am}KR-hi9v1^>3x*vY!S(;(Xgj_j%7R4h;b7D(FldmYxFLYm)&okU*Cwobo_s z%0ESHeu1C?nt=gYX9L7UjX?=dc9jQF7r_Annk`TQ2LRgGw4t}byW>nAxK{Hr5So_) zye0soq+!Ma!K)7>Ps#kxtGTs67qIUbkAk&6tYBfhDEXI;_{$ zV(kAQXOs3hr1!%hR?=0~;TBp*3eb;n<*F~ZMcqF%UQ4F1`q9m^OHKB@kVLD>=lhD0 z#kt}i2-r6)P+H5VdJ1Ywg^N&=1D1NBNpHpMUvI@~eSxMh(iaBjHf9zBDU3Eg74cR1 zI!hDdyf@1T-TuNc*fpu9lPdVFLSu0~UQ_*SqAjSRrg`3F(w&}Ct|Y#@)-}ZMHQ$6W zav4l8^xUexaZrj`e@BNTvYI6xMY$>#1NE66J)ysA7mCa<)>-d3O@ zq#K)hBp{izgYt&){To=jjS_d-T!K01zkm+grVXsgX_UL$nH=g8!3|{n-4v=V+6|*Z ziHrH9-V$Hg7~3fPUJsY#P~6}9Zs>B{A8bDJD1Ds!4grmbV7F_?*vAEd?bFfW_*=&h zHU03xgji`2>mFwpWmzuh(klU7BQO9Hxc>vkdL^KfMaCXLD)_%~tQR=w1&|X4{6BFF z07A+66A1bX$87!>4sU{h{AK!^g8Rqs0&*6fnisOMo?MkF&W~J z!6yzFON$!uTJn*Q~o!RHY+#6QI^Kav}V=3?%_#9fm_edhFD6Ma4?kOik;~r zCO#QUWU$1^VNY@=y|KC(etjmo^J@!7G-;?ikdOz;y<_$A`}RYZcSxr{!izOJ!zEed z_U-I#nTRCEGma^et&%TpvG{NLc~Gqh;sYEZ$R?GSLC=b?D@j1iwZ>=NcrV}6bFvm7 zuijLbjGCm2q!y3Zw<+Dfcl-X7US*AD(ay;RDG*>!(T^^!-0RMyi|x5TztQ#4k8G~;To@a=|D z{)F_8vi0wuKJfTKhZp3dFM{eJ-=G+CQ!n>k#uP1)nas$A6=kdhp-A2}O0&Fo?~;{G*&`(^zn3?OQC@tgQtV5+Cb z5t@g7{E~*LcfRS+03ScpUVkUSjn9pOR+9b6IOp#Ct+E^w?b8#s@9ezvom{EwbHC}4 zMDjXj-!`j?o%>({s(zM+EyzLDC!}zTx@e`pXyi^o6@G;<6XB*i68n-LW8J3^ye8%K z#7d_mSNHW>h=G(Js0Jp{v-`I(gxO^ROzr$k_8J}KUf8IdIZS_1&HuDPfvZ9Fj>0-U zcy(E9tEFbYB=3BLRr)>0m>zCze436);Ov`Ey&OW6ETC^BMpZ2cW!ym^9=fLqi zpkUNRAGQJU1<(aSJ%D}!$nIG1PB?)6xGm%t3Mg>|pnyw2p*`Pb_r2}14%w#oXV3q( zCsqtY0!w%lR7z&LA8@|7fO4t?pEHJ1|Bf*)3MDw4jL)mdR<%6&+CyhWoVxOD>0aWk z70}NS(8_wPF3Ca|K8aK&++mCxpPMc~-foUSRnJUL{xYD3`FTwRqiYW` zU`iQi?K6fD9o0WCd3|;zTq{KFgZw^ss(3~1GgW=jc@4B2Y_Fu3#fQvMm?=++7P(A> z%zEj=RDV34pHyq()7AQr;nYvgj#i&6Q)bV`bieP@-cmM*yhk}KnJ{*PE2JvFLf$3) zneek86I1VbZl=#rzxj+w!+g`E{EY#|*Py;k+U2_>T?BVgJ(t4Gljuf#qbmi97F>`< z_dFkr4l`!P_`hQ=v}_pMTEs%C$sOC4!g-t>C$(_x{N5za5_#e2Eu%J6s}-_SVAE=2 z;ef*)|2Q^Ip}Op_1uYI$Y$Js#AZGuRuQ?d|tTm6K-j`rJHD(zEKAt~03gn0bWwphzn1OQQDCjnASDwR3v`a-#<0GRr zrTrtYL2SVn9J~8+8c;=wm>mnEQZ60U-E| z`UeE8tN}|vwMnR@PDTbM6sRZuKR*8n0(R4Xf?$^5f___i6AY~bfb+)j^j*k2vv5=J z?N36_f_ij}*<_V(8HV0<=???%!LJw#CL-?I{nZ*LQ#&Y&~2(`QM(RP~(aalAgNe^&SBqy*t zWLLfGj1Xx_Th7L6I;s$xzbGry_%u(_O3CniVmwszA{~*Q=$d_WZMpH=tWx9s1k#*$ zo+1$a*+g&BozCGj*~c$YXIJKAY#ct-)=}r2mO$LyD-jn;N28J)6Z;QrQ5E;Vv*QNi z#^I9PBAYKyWGw66UZkr2XXf)LD9-}%0kDYMAc*z`mU z8|q|N58d9NiH=IDP5Z(5QLdVau7bHU6uK7noLn3hhNR^Q0qlDrO9XqjU3a=d(Ku61 z=0Ewd_W!qhu0>4M{tV+V|x^k=)qIk^MUBbyuLV>Ru^KeA%oiL_;c zwSPy0To3~qMiEfz6!Eq@{~Xd2ccH~_WmSHpId}I(p(o0Ns^OP5{O9<^-NliBTe|pw zr~C{m(8ov>1N#)fCL|>$s^gZU^~^;r*Z|Q>?h;ty2ZJie-6b%;{_BAY&{l>1GzU;n5Zhq`xunP${UviK1?j&5;FOX zf3G1gJRn{S0#g0*kb4!ocQEpE;eZFx<@06Xfu)K;z(#Wssy$|}B5k zPNxkxc~#W=7^Alz3WR_CS#)%27gAf-A5P=yfSz;27n%l&NX(M(dTU+lybTmSjpny= zcuOKGR$Iv%Mjjz;$hIM68_8v6qU93jy8IwqxvKp^^4|A+KhaDB$H9C;^=Hp(S&AK! zD0be&cVjyX$Sk061OLK@^~Z1h>+%4}oJEK~x1fmOR#2B=PDxzON&E?M7b{CzUHMo- zGY#GL=F6Hv5%l^*;neC2P5==FaI6HdH7kvkkE%ou9J+5skr&Npk-ZdOm67G!fCKxo z|4dL;G|huYS&Gl@ouby$${yC=zPrO0?LpkCkLd)D_OvSAy%XX0=c;Y-m)M9kytw{A}eV~zR zL`n2Aah>`@79Gu9_Hs?JoWykXnXLEv287PZq)37 zW^WqGF1hRiwL}mECyW}>oe9>&6%zPDP^yrydRjV54hArwwIRr$?eYOmH(gAWy>A(U0_tOB7x7=sb@F!nE*F}k) zuaVNX*#(013M5m&Xg>NQ4Bv&L^5hIm!i{%cKIrB~yBUXbDyn{TYxDXV=@3r!tiqQ4 z1Gh&p1yZkO)DOu77$2PS(La1}pDTScfxRJ4@HGC}czvf!FFV$t6V~Ce3rD0u;d+)D zcYIGq5~H6_eIBGH>S;0xZ=DOK#_5fv8mb9JuIFP%{N*(3d)Duze6*GmI<=T~n(AY$ zdVQ(#Tx9yFawa)Dd+Ex)r5di?j1S*4^C-J#nr9+;+pt8K2?gFP$S5NSMG{m@MFl%XX%rtIwku%^bm(I_f0m zue^~}euQ@(vKoKF6ri@_yE!|!jTE}lb8KijL@3<3*(rUXaB$o^8tCFfIhvkK^m$ovsEYAf9*M6T52^L+ zhZ3go$~w(6Jhc5zm2UiLq<=+ZL+j-2ftPU9%w%WlM@BOt-cx!41%gNd0>1B7Rc zcUgVw{T%!7rYBt5mOD49140?(Np(KWG|`JINt)Il`45c=5x$1E1zM|;W3br zea>sbG1>p*gk@QkkWKF9%!nL&sJ7>*PYB2p zUGEdRXP;jhlyz>NcPE62%1rNhBTM*<>5b7(L0L6e>Z!cMKPEM?M`uU%Vv=jbgO91Y zPmAlqSL<2Q^_B_G-i7RYq`fv9S<2xWX)jG@JyuzWdt4Qo;*6HHU+mF%k8EGHC=!uC zDH7uPvC?uNy1FK+`^+`*)c!f+O2mxlzTn$vuk!;fM~nXZoUB&*F~sgBf!rLM`J=UZ zrVlkYcwIWjw4P%(baD4IP~~Wkvt|s%HsQx8ybW$J*zg~!ysscJRzg4EeqXW%lVyCG zaJh>k_DZOSgone^{aKmrII8i$NF;-V`N>kSgjX{ev7Sw-e~O#dCT94ZnP&m-^5WC; zcqnJ^!}c3ebTbL}KcTLhMZ|1awn_1Q4IF#Jm}`SA`k4P-!Mm7%djdObVAOjelH-VT z+kf1hq_NBWGqjtTi6?V8tEs5B&oa%X`+7?DG_Scu^s6>FOx{@!ntb7Ma#S&+ z^2MEcyzGe9p7q#ztMiy)W+*sn)*vs7cs@3>;lt{7pV+v}u}{K8b8CJ`sGDs7fek3# z!RDHtoKEGcx^+Cl@h+_jB6BzfZ&9fB9p_LF?}@x#PM+kFbG53#YAgrhJ@a|=kX~Oh zW#Vvr91L<2;2OmYb*sq^UH^BF>bN*uGB6YU%K-AOl+5WLgz4@ zxm-{9+ju02(;-W%JCUh^_x5;WH_cNI;P?QlgZQg9-fdN%)6K3BvKZ)&k3YB9O+Yk47L z(kBkmUQzz}FSdq-R2fLcm0iipG85X5)L2^evB}zPRDJRvMUbTe&_w;0wC$5!4v^6ox=5HEy=TDiaTFK!eB)zD;B|Zq&w^ir2$Pi#DxkFDQVWXP-;z2~G`Sr4_ zLbLZ@U6f+#R5RQ7Im>D#$M^RNOoG3G8fFW^H$MjC=-;LZeXLST?LT4=JjVr{*Bhcvl@5UiQ80L4 zb-O*&(mRUI$-Y$?9tPpl)?2#UZ2GBGSl$i8$}C5(vZ>vaR!d<A;z|){K+XVWVP`SmrT}oO9zy^-(oewn+}r zx@nUB3(gaH;l+0R{y+{H#5?ePbHbxSgsh zjlUq>UQ8M^hCZY0h_7k)x+xkd zkdug+jBefpbK&7p%J|#pcA1#vCZ)t#eLp<^srK?bzi7O1?eL{);r=s34|Ud7cqLH{cI=AH^aD9Dg@K`6^Lr~!I@c+fF__kMBp_K{!zDfv+OqO5FY(taQz*PUXaI? zLyFd!vmo?r#`e-WGjkOmRv9xs%&(eTj)5i@uKu-=B26eTM zZBI{!@EBk}@stnyaZfjmOTh2@6{@^6w`({xL+W@Dl^!0N$q_pPdNZQQrQ zQ^_cvZ?HEx#m#Ze(kKA8?lvq%e*@?_YJ%8f{;G<@Q`S{KN1A7;u!Jl7u$8tty$Nsc zyTt8A>%D$&Fw%8b4^4z+wbbJ_+j)kqk2C~HyY~A_PjN&>j9C{P)(c)QQDwZ)K4sX0 z#2pc&nV8$vV7PYXIqWLBxi&iLXGf}O$I^r|mLs!-Xfop!bSC?2=)UG!iXf|cPn}+s z7}%NCBvf$gBiG`?C8T9xRwGuUoodz2glpse!rhvz51k=TvC3Ud2D#(a>?89@uGlAp z!U2&s&qF^{ZL=Hs6I7use1|yTATdY9a=Ir4(zRJ6Xc+_=^eg^wJ?u>!mjN%8jDBI4 zw7B6aPUjK5M;tv+&?hEfbw*V?AFIi1h(K4n&0RqYAy{ljW6PJocrDv`-8z^9yzQUM z+7?EKsqeI8IPS^l#)y@G_(OtM5sa|y=2|lAPK`8tC04@m!*P}9TJscpX&J;efKH|d z4H8Qiiz(7*n}?S&PoGk?nY-NK0j{f9E97+|<-JiQ%iGR#lsHeaJ-=w;q_RDP!apu1 z&mEj;k0l9AG_i=i>s_ToJL>%ni+uT-2G_>dl{74FG&1fIzndSpgSpB}o2*}uXRP6Y z`tER`L1nx7X)!+z*y~0Q+BNV>b!3LKpVpVqrquDM&b9IT6^t3{`|>YqV0S zw6*kfbY)g^;Oi8JZW9<}f{Qf-l4QgSJ~XPwW41hD;MZg-p}ez^AIoHCoXZaT&8`iM z6f0IE%G>ikiKp>+iTO&X)~$A5yBF^V7FEZoE&V>0E^Q|f>74cVQHFh~j>gtVG|o8$ zQD5ZY^_55pvbnXFkrm1v-h3UKhZCm7#zzmY~|~@xNmIl04x8+ z84b?4scVf|S7vk4bhJ7SIZtxetkYf0`ZNzqb-@jOJlW6CZcwc;@Q-c2?0#LE#w0xE z??y6dWLF!H`%!^07ZEMX%eBId+Ehctw-rt^V%+Lz?xG>bJA)X=~;~2lp$lJ|^ zXir%?!ephdzM8hnP1EnxxH|jWM2T*~*MoOp45EgK96h?O+KIV!S8eVB5vS&o;|jJX zd5++w3GTO5nJOfE0`B>`V9Ax4?c9<>E^Tw_9ZsvE`NlGE`>DBe(5gbk>eYU7THd@- zqVByPXH^Pz%^H(S>*7^dz;pH;%O!9-1^N{Xgdk2g-nQcpP!x+oZ;n%%U_xH>#)<$jOP8IC; zf*0>m#pzXaRVQs5-;-XX#$1;CB%#DX(eT+;cVQ*|Yk?_*9gOGda?d^r_={@EMYCPK z>cL^&mF6*(gS-<})R-=wBYKZ^U(NM}Oq;&U@R+&nHz4=I;|P6==$9Z@@i>2%Rr}_z zYou-g5%#aM)-0+lav^c^C?Y43qV46a1ooo`(O=cSl&_vjHt3J91e8ZrS&aGmw(~h? zlaJ-E%?6Z*>e*9#wQ#A#NzNSQO|dwCHlFu&bOQ25dyuB<%Q3P@eI?)4ww@c!lVu0+ zmr-uzk~WN>U1sIM`w4Q6W;ulWvLAMgv`O{H7YXc%rwvMjQI>gnAv*Ebe-NNj47kbj zETxSkr1>63J>KfcY!fM%-^gzfqpf#{3N5V9OnsT|&eAbA`ZNj~*~MeKPu|fcdyOTY zoNbAgn zz?NL@!rW%9nX*)EoP4*d)Hpd3amS;5gyRNyp{I;>@D{qQ6?r7hjeYC2PBw{|FXPrU z(dwls-|k(-5@j>74Pv1KXMS*HC)75n9y_a2QwZNLj0*}7IYZ)6d(UMP1h_&C3FY>rd|zOv(b5_n)hb9>*}+!C}eFtGgVHpcPES)Ti`x= z94R4B(E_5rKkJZu>uK#w*_3`qulARFsxZDQTs&=x&A_x;uw%W*G7t^qluS=e&N`_5H5jpD?r6v!Aus z+Iv0E-0Qx1G&J|-M2jp6oZeyYCd*JLj>V;BF_jnfqc+_#>ZFv&L4GJ}I474>S1F9x zd5upX-IbLbRG0KJ)YJ0np4YE&=)V0~=#yOHEcT2^?Ag@KcvpPJ?5J95Rv~|$#rzZZ zrgxprx-l{uP;OnT-4taFjolsc$vCTB;*2Z{OD+AU?q1T_&brb+E!^QYmSP!~VrRW# zMtQirVgyh=UbLGl6w}z?y_hJcE4I%KEuQWuXe?hl-Q~bv4WrJ4_N`Lr*^6xzD6yu)zyBW_G7NOqEQBN z3p`Yjl_zXqq={YWJDMivL4zLaZ263X%R&*y)rVgTgU$9BLK$_Wn6 z_dv+u%~;QhmP*|d{e&@gfhcDMOPA%&`8vl=<0LnR%Px`%?zJsA6;7Du@bANxp#avn zt)!pt?}dS{5lILlHN{8J&a zLcaWo-E{ciYx&8-(*~n+!270S_~kYgynz$fz32Pq(eInK@2{`nyD`9tL*jHM;!{3l_cXVMZZa22Qf0Tm>iy+sH=(6U)3wi(?) z>+V~)k;;8|IFr-hMLvy|)N*v%txs?LVd*Us>)lsi5iSYK-8Sz()Y;Ba)PU8z(`YFv zBlZ!{OwlFg5}DsRNITSw|BmU4><3-aEX6TZZcG_iM`ApXz5%glcfP z#(CmlY5BWOx*Ca41TTr6Yd}0ul)#-=G;fzzFSWF7bzspzFYNl$vqcEoRbU3VmFpz! z)?f*!GeA)nT4&*%qm|&;;vDM!k=wm5hdfO#5M;TiyGkAx&Q-eq5TmrvD?s;jcBsS6 z4j<_tH^yGE!C7~|YS&sHqridyAXk(y3ScqccR*TkrS>^b&zboqPp3OiaOULefVjy0 zqr8{lwJF4 zg@;<8TYwZZmr9VpZ86l`ap}#%frfI#BTw2GccSi|nU6&H)%F*jDhEh)i`^C42Kbh1 zb-pKL57=8u_E(rdgxyWi?AQZ05d`9T`zpRL|2muO22G#GFvra94l&byWJiKZw2>2Y z-HyPNi_Z&_A2sw+g|ajI4$IPnve`c?QciwnjBr zaB*&jna*+qC@hg-s37DV1IIWu!mj;oSDE$r4RMrpTYg+dcT+#12J%YmRxKyv&=KEI z_UasDJ*SkxE6KwO;uiRKG(U!8#uc8Gh;O_qutx$ zQ~;gMn=seQOne>UpEP`PJq%OUgou1Ci0~jMu5%yY-&D1$N;tBpk+rT*t_Vwi@eH?Y ziLIgH+dC9f%OHJRl2MKB09PU2Y(ZY?yNBfuSKk1UJze_s(&KJOj*Bb<%}g4EnXY`g zDx&d>WL`L&-*C_rx~f+XRsb}Pi}vD#nF>#fEK|(#9b#Her&k}94D<}#zO+>G!Y!E2 z0>#DXFnK(l>eK730$7#AP1NC&J@7m{e%o^qag3A^y-1)B;B3ZurvDNmwyr%>2vdj1 zG{+@*GRm+tj(LFtV-+XGymys$$T58s?|oCij>9T!Gt;{0wV>jYCB7 z&f1T=RbVzlKbrbi%&(Vuw3TWEw7sF;gW)RsQ_2Zp7bW^0VKNQJp28yX6kBDRbF~gu zjcn_xOUP3a5r@XM12ro%q9#7=xQ@d>D}(;Ri=keNRk7=f^prI-g=;pHMSZe6H@b;q zv5mB#qqK`9kC47*?E#PPi#(Q6{*ML7NYsG=X~B>8I*>7~Aqz&2(p15>45YvSyy=%@ zDcS9`@Ncw4g!|C)8dLCQw+DDar*Wz#9xqkMMHs0Z^8f~?Bs>;F{f6+;01Db=1J_IsNu0M>O57V^|Ibhz+E^lDPf~w|aiEf%123*PvJ-I;hfG z=l6uJ+N3Qm;s$+P#Rk=r`OcO*r zl52xjJ`-#LRV)4GEh#!A0hN_qn(lMQALe)8HT83liB_ru9C#aK$6CB1Vag#67MS2k z<@kdPZKi!cJBcnDs}vE7K0$c_D(}f;d)NUz|G}=cFaAyNVF%8fCddPzVNj8Pn>f7} zs^Rm57r|EBZyigrJinH=u((jV#Hul4d)%oi)q=n^y|b#nT1q>CBhPgS-7xMHu?NcG zy(IjKKK-*t)u@;7_tCjT6ceFc(1yn-NXv!wf>gA@*^+#`vvqxj$$c&ZvQ6cdxA|s< z3H;`+$e&3E@e*G2p7dmHs*zN}5yDVXyOXek}A08L1*q16o|gEp3TK*GsljP6jv z(x!psxPCsCd$AVd+D3G|KzUEgy=5+kAh%uLRWAFf8pS4x-fc7RO3Ypdozlhn(58~v z*d}?THLJwz0`l;IkM+ z(^gO_-+ZavQ4SqRN^qD4Wm<}dSa<{Q2q3^_Y4TG%Ud~)4&(1^)F$=37v@YF(xDa3B zmO$c`JL{<{a_ScF;kvCqmi2Uqy53~}3!9DetUdDyCa;ct*KbXS=j!Yc)DY}L!9#v> zTLh)R`D)sm#W$C8c@rub6pkRubtlJBTiGn>(xs4f&2}*jABS784e<68|6%HH+}!`b zDpVEQ%)heZh)k7!+xqSih3Jp>R+HCR3Oo4VaUUcHo2 zbibcp8Ge0;V6fW@9fFs<7XDp!lCL!rv@rbM2tF$Qobwp3CjuK)xkSFsn1qm%?yiY==>yV+31%Z4C zr5LtRf}x))cFpQFslJ%m5amz91XmyV|Aw@}MR4V-;jk(=jteb>t@;SteuWuQ6Xde8 z`cI4^K#?&5eCF~$yasR!yuUC^_aXrQU$ip*HGdF%@E{zWgcbrlsyaI5q6f(E^`Des zo}7o)uuDOiI4dgQZL$9VdtsfF9fdsGx0{;P4_)YvTJ^7n;0xnW1BMqg8gu6sQD{LXh=MEzd ztoKTvoj4UBz&{$(A*jkHP7!Pnhw31x)A6a@=HEmLzYrAC@-=YB^T8*|Y1<#cS9WwN z%O+C}H|H2SgnWz{QlvckM@>pV+&t#>Dhp=O&0oAFzwPm&4FUjg$~#WGevCe6-k|%N zLA|$qFQ2fi{D-D!b$hNJxKorl70dtEi@b1dTDUQe5r;91K33kKzwX)2L1M!}K>Lcw z1MwMf-Fa1i0ptH~injYGL7S+6TZ99krLazpR3L2C zWuJ$2@c)UQCYQnQ>$>&E*O8gj`Mt7XYT6dN{5akv-fyK(mcK+kQ9bM7d{|*biu9sR zj#o7DQT6i=NqEdy{kKlkGx-co~jGw3ETArhD1O>G#~_gr}KXIqsA3+dwR)I?w-cV9plu*LiLI2 z-r=`eJI8`fU?ys=M6BQ}eLqmGW2(_{ytNg|1W{NCsj>~w6BwRnHY3-F zlr`#6%i(_TEWtO_besQHPxz~LLMjV@7O3M`EGWUKw9+hJ^KqVwcp>WH3H~}!3h~>+ z(K)-c7d6W;P4}n*QSr%j#>2Nb?=xliT?2ie9`%s<4TzfSjP?=gPcDA}5TVEOegEd& zrzk_KsYcHcGeN4cikB5772BFs-A}em&`b)td}4L8_v|6})X3)Z^KU`o4_p<|WGvDj z*XOn(XuKhbx0hCOjf*^XIV)*P=|9Z|UsKRTC7085JWN|$_GhJ{ksjWd(-fp#!B0J3 z$@BHlMi~^QR;xNmd(oS{t|FGx|>JmhPsq)GZ;V3)!CmCg;ps3+GqLuJS!bD2cpY z8)LA(E1G<{+-bx)_-)}df&5*G2lvJ87qe;s3yP{8Jla=|f(%6ooQYVarXYI~ zX$LTlX0RcLk%!(;X0y9Lk#ZYH{L+z<0PmP-63x<3OW_!?J?_tjOMn+{HD!ae>7b=o{cGj<-t*5ni z`X~S5UW&s({t7KMud25;5)c?Y3{vOSX_70AjR7Pcku)tB1%P0RN@MKg+*C>Ph zCxPehk(2jmW(?)w%A+bcWb#iV0g9ule;COri#AaPA35phJjwn4D46vN5`OQizJ54w z37l7FoY@Jkv=#7&+kMFZR(@wfWA^ATYB%8l4h%R@^6QF-7?lcg)a%Grv-p>?J)@Xe z72=4mLXb}HzJC&S?-wE!J~cGU2;-nhW8kev=a^~tXM9q?Q?t|Q?)(8m2p~kFH8?u< zAF#-Kh~%J(w9exrc~wG18hVucLFKjc{T8;{mQ8vc{R89KgF=z^{W{Nx^YiJ&>cfTc zw5z|Qm85=g)>H$OQ6Jw!A5mqLd;Wa*Dk)3-*TFllYh|O`M^rNInd?sx zn{YbU7w8|~42lqc)!6h1v40}C z4O|2wp5t`xU`G#qlb1L==;%5$(F$E6Ll`-w)fDJ3;J$q-r=dZ0_~qp-Grd6*xp)tR z8HWb6DZDkA;V+~Q@^jqPDs#u5zh)LTxB3zYbxFs4qu>2wdm_X`%}t}Xfjj0fV0Tq( z+>BDM(Jm`wBU6+iAJKKe#B1IB+Se@IVA>MMw2Y} zq;CnmC!AUiNwvzf1+l$5CRvSgsR_X;{n>GxT0iC9v&C$f)Vn2FJ0uk;(-y}D@0yH0 z{ZS-`A(5v{TN2B#W3u{`s-Q2MH!M>*Cogt;vLBB|LMsVB%=M>Sjk2i@+ZYQ+Utg!l zylT!G&4@AXK<s-_8l@Ey#k~NVl z$&OJ3T_98PY$_WbwPO!0&-ljIU(QB^G6q>uhw6NZ)3c&U$~FTItcW5DJbNFPgaDNU z^`r7p5;n}T4No{|0B^PtYo)|w>N`29)q+JZ+1pm=<(3$76y-6b+VPEL2r?cZO z;XliG)ax!0wf7}xt{NTFM2xm4Fw0=*kJ1l%_7*gEYKkybUq-8YN;5Tgs_Bo;C-B>O za7L63CKRp8>Ky;fgFPi^mJ4Hxkj zD<#k=uV0KHM}0WSyZ+`5NOPJHQJlw3@o?Qw?>zS7$)G&B`1Hp6U7&Gu^q_o!Ax&yH zaM98887N>s>$}Bt&!1xPoP4%a>cFT^q)N{uiC^827aguV zgq_j1+z7rXgq6j(KZ=`Dw_g7!v4eN>m~}I_yRqF!s65TIoGhl-!ibb9Y^{UvR5xtFDr`*` zuCqp3a`h26vbMB$C8Y78G-u3Rmot`vvsKqzb%?HZh0eg)Cpscd^k>v*9oUIV!YIln7OLW`=44!~x&#!gPVFWmIlW+^XdV;Z zcyahpJXsF(nA$pu4V);4anNZ>s?fsr)z0mU*qgU8E*dAC6XdydK6*(hT1Cb2Fip#~ zO=fIalGCzE25ec13in1nY}ruZJ*T>4e78j6(lC;`Waa4d6c^hKx4Fugj88((2e00H zMn^uG@Kg%7yY1tUf0i-Q;n@u!Y@yOiHiqD@^=a3c0&H~FpA$;WKpjqOr|Jk@g*XP! z#T2h$+Q1eZ=!@?PSY8yn)CPQ(3k~|FHKfQtsb==cP}?xI9W$UG&eUt3C&&G zbUiH;rH;2HZ+!~5edD`fOwu1+12wEeF9|$-?zS}_<-4}Ol206ceYn9;phaY!^dJfaYQrh?+uV!0N2@{qYZ72v`@S`HH zsS~|UO?#w8-@v=?D_Wt$d)lO4ww^A&l|@&NiL|K0n4e1En*lWYN9E!fwc>jLuklR) zJw2~!G2X|U0d#t4F@^!XeCz-m60M*(=8KYeB;XB>ZwrnLzUk7}=&mGYR^v~!vf<4A z#!2ySlbDqO-+Es^Pl2IVmOgc|;k?Qzg_W~PUNLCaUW%Rzx9e|lih7QTw#y)cIaT`= zsXD?i#~@~$vwYt~Vxr(MN0`F@TuwCit-ZFB^#WyQK z7UR5V1DSvgPN{xMsz(wM)mDw)R-QCiZk%r?eB9GPX31XLCa~vecFa;whlZ7U+r1w# zNrGN;Mp$1Ke_)r+#UhgQIcr(WZhPk=O4_t5G@@ne7gEa&hbIcLo#lazbbBs@BI-$I zE|Sfr1Q_wAzSec0^P~l$EKpB4D{Zt`J5#7YrSE={b2e|~bo+cTE{j^}^I3SWA8X|$ zc@J_FD)l);DYh0ANf79q)^dsS89kjBTR6?szRYdd$T*1isi!G*+JGK#61t}OuG&F} zP!N|>3U`QfD;|jAY6be&b)WGRm3&_%=J}0sWGmSgpg0p4nR=-kIz`{mJ;=jHiMDlF zA5VG=BY8+hz~7+Ig>*6%ib4d&(WSB(2Ry*#|13ALeypn#GS; zIGX!QzH92r#y%zrED-}Y%yb$9?YFH;6Nb*hJWZ#G`n^qZ}0F0D5&Syh4JSw?T%Cub``?U0r^ zs8?Fb#Z5*0l77wW(Kv=dy7Ue3&1BM&O|jQ#Gup&ZefYHlX?j(I!S0FoY1P6>)pZiH zThsMHjrNMx-4gV@8PneFwvT?zK?me=$XfQU8trCdFo5}XjSX!#zz|$Rayr+nV>DLM zhn&Yskm+SrK~c?TTvw;XdVPnOy{lnDeQq)YyJ>KoU3HVjUzt+Zjyv@tt#0X;>>1rrC~(p#86CM`@Aku@{4X!1!+V< zxqismbg3T6={4&akuXf7hE~DL8#4npTGi=Cj3ZU3^-NTBy-7lWmW$5Rp#12dWqtn0 zyA-Der-d`>h4CCA-ugAug{%^ijBFBZN2+YcLc4Z}h1wGB)NJi(M~okH%2OY8YdoT@ zr?OJE>$@$T!Y7=7blVYDa5Gl<7I`H?0@5yqV`L-?@%6|OF6DYBgbOg8^!Hc!v*8CB zW-DIWyb=leH}=ATFS-hYMh&eBR@7Sh3WLp|YHsG?-;&udKefH%o0WuWy42<(SF7ipjmycP^cvL;Ay(BubIhj7v^3L(@TIa6 z_|F+OJn*m7%sZRcEL7$OS`w(u9e=8xg4@RTV761Jn2F)yV&wswS5n8Ok;<2Dk){uV`0P*IEq7qODEOB(u#35h zE4imF1LBdZd_0SvM@>^>zRW!(0hO#)BbYhkfeOTim5q2z1xF!+yWE0(Jeyt~fqvV4pUIIgyKa$a6M*xt$#z>BdutCyjkJlg! zcY)&NaL0TEN8txjiby+$^Z>Pt2NYYlndsfU(u8#3gg`>fZh*dG#|0pOgFXzrX1IT+ zb%~b>ZUzCrr)QToyqe{JeXpBp*VQ~nIr6=Iz{eYTDuPhpZE_VLce9h8aL%-!>}}&* ziexr{{SEdUUp@70*5!Pc9>V^i<@LME1|ea#>oj*jh;-_hcwJJm=jgS6Qn58gm;NVq zRtRa2V0`2wNP`a|*o{o~CUe)Zk^aVVXAQ|9TvKHLbJASC;dy!&mz{;?*o`I>YOpY1 zpm~mTp~>3T_o<(&SSWrVMQUA9zCP9ruJS;bw5FOQ zHS()U-nHybo+yh@Xr1jg(R4`Sxs!A%ioq?j9_X;m0zZlyfe6dJr1r{(CLhh%X%fIn z!-u|Za#A{@|5&z>u%lT%11R z8#DJgRTLR=IP7l3OlczHgmyz3F&mIJ&r}Dj8aK`L9QGRn3KJ>1ENC{XubFuhfrBt2 z&`AXX95uPgYaNPV9lD=5#<(eIryWtpqM&kxFka2?kshGs>*mS0$?Gl4-9qE+&6PN1 zUuERP7nv`;P%^SV+dVF`a4offa+#C`6hP%sx7nUM4bkI&YjetULBg<2kRFlTPC?%R^&o4?zlhr%EQy*+_xFrQ{3bNo+!JwO*#jM=y`@L zZXR>y6Oc4b^XjSZi16}_xu<|1ecd?>dUQ%znKdN>zXV~@p3~>i&=Zl(D`1aI(=ptJ zfb7msiPE@=t=`n1=e(zJY)DUDYz)?w4&RV|-_$*E zKDI2>%^v!?>&&5Dng_hy<;C~fx=#1B8NT&S`%oZaoHbc0G-r;TG>f4_)UjlBSJN$g z+N60k`|A6oY2n}q=XPP0pPBYPW$1+K+bCJ9nk$cPK@}!RjzOg&kdm1;Y1dBTs1f_m z!Mcb{WR(zN4wIob;~ZTm99{TwCV6?!iITPzg>q^;RY?Q$%Rb1cQAq4W>?e*g<{T&` z&bp#m=(RiP!EfLvi`<$Kdw2?v3XwO_(7Xe0g5w>QVX`KB++bKCyAx8i5jw5SphI3- z`9QI7n%V9Ibf_P7OzdfUNlb#^3ToPisifm5H9Ahu*hyGV7VeBwvS{1$G`sv5vhOi7 zPP8&+_ENdpJK2(3+4yMy1}=yG_NraHpYonx_#4@)s8bn3^VKr4(jYYPpcf? zCjUNGwH0=Lgm(6_(>bkZoQUE(SM@HpLtvm|ma>`sS5RjO*V^|-g5NE*jT_n`S6~>% z{ozkL>ZBd4zgF8*B|%B!ay75)f)9W+=ic)(>S9>t`=K#eemap-=KYaR*(FD(PpR@Y zB=d{3QRaB!U-XljfTV*TYqO`SUPO`y7Sl-DpL@b(jZ5dc;h-aGPv+`DFaCUNzrxF+ zS|aU6zhZvmxo+WJH46fxD(8_Zu=LB_>H5HOCzk2HAfD^>FJ#*49lWAg+Oj32IgzDId#DsW*hrJ zyeW=nzz>Yc;Bj43b`v|Q97hxtC}mCwlFIv|r&R`h*Y5I;m^tN0Dg~Q*+1BP=coXdJ zBHG8hrBxlC#-*xuodF^k-aOLJcqWr|N(>g;aIF^I-HmTH1c^^?s-!VJF4YhZOyw)- zPy{!;zouu(w|whSl9J&whJ7XWdVFX%)I6opO{RNfU>ha$Dvryaemd5}oi#15I#75k z;p+SKPL+PQGFE{HAk(=RTdnT0ii>qu6mJNDYo<}c%>6FZ+#x6dly=N~Iik;|b`=d0 zvFD&5xGDt~ZhvG?0}VAjtRqp-_&)V%2|BnKePw$*2bc)__OijNWis))y4L2EkMyi? zV~gf)6Lsju4Z_LIu=|ov^%K!0>?X~5wv8K@sGHv6NTb4SbCV{b>}P+}Lzv-A?UZ_) z7l!YoU4Oq<^0b;msgBdght(a|!ymVi-sF#{xtkT&lAkuT`;dh9XY(sm)VIXM+Dekt5-lZWkPR_8_px9R_-4D%JhW!|g!MZ=HkA;j_+3W7lo&pk4iAOC=Z*zT z_tEn0gV~l==%JRL6#1jzk=4l$afh#5CbXQQd5vah>+nTYJQxU+?(`;w^12Ybl$e(Z zx)F+j2q2?}P3M|Y^V6NLQ>Tr5H_AVUXyUL%AVK}hDGSP%G;<_8VET?p}41-8p=GNA{4D(mCVU+s|9 zE1o(}?JM0EE4_jO&ThWDD!QXFq`$3FF=Il_$-kcPNX<3k%rGgB+H`w!z@?>Y?97ww z?g#te$vV=g?R072VQ07GJ;srZ<&Wqj@qx|sF-NvnTLq!=4eExNS&6-_UXh=G|Ip}{ zp=D}OrYSr74zro}>#0LMK^@wWH0Rx@WU{ElvvHO2Mhq$Mm`!%&MuJmKJ$vLgD=Vj6 z5GJa|iE>|6r=PF@{oN(~_kMH-v#=Jp#g`0e$qf?#5xouMhRx-cIcbMeBGLFvX=xKJ zBGKZ3hy}o}u1a#XY+-0h@c&1mL9m0+&h;?mJvgen-ta6HbicV?O_b6j#I@t0jpn4? zf{(^G!o^Mejy4w_99YJWVJ%7$(?WCDH>Kv+S*FwAY%5pDU;1uSgE~1W)#AaMNQ%Wl z3e==XGZ=rbc;+FKCkG8v@P;FMq6b)ovw63u(RSouNn;Ip$1cX84?~VebT}+Bm}imD z;tE9CZ$ypweFw!xP@km(roN3De_gGk{p68`QD6C%f6(sn5XFsX{Z5MAWSf!Z1s%!U zsOC=Xa-3I5LRa1Dwe6x#qsk`dp-KVFYoyh&Ze~k&j6gr%h_kcuHNOe z+Q)jw&FIW?ta*l-77ZZvMv&cS=QZSo{EDJWu}xW6SkSoL=cj?p`pXlZ4*}H~K3|A) zO{`i*|a2qjM6)!D$E=%N*iww6N9bPFyj7d z8Tz0=6Tmcrj5GA$3Zv^-P>=B@HRdv-tL{;PVyc&IUU40=a_Uc}(;Guehh1o6)5uWD zx#Zo*DbN}LS=~#HM^ge_&ZI$G^}|c7=pwE>Z|SY-AK;1 zzKpC#*scB?{-N&B{f9c=RvO53K0YIG=Vq<#M9K(~ov*Ib`RVzm)#nY0;- ztIc!SB5(Eoq%(}g`g#p;*z^?T#BcSct{z*pS!g5HIoJyLxG;=_oyWR$5mNhbV&)4X z-S;k`;DR;esYru^&=)nPZq_3Co0BsFlresFPD)b~f)@Vo^iakdokzc{n>RG%QCtRR^13vdg`BIn)+_puSFjXD2Zn2pm;euBKssN=Rx`M4>L zi{8~BIidumuq}7{Eh-4ua72}7{W-Q?V#ShuPpTx%sRZS+f>p&+wSnMFLj7K11`O>E4U@Y^KMY(2{$%Gh#twd(H}&~h zeb~=0r*{TcY@zB9LAOOZIoBa-@FSJBQh+bm^!SOg|Ogrm5kU!NSpQrH%woJW^&#&JygmQWjg=G#(*ilwrkjJqGKe{ zYMsk1+8?abf>&_i91Vm9}PL%b(MNkN0YH;2M!CN4@bT}SRjeU>=ymz zq+Im`!_*BS$L*zpi2q2_CFGZm?!SOu(s0d!a!$CSlrt8iI-E?0-ueHXOh=mIp7e^7 zqhiz+O~&3X7z&nC`USm`3vsbK)^J{7?t>Gb{fQpdUfMqR9<=r!=&N6>LejmzEW*{@ z957Cx4y@{|aM|UalNwBW6$q2_Bt4v$>ra?2Y-NQ0e;}Ji;JVGf#040zIFHzSuodV9LFPq;6BM2F{7pIgFK`(gv<0VVg3|<@qM~C|*oHzw`Hmcz`go;!;e=hCw3~lm zO2Wh6T-hYBF?c`?D1Q7G2<-Q5Ne}(u{$1bX{c=5>te8$hT2JCto2nCsyqzE|0C^n88?*h;`t5`<~ zcTw!0>P=zhXVHz_8kfDk!WEyPwKR~$X0d7L$)K3Eoci*mEYa?D-dFPM`U8SH!l-K2 z7q@d&J9`_K?I{M68?8f12|x$u<(U}PusD+Q4~YMeq|~c$l1my_|5L5ZqXLH zt2%34IJ>?|dBOM{IM(I{-w1c!GH_7LmGok0$*=*Dtk?8Z7A|Ucr1aR;E*Ejw)H{0k zbR$~L_YUR!{BT~Ve%^X}>NV~e$Gs#uh#j+8uq{2bIxi*ua(ZYwkznI1(*O8Ta83X}J zY>wN5L3AQf#T_7b={K;rCh|3o@A=pp1lB-aHy(Q-=Nap}=QV`~6vrt}UXey8^B%%Y zrYet@*3A2QOfC`+g%1KMx`+>m*Npt_KFbWxK$*Pd+-wKb36>g=wkGp2HR11MWg4mn zSex%2PdHOoha1GswfFMiV`($&UDg#(fj(`7pNAPc>%7$mpI+6*M_wmZ84px+ycY~j z)6{-`%vLqlckJo$RKt~YJ7qVgQD^L$LNmg7z{c*@oWwxM2S&91I?mrRTfvN(Lc4S4 zitVQ=+w~FG=Ii5LIoD3sL=V-9U55|bS~$!ho%#4%de?T57_V}gyd}?jv}fxYhZplZ zP5L0?1UDzasmVgR{B*Hm3p@;=cd_#FMrnH{12Lw3xbDlkm@);}A9Rqmy&U6fBn?;8 zTWr66-4Kj4yJGIY@b02`zOj=!_@*`0E}_|VX#OE@8{dl$N=gr>cp#4T`m6hZp|dA) z`o5p?G61Ofwa@_23@YDy`BNA#Xe}0DC`cmX&o3ZWiI$$u{kX&ObCwk@ zwta%B?E$CM?dMR99LO$@QM$Mmg2!fq{?9ONk?whuNmb(Xrctd!g$obtrM==B;e%_a zP441i#9IjJF))_iNd4=!4xa+JaKlmTxg`{Sy!><%+ISRX7TH*FSgcMG&ipNq(obU+ zYqJv1HZ3wfh1TSKZ1cN@pTx^tWy?CFtMBhzts_}|U<3B_kIz&uLjxbB3;RC(u3hT7 zv~qj3ol-$ywbXH%J$Ax!i)o99*U6%94!n5x`n2X!c|TY)(1|UYf>y4Q&l~ct(&Y7( zsaMw62JLa#qTt(sdce1#1{q7Ymtq4lBI|m(p!HZz%?ONe@(`VI?w*5hYBLQ88gwJUwqFK z>?fUQa~%(BdR?lBI7>Kbo~w3%reV;~{>eP)g!RY4RK%NClU2m0#0huj!%7hMi4Tc% zqy-PQmtJpWfq=A3^r4LR@sFa-Pe!Ak-XF;J3e}4W zo5)loteIHTy8EnOf`)~gM4ZEBXNj><#REPjjkesvbYbPv)L;%+KQ)+2H>ENLaF%LA zl)M&4?ot_%SQ<|DV0aUit{{hoW#bsM;UX#>{d4{}%4aa{dZ*MnDIea-&bY>6Ooev? z^GBmy8ehVi(GwRoLPf5qCt~c}Y(g0XJv36SMQNuDDWUg%^f$=6ckI{cJyJ31fOY~# z{1eS7jl2)R|InPm<=f!8-1kLDIcEjxFEINr(0h&Z%0JNCtXRqbTX>zZ{x@p-*8$rr z`>!%))D~XGM7Z#l(L=E9;gGe6n(Cu}9Qtr82>lFN7upUF;c@a8p<*vwCi_=8BXeId z4EM9$qsX~?*dX+M@VetqWy}dXJ?L*{VZ=5L^v~>=4_cc_aVRJsVocVe%4``1VCwoU zt5%IV<9If?aP@}q{tUuz_?ni0L(0I!9)}z8(av(+3V?N$b}j@llnjgEV;-KWVs!Ja zF4U#|hK(KpQ$-k)-~8QM@T&yq9s5^d^Z&b;=#{-MOGe?sXeaQp#KAfA9-Geo%8)?I zOv@e#=0@0nN7Ct0`wR@exD*IPVsPsWtP>zvr_R?*`8UrhX6QY8Iwlg-Q=;0^9~BYw z^do~F@i*_~=VfhQM`b$i6g=n1=F^=N&Zro-nS-P8?F%BTF~X=2#J_f>sPhxWix#w5 z1hLPSzk`jQAA7G{uHSuM0`KX4nipwRf7HgB_|s}^8Tmighy%`s3+Ik3M<2ytVV7nJ zQg}Q-&&`G!#wI-;hK)YZic^6#u>8Me9xJM{OgI}m8uP#dMl5cHuqkG=O3=R*VKMvv zS~pbDmx$tBj!$A&v&2Pl5ahcUtpZ=`m)0z;x;^*AVL_6Wnm2m(nSth6ILny-cMvA7 z)YEqyd`$?Wo`Mww;9A9v%T<#Ex8jteT-0mwhRqfGzhI8=T;k$@OG&~h&EXD`WsB5MWM^ZR zW5&iDVCRlh3sM*;Mpvds8GSi|nVI*+pvXg1ICqdHgTe)wFtY>+tWV60vM8#8H zr@wLjze{4cVK~(&I-Iie-t%z7QgAPhs4CLahw-WQJT8!d_gj?6{4-;*m6fGbgQmur zgEi=x71;;Wf=U7Me+dKrj%Y3p>6$*78n|hh5&HW@yA-Fa;J=%&?)OAU1Un z^yo1oy%f*GzF55O6uKPzZi4PdCZSxbBA#&~CpSfP!XbWPkLPt(L%n?GGfB;8Ja_71 zi|YOb;Qd$XaQ&*D;XNaq(hwyOD{l|h2}89y?>_ZyfDTEr<#W+ z&Ap^S#Sv5yg27n*U~IAr{~xTa_^)Khz58yvCh`9*)r#5n9lezj=fUuSSssi(Q93j; zs7<%_gUGj^4BAI`1|Dqq5sMx+GA z+z0!AEb4kd=PVrpv%hxVWkP1cC2)-lRLF^NiYTF1XeCPa={0G4H+<{jy zg6$8_WN?GOBKv-B7*6*FA)#!Lfe05kvmCZ9+DREa^&w^dSV`x{%D=D33<>3fx81m) z9i5g{|CRf{SY7e_S41M8OucwbR-}cX;fE!n_jSOG`RnLwFQ2@-+ncKq=$6=I#+|3&6U!;rp`;C`GR`0ROQ2e_hlR=J&1M+HkJn+0!`!{Rarjgb$>wy^K_ zU(A1>ZVP6Ky6C2P+b=o;SWQv6EeLX7pkMk7H>g?CG-AEkkwTgIn#A*k@A$#>nM~;W zi11gfX%?>Z=O*kdr;q^k^`;?Rfw?@Kx;p+a($S-<-y0-6F+RV z@xe)+F1MkIAu3&9(a0`+Emq5~x&JG7WjTK32fT4$l*{2)00lwM&MR$0YiuEp?;{VQ z8UeLEtvWgjcd7o9rrm3ej-SSZaPfirn&J13BFphB%I|Id4oXl26b&9_|8GHwecBuG zhoJ2Hj`f)m2YJ~$a>WUp9z6~Bw75%7Q`89~|glalV&&q@jM zdMVvrp*4L!oRuPrR4J1^P*qpbZMVIDpLaTa<>>JFKNwyZ8WzE_A9i>mS4R{02uxx> zN}qQZ2wA)~TnU2gRIhxTj!K})-NBR&U_c`OeqdMD&tpQR`jXaH_{WdZS0nvQvF{es z4*JYSTXNMDcYf#1zuo>TZ|>bL>->8uU3l*I0fv(@sq)G`^!w#>R*Qh5vIoK20*~qc zZ*QVrtK|MoZGB(CwNhfj4{9TLj5}Ryz0jnQrCLY8vR0mb4h?M9sE@~6dgd}KRGj_1 zl94iwe0&f1L|^w3zn(EG6B>BjR5dMgJa3py{)y`9+FtqV&gdJWz1l1JiuVDzlowV*D(2Vfxv^Fs29XfqlZGb|Vq5vWYwjb3-Qx-9dH35M9{w|BRDQE9_0BIapIRtZ zx!+`Nak%>riTLz^5JghScdVIhXL=$wIiL3)$v!RZduY@0am-7wLp0P=#2c*G;MQFf zw%jFI@El!eXbc{YcXxk~YE!f!XfV{`FHk zZvG+u?$12tg(r2EQCwe9@Mxn$Ym{wG2(Vf0JnTOs<~3SR%B(G$mRz}eFjn6z@uDnv z>ixPE&t8uE9r(fhDid5B360mHjw~-LJomH6yis9!HgMBMaxuvlGl1icMrIy}aKgr9 zf0h%aJXvifGWLCahJF5Fc0{Sz#0Z+rQkQ6bl^eupe z+w8e!PXTFqAx-6mjCtD`^S4Qz7`e}CfU(Ua{cCe;TaLm_Q~4iO_EXf{(pe2b!o&^V zBm%=aiYF-5-$y-<|&V;cmE<2HVJCG3AGKW?u#udo0Ac5sPBs@h6al#_e$5l{> zT!83DVI3#U`MJ}xd!3Ex*|-U8L1feQN!r8*ToGAx!H$030s5oUsrRp-D-nDyb~{Ny zIsY$M>hU1NisIe8?`=?UTXN1-&RWPw-AAW=o$rpapoxnTHBlCw$XNz08E~4Ouym5$ z28GNNyHz;x@cx!bmGN6p1sm>JW@XrOLK~XIDs8C-KaT**m#kGna!`FZyx#@IXV}p! zEK9y39%HGqb%rqFWk?*p0?CSU*#gPhK8fmP5f8ea%ZfN~G4uW1-^rFi(b^KY7Cc<= zw><>v&UF~H#j=!8s)Y>s(Vp(TDy75~Y~ge#&`JV*Qz!A^j0HNzogtIn-@`ro^W5|C zu4Ey7oYt)O_70iMnYQU6?xhZMi}sUR`FLWrc*DTap8}Xa*XhAZuzgl}jJZ9QA)L#C zWx={Eg0?0-J%me566-;&zdo&|+_&TXc{JN|aw5?GfhQXOtG`jYf!*i*dVK>=2OO{WPkx?zf1LYHRy+l-FdqB0o0o4X zZ51pDhL}dx35QTB@){K5n=$NRv;SjrwH|+im(4hR9q-|0^T!^p#%sSe7#D+Vy?=fB zYyDyTas%I9H>qFyy4kNkJgxtN@y$!{ZBvY2$6lA+)p$JKfADAjMCLhVL*eS?Z-4&h z^?nDiezH=AYS;a!`xC4o#J7R!3cGB>B}rRi!$20uUAbl$&HmS6mY48+S&=jpnm9i` z1Fr&d>0_H)res={=zbP(RUBguWj-D;Hqb*tL&!6C!f`xn$r}#t5C@ni>&cK;%8|iv z&T^iK+>-3XA9M*^vKyRKk}v0 zqQso?UER}WD#t%gFkQ-4RpcTxr};B}al~$vG}|buljdQYOb#6OgB^{_V?&M9Ex8i+ zBihH!{XM%T`NHw2!rY2pau&xN<#GKJUOQpj<&tAfRbx#hro%Wo8`HC~tGn``@Ofb} z)DmTg$y85EF%9|ejD4=5e6YW(bx4=mUUm)_-p0;%4r6ri-#b0kbxU1s_A_0vp71%X zME{_zES6{|Y&5Jt$~k$iF3&ONFyk=p>If|8W1e-lgu;^947*T!ZzzJ=F6J{;!)P+F~DJ>}@t;=11LDWXNA# zXWqr;uj2B5QIlrHAxB4(ri?wtr>>7E`Sf4MIiGsGJRWKTSHs$rNZOrzf*vPB9amH2 zp!Byn=uq2Wt{L)1%9Xb@9>-ii;N%BCdn~wE@5v=atU3R`Aied93tZyW{_+9$In z4vd!9!V-{~?Vc6(2Ik^dYcA|8FmyiOI$zgGlx(rVG7pp6QD)80bmL}aGbuW51}sJc z7JrE;SLb7Vr!LkR0pa={QJmu1#nCC|r}f!5IvdlsvGbG8GuwweaxtOP-;QrT&Zftj z?$O0H>8wnh-`%~OPq4$#K=i2&J;q%08!_j2!S^d@D+ZRAD)sS>T-^uJAU|;WDVIc; zOGr>)gAVP4^zV5k`tQ5~*rz1@qzPir>DZ2m4E0f5KO1)O^EDSCasBk4DwD?5Sgw9_ zHJrP1 zq%10yESq#?>ls-yiO3S|@i2+nUmr=9IVMgqkD1 zlRlz0KE1>7)Q>S^o-jPCe~eLUF8sU;CQj!)MD80v9VO92q(2(gGNX>YkK?StrqOxc zGKbip&0`Wf8y;-nI6Z1m#|HNdaW7kz@8)LaEiRnTzdPqV{tW)}JnnkFS@feWxw-Ib ZF`vwXaS;3m009600|4V$MHt9=0s!1wLFoVh diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.tlg b/impl1/synwork/distcomp/distcomp0/distcomp0.tlg deleted file mode 100644 index af7a7d1..0000000 --- a/impl1/synwork/distcomp/distcomp0/distcomp0.tlg +++ /dev/null @@ -1,221 +0,0 @@ -@N:: Applying property .distcompmodetop with value 1 on module top_tf in library work -@N:: Applying property .distcompnoprune with value 1 on module top_tf in library work -@N:: Applying property .noprune with value 1 on module top_tf in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo_colector in library work -@N:: Applying property .noprune with value 1 on module fifo_colector in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo40_dc in library work -@N:: Applying property .noprune with value 1 on module fifo40_dc in library work -@N:: Applying property .distcompnoprune with value 1 on module trb_adapter in library work -@N:: Applying property .noprune with value 1 on module trb_adapter in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_bundle in library work -@N:: Applying property .noprune with value 1 on module hades_tdc_bundle in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_tdc_channel_raw_out in library work -@N:: Applying property .noprune with value 1 on module hades_tdc_channel_raw_out in library work -@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work -@N:: Applying property .noprune with value 1 on module output_decoder8 in library work -@N:: Applying property .distcompnoprune with value 1 on module hades_LVL1_raw_out in library work -@N:: Applying property .noprune with value 1 on module hades_LVL1_raw_out in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr_short in library work -@N:: Applying property .noprune with value 1 on module tdc4ddr_short in library work -@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work -@N:: Applying property .noprune with value 1 on module pll0 in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc_channel_fifo_out in library work -@N:: Applying property .noprune with value 1 on module tdc_channel_fifo_out in library work -@N:: Applying property .distcompnoprune with value 1 on module trig_inv in library work -@N:: Applying property .noprune with value 1 on module trig_inv in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work -@N:: Applying property .noprune with value 1 on module fifo32dc in library work -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":168:12:168:23|Object fifo_in_data is declared but not assigned. Either assign a value or remove the declaration. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":169:7:169:19|Removing wire fifo_in_valid, as there is no assignment to it. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -@W: CG1340 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":108:51:108:62|Index into variable hit_valid could be out of range ; a simulation mismatch is possible. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":187:37:187:56|Port-width mismatch for port raw_valid_vect. The port definition is 2 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CL134 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Found RAM hitbuffer, depth=4, width=24 -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_0_[23:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_2_[23:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":179:28:179:57|Pruning unused register hitbuffer_3_[23:0]. Make sure that there are no unused intermediate registers. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[9] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf[11] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[2] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit buf_drop[3] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 3 to 2 of buf_drop[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bit 0 of buf_drop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 9 of drop_cmp_buf[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@W: CL265 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":273:2:273:7|Removing unused bit 2 of LVL1_INVALID_TRG_IN_dl[2:0]. Either assign all bits or reduce the width of the signal. -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":795:12:795:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":843:12:843:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":891:12:891:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":947:12:947:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":47:14:47:14|Port-width mismatch for port Reset. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Input RPReset on instance fifo40_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 34 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 35 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 36 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 37 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 38 of data_buffer -@W: CG134 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":38:35:38:45|No assignment to bit 39 of data_buffer -Running optimization stage 1 on fifo_colector ....... -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":54:1:54:6|Pruning unused register test_cnt[31:0]. Make sure that there are no unused intermediate registers. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 34 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 35 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 36 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 37 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 38 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL245 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":40:10:40:20|Bit 39 of input Data of instance fifo40_inst is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":51:7:51:19|Removing wire fifo_in_valid, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":52:13:52:25|Removing wire fifo_out_data, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":54:7:54:19|Removing wire fifo_out_rden, as there is no assignment to it. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":59:12:59:23|Object buf_positive is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":60:12:60:23|Object buf_negative is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":61:6:61:23|Object buf_positive_ready is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":62:6:62:23|Object buf_negative_ready is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on tdc_channel_fifo_out ....... -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":209:18:209:23|Port-width mismatch for port coarse. The port definition is 28 bits, but the actual port connection bit width is 20. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":211:25:211:62|Port-width mismatch for port fifo_data_out. The port definition is 32 bits, but the actual port connection bit width is 24. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":137:23:137:34|Port-width mismatch for port LVL1_offset. The port definition is 12 bits, but the actual port connection bit width is 9. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":199:19:199:19|Input raw_enable on instance fifo_colector_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":194:18:194:30|Port-width mismatch for port out_data. The port definition is 40 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Removing wire hades_raw_valid_vect, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":66:22:66:29|Removing wire tdc_out1, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":67:11:67:18|Removing wire tdc_out2, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":178:13:178:26|Removing wire fifo_data_out1, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":179:13:179:26|Removing wire fifo_data_out2, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":182:21:182:28|Removing wire in_empty, as there is no assignment to it. -@W: CG360 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":183:21:183:27|Removing wire in_data, as there is no assignment to it. -Running optimization stage 1 on top_tf ....... -@W: CL318 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|*Output hades_raw_valid_vect has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. -Running optimization stage 2 on tdc_channel_fifo_out ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[1] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[2] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[3] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[4] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[5] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[6] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[7] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[8] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[14] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[16] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[17] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[18] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[19] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[20] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[21] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[22] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[23] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[25] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[28] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[29] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[30] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Register bit fifo_in_data[31] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 31 to 28 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 25 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 23 to 16 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 14 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bit 10 of fifo_in_data[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Pruning register bits 8 to 0 of fifo_in_data[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":6:10:6:15|Input coarse is unused. -Running optimization stage 2 on fifo32dc ....... -Running optimization stage 2 on top_tf ....... -@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":185:48:185:56|*Input fifo_data[95:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. -Running optimization stage 2 on fifo_colector ....... -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":5:8:5:12|Input reset is unused. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":12:8:12:14|Input discard is unused. -@N: CL159 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":14:8:14:17|Input raw_enable is unused. -Running optimization stage 2 on fifo40_dc ....... -Running optimization stage 2 on CCU2C ....... -Running optimization stage 2 on FD1S3BX ....... -Running optimization stage 2 on FD1S3DX ....... -Running optimization stage 2 on FD1P3DX ....... -Running optimization stage 2 on FD1P3BX ....... -Running optimization stage 2 on PDPW16KD ....... -Running optimization stage 2 on ROM16X1A ....... -Running optimization stage 2 on XOR2 ....... -Running optimization stage 2 on OR2 ....... -Running optimization stage 2 on INV ....... -Running optimization stage 2 on AND2 ....... -Running optimization stage 2 on trb_adapter ....... -@W: CL138 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Removing register 'FEE_DATA_OUT' because it is only assigned 0 or its original value. -Running optimization stage 2 on hades_tdc_bundle ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[10] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Register bit drop_cmp_buf_coarse[11] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Pruning register bits 11 to 10 of drop_cmp_buf_coarse[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -Running optimization stage 2 on hades_tdc_channel_raw_out ....... -Running optimization stage 2 on trig_inv ....... -Running optimization stage 2 on hades_LVL1_raw_out ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Register bit window[8] is always 0. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Pruning register bit 8 of window[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -Running optimization stage 2 on output_decoder8 ....... -@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":252:16:252:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible. -Running optimization stage 2 on tdc4ddr_short ....... -Running optimization stage 2 on pll0 ....... -Running optimization stage 2 on EHXPLLL ....... -Running optimization stage 2 on VLO ....... -Running optimization stage 2 on VHI ....... - -For a summary of runtime and memory usage per design unit, please see file: -========================================================== -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.rt.csv - diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.tlg.db b/impl1/synwork/distcomp/distcomp0/distcomp0.tlg.db deleted file mode 100644 index 8cb5d789bb0d24c46d3c078fec207d8522d3732c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 36864 zcmeHQTWlL=b|$GSB~e^CmK{ZLcanDNO=3%&8QxttktM}Zqgb*eJNBwBGbTsU#N-S^ z4kas=lnnE-SS%KW9|{y(6b1TPpeTyIYzq`c3#1QS6xcqrMW6Ce6h&{?hZZP`0{zZE zyh)moJtQ?&xwn-%e?RLL@J*fnDulcI;qUqI&wF_YcnEk1cnEk1cnEk1cnEk1cnEk1cnEk1 z{EQ=@`v)#wy5u*m>C(fzT#(CUX;UuOuYuW>`I)tOZf)kq;yhP>_uER2+m=e%Eva;c z%PZ=m=3lj2nr}Q()Rvoz_@tuhZ}b86{_t0XeK7n#;r|N%H2kmOe+qv!d~xX0;2#Aq z41Rau$NhiMAL-lb{hgk_>sbx_IB?VdrT?by%QMwo2NMGqjmZzk1G9^KGWGiOmR69b zx1^l($#kKh0H3`4XgV+Hx{{Tr%Sxe`S2h$mN4Lo3OhL<4@^X1<`}H(02x*?R@x2v! zQz`3miF>H%+{4O7CRfsm>*51WDRWYON7^lOkttQvWnDdZ*){rtCH;%8(T`ZsH+n7* z1JWsW0D+&$7K$14#5&Jgb208N7uHw=&J!0Ix3EZALNWi+;6>w`#{Eee67i0PL?V?I zl4%~7SYmIvR8bXmldGtevYg{e^)a%g=;)XYxs(wz>w=h$JecA>kRHigxl)ojeGAq_ zeM`o#5`I*z{&~zna;YHa6bV+y`j?fbcBB$f(N$yq+>4S!=&l@NFG`L`H|6;38>HL! znQn{GE={!WY89+aD>EN(4K2FD<>aEibv=58+fj1(MTnX+ZFM3{Kz`weVy_Buu@e@O ziL{tV^SH#~d&^o$zshKF1*HsYcy^1-;#?8$b0ujfvn}P7TxMI&>Qmg>mTdkEf z{FpWj8f_>P+M!TinV4`{t&-1i4`oh+++eLFshcu)jgvSmwG}M8#Bu{v#&)@^;5%Aa z9}YpW#&@7tH^q1-iY25IX(25Ld#k%DfGaDX(sX4m@tnEd>$xme5j6)P6cziXhb5`B z%k5~TN44eLcy)x0)&T-ijJJ!Uz;+bz6ga{ZoaR&5QWUgp;%7&}G`OK`XcaYch)-$0(^l5lWcMAu7%Mq|NkkrUorN{>l); zIM`X2n?mpr!WgZ{KcnBV7sNQsXJ|x|y4ol}AP9AQY11)pwXG!MN{sU0idsHu$(3GG zHqrmvc1(;8f{BYy95ZofSIbzb4GL>E%-a|5F7nSp<=OzcY}{CKtaq)j2r*K(G+l&v zUE`=bFi~W;pk$||aKV1+(~4s_4>2#sX?{T~SZf+|s#wu8PwNG@X4u2>gwt;KaGicI$z0RLY$Vf#aN{f+pJBn z)F+r><7r;BWMTfjd&`T9i#A;B1;E7EgN~R;#A&QkYuy!h7nkg)7jQT@6BmXjTb@;cu^S^igx3+&+ zpLxCWf5R4Jc;|ob{Lc)BhwK>M`QO&i>Ye|+^S^ig_s;+AIBmT1|1-Q=-ub`oO7PDA z7N$<`{ICAMKL3+vo4fnof{pco&i@zuGrsW9=tSt!$Zrn+&G4O}za6?C{QKbA;9n2E zKk((iZ2zD3zti`Jy?@;E=YcQ%e}$X9R}%qaa2ocTap#siX8g};dDz>v64|jtm~ccp zQ{JJwZTix9JO%UYTUC+Fvxy}C{N5k>_Gl!N%T70bBaTv0nAL>Z1wJ4cHo4h_TO2vN zm^&&9A4VmgXKwkdl3~6A_*F{EwyeVa!yFjo?STIxGR1ML7T%zuR&xa%@g$f&FQRDg zOW>Mr;@zuE^jNnkMf%FK4xh-Z+ymP&e?wh zyo4$4$8;aGW57?4`5p~#?NOPXy(7%pkT?9_2K|>hbs#kSDAw+Scjx$3@y0z{9xiu- z2kHj$!rHhn7!PyyJp5u8c;K0*8m&DK%i;+c5+a4rpiML*R%!u%6uTr)kPnL& z00uLQ3v-#Zm7AG`TbW#bU0{)aN1{UVc@`LDZsl@t;j*w0GX#o-G9gS5u`W`+B|OA` z2_Oy^8Y|25u5t|_M4Cwiw0y#HY12y&Gl&o_QiQLyZ`{~@6-Z82=NXcTj)Ev#;)?4b zl=W~&6C0kVZE}jBJre555M8K6e6iRdGrEjoClQxLkyl&NwxS^hoNc`sxC-so%ZM}5 zw$^a}g4{8DQPM zyf)%WbY7vO#EAlzUtt2L+~{nP`kD=+ZiwAMH`Dq5CI7d4qyHZI?~p$7A0r|!JJSvXw{yn}V;Qga9Syz35~l#X{bmLP2Dt>f*8_lS zrv^a$>j6Oe)BuQmJpf3Z8UWF+1pwER0N^6aGH{kcc5D@hMX?g0L6(h8`j{@4^-NaP z*G0Z-sbhfz7SKt`fTLuX=RXD?V_!_B#aJ3`G`4r^XkrE(h|N`vvLz@x5lL`O$3!6R z8WU_~v1TIX8WU`Gw`L;h8WU`WwPr$ejR`i(Su-KH#sr&bESV_rYz9b`z@W(@LeWDJTz z_fiJw{D023>(bF~{0?(5HoG!>fJuy9(jZQYp zA^pl060sdfglHEr8M@7sq|!bn5sV6CYT|-y%@Z-nYEr2z+kzn^+n9L-L~(R0S-Cp4 z>?z2R1n%n4lBXc`(ht?KTb_a(Q;-il1*t2D@%AFX2pbP*ufdBB(%@S&dgDSmjs=G1 z(^~dBxnxv%6Zz`fa;79px!qGsNq+nNZb*OyGL6jB!xA8{4s|I`U4rzlK!UM0N)a6D z16YaC4X_ehcEYK_pI+z!^QK<|?P2EY_@5f{=ig(x zhCg%cpP*ghHH+4+68=YY}WHUo%{Ilofaxno$H7aNb?83`ZW znPq~v7e0JU@MMeylA0GA!OuwWFrEKj^*!~C{&e(i=r2R*k>4E|8QvTEx1nJ0d%@ws z?+=CselQU3|MmW{zNdZXdY|^5>v`I9F7PyP&i~YZ4j=6L>!64MG3LCITlXQ#mG137bc?*D>hDW#k+)oV_djxryye2XpK*)4<+{87Yi^OZoOTT90k*)w z>SY*H7DYb!{O1 zFsog7I+>%Lar^eNBfTIlj4-_2&CZ;JLCox z4Pk;qd(^a1MmGw76QUJtyFI+Uzh8M2e{{IWUpZLO`hkc`;kNOY;@ZI6x82att?+yNF;4cR5 z_ho;3q6edr*<<}SSD100@u(q1J_!U zb~qMswSxyMXgll47n8Q~#Gp!|6RVET3&)GZHibP@`L8aY)rPg|H+li~Wc3aM+m#e4 zo}~-5=13t1gnZq2DnR>v&_NE3F=S8~(@CwfJ~)~xb*K}p#kJ}Za6|P>-RH)7Tlt3J zXG;OanJvO1=X_r&Mi2yosTK*5%`HV^7+!vNem*ldvo@1iy0dl}sc=~d4<b% z4fODYTCwrsXGHXR7l@)}0~y?rZeoVv<&<((DzSpfX7*-{V*UUW$5WkCjDaATy6Zx+ zpueN?8RdPp;@)H$5Q{t406rN@MMy%w?UdXA3vDU>;Ev=3Rx@+_;_lE~%x9AJj-oBD+^ex>j2cNh` z-_qki{(pZM_5Zx8erMXM;W6hS;3424;3424;3424;3424;3424;34pW5iqV9=0h=W zPmqHv)@Byk;fG?rc}F#ir&Do9=CPuO>NcK`xt<`02R%r;B%|1ftY&eaghwdrc&5E+ Wq`!LA^4YtMYU@&NTgl?V_5TMMMofnQ diff --git a/impl1/synwork/distcomp/distcomp0/distcomp0.xmr b/impl1/synwork/distcomp/distcomp0/distcomp0.xmr deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp0/modulechange.db b/impl1/synwork/distcomp/distcomp0/modulechange.db deleted file mode 100644 index 8cfb8423b12b0ded02ae2ccb7e837e932a0bbb5a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeI2O>7fK6vt~%!YVgKMAZZ#P0YXJZ6$(jP6$!IhkL^izz02;} z5L#O0&zoRD zw(|UT?e~8(zj=P+wR8N{Bh)8q&UP)`SNqTkBuQvQRS}ZjK?p_IU-i~-k2!L1#2%#@ z{|PSBNUixb&YqPMlL%i-TuMyhZBKYHoCX3w00;m9AOHk_01yBIKmZ5;fv1hYF}bO2 z`*w-=`jkm5J6keImN=xC^&UEi95^;MIx(hBjP5@&ratu4j#myJRB6%gRu5I2u5*n_ zTW6;7+wnDT zw#Wu)P=8h%-`U%f9!&MTu=DuQw8lP=XyrmyD_L&F&>d=}*wNzQjtH8IhtKJlX2#Wv zS=-VcxT$jHqdR+t+htU$OKFg642tOf;b^_lJv_QcM0e=y*Mzw};gj=~OmkLeYHm0$O2~ z#j^tTQsoo(w*Eb^fyIWcprS|fMUoW-#1ijrlaU=V*7LLJ^zQy3w0E71^5H{+u;H~b zdMj*L(eW|`of&5)9|-JT6Mo3WlEt7KLFmBh@T5%J(0ytbQ zlUS~fd)6ouH_+K1XF8GPjE7Y|sdPXF=wK_8i7rQmU0CIGg9PJ=Uq&%Lo}o?hz$Q^9 zVK)2%@x7*Xrm(RicF z7&g0t^=-C9r@s5}=a-)2WS8i6HIv{H{XLm#*AyNT+H(HJP;(uJTsGl?%K#?ro|&-kzFf6so;-L>3sA+@0BWL>;YQ5UQPH#`8;4LLvFp zP-D2+n)-Kj5Met@3TxS*YPbJsRe8Yd6 zm+)PL@3Q+J_yhbNPT?JR3*L;s#+UH-_zu2>f5A8LkN9ou;c2YnH}E(wor7|8N5WKmZ5;0U!VbfB+Bx v0zd!=00AHX1fF36aQ*)bFD^_C2mk>f00e*l5C8%|00;m9AOHk_K$XD1U?DO_ diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10149.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10278.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10329.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10384.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1041.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10441.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10548.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P10663.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1085.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11159.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1118.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11471.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11573.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11683.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P11697.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12242.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12734.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12947.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P12955.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13712.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P13926.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14472.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14698.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P14723.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15017.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15137.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15585.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15714.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P15873.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16193.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P16594.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17421.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P1747.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17661.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17826.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P17995.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19179.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19324.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19451.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19542.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P19750.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20478.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20528.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2072.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20829.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P20832.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21244.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P21323.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2210.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22101.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22229.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2236.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22683.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P22994.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23089.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23154.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P23975.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24037.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P24622.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25082.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25289.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P25480.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26115.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26179.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26304.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P26500.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27019.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27327.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27704.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27738.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P27916.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2800.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28001.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28127.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P28918.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P2924.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29523.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29704.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29707.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P29716.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30229.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30471.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30618.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30660.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30679.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P30784.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31220.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P31325.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32054.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3221.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3262.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P32631.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33018.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33181.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33323.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33390.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P33965.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34643.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34730.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34787.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P34833.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35092.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35253.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35422.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35589.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P35836.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3605.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36185.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36415.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36564.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P36760.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P3677.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37030.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37437.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37847.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P37886.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38080.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P38749.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P39844.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40254.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40340.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P40619.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41319.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41545.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P41683.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P42085.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4325.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4382.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P43927.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44365.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P44737.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P451.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P45193.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P458.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4590.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46525.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46526.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4659.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML deleted file mode 100644 index a473cbf..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46715.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc4ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc4ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P46784.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P4729.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47461.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47661.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47758.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47836.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P47943.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48181.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48270.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48304.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48423.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML deleted file mode 100644 index 6525883..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48452.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48600.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P48924.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49177.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML deleted file mode 100644 index a473cbf..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49240.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc4ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc4ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML deleted file mode 100644 index 6525883..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49670.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49765.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P49964.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50294.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50614.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P50767.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51098.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51455.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P51506.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52395.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML deleted file mode 100644 index 6525883..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P52914.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53068.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53162.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML deleted file mode 100644 index 6525883..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53247.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53374.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53687.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P53937.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54302.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54351.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54510.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P54931.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML deleted file mode 100644 index f9f1187..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55318.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5557.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML deleted file mode 100644 index 077d6c7..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55710.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P55796.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56168.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P56339.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57010.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57046.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57112.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5729.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57445.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P57870.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58183.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58742.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML deleted file mode 100644 index 395cead..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58842.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname tdc8ddr -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top tdc8ddr -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P58858.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59059.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59151.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML deleted file mode 100644 index b862748..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P59853.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P5997.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60104.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60487.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60777.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P60992.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61034.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML deleted file mode 100644 index 6525883..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P61156.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62598.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62664.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P62788.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63146.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63442.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML deleted file mode 100644 index 4211801..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63702.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63742.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML deleted file mode 100644 index 15565b0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P63779.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64098.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6440.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64534.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P64797.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML deleted file mode 100644 index 1c89075..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P65185.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6535.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P6944.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML deleted file mode 100644 index 0a30307..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7356.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7498.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P7969.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML deleted file mode 100644 index 4226b0d..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8262.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P8319.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML deleted file mode 100644 index 69dbbb0..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P9001.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML deleted file mode 100644 index 367ca10..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T0P951.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top_tf -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top_tf -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v -lib work /home/hadaq/mmichalek/lattice/simplified/top2.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P10357.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11069.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11184.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11339.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P11871.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P12447.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13737.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13855.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P13908.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14207.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14481.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P14525.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P15089.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1553.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16032.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P16159.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17025.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17528.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P17685.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1811.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1815.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P1816.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18740.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P18777.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P19659.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21221.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P21342.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22066.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P22949.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P23803.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24022.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24138.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24515.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24554.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24717.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P24926.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25101.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P25372.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P26023.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27368.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P2789.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P27961.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28205.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28730.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28831.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P28916.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29257.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P29449.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P30679.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31655.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P31773.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3318.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33223.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33269.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P33488.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P34176.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35393.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35493.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P35891.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36431.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36567.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P36968.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37025.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37272.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P3730.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37316.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P37711.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38022.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38264.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38281.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38532.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38581.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38588.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P38636.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P39927.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40534.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40681.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P40902.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41215.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41268.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41682.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P41956.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42114.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42430.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P42943.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43492.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P43796.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P44243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45555.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4568.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P45916.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46449.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P46932.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47032.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47147.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47440.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P47660.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P4769.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49489.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P49913.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50169.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50820.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50866.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P50987.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51115.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51253.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51276.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P51676.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52823.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P52884.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5314.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53189.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P53679.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54450.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P54711.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55086.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P55200.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56321.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56637.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P56890.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P5696.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P57194.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58438.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P58948.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59000.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P59193.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60160.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60506.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P60927.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61602.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P61813.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62596.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P62978.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63085.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6329.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63355.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63396.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P63760.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64169.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P64713.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P6484.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65366.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P65389.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P7786.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8240.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8636.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P8653.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9058.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9311.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9412.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9564.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9837.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML b/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML deleted file mode 100644 index c070e80..0000000 --- a/impl1/synwork/distcomp/distcomp0/synwork/syndist/_CMD_W0T1P9890.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.cdc -mixedhdl -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -noobf -lite -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -ignore_undefined_lib -top work.Uart_top.uart_top_a -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl b/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl deleted file mode 100644 index a4b3e47..0000000 --- a/impl1/synwork/distcomp/distcomp1/_info_mixed_hdl +++ /dev/null @@ -1,154 +0,0 @@ -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top -Uart_top diff --git a/impl1/synwork/distcomp/distcomp1/_slc_mhdlc b/impl1/synwork/distcomp/distcomp1/_slc_mhdlc deleted file mode 100644 index 3c82fa4..0000000 --- a/impl1/synwork/distcomp/distcomp1/_slc_mhdlc +++ /dev/null @@ -1,12 +0,0 @@ -pll0 -pll1 -pll8 -pll_random -async_testgen -tdc4ddr -output_decoder8 -fifo32dc -UART_VerilogWrapper_TOP -tdc_channel -two_ch_diff -top diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo b/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo1 b/impl1/synwork/distcomp/distcomp1/distcomp1.SideInfo1 deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.cdc b/impl1/synwork/distcomp/distcomp1/distcomp1.cdc deleted file mode 100644 index f465fa8..0000000 --- a/impl1/synwork/distcomp/distcomp1/distcomp1.cdc +++ /dev/null @@ -1,29 +0,0 @@ -define_directive {v:work.Uart_top.uart_top_a} {syn_black_box} {1} -define_directive {v:work.Uart_top.uart_top_a} {.distcomp_black_box} {1} -define_directive {v:work.Uart_top.uart_top_a} {.noprune} {1} -define_directive {v:work.Uart_top.uart_top_a} {.distcompnoprune} {1} -define_directive {v:work.top} {.noprune} {1} -define_directive {v:work.top} {.distcompnoprune} {1} -define_directive {v:work.two_ch_diff} {.noprune} {1} -define_directive {v:work.two_ch_diff} {.distcompnoprune} {1} -define_directive {v:work.UART_VerilogWrapper_TOP} {.noprune} {1} -define_directive {v:work.UART_VerilogWrapper_TOP} {.distcompnoprune} {1} -define_directive {v:work.tdc_channel} {.noprune} {1} -define_directive {v:work.tdc_channel} {.distcompnoprune} {1} -define_directive {v:work.fifo32dc} {.noprune} {1} -define_directive {v:work.fifo32dc} {.distcompnoprune} {1} -define_directive {v:work.output_decoder8} {.noprune} {1} -define_directive {v:work.output_decoder8} {.distcompnoprune} {1} -define_directive {v:work.tdc4ddr} {.noprune} {1} -define_directive {v:work.tdc4ddr} {.distcompnoprune} {1} -define_directive {v:work.async_testgen} {.noprune} {1} -define_directive {v:work.async_testgen} {.distcompnoprune} {1} -define_directive {v:work.pll_random} {.noprune} {1} -define_directive {v:work.pll_random} {.distcompnoprune} {1} -define_directive {v:work.pll8} {.noprune} {1} -define_directive {v:work.pll8} {.distcompnoprune} {1} -define_directive {v:work.pll1} {.noprune} {1} -define_directive {v:work.pll1} {.distcompnoprune} {1} -define_directive {v:work.pll0} {.noprune} {1} -define_directive {v:work.pll0} {.distcompnoprune} {1} -define_directive {v:work.top} {.distcompmodetop} {1} diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.log b/impl1/synwork/distcomp/distcomp1/distcomp1.log deleted file mode 100644 index 693a568..0000000 --- a/impl1/synwork/distcomp/distcomp1/distcomp1.log +++ /dev/null @@ -1,262 +0,0 @@ -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/top.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules.v" (library work) -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":247:44:247:55|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":248:53:248:64|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":249:52:249:63|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":254:46:254:57|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":255:57:255:68|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":256:56:256:67|Ignoring property syn_preserve -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":424:7:424:9|Net wrn is not declared. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":425:7:425:10|Net adsn is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":85:44:85:55|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":86:53:86:64|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":87:52:87:63|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:46:90:57|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":91:57:91:68|Ignoring property syn_preserve -@W: CS133 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":92:56:92:67|Ignoring property syn_preserve -Verilog syntax check successful! - -Compiler output is up to date. No re-compile necessary - -@W::Specified module not found for constraint application: work.Uart_top.uart_top_a -@N:: Applying property .distcompmodetop with value 1 on module top in library work -@N:: Applying property .distcompnoprune with value 1 on module top in library work -@N:: Applying property .noprune with value 1 on module top in library work -@N:: Applying property .distcompnoprune with value 1 on module two_ch_diff in library work -@N:: Applying property .noprune with value 1 on module two_ch_diff in library work -@N:: Applying property .distcompnoprune with value 1 on module UART_VerilogWrapper_TOP in library work -@N:: Applying property .noprune with value 1 on module UART_VerilogWrapper_TOP in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc_channel in library work -@N:: Applying property .noprune with value 1 on module tdc_channel in library work -@N:: Applying property .distcompnoprune with value 1 on module fifo32dc in library work -@N:: Applying property .noprune with value 1 on module fifo32dc in library work -@N:: Applying property .distcompnoprune with value 1 on module output_decoder8 in library work -@N:: Applying property .noprune with value 1 on module output_decoder8 in library work -@N:: Applying property .distcompnoprune with value 1 on module tdc4ddr in library work -@N:: Applying property .noprune with value 1 on module tdc4ddr in library work -@N:: Applying property .distcompnoprune with value 1 on module async_testgen in library work -@N:: Applying property .noprune with value 1 on module async_testgen in library work -@N:: Applying property .distcompnoprune with value 1 on module pll_random in library work -@N:: Applying property .noprune with value 1 on module pll_random in library work -@N:: Applying property .distcompnoprune with value 1 on module pll8 in library work -@N:: Applying property .noprune with value 1 on module pll8 in library work -@N:: Applying property .distcompnoprune with value 1 on module pll1 in library work -@N:: Applying property .noprune with value 1 on module pll1 in library work -@N:: Applying property .distcompnoprune with value 1 on module pll0 in library work -@N:: Applying property .noprune with value 1 on module pll0 in library work -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":8:7:8:10|Synthesizing module pll1 in library work. -Running optimization stage 1 on pll1 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":8:7:8:10|Synthesizing module pll8 in library work. -Running optimization stage 1 on pll8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":8:7:8:16|Synthesizing module pll_random in library work. -Running optimization stage 1 on pll_random ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":194:7:194:19|Synthesizing module async_testgen in library work. -Running optimization stage 1 on async_testgen ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":218:7:218:13|Synthesizing module tdc4ddr in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":238:12:238:19|Object in_up_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":239:12:239:21|Object in_down_dl is declared but not assigned. Either assign a value or remove the declaration. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":228:10:228:27|Object in_clk_down_synced is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on tdc4ddr ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":263:7:263:21|Synthesizing module output_decoder8 in library work. -@W: CG133 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|Object raw_latched is declared but not assigned. Either assign a value or remove the declaration. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":759:12:759:12|Input CIN on instance w_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":807:12:807:12|Input CIN on instance r_gctr_cia is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":855:12:855:12|Input CIN on instance empty_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":911:12:911:12|Input CIN on instance full_cmp_ci_a is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on fifo32dc ....... -@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Could not find module with name uart_top, performing a case compare ... - -@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Found module with name Uart_top, attempting to match ... - -@N: CG364 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":47:7:47:29|Synthesizing module UART_VerilogWrapper_TOP in library work. -@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ... - -@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ... - -@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ... - -@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ... - -@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ... - -@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ... - -@W: CG309 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Could not find module with name uart_top, performing a case compare ... - -@W: CG310 :"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":103:14:103:18|Found module with name Uart_top, attempting to match ... - -Running optimization stage 1 on UART_VerilogWrapper_TOP ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":4:7:4:17|Synthesizing module tdc_channel in library work. -@W: CG296 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":50:10:50:21|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. -@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":51:5:51:9|Referenced variable reset is not in sensitivity list. -@W: CG290 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":54:23:54:28|Referenced variable s_data is not in sensitivity list. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":88:13:88:18|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 3. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":111:5:111:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input SIN on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DCDn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input CTSn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input DSRn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":106:24:106:51|Input RIn on instance UART_VerilogWrapper_TO_inst2 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on tdc_channel ....... -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":366:7:366:17|Synthesizing module two_ch_diff in library work. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":475:13:475:19|Port-width mismatch for port Data. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":496:5:496:5|Port-width mismatch for port A. The port definition is 3 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input SIN on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DCDn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input CTSn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input DSRn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -@W: CG781 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":493:24:493:50|Input RIn on instance UART_VerilogWrapper_TO_inst is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. -Running optimization stage 1 on two_ch_diff ....... -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register dbg_cnt[31:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning unused register fifo_read. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in0_dl1[3:0]. Make sure that there are no unused intermediate registers. -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":435:1:435:6|Pruning unused register in1_dl1[3:0]. Make sure that there are no unused intermediate registers. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top.v":1:7:1:9|Synthesizing module top in library work. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":89:20:89:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port. -@W: CS263 :"/home/hadaq/mmichalek/lattice/simplified/top.v":101:20:101:30|Port-width mismatch for port dec_out. The port definition is 3 bits, but the actual port connection bit width is 4. Adjust either the definition or the instantiation of this port. -Running optimization stage 1 on top ....... -Running optimization stage 2 on top ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[16] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[17] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[18] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[19] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[20] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[21] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[22] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[23] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[24] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[25] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[26] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[27] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[28] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[29] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[30] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Register bit pulse_cnt[31] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/top.v":128:0:128:5|Pruning register bits 31 to 16 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -Running optimization stage 2 on two_ch_diff ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Register bit uart_quad_cnt[2] is always 0. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":507:4:507:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 3 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning register bit 1 of lost[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL257 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Register bit 0 always 0, optimizing ... -@W: CL169 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":448:1:448:6|Pruning unused register lost[0]. Make sure that there are no unused intermediate registers. -@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":500:13:500:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. -Running optimization stage 2 on tdc_channel ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[0] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Register bit uart_quad_cnt[2] is always 0. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 2 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL260 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":124:4:124:9|Pruning register bit 0 of uart_quad_cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. -@W: CL156 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":115:13:115:15|*Input rdn to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. -Running optimization stage 2 on UART_VerilogWrapper_TOP ....... -Running optimization stage 2 on fifo32dc ....... -Running optimization stage 2 on CCU2C ....... -Running optimization stage 2 on FD1S3BX ....... -Running optimization stage 2 on FD1S3DX ....... -Running optimization stage 2 on FD1P3DX ....... -Running optimization stage 2 on FD1P3BX ....... -Running optimization stage 2 on PDPW16KD ....... -Running optimization stage 2 on ROM16X1A ....... -Running optimization stage 2 on XOR2 ....... -Running optimization stage 2 on OR2 ....... -Running optimization stage 2 on INV ....... -Running optimization stage 2 on AND2 ....... -Running optimization stage 2 on output_decoder8 ....... -@A: CL153 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":279:16:279:26|*Unassigned bits of raw_latched[7:0] are referenced and tied to 0 -- simulation mismatch possible. -Running optimization stage 2 on tdc4ddr ....... -Running optimization stage 2 on async_testgen ....... -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[14] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[15] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[16] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[17] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[18] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[19] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[20] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[21] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[22] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[23] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[24] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[25] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[26] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[27] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[28] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[29] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[30] is always 0. -@N: CL189 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Register bit pulse_cnt[31] is always 0. -@W: CL279 :"/home/hadaq/mmichalek/lattice/simplified/modules.v":204:1:204:6|Pruning register bits 31 to 14 of pulse_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. -Running optimization stage 2 on pll_random ....... -Running optimization stage 2 on pll8 ....... -Running optimization stage 2 on pll1 ....... -Running optimization stage 2 on pll0 ....... -Running optimization stage 2 on EHXPLLL ....... -Running optimization stage 2 on VLO ....... -Running optimization stage 2 on VHI ....... - -For a summary of runtime and memory usage per design unit, please see file: -========================================================== -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.rt.csv - - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 73MB) - - -Process completed successfully. -# Tue Jan 26 20:17:05 2021 - -###########################################################] diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.log.db b/impl1/synwork/distcomp/distcomp1/distcomp1.log.db deleted file mode 100644 index 73deeb36b8b11e11bfd8753514495b6f1197b004..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 32768 zcmeHQYit}>72dVI-nG~EHl)RA)4-5Y(uBl2Gy9%UTGw_GQzv$8Ck>de9q)|oiFao< zGqbz(#!i_P0#u<2AwUTJM1T-KkdQ!?kPs3oum0c{4+$hB#IGW?szeb5S_wGk?yh&8 z&N$x3ti57Z_Pu`0`aJHv=brPObFUXJ&q%sRtte`S*Qt=}K9}3=dXl1CE>|yn`rxzr za>EyW)o-B3@9*{Mb&cKsmtlCy9eBY7AI{6sfTICN1C9n94LBNbG~j5!(SV}?M+1%q z91Z-RYe08 zno3LZdhNT)Befr_OLE=AS$L-;>nA;+bx+_`)V(k8PT;M;-vX}(ULBhB|JuJe_@_Z( z;PnCB_m=ND@0;FS|G)Zgd0z7@_x-u=(O#+N`|iKH6RxcmhRsME^NkvZjf+QnCeAaV z(DC4!k`aSzyujZKW-=1Ul@`~7XUzA*OT?Eh#7kXwsCVQG%FC^QtIN%Q>Br6`kTWO!BklDxWg+=x9)c%N>K_js9i=n{3j=dyNko;cdYT7Rf( zwftkSPL@*Tn??o1Fw!#9F2m=e)f|)R5f!8+VR8ki;eN~jL7#V&5 z7y-a|lrw6-LatR95v16ylK(l>&$XIPqvkI{)U z3v)~mCUh{JONp``6jRwqE)!Wr;!HFV#Tkj6#j2RPaBXg8X2ybx&HI3fL)W(lzZoWC zQ3iOx)_hT1otd?w9%uvg2+-zY&{|NxFl|9SKZ4Y!kM>S1G~@KJH~b`LkbYH`uBuw>x_y9SnR!P5r9FreVWL?Vr>+d^L(2#0aqvXO8j3%AhQI^l2v z7cL8311q=C(+0wET)AvG-pJA|K=9w{XIcDTJKI;>v;DL+On?!9bUc~@^EELyIrj_`eR|SrLiC(yorxHz09FMm!kmfu*^5l{ z8Z&Oe#O)6u54A#|W)u-8JYWm?W3vjWYqRsL1^vxOfqsj%C{f7iLXiNp=6>fc)IZod z^-vVOUTn>&PhYxfCHo^lJM@x8 zkYk39jaG|jRlbk}w=J~>Rljys0Q)|GBbVFWPUOsJ;^k-v29AXmYM0HFr{r|- zV3SY*p$MXCRn2CMQ$&x~Thb#77MJXEFHu z2=Coj436>tVb`x*fr*i?4*zlZ^pN6z+3y*=Ht>7j8@^@lZ~I^I{Iu`o-kwva;oZnY4gW0po+5fsTG2xsLs|~o`0jd`KxQXrC&Kp>g!-H*hmx6ZZnG z&HYlS*JMK+w(-q*aYa-`;`+f^LkUkOQd&{~72v?*aXL8oqKUEwlOYc$2;dNmRyQ)n zz>~m^zt9ppI6os;=WoUg7Pjg=vQNthX{SZFLg{V| z5G*-I(C_LqG92n0qb~C6@N^Dfa6X-eI>UEqS3`wX&u@}3q!2Wh8p)pR-jzvBu_jl4MG z9eUgU=HNdD{^|R-_nrR#^iO!c(D$3ZBfa15`G)(8?jx={oe%%>OE3|{OZprs?m`whX*03L2m6&EY7CjV(3(>oKu>dM20bjIsWSj6~!|n59Oa0eC72f7m z5eGn+=Ai9zMX1m8k3L^JD!W&hxjG>LV759T3y)a&Z?UVO`~bO{V+M}-HsvXYLl9MR z*hV+!)Er)%0i_l>4SZO&x)>#yfx9l4r4UD7ulJ4hHMoxyqCa$#;Zs(s?}S@RL^UG{ z5Dtple@3fweq&cU#W~$(&clm@^YgIwo7Q;*svzL79kdBconxXrsfs+@e^LuZnpb#y zfv}B999!8ImRE_z4l!+;E5&(W{cwropBkz?szXo02|Vt{VHcqrhmCRb*`NBOTbGIO zEn((n!Z(5%@1yi{_DJ6dXuOZo&)Oq>Bbf32NngBV&$4d-GTt}gOP-4$e2a*281DUm zn*y-i-N!t@i1FYInFK8%#^D%vI3cJvh7R`I-LUiaW5)6J`PxR`(-7|*Y6&q6MX>}1 zTPxJCpa5!^6r`0EE3Y&BF`S!5OCAt|n=!m^s<^MU(DzBWP)e|MOM^Z!r!U-8ck{$cRhfxix9eV_KZy`}yydA`~Ab1QC7$D{AH*>r|Tus(2M&HsqMV>YzZ`{y`;R+Ie zJJM_t126(~SfPt-o+{VLs{&*e6iR#!?+(&1U$<1PnZHi0@ijk{00Z^K@>K_x`~v^R zy-VlE$sLR&2ZE_Xisbbw_49Sn9IKM0HPK3N5r)e+AP&VVIV>$gTG8~SHie*DH*tb2 zA20LyGzEo{Ql@+r-Hx*$LKbya!YtPe8*MHFXr{C6pdAr321kr& ztsJ^fSMsuzJX|?(tBW#btd_+!J})V7NhvvJQOWA!(F}6d1uoqr7n#D4bm>HRfnP_D+%}{|Iqe-KfJ8j>74QnRT0eRU2 zBkxwa<=v!ybaxnwodasVnXPwL~6=vX%=RS*eq>Vqm`FH-L~d4LX4TykYBT%uIc#ZSM8?DCQRjBv7K(* zl&)wyUGsdEU^`vYd{sVWJKcz>o|kQ>8#blO+fFxRO7~gY>6&g2`K0Z1&F$5vY^Q5( zuddromoc|jpR}E>slCGZf3)W(E{OiA;m}at|F-|Ozi05XgM$Mv4jl4***EI_y7yTB zo&HBW-|?L6`(9tL_XqH}^Kvw>{~9oE8bc&jXxw|OgMwHZ&_bvb2-l$lrXFPYKzNWv z1Ftm>G+q*8A@YuZq250>+lGn;-fe6@aZ}q|H1L9B+liYyltshW5#pv+x@dSiLfq7~ zEE;(8vHfZ{^)HJC-hOO9aZ@L=Xy6UV_7gYtG>Zn_f^0u=Q+Kmy;7!Q(6F2oaiw53? zY(H^R$Fpd-Izrss!ad&!+U6c;@peaOo7=aoj?gwYZ<`&VZEoFeb%eILaVvI&wyAA1 zxDD{z4jY#r#FDW{bEnquz<=%B|EVi-^}l+RlTd*6)m;Lx6oZ;EQb|~M;0FGu4W+}s z6C(*L>dYAm3W%*Qd*X#W{1-B~YU{>x$b6}#{2RlN!U579==@uzKs@Z0vJdsiRx^y2 QI!M`vdE+M!}2oSV!C%C)2LxQ`@ZF0`coSBok z_xmo-`-5&+yXvi~z4oqMwTQyuUi|ujR8Uq{rljm=kdUVL9V?_d`H;+2sD)Je{Ku!K zb$hv0h+n@oC1}cSaAJI1xp|G*v=96e`kB?r)lg4m;x*)Jy2knZUTOSwvKBq=Je;kb zBRdTMHw%rpSS5yfsl%|#p^WTk;MdM^h!Tw|v%qiab2Z!Tq4ruE-{AQ^Syib($Ac&v5fY1Yh5*9g7q@3 z1wFpM%7i8);Wf)0i;>ZX%#g1kArPM$L_4vQE0?E)wqND9qwU?>2>~VZaH`+e_V$-mKFN3u*0RW{hum3&QL%Ogs zIwPs1h20sc1^B|;bQ|LXpyjpnp=*A~fL}Z<#e$7Ot{+a(+_#@^URn%)wsCmjci86h z^#$4vV}0QDcdafJ!~m^BU+5GVsM5lcwpl)0IZbwq2N@^;dO`mj=erJ6fIkXRdfmv7 zCs$*=P8xwrM!>1DXzFm;+k9^k!08W%;nT3m^R}|k>KMEg#>3m-v33{k{ZthmiHB9Z zvJ6j^&1!PY+wJWQMOTE6l!|YWBVYto}1xe+w z3;ojzTz&X?0VF?pR4o^%=aZLcje&~81wjIl>rnfNmWHm13&VyvU*55t+sT8_S`egN zcan2xN#rBTn=v&Jj?oE$luYMi^XbFO2WKdA+Mdl}O4A&7>X$aRp9r7}Ym*FHO^Sv! zg9Sgf2{yolal0w@l;I^2?@ee$;_Z?>o+@noA1x(1QPZOlr}k0&1w? zka$-wobmXa`Oed&I&G+o&!lxoufFbvCsRAUv9Is2)O4WuENyGK0b!hNSawcATh7bV z(caF*!}(r?TBNd1JfYM3P~-XS=0|2I(gH2{# zFN}iUY&VtbNe8JEn!t|Cb99#Bg4N;TZgH$b160Omv8uze2picpT3 z-v%RgD;@-L@@Y{T^AiGXH+zxl<0@-=$2}9*VokEvgS5k)u&v()FGZzF;rl(b3zX0`ztEBD1L6dVw5;sg9&Mv5tupP`KVaRyPiD`gsI3`MH<^ZRy7*DzCSg8B{8J ztU{spLC0|f1SU!hOEs!i<(RAMg-|kNAd_M6f%D1kkKE7DKc7RKlP$s(V5yH=y`kpbhi!e@6%I26cd6! zBSyg06-}6(EeHxxK_}sRWo(-f=V+UVtrUQuqUx!|pz&&THR0%R5pL$~;m}~=j){zA zd1-kDsiSI8MI;|zM=n~i(%e!TnTa8iE`sBW?8fMk;pp6>jE$fDy$z|Z+U5|EFH`lu z2_uUU(=nB=)ack^hV8(CUJNzOe_&!CmE-a)3Ztqiqv^Av>)xhH3gh`f$F`2M&s=gj z6vvcDE}|8E+5TBOQSQ}=w{2G+WQ7U4_rC^M7SQ}Wz!8m}_kS5+5`+%$06*Nl&P^`( z0LN<3l=OWM*okJBlS9s!9HG)_`Q)9Oy3*E`d~|q^xPrA@yj@{ehM-wYqm>24Qd79a z^@W%3T^lgH(c`+^@}Q@oP3etUfx(w4f39fiVJ`ad%^=)^CDgDh*lapOjaUsR334Z+ zSeqT2RHs%ZOSkniQZ4{s;|AB^8?{)xQVg%oARQ&FWQWBy1*uOC$FDW}9|P>DEFHeV ziNY)E9VoY5-jWmo1!V65kJTBF=9NKZL&>u&>s5XViNEh@}JIuY-*sJSEoe-j=`eX`t?`zd7Xp*B8 zc<4puz}M{+M+(^$#!RrD65y5x1@bNyC-fs_&%915qJB%xKsU$vl`V{=5Zm!OPp@FE zzQWBr(FL;s!nurOoMc+RI-ZXu*vUG$X`1L1aoV(aDw@u9Lz@DnTtg8F zdKpRYYb6RzQ+(6tlh_rsJ{AdFWEf1=z;fIYS2eXfybdu}A%Ig- z$iCrBx;uxM(3_ywNf-)gthOB_%W6M;iRTr=K0!IC3lfskVYX5; z=L*syWtGQ#ji$*hk}rd8ob2`{u)NeuZ86en-@niq`9Snz)9-~ved6w|+_2QbDpbI_soJT?mMfl*l9@-2Y>kK)t;czanS|$# zICgp$&LpFTq-Wr7kom^ZqV%&zlp(^x{1O^Qq*>i5@m}TS41SK?_W8=RTzJje@_FK| z@~Bta=_;~U$jNpoi9_P)3y$RD2=T+Ea;|Y1jrhTRzIwrAN8UI>3Rg?(?6o+P>@L}U zO{_jnv@+D%+@B(taN#UdOb6z(k3XY0^2*=Kvwqpc^x3Sus{3ejBlXcKEp5Lvt1~S$ zuxY|SH1dM)z+qTs-RGQyNp_z{A_0z4X3}hMDs8aa|8Ni|`4mmjB`mSG>EX5WU5@Mh z*M(+>`_^rGrPg*AUb`1D{eu0rcd_T#(i<}F0yl#+)r+IpVu z36kldY(@=WXyu&$!R1CnDxyEvxP5dHh+x6eyixn-@b)>k-tL!^x70G<&L=Ys*Bg(@ zzJ?cbNmM`0x+vb!EQ_Yu)dt@_Eg|7PRz9|FNFM7SeNTyALB(=dJcd_o^1%|V@sQJ6*9i>0^-ULH%dj_>AT&@W8MqZSttId`{HXs}UbY|z5Ev9h z4uBR6%mW1h071}NDfPdaQvbi0QvanuTDXA2f{a{b^cM8=e|s-RmNCc)w>3ATLE^eA2Xd?D z3O?Bmu{2r7dkcEv|9lHs4kqvv0kQ>gz)P+kkcW~|G&w&q`=)?%`Fj^#>ukr&90LWV zutXbGEpcU>WM2xx-KFFBYhNS)lr#Sg=KS_TKUG{{HdNa^^mW3Tc2}8neH>WV$^9v*bf@Jx`c_ z#H&TE^>8oV(+5BMw0P!pfPIN%eBGbJ_%8#@|M1?RWH9}Lhf*u(?~C)7_kuh2Pw)LV zJnV$K40tJk4Y)%K{?{>(sfSJunsx{NV?F-M#5hYINh5U z&u;d^NDW6lqhwn_-}^Tjokmnpprmx^-&CmB{==!_6r?RS z7*U${R0Cv?4zt_agyF|UK(Sf=WWC?F&111~2b`=JyAE5+idmO<53F}ip$syXgC{dE z+&{rZhm4@Q4Hvdf2ct)(-jB}A41I_T;sRFcbH{mXyt}*2`ssaTn-I~Y03i<-<(J|( z3YjPU?L$nY$)=QvzB=K7H)WOeXzW{O6``AQUvWR8HmmB~jRb+7v-AnW^+54aSmMsY z{HCv$yf$~YOA;m@E4GFcN`1%uAal7JWe^}^V+zlfG#OQwY=I%WO*Ut*FNzu>TM}^8 zR1d!=M6$eCn%{+x0wQjye>x2nAad0)+0@Yr`Fis(m8Q75%0Jq6LTA9XCJkHit+$K% zC$q2|{XwbYD3pkvbpB9-II8y!+Ya$J-C7>{#Gk-m#jL`kYe>2&Rr0BGQP!iH$(`ay zegY7tXOwtakB&_6UXqQqk62Xd(X#%IA2tF3w&suOY>eY*Z@WW|Q{qg_bIu?wGf%C} zin6Ev6Oy@!R#9FMG{PDDZ*~z%QA`#c;CaDy&%-|%4enKSMFq12{7@w`d_Q>o z(Sk$yCZOt)2d&`TF$<|3hAGO4qm~3B9Wy*;|O46uM_nvYRaL( z>dVzr1ZGBhXR0Wdv*UrQA$fZw`+mA!+O2=CT>F2Z#|IFGDuB=J_Bt^mQZo+zS2XLt z*8M-xK#7+MRKJJ^%%Q&=T+99U1O(>Rzr?cum6hmJP89FbCji2&Ef0o1T`U=jf~~^) zyjOV0L(Ym+6+h4jVk+3y@efaDGD%2Cege0kM_j#cQf?A-8(s9?Gs+P3{_E$I75{vrC(89HQzAL;GZPCF6j z>L3N2xHLO;(&P%}AMKA3z--5GJRvPwe~0F9R-rIUJX-kD?ld#hyvTX9s6wZ*0mink z@6zcs=tkL$mTy@BYOdh6|6UKfMGF}0oY=1n`=eO6XN&_3=BGDAdBwEK!! z^N~Zqy9N1Sy0ET+HE|EANP^~T_}Go|A51}KcU6f~Vh7c^5Sp;go-eIO(?=ps2B8-6 z3H2F+YGs3)QwUjPT=0o#?E(_z^4IlO&IqxFn8sE~p_VEic`px3ySJ4L9STv4TpV6G zjcVC?zRf>GA!v1KI6dahGotn^b+AjcEF< z^vujRP|KunI$Hz?S01EpI%^g$bNA94T zao169&mWGD)|-8goGuu!9J2xf`Dd7n?&;N^kDP`f+(Vt(K3el@T zZ6}F@OxF_w9n1ucYXRK zgXyvHmEOVQCql<1RRp4oC%uk9YR7y@fB!qVbi!8m6&Q14B{#MtocZD%hQs2rE>xCk z)U?+*J7h|tI_bsVvgsvf!dnRu+Sq}|2H)GuNuCt>mL^iw_|LVo$6cURpT1em_%}}s zYua88<7@cv9~tt{4n?oK;Z#ST-7IVSwGiEpUikw(>gZiBE0bxr;dvOory=h>d7l52 z9oa{37w3P1{B2}t1VAvMh*+HA;2|8uLB%bZFl{hmqIZ0(@nz+6Cg}}XDYJM}vty5( zZ~9Xn~G2ys=YJ%mPq$yNr=# z8#%lnJ6CQn$|(>IySTkl6wFECT6oRALsYxI?J?{?=lgnq82`TWW`Yr8OLlff!rH>l z2_IyuPas6GEG{*3zi4@Cf7QS{tr+e0tMkw4I-GRv|3_SiP}a7|<;3tJe5Tg+4&ve* z4N@V13=ETk@W#N`i3kjJsZhX|0?~*LOYa9OG3P+l)KA!_>MqL=<%1WQ%x>gt2&qM>{?`vGyOukdAQyNL7P)X^kWbD<`*ld|=o$=mR_|j#z zRlw)oEI=l4+YvEz)l%AHlAnIg+KPa-}f{eM94@;^aM?ht?!8kBg^f zBc=PvHL9UTDf0jjse~JSc$oI}>^v-mN|D1&Ngz(FNMd5G8!qjAI!$0Kxh|(r+{g)( z2wI#J9jSR5BnRaur;ikq0w`jGnaV{enO>-%!%uGE;|77sM8<5b&mQd5*(GF zHD8j;IX7Q8;20WzR{N=@5C$wah^BEz&CH)BM4-;r$=ngY!klSRmBT9;BzxjLFL->N z%h#oZith@nO;X$=zLbT52Hs3#+iJirc|yb_dU}6n%GyUXebUu>!OGe3bD1yw;N>?* zNv>K-OxZhO>9*DG8bYpa;AXlvBlb;l)VosnAt;yHqcfDwuitAA)rX5JcZWwd>R-_x zQeiFfbv4$rRc9IIyCLch&4#Xy403Mw&db2!TpsxLyi%-|we8+Vh`foJ^GYA&+wHup z%(d>_O4d$?)sDO}HGPl~ET~>JL}loPJs?!r)>dA9-rB8yctN3BjUP4~XkCfdjYs`(uidNWPuCpAa?m?mQT;+AEaHY&)y zp|fW)>yk1yn}Li-M{h=~plpMUt?iZnlxPVm7w?xaR@0Nsh<*}k!>B~U4B}x!tlf7C z*4!(*|Cp?SFlO-JQ7$y&cv{n6z{j zf0K$-r+OQ#?MPRxfT0J=8V9Vbl?~lnUV656r?yI>Ay>ZeH9Ms3;*}>}LER?{=~mK+ z^V?siNdHkBR*C|dLo%U2@BLt*#gahBmsz!)N!mA=!=MR=-BHQv?<0V#Bwr!2R~~QC z4{~8n>ptg+-q^TjBfk#jVZ=?u=`2ONjSKc0pw1Z4>Puo#nYY{E+GqcY5gu-z83SRD z^Q}8)6Y(dNY&INBtNGK8gsd$}4(Vr#S7)uqhc_E6^srhux0?Qu+Ot07fH_b6CU zb>H|Rnm#qjhHLXo?S`V)O^es#aO(RDT+0kj zo2!9TU@&4oozruIeDRw)%5!R5O|SfC9VJ3V{*TPnClK0;5?Mqod|KfjnQQ8yvx5R_ zj+moB!gR>H^V7YNpjQ&k9u2}_2GKis(XBV#jL}`5+l|O8riaC@NmB~tK-K`Z3epcB zV`UayPtY2aPv5*AK`1h)fDZ}WUi#=jv^!_HJ$-1Z+nM80i>}!sgSn*8$-m!t=XDD| z-3LJ9J{u*v%5DyBbR_Tu4!h2*F0tsat6q~8Z*W{2d$zCKzB@UpTu8Rv8#!8+;aMw* zRS2_g7Wbw#B#GZ#?hh&!jToSwym1I(#!+s@;YbE2q?)wwm$D~g%)=VhWZ38*X4bqK zTK!#{-!Dj2$LU#f&#(*G5*n~=70K0f(S54=kdE?{whv`|6C}E}+|sIGO4g=f$gqg)`Ly!P?aXr~Y} z-pQjkbYc?@-F~=jo@WeA-@!a&FW_xaP#~_3U0l30{alOt*2bIQHJx|LA;u%r9Ukf@ zJo~x4#hzVxTD}KUFYCm=gxY^86++6J0?gZ^$%oSAwkaIr-~OPnrfH)C8sV*d)PNDr zNwWrir;FO$V>34wXJp;~p+`+i_(?@02?ib*$i)$p!@cZX#Tiq#kVlw;zOmnHXol6w*Itvv-RhEX|vE^!XQ2Cnb$3)hC`we5m($B$jL zb5%Ln*JsIepJ1^f>&)8qA@T~TFjd^-7lH^Ko)c7j&aixy{9a9?^czb%9Qfwo8~y|1 z>(S;H^Qy!?=Ti+XT%+2=_k|`V-ZXqtTyoI&ch>8r`KY!}JUee%7_U>~9|)T!Jv^ft zSx@$Lr-cxi?hGb_@Gw>1(b)b-X>wd?t5LNQw{2TwD#JPm$g$O}nruzcEh$pn+cnVk zZNYGAh2UjXL}F;jzP((KV!xRF>X1jWBJGxZmN8BFQfI%L#jHfy`_`L{2f6--hYPl5 zAh+%1W4Df5jQf(|J*~n>!@fvZ2aWfz!_`!SN457ZFX}jrbrnj_BW`^jgPV++*NAU@ z2QKHRVzH!-&N>xr)iTmYjtT+;b3#Bz#|QphziC5GJLbqKRzk-!W`xLw7ooOM*9gmTh`_G4PKE&G znG0#F44;z^v}E^VxuyQ@KZ+j1{iAP}D%P@qLlHNa<-5UD!?pEEdmJrCdzlOHHb->t zDJ~Ig#t!o5yUX3R9K*Rmx;HBjZ+CAz1?nE9Xo(c>>`2DD#tFO4Q12g3_zBNXHt_WW z9)EY%X*tYf0m+0Iv{wI!;{q;Iv<2b2NERrqAt^)dSVib_K4-N3)+~Y9k6-=?&KJ%+dcK**UkFU&ZW_8cjNo?jbD9O zm@6#pFTeTR?MZmmSu(DXj{d`h=t%d{-4oPtwbQdwOZ3l@MLD=!A^it`j{kp z<#^>Y`7->k$oIMK@Z9uNB@hJsllKw(*&M;t&HB3%_%G^a|3}3nK>6ROySf~+gbZbT z{YwZC0q+-e8;y~@BQ~~pPjCpPZgO8~dyjWtC@)=Gl214?4;qtJZgg(0^L1|-q94OI zt3>Ix+2XA}qOPjjSMFU=26{7{p%7+YtJTJHB4wc=KA{^^LHG{BQ#Tlek&wnd$( zMeS0;@@XA;?oj7#5ktF-!WD8%F!$Y>cYG)Vaq zmYuuW=pPmxhRZ%5&Ch7-=6JL=g5MFgw2jRy=ou^IFBY_Sj5vTG+#1RDRWLCu-EUh);PU`I9Rc{B<*<{ zF?|V6)HTDDiya1Jyvt@#RN1}GI_eeEcCyN2zgds$`B#j4n4RDw_%$(mAuzf3s0_1r z_=g(r*FywB(h6(%WA0Ggn+=TFS*ZpUo(4#fRpP0BWKUGu9sD@$)<&&f%X;oy7z1SH zs1BTgd*NU@3Tkij#ps>yG!|BV|Do>ei`=+LATg*pG9z&&2dDE9qMg~+Q zd25O>UPV?z_$#Q;Z#-VkR5bRs0ZdoS`CzS`G??TR+CPez-? zX2<~`I@HlQmta%H0rnrum-jlQh2G><3|A&H@Mwbzr!$pl0hLy6(+n&=X*i9A*+P zsAu+IOi8(iQ5Or^QKZ{vCA>2~ON~~iUYzyXUCP8soDPlF-}Kiy5tgwT>w4FqG2;|* zkA|&d+aYY>~vU|)Rps>spd?b03`NwVP(e#`}vPIkbX*^D2FdR}3n5>!>o(R&bY zIv}|=0;J}Xdo(yEX3azm#rTMc^rT7U3#<*7m9+`2X}5owRySTH=KaLg0v5PeSfv{boZjp zfAtSy{Ew7cYpl(@lNbeN)xisKh$LSmg!W*&f|2x+ks7j5l?48aWjo;FAzOm7ira6M zV&j-a=Tj*bOUeLG&6)Eo`;_d}S4vi#-03X9OLF9?%ThQ%VUbJiwq7oDIEsqGX_*Sd zr392hI{$JE4f#2#+b+hYQhIG3g~RztX~G4K0CAy#zxsz!HG#v6__QmsqePiysw{I- zqY?ouj0$A!oC17v0>(r@Rd1UK^a);d_Q?h)#D|ZCKUs4d@9cgZoj2*#S*V)~_LU_kD_u!Od6Rm7~G(27Qu%4cX*KaX-cjfcAaxL@^0M*k(*7PS`Erd7Tf?UHudWpGy>*15RX_$YUO+_e5hc7Uq@T#`v zyyx9-qk*Ck;%UKti-Ar}hS;gA4{G*pGFi6Z#j z5Y8ZJ**2bYTRzvag50bTHokt((YpbgMr^THdioXGN|1^GO7x5UcS}SKA>Emb5+Vfr zxN9AnX^=pfEl=cm$`=6wdRp57p{B{7C`j?{MoFCbBl;Q=B_3H{0mj`eMbfNaoFiHl zhJLH9N_1$lMJ>MXgz~3^aZ&~3s73*`U+_o+$@6XMH!9aik>oV@l|_tYOJZwoO?m7} zbZm>@Yg61*dF<4;sE1at=q=YtO9K(`CO7WvB5%3 z5{XPOI(&MBI7ocAyHvOoLJiB;_Ek!T%koLi?C&OZFhLxJBzqG zNL;dG4IjJOo*PU&S{+GBlN0Me>dCq^j}UpCUGzA7L+D=R+l*qPz87U&d)Hzmo_OMG zu~qRigH~sAd)lFcWAkz5K^2+gz~vP0H)Y1RL(R`+MyS1t*w zB<5q=;Sq+QvEMlgAxzgz*Uj)>&T;;9+h-e76OuL0HpXq?Pj{r`=_>&J73ZqXYqb49 zP{r?(v-NWq`R#ulNd4N~IS2xD5Tm>p^uoKQVig& z;GbIRtEy1Rr2 zyj6;mUR)SXh-APl?i;>L(|>l;@NVj7z}^`OXNgIl)db&U&D&aU`=9=p4^>E#ExZ%c zX?PmmoG71B_=`<@D!neCG4$$``tQr`0 zwq*+|;vew+Ey8#6KDC%K@i4J6tC|p}#J42|6K0~S0%+k5AYMn`Ark;EghO9-I~7rV z&6q(V6WdC9V6NBx{_RN6*^&K)@s4iY^<@#|hm3h92mZn)ufd2gYk3Evv3bvq(#-y3 zDW|LJ;VE>MOQoA;lbNa5!35qN<1gato?vuQ_;jTR>n`TN>EwHd)DRRB4 zL`A+X{6H#u=WD1Ot%dWoD3-MbLc?0WPA4}-$CfX=NMWw6>>A1f+@2HF8wF+5_wg++ zLNiGgX8Z(QO3P27vP~XvLVM|=@KR_#&8m2+ZQzRI+`K?Nc>^&ovS?cT&aoZKho5T(rTG{trh# zoyNR;1Q{5;baOi5IOVoRdF3L;_=*SE&OM!PPQKOeyd+vg)>m;Yo>)`hr0x9>j-ulg zl%u!&+CviZ`=}_EJezuMwfC4_Pcqt};V{I}7Rk|-efb7Um{HFGP0z>74e+4kTOA0Y z>r_FctFTfKV5;6t5G$t#EnrujH4aL~(Nrk0*;tAxYE6O~IlX+~rB(<)MzCTYB2$D` zuHTfIr>Sww;<2lNh#F+A`O5as9|O-d$ljF15>0$dGgn5cqNdP@hbie_8UNPw>m!3k z{F{>gC*`6?iK54e1`WQFqOC}kk>>U*R)@|#Kzq{v`Z*k`CfwW(1>eG6S-J=XiMW0zF;A(y>uCjUR$Kz z;_a&m@BZ%aGH^A7XG_gSt4;HpioVjC+fK;5vhfc{KO2iu>`qu$;V&Pnc?UIy&gR?e%}~|=Bj7y zn{&t5Kaz}0&F%nGvs8{hYp;(zjvgdymPR9BKu<`iFqA&hLR{n1C#^CMHDPHnwi_RE z9Y-N}BV#46l0s@3MTAG#E+yv^4UO{qOUl?LZ?_=ObF~|nR-Y0i-g|5DiTmhy$47%D z6!E%S9bERVI*8jTo~0}T{<6cLY!%DSxw`93KQ0{Ys{2Qqww!SzbFN<*un&PYa`Cx` z`#~EMb4K{+9rT=0d!`-_TWPPQw&U@lM$Y;>n(bffEH_(nEn!JB;T(j2uJd-(E&ke4 zs}|^TR_=k!vN;ELx6gOUs-x>xR^JA7<$wrbh>WM7veeN6jn1S`I+6Ss5en74hztIz zwFUY!i4D08ov;)$<7Fx8*SY3B$)tN0avxE?_^Y$Rw0POGyXngL$1Vad&byU^5AHA= zm&Mu5$V9v9D`+%^GB}r;EG|9jTx_knOKy;9tB=PpGos1|Vd)F*qFbX3Cr~{^GwU{Ua2@zd2eJex+ zOtc4|gx96xZ|x7cY6okFyh;|%PEHo5gBMg1WZhGxx+CU_U_*P5tc9pD$Y>9S6TE79cGobH8YIE5Nw+IjXf?}&_UdJRaJ8Oh(OrUf7Sl!-vfWY zq|8X=xFkEch7JzKFMoT1&xZ_4=HD*xf$J~RmHjM|U?dATPQz259#555_4|$e?$#FJ zbjv?->OT|o>B@0&_OXG=aYl(6zz~u>OF8xUfPE!m|1=9_Ma6K%-vc~?LVpdr97HHh zPti3w6&5!)Hx?|EU9y_PAMqZljS29b81cpTCDU0X83i-SoN&Du+MpO@xC4#-m?z;Q z^O=;jP%he#7|3Ez5P+JDq`R~0(@!_YH1;2cUa4aG)P3B>^V@ufLmC$3yIFNaf7wld zUlc(a{G#A1GUEtgSI5eiswYm)ppYvN^?2`TIpV2usOn|)u?v0wc=>O09HHrsJfopM zwm503@V)2YV`_+no7$vqyQg~{{&Q_4&Qac>UqAu#a8@FSqT%k+L%`vt zudN{IHAe?@ye=_^Y-$^MBGw&$Ubb)Sx+LL?<)flEg7VU|7>;k{NRVw!07tQ{w8JE!U)WsZl^h7H#H;rp9OqQDlb-P!pN z@_mFRx-mxfD5e=Fwv65jI^Oh7FeIy?#`x*$JQQ!FxI!RZhV$Wj_B%`H=C1^OskF1Y z#h~tbvbUmoS$RxsbXA~iW@J~mOidCcLD`@%9}PI$qbEDaH}DiNB)oyK@>jgbA8aZ| z6t&qBaslG8?LXt3_ZJ;^Xze+NsrD+i7uh~_^bw6-OzRM0EhU?X_XSgZzMOSKH#40y@?j5 zv(0_INOKbDTs;*y0XO{xjd&s_AfX4ClmvJ?2MQ#unGb455jREN7=8lKhKHmg`Br=&3j{@vm2<8423UFiZ3M6bY}TZT*a)A;#^) zM6iYw5i}}H){&(jpx-%+lJgaznyzm&)g-U@SW3G-Fzy`}NEd&aAg>@W%9aj?m8}j< z_U;=JN?kc-*$Zy2(LA=>F`N8WL)Q&Z5qsSh16)|8sEg^^+S1HT>oITn64QT$Fe_nIVu5E2lrsCTg(fNXV^~!BCO+k-0 zp1uVIX+aAb)YgXAu0@F*Q_}&5KhmM|;gNvAjDFDRVU05qb-DWt(Q=EVsmmD8qZ`2v z?gP8a?WY}=YRn&*wyJdXsZ;IIb&{ATBTnx!v2HUgv(!4x-Bc{f!j7`A{=fx?(V6L%>hS(UPf5Ti>2RrwQsCZQMC|yLa+-dc;pm{E&^ETk|19=_HQsxkty3zSkRxBo-QA2j# zy>r2-D}2eJuNejpB*it_yVHI4dJdGF-+w@p%4+s}*lN8}p3#dfdDyARSUgz<77(La=PO_kD&W*das4r*~hf?I1xK! zA-Fj(!!D=20A3FV@)fy>tH`%d(s$vHxUz0z9ySC$g!^HXS{aN}u ztXh#$gxLsZj?m+A1Al(M)j#%9{}Gb4B6-1@HJD30O{3J zc2%Gdcgx5fn+aj6Ro$zOYP(u}1kahu_4vE5@8!xRf&l%{t3h3GgtM+hsJguZ`9{f_0*ng9oH*rVI<=-#e)DH+xeJ z>KpYEI4NF=-dC`P*9edrO++Y3|2#8Ac-oBQ*#32C^?BPoIsg`MQ~+ndffPVZi&*iS zJDb#hxpDai0vu+*h?#PLz2k2Y_WwczL_F_ajjahW*TLab z$F$`=+_C!(H&5Uka#;r{22KkFiIc=3q%@@FKqvZyVDOyJ`95+Eck3lMnHi5a-jrEk$U#z5}0HvrS02~7_FkME+ z7{+t;Qt}e5m0~fB93B%sO2fIJgCi_>r}?+p`-{LbD$w~)`QHSdmJJBIDrxPJKSV?j zzqMz>D|j$?&&%C;iPdRl$FYH_;?Sg2GBm5rkVVS)#~R!hE?2_Z5-hF2b}oTl0UA|q zhHiIUfS9caQ_!UoSwl(Jtmx@iVq^`&H#%+f4%IeaBbeCx*4?YHGOV;cnL6*Nm@ejR>^!Y-F#I!z5(i6gB$2Bt0MdPx)KbWRb?U$0 z*;P=W{+I0L-&C2(5GIrilB?={dd!QftE3^sZ@ZAx=Y3ZGsmgp&OU5@i{BzYx){=4L zmn!qN0+Eley%}v#X>RISmC0xQZ>mhS_O~LUn|dnGs?7Hm*bf*}Z$rk5SU!7l`z$os zz;=A0;QK?BSzF#&obas5gj3~p2dgsO*nX)pVg4V}0^1lT6fRr|hgAv|zAmo1=jK?k zEIz@4C_^@`T$_&KZmRgYH}na5oOq*l@ZRiMuYILMWpynMDm*8U5=imi(O+=yQm52{ z2tZ_YFif0Qll5AIE2Zp~Yb||WTaCRZu#B;(a|A*g(Obv^J$V!XIob(AJt`e`Z)VZ) zXc3C@;g;gFi*uu+ZOfn#l${-HL+6sB7a-EBvxvhJVr9P`Dq+tsN`8XpN*Y3ob)Xo- z?Pe5XL&!ng9eleoyuyAYHp2KbbR^uYkH+zWu9&Hat)QTZr(IcAM;+T-XNVuQ9-;YH zMgDJI#tS}pMtN_sGQwFOg6BZ2>=LP;cmeZ;mq~9!#)@;HVD+>LfgSIMpu z>cf(=ssY_yjA-qk%zS#uGb5Xc+k-kBXUj(*OT8mFb5AQvebA7OX`se zF3kO%FO6aZ!9oYbz>$lQa!3msn7cSRO0_!N*>7Vco7)}qZzK)F)aOQYV?iKm7~eb! zUcwcs(+~VL&V|m43ke4UXTz#3M5WWi9Yc2C2(#rVVhtTi=S9fNEmkT|lqhU(AfW7G zqmVD%Gj06ii=r%*q>&I@F>Bs@#{S%oMD4CwC+Sy*8?B`Cw4`zwLe^7UmH3bgWBG#@ zGliPU2nXGKR{-#J3yX>FX7h7;$Mp_;y|G+<=%hun$qW%-sWv!pWAS9$Fvq-td`Y$? zcCzV)5I$(7!9y`#cvg*){Z(f~VhjP~{h;F@0&{<|k{ac~@LG5v@V=bk9SPsBW&JCF zf_+=!d5R|(K>%hZDnw>ksw#Hbwf|H<(jzJ`*UHHMMF%(fjFbgc0LT7;oS~^=pV{~= za$50k$eIe^^goas;5Ipa-zNLt+T^ILVE$)sN2sgVN7jGa=CHz_ZT>T2+=q>G)=|DB zQu|ZKU)QE=EA{P{jK8MJ;dxmeadNazg@!uIbY3holUyt;Oc%jT#AnmyMqk--Bix=P z&`$2o5?nw+)`|i}*+l?SDh7r-*@@Hv%)_z90L(9o0I{Faj3ab8h`1g27qpr83&qLK zw~rru#iHphoFxHcE`qAzE!||>Sx58167+dEHzMEfdWDZv%-3NJldp)aW*HZ@u}%p)!8**(kck|pF{&fpweOe$9 z=CRz=M4vWWy2_Lh!17^_{KKl}b{8J^F>*N!#N?co3f1h1Fj&K7?)RMd#=Swn8Zk+_WbAUQK+GxaQCH&fzLn~s5 ziCiu58QHX{i)!rd^(M|R?KfITQ3-kU{b{X!v~|;Yn<6^yWoS)TFP3>v1uyX-qGP;n z+Sq)FJ;CRN2l25#(Ba#yqdzxqet{$2^gy$Z7VkZ?a+^1UcS=uO@O*PoIE-V-;a0f! z`O8AW=+^cZBP-CJZ#wqnXr+tlzP%nz$8LsKlR<~?RuCEQ-G|D-b7L=E=cz>XeRn;I zpz7QCU;m@wWyOxKX029K)}=6!cEb z2XFX44K#gnj=k<_@v5n`*(qE>;1jQhl}WQYMvF>I9-X_Ivv1ixu$Sf66yer%$S+M# z(O!PZg9wLw1@&d-aClGM>!-!zk<60Js^Wt#{|Ym<5R6E#92|~CKm@!{_e+uuBof2W z7Aku#`k@H-ydF= zo-_Be_FntmYwu@0E12Q3!GDqcFRS_!-2tGx^F%NJbSnrZyEzxJ>|d4@c7njs?LW09 zg3%4Z6vIRVL#ITF5TT)Y5^{fN4dwwo(;65RK%=3<(4YduXpEmR#6M*NXt>rcfnB#+ zFSA^7ZQU+rPCxeLcJZD0_68tm!_vgT2S0Z8H z3QT1H(EybpBpRTyb3}vWz$VQGtT{|JjA#HF;bH^mKZz#Flmnv*8}J8)h7k=q)%}-| zpC=lC2B^Z;1yBVxZ@6s4L<8o1PB!2uKhqi<4I>(K3Ng{3dFO}*`K2{5Dj3*c0MXbc z5EG3p=RDDVXze1{RjlJ?=Tq~e(wuxqh3TMk{KS!0GJQ!7=q5xF@G>m9$6Nrh%mUEtHJ$W#y zKwAK+z*Ghh4Nw_Eq5&%VlW3yAD#K(0qlcq`#Rkv_i3Xt0EjEA#r~>T)r~=a$eB_9U z#+GxQXh0mpnbzQF7}0=v|3&sWqCtLX4Nesp(Eyzzv}l0Nf8G^;ZSEgh6Di2jrbaO>~LM-YU_Gnv47!}@obn&*(Bzvc-) zss5^4Y=p=kGGV6YZ^%d7=aCXW=LzT1Uy)b{k!Lc&sLkNN%B-e6kCX)7ae$A5fW@Fe zW5L7(F)(8y%8fy2F@y_Y+?T`vECzssGGbDr&2?w*{F%-UmZL^1>VNvji3*D%0(PyW z1Yj`$bO!{6MqqE?==1glFf@S0kZcDm27qRRqY>B}IQpEu5fv_kSqw>l$uP7eD@-;5 zdjm(Gw>JP9rtN;fV!+T$aP;{-e}+D1ZzO(d4UUGwM~=YWz|rUI4dj>Bz%Z?`!DS<` zH)r$yQ#OExYYiFfT7%k_*XjzYEy+E94`~en)n??KzlQ)XweZ7*$plSW$RuA@=-lhD zC7QH!_Bj&^VS*b;ww`RjXqY{}fbjdXAUV?cEztvns{sqeCJGo0u*u(%=eGoaYzD~5 zhFSoa8`Hlc-4Sewj=W1)yc84?yr2n*e$a$6uOo3ieI4>Tu~FSVN2O!C1g{9Ff8y8Y z?jL6_1Q;j4rw-U8fpmmxu!M(c(E0o2S#gIy@0UF-dCkDBxC1s(kQKNWf@TVuL&S>b zrl6v8tbn0`$##eq!O_f2Ff<}oz|iMTA{S!yzO_76({bKwH=p^bnOubY;c?S3yR7}~>} zgXlvEAfb2aU$KPni)v3c{07jO{o@J1)rYO?uTNl}IQIlmU<|M_TSA4vbrUv*RuH(O z`>#)Eoka8m_#LJ(7q~RiGE1@ndYDFV?E`jZZ~nP!pJ@Nt3;>%3Lu0bQ&J3PpoyZs&h}xdEK`z_>Ai{3O_#!R#=gafEgl(D+Km21I?pbOs+cq8$fYuk$+&Km!`b1QL|se1XeGwBumt^E(cBAA^k?y#S8x z0K+wY{@w>)?ejZMvM5(X5~edI6OeSLd9G~d`Cu9lV2JyFCPe+ZF$x#KZ*Ne*MoBkX zben^kWxjQvcbJ<>H_Mzy_lOq3_K2h;>;`8}-3c#Wg8&V;aOY&h(7>F5B4U8P&EXcV zdm53xpPP1{*SDx}5zIzOvcdFi4u)B{?rB8&hM~{vTet|+21DlnyUQGI;ku_0Te$B0 z^ZJ%J(;Bee82@AaGayF+uuI(+03VMz`k9Ys1m@#W{;xisA4s5X7#J{WKYTnL;_c{& zeLT%F|MKztKm(tg!Ce6Q%*WFq-ULUV-x+71b<)4IIHj!O{OL)K4_v;yF_qu*{GS@eXvD$Km`D44{8^@%%tD{!$uX1|c2j zZ7?(f6AVZHV}gI8e=4o~F88Lg-^g7vZhCY?N;BiuM?a@DxQhq)+7EN_wDiHmxBXWa z&riXCiwBtW4;N1dOABn+2<$I>*#FqyALvfNSph894;K%dX9!(9XDa*k=KT*EsBHJs z#RKOVLKn{&`cIw-0Ztm2Y`_WwE}o7)_{b4h1UUL13;aVi3=L4_hl>YJG+^EcIsUtg z=O-F)@tkQ5P8Ar@5W0BavdwA6jdMped z0j~V;@xYnJhRACTN1taJ;Nv;dnh4+_f-?=FkLPUOf68Y3r8PKLU`#{kdGnp_S&tH)vzxjB6YUtNI zVLqO}BY*Sp{D%A?6L!%2ZB>+id!hY_1bjSa^MrHhugHI1XoEv@J_DsE1?-&aHiB!~ z2+;78?y@0MV&dlbTufzoe91Z2)SG#%O3g1=vuLOf6|ei1eZbrZ`zWqO`{I!NvfeVS zp0FxX<DDWa#3j#a$UTTbO!AGUF15&R=s0 z8XBO9K7&S}?e-9s;b)9T@qF9`eRp3~ zar(8GW3^CGFm3IwcSc`bkL)1q*7qeGdyG*abvL|^@NUl1&dcb~_jqB$%-2kKe2*2- z&}9ZxITyI%-VeRHb2%`g=n*J5vC}2()$N_c0lG=%x(kWLKI&Y%p3b+Op@sLxE#{*O z{qb9oAIl=$(HUs2ifhu1_)3>@ead*%v$lkn*C|g)$HK5eHG;@>24B7zWBny^mZ5f0 z{M~_+Wmv@jia#2gqKpnV~#iD*CSM@6=Jzpl=Y^U(&m;v&W01s zB`n!Xi2C9`HS)M7W6YIknmpLWj?d|4J6o~8l+G}!L`#%M`fAf0XKKYKMj#CkqHl>a zpg^VL8HvAyLx5|h6e~6O($W}jv=;ASZd9w0$l%nfv!=&>fz`K)usr=X2ma~Gy2H%- zhl-Iz-LL(wEVFYWr4Bvqx3K2C%%Ed$no_(N7~{NzhCGd5r&1Ic?OX(DRB7m*Lta8V zGC_U@%}HNevqTPpgqQixsCX`+Y3gWdht;(|GDRM1|Mt26b+(SqT@I{OrPL)0T}%DF zeBY3k_Py`E47Nt0aZyaV^@S;Rn=+BZrNxk_G4XKQcDWn|S%TP{hvVqws~i4GFMy5& ztnUVcA^b0qwL{-2IQrm2AY|GryNXLqQ5<#&3ysQ^b91L3<_7m3ewuZPJ5G0WI9c6H zT=+bWD2PSbKgS!W*7^5WH-mFFE3b_ZhB)R`3>AFel~S)53Mwt>E!s$`^jQc zkA_xG$_KT*U!c7fSdRo59ap)q(wD)$+$Mz|9=y(dRQhU|tmT@2;nKF>sBfK0Mikai zh$d%EcN8zECf)35zscIu@$&8u_B%pvcw?I6Fsyta1*Yzf_*Y5L55$!D(8Z>WUo4D`@?0+=aQF+yV3n_UwoA^jZp5{Wivar?WT+a^_a0#)3CAza#HOkFoBukICN)ZTh=H@uQH z7Dcwg_dP{B>+?DBl|YH+ohGnLVrWHac2rJro`o4-Sx_ey?T~K*X)EE$|DltoFj zGpS>D*c)ItMfPcw`xZW(Ab+QQ&`8L4zRly|!Ppyz_f)*_ItVaR!&aS6e#HyGsz{5% z-VvC93*7&KW8I>#%Oa!;a25RDIMyu+yFCEX0O0?LV*n6F&L2SVUpQv^+jemC2f~*b zuk-I7dP`gRF->2aDaWHnCw_@}PZQld9~Hkm-)TI^GV4+Nj4%l65^fHcP)-g1jr!bb z!DeFzf??LW^3(=}oX)}V%X~M~PX<_v7qHP~VhU{;!^VXGBM^@V&c0;~>#kwvjeI;4TBzI>D#j|cYi?o2Oe{8`~B}hJ;N=0P(G$!1xz1ow$jA?{! z7IfAhB~?E@RkizC9p5~ykILqQs$1z2y7{%3H||r&)7rqtBu+C7xc(kmf*>d9y5tYm z*Tb~OtBA>VkL>I?7qSfJu6!ERp}seSgU-7v{8BCfb#(W&j;9AZ_Jqh+>oIF~Zimy& zs$UV9FrHnQq(!HBpH55j{;t{PT|}kc&FIPXf4=pf8NhBvrW_zM3VczTf)^<5EukE7 zzBX`#h=jyvG0HOJmTBM)Whn=)nl%CT2VkTxcDFUvo$g6FM2Qf+i=y3m90GsfhakbXP*IwxR?jdsvNNB=3D zJW|tTWnFLe3p-;$)=u2pBd@W)8782GjKCc1@cS@GyH)*y4mkWk-9Fa*Ybka7#$vq* z*r$%XO-~<;wM>ked7HavS=-arW>;(64d=1SylGGoJ^M}%Tq&Q5#s7e&N8s5F+JdFt zf}vY^6?kP&m!rxb?ED@#WSZ>>XEcT=t`WN7FZsmf5?B{)9u)SKr)A zZ>P>mO4C&C#B$=JLT=I;C5|$UH>Js^faOKujmE0oqMXwqHi^IoBN{kgdgDXIF9?Pu^8;>oOhgF|;JJVK%K@G> z1K)#TC}H5#1XjM;e6snxAF}!R?<@aH9#Ap_hJ>Xvf~Z*-W)PgXfag>OF=uqd|7~M5 z^F<$6>z-DUFRMB~YI#2`Xx*M`#$bcHlE*lUPyf_qdEqIPDM_$A?iM6wbao=|+Gax- zNGUxb;bWg7M#{VxA+-2a9}4-#?6tu|*W&CK@<9sN!dJ~SyMY!yO15K2(Q$j_LjEqi z(2>bVZ-qo*itnVV%h2iQce2DKYWk4!<-WBgv%t_V|6 z=k)gz^V!{8X=1N`_?E8;3Js7RGG}P<*Je)aYwFR35+Bs67rCBX2vrSId?&rjoh(xJ zMP5NmXigb53(Mt$P2oOE1V-Zhf_W}I0fTPFV1*f~xpBqjM=w?1rCIkSqg|N3kH#ylo+RrbiHI5t&g zjQIB}r-b9!3l#asH(oV^jF-rdfsa;e-}fF^;2lQCJgY3(Z$ym&39lv6_(ts>6ZG68 z@op5S&8CvWX>V~%&D)sG*r~L~c~HseMEXS`v1TcUWTjykL?jA1)@AMgr-ua)A`Voh z5W!>-1_*;@+I&GBL7-hSTI!?U8xH`64Tb{_GXMwh4MdHWOW%qpinsaS--2K$37}jh zkS)S$B8CAVfr#{TW!jNJ+V_7JwD}>bKl=v=gbo8C*hUCItU29zfTVs16cqpg8{vPD z1O~E^fZiZ^%|ONkFezq)pX&boi3}EHFAAR&3j~-Hm*<_tbLm7%3@vhv`igQ9BG!fvmjJ!I^Laht8Fm#DU}UqdTCbD)H3Ny4Qx}jp7g6lR%lCNvtp5;FMkyE1SpY!=gVeNW8g7ut> zVWUr?%hhQq2$01H-r^isl5jmaax@V&T%90Xah~ZcsWO9RbcD5g#TxSlb>n0i5?(34 z89C%hArkqt_8TO7mzP352G>FsmtUuQv1@@w{g;hO5x2~(x9VTdUD+&^vS(EpNNuM#l2xt)x^_r zdUyzh2dl%*4B-1Ds1M*FP=>I10~O3Bv`z!g$p<*XxVs6t510l7$>>1z)5bF};8(r$ zTPG#hgMbbUXY~v*Kvo-8CR1(*3+PBp)X_&9o&0g(fe+-Yq9Lf@TDSRsz(?Zz1<#Tr zQYeB^AVQA;lDoExPF*OwcFwJbfhkQbE4}vbH^(zAh!lbWE#zM7e%`r-o|}yT+>a)m z`xFrvsKE<-UIxnkV01qRs&#dm|4-Gre&`?Apg_76P{0?xyB7w0gHUaek;(1I&A-V7= zJ3r>;mEGwo;Q*tAxvovBp)EmD%1B8^!ertI-<}4~LHj+z0=DI@k9Rocuby1oz3FC0 zHLtE9;hU&iYKNPVctJ(nW1i|Z&r0WmyCeJ(#Y3a5-JwUPb(&mdLoWgv<9Nh%<^$Q^ zJ06f6yt%RZ0dLn9?}Msa*VZVzpQBP{;+7t}4WZwJPHs)R5!S;1S<<;4+Gu5)DRh&y zO8XjH?v!R!nTG=zU5uq74ez_A9tR&0y*Dfho+^)SYB-WW{kZdjRq zwT|2EnE29gXm?@Sc)|o#jBi*#SL7)&>yqMF?eU>xJ9T+vYrW>wdj9I;z1pkvqGc7T zXs5N$Zu=!}jj}G_R1OBwZx9k@m6jQQxA6EDwX*hU*u-Ou`WV~tkf>unklH|#NcfVI z7qNf$yu7UWa0TCig3+DCbb2e6QFos~>nRSmtQ6e+4r`WU?4bRrl7>0EL&leHh-&3E ztPbhHajQ6nWsj}#45E#2rXuQ>_>O(SN9|2h(bi_s!?gOr*BS-2&?Mb+@fYqhE{z%8 zpopz{e{x$AmjJxkS$Cp?>}Veyw7IX$`Ua$|Fu6-coL+rvp~(bEjY|1bo|0QnPEo|W zTW0j$ai2E5++aczXC%1lz_B#`m);5yEG@0WMmR-V>Y4^vLNn){2mK-bU zE~zc&OY-nM8E+&Kc;kSVJ@3Lrt(Jhz@kP(`4gVX-WCPyoX6kQz>^@d{hOMl}+#T7t ze=i_RV?*@8J)gGhspQV08AzIr?`+}@ro8e?!_ouXlb{anQ`3jRVd#SCkw7JKc&tvufIBr4c}BkbfzZxENK7LQ@P_Tj>JWv)Tn9>J5u z3h61eK9pH9GIzq-P8HRm zp*h=_>S;@JJxh7|FGZ_(3Q^W%Orx{1{fD^=m#!D)`)0geyTuz;6=+iW-ItXZKV>98 z>X>pVrP;`~*XYA?<_3+g6u6ywhA{f3yNy@cv_n+;qD# zr^cUL2@E{H)hqAM9tXrk2+pe7ayx!+B}Y2tFwi*x4a=7oQ%2g=ZJ!w0#YMfxGc|LW zA}zr`v@yz@?Y*=MN{NK#G%XHjbDp#p<`D~qH&v0x5#_|3AQhTvmA&i9#@{^RY~Y&e zHtKqRsxkShm1guycljM3-7)C1K4_`{acv#?wAJV2kVB$6ReD(O?Tq*3}QU7mv9gzK9X=v)!k9cd8}E>LW$D?ZG&{sj`W$ z#dx1Qk@%VZ!&-rdkToBfhct{5%=Hb$bZyNI;}uR*@(Q-m!^JD(cIC?M_rXkl+r=7A z0sTq#S;9qWZ{{>Uob(=NGSQLayM#YMn?;=(3YVY)bf;F&vN*n{bvmXIQJ1&jE}1eO zRd(GtEMMWP<%+l3j+)|f)k(_<&2vK02Xb-A%i4rJtHcey{DhECZ7-Dwbt2QN-w{pf zD$eSTf1Brzq@`mXv}y=B`5hyYkg|B%u3 z8)e7PA;Yf^3(W?0V<7QJo>DZPQm(b1nW8p#P~*Otj%@NDTnRhiI9)l827RAh) zr(;W7vHO--gLJ#qOYn9Z5t_~3nrdi;8rStKi2aT6BWZ!66Ty=;+=e1d4KcN#p?7=j z1yJtwt)qaiEJ|5IpUvJ}HCyLr57ruIXskU>;1N;#3TA7ab~2$AJ={79%kRZ$VfUFi zG+rPdw62lor>ZkZDN=2<^UGvQyqa5lC&=IGuD01>aE9RtZbNz&b0`Bx3vr%uK$Ks2 zOsGa7vxN1HJSf*lU{|9{^2Ow%HE6rm>=aTFE{U4@{ucJgk-tEoh7IxPc!%)8qib`F zxYaJnuP4cPdYW})_kF43*16EQSWjK#csMSq<#wXZnw_{GlO5-vN!{bIQFG+;%2P(7 zdRx1X``SNxFZC8Els;HslYu_?mS|G5Hv<*TqK=k>N~pHhC+e2mT(stdbXw}>$#mL& zEgRX;)BKt*VCP)x6LRO=^_ywA>$vGHFXh7O=!5H=pK9fhK3CwOS>#uU3`rJH2o2FH zrEPA$CxfG-1yP%5l`Ay}{Akw)ac`0DyXDXEu#FKH5o3i!s%+h1VO9 zH2WtZ9mN|ZU-L$JX$Vv1Af95f8O!le%UMrP<}GVCE1XJioto2}+;>><(6Ji*fUQ$) zLbA!@NP@>n|8+1lXpI!-fyWF>O4k0uZ5RFgVvlW>luVOij}3jQE-2&HvLPDO+N8~0 z|Fha#I?%e{hQMY+zvp4RS|gYD!|uRqN8~h#vHaVp!C_M6Id!FIJzCa6PgRi@b)H6N z*OmHC`ebmTvh76&mpnUBeeT3?%BT{?(4e^&8$F(?c~WhGe?{xNGgv-Ms-v~~D*L8N zed0#s29fDa3-NvWe&wR$a4G_9Pmf{wamqJrh0Vy{Bz4m|lEA zF*?_;P?qeNI_un?z?*G|?qcNgIBeOW9TQn6<3+Zi!1R-og`nM>ZUd*sI-@(81(nwx z7CqmW?d3ikDjj~pn^y7gFjX&)(@SxfrxH0g#zKGi__8CeSOQVW@aPDgtCK)d3!&8U zsNccp2QI?L%afH)L(!jV+E=POm_L;iksNvVP1^=~jEmwL|D58D&H;6t*?vfR)5c0k z!4cv1@aNd9r0s2p&Fzol;zLmAtJZcwpF69EsQfKtOzB(I%EhRPv->L8j7R1s7HJmq zn;KiK44*{$FUx4u63`DR)kG^7<&)nQtlKOwas#fp0u+d zuS&VSSmH0~^~vnU+vBh<)#7Dh5R8q>somGR=~hRalG>-h9-ZPH#wXmDXwGPfvpU`3 zJQ)&jSOJl5sJ}BR+pFp{rjmcatIoM>;(TA)tfnTLo6%5GXwoh1MbN6n12b7ko7g=E zmTOx5cohT;WP+GA{ss;+9Cv&yxO(GGNu~-%{S*F_vD60d>UoI`TwJ zA+uGjZfdYK?p8TG$CHv=<@kPLf|D_vp|Ut>78u}8*2~D|rMYNQ`I_c!tjXF}BQuqK zLT)U|8%VP!y5Wbitv4>U-gvSdeyG)2Cmil$+v;v0ukP=LZl+i>!i{8Bgk#3>b@mNM zYO6m7geibPgLs(9(}s>L&UuJQ5NWnaH=I(oRRJx$mhc(fth`3->gW`Z(mqF6JZed; zA?_maZq%|e64{pLUMyQ4cN}WtP6^>xl|q^eR=l6kck%i^ZB*FB(?x!Z4d`0tnp+It zU9_QZx27MT8VH=*DACuh8%upt!7!DDV;A<7VrL6`DZrSh^~T*(JZN1)^%xJnT@{X< z)U=#>!x&o*ZmRn08O{$mxZC!)I`(oe#(h^!msDtW=&vrR^C;5or29J9gLVYjJCNGV z0!&nWFC4z~UnLu-+^!7xl;(hWn781NWv){H!H=DRK!142qe7bMVZ9X-+fu#Xk_Qt* zIuW!%Dc#V2ajMOM!b{zZl=~_xX<1vg=QVP0gQB6OMy+=Lh_>u&NU~QU#|PFZmD<@S zN1<)C1BU(~ZI(u6?&^8tBidDC+S6v)gPs+%I8hG3FK%NP-~fNCaJnL_h-(@3Nj-0P zL>n3;=#Xw$=!=`w)|y>%BTUQ8oHdF`_9~t|XFy5nW_a#ky}EnbEsQd%!Dv5mpS;UD z^Uthf=K?mfm3+m^)Q7qhRmK;Mm3&D?S##_07z+F_i@4c)3;i0r3m0v~G`VE+{Ulxu zr$FsfhPAg%D7;N{O|(DQ471YH3}w!N-Bp^^rA$dCje zsafAp%p~znjWpa))QBt?NY}8^XXgRD-dzYo;HB{G8d7xdQV6^#lX5nZ?00+-h zQOyqWQRuJ{fe-bthE|zM)_y|vC{LdyO+($#PI2tik?#~}n7~-ss4RP!*wx4pSynjKHji-N5}(*b`AFSX{oXr zsCjTV-)!KE6cb0%ETwKo*MZt!vMMQ5J_)SiNpQ|+G)n6%^tM&fsA(?Dr6}yrau89% z%4XrvPAe-4Va*FsGz`(;bnaDrnvs#9mp1;j-!?V@Nm8mT<77;>t5sILh^4=g}a zQLP-+zNniO>s-UTYVYl?_{M0;(FMe`QTyepX2x#BWqQ1tFi@3hz5) zBN3X3sj2$NHD~=OPr}gbMST48cBcA|Iw8@n8!RoYRwAMy&;?cB8wWkMsyC4sPzX|l zHl-D3$x%~!{XhBiiTYp3ed+Dy^=bUVvteSiE;EPf=NM=UOxtPU-pJvKvn4Ml^u+wO zvoD8tgHwzyi!E~8r)R%ksL{L=UXRY`w;W#2IOfy0kcR$D^JOG+buVi>R>c64*whC5 zYC5=`pPblSTD8xep}**c@UrcFDck!wi^+Or#lmHlsv_Y=&}Px%ZhF1$Oce+@Uy**F zSf8cBd&^~waTkKKVUT+TUyV44jh$HshjpnJ1r(rKHbpIu&_H9&Xxjf8EF~4`(Z-{ zTD%IBEIEDclF!$%LXI?ZZiN_%M-C|RRK71rgIT7Yw`n)T>sFju>xfFd&Q%wuS2pNRWg;VjRl9e6nBf3kB(5=J5njqQ+}85-r6yyU z)`G;*Q&Tr-Hlv%btakVr$hp4uDKkb}e9|JEPkb~KL`>3ESdsay7S%pD%cLSpD?-b> z!Dsi1CIiY-r-k+@dh(7JUe1JAm-@?BR9Nw~i#nfJH@x<%oNhMpB%=%~39Y=cI-!_} zyl7JV#_9_8YMAS8XyjbIO8@^Uxm>~G`sk*!d>3uA?Z}1^&O#gzU%vxc4{u(Is_7)?cZG0m@ouz<}6la zo-$o`FZztWc`V_DYKN+6^%jfELI#5%{!0;W<|pAKo7?%xtu&}QzIU^*R}E%moJ`+K zikysy=j3EsI*ZfOG&p6i5`a(kAD*Z?akn3OaK70LA78;aW`a2Qi^pA-Tn9@Ew|^;! zzN}SDl*+$a@bn}^Icbt`vvw8KSfX!}cIdmVdIh)tKqa&PpiiOZOW7;NJr7V@(99KT zLsk0z3B0lSoDTH$MN|Hb=8@~GX8bQ_kq-*Z_*?s;k>)A}vbq%JPf21zh{^3WytZ<)D}` z2P!p&Yh)C3Lv=H@LKJC6^)t5K^f&L&R?Hk-N)>-IeqBOu!)FDRs)He@s$fh+ExD*$ zZXqK-y{P;1nDn8>xV67JW2jEWKnA`Om8#C+`c-M2a?1m5ja0qNt&m8X486?!^peK# zihZVQAvUUhEgH6DYEMHL!hLzHUyB{+jfPZ8TP3Hgh@_RG_7ug@$S*A_Pe7Qp7|iPU z^PSj+?Gp}>%d52HW|Fbi8h1-B3NG&s5%sC?@3oU!I}JUSPU&^lAs}q`2*+M+B=u<` zJfNKp@O(Ndw`cf-6>O}IK9n& zH7kgLjHd95W>#0ihCY%Msedb+toYVYj6ON*jJ_J(la+;c%dnJ*_;pJIqTvEM_4&srPF9(>^EX*YLSoSUSJ)*5l5p;F&xOY zdzSS9*LJzn>LN2?M=@@FwBJ}(Czs%j8jNic?eFYcw~0KRs9t>TF%ghHD6>$O_C0*B z>b8eU#Afg7J%Z-IAHaf7?Z=`qcP~!TN7xoSig34`+nGBHm%rRe(5RF>bN)ppMV6~b z@V6r~8Nuqjnqo?&)Zmg0ncEY0F;bqe_l}=n_ytxU-3DTAAD^s#8_>bvP@7Dg3=7<> zJAE=9(!z4*P;>R-!;V9AN;4M0i}DwYjyaqbH!q?@b6(;~B7Wp)P3I(NoMLk7UDAFO zgN*x3xjb?9RpnsdV%N*Z#ANTquSMW0YoCmfm_5@^<8W!kjaoM#IVG~yw0=0)x>8|D zc{@LBk&Q>y6pOtINv&*pcDzOEHiO~4$MT+FVGs1qq*Yxe;NiVZFs+nxU*AwRJ?)kv=jlT)Qbjw({vnQ7 zzkEyoi>#)dEEM}?dF!f_FLwGZE-jKPQj(?b5#M=6sm$}FWVDWps%4H>bg_NV4wSN$ zWHEP1a{M7?=>$32(}JqIetnJ-!4)e$#&%iGv@nFqC zxMB7>wSKqFxQXOEXZ-OxYOKbSarM`gt3n1hzjLm&eGxp6$a&Hx|7rE>OeNNxMNXvI zY(b0z$(7+73Q4Ko_%SE>&Fr6Z`fL`(S$!K0dN1!F!;UPzJ6!f%O-|HLa*nC_@WQ;9 zHnBZ}Ge@jyb7bjGohosv$s{m5EPG3{*1yvLU)1r$|vIOTyn>0{$Tv1-JzOCVTsuI%kI8+1 zF0rkXASLS6RB~-Jfi?t8teRRoI71PnxUc#$E~NSueSvTdreKWF0m{kN>BQ0DorV)#jyut(h>9;7_%Z<@jc5XM2Y4o!FW!2*WVndm=dQ@) zqRoX@YE+r{cE)astB?7gc^;zjR`W#-&wgPv-{YrBcAu6d_( zAUkU;KDL`-f8vV|#3U6;%G_@qoe<5%W4XbMQkOmOP=+pCk&NkjF$14?&!XhvOkc`U ziU?2DVCA(02%JN zmf-&|BNoi=EhKe%efr-59siWohX&gH*KZKa0En{2WM)GH7hy2}l!o9}ZP!3zXuW97 z*%G}!e+B<;{%>snx@*1g`~2w2<&la-D2i!MgIRur4}GC8{00rX)f#Te^9(Qnkm?P16?Hlzbp?J%DjsX z&hP(E64BBASRw@D7Y8ag0Z$V7=Sk54IY4L~P%YU(;0tjA$&0D0(n$g@KC;N)tbD;w zK{CkCsOgnDySSL7fs$OZXt!$|ulcQM2hpG2iTV6Hsx@z%z^zx-iGxOk^J{G#J%(XYdWIbG*;CnpH_L~2eQiM8@ zR@XV?b-`|U?lUoicu01%Jv~}K<@qMfM<7D7q$AHgwf&68@z~Z*=^f&g-~D8 z{MfVYZ|5Mc3Q>x`Pl;QxT-13WG87(zT(LDXPN|G?3);n;-)oe(!>uWD4_P4!bB zMYL6GpV7lY;@)|X2~Sc~_u~AF2Sb~`Qyt;p)!|Jb!^gytWZzW^ zG~1na+U7~qDHKBjZTELrx-XS-7GAP>u+I)c4W54N_d)fw<0(f z+;&$SK@1>yGFbdy6>@+bkJ8tZ2ZwRz<%*@c#Jhk~#SlUNsM7~Wik=DNuHZ|%SCP)w z5}!cJO(Tj3y~y_~CHQRPqx1oxX+YzQ0#LUo69cHV6X?7FYG%Zwg_%G^2_Ki5@0%!? z{R}BQ+X})!swVIdks{zBtUv8%>kpgym#C*^na?8s&Kx;YLiP_O@Tr;A-mT>`Q$sWj zL`s01sjmW?lCt(LKOz)4CI5M?ix!sGc|F2GqudSJeV3`FI}xMizbf<)p&H; z?vk77tDVyuYQY(BdhM?GxUs(YIpEydU2^f?fWOQJ5QPqlMh8OCA-`E|1a+~%avS zglQUv^m_~lZ+!e8gttBZL--lVg@I(?AHvPlC^zq#nNj|av=WBGHZy$Kl;e*9UZp<% zpOLWr3`d%&@dI|ijQ@W|!uB(Otk7(Wf21b9_~;z908S=9I!7&F8v?B+J3@0-JF#B>K`)|AEDfqu-=6^%*3 zN6+?f_xFZ(A38-vF|F>1zmv4IR@$z-U5s+GU8mRDqjP>2x~ad5k!qYCMm>LEEgcxD ze$Pq-wZJ@*!a^}A`--<`OB?5_QrgK=P7^W;2W;mLi*7jAoC8@xjul9GE}I%Zc402L zTRnkoVU7j5CLuQDjuO~kOxJ4b^R*T3#uF>BuTf9UvR{r*SZ2^zNV#iWNi40kYo?hIs0YQ`w58I$W9a@Of-k0*lWeTMe z7Q4XZG3!m?M%%5ZkgTPY+j2Xfhns7T8;<2Jzo@L`L6n*C*dG?rd;Q7Wf{qYA_?9y> z`_4^vg^$jhUIe+s1ESez9wVootoM@_ch`wmz3qvnO8uv7xC7p8(>S3mEz*WuV7kcG zMoz>WVL2Blyn96&i+qGGJM4pOGzwkPC;XSVA~f+{n>WB2NMhY3d&%9=O)Vvn|VHdhlKG$R05!n-N;7_ zm$(y~obrk?i7ykvvq-#VYS^S}b{!XSdoi30ji?;6Y!n!2%r&tn&yMx8Gf!BeJr{^p z6)hA2nxM%3?;Td*yHi-AKN~2+0URHeC?cjNUb{bgJ&Ji-nXLb(evhWYre1T1dOiYA z1loB^01aP(&XHS~=%zWd=j#scU`m@xO``o7yecdKWKI`?MGKoj|3A$le<}os%+G^8 zga+t;$=HZVUAWUYch16J1HxxF8vjXy{L#@$LZS%h82}uqCYa!Cgh>SCsF$sNPa=R@ zO4!JO;8$Q3tT1xdI{d95uufRH*=VMgn*kkv>xNZ$4QO|%^sDP_tGrskB>PRL`nZ>m ztuJ`_`PN_3z(y&^Bgr4aSfi96azf^WgYX zu3hX$4$?A}#sh;2jazce?`?0T1xvT($xv%h>rfReKqOuo3fKnfb(G=HJWy>ie^U0! z==k<_skUz)i-NyQg2C0*S5Iygqy-PllV45O4SjjzZq!up9gO}b?A(O;kHhC;XffoU z$qwsc>*V-HNj#NMaQC+V0!f<^prmFl!uRInkPv&eJsA9i9rEBy`n=peHu=!E)Eew) zMMu`t=L0UAZhAcp==^=X4zSN>E1VF&D-@9_5jf&+4zuUPNI1vaP&AI2=Aj14xlaeR zx|yiISnD%S$I3TDl`{;2>aTi6bm|6b1Phqxq)oA-PD;2o>y9PWWZ-LsFHEAiOohfa zjNlO-*i`q--O8N@%>>o!_P&gM7L3fdTio~^>(P{{o%c&R7u9~_g?>SBk?1Fl);u-c zC|vT$@mBp&C#1p%P*d)Ec^Pb7z7|IPO<{F1F_8cikg-3dbWn<>6bs!Yd@~N(N%iW} z)wumY$M2-(@>O4VNW5}I9f^^dSI88u94J-Ak35O{D!h9+_?dOX$nCG2yw^>ZpziBD zE*IyJ{K*0?_fA)Z+*0phruM$_Tz=AnU1DcH)zHmOAPC2{WtV;RL)A+xL5$alK6rHy zPB}BaYAf|N%Uh%@>Ka)EY}*g_a=W++bzfpK1idcWi5ffVGBwvxz51!z=Iu%T<+rTg zzLT78@(flb;#u_D?DdaK8@p`GoyhSB@@#om&b;3}sSm)XYdoAaj9`hoE$vFlxMmGHV#-rnyF`6LFRZpV6NNT)^7VO%DhQ`&cx_VuINAmjMp@h~) zl8!FUvB#)u1KPQGKpa&5ciwW$eNE}Nq*YNz>OeEAjiz`9$M&myPpUO8EQA|4mfrcw zemzR+v2UmAZV@_EjVo-U&S*JQzhZxOL4&ltvJXz@T*xVyBMeLCcO06pfF&lnbEOF zkV!$V4;0tI+T`k*XeRp{sDAYzfp_6e9iKqvl1HDlUR)x%{Jn)MSu*^}LXvAU9ax)F zPTnnOiyyVKRC7GX0ITgV=;RG&Xuodl)XBRlv}hPYjTuPKBvDM*p}Oksjpa& zx@xD3bNVX!n<@(XJtU`wb-@TJAXq=7c|b7TFO*roIwhn2Z4Vyf^PtH4d_l=FIJdJt zGD*GEWof^n(BF`A-S#*=@+6+cdQH)6-_$TUK|hO0mxHcLu;-aw)Xp z`ZU(wi=_9YVKc9dBL!X302_~QW#!<@k-tipHn6H+d=~)HufQbsQxwWV-GB8lZ9-Ab z*=B?Rw9oIb9$mQC{;F!Up$oa;)6K1CsUqq22K4lv1V|*VnM$!%B=IL8%-rYkdwuQ{ z!mHpEf+9EbSf-knLS!)$GM_^y0V3xmafrX z8Okk98bdD;S!$teRn9j$UTS6v#ZC>^!^O%+XLpTWSPSu#WIt*fi3oEF=S&l>Z1(>^ z5wr84p?@M=FEE@U_73Ra-elvV0ZElUtGN|U?z1J93xt{Go&rBQ3yP=CoGt~zFdb<6_4^gt=p;Hrh&gV^+kv2!E)w`~`M zS2K6`s+3(el#eZUqw)^847iyL8lF1Tpv!BGk#5P{0%e-snUk8UDjO@FcU`N*e34toEV!8d$cVdxy>gCVcy^IpS)vc~=wi16TbTHV z5%d1*DsNuDwEa3yDAz%@w5v#^Xup@&_DM?9cEU@SpPu=)<11{sq*`XBh8Qf>cr~ZO znm9uPi=bxL0jrWy`PEh*Xk_V7QTaeo`2(j%CleMK>MK6r7RJ0T zxl%8ASpLekT!m6+?dztuRD71p!*0&2o-`r>POMl#qo8yem#_XwM;{%}{G2~7t~t#; zoj@VYu4}m>yO^dETZr0;!>*Y*v%eQe1p1u<7quQnVZaFhD@khh|8r-~X-4e>M56%t zk|@-f#+GInpQ&a|&sR}5mHkXrX!(0J%ro(#Pyj8A2@ITSqfG>srPjQ$M)$YQ>i>57 z{F=Qe8*C1+f{PpI8;u)2m_VoY?6tSMZJ@O^vm8Xl!T=$DRw!$m*@eHCX@(D}yAf8l zs|f@j5|Ba*3<TIhpX46#-ZZm6jvjRh&dosoRn7RHhp+;< z=O7@tSEK{O6bPG#YsuKBgZ0{9hh*I1|A&@-KCQd62hdU%Q0oiDd)I`Os#*9f#c*wR zlg)$FOD)ngnTsG* zUKZ%E`>*n0XRFuQBg%B~oov$}uMzTn3ISPOh0urUgX$Er0{0b^L(i9K7!)x=?x*-! z-1t||-HHxlQ?%YXAo-3&lnAWZ_JV>Ad+W5bOhlT=qTxGJf?WgIXR)4Z-KN3sLgdk3 z(Qh&PD-Sj0q8lBs^2ph_yHdYvyEL(P*3#+MEQOeayRy4GMRS@ruYpj_EPXnFWVs8u zTqCBFG4IpSpBMkRl(jCwT$8mU(dec@&;MUrXW|WI|Ne0l*&6#UlZVJC%h(A?wutQ6 zmn_8yqin-SvSba}w<3uVlYJc`BL-9Uu`_9sv5Z|~`A+Bgo#**|zt8gre6Dld_qjjk z-0$mppVzzTWo0wv*8jD)qFml#{jY`w=h7ssLZq}#^5G<0&k3ED6fU0xAMc_22gdnC z>z1=hsq2})Mq&dt4!+aM+~Eyy9hXBbx@$C1?BJ{2*I7X|?9W~rR$CG|Tnu$Q3?}B{ zvvH7!V@I>hKYEQvdavHGcq_UEF9^U|`kMO-;A`TeDk>EHsjR&uSU*G@&R`M`5{GZ{ zXI^NY91+&Syv~8q%+F~A3p5ZQ+iTYzO9>nroMl$z8x&^0BW*TT9XW&R- z>ur9CY84XX!DP%4k;XYA{o~u|_bC%Ic|>=u!ponwmLwvgQE|l~jS!_%BNU8(HdC4q z_5$PficP7|CgS*IO|+wMpFvuPoBGMK$*$nss$@ZbM_uRMyt5MqgrTL-&+49-1nuhz3hM8veehB8310@QhVA-w4r_ zv*C+08!X^*4>AQ0t!w4fK&MmijVd3^8H6_ zW0fT@wsMxEh+D(ta*@2ok;<_d;$opYQ`eH}oz)zrS@`M7_(jo!*dvvbh75UG8?R(1 zmD#m{pymuX`pe285E5Fusp1ke_X~aHg`>G|TQ(Ta*5KjP%e3b#+HbQKUAvpLvh%$p zT>bgPv~)zWCS1z?G-TV|CEy`8U#j`Nl9A zg*trRkg%K^Y)1xs3snJsYPB;dqxFWiJIv44O(?CdG_{}92-PZ{;#V@mA@`b5d=W=8 z_PT`&IM44XZdEq7_%IB`&@9=jFEr0;ijS;Zm^NO2_!a_{cc;f@;JV z_B;xbgoDka0V0;3B_XdL%%e_xVFmhTSVT@xYrxT6^jG1tBgLDnl43Pn9Q<~b=*Oiy zMo3OW2kLqT1sLd2EnYrS(6g;{LxaL8@XYR4Zo_C7-gH3#W zvfuzgv$4RZZ}RB!S&2>|T9UP54BzC9mqwsv*Ss+!%gziM}76RiL)^+=A!;#0K&qF3Rj@#w{5qDBLn6%ZWkE(fmlqUbI!mR z^8Isq5K!-nwCre4pR@?QTtHV#@WH-4bnr;z$@cR!W|_E%<^A%v495HsAAzv~b}6iV zHm7_UqjHK5;4nV6O@hO;b;U>Y3(=0m+X;P5XeqI9BU}?+Zl=P3Y{zQy?S|-_^N^+| zO`Iw$D7f~0DHI{^VBs{lB>R#591gHLc^8i zxVx>xTrR(I$j9hc?fUr1NcMv08I6_g7}asbw?pT&pOhXE>ERCeD_FXN{Kip*In~Wu zGFnzt6=H!J`4+Vz4J2Yw(kxE(2^<=TdXf(D+1s8OPh9@czxzvudpWY2m(90%Rojt? z+-Bv9@xBwCnv}9kEfpZT1;dzz41HDSQK{I5<(*nbh>#~6asyrPFWm z`z=9`EgsS<#;;Px3~GXhllR+9ds7xal0*(Tb(2h9DbK(PJz+QMUhQmH?eBIicmoZ>c-x4RCS%o;WAxM?z>a(w56|ivS`(E(_pcd z(lIXdnOVZmx^{UG!n9Tlx5AH#pS?H8^4*x+6&3L1(we^p({m*!kNUX*np*V^)ks5D zK8Z^C6nk^5pO#`(nV{+^;UJ#<_9Dx`rftHxz#$Q(8PWOe5da{h28w$rH|L z0KUJ|S8r1q?r9uj9iXFZXX8-v;w9|VG~rSZX+I;(eqF&=!GuLyy)D++i;Aq{!q0Fo zTqKR0OO5^@+U1$gHoszth_nN0iBr!Y&5dZRVXw0Q_v#ZZG&mFqW;zYV7rt}mGKk2B zV=h&c`2xOla}it1JH?T9uks0bFdL?8YHRHu%i7oYi**x}W~{IzVtsYAsry(=97c#+ zfO*$-894w{_;3jE7GAuq5i01X;9)gQ%D9jJ7To1^s%ZQqiIJY`g;_?XQ=!!jMDYua zhtQH9b77`vyCbD+gy47Z<33Wy6ps@zA;Q}!jJOT9&{XD*EnSs+Qmb_L<5hH36;B%; zd%OEIGZtHCXPwn97pWkbCrx0Y2B0f3DQjW}JV%o|=juegEU;5@c40&QoAEhN{PhQ9 z`KyfnxvAI_+Vy@NuyS`wj~hrsAm;+`j_x|4xa|k-IqzHTju7>9)lk=asrI;T z3G0p)&*PAi@K%`5(M!uttEln?+*Z7bpqTkIedF5W5f@AcF!_K2ko$yJr_|@6L8^*nOu5k3S3tIIQ?0#$ezjqS>qMGy!9X|I>0AVv)=)> z9wtx3KF4;-p5u!B;uN=PS9bS}naI&l+m9vR=D8uWj_&To)@y>O#YIFtn`JU>Nw5=R zfpi`!swi(pULB8HIc~@@YH?)8{n|j~G4LKcekw(;tR|-m!S50HfEw(BKGnprM`gZ( zsJZc@Rc5XW#75~dl?rxw))o14KU%*GUfG)+X%rzJ_s7NHiPuOntB>ZsSrRCY>xmE? zH6wege=Yl1an7-M=deVI1N>@orBv#PG^q%n(Be3a>=?{j=BKgekZC;Sb2_V&ju>g| zMbyhWZ84!Pxn>XI$dmPl=>6))&V){@th!zQr4XWJR`znY;Q4LxTo9d_{U^|~CL14U z{0HVUjae9uO*iKNm(_^k@-cA^a`@}{6k@n+0RQNg{sf^irF#1SoxHSQn9Ya}9+}*z z3(ejx9$loIq)EcXVh1AG=gZHZ4u*I(*nemwN6-lrjRZ|H9i_T#Cnxm)Pml2>nuS5+ zKJuT|h5rGt*nj;<@vbn_Eo^V``U6zBq6RWYo(JmI$XWp( z9h_}|zu_SD?e*fVe64k*Oma<&W0!OX&d1*Gr=8%O`PRwyEaSu2aNWH-scNsEIhF^l zQN7>f&FkzxI99*c-~uW3EV$Eme2f$6?~{o{Wb zp(KsS)z)lH&_hWCX6WM5KV=Zqbc^tJH2UwYkN#Iml)5bClnDz|7C*|gv=j98-}vai zPg+pQ{}=H^f1Gkyv9<62*c7mZKi_z-bvsk@|<=sD9ANXUM*8gsZp}rpq*m`aP{w(qP@osvMZ303#&+!Q~HGkqEhkhf|E-Op+ zkd*~4FN;#*4Ji`x|0EyfGCf>F4^bqc|4-wgbU^u> z`fDhG0df@R;qNg`U_b)4N`@Yqe6FUl_WVDzCxzYD3B84*8@InsX@SziC#!jHyfQ1i z;UvD~r?$}3J1Q;^TJ3jr@wQfhR$_1vysV45>}tZMa#m-$7zRZaId#)x3mY+KGf*Ot~vPRWF&+-jcQ znSh~`!dX@XWFS(5f--f=|)6-_AS^X<2;@t9|`x~0noQ;z&^ z{SCkFru32-*X_sk?URMn8z%P0y3M=YGDSM#y_ueLV%hS~=i`D)YTP|+7aeskXZF;r4H@lapypkG=xCLp+4ps|jn5^w7+~5O>sk$DYhvW+21a(ifB#euxJ2K(%5?5Ur?2z zzE(L{knyfpAQ;gJZ`AT3+%#%Z{J_yC9)ERg$D+ryC{60UB5m}2DkbTc@RU%uGC#lyu-UmbY`j&=5U{nz+Jr_0z)*WbG-f8ab}u_(I?wj0iyw zHDUQi=hE{xUba7%uT@Hd&eut{`0Nj#?(B$-6vzpgi%yG?H}^F69Di1WG?-}BsCkHs4`Q^tG}XOB*fwh&@@Pf%S*$dYYRx z+E+iBnhRos%O&Y6?0J8DPD^^&YJ54Ui6}91|FK`O-cC*QuNGb}5JJp5$lRx_jj<(? zf45v0Hpu|PM0j~OjN~a+z0O>lFDi2+x?~1tUqWgsyUft>>(t5LxsSJG9XWZzx1d_G z6eLU|x2Hho#%z_D4wx_-ZAj-%SefYb`^rCOTcb)OX7;w=x z_|OLRt32!U&`5_FGkUJz?puxA!^l(v=p>8V!Y5mUdD2qHHG;?sJf?5{(^s&6T_Wb< zNjao{m8U>@J5n845aJ*6%PyAX@noklGcR2;X|(wa>U^Migv~V9_Wjvu1-s5LjV`ri z=D;68%o?xdmU-Hm4)UxD-f7k$6-1^T9X zzvF$~JKpovo`B~Yo+0{#$Iu%Q$6Qt#$o3k5=u`KFRNm7=W zyebrBk(nN!ewK?rGY(P%QVSZdZ7}Pqwlb=yhPZXQ>^W(ji3G<26WE$CF*9|Ui{Icf zCQQ8W0P>Kv1VobXfGx*Tfw(a>6E>m0c>?GkyJ?AjJQfEGuuW0P??L^3>(nE0z(0*G zo%+O;>t?dw2h@Ysun)(8I5Z~6XReH!Azx14>xZr{Pdx;afQv*~$-D-y7m5Z0L!aSwU0PB^VU)Qj!KBfuZ!kQp9CA@)RE^QZyt*bb@Zajkc|%f_ z(RE%^V1mKi@gK*YEAEV&R(Ov`5IbnY9Ch5NMWawOvcSJ8h+5L57t5KC5FBq>!ZDnL zE=-5v7EaV~l$2~vUdamTx{`&(DQ6>`sbfTj%a&w_z*q>U!*ByYt78FVAp8rmZ9^e( z58-{n8t;HV@(#CD1MkH`)<(`#!7fI9xNA`#>SELfyB76?Q3JY8+3M^m?i!;sA=21On4N*6iM8%AeAs;aE=t|R! z6l6K8@rt14L-m(v{2(rXN}S44{ZSKsZubE@Lv`!#pcV{#aS|CxHn2c9yYV42;=L^s z=a4ve5aOH}ac|4SStQOLgg9$Lyxh|R)KAo>L@TZz7f+$fL2f3q;^NacrY9#SO}N2_s~m2zQJ|J|8FS>;rRcjiRbV5|5PpH`2TyvE*$@VC!FH=|BnB!G!=kL zIR5`(#JU{+|1eN@{C~&)cl>`y{h;gb`2Q8h-|_$V^#7lpFo`~(|9`*hHCJ$R_`P9c z=$)a}!8-%*_J7dt4*307e6RGq*LS}6Ti)M!AL&{0yz2gsdm0`-s#n>?LM$baZ#t^j zkVM7cCWJN|#yzq%4mGIiSroX-!nlS8K4UdYc_(m{|!%ASt_I@{(TBkqe6>IBr?g4C6piPY;yKx!WYOX#V3jqyPf{IyBFYj#&_4d{i&wNIEV z=35^JMuPl~+G!=@oxprIG#tHDa%}8cc+7-++5It~f81)u9qXLAIMf)^t5BXA=Vl`p zZkY0LsvSIFFK}_wN*Kb!xH%6WZ37P+7M*j@n&U7X*@K6N+Q9?q3#|7x?TcyizCi!~ znClH!@Z|8zL;oH8=fL0k-wM3#|GV# z_kI?H4{l4)^|Mf7esJ4vm+N12Rps|aI9tkmaM z%J6r-7syr&KC~(gsbV9li|{6V8kwkvd$#*OLk59r35Nt2coFbz;Fj7OiE-ZG&A|w_ zfJU-?V3fU|hQ;@orC4Dkj*1vtvv}dU3h~0MAT2JM>B8s}I5x|dpid^Dgsr8q$>Ev= zW>^%;zoxY!?#cjXqNu|j1x;L%bOW|^pjndDL>@MJT;^9qMlV7<%~*y*UtsvaOAN0m zYVBjNHB8j9>1hAiYI1h=afuXnt(>R{lrW4Dv?_4wlTIB>J6cY?FKA z(0(H*(ncd_FakzUa08V=IJIB4vLWc%pbTPB*r}JsHn}+?E`lvVHb=s?bO|@IGkR74 zI}jBfZa0OjsV*uy*u-nFw;Oh1>kS5KIS>YR2G%XHgX1%XW%x8^G*K6c7q&ky0!K#4 znF=%UmJG8P?!pFF5%*wDD44~RMKGxDMt}r-izMM$dq#o%|BdDjFUw$ueF$A00j+KI zCw)i^IZ4UMMFF>{D#Saun_%6LL;wGz>)WoNXV?ps|C0mX>;F^#!-1dqU-A9G_i*2j z`?%g;_GY}l@m}ruV-N3n!?Wss-(7YG;3M{2YtO+D@XbSfY?4bhVGcvWn`Fpg(=LDx zZ43rL)%Hb?s!)`5v0_THH*qxb@;bkvGi>z$fVI!tO*fpP(!F6j-6WOnv$oSsQ0ZQ` zoo<{;_nPf=V^q3xw$qJL>CW0tH$tU5V>{h2mF`vB>2g%M)3(#4uUAuc)8**v)fL<6 z($}lYw$r7rSCh8WrLI@o{%64c7}(aq{%9^}S<{3pmky)-!KEYY-Zm;6s*#2BHOymm zErjZ#?Xyz1`#uLy_*#b|35Q^?X=u9~2yLS8#EbRgc@CPxtPKdvRheuMg-6T+l!>R& z4ld(qBrQk!q7m>J)7ZvM1C)}&!SNp4e57rGzQm3JM>DZ5x8ZrEy^W_%^cMa#$48f_G;Jn+OUYUQGD*7!lr5M4TpkGcn;q zl>UM}(l-+lJ~Zjk|3BfHcLl#T{QcpRLq8n+$-t}qzYn|_$oqfc`>k)X@3r1Pd*AZ9 zdd57z_B`W$-979213Z3^tF#K1Q?PkYz9F_0W+BG{x;qMb!^E4XTdAc&M`%+m)sor~ z+Ei<`q;!Nf)nYB>J3^c4WtZfR(58CY<@5?JAmytk(L#!~R$j3C?7p+tl-jv`#Pnt$ zq2F+j-+TgWBogRr2noWWIE(=&0^(K=mKhmgAY5x+Gs+8Vuo)lD?z?r1tbQS4-o;uA zb8;N12_U!F=GjWQt0q9~QDwyE3lMbGu>@kiR{DCAS?25cPa#+Vo`BT1RM8lUb!=M`%+^M@vRWXj5bN SCA}lGsXll~>j-V?y7oWh7GPHZ diff --git a/impl1/synwork/distcomp/distcomp1/distcomp1.xmr b/impl1/synwork/distcomp/distcomp1/distcomp1.xmr deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/distcomp/distcomp1/modulechange.db b/impl1/synwork/distcomp/distcomp1/modulechange.db deleted file mode 100644 index a055fd70b1c5ad0c2d9ee9474f14a108741d8199..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeI%PiP!f90%|>-Pvs0?9Pi&$Z2KDTH0W;FPmD4X^f2;p;&26HVPKH%+9>czGh}; zI)Aoq!NcOwL#qc7dhlGl34&e!r=gK<^*PPi;rMUwE68 zkNsJYXLVzh&`*pz#wtCr-^KVI0uX=z1Rwwb2tWV=5P$##4w%5QJ~Dptq{d^b?sCs} z5|=wX;4LTGb&!2+d1+OM}nR2_f$$p!oI=MDSH#|eqk=3PQnjj7Ij*3qPB=T?BdkSbY-?Y{nFIRr3#bVH`aFjHI{f` z&9(yJmD`uEeqLM{)k#NZgXKmx_e3oa0guX2yLtKF=l)qZI&{8Yzsl`6lJ#Z&+>s&1 z-s}WCls9lI_uOHfd@#V+C5i}G)8>NRkWCaP^|Xi57jwD6s=JBJTQLjd>>b`vBQLF- z9ZA>S6XmvYxgDHIyfbUPj!eASIYNS<$v+r6Hn;IOWat<*|Ee5<%8oVq5Pp(U0kl#-r=E;kIK8D70C5gt6scR zZeQ8B^@G~~%Rl`I{hR(p@6+GuJ^9|CKhp2%cl0j(ntu6Ie&En41Rwwb2tWV=5P$## zAOHafKmY=d70~k;qHXGk diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P10357.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11069.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11184.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11339.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P11871.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P12447.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13737.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13855.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P13908.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14207.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14481.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P14525.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P15089.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1553.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16032.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P16159.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17025.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17528.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P17685.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1811.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1815.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P1816.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18740.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P18777.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P19659.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21221.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P21342.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22066.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P22949.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P23803.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24022.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24138.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24515.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24554.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24717.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P24926.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25101.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P25372.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P26023.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27368.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P2789.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P27961.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML deleted file mode 100644 index 695f551..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28205.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28730.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28831.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P28916.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29257.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P29449.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P30679.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31655.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML deleted file mode 100644 index 8f01e54..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P31773.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3318.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33223.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33269.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P33488.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P34176.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35393.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35493.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P35891.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36431.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36567.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P36968.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37025.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37272.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P3730.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37316.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P37711.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38022.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38264.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38281.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38532.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38581.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38588.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P38636.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P39927.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40534.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40681.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P40902.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41215.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41268.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41682.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P41956.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42114.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42430.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P42943.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43492.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML deleted file mode 100644 index 1764a2a..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P43796.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P44243.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45555.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4568.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P45916.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46449.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P46932.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47032.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47147.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47440.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P47660.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P4769.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49489.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P49913.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50169.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50820.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50866.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P50987.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51115.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51253.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51276.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P51676.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52823.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P52884.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML deleted file mode 100644 index 695f551..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5314.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53189.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P53679.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54450.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P54711.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55086.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P55200.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56321.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56637.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P56890.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P5696.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML deleted file mode 100644 index 695f551..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P57194.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58438.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P58948.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59000.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML deleted file mode 100644 index 8f01e54..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P59193.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules2.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60160.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60506.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P60927.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61602.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P61813.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62596.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P62978.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63085.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6329.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63355.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63396.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P63760.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64169.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P64713.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P6484.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65366.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P65389.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P7786.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML deleted file mode 100644 index 695f551..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8240.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8636.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P8653.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9058.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9311.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9412.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML deleted file mode 100644 index 07ca1bb..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9564.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9837.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML b/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML deleted file mode 100644 index 2cd43a0..0000000 --- a/impl1/synwork/distcomp/distcomp1/synwork/syndist/_CMD_W0T0P9890.CML +++ /dev/null @@ -1 +0,0 @@ --orig_srs /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs -osyn /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.srs -realtop -distcompsynthmode -cdc /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.cdc -mixedhdl -modhint /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//_verilog_hintfile -prodtype synplify_premier -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -I /home/hadaq/mmichalek/lattice/simplified -I /home/hadaq/mmichalek/lattice/simplified/impl1/ -I /opt/synplicity/O-2018.09-SP1/lib -v2001 -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v -devicelib /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v -encrypt -pro -DSBP_SYNTHESIS -realtopname top -noobf -auto_infer_blackbox 0 -proto -ui -fid2 -ram -sharing off -ll 2000 -autosm -D_MULTIPLE_FILE_COMPILATION_UNIT_ -top top -lib work /home/hadaq/mmichalek/lattice/simplified/top.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v -lib work /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v -lib work /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v -lib work /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v -lib work /home/hadaq/mmichalek/lattice/simplified/modules.v -liborder -log /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp1/distcomp1.log \ No newline at end of file diff --git a/impl1/synwork/incr_compile.rpt b/impl1/synwork/incr_compile.rpt deleted file mode 100644 index fc9bb81..0000000 --- a/impl1/synwork/incr_compile.rpt +++ /dev/null @@ -1,79 +0,0 @@ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL compiler and linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -Modified Files: 1 -FID: path (prevtimestamp, timestamp) -36 /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) - -******************************************************************* -Modules that may have changed as a result of file changes: 8 -MID: lib.cell.view -6 work.fifo32dc.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) -34 work.hades_LVL1_raw_out.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (module definition) -32 work.hades_tdc_channel_raw_out.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (module definition) -3 work.output_decoder8.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) -4 work.tdc4ddr.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) -24 work.tdc4ddr_short.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) -25 work.tdc_channel_fifo_out.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) -30 work.trig_inv.verilog may have changed because the following files changed: - /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v (2021-06-16 07:57:00, 2021-06-16 09:19:06) <-- (may instantiate this module) - -******************************************************************* -Unmodified files: 19 -FID: path (timestamp) -12 /home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v (2020-06-02 19:47:55) -11 /home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v (2020-09-13 16:38:29) -32 /home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v (2021-02-09 13:19:26) -33 /home/hadaq/mmichalek/lattice/simplified/fifo_colector.v (2021-06-09 11:46:02) -35 /home/hadaq/mmichalek/lattice/simplified/hades_modules.v (2021-06-15 17:59:12) -0 /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.xmr (2020-07-27 07:12:33) -31 /home/hadaq/mmichalek/lattice/simplified/modules2.v (2021-06-11 16:48:17) -9 /home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v (2020-10-21 10:28:14) -10 /home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v (2020-10-21 10:28:25) -28 /home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v (2020-10-21 10:28:36) -29 /home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v (2020-10-21 10:28:46) -34 /home/hadaq/mmichalek/lattice/simplified/top2.v (2021-06-15 11:39:51) -2 /opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v (2018-11-28 06:10:43) -3 /opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v (2018-11-28 06:10:43) -4 /opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v (2018-11-28 06:12:11) -5 /opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v (2018-11-28 06:17:48) -6 /opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v (2018-11-28 06:17:48) -7 /opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh (2018-11-28 06:17:48) -8 /opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v (2018-08-08 09:43:25) - -******************************************************************* -Unchanged modules: 10 -MID: lib.cell.view -7 work.UART_VerilogWrapper_TOP.verilog -27 work.fifo40_dc.verilog -28 work.fifo_colector.verilog -33 work.hades_tdc_bundle.verilog -1 work.pll0.verilog -5 work.pll1.verilog -18 work.pll8.verilog -19 work.pll_random.verilog -26 work.top_tf.verilog -29 work.trb_adapter.verilog diff --git a/impl1/synwork/layer0.fdep b/impl1/synwork/layer0.fdep deleted file mode 100644 index b564550..0000000 --- a/impl1/synwork/layer0.fdep +++ /dev/null @@ -1,84 +0,0 @@ -#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946 -#numinternalfiles:7 -#defaultlanguage:verilog -0 "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" verilog -1 "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" verilog -2 "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" verilog -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" verilog -4 "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" verilog -5 "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" verilog -6 "/home/hadaq/mmichalek/lattice/simplified/modules2.v" verilog -7 "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" verilog -8 "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" verilog -9 "/home/hadaq/mmichalek/lattice/simplified/top2.v" verilog -10 "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" verilog -11 "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" verilog -#Dependency Lists(Uses List) -0 -1 -1 -1 -2 -1 -3 -1 -4 -1 -5 -1 -6 2 -7 8 -8 -1 -9 7 10 0 6 -10 11 -11 6 -#Dependency Lists(Users Of) -0 9 -1 -1 -2 6 -3 -1 -4 -1 -5 -1 -6 9 11 -7 9 -8 7 -9 -1 -10 9 -11 10 -#Design Unit to File Association -module work pll0 0 -module work pll1 1 -module work fifo32dc 2 -module work UART_VerilogWrapper_TOP 3 -module work pll8 4 -module work pll_random 5 -module work trig_inv 6 -module work tdc4ddr_short 6 -module work output_decoder8 6 -module work tdc_channel_fifo_out 6 -module work tdc4ddr 6 -module work fifo40_dc 8 -module work fifo_colector 7 -module work hades_tdc_bundle 10 -module work trb_adapter 9 -module work top_tf 9 -module work hades_LVL1_raw_out 11 -module work hades_tdc_channel_raw_out 11 -#Unbound instances to file Association. -inst work UART_VerilogWrapper_TOP uart_top 3 -inst work UART_VerilogWrapper_TOP uart_top 3 diff --git a/impl1/synwork/layer0.fdepxmr b/impl1/synwork/layer0.fdepxmr deleted file mode 100644 index 37d628b..0000000 --- a/impl1/synwork/layer0.fdepxmr +++ /dev/null @@ -1 +0,0 @@ -#XMR Information diff --git a/impl1/synwork/layer0.srs b/impl1/synwork/layer0.srs deleted file mode 100644 index 4b7af3d..0000000 --- a/impl1/synwork/layer0.srs +++ /dev/null @@ -1,5557 +0,0 @@ -%%% protect protected_file -# Created by Synplify Verilog HDL Compiler version comp2018q4p1, Build 004R from Synplicity, Inc. -# Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. -# Synthesis Netlist written on Wed Jun 16 09:19:13 2021 -# -# -#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946 -f "/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v"; # file 0 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v"; # file 1 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v"; # file 2 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v"; # file 3 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v"; # file 4 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v"; # file 5 -af .standard "01"; -af .is_verilog 1; -f "/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh"; # file 6 -af .standard "sv"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v"; # file 7 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v"; # file 8 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v"; # file 9 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v"; # file 10 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v"; # file 11 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v"; # file 12 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/modules2.v"; # file 13 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v"; # file 14 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v"; # file 15 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/top2.v"; # file 16 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v"; # file 17 -af .standard "01"; -af .is_verilog 1; -f "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v"; # file 18 -af .standard "01"; -af .is_verilog 1; -@E -@ -ftell; -@E@MR@(j:n::((4n:4FRIsB RBBz.RsPCHoDF;P -NRG3C0MCsN4DR;P -NRF3VsDlN_DOCDlMNCBR"BBz."N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CRB.BzB -";NFPRs_HoH0M#_RFV"zBB.;B" -RNP3MDNosuNNRl#"QQhaQjRh4QaRKQh 4Ba_QjRhBK a44_"N; -PhRQQRaj"'4nLjjjjjjjjjjjjjjjj -";NQPRh4QaRn"4'jLjjjjjjjjjjjjjj;j" -RNPQ hKB_a4jYR" ;1" -RNPQ hKB_a44YR" ;1" -RNP3M#$_0N0VlFsNH0#x"CRQahQjn=4RQQha44=n;R" -RNP3M#$_0N0VlFsN"0RQahQjR=XQahQ4R=X"N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3oI_O_0sO"HN;P -NR$3#MH_DLC_OD4DR;P -NR$3#Ms_0C_N0NL#_D NOLRFG4N; -P$R#MM_kOMFMCCO08M_Hb#k0RQ"Bh -";N#PR$DM_HOL_CRDD4 -; - -@HR@Uj:d::gU4d:4QRBhQRBh -; - -@HR@Uj:c::gU4c:jjRqR;qj -@HR@Uj:cd:4::Uc4AcRjjRA; - - - -@HR@Uj:c(:4::Uc4BURjjRB; - - - -@HR@Uj:c4:.::Uc.7.RjjR7; - - - -@HR@Uj:6::gU46:j4RqR;q4 -@HR@Uj:6d:4::U64AcR44RA; - - - -@HR@Uj:6(:4::U64BUR44RB; - - - -@HR@Uj:64:.::U6.7.R44R7; - - - -@FR@Uj:nj:4::Un414Rj -R; -@FR@Uj:nc:4::Un416R4 -R; -@FR@Uj:nU:4::Un.B4RmRza;- -y--------------------------------- -@ -ftell; -@E@MR@(j:n(4::4(n:IgRFRs eRpmPHCsD;Fo -RNP30CGCNsMD;R4 -RNP3sVFl_NDODCDMCNlRp"em -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"mep"N; -PsRFHHo_M_#0F"VRe"pm;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3M#$_Ck#sRLL4N; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03DbDj#HM0O3#k_LNP_DFH0M#"N; -P#R3$DM_HOL_CRDD4N; -P#R3$0M_s0CN__N#LODN GLFR -4;N#PR$DM_HOL_CRDD4 -; - -@FR@(j:n4.:jn:(.j:4R;ZR --y--------------------------------- - -@ -ftell; -@E@MR@(j:6((::((6:IgRFRs eR]QPHCsD;Fo -RNP30CGCNsMD;R4 -RNP3sVFl_NDODCDMCNlR]"eQ -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"Qe]"N; -PsRFHHo_M_#0F"VRe"]Q;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3M#$_Ck#sRLL4N; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03DbDj#HM0O3#k_LNP_EHH0M#"N; -P#R3$DM_HOL_CRDD4N; -P#R3$0M_s0CN__N#LODN GLFR -4;N#PR$DM_HOL_CRDD4 -; - -@FR@(j:64U:j6:(Uj:4R;ZR --y--------------------------------- - -@ -ftell; -@E@MR@4j:n(U::U4n:R4dI FsR4w71Xd7RsPCHoDF;P -NRG3C0MCsN4DR;P -NRF3VsDlN_DOCDlMNCwR"7d417;X" -RNP3PH#CDsHF4oR;P -NR#3H_sPCHoDFR -4;N3PRFosHhCNlR7"w471dX -";NFPRs_HoH0M#_RFV"4w71Xd7"N; -PDR3NuMoNlsN#tR"1;)" -RNPtR1)"q hA7p "N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_wwc;4" -RNP3M#$_LDH_DOCD;R4 -RNP3M#$_C0sNN0_#D_LNLO F4GR;P -NRM#$_LDH_DOCD;R4 -@HR@4j:(4j:j(:4jj:4R77R; - - - -@HR@4j:(44:j(:444:4RRBiB -i; -@HR@4j:(4.:j(:4.4:4RRB7B -7; -@FR@4j:(4d:j(:4dj:4R;TR --y--------------------------------- - -@ -ftell; -@E@MR@4j:n(j::j4n:R4dI FsR4w71XdARsPCHoDF;P -NRG3C0MCsN4DR;P -NRF3VsDlN_DOCDlMNCwR"7d41A;X" -RNP3PH#CDsHF4oR;P -NR#3H_sPCHoDFR -4;N3PRFosHhCNlR7"w4A1dX -";NFPRs_HoH0M#_RFV"4w71XdA"N; -PDR3NuMoNlsN#tR"1;)" -RNPtR1)"q hA7p "N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4 -";N3PR#_$MD_HLODCDR -4;N3PR#_$M0NsC0#_N_NLDOF LG;R4 -RNP#_$MD_HLODCDR -4; -@HR@4j:n4.:jn:4.j:4R77R; - - - -@HR@4j:n4d:jn:4d4:4RRBiB -i; -@HR@4j:n4c:jn:4c4:4RRu7u -7; -@FR@4j:n46:jn:46j:4R;TR --y--------------------------------- - -@ -ftell; -@E@MR@4j:4(g::g44:R4dI FsR4w7uXd7RsPCHoDF;P -NRG3C0MCsN4DR;P -NRF3VsDlN_DOCDlMNCwR"7d4u7;X" -RNP3PH#CDsHF4oR;P -NR#3H_sPCHoDFR -4;N3PRFosHhCNlR7"w47udX -";NFPRs_HoH0M#_RFV"4w7uXd7"N; -PDR3NuMoNlsN#tR"1;)" -RNPtR1)"q hA7p "N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4"jj;P -NR$3#MH_DLC_OD4DR;P -NR$3#Ms_0C_N0NL#_D NOLRFG4N; -P$R#MH_DLC_OD4DR; - - - -@HR@4j:.g4::44.:7gRR -7; -@HR@4j:.g.::.4.:R4j11uRu -; - -@HR@4j:.gd::d4.:R4jBBiRi -; - -@HR@4j:.gc::c4.:R4jBB7R7 -; - -@FR@4j:.46:j.:46j:4R;TR --y--------------------------------- - -@ -ftell; -@E@MR@4j:4(j::j44:R4dI FsR4w7uXdARsPCHoDF;P -NRG3C0MCsN4DR;P -NRF3VsDlN_DOCDlMNCwR"7d4uA;X" -RNP3PH#CDsHF4oR;P -NR#3H_sPCHoDFR -4;N3PRFosHhCNlR7"w4AudX -";NFPRs_HoH0M#_RFV"4w7uXdA"N; -PDR3NuMoNlsN#tR"1;)" -RNPtR1)"q hA7p "N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3_ww4"j4;P -NR$3#MH_DLC_OD4DR;P -NR$3#Ms_0C_N0NL#_D NOLRFG4N; -P$R#MH_DLC_OD4DR; - - - -@HR@4j:4g.::.44:7gRR -7; -@HR@4j:4gd::d44:R4j11uRu -; - -@HR@4j:4gc::c44:R4jBBiRi -; - -@HR@4j:4g6::644:R4juu7R7 -; - -@FR@4j:44n:j4:4nj:4R;TR --y--------------------------------- - -@ -ftell; -@E@MR@gj:6(g::gg6:R4cI FsRuu7Wi4n7CRPsFHDoN; -PCR3Gs0CMRND4N; -PVR3FNslDC_ODNDMl"CRuW7u47ni"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CRuW7u47ni"N; -PsRFHHo_M_#0F"VRuW7u47ni"N; -PDR3NuMoNlsN#7R"q_aqWaQ7]R_W7qqa_7WQa)]_R)t1Rt) v m7R1) mav7q R1BYh_1) )a_ qp 1B R1B7 m_7 W1RB7m B7) _RQQhapeq_RjjQahQe_qpjQ4RheQaqjp_.hRQQqaepd_jRQQhapeq_RjcQahQe_qpjQ6RheQaqjp_nhRQQqaep(_jRQQhapeq_RjUQahQe_qpjQgRheQaqjp_qhRQQqaepA_jRQQhapeq_RjBQahQe_qpjQ7RheQaqjp_ hRQQqaepw_jRQQhapeq_R4jQahQe_qp4Q4RheQaq4p_.hRQQqaepd_4RQQhapeq_R4cQahQe_qp4Q6RheQaq4p_nhRQQqaep(_4RQQhapeq_R4UQahQe_qp4QgRheQaq4p_qhRQQqaepA_4RQQhapeq_R4BQahQe_qp4Q7RheQaq4p_ hRQQqaepw_4RQQhapeq_R.jQahQe_qp.Q4RheQaq.p_.hRQQqaepd_.RQQhapeq_R.cQahQe_qp.Q6RheQaq.p_nhRQQqaep(_.RQQhapeq_R.UQahQe_qp.QgRheQaq.p_qhRQQqaepA_.RQQhapeq_R.BQahQe_qp.Q7RheQaq.p_ hRQQqaepw_.RQQhapeq_RdjQahQe_qpdQ4RheQaqdp_.hRQQqaepd_dRQQhapeq_RdcQahQe_qpdQ6RheQaqdp_nhRQQqaep(_dRQQhapeq_RdUQahQe_qpdQgRheQaqdp_qhRQQqaepA_dRQQhapeq_RdBQahQe_qpdQ7RheQaqdp_ hRQQqaepw_dRQQhaq_7a;q" -RNP7qqa_7WQaW]_R;dn -RNP7qqa_7WQa)]_R;dn -RNPtR1)"q hA7p "N; -P R)t7vm hR"mt) "N; -P R)1v amR7 "h1YB -";NqPR1BYh_1) )a_ qp 1" R1BYh"N; -P1RB7m B7W _RL"jj"jj;P -NR7B1 7Bm R_)"jjLj;j" -RNPQahQe_qpj"jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpj"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp4"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp.".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp." RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qp."wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"jRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"4RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd".RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"dRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"cRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"6RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"nRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"(RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"URjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"gRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"qRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"ARjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"BRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"7RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd" RjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQe_qpd"wRjjGjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj;j" -RNPQahQ_a7qq1R"aQqaB -";N3PR#_$MNV00FNsl0x#HC7R"q_aqWaQ7]=_Wd7.Rq_aqWaQ7]=_)d".R;P -NR$3#M0_N0sVFlRN0"a7qqQ_W7_a]WR=77qqa_7WQa)]_="7R;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3M#$_Ck#sRLL4N; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03VVHFF_OD0COFHs_M3#0VFHVcHj_M3#0b_8bs_Nlj__j4 -";N3PR#_$MD_HLODCDR -4;N3PR#_$M0NsC0#_N_NLDOF LG;R4 -RNP#_$MD_HLODCDR -4; -@HR@gj:ngj::jgn:R4.76QdRd7Q6 -; - -@HR@gj:n4j:6n:gjU:4Rd7QcQR7d -c; -@HR@gj:n.j:4n:gjc:.Rd7QdQR7d -d; -@HR@gj:n.j:(n:gjj:dRd7Q.QR7d -.; -@HR@gj:ndj:dn:gjn:dRd7Q4QR7d -4; -@HR@gj:ndj:gn:gj.:cRd7QjQR7d -j; -@HR@gj:ncj:6n:gjU:cR.7QgQR7. -g; -@HR@gj:n6j:4n:gjc:6R.7QUQR7. -U; -@HR@gj:n6j:(n:gjj:nR.7Q(QR7. -(; -@HR@gj:ng4::4gn:R4.7nQ.R.7Qn -; - -@HR@gj:n44:6n:g4U:4R.7Q6QR7. -6; -@HR@gj:n.4:4n:g4c:.R.7QcQR7. -c; -@HR@gj:n.4:(n:g4j:dR.7QdQR7. -d; -@HR@gj:nd4:dn:g4n:dR.7Q.QR7. -.; -@HR@gj:nd4:gn:g4.:cR.7Q4QR7. -4; -@HR@gj:nc4:6n:g4U:cR.7QjQR7. -j; -@HR@gj:n64:4n:g4c:6R47QgQR74 -g; -@HR@gj:n64:(n:g4j:nR47QUQR74 -U; -@HR@gj:ng.::.gn:R4.7(Q4R47Q( -; - -@HR@gj:n4.:6n:g.U:4R47QnQR74 -n; -@HR@gj:n..:4n:g.c:.R47Q6QR74 -6; -@HR@gj:n..:(n:g.j:dR47QcQR74 -c; -@HR@gj:nd.:dn:g.n:dR47QdQR74 -d; -@HR@gj:nd.:gn:g..:cR47Q.QR74 -.; -@HR@gj:nc.:6n:g.U:cR47Q4QR74 -4; -@HR@gj:n6.:4n:g.c:6R47QjQR74 -j; -@HR@gj:n6.:(n:g.g:6Rg7QRg7Q; - - - -@HR@gj:ngd::dgn:R447RQU7;QU -@HR@gj:n4d:cn:gdn:4R(7QR(7Q; - - - -@HR@gj:n4d:gn:gd4:.Rn7QRn7Q; - - - -@HR@gj:n.d:cn:gdn:.R67QR67Q; - - - -@HR@gj:n.d:gn:gd4:dRc7QRc7Q; - - - -@HR@gj:ndd:cn:gdn:dRd7QRd7Q; - - - -@HR@gj:ndd:gn:gd4:cR.7QR.7Q; - - - -@HR@gj:ncd:cn:gdn:cR47QR47Q; - - - -@HR@gj:ncd:gn:gd4:6Rj7QRj7Q; - - - -@HR@gj:ngc::cgn:R4.qU7WRWq7U -; - -@HR@gj:n4c:6n:gcU:4RWq7(7RqW -(; -@HR@gj:n.c:4n:gcc:.RWq7n7RqW -n; -@HR@gj:n.c:(n:gcj:dRWq767RqW -6; -@HR@gj:ndc:dn:gcn:dRWq7c7RqW -c; -@HR@gj:ndc:gn:gc.:cRWq7d7RqW -d; -@HR@gj:ncc:6n:gcU:cRWq7.7RqW -.; -@HR@gj:n6c:4n:gcc:6RWq747RqW -4; -@HR@gj:n6c:(n:gcj:nRWq7j7RqW -j; -@HR@gj:ng6::6gn:R44AR dA; d -@HR@gj:n46:6n:g6(:4R.A R.A ; - - - -@HR@gj:n.6:4n:g6d:.R4A R4A ; - - - -@HR@gj:n.6:nn:g6U:.RjA RjA ; - - - -@HR@gj:ngn::ngn:R44BR WB; W -@HR@gj:n4n:cn:gn(:4RiBpWpRBi -W; -@HR@gj:n.n:jn:gnd:.RWB1.1RBW -.; -@HR@gj:n.n:nn:gng:.RWB141RBW -4; -@HR@gj:ndn:.n:gn6:dRWB1j1RBW -j; -@HR@gj:ng(::(gn:R4dq47)d7Rq);4d -@HR@gj:n4(:nn:g(j:.R)q74q.R7.)4; - - - -@HR@gj:n.(:dn:g((:.R)q74q4R74)4; - - - -@HR@gj:nd(:jn:g(c:dR)q74qjR7j)4; - - - -@HR@gj:nd(:(n:g(j:cR)q7g7Rq) -g; -@HR@gj:nc(:dn:g(n:cR)q7U7Rq) -U; -@HR@gj:nc(:gn:g(.:6R)q7(7Rq) -(; -@HR@gj:n6(:6n:g(U:6R)q7n7Rq) -n; -@HR@gj:nn(:4n:g(c:nR)q767Rq) -6; -@HR@gj:ngU::Ugn:R4.qc7)R)q7c -; - -@HR@gj:n4U:nn:gUg:4R)q7d7Rq) -d; -@HR@gj:n.U:dn:gUn:.R)q7.7Rq) -.; -@HR@gj:n.U:gn:gU.:dR)q747Rq) -4; -@HR@gj:ndU:6n:gUU:dR)q7j7Rq) -j; -@HR@gj:ngg::ggn:R44BR )B; ) -@HR@gj:n4g:cn:gg(:4R mB)BRm -); -@HR@gj:n.g:jn:ggd:.RiBp)pRBi -); -@HR@gj:n.g:nn:ggg:.R)B1.1RB) -.; -@HR@gj:ndg:.n:gg6:dR)B141RB) -4; -@HR@gj:ndg:Un:gg4:cR)B1j1RB) -j; -@HR@gj:ncg:cn:ggn:cRa)1Ra)1; - - - -@FR@gj:(gj::jg(:R4.76mdR -; - -@FR@gj:(4j:6(:gjU:4Rd7mc -R; -@FR@gj:(.j:4(:gjc:.Rd7md -R; -@FR@gj:(.j:((:gjj:dRd7m. -R; -@FR@gj:(dj:d(:gjn:dRd7m4 -R; -@FR@gj:(dj:g(:gj.:cRd7mj -R; -@FR@gj:(cj:6(:gjU:cR.7mg -R; -@FR@gj:(6j:4(:gjc:6R.7mU -R; -@FR@gj:(6j:((:gjj:nR.7m( -R; -@FR@gj:(g4::4g(:R4.7nm.R -; - -@FR@gj:(44:6(:g4U:4R.7m6 -R; -@FR@gj:(.4:4(:g4c:.R.7mc -R; -@FR@gj:(.4:((:g4j:dR.7md -R; -@FR@gj:(d4:d(:g4n:dR.7m. -R; -@FR@gj:(d4:g(:g4.:cR.7m4 -R; -@FR@gj:(c4:6(:g4U:cR.7mj -R; -@FR@gj:(64:4(:g4c:6R47mg -R; -@FR@gj:(64:((:g4j:nR47mU -R; -@FR@gj:(g.::.g(:R4.7(m4R -; - -@FR@gj:(4.:6(:g.U:4R47mn -R; -@FR@gj:(..:4(:g.c:.R47m6 -R; -@FR@gj:(..:((:g.j:dR47mc -R; -@FR@gj:(d.:d(:g.n:dR47md -R; -@FR@gj:(d.:g(:g..:cR47m. -R; -@FR@gj:(c.:6(:g.U:cR47m4 -R; -@FR@gj:(6.:4(:g.c:6R47mj -R; -@FR@gj:(6.:((:g.g:6Rg7mR -; - -@FR@gj:(gd::dg(:R447RmU; - - - -@FR@gj:(4d:c(:gdn:4R(7mR -; - -@FR@gj:(4d:g(:gd4:.Rn7mR -; - -@FR@gj:(.d:c(:gdn:.R67mR -; - -@FR@gj:(.d:g(:gd4:dRc7mR -; - -@FR@gj:(dd:c(:gdn:dRd7mR -; - -@FR@gj:(dd:g(:gd4:cR.7mR -; - -@FR@gj:(cd:c(:gdn:cR47mR -; - -@FR@gj:(cd:g(:gd4:6Rj7mRy; ----------------------------------@- - - - - -ftell; -@E@MR@(j:4(j::j(4:R4cI FsRv)m44nXqCRPsFHDoN; -PCR3Gs0CMRND4N; -PVR3FNslDC_ODNDMl"CR)4mvnqX4"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CR)4mvnqX4"N; -PsRFHHo_M_#0F"VR)4mvnqX4"N; -PDR3NuMoNlsN#HR"MPH0N;D" -RNPH0MHPRND"'4nLjjjjjjjjjjjjjjjj -";N3PR#_$MNV00FNsl0x#HCHR"MPH0N4D=n;R" -RNP3M#$_0N0VlFsN"0RH0MHP=NDX;R" -RNP3HFsoLDHMCNlRF"Is; " -RNP3$DNC8sHR -j;N3PR#_$Mks#CL4LR;P -NR$3EbQCsMu#0Nv0EFO81FRbC"b0F_30VVFHV_DOFCFO0sM_H#V03HcVFjM_H#p03z_ac.;d" -RNP3M#$_LDH_DOCD;R4 -RNP3M#$_C0sNN0_#D_LNLO F4GR;P -NRM#$_LDH_DOCD;R4 -@HR@(j:4g.::.(4:R44qR7dq;7d -@HR@(j:4gd::d(4:R44qR7.q;7. -@HR@(j:4gc::c(4:R44qR74q;74 -@HR@(j:4g6::6(4:R44qR7jq;7j -@FR@(j:44n:j4:(n.:4Rj7mRy; ----------------------------------@- - - - - -ftell; -@E@MR@Uj:4(j::jU4:R4jI FsR)Xm.CRPsFHDoN; -PCR3Gs0CMRND4N; -PVR3FNslDC_ODNDMl"CRX.m)"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CRX.m)"N; -PsRFHHo_M_#0F"VRX.m)"N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3#M#_kCLsLR -4;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VH3VVOF_FODC0_FsH0M#3VVHF_cjH0M#3)Xm.4_0( -";N3PR#_$MD_HLODCDR -4;N3PR#_$M0NsC0#_N_NLDOF LG;R4 -RNP#_$MD_HLODCDR -4; -@HR@Uj:4g4::4U4:qgRR -q; -@HR@Uj:4g.::.U4:AgRR -A; -@FR@Uj:44d:j4:Udj:4R;ZR --y--------------------------------- - -@ -ftell; -@E@MR@nj:6(n::nn6:IgRFRs mR).PHCsD;Fo -RNP30CGCNsMD;R4 -RNP3sVFl_NDODCDMCNlR)"m. -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC".m)"N; -PsRFHHo_M_#0F"VRm").;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3M#$_Ck#sRLL4N; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03VVHFF_OD0COFHs_M3#0VFHVcHj_M3#0m_).0"4U;P -NR$3#MH_DLC_OD4DR;P -NR$3#Ms_0C_N0NL#_D NOLRFG4N; -P$R#MH_DLC_OD4DR; - - - -@HR@nj:64(:j6:n(j:4RqqR; - - - -@HR@nj:64U:j6:nUj:4RAAR; - - - -@FR@nj:64g:j6:ngj:4R;ZR --y--------------------------------- - -@ -ftell; -@E@MR@dj:n((::(dn:IgRFRs QRhePHCsD;Fo -RNP30CGCNsMD;R4 -RNP3sVFl_NDODCDMCNlRh"Qe -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"eQh"N; -PsRFHHo_M_#0F"VRQ"he;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3M#$_Ck#sRLL4N; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03VVHFF_OD0COFHs_M3#0VFHVcHj_M3#0Q_he4 -";N3PR#_$MD_HLODCDR -4;N3PR#_$M0NsC0#_N_NLDOF LG;R4 -RNP#_$MD_HLODCDR -4; -@HR@dj:ngU::Udn:qgRR -q; -@FR@dj:n4g:jn:dgj:4R;ZR --y--------------------------------- - -@ -ftell; -@E@MR@.j:6::(.46:jFRIsq RhR7.PHCsD;Fo -RNP30CGCNsMD;R4 -RNP3sVFl_NDODCDMCNlRh"q7;." -RNP3PH#CDsHF4oR;P -NR#3H_sPCHoDFR -4;N3PRFosHhCNlRh"q7;." -RNPFosH_#HM0V_FRh"q7;." -RNP3HFsoLDHMCNlRF"Is; " -RNP3$DNC8sHR -j;N3PR#_$Mks#CL4LR;P -NR$3EbQCsMu#0Nv0EFO81FRbC"b0F_30VVFHV_DOFCFO0sM_H#V03HcVFjM_H#q03h_7.0".j;P -NR$3#MH_DLC_OD4DR;P -NR$3#Ms_0C_N0NL#_D NOLRFG4N; -P$R#MH_DLC_OD4DR; - - - -@HR@.j:n::g.gn:RqqR; - - - -@HR@.j:(::g.g(:RAAR; - - - -@FR@.j:Uj:4::.U4ZjRRy; ----------------------------------@- - - - - -ftell; -@E@MR@Ug::U(::R4cI FsRVVHF8d.OCRPsFHDoN; -PVR3FNslDC_ODNDMl"CRVFHVdO.8"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CRVFHVdO.8"N; -PsRFHHo_M_#0F"VRVFHVdO.8"N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3EbQCsMu#0Nv0EFO81FRbC"b0F_30V0_8OOMENM_CDVFHV_0Fk_#HM0H3VV.Fd8HO_M"#0;P -NR7ht_B7)_1vqi;R4 -RNP3l#00#DH0llCko#NC3Rjjjjjj -j;N3PR#00lD0H#0CHlRjj3jjjjj -; - -@HR@Ug:::4(Uj:.R07NN4rd:Rj97NN0r:d4j -9; -@HR@Ug:::.dUg:.RBWsD FORBWsD FO; - - - -@HR@Ug:::d.UU:dRB)8D FORB)8D FO; - - - -@HR@Ug:::c4Uc:cR WsMsRW -M; -@HR@Ug:::c(Uj:6R )8M8R) -M; -@HR@Ug:::6dU(:6R#)CC)0RC0#C; - - - -@HR@Ug:::njUn:nR))uC0#CR))uC0#C; - - - -@FR@Ug:::ngUg:nRdTr49:jR -; - -@FR@gg::gc:: URl$b0R -; - -@FR@gg:::44gc:4RDwkD -R;s@R@gn:g4j:4:4gn:R44I FsRzBB.PBRCDsHFNoR4B -SQBh=QNh_4q -Sjj=q_ -N4S=AjANj_4B -Sjj=B_ -N4S=7j7Nj_4q -S44=q_ -N4S=A4AN4_4B -S44=B_ -N4S=747N4_41 -Sjj=1_ -N4S=141N4_4B -Sm=zaBamz_;N4 -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:6g6:gU:6.6:4FRIse RpPmRCDsHF#oRONkL_FPD_#HM0Z -S=#Z_ONkL_FPD_#HM0N; -H$R#MF_MbMskC;R4 -@sR@gg:6Ud::dg6:R.4I FsRQe]RsPCHoDFRk#OLPN_EHH_M -#0SZZ=_k#OLPN_EHH_M;#0 -RNH#_$MMsFbkRMC4s; -Rg@@:ggc::4jg:cg4IgRFRs B.BzBCRPsFHDokRVDOD_lcb_ -QSBhQ=Bhk_VDOD_lcb_ -jSq=_qjVDkD_bOl_Sc -AAj=jk_VDOD_lcb_ -jSB=_BjVDkD_bOl_Sc -77j=jk_VDOD_lcb_ -4Sq=_q4VDkD_bOl_Sc -AA4=4k_VDOD_lcb_ -4SB=_B4VDkD_bOl_Sc -774=4k_VDOD_lcb_ -jS1=_1jVDkD_bOl_Sc -114=4k_VDOD_lcb_ -mSBzBa=m_zaVDkD_bOl_ -c;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'jL4jj44jj444jj44;j" -RNHQahQj4R"n4'Lj4j4j4j4j44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@gg:c44gj:c44:gFRIsB RBBz.RsPCHoDFRDVkDl_Ob -_dShBQ=hBQ_DVkDl_Ob -_dS=qjqVj_k_DDO_lbdA -Sjj=A_DVkDl_Ob -_dS=BjBVj_k_DDO_lbd7 -Sjj=7_DVkDl_Ob -_dS=q4qV4_k_DDO_lbdA -S44=A_DVkDl_Ob -_dS=B4BV4_k_DDO_lbd7 -S44=7_DVkDl_Ob -_dS=1j1Vj_k_DDO_lbd1 -S44=1_DVkDl_Ob -_dSzBmam=BzVa_k_DDO_lbdN; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nLj4j4j4j444jj44jj -";NQHRhjQaRn"4'jL4jj44jj444jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@gg:d4d:jd:gdg:4RsIF BRBzR.BPHCsDRFoVDkD_bOl_S. -B=QhB_QhVDkD_bOl_S. -qqj=jk_VDOD_l.b_ -jSA=_AjVDkD_bOl_S. -BBj=jk_VDOD_l.b_ -jS7=_7jVDkD_bOl_S. -qq4=4k_VDOD_l.b_ -4SA=_A4VDkD_bOl_S. -BB4=4k_VDOD_l.b_ -4S7=_74VDkD_bOl_S. -11j=jk_VDOD_l.b_ -4S1=_14VDkD_bOl_S. -Bamz=zBmak_VDOD_l.b_;H -NRM#$_bMFsCkMR -4;NQHRhBK a44_Rm"h"N; -HhRQKa B4R_j""hm;H -NRQQha"4R4Ln'44jj44jj4jj44jj4"N; -HhRQQRaj"'4nLj4j4j4j444jj44jj -";N3HR#_$MNV00FNsl0x#HCQR"h4Qa=R4nQahQjn=4"N; -H#R3$NM_0F0Vs0lNRh"QQ=a4XhRQQ=ajX -";s@R@g.:g6j:4:6g.:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lb4B -SQBh=QVh_k_DDO_lb4q -Sjj=q_DVkDl_Ob -_4S=AjAVj_k_DDO_lb4B -Sjj=B_DVkDl_Ob -_4S=7j7Vj_k_DDO_lb4q -S44=q_DVkDl_Ob -_4S=A4AV4_k_DDO_lb4B -S44=B_DVkDl_Ob -_4S=747V4_k_DDO_lb41 -Sjj=1_DVkDl_Ob -_4S=141V4_k_DDO_lb4B -Sm=zaBamz_DVkDl_Ob;_4 -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:(g4::4jg:4(4IgRFRs B.BzBCRPsFHDokRVDOD_ljb_ -QSBhQ=Bhk_VDOD_ljb_ -jSq=_qjVDkD_bOl_Sj -AAj=jk_VDOD_ljb_ -jSB=_BjVDkD_bOl_Sj -77j=jk_VDOD_ljb_ -4Sq=_q4VDkD_bOl_Sj -AA4=4k_VDOD_ljb_ -4SB=_B4VDkD_bOl_Sj -774=4k_VDOD_ljb_ -jS1=_1jVDkD_bOl_Sj -114=4k_VDOD_ljb_ -mSBzBa=m_zaVDkD_bOl_ -j;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'jL4jj44jj444jj44;j" -RNHQahQj4R"n4'Lj4j4j4j4j44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@gg:jg4gj:j.g:.FRIsB RBBz.RsPCHoDFRDVkDl_ObH_O_SN -B=QhB_QhVDkD_bOl__OHNq -Sjj=q_DVkDl_ObH_O_SN -AAj=jk_VDOD_lOb_H -_NS=BjBVj_k_DDO_lbONH_ -jS7=_7jVDkD_bOl__OHNq -S44=q_DVkDl_ObH_O_SN -AA4=4k_VDOD_lOb_H -_NS=B4BV4_k_DDO_lbONH_ -4S7=_74VDkD_bOl__OHN1 -Sjj=1_DVkDl_ObH_O_SN -114=4k_VDOD_lOb_H -_NSzBmam=BzVa_k_DDO_lbONH_;H -NRM#$_bMFsCkMR -4;NQHRhBK a44_Rm"h"N; -HhRQKa B4R_j""hm;H -NRQQha"4R4Ln'jj44jj444jj44jj4"N; -HhRQQRaj"'4nL4j4j4j4j44jj44jj -";N3HR#_$MNV00FNsl0x#HCQR"h4Qa=R4nQahQjn=4"N; -H#R3$NM_0F0Vs0lNRh"QQ=a4XhRQQ=ajX -";s@R@gj:g4j:4:4gj:R44I FsRzBB.PBRCDsHFNoRjB -SQBh=QNh_jq -Sjj=q_ -NjS=AjANj_jB -Sjj=B_ -NjS=7j7Nj_jq -S44=q_ -NjS=A4AN4_jB -S44=B_ -NjS=747N4_j1 -Sjj=1_ -NjS=141N4_jB -Sm=zaBamz_;Nj -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:dUg::4jU:gd.IjRFRs B.BzBCRPsFHDolRCb_0$O_lbcB -SQBh=QCh_l$b0_bOl_Sc -qqj=jl_Cb_0$O_lbcA -Sjj=A_bCl0O$_lcb_ -jSB=_BjC0lb$l_Ob -_cS=7j7Cj_l$b0_bOl_Sc -qq4=4l_Cb_0$O_lbcA -S44=A_bCl0O$_lcb_ -4SB=_B4C0lb$l_Ob -_cS=747C4_l$b0_bOl_Sc -11j=jl_Cb_0$O_lbc1 -S44=1_bCl0O$_lcb_ -mSBzBa=m_zaC0lb$l_Ob;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:6UU::4jU:U6.IjRFRs B.BzBCRPsFHDolRCb_0$O_lbdB -SQBh=QCh_l$b0_bOl_Sd -qqj=jl_Cb_0$O_lbdA -Sjj=A_bCl0O$_ldb_ -jSB=_BjC0lb$l_Ob -_dS=7j7Cj_l$b0_bOl_Sd -qq4=4l_Cb_0$O_lbdA -S44=A_bCl0O$_ldb_ -4SB=_B4C0lb$l_Ob -_dS=747C4_l$b0_bOl_Sd -11j=jl_Cb_0$O_lbd1 -S44=1_bCl0O$_ldb_ -mSBzBa=m_zaC0lb$l_Ob;_d -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:(U(::4jU:((.IjRFRs B.BzBCRPsFHDolRCb_0$O_lb.B -SQBh=QCh_l$b0_bOl_S. -qqj=jl_Cb_0$O_lb.A -Sjj=A_bCl0O$_l.b_ -jSB=_BjC0lb$l_Ob -_.S=7j7Cj_l$b0_bOl_S. -qq4=4l_Cb_0$O_lb.A -S44=A_bCl0O$_l.b_ -4SB=_B4C0lb$l_Ob -_.S=747C4_l$b0_bOl_S. -11j=jl_Cb_0$O_lb.1 -S44=1_bCl0O$_l.b_ -mSBzBa=m_zaC0lb$l_Ob;_. -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:gUn::4jU:ng.IjRFRs B.BzBCRPsFHDolRCb_0$O_lb4B -SQBh=QCh_l$b0_bOl_S4 -qqj=jl_Cb_0$O_lb4A -Sjj=A_bCl0O$_l4b_ -jSB=_BjC0lb$l_Ob -_4S=7j7Cj_l$b0_bOl_S4 -qq4=4l_Cb_0$O_lb4A -S44=A_bCl0O$_l4b_ -4SB=_B4C0lb$l_Ob -_4S=747C4_l$b0_bOl_S4 -11j=jl_Cb_0$O_lb41 -S44=1_bCl0O$_l4b_ -mSBzBa=m_zaC0lb$l_Ob;_4 -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:4Un::4jU:n4.IjRFRs B.BzBCRPsFHDolRCb_0$O_lbjB -SQBh=QCh_l$b0_bOl_Sj -qqj=jl_Cb_0$O_lbjA -Sjj=A_bCl0O$_ljb_ -jSB=_BjC0lb$l_Ob -_jS=7j7Cj_l$b0_bOl_Sj -qq4=4l_Cb_0$O_lbjA -S44=A_bCl0O$_ljb_ -4SB=_B4C0lb$l_Ob -_jS=747C4_l$b0_bOl_Sj -11j=jl_Cb_0$O_lbj1 -S44=1_bCl0O$_ljb_ -mSBzBa=m_zaC0lb$l_Ob;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:dU6::4jU:6d.IdRFRs B.BzBCRPsFHDolRCb_0$O_lbONH_ -QSBhQ=Bhl_Cb_0$O_lbONH_ -jSq=_qjC0lb$l_ObH_O_SN -AAj=jl_Cb_0$O_lbONH_ -jSB=_BjC0lb$l_ObH_O_SN -77j=jl_Cb_0$O_lbONH_ -4Sq=_q4C0lb$l_ObH_O_SN -AA4=4l_Cb_0$O_lbONH_ -4SB=_B4C0lb$l_ObH_O_SN -774=4l_Cb_0$O_lbONH_ -jS1=_1jC0lb$l_ObH_O_SN -114=4l_Cb_0$O_lbONH_ -mSBzBa=m_zaC0lb$l_ObH_O_ -N;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@gU:c64Uj:c46:(FRIsB RBBz.RsPCHoDFRos_O_0scB -SQBh=Qsh__0oOs -_cS=qjqsj__0oOs -_cS=AjAsj__0oOs -_cS=BjBsj__0oOs -_cS=7j7sj__0oOs -_cS=q4qs4__0oOs -_cS=A4As4__0oOs -_cS=B4Bs4__0oOs -_cS=747s4__0oOs -_cS=1j1sj__0oOs -_cS=141s4__0oOs -_cSzBmam=Bzsa__0oOs;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:(Ud::4jU:d(4I(RFRs B.BzBCRPsFHDo_RsosO0_Sd -B=QhB_QhsO_o0ds_ -jSq=_qjsO_o0ds_ -jSA=_AjsO_o0ds_ -jSB=_BjsO_o0ds_ -jS7=_7jsO_o0ds_ -4Sq=_q4sO_o0ds_ -4SA=_A4sO_o0ds_ -4SB=_B4sO_o0ds_ -4S7=_74sO_o0ds_ -jS1=_1jsO_o0ds_ -4S1=_14sO_o0ds_ -mSBzBa=m_zasO_o0ds_;H -NRM#$_bMFsCkMR -4;NQHRhBK a44_Rm"h"N; -HhRQKa B4R_j""hm;H -NRQQha"4R4Ln'jj44jj444jj44jj4"N; -HhRQQRaj"'4nL4j4j4j4j44jj44jj -";N3HR#_$MNV00FNsl0x#HCQR"h4Qa=R4nQahQjn=4"N; -H#R3$NM_0F0Vs0lNRh"QQ=a4XhRQQ=ajX -";s@R@g.:Ugj:4:gU.:R4(I FsRzBB.PBRCDsHFsoR_0oOs -_.ShBQ=hBQ_os_O_0s.q -Sjj=q_os_O_0s.A -Sjj=A_os_O_0s.B -Sjj=B_os_O_0s.7 -Sjj=7_os_O_0s.q -S44=q_os_O_0s.A -S44=A_os_O_0s.B -S44=B_os_O_0s.7 -S44=7_os_O_0s.1 -Sjj=1_os_O_0s.1 -S44=1_os_O_0s.B -Sm=zaBamz_os_O_0s.N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@Ug:.44:j.:U4(:4RsIF BRBzR.BPHCsDRFosO_o04s_ -QSBhQ=Bh__sosO0_S4 -qqj=j__sosO0_S4 -AAj=j__sosO0_S4 -BBj=j__sosO0_S4 -77j=j__sosO0_S4 -qq4=4__sosO0_S4 -AA4=4__sosO0_S4 -BB4=4__sosO0_S4 -774=4__sosO0_S4 -11j=j__sosO0_S4 -114=4__sosO0_S4 -Bamz=zBma__sosO0_ -4;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@gU:4d4Uj:44d:(FRIsB RBBz.RsPCHoDFRos_O_0sjB -SQBh=Qsh__0oOs -_jS=qjqsj__0oOs -_jS=AjAsj__0oOs -_jS=BjBsj__0oOs -_jS=7j7sj__0oOs -_jS=q4qs4__0oOs -_jS=A4As4__0oOs -_jS=B4Bs4__0oOs -_jS=747s4__0oOs -_jS=1j1sj__0oOs -_jS=141s4__0oOs -_jSzBmam=Bzsa__0oOs;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:6Uj::4jU:j64IgRFRs B.BzBCRPsFHDo_RsosO0_NOH -QSBhQ=Bh__sosO0_NOH -jSq=_qjsO_o0Os_HSN -AAj=j__sosO0_NOH -jSB=_BjsO_o0Os_HSN -77j=j__sosO0_NOH -4Sq=_q4sO_o0Os_HSN -AA4=4__sosO0_NOH -4SB=_B4sO_o0Os_HSN -774=4__sosO0_NOH -jS1=_1jsO_o0Os_HSN -114=4__sosO0_NOH -mSBzBa=m_zasO_o0Os_H -N;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@g(:g(4(j:g4(:(FRIsB RBBz.RsPCHoDFRoI_O_0scB -SQBh=QIh__0oOs -_cS=qjqIj__0oOs -_cS=AjAIj__0oOs -_cS=BjBIj__0oOs -_cS=7j7Ij__0oOs -_cS=q4qI4__0oOs -_cS=A4AI4__0oOs -_cS=B4BI4__0oOs -_cS=747I4__0oOs -_cS=1j1Ij__0oOs -_cS=141I4__0oOs -_cSzBmam=BzIa__0oOs;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:g(U::4j(:Ug4I(RFRs B.BzBCRPsFHDo_RIosO0_Sd -B=QhB_QhIO_o0ds_ -jSq=_qjIO_o0ds_ -jSA=_AjIO_o0ds_ -jSB=_BjIO_o0ds_ -jS7=_7jIO_o0ds_ -4Sq=_q4IO_o0ds_ -4SA=_A4IO_o0ds_ -4SB=_B4IO_o0ds_ -4S7=_74IO_o0ds_ -jS1=_1jIO_o0ds_ -4S1=_14IO_o0ds_ -mSBzBa=m_zaIO_o0ds_;H -NRM#$_bMFsCkMR -4;NQHRhBK a44_Rm"h"N; -HhRQKa B4R_j""hm;H -NRQQha"4R4Ln'jj44jj444jj44jj4"N; -HhRQQRaj"'4nL4j4j4j4j44jj44jj -";N3HR#_$MNV00FNsl0x#HCQR"h4Qa=R4nQahQjn=4"N; -H#R3$NM_0F0Vs0lNRh"QQ=a4XhRQQ=ajX -";s@R@gU:(4j:4:4(U:R4(I FsRzBB.PBRCDsHFIoR_0oOs -_.ShBQ=hBQ_oI_O_0s.q -Sjj=q_oI_O_0s.A -Sjj=A_oI_O_0s.B -Sjj=B_oI_O_0s.7 -Sjj=7_oI_O_0s.q -S44=q_oI_O_0s.A -S44=A_oI_O_0s.B -S44=B_oI_O_0s.7 -S44=7_oI_O_0s.1 -Sjj=1_oI_O_0s.1 -S44=1_oI_O_0s.B -Sm=zaBamz_oI_O_0s.N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@(g:(4d:j(:(d(:4RsIF BRBzR.BPHCsDRFoIO_o04s_ -QSBhQ=Bh__IosO0_S4 -qqj=j__IosO0_S4 -AAj=j__IosO0_S4 -BBj=j__IosO0_S4 -77j=j__IosO0_S4 -qq4=4__IosO0_S4 -AA4=4__IosO0_S4 -BB4=4__IosO0_S4 -774=4__IosO0_S4 -11j=j__IosO0_S4 -114=4__IosO0_S4 -Bamz=zBma__IosO0_ -4;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@g(:n64(j:n46:(FRIsB RBBz.RsPCHoDFRoI_O_0sjB -SQBh=QIh__0oOs -_jS=qjqIj__0oOs -_jS=AjAIj__0oOs -_jS=BjBIj__0oOs -_jS=7j7Ij__0oOs -_jS=q4qI4__0oOs -_jS=A4AI4__0oOs -_jS=B4BI4__0oOs -_jS=747I4__0oOs -_jS=1j1Ij__0oOs -_jS=141I4__0oOs -_jSzBmam=BzIa__0oOs;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -Rg@@:((6::4j(:6(4IgRFRs B.BzBCRPsFHDo_RIosO0_NOH -QSBhQ=Bh__IosO0_NOH -jSq=_qjIO_o0Os_HSN -AAj=j__IosO0_NOH -jSB=_BjIO_o0Os_HSN -77j=j__IosO0_NOH -4Sq=_q4IO_o0Os_HSN -AA4=4__IosO0_NOH -4SB=_B4IO_o0Os_HSN -774=4__IosO0_NOH -jS1=_1jIO_o0Os_HSN -114=4__IosO0_NOH -mSBzBa=m_zaIO_o0Os_H -N;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@:@g(:6j4(.:64j:6FRIsw R7d417PXRCDsHFwoRw -_jS77=__wwjB -Sii=B__wwjB -S77=B__wwjT -S=wT_w;_j -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@(g:c4(:.c:((6:4RsIF 7Rw4A1dXCRPsFHDowRw_S4 -7_=7w4w_ -iSB=_Biw4w_ -7Su=_u7w4w_ -=STTw_w_ -4;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@gc:(c.:4:c(c:R46I FsR4w71Xd7RsPCHoDFR_ww.7 -S=w7_w -_.S=BiBwi_w -_.S=B7Bw7_w -_.STT=__ww.N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -Rg@@:4(c::4.(:c44I6RFRs w174dR7XPHCsDRFowdw_ -=S77w_w_Sd -BBi=iw_w_Sd -BB7=7w_w_Sd -T_=Twdw_;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@g(:dU4(.:d4U:6FRIsw R7d417PXRCDsHFwoRw -_cS77=__wwcB -Sii=B__wwcB -S77=B__wwcT -S=wT_w;_c -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@(g:d46:.d:(66:4RsIF 7Rw471dXCRPsFHDowRw_S6 -7_=7w6w_ -iSB=_Biw6w_ -7SB=_B7w6w_ -=STTw_w_ -6;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@gd:(..:4:.(d:R46I FsR4w71Xd7RsPCHoDFR_wwn7 -S=w7_w -_nS=BiBwi_w -_nS=B7Bw7_w -_nSTT=__wwnN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -Rg@@:g(.::4.(:.g4I6RFRs w174dR7XPHCsDRFow(w_ -=S77w_w_S( -BBi=iw_w_S( -BB7=7w_w_S( -T_=Tw(w_;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@g(:.n4(.:.4n:6FRIsw R7d417PXRCDsHFwoRw -_US77=__wwUB -Sii=B__wwUB -S77=B__wwUT -S=wT_w;_U -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@(g:.4d:..:(d6:4RsIF 7Rw471dXCRPsFHDowRw_Sg -7_=7wgw_ -iSB=_Biwgw_ -7SB=_B7wgw_ -=STTw_w_ -g;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g.:(j.:4:j(.:R4nI FsR4w71Xd7RsPCHoDFR_ww4Sj -7_=7w4w_jB -Sii=B__ww4Sj -BB7=7w_w_ -4jSTT=__ww4 -j;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g4:((.:4:((4:R4nI FsR4w71Xd7RsPCHoDFR_ww4S4 -7_=7w4w_4B -Sii=B__ww4S4 -BB7=7w_w_ -44STT=__ww4 -4;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g4:(c.:4:c(4:R4nI FsR4w71Xd7RsPCHoDFR_ww4S. -7_=7w4w_.B -Sii=B__ww4S. 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-NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@gn:jn4n.:j4n:nFRIsw R7d4u7PXRCDsHFwoRwU_c -=S77w_w_ -cUS=1u1wu_wU_c -iSB=_Biwcw_UB -S77=B__wwcSU -T_=Twcw_UN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -Rg@@:dnj::4.n:jd4InRFRs wu74dR7XPHCsDRFowcw_g7 -S=w7_wg_c -uS1=_1uwcw_gB -Sii=B__wwcSg -BB7=7w_w_ -cgSTT=__wwc -g;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@gj:nj.:4:jnj:R4nI FsR4w7uXd7RsPCHoDFR_ww6Sj -7_=7w6w_j1 -Suu=1__ww6Sj -BBi=iw_w_ -6jS=B7Bw7_wj_6 -=STTw_w_;6j -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@6g:g4(:.g:6(n:4RsIF 7Rw47udXCRPsFHDowRw_ -64S77=__ww6S4 -11u=uw_w_ -64S=BiBwi_w4_6 -7SB=_B7w6w_4T -S=wT_w4_6;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@g6:gc46.:g4c:nFRIsw R7d4u7PXRCDsHFwoRw._6 -=S77w_w_ -6.S=1u1wu_w._6 -iSB=_Biw6w_.B -S77=B__ww6S. -T_=Tw6w_.N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -Rg@@:j6g::4.6:gj4InRFRs wu74dR7XPHCsDRFow6w_d7 -S=w7_wd_6 -uS1=_1uw6w_dB -Sii=B__ww6Sd -BB7=7w_w_ -6dSTT=__ww6 -d;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@gU:6n.:4:n6U:R4nI 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wu74dR7XPHCsDRFowgw_d7 -S=w7_wd_g -uS1=_1uwgw_dB -Sii=B__wwgSd -BB7=7w_w_ -gdSTT=__wwg -d;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g.:cn.:4:nc.:R4nI FsR4w7uXd7RsPCHoDFR_wwgSc -7_=7wgw_c1 -Suu=1__wwgSc -BBi=iw_w_ -gcS=B7Bw7_wc_g -=STTw_w_;gc -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@cg:.4.:..:c.n:4RsIF 7Rw47udXCRPsFHDowRw_ -g6S77=__wwgS6 -11u=uw_w_ -g6S=BiBwi_w6_g -7SB=_B7wgw_6T -S=wT_w6_g;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@gc:4U4c.:44U:nFRIsw R7d4u7PXRCDsHFwoRwn_g -=S77w_w_ -gnS=1u1wu_wn_g -iSB=_Biwgw_nB -S77=B__wwgSn -T_=Twgw_nN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -Rg@@:cc4::4.c:4c4InRFRs wu74dR7XPHCsDRFowgw_(7 -S=w7_w(_g -uS1=_1uwgw_(B -Sii=B__wwgS( -BB7=7w_w_ -g(STT=__wwg -(;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g4:cj.:4:jc4:R4nI FsR4w7uXd7RsPCHoDFR_wwgSU -7_=7wgw_U1 -Suu=1__wwgSU -BBi=iw_w_ -gUS=B7Bw7_wU_g -=STTw_w_;gU -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@cg:j4n:.j:cnn:4RsIF 7Rw47udXCRPsFHDowRw_ -ggS77=__wwgSg -11u=uw_w_ -ggS=BiBwi_wg_g -7SB=_B7wgw_gT -S=wT_wg_g;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@:@gc:j.4c.:j4.:(FRIsw R7d4u7PXRCDsHFwoRwj_4j7 -S=w7_wj_4j1 -Suu=1__ww4 -jjS=BiBwi_wj_4jB -S77=B__ww4 -jjSTT=__ww4;jj -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@dg:g4U:.g:dU(:4RsIF 7Rw4AudXCRPsFHDowRw_44j -=S77w_w_44j -uS1=_1uw4w_jS4 -BBi=iw_w_44j -7Su=_u7w4w_jS4 -T_=Tw4w_j -4;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@g(:djd:4:jd(:R.6I FsRuu7Wi4n7CRPsFHDo8RbbN_sl__jj -_jSd7Q6Q=7db6_8sb_Njl__jj_ -QS7d7c=Q_dcb_8bs_Nlj__jj7 -SQ=dd7dQd_bb8_lsN_jj__Sj -7.Qd=d7Q.8_bbN_sl__jj -_jSd7Q4Q=7db4_8sb_Njl__jj_ -QS7d7j=Q_djb_8bs_Nlj__jj7 -SQ=.g7gQ._bb8_lsN_jj__Sj -7UQ.=.7QU8_bbN_sl__jj -_jS.7Q(Q=7.b(_8sb_Njl__jj_ -QS7.7n=Q_.nb_8bs_Nlj__jj7 -SQ=.676Q._bb8_lsN_jj__Sj -7cQ.=.7Qc8_bbN_sl__jj -_jS.7QdQ=7.bd_8sb_Njl__jj_ -QS7.7.=Q_..b_8bs_Nlj__jj7 -SQ=.474Q._bb8_lsN_jj__Sj -7jQ.=.7Qj8_bbN_sl__jj -_jS47QgQ=74bg_8sb_Njl__jj_ -QS747U=Q_4Ub_8bs_Nlj__jj7 -SQ=4(7(Q4_bb8_lsN_jj__Sj -7nQ4=47Qn8_bbN_sl__jj -_jS47Q6Q=74b6_8sb_Njl__jj_ -QS747c=Q_4cb_8bs_Nlj__jj7 -SQ=4d7dQ4_bb8_lsN_jj__Sj -7.Q4=47Q.8_bbN_sl__jj -_jS47Q4Q=74b4_8sb_Njl__jj_ -QS747j=Q_4jb_8bs_Nlj__jj7 -SQ7g=Qbg_8sb_Njl__jj_ -QS7UQ=7U8_bbN_sl__jj -_jS(7Q=(7Q_bb8_lsN_jj__Sj -7=Qn7_Qnb_8bs_Nlj__jj7 -SQ76=Qb6_8sb_Njl__jj_ -QS7cQ=7c8_bbN_sl__jj -_jSd7Q=d7Q_bb8_lsN_jj__Sj -7=Q.7_Q.b_8bs_Nlj__jj7 -SQ74=Qb4_8sb_Njl__jj_ -QS7jQ=7j8_bbN_sl__jj -_jSWq7U7=qWbU_8sb_Njl__jj_ -7SqWq(=7_W(b_8bs_Nlj__jjq -S7=Wnqn7W_bb8_lsN_jj__Sj -q67W=Wq768_bbN_sl__jj -_jSWq7c7=qWbc_8sb_Njl__jj_ -7SqWqd=7_Wdb_8bs_Nlj__jjq -S7=W.q.7W_bb8_lsN_jj__Sj -q47W=Wq748_bbN_sl__jj -_jSWq7j7=qWbj_8sb_Njl__jj_ - SAd =Ad8_bbN_sl__jj -_jS.A =.A _bb8_lsN_jj__Sj -A= 4A_ 4b_8bs_Nlj__jjA -S Aj= bj_8sb_Njl__jj_ - SBW =BW8_bbN_sl__jj -_jSiBpWp=BibW_8sb_Njl__jj_ -1SBWB.=1_W.b_8bs_Nlj__jjB -S1=W4B41W_bb8_lsN_jj__Sj -Bj1W=WB1j8_bbN_sl__jj -_jS)q74qd=7d)4_bb8_lsN_jj__Sj -q47).7=q)_4.b_8bs_Nlj__jjq -S74)4=)q74b4_8sb_Njl__jj_ -7Sq)=4jq47)j8_bbN_sl__jj -_jS)q7g7=q)bg_8sb_Njl__jj_ -7Sq)qU=7_)Ub_8bs_Nlj__jjq -S7=)(q(7)_bb8_lsN_jj__Sj -qn7)=)q7n8_bbN_sl__jj -_jS)q767=q)b6_8sb_Njl__jj_ -7Sq)qc=7_)cb_8bs_Nlj__jjq -S7=)dqd7)_bb8_lsN_jj__Sj -q.7)=)q7.8_bbN_sl__jj -_jS)q747=q)b4_8sb_Njl__jj_ -7Sq)qj=7_)jb_8bs_Nlj__jjB -S B)= b)_8sb_Njl__jj_ -BSm m)=B_ )b_8bs_Nlj__jjB -Sp=i)B)pi_bb8_lsN_jj__Sj -B.1)=)B1.8_bbN_sl__jj -_jS)B141=B)b4_8sb_Njl__jj_ -1SB)Bj=1_)jb_8bs_Nlj__jj) -S1)a=1ba_8sb_Njl__jj_ -mS7d76=m_d6b_8bs_Nlj__jj7 -Sm=dc7cmd_bb8_lsN_jj__Sj -7dmd=d7md8_bbN_sl__jj -_jSd7m.m=7db._8sb_Njl__jj_ -mS7d74=m_d4b_8bs_Nlj__jj7 -Sm=dj7jmd_bb8_lsN_jj__Sj -7gm.=.7mg8_bbN_sl__jj -_jS.7mUm=7.bU_8sb_Njl__jj_ -mS7.7(=m_.(b_8bs_Nlj__jj7 -Sm=.n7nm._bb8_lsN_jj__Sj -76m.=.7m68_bbN_sl__jj -_jS.7mcm=7.bc_8sb_Njl__jj_ -mS7.7d=m_.db_8bs_Nlj__jj7 -Sm=..7.m._bb8_lsN_jj__Sj -74m.=.7m48_bbN_sl__jj -_jS.7mjm=7.bj_8sb_Njl__jj_ -mS747g=m_4gb_8bs_Nlj__jj7 -Sm=4U7Um4_bb8_lsN_jj__Sj -7(m4=47m(8_bbN_sl__jj -_jS47mnm=74bn_8sb_Njl__jj_ -mS7476=m_46b_8bs_Nlj__jj7 -Sm=4c7cm4_bb8_lsN_jj__Sj -7dm4=47md8_bbN_sl__jj -_jS47m.m=74b._8sb_Njl__jj_ -mS7474=m_44b_8bs_Nlj__jj7 -Sm=4j7jm4_bb8_lsN_jj__Sj -7=mg7_mgb_8bs_Nlj__jj7 -Sm7U=mbU_8sb_Njl__jj_ -mS7(m=7(8_bbN_sl__jj -_jSn7m=n7m_bb8_lsN_jj__Sj -7=m67_m6b_8bs_Nlj__jj7 -Sm7c=mbc_8sb_Njl__jj_ -mS7dm=7d8_bbN_sl__jj -_jS.7m=.7m_bb8_lsN_jj__Sj -7=m47_m4b_8bs_Nlj__jj7 -Sm7j=mbj_8sb_Njl__jj_;H -NRM#$_bMFsCkMR -4;NQHRh_Qa7qqaRa"1qBaQ"N; -H1RqY_hB) 1a _)p1 q 1R"Y"hB;H -NR7B1 7Bm R_)"jjLj;j" -RNHB 17B m7_"WRjjLj4 -";NtHR1")R Ahqp" 7;H -NR1) mav7" R1BYh"N; -H R)t7vm hR"mt) "N; -HqR7aWq_Q]7a_d)RnN; -HqR7aWq_Q]7a_dWRnN; -H#R3$NM_0F0Vs0lN#CHxRq"7aWq_Q]7a_d)=.qR7aWq_Q]7a_dW=. -";N3HR#_$MNV00FNsl07R"q_aqWaQ7]=_)7qR7aWq_Q]7a_7W="N; -H Rvvh_QQwa_QRp " -";NvHR pv_uwB_QRp "VVHF8d.Ob3DO -";s@R@g6:dUd:4:Ud6:R4UI FsRv)m44nXqCRPsFHDozRpajc_ -7Sqd7=qdz_pajc_ -7Sq.7=q.z_pajc_ -7Sq47=q4z_pajc_ -7Sqj7=qjz_pajc_ -mS7jm=7jz_pajc_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4jjjjjjjjjj4jj"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@:@gd:6c4dd:64c:UFRIs) Rmnv4XR4qPHCsDRFopcza_S4 -q=7dq_7dpcza_S4 -q=7.q_7.pcza_S4 -q=74q_74pcza_S4 -q=7jq_7jpcza_S4 -7=mj7_mjpcza_ -4;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'jLjjjjjj44jjjjjj;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g6:djd:4:jd6:R4UI FsRv)m44nXqCRPsFHDozRpa.c_ -7Sqd7=qdz_pa.c_ -7Sq.7=q.z_pa.c_ -7Sq47=q4z_pa.c_ -7Sqj7=qjz_pa.c_ -mS7jm=7jz_pa.c_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'j4jjjjjjjjjjjj4j"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@:@gd:cn4dd:c4n:UFRIs) Rmnv4XR4qPHCsDRFopcza_Sd -q=7dq_7dpcza_Sd -q=7.q_7.pcza_Sd -q=74q_74pcza_Sd -q=7jq_7jpcza_Sd -7=mj7_mjpcza_ -d;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'jLjj4jjjjjjjj4jj;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gc:d.d:4:.dc:R4UI FsRv)m44nXqCRPsFHDozRpacc_ -7Sqd7=qdz_pacc_ -7Sq.7=q.z_pacc_ -7Sq47=q4z_pacc_ -7Sqj7=qjz_pacc_ -mS7jm=7jz_pacc_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@:@gd:dU4dd:d4U:UFRIs) Rmnv4XR4qPHCsDRFopcza_S6 -q=7dq_7dpcza_S6 -q=7.q_7.pcza_S6 -q=74q_74pcza_S6 -q=7jq_7jpcza_S6 -7=mj7_mjpcza_ -6;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gd:dcd:4:cdd:R4UI FsRv)m44nXqCRPsFHDozRpanc_ -7Sqd7=qdz_panc_ -7Sq.7=q.z_panc_ -7Sq47=q4z_panc_ -7Sqj7=qjz_panc_ -mS7jm=7jz_panc_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@:@gd:dj4dd:d4j:UFRIs) Rmnv4XR4qPHCsDRFopcza_S( -q=7dq_7dpcza_S( -q=7.q_7.pcza_S( -q=74q_74pcza_S( -q=7jq_7jpcza_S( -7=mj7_mjpcza_ -(;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g.:dnd:4:nd.:R4UI FsRv)m44nXqCRPsFHDozRpaUc_ -7Sqd7=qdz_paUc_ -7Sq.7=q.z_paUc_ -7Sq47=q4z_paUc_ -7Sqj7=qjz_paUc_ -mS7jm=7jz_paUc_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@:@gd:..4dd:.4.:UFRIs) Rmnv4XR4qPHCsDRFopcza_Sg -q=7dq_7dpcza_Sg -q=7.q_7.pcza_Sg -q=74q_74pcza_Sg -q=7jq_7jpcza_Sg -7=mj7_mjpcza_ -g;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g4:dUd:4:Ud4:R4gI FsRv)m44nXqCRPsFHDozRpa4c_jq -S7qd=7pd_z_ac4Sj -q=7.q_7.pcza_ -4jS4q7=4q7_apzcj_4 -7Sqj7=qjz_pa4c_j7 -Sm7j=mpj_z_ac4 -j;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g4:dcd:4:cd4:R4gI FsRv)m44nXqCRPsFHDozRpa4c_4q -S7qd=7pd_z_ac4S4 -q=7.q_7.pcza_ -44S4q7=4q7_apzc4_4 -7Sqj7=qjz_pa4c_47 -Sm7j=mpj_z_ac4 -4;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g4:djd:4:jd4:R4gI FsRv)m44nXqCRPsFHDozRpa4c_.q -S7qd=7pd_z_ac4S. -q=7.q_7.pcza_ -4.S4q7=4q7_apzc._4 -7Sqj7=qjz_pa4c_.7 -Sm7j=mpj_z_ac4 -.;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gj:dnd:4:ndj:R4gI FsRv)m44nXqCRPsFHDozRpa4c_dq -S7qd=7pd_z_ac4Sd -q=7.q_7.pcza_ -4dS4q7=4q7_apzcd_4 -7Sqj7=qjz_pa4c_d7 -Sm7j=mpj_z_ac4 -d;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gj:d.d:4:.dj:R4gI FsRv)m44nXqCRPsFHDozRpa4c_cq -S7qd=7pd_z_ac4Sc -q=7.q_7.pcza_ -4cS4q7=4q7_apzcc_4 -7Sqj7=qjz_pa4c_c7 -Sm7j=mpj_z_ac4 -c;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gg:.Ud:4:U.g:R4gI FsRv)m44nXqCRPsFHDozRpa4c_6q -S7qd=7pd_z_ac4S6 -q=7.q_7.pcza_ -46S4q7=4q7_apzc6_4 -7Sqj7=qjz_pa4c_67 -Sm7j=mpj_z_ac4 -6;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gg:.cd:4:c.g:R4gI FsRv)m44nXqCRPsFHDozRpa4c_nq -S7qd=7pd_z_ac4Sn -q=7.q_7.pcza_ -4nS4q7=4q7_apzcn_4 -7Sqj7=qjz_pa4c_n7 -Sm7j=mpj_z_ac4 -n;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gg:.jd:4:j.g:R4gI FsRv)m44nXqCRPsFHDozRpa4c_(q -S7qd=7pd_z_ac4S( -q=7.q_7.pcza_ -4(S4q7=4q7_apzc(_4 -7Sqj7=qjz_pa4c_(7 -Sm7j=mpj_z_ac4 -(;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gU:.nd:4:n.U:R4gI FsRv)m44nXqCRPsFHDozRpa4c_Uq -S7qd=7pd_z_ac4SU -q=7.q_7.pcza_ -4US4q7=4q7_apzcU_4 -7Sqj7=qjz_pa4c_U7 -Sm7j=mpj_z_ac4 -U;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gU:..d:4:..U:R4gI FsRv)m44nXqCRPsFHDozRpa4c_gq -S7qd=7pd_z_ac4Sg -q=7.q_7.pcza_ -4gS4q7=4q7_apzcg_4 -7Sqj7=qjz_pa4c_g7 -Sm7j=mpj_z_ac4 -g;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g(:.Ud:4:U.(:R4gI FsRv)m44nXqCRPsFHDozRpa.c_jq -S7qd=7pd_z_ac.Sj -q=7.q_7.pcza_ -.jS4q7=4q7_apzcj_. -7Sqj7=qjz_pa.c_j7 -Sm7j=mpj_z_ac. -j;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g(:.cd:4:c.(:R4gI FsRv)m44nXqCRPsFHDozRpa.c_4q -S7qd=7pd_z_ac.S4 -q=7.q_7.pcza_ -.4S4q7=4q7_apzc4_. -7Sqj7=qjz_pa.c_47 -Sm7j=mpj_z_ac. -4;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@g(:.jd:4:j.(:R4gI FsRv)m44nXqCRPsFHDozRpa.c_.q -S7qd=7pd_z_ac.S. -q=7.q_7.pcza_ -..S4q7=4q7_apzc._. -7Sqj7=qjz_pa.c_.7 -Sm7j=mpj_z_ac. -.;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gn:.nd:4:n.n:R4gI FsRv)m44nXqCRPsFHDozRpa.c_dq -S7qd=7pd_z_ac.Sd -q=7.q_7.pcza_ -.dS4q7=4q7_apzcd_. -7Sqj7=qjz_pa.c_d7 -Sm7j=mpj_z_ac. -d;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@gn:.d::g.:nd4I6RFRs X.m)RsPCHoDFR)Xm.j_0 -=Sqqm_X)0._jA -S=XA_m_).0Sj -Z_=ZX.m)_;0j -RNH#_$MMsFbkRMC4s; -Rg@@:4.n:.g:n44:6FRIsX RmR).PHCsDRFoX.m)_ -04Sqq=_)Xm.4_0 -=SAAm_X)0._4Z -S=XZ_m_).0 -4;N#HR$MM_FkbsM4CR;R -s@:@g.:6gg6:.g6:4RsIF mRX)P.RCDsHFXoRm_).0S. -q_=qX.m)_ -0.SAA=_)Xm.._0 -=SZZm_X)0._.N; -H$R#MF_MbMskC;R4 -@sR@.g:6g(::(.6:R46I FsR)Xm.CRPsFHDomRX)0._dq -S=Xq_m_).0Sd -A_=AX.m)_ -0dSZZ=_)Xm.d_0;H -NRM#$_bMFsCkMR -4;s@R@g6:.6::g.:664I6RFRs X.m)RsPCHoDFR)Xm.c_0 -=Sqqm_X)0._cA -S=XA_m_).0Sc -Z_=ZX.m)_;0c -RNH#_$MMsFbkRMC4s; -Rg@@:d.6:.g:64d:6FRIsX RmR).PHCsDRFoX.m)_ -06Sqq=_)Xm.6_0 -=SAAm_X)0._6Z -S=XZ_m_).0 -6;N#HR$MM_FkbsM4CR;R -s@:@g.:64g6:.46:4RsIF mRX)P.RCDsHFXoRm_).0Sn -q_=qX.m)_ -0nSAA=_)Xm.n_0 -=SZZm_X)0._nN; -H$R#MF_MbMskC;R4 -@sR@.g:cgg::g.c:R46I FsR)Xm.CRPsFHDomRX)0._(q -S=Xq_m_).0S( -A_=AX.m)_ -0(SZZ=_)Xm.(_0;H -NRM#$_bMFsCkMR -4;s@R@gc:.(::g.:c(4I6RFRs X.m)RsPCHoDFR)Xm.U_0 -=Sqqm_X)0._UA -S=XA_m_).0SU -Z_=ZX.m)_;0U -RNH#_$MMsFbkRMC4s; -Rg@@:6.c:.g:c46:6FRIsX RmR).PHCsDRFoX.m)_ -0gSqq=_)Xm.g_0 -=SAAm_X)0._gZ -S=XZ_m_).0 -g;N#HR$MM_FkbsM4CR;R -s@:@g.:cdgc:.dn:4RsIF mRX)P.RCDsHFXoRm_).0 -4jSqq=_)Xm.4_0jA -S=XA_m_).0 -4jSZZ=_)Xm.4_0jN; -H$R#MF_MbMskC;R4 -@sR@.g:cg4::4.c:R4nI FsR)Xm.CRPsFHDomRX)0._4S4 -q_=qX.m)_404 -=SAAm_X)0._4S4 -Z_=ZX.m)_404;H -NRM#$_bMFsCkMR -4;s@R@gd:.g::g.:dg4InRFRs X.m)RsPCHoDFR)Xm.4_0.q -S=Xq_m_).0 -4.SAA=_)Xm.4_0.Z -S=XZ_m_).0;4. -RNH#_$MMsFbkRMC4s; -Rg@@:(.d:.g:d4(:nFRIsX RmR).PHCsDRFoX.m)_d04 -=Sqqm_X)0._4Sd -A_=AX.m)_d04 -=SZZm_X)0._4 -d;N#HR$MM_FkbsM4CR;R -s@:@g.:d6gd:.6n:4RsIF mRX)P.RCDsHFXoRm_).0 -4cSqq=_)Xm.4_0cA -S=XA_m_).0 -4cSZZ=_)Xm.4_0cN; -H$R#MF_MbMskC;R4 -@sR@.g:dgd::d.d:R4nI FsR)Xm.CRPsFHDomRX)0._4S6 -q_=qX.m)_604 -=SAAm_X)0._4S6 -Z_=ZX.m)_604;H -NRM#$_bMFsCkMR -4;s@R@gd:.4::g.:d44InRFRs X.m)RsPCHoDFR)Xm.4_0nq -S=Xq_m_).0 -4nSAA=_)Xm.4_0nZ -S=XZ_m_).0;4n -RNH#_$MMsFbkRMC4s; -Rg@@:g..:.g:.4g:nFRIsX RmR).PHCsDRFoX.m)_(04 -=Sqqm_X)0._4S( -A_=AX.m)_(04 -=SZZm_X)0._4 -(;N#HR$MM_FkbsM4CR;R -s@:@g.:.(U.:.(c:4RsIF )Rm.CRPsFHDo)Rm.4_0Uq -S=mq_)0._4SU -A_=Am_).0 -4USZZ=_.m)_U04;H -NRM#$_bMFsCkMR -4;s@R@g.:.6::U.:.64I.RFRs QRhePHCsDRFoQ_hejq -S=Qq_hje_ -=SZZh_Qe;_j -RNH#_$MMsFbkRMC4s; -Rg@@:d..:.g:.4d:nFRIsq RhR7.PHCsDRFoq.h7_g04 -=Sqqh_q70._4Sg -A_=Aq.h7_g04 -=SZZh_q70._4 -g;N#HR$MM_FkbsM4CR;R -s@:@g.:.4U.:.4.:4RsIF hRQeCRPsFHDohRQe -_4Sqq=_eQh_S4 -Z_=ZQ_he4N; -H$R#MF_MbMskC;R4 -@sR@.g:4gg::g.4:R4nI FsR7qh.CRPsFHDohRq70._.Sj -q_=qq.h7_j0. -=SAAh_q70._.Sj -Z_=Zq.h7_j0.;H -NRM#$_bMFsCkMR -4;y-------------------------------- ---@ - - -ftell; -@E@MR@:4d.:dn(d:.n4:.RsIF kRF00bk_O8CFs8CUCRPsFHDoN; -PVR3FNslDC_ODNDMl"CRFbk0k80_C8OFC"sU;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNCFR"kk0b0C_8OCF8s;U" -RNPFosH_#HM0V_FRk"F00bk_O8CFs8CU -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_ppe4N_sIk_F0M_H#803CHO_M"#0;P -NRM#$_Cbs#PCsC;R4 -RNP3l#00#DH0llCko#NC3Rjjjjjj -j;N3PR#00lD0H#0CHlRjj3jjjjj -; - -@HR@:4d.:d(gd:.(4:4R ODR OD; - - - -@HR@:4d.:dUgd:.Uj:4RrHM(9:jRrHM(9:j; - - - -@FR@:4d.:c(4.n:c4(:UkRF0:r.j;9R -RNH#_$Mb#sCCCsPR -4; -@FR@:4d.:cg4.4:c4g:6NRPDRH8;H -NRM#$_Cbs#PCsC;R4 -@FR@:4d.:c4gc:.4j:.R_HM#O$MCD8_L:r(j;9R -@FR@:4d.:6.4.n:6..:nNRsIN_D0COE8:r(j;9R -RNHb#sCCCsPR -4;y-------------------------------- ---@ - - -ftell; -@E@MR@:4d4:nj(n:4jg:4RsIF 8R0O8c8sE_#FRs0PHCsD;Fo -RNP3sVFl_NDODCDMCNlR8"0O8c8sE_#F"s0;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNC0R"88Oc8#s_E0Fs"N; -PsRFHHo_M_#0F"VR0c8O8_8s#sEF0 -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_ppe4N_sIk_F0M_H#0038HO_M"#0;P -NRM#$_Cbs#PCsC;R4 -RNP3l#00#DH0llCko#NC3Rjjjjjj -j;N3PR#00lD0H#0CHlRjj3jjjjj -; - -@HR@:4d4:nj.44:n.j:(sR0HCoossR0HCoos -; - -@HR@:4d4:njd4j:ndj:dDRO d#r:Rj9O#D rjd:9 -; - -@FR@:4d4:njd4n:ndj:UkRF0:r(j;9R -RNH#_$Mb#sCCCsPR -4;y-------------------------------- ---@ - - -ftell; -@E@MR@:4dd:c4(c:d4c:4RsIF sR0HHo_MPPRCDsHF -o;N3PRVlFsNOD_CMDDNRlC"H0soM_HP -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"H0soM_HP -";NFPRs_HoH0M#_RFV"H0soM_HP -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_O08_NOEMDMC_IsN_0Fk_#HM0s30HHo_MHP_M4#0"N; -P$R#Ms_bCs#CP4CR;P -NR03#lH0D#C0llNk#ojCR3jjjj;jj -RNP3l#00#DH0l0HC3Rjjjjjj -j; -@HR@:4dd:c44dn:c44:(MRHR;HM -RNH#_$M bCCR -4; -@FR@:4dd:c44dg:c.4:4kRF0 -R;N#HR$ M_CRCb4y; ----------------------------------@- - - - - -ftell; -@E@MR@:4dd::(dn:.RsIF 8R0OE_ONCMMDH_VVFF_kP0RCDsHF -o;N3PRVlFsNOD_CMDDNRlC"O08_NOEMDMC_VVHFk_F0 -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"O08_NOEMDMC_VVHFk_F0 -";NFPRs_HoH0M#_RFV"O08_NOEMDMC_VVHFk_F0 -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03O08_NOEMDMC_VVHFk_F0M_H#;0" -RNP3l#00#DH0llCko#NC3Rjjjjjj -j;N3PR#00lD0H#0CHlRjj3jjjjj -; - -@HR@:4dcj:4:4c:cCRs#RC0sCC#0 -; - -@HR@:4d6j:4:46:(DRbDD_O d#r:Rj9b_DDO#D rjd:9 -; - -@HR@:4dnj:4:4n:6FRONCs#r:.(jO9RF#NsC(r.:;j9 -@HR@:4d(j:4:4(:dsR0H0oRs;Ho -@FR@:4dUj:4:.U:.HRVV8F_N_0NFrk0dj4:9 -R; -@HR@:4dgj:4:4g:UHRVVsF_8RCMVFHV_Cs8M -; - -@FR@:4d44j:jj:4:R4gVFHV_bCl0;$R -@FR@:4d444:j4:4:R4n0_8OFrk0(9:jRs; -R4@@d(:g::4jg.(:.FRIsV RHdVF.R8OPHCsDRFoVFHVdO.8_#HM07 -SNr0Ndj4:9N=70VN_HdVF._8OH0M#r:d4jS9 -WDsBF=O WDsBF_O VFHVdO.8_#HM0) -S8FBDO) =8FBDOV _HdVF._8OH0M# -sSW WM=s_ MVFHVdO.8_#HM0) -S8= M)M8 _VVHF8d.OM_H#S0 -)CC#0C=)#_C0VFHVdO.8_#HM0) -Su#)CC)0=u#)CCV0_HdVF._8OH0M# -rSTdj4:9_=TVFHVdO.8_#HM04rd: -j9Sb l0 $=l$b0_VVHF8d.OM_H#S0 -wDkD=DwkDH_VV.Fd8HO_M;#0 -RNH#_$MMsFbkRMC4s; -R4@@dj:g::4(g.j:UFRIsF Rkk0b0C_8OCF8sPURCDsHF8oRCMO_CHo_M -#0S OD= OD_O8C_oMC_#HM0H -SM:r(jH9=MC_8OC_MoM_H#(0r: -j9S0Fkrj.:9k=F0C_8OC_MoM_H#.0r: -j9SDPNHP8=N8DH_O8C_oMC_#HM0H -SM$_#M8OC_rDL(9:j=_HM#O$MCD8_LC_8OC_MoM_H#(0r: -j9SIsN_0DNO8ECrj(:9N=sIN_D0COE8C_8OC_MoM_H#(0r:;j9 -RNH#_$MMsFbkRMC4N; -H$R#Ms_bCs#CP4CR;R -s@d@4::Ud4U(:dc:.RsIF kRF00bk_O8CFs8CUCRPsFHDoCR8OM_H#S0 -O=D O_D 8_COH0M# -MSHrj(:9M=H_O8C_#HM0:r(jS9 -Frk0.9:j=0Fk_O8C_#HM0:r.jS9 -PHND8N=PD_H88_COH0M# -MSH_M#$O_C8D(Lr:=j9H#M_$CMO8L_D_O8C_#HM0:r(jS9 -s_NIDON0ErC8(9:j=IsN_0DNO8EC_O8C_#HM0:r(j -9;N#HR$MM_FkbsM4CR;R -s@d@4::ng4n6:gn:.RsIF 8R0O8c8sE_#FRs0PHCsDRFo0_8OM_CoH0M# -sS0HCooss=0HCoos8_0OC_MoM_H#S0 -O#D rjd:9D=O 0#_8MO_CHo_Mr#0d9:j -kSF0:r(jF9=k00_8MO_CHo_Mr#0(9:j;H -NRM#$_bMFsCkMR -4;N#HR$bM_sCC#sRPC4s; -R4@@dc:n::46n.c:.FRIs0 R88Oc8#s_E0FsRsPCHoDFRO08_#HM00 -SsoHoC0s=soHoC0s_8HO_M -#0S OD#:rdjO9=D_ #0_8OH0M#rjd:9F -Sk(0r:=j9F_k00_8OH0M#rj(:9N; -H$R#MF_MbMskC;R4 -@sR@:4dc4d:jd:c:R.dI FsRH0soM_HPCRPsFHDosR0HHo_MHP_Md#0 -MSH=_HM0osH_PHM_#HM0Sd -F=k0F_k00osH_PHM_#HM0 -d;N#HR$MM_FkbsM4CR;R -s@d@4::d(4dj:(d:.RsIF sR0HHo_MPPRCDsHF0oRs_HoH_MPH0M#.H -SMM=H_H0soM_HPM_H# -0.S0Fk=0Fk_H0soM_HPM_H#;0. -RNH#_$MMsFbkRMC4s; -R4@@d4:d::4jd.4:dFRIs0 Rs_HoHRMPPHCsDRFo0osH_PHM_#HM0S4 -HHM=Ms_0HHo_MHP_M4#0 -kSF0k=F0s_0HHo_MHP_M4#0;H -NRM#$_bMFsCkMR -4;@ - - -ftell; -@E@MR@:46U::(U6:4RsIF HRVVjFc_R8OPHCsD;Fo -RNP3sVFl_NDODCDMCNlRH"VVjFc_"8O;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNCVR"HcVFjO_8"N; -PsRFHHo_M_#0F"VRVFHVc8j_O -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03VVHFF_OD0COFHs_M3#0VFHVcHj_M"#0;P -NR7ht_B7)_1vqi;R4 -RNP3l#00#DH0llCko#NC3Rjjjjjj -j;N3PR#00lD0H#0CHlRjj3jjjjj -; - -@HR@:46UU:4:.U:4NR70dNrg9:jR07NNgrd:;j9 -@HR@:46Uc:.:dU:jsRWBODF sRWBODF -; - -@HR@:46Ud:d:dU:g8R)BODF 8R)BODF -; - -@HR@:46U.:c:cU:6sRW WMRs; M -@HR@:46UU:c:6U:48R) )MR8; M -@HR@:46Uc:6:6U:UCR)#RC0)CC#0 -; - -@HR@:46U4:n:nU:(uR))CC#0uR))CC#0 -; - -@FR@:46Uj:(:(U:jrRTdjg:9 -R; -@FR@:46g::cgR:U 0lb$ -R; -@FR@:46g4:4:4g:ckRwD;DR -@sR@:46g:g(4gj:g4(:4FRIsB RBBz.RsPCHoDFR -N4ShBQ=hBQ_ -N4S=qjqNj_4A -Sjj=A_ -N4S=BjBNj_47 -Sjj=7_ -N4S=q4qN4_4A -S44=A_ -N4S=B4BN4_47 -S44=7_ -N4S=1j1Nj_41 -S44=1_ -N4SzBmam=BzNa_4N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46g:g4Ug:g44:.RsIF pRemCRPsFHDoOR#k_LNP_DFH0M# -=SZZO_#k_LNP_DFH0M#;H -NRM#$_bMFsCkMR -4;s@R@4g6:UUg::ggU:R.4I FsRQe]RsPCHoDFRk#OLPN_EHH_M -#0SZZ=_k#OLPN_EHH_M;#0 -RNH#_$MMsFbkRMC4s; -R4@@6U:g6j:4:6gU:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lbcB -SQBh=QVh_k_DDO_lbcq -Sjj=q_DVkDl_Ob -_cS=AjAVj_k_DDO_lbcB -Sjj=B_DVkDl_Ob -_cS=7j7Vj_k_DDO_lbcq -S44=q_DVkDl_Ob -_cS=A4AV4_k_DDO_lbcB -S44=B_DVkDl_Ob -_cS=747V4_k_DDO_lbc1 -Sjj=1_DVkDl_Ob -_cS=141V4_k_DDO_lbcB -Sm=zaBamz_DVkDl_Ob;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6(:g(j:4:(g(:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lbdB -SQBh=QVh_k_DDO_lbdq -Sjj=q_DVkDl_Ob -_dS=AjAVj_k_DDO_lbdB -Sjj=B_DVkDl_Ob -_dS=7j7Vj_k_DDO_lbdq -S44=q_DVkDl_Ob -_dS=A4AV4_k_DDO_lbdB -S44=B_DVkDl_Ob -_dS=747V4_k_DDO_lbd1 -Sjj=1_DVkDl_Ob -_dS=141V4_k_DDO_lbdB -Sm=zaBamz_DVkDl_Ob;_d -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6n:ggj:4:ggn:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lb.B -SQBh=QVh_k_DDO_lb.q -Sjj=q_DVkDl_Ob -_.S=AjAVj_k_DDO_lb.B -Sjj=B_DVkDl_Ob -_.S=7j7Vj_k_DDO_lb.q -S44=q_DVkDl_Ob -_.S=A4AV4_k_DDO_lb.B -S44=B_DVkDl_Ob -_.S=747V4_k_DDO_lb.1 -Sjj=1_DVkDl_Ob -_.S=141V4_k_DDO_lb.B -Sm=zaBamz_DVkDl_Ob;_. -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6n:g4j:4:4gn:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lb4B -SQBh=QVh_k_DDO_lb4q -Sjj=q_DVkDl_Ob -_4S=AjAVj_k_DDO_lb4B -Sjj=B_DVkDl_Ob -_4S=7j7Vj_k_DDO_lb4q -S44=q_DVkDl_Ob -_4S=A4AV4_k_DDO_lb4B -S44=B_DVkDl_Ob -_4S=747V4_k_DDO_lb41 -Sjj=1_DVkDl_Ob -_4S=141V4_k_DDO_lb4B -Sm=zaBamz_DVkDl_Ob;_4 -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@66:gdj:4:dg6:R4gI FsRzBB.PBRCDsHFVoRk_DDO_lbjB -SQBh=QVh_k_DDO_lbjq -Sjj=q_DVkDl_Ob -_jS=AjAVj_k_DDO_lbjB -Sjj=B_DVkDl_Ob -_jS=7j7Vj_k_DDO_lbjq -S44=q_DVkDl_Ob -_jS=A4AV4_k_DDO_lbjB -S44=B_DVkDl_Ob -_jS=747V4_k_DDO_lbj1 -Sjj=1_DVkDl_Ob -_jS=141V4_k_DDO_lbjB -Sm=zaBamz_DVkDl_Ob;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6c:g6j:4:6gc:R..I FsRzBB.PBRCDsHFVoRk_DDO_lbONH_ -QSBhQ=Bhk_VDOD_lOb_H -_NS=qjqVj_k_DDO_lbONH_ -jSA=_AjVDkD_bOl__OHNB -Sjj=B_DVkDl_ObH_O_SN -77j=jk_VDOD_lOb_H -_NS=q4qV4_k_DDO_lbONH_ -4SA=_A4VDkD_bOl__OHNB -S44=B_DVkDl_ObH_O_SN -774=4k_VDOD_lOb_H -_NS=1j1Vj_k_DDO_lbONH_ -4S1=_14VDkD_bOl__OHNB -Sm=zaBamz_DVkDl_ObH_O_ -N;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@6@4:(gd::4jg:d(4I4RFRs B.BzBCRPsFHDojRN -QSBhQ=Bhj_N -jSq=_qjNSj -AAj=jj_N -jSB=_BjNSj -77j=jj_N -4Sq=_q4NSj -AA4=4j_N -4SB=_B4NSj -774=4j_N -jS1=_1jNSj -114=4j_N -mSBzBa=m_zaN -j;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'4Lj44jj4jj44jj44;j" -RNHQahQj4R"nj'L4j4j444jj44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@6@4:gg.::4jg:.g.IjRFRs B.BzBCRPsFHDolRCb_0$O_lbcB -SQBh=QCh_l$b0_bOl_Sc -qqj=jl_Cb_0$O_lbcA -Sjj=A_bCl0O$_lcb_ -jSB=_BjC0lb$l_Ob -_cS=7j7Cj_l$b0_bOl_Sc -qq4=4l_Cb_0$O_lbcA -S44=A_bCl0O$_lcb_ -4SB=_B4C0lb$l_Ob -_cS=747C4_l$b0_bOl_Sc -11j=jl_Cb_0$O_lbc1 -S44=1_bCl0O$_lcb_ -mSBzBa=m_zaC0lb$l_Ob;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6.:g4j:4:4g.:R.jI FsRzBB.PBRCDsHFCoRl$b0_bOl_Sd -B=QhB_QhC0lb$l_Ob -_dS=qjqCj_l$b0_bOl_Sd -AAj=jl_Cb_0$O_lbdB -Sjj=B_bCl0O$_ldb_ -jS7=_7jC0lb$l_Ob -_dS=q4qC4_l$b0_bOl_Sd -AA4=4l_Cb_0$O_lbdB -S44=B_bCl0O$_ldb_ -4S7=_74C0lb$l_Ob -_dS=1j1Cj_l$b0_bOl_Sd -114=4l_Cb_0$O_lbdB -Sm=zaBamz_bCl0O$_ldb_;H -NRM#$_bMFsCkMR -4;NQHRhBK a44_Rm"h"N; -HhRQKa B4R_j""hm;H -NRQQha"4R4Ln'44jj44jj4jj44jj4"N; -HhRQQRaj"'4nLj4j4j4j444jj44jj -";N3HR#_$MNV00FNsl0x#HCQR"h4Qa=R4nQahQjn=4"N; -H#R3$NM_0F0Vs0lNRh"QQ=a4XhRQQ=ajX -";s@R@4g6:44d:j4:gdj:.RsIF BRBzR.BPHCsDRFoC0lb$l_Ob -_.ShBQ=hBQ_bCl0O$_l.b_ -jSq=_qjC0lb$l_Ob -_.S=AjACj_l$b0_bOl_S. -BBj=jl_Cb_0$O_lb.7 -Sjj=7_bCl0O$_l.b_ -4Sq=_q4C0lb$l_Ob -_.S=A4AC4_l$b0_bOl_S. -BB4=4l_Cb_0$O_lb.7 -S44=7_bCl0O$_l.b_ -jS1=_1jC0lb$l_Ob -_.S=141C4_l$b0_bOl_S. -Bamz=zBmal_Cb_0$O_lb.N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nLj4j4j4j444jj44jj -";NQHRhjQaRn"4'jL4jj44jj444jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46g:j64gj:j.6:jFRIsB RBBz.RsPCHoDFRbCl0O$_l4b_ -QSBhQ=Bhl_Cb_0$O_lb4q -Sjj=q_bCl0O$_l4b_ -jSA=_AjC0lb$l_Ob -_4S=BjBCj_l$b0_bOl_S4 -77j=jl_Cb_0$O_lb4q -S44=q_bCl0O$_l4b_ -4SA=_A4C0lb$l_Ob -_4S=B4BC4_l$b0_bOl_S4 -774=4l_Cb_0$O_lb41 -Sjj=1_bCl0O$_l4b_ -4S1=_14C0lb$l_Ob -_4SzBmam=BzCa_l$b0_bOl_ -4;N#HR$MM_FkbsM4CR;H -NRKQh 4Ba_"4Rh;m" -RNHQ hKB_a4jhR"m -";NQHRh4QaRn"4'jL4jj44jj444jj44;j" -RNHQahQj4R"n4'Lj4j4j4j4j44jj"4j;H -NR$3#M0_N0sVFl#N0HRxC"QQha44=nhRQQ=aj4;n" -RNH3M#$_0N0VlFsN"0RQahQ4R=XQahQj"=X;R -s@6@4:(Ug::4jU:g(.IjRFRs B.BzBCRPsFHDolRCb_0$O_lbjB -SQBh=QCh_l$b0_bOl_Sj -qqj=jl_Cb_0$O_lbjA -Sjj=A_bCl0O$_ljb_ -jSB=_BjC0lb$l_Ob -_jS=7j7Cj_l$b0_bOl_Sj -qq4=4l_Cb_0$O_lbjA -S44=A_bCl0O$_ljb_ -4SB=_B4C0lb$l_Ob -_jS=747C4_l$b0_bOl_Sj -11j=jl_Cb_0$O_lbj1 -S44=1_bCl0O$_ljb_ -mSBzBa=m_zaC0lb$l_Ob;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"n4'Lj4j4j4j4j44jj"4j;H -NRQQha"jR4Ln'44jj44jj4jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6U:Ugj:4:gUU:R.dI FsRzBB.PBRCDsHFCoRl$b0_bOl__OHNB -SQBh=QCh_l$b0_bOl__OHNq -Sjj=q_bCl0O$_lOb_H -_NS=AjACj_l$b0_bOl__OHNB -Sjj=B_bCl0O$_lOb_H -_NS=7j7Cj_l$b0_bOl__OHNq -S44=q_bCl0O$_lOb_H -_NS=A4AC4_l$b0_bOl__OHNB -S44=B_bCl0O$_lOb_H -_NS=747C4_l$b0_bOl__OHN1 -Sjj=1_bCl0O$_lOb_H -_NS=141C4_l$b0_bOl__OHNB -Sm=zaBamz_bCl0O$_lOb_H;_N -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6U:U4j:4:4UU:R4(I FsRzBB.PBRCDsHFsoR_0oOs -_cShBQ=hBQ_os_O_0scq -Sjj=q_os_O_0scA -Sjj=A_os_O_0scB -Sjj=B_os_O_0sc7 -Sjj=7_os_O_0scq -S44=q_os_O_0scA -S44=A_os_O_0scB -S44=B_os_O_0sc7 -S44=7_os_O_0sc1 -Sjj=1_os_O_0sc1 -S44=1_os_O_0scB -Sm=zaBamz_os_O_0scN; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:(d4Uj:(4d:(FRIsB RBBz.RsPCHoDFRos_O_0sdB -SQBh=Qsh__0oOs -_dS=qjqsj__0oOs -_dS=AjAsj__0oOs -_dS=BjBsj__0oOs -_dS=7j7sj__0oOs -_dS=q4qs4__0oOs -_dS=A4As4__0oOs -_dS=B4Bs4__0oOs -_dS=747s4__0oOs -_dS=1j1sj__0oOs -_dS=141s4__0oOs -_dSzBmam=Bzsa__0oOs;_d -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6n:U6j:4:6Un:R4(I FsRzBB.PBRCDsHFsoR_0oOs -_.ShBQ=hBQ_os_O_0s.q -Sjj=q_os_O_0s.A -Sjj=A_os_O_0s.B -Sjj=B_os_O_0s.7 -Sjj=7_os_O_0s.q -S44=q_os_O_0s.A -S44=A_os_O_0s.B -S44=B_os_O_0s.7 -S44=7_os_O_0s.1 -Sjj=1_os_O_0s.1 -S44=1_os_O_0s.B -Sm=zaBamz_os_O_0s.N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:6(4Uj:64(:(FRIsB RBBz.RsPCHoDFRos_O_0s4B -SQBh=Qsh__0oOs -_4S=qjqsj__0oOs -_4S=AjAsj__0oOs -_4S=BjBsj__0oOs -_4S=7j7sj__0oOs -_4S=q4qs4__0oOs -_4S=A4As4__0oOs -_4S=B4Bs4__0oOs -_4S=747s4__0oOs -_4S=1j1sj__0oOs -_4S=141s4__0oOs -_4SzBmam=Bzsa__0oOs;_4 -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6c:Ugj:4:gUc:R4(I FsRzBB.PBRCDsHFsoR_0oOs -_jShBQ=hBQ_os_O_0sjq -Sjj=q_os_O_0sjA -Sjj=A_os_O_0sjB -Sjj=B_os_O_0sj7 -Sjj=7_os_O_0sjq -S44=q_os_O_0sjA -S44=A_os_O_0sjB -S44=B_os_O_0sj7 -S44=7_os_O_0sj1 -Sjj=1_os_O_0sj1 -S44=1_os_O_0sjB -Sm=zaBamz_os_O_0sjN; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:c44Uj:c44:gFRIsB RBBz.RsPCHoDFRos_O_0sO -HNShBQ=hBQ_os_O_0sO -HNS=qjqsj__0oOsH_ONA -Sjj=A_os_O_0sO -HNS=BjBsj__0oOsH_ON7 -Sjj=7_os_O_0sO -HNS=q4qs4__0oOsH_ONA -S44=A_os_O_0sO -HNS=B4Bs4__0oOsH_ON7 -S44=7_os_O_0sO -HNS=1j1sj__0oOsH_ON1 -S44=1_os_O_0sO -HNSzBmam=Bzsa__0oOsH_ONN; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:dd4Uj:d4d:(FRIsB RBBz.RsPCHoDFRoI_O_0scB -SQBh=QIh__0oOs -_cS=qjqIj__0oOs -_cS=AjAIj__0oOs -_cS=BjBIj__0oOs -_cS=7j7Ij__0oOs -_cS=q4qI4__0oOs -_cS=A4AI4__0oOs -_cS=B4BI4__0oOs -_cS=747I4__0oOs -_cS=1j1Ij__0oOs -_cS=141I4__0oOs -_cSzBmam=BzIa__0oOs;_c -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6.:U6j:4:6U.:R4(I FsRzBB.PBRCDsHFIoR_0oOs -_dShBQ=hBQ_oI_O_0sdq -Sjj=q_oI_O_0sdA -Sjj=A_oI_O_0sdB -Sjj=B_oI_O_0sd7 -Sjj=7_oI_O_0sdq -S44=q_oI_O_0sdA -S44=A_oI_O_0sdB -S44=B_oI_O_0sd7 -S44=7_oI_O_0sd1 -Sjj=1_oI_O_0sd1 -S44=1_oI_O_0sdB -Sm=zaBamz_oI_O_0sdN; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:4(4Uj:44(:(FRIsB RBBz.RsPCHoDFRoI_O_0s.B -SQBh=QIh__0oOs -_.S=qjqIj__0oOs -_.S=AjAIj__0oOs -_.S=BjBIj__0oOs -_.S=7j7Ij__0oOs -_.S=q4qI4__0oOs -_.S=A4AI4__0oOs -_.S=B4BI4__0oOs -_.S=747I4__0oOs -_.S=1j1Ij__0oOs -_.S=141I4__0oOs -_.SzBmam=BzIa__0oOs;_. -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6j:Ugj:4:gUj:R4(I FsRzBB.PBRCDsHFIoR_0oOs -_4ShBQ=hBQ_oI_O_0s4q -Sjj=q_oI_O_0s4A -Sjj=A_oI_O_0s4B -Sjj=B_oI_O_0s47 -Sjj=7_oI_O_0s4q -S44=q_oI_O_0s4A -S44=A_oI_O_0s4B -S44=B_oI_O_0s47 -S44=7_oI_O_0s41 -Sjj=1_oI_O_0s41 -S44=1_oI_O_0s4B -Sm=zaBamz_oI_O_0s4N; -H$R#MF_MbMskC;R4 -RNHQ hKB_a44hR"m -";NQHRhBK aj4_Rm"h"N; -HhRQQRa4"'4nL4j4j4j4j44jj44jj -";NQHRhjQaRn"4'4Lj44jj4jj44jj44;j" -RNH3M#$_0N0VlFsNH0#x"CRQahQ4n=4RQQha4j=n -";N3HR#_$MNV00FNsl0QR"h4Qa=QXRhjQa=;X" -@sR@:46U:j44Uj:j44:(FRIsB RBBz.RsPCHoDFRoI_O_0sjB -SQBh=QIh__0oOs -_jS=qjqIj__0oOs -_jS=AjAIj__0oOs -_jS=BjBIj__0oOs -_jS=7j7Ij__0oOs -_jS=q4qI4__0oOs -_jS=A4AI4__0oOs -_jS=B4BI4__0oOs -_jS=747I4__0oOs -_jS=1j1Ij__0oOs -_jS=141I4__0oOs -_jSzBmam=BzIa__0oOs;_j -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6g:(dj:4:d(g:R4gI FsRzBB.PBRCDsHFIoR_0oOsH_ONB -SQBh=QIh__0oOsH_ONq -Sjj=q_oI_O_0sO -HNS=AjAIj__0oOsH_ONB -Sjj=B_oI_O_0sO -HNS=7j7Ij__0oOsH_ONq -S44=q_oI_O_0sO -HNS=A4AI4__0oOsH_ONB -S44=B_oI_O_0sO -HNS=747I4__0oOsH_ON1 -Sjj=1_oI_O_0sO -HNS=141I4__0oOsH_ONB -Sm=zaBamz_oI_O_0sO;HN -RNH#_$MMsFbkRMC4N; -HhRQKa B4R_4""hm;H -NRKQh 4Ba_"jRh;m" -RNHQahQ44R"nj'L4j4j444jj44jj"4j;H -NRQQha"jR4Ln'jj44jj444jj44jj4"N; -H#R3$NM_0F0Vs0lN#CHxRh"QQ=a44QnRhjQa="4n;H -NR$3#M0_N0sVFlRN0"QQhaX4=RQQhaXj="s; -R4@@6U:(n.:4:n(U:R46I FsR4w71Xd7RsPCHoDFR_wwj7 -S=w7_w -_jS=BiBwi_w -_jS=B7Bw7_w -_jSTT=__wwjN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6U:(d.:4:d(U:R46I FsR4w71XdARsPCHoDFR_ww47 -S=w7_w -_4S=BiBwi_w -_4S=u7uw7_w -_4STT=__ww4N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6U:(j.:4:j(U:R46I FsR4w71Xd7RsPCHoDFR_ww.7 -S=w7_w -_.S=BiBwi_w -_.S=B7Bw7_w -_.STT=__ww.N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:((.:4:(((:R46I FsR4w71Xd7RsPCHoDFR_wwd7 -S=w7_w -_dS=BiBwi_w -_dS=B7Bw7_w -_dSTT=__wwdN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:(c.:4:c((:R46I FsR4w71Xd7RsPCHoDFR_wwc7 -S=w7_w -_cS=BiBwi_w -_cS=B7Bw7_w -_cSTT=__wwcN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:(4.:4:4((:R46I FsR4w71Xd7RsPCHoDFR_ww67 -S=w7_w -_6S=BiBwi_w -_6S=B7Bw7_w -_6STT=__ww6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6n:(U.:4:U(n:R46I FsR4w71Xd7RsPCHoDFR_wwn7 -S=w7_w -_nS=BiBwi_w -_nS=B7Bw7_w -_nSTT=__wwnN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6n:(6.:4:6(n:R46I FsR4w71Xd7RsPCHoDFR_ww(7 -S=w7_w -_(S=BiBwi_w -_(S=B7Bw7_w -_(STT=__ww(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6n:(..:4:.(n:R46I FsR4w71Xd7RsPCHoDFR_wwU7 -S=w7_w -_US=BiBwi_w -_US=B7Bw7_w -_USTT=__wwUN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@66:(g.:4:g(6:R46I FsR4w71Xd7RsPCHoDFR_wwg7 -S=w7_w -_gS=BiBwi_w -_gS=B7Bw7_w -_gSTT=__wwgN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@66:(n.:4:n(6:R4nI FsR4w71Xd7RsPCHoDFR_ww4Sj -7_=7w4w_jB -Sii=B__ww4Sj -BB7=7w_w_ -4jSTT=__ww4 -j;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@4(6:64d:.6:(dn:4RsIF 7Rw471dXCRPsFHDowRw_ -44S77=__ww4S4 -BBi=iw_w_ -44S=B7Bw7_w4_4 -=STTw_w_;44 -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46(:6j4(.:64j:nFRIsw R7d417PXRCDsHFwoRw._4 -=S77w_w_ -4.S=BiBwi_w._4 -7SB=_B7w4w_.T -S=wT_w._4;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@6@4:((c::4.(:c(4InRFRs w174dR7XPHCsDRFow4w_d7 -S=w7_wd_4 -iSB=_Biw4w_dB -S77=B__ww4Sd -T_=Tw4w_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6c:(c.:4:c(c:R4nI FsR4w71Xd7RsPCHoDFR_ww4Sc -7_=7w4w_cB -Sii=B__ww4Sc -BB7=7w_w_ -4cSTT=__ww4 -c;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@4(6:c44:.c:(4n:4RsIF 7Rw471dXCRPsFHDowRw_ -46S77=__ww4S6 -BBi=iw_w_ -46S=B7Bw7_w6_4 -=STTw_w_;46 -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46(:dU4(.:d4U:nFRIsw R7d417PXRCDsHFwoRwn_4 -=S77w_w_ -4nS=BiBwi_wn_4 -7SB=_B7w4w_nT -S=wT_wn_4;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@6@4:6(d::4.(:d64InRFRs w174dR7XPHCsDRFow4w_(7 -S=w7_w(_4 -iSB=_Biw4w_(B -S77=B__ww4S( -T_=Tw4w_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6d:(..:4:.(d:R4nI FsR4w71Xd7RsPCHoDFR_ww4SU -7_=7w4w_UB -Sii=B__ww4SU -BB7=7w_w_ -4USTT=__ww4 -U;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@4(6:.4g:..:(gn:4RsIF 7Rw471dXCRPsFHDowRw_ -4gS77=__ww4Sg -BBi=iw_w_ -4gS=B7Bw7_wg_4 -=STTw_w_;4g -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46(:.n4(.:.4n:nFRIsw R7d417PXRCDsHFwoRwj_. -=S77w_w_ -.jS=BiBwi_wj_. -7SB=_B7w.w_jT -S=wT_wj_.;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@6@4:d(.::4.(:.d4InRFRs w174dR7XPHCsDRFow.w_47 -S=w7_w4_. -iSB=_Biw.w_4B -S77=B__ww.S4 -T_=Tw.w_4N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6.:(j.:4:j(.:R4nI FsR4w71Xd7RsPCHoDFR_ww.S. -7_=7w.w_.B -Sii=B__ww.S. -BB7=7w_w_ -..STT=__ww. -.;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@4(6:44(:.4:((n:4RsIF 7Rw471dXCRPsFHDowRw_ -.dS77=__ww.Sd -BBi=iw_w_ -.dS=B7Bw7_wd_. -=STTw_w_;.d -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46(:4c4(.:44c:nFRIsw R7d417PXRCDsHFwoRwc_. -=S77w_w_ -.cS=BiBwi_wc_. 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-=STTw_w_;d4 -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46n:gj4n.:g4j:nFRIsw R7d417PXRCDsHFwoRw._d -=S77w_w_ -d.S=BiBwi_w._d -7SB=_B7wdw_.T -S=wT_w._d;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@6@4:(nU::4.n:U(4InRFRs w174dR7XPHCsDRFowdw_d7 -S=w7_wd_d -iSB=_Biwdw_dB -S77=B__wwdSd -T_=Twdw_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6U:nc.:4:cnU:R4nI FsR4w71Xd7RsPCHoDFR_wwdSc -7_=7wdw_cB -Sii=B__wwdSc -BB7=7w_w_ -dcSTT=__wwd -c;N#HR$MM_FkbsM4CR;H -NR)t1Rh" q Ap7 -";s@R@4n6:U44:.U:n4n:4RsIF 7Rw471dXCRPsFHDowRw_ -d6S77=__wwdS6 -BBi=iw_w_ -d6S=B7Bw7_w6_d -=STTw_w_;d6 -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46n:(U4n.:(4U:nFRIsw R7d417PXRCDsHFwoRwn_d -=S77w_w_ -dnS=BiBwi_wn_d -7SB=_B7wdw_nT -S=wT_wn_d;H -NRM#$_bMFsCkMR -4;NtHR1")R Ahqp" 7;R -s@6@4:6n(::4.n:(64InRFRs w174dR7XPHCsDRFowdw_(7 -S=w7_w(_d -iSB=_Biwdw_(B -S77=B__wwdS( -T_=Twdw_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:n..:4:.n(:R4nI FsR4w71Xd7RsPCHoDFR_wwdSU -7_=7wdw_UB -Sii=B__wwdSU -BB7=7w_w_ -dUSTT=__wwd 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"s; -R4@@6d:nj.:4:jnd:R4nI FsR4w7uXd7RsPCHoDFR_ww6S. -7_=7w6w_.1 -Suu=1__ww6S. -BBi=iw_w_ -6.S=B7Bw7_w._6 -=STTw_w_;6. -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46n:.n4n.:.4n:nFRIsw R7d4u7PXRCDsHFwoRwd_6 -=S77w_w_ -6dS=1u1wu_wd_6 -iSB=_Biw6w_dB -S77=B__ww6Sd -T_=Tw6w_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6.:n..:4:.n.:R4nI FsR4w7uXd7RsPCHoDFR_ww6Sc -7_=7w6w_c1 -Suu=1__ww6Sc -BBi=iw_w_ -6cS=B7Bw7_wc_6 -=STTw_w_;6c -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46n:4U4n.:44U:nFRIsw R7d4u7PXRCDsHFwoRw6_6 -=S77w_w_ -66S=1u1wu_w6_6 -iSB=_Biw6w_6B -S77=B__ww6S6 -T_=Tw6w_6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@64:nc.:4:cn4:R4nI FsR4w7uXd7RsPCHoDFR_ww6Sn -7_=7w6w_n1 -Suu=1__ww6Sn -BBi=iw_w_ -6nS=B7Bw7_wn_6 -=STTw_w_;6n -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46n:4j4n.:44j:nFRIsw R7d4u7PXRCDsHFwoRw(_6 -=S77w_w_ -6(S=1u1wu_w(_6 -iSB=_Biw6w_(B -S77=B__ww6S( -T_=Tw6w_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6j:nn.:4:nnj:R4nI FsR4w7uXd7RsPCHoDFR_ww6SU -7_=7w6w_U1 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-H1Rt) R"hpqA ;7" -@sR@:466:(U46.:(4U:nFRIsw R7d4u7PXRCDsHFwoRw6_n -=S77w_w_ -n6S=1u1wu_w6_n -iSB=_Biwnw_6B -S77=B__wwnS6 -T_=Twnw_6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:6c.:4:c6(:R4nI FsR4w7uXd7RsPCHoDFR_wwnSn -7_=7wnw_n1 -Suu=1__wwnSn -BBi=iw_w_ -nnS=B7Bw7_wn_n -=STTw_w_;nn -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:(j46.:(4j:nFRIsw R7d4u7PXRCDsHFwoRw(_n -=S77w_w_ -n(S=1u1wu_w(_n -iSB=_Biwnw_(B -S77=B__wwnS( -T_=Twnw_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6n:6n.:4:n6n:R4nI FsR4w7uXd7RsPCHoDFR_wwnSU -7_=7wnw_U1 -Suu=1__wwnSU -BBi=iw_w_ -nUS=B7Bw7_wU_n -=STTw_w_;nU -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:n.46.:n4.:nFRIsw R7d4u7PXRCDsHFwoRwg_n -=S77w_w_ -ngS=1u1wu_wg_n -iSB=_Biwnw_gB -S77=B__wwnSg -T_=Twnw_gN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@66:6U.:4:U66:R4nI FsR4w7uXd7RsPCHoDFR_ww(Sj -7_=7w(w_j1 -Suu=1__ww(Sj -BBi=iw_w_ -(jS=B7Bw7_wj_( -=STTw_w_;(j -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:6c46.:64c:nFRIsw R7d4uAPXRCDsHFwoRw4_( -=S77w_w_ -(4S=1u1wu_w4_( -iSB=_Biw(w_4u -S77=u__ww(S4 -T_=Tw(w_4N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@66:6j.:4:j66:R4nI FsR4w7uXd7RsPCHoDFR_ww(S. -7_=7w(w_.1 -Suu=1__ww(S. -BBi=iw_w_ -(.S=B7Bw7_w._( -=STTw_w_;(. -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:cn46.:c4n:nFRIsw R7d4u7PXRCDsHFwoRwd_( -=S77w_w_ -(dS=1u1wu_wd_( -iSB=_Biw(w_dB -S77=B__ww(Sd -T_=Tw(w_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6c:6..:4:.6c:R4nI FsR4w7uXd7RsPCHoDFR_ww(Sc -7_=7w(w_c1 -Suu=1__ww(Sc -BBi=iw_w_ -(cS=B7Bw7_wc_( -=STTw_w_;(c -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:dU46.:d4U:nFRIsw R7d4u7PXRCDsHFwoRw6_( -=S77w_w_ -(6S=1u1wu_w6_( -iSB=_Biw(w_6B -S77=B__ww(S6 -T_=Tw(w_6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6d:6c.:4:c6d:R4nI FsR4w7uXd7RsPCHoDFR_ww(Sn -7_=7w(w_n1 -Suu=1__ww(Sn -BBi=iw_w_ -(nS=B7Bw7_wn_( -=STTw_w_;(n -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:dj46.:d4j:nFRIsw R7d4u7PXRCDsHFwoRw(_( -=S77w_w_ -((S=1u1wu_w(_( -iSB=_Biw(w_(B -S77=B__ww(S( -T_=Tw(w_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6.:6n.:4:n6.:R4nI FsR4w7uXd7RsPCHoDFR_ww(SU -7_=7w(w_U1 -Suu=1__ww(SU -BBi=iw_w_ -(US=B7Bw7_wU_( -=STTw_w_;(U -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:..46.:.4.:nFRIsw R7d4u7PXRCDsHFwoRwg_( -=S77w_w_ -(gS=1u1wu_wg_( -iSB=_Biw(w_gB -S77=B__ww(Sg -T_=Tw(w_gN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@64:6U.:4:U64:R4nI FsR4w7uXd7RsPCHoDFR_wwUSj -7_=7wUw_j1 -Suu=1__wwUSj -BBi=iw_w_ -UjS=B7Bw7_wj_U -=STTw_w_;Uj -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:4c46.:44c:nFRIsw R7d4u7PXRCDsHFwoRw4_U -=S77w_w_ -U4S=1u1wu_w4_U -iSB=_BiwUw_4B -S77=B__wwUS4 -T_=TwUw_4N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@64:6j.:4:j64:R4nI FsR4w7uXd7RsPCHoDFR_wwUS. -7_=7wUw_.1 -Suu=1__wwUS. -BBi=iw_w_ -U.S=B7Bw7_w._U -=STTw_w_;U. -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:466:jn46.:j4n:nFRIsw R7d4u7PXRCDsHFwoRwd_U -=S77w_w_ -UdS=1u1wu_wd_U -iSB=_BiwUw_dB -S77=B__wwUSd -T_=TwUw_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6j:6..:4:.6j:R4nI FsR4w7uXd7RsPCHoDFR_wwUSc -7_=7wUw_c1 -Suu=1__wwUSc -BBi=iw_w_ -UcS=B7Bw7_wc_U -=STTw_w_;Uc -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:gU4c.:g4U:nFRIsw R7d4u7PXRCDsHFwoRw6_U -=S77w_w_ -U6S=1u1wu_w6_U -iSB=_BiwUw_6B -S77=B__wwUS6 -T_=TwUw_6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6g:cc.:4:ccg:R4nI FsR4w7uXd7RsPCHoDFR_wwUSn -7_=7wUw_n1 -Suu=1__wwUSn -BBi=iw_w_ -UnS=B7Bw7_wn_U -=STTw_w_;Un -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:gj4c.:g4j:nFRIsw R7d4u7PXRCDsHFwoRw(_U -=S77w_w_ -U(S=1u1wu_w(_U -iSB=_BiwUw_(B -S77=B__wwUS( -T_=TwUw_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6U:cn.:4:ncU:R4nI FsR4w7uXd7RsPCHoDFR_wwUSU -7_=7wUw_U1 -Suu=1__wwUSU -BBi=iw_w_ -UUS=B7Bw7_wU_U -=STTw_w_;UU -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:U.4c.:U4.:nFRIsw R7d4u7PXRCDsHFwoRwg_U -=S77w_w_ -UgS=1u1wu_wg_U -iSB=_BiwUw_gB -S77=B__wwUSg -T_=TwUw_gN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:cU.:4:Uc(:R4nI FsR4w7uXd7RsPCHoDFR_wwgSj -7_=7wgw_j1 -Suu=1__wwgSj -BBi=iw_w_ -gjS=B7Bw7_wj_g -=STTw_w_;gj -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:(c4c.:(4c:nFRIsw R7d4u7PXRCDsHFwoRw4_g -=S77w_w_ -g4S=1u1wu_w4_g -iSB=_Biwgw_4B -S77=B__wwgS4 -T_=Twgw_4N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6(:cj.:4:jc(:R4nI FsR4w7uXd7RsPCHoDFR_wwgS. -7_=7wgw_.1 -Suu=1__wwgS. -BBi=iw_w_ -g.S=B7Bw7_w._g -=STTw_w_;g. -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:nn4c.:n4n:nFRIsw R7d4u7PXRCDsHFwoRwd_g -=S77w_w_ -gdS=1u1wu_wd_g -iSB=_Biwgw_dB -S77=B__wwgSd -T_=Twgw_dN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6n:c..:4:.cn:R4nI FsR4w7uXd7RsPCHoDFR_wwgSc -7_=7wgw_c1 -Suu=1__wwgSc -BBi=iw_w_ -gcS=B7Bw7_wc_g -=STTw_w_;gc -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:6U4c.:64U:nFRIsw R7d4u7PXRCDsHFwoRw6_g -=S77w_w_ -g6S=1u1wu_w6_g -iSB=_Biwgw_6B -S77=B__wwgS6 -T_=Twgw_6N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@66:cc.:4:cc6:R4nI FsR4w7uXd7RsPCHoDFR_wwgSn -7_=7wgw_n1 -Suu=1__wwgSn -BBi=iw_w_ -gnS=B7Bw7_wn_g -=STTw_w_;gn -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:6j4c.:64j:nFRIsw R7d4u7PXRCDsHFwoRw(_g -=S77w_w_ -g(S=1u1wu_w(_g -iSB=_Biwgw_(B -S77=B__wwgS( -T_=Twgw_(N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6c:cn.:4:ncc:R4nI FsR4w7uXd7RsPCHoDFR_wwgSU -7_=7wgw_U1 -Suu=1__wwgSU -BBi=iw_w_ -gUS=B7Bw7_wU_g -=STTw_w_;gU -RNH#_$MMsFbkRMC4N; -H1Rt) R"hpqA ;7" -@sR@:46c:c.4c.:c4.:nFRIsw R7d4u7PXRCDsHFwoRwg_g -=S77w_w_ -ggS=1u1wu_wg_g -iSB=_Biwgw_gB -S77=B__wwgSg -T_=Twgw_gN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6d:cU.:4:Ucd:R4(I FsR4w7uXd7RsPCHoDFR_ww4 -jjS77=__ww4 -jjS=1u1wu_wj_4jB -Sii=B__ww4 -jjS=B7Bw7_wj_4jT -S=wT_wj_4jN; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6d:cc.:4:ccd:R4(I FsR4w7uXdARsPCHoDFR_ww4 -j4S77=__ww4 -j4S=1u1wu_wj_44B -Sii=B__ww4 -j4S=u7uw7_wj_44T -S=wT_wj_44N; -H$R#MF_MbMskC;R4 -RNHtR1)"q hA7p "s; -R4@@6j:c(d:4:(cj:R.6I FsRuu7Wi4n7CRPsFHDo8RbbN_sl__j4 -_jSd7Q6Q=7db6_8sb_Njl__j4_ -QS7d7c=Q_dcb_8bs_Nlj__4j7 -SQ=dd7dQd_bb8_lsN_4j__Sj -7.Qd=d7Q.8_bbN_sl__j4 -_jSd7Q4Q=7db4_8sb_Njl__j4_ -QS7d7j=Q_djb_8bs_Nlj__4j7 -SQ=.g7gQ._bb8_lsN_4j__Sj -7UQ.=.7QU8_bbN_sl__j4 -_jS.7Q(Q=7.b(_8sb_Njl__j4_ -QS7.7n=Q_.nb_8bs_Nlj__4j7 -SQ=.676Q._bb8_lsN_4j__Sj -7cQ.=.7Qc8_bbN_sl__j4 -_jS.7QdQ=7.bd_8sb_Njl__j4_ -QS7.7.=Q_..b_8bs_Nlj__4j7 -SQ=.474Q._bb8_lsN_4j__Sj -7jQ.=.7Qj8_bbN_sl__j4 -_jS47QgQ=74bg_8sb_Njl__j4_ -QS747U=Q_4Ub_8bs_Nlj__4j7 -SQ=4(7(Q4_bb8_lsN_4j__Sj -7nQ4=47Qn8_bbN_sl__j4 -_jS47Q6Q=74b6_8sb_Njl__j4_ -QS747c=Q_4cb_8bs_Nlj__4j7 -SQ=4d7dQ4_bb8_lsN_4j__Sj -7.Q4=47Q.8_bbN_sl__j4 -_jS47Q4Q=74b4_8sb_Njl__j4_ -QS747j=Q_4jb_8bs_Nlj__4j7 -SQ7g=Qbg_8sb_Njl__j4_ -QS7UQ=7U8_bbN_sl__j4 -_jS(7Q=(7Q_bb8_lsN_4j__Sj -7=Qn7_Qnb_8bs_Nlj__4j7 -SQ76=Qb6_8sb_Njl__j4_ -QS7cQ=7c8_bbN_sl__j4 -_jSd7Q=d7Q_bb8_lsN_4j__Sj -7=Q.7_Q.b_8bs_Nlj__4j7 -SQ74=Qb4_8sb_Njl__j4_ -QS7jQ=7j8_bbN_sl__j4 -_jSWq7U7=qWbU_8sb_Njl__j4_ -7SqWq(=7_W(b_8bs_Nlj__4jq -S7=Wnqn7W_bb8_lsN_4j__Sj -q67W=Wq768_bbN_sl__j4 -_jSWq7c7=qWbc_8sb_Njl__j4_ -7SqWqd=7_Wdb_8bs_Nlj__4jq -S7=W.q.7W_bb8_lsN_4j__Sj -q47W=Wq748_bbN_sl__j4 -_jSWq7j7=qWbj_8sb_Njl__j4_ - SAd =Ad8_bbN_sl__j4 -_jS.A =.A _bb8_lsN_4j__Sj -A= 4A_ 4b_8bs_Nlj__4jA -S Aj= bj_8sb_Njl__j4_ - SBW =BW8_bbN_sl__j4 -_jSiBpWp=BibW_8sb_Njl__j4_ -1SBWB.=1_W.b_8bs_Nlj__4jB -S1=W4B41W_bb8_lsN_4j__Sj -Bj1W=WB1j8_bbN_sl__j4 -_jS)q74qd=7d)4_bb8_lsN_4j__Sj -q47).7=q)_4.b_8bs_Nlj__4jq -S74)4=)q74b4_8sb_Njl__j4_ -7Sq)=4jq47)j8_bbN_sl__j4 -_jS)q7g7=q)bg_8sb_Njl__j4_ -7Sq)qU=7_)Ub_8bs_Nlj__4jq -S7=)(q(7)_bb8_lsN_4j__Sj -qn7)=)q7n8_bbN_sl__j4 -_jS)q767=q)b6_8sb_Njl__j4_ -7Sq)qc=7_)cb_8bs_Nlj__4jq -S7=)dqd7)_bb8_lsN_4j__Sj -q.7)=)q7.8_bbN_sl__j4 -_jS)q747=q)b4_8sb_Njl__j4_ -7Sq)qj=7_)jb_8bs_Nlj__4jB -S B)= b)_8sb_Njl__j4_ -BSm m)=B_ )b_8bs_Nlj__4jB -Sp=i)B)pi_bb8_lsN_4j__Sj -B.1)=)B1.8_bbN_sl__j4 -_jS)B141=B)b4_8sb_Njl__j4_ -1SB)Bj=1_)jb_8bs_Nlj__4j) -S1)a=1ba_8sb_Njl__j4_ -mS7d76=m_d6b_8bs_Nlj__4j7 -Sm=dc7cmd_bb8_lsN_4j__Sj -7dmd=d7md8_bbN_sl__j4 -_jSd7m.m=7db._8sb_Njl__j4_ -mS7d74=m_d4b_8bs_Nlj__4j7 -Sm=dj7jmd_bb8_lsN_4j__Sj -7gm.=.7mg8_bbN_sl__j4 -_jS.7mUm=7.bU_8sb_Njl__j4_ -mS7.7(=m_.(b_8bs_Nlj__4j7 -Sm=.n7nm._bb8_lsN_4j__Sj -76m.=.7m68_bbN_sl__j4 -_jS.7mcm=7.bc_8sb_Njl__j4_ -mS7.7d=m_.db_8bs_Nlj__4j7 -Sm=..7.m._bb8_lsN_4j__Sj -74m.=.7m48_bbN_sl__j4 -_jS.7mjm=7.bj_8sb_Njl__j4_ -mS747g=m_4gb_8bs_Nlj__4j7 -Sm=4U7Um4_bb8_lsN_4j__Sj -7(m4=47m(8_bbN_sl__j4 -_jS47mnm=74bn_8sb_Njl__j4_ -mS7476=m_46b_8bs_Nlj__4j7 -Sm=4c7cm4_bb8_lsN_4j__Sj -7dm4=47md8_bbN_sl__j4 -_jS47m.m=74b._8sb_Njl__j4_ -mS7474=m_44b_8bs_Nlj__4j7 -Sm=4j7jm4_bb8_lsN_4j__Sj -7=mg7_mgb_8bs_Nlj__4j7 -Sm7U=mbU_8sb_Njl__j4_ -mS7(m=7(8_bbN_sl__j4 -_jSn7m=n7m_bb8_lsN_4j__Sj -7=m67_m6b_8bs_Nlj__4j7 -Sm7c=mbc_8sb_Njl__j4_ -mS7dm=7d8_bbN_sl__j4 -_jS.7m=.7m_bb8_lsN_4j__Sj -7=m47_m4b_8bs_Nlj__4j7 -Sm7j=mbj_8sb_Njl__j4_;H -NRM#$_bMFsCkMR -4;NQHRh_Qa7qqaRa"1qBaQ"N; -H1RqY_hB) 1a _)p1 q 1R"Y"hB;H -NR7B1 7Bm R_)"jjLj;j" -RNHB 17B m7_"WRjjLj4 -";NtHR1")R Ahqp" 7;H -NR1) mav7" Rqh1YB -";N)HR mtv7" Rh m)t -";N7HRq_aqWaQ7]R_)d -n;N7HRq_aqWaQ7]R_Wd -n;N3HR#_$MNV00FNsl0x#HC7R"q_aqWaQ7]=_)d7.Rq_aqWaQ7]=_Wd;." -RNH3M#$_0N0VlFsN"0R7qqa_7WQa)]_=77Rq_aqWaQ7]=_W7 -";NvHR Qv_h_Qaw QpR;"" -RNHv_ vp_uBw QpRH"VVjFc_38OD"bO;R -s@6@4:jd(::4dd:(j.I6RFRs uW7u47niRsPCHoDFRbb8_lsN_jj__S4 -76Qd=d7Q68_bbN_sl__jj -_4Sd7QcQ=7dbc_8sb_Njl__4j_ -QS7d7d=Q_ddb_8bs_Nlj__j47 -SQ=d.7.Qd_bb8_lsN_jj__S4 -74Qd=d7Q48_bbN_sl__jj -_4Sd7QjQ=7dbj_8sb_Njl__4j_ -QS7.7g=Q_.gb_8bs_Nlj__j47 -SQ=.U7UQ._bb8_lsN_jj__S4 -7(Q.=.7Q(8_bbN_sl__jj -_4S.7QnQ=7.bn_8sb_Njl__4j_ -QS7.76=Q_.6b_8bs_Nlj__j47 -SQ=.c7cQ._bb8_lsN_jj__S4 -7dQ.=.7Qd8_bbN_sl__jj -_4S.7Q.Q=7.b._8sb_Njl__4j_ -QS7.74=Q_.4b_8bs_Nlj__j47 -SQ=.j7jQ._bb8_lsN_jj__S4 -7gQ4=47Qg8_bbN_sl__jj -_4S47QUQ=74bU_8sb_Njl__4j_ -QS747(=Q_4(b_8bs_Nlj__j47 -SQ=4n7nQ4_bb8_lsN_jj__S4 -76Q4=47Q68_bbN_sl__jj -_4S47QcQ=74bc_8sb_Njl__4j_ -QS747d=Q_4db_8bs_Nlj__j47 -SQ=4.7.Q4_bb8_lsN_jj__S4 -74Q4=47Q48_bbN_sl__jj -_4S47QjQ=74bj_8sb_Njl__4j_ -QS7gQ=7g8_bbN_sl__jj -_4SU7Q=U7Q_bb8_lsN_jj__S4 -7=Q(7_Q(b_8bs_Nlj__j47 -SQ7n=Qbn_8sb_Njl__4j_ -QS76Q=768_bbN_sl__jj -_4Sc7Q=c7Q_bb8_lsN_jj__S4 -7=Qd7_Qdb_8bs_Nlj__j47 -SQ7.=Qb._8sb_Njl__4j_ -QS74Q=748_bbN_sl__jj -_4Sj7Q=j7Q_bb8_lsN_jj__S4 -qU7W=Wq7U8_bbN_sl__jj -_4SWq7(7=qWb(_8sb_Njl__4j_ -7SqWqn=7_Wnb_8bs_Nlj__j4q -S7=W6q67W_bb8_lsN_jj__S4 -qc7W=Wq7c8_bbN_sl__jj -_4SWq7d7=qWbd_8sb_Njl__4j_ -7SqWq.=7_W.b_8bs_Nlj__j4q -S7=W4q47W_bb8_lsN_jj__S4 -qj7W=Wq7j8_bbN_sl__jj -_4SdA =dA _bb8_lsN_jj__S4 -A= .A_ .b_8bs_Nlj__j4A -S A4= b4_8sb_Njl__4j_ - SAj =Aj8_bbN_sl__jj -_4SWB =WB _bb8_lsN_jj__S4 -BWpi=iBpW8_bbN_sl__jj -_4SWB1.1=BWb._8sb_Njl__4j_ -1SBWB4=1_W4b_8bs_Nlj__j4B -S1=WjBj1W_bb8_lsN_jj__S4 -q47)d7=q)_4db_8bs_Nlj__j4q -S7.)4=)q74b._8sb_Njl__4j_ -7Sq)=44q47)48_bbN_sl__jj -_4S)q74qj=7j)4_bb8_lsN_jj__S4 -qg7)=)q7g8_bbN_sl__jj -_4S)q7U7=q)bU_8sb_Njl__4j_ -7Sq)q(=7_)(b_8bs_Nlj__j4q -S7=)nqn7)_bb8_lsN_jj__S4 -q67)=)q768_bbN_sl__jj -_4S)q7c7=q)bc_8sb_Njl__4j_ -7Sq)qd=7_)db_8bs_Nlj__j4q -S7=).q.7)_bb8_lsN_jj__S4 -q47)=)q748_bbN_sl__jj -_4S)q7j7=q)bj_8sb_Njl__4j_ - SB) =B)8_bbN_sl__jj -_4S mB)B=m b)_8sb_Njl__4j_ -pSBiB)=p_i)b_8bs_Nlj__j4B -S1=).B.1)_bb8_lsN_jj__S4 -B41)=)B148_bbN_sl__jj -_4S)B1j1=B)bj_8sb_Njl__4j_ -1S)a1=)a8_bbN_sl__jj -_4Sd7m6m=7db6_8sb_Njl__4j_ -mS7d7c=m_dcb_8bs_Nlj__j47 -Sm=dd7dmd_bb8_lsN_jj__S4 -7.md=d7m.8_bbN_sl__jj -_4Sd7m4m=7db4_8sb_Njl__4j_ -mS7d7j=m_djb_8bs_Nlj__j47 -Sm=.g7gm._bb8_lsN_jj__S4 -7Um.=.7mU8_bbN_sl__jj -_4S.7m(m=7.b(_8sb_Njl__4j_ -mS7.7n=m_.nb_8bs_Nlj__j47 -Sm=.676m._bb8_lsN_jj__S4 -7cm.=.7mc8_bbN_sl__jj -_4S.7mdm=7.bd_8sb_Njl__4j_ -mS7.7.=m_..b_8bs_Nlj__j47 -Sm=.474m._bb8_lsN_jj__S4 -7jm.=.7mj8_bbN_sl__jj -_4S47mgm=74bg_8sb_Njl__4j_ -mS747U=m_4Ub_8bs_Nlj__j47 -Sm=4(7(m4_bb8_lsN_jj__S4 -7nm4=47mn8_bbN_sl__jj -_4S47m6m=74b6_8sb_Njl__4j_ -mS747c=m_4cb_8bs_Nlj__j47 -Sm=4d7dm4_bb8_lsN_jj__S4 -7.m4=47m.8_bbN_sl__jj -_4S47m4m=74b4_8sb_Njl__4j_ -mS747j=m_4jb_8bs_Nlj__j47 -Sm7g=mbg_8sb_Njl__4j_ -mS7Um=7U8_bbN_sl__jj -_4S(7m=(7m_bb8_lsN_jj__S4 -7=mn7_mnb_8bs_Nlj__j47 -Sm76=mb6_8sb_Njl__4j_ -mS7cm=7c8_bbN_sl__jj -_4Sd7m=d7m_bb8_lsN_jj__S4 -7=m.7_m.b_8bs_Nlj__j47 -Sm74=mb4_8sb_Njl__4j_ -mS7jm=7j8_bbN_sl__jj;_4 -RNH#_$MMsFbkRMC4N; -HhRQQ7a_qRaq"q1aa"QB;H -NRYq1h)B_ a1 _p) q1RY"1h;B" -RNHB 17B m7_")RjjLjj -";NBHR1B7 m_7 WjR"L4jj"N; -H1Rt) R"hpqA ;7" -RNH) 1a7vm qR"1BYh"N; -H R)t7vm hR"mt) "N; -HqR7aWq_Q]7a_d)RnN; -HqR7aWq_Q]7a_dWRnN; -H#R3$NM_0F0Vs0lN#CHxRq"7aWq_Q]7a_d)=.qR7aWq_Q]7a_dW=. -";N3HR#_$MNV00FNsl07R"q_aqWaQ7]=_)7qR7aWq_Q]7a_7W="N; -H Rvvh_QQwa_QRp " -";NvHR pv_uwB_QRp "VVHF_cj8DO3b;O" -@sR@:46d:6U4dd:64U:UFRIs) Rmnv4XR4qPHCsDRFopcza_Sj -q=7dq_7dpcza_Sj -q=7.q_7.pcza_Sj -q=74q_74pcza_Sj -q=7jq_7jpcza_Sj -7=mj7_mjpcza_ -j;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Ljjjjjjjjjjjjjj;4" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4d6:64c:d6:dcU:4RsIF mR)vX4n4PqRCDsHFpoRz_ac4q -S7qd=7pd_z_ac4q -S7q.=7p._z_ac4q -S7q4=7p4_z_ac4q -S7qj=7pj_z_ac47 -Sm7j=mpj_z_ac4N; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nLjjjjjjj4jj4jjjjj -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@66:djd:4:jd6:R4UI FsRv)m44nXqCRPsFHDozRpa.c_ -7Sqd7=qdz_pa.c_ -7Sq.7=q.z_pa.c_ -7Sq47=q4z_pa.c_ -7Sqj7=qjz_pa.c_ -mS7jm=7jz_pa.c_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'j4jjjjjjjjjjjj4j"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@6@4:ndc::4dd:cn4IURFRs )4mvnqX4RsPCHoDFRapzc -_dSdq7=dq7_apzc -_dS.q7=.q7_apzc -_dS4q7=4q7_apzc -_dSjq7=jq7_apzc -_dSj7m=j7m_apzc;_d -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'Ljjjj4jjjjjj4j"jj;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46d:c.4dd:c4.:UFRIs) Rmnv4XR4qPHCsDRFopcza_Sc -q=7dq_7dpcza_Sc -q=7.q_7.pcza_Sc -q=74q_74pcza_Sc -q=7jq_7jpcza_Sc -7=mj7_mjpcza_ -c;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4d6:d4U:dd:dUU:4RsIF mR)vX4n4PqRCDsHFpoRz_ac6q -S7qd=7pd_z_ac6q -S7q.=7p._z_ac6q -S7q4=7p4_z_ac6q -S7qj=7pj_z_ac67 -Sm7j=mpj_z_ac6N; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@6d:dcd:4:cdd:R4UI FsRv)m44nXqCRPsFHDozRpanc_ -7Sqd7=qdz_panc_ -7Sq.7=q.z_panc_ -7Sq47=q4z_panc_ -7Sqj7=qjz_panc_ -mS7jm=7jz_panc_;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@6@4:jdd::4dd:dj4IURFRs )4mvnqX4RsPCHoDFRapzc -_(Sdq7=dq7_apzc -_(S.q7=.q7_apzc -_(S4q7=4q7_apzc -_(Sjq7=jq7_apzc -_(Sj7m=j7m_apzc;_( -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46d:.n4dd:.4n:UFRIs) Rmnv4XR4qPHCsDRFopcza_SU -q=7dq_7dpcza_SU -q=7.q_7.pcza_SU -q=74q_74pcza_SU -q=7jq_7jpcza_SU -7=mj7_mjpcza_ -U;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4d6:.4.:d.:d.U:4RsIF mR)vX4n4PqRCDsHFpoRz_acgq -S7qd=7pd_z_acgq -S7q.=7p._z_acgq -S7q4=7p4_z_acgq -S7qj=7pj_z_acg7 -Sm7j=mpj_z_acgN; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@64:dUd:4:Ud4:R4gI FsRv)m44nXqCRPsFHDozRpa4c_jq -S7qd=7pd_z_ac4Sj -q=7.q_7.pcza_ -4jS4q7=4q7_apzcj_4 -7Sqj7=qjz_pa4c_j7 -Sm7j=mpj_z_ac4 -j;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4d6:44c:d4:dcg:4RsIF mR)vX4n4PqRCDsHFpoRz_ac4S4 -q=7dq_7dpcza_ -44S.q7=.q7_apzc4_4 -7Sq47=q4z_pa4c_4q -S7qj=7pj_z_ac4S4 -7=mj7_mjpcza_;44 -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46d:4j4dd:44j:gFRIs) Rmnv4XR4qPHCsDRFopcza_ -4.Sdq7=dq7_apzc._4 -7Sq.7=q.z_pa4c_.q -S7q4=7p4_z_ac4S. -q=7jq_7jpcza_ -4.Sj7m=j7m_apzc._4;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@6@4:ndj::4dd:jn4IgRFRs )4mvnqX4RsPCHoDFRapzcd_4 -7Sqd7=qdz_pa4c_dq -S7q.=7p._z_ac4Sd -q=74q_74pcza_ -4dSjq7=jq7_apzcd_4 -mS7jm=7jz_pa4c_dN; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@6j:d.d:4:.dj:R4gI FsRv)m44nXqCRPsFHDozRpa4c_cq -S7qd=7pd_z_ac4Sc -q=7.q_7.pcza_ -4cS4q7=4q7_apzcc_4 -7Sqj7=qjz_pa4c_c7 -Sm7j=mpj_z_ac4 -c;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4.6:g4U:dg:.Ug:4RsIF mR)vX4n4PqRCDsHFpoRz_ac4S6 -q=7dq_7dpcza_ -46S.q7=.q7_apzc6_4 -7Sq47=q4z_pa4c_6q -S7qj=7pj_z_ac4S6 -7=mj7_mjpcza_;46 -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46.:gc4.d:g4c:gFRIs) Rmnv4XR4qPHCsDRFopcza_ -4nSdq7=dq7_apzcn_4 -7Sq.7=q.z_pa4c_nq -S7q4=7p4_z_ac4Sn -q=7jq_7jpcza_ -4nSj7m=j7m_apzcn_4;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@6@4:j.g::4d.:gj4IgRFRs )4mvnqX4RsPCHoDFRapzc(_4 -7Sqd7=qdz_pa4c_(q -S7q.=7p._z_ac4S( -q=74q_74pcza_ -4(Sjq7=jq7_apzc(_4 -mS7jm=7jz_pa4c_(N; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@6U:.nd:4:n.U:R4gI FsRv)m44nXqCRPsFHDozRpa4c_Uq -S7qd=7pd_z_ac4SU -q=7.q_7.pcza_ -4US4q7=4q7_apzcU_4 -7Sqj7=qjz_pa4c_U7 -Sm7j=mpj_z_ac4 -U;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4.6:U4.:dU:..g:4RsIF mR)vX4n4PqRCDsHFpoRz_ac4Sg -q=7dq_7dpcza_ -4gS.q7=.q7_apzcg_4 -7Sq47=q4z_pa4c_gq -S7qj=7pj_z_ac4Sg -7=mj7_mjpcza_;4g -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46.:(U4.d:(4U:gFRIs) Rmnv4XR4qPHCsDRFopcza_ -.jSdq7=dq7_apzcj_. -7Sq.7=q.z_pa.c_jq -S7q4=7p4_z_ac.Sj -q=7jq_7jpcza_ -.jSj7m=j7m_apzcj_.;H -NRM#$_bMFsCkMR -4;NHHRMPH0N"DR4Ln'jj4444jj44jjjj44"N; -H#R3$NM_0F0Vs0lN#CHxRM"HHN0PDn=4"N; -H#R3$NM_0F0Vs0lNRM"HHN0PD"=X;R -s@6@4:c.(::4d.:(c4IgRFRs )4mvnqX4RsPCHoDFRapzc4_. -7Sqd7=qdz_pa.c_4q -S7q.=7p._z_ac.S4 -q=74q_74pcza_ -.4Sjq7=jq7_apzc4_. -mS7jm=7jz_pa.c_4N; -H$R#MF_MbMskC;R4 -RNHH0MHPRND"'4nL4j4jj4j4j4j44j4j -";N3HR#_$MNV00FNsl0x#HCHR"MPH0N4D=n -";N3HR#_$MNV00FNsl0HR"MPH0NXD="s; -R4@@6(:.jd:4:j.(:R4gI FsRv)m44nXqCRPsFHDozRpa.c_.q -S7qd=7pd_z_ac.S. -q=7.q_7.pcza_ -..S4q7=4q7_apzc._. -7Sqj7=qjz_pa.c_.7 -Sm7j=mpj_z_ac. -.;N#HR$MM_FkbsM4CR;H -NRHHM0DPNRn"4'4Lj4jj4jj44j44j4;j" -RNH3M#$_0N0VlFsNH0#x"CRH0MHP=ND4;n" -RNH3M#$_0N0VlFsN"0RH0MHP=NDX -";s@R@4.6:n4n:dn:.ng:4RsIF mR)vX4n4PqRCDsHFpoRz_ac.Sd -q=7dq_7dpcza_ -.dS.q7=.q7_apzcd_. -7Sq47=q4z_pa.c_dq -S7qj=7pj_z_ac.Sd -7=mj7_mjpcza_;.d -RNH#_$MMsFbkRMC4N; -HMRHHN0PD4R"nj'L444jj4j4jjj44"4j;H -NR$3#M0_N0sVFl#N0HRxC"HHM0DPN="4n;H -NR$3#M0_N0sVFlRN0"HHM0DPN=;X" -@sR@:46.:ndgn:.d6:4RsIF mRX)P.RCDsHFXoRm_).0Sj -q_=qX.m)_ -0jSAA=_)Xm.j_0 -=SZZm_X)0._jN; -H$R#MF_MbMskC;R4 -@sR@:46.:n4gn:.46:4RsIF mRX)P.RCDsHFXoRm_).0S4 -q_=qX.m)_ -04SAA=_)Xm.4_0 -=SZZm_X)0._4N; -H$R#MF_MbMskC;R4 -@sR@:46.:6gg6:.g6:4RsIF mRX)P.RCDsHFXoRm_).0S. -q_=qX.m)_ -0.SAA=_)Xm.._0 -=SZZm_X)0._.N; -H$R#MF_MbMskC;R4 -@sR@:46.:6(g6:.(6:4RsIF mRX)P.RCDsHFXoRm_).0Sd -q_=qX.m)_ -0dSAA=_)Xm.d_0 -=SZZm_X)0._dN; -H$R#MF_MbMskC;R4 -@sR@:46.:66g6:.66:4RsIF mRX)P.RCDsHFXoRm_).0Sc -q_=qX.m)_ -0cSAA=_)Xm.c_0 -=SZZm_X)0._cN; -H$R#MF_MbMskC;R4 -@sR@:46.:6dg6:.d6:4RsIF mRX)P.RCDsHFXoRm_).0S6 -q_=qX.m)_ -06SAA=_)Xm.6_0 -=SZZm_X)0._6N; -H$R#MF_MbMskC;R4 -@sR@:46.:64g6:.46:4RsIF mRX)P.RCDsHFXoRm_).0Sn -q_=qX.m)_ -0nSAA=_)Xm.n_0 -=SZZm_X)0._nN; -H$R#MF_MbMskC;R4 -@sR@:46.:cggc:.g6:4RsIF mRX)P.RCDsHFXoRm_).0S( -q_=qX.m)_ -0(SAA=_)Xm.(_0 -=SZZm_X)0._(N; -H$R#MF_MbMskC;R4 -@sR@:46.:c(gc:.(6:4RsIF mRX)P.RCDsHFXoRm_).0SU -q_=qX.m)_ -0USAA=_)Xm.U_0 -=SZZm_X)0._UN; -H$R#MF_MbMskC;R4 -@sR@:46.:c6gc:.66:4RsIF mRX)P.RCDsHFXoRm_).0Sg -q_=qX.m)_ -0gSAA=_)Xm.g_0 -=SZZm_X)0._gN; -H$R#MF_MbMskC;R4 -@sR@:46.:cdgc:.dn:4RsIF mRX)P.RCDsHFXoRm_).0 -4jSqq=_)Xm.4_0jA -S=XA_m_).0 -4jSZZ=_)Xm.4_0jN; -H$R#MF_MbMskC;R4 -@sR@:46.:c4gc:.4n:4RsIF mRX)P.RCDsHFXoRm_).0 -44Sqq=_)Xm.4_04A -S=XA_m_).0 -44SZZ=_)Xm.4_04N; -H$R#MF_MbMskC;R4 -@sR@:46.:dggd:.gn:4RsIF mRX)P.RCDsHFXoRm_).0 -4.Sqq=_)Xm.4_0.A -S=XA_m_).0 -4.SZZ=_)Xm.4_0.N; -H$R#MF_MbMskC;R4 -@sR@:46.:d(gd:.(n:4RsIF mRX)P.RCDsHFXoRm_).0 -4dSqq=_)Xm.4_0dA -S=XA_m_).0 -4dSZZ=_)Xm.4_0dN; -H$R#MF_MbMskC;R4 -@sR@:46.:d6gd:.6n:4RsIF mRX)P.RCDsHFXoRm_).0 -4cSqq=_)Xm.4_0cA -S=XA_m_).0 -4cSZZ=_)Xm.4_0cN; -H$R#MF_MbMskC;R4 -@sR@:46.:ddgd:.dn:4RsIF mRX)P.RCDsHFXoRm_).0 -46Sqq=_)Xm.4_06A -S=XA_m_).0 -46SZZ=_)Xm.4_06N; -H$R#MF_MbMskC;R4 -@sR@:46.:d4gd:.4n:4RsIF mRX)P.RCDsHFXoRm_).0 -4nSqq=_)Xm.4_0nA -S=XA_m_).0 -4nSZZ=_)Xm.4_0nN; -H$R#MF_MbMskC;R4 -@sR@:46.:.gg.:.gn:4RsIF mRX)P.RCDsHFXoRm_).0 -4(Sqq=_)Xm.4_0(A -S=XA_m_).0 -4(SZZ=_)Xm.4_0(N; -H$R#MF_MbMskC;R4 -@sR@:46.:.(U.:.(c:4RsIF )Rm.CRPsFHDo)Rm.4_0Uq -S=mq_)0._4SU -A_=Am_).0 -4USZZ=_.m)_U04;H -NRM#$_bMFsCkMR -4;s@R@4.6:.U6::6..:R4.I FsReQhRsPCHoDFReQh_Sj -q_=qQ_hejZ -S=QZ_hje_;H -NRM#$_bMFsCkMR -4;s@R@4.6:.gd::d..:R4nI FsR7qh.CRPsFHDohRq70._4Sg -q_=qq.h7_g04 -=SAAh_q70._4Sg -Z_=Zq.h7_g04;H -NRM#$_bMFsCkMR -4;s@R@4.6:.U4::4..:R4.I FsReQhRsPCHoDFReQh_S4 -q_=qQ_he4Z -S=QZ_h4e_;H -NRM#$_bMFsCkMR -4;s@R@4.6:4gg::g.4:R4nI FsR7qh.CRPsFHDohRq70._.Sj -q_=qq.h7_j0. -=SAAh_q70._.Sj -Z_=Zq.h7_j0.;H -NRM#$_bMFsCkMR -4;y-------------------------------- ---@ - - -ftell; -@E@MR@:4cd::(dg:4RsIF HRVVOF_FODC0RFsPHCsD;Fo -RNP3sVFl_NDODCDMCNlRH"VVOF_FODC0"Fs;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNCVR"H_VFOCFDOs0F"N; -PsRFHHo_M_#0F"VRVFHV_DOFCFO0s -";N3PRDoNMuNNsl"#RBh]qh1 pRa7qqQ_W7Ra]q)77 _11WaQ7] -";NBPR]hqh Rp1dN; -PqR7aWq_Q]7aR;d. -RNPq)77 _11WaQ7];RU -RNP3M#$_0N0VlFsNH0#x"CRBh]qh1 p=Rd.7qqa_7WQad]=.7Rq71) 1Q_W7=a]d".R;P -NR$3#M0_N0sVFlRN0"qB]hph 1R=77qqa_7WQa7]=R7q7)1 1_7WQa7]=R -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03VVHFF_OD0COFHs_M"#0;P -NR03#lH0D#C0llNk#ojCR3jjjj;jj -RNP3l#00#DH0l0HC3Rjjjjjj -j; -@HR@:4cd.:.:.d:(sRI_ ODR_IsO;D -@HR@:4cc::Ucd:4R_s8ORD sO8_D - ; -@HR@:4c6::U6.:4R#sCCs0RC0#C; - - - -@HR@:4cn::Unc:4R_HM8NN0r:g6jH9RMN_80gNr69:j; - - - -@HR@:4c(::U(6:4R_HMC0lb$:r.jH9RMl_Cbr0$.9:j; - - - -@FR@:4c..n:nn:.:RdgHsM_C_N8CLMND.Cr:Rj9; - - - -@FR@:4cg::Ug6:4R0Fk_08NNgrd:Rj9; - - - -@FR@:4c4Uj:::4j4FnRkC0_l$b0R -; - -@HR@:4c4U4:::44.F.Rks0_C_N8CLMNDFCRks0_C_N8CLMND -C; -@HR@:4c4U.:::4.48cRHN#Os88RHN#Os -8; -@HR@:4c4Uc:::4c4s(RNCI_MDNLCNRsIM_CNCLD;R -s@c@4::cj4cj:jj:.RsIF HRVVjFc_R8OPHCsDRFoVFHVcHj_M -#0S07NNgrd:=j97NN0_VVHF_cjH0M#r:dgjS9 -WDsBF=O WDsBF_O VFHVcHj_M -#0SB)8D FO=B)8D FO_VVHF_cjH0M# -sSW WM=s_ MVFHVcHj_M -#0S )8M8=) VM_HcVFjM_H#S0 -)CC#0C=)#_C0VFHVcHj_M -#0S))uC0#C=))uC0#C_VVHF_cjH0M# -rSTdjg:9_=TVFHVcHj_Mr#0djg:9 -Sl$b0=b l0V$_HcVFjM_H#S0 -wDkD=DwkDH_VVjFc_#HM0N; -H$R#MF_MbMskC;R4 --y--------------------------------- - -@ -ftell; -@E@MR@:4n.:dj(d:.j(:4RsIF sR0L8_NNCb0sCRPsFHDoN; -PVR3FNslDC_ODNDMl"CR0_sLNb8N0"Cs;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNC0R"sNL_80NbC;s" -RNPFosH_#HM0V_FRs"0L8_NNCb0s -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_03L0s_NN8bs0C_#HM0 -";N3PR#00lD0H#lkCl#CNoRjj3jjjjjN; -P#R30Dl0H0#0HRlCjj3jjjjj; - - - -@HR@:4n.:d4gd:.44:4R ODR OD; - - - -@HR@:4n.:d.gd:..d:4R#sCCs0RC0#C; - - - -@HR@:4n.:ddgd:.dj:dRppe4)_atq_7aeq_q7pQ_RQhp4ep_ta)_a7qqq_ep_Q7Q -h; -@HR@:4n.:dcgd:.c(:.Rppe4h_QeQqp7)_ath_QRppe4h_QeQqp7)_ath_Q; - - - -@FR@:4n.:644.d:6.4:c Rw q_7amq_z;aR -@FR@:4n.:6.4.d:6d.:j Rw q_7aWq_) Qa_amzR -; - -@FR@:4n.:6d4.d:6dd:. Rw q_7aQqwh]Q1 m7_z;aR -@FR@:4n.:6c4.d:6dc:4 Rw )_at _)p1 q z_ma -R; -@FR@:4n.:dggd:.gn:dRppe4)_atq_7aeq_q_pQQsh_HM#Ho -R; -@FR@:4n.:cjgc:.jd:4RsLk#;0R -@FR@:4n.:c4gc:.46:4R#8HO8NsR -; - -@HR@:4n.:c.gc:..(:4RVLk_bCl0L$RkCV_l$b0; - - - -@FR@:4n.:6g4.d:6.g:jkRLV8_sC;MR -@FR@:4n.:nj4.d:n.j:jHRVMEH#C;8R -@FR@:4n.:c6gc:.6g:4RDsCCCN#_0FkRy; ----------------------------------@- - - - - -ftell; -@E@MR@:4U4:4j(4:4j4:dRsIF NRE8_C#0_8OOMENM_CDs_NIFRk0PHCsD;Fo -RNP3sVFl_NDODCDMCNlRN"E8_C#0_8OOMENM_CDs_NIF"k0;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNCER"N#8C_O08_NOEMDMC_IsN_0Fk"N; -PsRFHHo_M_#0F"VRECN8#8_0OE_ONCMMDN_sIk_F0 -";N3PRDoNMuNNsl"#RB)mq1W _Q]7aRBa7_7WQa;]" -RNPB)mq1W _Q]7aR -g;NaPR7WB_Q]7aR -d;N3PR#_$MNV00FNsl0x#HCBR"m1q) Q_W7=a]da.R7WB_Q]7a=Rd."N; -P#R3$NM_0F0Vs0lNRm"Bq )1_7WQa7]=RBa7_7WQa7]=R -";N3PRFosHDMHLNRlC"sIF -";N3PRDCN$sRH8jN; -PER3$sbCQ0M#uEN0v1F8OCFbRF"0bV_038ENC0#_8LO_kDM8CM_H#E03N#8C_O08_NOEMDMC_IsN_0Fk_#HM0 -";N3PR#00lD0H#lkCl#CNoRjj3jjjjjN; -P#R30Dl0H0#0HRlCjj3jjjjj; - - - -@HR@:4U4:4444j:444:cCRs#RC0sCC#0 -; - -@HR@:4U4:4.44j:44.:(DRbDD_O d#r:Rj9b_DDO#D rjd:9 -; - -@HR@:4U4:4d44j:44d:6FRONCs#rjU:9FRONCs#rjU:9 -; - -@HR@:4U4:4c44j:44c:dsR0H0oRs;Ho -@FR@:4U4:4644j:446:n8R0Ok_F0:r(j;9R -@FR@:4U4:d4c4n:d64:.NRsIk_F0dr.:Rj9; - - - -@FR@:4U4:d.44.:d..:cNRsIk_F0N_PDRH8; - - - -@FR@:4U4:4U44j:4.U:dNRsIN_PD_H8P0COrj4:9 -R;s@R@44U:n4j:(n:4jU:.RsIF kRF00bk_O8CFs8CUCRPsFHDoCR8OC_MoM_H#S0 -O=D O_D 8_COM_CoH0M# -MSHrj(:9M=H_O8C_oMC_#HM0:r(jS9 -Frk0.9:j=0Fk_O8C_oMC_#HM0:r.jS9 -PHND8N=PD_H88_COM_CoH0M# -MSH_M#$O_C8D(Lr:=j9H#M_$CMO8L_D_O8C_oMC_#HM0:r(jS9 -s_NIDON0ErC8(9:j=IsN_0DNO8EC_O8C_oMC_#HM0:r(j -9;N#HR$MM_FkbsM4CR;H -NRM#$_Cbs#PCsC;R4 -@sR@:4U4:6d44(:6.d:cFRIsF Rkk0b0C_8OCF8sPURCDsHF8oRCHO_M -#0S OD= OD_O8C_#HM0H -SM:r(jH9=MC_8OM_H#(0r: -j9S0Fkrj.:9k=F0C_8OM_H#.0r: -j9SDPNHP8=N8DH_O8C_#HM0H -SM$_#M8OC_rDL(9:j=_HM#O$MCD8_LC_8OM_H#(0r: -j9SIsN_0DNO8ECrj(:9N=sIN_D0COE8C_8OM_H#(0r:;j9 -RNH#_$MMsFbkRMC4s; -R4@@Uc:4U6:4:U4c:R.nI FsRO08cs88_F#EsP0RCDsHF0oR8MO_CHo_M -#0SH0sosoC=H0sosoC_O08_oMC_#HM0O -SDr #d9:j= OD#8_0OC_MoM_H#d0r: -j9S0Fkrj(:9k=F08_0OC_MoM_H#(0r:;j9 -RNH#_$MMsFbkRMC4N; -H$R#Ms_bCs#CP4CR;R -s@U@4:d4c::464:cd.I.RFRs 0c8O8_8s#sEF0CRPsFHDo8R0OM_H#S0 -0osHo=Cs0osHo_Cs0_8OH0M# -DSO d#r:=j9O#D _O08_#HM0:rdjS9 -Frk0(9:j=0Fk_O08_#HM0:r(j -9;N#HR$MM_FkbsM4CR;R -s@U@4:U4d::4j4:dU.IdRFRs 0osH_PHMRsPCHoDFRH0soM_HPM_H# -04S=HMH0M_s_HoH_MPH0M#4F -SkF0=k00_s_HoH_MPH0M#4N; -H$R#MF_MbMskC;R4 --y--------------------------------- - -@ -ftell; -@E@MR@:4U.::(.c:.RsIF NRE8_C#p4ep_IsN_0FkRsPCHoDF;P -NRF3VsDlN_DOCDlMNCER"N#8C_ppe4N_sIk_F0 -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"8ENCp#_e_p4s_NIF"k0;P -NRHFsoM_H#F0_VER"N#8C_ppe4N_sIk_F0 -";N3PRDoNMuNNsl"#RB)mq1W _Q]7aRBa7_7WQaW]RQmh7W _ph]ta"N; -PmRBq )1_7WQag]R;P -NRBa7_7WQad]R;P -NRhWQ7_mWpt ha.]R6 -6;N3PR#_$MNV00FNsl0x#HCBR"m1q) Q_W7=a]da.R7WB_Q]7a=Rd.W7QhmpW_ aht].=dR -";N3PR#_$MNV00FNsl0BR"m1q) Q_W7=a]77RaBQ_W7=a]7QRWhW7m_hp t=a]X;R" -RNP3HFsoLDHMCNlRF"Is; " -RNP3$DNC8sHR -j;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VN3E8_C#0_8OL8kMDHC_M3#0ECN8#e_pps4_NFI_kH0_M"#0;P -NR03#lH0D#C0llNk#ojCR3jjjj;jj -RNP3l#00#DH0l0HC3Rjjjjjj -j; -@HR@:4Udj:4:4d:cCRs#RC0sCC#0 -; - -@HR@:4Ucj:4:4c:(DRbDD_O d#r:Rj9b_DDO#D rjd:9 -; - -@HR@:4U6j:4:46:6FRONCs#rjU:9FRONCs#rjU:9 -; - -@HR@:4Unj:4:4n:dsR0H0oRs;Ho -@HR@:4U(j:4:4(:nMRHPHND8MRHPHND8 -; - -@FR@:4Udc4:c4:d:RcgF#VVC40r49:jR -; - -@FR@:4Ud4.:..:d:R.dF#VVCP0_N8DHR -; - -@FR@:4Ud4d:.d:d:R.4I8HMFCI_M;8R -@FR@:4Ud4c:.c:d:R4U8OH#NRs8; - - - -@FR@:4Ud4g:(g:d:R.nHNMPD_H88dDr:Rj9;R -s@U@4::6446(:4c:.RsIF kRF00bk_O8CFs8CUCRPsFHDoCR8OM_H#S0 -O=D O_D 8_COH0M# -MSHrj(:9M=H_O8C_#HM0:r(jS9 -Frk0.9:j=0Fk_O8C_#HM0:r.jS9 -PHND8N=PD_H88_COH0M# -MSH_M#$O_C8D(Lr:=j9H#M_$CMO8L_D_O8C_#HM0:r(jS9 -s_NIDON0ErC8(9:j=IsN_0DNO8EC_O8C_#HM0:r(j -9;N#HR$MM_FkbsM4CR;R -s@U@4::cn4c6:n.:.RsIF 8R0O8c8sE_#FRs0PHCsDRFo0_8OH0M# -sS0HCooss=0HCoos8_0OM_H#S0 -O#D rjd:9D=O 0#_8HO_Mr#0d9:j -kSF0:r(jF9=k00_8HO_Mr#0(9:j;H -NRM#$_bMFsCkMR -4;y-------------------------------- ---@ - - -ftell; -@E@MR@:4(.::(..:.RsIF NRE8_C#0_8OL8kMDPCRCDsHF -o;N3PRVlFsNOD_CMDDNRlC"8ENC0#_8LO_kDM8C -";N3PRHC#PsFHDo;R4 -RNP3_H#PHCsDRFo4N; -PFR3shHoNRlC"8ENC0#_8LO_kDM8C -";NFPRs_HoH0M#_RFV"8ENC0#_8LO_kDM8C -";N3PRDoNMuNNsl"#Rat)Q_7WQaB]Rm1q) Q_W7Ra]a_7BWaQ7]QR]awAzw_ )7a u]mRBq )1_7WQaQ]_h)a h"qp;P -NRQa)tQ_W7Ra]4N; -PmRBq )1_7WQag]R;P -NRBa7_7WQad]R;P -NRa]QAwzw 7)_ ]uaR -c;NBPRm1q) Q_W7_a]Q ha)phqR -g;N3PR#_$MNV00FNsl0x#HCaR")_QtWaQ7].=dRqBm)_1 WaQ7].=dRBa7_7WQad]=.QR]awAzw_ )7a u].=dRqBm)_1 WaQ7]h_Qah )qdp=.;R" -RNP3M#$_0N0VlFsN"0Rat)Q_7WQa7]=RqBm)_1 WaQ7]R=7a_7BWaQ7]R=7]AQaz ww) _7u=a]7mRBq )1_7WQaQ]_h)a h=qp7;R" -RNP3HFsoLDHMCNlRF"Is; " -RNP3$DNC8sHR -j;N3PREC$bs#QM00uNE8vF1bOFC0R"F0b_VN3E8_C#0_8OL8kMDHC_M"#0;P -NR03#lH0D#C0llNk#ojCR3jjjj;jj -RNP3l#00#DH0l0HC3Rjjjjjj -j; -@HR@:4(dj:4:4d:cCRs#RC0sCC#0 -; - -@HR@:4(cj:4:4c:(DRbDD_O d#r:Rj9b_DDO#D rjd:9 -; - -@HR@:4(6j:4:46:dsR0Hjor9sR0Hjor9N; -H#R3$NM_s$sNb0FsR -4; -@HR@:4(nj:4:4n:UeRpp04_sRHop4ep_H0so -; - -@HR@:4((j:4:.(:4eRppH4_MDPNHp8Re_p4HNMPD;H8 -@FR@:4(ccj:nj:c:R6gsCCVsOCMCF8_k.0rd9:jR -; - -@FR@:4(c44:.4:c:Rd4sCCVsOCMCF8_kP0_N8DHR -; - -@FR@:4(44j:jj:4:R4gI8HMFCI_M;8R -@FR@:4(444:j4:4:R.jp4ep_VFV#rC04j4:9 -R; -@FR@:4(44.:j.:4:R.np4ep_VFV#_C0PHND8 -R; -@FR@:4(cc6:n6:c:R6.L_kVFrk0.jd:9 -R; -@FR@:4(c4n:.n:c:R.cL_kVF_k0PHND8 -R; -@FR@:4(c4(:.(:c:R..L_kVsCCDNR#C; - - - -@FR@:4(c4U:.U:c:R.dL_kVVHHM#8ECR -; - -@FR@:4(64c:(c:6:R.6E_H0F_k0H:rdj;9R -@FR@:4(6dn:dn:6:Rc4E_H0PHND8:rdj;9R -@FR@:4(44g:jg:4:R4n8OH#NRs8; - - - -@FR@:4(.4j:jj:.:R4gHNMPD_H88dDr:Rj9; - - - -@FR@:4(644:(4:6:R.cL_kV8bsFrjd:9 -R; -@FR@:4(.4.:j.:.:R4(8.Lo_0Fkr:d4j;9R -@FR@:4(.4d:jd:.:R.j8.Lo_NOFsr#CU9:jR -; - -@FR@:4(4:4U44U:4.U:gsR8FOb_lLb_k4Vr49:jR -; - -@FR@:4(4:4g44U:4dg:nsR8FOb_lLb_kOV_F#NsC4r4:Rj9; - - - -@FR@:4(4:.j44.:..j:gsR8FOb_lLb_kPV_N8DHRs; -R4@@((:4gU:.:g4(:R6(I FsR8ENC0#_8OO_EMNMCsD_NFI_kP0RCDsHFEoRN#8C_O08_NOEMDMC_IsN_0Fk_#HM0s -SC0#C=#sCCE0_N#8C_O08_NOEMDMC_IsN_0Fk_#HM0b -SDOD_Dr #d9:j=DbD_ OD#N_E8_C#0_8OOMENM_CDs_NIF_k0H0M#rjd:9O -SF#NsC:rUjO9=F#NsCN_E8_C#0_8OOMENM_CDs_NIF_k0H0M#rjU:90 -Ss=Ho0osH_8ENC0#_8OO_EMNMCsD_NFI_kH0_M -#0SO08_0Fkrj(:98=0Ok_F0N_E8_C#0_8OOMENM_CDs_NIF_k0H0M#rj(:9s -SNFI_k.0rd9:j=IsN_0Fk_8ENC0#_8OO_EMNMCsD_NFI_kH0_Mr#0.jd:9s -SNFI_kP0_N8DH=IsN_0Fk_DPNHE8_N#8C_O08_NOEMDMC_IsN_0Fk_#HM0s -SNPI_N8DH_OPC0:r4js9=NPI_N8DH_OPC0N_E8_C#0_8OOMENM_CDs_NIF_k0H0M#rj4:9N; -H$R#MF_MbMskC;R4 -@sR@:4(4:nc.44:ncc:dFRIsE RN#8C_ppe4N_sIk_F0CRPsFHDoNRE8_C#p4ep_IsN_0Fk_#HM0s -SC0#C=#sCCE0_N#8C_ppe4N_sIk_F0M_H#S0 -b_DDO#D rjd:9D=bDD_O E#_N#8C_ppe4N_sIk_F0M_H#d0r: -j9SNOFsr#CU9:j=NOFs_#CECN8#e_pps4_NFI_kH0_Mr#0U9:j -sS0H0o=s_HoECN8#e_pps4_NFI_kH0_M -#0SPHMN8DH=PHMN8DH_8ENCp#_e_p4s_NIF_k0H0M# -VSFV0#Cr:44jF9=VCV#0N_E8_C#p4ep_IsN_0Fk_#HM04r4: -j9SVFV#_C0PHND8V=FV0#C_DPNHE8_N#8C_ppe4N_sIk_F0M_H#S0 -I8HMFCI_MI8=HFM8IM_C8N_E8_C#p4ep_IsN_0Fk_#HM08 -SHN#Os88=HN#OsE8_N#8C_ppe4N_sIk_F0M_H#S0 -HNMPD_H88dDr:=j9HNMPD_H88ED_N#8C_ppe4N_sIk_F0M_H#d0r:;j9 -RNH#_$MMsFbkRMC4y; ----------------------------------@- - - - - -ftell; -@E@MR@4j:n:gn(n:4g4n:dFRIs R]pXupPpRCDsHF -o;N3PRCCG0sDMNR -4;N3PRVlFsNOD_CMDDNRlC"X ]uppp"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CR u]Xp"pp;P -NRHFsoM_H#F0_V R"]pXup;p" -RNP3MDNosuNNRl#"iBpQQ_7epRBi_wA7RQeBmpiuQ_7epRBi_m17RQeBmpi17._QBeRp1imdQ_7epRBi_mu AhqpB Rp1im_q hARp Bmpi1 ._hpqA pRBidm1_q hARp Bmpiuu_B] q1RiBpmB1_u1]q pRBi.m1_]BuqR1 Bmpi1Bd_u1]q pRBi_muwqu]1B Rp1im_]wuqR1 Bmpi1w._u1]q pRBidm1_]wuqR1 w7 Aui_qRa]Bmpiu)_aQuv_mBpRpuim_Qa)v _7pRqYBmpi1)_aQuv_mBpRp1im_Qa)v _7pRqYm7zaQ7eQ v)_zRXqm7zaQ7eQ v)_zRXAm7zaQ7eQ v)_zRXBm7zaQ7eQ v)_zRX7u_pppimB_7vm pRupm_pB7i_ YpqR71aA Y_hpqA R)w_Qh) 1aYR1h B_hpqA hRQam_pB1i_aiQBYuR7] q1_z1m)RB u)pp1 a_hQqRhAaw_iWq -";NBPRp_iQ7RQe4N; -PpRBi_wA7RQedN; -PpRBi_mu7RQe.N; -PpRBi_m17RQe.N; -PpRBi.m1_e7QR -.;NBPRp1imdQ_7e;R. -RNPBmpiuh_ q ApRh" q Ap7 -";NBPRp1im_q hARp "q hA7p "N; -PpRBi.m1_q hARp "q hA7p "N; -PpRBidm1_q hARp "q hA7p "N; -PpRBi_muBqu]14 R;P -NRiBpmB1_u1]q ;R4 -RNPBmpi1B._u1]q ;R4 -RNPBmpi1Bd_u1]q ;R4 -RNPBmpiuu_w] q1R -j;NBPRp1im_]wuqR1 .N; -PpRBi.m1_]wuqR1 cN; -PpRBidm1_]wuqR1 nN; -P Rw i7A_auq]BR"puim"N; -PpRBi_muav)Q_pumRq"wphpQt -";NBPRpuim_Qa)v _7pRqYjN; -PpRBi_m1av)Q_pumRq"wphpQt -";NBPRp1im_Qa)v _7pRqYjN; -PzRmae7QQ)7 _Xvzq7R"Q"eq;P -NRamz7QQe7_ )vAzXRQ"7e;A" -RNPm7zaQ7eQ v)_zRXB"e7QB -";NmPRzQa7e Q7)z_vX"7R77Qe"N; -PpRupm_pBvi_mR7 jN; -PpRupm_pB7i_ YpqRj.j;P -NR71aA Y_hpqA 7R"QA1qp" 7;P -NRw) Q)h_ a1 RQ"71pqA ;7" -RNP1BYh_q hARp "17Qq Ap7 -";NQPRhpa_m_Bi1BaQi"YR Ahqp" 7;P -NR]7uq_1 1)mzB" R7qQ1A7p "N; -PpRupa)1_q hRQ"71pqA ;7" -RNPQwhaAq_Wi" R7qQ1A7p "N; -P#R3$NM_0F0Vs0lN#CHxRp"Bi7Q_Qde=.pRBi_wA7=QedB.Rpuim_e7Q=Rd.Bmpi1Q_7e.=dRiBpm_1.7=QedB.Rp1imdQ_7e.=dRiBpmBu_u1]q .=dRiBpmB1_u1]q .=dRiBpm_1.Bqu]1d =.pRBidm1_]Buq=1 dB.Rpuim_]wuq=1 dB.Rp1im_]wuq=1 dB.Rp1im.u_w] q1=Rd.Bmpi1wd_u1]q .=dRiBpmau_)_Qv7q pY.=dRiBpma1_)_Qv7q pY.=dRpup_Bpmim_v7d =.pRupm_pB7i_ Ypq=Rd."N; -P#R3$NM_0F0Vs0lNRp"Bi7Q_Q7e=RiBpw7A_Q7e=RiBpm7u_Q7e=RiBpm71_Q7e=RiBpm_1.7=Qe7pRBidm1_e7Q=B7Rpuim_]Buq=1 7pRBi_m1Bqu]17 =RiBpm_1.Bqu]17 =RiBpm_1dBqu]17 =RiBpmwu_u1]q R=7Bmpi1u_w] q1=B7Rp1im.u_w] q1=B7Rp1imdu_w] q1=B7Rpuim_Qa)v _7p=qY7pRBi_m1av)Q_p7 q7Y=Rpup_Bpmim_v77 =Rpup_Bpmi _7p=qY7;R" -RNP3HFsoLDHMCNlRF"Is; " -RNP3$DNC8sHR -j;N3PR#_$Mks#CL4LR;P -NR$3EbQCsMu#0Nv0EFO81FRbC"b0F_30VbjDDH0M#3pupQ0M#_;j" -RNP3M#$_LDH_DOCD;R4 -RNP3M#$_C0sNN0_#D_LNLO F4GR;P -NRM#$_LDH_DOCD;R4 -@HR@4j:n:g((n:4g4(:jpRBiBQRp;iQ -@HR@4j:n:g(44d:n:g(4B(RpAiwRiBpw -A; -@HR@4j:n:g(.4j:n:g(.uUR] q114 pRqu]1 1p -4; -@HR@4j:n:g(d44:n:g(dugR] q11j pRqu]1 1p -j; -@HR@4j:n:g(c4.:n:g(cugR] q17RQ)u1]q )7Q; - - - -@HR@4j:n:g(64.:n:g(nujR] q11ua Rqu]1a 1 -u; -@HR@4j:n:g(n4d:n:g((ucR] q1p7mq)R tu1]q qpm7t) ; - - - -@HR@4j:n:gU(n:4g4U:4aR17RAY1Aa7Y -; - -@HR@4j:n:gU44c:n:gU.ucRpqpWiY 1huBRpqpWiY 1h -B; -@HR@4j:n:gg(n:4ggg:Ra)1Ra)1; - - - -@HR@4j:n:gg44.:n:gg4 URhiBpm uRhiBpm -u; -@HR@4j:n:gg.44:n:gg. (RhiBpm 1RhiBpm -1; -@HR@4j:n:ggd4j:n:ggd (RhiBpmR1. phBi.m1; - - - -@HR@4j:n:ggc4j:n:ggc (RhiBpmR1d phBidm1; - - - -@FR@4j:(:jj((:4j4j:4pRBiRmu; - - - -@FR@4j:(:jj44d:(:jj4B(Rp1imR -; - -@FR@4j:(:jj44g:(:jj.BcRp1im. -R; -@FR@4j:(:jj.4n:(:jjdB4Rp1imd -R; -@FR@4j:(:jjd4d:(:jjdpnRmRBi; - - - -@FR@4j:(:jjd4U:(:jjcQcRhmapB;iR -@FR@4j:(:j4((:4j44:. R)wiBpR -; - -@FR@4j:(:j4446:(:j4.B.RphiQaRwA;- -y--------------------------------- -@ -ftell; -@E@MR@U(::U(::R4jI FsRDbDjCRPsFHDoN; -PVR3FNslDC_ODNDMl"CRbjDD"N; -PHR3#sPCHoDFR -4;N3PRHP#_CDsHF4oR;P -NRs3FHNohl"CRbjDD"N; -PsRFHHo_M_#0F"VRbjDD"N; -PFR3sDHoHNLMl"CRI Fs"N; -PDR3Ns$CHj8R;P -NR$3EbQCsMu#0Nv0EFO81FRbC"b0F_30VbjDDH0M#"N; -PtRh7)_7Bq_v14iR;P -NR03#lH0D#C0llNk#ojCR3jjjj;jj -RNP3l#00#DH0l0HC3Rjjjjjj -j; -@HR@U(:::4dUn:4RiBpQpRBi -Q; -@FR@U(:::4gUd:.RiBpm;uR -@FR@U(:::.nUj:dRiBpm;1R -@FR@U(:::ddUU:dRiBpmR1.; - - - -@FR@U(:::c4Un:cRiBpmR1d;R -s@:@(n4j:.j:n:R.jI FsRX ]upppRsPCHoDFRpupQ0M#_Sj -BQpi=iBpQp_up#QM0 -_jSiBpwBA=pAiw_pupQ0M#_Sj -u1]q p1 4]=uq11 _p4uQppM_#0ju -S] q11j p=qu]1 1puj_pMpQ#j0_ -]Suq71 Qu)=] q17_Q)uQppM_#0ju -S] q11ua =qu]1a 1 uu_pMpQ#j0_ -]Suqp1 m)q7 ut=] q1p7mq)_ tuQppM_#0j1 -SaY7A=71aAuY_pMpQ#j0_ -pSupiWq h1YBp=upiWq h1YBp_up#QM0 -_jSa)1=a)1_pupQ0M#_Sj - phBi=mu phBi_muuQppM_#0j -ShiBpm 1=hiBpmu1_pMpQ#j0_ -hS Bmpi1 .=hiBpm_1.uQppM_#0j -ShiBpm=1d phBidm1_pupQ0M#_Sj -Bmpiup=Bi_muuQppM_#0jB -Sp1im=iBpmu1_pMpQ#j0_ -pSBi.m1=iBpm_1.uQppM_#0jB -Sp1imdp=Bidm1_pupQ0M#_Sj -pimB=Bpmip_up#QM0 -_jSaQhpimB=aQhpimB_pupQ0M#_Sj -)B wp)i= pwBip_up#QM0 -_jSiBpQwhaAp=BiaQhwuA_pMpQ#j0_;H -NRM#$_bMFsCkMR -4;NuHRp1p)ah_ q7R"QA1qp" 7;H -NRaQhwWA_qRi "17Qq Ap7 -";N1HRaY7A_q hARp "17Qq Ap7 -";N7HRu1]q m_1z )BRQ"71pqA ;7" -RNHBmpi1wd_u1]q ;Rn -RNHBmpi1Bd_u1]q ;R4 -RNHBmpi1w._u1]q ;Rc -RNHBmpi1B._u1]q ;R4 -RNHBmpi1u_w] q1R -.;NBHRp1im_]BuqR1 4N; -HpRBi_muwqu]1j R;H -NRiBpmBu_u1]q ;R4 -RNHu_pppimB_7vm ;Rj -RNHBmpi1)_aQ7v_ YpqR -j;NBHRp1im_Qa)vm_upwR"qQpph;t" -RNHBmpiu)_aQ7v_ YpqR -j;NBHRpuim_Qa)vm_upwR"qQpph;t" -RNHm7zaQ7eQ v)_zRX7"e7Q7 -";NBHRp1imdh_ q ApRh" q Ap7 -";NmHRzQa7e Q7)z_vX"BR7BQe"N; -HpRBi.m1_q hARp "q hA7p "N; -HzRmae7QQ)7 _XvzA7R"Q"eA;H -NRiBpm 1_hpqA R"hpqA ;7" -RNHm7zaQ7eQ v)_zRXq"e7Qq -";NBHRpuim_q hARp "q hA7p "N; -HpRBidm1_e7QR -.;NBHRp1im.Q_7e;R. -RNHBmpi1Q_7e;R. -RNHBmpiuQ_7e;R. -RNHBwpiAQ_7e;Rd -RNHBQpi_e7QR -4;N3HR#_$MNV00FNsl0x#HCBR"p1imdu_w] q1=Rd.Bmpi1Bd_u1]q .=dRiBpm_1.wqu]1d =.pRBi.m1_]Buq=1 dB.Rp1im_]wuq=1 dB.Rp1im_]Buq=1 dB.Rpuim_]wuq=1 dB.Rpuim_]Buq=1 du.Rppp_m_Biv m7=Rd.Bmpi1)_aQ7v_ Ypq=Rd.Bmpiu)_aQ7v_ Ypq=Rd.Bmpi17d_Qde=.pRBi.m1_e7Q=Rd.Bmpi1Q_7e.=dRiBpm7u_Qde=.pRBi_wA7=QedB.Rp_iQ7=Qed;." -RNH3M#$_0N0VlFsN"0RBmpi1wd_u1]q R=7Bmpi1Bd_u1]q R=7Bmpi1w._u1]q R=7Bmpi1B._u1]q R=7Bmpi1u_w] q1=B7Rp1im_]Buq=1 7pRBi_muwqu]17 =RiBpmBu_u1]q R=7u_pppimB_7vm R=7Bmpi1)_aQ7v_ Ypq=B7Rpuim_Qa)v _7p=qY7pRBidm1_e7Q=B7Rp1im.Q_7eR=7Bmpi1Q_7eR=7BmpiuQ_7eR=7BwpiAQ_7eR=7BQpi_e7Q=;7" -RNHw7 Aui_qRa]"iBpm;u" -RNHp_uw)Q 11)amR."("N; -HBRQuz_B)h) agR""N; -H)Rw Tzh_BYu_QhBQpiRj"4jj3jjjjj"N; -H)Rw Tzh_BYu_QhBmpiudR"jjj3jjjjj -";NwHR)z T YhB_huQ_iBpm"1Rd3jjjjjjj;j" -RNHwT) zB hYQ_uhp_Bi.m1Rj"djj3jjjjj"N; -H)Rw Tzh_BYu_QhBmpi1"dRd3jjjjjjj;j" -@sR@.(:n::U..n:4FRIse RpPmRCDsHF#oRONkL_FPD_#HM0Z -S=#Z_ONkL_FPD_#HM0N; -H$R#MF_MbMskC;R4 -@sR@.(:c::U..c:4FRIse R]PQRCDsHF#oRONkL_HPE_#HM0Z -S=#Z_ONkL_HPE_#HM0N; -H$R#MF_MbMskC;R4 --y--------------------------------- - -@ -ftell; -@E@MR@:4n4::(4.:4RsIF FR0bV_0RsPCHoDF;P -NRF3VsDlN_DOCDlMNC0R"F0b_V -";N#PR$bM_FH##L0DCF4bR;P -NR#3HPHCsDRFo4N; -PHR3#C_PsFHDo;R4 -RNP3HFsolhNC0R"F0b_V -";NFPRs_HoH0M#_RFV"b0F_"0V;P -NRN3DMNous#NlR]"Bq hhp71Rq_aqWaQ7]7Rq71) 1Q_W7"a];P -NRqB]hph 1;Rd -RNP7qqa_7WQa.]RcN; -P7Rq71) 1Q_W7Ra]UN; -P#R3$NM_0F0Vs0lN#CHxR]"Bq hhpd1=.qR7aWq_Q]7a=Rd.q)77 _11WaQ7].=dR -";N3PR#_$MNV00FNsl0BR"]hqh =p17qR7aWq_Q]7a=q7R7 7)1W1_Q]7a="7R;P -NRs3FHHoDLlMNCIR"F"s ;P -NRN3D$HCs8;Rj -RNP3bE$CMsQ#N0u0FEv8F1Ob"CR0_Fb0;V" -RNP3l#00#DH0llCko#NC3Rj6cn.d -4;N3PR#00lD0H#0CHlRjj3jjcjj -; - -@HR@:4n.j:4:4.:.DRO DRO -; - -@HR@:4ndj:4:4d:68Rs_ ODR_s8O;D -@HR@:4ncj:4:4c:(CRs#_C08sORC0#C_;8O -@HR@:4n6j:4:46:dsR0H.or:Rj90osHrj.:9 -; - -@FR@:4nnj:4:.n:.HRVV8F_N_0NFrk0dj4:9 -R; -@FR@:4n(j:4:4(:UHRVVsF_8RCM; - - - -@FR@:4ngj:4:.g:jHRVVCF_l$b04 -R; -@HR@:4n44d:jd:4:Rd4p4ep_ta)_a7qqq_ep_Q7QphRe_p4a_)t7qqa_peqQQ7_h -; - -@HR@:4n44c:jc:4:R.Up4ep_eQhq7pQ_ta)_RQhp4ep_eQhq7pQ_ta)_;Qh -@FR@:4n446:j6:4:R.4w_ 7qqa_amzr:d4j;9R -@FR@:4n44n:jn:4:R.(w_ 7qqa_QW)am _z;aR -@FR@:4n44(:j(:4:R.gw_ 7qqawQQh17] _amzR -; - -@FR@:4n44U:jU:4:R.Uw_ a_)t) pq_1 mRza; - - - -@FR@:4n44g:jg:4:Rd(p4ep_ta)_a7qqq_epQQ_hH_s#oHMR -; - -@FR@:4n.4j:jj:.:R4cL#ks0 -R; -@FR@:4n.44:j4:.:R4n8OH#NRs8; - - - -@FR@:4n.4.:j.:.:R.dD0N#_VLk_bCl0;$R -@FR@:4n.4d:jd:.:R4(VHHM#8ECR -; - -@FR@:4n.4c:jc:.:R.jsCCDN_#CFRk0; - - - -@HR@:4n.46:j6:.:R4gECN8#s_0HEoRN#8C_H0so -; - -@FR@:4n.4(:j(:.:R.UECN8#N_sIk_F0N_PDRH8; - - - -@FR@:4n.4U:jU:.:R.gECN8#N_sIN_PD_H8P0COrj4:9 -R; -@HR@:4n.4g:jg:.:R4gECN8#P_DDE4RN#8C_DDP4 -; - -@HR@:4nd4j:jj:d:R.(ECN8#P_DDH4_MDPNHE8RN#8C_DDP4M_HPHND8 -; - -@FR@:4nd44:j4:d:R.4ECN8#V_FV0#CrjU:9 -R; -@FR@:4nd4.:j.:d:R.(ECN8#V_FV0#C_DPNH;8R -@FR@:4nd4d:jd:d:R.6ECN8#H_IMI8F_8CMR -; - -@FR@:4nd46:j6:d:R.UECN8#k_LVk_F0N_PDRH8; - - - -@FR@:4nd4n:jn:d:R.nECN8#k_LVC_sD#CNC -R; -@FR@:4nd4(:j(:d:R.(ECN8#k_LVH_VMEH#C;8R -@FR@:4nd4U:jU:d:R.cECN8#H_E0k_F0r_Hd9:jR -; - -@FR@:4nd4g:jg:d:R.cECN8#H_E0N_PDrH8d9:jR -; - -@FR@:4nc4j:jj:c:R..ECN8#H_8#sON8 -R; -@FR@:4nc44:j4:c:R.6ECN8#M_HPHND8D_8rjd:9 -R; -@FR@:4nc4.:j.:c:R.dECN8#k_LVs_8Fdbr:Rj9; - - - -@FR@:4nc4d:jd:c:R.dECN8#L_8oF._kd0r49:jR -; - -@FR@:4nc4c:jc:c:R.nECN8#L_8oO._F#NsC:rUj;9R -@FR@:4nc46:j6:c:R.(ECN8#s_8FOb_lLb_k4Vr49:jR -; - -@FR@:4nc4n:jn:c:RdcECN8#s_8FOb_lLb_kOV_F#NsC4r4:Rj9; - - - -@FR@:4nc4(:j(:c:RddECN8#s_8FOb_lLb_kPV_N8DHRs; -R4@@nU:4(n:4:(4U:RddI FsRVVHFF_OD0COFPsRCDsHFVoRH_VFOCFDOs0F_#HM0I -SsD_O s=I_ OD_VVHFF_OD0COFHs_M -#0S_s8O=D sO8_DV _H_VFOCFDOs0F_#HM0s -SC0#C=#sCCV0_H_VFOCFDOs0F_#HM0H -SMN_80gNr69:j=_HM8NN0_VVHFF_OD0COFHs_Mr#0gj6:9H -SMl_Cbr0$.9:j=_HMC0lb$H_VVOF_FODC0_FsH0M#rj.:9H -SMC_sNC8_MDNLC:r.jH9=MC_sNC8_MDNLCH_VVOF_FODC0_FsH0M#rj.:9F -Sk80_Nr0Ndjg:9k=F0N_80VN_H_VFOCFDOs0F_#HM0grd: -j9S0Fk_bCl0F$=kC0_l$b0_VVHFF_OD0COFHs_M -#0S0Fk_NsC8M_CNCLD=0Fk_NsC8M_CNCLD_VVHFF_OD0COFHs_M -#0S#8HO8Ns=#8HO8Ns_VVHFF_OD0COFHs_M -#0SIsN_NCML=DCs_NICLMNDVC_H_VFOCFDOs0F_#HM0N; -H$R#MF_MbMskC;R4 -@sR@:4n4:6(44c:6.(:gFRIs0 RsNL_80NbCPsRCDsHF0oRsNL_80NbCHs_M -#0S OD= OD_L0s_NN8bs0C_#HM0s -SC0#C=#sCC00_sNL_80NbCHs_M -#0Sppe4)_atq_7aeq_q7pQ_=Qhp4ep_ta)_a7qqq_ep_Q7Q0h_sNL_80NbCHs_M -#0Sppe4h_QeQqp7)_ath_Q=ppe4h_QeQqp7)_ath_Q_L0s_NN8bs0C_#HM0w -S 7 _q_aqm=zaw_ 7qqa_amz_L0s_NN8bs0C_#HM0w -S 7 _q_aqWa)Q z_ma =w q_7aWq_) Qa_amz_L0s_NN8bs0C_#HM0w -S 7 _qwaqQ1hQ]_ 7m=zaw_ 7qqawQQh17] _amz_L0s_NN8bs0C_#HM0w -S a _))t_ qp 1m _zwa= a _))t_ qp 1m _z0a_sNL_80NbCHs_M -#0Sppe4)_atq_7aeq_q_pQQsh_HM#Hoe=ppa4_)7t_q_aqeQqp__QhsHH#M0o_sNL_80NbCHs_M -#0SsLk#L0=k0s#_L0s_NN8bs0C_#HM08 -SHN#Os88=HN#Os08_sNL_80NbCHs_M -#0SVLk_bCl0L$=kCV_l$b0_L0s_NN8bs0C_#HM0L -SksV_8=CML_kVsM8C_L0s_NN8bs0C_#HM0V -SH#MHE=C8VHHM#8EC_L0s_NN8bs0C_#HM0s -SCNDC#FC_ks0=CNDC#FC_k00_sNL_80NbCHs_M;#0 -RNH#_$MMsFbkRMC4s; -R4@@n.:4U(:4:U4.:Rd(I FsR8ENC0#_8LO_kDM8CCRPsFHDoNRE8_C#0_8OL8kMDHC_M -#0S#sCCs0=C0#C_8ENC0#_8LO_kDM8CM_H#S0 -b_DDO#D rjd:9D=bDD_O E#_N#8C_O08_MLk8_DCH0M#rjd:90 -SsrHoj9:j=H0soN_E8_C#0_8OL8kMDHC_Mr#0j9:j -eSpp04_s=Hop4ep_H0soN_E8_C#0_8OL8kMDHC_M -#0Sppe4M_HPHND8e=ppH4_MDPNHE8_N#8C_O08_MLk8_DCH0M# -CSsVCCsM8OC_0Fkr:.djs9=CsVCCCMO8k_F0N_E8_C#0_8OL8kMDHC_Mr#0.jd:9s -SCsVCCCMO8k_F0N_PD=H8sCCVsOCMCF8_kP0_N8DH_8ENC0#_8LO_kDM8CM_H#S0 -I8HMFCI_MI8=HFM8IM_C8N_E8_C#0_8OL8kMDHC_M -#0Sppe4V_FV0#Cr:44jp9=e_p4F#VVCE0_N#8C_O08_MLk8_DCH0M#r:44jS9 -p4ep_VFV#_C0PHND8e=ppF4_VCV#0N_PD_H8ECN8#8_0Ok_LMC8D_#HM0L -SkFV_k.0rd9:j=VLk_0Fk_8ENC0#_8LO_kDM8CM_H#.0rd9:j -kSLVk_F0N_PD=H8L_kVF_k0PHND8N_E8_C#0_8OL8kMDHC_M -#0SVLk_DsCCCN#=VLk_DsCCCN#_8ENC0#_8LO_kDM8CM_H#S0 -L_kVVHHM#8EC=VLk_MVHHC#E8N_E8_C#0_8OL8kMDHC_M -#0S0EH_0Fk_dHr:=j9E_H0F_k0HN_E8_C#0_8OL8kMDHC_Mr#0d9:j -HSE0N_PDrH8d9:j=0EH_DPNHE8_N#8C_O08_MLk8_DCH0M#rjd:98 -SHN#Os88=HN#OsE8_N#8C_O08_MLk8_DCH0M# -MSHPHND8D_8rjd:9M=HPHND8D_8_8ENC0#_8LO_kDM8CM_H#d0r: -j9SVLk_F8sb:rdjL9=k8V_s_FbECN8#8_0Ok_LMC8D_#HM0:rdjS9 -8.Lo_0Fkr:d4j89=L_o.F_k0ECN8#8_0Ok_LMC8D_#HM04rd: -j9So8L.F_ONCs#rjU:9L=8oO._F#NsCN_E8_C#0_8OL8kMDHC_Mr#0U9:j -sS8FOb_lLb_k4Vr49:j=F8sbl_Obk_LVN_E8_C#0_8OL8kMDHC_Mr#04j4:98 -Ss_FbO_lbL_kVOsFN#4Cr49:j=F8sbl_Obk_LVF_ONCs#_8ENC0#_8LO_kDM8CM_H#40r49:j -sS8FOb_lLb_kPV_N8DH=F8sbl_Obk_LVN_PD_H8ECN8#8_0Ok_LMC8D_#HM0N; -H$R#MF_MbMskC;R4 -@sR@:4n(nn:::(n4IdRFRs bjDDRsPCHoDFRDbDj#HM0B -Sp=iQBQpi_DbDj#HM0B -Spuim=iBpmbu_DHDjM -#0SiBpmB1=p1im_DbDj#HM0B -Sp1im.p=Bi.m1_DbDj#HM0B -Sp1imdp=Bidm1_DbDj#HM0N; -H$R#MF_MbMskC;R4 -@sR@:4n.:jn..d:jcn:(FRIs0 R8OO_EMNMCVD_H_VFFRk0PHCsDRFooLCMD\ 4r9.\\830OE_ONCMMDH_VVFF_kH0_M -#0S#sCCs0=C0#C_MoCL4D \\r.90\38OO_EMNMCVD_H_VFF_k0H0M# -DSbDD_O d#r:=j9b_DDO#D _MoCL4D \\r.90\38OO_EMNMCVD_H_VFF_k0H0M#rjd:9O -SF#NsC(r.:=j9OsFN#oC_CDML r4\.\\93O08_NOEMDMC_VVHFk_F0M_H#.0r(9:j -sS0H0o=s_HooLCMD\ 4r9.\\830OE_ONCMMDH_VVFF_kH0_M -#0SVVHFN_80FN_kd0r49:j=VVHFN_80FN_ko0_CDML r4\.\\93O08_NOEMDMC_VVHFk_F0M_H#d0r49:j -HSVVsF_8=CMVFHV_Cs8MC_oM LD4.\r\39\0_8OOMENM_CDVFHV_0Fk_#HM0V -SH_VFC0lb$H=VVCF_l$b0_MoCL4D \\r.90\38OO_EMNMCVD_H_VFF_k0H0M# -8S0Ok_F0:r(j09=8FO_ko0_CDML r4\.\\93O08_NOEMDMC_VVHFk_F0M_H#(0r:;j9 -RNH#_$MMsFbkRMC4N; -HsR30FD_sMHoNRlC"O08_NOEMDMC_VVHFk_F0M_H#;0" -RNH3_H8o_CMM0C#C"8R4 -";N3HRHo8_CbM_N_0EjoR"CDML .4r9 -";s@R@4.n:j.n:dj:.n(:cRsIF 8R0OE_ONCMMDH_VVFF_kP0RCDsHFooRCDML r4\4\\93O08_NOEMDMC_VVHFk_F0M_H#S0 -sCC#0C=s#_C0oLCMD\ 4r94\\830OE_ONCMMDH_VVFF_kH0_M -#0SDbD_ OD#:rdjb9=DOD_D_ #oLCMD\ 4r94\\830OE_ONCMMDH_VVFF_kH0_Mr#0d9:j -FSONCs#r:.(jO9=F#NsCC_oM LD44\r\39\0_8OOMENM_CDVFHV_0Fk_#HM0(r.: -j9SH0sos=0Hoo_CDML r4\4\\93O08_NOEMDMC_VVHFk_F0M_H#S0 -VFHV_08NNk_F04rd:=j9VFHV_08NNk_F0C_oM LD44\r\39\0_8OOMENM_CDVFHV_0Fk_#HM04rd: -j9SVVHF8_sCVM=H_VFsM8C_MoCL4D \\r490\38OO_EMNMCVD_H_VFF_k0H0M# -HSVVCF_l$b0=VVHFl_Cb_0$oLCMD\ 4r94\\830OE_ONCMMDH_VVFF_kH0_M -#0SO08_0Fkrj(:98=0Ok_F0C_oM LD44\r\39\0_8OOMENM_CDVFHV_0Fk_#HM0:r(j -9;N#HR$MM_FkbsM4CR;H -NR03sDs_FHNoMl"CR0_8OOMENM_CDVFHV_0Fk_#HM0 -";N3HRHo8_CMM_CC#084R""N; -HHR38C_oMN_b0jE_RC"oM LD49r4"s; -R4@@nj:.nd:.:n.j:Rc(I FsRO08_NOEMDMC_VVHFk_F0CRPsFHDoCRoM LD4j\r\39\0_8OOMENM_CDVFHV_0Fk_#HM0s -SC0#C=#sCCo0_CDML r4\j\\93O08_NOEMDMC_VVHFk_F0M_H#S0 -b_DDO#D rjd:9D=bDD_O o#_CDML r4\j\\93O08_NOEMDMC_VVHFk_F0M_H#d0r: -j9SNOFsr#C.j(:9F=ONCs#_MoCL4D \\rj90\38OO_EMNMCVD_H_VFF_k0H0M#r:.(jS9 -0osH=H0soC_oM LD4j\r\39\0_8OOMENM_CDVFHV_0Fk_#HM0V -SH_VF8NN0_0Fkr:d4jV9=H_VF8NN0_0Fk_MoCL4D \\rj90\38OO_EMNMCVD_H_VFF_k0H0M#r:d4jS9 -VFHV_Cs8MH=VVsF_8_CMoLCMD\ 4r9j\\830OE_ONCMMDH_VVFF_kH0_M -#0SVVHFl_Cb=0$VFHV_bCl0o$_CDML r4\j\\93O08_NOEMDMC_VVHFk_F0M_H#S0 -0_8OFrk0(9:j=O08_0Fk_MoCL4D \\rj90\38OO_EMNMCVD_H_VFF_k0H0M#rj(:9N; -H$R#MF_MbMskC;R4 -RNH3Ds0_HFsolMNC0R"8OO_EMNMCVD_H_VFF_k0H0M#"N; -HHR38C_oMC_M#80CR""4;H -NR83H_MoC_0bNER_j"MoCL4D r"j9; -@ diff --git a/impl1/synwork/layer1.fdep b/impl1/synwork/layer1.fdep deleted file mode 100644 index 29f3a90..0000000 --- a/impl1/synwork/layer1.fdep +++ /dev/null @@ -1,53 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-mixedhdl|-top|work.Uart_top|-mpparams|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_mh_params|-layerid|1|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-distcompmode|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075 -0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl -1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl -2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl -4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 -1 -1 -2 -1 -3 -1 -4 0 1 2 3 - -# Dependency Lists (Users Of) -0 4 -1 4 -2 4 -3 4 -4 -1 - -# Design Unit to File Association -arch work intface intface_a 0 -module work intface 0 -arch work modem modem_a 1 -module work modem 1 -arch work rxcver rxcver_a 2 -module work rxcver 2 -arch work txmitt txmitt_a 3 -module work txmitt 3 -arch work uart_top uart_top_a 4 -module work uart_top 4 - -# Unbound Instances to File Association - - -# Configuration files used diff --git a/impl1/synwork/layer1.fdeporig b/impl1/synwork/layer1.fdeporig deleted file mode 100644 index 8082cb6..0000000 --- a/impl1/synwork/layer1.fdeporig +++ /dev/null @@ -1,50 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-mixedhdl|-top|work.Uart_top|-mpparams|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_mh_params|-layerid|1|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-distcompmode|-noobf|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075 -0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl -1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl -2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl -4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 -1 -1 -2 -1 -3 -1 -4 0 1 2 3 - -# Dependency Lists (Users Of) -0 4 -1 4 -2 4 -3 4 -4 -1 - -# Design Unit to File Association -arch work intface intface_a 0 -module work intface 0 -arch work modem modem_a 1 -module work modem 1 -arch work rxcver rxcver_a 2 -module work rxcver 2 -arch work txmitt txmitt_a 3 -module work txmitt 3 -arch work uart_top uart_top_a 4 -module work uart_top 4 - -# Unbound Instances to File Association diff --git a/impl1/synwork/libfileorder.txt b/impl1/synwork/libfileorder.txt deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/modulechange.db b/impl1/synwork/modulechange.db deleted file mode 100644 index b76d9acda5419a630daaa1a2c1f4460ed4455a15..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20480 zcmeHNe{2)i9Y4qS;yCfWmykHlFZ&$ZG^BtXLx2=05FqVn!+;Pd9TV4!eNK+}7xp<2 zShZ1&P17_+E1^#6w4zP@gROtCZd0YTn?Q6L6&jT~wc4gu6WYojUDu9jQuj;CzTfj* zVoK9ERQm(%1#zG6d*5I0eeS(?_W8Sa&#-Q2!Bno0QH|hgp;2%+ge}3KAkyLaH1kr8*Ix6IOM2Hb>xh}D#f+*b(*i-bpbc2r0W6Zlb1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXW&yaFnMawSB{Av(8>3=NJB1xE+B4i5z@6w4mi zu|23~4Q*U21oH(wqZX!vliKtOXlPT0p3#bin#tQHy(6c#*7|yS9GaOdlS`J;T2jkv z*<|sS2Dv5SEvjWZ%PCg`t=zrGoi1N@x8vmIilBNnl`FfUBz{ad?6+gxKK!&k7MxNG zKt*9iFrlT>bFC>|J8HLjf&a|^n!VangSF;;PCHyazu$3k`RuL2N#N~3thr^9cJC+L zA=Q|$=dmJq`@NEwCM>Pp+2`8HuCitHJ^Fo`rBUg9=>^G<)_Okhe9JT9X=u3IaH1hz zf35y({ek)}_jUI2$CQhtCJS4F2D zd-b_@w}eIE@jDCw5w2X@y)GmQlhsEsa(PUBr8K^!dr_%VdMc+Ra_~vY$Q2;M#c%vh zh4q7$U2JM187pOr`gm4LMxikSz5^XV zpd(hDFL0hv^Loa1UfV7TxhkEDMlv2>+i$zBY7>R=>RoNOjXqI0QLS4xUsNVkxa23t z?Eq_As~>WS>;s&T9oNYZUFo{mrn2tDLl2 z(2WV(@z4_7fYmSWg*IS(b_2$71J1yKJk$g!8Wu>ADWwe^mTat~7GRC$N(DIiP*&i$ zF$W8gwlzW|*PTQ%j%9Sin2p2kG*01IVoHOv3w8#KXDfv`*H#`yad~712>9ON*DH^3QGeYz&nQPnQyK8pZN3`=pk_k%#wg zs4<_r3ud=`wM2eRDYFJnVRVLF;n(L|bPon`zs#q-{ZkXJ#Qr|TT9c*(pFTp5Ut8@E z1$}{iSFyCslW0bQu{qd>0{amDz0clZZ?RvqSJ(^eJUhppW~bRH_61gChuKT)G??-~ z&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0Wh+0avF}5b-65tHT!BZK2H;e74YP3tkjv z8VypV!v@MK|%TYlcL}h95b#aXyVH*SEDV2KzQuZ%OAK*;mY7kt_b$L z`qcCI{XguvM__+qZ?KoyGwcbLW+SYZQTlg!o&Jjcm_AFtLXXfzp0nPwtfHS}u;0$mEI0JV*1ECNRyzx#f zQz{p24euY0LwV0pC08<_gaChQ4|api$_g7JnNY?`*<@O?EPCOWPVeTASYRD`R>NAM z%3$}(U^+ODsabh7m$)qewtmyrDCpygo}IE1c0$dPH*9If6sSnc8(P6q`ny2cV=B#n zb}5&oZtn!OJgYW;XSGzV9iVD2ht1^`BW3kR+M$0Q$%0ax z$Q5iFWgn=QmxCOI0<#Gvsi#tkk;z+GI$OcOn$(l zQJbM!#oKQBl*?Gq!w01&-gZBFlsn5;u!dq1%eq{wVp>COh-F>wEMFCM2~>A@eP(R4 zBn6GV_1I^Q-0U+iirV6a?oQLxDmy{r_B!m9aU52!1&Z3^0@VgH&O8++7AbADU|3#` zc;~Tt#3qq|W|qXb)$0>6ry1B<50*l9f}*?*22>*?pwgyb)9HyBL zufdyv6U<;4mSPHflsTMWEeNqr*1{xKOK0G{!A<%u{R4fAzCo|iU($>8 z7xd@!MS6jrr{AOBrf2DC`c?WRdYl$%nx?2i570gIVY;1erUNuim(vLK(^kr89j%f6 zCH+nMvvfoHz4Tk@b?K_~iu5z-Md^ZcUiz-|jCA&{KU(<&I0Kvk&H!hCGr$?(3~&ZG z1Dt{XZwAEAJ00#Oa?t5;G|A+12m$gaf`=SHXc8X*i$<~^8jUj9hY%p62p+N*p-CJ8 z3r6-pgUMt!LV)Z-@Q}|UG?ASMjp8sEQt~h~s7xM02#_5J9`YH4Ch{Ocqxb+Awvr)e zw8~^VLcqDrS?4BOL2j4DLC|~27HD{7vKb*jHUYHB;{Bi!$wp|1GTDF-5Z6PWMDBxz zB$EMz09l9NA!`wu$QlGD_Jg5^tcHe1CaVwvB#z)AeIyD(AVgLogvkno2w9FGlY0UD zA<_%b5hBX~+C!uVAx!Q;h>)cSGKm1Rg-947OhO0|(v2XKAb=PmGD4UH5F*5nAd@bD zW?c&86X%UOAx}O2_Zrn0lGtk zA%qD9fR}F)LYR0EBBTMJD@5uMx``X0GeqhTx`_)RNNNFULxdoNiHHy(P6V0MAT$sM HfXnk=UHm12 diff --git a/impl1/synwork/s1_impl1_comp.fdep b/impl1/synwork/s1_impl1_comp.fdep deleted file mode 100644 index 401df9d..0000000 --- a/impl1/synwork/s1_impl1_comp.fdep +++ /dev/null @@ -1,79 +0,0 @@ -#OPTIONS:"|-mixedhdl|-modhint|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile|-top|top_tf|-layerid|0|-orig_srs|/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/hadaq/mmichalek/lattice/simplified|-I|/home/hadaq/mmichalek/lattice/simplified/impl1/|-I|/opt/synplicity/O-2018.09-SP1/lib|-v2001|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v|-devicelib|/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v|-encrypt|-pro|-DSBP_SYNTHESIS|-distcompmode|-noobf|-auto_infer_blackbox|0|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-D_MULTIPLE_FILE_COMPILATION_UNIT_|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_ver":1543382462 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork/_verilog_hintfile":1614215581 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v":1543381843 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v":1533714205 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v":1543381931 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":1603268894 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v":1603268905 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":1600007909 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v":1603268916 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v":1603268926 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/modules2.v":1623422897 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":1623231962 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":1612873166 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/top2.v":1623749991 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":1623772752 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":1623827946 -0 "/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" verilog -1 "/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" verilog -2 "/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" verilog -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" verilog -4 "/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" verilog -5 "/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" verilog -6 "/home/hadaq/mmichalek/lattice/simplified/modules2.v" verilog -7 "/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" verilog -8 "/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" verilog -9 "/home/hadaq/mmichalek/lattice/simplified/top2.v" verilog -10 "/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" verilog -11 "/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" verilog -#Dependency Lists(Uses List) -0 -1 -1 -1 -2 -1 -3 -1 -4 -1 -5 -1 -6 2 -7 8 -8 -1 -9 6 0 10 7 -10 11 -11 6 -#Dependency Lists(Users Of) -0 9 -1 -1 -2 6 -3 -1 -4 -1 -5 -1 -6 11 9 -7 9 -8 7 -9 -1 -10 9 -11 10 -#Design Unit to File Association -module work hades_tdc_channel_raw_out 11 -module work hades_LVL1_raw_out 11 -module work top_tf 9 -module work trb_adapter 9 -module work hades_tdc_bundle 10 -module work fifo_colector 7 -module work fifo40_dc 8 -module work tdc4ddr 6 -module work tdc_channel_fifo_out 6 -module work output_decoder8 6 -module work tdc4ddr_short 6 -module work trig_inv 6 -module work pll_random 5 -module work pll8 4 -module work UART_VerilogWrapper_TOP 3 -module work fifo32dc 2 -module work pll1 1 -module work pll0 0 diff --git a/impl1/synwork/s1_impl1_comp.linkerlog b/impl1/synwork/s1_impl1_comp.linkerlog deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/synwork/s1_impl1_comp.srs b/impl1/synwork/s1_impl1_comp.srs deleted file mode 100644 index 6cc1a978a44998bdd0ad817a0b8280b2e4983f9b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 53444 zcmZsCRZtvSux%0&2p-%axV!7%5F`Y5cXxMpcZc9E0}Sr&1b1if!JXlqcRz34{_C#V zKV7?R^=gvn@1OohU|f{?;?`Jxbb;w5e-^8ev3^d|>o`TjGjGI8T&WPG zjU60umqSc-Q>9fJzRrH!>KwD+2wLKo99ZVYeoeBH3mf~vHOl!dEScJ@X@|jQF|?t>ivuiQNa}Ao}NG!Jw9J$L+90LF~mte3;WN$XZKsf3Zc_ z)Xv~FUx`<`Oye+PFNd@?2R;`fivDvGa#?d4bPnx3&UOgIH%E+G_^bo}f*lhR%N0?i z9*=v!E3VUp^~#`^`{RX%9X5Wi=2-54Kx`j@ZtNI94K7UhBuLagLGc$mw{u1~;CinI zP1+%GxPFq_35!TtSX0NIZ9_;9V8`9DxRWEvxu2zGv%?$f&0luDCc>uEezFUlDa#{=%#Kw2$ifkBkJG#ja{D4%MHP&PahwX8s7GM zJWU@RK2bCk90gW4f2yfuR4N8Z&uT{}&@=y4jgy6Z`x01SGcE^sZ$>UGEU8-MUz;PU zFt#Dd2SW%+q~z-VdR6SnE?XXx6_+ndKviL%rSq5dIRh}=Ta`Bcgmx$OUp=@rZ$){T zP(Q)-GfgJ{4xp^AGTVV`Ws_iqNdFm0huWr15R8I?etyOxS7nVQ#;$OV@*qx` zs&cq?uUs5<{8FVfT10rPf7@2N(5pH-8(KB1plWJM_N7Q1$A5(jz)8l5%Kk@_J;Dgu*XX+OCI+p+YSkdi}th_#-bU zmPIq0OX8ly<%1Spv9*S0JFSF9lYc9G5D^0$PoLM%3O`d=vp9)aG}~^;1WZzmww3ju zBBuJA0qcy)(%9R$CyZ{l)KP8QR9B5egIu!BIPn-i3Oh+vb0HO1+V4IjlDYv-{NCO!1Wa{g)vt+UHI@wM7$TIv63oq zWA|Tv^VTP>Tus%J44t-Z1nE261*7-EeUT3oDI=4?MGWcN0Yl+Y|1@z$qqJbHU z>dgIEBHG0-=zV%*O3&4oQg_7Nde7qc{Z<~W&g8k>tlxcm99J(m%hf~*(8nkT3~=>4 zcjANJW{#_x#UakWN`xi|G?^HMXL~A-vqp_xs%Q3w-BlDI#M@wyntO_NFTSF`=1>2| zYmCE47myPC8C@nIub!r~iDVQ4Vf@4(3%eAXrH!T6*K@PcPv0DbrKWy&T6vCj0M7g! z2~idMuHI|@?(1d03BKd_#GRG{r?zKw;;<$Eg*GsQ>lOWDGtlit4@8gvUh&$yQ`ly` z6j0nIXGpa67ye>N`TW_J#g>#UobJCE$R9h?BADIO&<&{JH4~z_t`2zGfjOe~f`Vqqn@2FTrI4G6bwqhWBR$L=Bz(0i>E*rT9>F%Q~RAl)2DkgL! z$&KOz9Ygf}O(V+mxz3Svc1=lWsYKUra2V(@dl-RQ8KV!UQcq(@&6I9pHt2DZ;$5U* zWF9u*rO9C(T1d3iWJ)?Rn31}oX%_0XhGW%8$ck^e%Pn!n>klmBLP&HFWLVePgyvDtoZjB^#_Vd7)YY*5II zJ3&-IJ$)-;Cveh*8NwHQTTac~m5~xw?>w9{)8Tv3q#tu_Ex>9fYICPIHeuZ0%?;_v z<_F)d^)?AoesfG?78Rj({Z(Em8;DD}726CQ#N~#rJ%+SOQDeyWBHEsFoF#ko&B#Sy z$LCV|ah(#)eXUXN*Tg_%!`xZxSvi(7Ip7!Qv(1Obv*>|2WAzuvyc^WQIq^&z& z`25~CnnhHwd*Z}B9(CIhhugjkkswJA8kG!=L$(b@OdJZ1m&}F$&Q0?#d8HT#Z+DQS z&Y>oJL=M-6jNU!N*R5cWNo_u7q_O@?)TgyOn~Q+vDM$GgMA#GNGw^1}l8HGj_I;$A zQZjL*zLm}_<~C%!XJ2AM%3fn~#Qu$X4Uju0l#_{BCrLPiM0Tg=Ru|8M9h=#;&soT# zN8P|09hy$;ITY`kI9xYlC5o17tm;y~JIKxi#=^mn!Ffaq6zJ~6hs8GbN|>->(MiA| z2dsUdEH~zY1)6ljE;BF84H#M#I}heLce2Gxrw~wvXdH7tR-@ zZ1OC&XNaByUW??y0D8>qyA6;c`nCjQOP)DF%z4=E<2jD zgtRA2cYo}c?6f!S`+*3||Hc5Gkl{|p%%7$m9u6C~-^`q}dzv5YkC=_!mRBa;tO#un zTL}6MXXa44EvGrV`KEwC&&`z!+;Ci?ccaeRwtF=2lqG=J#!zqavj!?#WdaaF9l*|w_Tjsn#%l1`#dc~|mi^Yg#ZMOf)VIV&&NkXtzyp4AY`VpEt@$xIbOF}ag z`*j}(#Lgg=^wjdFpU7>&9QN4F@mog(Covt?zO@h{uJyaEb>}%xPSJM2ccC9|Q}*16 z+dBO-oOVr!-i0X?{UB%kDb5kT=X%PSE7QI2pjz z2=|M82Pmr7Uj9nypBZP0~M7b?S35uPK4c-T3 zxwrEuZ%z3}+<=>GEvEs6>1+KZ_whtS9P4msSeG&MxnrgeuwmdiFp`Zl$^g*tYjJg9 z^BGrt=(5>S#-iMl4Gh^?;$9?8TImS&_2)5k8yu++=;Aemj3)2LWKBt}YeEtAiLW{v z8ncy-+Isgj{YK0^`@BK}kSOx2zfkO0iDDmGWF(+%F*%d8b8v6$$OJ;| zdNS_(x7=n0Z_Ir>f4?;k^0wSSMm7u~h9gWLtC!v#c1=;V3L+mhUPPeZ($~Qb`=!CUst4|K*d{{|aMCNv#x5$Wxb3 z5ok)uy$8LzjPMPecrkBHu!1UGg@^W4@{g!})b^%h0|5I>hIsVIRv2W~tfRdVH$f|! z;y0F^p9h-Xn5~hyR-;UqnDH=F8!94bF*wJ6p_x)NmSyvBGvIVvSob8ib$X-?UPu(U zTdQmtcYFP`bX17p0MfqQbSp|1bZGT=oMpy=6W4Rtp(y$YJf0w8z^D;v@j&vL*(ei|q=ft|cCcPt4&ywUnlFgvY%@MF zgBkfBk&fM5gduNo4kk7`1Ii!4FK(V;%6~FIgRA81Axa}C>v0M3uB+;FJ-QMpaj0j> z3<6^t?t)e6U7cr|AB+1Y)Yhn3hhW3Xm;6aFrX#W>XI9f6T*Zg{W6V*)hi<*lejMtU zhEimBKkGR|H{!Q!6U9C5ATt|8bRaa&$*{XQ1W0tO9q4=U!FxCg0PgyOEU)#BnPu<*Z9l%d^L^Aqu92_5 zaXoczvmh{e$*<_$X+q8jVNU8GSmG>*E$lwSMNpxk!Y!!H)T`?ZL7R{h6_1l=I2!)7 zJ*p@4er$33U#BW6aq%Sj%EvDbb2 zap`<_`fvFPFKlo9qOI10O%t>=eo6M+@&h#nMJ`h^k>;Tw7b~Flpp4*&N$^9#*%-f~Iligzf%$*(`Tt7q3!2-}ReV4EmU{M#UVffy zq9IA_%knx>;@~sFyr_J)SaF^!33~q6mFxg0HDB7z1PZ?XW2()Z^kLuTPIehFl&T** zSZJjV%GUoXhVVhR9mFzu_Jj6%rwm~su#xH4esHb`ehQuExOme1L8SQt+=$Qen9*zR zPvIHs-eE^62PTLIfYilA*J!5l9$V%ZKc~g}QzbGnzA%DH-VW0q zU*9M|kN4dxTl24z$);_Lzt^kFADah^2(Ij?;pAAZrGphhJZiUTmp-fRyUV3M1b>UX z`6jFS7!!J`A!U5H!v7FeGlGP7dx^(f&1yex0kwYC%N=uI zb#?zT;4P;ko2b~Qrr^a)@yO$%t z9q>~Qqmbu}&Es!en?4~*`&el^?@mxSZb_VDL^{@B6aP_J$RDwJ zN9%k8pYwPT7Zcv)d+SK#!?q(b*yNFO+zc+S-nnSE?j>B8MTHCJ=Ffx5iWP&*?8kou z2MdLjeFfuwdVW`Lz&)o^R17`-tlY|2w#87Em#A!?rEH(149PxFVLDRLyGz#meMnJu zbLPZ%92Ezmxsn&CS@zH(;PsuOAsE`6LD)NOn<=Ne2eO@5eU%kF`Lb--4Ua1j!SajK zFUL%wH<#O=5TEIRSu9yfkg~Y7p5G!9O4D(}i7gOoT4k&WzQ)d|<6E3lM~?djCHBm9 zzHb^{oEOy#*V9`iS^?}Msn%DxpwgxS?kwxiSna)9b!N121*(sT8|G@w=#?A_R?ZW> zS_y8n9d68UEXr493XmpTh1%x`u${s}&!kwUOKZF?=5Oq0OAX_EGoM+I&DR!k&N#4Y zdYJEzap_ybS7ihBr?e~*VRid>I0PI&C{Fl<+jdU>DCx5ZE^WgO>iRBJ?*&228 zgJ3>CfHR-r(7p0ABBzr)3<9s*zSh3|e1MlO%&97J`TB8na6@Q!42+q-cRGwm+I~&q zex{@i7@zg*9`x|UJYY}@10=RzQ+xZXMEeAMRH1ckBVPKw@?}J1A zT3v8lR1wprcX1xBH4y>cP%h&Rw%1Ir`!b{aYoE0X^WYDDC~*VxCJBCn_x#Fs zE}9*0k-y?OyPm=f_||**%$gGV4*lq8(4X&&zkc_E==05FTU!&o#)6+TZLEPaQZrsh z=OB;T+`IQs_RbS^)O8D2GmlK~yJuAY;0@+?wT9tmcW|Kg%*)Yvk4s%c$PC=2gWP28 z=7jFia+lC!$8Pnqg4q#Z{%o87Rgd=-a_(>Q>i>TgiB3&j>$7%r-&+46%FE!w&Hf*T zHqVqcCr?&lhZ&z=X@AzsJJ&}e&wYfmJMAy%U)Z6z>(fw(|C_Who2tgUFWBj|kk{Ds z=h{rG*~QE*oICP%H4gN+_F$ZLiL7w zv~m7#WsKrnH`#GD`YRz{PI6`y9B)%NkFyfXt9a@Awmm<}uhkdZV{2k!jBfVldM1o{ zddAJcWr;5xnevX^&Oaq0<11Z|!5bz;#INhwXZRN#I$XOQwIf|s#n|Hl4sD2mIObZa z2ZvI5%My=8bb6!lJ8;*hSAbw~0M9$=Odg>C2jV~JUscGG zwxoyVxqo!*2Lq!IKcl29R11M)4xd8jB)v}i3nI<(9Wi!^4)k#K*E_l^Qe;rQ>(? z)p-s4O0=Hdp42VwG0}>3T4(-BZw3KA9y$h=9p&9g*lJK^bVwlEBXLTzN`n<@m-}=3 zg>JDa4X1ODR{3qTV6A6S9NG)rW9c9CWpHbB?+%zxf}t)DvnXr5C#_aX1(=_kN|&MG zu^5H62s(LYYa=k0q+SlRk-^h}dd*sjCv@+li>xtBcf_j)LaX>%!?jmv=5D#&Mj-aDJ7wx?g~m`&BuTb@0n} zLyyj&PQECiy~T-81u$?K!Mp+3n-}wmdl9JC)|iIJmSH>QS7Ov7DfqlpP(3-$7vzBp zh;Q(4Ksih;>O%Mxp`yU>9WxsoP*bPv7H7Q#FlM~ycZcHHnx)sat*!i2G(?u7&;OF2 z?UrEKYwwE!t7Yd;(Awu@`B$|M**{Qi4xP7vmoRMJqpgh0pd}9ltW5LO%zU>rXdTip z0k~Z7l;?J^{*gC$;?mAR%_HFvC4z?SfG|X9^;=9A=f~Q;#R1Ce>R#DBsgvUeFr-y{ z{c3A1CDQ&(_^=;4Jru{$%B{>o1NiD`xq-xt0h7D3^utLq&obkFgl-tQv$5&(H^T?Z zH~;YDNB%jQb`Msb!$P4yN1AHZf0(_#LHz%gP0;e?!s=uHz~0C6{$TlHxZGtCapJ(d zaS_W3dQ&p;;{hasCIUgp{ZB1H_n)L{XWKT^*D38w6{3NV`xT6upfpOM(?KWue>w^D5A!Tz25KPNe2z`- zar=H*jxj~P3yA=6<-CsEiX-!&lg!p=AqR{fQ78!C$-X-p@8=oVGql~r{-O1pGJh7* zw!Y-zWE+OkwM5r_Q zL8sUUTf@}{<$3QFU;lqgSS?iqE!M>kQH@zP1|2V$>x<`1i}@`$l_fDdVfUSqXLBA| z_6CAaNN2acwpacQo~zCh`d8Gp_iFM!ki#_V2|b)q&tcN(XEpaS=bKr3CNK(tb0n)h z@LsNQVUyv8xi%Z(w51W=!c%8=(!QO4got&|2wgIdaZ@9KZ>Mg#8EST0={7dDE#W6+ zw@HQ!ACoUHvo=~=Z{Ew*Df{zFF5<9OrnOh8##BN^Xr9O<`@F)khiNhf%Lz(T2uNy7 z6f5hTB^qythPCW>Ki`qrxlDs5gzS%Cobo3B=$fuNX?}2=;=T*iYrW|*;SZ5&E z!U5b_@O9GrU2Gei>a$Ijt-O^oU}%LE`NEWnIv~2s7zPfiN-Y;A89O!?SU|q4l_=-1u`7g?!6XN&c#(!;X z%I}iX81${qN=C>ms>SCO(n&p^9@gC>#q19RLT_C!?eoFUmfM=XP@6n$p@9s4*w^*b zn8Um!?hS!g+x~p8yx%fdf-I7{TzFf3j2{XB+0qQ0|OHS08Su9E6G2aZwL{rNb zeE1d76>IhNpkzwfE)^J)i<1;&dSeaT^a~PXQ_7R~9BGaZ2hR7gvQf|=W~4c`U-wQi zz6xWjLvlZf2@(@h@n-}oW;CspH{|4!|94b{?QP(R97s-!;n@O^&^hu+>@LXU2iOWJ$7=iD8hUEMuzpWd9x z6d)x2A2)9eop}{tzz1}{i9~`_wnsAH}p3cIRQig)Kue|f$6`*_xNq=KYtv%Wa-GUM>?3*A3KW;g8vzd&-xr9?qwZKx#?-!sf&$$Fn`-?aYE^1|v;IufEC4-7T5n??|H%r4@WCA@7yQmp(1qbsXp;fRxDn)f{G$^%N8ezdn z&Z=KBR0bi&W8!;7aw45aAdBUg-X_Jk`+fjzLq=szC@HXUfTbdXAlVC>UIar0(AE*y?9x6h;GGLBNU4~s6?J6)>f9kUfAI_ z3%&M)WBv5p{wSoT^| zv^q?(UZU7CwN)kaudQ};EaGO;YiLhuVGG|f!h*9L8lor>BBMIZI<hqE?hym1&Wvcsli(=m^$GTMF?@W{^{I_X=`Rs?Q+xbGyz8!$b|x`)yx`F>&Eyno zMz9#me1))+&2gEBEz@V{Gba5cVe9F9Tc}%`82Mj+AAha!nFm--tng>Jr;b3YFUbS0 zsU$Yr8*Ax=HrqZ6VQ}l9@%RRNJ>pPaK3HdGmZKfx$>E~`HgkECTf@~5d5_`J3_jxW zMHpFYnzJc*rjryatAyv43UEb#9LTQ0{48e?i~FJSTIQz0od85#j^FS?mpAfaf=`|e zu$R*N$K+_Rz3y7@+x{#dR!*P%2ewG;4{_2!(W7d-C)tMZ_Lg@Er@v{k0wZbco}yC> z>a|h@^oJgEVo%shT6OSmXQrV38j-rIg$MF#WLUz&0TEB5fLFq_gjln!ni}mTh%L0I zBu_XK+7G0CuP~-&?(oW`-xS(e=UKcV$h!$>IjyzTeiVK1Frjy{r#fnIT!gYRE@zlwgO(-DAdf}V>RLk;|2;x* zUrd-H({(%c``Dm{g zH7y5W`D2XR>Drg0jGzO_{IS@rbb^b~*p>s>{4v|D^!4*m+m?g0|K9#*KOaSIIY?q` z^BfZ$zUj0Y#RJ}=VJXwa?xRG6X^uqeGS~YutGG8iYAR51mE#UB;n`&Y)L^em0as}2RQsgw$Css!UzHdG{k}CG49`sqJwI83$tSHDyY8C zd%#|$z^+g~l}xGh`XWQUTy`B+chmWK9tey=B5beEplFTwOB7DmiCfFDn=sPq__F#C z7??~BnleyaV-K7LY-U9bPsh=*u0vWNpa(*`E5^UQ;{u5EBW2q6>A|Bxz(n3+1!yIUf0nZYO6!~ggdWM`o0@4-x|)Dh+T9DOF5Za8pmdvcon(( zmZ9y3N|ou2ZkN~g84TY-nnwQl-u1@t{etPQo*SWKddR7|_Y?qS#3tYXg43(N~OTeYC zjQ#??{t3UgonZZh&R@eN6`Y>mr*8ka6Pb(*wc9y+tDNjDy5<~-Z5$$NpnXj+a~ysl z#M11+D(H?yCO04WZnH8&8-6caK7+6Q)bKlBU~v`3^-Nh6^UR%gbMU-CVH|i2m_p3-;}O{5 z`Nis~kNHtZ+mGm+bESWLngG^U_I`LdV!^)E#oK0N+eLIqXY+M3tE%Y7KlJF{s*aqd zXo%{j$@|j7axe+R8+6+_r~YS++>Pt1QjnhbwDF7L=uM}7$Nrq4`4mCi=AFTK-XU{C zP`^HZTQISJXNvDD;Ss7A{HN-n&X$_PP$BF;B8V{EExy=-=j(?%k3NnOkG|$VM+PSx z^6X|NJAf}DBZ|0zaoLr1%7%+@8;74w&6c`RMjX`G-Xt625{V}?lADP|vnPVfPu~Zo z)U!Ho5IazwCbzs%>zt9w7lx7H;d}<#f~O=&RS=A zDEJX_Y_ti~@Da03@Kb-slQ*6r4dbynhqk<~s)6k`7NOvl2LLx%Hm*%G58??Tn6Wpq z+6iYA)FR3KZ)^&OTK58d0S4LeT&~W1_)o<`G;vR%BF=Fa_94x$;Y3B= z(sUeidu=DtUE9h1Oo^cqSwilArw^3ln_SeKEH>J3Iw)RlMLQO|$d-aZ9}g*jt8#R* zQfM@AkywVZ4oj&Va6~j6HRhhfR{S^Z^pvT&1E6sK4bDBQ^3?~SZ2R_A$2cR;qo(Z7 zpJc?Qi_SxTe2ryRJQzwe#15)53Ugcj{0wYrR0f2-uqDlE6k>Klg22w^ZSRn0yHcwm zabs7^Dt*?b*daAQgwY*dKTYg`vGv-gGY6imN;%090+}Be9Hlgh)N+4~Q7w5pN z@u$ZS>zc@(%o?Qfy)M6H%>VH08S(#M1>|Td+84E>`!V$xVS!1j+!EuhOo@u573DSC z5yJKnrsv1k0wY$SL)MgV8j_a5r8PeS^dsPn z;=KD%fBUO5ltG6Ekn$T`jK)TQOI?6RB>-HZOO5WZ&O7*Eu~?ee(6#7;KEy{V**^~ot%N?^EJFZ2 zA1_S)fcFaMi_r7?#2Sgv?ZHy@drdds0?O3hHLGG62z(Td{!!%Lw_H}||8YB_ufLGr z)BT}0-oIJrm>$Xj6|I(*Cr>ma{Qe%7e{cW+K%ZZRR`j6I`>w|U9dD;bP|-Hp9)cm> zzkdc12m1^0Dx*dG$d6P&O*vZK^fP-P4|DfacS$JC+1q;cC_8tyV&jx@JxT3BR6+`x zDDFXKLJnFO2N++rH`beUFpi|TF0~K9_B5az62H{$R>L3M3>{W?Z;02>PRS0vGuD5; zAfm&rP8l$t{$hkms=k7XPb8_+Df=HK)E8^p(_*i>KQH(jDdh^yihx0aee4>WX|!;h zJ`8qYT0GBHYFt0;%{Vm~%H3C^#NVwl>LG_es!KS>;F)lD77eZp8PuHp(LLfQs!|=z zP-^SjboGr5RA<#Z%#7GKV1+=3F^uJd4ZGyl=0%SGemxShAi3dU^BTGu7UlqTZJQ<; zWx5j5>X_^p!v@Tay`#svu^+q#N}0|tjwUZ2)%?grhq^#wwfcTxPfKn?;?eUi=?Glq3XRJGi5wmuN!*0kGT+}f!= z(lGiq|A^fdfej^?u2_Q8g82PYt>cFF65=?cwni%0hK;P`D(iiow3%D<^2?1LDiTSU zrU?Dya1FQ}f{zVwM){|{LRaKVZ~eMnZ}1r>kGB3@Zs34$=oplFA=m2}J;??N?P!xN@=(Bor#I<=1#eZ?Mh*xJLS)r z&!DSJ^h04uk3LnSj8EuZHo~slFs;MxRr#;4k`sKSzN&^HdzOQ~l}lzl zRta9KA^GpOk<8TlS3+ZS!Sn9<8zF_PEZIgb3(vjJjTZCvbP3pc|TM$&Jl(y!)3 z*rgAjMk+)T8`fT|J04FwjrU;QCJFaOz5qZuaoup>q{E6#!%3e>ZhT6efmx}X#nODr zU)-`^ybI&bZIab=rzF|rLe9;obKRU12P<-2xx?4$;8P52t^Mt+w->4gH;fRQ8O5pz z3h`sw&aG=YxX0&W5059Enm)x%Z@Bo)ggO7yW|AF~nU@NCXRkZpLtKCjCH+k?6JO5> zO{4#gH>{Fg@14^hqwOlBrs2%!X!>?bhw?7iw2je7GiyCfkM8Q%plTVW<219OQa>4v zVzd03DU6pM^g61?zp;Ma3aZgHwx77X_0(z*^Z)j7u0{8E@JX;0aK71gxLqq`uoO*U zAIAE4Ti6Wlf767qaRvzhmmhDrjT$h1iC>(<>!7`#|2j@V@;zCuj;#KR^m|rP7v2o9O}SEhapsZ4es3jy9&AloB@a6YgJ=MJtC;O5_qzl7@eK|ko&?TlgSPs0 zP^AXm`Aofg!0_A7FSwBBACTv(%#m9^{q)q^c9Y9Dmu+IyUmJqkQVymv#gt=TOz*-cjU1vKn|_lf zi1bnw>HQ>+%yCQuB6L({81Txz^PO=(x-oi6dnAN7`$g`T%^;7!Jp=ZiICU0ifxc~n zGF?Uasc)nYz9nEudj&+#m&@+$`1>FsHDg30PPZ8&P6(X`=&`GcRb+XL7nDk7?CAf3 zWOY_f{ov=?Y^c#(^X<%t^IbTs37q`4v%Uqzqg$LIfuvp?ip&I1ZF$_lPY1<5V|RT< zwgkf|96k74ajF>>5Zp5APmDQik7f7|=xyAt8KnNos(B_o;@Ul;Ki9Yz-_%LW;@dh& z2|oH1%X#PD+I^tg-9_@{D0m7Zr-Q)xQZ(0+#9Wk%hU8UJU=qmAo5RYUe%K5DQ^HHX z#0DVM;HKTp$TuDQvNdC*U9McdI^XliiL{(?W;ILyiOU@kXMN#n>Nv}gC>sj*@qTWe z)~&CiBWeBj0URdh5f(BtBz6QSC^|Eg2T6=$58%~pG!6y4USi+HT2C*yAed~CMhNQ=7dxgdCopiRbdgwsCnS(p*EP=Y6bWST6_-}FfckNAkNL{XzmkBVN2rR zoriVOir?hV6`bi7^LF7o=C<1ed!L_sS20^hW&M_d+_%yUj&O{i;Yd%l%sPNS^-41U zi=5qY2W-q=f!;eaTX|zZZ6KTL<3rrhv9k9-s~LGi+$O;qyB4z93LBhtX&RFM%qz)> zO+VrKa=&F=H%CvrCHD#hNy=Uebtb+4?#&z50(qO+2dDmBcH-yr&U&AOf8p=pZbhFs zRoe#qsaSqN0E|>?Ny7U5D?xtjY4g1t3g?kjH}S4K)03CdIznPFfJBhs*0mtNrp|@x zLLmS65>#XD+ZA$_3Alvo_6s_zsDoXG>iI>T)#^#Qww@kUTHQj88G6oqiiuV1X2Onl z+2W^SGz4R=4xLblC0&v_=6~Vr^A7EDBPbJ^Csyc6G!fvLAcj!?M&qc^VBwzV&kT!wZ+ zu@YBNy0OC0Sio;goVXYaZ16-<_v>cRue^*wMQZAPscp zET8GHZ-nfH&BO2dh<>N;#{n(A1xGL(jh9TBw9;f;ZK&?3ZB1^+i8sBd3_*c0oh4we zLIS~P3jyqdo{hxK=gLyAK&n?4 zsX|w6O+mA9CH^isv(YV!`ic~JHP@T-&-v~*Ao}aOr{}kL2;jqw3PN0$HwZ4H_q<=< zoZl~MeSJMiCjkSd5A@Z|74k`jNC5r-z<~R~{Ql-DsO&b~etTrjril+n!M*2QvnT%c zy>kr|3T3x}!O73wriFH6#47;&o?pWS_Fxde4g3HizQrH*q1e2?Ti+HOw+AbjZ`bzp z6dNm@?e0_4H<|vo?3XYBu?0hGC*A9a>$KZ;IU~U7|AG8G9enBL@&1Ck{@wT~oA*zZ z#3LU~NaPbJ^xEzFH3r$^>Dhbb%4p&?^H(TblLh2& z9g*tdg0jbu4>=Bb!L&8#muqSC)#I*GTq}M*=`6i1w#UOa98F_&y+8DVAe1ibyE_*D z)_v>$(awZ|t`EXX%&&E`>`VK7xDbVp9?HgpC1B^cd|>(4q-V6Xw!$4*2;jY(*>^Vz zQSOj1fQIKpqZ04Ahsqk(1xs2Ist5iXDht?RzDC|fJxOVmJ@<(3?-HAy{){@K1!!FH+EaMr$?6d1a466c`7Z1J-;&F=U`4tsEm zwr$vfyLzLe>q^@@M{aViJ)0`dsB}I@tyEOMrrf4fp z;X-H;ZL!wtV>=p?mfOpXF2ZTFPyb!Gn*8>h9c{QkJ#0eE_?Ik*nxaEnHA2v6zFE4D zgEzx&YEG#Qt42Xr3Z15N`w^Uh3zyhj9rO6>LjCJIT||E>HO#P*efag>;x?aM);pXL z;oci=avmv+!?&ni^;PBM8Ljofx6qroGBPK@vwzX#*1LL@ZVA9+7pcXrME+{!$#7t7 z1989e-z9cKlZF~wKnZVlkf1I6a4SdIPkl7+bZif`gSNSn_B`e<9S+9FN=kP)UMF&k zw>wUD13JbhYANGHVI7vY)7Ou*^7|(xS{TR3gfK=30=xWd$Klbe>o4Ni?CTnc2Y;HJ zBPgsG<$voJowwMC__W1rjISM93*8Svy+++)9*ld&0139s*0WRif4QkO;mQoEVKQA= z#?aba9Y(TH)?rul)|Xo&wEd?YY}&&rOlaw!fBx>f|C=i?aafuVtx-n+wpc@UW`^5> z^B)g0W&3}eeRWVALGx&YKyU~NZV8qIcZUE05x2LXaxa6c?aaCZ%GIEOnN ze)s_g9EU!>-}l$6_x^dWYNx7aTDG^UyLYE&wrAXmm1^8M#+j?=4=0uGQWICdNP6ig zx0?Z;yuMVVT8%fx{7bdF?_)jhe<{ew-IqrQ|Ag38-BB;fy}LFqm)35nW*28&{4W37 zMU*Ny_x%sXrA1?kF@`U}MDcn0Z$b~p;}egaj@}xJk*@~BJ=!kbMXIew4J|ahlocwf zDfi9W7W=g?x2hEvaiJ4*$jCHgDPz(+p|E%&7SUc_^*&8_`-`2-%U-u*xe?Pzz}UCs zw;C)pEq$rjI(>OW@>U-fWv{F)WGh%@mJ*ylHzvOicMVjE_h%=8cgB51XAhX4A zmZvqp!>ss$v+4jGg@s?no9qbTDQ=P@jvx3##8jR8`)KB5DS|+9o*ed z*7DM}3u$@#B=bfqo9Qx~+?2FRaMN)!1(9Bq*xgzM={U-8ov|O(=b>S$9JV4AK^U?I zOTgm!P5FDDBJ?U_w0|G$iJt#Bzq2&px>13xlax4~WTQqlpOo$>4Otz`nO-vah=Q}J z<+G+Xi(Or)-BqIVpWAxNKLWA&Shn80F|-xi;^><#q5Vu+`7D2;|7j?l?>k$JhuBF2 z)<=WkM^kf4+W3vy@xP|xrx>>f`@}X&v_7doduNR7<8Z++zZ2E~^83E{f#)T9pXnuW zz5uTDgGbl96=hLPe&!3Pfi&$){xdiO!f(^t1^qU-1|^bhok{ zcc?@ZF>Ga2Is=mGf^Lq!I19}^DJz3P!+Em-j^H&K~$$U&Dhz296+8C7y zOkO$BIc9j}jbg_A8sVkYM#@)?jx&0)xB5ruhOfk)S6%4OyXcP{ic8?y@yXX0%hHQpS623z#q{9Ll#L(xCGuj$nc@euMrSn~tO^+@&{3?+x0DE*YI-mr_g)wT`7#!WV%p9DL>+Xvq=ZKZO(nOjUkyy@nL#dr znR@-83CP?BxFP2M~XrCsno-TpSr!Ouu2BAv5xTIz>93Y z`&ieTp+q|Q(%;xfziyF>tQuV!))Aqn9wKjvesRewQ_{)7v~ND=_)fDA2M;HA*iHuw zLENbG0v1)j`Sp3)s8&Z4HWg(~Wg7jiuOTy_Q!1^7hUJd(Ia}tL;YrMSlZh2XEAyrw zUZhFmsdy#5WZG zY`l7Y5`>U3T)bSeo!b%Y#ZJ;Rdv1vA6iC*!y6CsvS)!<&TaC)iGN?Sb(~3Rd3I5XH zp^y~2gnB|jH!wG^E=Dfjm@RLA_y<`QBa?sY?rYF^NnTcmzagGwCR??N2v)&FvhE8I z1df}!&T$`By26&H-i&zjS294CuQYB9BpE`YcT%nCXHJ09-#pVruk=1Pqa#aJB{}U& zP_27yhsQ7I4u;p>jQ}TSuXp$>@E^v0SZ^KTff7Ffo$>Gj$@53Q;hFv%>@&U{zml1e zucOl6naURqF3HSrEjDqgj5Ma1+WA&Cti}m#e!pY%8Qx(s^?6tqVYt~$Iijj3=q)I* zgv%wqWUjR+8v2TScEru6bTP=|Mznv07|=k0t9P-QAf%*eWRB zKYl~_N&DsNsuw%U|BhS&e1YjduV;bZT&hf;Oqy_oD&;`J*-7*5DNxG#WIMVc(Y2B= z4doZJ?`lVXu*zjy#nltj3Fe+}4#@$e-rpaV*AnyycNwr)pRl*x7P!I;B=`1dy*b{S zu{J`L8#a}Bdb3Ho+DN9r!Ho7mzUF_qwj)_WSatTSDV>2G?|L3w#6tUA#}O^FjwHC4 zn_Sma*HILqzDJ|i=5#%?<()+JGwwf{T zJgw~ZD;St&D%F@cyc^|q)SP2K;s7FUeqI*Pg_(u^g%#W$_LNuRkd}70rzZ$vT^&X^ z1}d(VRQ7GouaO{Od5x9pg#}U>>#Zz20+%R?H)6e)mD>az8$KV=F*`0lSiyiFN;L&n zzq*~v?CbI>9h2;>5OJJbbf-LQ;WtSmig*YmH=f;)nYT0Iq`MArF#7z?V7$f8qCw3n zGHQ7eKCpN_pI3kX>rW-RC{vyLTxGak=0v!Q;<<~fTf1i2TDJN_P?PuCR6CO8H9C`- zgQqH%01&)fdz`H}ff_+dl*lQG-mk91>)EqSc|)zN-8!BJRC>p6mHXK$eWhlyTEDkh z<*g(fBT(#G1g6x(Z82w?p}q^h=-Y-T2{3KAlZv&<$9|ZkFcZA0vqKQh|6GR>?PEi( z*+!YOoVhs7l|rC`~FV zyjqf=si0B*bL`&H?tOF`^ket!wwwf~01?@ygMrwoZlpi89A1n(%{~*;RY-%?_Zce% z+v6M`xd%H_ZApg`SSrd5n4?@l9g*JxnT69wr%qi*FCrEkB%pwML~*Pgyqo&mX!LW5 zAI!&3gPS=AEZp^_yGde7&;xaw7vx3EC8U~#ak|lk=1PmJC~u#%94LBuJ?-*QuY>&b zpp45ah0(K%@(dT?n(5VXn#wWS1Su91inWC7&4E!i$78kMrXgR8*qR3mF1+~udetxk z_y3t;V8c!x5c`E`|qZRDAQ zn|U8wMHPW8RX&xbe(rtJ%6H8J>PB&ro2I;HBUY>rQS`B(*8@@xAE7Y})%Ee+2<&t; zxfhGF2Ca(s&Y^AnA7R4imZhyc?QF)Z+NqYKE(%R|Lj#T{6Pn=d4c%=}v@SeoI472K zR1cnme>D4!DN!h_>PZkQf%VbxCWh&W1yj^r-d(*nL@QgD$;;Axr7z{-GlblAzZMyK z$wl56C5F?mo_=iv`94Z<$Rg@OtKI3(cbo=0I-f0Xu1?rrwgC!B_JBp|^@fec4Y6*h z45S@qTYLzMCj0}%LhmuLI~yl~TYq&r_d3g0Ubu>Rq@BB~QKHC0V8dkaB5Z?O+8 z`tphJPmnPGqxAy0cjtXcfUDM0%lX+lOJ13d@(R=D#+#u_ z?rGH;%8LpHab*wZzY+&nN$j_V`(#nPX3$A+vsun!L(=xotP0vZO-sS-pA#)IU9=8u zw7#JCx( z{x~MzHr%*>p60Q5;Y@W_L{C+FsmVjNrniWQxy~F2JNAw-kCqCpPzQK4-IyY8Enaep z4=aZb_j?!$!&5B9pedk^6c6xJ5d04^lUhub(-$obN+AhTT_@YwFxaD2wJ=`7QFV8! z2siYFZMl0@7VaR{?0Ox`ITQ+TYXO~yyJwPXKQgNEz@)L}pM;+X9|cX>#eJT| zzVaJnFm++rDJPtiFL+H(cxc8vy2^H~WGhOk&8~Gp?a~^pj%8oZh7xf^i}S24U5k-S z@B@N|MN#fX_ypF%bvuoFMR(}THpf{YE{IozD*B%8|B`x~HuQJQ7?`~mMZbRe(Xecp z#>5)~P^M7rY*;x<#QRaDv4wT(Q-o-YvrhVGN%p zG3lZe1DPf{6S*N2hNps7x7|iW?;26F#H=SD8Vu3ca-xmF$8ufc8sT_X} zX>iQj4Os$|#QLU00gT|rRQoLy^Wl?J`vi_0^CxG|+@dMoQ^d?}&!Ymd1g0H1j0rYv zJ(Ry57yfj@{%V*~SOBL;?pMf%>sG}$Tj}U=S6p-xw#Dz!j%d!LD1fZ52Uc#b;>I>- zt%~07oNj`MLsZ(DtYTwbDH}7Prgtcl(_OZWD#4I?y(||U$PY6*``a%Fx=kojOAHHJ z7Ekh*%Dnz=%G{>SLjs-~bD`pLf4?t|%P+A{zz~FPPkp}6agXe}Scr5sEr-vci(8hF zdde%RqfZ7I@$g4CDe`$V*-^&q)M zvwJ+bPA4gN)Hp!{a|^1u`Pk z6(3Dkrqbs4IBd_9ZMI_`Xm;3}A?QK$}q16pp!reBJ2UY47P;qERP3s*nwv~=6+ z|6yBscr7JHbuFVqzJ@=Gz3~^`59Ze=d>*7`X|&URF=^%ZbAyr~b z#h)9=`C|p2p&TCrUpS%m^<7x_DlR2Sn-9X44_fiFT}gDFKcsWOwTU*3*^Q8_V-hW9 zW4GIh=vY39umd7(v&RxO=mW+PF#`ho0PZ*-sIrjJb-(5&VHrZWIGt z;?IsvcB%=sel9HcA(RiWmbs&{j3e0}X|jBmFYmuvv9d*8p_CzWzETGAr<=LR1Dsy%fY1$YVJhBQ?u$kk&GeErqBTfkiQ_LZ#~>LI^R$W?eCBTp;|aU-dHk0Ig9 z0-R-}=v@kHN=qBxjku|(3O=#7Y=4H^Y=`4oG8=MgjJ647vB_+D{;;{`_U?PG^7!^R zCh23|(kEG)BbX|W?m3|m+E47vlIe3e)2ss4)ki^-V`*XDv1g7yxGq{CVE(PHlCVyL zv0%KYr_A97^PW>#X&j%|Pc!BZR+SZ14{xH}t;__Fuqb>)1(i&&V7c9MR?easghNZ- zm@eV54uSxyABJz-i2!i- z(Diw4kEg$|vu89al_jOuw0$^UyZh=b5WQ@kl zU~nvr+%R=+5~(8|R)|PUvfs|FT+BalS*E$9@tiGw?Oo6xA4GjKa1LpX?64T|I}Lgz z4O^MSl0GLFAK-m`hPSPKyDAQF1R3B`VW@ZdR{0mrdJSI)BBv(AZ_tE#{n`XKFFw3< z4OX6F?QkoggWd{}6NZYqu0Uy$pxS26D)_?Y{hc$JPu(4|comM1;kdc3FBiITqvk2u zJv;inD(?-@?$~knE-lg4fA{3l6h}ttD-DJ`ZSYCeiDg;>jJ9>+v`r7*+$}&H7juaKnhA1aXyeHaxe{V1*N9fGeM&Tnf(ZhcJZ;#kp)f%Th z#>anX_ft~4FCngPXCEy=Wgld|(em_%JnfE{qjjPkPp+3Lo^5+BU92N>b$>|Db^43? znC%zN)Z_^nCQhdw?=C3RXNB&&WAWcVL|0n{n4Rg7U0uB>YrnyrlFvHJqsJ|(P3zos zMPKlbe+=!&Zj#-p8Q!QWnz?ue1Obl#uJKaykSfTsUuU>zd&l8kE?2BEAs1wdkm!Iz zl5g;i-t^@_UrREe`Ip{Wgc@PwRoI2oU>VaY^#Qwh_j7}(5xOK2sJ^t5SQoUIb>BEj z_-O`yu3`oS(c0+^cpaNg6COe^v`i=s3+>e5SKV5ps=AvzdH&MV)^RyYXZjOJVqdYk zc6epl+yOFVBu9ozy6S7E7Xy(w{8mJJ&=!n;u1k;l0TId10h0T0AMU743*>e*RSGd( zVJqd$fWC7k*L;k@Ip%!EX?~sO3G1ys0W|kFv*9~RvxuSuS&B0V8t068bG+*V!-)ww z12eFx+TUDr%kf1EZeSUcyW!5J8lLIRojhx()sI>D@=$=sDH6E{lD~>->g2VYBN8~n z^Cfu6Xat}CVYU?YF2qvpM+=<<-`QbM)OOu*M8%gqz2R7JSh%}n@NM(?zWBxP#E8BR zNoPr}25=3h<0Z!@sP%~0g8Dj&Ugq4`>wvU5pmR%uIi;nkM5&Dm(*4Zx%xIUX_|%TiZ}?Ft#Mh{=SecIVJhwB-)PE;w^%py6@h6${ z*Q1p;W17zRv*5w{AkIH(iojd?EBrWx>lcfc_|x5r442VQMp`dhXU*+i`rRB-MjJot z_x@}s*BqwFdU@Xmv~4$vQw9c5x(W(BjrQ1>3v(apvo!j+`~&A+0uaj{_Rfw^efv&z zbLJ*eg#`X?z8J5>_SO#TnYwdV_%oqz+p1p}bPm;TmEiioptuib?6MP_8~SHKKt+{x zsxr}n0gCh%F*HF(+8dbCmVV8;{s9!lS2VR@k$F>FpU3BK1SCXg97>=rx1|4FWT`!<2BPx8>6h)ggS(=ogK^9o_Agd~>B&WLM)H zdbN{2FH;E_p4p0+SHk8xLmMVjy|(}8Q9&SsL^_~N{25!YCT74JsvfUbN)8-y=jB^B z)u-D*PwRh~R6D1Xo-QLf6`Beo@AfoqYBL(0Is4#=h3_kIcK*mhzh(ft_X=<@5&hHT z&&VgE-r_Jjul#|ib&Xr%X>!dcOp_CkuSTucFw5cv143Gu`K+h6$0EA56FNn%Bj{!e zF9{!8qwQ3?a3E}vK;Joc3LRNaJ*M?88PqB_O7Hne5gcG`!FlfXG#S(~y1)XLz5AUn zDZbr!t`7C~R;>$N`KycCzV0zL3}mUnlIf@AiE_;Hy1!w!JHBlQ>w#r?-!}IxmXl6t zWk0y-QBLjHAF0}JSHU7K^Z3I~;rpx4T`}!PDa!arVFYyzyg!|t=S?GToB${NsWPLq zq{th2O4lm~ZvS69VCPq3Wa}UUu`{mne&!h+Un{!~8rxa3d>gw4-iG;@qd7CI867LD zvId$Pw*JX1^yHC_9yCP@Ss;qk?B7|cwiMS&s}%V!WfHo?to~?z6gW5r9Q0uO3s)>b z$7ekbB9C-xX-h}6Y4q*-FAu7RfHT#L9*344dt<<zPua z9+)&xtMTsK`>PvdKdkcqm5uK9|A%e!91p#Tn3EdIVGs|B*}@Y!9u@0Q&#Xs&1mG&c$Ez#|CPJ+`El%vQ}B zCrC>GEQUgHLs}9p?a*wWLZCPw6 za6|8cyi-F&eiiJQ{418YCWzJgX-fnztHDr~#>ON=lSW^+gQHWk3}Xy+H}RVk&8A;M z8XLRB)GPIhHQllVDMEf2{hmjrikVqLx?d<>jPb3XTvr$hG-Zm$^~%aS#Rc}DO1t6M z?qO6sHX@c^sIvP54wm3Yy?#rt$lh{bjqz=sfv9uC7*qme!_`asZ%OT!{-O4!0f$>PgaMRSAEM!84lW7f^0A;ctnku$BJ<`O`tto{M zFOLuEcri8<8+_dc7jX%9eg0`3!}?Km5@WMv9<^+eyLT>)T+`(o0OeAuckOXm7VaK2 zlki;G_|3A8B;6*&vvt$BBFEji9{3<6OW3xeVcx{mg&Jia0{HpiU~^C9zrBS`g|BDb zuI#dO65>54eU#sU^Nr|qNxsb`uBE?fW*!la=KghD`GMHBrY~Kn?5{Aa_>>{eH)A}o ziJ&z)VxZYRoeogx&Qve?oI^TOH&xzgM?&SwRXPI0**lJ|dmBq=%RZiz+S$W|u6yA| zXdU`e+(zzi3cj8od0D%WjU0_alw$ke1u8#7lTR9U&hd`{W5g1 zCIg%>2vw||$YL7MFq@4Y6;U1t?)27G9vN?em+Bl_^s>3i|N2dyccc^ApIZblS!Y|< z!KMhZNsf38)ooc!TZK&-y3RTvYo(_Y_J*4g&^6I-x&$-9zM|vgKz`W|QLc+KOJPOGQy)d<_#;x+q1-}bWeLUll& z_;+^nXSc{~FOq4^lVYs#Lu0N=y@QIa#F}dY7qdc%|tJtW)NqM#G+MQ;0Q?X$;F!+j0DvG4Z4EPNR zU`7Juu%>4)*~2W#3v~p3{3S25<}o30oq1dwE5|H{)Y56S3K7^2|1rYTi_M-d>NaB_ zs4Q)2gIGMD45`Oo9Bue@@R2~oEL`#EX;PD={y+COWRH$X(A3Mn^r`}}$h5F_MrsSy zZ@*mk)?yD+o=2*f*qh5{|jc@0C?~=N$c5#Qh@y z@^_ci-z)_K*Ri03k7H#{(F|0lceY_p}GcQ>|9w6Z) zn|{;vhS4lEn{GMG;yjUQ*Dp+|Mn1%!Fc#dO8HMx1k;GD_p-Gt>!6xe%H^_>KV5(-^mo4Ub~hZm8F8t+j)}c zKCJR{sW%s5%uc8J#^3Q5m@2dJ2m#cRlYRuVwni5->_*I&( zqe_q9SVe>Xynca#5@p}$y4By|ZNAp!VRo>Kb&q)$S=Nx9pUI57c?P-EvHegpIdfT? zsct^FTvaVT>l;yKUVkUH_ga^{yb0*fOLnol6BU-VcwUP54*N=1X9CiJ|J(~^8wjdr zy9GP!my%d~OH2ym{p&K)S6`+yG^CQ0^eH#A=A9sMO%83bg|lwwsk%kMIA$(eP28g{ z8bf)UzmxLHmX(9q@&?|0Cl%Ht{cF!@Q4mq4F{EHbZ)@iJ&YUTt?DLR+)h2k=9j+6aU zmeBm7=64Ze<^PTff5#eEqq6g;rK-Sk9!}$QDS~$*$_$2vRChjrWpd6E)Ahj{ z@Q{p-bqugHdt#X0?oeTTQQMBSVP$4-xjl$+wqMKb1}rf>UIg#e*s&>26Y%bANYE># z5!K$U$Q8hlninlb6LkWN8Q$3^I@l#n3zQs8CtTH)M+yqmGztVt*tkMZUsFvexd~0m zp<|*O_^-bTES_UfQO(q6WAluX&3{?-eIl$e@b^GsSL)vGMR;aeP||2h8)^L-Gv;uD*?SHJGq zD@zzW?!{P)Osj#*2%)Wr|*g3X+kv3w2!+JBL5zjV{UqVRL7)LFEMUf#6@4m2L9^-^kuGI%(n)eA}FB*JpNUcJgR%8 zPCkhaW1QTlhdG`z3sQ(x5HH|ra)){KYmt|S+Q%^hmw8@yCr%@ehE-&OjQWcA!v^v~ zz;Da$_6MTvm2gUkYmmgjQS$iA^|B?dA#2@zK2p_d_86VVFv|<-^lc!VPY+upH2Bxe zi_R>3Z0wEL0k4(9*F0|ig3xY4_g@_yv*~iKGGC9gxT9G-yL^IFm9shhN`NGCEdKM?fj6r^??#WQY zqa_T`>shl+iUeX;Sa=(X0GbN)oJ5PS?GpPrP!?n$eZibL*ai0U!zo$$FSy(8B-}gT zZC&t&4f*}FfJxQGr0m1YmFE)lZv2_TXPpv8YGp;6Z7~1iMAHY==G_N0cJotTuG@?+ zeV^#6O&g-bnblZVAFRJs)naRv!HP zP_bvN4-fIMJ4`<~20BYdM!SVO6k7-hfq+eAtiZ_1u# z7{$@uE>UdtUKy76%Mm>g_-#JzR$GLR?+&%x4;z0f3`%jP;?8hQ253wXo_CXF;SqS@ z3wv^1NfYdQi)p8Zx;pP@d|5C(DHVY8S$2ltMicCCOQ^nZ?Q$*7`8I(Z^uKpMzrz$L zy7vEZ&)MN?{;nTxs}|C5oM>U!N6T^9z4YkJe_H;Q*$Ra>?Z1HwLaL9#qr#H~w zvu$rNF3jF-T+A;grk?>|zws(Xc-op4F`Yfp{4K_+IKm1`H={8FoUyIOiilFBpA0*# zTVeBe1pYb;zpV zGzCvvY4|q4KnoVUCxD$hP;^q6#7D^iq~(Ob{gH?Jn$$I=%{miEq1Mb0)mrpb4M`tT zPq++htW$p|*2n@mwS%YnaP#3VP5_BNnr209m)lRQ}AylfSg2l~Y9# zwp#=F2`lHDb4pblsYf|Cqe4`3I}fM4{AOBPaNvpI$kUR!@cd!H;d@&j6!KtCOn;TV z_Q;Le?CMVZ4kYv^XpoLB8yX>SbAEA_3xgKJvO_kO>u#=<{V66FczpTsec`9R5`98a zx0RViQ>C3enVuwZjr^0)_%Qv5XT+K5L1DjzgxBjE2&o8g~y+r#F!3AN(W4^jPg z%XOrT39r>gCM^jl{@fn#I(vrRYuqt*Gw|#ajHQ&cJ6QeQ zqW%a%*P_))If^D^fU8t){lhfbN;BG8NlNlTeqt9`Q`RuaX)U9qs5=@O+QB#_xz&`3 zPgB5fEO~3JAWrpy%~jx>Bqwo%kt*Y~4-x}BT*n)oJR$z8L9q-K_;e|*J* z6YBcy@oMzloUhLwq&;-bvtz1)hpcR|@6e(ltFJcY=ul1c#FuHV=!gffYT^T4nfM~6 z_K~ZACeOSj>Sk&;{(AUBbcLm=GhIG+T-KF!bAcjI9*W?h6o08uO|D*erPtAXC_nYV z@S4}>&3cg^8!-i^s4Dj=$KJ|{FlgYNCe`~Nd0u*#n}WpcnH+o5oj&QZpkHQ_aiQLn zW{5um-=$^{`9eNZof?Lz0JPg|ESM`i4*1=kbCX>{`!(_C8ELQJiJMC&deENU?K{;M zHK31V@83J2uMK8Ci#P34?x8A(TCsZQmfK1e+uZrNfJ&{@xw3#)dYJ~*>Rw57*_6I{T3)XD8 z(kj`NvSLO3lejlPw>(ITy7=tmjNupUI(!(Rn~(h69P71HW5mCNebyVB+?&0iP9J5u z-j%NiNKqSA_N9Z{Q0s&>VyCDrkj5d z-feR&HobhC+5;eDSa{`ngX{vyCu$Tkqh@Ro@a38RTZTyf_6JQN1fU<)N$N6gakAQa z9MtK(g0`Uem2wYMO!7xuAOB5MMP=p6^HE;m6yGNIzM~EAEA=ML?+@74yi+2flX-9l zV7KjfGY-5%Vu4sg>we4FY;iSt|MK%8s1!VIjdWS_?9lnJbkf&%Y=u|jr8kaze`a{^ zUE<#V=Hb;!&IAJuy(Hwjwc~56NOWocm8Da7)V%}P)Nr-irPhl;YZyI?P;1jQcrBSf zx{>lzP8BW@RUn$>vWv^jm$m3IujDMtH z&ihy|WEVTC5@Qqbs}zhr%NYHdB7^QJn%-;(gWk#-gJp$>q)*wZeE&@S20 z)!!+(jk>r+f%y1iq(GY?)mJmBLFQWfFlCQwWCoj~jF9~wS*pDX{K{&4sP%JEd-^3z zj=ii;R2Z9vR5jK3dvyVs0!{YMlYkPAL5M~AXnUd}{NuWAJF2!n$Toa=cv&_6PF;7V zK$v|{k{h^jeK%9Ep*u?;Y$~MA{&)NsQh+)uA0qI3D#UH^#Ez=wk1MwQ7j1Y`HU44U zy0ATC1AgUy<>Xc4uh+#rYSVx}hgD!>_Dh)ZYxuWol53G`x6;I82<)lft&9ZBn5xl1 z5@eB?H|B&Kv99u3tk@YI(UxNqg?1B3t%{)DKrVR zyc_nR4H8+Fzhy#)h42_2TtYU%zz1mO%YYgGlSZNw!7|NXAEACU?0+Rul{^n`_f>oR z`-j1~3EkZy4Q*u0I=U~nD0IF4CB3kTe<8w%tC9Rdk`Y%c`GqhC?rpn8cNtqMEABEQ zF7ONKS6xzTj!4aM*d%Jg!b$)Z1~;iXdR&y0b8ATR4C&6-**YIY9s8QzfSW*M${@1P z>*J&wFm+9k#*);-oekCK?ly3KL5$C%M@k5`$F`mY9 zoc~$|xg=RNoaDx*^sLmaCyDlr}%lV(3GxtZL;!S4$opTAL8bhI4n{={uz}^^STwA|6@!ip@lqU~qbiuf>sDg&N3zwTY<+MB8!A78PBwwp+~43pch{%FPx3 zv3=%VRnDMHvjkJwvF|;p?)sVbuc`!fdd72}zsd&jk9z>d%2oiUKu>Ke9HrZ}C=Jo~ zVnejI{-_>naugp8_{Eu8R^F{8>3I$CPO;!iU@SdpA&ybuE(zsc$KB46OO+&MEctK- z+!~lR+OseuxGox`um#mbHu8Z$ zO^X03ivW~GoQB0yWI~Swf!2i9i^<`Ib@I6F^FdF9?=z5U35YBjM0Nv0m4H+)kLbnu z0Oni(Heh@5tzkdzpAZ~=fD^x^X=3W>JBvDENlNMw-V8!^oZCe4ZP1{rlHGwTACFcEp4w_&A}k`jv}2V78W)lV@u`E%nq`TYg_eKwD=kb#TD6%^3EE z*O_NS2mhr(Uw3b}lJfk78DBqk47iz=q#V4EH;|DjLa7*eNHq3w;qfC|pv(SnvjTs> zlInLb{-MeGKf)5^GnPK7^Of!2{oV1@l+Fwzr=UpcA#UQizFvexcAyY1cifTbJ6jTx zwD53w*YHCpj&ElqCbzw&`!7m*u}|AKF@mV|3$$xqvruv|KsS30f1|A(aAoO6<^xJy zm3%wY4pnzy6W0AO6jts-&*kGemy$%0gy9E-(a6Xui6{4KR-P0in}MsY*(xaHUXV`L z@$k3H1ezKUTjoR66?BZLgrGs^gjl7hhM&!@rlr@>~MxO0$lx}wM)0l=ZXaG|aC!hZk5 zA+-o9szN+~2#uW;dq^uytZoNa2{}#SJfrk)qfT#5Xf2vQZte;6n9X=g7yk({jQHJ1 zC1Ftee%u$iuw!pEFei2r`mI+I*{Cpg@ROlE`+;3PgcM$_ z_r-z6+zW90x?U&z$cmkXaNm2v>TWD|8u2?Mgq*Sux0X*<oN5S4vJR1d`eRg!Wef zu`z5elCde@uMi1dTjV|MIuILPcVFYAXC4~8K>q#-CEDbj!!5K<%^frg`?TMya6J!Q$24+_yt+m*9~xj7l6d+RrmTOS;HU_SQb{>M z7Oid8OOQ)RGE9Rd6W?wo=f~GNYX1kzlb>YPl!Yz_O3myZh=&=%P}xZqpdhcRv+{s2bCbz z=Cju)IJLDZA0?s%P$pPPP! zo3*R-$AD!?|9$t+^n0at^yy`+NhOseEc?#v*#)M_GU(Ru;ke^Q=!(Wq5O34U=LQIB zrM*|I?=w;LLwn9$dxoBDaUC!C1mw}=&3kw3n7I*o{$$%d@d1fmk>Q8*yc#9)x|TU@ zz7Gmq2DBWgo;E#}E5kavKMnUw+l2+Um$GtOosXhzW?S`-E^WA;nh8^3SBfNWrbcL) zHFsIEArcJ5#-U|rBdpNkvnW<*-g(ru^|tU|G2bLBU2oz&9sRU#jS`-%KndnG=5L+n`nkfc*m$#FZ5nE zSWG5Tj7X2ngVU?C0&XL!vt+~xAs!lQPZ=cbeuU)`({~1xwpsza<&vxnyh*p=U&m?8 zhmjvNYk<^0fi*~J2^>N^k24C5|FQV0;RDQlZzrl<@eVG4J z!OsWGE({_`ViC);sPaGlYN8xOatZyCjtYM+#whGJFPRS+A68EPshs(T#19HvkM54K#ztqBAAy9!MKx|@1gNcI7Hj`$gG6>*o1;8r`wnB?_QD6 zrydi~#e-Q5B65&?lc9YglQ*g@dwh6TcHPVbJ_!Ky$;5OT7_5@BU7o$}e5on3pk0N7 z^k$q8)(2J#@AsRQUFSi9thshQ3-2vYyURYL)%LF=6xQ0|$9H`v>T_wZP}Y|x?@hQm z5xHc1fep(b7fz#))c&3fQvl*cXV-?3Rntr9)=m+jn>=V&v9qbm9rrkj(GK9w9Axr4 zd;2N}ez#_TyX$vyqYH$oW4fPO>x?vVr>e^_Fp-Cxxe9ac;VK_^1)RkjjGHto5e&Vc zNs8Q%3N&Ek^*xv3z*a65p==TPzFm^tQzew(Ji7oK3=AGilXPJ2-VzDAp_{%E|KPGp z=m8~%p@>E4`opTp-f_i402|Y;RX4b_e(QpL)LV+T(xQJGu|orrg^||qNXkH5I}#;{ zMRb%g&otaYLdc3c3h^MZ3u(Vmg_5nDjvup{b3F`?hZ$Rr$&aU`oC`K*5cYBQa0&uF zNwJ4asOJ}OtnFFNm#3BhBcXI`RMOWfrPFk zF=O7Ul<7r0>naLUdpWQjZ@*b3IWdWExRa@4`)F0oXkA2m@TeERfXu)bV`1qCmc4mA z$0`ayP1+V?#^1gr*OAVSnDOqOM{kyyXxPqo!5J#IC(nNi#~*<4YbeTy};{-fgImbasr%&>uj*`d!i`bjb6Lm{aj z-xeO52gVGV*Kj6m3Tc&`8g1&lqoHP{aw>DP_^0~&E6CuYuDwM#)h?{`)yBRG^C3oB zRX)#YVt1fY>h<5>;dZ~n*@k~*(kEQc?=#6Uhci3^AKx|{o4-^2J?MOxu5*|!G+z&3 zE@LA>V5Cj=&wcKn>kY50dE227Rwnh6l8nk3SF{|vRLq(Q$A#^oKCS%0NQ8Pbq1mY+7-i6z3)H&*L4h9FFDa5 zw_|x$_hmUIgz75O&mDto$n2KK$Q6g0zKg;c@kCP6Zhnnr^H`568?`6LyAHcd$Wd-^ z1%lc(i@vpUfy(;oiO;z8CfXFya#(&^dA5W8hjeAxGOo+=NeE3-rr-G=(sg-^OmV2| zyXX@mUULeCp&jZt*V5!Lr#o(9_2)YM(CrWWfy2wH%<|+<@Q9FW#WQpK5P`ATMBgf* zxV?Op`!GMU%LDT%Q;}gBLuE=Qu0ZFvqw_6e)HkP4*s)b| z`m|Y%ima3%LT-X)GJ?j_`n8^jT!~6VUYv8X9NHz6tuwe^H9F07qq%q~8k~Nm zV#A@$5*eo2V21F9rfd|7#~BQ?;pEP3U;PDUV-~8?c5}2m=vm%x$vK#qj(50^`nIzl zzv*^U7xpL?nVlyEpcuOTjC7XQk1Rx-`RNSY2~KcUZ!XpT)zzfsiG`+P`&raPCg(Wq zd{MWANtBPJGfFxDkUA9g4OM>hnEEq=iUbp%=^dG~C?Y7$na>OjOu6jyxE*zXYzsj* z(MDC#>|Q>zfUgNnEhy|H9U+0zBsaH0Gi?0 zbZ~WNZ;tRt9xuFfs0lHL|Mu_tvnZ8Pby)WE?w_r5VOTVGd=Qg5TI?ql>U5x!XqRXM z0^O?A7*LiH5|hx(Aiu#Ve|-FC%N8ZZx#!G;b8M;v`^n<0k%I1+f?l199ww2+!Miuq zYZo7a82QzhEJu^mQ0H{Q?9iR0n_?-GVJWk3`NA`VX{TQqM#$q##N(wrnCX>%~MSBfMb6f*iQ~V_EAP)ikvR5i*OcXnq@n~oim zO`b0KGM}A*#Xe$bIM3mcxbw?@EY?JpGnrWm3Qohq5*a?~ z@yTmUlZW$k)(;Pa3R+N}b2V7FYUZRjU6?vVS{ss0--7ncm5Z#VMgaR~j!=H^+Iluu zyuQI(Gv&nz!2S-0WHZ6?M{hNd8BWCnU?GPK6a!wHUH*mXtiiWI2JWT;2BrcTY%Fjf zh<7B-F!Y^w9sRW-w-o<_A{vspX0}(2&FvZ1#SOZ@8N59*n>r;r4iF14$}V^?Kl-mz zW!lRqj4jGzyK3b&?X?x}Wwr#3x4&DL%W3vxfk&!Kg~pgx49=~p1I2l1Zsi7Vol9w+$<(jwi1U;cw3=Piv1|VsW%DX&MRY6A;L5dhx5fuRnL5I{P{fg% z9kJhZC7@5v-4B-U1U-&H)2Q}sX;P#fq^Wn+=Le6J zW`ON+@Dwunh4u`pNte14)4tLzV!o;8mbH_7-vp6!`N?u$gy;k{dgMayVC2}n(+PToV~LnZzcN$Duv$3XS@egN7HR@<8pXIKXnVZhc|gws zX%Ri2?s7ee#oaUJK zEYolBPChrG3JMa>T@UciUB`YK2Qk0V@=byk!gu+V7OkdwtriH@ z`M+%bmxl9xf!nU%WATZ>K9#25Lyv6P^2yOmJcTkFu)tu~>yaLHRQDb{+KIPp2@gN= z@L6~A_-{EKdGOe>$xuu2YZsKZ2nx6J!$)r9b$(R1F}&is=Dw5nP5pLiq&?{A7JEvt zF0HZo+QvEfly2r(uC?|${^PKx>Hug_*t~tkSO((hL4i~_p@EuXRd0y5&v{-?c*Y-y zmu$2jQaKxI4|wUlK}?E1@%ge%f*5Phu?IbM3y?Lvo}k5Ni1#z3W5xLMGeq})kfJP7 zUpAG*Nwx5Tca)Oto##hQ2XTA53^}XnPl7PZ&Pdr!1t+$7S2Bdr>v_5n5l7utD?;+S zZ?$I~D>;+$?N-P{f@HmxwCZMq0C$Bxe8FZU!@tXl=oGi|i`FbvoyVKRP|t@-x@w;! zADy`73J8omf^Fi)Q&_oZ^b80if?U2#ycJY&!K z(#a@Zf}C-#pzX|kYz1{&z0tXC=Ctu5aqes}|eiVw_mqSgD2y=<3qU^OXe zDz2Orx@n)~fTA!fVK(u1m~SUVJ>xdnX*@3d zf6OCr9{wq=!AiQH@;4?HrTJBv-yJrQ?1d8r|JDR5=+w`St?i`IW}kOt0Ih`7{xbq1 zgIHi@#&e@e2Q0VT={VVrTxW)VjHUl1ZQRLzyGK6K?i4xFbzz8hHP;w?1GZ@Kb>~(U zueY2%wgCf(QFEJjtGQB5On^+nhZQJ?0DGsjJL!|7MS)KOWJJPb%5$0=^a+mcY}RGO zmT@MA=&X%;X<*(eqSVCw2%n;fBV^KP>dA_tW0d-gs}ONP1fZd-jBD|UfQfirl9G!J zcy(gb{i}UX2mKck#37C|({NQcgiM;*)IY71*ChZ_PFL|Zwu>yluU=d+{3O_zHG~u0 zb2*>KbHkdwzT`f|G^ZC&^{a@)r5|sw{_SB5kwklJ&aG(VToeB)4mYoItexwW^XQaQ zz2a&>7z|xN-xCapk@v@A*wbokTI|@^V_t13>KIxOEO^pDRJ}v~@DKpHULf5%5zc{}PSSNbv zQ*%E0;XJdeJ_2GQz1VDE`p-!)q%qDnyrVFt1F4&gvv>-sBnvqus7S-Vzx#4DYkDkP!_pZKKnPuWRM>!aX#jjZ`Qk5x7BV?C4z>fnFt6`_BlLtp6xH@SA$z~JK)5E-~3LEr3%dwJ>W0>yvWoK00 z0dXq|oKW{yrw5ylHkf^=`Rs>NA>XidhwBr!r|)6a(yK{LR}<%u<>Sr0NAg#e=Ao_& zi>Q@@ySR0#z`D!5`-u%8(yD~c#um@L#ZV!X{W?yhLt&7moxrn=?#f-nKY+vYRVd1O zoZ%ISRRbd`uwHLAS0D)AmPha0ZI=yaNpYD5@J{1rASfLI9Jng^U zbIUX0A~r2?Z;E9!W5Q;yighenV$VZTSB3EH?F3~d-w3C0VZu}3(Y&Fxj>-%hb!|iC zhOhe#RZM$FSP)t9b)#5KnyE70!sA&gLE>Y1y;=XX9I~f+D|$jSeNv0^KEE_g!df-t zK9P21iPOwn830kENJ1#4I+e38Z|0=n+)=;`SV+&OMi`Y-Ck5dIXe-!>^i@p%xR30o zi`@eZ6WCf5$YfwCBQ)ci;2KlROi?Xg(2s#UN~1#tsS%mnkr}Z{@DL4=e$lCbWK=`7t3cI_D=*b!uva(nAI^tddb{RK+8Tv#_erj2qVa}zNz|i zR7w`n>EnueA90L?z=L%x6=R7|%vcKEPkXSn@<+)JCKERo+g_e)_S<=;vx!>m>~vTt zG5gfydCN8F^8E!4->meQIKP(@6X-jZpskf=ax3So%eo436n+<#@;GO;t9om3KYyT) zm*0ej7hr~Ow(z;;I#W$n!bI%+ zf`oG8$$XCOow^R7L}$8lzA0^nx`*$=((Fg+(7YnQP3{EjSBRfXO;8wa&6{&#wkh|L zuU`CG<9U4ODQQ+0*AFl+KnRNv2v5K(q}vVrTbG&bNxwWla{!`Gs!-broZ;*@a$G_w zHMvZsKXu;v!g=gT%&1HY0u1}wbfq63<7-uigl?qf0rC?z6$29W9(tq&z1@He)$F0p=XH-=iE9Q-co*XedjZgX$S z9JUbC`tCz&Tx;y1OsYn4B)>xT&Kmu)uv90(q7 z^?GRC>c8K;*_c~$zOqFgth#g2{-_Rh9H~=~XXDO>0yAHjJeuK_3TJWy2J4Q#<+{;u zirVbPba3Ele2>d3%6I*;!qvG4!w2j>Zr=BiETq5x zXuNqzxxCrPS4%zmEs^H%m*P;_d$+Nf*#^CfdFl2-oauVdy;j=>PC;8-caVyo9t5!GZO)Cx}lr$U&xRyE!pqT>tUbS`l^Z4K0I;;8! z99$MNA$LC(>)$IH^s~z;H?F$P+8t{*CP0i92d1&MeR8oGL+lM+vWy;&b&2 z3I!uL)h8pw!;C34eO2clQ&3Wji3-5^(Vf>lf59g+hF>gQUhN!m{I>IrRiBdQ>EA<4 zY*2R+y(qzL-vH=rUqZ-awz)*_el9cGMhIFtD3<)ZVl@+CMy!H+y&{1{B+39wyUGeOO-aYiqv#EIN0!G>;^Re9nbA z^_dm2+;=>qa67g@x013HkdNb$JUwZ^*bPlC^T<_gLU)BASX>PAn^=O9%MOM#(dYp$0F+deu5~8Q-TpYgUb+ zdk+tyeq)S&ew?MZexwSHK05nn1$J?>_3xF{@j>@ z24qa4U%ub|PyMbXT{Km-V9x)$w)D~jjoIz>?P>uE2mQj_`|Ji1eeQp;%Vj*R;0%vF zWujTpL_Q}wtVU^8#i+FjNo_Cf8lMt0ojJbhJXa(~DLC_V2}$29-S67fCsmK@S652Z zB?k}{S3dg1>}AA4OrzukB>(2lZ(d$o=jhK%M=ER{TrQZ>$4cqQ#b|R@_-DCri*3WE z2j?epZGG>5OVw*mNESl{Y#}<%m3vvZE?FA9@rbWKHKVtvt_bb@2-Gjs`x){34`-R9 z9*)o`2jsgX`**HCi!5`t?^Wzf3`k@ddnE}PnIYymvto)}|DJhb+)$yvW;=18d3UCTBW!+H9>d+q~=pqyQO1CUlPI$Icy?-$4CY5JLVC5x+crD{dv=jK<@#}vN zy)(*{2f)c7IxC%my=f3JIb=N}`|;*JzqR=10mrZ~-M_MPsVI1#I|=ctPkw_`(f<`nLgZC?si zZ#|hjTWx67_S%X>%~@gbIRD;wF*>xK4QUvHw+$Bs7!omchjVZ;w_5guUL}xQ zlzG$bdi`hEwEJ|VSrI3$TlHhvi7&T8Qo(QQF#npi@_E2Qz*`LE^xZk={5Qus2cEFQ z3np_jw>$RLem|{~0ulUX=v>q=wU=oS&V%GU{7Fo_M2+Z@QEMTvl&>4a%a`@So|G+Z z;7zl`aQcRb(~tKCr3?F~QTsj^VC|((dE0@|U z65x$d<{v;N{U~dHT?8jk);^Q>U)Aenp&l-wo)ncrOOodby&FEX%$nXf*D<*$m0(Mf z`8p+y`UpGwe5pX|Ox|Ba?|_Lye)69?T&N=iV;iJm3(rn{sU1EVp0dA&HoWcI+#d2N?VH%T7q4BYhR<}ZX{nCTZ&dY^>CQ`X1_H~NYtUTWb!Nm z%N3t0kk6tFml;Qafze#yXU;&JUZ6ods{x@!RK?lRb2IqCLoNm6FTUb|ac9w&At&ur~GXzFND zVB%@Zk+@=Xq0F%?cWIO%qj^nP7;ebLhvNEE&am zuo5bcx-3Ol%0pC3R(-w66gH2$YVWa3uw#OM$vjCD8i^>(ueT3PyZ4vP-#L1c9(b4u z45HnfWmW0WcDc8PE@Pt&qEYiE$HLc0{mh?lXB7-@p!1Iy7G7;!zPkqZd#dQz6-T4M zJ5~-Y#DBYrU15E44cZu8ly=krGe;Gk0uC#QN#7w?jU8q*!84G*;AQ@?$e{FafQflR zQa7&AF6EBaJa2&=H1pG90SdnACJ@usN<$mw^1R$b72V1!>C;5TrLE(Cj^>)iSegVrRgili|*I_Fj%Wdw<=YIcNLBjE2@SK@+0>o-yEy*TS`Af~OzsX}P0FT|ydaxxty*@|F&B3=qnNSE7pb?r z!5KG(3`AZ!7Sx{G+g$;_)-96IaY>!i!yH7;+#exH1;=+q||ej9JG8xFO`op{hqiiKOrQODOaYJV5g9vf+o71f8#JiN3&+>sjW<|k(^&BN!BtBya~b+y(!3vx|;5|Nx={8H+;tfgDwwmFN+GuCQL@o=aMqeOU zH+}mk2}w)ml&|0b`RuIaOUNpvb>-GLo&Y@WA1nCl8XXEq4qdJARUeDM4PnNq5bI0iVXVZT1uyt@13u7 zaizC9;4}aVay#@XW2znOkM!c%iA5JCHHI6IIFa4`7s^~K(4#Pwg^5*Qc?i$OB+UW^ z5>y?aNqoGsd#yK7gv`PuvSKB8AFOVE_J=sCvZZ@0;hMHBN|yXETYBcKcqg{hOf!xM zu0vP*Uh2KL{K*xC*?yFw_L#6dFtp=J;Vhg>#pvfr?98TrL+&P zcz>3PHj$S?sv{9 z({y?6x8-$}PF2WF1LdQ?YeC|nQ@d`5OX%+5V66Jb_VfBu|4^v%}n{&_DUlE&a!57NkN&!y|MoVYun4 zAD6w4azUZ?d4%T~dFD9!ZW(4nk8GY-tXSbwtWmc~#QwFQ6yGYmO&jFqt93YMn6>!F zCjevKk-&1cD1iKTsu}Z*(qIc1?$D<~^<#-1nA(mvcbz7+1^kWQz0m(9`CL#tXp6== zX?vwFarI{TNDtOw;D8MMGut$MZGT;j={<*ZyY+0Sf0z+H@VG#_<%maxJr?s{+|f{) zcyJi45kSQrou(u9Vs2-PC`>B@9>bxxD?r40@6*iWk+}2Ip&i13Z-)q z>KvkD;y3ZpYWfMyAECC%)v>$^<9c}NZ-COY+_h0XwE3MANFS#lLjG39nI9miq(1mG zrps=`-U^SlJqB3s-ZctIUF?Rs-)|)I?+FEdSSW9-UiOgT&jkdK%^GdMill=RX+RU0z1Ff7@|VdT!|si2acs zOOl73eZm=94{F5jx?X}xYaJv8*Ur*CsKWfN8#;DzeW%G&_PyH^>77cJ_M;Y#qPnKZ z)vwTnFDL*q!OT z`ddjH$BT2eeV;B}sK}k^4%&|g&+MdudrjUB!U%L*Zp?$-oFFU85+za8$)?p|z%G7i5E?5*A7k@RJ{*!Jbdsh}EOB%a55lCve&$-<1g^9pViFfh*1{Jg zy8Th{8xJya^?yj0EP4Z{DZT+nDw0^O~`+9^0ffw^3_VxxhnfBVH zF_)MoQuha!y{Q-s=EotK`Gv*Kr=-@$4D4r~Ok)PHHlvdaZEjOeB#U4tnLDhITD@^f znHA;Gzh$)b>tVYrdN=VtynZaQUP(Die z?o4X2u5yiWg~7m5AIWPoQ< z3Mg~y6nr@9dbF+SJoU0xs3fRJlniX;hH3|lj0}Jy#w%5 zqP**MGqFF;PwAwGM;2I3>?`w;Klusbo+JEcB|sEA&;Z}Jb4+CvmG1searM`E%Znb| zQa7_p3Mqg7N3`jvt?#m4{oBaGE*PBVI?md8Z0|BLSTXtku zI}H8ANnylV+j*Y^5P6>}e)u=yOG(_l&$MD{%@FI$gqJUUf)lLY7|$XITBTm16du32 z7CA^C8%o$qyNmm)BP?nFs>8vbPPL^i{#?}G@d0P%xhuxs+NDDV^o>fa*Dxzof)rkT zu4?6So*Un^&r^?E$D9cUd8AS8pTBVmD#Is(Ih8FB;kmbOVTeaispty{!W6l<4#3uW zI{Gkrh-(n_7Dk|;`l~%r-2uF*UOaQ>&E{romgKYD3=Qi~D(+{_d1T%es&g z8s?|}gkSZr2!n8hn+IaHm>mRmbrPk6e{ntRgLiev^GRMJVB@i?B^vfnQ(^P ztE#DRe}L+!mA963-A&7$!V{{_^_>8 zisoXGv=q-#qE}=wcH9Om=>9`wZa0C_*WtL|Bl7;Go856Xr@n+I4W%WvIT?~~an0i<;rMKJ3(6;Tab1 zL`+vc^$^)e2eh#HD;5QC#@2kKe$%<7_)&rd<`isjss--Xe5V{6Pa+~qDbjnPS+DDy zl1$COMa|$IJ47NfMXGr&s!gV8sr)6`>kF6YMou?TQy|l){}fDfzBvasIR!6ME2*w2 zY8tYHGWAE6*RfQ6)^cH%3}jNd)pGCN)s*G*TN)#>7txR~VU1l^tUdlK3jQ1v(O_O~ zA5p1ML3%vEKc--&0mF3sSN1B$f=Lltjhzz@$o~AH1OUbF?MPq(P3e=+Z@2%AtS)5f zOw4DE|0WnH1b;Voe=^vD%jcckoMOzv<(<4>XjbA}^lq>K*c*j_L1LaaOnGai@CPvrNK>VW4{(F z7w1r|E_Fq9FWQH+Zb>O6PEN{$a?a}NoP53iK`mKW0NVa$T&OyV`WmOWfellYZ@nFo zxTq^;aE*0ESzUW^hJ~{huAr_!zgh$?U??)Tg2lfsX|u$*U@1JLyw-_})3)~fkOeUC zQ2rO=EA-rwrck5=bOkg~-3$~ERXKZKf;HmdvZTjVQnuO3s<|6ZRuu=Y3M56~zW4nH zsJYc!{&hYAkf>bVu!jI7LcG6}33{I2<}7*d{0Z__@B?o!jn#7i$D~;WJ6yp9p4aRz zI`}yRc9gk~XJ+c}TcXem*9du9$arp4+hN-;tB+N_xjq26YcRNZ1(haU?exYgS+-*g zzd{ZS=^;*m)LSnT#++VUO}%URpx^w#o_naEnVzb-n|SSI{l3fnbC}x8^5!*KNJue- z61_Yzhx}PKMN1e?`$R}#GL8}&dARY-pB=fnjE@BX?mtG{g%BqO$su$d;y&~ZeZy`p z!)|XWEm$?YG99`9kghNON93cK0K6Rq6Gj}kulp-~FT!cz1}R^0W{2=}X?PW8oi4vc$x44ViUTeCH=>Dm%S4HK^j zsM=Vz zw^*YM4D=yH<0J`^`Nf3`!oh$I(u=+f3PP>1%rH{SFf!Nke&C|`BZjd@L?JNH{}PRZ zH9sXSye6BjKG`~Ml<^~;d%P@vamtTRTp2{OE8@G@xo0(E7%}OdwW#J9LN;q)kb;b!r$NLW|r+k80ij~*l1{+Ks2U(^^S*Cbd zgx=&DEc%9KHVUwOnp1qXA-*gT5vWJr&WArcYs66`g&`#UJHZkuBw?2YRN=4MoS@RR zB9j$#wUu--RJ4$YP~E-#mQE^D4(*K;-3YI25+!lAL=4rnZb8bafs|1DombvH5f>Dy z)L9m7UwxeOt~Oc$Y?O$F<}?edfqSnjm+?N;O2Fiz49#Azgh{sqoJ^aJ(w%vAGU2*e ziaI*AYH^g}wp*!Ds&NwVY%>r^P*3)^+I>NjEeG%GN24jZ(B}lI3<_0n|42sc7R1cS zDYlYNQ4nK*wxnjF2pz2{_Jue`P^fp|C>{p&H;N&7TwAe3>M$A2=-`J4A|1X&t;<^g zt|ASZ7cK^#`w($ZVecPNsX4boA8HIt#5^~w4dR4c9VpD0Z#3;bpkRiW{`(r>mfrKT z78`9QTt-Eq7-II1l-!KRtozS`1;BiQ8-v^(_r!K9?6!lX{QTh{MvU&_G_>`XT|-swpzj9V975M`!E<#vgA}!{7P7Va}owPFcU|Qwl;TNW_dlX$Sip`6vN= z6fW^iL%VKdqJ2&`H6A;k>mABFK5=J#J8GG5dOLzJ^}AbuYR*<&MRQisP?@(GJuIaE zv?3kt?DqbzT@2?4l_D~2eFm5**xU~-j$tR zRVYD{(+i*F*LE=%AsumHUppPm_LreqnhFW~i%?C{W+tLOxo;Rz3I6eUu?RILT z0l`O1Uv3Dha)eTlb`m3GYHJm;ZF;9wV(6rw|gmZpF@)f4<0^OQe{y@pqQB?j> z;K%g4-aJXOhKG$4?YrbglW;2LcUz^OY_#S_)IC-L!b9Pqat?*H5h#wT^XcAn`XROL zHlluqFT_H{jcEJDc}?7UV#Sx+9I?S6_IU`D4k?6C7o`OxI&$jLEZO=Au8X39Z3C=I1fcO zenyRkG!Q@JPX`+n3J`C-SwNVz*~KMoq`M#HpT!7u1wxA&4x{|9Tx0r{#5Y~&MzD`` zObfR- z9L9}*@AgY1o7u%IVR`-4KZyO3GXiJO+SxH)=Y>lq?cc-rSSj3vjii#%~&I0B#M=MQX_XxhKtDETJ3!X`zfmY3M$5~fE zlb)+uIw982 zxP0o2)UP`feq6?G1c{D{DJ%;>MkfrsXsSV0u_Ek_WbW-7D`H>c>_!ai)SDP~JB`}d z$8~NQZ)}m|}lX)UDc$T2t%e5{Sq&gJqjHy^!qn1N0 zX~}mkR*;>#_D-FJ^xUneopb`jJDPUog{k0OHQV0zW;9d58^rT2%THfPWb@RTWi}%J z3uNVl*diO-3l_Pe<0l*`&Zz3nGpp{%kQrtQ2;uz0EIUyCAuI*%0e>h!e8-pIhShI0&bQ9^P3aCT zY&BD27CJ?+`~>yoay_NK-k_jkFYp%zbI=YOkx%CMKQ%!Ps@?4Gqfe+2{-JIis5L%nZ+8dLCq9JFW){rr?4*n+N~Gs!IT} zg-8J&*FPbrZV=q)0ohIbWl)5z-b)1fWcBjtP8X(j^tz z{3CHVNA!7lY?N|kmoq)dlkOA$<6V?x4fv<0QrvlKIE#{6{%zO?KYa9t6F)?UFo59bNJX@ z+6cHm|E)Cu)oNj-F|(}U+V#y3C9k5)xKR7}p>x2w@Z7#r`|8P3)rCuT?b?f|i7#dZ zga@PiBz@eG?<1&2%B$A@LgMR7DP&AtBNzzqv3oYhIrVPmeP2o#H=F%Q?h zLOLqhupQf=+J=FMf15)Zdu4x1I@{HM^eImBg6(5Dh0?v8K|ic>maU4&ctVoFWACTe zWnI{&D&nHKX^qlpDgZ5Ovd(_IZn5W9nRZpbf1)|{dc4aC>j?Q|D3YGAS}0eD=ly$* z%;HtBg68jcEMP zwo&GrEZJ(Z>5F{%jc-;=bU?nbYhBBxQmf{dTCvj7Srg^x->2V=8Nc1{-`d^C%sITA zC!Hhk>|Js;2a47TxkDbIji3!udj*Z5X4MR_)VTxQb^8}oEEUAoNs!-d`N zI#wr5Abww#Zk&@d6df|~%nE;SSqM4{Zc;c0Q6q>jjz4d50&+4L@ULNcqL6u4jsOR_ zzbrwfwHpE-ReJTA*v+h3KHz@QX8Cc?olMAdJ&9$-U*_YU=Bla3;KKaFHC;Z`UWl+- z!R6Jklg#n^7;}Gp?-nsA4C}PnsE(PRkPbgvx81&Ai)qfDb~Wxh_wf56d)`An;x^jD zciCS3={2gu#+hijcbC>VKd9;%+6Ix1o_ta1s6-Ue{T`(+BP}$>PE#x_?UZk35x388 z3f?3QZ-Vm?9~aD>YP_LSR#ks2qjqYcok(nbh$gnEG$CTbm)6a5eLt@%G9lM*B*hpU+UKLxw-xa*AHQdq8 zCX_tufm*3VI{`1g(l>%>qJpy=vA1^~|#D(p~HYmi-r zx{d7o4x`2v#h+`Kj4S=Gw!L4QekCb6BF>NUouyc>48xGcYv13`lcxR2V04|7%{uaK zQFHCdQ?#91?y+(oUOLCY_I9*-x#x?=s~?N6mfP(8>XJyZwGxhgN&(n4tlrzouOVo*9VP9od*S=E$L6sP6@IfZb;6{4aNevg*6Gnm= zMC;k#Yg(SUx!%FuG|(?@bbK*PQ|mmropN0oj`#3E>|^c*UjohpdJyr<2R=L9`&X~5d<|WP?93HmBTNwFgNcL00$@-J9OkqJAzjQ+kJ8HhWUk9Aa{w@S45>fpBsH5t?cDZQ@QhK4?O4DsEg2{8q*= zkW6#Snag}UjZ>l2xl1WQ=!=i{(dpw~=GU>qD8@=TJgjp5tp>LO7~0Ws$vKD1PN^kP zng`G0(4jo|*KeWJ{Z=(bV~LDQw(MJ$Mx^=@z!ZoETU>XXh;2m? ze$2CS+%Sdc_>Qaf-FEB2qab=8F}c?QtW{L;44RZ88rE*}ND0Ebd}yHyyyyJ{kaOdk z6Nib4(JdL*K-y1b>cfuSw9x%6vrBdEu_?T<7sI3}VGoG3r{kMy>w`MB1fBXzOQ}~~ z{$v;L3=s8ZtP*l6bq{Cc(N+g_zQYw!%}f3_pZgqB_4We_s;O<)mJUcCeD28n87k(B z!U^F*Pq_RG-sap<_{%)Alsw$^P!FO91vkdSBhD;xn{BJVw-Twdf=p7YkXxi5?$BIm z9WS}~ajnoMlG(xW-VpDmKnxKFB8Tt=k=C`&2sodJFJZ33 z`F8UryRA3C;_vE?l;Y>k*!Y#ltW;k=+CvH#lIX+`Bwny2#5Anxa$)S>z>ZDQr%deN z-u5pNul+0J>|@6pezrzY%zTYX;RpI>BuD$TQ6eS@q% z!F}J3@7Sgk&hqiRhWxQaK-kMYq9r?b-ILI@oM8t;++aEX7_km1#}{$WD^2${*)Ol= zoI6sB!f(Ahb>KnIy)o1lIXFKY@D%42_+uaYUmw!*Dx~YLQ*PIxL|oT@CgbVVq2+ug zoVG_$x-iwa2g1CDfWKe#Wz-N|o6YQfo%4SaZhUvb#7&E7@1#sQ;_RuRck|4qA6dAv zZ6gP~r!8Ft*(J&~9f_59Lq;TF5X|9ja*m1mciOE3hvQ!YWU*vE zsotV9>J)~53^0(CA^3VjOJAQ%LZLfd;Ju$YNpX%R73d&>1>+{-%4-2Z+Gh8Hq&PCt ze8*CM(l%TNFH2SZRPKn#`Qz~|&%?5)&tINb{o#}st*$d_5GIQg`^+xE6rHb&Z+k`rV%-YUS=T;hff&MA5+({#7;8}G4zt7uuWdmvAzFc{@3@IY<(zW zaAS^OwgB>dE5!I@!SbcDbWcIEU4)bE=qP=yUuJzoSV%6RUucwpfyx^m2@~D#q^qjv zVcBDvFt!j1mCCQB2DxDaJAx8jUk#Tex@#{&-~&pW&N_V;{lIJFpVxHXtOEcmVdMVO zL~WTp{$0O=cK)JM;@XRrGK#|&9}t88;-#9cnQ`fw0{z}O zhi@vFJgc0f9BHpIGbbi!aC4wIo;6*RxMF8J#gEJXfd3aK4%qRF+sknvFIB<<J>hLKcfIm$6U75KHXmUB98bM|y_tMeOrfGDQOpSdB+c{alAMFX@MCg0B8|=oNu4YOy@M)u4Q9KI_$GH`DX)GQ z-`;)O&t?O;IVIQK?i+#AKlXC4{I-|-!EPqIvrVIOP&y%*vs!?x_1=w~eVgrf1APXb z#fi03wqWS|Hrp8Zn%)YBf56e#IQj%|yw(%g#gpuG3?Iwyze?aadm4%kc)X4Q-^*Xi zG$W^NrVXpM9kO+{+Gn)yJoTI!&X?uYtfTjJ#8XGh;>%uMb!Gw4eQY__=>Jaja?#uhiQ+PQfcXuQ9pzrC-;$D-n6fu0slXW5Zg zS3hKDzw6v+dY+czXw6zeyx~Gg?CBg4u<%iIx=$UgH`uzn>FhhNaI7mF>vY$1j%*5a zEo}ucE+~%da5j@04&kxj!C8Aav%m3~4D12?9BKQ@orw}Qp4hp(IY>j;Af#7sS$0RM^2{Wi-S@RhqjC-x$#r)QiKxdka=wU@)Rw$ z7vfw_;z!AnF1~!WbCePY*r~RSAm*IeV+wI37;~Fh^jJ5%TfKWh7sTL|p(}&<>H#gx z7ddX8M>#&?Pl+xIJ!bn%=0-+`+(G(I);BU*k6B1PskhEwE$3o*+tXnvy_Xd`X zrVKkJ$;QKq_InjdZyNF`m8^`giT~%$Si@tvhutxp1aXA-QyzK%aT>jl+uF(2ExApl z=Z#5)+w-R6oZLKHPP-m?j;#>6AQwZdsCd%vrAK%eK&i%Q1Dg{WXns!F$bnXmOg%Z} zf#$98AL69ie^LagJ9NxG-;QIpz$V`s_)sIpkju+#0Wnm(+;b{Njz!n-8T+x_W%yY? zfCYF#H7`E642x}}$C{S|F8Ky82LHiM8eYKhmVpw+R(le8@>GF*Yd85yn+8mG^;;Zv1p zebh1Yt+n6iP1_Ysl;85zgZ#j0Yx$u`p=)YWzt!*yIzifo4t1X4bs}luqo!^@Yp3&r+dgm&CBG=`C{N}Da-!d=5{$+=(2x!?GpmffR_ z675r@Bn^*BQa?)M<0O$eiOVKGf!zSAB$AKGq|9S-uC9H(x0}b$ab~q8D~K~I@YUD* zKu?kKLz}SEI6wIQtbE%1Me&iGs#vw^rL{e_<Z8+2T_i^{c-fl6nf#TNAeMj=oh)N$_} zy02(meTdfn`)S?2o7Q*ev7&YHAzIh(rgccN5A1!vzJ|cU`}d|F*t`0`-uLTlNVXr? z+xx)Y#RvAD*IRO^OBRQD0$Moh?Wfayq>$wAEOP|(zbAV}c;ED?I#)rhHpMI|1sTRR z6!Y-j{Ej368%*?k%G6GFA}*5v8X$!=UDceNo7r#tGo0vIaH8`gs^>arfzbNX_E0~) z=tU8h!T~Dv?DSB(9KAn9`>@P}7wh~j>)%lVKBebsRj-$ry9n$n;~yijFnyGsTSI34 zITFOWQ>NDHnHg+vOHlf0>p6)RWZeE6i%dA#{e`cDmv~uy2jYq9{Ty4LXS;vgi^#Kf z^Uwdd-~XLJdmGu_MQLTj`9Gg`-;*2Hi#+L-7dDv>t~SwqcQ+N|lAr4I8d z1bs>mIb_ju(oc0Ac$B}z-_Cs|e4#F0zZdnL%VEwzCy~s(fHED+fqpa7W-dsUVT!zR zm{{|M4ycJ-;9CNJwyv3hRx{Ifo4OD4d10B^mzl4)P48}fo9}jYpFgH? zilH|QBC2cVv_wt~x1O2kH7&;&s0I0lkNSSif(2>N&0G z)O~)*u&G4@_iQai*1A@`emOtTwCMS8yYH`g({MqChK`9fH@!82+C$5*-ESY(tbG35 zSG$M$u-$80oX%VQv-`Too-?c6|2FUA7!(`uvBl_I_md zxqbwAJJ$~!oq6^C1)f8Ve(FqR?}wP(cSvsq@vukw&L^}+cJ@FEIBV8#yz6J0o(V z_bmtVYWAbr`+Duknm2bA?yse;6|q#4FrguqOzGah>dcSs9^Cp4;7Wd($z|ue^=mml zbuZ9ytFyEH)8=7z)A>G-zvfFz-#=(xt~#CFUcxfqK3dZ-U*7}C-E5{d61;^MCwP}~ zwox2B2jZET$>;7wSvH;@Y~8JGUi+<{gS+_h#T^9HP6V)+)L3$44cG63$n157*xAT(51wP?H&i1EDnEUj&5c-}iV!jtC?3)|` zu~F%JQO`|0{hLCG0koLAQtB!l<1IE41AyR97?XPEt>r!)~)L- zR4S3Tc%Zd2${^j96us;6m)f^i7tnP=$KcKxb; zJ+-H)VcWiozuun1e=?4>^_vXcw(c!|Uey#1>SgiJeYc+VbHuJqpS>=L@l{<1D;IN8 zl*1T&sP+AY(OofgYnvr+#gl`5K#f*?o8hv+$OO>QVM)w7^X21Zf=$fOK3?KW-DjN9 z_nR^AKUCl7KVIMHZGFF)qkgY%bWY#syuQ)@iN5vxA-jWcuG@Oz=o$qxmDfFdj+sy* zXL`-dw=Zw)z?VVH6q|@VASce78H2WqI1^gdqLRCL9tkVCbM7+z;Rb=tDBe0I|NKo% z9c0di0;q(TTmPQGF&^{cXB$UVPY7L47#!xlVUd#5SvYE2eG^tv4{|awyv2e7NlgxM z1Q|9qN02kD-x0_!?7DhRBGK;ai_eJ|C5Lb4R06$T>=i3poc-PmV0Y_z4|32-ep?FPGGZTU5MqXxyTO^;uk(FEuZ6As9a2$%lUY)ul()hYI8(Hx0e*pjh Z|Nr80P~ZXp009600{~q4*oi>#0suy;YnlK6 diff --git a/impl1/synwork/s1_impl1_hdl_.fdeporig b/impl1/synwork/s1_impl1_hdl_.fdeporig deleted file mode 100644 index e3d15b8..0000000 --- a/impl1/synwork/s1_impl1_hdl_.fdeporig +++ /dev/null @@ -1,66 +0,0 @@ -#defaultlanguage:vhdl -#OPTIONS:"|-top|top_tf|-prodtype|synplify_premier|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-proto|-ui|-fid2|-ram|-sharing|off|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-fileorder|/home/hadaq/mmichalek/lattice/simplified/impl1/syntmp/hdlorder.tcl" -#CUR:"/opt/synplicity/O-2018.09-SP1/linux_a_64/c_vhdl":1543382462 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/location.map":1543441258 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/snps_haps_pkg.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/std1164.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/numeric.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/umr_capim.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/arith.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/unsigned.vhd":1543382268 -#CUR:"/opt/synplicity/O-2018.09-SP1/lib/vhd/hyperents.vhd":1543382268 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd":1592814713 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd":1591120075 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":1614208538 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd":1614208577 -#CUR:"/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd":1614208577 -0 "/home/hadaq/mmichalek/lattice/multipll/uart/source/intface.vhd" vhdl -1 "/home/hadaq/mmichalek/lattice/multipll/uart/source/modem.vhd" vhdl -2 "/home/hadaq/mmichalek/lattice/multipll/uart/source/rxcver.vhd" vhdl -3 "/home/hadaq/mmichalek/lattice/multipll/uart/source/txmitt.vhd" vhdl -4 "/home/hadaq/mmichalek/lattice/multipll/uart/source/uart_top.vhd" vhdl -5 "/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd" vhdl -6 "/home/hadaq/mmichalek/lattice/simplified/endp_dummy.vhd" vhdl -7 "/home/hadaq/mmichalek/lattice/simplified/endp_handler.vhd" vhdl - -# Dependency Lists (Uses list) -0 -1 -1 -1 -2 -1 -3 -1 -4 0 1 2 3 -5 7 6 -6 -1 -7 -1 - -# Dependency Lists (Users Of) -0 4 -1 4 -2 4 -3 4 -4 -1 -5 -1 -6 5 -7 5 - -# Design Unit to File Association -arch work intface intface_a 0 -module work intface 0 -arch work modem modem_a 1 -module work modem 1 -arch work rxcver rxcver_a 2 -module work rxcver 2 -arch work txmitt txmitt_a 3 -module work txmitt 3 -arch work uart_top uart_top_a 4 -module work uart_top 4 -arch work trb5_tb behavioral 5 -module work trb5_tb 5 -arch work endp_dummy behavioral 6 -module work endp_dummy 6 -arch work endp_handler behavioral 7 -module work endp_handler 7 diff --git a/impl1/synwork/s1_impl1_m.srm b/impl1/synwork/s1_impl1_m.srm deleted file mode 100644 index febdd833428d27f31f07f5f15d38bd68f94e48ce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22210 zcmV)LK)JskiwFP!0000015#C0RVXORFG)=VU zcSrMvv5(K|@0?@1^&bz7@7LP%b4x4?VVXa*TIagH(&U|Y;TnpQ2ded%`fo5j#j|F*j#6={&BVv?E@VX#PM zns!Z?DKay11<8aovtNviNUc-*QP)=2UA_CVForkk-|l9eNGIt8<%u%MG;*z(nP8D{ z%}gQ%;}?@?GON{pbXMJKt-E;9hus^a+kMfCbwZdiH&YRrhSXSgZE8eBEOWDhd-)5& z@mi++Sas^xU9I~v)E75hqx&NCZaYEF)o=VOl}5y_vy=6Oo-_h##nQ5bM|#qyr~BH> z@FM`a~pV)bgCb8aYxREL4(N$UcuO zj-D+~mN&dGmV}n$KgSlbEgL>g$m#^8;BPS2ssQJ~zjt|TSGcr) zFc>)O4y+W+E&qkzxRINd%`;2qt^IL-o_;XT>T!n>Vf6zsbA8Jxqn#YAImlav#A&(f zy^*hG#)XgF!KK27p2IC-2^!2q-*+r`i!BFh+WTwv^V@(q(!KQZH@^2Uf7Ri`g>gR^ z8jdTOXXmf>H!axNOvNp7-$&HoPDEvyentnfsyOvT;8G{>2C|g?WS{<{@wG9~kLT$Y zr2F$2QVu-f1sME>x6a>}gzn3yKbUWPq%4<}=|$hhn_BmLq5OSyGx%D{Q?k#KWze7} z0`B;}iyIUfWLr1e^v$~Xuh!|W`QxpP^#dEDRDO^9!f{o7q3UGeC#8GN_xCL8YfAl4 zzw#FVYn%hbIam#A-)+tYK<-2&ZL~M=0anID0?SNp*9HWP53Vnm<6q#IrETK)!MGo) zIM%jvd|%9ZS-?S(Q7yJT8-A<(JAxFhQ|ibW{FZ|aH6PS^!1b_rRO{_Qje}q$f;(C4 z$G{+}w%+pMlMezld4aaI7N8ZpFN}xBHMVKHIhj8TWRH^=M!1jnTV&VZ`rm2FA#{N_ zx#9=>HSVp(@Um(^!ybNL%Zus2nfVxVHa7;qB#D@rLBZPxgZNCizPxalW^LCSxZY@J zh;`dJXsHbIue>6lGu*qedfAuv8?+ibc|F6Ad^vN<^ew^gJ&`N;5z1~q(?iSn*7&&| z*f+b?*vUN{!*uoVD!1U2bLpHc_i$|B`f|A^1m;Ta+VYL<8Tf-7;J2lZ-@QPQpJ12s zHvWfu^N@HkLRcqK$3je-lDfl_Y97sR+QPjq_7OsuZTdx5;8Gu{-QQ!T`?sm4i%wTpK zW_^IpX8^mk+KyW?3<1IrM>EA6$iPMZa;SA}j*;~t@`V>l1QCv7v7I*}IO0D+za3r8 zZKlQz#yDlJBL;{G>CS&1$57NDu&zN0JyL@U+`BY((Z6KiwtC19@j^9&<_HL2zN_b}i~cYf<~7RG+Ma%Mf!u z7jeI5OYGZ0=IB3=%WwXx{j(Hi{w+Aa-cq>r9s2oKfK~@qTg>u-4J-(J^=D0cP0!+f zF&}=FK6P$?^<_chUw&Zi=7d%#0X~0rz`vFB*TRq0{x#puyCrs4ep~oT<5;$MoR`S+PeQSpF6Fu$?_+d(LBNoQ%~dV_|GsSP10A)=$2!}9~iUcKIMJ( z)Vj}8wNB}lL>Ej1p5$g5cKLcgcPgJ!7}A1ojV(TeV1*dv=qR5%xL5JL+Si6I(v1{9 z5%%z5?s8&7to*!zx{Q?ndsyeWG~|$zWUgP0R9v8rF}f)qxWY*#yumN{JpKH6`lfcn zUhs|2M8GZm)Y|RFc-*(k8{OKId2PrFJv}PEl;5DoS!;SsVF||`;}z@rGkC=6qBgX5 zb?prdLDAp(-Rt_3>e`}*{b_wOTw_8+MZpVO=QX7RQ`xrmxWfj}g42Lrxk25`CUeT(l%53>Wyd^2C`nHe*IK}!OcU!-8Bn_oMBlY$T$@g9NFbI{$qP-LVp z`dbWjoLkH-J}+{p3z6%J;36SU*LM1G?U%&$a>=kwm70e+#->^^uJF_1F4H7<+KeiU z41{|TDBnhXx%fR}xk7)<$NZ!EQ4B`IZv3)tO9`Tdy%u2brRNxJhZ zF(aPDtW)?^SkTQdm!fuDKhqpIJj>Cx{r$Jpq1zI4U#zB7jL{qW}b<++aT zQNPC~c-ehKN2wQUreZjr)*DNEQTWXGTVq(PH}BW{?$5PhQp^#Z?&fo%KHuLA$1nBg z=SE$0R=8QLc--e@crT_6RWvRaldZpVAIk=c6-~y8!~O#eZ9M$)t>E_)Bzm{;xNLo? z?>_JL)ITMM@*K_=Aue3Q|HZIP+7H=gTa z)v1p=_n%62*I9hp?h_EtM_Bb$Edx@sydV-;KN7P^`1J92NPW+eQ6_>2?HQ&|=FynB z8N(bW)cD6IEHu;K`(hSak@TKG|CsiF_h(ip7!|aooXlJn>A0{fo>^$)8ls2Y+Au+G)I^-lXft%M!cVzW%!mNz7>7MdOQ;$$!F4w zEP;utxyG?jItbSmRy=}<_4)TMPFOy0_?@3!I0e&tiX%-oPohy3>i+` zpm_oFc3b~jaf?H7&L#!FQ};>fsTefVJc@cbTyMT}z5d?)i`>G1cy1(BYC();GryRt z##If;(I(OZt-#}+x5m%S8Kbbxq#|~E1&(nc@6`QNEX<+~aSbedFh_0hx|qv~oUdvJ zUeHx?srpKt(Muw@cPC~h743KHVE$emT)j&Nqxb7z@?JlxrSH^%ZoW$gy3pUH1D%Sb zq7ImZ1AUz%o{fSv8_`970`TiBo-htJ_U%^sq4+Fz#BYo2064lzjzX3xU1aSw2Qg@#}3i<5lE1z!{H(p)|zXG3K52h8cWE+d!+O*m}1B?}=M-p;66^-F! zGI^*f-wgVp!d+n^aR2ALSoQCiCA>TQk9Be{cHkFQz*GvTzFxpo7xCz1U)Zjb@LC@a z!nHq=bnV|~%Ahb0Bi-eKIOpm?(FhsyiPdwe$43cvaxriPtFBicW+oFoim|S%_pPQb z{!=}6mN!*nXQ^W6rgAO0Os6-MbJoqWG9Kh*IUoBmyI-7_^r_-a%}2TaWUhHUSO2rQ zdWE@3*XLn-T@>)LaDDLUiFrFcoPY2Q05!|H<&=1{A++c-FL4nT9lWMVcG{c5iBW*Wyq z*c`RPxEVV*WbtIAwfkjfscqYQJzpaka+%8+c8!(}&0@Y|$k6i85Pq)Sny9n7;!MK> zLk`gAedmrt=3H*yVW{tVU~ooghTm@c%b7albp_Ui!9|j$@viSCSTAxCQLP81@8|Z< z3;S3rY;{hZTZf~$)#n9+2eB}R%jv^H3_D}d_%^hr)ob1j9ksr*T#m)!VL2Rj#Ppo{ z$^q#ThdV0&*dnMJ^TivNZ{vm-BPUDouow=-l%W%#PAg-li?xLyRN=2fv*<$wehR(x zJ(y9fQLFB2dB8XcWMGNP_*J}>6w(R&YHL+Zs&Z}Bvs1OFkJ$-JVyn8nd??;`!Rz}j z@Jg{LPSeq;SX8`?as$utf*oEUe{ZozF!BbUR9sG3u3}Q#f5%paM@)O=SM%iNtjYCx zzLJDzaIbZj_33ocX~9yAm&F-i2bP^yquv^dFCA@szd19#pDw2L*5-V)h#hqfn%qNi zU$(yn#`n8BfWtGMYCaN16jH-kwWTY7Uo(XU3$ww}yK zfi+KcJ3fAwG>3_LA6Drs(6k_ZC$^f2nYRB2ij+$5Ye-tm{zaHuL;^|tieCEJZZK&=a4&OF1D*Pux&*D?@l?f+$ zq962+*QcL@Y0Ou;i_p3OaW5+8AcaTL6V4O2^mBUqb1-<#vxgsvP-ps)lhNSAe+R?& zb#2lQC+Dk;zFzCeV?Tw>yH-2coYgz|8mBK+&3HWja&vFReBbdV&`!5^--tC{Fq6A? zCo)8Kxr-2t9*mf4X~({|j;nz&VC2o+n#v&u_irj5r+-1`O%C|ketzH)pYq}@QwW-R zf6Odj@F&Vsbq~XQrETGJEO|}7zVA^Z7=Ho*fMboX?s5v92U(HfQTRmSVlo;Wry8M`VOE8AmoIHs5Ei(_WVm|ilLl#I1Y#*TQ=OL$32 zcuCg0oZMsRpvB1~(VNyNO@g2q#3Qrcob)G?=GA0krg1+tHO|X=jM%=KSM4#(&3gdl zt7@!>4d-%Q`)uA*^$=s2pRw0kXvTcvB5Lpe?5kH92$4|_+rzS-wXrkp4R6rz7j={a z#;v4|58O4kxPo!O(+aih1`B_h`;sU9oP1jRyd(=m)ttc2e3MZ00Z7DAXQkMaS3c`K z2bXtej!d07>Xmq1uQ~a?W^YZko>8qi=ZyxvfbyT+gZ0m+;MzddfdR`M-*t;Ru&mbE z#DeQ!rfGXHvD5iU?}{jBNBb+^I^)daPwDKxJNnr?&j@@@s4uB-v>e`Ie0qfOWf)qL zFOuVY5g*Yy!qj;wt*c{Nqhr3xcrDq}gn7x>aV|4U_m~`w=_UK>V3v&OC1c0=Sci7W z*fB492`@#=IRm&A88<)=S8v`oNReYqMXYJ9`%npnLSIXrp%gzWq?I;Y>--btQ=<^LmjCiy4N{F7(?$MZ})N*uF4 zv6?(c+L&jq`fbcJeXAe$`$3xad0@u>B^um1-C0RR6=D@o1C zvF37c1poj5|NrcLZExGSvhe5lR|HmoD(DGUh6!1gVPI=1s&KqZjL-J>f{H)?RR#g!r6%&J8gwhc) zB#*ipxeN_cU)Y_RqmZVy5KPOaUZ_jdHYLfaYebh_ZML|RsXLa>I>UO6*q2R9H#K4z zs52J%-_#U@(3m+`Bc02dO^l`+>UTEP9ZkQpY)v9{4zE`4*uo__@hobvE`3SY4D3aH zgr<3EYN1Yy1!nkMnxrXcG{Ub#Fo$Cr;o@$ZAJ4cXAvG7KWC@fQZrzg%T9;ftrrp#n zd+`_w_8s}X-di3|rw^?LS<=z+x6z>Wdy6bvjnm`Cfd1C1kACNUmc8Gn57XmDhxh=q zwOo#9>$kxO{Z7V!SGErs{XT?m0%@Mu7L^Ri4W&C<(9Hiy;rWd&T9Vf2wYA3Og`uKT#~{wpr-UXN4PC?09qEXk z5Ko)`)v0lM>7E`uJoo;f_YG6C+)xQM3hh1}kw_n+c{z@59Gy_fn=?J=)c%6syg=8V z|L8s3(*~;ASE7a|h3+%pc~m2x5*Y~{&4oErPdd>$WL~TN70nUoeb=XpPa%PCHohbQ z32;5UFpi9-d?2|``J4pNRZ`h;IhVe-XndKn!PptP}gm{*!n|fe1 z1*v!c@W*4F{Ke%Wz=40kY*8~j;=HRqx<&?{NZMzi^KbMoM2L09$f$)jBL?}4QP=uJ zRFGF@%B6>9?+xOcnQ6ba}XBKL8f%F0QyU-SbE*@sq49^QSn+gJ-+l&f#;hlW~ z_M*Y;za~g`9Wp7{B0pz~=0_1+SUaED8U{Q|zO8NFV`-n{cXZz<>fpR!vp0TE?Q7FD zgbONZw#4nYOPV@0E@r=2=FBu*4aanWcKQW11jD07KRhCu#eIdiy$6D2O4PFjDu6FT zG$s4H$^4Gc);u8)*5lb1%=}6k)x6LXY=P7;r>lFR8w`--u{B|42__TZJH=XPx!-M9 zmn=!k;ip_s?and0gvW-fU)c1{Q@ng%?c59<2?J8|Rv-D^?Ku6IQdS zGdg*WZflODorm5<+OIdV?MK})S|P*9ykv6-IIebc)N^e8Q8L1ot?4J3?;i((cE`}a z3}SzB)NI>b&T{k+iL4L|t!toOW77`);0 z*|U9i_ug{tXSNmvCL4#X5%d>9Yq;m8G3U3&(HYG{4JCe_T6^$ zbPX~DYCY>G7;w?;zUI({1AUlY+&$agS$L-{OfA1|1#JGt8R&?9$-J(+nW5;C_RM|r zyXUi+sY}9hD4c0-_)GAN0fnKk5D1Pt2Fote;HpjZ%XnxU&0I$OUM zmluqn%!lTBZ;)o+6POHU)(86DaU{bE1w&^`5}j#x{cu7MAIE9FH(0DDjAL77HYMgl z3k;rz{W%&=kSN!NTn8P;qvuDOBaqphjAc;_*pC2nMw+HcrMm?S5^TZIS^Ng;WULeC z%qKTZVny*7wACrJ)19*;GM8nP#u6c0d?e347f2o7v6)jH--S)#j;&GV&*W!}=BldV z0I~Q}J#uuy{?{>CU$&w%0W?f|VcoG<)2Zu6{JYVF7}QpX8P@Bj)gd+W=lRcA#l9M- zs*giCT8|YL`fVADuVI}d;E4%qBy*Y^zHTW;W;XzYF;v? z$Hr8eP9N4$7NdeM@(I5E*XT1$CH`+5M810Le|yaT=KhgUU;833rxgD&;6KKpsA>|k zL_~2|G$cq4RZ8a&|5h)<)$G&={`qG{S;o=;=<7?1&|C#bZHGiM(PE{Npq+k$F+yhl z4V|(@ashH#H>GgF{Rk75{?KMNJv2$(V&4ql+dSgi9H~fkU6aY1!h%ye^Q9GTs{uLi zTiM)P!(@N!cHR*5F}EZs-FZ(bEq+&+u@w zWXl1amd)wm;RdtbAC|N=x>?d?>tR6agXvCvVFHJ7ppJ)(f6#wQ2RDP|Lkq@X|0X5h z%6P?bzZpz9Oqj!VxJC?D2Dmb2aF3sk`J6w}`w?FGAd^q@_?XXkbpLV1XcIiO$#LtL zLSE*6^>O3}xLjVdW9^X{jOS`F2ihYsg*W)^baa1AKR%68c)yKK2gfkpE_kQ(w*eg; z-`78mHs;NIlDZM=q6qMCfRU(9j@74Q;MHLHH2r(^ie#d0<+qO9aj~`BtkB^rP;L(Qt zVNj*SMld>00uFoPKZxpvJTsYMF$`ZvHgsSxpi`5E0$YE!%H5XsJ8@#`O~7$N0q&30 znG^~n?9YUnw5iXtdOxfS(oWif9K-sBu{t+ZMPQCQgBbm{jD~_@I*J|c!x2R|BBc8& zi{GR^ow?lZut-Aa!+P&>J5xp*hNeK>{)~FsozywmZRb?vV+PCz`LtYu*XZ5;otqwE`Z4C9UiMjxH6RxH?{jBX_J?=9;Z3qAymk5xwZWNniZy36XsR?ij6 z)PFAO@9E=^lk_ShzbhiU*eSw)j`%~k}PhAc+BWKN@U$wG@2w|^uZmyfB@O9xAQ zP2b+9L>7Top+N1+3u-IO?Q|}+?dz=>pI@O zCNb;o2WlX)@smExUo>s&QfIz!3eUtW!re`C9kc0QnikBf)JIzDuMcwMBevwna%2c> z86Rfo=~BaGKG}*fCZT=WrW3Tc%9(4pLS5T!KTrZ6sbUuXrNnu{<(b7_uI367@U&wp zJK<67AUX3R|AWCsGM}SKFRTlNIZ&F#VO|JqcuTpkSU|Upr`a}p;mK+sb9h4zZ$|qr z_;)a;gtysmJLk!4TcUS+?T|kQnPTp0BvXBX&O+uM+B&mz8cD~C?NXUdN^#R@s0*5{ z?VYO#G7NJS)4t4cMzD;^A0o_;B^tbrrxpsAG?!;x1;4;bK!sW7v3-Hia^0)y1SEjNT z7id>EchiL}L4eDctwkutMR80P3x`TP&i1t$c%U#DXYp^iSI(F_%@#W>$8yFZOKzhS z7Hekb9NQ$iQgoOfDQjD6Z?$XO7Bai8bo71rAixLt8M#+n8mova?CMJ$gBY7<&xzfaZJ- zeX1-RL=C|XHFY)2!8ND@i(}U2a~y5Q2v>qO+(n!0xO;Kpc5$5A3ZSXu(YwA!XV{J6 z=9q2_jOWlhufLkPI7>T^1-_nh2R3D;vgm4u{AAni^g+jSb zJm7soAApz8?Q?%W5MNIFI&(dD$61lSGl$ks^gTO9)_=?5vv18Qw%ulT7M)r@$rJUn zd7^%lC+cVNME%V?QU8Pp7VLpg=P21ziS`Ei(f(9Y-=I8m7{J4RoLiy`P0>QaoEt_X ztG0ms7ic52R{{ImCX1%9ppFyebg5%OO$K}qn}%sY_A<^%!ah*v@eQMe)$BV8?7LV2 z!}Jq^eQC?k`u}x4N&MeIyzlTA?AKWF{uJcW%%dnD9PeFNFs}tw7;wH%$jojqk8+t- zNe)ireUhA+UN7Ivtvg2?rrzZA(llkk;*(J5XmyS|TRHh$V>s~lLbIi0j|nqgS+EBM z`9dtLz(=+O(p)6CI7ieVmd0^0NE2#Fn5!dk`FwcO`{T`hgTqgGYypq`PgaJ<)+Udw zZ9En%a-vu?2bJKfJ^FczLgbOu;o9SMl*szn565#hq-;An=G-~#$f8HFh5PLI6dd&IRj z5uQZpb9w|!KY?DXTi^LFi#gc81B<{IT#llBR4y0MK5jf8*h?#;1&V1=N14fX(m z4vxjgPv^K@*Me>OiIcfP+xijNx^)!Qq?`2g#xMlI&!t@GVFRaSM>=I!y64r3ZKbF2Z~+=Xrn2ot$B?<}Sk zp&dNocwGv%24m^ewednAb0qUI(3A#y$3S@B7-;_({=PBB`^S*?jWORphPZEx{WL|p zY3d(BQ-3#2{X=N#@207L2u=OnH1!XmslS`1)^we$`WD!i2*2pmD<{3eMp(T&|O=v zVlNJ*E6fS%owVk{I_m2fU$3s4?Q8hG@6KEeaB9l5SDSv`TKYw4j`B30@1Xf1>ziG7 z^(c-!Y<=sIn;y&`;$-H)B>rN(chdvE*NXjKT61>#2`iY*tK1P zjxiAM+0}`A_YtoA?+j zYQpdL+23J*zeAQavhe;Brny->gnf}AM(SH%#OFa22ZPR9{TY)q4Qvci87DuIhu-LT zN^S;IGI%`w6ZYA?1+`BVIvo!NPr=iwy<|AR-ouJI!BxBVpRg;L&VtgwT(w^srabt6 zPdE<~XJO)3fH@!h@r3d)Q5Gh8A((OA1NM8U;@Kbr$7B4C>CH0Ep>TMhN7=t=&5U#r z&sErG5hEOY&_~`*p_0RFtEDlk0c%D;Zq7xMPZ*Gd|jx`5Xr5q`oVZ24pTZb22Z&4 z=>Hq=k^Us1-KUCVdzu+iiwaU{Jpn^hUzrBTUF)X%@G!#kwDp1SbMrlZ*o(b#YK@!6 zZttpBYcM~*3pFatnmWDORcqS)(E63lsV{}pwiOTRB7sIX&GNCB4hEoOz91RJ z8X@=FI%Ev`{VTw4kPoLYPGqAXhvV90A>u+I@4QK0h>x zNdyhA<6B;P1ZyE%>+M-xARm{^qSlXFe9R<|;vG>Yn*xhP6-ILIf0&v40Y6*wCar0D z!}C|Oz5x}ECmIbGlF5LEBpS0hbDhwp3Y%8&KKkY~-_yQnNRDB-5zWj2xqnxGcv?0( z$5C!Kj{ov=s;BFkh17}KWk5`Q@^GRyGtHwk4M>oQkI#=CZ>qBkYx{`kF=HN89zzOtK z`<~p2f$Xcpu{fy(uiKUZ|Nun&a@weHPG% zoc}9$(U~YWlyt#f5GJ3CUp>O%GhFyMAS;l6w_SZP7x-DE(i)*cJx?mXcJm@sEDhG_ zq^8d-&dDsDlbM@SBDauVfErpd6Y3v6GMbK#i*oA;kke-VoD)WS&VsqlSJe-p`){xN@Q2415=YRFRyDt!%4hg%>c`;EwV`{?Loxdq3Rp|? zl3ebJah6x`vx~9@^`#((wO>1n4<2dMPB-PXGaql{)Dz!&hyC1|YdTc!22aa}&$Okv zGbaEa@|Pf=3yV4~1HrT+6g1nYL;g~?kKXrq>3wK*r&q1o zuXcA6UULh)W(@D|_#gjd-C;2@i< zTpEzGkd#E`U&)u*nahsWfT4_-hN$vH6yGAXxNkqX6^AdVBk8_=;@h0Jx@nxjWH74f z0UxIE$a4$ed+6QuenZwrFV+-5ya~E66es_ubOCDik~zlquZX|72Y<7Oe`4nahe|VB z5}rtXc|3S%6@3)jI~VF2QJ4eiz-!Ora+=Is7+q-AuApnXV0I zqijnsh+gm8edoyNyidns+CUA>x(pdDqcc-qalP>8YJg;>4t~J>{IWV?Ojxk)$>xQdJO7^ ze>>hx<&_!M1>X}i1&&LSBepfRtms<(#!`EoUNqJTTWdmxg1<@Bx^+|U^-_9ezUTHA zNiF2HOCak$QUg(DJ`$d9oE5kokzp_#R+jhdxdHRz$Y?P+P0pn-`$C4d12*XA$$EBd z`f=oZs9iN~PI(@B(Td~7uNAjevF*t@hwM3wZ8pBBpXR21rap*71r{RA$h7|P!|`(T zS$17{!}ljr-=?r{K8)r1|FRA|4F=Oj>-S@@r(}LREXE7>kuNkza>RXw+P21~0=fMs ziEf->N%SD8i3OWKAFRhM#LZkjog-Rnu|G4l11!GywG78^-R2kPQ~#E7G=C=_ljy=m zT}iA57G+LCU(d<4(6r(51TN1OsjIL*nb0fyJtH^C{vH!^$owD>e9?c4)#OeZ#^dx1 zhe&QGiG5D#!|k~cd4wYzaHh0!tR>vu>C z#j6k=gnQ z7U6sbR>g_Te0<+j&n34%bFa1V8tNw6*Vjb6W%?loV{wQp$-Z=M@_Gv#Qkv{T?aJ%G z87AO!dlfL4gLK~j{Gr)n*E+}4WF9UJ5T(RMx8h)p7qkIiX(e(242qBq~VpN2tJllY|2wwatChkXnzt$58{cE1hw_VCQ&=RA=~ zsU1)>Ah%c){UEOEJ7nK4IU7i^vzoKtH{$q5(%75V+D6yp_pcP&pZ85^rnznieCxEo z&pkaAw(cNj75vbh??!jzZ(eui2kXxK3+N91p*!D=?##b=-4PGg9q|k34*H=x-;M5w z-@NV&57wRG7tkI5hwgkgx-uv&Ud3blW$yiQ1-0JF5N-WD)<7r zBmdBy??ZRcd-AQ<;vlGhIZ$`-7toy_d!yfv?tJt0IEU61pf6BYfPU9cO>$3xIOGoii1RVO*Cy7p z=p6-gyVjHJ`a9UO{(_Bp5GdR=mb~Q@o#!)L!PF$9y~63eHdSeWLS+WMeYRDF(iZwyx=y%!eq_5&C6pZd$({zkvj`Q0=la<(cl^0^ zKEJK!YIpf6hnzQOYvZ8x@Ofu!vv0No{Eqo1Yp-10W|R&!ff!cZ?(2?m)PJ9h1@-Ol z)EtW})TUaPRPYMN96ede8ngjJ{+M$K`S7 zJsG^?_o6&BvS-it-BoRt-Q}D33UDWJ-?DXP*RA9|x6fTm>ollz4!F3c)+aY#(>K|B zR%NGeg1#}|D$vhPyGcY+Oqi7#h!1LZcWxy5ERxy_;! z3$tJD-kXeCw*eW5h`+by!@b&D?knJT957iEP9-{>Fe=^NkinQ)RCxGQ9{MD?$1HjK zkm36+)Fkx4epR{Gz#w%#zwh_{GF02Vzbv}b?1k~r_;&JWRl!NG6bJP#OnC1 zI!A`6av8xZ4DTe~X7!}(zMYD94{|$XNaiYg<|6Y39{2fKTrdgHFue!)pB$r%f5a%? zPmD7D5u<#C7)8#+DCxVHRL~qaKR>x0U{#jW^YiDA+xIFCw5!ZN8U%qjRx$ELus>z@ zpW59GdkX!)8&QV{`!$)QcO=Cy7`}4p{YbS(9*6Wg4}b8rf5V6O_W1B#(TDdo-qcBa zjqKkAJ1_>ETBKL`On&z5=^tnD`C0rIJ)4rX3Hi4I)40Ua?Y;)O`*(fnPEhF{zYX8I zbCcd_EHXm@_F@iq8iS0in4ZDg42Z3%iJm;jrFU7DulIDzdLOOD=G<7dTd^-6zy0fk zEVyI=(~9`*TYoSK#`5}(vww81V*Vpn@jc`!=09>3Uny51Zp&5hGv4w9e=E6)Z=s&( zN3P;Uauwo_T*cSORSe5>6>^fR2)>P6#qdY2;`_-}48QMO1=LBZlR2KN6BWj^kSd>-QQK#2vIdMRYtgp%!vHA6BV_ z%)_V7KR!mNlt+kY#_y8uDBpLC@Urgbgw=_> zamV;R9~<~(D4}Okyt6JTY$}H1(YwA!XO}LG)~z5~?_kZE6nyP%Z*(PZ+ZEp2ooD^x zzCe??Ie^nY^*-{?S?6Z;z8g}-=y*SL;|s^iFLB@h+*g^Oh~W|7ISvCgmF2dINpOoX z^IUUrE`Dk?{_QXMdX&5&4)3qDGVe>5+`Zf@=*_R$w_EPnngefLCqClz>eqCvDgCvy zMuy4iKOu(XZ|P3SuchlrRb67z%xUtSyln^Y6^Km%j&fuMgkrqapY*rZ=l!j?a!dTj zb3o%c^N&>KvyDX``)`BTk5s&naniZtYYq4Xx61lW`1=ugmtCJ=ExMzQ$JQPf{5%#z zGEq^k&IjFXzdQHqd@)}$=$!{X7Wc0by`A&)R5140Kaw}(3+;KH8Ea9_D*KK&vrFmT zS6LrVqc&Ff-Ae;_Q*R4C>G-vFO0RiDuep!M<@ADmvK5n2$hl|V7k@|Yvp()dA1Y|x z%2qJc@_!g`|MNcCe=8fm6SR}JY{$&u4uD>7{c-xvdY0~S?40Zw9>mKe-c~$&#qVDz z;b+oj!eZQAG@NMbci~@~uR~?k9_+vc_9b|3;eP9UR-NG&q^-D{w&EVzieHen^FwGm z-$UE^7o@Gco3`>E+R9&$w&O!+JKjUv@fW16znixH9@_d}khbU$+M+$QMPHD%csFhF z9@^qBNZa5L+6H@Qn_bIfHIRX}NGzpol6MXQHO(PCzFY5KL#&p>y`H;&onOsd+`+F3 zKiCWZ73V*R`4hcWalg@K;;v;yj%5YGetn6o0IpU18ZOJja#>zc2hJ6j`8fIY_l4;p z?vU4Le{z#X;%n1rzLiGvtu&gy9*yLkG?GhcB)>L|##?DL-b$nK>(R*HNh80MM*eHl z2yLYi+DaqzsdM44r^QqbhpK=(N#RT@82oAK87?Vl0yVtq_BxHD1}+W1R46 z%wps5`ml=PH%=oV=GiaO4pe-_kUQ1^1 zE}6kwWCp*Q%mmwICfFh~K}KeLkQv`E$PB!9=1Y6y2ADhSp8_5}%)OZ3itn0PwSD|L zFiUc3YnZPxPXsx$tuWE#bzlzjx(IvkAp6;TSMq(hLhbb)Nvwyy>KF9TSj{AV-x{0T z6$JL6jl`S|CU4?J-|utZk;EMCwf^~${`n}Ii%w{!`nzN4WL{tg=4@^S-2)mq@V#J@ zV16j)OZ#fzbG`F(dIw|UmA}^>!Mr?)=N#ms&SmbvERhNMb!1|^MJC3ZGBJKNneeyB zgkL5T{%gnt+9DHZn@pfrkqNv-CUCh-yoxHn%c4gzqJCh&$rT%OUek=4EmizrVOChj{)Pa>(B?+PX&K zSFwlu-LdU3$FBp^-v!fu9hj(8$8k2#oqR{Hrf+zQzTq-`!>^%l!4`cBw&`2&^7=N} zj0HFj?bT$14ijnhD!ka@8xG6#J(qudAsUEVX|U-Rimye3c_|G_ZQg76ge7@|m_=p5-0RG_+!k)+1o)g^!S5@{1;l(WwS%uigL0oQD5XKx z1|l^;1sWtZsOrk!X@`?`QEtZH@b{A6*>9OO5WyOVvTGpZXCX)Id%N>NNjuM5@A+os zEcqRIYZ{}3#%N9Bq@HzUc>b<6H&ge@*W8Rx1vze>L(cBiX2#8~btqcvPcwR0alQ1f?<} zD5j&>;VvK4v;`;h6lz~7>-fSk1)GMsxY z1FryXc3K`G-&d5MI zkAf_w-`gv+)(L-tne#gtXLKSNdu1v+bu&BPVjW2`4@b$%Ve%c;s6-!t1`M{3ChMA! zEY0@lWje3OJ_M=H5iu20F33E`(*&uRZ7iN2BzKRyDOCAImbWG^C9qjSmb%MMw@$i9?v7?`I4;x zwRbqjV;hY>$8$bU(x+o8YdPn> zt)KG&tP4}2#)U?#?Kqh9!n#nHzoA(<8f3p;IjOu~D5hm-7u3qw`pDn$QC0@{nZ($> zY?XoJ{C(;Cqw~+{8NHMTneXfMK9&K@{(me3$=Lh$KjZO=d-v-*L^69V@%<~qjQmII zyU*5loS*wp+HG5s^Tfq{`t?0W>o_`YyUOGa{mAD7e&e+tALF;nzN~4U-;+=9nP=A3 zq%CWgk#`L8&cLtbJ;86!9ww(tF>cP>!I0fYiSNhF`gAYC<8djE#~VBzzc`QmG9LSz zJoaCj$7qAcsFcU(MR|l`R0IgDpT;g zgK2!m+}7DzU{FhQJ>7t_NPO-n@yihN%O>gE;Vue}H;XhJTq5V>-G5RV!230q7m=Up zTxzl0;WR&RGwSxPdMV$FW4EJorS~Og)`p2LpvaFyOcy4pF2EfSus&Y0QCE(%kx&26 z{kyDe=HP;i2DzNV=%&`|r7}_&8)Rj1?`@vZ9szt7gXs!ntv5)-Y%vtGzCd!P%|2fs z+pZ`_$z2ykUm)8j;|rju?vK$5uW4mU;UcfM`TIN;p_yC%Ln@h9il_nMQ+OjKKg zSco0G4Ky|KmH7T*iEYrx`gf2Gpn2kV!Mwn~(7Nk3>wHdV#m(t;$6!5t`?M}Kq*|ak{vorDC1)6l{oh0)RbXx+S?2c+4 zl}>m}oc-33PS$+k_8j;!$4a2`n7QmMp7JNj#ocC?@x!sXAEexObFnr`Y!?bJ#8or3 z9}+<-le4}s3sd@s{h7e*BG86^U)v!JG{^oVqB-2lbV^4bmb5jxS<)qa7!1NGWz;km zWqi0H4-X?uPg@^Y+tKo7uza9&Fbz%S>3fT4J~!R%ZJY(iiQn<^VZY_1gWu_KYZo4DcB7}k zVA^Q?eoROA9}^uc{SEZwxchVrycjH>roRsuA}#u{Hi~2cC+8VK*4R3BtVV5rThi0x z!3f4E^%;(zjyauA>2Cu%%F_ep!g%!C=yY)Wk=~C$2A}RXzprb2Bl$scw1y{RLz^8r z_GG>Z4WM=`O9%elkLxND8r(1GM}M^5XJqr2qxs9+S4-xfwAA`Q4w81;a{I?*jiWc>dCv*>FWEUV8H5_ML=F>r&;$_=TWU$?tA>!V~*!&w5~II zDV`@aW(A%j*kdg4JX>G(QaqQ-c`ldmTz+|;k2iTfF5&t3Re0`~@!T)rx&P8UN85Og zN_dW5oaeZl=eUID_~m&XZ1OxP;d$^HJdbL{a^JDT?Ou-Oc(j_lG|z`|{YZi5nA^QP z&vB-1;zfAQVq&qB=UCk2ITl}<=a}2F0?+4h-AtAq^GyBF%kf+;{7QZQ=Q*4~JjchfC_i3a~fq z+hnwQahjL;Z}Hi)oD99RZ4=Aqyy3fvuQBHmyB6iP3v+&9zfCTm^M*~6Ut`WCK3jZV zEI;QLwr76%oHzV6|25`ZV#}iZc45vh?5pAOIhWb7m!ETqpBC@6=jWWYVf?Ha%z20( z0u}BS9xSIf4|LFi9LC^wx?Vd5@!Ik5C)sG{P1pIF0jAT3o8@5CqNjrobPDSSYt)ZEMCkLWC4 zZtmi%%za)q_j&2u=Py3@T{)KA+~rr9`?zfGdJ zt;6NE4!^Xm!`o~fF0*y7G51Ydhs$jpera2`C*M-Ab+0k^OZWz~CW$_$lYMow+ z=1@Dh86R%iIQA{gEy8_=3_il>ZD6W-e|uX@46#bmEF@tq(K*O;PeW+lIbjH_Ff{MYsYeQRu1q{S12csNq$KBlK@U>eI<+)EFxM! zKRA1sIrqfRUx`r;gx}}yP^FXx@xA#@T2B@KeV_SvhdOCZEXUW6&UL{VB%&Xc(IAAk zB)p?2Z=*1B9yz=&l7DxOX!hNmg=tF`Uaaf*;EbfIA`CjCtIknb-JDLGqXg%8Y=`Pc zj>qHx=6OyQ24T~V?_!-y+k|#}5$@o>hr5^#ea{8%bxPg|I&UrvNsvy6r}2B|HPZa$ z$T??<5?W^(!CPPtBiQq=0b7h<%U=WbJc2#`8nEREw*NI?k0aRVYrys+*!XL}MiK1b zYrw`FHky15*g*t)_{CwvI{=hSQBCBv(R>f$z&C7p|MdOk#kp`INglkH1#N$6Y7RX= z@~m*CVRFXovd3*av~whq+?z?zl+K}cd`0eI?K$X8Oo!BY|M-oKg>Y_2o^+zcZ{Rc? z?U!@5ZiL#*BAqi_yY={5$lDntx~q?f?Ws%=f7>OvU$qZ?FU6?y{`?(}1!>2th_6&H9Ym=|R>ww@X9lkcNV}DZQv4S|~ezmSfZ_?gMTn;XdjF7+0q!CLJbW?&i z|KRs4sg}Mu4CiX~uBYqFk@SU?3j4LpAEb`c<$fl}&H63#h=*>I%fZ6)Nb<%M#4hmW znHRXE&U=heP1!p{hES;t9SYO0g;$cPEU4b4L8UjL z!)DYkqiealTflCY-RT0~z1mf3W7}%bO>8mTQNiXCpG{_MQ94GYw|bMl=e4Vid$xzp zO6>;ivOBNg%x^N6+&%c&KH0nX9hdU+x(S>uZ+&g+o4}m_To3r0=H0~9u4L~- z;WR6`uZ6FTNnd!QJ9$&l)T3PD=3TB>?T**9NbVa{F-mO&oKtibl%AX2^qeE5j%n1c z__<+9u`v7P?!9TVHam3Wz&F^F`DX7opyy8coducmzD}2#*)zHH%B=O6PusN?S|962 z*Vn6{EnPPihj~brZD}r(NH*Xa7niMi^g`=d&1tW8HSJQo=xdgKeS}x-;QCr=O3bTc zJhhk%QkVCPWe#MMkCBCCTsLQZiOw|Fg?9(XJ(`Rg{EcyOaa=hWSL-gUqrQ%V>(zC$ zeGPpb>)f`erbl_#SZ@Iy*n)-B)O4$Vw8Gcu`nuhO-Z*eZX+Q;4n+LsP4|2s~FFuEOU6gb2 zFB{wNNPI7dyb=Gd`;^OR)@RDf42tPi_D%=vd!=*3-v)1v_pdgH@*ipCB0mmO9lsIQ*do*N>5oNG`T6@nvIJ}aZK(Hq?Y28 z@x!Fiy);mtk(FE6CxV!#0B<9%2v`JkC;T$&ytm8vl#gxFvBoLySu& z77p8*CxywLMfMxSx>r(-=gMvdQ+_@Q?%1J&DbMTlCFb7Sj7`k9gIN5gxq0pj?iGeS z&X%)QTgNFm`vrF;Lq09xG0*vA?}38Ya@YMsERNlEPY|4;%H8YaoY0N?n)jGZ#2 zdPbMI{FmIJ#OYNMKjmmw(6^nmN%n~nf4fMR0vvuvR7TG^o+jDQ|M+`)t}QbTuZ2nL zud2i{iOwZ-&Dxu7I<>wR7mnnC{tVT(zMs@zI+~$7p=5CRguT~`fEXk^;<+f@F*L(j z>k!PxF(ACrBx;0w-{<%$UkeF!oKNk1Z6?$jg04U=1adpJa}FCy6yyiw8}t!FJ`?%D zqTNmMT><2~cJ+Zbwb-26+P|Wl8jf;mV8^!R)u7HlX^#$QKVD(=U&D4T7icwS81nCB z`M{MRiHr8Xk~!dgbC^r3y|f87X|s3SB5e+tYnC>_=gJJXL0wgBVp}|+ka;B6B}1Euh!>< zVJ!gI(4U@Q2kd0_oH^K#Ok5b0{*L$jj`sZS@A-Ya=XZI}@AEysi+g?_?)iPP`}bT- z!2H-Jj}+`NZWq?bjdME1JXEpnd>;+r&9PlL$op}a@5Nyc9ou-g6Nkwj9N>K79vsj< zS!^S;69+hFx(A2xUL5wwV;jwP;vnwFVYnBEeKP6qlS#jb!%lm-qIe@Wx6i*Q#=#cZ zZo?_F;kleEi=}2B*=3Wdk2m7=eRJ5zl=RvX7ai9LNiC4ra z*vQ@OizTYhVO(hra`icE>_P0ELp7NVa{E08%wbY}4!F3Vu@5I)S&sso@of)+;eQT{ zaWxq7=fId(gCTwnjA1nxlj<-~b)HwXIRUE9^J*|E+Ner?6pMu`*(Z1_vl{M|Y*Quw ziQ!(!E{T{FwuV9CG`)a(cWP^D73TqB;U%~$H z_SN`X$@cK}74^0ve>Z$1$QQ?XpADOl`)v)!&(`V$Lbd$(B(6b;^X?j)(JtyQ=&MFU zexAOdt7%TG827mzNpoP?b0xd?3xdzi^UIleBzd#!-on0If1o1%X2=``>f5mhdu7{f z3P1B?kc&_{A{%YUOtN%MGKnA^R0~@Zq^pF!ffDTxMgLy4XSJ(+IoZm&f2hZXx_GF2 z4ouojYM!CiUB6nNMd}9a+&QJNc9qsNB(>M@ZfZ84>fi`};479+Aop3RP8sk98?QBU zIbis`@6KFJ2{qcB)85sz2K(BdJuWUASB}OF{>HdL*|_6q+{HA{r)@lPr6$0*utKfb z=}mJwR^02`V_P=zaJzF1t4g_~Vr|{tb-0lG+=Kf@{%#lUa%J4-)o>Rp;l7dg+lBk2 zBJROv{&i>jlDzfK_NZcezhe7w#r7pR@15=E72Asy+Yc+YFUgnh;qOLXc@KZ9wMP}( zm*m=cJ+|pk%5;az`EcXhX;5kH_BZ-ht5@FakN#$VzjD1a)a;bi{l#@cx&6BWJ=40a zs`%30G_3(YurAw=>%9`*9bAtMXZN9YtSY?t%zEy8yHYQ=opnLldQLYvlMDVC^LvmQ z%*SvhS5eEy%GNe1WU~#DD3L5pmzY>d8OtAj+AI2L znV2NCnTPlWL1n)NSMzI7CBJ6l&VXIGk1OLYSHpc?33ssy?!(HsPb%SFtTou*z8YWK zxSDScZ^u+?Kd#um8gJXUntu-O9aU>Ttk}LHe^EvLqKf=Q75R(u{FOYCt{sIM^3OhV z7T0L5`{TdaAN|e#e&sWBBG?g)q-WK0XF8&~dGt9rr8W4U;ok+H>EBg_hs*8)+GZa+ zQgla;CvcxmA!b-NOlt<;llN+we}<5+2IG137VNgMviIebwIS5s%%`F1`81^Db5&g$ zq&^!ushn%uTZg$j*M>eT*A|_zM}OmtJu05DpRdpE|D8Jlwx8Yqdv^kCziZ&oI|0n5 z>s}Z%Y-(1oHeKhX70ph4v230@&Pf-~<{Z8kc!=+UEBP)Pb%lrT1s;NXwY9uhH+Se> z;32q+m2t1Oju-3gD(nRw*1j5FaYg@oqkgo)Uf^NvtML|B^uaf3Pb=&N9@f4Ze^EvL zZq%(-*b6+YeSyCrN!O0tx$Dfi`Xt9+DUVZfciiXpM}M<_<$D1{9y_hiu4ZCwl;*b3 z=jFDNyFjY?cfn`+cRX)U0UjoP*}aKd?PGkOpt diff --git a/impl1/synwork/s1_impl1_m_srm/1.srm b/impl1/synwork/s1_impl1_m_srm/1.srm deleted file mode 100644 index 21e843919adcce65fc5e045e85368e2df5150c0c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 185049 zcmZs?Ra70o)~y*Ff;$A*xVt+92oT)e-Q7L7dvJGmcW2}7?(S|II_JNAdyKyK)N8%e z!<=i(^^IACk+9$X=Rhc`sHjj;jWJ5dF!;}wQQummahGW$RsZMm>+7$&ja@-I+NZW} zFchtgJb4giWA)FZANt(NG}bs}{FCt{kwMn}$-`mfr$@_r>pvyeu1@*&cy7m|fYW@e z08P8QO*P16Ga=S4@$qD44x1z0*2ln_9)fRn0A0PGuo;S@3SEH%YDdLXIjVRZGMYXx zdRg1V_Q6)I^1W*pcRzFnmi5;%)7aG0?mNnkISqEKd-^{(IS+I~hoPt*Pqh6GQ?{J9 zAoF_on^K}Lt0cE`(&LXa@?7_{8dY;U+v^D{kImMzZ+eh9)N$FC`&Q9r`1f1xavKPF z$2LMOa71;P{F_+S3}=doeHH?sechAQdjc&`IOV#<{a)$_`O5>{&6M!y%yi87ptt zW=B6*rOARU9~e5Qy;nAb^h+gx7wiIghh5r$GBcrdMx3RA@z(6OWXt1>e4blpq>Z-H z=-0k-Xxskp?Zj{x4C{%wG8>4s&7~o25j(a>*h%s7^#(gw8o{yWrA6EoX1^!qzZYoe zvSPcuJ4INs895RTtvbl8=(XD*;9Jd*Q9R+icHaF`n;Mg3NPf z=RhN36w6PrGYIkd#WrUQ9ZreL+bVwpiESEBW#yo^dDbmX?5;AoyK zg@<}*w4YvIVlCY;=<#f)862j##Lx~&Lh`wxM?t4FfOC(5EHAtXY_x)SY4yC7gkC1< z7AGghLmQS1�Eu{wH(hN|xKo5>*bENO@e)xWRQVyvm@6Bun!+c>HvN2sBUMZ8Bc5vhXD9Pm*euM;dRhN6+dS1v2fH=J zEQ$^+n(V#zbdcm7s#uLS9d^x=(uW<-OO~uA!S4iXSkbp?fen%TglMJlboqFZ^f;LS zS04Ueko4hgMtHjXq+DBh`_Bzy(rNCWNq0WsvM62K1h8Q2yAgMl{sWks@%24lc)ED9 z8W9b0FOxp~`KDaI-ij#Ab4bgLewIZ@kUXL6VrLHo99{K-DN??S(DvO%uwY}e(WANb zo$CqIOZ<{%%1`o|iNEm((R&^6S)i8na9pH3CU+V!JI%)OTfTPgmTnp;tXtiHlGC&f zx!Eh@69_L2A2#6_E0ZdSrEHVtNV9Tw2{v+vOC$D>j9T{b0U%o0Oi%7_wHPg*xNqlB zzfhi=gv1IVc#prWc{~V}WK!}*U{wlaznfMUb*5t`NsU$~bVu#` zYA~`a{&8y+vIZ~*O6^@~Fyr|~I*Iq(zO?j4S~G;cf7h1qQ}b{OXlKWETS4%IPz5@; zve<@tbreP_#KL<7qT}wd0b=iy=oo-)k}vR0J7$^sYye~)kXPj_i-nFIXO*#ijZY064{RA&f6vX_ zhO!I1BkPkK<4pI7CvM;aRLMx6N;EnyOiF{C^0MFz05CZ@3b-I@SOIpxIe zY*7+nca8yV4%V|$6SiXDi@-KCLzd~090lPUIjy}QBKEt}dbRY0Dh{&;CE>C;oWK_@ zhD{UPYRXv`q##RmRKbaL4ka~*C!YA-Wt4_9Od}Ro409T7C2*Ag5GzUbX61R+mh?lB zT?ZsC2wf5~TPQtHQ?Mv&S6_w?779mUOM+5rr>}KR*@ebxp6j&AYtE+_Ro-SQ!S6|) zM4J3(!iO_kvtX?&wbmtVr1h5`#rj*Ii%oatDZaNb^Lcz=N|;UUDS0I~CC`~Jb5yKu z4}tG?y6nDaISB4)jSun?z12+bjY^Q%qx!k@mR;>U5KQruu1E;pKlar}$>wYEUcXtz zDOzm5r&iSa*$UoIyVq9f$~tzOw>h00h_|*=VL#rm3h@2aiQ$uOy>N-@t3HAM+F^8! zl5#zo=~;M3CQUOM)i7B=l1`3|}$ z%>hXW;+;EnRi;cQO=_$DJiK86siydAhO;0_5?MtI(sW!NcxKh|RdE?B`WEKg2vka@ zon!E2`$rxB`a{87YYnmbmi|pCULIq3?TlIP?^Np(A3W&+rAM<;1#=kVT zYL4>S+pIH0JFWLbHtBxJM*1*@@Dj4ged_x3HaLyb1W(I1369S}Ka2X>^-`4#rEObO z@>?oQ5Z+Z`>u#hbLyK?ocAIu}N!TG1Uheh*J{g|?JYK`?_%G&8k>417t`~d+!@cM9 z-wwTg?Tbf?X;ubrakMkp3EKoA$1)>NH~iHYjlXhoy)asOR$$Tl<%c$Zt@(>^Uw*zB zJKn7zxcG!tm2_(Bd)pDWQBDfPbK&Fx6xnn_exl?p;Z^pdy6JS$NN`SY)Ugy)i3hPK z(WTb}Bfvt7KFXF)S6+JZ$I$BA(jug8bF@=SBl)$yAn#TOVdPgsm|f)8`xSa0r^PbQ zvXs`*FF3(VYyfdQZ}0a_QLm@hE>indf4}oWJbjgMFV$7TIeD!<7pIRN#a7GgkT2?R zFL7UYEYC@(8W@;Qxa9iN;<*x=y^F2qP^(tV$2~&-$Q}6{bS;=qg}=0gAISfSFp{(q zlcRMEQA!0DWheVok_G z77kuu4`=u(FrIyw3y>)*uqxnv#+*5NeTg>cm#d^wOlHD*!CR|*WHe@91e6PP%|GFZv2Dp zsXo=UXqlzzG$L3Efy8>yRHvOqL86uleRG{ra8;C(L?eA)=&8 zhI50&ZhAq3)DHor93N|aH@T3|4JyUdFLXzrM&d}0 zz_e+>kO;L!Q11~)2g1E87yfLV1geEk8&?*14? zu$hyVWNI9)*3bRx{m}$ z^vf_7&C>xNUW=G$fM!*D974+HzyaAq_WFGYh)RtZkQvBozb*-*c=qmh*HtIc?-_8W zDtq7!ySGkUs*JJ#Tk(Cn0o+dP`+bT}(bv-QQO?`iM}5s|&qGowuGns&>ltFtW=wse z2*KXZaEzwmu;V;z@MD=HG&*C+CTkFh0e-G)>=QyM`VYfugbIyaW0E&ZZx@q&I`S8?)g*V#ppu<*gr!Q%0KbI5S^`e|Du?dn-cuuvUj`Yl-C zvJf_U$6yb0abobz;6gLgC4@CLNjLRZzpX}LZLyNS&zR$|2QJt>W78E?@QJ9TIEpvB zJY6?f>EmXSw%Qwm#5OKA(~UNzSl9?(R2J zj|{_|rhPA~*hN^~*x(u)0WG9f?VN4Wx`sXoAc1(vuLWYvfi(1lgxV7a{s;m?lP~;= zg10(7JA;gdd=A;j#{wyjDoL+`71UJu+7l@XCis~Xs}I94yD_6NCbZ*yvr@0hAITTp zoMEjktvbtm*i8;r@I7n&Ud=bi&0K&?-qwb2W}?vJ?*b4>HoJ}5!-IKlcnt8?S;SeV4E*{iOXAEzVm3CcHkKM68KLRYh3mTD21LsChz+@K#K|J$Eg5#&oh(iy1 z@e%I>r$eLwJ6e-gB~b9R526^Xp@_E@hNghevDwZu@41n108T|dxAO7UMW^{-n_KhE zFxFN>u-wX?yZsas_WIflhaFZ)+tQ{zeOHiFq|w4PWBXEm&g1rJ=hKZZ{2Kx_B*8;m z3<#qy2 zsrkQ$LMHqYZTz|%E!M`Wa?WwFHf79qDfOn55bxA>CM6JUtD{(sO@D1JsR{X3i`lZb zRz!%kqBAU?))l8F@nUN%=2pDZzh^imc{K>t)$NXQ*Ek7N5{{E(%e__LM}943&+MK@ z|GG&90$E|SQ=;m~9{7A}%hJ{#{nMI0;vyUlRVD%sCWqHMOlm=lqeeDE2QVM9@#VP7 zGODl6>WH1Vi5e0juG2;GZ4JNd;pgBE+eTkct3wR0e)%NV$CxWagt3}i^pJH{!3wbDcj)5c1UXgky`t3RA~?lGj-3AXUF_Ssd%-z}@T`Qs*q z21~gU(CZxG@Bda(pXN`?oEpz#+ZkmOta6#Co#dqRHn+7w)CYp#OZhBZsg|EG-`y>! zM;6C22(IU!P`v6D0yTP+Eao#ur11V4n={agHj5%TRex|8Ust46rn=Vu4NaPS=R=2> zhVMrK2)neJ8llvg$Si9v@%_eFuS^zMZ4#|voN6Bni*qoj%eZ%STB^w0n%e9dI~5#b zHy(Ng!xur0{EXi4MD)V`F0gkAYS?>~Ih651dtJg`vHY##Ko<_u9?5XK9_|(^4hKme zWLQ!&Sv~(QUUL#kw}cu?SS;D_S<9;9E}HMGQd+U1@XHyQ{-H5|t<~0o?tkoB69o)4 znAqyNLplc^;7MD1b~LoIy895l?R`q{D&l9o-e1GH{o;6^UVb5%xS&j@Ph^}vCywoK z6x`S)$sjvsP81q_Hgr4KPk3*&_Bk-)ZBp|(W?luooWRvx>&&>}5JqQ!Zp+gVIrpWb zaAP^2=w_wvKFQN@puLo)qXm^GJY_`nn-7P+v4H*9}pv4KzOe?WcYPF7C1!Km=Wq5T_0!ABO^IR zp8^gvtgHwjY-=Vl(^eMsJ&dkzOE=~0OBc7_ZP%`oIX}F{)B2LfX|<9=C!-ddPpe2Q zZAg!3=PDb2amd(c{;76`3e~{0S{j^pl*#@?ib$Q;Cm+vQ=DxL6hjg?hEHzYELl-2? z`n%h0k~^asc0BbxusK<9oU={b@re6bl$rS4#xK_Kba;C@z0>r0LPj{flOzD$y62+i zi8bj0M$7M=Uexa?x!(5@%bVa_k=YmAS1`GYCt;=bPBk{o?9lfpF59M7)+ z@MV*F)9s=77Vl{z)ZE%#JlAwGpaHXG=EJq<^3)u8{r1@s#tDCJ^OE40hO`MiDG#B+Jm_vxx&D^?jMe#QPbm#03XNu$^MfCF}Y4cT+@7QS4*36MIEZhqO40WMwBNoF{(l(jf9JbKjsH!oM3rm)ij4^=i-FPWF@z|p zJ%1Z5{iRYwTk%u2K^7}u1KY+A)RfmKA)?iufj(M(wi0`JJHa~5wP^Utgx_m=^DDUl zud`EcXV(5{=i5iRt~~OeHSaQd8h0FoAyIn_ebOveh{!T=DM6gi1kx_*u3G>8{)Obg zGqCIsJV#b_!~5Cxo-ta!4nqFknO9LE+4gT*5I(oHmC$%N0`#Lh!~L;G7i>L0cHh(P znSxFk;f{1>HlVB4)(G4Bg7{7e+*bj*i~gJ*fzR%NRU3SuYtZ6WTIAD&@jYAbcm~jG zeB$=v?9+g4o&SFHD$OkN%jJTx?AZ-$;9DdqX@gP5DtLH9?~T1VQO=K!eLF!MK}@j6 z@ylEMi6?DrasOViTFKS1S_sBwbh+9%qu3t;j!|k_sT`^6&+YyG28Fa(>$*hNjHjC7 zehpL8L&fvRY^>W`UuoE@=6xJ^2K7{}`W0pV{CYFJ)NW6SHrK~~?)FV>+t%$*%pMKM z?{s$@VWZ^Iefg2!YNBSI5qN$LKV_vy=C@VoyA#imUKr)bl~H~e$X~_qdJvf58?48$ z;=#F^LSC=2tZsEgN3Tp-I}FSB1{t_+-r4|h5e6@~Ow9~1#&o*uXg8rhXE&LLJ(klc zP6*$^M{zlXr#Y$Cy5w}WJLEEOZ*e0@84*BX;gOi6hGJF{@+9HZ|wI4RXg9 zHLUSYMAjY%WU+lCY5e9WGR%=tRA|``Qk4Blx!^?$+JUT#BrhQfztadKNMix(9enO| z+<62IhPylw(}VN@0X*qsXq5Iln(vfQNZZ`O_L|_@YIz@5a2%XhrqBn+rR}SHCfZx# z>3{4`+PCD4X}yv{!u65$#P5hCy5t7CgFjIb`L*QTd8(Oj87Q!T&X<40Dm>+?MF@z} zMTMTAmdh^QKar17CwzWx5ztlfnpre?aq!iF*AtbG-j?CN5)`vRS~4%D4jHuMFfHP& zp0yO9;Ty7_T$J}ANcanHYplAORP6E3uItKN`l4>5CqAIE*HdxYPbV}bnG zO=`dtTkLxwDt7LL%C1gjr1D1%NzN>`nEcp$;HaZlzalCAN72I~aCdrsqq8Nm!r**h zYddeFlyWSG$-7gK{XWk{Wqq<2HSl#K3g1Q&j5Phb1wum>rC|+%OhFxU|AUD&!m)HU zril5%7isVIN1Os9A6f!Ttec~r%5k?5I|CFxq%Tbj;)~U*8mR1j`A-2+)%!i%@)t|a zJ8EZj*%GWsGmjP!74|Q$$E~;AgK~%42{I8<(mTQ|CzjFyAyi$xj)dY1@o~xaw_q@- zV7m!YDg~_4_ipC^a_y!2zw}f*l2D201>t2M2F`Bn`@sBP!~u#M!S?0R=^Z*w>XXyE zc7Gnp{}eqbK93*pgtn#XO@WR4@GbSwRKEsFXf8U;qgK{EH z6jkn*sK$2DR>~FoO&$3`?Hv}hLM$frXL#&VWQ(o+3wPugRazJ-wo;NR@(f-ghReHw#FmT1AbKgk^|Gl!y zRMN}k*1FoANy)+5B527?ZgG=TY<~qg=FDaMuesopP1TV`E*E{P^5?EL!y%xIhfp$> zDiQ)UEphGmDsz4oDKzx=!l%P`w}Q)#I^yDT_ExQpP-~2JeJ$sYIl-2qf!{4cDf&`= z)whzT9TAB{l9)L~ic%9&g2G6~XZQt3+f(o$GKJ%0W_teNuwsFGGUm&d`n#0zqBD4* zyIpA0t7*$$9INw)xlRk=N*0Cd-M>XMfVv7844 z{bO3+h~Y!yG$HJ=ZA}GraBO}*4%*gRv!wl*gB+8y=`9zdnLQItq{0ijwe$%g0SnJ| zc61F4Z(*+MUx-QKrAE)_Fp0}HaNl)x8`KWs zy_4Az+)j;q-kbb!Py2eruXi#cf>?84lC;dsrFy^if?%wD${u<~MwrrdANiT7rbD%BL1yOp+n9azg3eAA62mp`EVo9%lVxN%8 z=MZ7d=&Iu7#Ceg)s*`WZE*_=x_Uij&)ck_oD0>T4H9r`wp-K^@watBu@;86Vzq$?6 zt0(OXZ7T7T&sO&BrnUcKd|xjb*Toi>*_M(K#Weo!!xFbC;pUS5(|#}o@FSccz_uckqe*DLL>Brf@9u;Djjti{yZfZ{ z>Iy8cnk6e2`Nf5DTb+texaCybL}}BfSZeF4SnA+_Os1_EO4iFH{|E0o&=D} zy56N#zQ}6sh&q_)Y>r*zv`sFPL*Q!}V)KK|VbrD|Ph_PVn!EH{4*98y2zhJY#{-?+ zS!Y)({piYvlI`Bc1*ls7Pxj+(@s9>d&d1&KDlQ6^7zuRXf!qG)p^cc&K8M|+QE>UK z58)2(e%x)~aAW@<;*tNkc@Z9cd3uy{g`Cb!B_$9O*RE&2b4AEvKfK=mZ(f&;{ats6 zXFnpq_6EuGQWJlSmiz$ zSAkD79=n|I5TV!?eO}JkB;%%Vre61Y`qFO0WeRjrl|R{lhpjBo*>%|I7Bl&V`vrN5d`7yeLfvdgr#9%92__4M%ej!4VBxXLX}R^G|{Nb!=y zNhozyX6t1q@b~m?n9NdW5l=a`>uOM960?(2EmgMK4~LRn?xyB8$OEYRwslwfl;i*8 z_dntH|KOS0@yvGXOen#}cWM}>A#|!Hsd3=&;53Q~t#Qq=VIg!uR0Bv;j&%Nbem)W< z)N8WdTpK>m0A!4tpm*Fgnr?iVkXBCUX?N&>ivwc^q91@}Wu2(>htE|4YQBWRnRN*H z`&^3o`Sl_8r_tY3OK@O5D>QHVR4z{%CB3Q(>fDRytfu)_FeX}R(iMU}<;mNH_Hwbc zW5dXN)eXzQ{ZFH;=+X050khTCEkOcwX*P-qeypDd!nJX*DhnS<$2l&lzn@fk&b_j* zFL`$nwc!QhWFS^BAR`b-DPdrFGtC4WouIZ5jD}H#G&wy|L!l6GrfMN<^$v8yi<%>>kk!~*LV6e&$Mjj`;);=gLp0NJnh7VJC-%Jj^Lxd}bg?DG z;P1LRM3*F_TgHF^>&{>Z+GFZBqjBN(1UkAn$>D;d%JKVzE~rg)GZEWR`?X2fZh|A4 zxBgioqG2yF4$|W9Ws<5xuMsZ%Uw84(%F8763o=aaycvNH2@!F}B#OHXeI;G*m0mJl zU=B~!;Z)We{KVQX@Y>OYh4N(;Nzl_Zfh;U4{ij-p;24hP+t+?CO(p)=E!>bLwf=5f z{rt$E#?dO(_m3?L1klS72$G<)3|03H#%0hMp zd?@@ienT`@#Gw>Ym{Px*;;=FlYm|A7^X*TD!0Tn$h`|o{Z_k%0^eUb@F2YOdjwiiX zjeZ8IN7RMd{OAV1L|vWLj*RuKn~BqAiv>QDf{)ImVcQq%aX zM>UXh&|dJeMgGw!5UWniK6ecO9J^9v(Pw$dWP5z=Co>T%-AHmUG!}zU3sv;0nquXL zj$umdzHKwWLb6EFP95su%-)0 zIXK2`#jPuIOR8l%D6v+Ha3gS#kfDG`xgx9hx<4Y~5ubbK9{=6mu&g1+(=a!qC_IwI z6yJ%|q!rZQ9ui4FOYU;OVxy0dBB_OGaVnkS4;c;KTv8T#?c(U}iX5!=9oZgDEA?YX zO%{h%K}QVsje$r^MdOmBtk2j#5)>QBJpI__n&ofgamjyD<72ym@+Q4z(X!l=S*PGu zjK2b`Zhq@@kP89q*t2J1V5qvKQ6|4-6HzxGpMg(UDYrDrKJ7R+Bzh7hBI?sZIxR`w9qv~J?*8s)le7wFj=_t zR|Ce`V~Bg5^Zh(Dr)f5^JGGDhx?fPJ>bqs39VR_#hQd7kvAv1chMt7e{W)QsEPQPl zc;pzkgx#%KP^VL^wlGXtE3(0=gp79G&>bxf2fzzw=^VmK*omp z@RnAKhXf7H1y^=sOEGSd(@s2Uf`6Seu+`Z*>gm*Gt2dG+BiNCFrY2-!6``i#C6iJQ z^(zuczoH@Agh#-!2)SOvSgTj)1@^faUOuGd5W@lZbWT<$;&35=?5GxVY!gu<2T(XBujSZe^wB8 z{5?9tr!@A@3IqvcCN%&%D>bieq+O81&(x>II4GSJbx6k1XI6VwL)L2=6OEDSl{^ei z0*QZxqJLH(ulRCzLTRac@YTeXTK3F(tYl?Gq$dyBz(pTDw|5Jji7;zjDN|GgGAu(= zIFvQ2)Fn?naQ~j6()Y`@a_=yMpT6q8k=zAL86r0jeoVnBk(ZA{3T;CT7SdGc(6OiT z+1GtJFdwybZ|NNGtTaCX9-eswceF}bPmfl&KF*_}-;*8na~jr8U5~R7Om47nWxszv z@7O?>0u4NSHo$tH*La_625S(4=5L%*scWKPtGUPyT;R9QUbOmO-N4NfykDXns-GEA z_OP)7I+yP&U1tQI|5<_mJn?^7!Qwww7&ghl^NiN_Fm^v!K1we6iA}1`u2~T`;2w!L zlhJLL`wC~cb>IE>*~FUIr>~UVWD6p?y44tX08g)yCf*ugYw7een-| z@x6mHGi6+IGQmCgQHaWo3B!i_5g9itZV+n0bvj9OV%*Z;`p851(~du(yCMAQj8r2b zKU74l@7~#QvxZNo!%K7vKuPlXjh`z+!qOd~svL%?@I}0!@>%Zj!4UHTg{<=RJ$(qo z^Rdy!c#=LBlNCz(;b0P)wE<9AyDm95{qd%MJC-1jf^uS}D(K}R_{h!wkYP4I{W02a z2;qM7>{P+~jr)fFreoo){Aa&c+v>$}qRclh=4mgekSW%twE1TQ7hz}>w0O#LSe1z9?7zQRWS5ayQj8cX4;=%dNv2X47T7E3Cox|X7(XG6YB#BbtMz17Mk~13Rh!S zFu0^B2i=qN(96l+(r^U}*oZA)Ju5w$g$3uGYRKqTQ2>L!Qv)js3Yopx{1ZlfSzO8z zxI(aX#!MPG2*~#c`lang4;byW`shrzBgY&Df@b%j{N`VPKbNoCgJW<;ze#K&yK6 z!EU`G%W$=f(k*8DZ5ZGQhG6-?kLJ*BCpYN?lufcSQj&zfPneab(o;*Sx=uv#zn=xx zF!6zhk{8h`>n7#Tz4D#>$2@}=`i@WcD0KDyHi z!Q^~rD*qg3!26Y)vq1Zf!-_a)g)>^_xlKlm{dLT|wvTbvxTGutL8$65{R(jD;jSCz?IM zAfHmHbqcxkNp(jTedqW-a>`~X!DI7Km5asAZ(*2}ssktWaunATV=LFFr3q~WX)zzU$WW-waAP0IBeENV?iZO0u|_R!ECR0-k*r6WiBA! zK?!GO9E%*ODy5sCul2TveWlzfG`OWzY3Lm)`xs&CCK=OA##XF zC8ip;mFA*}ot51`y}#{uK68+yfJ1ETtlFPb!?yyCmCm|v?f301LzJo3THA7t$dz2ywa;*`rMR{ds>p5{Le2W`^248p0jNmdm-lyZNeJ z3Wqk09Aqb|V{XnyzM00OI-HmVDmtSxzD0U$g-QnDt&4%;IZPTBJF_Ool2I;rVCE6xUND0RfEP}l|jlIGLqw*}iaS=EdtQAI`E3&Fsp`7KD% z^oP;r*o>|x1?ixcCup*~8x*hpJ$!m*fpl;PYY4na50pac1jHCT2v_Kybys6!pNmdko_W@#1F!dH z9UuM4O8J9zd)k1L0IzrC*FIl7!Q|Q>d!|mXQ@|CtP(p=oo%DRmMeYlnlV;+d`u*=m z?>Gt|F6Y0^v#tU$AHLoPslqWb3W^~PC%xiBV|G8iF*8X=-h$Kd>~go(TXy^}D<(TrA_4AQ`yMiFpu!Ik zx<2BETI2|$x{ul)yHbYl{O^m8!z<1?*6mG`#TukEI@kVFC8IU7UmcWR<;<`fB5hVNST-9!U_E-LGFh>1PEK7tr(V#O#(9@cXPZNty8>;lSF=Z&X9eKb zY_8z^-9bT<4A{JJ4fl0<=bUx39Gh!L87ufqH&?lrDG!80(@eguVLAMfIcFecd4rFO z#}^x)r-s9}Tcxj08(Z@XTbujI7o~q1>;eYc0^79=C756Ooq2T%pdht5qd43hs{Ow+ zBdBZb-<;tJNv;b#NBvoUS>-l^G`ipB?qSx}XSUKl>$)3vQr;xYJd0l?HL7;`=$Uwy zJ@!iZQl+2y&wEzA&AuSE^(vnAEG8@nl>3maee0EG^&^qECaYsKqaHCSvM!Q5XM zN!v)iEm$PHSL(A2ez<`M& z5^3Dh>U&M?c0EQ7BN_?V_BvKr=X;*ofAmgslA^wT&`DT&>+!n2o!>O6T?bt?O|N`> z)%XM|;@U8|g^p;mUa>9nP(J4;9BkRFGYSG@`Y z4Zr`kfdBtc3^b#wNop-P`hQRiS5TCTFuO7FFZeo#WE;4RhjS?!iCNdZf!(W)XZKv8 z$|1I&NkFySO=8!jd~V#@6VI9#e;oG}MW4EM&KkMyf?6^w+h&;DC!y!&yyr;9%>tEP zH7oF=+Qo-H#k0*si9htEF6E4#rZ#dQB==KA!(~=P1A;(*dJoFaqn~5=(P>nT;CIkK(6JfbZ6LY!SnfK&xy=y(B!=K)z zxdg>VAL7gYFpJ1sP0drIVXHW%cYG7@iR@5$^|o^pBLQMd1Vu=?K17$K|5yxHhz7n~ z0Zd7Vz?;$j@3W{Vx;Pe!e5^{@`KT@^9iD4p+t{0KLX_fif;(>DZ1y*x`}BzE;1RLP z@Euo9Lp!RTz+6bWuvl`p)R91g$8Uyk1P=z5_)j$N_Eoc4oVDL!4Gk0t9jzVWtzl-Z zYh@~ml-)D`_6?gRmGI=P4fwcRg`Y0jUpH2AaMQj{f9(AcGex1C03RuEO0;X|kh9yE zgN2$EJ|yg^B=swPbi?51*PGSfrX_(ri8%+H|BcH9Dfii~bD{93=+!YfjSxT4Fe%^? zLn;^U+50CX0c(-kP!cv)a7L41p9*XA6g99%bv;oYnD#o;o=vG{h*S-K7^DDOxHJOI zD@C1H^y^N$_Q;v-TZ-Eo+BpTYLGk_k8V(H%{%gFO>k&v<+Z=cme;CyurQ4PsrWDUI z%o4w8$*-4opQJVMKl&*(KXvMT2$aA-ic0hdsato4v`bMSXY4;8mh0G*AMTz%yRK#* zs2Hl$4b|=a{7d=|#{lZwfu~-X4nwxLxYG`OZe}FS_Pa_lfR;a6vVR0w?vB8A;eZb1 zZbnFnRa(cgu;sTPNTbV{1ncV!fJBT2pcVzJB((^vha-ABA6Z+@F6`D@;3^kT@?=cF zfy7tpJ6P8Ip2;<#Ju-S9$0)6e88qgTWGaTm=7>n;a1iSl3&Cr0*1!+eI?5b+0Lc;W{*(nXOK8oB*BE|4J)N|Qz;|*;3oqSg^JcC zdRZSv{C{vvUGHO^tI{8{bqe#D93O$*3)a))&8?69Xqk{0NBthRrsYlKFKeoPR76Vh z;71+Qu%b^i(=Lr)-H+nkE(Lql9ro<~fFqg*F-SFh#k=-kIf2gv`_H8Qw8Cpo^i0qv zobbnia9oS&)*_%iWfv1nUth!%vbrC{W~E7E(NrYCjuE1(X78u(zO($4Z1&SGWEU0) zg92d@CZ7)0b}w8a zXJ=Uvsu;vtK&bF)t%m?q=WSI|Yb(=B){@jiE$s~9a}o~qd^(3(4}2V z(e$T>2md<8-(TE?d##Vsb+shBI#`wTNiDN1>q9iw<-daK+m0tso&~eYV2sk=&aiGVvxt%@dYc#N5}I_O_h7>iOT<@{~vYk1CcE}`w?BsFnkM8j4{6s z?2mjzO}X`_;BIh9rvWIcE6qMCjnog#<;VmiRL2>BwQ>=u1e;}>_`=jeFnH7(@I=vG z-ed0=0rRSC)cvnU`drI*o~c=v9U*r5r=-o|!hu5gOg2Psg9H{*W!rJle>AdS3FY$S++^$0oWd6jXqbG`JL$dlOh!~Sy$|QSO2?U%wl;OX?&%|fjmF29KuJ*o%D&}-QH)W`a@GP zYy%8^ROe!oD07fM(?*ZFtVCcQ+S8%BQALTqtIe25sNl~Y*ThYi9MZFIvwy8WF1{$3 z2;f5t{Y_H&7?9t?8m6nF`d+r6Utc=(IcrE~?sIX;azp1vEW-8K+!J8*2pKzc9-Cp< z>QYe}XqSyE%klk)Z3`UcX}hbL=`41y+%r=UlkCoRpjPESG(-W)>`}9FKbttf5G9C2R888RZK@{#258&;yIWLzl4O3Nhr$%N3luzFGcZyD-Q&tcXJ1@Q%oTKZ7& zC+~n*&FLdibDsK7It&{_74sn3X2zFZhE9Bx9^L=dvlNAO?* z9v-~rG=8?yC7r(JNvmVk7IXwswdR~Rz2sbrh~TjC3(pUeJ^uOPi!L-FBK<}7!X=+|6Z8lYIP8=g^n+~*nqOu|7sVXx zRAU3G{HCR7+1KA-jZCsUW3pav`Aq^Ov4+l@0`D>_Kle|9-Hx)>7v>Dip2A1`7(5PM zpe!Gd=CL!457oTH4!}{?f~!rP_{x5W z@9vC!F!AX$-((S&I^e}?&LQ9R)dPD|iQwGuJEbsS! za09UUrl*MJw7U1Dv`{41^WHLcv_V-O@fM6vha!9X+fb6jnB2)YbnJ3^a^9RED|c_F zck7(iKZCc9Zxg~zwjNHqEkJWE&3-HZvZ0{s_r&MJo-Xhf;(O;F%vYs0`Y}CFv@2Qt z?psq=#!0a)o!3V9cGgE+-GpKst^uwd;o5a6r`DW{Ymh0DrX3NY;P1WPY zb(q=F#b((C8l2Z2_ONV8!aAkkl{J4#1&a2h$}$w^?3h>aomISV$N>4==i-I#32SU9 z7IP9o``$oaF5h>7I{@pV%PT&sh+&&rwZP(f_~ht-h#4;~Tw~edIUDG^$n(7}cJ)+; zy|3R(Xs9sFg14o13}e-pNw1e_)uNRL6>?)Tgp^YU_UMUm%zR|TQ<)b_1H7agD^}W= z-ye$FP@2|(8m}3UH_~RsyCBju@kHm3NBEQ!BTYDlD&5Hg{+dO!g@!hjy(>{QyjRND zm)Am_O#2pE5M{>R?=>_wfz^il-%iJ~x>@2pS-=Td+E)qCs5;fMYG>&4U)S;>*)mP~ zS;Hib?V>JA{U`UT;JfE)8>-?W*(M7dy%1{e%XY7v@tdFGz^rZL-A}%Eh`7Ur??#@h zZJm|s=7b&I$Mb+HZaXfSAMYui)X_0c{=2E9ed=Av=&&5d73Y=t=%<~o!la2J%s$eQ4A`a$1W z%*Valrf!K1>Eb`c-bz)E#0wE2ij<1Uz55`rOd{6l$9|u&@j{Fvc{B7=yJ`Kc7z8&c zm)rID^;5?|teHpcX+nGTO*<{qYNBD~fQ-ZxS?q1V!=tri`fAio!3X_7DI1X|GT3Zt z7(H~%bi)0@|3b@gJdgc!+aMv5nL0KK$h?}wIb?ypBPrF|67?ca%T%*%VGWENJDnF@}nKC+GK-MDyp&lN0g z)~c`-fMyNt4~JWYv%F5*^yEoH6JWLTauUam&oO_NKJ@K8oyxX~MSJ17XlwTQD+2H# z&-=s6tTE_N7Ad)8#XzyRu=lx(shP7+_WA&|!zjbGn$~`uI(g2pX)}niY^lpUlkQA0 z@a`&A>Gf)J^maFCzg^L7ToGtjjBmD0LR|g#4$lwk=h;J|uZgFgBc_Gk=jZyYG9HcT zZ*W%2SB;Eb$Pz?KE3%o%zLlR=ysJ9kz_nfUmk6c+G>Q~&nLD3R5Z1+I1CC>H*IB>!JZ!{9usRy_Vi0F3UFY0om@)t}dwNCO~R0EDUxs;)O)ygYWazJzuG)S>Yd(OV&Z$Ydw{!3*%#fiYOR?yR3e|P zEiIM{9zh%&e}0Z&RLGmIhp$|B1_sv|PM>-|Rxx(X8zo7AuJ;c0XT^ifQjhCR*ff@_ z{}x&(A(SU9dm8+UJp2QcVAvH&X-2C+8KM(ID-LPpn+ooAEu|4%2+|J|EYd&R1sr43;nW#%VpP}=M!%-Ta1vcUBQ4x z9zDv3jAi&{zt-o)O9Af?$524*m0zd`*B5DpN1mU?&s-u;&!vLvIIj2=jiGtYTGr`6 zzGJ8M&OQ?@x3!_$#oh2I`uaQRoK3v4X&U4KQjR+D8%j@n_ch&JkSaKpbB-iILaWA5 z5JW^GJ4KxrDK_@q7V`#yz;0}z%-`GCiL|npk`lqO@w%R9+|7pLw~kCXqjM*d>4~JO zDVM1-6lMiE${Qy9tZVK=lN`t4*+vvOY>vdyUUEKSAnacD4I0-?T8^X^|M{1GJhoWr zW&g46A5U!&LdCGXbbxniOK|MqYHe#q&MmkK=_9b#i{qkHxGJCMaMWq1 zcU`k+O6BPJDbjJma0K5f^Zx*VK!3j{`7~p@eA?=M!w-^Aqf%$plk-P^;%XN+U4+3xE?^)rl)Gm$*sYI|@#3P7$=xSKJTC8X|C-oZk;VTL zwqBLr?I=&Z=9>mN{BH0>p8BG@w#PHraF1uO{T`38QEaq9EzB>J%g&R@TjsKjo#(Ri z>V@7smt8EWI7;TSSz29;g`sr4;AU@2Z&QtbC&Qsqfb* z=P{H1YF3Y7ka4Av6Jy=3VzAL&%1PvLz@IEuTAEK@tQ6{xInJ%~*#E{#uMsOX5i#hM zn%|elHrDdkgQxP?vc8BlmU3^tBOF8w~Ph)FsFSfMdUTkT*JbAwT{{PO|<=UV(jGJDg=HZ{l*UI+~ zOL%x8zE-d#W1#ZVH?0?JX@6Gow? zwoCcBZTa2bMY@KO(uNpW<$7CVWS4uhyX1O#II*p>Z(?mnanzgb6YV07TKj%^)sOz1 zb$01$yp-nb!=}&G*`+ykcIk%PF5Q;f-Tx3Z-EZ;D-F=QtdCU4CDeGPDv*w>G@YB`U zt>LFKPIK}N>9=a^(&ZYv{BMQQ?Q87r^S-ZJ<1zX1&CW6MgpXOv<-ItrSv^nUZTD91 zcM#Xq!k}mGM}lW)#n3$n2Riw_C-3ZxpRB$v=j?{D*3PM~Yv2--k?7>b zN2_!Fk-lR^EW98-N>|TbQP^VTm70ZbU~8qmuDxM>U3=@?c#i%4fomMzVt+Qz2EAF1 z{Qed44?hIHc2ZlHuIC@pZ`anPIkk1^hP8F8-0x?KkKW>2zJKGRAGoeAU8}2WKUG)9 z-7a0lNP9z!ta82Yz{n4~Ka_)$rTw8itnDI>dc*ypUBpqV`$MaK^iB7N26F$^sHWAb zLBAO9s)&Q7Gwsf={;T357p`1+7M{$5ftINEn)qUs7HQQ$C>G!4j^)~f6sl>9pqRRF zSC+pJ<1}pl^Xc#$+}p#^=i%4(9^V@!dmtRv*W?+mkuAranUqYc zr(`)fm)0+!ZIvgUe$`c*)^eMc&{@e~@C$*}Ik-&z zfT!;4x_|&6GqSP)N6h8&oYN$Q>uQvuyS0H*$RImCGM1lDKOMm+L)@unTPeto=b?Pp zl|Lyzbv9wo6rPl;{N>5yfj>MX#>O(C+TeMaOxk>jOir2np-fI6uSd3l^G3Oh_|YkI zc&c3|>+Ad|6SH^a0jiEVqf*HvNI|67hWiPQvhtDf#QclN!^ZQU>>oToe{6HJ`AaT~ z_Tdh?6VsA2;2^Q2^))`96fiWG2sno!oS)u~4&7n<>t~$J-kyMjX?-+M;6b4?uWftoJE8} zXMS$;;yKW=O>4DHD`D~+<&lyJJ5_RWrJTyzr{HnC7-y3^54v|{=xXK3+M2kw(DSaq zbyb`-l^X^fAJp6+qnT?=Y<*E!z9;`I?;A5E^07W+1&uFE^8>2yuX$_|7>fUoDDho^^d>wX;# zKO1dsz=M(W1ylMdEIZ0R@*bFk&g343ym!`*@g^~x;$Xf;q0b5oMUw)B-h|nb0_Ok4&=2@6S*_ANvCz-3ayA*)aylCrRIS$oa)kx*KaOU`CGIFh+`h5 zyu+c}J_5JwaHf2JokYq9v`j8Jhf#z9ZKh3$(?uJ=rB1ZF{K(0S=iXbBdArRYpxxf7 z%w?O_q|J?FK0=v~W-=eG`-jo#cgfsEdAk$6oL@%*VrOZ}IYgZ<@OGIWxylZ2CwKZ{ zxtH6VLYZzVcj|mGo|U_7)0(uowcPtD^s)~qBlx7S4B(!=%%11i*umyDwhcz^S^H}? zcJL}TR@$o+CGtsOk+ZJDOB?CLhZNMioTneUZPd6n--W$ZHecy!U+QTIJziPytLdJ6 zB>#H=jPbaPD}We-v`Cxn<{*C^9v)6NU576~H}iF}&E2oVQ+{T$KB${VM{aq>owWCR z+W!Cm0RR6=D@o1CvF37c1poj5|Nrb=e{Z8WyZyWQ6fIO5s%W{iaS0)cGy#V3+_ymE zmS|P=$|}$#aLqY!Z0vcl zOX5l>{>HLQ-C&s7O@b=KKd+@-cSL<>bsuTtK2lcBmd{fcJJY-z#qv3}QwM5+{AT6c zCAD;br#>0k(nh@{em*5G##8E1S#zZ>aigI&G&E`(fon@?*gUWJ#FG!H9i{TQy{aES zmX2iEhJpkejNeNpwL{0F*!K2PI41e3ZrELw8Ncaj-2Kh}ZK9q{ChBj7YTHT}t9GBE zWjkbg=y}0#^g;Ghf)rKF?>F*jcPi5~a)%V|`CCO5*Qc)Cbvy%4F+I2OCu%gwMAQqr z>C`^QpGKZ(rx9FE zkR;OxkDL*rbR?($C8Ju}97z=o6T=PYP|+49VGWH!hb@Mh(lA*Q!@ZrF9PzrO1}2__ zU1_L^<8CcV9nCigP9+I@O;T}Px!bjMjV_pKHsBR>HRx4UUzknSfcoHCBs)B&L>U)* z!=@&Q%>DO}e)MsZvS-zWOucjLJBClY@{vXdedwjiExa#}q*Q|}Wosg@`qH^WvC-9h znRbo_{o8(Dnl>w*Ln6na!CoRS8t`7c0N&-E8xTi|9E<%mJN`UQAk}qK$cceL`8la{ z9i7^Soe~Hp*=~9epK=XDf_DP6N8oQrK-K{2?bY}(X^%wAasK*j&BpXNf&AG`jno#` zH}|CCI(v^AWNJ%J*LOthc?1Wtcs8k^>~F}GzM z8WlWaeDG~erp6iMM@Z5(FZV&K`7+>XHoHYWO+O8(tMTK8RL zEM9<#>q+&~17g9y>S=p!om5G6eo}9f)9T6mL`orNn?1&$pRAkx0lDoANayR(9{>po zd>%kPRV-Q?%qtfyCvxas;K+?d0)261RR$uDi~P!S?-Y9+PvTvviK!sfG*##tG^wh- zDf$F3s-=$S6QzgxW}n4|Rq_Au%6kU`a9`X|Br^?^Wzn{uw@Hf|foI|@)$CsNRiODpwcwH`+vCzC6+`BF& z6LAje-;9^JLD zeomDAKqDXqkl7F(QlJ&};kjGh%ltq@-Z|J|Jip}6f5+Q)NMsLKCIH;y6mqZY%ibB0 zoIO7{liZKRz2K7I+~w~|1C5+<=ux%FOnPCWG7}M| z&-TArgS#72PtfuF>+j@6*)nLFG&9_~^E2Sv*eakkg~j#1b)ZSOaXpWxNf4?hzg{54Lf6zU%l7$NJy= z-9<~D)~0^W=^3v^>pUw*g4}f z!CbFApi9JgpL8AM5D}k%PhZC5aO%-O4yZQtHTjN6^Zm}O&UFPp2gE6Kj30fFfp-lX zr@>Nd74hp*d1$AgiQYwy$FOW^HSzp+6c_OqOarKm4;-HQp6r5tI`hwhJ-7L>xEDky zb#3oF1>HiH9^pKNjLkhLnm0V3~659K5&*ek9B83!h23Vhymnogz{ z4*@Uy8Q`^uDS7`$3w;kOtk(|_GebRQ#F~BECxe^2<2p*n{P(Ya9Cd_7zA&DSld>=A z8Dt#x8RM*5#>%DfQ|IN$?wEWz;?LkY&ZXSfb$v3GCx9~^8(gDt4^ZfL z2^%|`%jtQL`nEShc7}_f_K_L}q!T;h<3IR`z6FqQpS%b4rvgftInhe^jdTTq=}Gv?Q*TzkSb94j2p^m2e23syP4 z_;O^mZY>^vO;XP^$Y+uJH*;AC2OecxD7xdoU+RtLuOarciIL83bm0 z$bq2CDep%~Bc5;mm|uh(E&L05|2|Ow9VUPR+~Gv6BD3rx&4tS281w-K>*BJQFA&#^SDXnL9SmEpHlUXj zp+)0M<>L7E2nvP%xxA|#f%6R*jGPIwMmjSoF z1lG2Wp$*N|_^axO`Lmvml(>lXviAE=q5VqSBk(e!NXL9^Gv1>8T3_o}_UNJQfp1j! z2pXOeihFSfB_?8VG70%O<|W6=YAkrs5aVWgQXV%e<8rAN(NC)vn_ufM?y>kBRo+KS z|NN#O(aY(_ml%Us=DL8-$NvMLCNT9J+^&sTKZ;v*`}jAal;M}wr|Q%6srsf*cU+&U zzoI@JYBkSAw21e_cK~GwOO(CLIE;F497cV@IE?!JaTxWd<<+-wn16{!)t_@529Tj- zeohg7E}w%{jEwifFkzvYC?sUt=D-T=$;TFf^NfXajTYC92gfS$Wx;U^e*a|5pJ0Ye z35BooTE#r}&pxj5qT17wvUW@M?vC-Vd%UO5;r>5+ya@y~AGS1+UR6Cadv6Qd;NL`& zq_>LaZJd(h3mJ<>9kkrF0cH$ce{US5gfT?I-WW_9OTthQS`QBjJpJ^Z?IpQ|e`mOC zccHaX8ri9ApXYN#_vgv+BlF~VZJxZG|3TboWGG9WyZKDoudiVu+M|$jWr8IGBto#M z{p8dg2JdVU!y>No=ksr*a}MjmBOsGO^?g_J$Ql1u_v4u>l`sXe%RSfN{V*eIpH~}p z1JFbUq!9G+XPz%s_%ecN?pho6< zI%VHe%pK<#Qw=fB5wb8e6?npOoTI=KA3s!gXZ)~e_nRMjaX<8;^TtZdt@`sgl`GMT=NOvlH-YgZ?T{#0UYkcw@G=scli6Hbq|xgP7hOx=SMtDT=p>WlRQie z9%&pV-}Nx@n}^v=4->yi4--Do!|0nHMt_Qj(Yc2Szwcr6HxILe9!7t?9)|yBBuV<} zV;*L*?qMd6dYDP>VJ3;GCjDfahnc*2m|gWSlUM3tgb&eU#%B5>9!6Pt7$x^G<=^|< z_b^I6_rlCr&%YPn@G#1ohuKjNqr46e1DfiZ$9&`ZTFg^!{q|s~$8!C}=SnzM7?fk* z@%tI?3h=^-2 z7c0-gzB})dj{~5bPx5g9&L_)w*{L}f&^n?In~gUvdFgNCemX8uS6re#iA(N(hql2b z>Km8r9+#-UFqb5oT#`J>CCTGllDu)rE^^5$nOpfGE{RuM5Wloe&dqeFpg}G$1;*!aexMcDemrUNcWcRpa@>;p1A3iv5 zl5>f&$tB98Tq5R7LZ!bpXR^*E${UyLBA2|P`4aXVE@9bxiB@lk^^KXfXl&quEq}+d zU1PE9t!wK1vb@1|mp9zn+0gflG(Ciz7uVw3a$Kjdl zrG|e9oHNz1Y$xgK{jEx&z1Y)yd_GsgwHNZ|yM*f9-wn;a?EkFEvfkQ@hmUFv$ir$mx}Z=e5Wev@O8 zr*KTN8{gVHQr3sN`W@sMskz`CK>i%2*q+L%R?MNi+If{{`0gwxe^DO#y>QMk%2PN-dGjxC{^jSNf7x8Wy}aiT@tw8xGH+(zW~9>| z&yTEG{OyJ^rm884@cD?W?d3F}M`ONkl{%pP9wQwc#S^$k%;E`Y=f~0daqv8?`}>gT ze5Fk$_5+I%i_IA1j#!`UwqjWq!>iWjnt?iBGZ3&@UUR;=ZQrh|<-RPMGo)U37`X7z zQz9LlTI68fCMV645*I5mm^?M+T+Ur9*adDYcj&~!#vZYZNc}YIpV9#YdG4Fc0C+u z+_#*b)~nV*^|XCL<{N!BiTluJv57$IC)?Ig-Q0_8ZNIoXdZ$EpV!ybD)?bA5Wig(R5V&`VoJ|bi5+kAGT z#B`tB?MI^&udQ`UsmfbfTgD6T+l}?gI%2&t{@ZBi!*;0;#X6c{7_z>Zs3hTiXqCz) zdH?5S>!q^U+8k?Tuf&?ZgeJXs42?k9d#jM+m1XgLqW@-j(moncV%)*X(z%^ZUPh<==kreeiI* zg!|R^9Zc7m$cd1vi+qQ#wyrBYF4rx?>zw1Yo&En6=Qjr;s~ZeG&BHEfOVB3=^K#oK z5K)PVLJ03_;+gAvPU=p=W50~C%^atyYL??R_p9V(d7i7d%6g7d8@;fzTA!kv3`mw}i&+f+yR+(?C^R$7Vt+_A9UOD&a_i(Q0q=~ zuD-|H7LNzgY26~H)n$JQto{fGf2UvL_%8k)2lJeb<`3{}zFxx`R+AzI`%Fy)R`arP zDSnHx^-@{Ah<#C3@CZ}^37#Gox%)?B^q@`VJU*?{gDN?_&mS>FX_z3h3LQ2~%zGM& zP}D1Hv-|lDA)fDskngtWFP6~J27j=EKbC97l=%Z?aagQRyTKo77Q?Hubw0*@wbGa4 za$O&Yy$AZrf`9D;U;<0*%X%=s*H5w9f2f}j@27IyZ}yV{|2@!8Vr^?4ee(zM-qx7g zh?`A**rJDv=Zx1i^nE?DMS}nyH+drFtLsD0=*h-jPYciwe9fV_x8m$gO{YMQM2gUK zYkO26mC_oc*;@XTt@Ff2o7)>}s&qEiRJpZU)`hi-5w2(0L%7VTAFXS?=VVP}i>+LHgT z#Gcl?K99!B6ZSp^p>;ZMS5KC?sMrUY=lS-$N;ux0o8!xSiEa9<_V;}j;y!CI&$U3O z&;s{xHfi)GklWY1X_22dd{nkq8GpuhkA;>VYq?LvKk``BtiO6Ga2-paACi!NKU~)L zcQL&qEEM{_v=8l(KIqiZB_HRSf6=K*eMS>XcvA<2CgN}QyZm5Hf z<#7cZSJv{7wN<1t6Y{o-0+8~(J;I2Y%`4sBkpKDG5pzl+XWm|kwU(mi>~qfd?dD^= zM7F<>LH$c}P_I4EF$eqYr)EWGLluJ5qGGy1WRe{)||OK%oY zhxM;IA@jQ9(!C408#(S>5IW~f302eK_xEpU$jgfv_w6E?fG802;fCe=i|?`anKF@!t#@Ce3>c6Kyk9vIm z^Zon7=`Hz%8688mr}Cp99P7FVP3pg?zGE|Ge!4t99PyufgWF%STf%xj+p-S>mXV)( zqv`zqXMT7)eg6v?WUTJ@Mm<|~^m^>pZoZG$&(oiKb3VO4d=G#Bz0Z_ty&_Ky^iX$r zxwv48?*-inTYWcku_#%^Hx z3!h&({slMtES3Gjb#<=%3&hYB`_6Go-|H{Flh4%iQ1|`2fG(;v@Vhh416PgQ@StEn z7=2=_#s=t2pg5z7$`k+2y`!ApspbEuv|IM?l#b`Iu`^cn2X2rvOR%vwR=J}a)&mip zGw7qwRL@OH?4km*F$-!;`7F`BGW1=u^q4a1>q;l_nH#y>eK=4vtjkSYeh|5;^^iTe zE}tm@{B{|#bCWx&9|l)0_e~S(eGr*-_UP~Zjt}$f!UX&NqN+#tW{6||h^axzbw5;f z9qBabEF_)#D$Lqd2(>_;c_jO&ChRB)xHm3!R}B}e6ZaSA36penoK z>NwP={CJe-`PS@Pm$dW@oU%n?lPQ;Ttag2_FG44Rbvp1O z)}ioD!u&{G{av*|pWg<3ZX4qHZHVW!(f6UO+f@_fFF20@utbz4zLZ@_>FS|eH=OfD zzmwoQPpsdsY15@hnh}3;TZ$h5w!LY}(`WV1>vvc><>I-R;cS}v#nb!Ov}H_r-sk>P zF)r(Zah*G%sg8l{kzSD}z#Kli?V2yspSXG#&R%l?tb)UD=pC^AQro(4q#$VE}c!zw&JK3|}@lNTd zU%3!+otp2@T6Z7T9c4+W^3c2Bvn!n=zkF^#>h(3%G78N;kDj$Im!FZ9-Ai_v__}A7 zx=%~?SXsJVmONgTJfm#3uWSHi?YB03hD`64uERn5?$tst?b) zl4sr1xA**_3^~lZ{N3)pwE^#oBv|V-vb}&sk?S2KOmY9|3VVM4?$pnCP>!9FJEnXl z>7*_Pl`o*}5;~9kDDYWVb$R5m=zuQd-xb}dg8%gTZWboy?BDLY-`%Mbd3i8q6%SHr z^*hij^3I@ST`+RE69B#%TSHg5c^UB;D5nnE7w39+$F`{Kj;_=nIj8FEr@Pla)GBrB zMKJC2955Ahuhh`NvABF3(uK+jV#sxhL3ZI-!>)Q2INTZQ9Q7ho`%gT1& z$)mU;Uym!4+xz;Q%}@E*4;-f~O)RfO2di>CI&d6w!9r#1_T6eMu*9;x%0`ucFPu;} zx7w<7m#>)rG1#n%>+YHVy*kIj4jAByuI5=eV2Nt;dw#sUz5kTvJRc@G1F3#@Vful0e8Hz;{&2SJTn~Z^-+b^c z#N>>P;#`Q-N>f&d&ft1D;{lcS2M3jl5D;sVks3;BvDKB32*o#*-d+}n(mh5D>v|paE;j0%XFPAS*@LBV_^719f$nwYHM{32C zSQgc&MdFNVC)PebH~~|drn27}OU3>Dr`yqd$d2#r` zg3D+6IGP1|;Ct+a@~UUESM21~aC!3bWpBt{;XErP=r8ogABzgB)%>1h8VxNew{&hs zm*xyTYCK@7J~5~$pbwgea|SrQXQSbKd2HXOpKf_kESDuq{L?%3iT_GPhl}g;<-qrK zzzaQ_#4r=^ZXtkJa4yj%6@ESTIJQVyP>Dmk!eJvXaXu#|&Ld2bl@dnfJihJN_VwwT zfou!x@k=f_VUH@CGe$Z(XyCO zt!aCkmY2L(CQC`nQ^5`H`yBeeM17UTlTmENBBccp*U;1HU^$$SimumVwNZx#elZfQ zvOQT=Y?po0v;nj~7eXtnIMwpLV2F=pg^!`MORMia{Qd^*uo-jp86O9JquKlx;Pm)y-(J(nyV`C(>Z*ayLn+t(aRBoaCM$WxPqPjEp?;1s9cA6W z{?+g7_<_>e$JDv$FK!Yxg}F`8zvXe%`^O<$s6{93FWx8Yv~#@cbLtnV)brg^=V(8m zf3fk4g1|9r8&CROBfpZn;XgXQ%M#ZX|GYnaH_x_Yx_s`lQbpfdzw@t7=U>pS&yE%W zkJO0kvrtz*GG%!hJoraSGf!?qXV!1dR5mVin!+lSEZ>ttoE^72Hwm(0y(sR z*#=fr_8F1$vaM5WuTiDr`TKP|A0)ea6hU89=IF|Ku$P{@+rE6@7V>wnTN<7jrzo(cj&Y76_LHulBE!&$GE=YZ4V>_MQs&P7VBn2;QK;lO^E zaMz7g_u!$Eox$I|`rXQ(V7?A#lZ1_cC8Wq(jW}aBn>xZA`2+NYGGVmo;zmp#&fa&f zPv0I7?2g@E^lBd2x8EVgrEi*tex;|ee*jgm$L%S2UM37s=}@Ez#2D0pYm2@JsUu0h zIq)6S32vIUZl*isK-rMbj^Cf|&{mc*lH2 z@(88&KOKcY7_~n44{4)6qH{OT5jUt00=@jJ@l%6V9O+yQRei>m%EwXf{&3~P#&v9@M-k}3z?DizMHv-dx{-Hq`MRkK z=@uFa$}2}_j@%Og{@o42aS6@%CUaiP->yJUMSU+ZRbVh~Qt7r&qoE&5_9Kct(DE!x zON;b`S~adT^eJl-0%FH#^jG`#aLVY%-s#`75gUCt{K>mUD0rITKItJ)SH-mbwh=LrQ=O7zF z8>I%w#+!?2^=!&-Wcz@n0s0&oofPzecgUBwF_C-$6Ui-n!&jR4d5#ZH)-Qc;_xz#anOXekLqxrQB3-absx%d=bPExHf z(BNR1(dOlUYx8ol$;(CU12)+#nTQe6Nu?VCHtpoyVCAp6KI?pF(FSSJ2HoQ2MDlX5 zC4@yYmTvNL^55a*AO7Oy{}EnJo{HyIxeec$9Dg@F;z9J)dQUU&Ut7mEZ78!u+VwHm z^&np;(jYBPQs1iN1{eTm1Z+ctWKtix7wps2KD_O*k92gJ{r#AI7+w6zY8ilbL2vD! z$k5&-#L6o9w1@8OhVB|0dls4r+8(JW(4IniM_WVInE`#z(N4``%bd6;$^<+m^-`{TpoSrZas+jx3V*{nO*U zw28QIx}};pdZ_5EAwQ+2OWkvM8PxGDxPFRvA>Y}xnfx!n!t);# z&&9XJb8e*c33%2v@vPzA7fHbi{U&(UzKCb-FFgN2@vMCfo{gO3mSIutBrUCKpB7`3 zCud9(Mke>P+IU{pc-DVqCHEI5bt`|&YQI*TO^lJ2HG7xaKF6DOSqf$6>$31{S`M1M z;{T36@!!ShmcLNO6f36tr@*4uy_|)CS(ZoKQ5U|>oRaSGu{_yl_yiw|jKK()vNt~A zu{f=_de`pTE5AE1UJL0!L%(~2O^lev&K?Nz^d^2>`rR|_ zv-_$|*_E%ciCaKlW8DY-a5E*q|9{u}sX9|6pQvJg{`fxg*`*hhW_W}-Ho6ZTFL(Jg zc?O?u$~AFRzEY}vr<%(n=vNtW^yxB73BD$#Q^pn;u>}-B3@w+j1r0W3-by}M$K}}f zpAOmd_Ty=fW^DQQ55FFdSVJ$kXR7xGa;=G5$C`i+g7RbE{;GacmCanKuV^BVS1~!D zugE@d)4j?5JO1{YD&GHQuP+^+owE1GkI=`CKfP2cKJn*`C!l-wld}J}F$P|0$vEDS zU%AXTCmInc5x}6SwxWR#NCTsa2I_nS8E1yNP&VZ`F+5nVMFI{ufd;} z&Ym8(vrqSF^6uKaf2GIo;r*@h6!er{IM~fcl<}*hRy}*{fqi)rQZLf-l@5h^Q7bR- zhW-KMLZGZ-Q~wlut(UCpnX>>?@gwNPZZw`PT zvaT8(1svl#6rBb8;%q_hle`lI!+lAsydqzhzrR&%d#{ZgSgSQ_Y=iaI zY+b%X&Q`JCTlurVuSacuz3l_K*-KmGY*NhQ4D_?qh>5hHgTXr9`Hx^fVE$sm7yi6_ zJ=>!{{r`&5MEWp@m7jnX<)_wa&1zp#Wea2}xi@xwN&c^FRlbfd_-yR{V>ZS4%|6=7 zFlJ5K@kpbn3;EN*sy*pv%6|8LrWIfKv)b9&9y|Lv@dW<~J6o$___aEQ-;8`UWTiR5 z+@CsbxE1&Ip^0IZYY3KTbKd5qB1MXlPXC@2{nu@hYVw{^Z z6r?N>BT6l5q*+nXNiB0^`@A$Gu+wv-V@imq_Z6CFe>i)h&dvJs>Sg4~I#`2k!?G}) z1hH+b^5ZC*$h5`p^&qucx8F`L_;miMGhLOFmA7%;5^^Mv_MFEAhMl}Fu z-AGfJFZehQmi6L%HF=%P2`1Tm-QTas-R!+Md1Vh_y4ty5kI@nx3@Egjog^M83bT& z$uoOG!3ow|%rT}zK+gfdU!UVTe94wCTNo+~m?^6;DA1iz@7K%RH<&9a8=L*j_FNI1 zDLL?n+@I*>vKIH~)(MTb6 z@r&UOZy|Z1Nn3WCw-C%t)$&JqFSLVmU;uZru!ql?gBQvx`vovx#K9xxb8Lhhjunx{sc3s=$0vcDKMwA1pD?aR&W0d9cRyuw^?%v*lR?7bMe zFsvqrLgpsLlXWcCHjV`U_%TV>x%D{bo#G60mA{bxJ~TbF;GI(1e=B;b^XF$akPGEC zAC4o?TMWR>X)XVAYFIh01L6z$oTOz0Tk4^QeT<(jdEYg zGP}o~iocCGxG&?+_~!UKib^hE2HB~Y7$e{dxj~D(;!peb9`>G7fN`etH5R^-hug!G zS28c0o%HOsEX`muv(QGXTfp1vopC=^F8r*N6HSqDHNb#(J zi#yiP3i>0L+qU7TwhbHFGKT}O5IpCql;<=xGNHkhjk{iuoV(D|jI2H`;uitNV?4V6Gt#L~TW^X}HPT zg*ja1?C#b54>$DLRc=^kmR#%0-M9^r0tf*g`fwemF>2y8>Su^SpRV`q8aou10BqSu zY1a_KXw&Xy?(uvzj<2;Vr5$jxVF$!T26Go@l;${h6=o(WYuh{9vO|DwT+5ECJj^57 zOVaMH={7}uRS?c685K7K+>{{EtT%ApWWL4Sc_9{1Mw3Qq5wl}b^?arIpW}VY2 zHbB~2kI>^I^H7~5vf+cs4S-N?oxq?Q9@fMnfE`OIF~lQs6#s4bA#lx)O+LMz|NF84 zZJ?GdFwJ?!CqA1Slu#V|etm40{|psLH!GeElGKU|D+8KGo+JC0mL|&prWO#f1}nA8 zufg`AYaarXmv$elbGF>f5gxU3gd6+MXsu}zf4#Q<3bg-F&!DNuHvKMIbyJ> zd{*m0`d?`wjK=od=6f3alYH+JJN*^)1F!Z0?Kz8db;eXoq~Bxc59GPfm2WJLfw!g_ zi}#OtB9Pz7d6xRiQ}`Xw^Kg0c;^iazOZ9oU5As}U;CV6Ng=(PbZ}Yq%9}bhDz58O>@M6;NVzBvBqgt<;7aJAtA;@P_()M!}YgtY}dszE9wHDt81)AWT zyni#`9As+7Lk_w_g=s)O1$_J)K6AwR>TEE{leDVN{XSpX*87g_>FCo#YD*h#HC}Nh z?b~L&E!~Ay4>O}aLk`bzBSNG9j=xu)UHJ0l z%HN6S$K|P2(ftW%O*3Kz=U^xK7ddWe5f`906MuluzR_o;OL zIo=OrkJ~;_JoCH42u62;?(}TGCkQmuduv>PmH{FHSh8(k_#PSALuT8b2p0%R&?&-P z@IZ7m72VmxLpzuh zpn8M-TFnnd{sCo2)9HX;(~f;R|Fq+O!Mfu)*cXNXt+7DNozBFLjg0GgdM)4?-Tw^F zRRt{KzG#xL?pVgz01uY2ISEV1xQR0qa!;EjV?3`Erm-jYmd8-2u7mE>LAUFm8+FjF zI)DyF7$4Gp=aW6ZUDqqH-qWUUqN(?ERj=INby+w35G=yGGE_%QnTpXZ8;z#7Bg&@s z-wtm;LaHTturrh~pkT zQweEwdI~x{1~d?ANncCBBPd;O1<7j?CtDvjjBB^Ew6O{w?fMQw~y}*p*Rhb@@I>*!=?Wdj52JJjTV+3hT1I`Itg*--M zl^+W9nc5E}eWs^1t+#!CwDS2;xpx6VBu3wisC4)Kaz$UHqOakaHi)E+7L8JA_cU}s z8#-9hjXLOV9dxG-x>*Oz*Y-Q}{-@g&eN}xsU6&F4#py=9RlHK*hKuq;7_vK6k+dh+ zlmZ<#bccTECP)Elrs+Z|D?xLau}`gBAVbIpvruSD!;pkcTzC z6m%aV9X7UNv;Ge})~dL1;PDwcR${|u_NNiKAL1t`wv;)5;~Y&|l(VxtwvC?*&$AsY z#g3klle~~v9*XT)4Vg!gp>G}Nlof`QRonaA=vyX5EOIagsxmurEM1=?T$TBP97~P7 z_>vsUu}oWz&89mvLy)Fhe5*6Rwm;2ocgm$`=VmfqjK=6E7T2eH_acPci)1)j$a>_N~x%N~<~Mk52; z`_cPkpwW_npkOrnUVq8J-?4nWJPv@2z7mZ<$M@^e|spW#{#(fax4~oZFwSZ+B=xKC5Ms zVdU|nvZ#)MspZIW18>7!S!D0vyeGEg$W9&GvdG@XdB3+Qi$=_zZodOOVH@XSM;6hw zEb`@@E^ZJmK9p*B$EFI(2O%-KmIGpi$L3xsyq_|;J#rM4t>n!mSn3T8)G|lnUkMg# z8A8`~RIC1#oLSKVUDE>eMdVBo4ZYwUG?*X7)%wm2g7@tu(w~~r!mosc@O zYA5bpu!*%0>|FO$nIHS$==t=F@lM`f%oFxd-H-RA+y?2BY~|nlZgLXHo}7fd&Ph1$ zE<9b;k67Z!^DrFN{plb&=d+{?esCB~YJXNyIj`lspQIT*C)VCGEhah>%n}Rr+|%nl zx`#6=*Mzpx4w~2*r(O{c#CuONY@k01;aJ?sp~}i{2&R+ znM2tR-vZ;5(X(lvYsd%YXAk08`OAuGBrx~l4xc(_)0_qW^ zdi#sSc#o#DZX6PQZ!^;-iRXc5@T@<#^#ab_(BwmFL>*~}H?`^C+#7i27to){hJI$D zUlM#Nou|681mPJ~7DMzCykI`aEb((?Up3f^9fon8;1|}Yxdm$Hg>KXRKe$~1DFPa~ zt)qrRoBpx}6B@owgvKSTsHzxmI43oMg-3RhJs#kgFA}^H$hRW&`}yqN$Lu3_WL|#< zvc98s;Mo9vASi~3`h=Ike_HZ%m#v!weEgBYUN^|IR)F8S6=`7+Vl#zoJ8QZyMYUEm zc3aCC)nSVj+mvhDG`*^_Hk=VM*zwyXhhuFY_r#6U19g9wV{zHa*Jb0nk;Gy}NPVrX zbzda2(sABXvMIZ81w`05sICKJ>YZCCNukd)iAOGS$%J@WBP4P4>__YaJ`|p zm#8{8V7m{?Yu6{dWS#%O1E01}jh zJOF3wr(B9ofvE3D!o{oW&rI(6l%Ib*zv;nW$e_y4(c$u{l|Rp2ML{voo%bHL z2W=R)K<3xZ&p(w!y7yhuNGvR^Rn+Nxf6HoT!nv?JLw*(tW>2SIHsS;xDLs{b6frGqHxNc;hyzvom@_WNwt(yQ|^6%mQ zu(@>^VM)?s)78DipH-Xd*vq;V={7%bQwo#%e9KZ$)X663@Cvg*H{n&J>f#D^aV_WF zTdU8aim_j;-FtW;URPQ5P`P8lqSs7~+T=dlyKjzBu67*CeOfn~y%*p-yDj_2dpu2tS;Js_E<&*Ut{urt$s?wb8hv89O_*810cxS4)G%x9jJGX(qf3Q% z%<5E($Ccn9AMCMHTdf7+-3e;~IV6C)2CjP}t0g*obCE zCr^iBoiC+U3_j+O%%YPDr%HY9b`lx##`yC0GW_>yRip4)627jOBCzCj&~kGu%5SX- zxx*+$zb4e#S3aSOL?pl1j%-KQU42}$kB09fmz6e>N478 zf$C+5*;zf8{8VS%)*udh*2mnpsBkFVl2asr;a?c0Jz9c9A6Y`uj>-`-+zJ$zI~iyW zbj@r_%uhiRMx~gnTtQ+r;u-ixX53M4s)Akykyp}Io9^e$Wu3MTD_H55HfMFM<;;?R zsvaVHG?^8LP^D>7CdpAVEOpZUgrK>c1;zs5gN9bnjn*6Tr8{c?U&4;~F*DF$ zQk@z#sg`-n#5!{_8WE!E4;_f%3OYb$dY-%FShdMlY4$g72?Pi|Fk$YiHxA+d>7p3c zYMKnv#jjB_u6@^xl2~}|0DktL7latTjkK5$$?_y@c{g!w1h_nw785S6=n={JlAP1) zi6v_(G-9c1sKNfYAm-XEwwU|(Oj_xOe3Gs@1$BYwT$KV|7Bb|siI9Q`7vZ-Cp& z6K%l#D7}3{@E_b6nW{Z8`5!Mjw#yj%o-EWZ8An|>nw)_%3nFb2s)~iuqA6Tdyf^h} zm*?tECq!P+{D2c){AlU!h(D5*}rS)--sUS!G z9r~ox2*sG+kgSFIQdC#|h z>!^L}f5xlWqIib58&B|dO!V5KU54*&ttvNi?)XZcYHJ6VmjhsyAg&eTf)s&zsHq92 zsi3>oaRlsVR(nPA~v`kK&z}q{N7Y=zQL?_}+{sRs}K# z^Kdto*21~$u<_N5n9nHGWqG?S2d$+Qbqks`s2x;#EzI?f94BI7<+Txp2R{XLDBxr> zJ&ohe&w!r%G++*x6H1~lRg2IPcHr#1U+6Z^%#rOWvroRB?cTd>zIcuDcvKc^*>1he z5HUbGS40v>Q>`l!O^YJtBYz!Z1m9wGUw5C9b+B`J=)t(x@{Q{`&M_%b)CyFJ$i8wg1wr6+z~Gv%!r)yeO$gYFb2Af{%p^|qH6s|T(G~$6KWKZ z-Id%E>eVT3Re~1oSXBJNDk>`n4lqSYq(L~+55E z*sjI+)A@crldRx$`A6aSW6Rn$xj>=F%?iO>pYeXAS*OLmjvSD{dxP}@7&iF!m29X* z;{mEP7m7_Sa(-(a0UYLr@Ps;K_vQR`IpRT6odvc<8Rx} zm=r<#3-SqGkpXp>5AZ=yA0y-bSBXT^*Ct_OPjhzS z(b~UG`&mwC=mq?pKE)z|=_p5MM9k(C zwUgM+tIOW#2-JbGSIqZ+{1ux9Hr2N6mT|hdU4=awcS-s)eqg?2H=DXglC9>wZsNYDm@&`lG|K z+b!}9E_7^rODYRm|FqHhrx6mat6w1r0E7UTI6gtv-@sm^w_>mzrYczl#J@YXSlV4! zaq(y>vsb};9Mq+aFFi*+nKmWls2@2TGJn2qDepLiK(w|vV7Vle!pS^`iC9uLRx1*c z4kA0RC896e1Y3%?Ak3Hw1jeer!ltc1xe2~)IXq(aeIB@Y4KcfV#$|>?vWBdun`(F+ z>W65+K*8W|B>g;Sq)=%ey$Nj2jn$DC=~tWLUMy4@N(mpxC(7ERBlCv zm1W*ggsbD}nai_hDjIZ@VRFy;Y%uqZMX%GRviwR;(*s{DC~i@64)%-5Kc$u{n~?SC zYJA6Ij$2t?RVaoSM08Tzzy2SW`Tt+y_+btRL;fFgK;r*32jI&%e2}tNA3i|YF4M_K zBq;3{>pT8%wdh6xMRHBT)@X_g#{7oU(fU^uADH<3C!0HqY?9aTUV$ZtIzH$IH_v*a zj%?r=ME#S2{g>1og;_q?Qny%Yn8v(?(%Nrn4HS19v@0HhRd4OHNl$qN8$x}f?OT4< zgNqLDwVY!2kQz>s=TH|Kl2(%E9DB2dmIL8Axws!etd>`$H=qwr_S$iz{&4`;h4`Gq zRxZuTx0-#}hvaw-)GzRvMN?cV2tANK?}+K78xz0MoasM#SqC^W;S%@_Xi5i~yGmW$ z2iCXoF76U?7h|RVK8P^O_-hFKC62vQD~*(FIDk{Su|+1iX|Zum&tnkN$_QR#=4yKgORQN-;C^i;A7uP=C|w@2wqk%&bkDQ?0;(m za&cd&gsouw!>Q3)ThZY5&HuYvfJ^^K$RzAp6GfNg zi}7i|;s>|>#^Ok~7@4RsK2UiDz!&O?WoOmC26#5$3Dy(!Gsl&(qoU#q~O#IiwKSTMELDdDvLI+Xk zUrz5Gp?v_#Qq3`X`yFPJF>(G07KPe#-*Ry@^@wU`HvSU7QNG1Mc%fLPHD>n9?etXH zYkme;n-*mJCv4ZC1217CSpeRsx+Zt)%wv}3&xc|$Ek}m*5;n_}#WCn8#R-FD=sSfA ziX=7eA2)CWi(}tE%!LVbY@>0ar`kV{o+NxUYBj0F4?l9uXDYKn)Y91GeoJ|BZ((Z%W$Ad5H@3PkxB~U}Y=X4r4F%!%(034#6=Psdu z7Ep-5Ljt`+qD=W;qP6WY-dB=TwugJdLbn$%uRtN-gHLfaDCZDVea`evNT$>Gnc=z5 zSL6+Dsd_Apzm)bQ<`td&maB5B5X{95bsC}6hHcFj*OF@I%n+^IIV&4Q{B~zEvQ!)< zb$#N!l^n#?&N4M!CX_fvSX>iiV@@CrGbfa8Hk@9@H-r9E$aXj+e=kFR%8vCVTjm`P zPKe7Zya22ipQ~8DMHt`F4Y>_MgYG`NY zZ>~&-3k-b63DTFRip4J@$DT?i%MtxKL2^;-OPpajA?HFuvjWdAWuJ(jpy)C*GJV|O zh=N$XlOkSCRc$8z<&+mmJ9%?DdkRj|@u>}+iY34PCrRC@?*B;YqI@NGqp|YJIwke} zYlE>oKJe|D88%hRGXG7KIxoN7^I1c)7=G)OkzSrfRfB1~cgapO&nD`_ z_ccJEjFs~uwbg+wVNg+VNI>5x7>=%wll}3RGV*20TmwER1BUNkFhjfze39#Bh7O+1z@TU=|a!L{Fv9JBwp@C8$}iksNn z-ZKm4A2dpjlwBaH-I+lTrYO01_y^x{;@QZ;fH_Cqkl!`yBwUH4*goOd&v1u*l&)pG)_92|b z%3wM`i==?UypFv_7!n=>m{n*qX3sb`krCQ3!{b3Vy|5CtvxxEXLI3b; z9N{c*E=)^KrASBRR#+)qHd-t_s*0`oO=chMxb_9Pvu0SH`Qf}`zr&@o&)9h_;Vnq6~0kp8{I@5N-H}xsk4hd z;w6#{^ACnrb>BSSA;zj~y!#xj>CP?-8JsvzXm9B2M+&-sCoinbp3NWiw!6e5a~bGzueTpndO@51g&J3rN+ z1g$)fmoD_|eN}iYzBRkBw|}^!u%~Q>JVIcEc87dTiF#k^5VP46>gwWM-cS1nM`Tp2 zYjD)O=(?MvFpX(&<$ZK5RNDBjwC|s@EGiT9NhQsSg^n>(F+(og@3vddDUUW)?$`yk zw3+Z4C5cp`q`R0{YJ(5Is@&O}?T+PwdG8H{j8nJ_*Nhe0J}lRS;XoWoXWskE44m@U z*1GxMBkDINiLyZmZhB{-MX!F%cn6LwhqAL$MuQFh8F$9#gND_1_Ft@t%LNk+j?I0- z;Jh;p_+FF)-^HqoGooPFPM??Xu0Ab(QR}3<4F1hN1`NMOeMONY+%Aor7gQdD=Sm*} z;9y{jA>OFFO5gJsEBA|&Jbx?LqjFgJzTV^=Mwtu&WVAwitn^d1FFF@=1Zwbw(w z*(XYnix-VZNejI_JxXp^k5`wP??hN6p!u&Y&rnW#^N)7+6vZP;qC1eyb8+DRGkg6Z z7(}}PN)3CO3jQmIEQIVl$k+Y%`vq@LJHsVTfP@G*=vBtn2UiM*B~JH)fGq(wj?{i8 ztI(qCw#Pg_MBX=~2s=lc<%<$V8kGuNVD~|A_*_B6D&kGodq2u~(?YvZb$(L;K&`nW zO=h&wmp=&ySmEW^DZkxMtvoMo8eAP{UvI^25S#lt8UnLMVRJtHNmrl7DQdPz+}v&s zLt^T*nJ^(WtTt~d;xF_g+exU6AiH$yaHgf!p5g!GW$SUEZ`Y;`^I|&AWW;1VkYI>? zm<4(+vhiGd0#*I^2qoZd9)wznotcxWR$PSgiv`jtcp(-GV817`B;WMXzils|$X*pf z7V9Z(-@Wvh)^|soaJ*sZ~TW024CT+M_{q4yC{X!=Ou>@RR zV|d}{m+%C}Hk9E!1gLR={0cE~KY54!k9C%oqdCqt3gJg%<~@ItN03r~TBZ`=H}qV* z%Ktm#!DTILgv@K)9WAe5gI#SY)2h|UK5)$0yIR(a0hU%cUS3;rt)yk)W zRR-Afm{;GgZYn$@_7iKO9T#nHb}a;e^PA+ML1Ht8eg5yLh&o7~(pu|cN$;ZAwTha* zQ}zU$oBjG`+7JGCwMg;bXBB~0PLByQN zG!eDr3Vuu+BogU~dO?hU;5*s^_q$AB^%I8~b1b!F1p@>(DGq=7xS7w=V(inhPis{9 zuJd(T(hnsw+fjt2aOScqd#S%_2ihXyX1(@A7o?!A(HY4wvuWQqNP&x$2X ze-xBeg3)}jZ)>VV3EkT|!->!}yT&;iY*CslA!b*4hiNt8oKQEFwv%rXo2nRYh{JlI zX%$IJ8TFVOck$6xcQwe)Kya$Q=2qpEJ;vdYNN5zsjppJfnq_U_z|nwvx=)AZ;fl+sBBt@$(spTTdcT;D(!Z9EfYEdnwq zYQ^eOfrh{HW0iqsHWd)w*{O4M~!*~)qO;^3cGW=8GGYn9>5u(Aul@~fK7NY*;iXM!YzHP4Y|yBp*LbWuAK5-mBz%9CkRC6V zJhK?|;K~=lVFc$RD?$HZ1pm>_3edj z<4f*?;Cj@pSF}Xal^9;%$|2k!(uwWh%^_ShysTm#L876hZa|@9sU7J@s|1%7Lncu) zQ~FD*y8=7^5yNIh=zs(H49l*%fp$Y50DO}O{HaSW{DI# z;Xk^~qBkv*%>>VyO$DzF2`uNCI&F7N;rTUvU>lu_P@81S_0yr&$){{`3-@8wohXMu zh%RU4m-+Mj<0{Hs19;%TwMY;5flxlnc-$S!=flH>W{;I)&87XAT0+N0My@@$5uqJW zo10uSzQH+-G1@$il$CHUDNDOk>YP?An4fIOANo-xRO8mM*-Em%G8w=a3XWA&Shnu^ z)=-dV;Y$BptFIBDn2X7u7lV|aC&=ZeUToNjA~3Q%+jA8J)6Vc0!wo-6gcDf2Pei~2FPiw%XYXi?7XZ;fX z5nv80(XpO9xiN}|sjRY;W8J9pM%zkU(Z4~SBhZB-5A}w#U7JFisT94kx}VI&rwqZ{ z7^2;{oZOmrAlyd|@pL7&K32rHe!9BGH}BAMkU!?y|_lahuN zFP;oOOzg6+eZHC9%PejV#dY^Oox5T`pmTa?)zc@5DCYTvFv(d8D7P=~>PY?;glz|@ zOJ(12i=F?f&yDICbCbPMKKQkIu6ZledetG^)sJfqC z;BiuAu4!xLsqty~iE{vCVSjX5zusPAuyLRfQHQ-znQ_2(H{fla;28i`7SqeiWtjVw za^w&zutT?3#8+YOg%W+nk-cMMARAY;fKfoz0DJV*npt1KNV8V+Q6IQ-$i^)(T?cTw zE^EcSd;0pVqxGp#%CX-0im17M_oH5jnl&G4&V8tc*5qiU!6&ds3%nv}Uu}n{eTcF) zA*L-$XN)cZ|2D|oAM2(WTmqc6Xz&sbVFNjM{guivkvZoO;B<~)$GTXqGEQJkuUyS} zd(PMnVNJWxuSI!#R4nFxJSe$#lqsPuSj-LbLy#ASvU^kpvo{p;8KVW-W=jmTPCdfi zyc;XVWKvF?X6{^gki2arxTLw}zRpOUz*SRkEQQ-$(rhe^@O@bU`xceo=6jy)TJTEpAGUFJ zb*&Y5T5(=iUl6e)rgz2s81IV+5Np3y@OarJSS);gsL(p&Z(5 z%t%~GjCgLTjXmm<2+E3y>SywC$6b6cIqtAg0qlRIIgNdyNjcHvR!9kP?$U98i1<{C zd%A5fuj!!0M6$g_#bYoHaVWvj?0j~N|9@1`~SfiCaCcT{K#U2VY zQwV@wG?s)7Y%p!tM15`hDViZJGF>zz|A8HV_3Af_g?5K?^_pco4Qw<`{z4O#NYpJ1 z%axYq1&1mQ?L`PyX1DC&;}5a7Hll}SLwGqo*qc1^7^NbhEu+=!^f8<4paJ|W!I;9! zBkt-U@M8~il<$5AY>_+;Tr}oGFM9Do^Kq6QPKA-ypw)yk7Q>!~_OKO;QA#vYI*#+9 zr?CHGeZm;6ov?`^v{f-w9BAtV?Dl!?2{P@s&osmLMvaq}5Z=#qYGanW6LUL$;bz{t zKfNyYwaU5}{zMx7{d0b-7+clEdf;9`;x05NoQLWKwi~6GBVkZO@4@aWNYZJ~l>&g~ zE@Ik-K*}j8V!OSiex(Z!Uo^8N33LinM?R_vmzO-r~j}fneNhfK4 z&}*z3CGuR`E68uDRy}Z+Z_NS~pskJc`R(h)d65e)moC?UU58^Fu(t~07I^Lsl_3>V zTVftPCxEx0$jEkeKfLj73|hA5gp+ZI&nFWSepH4@JD2pj#RCbuQxnmjpT2AnMQgdY-g zOg9rP`?Y);&-fYed}J}x%Ie7{wPL$*+0mZ%g~?yw>P1Dfu3!@nzc%9zT_}$dy-vW~ z((-k)2O60ol-r&R$tfLvxZo`|!dfWAbeeRSDGu-0 zoNwETU_oFBD=d^%$zLE$JccpKXp1YU9w|rj@@=s_BSEHS=&$^?bGJtj{V0-eK2X{X zY7B`p2x;9+w!QLopW2Ov=9#ugv%uRGTyI;MpXM zNGnl_+DWdFqFAp971{2!ABMpUtps39teu7n{!x2`7*{F4LQ^kTn*oekVLyI1Wm=hc z{V)-2b7RiL!+wV}yNX~P`4#o7$rd(SSa8G{Et#~{i9olqT8 zTiA3$u1JdSB+XhD{JBRMx!xdB8(k4*5pJD&?{tj=Zw4MI*PAtP-JjT_v-rHGnx{3t z@0_sEFTHY3>-5;l%zDr8=5*R?ab4U?-EdOTyechQ<7=E{ol$`98=|=yh;k6SY8)%K z44V+&@A9eH8O?m8&kK;=&LAz2zU9!@nUB-`4zqKxy6tGs!6MWQPI~!{&Ns-pD6YKd z#SQf)g}&J~6^9%Yz<~5RMp4$V;5;G!lelksyeLVoMAR8oMajF4Ujs6%yVR?@bf&w* zpA1E=6BXa`{<>1wGMyxf(%eBL&NI{W70%`z|y)e6<$ zcbPx6n}>uha~5l7F=>P^C%9Voi2}bR%^)pjv{MAY*`|TS?7&)MRttOjYb)JbPh0vd zLNBUE{F4mhAUvbsLt^wAA3b5hJWnY{DZ!aOpeMH1KF_Cp!(rCOU0G<@v-k3K7V^ct zNTB*%;?;=w7?Wq_?Bcen@f8wZ?YI+OG#F=}8PKH|1o2QBw{sVGGNROOTHoo5I6(i! zg(BV~vYC-`YG9HtwAcD(5ndd!o#);NY)~0dS{6+7qe3j$rUzdo@^tApJ#|vZa4358 zXFgrS`b!mBDa!3c&gd>t08C{89SycvvR;Hshi%MVwxdr zUE-hYMTpJDKM>qMZii3eUFQ$OX2MtUsk`snw6OX|l55R4p1$MDqdS@*i5GOnDvkt5 z43aPXP5sKv^cN8zaV%yOd*7hFDt|`FaA#uz|!Vi1%HVlJPPDXF(Vu7IC z(uLVZY0O~AAv;%pvda%I%_fvoKLmI{t4mQ`w|-u2c>n#F{WF0+0G);ip$bk3)7Z*t z5CSdKBZ&K0CT{bYez?9;{&^!E9D!cZiAed?AGg&nQX9){;xblC=kjMe?(u8d{+~r< zdX@e847_lLerZo3dob2zD*~?^nTTy&-&&g4&Kiq5j<&c*!KKK^a2LA+pt-PEPe zcI^9pDc9S2H9R++%@%?&9v^HQ6Vl4P)XHn=eappcxdoeLL(_a={%xkFJK*55Z&bNWVWsD+Q$Np>1yO)z$x2=B9~X0UB27~h79{i z)UY~+D-#%@n%!j2H-t{hH!A=hvhQvSTQ))fNxR@$2>46@(v*HNvM6*5rG@+ zg}xt-v3H}ZCa*Z>wd*MNSlrNZMC{4i#M9iJk!!DGU0nT#C-+&@3Ik0-)$hyexctR> zgmWmUH0nS2oy{PB9rJ71NlvW21wP4o>U$!4ivrdLpN=dw_zJNevzAVGXxn%mCX!1pD3+KmmL5OjB$jywjI=SXo?b&DN6MKetj^Jn-ha z^<_>AxYqkQpMe09_x5~m9jc3V!%kbG_SwCyR2#{k`+iW&fW7eBY{Gy$Gp8?pq`JFk zD3?M!It`;9r;!nL^O47OYCuVY+!My^yc7M;8YB|n4mR(~UJ0gT5aUs6k`to3sX|ZL zI34U+h9^0ay!I=`B)xLlkiJFJu!&Bj$LU7p(SlZF_e5LsRW{pP@Z+0KgPsI~=n`(b z9YgOYMs8^^dChnh2wp(8uU5?bZACP6X`=BDJ;?I6wQb|yrP20V%68ofc&5MtZ@BB) zD`nn|CkOYmh1HJW zs)hF!txe9Ip7umXb(0!bGmlpJ+ujY1io^sdJSA7ED4w6?fLJJ=ii_I8f$LgCgpA;x zt)Y`m2MHoVAMKBFC0d=y`iGk7RSrRAa`XMP;Ca@NpX3I;F}QT}^U+E-t=eu?14iSp z9#PN}TK$`KTy+ge}}Zn?h~RYm*4(qx1SoL0*uX?Y3TFmct=$S4P&mfD0uqvyn= zi`v+RZVv`%Ymg-2qN$8FP^Y_rdZcHn3m*uENaHsa> zY4^iH#lM4!F&+E{tZ1Rtq00fjqFyguT%Ic?k$BX$L+-v^FYjfFc)SaCug%&#o*&h0 zf7JDPCRt_hP0m)wflyz=_8y(v-um>TB9(%E8KXH7x5wb4qDNJ=R}8O)Tg}s>Vx#vP zTLt$!{(3@FV=}kJ13QYR$Nzg!`X~BmZWr6D=JVuGNRH-YG{5>K%7FLxEy(Fi3&g+u zYJCt)maaDhQ$ZZ60}_g3Dh6HQbu%f=UfO#k`jCp-C$8Pn^0%V-749E;EQ(o4H*L<4SnbZANQj$VkTgrri*k6IopgHzCRr;#!{%ui&$VAm%J(g< zG5;@^L|gln=6`R5uMv{pe|=t>S2I@sV~SToC1F|{|69@61bsK4q;Q$>Y}j$m&hPx( zw@Yl4>7NPBksYWd!v-2w`c~8_diKF>G~@RjQPKCHHgqxg9ct zlB*td$Q}}2ZC9^{eUJ2oF6&>IrCAANVWk{rO_IPgq8>bcfvde@(4eUMgF1bGCsLS* zadhS{gf|TDF24i1x^#8MM4+i+3$$i8>f7kUnK{cH>D$Ok0r;1@SD+x6B4$#ZPm8ap zP~Qwiap8))Cr`eRVO4P$Y7%1lR)Kf@NPg=jvO7g*YMbL@r~u=%#P|(IrAuB&E^pDk zk3fjlVllNd{=Pn8vA`K4o=&>O!ggE}%VJT-3s!o$`&?_d$WnrY1U}EILXoB?h?#Rb z;(c1W(n3zP@b6{@tpEV}Tr8Jm!#QfRDCVqa@f?aE%G2eNg+sIhNpDtguD6*vus0X2 zRJHKyXN*}R_xF$!yR}bj_;pjx_RdvvN(zYDc(+JoMG@bKq;l!*By#OTB;*4BdAH*{ zZBqIiV(mS{xgC=}Gt)0FGTX1hRp;B(FMtCaw12@{+!HQ|RtrBY>E5^__=fEmgmlwmmgZaQ*SeTua!k z#1UPKxOyAK8<-I=Tu`6*zq~!1>KWALBiq($a0i3>I|j2`y(c$JP~<))^aK8Lmay#8 znl-r8f8z#kRbaEXM@~MoO_u>xwwcuxe{oLyR&Y9w%J+MsFSFbaC*k`B`R&yEXE8R9 z)NBBL8uttQ1dFwx{4O9z6_j90ZSgCU^@R_vP90V=3ct=G@2Q5~dR&2G10hxNO5aw? z9wV!NG5fFKRVdn(+=O&_u0b3qKD|bDRH^8Q5?YjD5bLdPFO}I?Dd|c%*^$yFH4Q70 zG0)FbyfL?@dCu)uDzddHbOO!a!EcRfi$G^yS3FPAX`cg1Nq&T*MHwuq!yZjSA43zX z(WjcqaBn*ey~sv93Nxkaom*ZeMFzC;-L*D3x37IJ;akU&c7zyQ7DI`7w82MGXz+n# z)1h>3F6%@AZm(z9QG)BlOO%0=)ds$Nhr)LrR49{!u55@hbj8id1D_yxxkPwzxq{+N zajr(gNg#85l`Bbec~Fsdzy7n*HWqJwykv3rA?aD%I2HfIb(IU;sK=@ed=#(6yBWGT z%VFS;u?ctHxi;NZ``Gka%&9_Rsng6X$35Ab!%daG8?02wnWfl~uOvT2DW%$4TU?9Y z@%EY6unXe0ZR67wN=aLDdyw;0BAJW_=2c=9si+jrUEUCkJ(4rfty2=;8 z1b@i(R4o!IO6@Jo6jGY}qx3ekw=vi^eFc(!I`fgHMqIc@ny|+tDPU^(fe93*Zl%V| zYT`(vreBc5986zs$rtdr6*P2Ji5=n>e+$XP=&GbKvq_<@jIpgzNU;rfPL2;+0B0`&BU-z84 za*72p>_>^Mu-5tCsIM+pj9yYxWdQJ|ogMx;S$fm$8ZUB)T}lEW!xMq77l}c%-|Dhd zml@lkx4;8Ki0j{92Nkx}D;UdFla=FVMNhxB{5YSN_z36@eCl>fQX61)uX`?kUSOP~ zc%=8WIB}-0obr&c>>Zwt`Ga3}!#nN$>d_S+qkwBEwW66*Ga5r(KVG4p{D6POcLvwxOU#*k zpr$NY$~{Uap>2cWH2mkeab`ma_Sgp4NrISNX{}`Shm!lo8lsUC0@f+`-+$eHr>+Di zGXn@SmKjRwG_tI99MYOo#IN;m?iJZ@fia4azbBXS&M6UkJK`)&x}-_nXHm%&I6xI6 zPaDjwW-C}c7=d8!8PP9uvk&Y`NCX!trt;I~p+0krgtPD?99X{}fxiNUpwIR6dR#R4s-bA_DOJ4ZpU z)kIsVGJ4~f+TD5Tm`SO52&=2$_8q~S!O$pJaM4unV8-o7ejAA6T6Oh#hMRXWf`<3t zARw4M`=?LUD5UysNy&Cqc1n!*Q1^E-a!T=qnV#Wk z3qC2lmNLF}7ljegey~W%jYktkpzmZbYtc%5P@Ozh+5MHiKEoQ1Xf8M5Xn{zV_h7;_ zrhfu)9XUUOt4Hde?(Mt$MFLHWa4msKHENE89Qn0s6k+Kh(rNL=XQ|WU@;%^fDS3)y z)N2b>mCQTlgZAz(w;PY|0DYX<8Lqwy$DCffjp%zXtY2Y%U*r%BYB!;iDZ|R#E36#6 z1Wwwm7Edw(y;B1goe>^c)ztgn_Uk*GkPA@lp}#p85kx+1s4^$?mne;+zM!2wVeyzT zDJaZezW$^4rnC$dJt&%mV%$54o=*Bpb4zjXy1l$}Ezv4qApTfe1?!;%v!SX;es90W zVWBZbNRh$=_fN@AlYA&{2WD6vFE$)+9q-#(<<%mdXq}H(;(l7kptbNZOnJWfSi3mS zGryJR!|Efs1}+{&Si%o~%sviE1xfP*`FQIjez9zCxkfy~e_&g|?{#ou% zkNv^OoDK+|UZqkGS7JGjBK#MXTlP3x@kaygZ95Ujy#T77!=3g<$8FB+T(CgJqHzo`du?cGKEu zXE-$Md!=8a;{MK|wIelH#ne5G|Y74bUAh>oKeAGu?WU_R;NKCRZTRugv1J0Ps)vyGjap% zIkx6kmu_GCFl&Ulg4i!}S#M&M{6j^ZJNLrT^Q3WjV5=)@O0iriHt2c1ev@KaNi?3$ zVF`utWmeb7gaq0!Z^)+><;CJSP&H4U{4!15J_o;=hekJF%5P)j)Uc~fF)o_iEp-4& zTJ<3eD^|WvZ#HxJ(I)Jrzh18P+1$v zCSJz$C_8co)XkJ!DR)^rD7WqS9cJ3QlyA|rLTwlv&3aXCR4BOalCMH3wV{PE`pxoA z1n)xtohpETq!^fd&LIWzeSyx|$nO&|s8tVm!YvM4_`3cOGwgNx_efWNJ&t$Zh|i?` z^L`k`(3bd7RSd`Y&{i^pVw?XOdAnVj!KL77ax68IFoELzmZb%rJMURKhPjN;h(CgY zS^Y$?AAJx>ik~g!;ov~%9st|Br9>EC2@r>nO8rKPIW*(rA@|w}Gap7@O4tuOohFP| z=OG7TNfrE|_~-R8`ZzR*ew1(!HnfMnz$>MR>J-$l8@A>Vbk~axileBYnMCIyX-)gI zBt{so!9(tgCAE7eqVLonN3i4?Gi<=Uo#rV1mdIn=xlgsX`j2??3owhqxd+|&^;#ij zDr-KS3Ca3bMH^vmmqS0>?w3~?$Ns`Vg*S|jm%Tz=m=>3{G4HRGf?g^^p#z!zCR{Kv z7gta6KydmCw*Etwy?CY)8`@nqcu$w~{XG>)b#jllW*S8&$LFXo-l-;#tLCD=Not#q z_38}$$%sxd|BdyX=HUHp%lhtafY(s33dWT&P}ZnC#Ub2r=KI1D4h_S0-slTVm)o0> ze}?Tz3l5$KBLLN3d-Mi_WaJ@?zwlw0MK>IpGH7g1yFA)n4ad4Nb3^!vFJHfkA)YfP zh!pH|s)?$bmeO3dk7>+sNl0;X*FBhEfXbh8U@FhNz4UNUjW9WlM@18M7vg{N*Axj$ zmk|)uc2Y4)NanY<+DmS}Z?Ur^un{c1`unbO!%!xwX3R5<$y`y;Ao;o^7@ywObqX)fGfX4}dv&TixUtr)l4Xvu^RfTLlDq zvvCcRjDNij1q8lOak)#jh`iMUV0hqbtltci2oC30g?(wcrf^$&YIL&rG(lf)KQ865 z2d8Mi?&qs$*FEL|Gi%2iU_6lhh2Sj*)MdSR{{FbPARv>iP2Byy=Fx456_W*a>?sOX zoW{nD%zOwx%e}m>6;{_IU8xl&9)$Mj>8%^;oqclMVlwK{H0oK530?!hc|T|NAmL=Z`=^A`pcA73&;+IEV)IegLuLa%0Vz4_rt6zzSs+FHo< zwkXynv5)$6<2xM&>V`z0UTO_1YYc6N0`8b`Dsbufz3BNXFL2&4aIUd&uFo_V1)92> zKn(4MTRg^OzHgdS8k$oRp$mqWkN3#;`)E(HC|CA9LqcA}+g_8y5ALsL-*_v_m;Bwb ze4dB7xuT$->IM9xZ|G2}%tp0l@oK%Nf@36R2*;!cmOfPu+-*I%*q``VC9l4gu98Gw z&dI9`?{&)OV1f7u3~YpAcdUT+_cIXlXiICs3;G2w-PF|!HPM;LLD^?`@cJpibL#rHrY7O% zf!{z>oGn%DIvY?sUi+FVO;T+S85BcHn&zlNAB4WAtKK(Yw(Z%Tx82vetbMvTHVkP@UjL`l z;fwTnYNXLkVr3e~EI$)p&xpdqO3kJ~?NySbH85sz2l^{x(n&DRhVuG@!lQs0SM@Tu z>S@t$b$+Mg8A`u$SLH8D7K2R<)j>)MV1n;-TC(Hk+9b+-?EKEoUix>-_!6U2&fJxT zI=C<;pB!!518P_MJB?~s*FJ=bB{pr!oSO9dv^u#owOh)4MP6g`j7P3&0$$FaL~b6* zU!&!TQcm33)<)YPjc;1*ULxsEsI#Y5M9(_4?V4?cy6oG2z0Kx%oOwYJF5-|CpfGl4 zRs%}x*^b!d?t5igsBhEyISKKF{qm_*&T!*a)guRVV4^v!;~#S{j`xXoyB$$?(!H(g z>$F1J*T%IREG!&N0f$A}vwHob1FkzQ7u$4w5@f#CZmuT!&Jg=GtpVJ~2E?59BDa0I z#;|;*?;utwCR(d_1*(t~TWd`>=639+4koxHZtwNFzVb_n*EeHFk~Kd)2NQHR@okHRm;WM2b^+EljfaXU1{M5xH?9x9+bl z66X5nM~lA!-}lh1BwVW1`^X-u5vASQhvdS&BUQgPYC%J?LjeY3t}{d4WDiT<`1p0u z=L(Wt>GteW0u52vFlNzw#`!s^Nd|hDo>f!sTvimhzVgXpHIC^6eP_`)gKjI7*KSV3 zjFSUI{&qspfHfhH9fpLy67Cwl63x7@@ngHQB#G`=5edOc5s9!fF8+VR=$@ory9UuE6gxj=wi+`bGzhjnEY?in4PqpvDu)) zx>2P`@Y+1me(nc@H^se4@1*DXMCbB6Y`-&+uO2mI#(zcF;-Qka1Ne7svzKyUV_Ed% zrmaKTKT2c$=c`u)8mZ+)P8&86u^Mskgt$!W8Wp%~-+tF6? z)%JRVKvNXpZHvqC(^fGgZ*);}spX=so4n)tvb8yoUkIjS75Mj+_cobiP~V5@hw|Mp zzTnH*Y*L*dQyUDTJPC*|;U32eA{|IVdLj;2!@pt|{g9q1kg=>ZJ z0#5Gl?>o;*7=;kJ%QNu(OIwLenN@xsTRMAjU&FRIHUT0_wy5=%qNuJTf5;?d=xW$WQG-LDqR-7DQ_RBN1Z*s| zqn`ynWfXUzIZCe7U4V5Msb{GMM#p>DZIpzc`$mjx%)YAP)nAR%^kiGFkhbF++SN5(^cCUVK#4(a6T_gj&zC8u{UCMHo*j8+DjSaIT0xXi^!bj z62aIz(>;KI3)peBdK{^6iL(2*>(QHX7U<~R@rMzJIj}!jL8Rzr#aS`Coel6S&Gy(8 zaj3sUpJPP7{v)Yk)cEPXeE%Fq+Yw+ZvV6gE7B{+@!van4 zXq}|*89hTQ8Cm2N-|hrUTPmy%+eK48TieL!K2j+3sBAO7{$B#dGyP}BESc69fhT+n zNv7XTdN|78MjF%*3sk!i&YbP43-w~(FM1#$kCtr7Y;Cz^xTrc~HZ zqfe3L9ts~$5f0Jk!Md`K3`pkG_(bTr;Yv!_MUr>qnxk@D$?p?agwGTt_?(`{eZ#$e zSCp10k#pUUW!`1n^bju!4!PGsMkykTd+zx(@J>RlFStYC| zHCJ9KN)9Ul@0Tp3?G@%0xw&9^XJ++*Rl ze12!%?>O>hIY2&ul;%*@5FRVQBBk_S4px)V99AgBeL%X>O!60cmebMwXF5@G1^i5D z1G(MYUfE2BJl~nVTSejFCh(5(qFtgw(9Tqs;v?*+IB)a-&FW& zE;%A#S4XZK!gSdJ`~2M**FbrV@8>u*gVKLhvna}&sD*BYd#^?LI@{S}DshoT5|Hv^ z&hR}ncQ;knLkugvFpthzqq<7eVKd6J8T(jj73g0*Pgh)A!x2sgIhsX9w3XvU&jW>K z61us;WSr^;d6~W`Zz=upPZFHJfv+2xa=zqRDrF^#(RnN& z$Fw!iQt#%TNwIapCwpWa;*a0K`Nli5{8~b!_ME zOfSA}HrZcwW}V_aA?@>vP`l)dzw#42K^On+kh>X{XILT_#bg@G0G|4gH5U5dlB!jz zy(Qwt^f%>P_~z$;7Arm~vhs9SAV5~}PXDA&i13LW;z==&HwJ#Ep7Lhi{YW5KkZOPDEPH5l_hOg(3~KM}dLUDXB2)zc^3HvwNK{KI!5k#QHqyIJ{OM&zr(G}Vzq=-;Af=mjkUm7)Q(!p*IYN* zyVG4t1Z`&aW}n;S$1y}hgO}7V!Si3~wy;&CIU3cLDY11=wqkT!)F5lDQU0{T?@ZHe z;_5-c0D7y{Sna=60ok;P-+gkTHHP{s%0efxx3SF%-ib62=O~99#Ip~ zW3lN8zEIu9iBS$noE;_iF@iu1q~K?Qo*=Y+#94v6R%0mxtS zcQPhUgCpK0=-qg#+VB?lK8UojIf-JGIOKDGXB+4Ki^)?;xZlV&qPuUB7-<`B7`OWx z8sHpAfWB#6^0|gJ-E`d5`hvYF0ZxGKH0?f`hS(bEc|x&$fg4b$?A558-s&zl_-pR= zOA5YAAm3?^?ehM0W|^;4(I18{{g>Stm=<=+e^<}s`VvJs zZ%y>4^nILwLH_-rq{rRgOFft<8|359fw)os49v%I$=CbmeGwdvmFLrup3dS?R3p3p zvf8P0w>FcCu>>BB3M3mjW6l4ZP)~}JPlHy!78R^Z#}o-r!?s#I&HVfW^`ucVo?mX` z2ibN#E;3X^tn6L#ZM9_kgD4X0;3Ygg|M^ra0>!cuH+lq3s6X}FTFke3&Vg3grUE}k z6Yk^{aggzm;W#!_i85?7c|FU@r+1vCF0n zwf%x8AOxZmS;}`113#x{x|+6sFUUO>L}^sLfBOerZx1KP^Vrb}kq-F_ ztN=$v1jB7VcdXHKt5a|ky%)(bYo++RTgljGVIh7j=5uVn%d$j4Z<)=zgj24nRUbv+ zSCL_P;qZmeI=F3r#QF-P^&W)zvF^GKM)$klT`jskDLI^ACZr!3X2KDTxNpTWCxJs; z)H_qbo2i=n?-*3A_yQfNQZZy=PlfkAlHEbb%Xg#fB?hj4hA;u23eGIoTE4yj#Aqo0 zi!kOkE6=bX*Ot*8-L&;1 z`LrMDx$R@~8qvfOL>(8u!ayXd2k&DAd^n|;M>$a5+jpwt#%hzS@G@{6Y?3WRw}+63 zL`>@DSBIvGvp7ocg@Lo<@5I?T0F_@4Uy`7pf-YZg@^1rR>b?V@P#cxkVhDj#k1QCO z+nU7Rnu79TikhF|RtGce&gq>1yOBgp_)`VP`j=aT;ID580@Jm_SAcUC6Nq=LN1au7 z$X;H7{r=ZdcBd!s?CP1Poc`!u%rKBX{2zQYbHw>c>4Y`JyC+tL@B6ct5b))(%5S67 zO1=4WinBp^pn0}t%N-D;oa6T_4eDut^t$vs1FmG}{Hb(bS2!8~KGP2CE)Q%0>;A)9 zg}-BHFG!RxxtW)4+J~Y4=3t*Eu~b$Prmm#X!4whPz)OkY9?wWsr}gZEs@FPF2IAnx3bomVZG=xnBl`D-7itS zmT))~$pvG3S{Q^p$a{Bi@(}vazf)Gr1FM4izwc$E)GwHHn`bd<`vWk6Olt+epLB@RGtow1{BV|RVD!D0KnPa4d zqSgA%F-f6};|%J@Xb=zVk?ZaN4kWwkx+{#4ay*$vd9#IqKHQ_|Boq1RnfO2bU^eM$ zAUBWEBqx30YlHGo-3Gq#LT{d9<;61O|C4`NtdF|Ze;R_vncJ|8ihoHC85)^DSC0u| z8Kt}TV;yqxPra$8IllAU*SyC9QT`f!^97c#n&UcUCDfm;)dCxLGd&1+DsT|2hI^%m zA>`7S3~?^+neO;iT@|0IujQ3I@Wx%KjC{=7lS~zk$F&+py%AQz^Hvq}4Z%H%#jTCS zJ;HY?d{t1gVpg&OfI~FiPEhC#0t}!dkr+x=wZXV2uKWpA{0VQ1WkYdK9F%Arv%T!I zWdgn`4KXVX0l<<^-1Hzmr7m8jq1qta=R@ZKE$0C*3i=qT(SR7-5mI^sQu-J|0BTBX zuE0fdHGhIgJZ{ELh@cNm-q<$()jEGd_j{#xHL>aSLSR&-GG?VRTKYfA@lHQj4^K1j zNkfQ*_zQZRLCwxT{GGGE)oxZ+Rtj`bX%6c>#=VK#^*RJRYiFM-zAl@0u;QN7OPS74 z=)v91JD^DaNmW^Hr(?046oqNE4j4Rjup5&;R9v-a{H#*<#gi*fYH9oSn&!zxp1O$s72%-#ZPKkp@2$H(5h}puwqJN9ctAza;+=(z+#6yrl9`B} z-81{KhhVi?L7e*6?n%XFZ-XhsxIS>0mbPYC5a$As_*(>k-L29Vf3o@UVAv+tWc1N@ zSK?S5{DTxg%I@Er%1qe82*%qXXXr>wiVG%y$F8_xh!xm+>8_-{=#--U`bx|7(4*Vy z+ZuT*gFtDGLmb{-O4%(-2+lE@Y+HEdH9r9hlD-PZv2Q{}BeFmfjyYk(@X2eqO zKzc#Q58k75k<>6aIC=5O=)XbJI@#=al2=w5p4}|Hhwr_#niF&7rhj3B-2 zYFY&X_kHV*VNvBDaR|vi-B%n*)6YnC>F4o z^s2>SNVh8@Z|CPz32ChXA84h36fnjbqqz0W|VKRkzD0*2^1C9w15GU>`fy z!VOCBMrpC704Y)%0hNHn_)Dw|&x}kS{FOU{qm&sQNle;gk^FSH1#Va-z?jC+rOsuESFXPu^Nxn?(3s@8|rXGTCe(=6^+-r zSqRij!%9xK>MP?*z<51q0E%RMaw-ZN>+!RJBrU*DGjh}bg$pK=Q4iW~BflF02*`7| zn*6st?;dOXWgN~O8#_`^xwN!xXLtFotqkp_y_T8FxTFYo)7*} zjsPcJHaM(~b$C5{(xhf%NmcODxeV$~Ra$yW?fZ&i=ff>zovU_`w!}iAtwW}Za+zV* z>+2Q&yn9k5dU?2V-pN+)h-JCr2?Y7B_rzbwDqWgs>Q8*zid_QfSg&A<33WG}jtCIz z2hfRs%$xLg_scO1Ts?QK)?Tc3Jj=O&t(+JTSYmD0JW?kdxV6lpl(T}$_kDUN%Vv$Y zLJzR!XM@wc<@WsR_Fu~Vo5XA>bH?cD-?X?pk0=Pd0xQye?y)%wZac^`YMxG(n1uHf zeb|%Y?9Gx}L-f(sd38N~^sixK1+s5Vscy`)WuBt8_WrFEll8gZ`9KO*`D+f55F2;# z?gvj-@x})dnJ<(JQZlO}9y*nd!I50}#GITCSqb-aLzZJRKH$mJdxOtbXARZB$t_+1 zTKdK$WPnIb05I&s#W%)pdBo2l?@BIYTK$EDnjj#@l_t#BeVPHUhD}P@&T#Ol?M?A2 zy}-sc{rHOHC0DF-XY;12w)R~gdN69-52f}qz8<|)b&ly2M%V*ij6oq zwZ+fJtwF33CW2U-qE&{qC@SY?yU~k|UH-VENIuJbZgBKR*#k~D&gJ8!aa_4f1nYdJ zF}{Q?iFVa*yRciCpb4=8u69=YJ&GN=3|bA!ZCOrXY3{0ZS>Z?5PkS^@-&tn|09zvp zUsz@WhAb1FAFcbjTvWsasLmIj74<|WTQ1Q8S6f6zc#JnFW2+>oBWIWOUl?SiGIuuF z0-GvyYZs^GdQ#mzPnek9KrI!x8*O^kliq)d+_SPNSkJuObm#|0PCNQiG@^$eMkAa3 zdbyo=Y}x$QOg&=3aIMvpK-ZGOg~I1(2x6V~N8PF+jrrClvt$%KjfZHG!K%Lf2ujd2a@*|syoiL?BSACL zL_elne;Kg|2sSHwKegr{sZgR#&X&U?v*G4I_r4};WW!Jh#l*VSAskBJTm;!BZ~+1|epAJpz8-AAZ=Tl?Zp z4~D1{Pa-7zEFL=k;qvfP2RVAbFHHO6W*!sa+c^-zmBNte;H>dEvF-m}9INH+ z3|eGPDW4~29H}aMJ(OjH-qe5&&x6^oIhPGI4Uh*3b@zP!+d$eC&U!CbZUL_a`d2G= z_CR^Ilwl$LY=*9G9MQFK?BC?>T4gJuJ=oLZS;5o>o~NxBh2&>IC~u=r4Q=_C3bS^# zQ9txMWf}l&i{_bjO_^ydX7GQH*X)s?(Q)?rrPJrcXPnb0eAxSp35~>%=tq(G7(fjo zB_R%)HBs71tqA87t%~GKx{>DV&tG28p{5x2%AT%i*}50>g`Ra?>C~s2&u-@r%K`z& zjc0;6PvpJyIS&=52EGh=%_}0rxS%x^Be*XyCQlICBi+x?J=0qS8XTANQxt3$)@Nns z*eKj%l99e|a7Cli4&uNlpAGZq&~iB|Gm`j1 zuuAUh>h0qEPcRg+-sq#P%SxnXQr=;UtMUu|(Hy&Q!@;-0O^*l}E*Z7jHoYIumg^2?-Kt=%Jit#I>f5kSx54L{N z7m}pyS>qP`A>m&Uu;2;VT$MPk6;rPic%^H~eZEON1*L|=Hg;E(zOl#9r~DTY`o0#T zHM(cO`P@p@5cNe}9UAj2YA3x$E_Hjc?#D1BS&h-G2Og&wk3X<)PdTR0=<(W0`cQjp z<=aS4RvmfDkET1?9f~xB7dhN;1x^k9r6i?%mhFT0l@6G6QDvzs^)9o{@oT?ooeDW% zECOp7t zy6^`*s&x<3tVn@E(!JyUmPgR+#p<;EPwMM4j<#AobBXrxK+TIXiO;d)J^0A;<&5KJ|6MErR7x7@g|TsfBYi~kBsp%Eua_iKU-tN zi=n-hlW;DylBy^s?&*3Ch=!N)B_Tq2Ujk$sxF^xb+QGJGAIq8mC}&1uv>_BIMOoh+ z=gEB~E;rjDN&wdLidc9-_WbHEvuvv$o=y|DEz&n+XZY-}w4 zN-xAO(`R`$5*&lhJ7qO@6w!{r*2|4?Mo~ZCDEex!gk4WywDQ_3UHJX|`QBxBB(TBv z{?g6G&yVFr9XcmrMivB6qfP6dY!+aIJd0%~Q4nMGugFyF=k~(7>I7sl5Wh+&aru-H zxyDJJxdOZAIr^Sv|4aJTReTR0^K)Gr2+V)^eGNeLTVW3vRTrBWF~-BC9UkhQfBeO^ z1X9C1e)q}Zrdf9#ZZ=CWRk);YB*UwO@*B@qsw5P(=QGk4l346uW!5YTW0RDHxdC30 z!>uSbn^bVHqqP2k*yPpUdN>*{PbQQ;ZH>B4{WUIKWZkHC0zT!*kwx>g_K=j)|3v+T zx(`u;@=ygmfX8OnTc0rJiE5xI?2z;8#U7B#kA}?c&Cm&+AWdfEJY}(~MBv(GPsp^p ziO-LH-)z%6BrsCm4D`=`zVLzTFSA|#2$G{QR2lW6dYNcO7$J=3oPBn-7--Y@6Z z@q47`by0e4=DoGc;_=sQ*LM)Vw25Ra0iB5hU5QJ^WIv0!;v`008cglW$;JvPX z+~k#bdv!b)oWjIG#lHaMJoa~2DGJR)D5e7V3>0qh7t3aE;F3Vr1+|8Jv;q|C4$=dIkO%syhz50^jLNZL@A3 zqXcrcYb8n3Rp!4TKQ_p%coyCJ>y(N%59V5D<`AZQht~V=r@yuOGmflHNg)KVMt~m$ zMr)(B;yNQF?#W)Ce6hIJBFpSw4=cUjJb@BPYO;asEVJ+X;sRgRu)TwCCc7&*Z#)> z#1`2!t&fNok*+$zyLx}97g}%OOknUj?nU%R?<7C%hC0_ZCfpf^APQ?2+3cUp0Zwl5 zNI}7@iUmGFr}(|xf{IN(f3mH|Lybck_L$bEy|^oW)cd*i6PfKMYoT=-g3_ zyoynjCfh|Yyy#2g*Poocq5YbjoqK|po|7jtAiSt)_t40;RAOg-s3T!B|6o;3mW}?W zEdPQ;>`lTrBp~M01)(dQBP*S%^uQKy!y%0Wk1lw~Q=kR^ve*At&&O70ToArQ<(Jf+ zHmtp+;l$8%Kd$GhRn`BT0$Jql<2Phq6-#MT@9sM-Y5pqdQaNeLqc3JY$@?~@+lBzw zY81P1Wm!)HHE&TxW6X?kKkXE*Ac{5~B8$vDv@v|5K%F7yU9Q;fPrh^Hhl#Tx&Z<9y zSzb_n!LE-NM-|>%~@g-f~%#J1hCGk7MbI)wTh-$7Zu6~YloSx*Pj(M@# zdgeL?zijnGMA^(0jN6K$%1gAYgR4`M(n&ZmRMY$V$&cgka7x*d)}jJG_q;uFA~W5O zPcNxx`3!xG`F1fik7|fN(ZMX(+`{~wN7rpG$F5%be3Ko0Gx1LsRrb^_9QesF5;}pX zOY)@tT0NvJJL8)_tT8q%-!cK%(Q6M9Lh;4zwcpxB_3JvM?oH0y6$bPO<1Sl+F|Gk1 zjgP;*W1J|8YKMlmcwWJxJAs=#uUxJ5D&mXvwQ_+*&etV@8#=?}0d90bSaYncCKKd#hf(u#xa{_5?dlys^ zyb*>*L-{^n&}~bT*Gz*_ZJncd^a+H9k)II0{+U59|Hi1&Dq$^h<|}3t-mu|pM^u$`02IJIrPCD8*X9l zKCMAKxqmH>P);Q7o5-@59t-Qt&PovtUvf_xTQ97c+bPt&4mloI z)DM!2W=`&C($$`}eDmoekg9B{i{lXF&)v-@XazQQut~*gg=`^`+a(8DAb#>I6y#+T z=DWLUrqx)EY@zUszluD>`cyWuRDa9iP0K=2YjV{#1hT$QGrhV;V4;B2-7gzm-KW&G zEk_LVgbk}+zGMG0+>Bh;)-njv4IXaR9008e5&+&E-t1rgtn-4sBLH}4`PsgWS?4Tv%9yw~h#%ktF zwZdli^uHDM?$@HKeEn`$b6)oVGlH&Y-%XL!dq0`j!q)~@g*S|$tOEzNO|UhoYeC)> z0|)>AcfUy?yB@{Wr{-m`gwHj`(6f&#_t=<}0|&d9S&pc@ScX_xrIo9C0or!Cq7l;z zCcK<2!GpwoZsuLLDC9)Gk*x^(mArfM(Z{cMB&u&w126*F0u^4l@*}fHR3$Q2RoqjmNSXBtCx-c|mSbNaG5k1qyS%1q-si6{Q8OUB} z?GSam2%GK4I1p0FG)GcN)X}r#j6b~z7+n&PeX^sjtVB*NB5cft{;Ww)WRjnW#*1~` zMqlLTNR|R3WViH`#@CF}S3Y_e*OPg4#QNNDxvWd)0o1)~JVY&tfo7IsFkxUA$8F}! zD`L*77bf2#ZR{d0TP?X~NiW<8H|kGaI`zVWWnTOvQC?U{1oSE@SM6%UEDmVnGjJVn zt3k+8ZYnT*CS3BnIME0{TQ|kqBdS1c z<(iuiJKNxvi@GQ(TR4UpztXwZ1jAF2U8**N@L6JoeFW41X>?6!rIcU3b72hp*yEQ9 z%$#Iiv8BwD>F<#y>Lpw{d{|~biCp8zS~2ihEHjapOqf%;TKb`Ua>|a|^TIhIuWc+4 zSpDz_JmJGjS5|yvjCNizB_T24i2ZnAucHakugZyZA6!0C4gSc^-IJ@;{P77rV()et zFK{nYU<^_S0kz*Q46`KCpOM#q0FUh#pU6L&A87+_4fo9GY6Ec{#sKS?huMogx&z;6 z@5RjB^>4JvI2;U%`CL!}1eb8U5vBdQ$)M!YPX%Ng+s;FlE|S$E{I=63koIlW3CAo3 zgu|%vuqGY08E6}o7(9Akh(VTxZ&;MQiClA&qNeP;4Fqj7X*t%#lzm_gPk92+yN*=t z#aLVYlgq4cZbh28&wO|knz@${Fl_gh!^Y-E&blm*#Ccswzm*(!MQA_4zd&GFOi)_Zn;i0 z1WY@?F&l%#3*?r5n3gPnHQS+b&J9x18c3|apwiFy@%Dn+wpaJk_*&20?Kr+=cP}mt z4CmE4$f&J!G1tZvdNE6NuCrjrns=&DqGRUV{ih<+f9Alz5u#(&9(DNp0L*Thi>ixeUzQ7&XUxo6%?};> ze_VI{-#u$(>!bOplsk#vthx`{JdnC55_;t2WYjBqHJ-r%5qx>qB3r$guLaoNb6yHR z4=BmwwR6vZ1Mb2^y;PYUryeYxeeCp_R060Wl}7R&C8HX{#uGiSG0y4q*}-rBzMt6N z**m0u&%kk)83_1OcgIS2&~y%(X`5Q4`X6CqL{ry(N&f^!o0=#aZwJgs1-1cg2KPrI zC+zhGV_u8E5K2)2Ae{K^qiMP;9Ki;YOK&2@-6uOTK=?uPl-76qO^mSu_R0s5I<&oN z8lZoPhC2I^>v8lBpOpQcG7g1uwf3ErCvO8NG^YsQYz^G@I^k_&9(vBcZ6Gkf9OyjE zq?w%6Zqj9pwb8IS4q4crsE}6DpTCg}*Rb%~QT7BDLj6n z(YmNwQ1i-ir0fV4h_-q)j8Cp2%E#_{ z>A-~@$Q1FufF(CxoF)$qB~uD7?=h#8rku%_*wJqYtp>T^k!C;Lk0r3CYk!J`ose>9Vbu2 z9qCI)y<9d0*d9Wr4y28>keJd^B+NGXMzvIGajY0`G9Wo&?d`+Q3t8hq-lT!OG}@Wz zALBN!cwq0<;_&|xpOjL&I8lEV)g30`lBbUz{YQ( zlCMEVV-$_eGcc^@@Pw(Yy?pQLS-eHa3`baAC8~EvMrKPUpDHeNhO`~BWhHH!`2*j_D9R+wMu7QE1Ij%+ z0^&ph>EsCjeR`L!5rFTF?w{w|pNd#wiFxg-C&X46v-NIy&@2jBOm8ysrUO;CYOk_6 z_^y0sgBAwwSf60skq_x$38+ZS-3EC4$~h98GMgW1aak|rOg^d!i(iBlZU*$80kc8D zx~|tbdLw^&OwXi--BWbaAeg2DEOy{5&GnimwdxVV48tJnl#+|S_?K~(IC44?rpf!wS%N|cmyp`|VdL57h(~y9sh5kF z-_(BYIPYqf%{-X`a7yJ>E`KDGBDUpJ2WW-Wu zzBZ+{kNvr_169{C4?n+6_or#BkfjeCUS~1zK^+V2$Qr|(O-^R)F4cp6vrv2S{m#c! z(9DMs)j!5c}>Kk9JeAn`4({qaTB-=avoh5>9{3N>_n*~oky@KvodC=5lQ2zr{PLS{hFsE^2&BhsaAM;B zyf+(jE$Sa}dcoU8!8klk$5mrStWFDBo)Ev~%!gD$Hr;v*Q}^e!H{wzOzvAwg_h&$C ze~zv}Gj~@!M%yn(4a!$2x9nH7&vT?^1~{NSy9dGYl%7!XT9uN2HrQhsf z`Vfl!0QD5aoxaI}UfKz{=;n>5*eBEEBJ$iMoz=UbTf;gVwB~+8)j{{28|ui_jy#iI z=SUYsJeLY+$ut!nKZ^n3Sbpm^e{o4zh_cYCHyn-n0xiwz5z=k}F3!=#{L>%zC%U(r zTakKRVzLZKJ{;$G)}Q0qx>Ls~UwP^>&p0oQY5p*d<~X=NeK!qYw%c+O$g|tBRM4!~ zqWmQ)@;)YzTWb1F9B?hG7>*xDEJv;(N6t&=@ow6!x_Pl#o7k!vy-5eDA|*&;;$6-~ zBay~!4&-3kTrpf*!G4=pC)Kx!A#K#vZgx$G-O`8oww}K*AE>u7r_lPHjo@+hd*iAc z_QT7|t$7HmteP(ys+QjvqtAzLgieOiOm!#t4mBp_WBTzMVc5x0>x-1o@x8N z*stzt-C-Iv^}NGWQIn4V+PqQK{=<5$KLaC|?S2v(^F){0WweYjdF9{yCIcjrzWj3e zhyB6rj}zI>ZbuJ;|K9_jZM@NpV-6XfkLIH!3)2g};97CzvJ&el%6W{gS$YITj)F!A z5xq`fKdC~kTZb$%c&%|4v?iN`8OBA9o&iK+ojVB7jYkt-=;tx!HLB5-6Zgxkd-@m! z=Rj93-Z~mT-?kE3Ubpvv7iEepF(Q0BtXw#?f>m35-1+c}kM&;_E8i9*t@)5RjXsKO z$0TnJF=H*BTY+~CF?71#=>ya^gk)mv;hA#pj_3D+#`8<>5TEp|t(A9dGiomCcah2T zPOR*N2m1k&Xd+>;!Pj;C&k7%6KBR9)Vcj9*;KB^=#X9=K5r2QpZ^R`a-0u*A^BnfF zzC<6~%{_@`0;Qqw=O6){+eRb4y}ut~fK1|5JmS@;O3hMLf{w_>Ezc-tKbl!uM3eNk z7VqsFt0siBpAj151eX6{nJi)xI9BvTM~R-(WcjbSdg-K$iltPhTqXFntzQcd5`t{X z29|sx)J(s}gKQPSzxVAF?>q(T!SA@1lO%Z?NgCAYJVA&$^ z>TVxrkO=d#MVtm}vTy-HqxmSjlQK*ZS)D^dmOeoiaHMT^Hrp zY-4aFqA`*g!UkM0hyo71w*KS_+^ZH`80%x1=rfIFpk0g=MZX-|Ic9z-M@(fOT6QS6 zYr18d+;>$oWom2$6ZrC2nKUsAI3o!y#HLf5FY<)W_0iCs#HBli+v3$EAmFscvqzjD zeKWCiXypyqv6VU#pevmX%qiATabGv+H>(mm>#UNoTB+AwJBXXF8E=iVJa<%1%FIr4 zAIdtNc3t;6zFPVVa`Zv-V6*&h0rv6CQtwGC|)Z~UYKkzXW@PMEw$`L zG%MQN5O;ZHJsaiX?7=ChNIIJHFrc694|7{PW(SMUH-hNf!2jBRas7u~xXQ1_`AD@e)hFKyvreYY8Mol$U2*(-vMGRR;s(W3+>aaZ1p&^v9$D9#|_Add1_CIphD$%U^wyf! zjJfePX2*95uPnhbZ90oXW~SJN!ytWyYm0}h6=I-nsfS_C+KAx(tstS#R>65DS-nV` z!f1k;KYe*`5qED=RqxY(<2C`Rq>GcaU;3u|%2e(m4g zq1+=uke2?QC9Mn>|LYu1=su=)*vxfJF*ClZ-K?@NrWc|mdW7D-WoW2Ie;wv$o=J`G z%L$J*avrA)u%0$&lR7~_k3$7sOrCFQ8KOg)!qGs)Kxfh zcJicfeobl;?fLHCn!YAGfL+MbU$=IB?!A`9S}uOouNLF43sy@btoy`E_Sp?5m0rNa zO!Dd_Y{x2z4K?Xyt?(`b>08~c)5msULuW-X)-JL;^=Go5>3LB7^}(fUt)A5U+MVVo z^ces`CqUWq&zlU9%#9zqFpKX*-rCA+sj4z;6(52C;K_w(V~+&WYUCc;R_}MC zKE4?702BeX5200lVZ`b78Wyfx3*_`Mc$2F)9^pMW1CYBOw%rWjalO(f?)XR z;zc!AXRT7ZMk%I`?)snGp83qpT3G9Mm?nH`KhH=soTnY~(~FhQEx5;7cW}MO1;_%n zF=|aIT?e7taj2l%5TU6g4-WDE6^W{iabdr9yqC{Amw34rI%xN`tESD|jaNW;`s(^r z@V_cnrpvKBnF*HvaaO1_P{)g=Nsuyx@9$;cyZ@`I@9+Co)nC2?E|)qJ`Owo zudGjkpfXnVu9Cb7{*QCX{5$$W!+*3RN!4c;o`G=gFJDph&xW`n!R71jG(7$S*}(SO za~(D1GHR#3Zgv8h);Q7$EV|CR&7Y#PH{wiTMEz9+Et}9!Ch|Dv-rz+$ zY(46WVQ;~+tzRqGEDJ6QcVTU}HBySQ1(_==BXLWdr-fUgtQi_McbCacY&L8OGjHP7 zblBoa0ttctT}e4Pf;D44_VGTpQ;QmZ%LNB^%YGZ@sF*Y~uf_ z865bMAc6(uVN135e#LIuef@R~`07XTAFxK$T{N(8ls>i++zHg7`6G~e_@fr->gtT< zE!WJD)q9i3RKwYITwGHv^IDU&cM_izl&G@?2jvKqs65qn6uXZd zq1POB_VplL{tcrr$d!-#q5pB4+BxOpv{zv4bz>}W{ZmJOuYk8;o@k(;L-s5fcu})1 zRg~y)?n6yl>Ukkh^N+v$$Mj>eRZ)|)^fm@LY}6HpCj-_mYwfr#VTgb-?mlIC0Zx25#sm&=B zvXfgU%d!3LaAz{!=pZ(pIJ|nDC(X{4=WF(L#5kAbbRoqTf{Flok z$Kz|WqG}SKlRJ8jQpyrk z{igQNfvm-O5%efai~MwDB`VdVWM)-4byw6((#!1GchvuiSMBF8^Lz4uyJe<0VN1T$ zFL9`R1N3Gry2sFrrx`OiT6?F%^A$@qvZK4zEe1boc{xV+X!3warHgk&_(??&hpZ|F zd&)Tp`rowoDhOJCUY@%C@1l=n7mh6eX)iZH5V@~NiSmr?JUQvKHo29z&aj*1eBjiX z$ZAUN%}#xpAbMHJH*Zp!Jc_o8#OsLrxoBc2C9g2IPUQMD+$34)CFy!o+$6c>6r0M> zMaXKeB(E!5O0ZNmAS3rclg=aNWzYrj5euYj8B*^LwY4Q_K3M#eCAa~5o)P$~wCkFP zH#~h-aV#@CT>uL`*CClo@ivJoN|SVHlLFh4beJ(csJ`ecQE#}ju}nzcvSd!qV~=@z zDG!$K%dvtqVX+q*o?2UXV|1IJ_iRNIKd@FM{EQctpFiB~?|6TN3GtWlk@(5UsB$Q{ zvLa&5&#fLhLp)D8AwhDY9Eu@MyRdL5ddkaXkZI$;Sd?oN0L(hY8pc`ux*f57BkgvE z@u24~y5e`%Kz@xsdL-*$<3bUQw!P3c+~Ba{MVBY<=Gd`DxBFqY1*?%EL1keP&t^-y zblKjL!!gTcAq0)$`VS@AIQtT(Kj_x!7p?u@OV z)b|W&@i1o{@Xm{{)uCVhA1qVfn;uu(CxAOc>udn|0$9@%b7M|t(f70CM)IUIz<&(tES?aE6~LCOn{fJvvBaFn zzT26yDU9PBOEFU?aoj!#c^=`h?s)ciU2kp+7d#BtTA&`#@apqxn~d(rsCaQ)ZA$LT)MVM{Co16 z=9B@lApr4C)fA(mw$Ofk-fGL4ZJg!JF|H`43kB*(-~JSWM%b9yEEg~G4*R-BoXai> zo_K#w%L;Id_|3(8*g(PFq2+(gEf_0_^nq8r;N9H36}>H{q~px6XN{eOI& zWl$VJ*S3QM5^MtrZowS_1h)thbRoFAyDqS}JHZ`-ySux?0>N!@*TrFxm*=Va{(SY; zJJnTF)zhcvPfyi!pL1U~$sdBJ>+$i0w<#n70S!jfyWSMdw6+y$PWzk1qBwbB)jP?E zA_D1I&7np;YCQ$w$wl>f`~D}#RH5c|jnRE;^TBPEfK+O$7v94Td%q{o0QkcG&0M)9@3)jSN4%>b2E z^mr!=vq{~24FOGmBLAV-mR6u3bFZ7!wD&L2@V8@;ytG518Vx-{T4bzirB?ayYX<9d z@a+yBz&Us>{ue?046+r^>FsGjVT(5w_&UC78U)d2V*x?BDXB(tpxAMuE7Pzha)g^) zWpZ^C_}R(o*+>35(rFpR$i}1DcB-i?=hN#u!-8Vj_dIv`RuhZruu|1yO)cxSCDR$n zU=xkIy=GFT=kdr<^Hu6%bLsU_-u2O5k`Pe9sH24DuGbA5nQw-yzyz&>{85FiK37qZ zQ}K7>Q7pq8GW`6Dh{vl(yoPvNKdl7V+QD*P1DCt`PB5XUlwo&7%}p@R0uy|2HW#ci zTJqQX#?7K7Or=0m1|xMstd2CM}JaH*P+d74dZ@-r%HhhtnB49eI>)~8n{<& z#>o_){`iqy4N0xI#`I!Hh^zX^)6;HLMRkdx%Ggthqrm5ZZ6gIOB zk!>vyJI8gfO*oS-;8`ru^g5Zf)Z4Y3%A?Z1yC9I-XiXr>_3)@21rDTc1 ztWdmZ22x}ZoSi{V(O@-SWHHD+=-C;w_nqeBcdU0EnaCD>y2_s=Sj6>SEK%SZEdPAH zi5EMG&(Cf@2oQagCY;VT1WQ$({+ZtvGZdF2eyr?%A$qh8emQA#?O%H{Xf}|=u{ZuJ z81!Md#l0l=?{Z^8H6KXL`4Zq|5Oy#L(igOSR%jK3yZ+-I z@mS(-{peKo1lgJXwVlwEnK8_KD^icWU#e9QZ0Vr#XcMQ@Lu+1d@lrbbJnxW??Z)R| zW}D3Tw^owHOm+>|usxjThLmrz&z8un zMa?p4yxtnv5ag*ksr-oh`rCQ@WQ694z;V(>Kz;$HPHRi& zpCP`WD6-C9`G!b#0!{>96|8Aq_1EJ$w?PAY%*VgR4wAqP=coQ%(IjCgYEqblad?S< zR`d^Hpj_-r%zfBa_$HBEnd$1Cl{n?8)o8%K_A`mB>aJi!acwxfNqSY^bj)f@Rts0V2T> zX#{Q@C_&9{4KhSdhigiU6Qwvr6Ohh6g#U@p(51Z;1HQF^%9+6f3wFgni#NM6hW{>v@V#r3`!i$|6w6j1=zS@sRYer z8XF{9y0R?!Jq=Q>t8)dkWvtU28Md@EK()1R{x!p6(F10_()3d}dp;d=dXxT>*jX_n zyk25sxECAbnA`bvEL0rBidy)K&1e_Z_v@pthnY_0`OC?kA&#zRi{<*Cv1jMoy z6Um7o8*zL1m1JU(b1qYOuI3RN-X&z-%D=`v`1hym{ITZW%DKztx3XFetZrm3g3*N2C`P zdVQS%RRbRsIE^qs)cLJrj%B9pj_t@U?^>szcC?xcK3WAcjl;x4)(p#GrOjgK82pLL zJl{>rj{?$nJ)YTwIgv<|8BtSMZHy z;kTY5yZE*#o<>Xmcb=OtKI^Sj%1J+AJKy(lOYZe817*GBBPzoyFxcKEe(PF0O7#!J z=89y;o(Sye54%uE$bJT60@Tf2^uy;+ZL{-WtLVtEB57tNFn0tp9@R=o)N3wmbu2ec@$a zA|Ji~Vp=a?UvLguUv?(8s2dC-vR;xuY9lu?Z2x#y+^^{bak`Q?I?m&OBAfyFfaUQw zR-nU`^H+~OLXj5MhY@Zl8o6)~{7 zt*IqE-4uZpR#>eBW1mo}Kfxs$*G8%X%5FXv} zDef<*)U*g-HwXPv9h#{sV}d;6V&Sz=4*G`_Pq~mRyb7HLTqkt<)_AvUl>t9{O72?! ziMZ{a(e8S7Up?)Cs`t_@$a+ zA0|$fG~P4Exs+LWs_T5m89qmCU8grU{mpGSNPgiaqGYC_Gjo(s}PjI@&QIRmxH05iCM*Q?xW0_8ai51<6F{*Az-34dkEpDtrw-J z;U*`uLOd>T#r73n7HP9iClp+}AI<|~b^ox%U@@$^+yzJ|)c9*VbM$kYUm;iTNGJY= zZqXIRwNVS5C3^fV{tV>CMFHoN=}@PhEhyK9GKr@Oh>Pd`#;6Xjk!Kfw8U!@1wD3n^ zIT>7s+js8erNU!JuZs<&X{Cm9x1~Ng;Ci&ETy{4%Fg<*pEj?s2RPg3&N%Tbi&i_ei zS0>)Rz9=E)3?a!OG%R(TGV$Gme_*x-1ih?8+4UqAp@&1yQMco_v8P$gCA&I={7QNW zs>PIlM+*MIcaD3u&8PD+1lL`@2`jy8+3`wiVsYSM^!`a`^Yq!>V`a0~zIFC>9iL41 zo=_dvde$~w_xjt1yR73qB{YfAtX$lm^{}`PoJ9L;UPUZ3S_KK%5kDt1VFCtE6iZUB zBbJ4lFthA61IP7HZTvAB>ANqswzzpo8iB)fsb*0|iWq)o~%QY$6FTQ>}| zSFh8Nt(1sh*dTFzL*3$D^j+Sr?6a=vDo=i4T@lVF(w}Hr^)az-!@Ou@NNNBg#Z))oQ$pfj|wFcWvG9^z8S|&)PF&JC1?1h9@AHR9e}b=1%j<+0)}#?b%(Q zW6YfA;Fl}FC8@vE+LX7)n!SBtLGqEx8oTQaX;#zO9X;sD)3IXKqX!3+ zgFpN1D2py9l*&e8G?dRG*_7(E*KXM^9Ie<&RdKMsTqz#gmJLcq*2T;+XIbJMD`Tu* zM0}f#TX`uhX^y=X2qjS2fbb}xv z=mVm$2G3pK&ND*Hj@@n`4~7DIZvYLMH&eh+90utcs_O;P_$7>*T12<-*& z$_G*L#e+uA^@1?~O=YB?qjD;ld;MjCsFVT9>N-gq-L)9rJsgkc513$M-j(q#GL{6^=M)@JkyRKYrR5XK6lEMtXx06>|+c6)rO z0ijVGX+^I`H|kzqRdd)iF80D(o*g^|YChA|^NLn`T*aNPtDo6)h`0O0u~G;t<%Ub~ zGgR|yStx#A)4x(zzRBp-#j%(C#v>lTT;4P6c&09XlE;tb~kCWxSb~+;Usj=>PW9ar|Gn z?$)qgmQ%W0Q`#-s88eVDl#y$L`LY$uY>UyUJjReW@|uv24sR}52%TtaKW=f~d5D<~ zTP4QEl&}6_Tu!^WUoLigHU>2uP(3X2g^WpHd_d7M%a9_@^WJho{8#MXKHDl?=znW(JNu^vJv*nPmG<7GSV-X-VpumdIqxL-S&PN@mZaVN z+9KN!K_Di|2{-tGAuBHEYUIA^m#x9VCEEGsX>Iqc^G24Sl4%SaHg@C{y<0j!w1lw*@n+cg#pd9F-;%)ru||47A}%TUio zuzAz}KF8kB?pgwKYjm-UG!Co9#Q)uXrroI6q)?c-%V16zq1nffc{?Emw_DSAqdH__ z()|Dfq6J|+v)C^p0xwVlWUD{wCaRzS%&aH4(7sBzqTzldX@50%TkNSG=GS)G#-G8m z?GfK!kR!-l-z1=t75sUg-Dtro<_O_#?5)s6YawtKhU@?_*@S3AB&sB;XS6d2!vxUX zGB3lvFINMsjpd&FB)Th@PxoZ4zIfB8Dxx?NQS)|*wZ7Fh`i`HqaSS;+al+zo$)nl1*>b(zQ`8W(75`NKt_p6PGU0A z#&3b#k_<-Iq|tTH8^z>BVCV=|RhE*z$gr+~2x0S6{L$X@7=X{S>M4LXtK^;(c66hN zBkxZzzzRQzocE5is?Yi{w7T0v-}oZXdV|dA$+mP-lQwtEJms}a2Jp_x9;%m8JMiqR z^oU+(%RU>>t}j)k#h0J@Of`c>d_mx`layw$T5m@+Uhw& zSdMcmMYq#0?9pvGQ#}6_?0clZvJe4lDMSpu1pQ$M@-hV?zXP3qzst~C^!S<#8jQ-u zF~FD)6QqD|XbLu1agpy-f;j2;R1P#Z>HnE8%ovMOYZN)#X&n~uXbb?)!95%Q{sW@3rH4C0?7bf1=WFpi<;j0V;YA;kQpH8Qg?Pe(*4qJ2N)$W3Ylrl%> z35*D(C}YlADJKZ8pR_Mla#>3i+(aT{&cfU0JikJgNxvCFf6utCNE)&VC{>B!sH3P8 z#fY{8A~}g&8{&s$20w7mQNUh}zwBQ#r0cN#UCg9jgg9de(|ety-pE)I*5mjXaohd7 z$Z=NscBAGsAC8Rv4H9hK{Vv|@_xpt*#l8?sBHbZm|54;DUztDMy%*}#t`$8&hJl!k z$Cpo=x5WHJ%eM4c2!>tJ4xjyPQ5`hK-@!jB12$H-~J3T&%7VZ8i@>Ly2J+qe_8AIQqGbh5tu=B}acxpL>l zFhgKs#lYl!|%u(s5iXF@B?61^cT%} zzSFw<;MH_R5#a(8zySm4`^2o?yH4JjSuIHI@F76`sonoPW4AdoTB&ZN2`LRq@SZmw zxT@bgJ@Jz%ACkNLjhZ+Z`QBXj#HY=(l#QmjZkTJWMO1&Q3=^)<6&vrrcxX63!b=-* z9d{PEYpZPb^H!Mqc^grV)+sLTTNK)et$7U^RQW01cyC#DK5s-Sp(Sp8Id8Wc{F-A> zJ*dp?snl$+^e7`7;MQfXMWsy<`hZf?GK*gtA5G|aMn%lmVn@+A=XQO^`>tVlAT8g@ zD9~!#BXmSiJz~c^Jo($ZX1ZYVG zOQSCbeNGrvuCQ*-I)ML(CeUL$jg9PIkY8p`W!~$AXlia#?k{u5HB(?+eCgxWsP7%+ zq8{Zsn!87Xy)YW-ecuX%uI96;`5>)F*D0pZ1reenM;m`F?$auMJ~mSDZs<{6=>cXe zmUylA{OXID#U_Tctb$2x* zE&N9(A~ach^4&2&cVU(s(>FU%7s0-3*n-4P5vVeRU*&mJOJj5OOT326K8jbYq2tgS zbzZvDiHy#3hSANE0S0DZ>`GjYE$LlA7cv0AkA@j{G9RhlF z6%&?c;omrwxjhNVJotlo^186b?o3eu%8}+BeHzRvLPD(!aA#$<9F^xRi|g{8?{34h zqRii39~HiCFixSjX1bD&_5P#%x9(ONzIR}zI1gLn@NuoFIzFe z5zNss)}gkzf;yAi|zfwwoLy9ali<30XrQG+{Fn_Y=xT*BoOo!{t!aAN8Y+R zSKFvb65FzoNa9MK>zNc7X4E0IJ6aQOKpAu-6llK{ESnrW9o! z&@9W&`Ikk#?#bf}CD!E-lGDj`6?%9DME3xE&(0)5V-}N)GYbpP9>Y^cU9JDxgpoKED9&dX`KHC0#?0>w?xDDSZJN2+PMcbp(QWhag zvN)$ay$`#TM5!o|ZP+Z`yA`qXSKM(lKW>sRm+z1mHUn((<~dk9n0uV+uo%ikXqt!Z zw(uwsc02k7d*(T6{_cY|{`0n)tcDWLw#hy!8H6 zCD^;plBh_7MpWpeI)`5Q28A75KNSCwFqu&N9r){D#^o0ygUf14m_3UBT?s^18xl~%zp^#?0YOcS7GC}U6tfAMmq zVa!_Ky!uahvD!XS868C;ChotzDIfo_FTzy5q|b@^Hg!g832sy+3NDM8)!H5;iFaz- zV@Pu)_qi#yv`-HN--%q4rRV^hE2D`erBI7uD72oQg_- zBVmoA3392UxmAj^e09eHLEWf>jN!_;vX-$I=g9V35U8o6hh#=?T4pJ$QU#hK%@x@B zNc?rg+PFfY`B5eW<7}s_oq~!Fbp~=LAlyrQMz)POh&cpvE(4*JRGX%J+lT~gcp+abF| zN7wS3xP`kx816hVx=e$e%Pz&vzPFnr7iEFcYeCHQdW0&Q_7DOCO<3I0v=+)IwLOQo z^9ZJ&f1=#fylg$ZWF&ORhQNxO2T>jrS0gqBO={xcRq5D}!^_XqHsln8q?;G$$fj!9Y!Rryz#$upc zgw>My@U_h9C)_Ghy<7IGackYa3>U8GY}=&{3M14n11BL;%So5-?2qbe z0vJ4+!@Qc;>bv7I-U4%8U4C%AEXvNEp@aNDmvbp{*IGc^T<{c8AJc?P2&~zq9ugPc zTwS(STjPn=kjLemAy7rv%<|raZuGvmicejiZjJ$RGOOUe18s{Jr>#En?9ao06@L8+ z)uqvtBsEWkS#(>fof8?d(7Kk-czf1Ba^u{!Hm#rIM|w6hxu@Gd++wOb?dKFD-@t$M z>3`I|tNRs9HN0VtuL=$Sab-EsVzfjR`|o6VWPt>0+AbKD{|se68YGU&mXk+96#ieR!jG0GQ5ZnB%0`)6S=3*d0|+D4jZfJ|xX|`bryh z&-rp1KJOP+zkcS;(xiqCf1dBDsi&^rhwDmz9bD9SeC_tC#=D2>hNo8s(kKmi^Hx@E zc{n#(0#}u$!@#@DjkhXP8Y3mAW83_-A|!xumDG8PESLPGFb=;ZlyBj>6SC1R(c*Ia z-0b(wVivi&vAR{K;f4fu!b5wRFXqPW7nXrva%zibP8jrF-5f!@Jc=^0CT0J&&CA5B z2f7v2r6(hL3u_Xq2y+W-@Ma=lit6Y#1INW>fm~Z5B|v=^g%#?${D*aanN-JyYsd~O zU*oDd{w~?>vmFq8WWhY2VOej1$Isk&+22I9lV4PcYhkk9 zAoFI+G9bVE`Z#CKi2qe=4N3OnUk010rxru)i5<^J<(L*(Tn{P;SA-c|Dn>MDQ?#p)1%ivP*I zT!p!q9BrW9xp-6A*7`L9hMJ!eUDHHAL_c=8_Nn$gYg}b)DD*L74JSPn-1#33;(7Xb z-|-k=LlkLYPq!@3a+z2hnJS%}nRw4sE4nw@u&;=jUf&`vZFkH!1iVxQ$2l?wya|E$ zrt)!b^zU9im!2Rz+A~c>U*X}`)8Sp7#x$DWhJ-k;LcRLLw7JpB4hvWZ9ZQUce*z|=P zL`iwQ3+x$tnw|FzM{l_a^TC=n(Sy@Y!a~q?1ugN!J4&ZU|UGbT$ny5(o z>$kfpw2qxZh+3p%fG7%|Je`(v$kycTY4~|VbE6fM!r3q_{<>Jrux@epqlBB^kXjCM zg|RJ*TiFShH7EJ8;svn^GVa<)UioP(lq$eE)^9jw2-`3$s@C2+|5MXy&HMVx>JBPr z7O68(LORtzH2p5qSJ)i~*NNp6d32)tCU0Ys*`i#_oeM_D6wdF%t+cTJ)XI{X|4DjF z*A}`^Q3Q%#&k>CtnB06c`d6^Vs=ShHhS&_W7vOHrt`lUw5OJhLD zwwkC8=OI4aq{z4Rc1vUYwST4yKI%NX-4H@*YP=O!Sf5vSoPw*-puV8x*(KsNZHs1sdx3G|lTEF)KUYEWt$@-LEBXvYZDD_vEMG8_FI$R|mv|o{ z{^N2_xT)U-r`bH`#wH>1jU6a{>JdC`0>JQ29V zPmwT@Pepl1dvO!)m>FWkU0RzskT=FUfk>#$DC=5EUuI!+aD) zK-J?+qT{y4&b~j8Vr*z1q_my4eNoYMT?6cZxb{8Od{#S9+~z3190rHXw00n=Nnd7rl;m<;oX+@3aRJrUa(qBzQPRDiWv$gJSUZvLHqAL z)%OKmZ~LE$8pQUv;tzh)+oEpudWmOC%y%r8{6zOezGS~48i zq4+n`UkLZXW}eheOT@N36#q8{zr}L9r{+2J%rtz}t;SFrYdaJ(OZaIVR z?YPRJr}FHZ<%;lF>lXUO|K5J3U(y@(yR)3v?=c-I`9GmKP!8{iDwlW0Mrn6nTVVFb z%1M^&eR54}$v(u&HIVDB;G-#ZD$R^*1IazpW`w!hY9&ocrKFEWVS;J0{MV5}l<|)A z@}1+qwAoCT4Nc>^*MwF3XBd{Y4#?d^v7C`DukpFmSy~O*E?vUqT3~BanQOg5ov2{1 zHA#VIaLpdbZQ|@Xa}D$laFR{F^i!lR*sI9TE6@hJxhN2m8UKa=XH7vfHMN5B)SMO? zQ^jTFz?vX})X7d6F8rMh_tip7ISgLLDWZ1Oc+uSDHVmyT^nj$su5Lv}hpej~tmxcp z>5=a~{DC<@S)I0PCW^Rb#ak`QDu!FEAM6%Qt6G674P2l)YkO>sitL*F(;7O+SlRHR zAHbp0sl6g>rdE7KD{bjIe!)j2r5cDSs=$z-?$B$#5^(cHFz1`^BBrRO| z!fUBX90U3ke1_ecT=Xp-}_dfSIFf;88%?kv?7!aY<8i&g$FGRN;n!V+VKK@R6g_+^wd ztVNo~M%8SUm16^9-*nU@nVK$ge&Of*qNMu529$Y-lN|qjOc*lhhy5q{J&N29gfwGN z`FI0R3im?-GX9{i(xU)d?i-{p$kkeo-FcKimQM|g#1ZZGh5pxi>gB6Y%65j;dE_U{ zkj#KGW!I$#G?dmnq&?ED^uJxa5ZNaZLoNrQ(On98Mjx~B4x_xVZ{=Mcb|B$j=d-m< z(38rQf9q!^mph_Ebzj0onR7Ygo=5W}Xw}ICEOD~<(Y-D{)I@BYuIvo3Oy><+x~4mV zki6$<)=3+C?o9Es<@<1rJnD?B)w6V)8=8gp9yr;og+=LrS{3zb(zwzLGq&O+1{1IT zS+7e#ib-;OxO(^ht%wyhYujaBoM)@2urh+r+fX zt+yiNZ?;j4qQ9_&3l-jccz)<0I$ww*PlGIDqp)bru3yX$UJ7PG1Zq$HR{F!gub(>( zFQ_S3qO2K>p5Bi6Lw(Kq@|t~HCC!r`1SzrZV?Quh{ZK!!nGih2frt(nhjUB^Zl}s| zj;3^kF3**?D#n{%(1IN`j81xTrj?Je{waErBd-30h&eaQOxka%6+-;mWtd^{{5Z-G zXp>&?n)Lp^FX1bx_TMWP1XRC#si@agU|F0M5a)|b`W9Vb)Yr4b`_D4TMTS7PW(ied zO;IT#PClTV*VjNJQT*PHCsrEA-_smzv&t?-0P*QANsGTmI*|a0+yB~qKcwG%4uei; ziqNKy@>7Lc(wC2xrVGp_mh8u}qNbcq_>_XJES^Civ{q_WSQ0CeP0di5)syGUxUtzF z>lgFX2)JHVy+18?TvYN^Y613AX2aW@mDZcfJ<-^IU+@A9B2JLEM!%3}k5LU+sB(O1 zCRJtxG6&myk`_?nX5y@2$BGH-?ZeK1iW?enTh0Bzz>j6`iPLyA*PS68Pag0X_9{!_02>^=?!)gjSX{P%x4sWKlEevn&UF>%Qhb>4&f^UOGepD zR9~3ZxFeYnX={EtBt2j0v_%kytb&`@En5MT2BVD8}=?wQq;_o z{8~iPDm5+!O)qTX140*nM1?qLnyg)=-X#5u4Nw@xtrN$JiN`jMV><0#6a7<{PV@rM z!z((grnRo%9mSjAlh&JE{0_qVtL=uh7gc|;q;lw1JbM#%Q$5HzK;P_?KXmYjwzP9F zQyZ4xU+>iT4vSXkZu2YM^eyS#*D+y{6`{`9nf++@rnHZ@v0-kAz2+^9Qx<6R`7rxW zSAk9+%g&9gA|56n%_$AQ(F9es_4omUuU<969XR2U?EERt55CxU&TOb6Jb$$OqX`<@ zMu)RMuurpdtXo>`eOPQBTCx3I7yDteQXKLrMd93Yt5x6Q)-bkLA0ig7FZWB!U*Ych z4tnaEeav{Oz&m{Sh4yXPm4>OKpSPjBDI;^Ax?1JCPmF`F59z5*>!aXX0(YvKk8S4( z?f-4v6x^W!)IAjjX)C_X$yTXIorTtnBK7UkF@xWVLJ4wBYRcK1Gkb8&H?pLDzn9R| zB0b=rgjbyj-hAKU`cBfABRVtFFQhgZU;)k}CP&Ns48%_JKX~F)zHwfFwbO;RhdrviP$IjUHpM`5hv4X332z{(N$z@zogz2A`NKxSw#e2Xzs6I>DDr z*`*>rA6=6l>Ta;fDh3vRDkuyYhZ$Ny>8(0~8UqQ4>2hW1_9qa_idTX&5uC{g$k}z8 zPbKXAB5@6K?QwlGOnaUSsxbABN_$XZB1$@fn&DB^V*uatU-X%y21SzD$2XrRT{#Ab zK;f!hjlYvuw(Sg@bT(&oafyK0b%C3+G|}ckZojY1eyi?Tlp+{pyi~HtcY2Sogoscx z7)c&_++s#Hl4e@OQ1>-#jZoXoGjo4bA_JbsH}=s)zW>|QHA6?lIpW*yC;1Cx?<^-kWLa7J$?w(1BowO59j8#WGc0n2P@^)v^6hE=G})ti<_wYw;| z0bzd~+P0FfyS1zCIDDZqeCERK!B`j~0MP_p!5H2r&!qp0|0I`iJ?(_N#KE z*aW_h3u^;n)VbYFy2BV^$U9-ne}y{vl#^GVTm;nw)$s>h*?-vVqtopH;-lG zhpeo!V=I&_m+iel#G88AG%z4FRkFLaFEi!4kA`$+C4>}6g^oR^<2LBuGYxw)vKKhr z;kBM}y^6q0t1IUY`ILH_B@7DsgUR?kf0V1hC2Q|3M%FQS1ZWtv9~Tn^azMJQlToas z4@*$!DH72U)Vua3l&0Nz!C$#l-LMR62f$`+fbCn(8^vy-;}pCMG6AWoK|(^MD~XAq zAW!=+kFT=RH?-9cL_k@+&Rbocx^bwa?IN2d^M^46Zq0p$44^l5{=p$bDIp zNHh1N>{L=Mx;CL{wTuECVxeVy=d&^Yr^`7z$n)NLD~hA8&2vl}fitS|m^K68Ee%(# zuav}M+22t^r}x@oWbkpfyq(V+-t&yRR9^j;49=Eibdnw|{m=R`O)|*!@81Fjli?tA zYJL;PfBh?|IHp{Cj~;>VvfPPwrW-(7$NfPdO9qmL(Ib{boiv8IEPdNZg1JSr)uS_Q z)IBRn64{e>x(McKzHp3!jFr95a?2Ogvhtw`x9t6_sb$TmZ{6wW{ok(d%@!<^|k$S>plXJwt{iQnUa zpxTHY6axvvU;5jb!4qvb6?-R68kBL3)2j8o9qqRy&m)?1Eb*oysh;whO`^2b=#(kC zYmZ*S4se5LS$hGUB2J#CILH_PF)%-~XGKCNt!=LNGD%3#8`_(-If)uMRbA8S11qhq z)e!KNeT5X1u1M)0-4Z+{@^b37M?Q>~K|RAiLkq21V&fGp6%1NDdce%(D%YKUqKz88V;Fl`Pi;=aw`p ztUk@LHe_*SidcaS%v342n5(JcdMnSR&n+G8AMv962fX2C5UqN2bP2@5lZ3*Zh5_=+ zPBlQV0|fzH8LR$j@iSL?85_Ud#}%%lP~~^%%uKpDRZmmUUBJ~`KVXhUYj8<*NvgeZ zJmND!xk%e_Xqe)M37K<#Hz5>!;2E@md7B5rC&_)V5O6jrzj#@!$bV};uu`e-YCrAd z=WNe|oxJwr2V@(^jN~_tf|-_0JbXWd#lE0sH^aXcBy=6vUmHWxo% zx=-;`d5rm-+v?18;WR}gJj))s$K$tb_~*+~jo=hsT=(3Nh2p20pqxtvoVY zKP*pA_5fZal#NCWMOK+#LYm%pqM#vlwpl}k_jzaRqLkgC>@`33Y0AM7Op!OX$(RYk zX`VrPp9sj6gmzm!6Zi700gkVrT3DTRKa>X2)Q4xo@huab5SJuGh)o*M!%Rzz7A_0G z3W_PqM7En1$G9!o(Y>poo}ZE!(2@gIf{3~Z{^TWD-cccO}?=> za?p}p3Vc6!^C;9oMfQep8{Jx`8(g|oA)+~F@GwsNMCR3K@qcSVe&LdA&apfVZ(wi2mNgb1cfUFPrT&6_+2nW@*73WwM)X zAiYN()XURf+;7U49JCsRSNjKNYB<{@xq*pOlF(>ANQYh7WRI|6qqhM_pXRcXTUFNz zPjPhNukB5X?y*pI53k|bMxTy8;Th01kY|>sZLd-o`i>mX30LdA=UH1c^$14wnK(`J z#JYrgVSr89YuS=n9Yj_+-F0sbZOX$rU4XY+K+DYZZjFz-6-85U7f`Cgmgt z7{By~ZjVqp;q>XO4~}6lb6$DG?H3AvK*br)Kz26ITQSwPct6Fciz5=L77@WyS5~H*bciSD$8!~ufs~7!>g4gi9~Jw zNkU-3ih%mn0CjT-NH@MwDe?;|TL5Kb-b{|(>~!Pdk1qLX1)y=B%By`F7L<+5kvB8$ z9pW67_MEWi{RX-0F$F1p7Le{B;C)_-E#ooS&ZD+q3+b7AmZAt2ahNu&T!(1GHr4?8 zEzep%IhYxHwI_rNow$!&2=hcW`D3_(x=F)dv%ZH|YcCmq#0|?a8%k0H_l5gW00XRt zY2dbqGvWir?v1Vz*Gr^p&LtwPkiRqhH*NM0fA=3T9YkNsYxVYpRq}rX@9T&tC z-oK05hgBt6A6d^pIT9U>K0KNpE*<)M9gy~NV%}g|*i@p*Z2o8P(E-uQ@oPvr1MkNwr`Vbum@t{+>h949UUSp9V`0;or8Gd- zyeVRn_@=D)F!>giiJ9}kEAdV5;b8R>A_ld?@5p>j(G`ISNoTEtEB>p>U;CJM^%FM@ znI{fybI_vz*wKY}Gy(5Kspl~XoN>q(_U7*1pM3w1?n?j>dPE^2VU=XvEm8OvAsW~B za5&`*U@<{r$={mPJ#~&x;@moGam&=2=Ct)+5LfW}o(&MONyzeLmHvy4kg^0x-;*8L z*9Dk7Y?!PNvV3A|S_N>WxpUWB<(NjNxTszzY^w>ZWE>pmv26$T8x(tG}OUb3TCUZP4a0J24Rp<|~5WLbs#zE27w%QO=AOl3)u}>7t!hv^WM>l|$()LsAHN(|Cf16kPl1*@#CApI(c$KPS|8Mw>$5a#> z{|2~hS!BQBrbWUd+Bpl*GOKeNa#mg8Ica_39DQekx@tASvkV)T`@g0GxY7Q$C;N9$ z-ze~rb^^QXN{=qZ1_w&9-)EGq<44HxJN0jE?7WPlsF~o643z5J#>~jwiP@co0A^!h z^_wk3HnUStG?b6Ko%h4yRo2<#WrlahM^voRBbLfXN&&-cgsN3xUM*_qi*uI#lld;P`)fp-bfehz)kn#Xu^ z(`&I4eHwG=^V9!z@%g3S^yjDl>tcYYm|O?pipuU+pgH<9uq@<0o<{{xgLohf{rvR* z-*`=Y7%|jJkom`Ab98gaw>s!b6j6My84fSsPS5TCbmX*}=aQgbi$YE0Df5Q+BAWLfw{c!OIb~tfZ54@1U@P5JJUA*TUI{ zogHw$t|`NWre?Fl^hf!~{E_@D+4)pg8VjuFd>H2l@Mooh~1*n z@P`wN@@#yG&>zz$uv=e}&;DWZ((9Mx{sZLU$mn+0f0Il_uq*Y`UyKVh!82 z+)zalrkdRUnUDW3@o!GfI3rVK|4mZ>8CBl>qd0d>#T2paK@Sx-Iu#M?BH0M+la1Rm zu%~&0gLeTe@kNoXfEo>KjUwp>;`h`urNk{$K({OWHlx+8`^VU0ri$!q6-cA%{H+jG zpr}*XWroVKf=I3;m9{U;-0(+-QR+4FM=U!=zaBHe8mYL+OuJ<&T6A^sRFkdIT!T97 z%tglDQb{>@4ujiasf!+ii~2$+l7%CLap_BW(*XK>s#&Up~ZxM)B+!SMKQret!g~j2unsROmF8r9a5^i?d(>(&i6R5Dv9rRng>c54hrAy;egSc!pGFDgo<#} zv4sVM-0(OOeN6~6AJSQWpLpy$jF?uURo@+2)w^2y(_8jIM$s(=%@^kd^bWD+epngD zKDb^tFQ7Jc_=+}7*pH=t#!3GQtd!^iIIkJDVj5F|_})M3t7gAtuz2GC2CHr4Gvh15 ze?xevQp5R{RQq=4GJ5&ZJdV@&50Yt;)N_}(i5(z9pc!}b^|0To)*^?7StJ1k?U}XW$fz&*DQ9zNrB_4F9nsv! zzL9&=8DG!*_f%wbsUBWV-+c4k)RfM{No_2l`6A)hMM~nm8HjB?KHVgWeq!8#*irxO zdvCO4&c61OF!|1v-YBI!J7hC`NaBi6*PCO~PfxO!rAZSM;l)M}bs{HlVt`2j*-vj@ zRG%PA5=+&9ABR9~w{G%>^i3`8m00h&CAQbTy!M{6bnIy_Zr(K}VR%Sy;HZ%sMAV2i z2B$q6E3j`|!b`&qlSTYf;w>2|7t*;wG&XYor&zp=kxFWXcK=0?Ht!w3C9K zXey^1?AY^&Q$@MIS`c%KH`zc%Oe@j{n+{9F%2s}+_C6gM@Bs1M?#9uUllYs6em%6@ zNUz#qY{5U92cBqWsr*7he63FoXb-6uJw7S3K{t2g7x5257pfzj_&EtPcLU4Yc@8Tk zi*07zQ9o)?efm{Kg_^}zusWPxcTcq?azcPI_NJI)JHJ;|A%W5>0*_?LS>$6g}DS0h4wJwO&!Nj3Ap^>cFNm5f5K!iTG%*3Kt z*4-!?V&qrh*L1S0v!;V2992J91J^SI(@9L|HElRG(z)GHenB|%BUIVQy)ZjTTztN2 z^NbwSL)I1QLOK=zt2#V$zTg9ihRUy#?q;(HeL9pAYyMxvV^J=*WT;<(FZU{20ShOyxyLN5dP-UHt@-z4JP%Fm0^6fNQ%iiyvR%BEL_rB_oKVaO1C3d6_G+dUikkNCW#eH>GCNqR) z($2J*zeb2r26f&C3o7d(N~OtqT{fHGVbtv%tO2#7JW*ES4Y>&{_i8f}BDj~8Xgnj>0W0ve&2UC^dSGkrS^7J*GpPs9c&&n#j4$(*k>np_q zPcHVkF9~P59oYg~#U)|y)G2aWb%%!+L~y;|PX&lgAa?s_`LL&Y1wx}#*G4|Qbqsn!}I5bp^51^D0Ma{BRNPMZ`T!XU$y+F@kAvQSkO(sw$# zogM->M8JB{%Wu)8EuUgddt!__;v7qsMb5Z0?sh~FaZb^JsCCR8{+x+kD+B;Vvglg3 zxXT~hORy?ILY~9a{?qVvGKb<7($|?nJeg!hO1ag3R3R07$d@ifr`cWnbJ7N{bWF^) z^&vfJgc0OvM{lyVi~>qhR`Zb`P&Bu;ee!0-?Jv8#Gom*upYDB5j%P7_E0-5D$+XOW z2j@%2${{h^!T$_H1alLX4zvQw-4+5VRyx!BUONywqf35nd<#Z$c6J{A7~yI1VU%4- zR5F!!1S_RWD70kkVT^KzF@<|qHnoB=F|eMOo0S^6zTCV7Nx=)JiM=B)k9g&3s86EM zALo^<%oSbWQ&HM3rR^S|W23q`(!!scFdHWmF*3lX)5o3Zgw;7@F$Vu}Q(PKH7x@(n z#6xGGqq)Vi--np#iiC6$(JN*j5oTdDWlei3y2@3H!pU4vf;@Z??Jm-BNB^=7iq|># z^y4X!<+BUpmm#;0VaP>WQ-%Rha345W*l$KgCDRLnq4bC{MvI|V{ApTFVry57P=_At zvH|-FOt)GM*q|BcmC6L63Pc51fVNBBaV1T1y|H#|0n8d z_=QIcjrmqp8LUNI$MTB zswZiwR;hOR#5@hmBYXYB6@#NsvAA@q)ySWj-|*z9);bRz!U_01_kjUW8v?toh{!um zB8mmTP*ZtgR7+j=$7^-n=RF*K19ZD=6?SX-TEGMQo0;Cxdu1oljw!QJsY(xH(@yVq zG^3%#L9$dkOZ?EPKI>`~SqYm9Go8N6YbGabR${aqnW^aQR$g^cTPCpa`<=snJJ(n5i#Y#l*5v;8L1PO@n zn&;_4dg*YmyJ~m8lxf!P5Xk`5ItcZ!C?-Y-1{M0*P5c;1@sP;+z$(t3&-??zb+G-YPj^4zj@=WUE zn1|m}BJJUdOtiE?5#lA++ZBqFef68Ss{=tm8!Hr8rM1IcY8{L_Z&;TvVQ%%ZF)i5Y z^;pEHXrh^c)Dw}AjVjs&tm^C|IT-?sbhGgX+|uluJ;~cSDKYC!BM1A6iJGqOVa4DN zS!QDGno7EX#dBZaAw=gEqnhc0S z!0zp%>lPZ#uQJv$^-JO>bShIS%tc}&9=_Txr$GgSb15t-$d4X;Mm{%{uXx-h?67DFiz^+~|wnUdsF`ID2mM(wa z+wp{$NZA1EdS`Z7+FaL9PLCb+YBQQlu+gZ*U4VFMJK_OSWOfU;|HOEx+N#xB6}(%0 zsO83#j)|WOdq|?!o!F@z+L`)@V{P%IQD?gFf|}dg&om`k|DhWd_}(^Z@gQ}~l_#(0 z<_BoUcWc}?d2!l#7#(cRoP4eK6fPwHudB zo`=4jki>#Xj_(m}exln9xmD^UWMG|YZ} zzMRvhyYCDBTOV;CNU%&yIL5{LzQ4Dl=vLF+2M1B>RsY-eyI&{lSb|gZ=GIGD&3wO}#5iVj>^X-^A+^(H?PEQ&SW_9nb#>t1r&x5W; zL$2ReGaK%Y&jsdNm*3x8%>NlP#)wpi@TvZ}t@yj&+~zB@eBKGYe5kv_x6y^PvjzJ@ z^+h|gihrU_)AOOUa!|yei+akC$wApbhreb}+G%Lv=UAy;SMK{**QC%5`dP{I5POFK z7dr_k5PacNEj(0?{)}Nq#p6{2=7n?EZQ9wXQ%K~Q5)uVS6WSKqnK?qk$s2k7pXP*e z@P~gdEySHv@rJPYbU_z>nL!b4Ubq2yrgww^(sz-n$adIr0m0Vi7islfhy5!8dc;o8 z3u&wV4&pZ9a)uvvW~Dk8ypf<%)^?jPy-W&FQDZIdikEh#%2;N&czqXF$-(6A`U%~T z=h1k(6a7h52y$;`C$ji9(#zrYiMk*IVjYa9JUjk`&%UX74Iy49xl~MtPGG+GHsw+f zsnKCp`QyA0%2l4|6U7Bb8xNcOP2iYs_rz$xS7L)u;5?yDs>pVz`<_4d&x+kzErUEM zwlp&XU4zEepV46MHJn>m1UFf&WK2xQ5RUOiruN+HH80PHUTHMd7m!yLJbGlGo!Wc< zmcRV|9f+j2*IZA3Ek!ea4Ye$PKuBG_EH9;`iZ?fps@5k6sai7^&n35d3S44CkvWmp z0i-_dn38Ng_&|Xhfxlx`tt)$8RcA(t`e9$C`OTE;VBHcw&RAmLF0|-CZ1O%OFez2g zH=jcl&6Koig5Jjelbl7t@;<*K12Qvt&qL>m{&*uudW%&77G{}j_P6iE~;)7`}x@#Grd?Tb%$Du0vqPRG2o__^ac3)Dzi<)tiMr(G`Ck zVvlTEc^d|_PztbCy@p?-yh4oos(QRSM{82q<8L{SDbe4 ziIWFyDNOHd?1CO+nnAzQ;D>TRxS_N;JVj5>U85MH$!o zoFvQwGH3m?-+d)s5^fYi^W)cDn0x-y<&Nb^eGcm++}K0UT2|lW>;i4~zDc zko(51Zyiq$S^B5@azQ6w$bM}7loxQx%0jlM{;VXUD3^+@ZA$cRGEPhlwaB|8i=9x@ z_08$XcrP(+Os?*UoSFl5u+#Uq8{g=E8NObXajv}Dy$jFj!>xr2uddasqSgE>QL7Wa zk|W1rG2ZoE+)2F>G_5M9+He+&L&kxB2#j|64&3`8u!zaDsC^>Y`=hU(Mg!W`L@9lcXia=`DkMx9GRI9{z%5njCyWl_l%bT(ILK+k z01r~N48O0;rl6nHRzY7QE-%^<%I4w5wN4Kh-z^`U?p3Q{fR#D;A54=Q(P|2_ACDF{ z3`XLggnE9mx@TzmaGNfxXl3cEx^53@oD*CUgJ zhuh#XA)?bU5!k^-{s&5Gz`ISMY%$AuKd~ZA`4o_jJG!fCbe^HW>i8I!Fu3qjjW>J z94Iq#jrs&IhXN5_J``U{1d@{`V#^Y%^(VD?%l8Y9VMdZ)NZ_5}E@SHSXt@K-Nfrr{ z0ta^YlUx-&Pu9YP*yp> zo8E>26C{PyzAzX{vwGtpcnT~;0GzOOhKjG6LD>+)+WSrYf@W`Si$W4aV6b*wYB_1oZ}mm>a=UgQWHBCBMj-Ay z`8(dLU0VR0$89%({0mdEP$GCyog+4Y63!Vd4`M@Ge^w#5*|uehPK-H@0QTQD7_o2O zb^ZFV87j>#Iu~(PdR@1BJ?G&t)`A*UVcaD!ZnGw$bN%opszc=(Rn`QMbVQeqA>%&J z#%?eG$Tu8oz9~M!_w(o+dA1WL)A@}+D}bPL9Jqkwo5PbPy;do=0VU&zJjYU!e0YDL zB?CI1G`!RhHWtPv?CD615uj>5-cK#u1{}^2!q;AU9J`R2!CVPIvF^U(MRTBE4gVFhyU1U6cgIV< zAk!Z6Suf2AHFtERF@1bzdr{aL_1q!Ecel_QxYgg9W~f-;a4xH0s72%*y{PHN-C~MA zWxeopNwj%unAD2j1@_-HBwIb)J-%8utZ`$DJVAH633sk+cB>>@J={LNT3a#RHRR#T zhoD=yN!fmJB=`eAu zRj6!dR;-34ebt7s)n(ItDtv>tqOo_?Qqer~E8R!pk*&2*tRJOw$`9PpSMJOnB3x&~ zF1dl^>9&C~cPJF@l!_{I-5xED-oFmdv}cFCvG(4IT{8#m>TKZ91(+9MS_P~tkq_OE zWQ&5Xe40gXS0-%q=`0`oBw9JAbH z#qZscjLb^mcop82bWOz~-XdbHu;NdK%HFC%fg)#73loPZ47R(KbSA2;&%UO3^@+3C zmBk|dA}Bu>6nWTG9ROcv%Q*DP=kdMzs4GOqFHR90wTLwuENicR2BbH4(OnWSi?vqWUc=H_c_^Ay?CPM(hX#XA4^{i#+cVW@s0x~u}V1xjN3UF?YiMNebuG_|563i19@N0+$# zT;A?$=9Ctn#12&7(jca60f7fPbLN2HUQ_3EP=n>>t0qEx6+;Pj_RCA;!+$yw2tedH zE~N5RzrbGHsuMTOuJ<4+A!wZE*SKal{d)wWXqP^3uEQ)6WSd;fUs+6_vfch_;G{>c zTwutrAZ>$+NviW zb9nxc^A(uv_j&B>80!_E-IsaJ#ON397Y_Q!6pyKuT z4Vt!-u3wKM3h?sY6o<83`i(`Dv9TN)I=D+P1=?|Y?j^*S)LXe*PS0k~Ywr(vw7>xk zM_HPsS31erE6~zI+iap|D`p`%Iw$vo87V7`f}`mV8{*WW*-G^*dtbHCE!*pr7dn&p+WXXvj(`GaT40lZ;h6Q~QS~Kkk123%(-? z|Hv0#w`pA-^}JX@pEclT%;J=G2+im4r0E##hWY9{@I==sn{4ISvjS{qe`F}lI&b=> zGANg14-9Ke$Lz74xdqSihdr8mPm#9-c#+Z6lg-o`q+Ydl56jFy{T@Gtl;7+^G1O&E7+8U(BPxy()BGB>P?v5_0@&4FeQzmiM>(3jcdr5bbEdpeTtLN%VI?}*P_2W8(q$V7G%w@&yjI#`3S!N{!`u$n+;PHl+r1;*2Qc+f~+Jj!<3csMKI2@|ogoo~15gZqb-H_;+NdhduXU-KQ``JLVg`xgeIPYsFx)897cvEf_ytN$}>J@)pZ z0q)XElanJiw(#x+EjXwgH1%MyLj1l6T0J(+6=B>!X4`5qJWDT zQ<$ju2fG_eDA@+mR3NhUFWX0Z80-aX%UFr{L_=6{Xvp~E9_I&^ae{PSI_0F0>@2h| z)o9G6&T{@3gb|KOHt^=*(j zCj9Sz6wtzjJ9CQGfijP>4xF#Z8H^c5Te~o09&XxlulGd8ku*^TdTi=&9mOMw>j>QF zNzgr%k}C@Wb3lY#*X!K)_TpvtW|gEly*+k0hQmR86!1sQQlAdF^E&=r#>Vz1&$|!8 z>}vO)<;nL@Utnek=IQGKlCqfI)?xUOzQm$DA{zsKiK6B&+43*Uzem0ZPWw2;{UP~5 z7Q9UQMPeu`Oa!le-y|+7`>x*~W6VHeJD^R`&PohsF%X9Mb~5;DN@Al!T%%J!!*~Br z0?GsPk^9vXEq@^UB5S8qF#49|7`@RO&|&gr_q<+b<1?z=GgW`T-eq}0X!15$^zz7w z?$s3O-TsvK$=mUP$>NIA-7`O&U3=S$Fvwm*w5wfA-RhmBxLj7>N3U?_gpCmZZS?a9sH z7;X%DmmxO}WMC}Hc~{co5W)Aao>tzp$Zu$(-{M50(?k6Qg7UvHXAuBZ+?gF?>4 z5SKu`5Nm;se1f^|j@ot`C+a`k2T*IH19yCp#vs=-%a^dmK)W`y!vN1zVLN+i2K8!+ zpAX^ub@VpuUO1Ubs2=w+0K;p#xKYXLhW|6kD!~d#Z3m?u(r%|9f9v6z@NWrzU`4#! z5s^T|EM-@*|G3J*0XsmoE@*R1<^D<4#iv_j@Y-8u(7d!eLLtQEw)D;zz)tiltYO!Z z9Ik>9)YbUc=+*78E1d6Ef(9=42c6c#94k> z)J7fjKFcpycr<52M24{_N;-hy^+jhYr*#eS9Pr&kaF5#){eHWvdG)l{1{hs#RhE#? zTfhZ@ZCLNDt_>G+Ogu=~a?K}EOafr${dnXp=BxQ7%mtS!j{jzeK+Gl+OueY^o1tO! z%_!eSdW1a}rmH${L;ACWJr`h9@=R{AtZvjW#R0Dv{Mi{QYn$m4b?UOHFqFw|l^O43 zni)UBd+~RYm&u_v)jacE)hb~>i{p6&m!|9UV~2YqGf*FsNCYw_MGKk+A|Q@ zUE?(G1+ZrHafFwvBi+HWup!-O!Lq>NI>Ej+u5(`cM{zBXb1|B{VYJCH(`U7h_ri2B zI<-OP#Zu-)w6Vuv^_ca?;ur@++zR0nRWKHf@1~|Aq_SW4gBg0VHdFQWM%7Ng_S6$a zS_zjLSvL{13U8J}b=Ovy*sg@uBn4G%qpW9MzB?U%b7aanWm?1s%}TtRP|0Fpb_1=* zBU~;kncvTZUjo?~(Q3Sap9{asBH8X{ZY@j!1d@0dm(ZA-z$Z)nN>;T8{qH>l7|4UW z=hCCu`tZHY9klN20IC`#yI}BMHJ96|)$0pQ~ph{J`x`>|pu{apo1bZ|0)`FpfVc)%%4|Xa03<(sidi-_FMMXK-C` zVx`t916FK(k}4QFBw`{LKK)x=enuqbEO@G=C^)z7m_hik+2lP2-{#=kKQR-9k&<3v{a}tH6AnLOs(| zwYynIIzx*$jj4DVym6mx<;-QtOd%aWN53L}wj<84JKC_G$f`$3p%SE2`B=K2e0X_~{NLVkoH6^j zc2|>wUB3I&6{%#nQ28JX@Vy{7g9e;(+0wrWebKpmXJF-_JO#4)>Vk}A3{ND!SMI*s|4|58+28=XF0cHA90xMvhfrI2*|}7f zfiAc<8u#Y~#PDiqAb`?`Ago%J3k-Nm8^W9kf)A4Zq+^CxFk!B_Nr}Ew$Zeo#6jO|S zPUtVQ<1ppLj>2BsnH5zrttIL+LljnC;hWu`KFNMG@D1=s%4&h5d znl{29EE#kSSDPNJRim7j6ocv3Mgc2DduDCHv!v$l)iO0;R`dB?an-ciD4Eb#3!Gp7}~6JTGP- z3RX8t)4`if-Cj6m4|^!_RMhEkGL)k8l}Pd*x~~s=WTqk!#v{R%Q<0&PRh%N!#>Ao% z?i)Ewnpy`v&j{K4TfeX)((D8|Vm&spTZTNqJNc85d{#F2d z#=ITG6e^~%;46aS#hjj1KmQg8ev@(k4$I2EZ-}MXa9f*tGFxnzs|lEWwc^8N{1eG+ z@E+Tbxqd&vO~?yYonVzBJcSXOX60yVCmd5Q(#M6+cOi^T+Qp?x3E7hL8i(y__J@@(qv5vA86&8#lx#EI zJku&%`gFwkrRyAm=J`kmALR0A90{}^k$LY5uNIzKJyp0s2H701rw0yl$%AwTxJJ{g zGKe5s5k9o5JLxM}!c&XgT&SkfG>}KXi;+%@cc%(ih=h*-xs!d!FRT&n-+ z+rx!`i}1dV-~)gaG2h!Vzdv|~d{Lya-}l9H=zreg%(iZu7h$FJkgM#*Ym_rq8Ej<2-*2Gq)o2f7aGcSYhn+OGFKCP3#Qz0Mg?$=hyVgAyye zEz>8KvHYj>?ST*v{-Z8fJf_Ph+Vdx(K#PE8??lnvg6%Ys28{kan~ba= z*LIz=|K5hzzubnOlcnYGYtAn68FkNG&!(3k7NnP^|J-=;Xyu_j&|&3}yPhr3{=<%O zXX6G<0X*F- zY*PH)FFtxhfXNibSdZUDJ%aLjC3OXXU-gElKgxq*@&^X4$$pQnboVX|@q2(qZQ6W@^3+@Es(A4P`YEHv+M>~UsH@AjIs;VCTJq&D)n{TCDJ8+QdP z8VhQGDwZ%~2xG!0iQ0m3mj;|khd*mFdW>^s^0_Z2JN!vCmX~Gj<#8(bwJ_Zly0OD~zvWh-gG$3?SEDP>ZXkJ`T5FE)VWDp$zWkB{3~2py~Ec#mTOC(^{zKl)u4X& zt-yY7Oc#n?g!iHEBi(qM&&W2U(zR~Y2eLRTtLQ7^-o|OkI2$KYSF+2v{z@`(A|Ja9 z=n38M-VpN%N9^U0?E4l_e?Qz-%*l38G#vH5mY;swiB8TbUqM&ElHz*|e{ViJ`AXu3 z0%TdkFT8)DJ!$hCgHqYMK!j;@d)d#>ieXqz=URQJMg_))!7*r_zCR&}r@qWIJd(xC z^mCak$pZe1KX5orXQ)Ok1x&4z(v#((gU8y0FUmOlmsCdzL^q6VU;~k}(3uF_QcFp$ zIoeIOpheW7eI79L3*E&hIpr#xCxv_<0p~FufyUi{or=vMkgHJU)!rbm;TQg$h zO@<#5BSM5X%o!w|k`76&5}bD8N_TGm99(+qnnrQmK;lO$QJ z80z%N|BswD=G4Da=7hSP>Epmb&N`~$Z@YsvuZ}pK^iptP4y^x#1RCn>xWrkI?W8kz zXR(TJ#AgeV?CO%nzVA+S%nNvWKc?d}S=}$Ok%-=x;gD?im)3Dxw7h@9Z;`Az!=tOB z(BM!vfxr#lzhJEYI*i=X!||tWZ};8Nwhv;^!vz{OIGh6v67aQ&~tF=?BQTYe*YFdAye5pT*8a%X;uD23Z-PDwUh>Sl1PA`r zaIEoPzw9J))KU80+b(B87^cHAA^Y=nlB&@fxmAMwQ`8+*lwSiWvz0lbL%jMsh0NAq z9L|o>95Cj_ATGUt`Di9xzN@8Hl%^t3EK?zII>21(_=D@TeksGOt6^)+-rOE@2wp#i zfhSxe+hk;KNSl#Jd-ANqat5PNfuPT|ppOuk%7vh=-FgY)$VNeca!)kkC@Qj)vaMS^ zsk*h8*)pGbLksyyASq^84b{09=j~fF&?}jtA7@P>-6tj^*9vW`mAf;nI*o)t$(V8N zN{xqed*Sx%$P&uYT}^^RuGD%}uO;(Sem0H zhoF79Vy+ zfkq2n?CBB-{Jf_7T|@SxVdzfXOr~7n8xhv`{pKF@EE<|K>d%He35U9-{SKH(<@v6t z1*4(%u@rb=bh~mGrVN+`WVDs&9;C{G!#Ga3v+4f(WtLA3Oq%W?qaRFl+JAlj+LOQH znQd+_ru8d#swveIw7ylH=JqaDgX zMQIDsA&sXXa*2a1vnsF4)lPq}Dn?#yjZJ8+izHbDfA@Mv-!S9xNE+o{O}!d7I(L+Z zFn!ribj`+7&6i^&`DxvoajaoI#Ub5UF&`8kX5GyR*`a<*nr7|zFmQ7h!^#(|l`j}h zljhC#tm%K##sJg8DUBL;4{6GKJn|u_opbCf1pUJDGN9x@Al^#3Rmu92qOsbbRAk4U$Ce6zqvAoc_J)EvzXai!FykvajB) zl%X*A=j|tPFtW1uQh4?_W6%vrDHrM@>0|EXzQRJxE#sZMo(wJ#TVF1+qTcQK>vQ0uqIfn49!xSISw`iIy6N9U+n(g~(`TWC@H6(&>zv|lsBNSY zuyEW<7$ ze#AVnXjRN1m>VvB(AzxWzG6E6)ocG~?&$k9riHaJy<4U)`I6ZnbyY8CzqqVcg$Yv{ zE5;MTk?yGEETyVJK&e>~ zd9RgvXdrQ%eU49b-c`e+5X7Xqmg$*D$lK6qxFegRVcW=z7~(qG5L9a$kiNZ@GcXM3 z99f?D+dy`TGP&4tXe&0vSErI^9b$|8`)* z>($9Oz7dTTOfx@J(C~DiE3Gdv2(}3bN*4tOaYD%rF|r(oq&3jrVcODnqGUB#Ww@Zf zqX~8HDQ@l@z$ieZ7oUu8nIKpObtmV>CPd`^;2@f4#x_t7vl%e587|yfvObU{o!t3` zn(xYZGc<_Y$Q4wax-pL(Y?ZY}NawAob$3$TYJXF0>=#fItnOBy9vZ8Tb6ALM+l04< zbEMJ}FDsXo!v7@Z{Qf~h(pn;L6tRfD?~fJsx?40TSUqWdde)i9IgnaO_NO|=RW!y1 zPAxca{%z4biF?*Phtf8e3f9YjRKITtrSh}5+=s4B_blPXy(-yEk`CrLl8~ZJ@FE4O zgVwpHoe$2|WU?}dvk+HIvOYD;@}cryX=V!S@uRC}AvPfw(XQbPd$GFcZd@XD{fVe% z5%!sIIgrn~kBR|YcxT-cDuL0J3WU2i__Gj$)d%ML-duF^Z`)S}Y3{Fi#G678j%?tT zHml+aG}U1UEuUoG2uA*C`x2yvN7a={FxaPD({+%tYSC|%*Dr2MC7T-Lj+Tv-w`eOh zHj=?(YW`szK0$3L4iv%ENmy{EucqwZ7gUr@z9?OYyVALtBy=z4aAc{~cSjj~rFJ8X zGe_b&vAb+H9MD^_EZ{~@%;Fy@kLl_^(tW1*)QHRbCc2LUc(JvBC3{5GT;alP?>R3X z=q9s7^Qq6YmeeDgGS8Hw;T>?>RCVbKocvM!a}liBZ?yPOCf(-Vl^N(w+r!-J(JEvG zWlA-GEXQ|qt{yx3?XR*twF26M_^L#(A6pCY=Q=)xv=)|Mv%P*|dn>6g$Ae;#6YkT7 z$o%7s=&g`9uA3&-ht_C|G?nV%xJ62!MRw20XCZ`-@4g}1zc{rC>3@XK!e_aaO}H?~ ztgSA#`xwrVj2f4lAAe8oq?|9~FI^^)m7TIKwGUlg#7{ONY(y-20g14foX{B=>&XUDf-q{zo}bC8as^eC-On zt+PvWy2KcP)yHEPXef5wZL_WS2cNc;2(up1*^JIxU(oWK7t#`o&duJk4 zBQlV_kA*#IdAes?(@RD;B_MU$^SD{9RWh!;P7s>ZA)oJ8BCw+0qVT`pUAoz2HSpd<%tjd-s`4|BbyVetcJ^3&UKQw>jXK=~7=QkJQhYgT6oEN}8n^5m{+SJfF%# zsKvovWc)iS5z2j>Ygr>Ih`AXv;4wmX!}S4|W!`v^7~Ldv$F^I5U>K2r*+lefSO7Zu zh|jq@Tg>M$@ye@@i4D0E5|3?K02SRJ)BaFLf0)BGB@l z1|z_>hrH7`U=`3S>4Op>?BT7gN&IiSQ!&ZuPPUx!8C zVI8nOF2CgI@x5H1lcQ3H8EyGen+6YS_8im)V`dKnRENvB!Offt0AJZDCJ1k#p_1{JqSS##+ zu8abpcY-EUCe(;4oj+(D{qO=%WjjeRX&<;5c9SvqB>mWO?$+YUPMJInp;~=ZKl(FX z>g=k*pO?I)ll9ngO4bFlTNI+x!wFp47{_PN&zgf|sUHwiGM=cukipjqbHdHWluIiL z?J8K>q7+_$sZHTTF|PCl%F!?SR<7N3*p$hi1b6QeE3q*8e};uijE7f?}_i#Q z@6Xu}8Ncg$l$Z+a_6V=x2?*IOun;*YhNz`DwvF3kAT$l>DX) z^9=p`+x2j3@lc_wPCiMG0RLf3*@$uFQZ5tm=1@q=@9tl!84+>DuLNz&Z|QXG%TukE zXoTie-e9eL5z;M+@{ke&I+Eawt|Qgo+9L8Z(51#ENbPFJ^K0h)nsJ#nq{iUbV-!r0 zZ7ztRlVbDnUW>DgcGsh51^-kkQvnLN$dBY^f`zQ6zLTcj{E08MZKj~3AU)|}Wnh`u# zLe+0Y&YUUI0IW?7V4dcL3I=1SPp?>6doj~H@sqf3jduMo`)|+NKZ&WPrEj-v zDYeZ1IJaNIycM|>pY8&Ui>mDu9S=+_{`PW~d3+3(PYsm85>zdZT?y0FT=8iuQw|j# zyz`T-2os2#1NqjA>8VDmm+g3FT=cyY{!v_UbLiEf6#JV#T&X)?)g9Lqhc!2-g)pvj zCQK3*9vF18xMnFoHv6CtbZZ5PO5>KliAMv4#&CE)bYPxg^c`lxJkW)2ebj363@}~w z-%4_9f3VM4&V9_5WSZgpY+aOj!ivvFsPV{oxRO)KTZuNEgdk6JUFR&=d(wLqL5EaK z2KV#3GU@HjUM))?(oep!F+PVJ&Xy9<-TX?5X-9baGtTXhWb^sS=ZB^C?KU$D+*VHQ zU2RCu1J|73=sCy4tPZ4?wOstrhkglzZQ#B9%C-DSu43&4+gEa~Ohb$Zf(gToZW^1B z%d{Q!uhn9#&^To-j!M=xW47<<2HM!?AAzr1Y*4*F3CZj zS*i;WYmL6bpO}es<Bf7E00$#L{Pbj;%*Nb_x6&R%# zMLMabupn_tTd{E>hlPBU5XF;{U7?)sgpLcGd@}hal?M;3+!%vk8COJGx!v!bvaEGT zMIZF(G|Am6hTHbiM{{pF*Te1zgf89!t2G&nRfRcS1jP{rVbwf0XnLiGv5-fNd!1F` z_z$sf!^2+~cQ0`LLHt#ztj~=;*+t9K$du025p+2mBL3(&ti*&iV|D)w1?EXMyWf6h z+i(fC;dLaU3NzM1^ZPUe1bSova%JMG-5hcGjXu0kx&MKZ{_(DcU946++0U~VpGCVE zagxG4`CptleM;OL*fPj@$&}@wC7y>3bv3^DuFv_;O-`7d0|?H^kePiw>06`g1U8YE zS&}LuliHxgcPVPbCNI@ma8o=QAbs1(agk!^`tIBZ*j~hX1_89 z{9(lC%04+}O+-{A*hhq5u(u(?<3gj?je~XXr0160*75sVE<`F_{Tf)b$ldCW3SWfp z%W>`Ob?$2W-0r4526HU-g)%nZvkMI6x7SH=AuHUx1S#sd3 z;tR>57c{yICFZhTg1Z-0JRULWP)} zpB3vEe8zip!K%s2#vw0n2bcbMw626}>^>zdFOyDI2$=_;fg1TwkxPajx4zCkWVLk zoklhC^Yp60xSg>7;_$##+rZzFz$pB_XVNZXK!Q>*yFpb&oiVXEPAG(6su1_e%yutU-d35B93fCoI#4CCYwomyKd8!%{SRY{f-O26_F&N7G69hO&c)KkUs!9`9q}dWF1bcH z;a^nmWki$2Eg|?WGk{k!wS_okqpg_*!ye(X#~y*zLCrt18@y?^Te7AV7y8bGo$ODK z?%}p|cCVXbS6>wRlak)(=9iMbzxk~~%9Jg@0`)TeH1HE4hA0IF_B#&onRa`>_2zKcEh@~C1*V|GgQoz{ADs26Umt_+t-07Sv8QOzGAH~c&j9Q2L-5I2V>*#mz%jDY9or?Y3Ktiq)^5eN$#IrS z%J$m$7ve#y50eqRL@;@;u# zX3v?+o^c49Ih6EOFRz}sj`%&MiBN;*i-E_Urm(kzY_Mm3EImMq+KSf&T}~a0v@a;n z>}a%TTsulNpRpW^3H`FLzZ^dr>FBg4`i+FZ?<;Si-zv-$0fH@+fGR&E!F%*;+X^Jl1J9s3XSj2=f(Sj*3} z&u8}sFHp|r{d9SGaa(~^72y@SnQO?4*DORF>yZUpoURihjFojja_|#jqR)_TwJxkc zP=v7Nh}C(B;AxH%OJJgAUH*z;Nn|XhN6=u@?E1)d5O zdhzLmBwy;WnMpM%Spmq7bE0eeV0}VH)SfpW;G@tUcTG#*Wb)C70dk1Vm8@S|&-6&h z$WOQ>^CNo>K{#GKIr*}3|zNM3k|5YtL0Y6DnDpVEn)*>{>>f?a%8kUs$KDf;rU z*d55-K6MvwaSkYQ&YwQkSFODwqh>eUK4rcMEBKR5-E1!nG%jNY<0B&9Ogerwj$Tq@ z>y+#m2gG;su#3>_%{Kb&JO}GF=6$HWQe)SZa~*B7Xh+VOW@5AGS-h-dL0uNr&00js zbgnroVy=3ZGDpk4Cw%z3RhCKuVmK`YI&s6vncz*`w^H9{2H(?e&SbHSd9|-1h^(ZV zdChdz6d7zK|7daXQSFO~d1-yPE|t6z*5?*cBjSS1kOG1?#-$9Kl+*PpjSRaRpNR!ec_( zL;+9^5UVVxj&fV{t8Cb-i+kLPb^9BnN&A3Ur>OGzgc_!4(PEOd-$QaTidYx-gl0_Y z#Ro{ZtD7c{cs7xR(B3Z* z+VR9{a?Q=o4Zcg2%hkj<~O@5Rrf)QAd-EH%uIu+|U`AtUmC z5qt};mIoq{iJ=Do|NdGZ-z7UmSc3pvn1`ks#jjx)?7MB?5%Kf2{Quj z9ixd1G+Qw5{&TPJdi8LHBvFmM^4^kh?3Q_#SIuQj*`-po030<|DT+&YC4ZP!k|^ht z>jlHgw_Y!nrE~>Q+bJ2F63wN*Y4b!p=joL}1i`m?0$5k&Uiv2t!+c@`#EBpd8hdER zRa_)?%6kRIvHvkliqn6BOQW&y(lYw>QV)uHEmP+tvugrHq1sgcr%+APMG}^NvNr44 zc$;pMH|$Uaic$yYz8dPz>0j|*^*WVp`Tgk(t3chYm|=%Dkap>%PDNXOG8eFGxQ8@$ z%X$hI7oaT;jL_JOE4BA>Q8#YgCbN5vMU1g&wT)VpeGSR@rkAtY^Ae}*H-n03&sg9P5 z+3VXf5Y04eyO_P|`%fW5Wn2BLK08Z67$O(&$SXE8`~)f`en%v-w7benGxtjlkbl1f zbuX{$7s@3R88GQ7*;a%M^wo1zY>oP7qWJzh5>7jT?(H`Z-+9pUcic2VaZC*}Bz?G- z2-YAb9oPQT=jU(zdPKG?YR_$12Ff-V&rEy*XpSFpsENTz{?oR)tQh|8`{jIQ^;>Fv znf1%|?uv=yjheB0Fqd@pwWrK^SMT9U$CZuSYi0bcBN4WlCzwV4c;sX}vhYgl$ z!rtYv)CNSbkH!M)GUxbJ)(BodY#?WK5_65w@c~3)(nnk@^c#MlQN_id7FbtK4N1R- zsls|$vfswe?xP=eLdIs=g7_Sga<;xb#ldn<%Mn%S{ErEbFDNzhwyk+B3~|HKj?#>8 z*~xzg=!{)scM~;)`_NcOY4k9kYK_eFk_w*MJ;t~Uj9nh8IsC;MDJfV;o0+a#(EK)m zeLp$!Lua&XJ4h&2iM++=bFJqNatI*b#eIqAaL&@d3)`Y*%?6wVt=nMfXfO)~=#Cl=pB7V_6uT)Wx#8KNSmna3 zr^Kw+02|(LV%Bf$8EQ`UUHsx3?NRVzM;_4I%hetfyG`bcxL-L?+R1JAA(4;bOYNjb zo}(d=caIHb2OHw64$c&YCK$GP*shitx0V^l@`Y~`x8%S5;lwIVClsuWdwfKubc z+Im(C{`H%%6~=Hd#U>mpd1YS1@nCQK$S0?{N?!+7;sP1n`N`uii8(#a@b&kD|IgA> zR%)cT2SoQfWg_d1Wn|17+_;r~uXauK0bUS_^U0`mKp0{gsD{McnU=!c-t)DRYSxZoAngQoc9dg?apIq91J zy-A{)KHC}n7X#&**7jS$6m0ysy|XP;zY?M)_h3yoE6FAOY=X6ZuaaI z%R)BC5cO3{Ku@0_kY}k46w&F^JbkdLH`dWPt-#52oko6|kP|r@B|1cN&k5WPM!WRV zy|do4&H6oVY#>gNsw>^2LG&2P?5hXRowV~TZp&C@JtXDx)36-CUPcC&$2{%v_JDZ~ zMQS+&5-kDDGY5_Qz$q&BS%?%cOXY{S3Tm*wHTdoYNh#hO>?GbPkcH1aEtxjP3~>6=74LAc z>Vcrv@&g+KYJPOZ$Nw!Zz1Dis6_5S5m{?^LHM(TWG%S_+IFt(Vy^&@M^_(}j82~=0 z)b-z)c@acgq5ldwd46CGep)RLSP+?NfvLecwa;=C_x7ZpRZ(B8HhI!_8^S6+kC;3h zv0(?i7!IfDZPVX#hYBBan(KlK6g}}pkbz(0YWkCNSo%&d+HQZriy=fjLVhMlz}n#a7QshZw6z$upSn+5>R|}4&g4{rY$_XsKzo4%y5Hyz1}Y3 zsfo~Gr5NdJ+3jPmXk~PErmIM|&sXHgS2F0;K##d>xY_^Ydxdx|lzx(V@pRPI9x2jn zLqyyiG#o~3!$`mVKp%_Y@zZ1p-`ZCFM41Q7uoh8sjCsZ7g>7(&YT!z0;1vfsYNZi~ zsCYtc9iO>u;_m&mDW?0Z(Yq87*KPm1q9?djs^<3zhz)-Y1xOmxHalU=+}V$>7jDz~ zp?c-o0|U70Jz?Iu8|(CorymzWQGJN(C`r7RZX3d|DyF-_uszN_sjYhP6r@+On`LT{0eVS-pf&gzR=IE3++`Vqd zCQQ&P&FC7ejn66EtI8~(hWPae13Gl``!S{N@)cedGNiraz*6r1d3GW0JTMmtHf*t#~eQT!#c*H2B8 zR;9zd%3%6ui@}r+#L$S}o$bS2O@Y8#?Suj#y>>eAEijt&^Ul{Bs*@BhIYTfGw_|`> zCVz`FqHmUP4xmk9wwI&QK0=qenLd%0Yq z^8V}fr^-fmy`)GxV+|Y*G5Mm#qT>?Sc3!w1Bzgk92pqg&&Zv z`f=DhIOfY2ayL&c{2{w{16{*|-ACX>UJqSW*5iS--;-U)7aXw7Eq}WSh5~T+z7YVqR7s>Ch$tT9a)+ zF@?R-Y2&NIoAf^V|9ZT`PfCY-l9>~8NnNs2Mg`&4_fF^ow|+l?&@WoR@DZmQ;N2JP z1!T2&;LTg1X~~zfDHA`@&D5$h@z!dr_-i(;Eo3h{@+UVx%@G->CAsEX+7f>Cl2?kE zU!u20T%MyYmzjV87q)=&r!>2}nZdi6NgKnsz0@96;Tet+Y|rkgi%ae$={0#W8&&<4 zVz_6z`NvlwcK^JclQ{-0pnG-aTg_8-{dsA!{;ERbo-o`kDT}4(tw890rAoU3?uU3143!aP*sNq_t3O8AywN zW$@TyzMsy;O!$0(!e!j7cT^(QF2YdApmyBc4zjf0CDW-C#y2??t1dU* zPrvXam7(b!-)Yjeyrri6d>xawq#wD3X)#o z9H0S;yUG(0h8`PKHB-2d;;--aqHA5F0*bK}kZ^y^i z6;t1SI1iM(6P`={so`R9l`KU5~>B_mIpD$UOod%JVC6?El=1d?iN8kX?AO^_LuyDlgbP`0{Rr;B%Q7 z+lH*ZBTbx}>%LA!P$K{GhvpWmBIr%eRs*l1t^8_d&yC>LCrzkXstvf^eB@1deACbG zw)|zTB-nqOIpyEdlmw1N;M-vTU@+y35B|2D2>d*`7)iSGgK{metP4t6f%eucllV)f zbxt&#@C#+k$X{GRyepps4Y@MoRgt^Iu})_k7I^I>Zd_WT2*a~!9kM0=!7LG zzn!!y^$Il{W1b)^A*V{61=h=Hk%iPOb#ZHAQ-R(?g3R%uWG*y8qJL0!)BRQn%qN<# zbsZ!=sX8DSHK)FIayp8Y(#uTx$FlJ3;>|ABflI-P4kqMDPsZ;HSwN1eP(Ka|qdz~8 z!TEBACf&7P^_6DNvC&8fgM^{-dU6EYXn1{{QejLy!EZ*&hu%7Y2W;+!M8Tf1GOSve zXbEhbk#v_esZF4?ky-OV$xjE!%h--tp^wXq)#2)t2prD8W%Ml85n>;Pf2`jV!tiEH zTRf$RH%4i^`dQ9&mJ`KEkd2t$3ff%p++2$el| zPz?ej#1A<5ULXT`HPv#p@?fhKP$o}iJvdG zE>hZUkf!B5Rj6N-5Dj>!qtmV@VH2w}w|?tAHc?_O_uZ+wlR=eCjo4qrK9P}^n~<~h zmyOt7{2~3HJ2-bHCzbOwyZbT9n<;UHLoWIXJ(|Q-ACR5PamEfGv^8IsFQtAJ7g$OJ zOU=BnDyBz*KisxooJ1P7x`+XK9XsvfYgIg$>pW#wbBY1$CA>_L4+7(uX%A1S*h89I?A6Wqtu)Q{(o{l{aETEy|0gjDmMSV_*wc~NiL?S z*wnaOQ^<;d?ob&4F?pVs$}aE?(h^(4mV5$X|6((-(#YZ;A}bp%jHK3U-^Z|ZsXFDc zF*|5tZvyBJvawBBR^r@qXPtFjr9WQjU)t(WA3mv##HJqCd9jfnq!c!9vw!Hs)coTV zojP&(OVE6rETWLNe?x4yn@}pm<6}V6xAViD@aXPZnRSe%m%4pI+X2YXbnQE(N+Kon z1o39$sC~rJGVr>j`%)RkX`k;O3~hj6?h`ZUECP+_MjW8w)V*9lIuYY!KoMSi;L}~* zm3T4Tgx2|a*=vui(B$rlG{}U!>i+&_$s^$A42LruI(>S|vK-b`;}w2o__G0AwPVQI z3}DN59Pmi%5Bce$uGx-cukK{C$5l$6#kp?u&%c`76qbA2KX)EVzOsm&&m+6kAOJIH ze%=r_c&I{FIN0iTkKvXR?YjPE9_{z-G4JbJUBZ+o*x~A6@z482D2|t@%Ef3c%hYcP zzFauC>#LMc0fujpqxSmROTB6&(}6fWC@k<#=7Hp--Uf~!40zw?b|NQ|M49(@wmO|f z09+t15z6vh8h8wrH4x~jF^*Zy37|)3^5dB{!Tu6tD1X!C&`|bL-WHZnNVCdGNuWV$ zHGgj`Y;7>S{KJ$tPFbL|4z0SD#NY_I-;e=JdA|2C2$A>s+ajOqPp3s;*YAFaCP5=c zz`?sjKF8@6z}{RfrBnlhiAY29#|n15Me5JGru<;x%GPPaS)$LGNNs}BOO%g(c=Yy_ zjwb2<28{EdLE;;C2{U6J10KybYse^6ciX-0TOnl~k8x40iRSjt#ZJgMSvI!-VViS$ zAHYu;N7`bS(v~u=ob zNj;9IJC_!r!24gM8E1XULN?omR?iLp`d+F7P9gD)*$o}D-8}fwa0njkbP=g!^ z2jt<+z|3y?y)R$RP&`z!hW@5cJWwRiHBP3MO5pib4Xcw_SThaZEuZ`%i{ObENui_tf`b$t^2Mjse>YF#*r9&&V2WPZk7Hnde_(v zTRQ3b4We6KX_}Uy#AVC7yF-&l+|{tMTPo>|d_nhPN7tQ}Eu-TAZ?1PR9T#xT4mxzY zxku%5ev_ghmXmD-m!^+TKLivb7oS%VWhrRr--7grf_J6Q3^jk9AekCe3ou$6cOa2$B52kzP5BpBE`}2{_rGMJSP)Ns*msQ>V-I83H z^321A+c!n3W?>~7htIau>TE9FU(FRE_#D8wdlpg-Kcv>#ZG*_PlF@{Xw3;mSi>8I~ z_4?(RMtwT&EOo2QU+B=&?|Yg5I2BbNuG#KGYaE>6rlBxm+;tJHy%)32LeoBkCjC4Q zDGfs!_}|{RW-HU$7(mR-L%C*v+m%#j&dp3wb$x5r4NMX_ z*iRx&^MLety0qD-1u|Birx_(D9XGACc2&Q`LuD`i^ssnBy-i5fZH2qngJ-KC$F|<^ zkrL=p-eM0TVw*KFvK`$T0N7UI8B?V25L)0Fh@^SF8Yhs<^~ zrZ`3>n=h&zVi-}r$Pn8ir?An*q)i#D&DIL<+tI-2W!9-}*l56Q*@vyumFbHbJKnX4 zp6^b@{4K}?cG`gBhGDNxtum$ZU9+O~z`6t-^8&8ZtehbN8w)m%-mz7$O_S|HSxAbL zN&-hKex_~a(u)_b7T}H0dqvEjQ=gqc!cNZKh>9U1<4NZ%EmgD6HUui|@Ww(Id3xf; zb=!ngH^G*Z4sXviADp;t#oRCEa_y1eRyfDaFQ!YG+(ct>WVr|MEEG!ZIErUTIJW!a#E^R zWQW%Vo+~fr6G^OdsL zoa&c6Hq&_)3C-#JIa&QrtA??*L^esS`n!AO_N+TO&v96u3nx`yesl`1J{-6VOawbO zGF&)I#{o*WEo159!rF(Kb1b;4y|PzY2fRQoWyqc}M3dt}d)Q4=;+F6feN}S}!1!`c zHC+RP_4ug`AZdlChR%oi_BmdeLv>7?{8I3mj`eE&WUQQRzO<6I0pB9&pcyzx&SRe` z(v61YV|Dv4;2n7f03w}p7-LoidP!d%#aq@qkU+%i2Wey4V6H4RnXY&-tz7Y(A^rn+ z0r-ULbq;!`&;KC!h=Ct1l+s}Q9pUR5$d$8%*FQ#?d^z|M=!?-AOk};PW{SclyAkYd z54H$YW$UQcX79!>&#yAxrIiQLWt~|71=nWmtDYx%u3v&}SSNat18y=`RuBd=%U_-O zb6yAK24pM1=~%Oabxms)=kW>>A-D3A(HKN&1|ya(5TCqv4clR4fC%&_m^HcXufXU@c33%Jsi%}AZn zqthgtK~yEN4vtU0no9Pq+`Th36NcutgAf73ot}O!#4&>ELhvqQ>W#tCUHSRtN#YXV zYvP$E)_9m8hv`hvD?lSG7%Z^<@VrzF2lO^1s{*-fsa!UAn&(i~TmSVXbSzTCLkEP4 zq%nJfdLT9d3`~DAMJ!sOZ>7lYdb!tm2E6gw?(>}#d8I}O_m;JR5UgK?ewtbFL zNBxN?=9aA8WcC4xNLjfp`e*$}UEMcdF*OyE@VKJoWBb7K^MHV`#)DB-v?v;SRmqDN<^Iq*E%w4I2^E=YP~PwM0uviPFzTrrzh*=ga)~F10I{+7)Rl zkaaouRr%m=9u#ToNbJWq6Rr1Y+-mTWu)YFQb!>7Hj9vW(BFPj%%$lBpt^2rcdg&N_ z+_~Dy2`B5DZ)M+YLvdi*EJ5a6MP}$J56JF9ibFp2Q(fWhp{ym zp6RUJDxY&2yhx?Ve|yz1qYI(ozbglI*cygSla()$G0GxaHLM*=&OtD&*%IpLNFueUsn6Z z-m&NJwvXlnzoKe_3y1}aQg(_49*UHo<99e2;3_~{RQsfhG%FUNkE9s|eg8PtPCffe z?$2ti3hSAY$_SUz6x$}v1SkN>u5vu+UE zB^$xJ_WbO$hu@39=BjIYB%QF0#XF2?ZTmXXgy=tmsA+v>XHGIrn>&*D0Ym*`WA(EXn zYqzxKt~yQ0WbRi-ey2x85Fh14w2{r5Rjc*0(9CvTkUMTY!Q@!y!2zWJPxyCXh(bpl zv5LJa$#_(#s{c508nno#H2{SCc9qtyAZr0_&@hU7*@h_QO4A5DgOs~5?^D<0FO0hP za~BNh@l)^;}EiU>nb0$0|{V3t_C;_xn7!Mf|-c*M~SkgyFIh#5PXKp4ku!(_gO_u z#ZzVVMaI~WE9FnMe2NPcj`ZdpcG~IZx2MLY#t@Phce>SZOqjuXKv9q=A5V5WkwGv~ zyZr*+rienD`J_Kr-x;jGBV*h9Fi2wFKOvzm>UevGD=!itWGleO=ns32e-;kuO2yQz z@*}o+wyQ+!ll1T|$7nx!8a8W-M7z%OVrFNVcw=(y>bRQRlhf{7era0^Kd2?nL`0?1 zUSkRV%)Ea;(HV#xHV!q}dP(wZs|m;e697%^7ha(7ZUk{u1K~`15^L2)FH|48y*ZRU zwnu?`NtztLORT%E)n>wSXQe8aNW?X^c03ieyV$XE?qxVX{h3V4NJO60B_ou@;(1R< zY8Q|ne~=%Z2``#tFRzOpP8sF}oVC>GZw#tOc_p;wE)-I_Z;+u6vo~L-1%}XmaWLIr zS2W;yrIu9#snNr-kwwdp_OYy_7BL;s3OgrD9t)$qpa)RPa|-Bf$vqjAE%Vi$wMN`4pKg2 zHa+|JekuN8Y|G3Sxo`Y;q|)wYVOSfG8T*$W#Qa!&fB$^h;*Yf^6`^B%P88~2%0LVm zvK)Dz7Aw}fpyl;llh>Yi?^5Llk0lMt9WS4GDdjBMxB9Ble}WTD86h;|ufP%%%Y&W` zahJs&qG%4mHq?ZqI5hO;_*yjGeZMXqmOf|JoDFPUA>IUR!4c?;Vy%!bS1~)7n+J|u z|4nyYcE3h6GYecd)%*}q?RMthxX;@sQ*1uErFCX*@bDEtur z;-mtEn+voIMgZvdslStC|0d(!-Is_Lw(kzDq3-&zyCM}!qXw7aaDC<#3vd?!_`L`- zeTM)jmjkR+`xy`-VxtDcmwe|5DkuccIY+i?1ccQt`dpmTkV7UvAnR8cZXy9yw&cJ9KIg5IX4*S$YH9xs&+!ot z+@$=BRkC1z7M_`-$l)t3K;pZC)o#%jmGaG>#1h{!TFuI;@mw}zD8SkZanra8i*c@Av%c6fi%Vz9--k9v1FMr~Aev+xVf zBFbrTIUJ)z;313>4?7@Y0EKT##`iBLC43L0bBHKNS*g*+{Z^s$Ws06V$_)MGaM$7A zqry^JKKaH8%VZ!uWNSK+x{c!s1)$oJctZ5oE_8hm+{q@K5_Y1Qf1sg=BP%%Z1bv<$B^i&TbUE{pFvndYk9i&xXCz&FIi&z1a! zND6rI^n}5B6y(>mWf;@p*}bJNrQD;{O=3{LRf@z_!=k|CoQ)!kdVIT!&PFk)Ym-=Z zj!wK)Frb>-Qm7n5TW7U*eCE2NQS3yLSWw(<*4ueCmrFVGKv(l2cr~}R3?m9Mha@Q^ zUGsEmZ}+p)G8kNp5mi!#u`iDq0ias#T?Zf)FCzVg2$o_@CUc7#jOnZht@ghDA2agA zsY;^6t$U7)UQ-0a4CJjQdM(gEqU+sstPlI*yZXY7W4Ok_0m%&1FE+wo+x~bW>3&<( zc=qb+?tf9$E$(#=LUDd4MyEO~%K`Sw zE!lL?YrRu&yopEv0qg+{nnMiD>DTU!HxyYL@`v(58^Y^yx(wlMMj}4N%MNG8@Rv3? z22=;j1kN`J>oE*KhE-WaJsac0hW3_O$cFtdgPy@*&%0%>!TU=htTR1nz^$R~2VUsZ z^uBNPG@dQ!zNOBg`#%cdAEqGDkXTrL_LfJ7JLR2*>p!54_PG_$=M$HA*BL&6iY4WO zzUti}TPi-J+%Vkp z<&#`vzV1rCtiX-)^6UDzu2b7HyHdZwvYFn+lWymnwe}}(gW!gSnjN|`2k}likvjpA zGygCgys7oB)?G8nZ(*SE@F$sUL=+(n^G{zAW&FsboKriXouRd9Ybib?#~i!Pn*k}1 zh;R^eD9Z(=WXlqK<>I&gV0G6trAVpX_6pfk-&iJgbqwuRI{9!4b462Pqd0nd+cuhK zmbKM%xAKgjwmu%TR5nE{CHvUd|6C7(flNZbN9pU)_DfcdPmCyhbs zxM2tdg`+9uPgXSuPgHt;&W?jl|1pntOXHiev~RDR1f8ZG2LYOxEjOyrwBx~nfM{k< zX#4h70Ot0Ht5{tXT9klWUzg3B-D$4h_<9#lu40#JZf~9cg}VlNsp6;JWe1jB2R?WT zvl_Ve&E%oIB%dI{_p4hf9CBdSRLec6cw6^idER^s&MIb;`4xq*R zeLY5m*|_Fubb;H4$4BA3bBb1{9tnd@7UdMXhVw}+Si7|a!(^KyZw|_##WZUL$8%#?^1((uY6snpJ=1vWJX$$Oc6I%xDt*_Yv9xHaNR?1=1+7zKfv4PIcr-PP)V_K zNM<^&Yh{L64W|{f-g^7GAnQ=QN48)eQ65`-<`J=8xa;ei+ugqHfOa6DZ1#i&-!Z_L zw{J1lwBrVk12sO^wfOL4aI|&Peteh!7gPwpzkWts<*~VT7qAmYym3ZegMG<~;!EM} za{Fh~B^)yo*F58A$I5tBSp@jaW``lQ)vJ0;rfbSduXO0_+T+&zMZ zZ0hf5@u|?^IGIlS&?M>%F(}Ss+mzp_ja;t~mr@nF;S8s7<&x+Eh)G07UgEz@U>v7Cc!VtqqEfuE@ z$0X~Wu!D;W6wNCRtPf~{eu!%goc305<^GP;K;>Ti?noPtRoyEm$M)`h_$KUy=AnnTZSvfbm>h*j2qJKJ|D3ECmmT>0b4uqj+8 z_M3K*$J|jbC)n!WK;zf5#*nsI{;iTV%2}Q|iTDAZHXAiEVxQ(LfENr%BNn>xLyL>`h9iNp}A{eir0lb&U>_tElYwHKXNjsg1bcVhK*W@8;VRs5!8Qh)%^_EFIGmMsap*`Ug; zv>62Nth#+}g4=bB-~Jfi3_s+?uiLgVNDcXz9|2>72dHjc8UY5|tt zgV5G~K`-0Dj{q*xxt-`&AhYUDG1Xj|__%fLEtiqAaZ^!)AsmPQ!`53zMfH7Q;|fTK zf(p{1G}0i=fJjOs-7$2B#4wa1B_)D{#3)F2cf$}guIl#aSFvQE}`@X;berw%x z&s}Tpea^Gby6ddF_TBqDGqmSeV89ZVvnBsj2YkKv0}Wnv=p`U;2&;S#ORY#VDCrB! zAUc{r+uEuTRFrSr9;ThMx7{8(EVtz7X_`LOsuQ2ssxw&4n~TAIs_Y(L%~P_N2{;gB z@W0W^ur@0YjWTG6S%DWLmB!aPZ4H)el(G zvzZ}j-AUTEsP&dNiqAV}?$b<{GKk!7W8Sr?^sg za|2+GF0wVlHt$qESOM#7x4*e;7RIMBHnB&kZ>Ns;Px@`+)B!t*Bi0G z%`mR;GuZ9z{N)_4$LfbRBYjY$Ll`N(N&$W`_bu}_jn&WxQ;_)^|&e?GY1Pz9+n{Ok6tnK zT>NVP0OZ`0RPzYKVp(A!kZw8B47-F+po_Zi{Yu z_h)tvxyECQHG&`ufb)oxfAjW_#|oRB3=|iHUe;+kNhy+D9L98gMVHhB8{F=f-+FRd z?)B8hf|J;EZ1oTl^?Sl#fwf}e{W>Kg{RPWO$QmX2ZCg%Ec}0goqjjz2Qri%JL3yPbWy0Z7_kOzjbtlHY)uD`* z*V=)%sF&w;(JMcDcyr9Tu-Q2N)#>?iLEJgc>+L}w+eK|>S?xEO1kEaf@o&mXmr7!&)o*WGvPoBM2L98A5HfOFoC710Ra@Q9A<$uD~O;a@1aJ#;SYr?1xd=IM0k-t9Yf zoV8te@L5QYd+&vuFKpoIV~XP>*D6t3y-JiI|1Wp zryKek@?yyAGwoWY8O?Jk0dKhvJ3O3~jm&3DIbh$m-}_L?zt|?l7<^*0Cu2TkJ7;1? z!WJPvrqi)jvlX0Wrm+&Mti#Uuh@D6(VkVQ~s9O@ud`t%OU@OR((`w-7Uk^sg!x>~v zDUv~TuHQ!eYaW|ESBI$A%1Qrz+)DmNxP|pqOmjkLtufxwu07QQ#s-ShFdA>V?(x0g zpj^L|{hCMNC%>c1OOOcwAUBvr`zqJ;B}UbJ@a7EBU{H+;x+Ht z{QbvfBf$n2D_a1h9x|VTE10$kICl;OtPvZMZde$1bebw@{Jve|xfY7;{*lE@X*WQ} zMs&CuB$*qt&kE4omN3q)c?CLxaK%8+Pzv?}uDZc8$lkhd*o!LCnkv$yDw&WDT_6(g z6N8HkpPsKq#|5(E;|lDtZ+?%Dy&%nUXJ#_0pY+t;>mfptO2ciwzmGowmzt2w-KEv3 z*=x8klh5R#Uw8fAz00yBd(g?5J*Nl9ns3ggQMo2wiNweNbPnlA92!(1s z^cH`Q^yJE-wQ)OBuXv5DaFkY>6kypOq57RA(AW=EAI1ePlk*zL<%|2p|NAkN!W=f9 ziJ%;Shs*&V_E;_ku0D;W-0#blERI`GfvPv8Rvhy4%2ynI`BxXTppuQvoN9IV6Et$3 zPW$T|#~_zI3vpF-wgMH#qO9G zg{s2R#rmEExD6Bj)}&&@@ePQl{$aU2ew8_oGk~I$9J|ZOjC^aiK`yib5|9%#3B4!f zyXF}7z!j1VgjhyMMN!`_r@ek%`haBl<3phhs$oK0Asa?JUonoJCzlD9Y`O?C3V|>Z zYkcZ7&h@LOcA0Hy(b=>@?@}HMJ$LZ1o_A1Mc#ChBd6Pzj20}sR!}94*pAnG>eFUg_`edH8@-3j$tFtzgZ|AN}1$LH_H)d?sRR&f$h( z|Ku~cRWXx@3If&gowv+`apWs|w|7>*{P8NMnJ#0i%QRG7i$lq-sm6qN__R=KwNNd! z_(qhgcLR=pU^iLO=cb7z7zS%0R(?CD2XCB_<6^q}E=UP=#yn zMe5$Jp8VV=fu59Ml}7eCL)PL_B|%_paqy565tzPUW+ppakY?+p;-* zK{9H52A4!fuz|-!|Q?gk#UBS_2=c ziqp27%&gVp$Gp19H8@}UjNyZ2y;*IGh+k=Ky=gaYrkMFx;)$w;P3}7whPNvY)b0BD zow;a_>@jxiB|uB~JY54zu4e-n?1MiEyW7q2f%*Mb`N!Hmfs_Sg*7h z4s#i`*>W1z33|a*W`*vvz7snj5J%&ZVLt*P57L=oAgcSPjuVi!quQL|B{ey$k5>-G zzb>=<-qQY=Ui{;&&IH+4!(Q4Pe&4o+9Odk2enCew`F<{k&JZg~Z4E{&GEe-sE{A$R z#Z)KFM+^ZXB!btjVFGmtINuwa^}t$ghY3!6Aas@|W2%{s59$=N+juyyf-tC4ops(G zTS~LPYH9JjD{cOrafL^#cU}lcJk*YJN1XT|w@T6YP~@a-TUT$~RI>^Q{?DDR zX5sf^W=I*&v7{>kj|WeYM9PRfl!rb?a`_5cE*>G!V;QJC{o>)z0fuq$dB}vpb@oPG zy=(=t{p7oqusPHp&-=(7it9oXj#~d(_Nj?1cX-S_Ik#2n4G$$q{KH_^kAWfDtUS7W z@9yB+d7vrM@$W1>^|lC@H`gn zq=$)vv84hUB%&~jyLKTp0Pl)l2&>!=UkH182|Mkc{G_jdN?4{vct7!y?Vci4w!;Pk zEUf9;EV!_kBd!^g(xs6^T%c((AVGlrxA3z+BnxKDId}*~kZ0Vh=n5zYU-|Ra3+x6> z*Uq}v6f!XGyKkBQu<`SHU4I;WNdfNimn0kyzw?KR%b(oVb$^(9EbR8A?K1B3e95`{ zZ@(&C6mG0v(KPc@m2D-7TSf6Vv>~~zVlsHil2+#CnT*!FsZq7>iQbbgT%Md=cFkO` zEuokt+=AtIuMIy*i`HgE2}wSG`rM?Ax)Q!2ow0o8^!w?IND65hel}4K|4#JE{$}Qd zQvsl3bdz{X=q=Xna@{bP5Vw!?HHpaeyHLhWsjlZZZ)N&PJ$AbeV)_AkVUMzG zJR!66uV0W_NOr%*a}J0yADiV@%2{43DP6etmxmaAJc^|IhIa2Qh>WHyrRmd~!XK1iiZ@biB#S`y$ZkIn1!xrQu+VymzokleS5p+PRV7bCBA)gn3eOAK z7@3*Z4zq#$BvB1Y$OAfFFrZEgYXgNS`zxn0X(NyJ!GZPS&sn{h1b5^;rZWkBx4)v+ zGC3H%&&JazxAEXNZQ|^WS!82x*}v*~zwe`=^6pMASbXyQD`u34J&Wv3{f1ZvuvG=- zo&cZV;5(P3*~$xsxwsj3AiOW=t&CZMmHup?!-kPmw$g+woxlA%d3BMm)7lHCrR7;s zkJzzPqoe+ezYO|3m9`LWu*-2V0;kNd4Y4F(kh-KaEN+$$BMw!%N>&NNVU^Bfsdse< ziihueZ$^`BT8iM`-!tj=!P_mtIGMYFWn+Ffc!E=x8D6@@s34sk`^732^AS42@NiSI>;GzV?pE+&{dujRCI%3ta@%mzoEw+!cCj# zK$}SJD*u=9O=;biuU&Fgj^S-EYdYs6vd2+!g4dL*V9w;|(I;2bc9|Q6X<^B@c5Nnp zr$1IS>`G-4b|(*(fS`BQ19$Qaou-3~-v}CC5s^O2Mm@l1SmWRLjp;NbWLyrDg4!or z>mg;``&?*kt*OSA@vxTr_VWfJaP^&HncbSD#n|)hBTSrV|>3>%W zECHh}-MvGDwC@sqasd%r?Ua(CXwUQbapKGJ5oz((q-G(luOaqB(T0S46e~^`A9$`n zwj(flbv?m?W^o%*#b!u=Fexf0pdHeLwNIQ(H6kJ^E>|ETUyU*6!cr{}|D1D1gf)WI zznhW$64#NQI6kMt{vos_F2YEyiHbRsVGVZ%AKcpP-Nes9-qVZ*wXLuw>Wch^cm1;r zGRV>CzdtGbX}$6l-85LRaUE3(p;sfp@Tpwwyt|vk_AcCnXCTM7rN_4=lLOgfk>wXX zH(~Y~r?-FpY2A(g^sa2T)Uhapsl5$M4`KH}(=P_HS0hEnR9Fxfa{!PZl3V#)WJViq&-iu=7 zIE8`h$&Y&FRSHf=E|tY^DvMs9Of){2e0JiRciqqNW|PrvUg2yP+y5l2>9hE(K%6nG6oc?kHU_i~g7l#D$JAtys7(;0U<^yw zjtwjmXqG}|?_Tr0+;)^C$3?0yv(ah>)1NB=@@MmDMLd4ab{`cy@Tk{~g~{5gX19WU z!X%j~Yqo8=gX!ax+DfE#=JBldi_dSSoax>is^IZ6?MSH{UwWAI->|4Iy&zb8?_a{HN)2Q6PX_HSf!#gvL?$G-2w$afvWhEXQV8kUZqr`DFv`GfuIyABrEX zWa-QyzMkA9W29=AM{Uu0VxQdqUaww+VJHq;8swbGeIH{|+A~%iuzzmxutF#7pXvXe zMQGBBt=JzgrTuemOn70T(~~giY`LO>W?4kOxMQAwcSTdlE_idQF_UE4b1rP-t)6Ug zPY7J-+D&_&x;>Ljpdr zVS{|&759~HDW$wpKXqzEa`_DSS?Y+q-Jx!W+4^(#w`Ov?sig-_-O%BESlz0>7X5^1 z((Of`yE{He5;y;p$vkei7&_GsF;HH_pp@Z|DX}>W0s8%S3o^F3e(%hm>n?XB>F}s$boD`G?okmNbg!wnty1L2fRwqN_owJdXRUgRS;c@`;r{Jk939Ys@(Gk? znYt09O+cI$BCq24VnaE9wpkC#Ss8o){?v874-E)XuP8b9!7R=hH)zb=S;ib)E*RZh z#b&{0#%Aq(jBk{DCT1j>Cdwef%|k+iqa`2P6J3jL{;bpl2>)hO-H zcnA1a8N&6(Xs$3mg&@#Poi-r%{78nPc|<7Sw&}zNRR4QsYsVX)vHDA-9A1`w7ZT^p zHtJZ5T4~vA5tKP;cDk((`_{4lThKxd*8^HUhb+H=-ucXfdaj@Lr`19%I=bah$cl7L zE9s(u_JFg4BQC5LT)lnh6ftUk&W^=!h++xtENGDqs|5b-kaer95CHaxoNqo%4v>3# zvMZ8ezXEL$vWrg$X**7*S^oieTp{XZP)lhK5gvru{kJG0IH3=r?fMQoBZ?4Bq6|a3 zgUqCE4i5I|v6F3)(%szRVMf)B=!Kh=OKLz%IV9+j%XmoXehi9N z=gv;c!?(U%$7ki2aCwRIukGfnC;v7T>SXqZT0(qezS+|27i(8g!qod1X9i+M%w?$x z8?t7wT=9!smKcm>Pob%8;@}4w?c{@}D;Bu_PEup|kae273~(XwzMs%a#1@Du`WxTl zBvX1z+UZD(AJ_T6`Cifj_xcB6jt#)g?ML)i3RpFXsfNWdjyi~E(MIgqE$cK29X!#L z`ULR^Y*M5t1K~2u+7xswJTEf8%n{$rHO|oC2JcC)Q(x!oVy9}}~c}+IMp*d@7NbTt3+0d?xt!jZd9vKAX&jert{VG(fnk9_sYczi*g!x(0 zwXS#`Gpt!6y97?->6wwoVt<_p-@g6E2j082S&&}dDc&xEZ6uUn!o{3E#Hw8nfPS!B z5`@Iz-2RQ0xt727A-+)cYUc@ias44iCZ=Pm$0B)+PsOVU=e8S^wy7zE*rGXO5N(gb zI58gHa!3{4u>1VOG1%87nt2I z`pR@WNs+08*DVgd$!2eb4w%x!c-xBfZm_+<5PDmomsKzf7!LrTt3SwVmXC)c?bOM1IcZq(w%8DGKYHXU!{0g@H%YV=}cZW@XVcf!O!^MEEU?nyY@=ppr}XDguj= zF(LnhotD;x_{LvK0l}qX6qM8<$%j1|p0%C1k^;5D#xqwZX%`FKV*Uist|bNn7Bq(AP%u4NVWY!dnr}gXpDrs4JKWaKtLI3!$x*O{?5g*TJEcyeQXPB7 zaGxSr4>G~`IE>NJV9e+x0TIR5VDw#}?8}s7_cM!hi(1j{hG1ED^QVo@pj@b#+bc@s{^K8*z1swZC97Az3|*1vBQ~l|LKkY z`NkC+h6z1f14t>ZPTc!O7x@I@@|N1Pxzo%`v$d>RT(`6=fUVeKhVm2grrv@@py{6f zknG{rm$y4@8?_uGvZno<;mFTuc{!N<>J(U?D7R?t-;)~C9)}}hrthOYCF13`tO=TH zdw(eo3U5vmZbrB17%%+f4r4lmPjC2Y=x}g8yv$tywTuT<{~B{@Pnrr;#+pvI)YFbA zada~cpDjtZB#|GCMqRyrae+M?<*1Pi4UH4T=*Jfb}!#tp-M-I5*(V($xL!Zbx?VzoBB2jCe?``)toW2~9pjEO1N(h$|O zOH&c#nFEBlTAFg-TO0t1(UPXrK5GgM7c)T8(p5^He46JUBRPk-c-vh{`m_#DK3@YXCv`@LgLgJ6Bw{c*E@!!lW8ws<-<5oL9Hr0D`Pi zZGpLA<~5xY02@*Zz?})Z1i*uVhV;9<0KP_ht6YD!8i>_7kul%U>p!Q%`+iToZv$J# zU5zYa&g(KWE5aQthy?<9UY$Eg--#mkDS<;c6ovEE*Vi5)-XdGMh{5VWz}|tEefzNM zirT)c$$dIYnV*w!f@L|$)t1y$K&QZ{wlSZFR~ZbVzJKCXMk)3`jgQ8p{FEGJlpa5v z+oB%99NONsrFKjNY=UYTIA;R7minClCFdHd`>!n}%g&i>8~|Riv&@gmC;>6EF=z*X zbzSyM0DHkX(+z{RO{)_5@TFB5EXH^YL{heMFcGl)KWoi>al`uW64SHe0UKgv?Dum^ zWy})aThoqN*R47_0@xGmJ!Ab--oa|lWH{KL)M&M))$dy?rNb)m zlhvUOqffWPH?0K-qf;?*ACXPJe}JEIy1WfuQTLnHwo8>U@~qbUH=OZtEGF_x)BOP( z@Pc!j;&Ty@{-^T$4+SwFbNJg7)}j3jtf(t@%(;7ZT8Pkw><0WvtRV$^wC#tTkfM;O z4?v?>Q=WmAa?R<057J(LeauswCFejI4nEm4Aoe^|H$|$-&O@Co2|mmC)v2NFJBF+s zHC(x!=*`x`f<3994Hmsk&>^qh0#EMv8Gn65)-Ncr9-XQ~ZMEe&;CllTvibe^g4M^n_`9lO{nb70R4PGgc+Q{l8)46$OcL78C=Qq~Tw|3GieYn2cSt^dhWph-MGHfq(=$%cTW>5Rd zwj(TgVl|4Lj9Nkc>NdX~PnVlt%$Qx30)Tb4+7t>EzFWBua${P8GJwYN7eO~ZrPYXQ!f^BJ=-b(rPE+NgF zw-Ky6(zW320qx~E9xq10QL|3Mt!2vUelN(@{mM%J#843R%;7XX7Ch2Hh45h%WJiOT z1^{tU%4f*b%FSN@$Hp`S+O{v&S9E|54G0Ql{3w|pU$&E2O zl9WA~x^(|w=>hk&CsEKI4FZqS1<+s;GqL1o(PevtF*hcQ3iG;~>_5+J$Pm`9n$F!t6qYTPpQl6zD8M#4^PJ#)Ryi<+h`#+&34N2aWSlA2ugWFD!Tj<0+B zr(V!|A8GwPt?ebvlsuDP5>j&+V;O~30ut*0WrrZIdUm4Z!w<23(K+JMnY7Q?mnjRH z9&Ty4b;3@}Q&M$Owzgtj$|+*nbb8IdlB1cJ4OEl2oIr%&>L|dq+I$bVlAQ<5jn*Iq zYkz5r8w(%q>6s^{7O0BMCIaW#lRgKdzxSo@@;b5VahXTwV)%L2(+|rUyBDSqC3UI16&kU}l zG&(Rk$f85z96Af2HhzeU#{xd~nxCo7a{)r4<}dD{CiR*pTaKO8(fQnJJp{MxkOH29 zM;Q)0V*vNE9`nK=9;>c7CK8|~c@?D;8Tt!gzDC^i-iK#ksjlo@XIWiXiquy?vbDPf zNh%ClS8AOC>rc+UQ}`aoRpV*P{?dS=J}P%(kgj@wIDuN6&Hh!o^-m#>B$&ch@FmI7 z5*Yt^l_yUMMk4`}lad_Tn8H1usgxyKyWUnU6vZ$E_MjE8ZIsgFO-w;??_`nhJY4>| zA@$t#bTcBBu?KWdCzctha=IyFJ=+5RG< zWLudq+#yg3N+S;Sz7O=L3p84lxkHr+gM_10#$IoTWcPWka(Xc+enVAO6^tfGMmqF> zY~4vKJDE!HTT<2@=4afQl!xn5v_tpv;)(Mqi}CS` zB`|JFxp`!xTrzhK)}`FU$GlcQc$%O7;&$Uaw#{U}H?;CFKjzLf2%vc0;K_ZDC=vC{ zpi)kej#%c1o9VXHlbdKK9ObdQ*<>Y>X%95K_nU5qRe&3RXFVBJO;sL?+FQzu3YEVAP?Pw$* z8%*Z$O7Cc7hCimP*L#DuF>vjA`#?0UZ^5XVn%5^=eZb!_Tisd47<jzXHS(j^@+*+F&C4O#oNo=mZJRD;fgwxNfO7ZmyQt$dZcIne1*;?v#Cp) zu?`X7VLKHgv+7Nc0@kK!d9tOKZ)i?g=Yc-<-Zs7{=_{qc4mk>tpUB6g?|hH?_nQKj zPF{gWk)f=wpMi%$!0Nv-3Ud3zw2fnd)(%xcAgw(+hGZTd3V=e40=Sl{%6QnRN@v2_ zG|LudqHXCQ5S&SY$fxkm{@a%cFpf3hv8$VRbP)If`|^yLVpExiO~jbn{}%<tWx#?@q{t=a&F)E8EgHRtREE2@srkgk`WY3erSyq zDX@}rmDrs1X(h$d=p&YeN^;=5^|19pGC#$xDNABvjQjxrSm3tJw9rizECoGgi2V>F z5L1=Zou+}1~1dWeE&O@md!vqSK{xkl{Pr*tR^Cb3AQs~~4a-loTUkcjG z5c`M%NC9LIuj21Abg*=RFNpcvzlA)pCoo_vvMUWJU?| zkkSmmb%xm2|IgDT%V7cj6ex(0JUskbJY0-aH>#CGGIMW zu57K=oY-y_bAh*~{;$MIGqs8havhab5HBb684_67VY$FBFSAn>O^lWS0bH)jZE-C! zagA7h84I?zqp4jIM+^fLT2EFf{Ssy_1=-BAPu++WKJX@#mR;WnxOju+F))qon<}lX zQ^Gh?2C;#y=k++zmE<-^EU@wW5VJJfED%et{+u~);Iv+(iecVKuw+0(DJfiHmietU z;CT7ZXYz;tSfVkGf|2Vy>QG3|fUa~xYnfV-RmND4Q#IM7O@E?Fk~oj!CaQD7G^>E? zr$+bIuP5$Xs8^aZHeY$;>IKy!;EMW5M(Vyazn(a-ixWc=p+@{^-$2hS7ao6jb~tDA z_xC_ffumq2%4=#?F=-)_K|d)gg3Y@-MOPf~!1?o^fp@wi54m3`SsjP6Ar#boBJd4uVH(@<~?A6$FajK5QT7yC24(ovPoPCma|3;@17e?e3gA@O{SSe;|5z*u@+A zx}Z%wm(oV^y{p%{V&V;~v;Nf0Y7Bn{tTC(v$5o(BlFDEYnt+u$(!;HQTvH!D%B2+@p$$yIfIC{=o`1nUV_Kyafo zu^db&2kL`f{3S!ul0FTEm}se4IV$7W;jnj7|6153jkyDUQN;Y4bl{q@?sXFQpUR_n z<=Qkt5#w0K)v$7Y^J#0%{{4r>!<M~EllUCg83eI&hjxloPZ_N~O~d>4rNe1St8b(wDGh`Y_*u)^Qiwf_zoOi$p{;V@nTsvU zbx=>wT)|l=p|b2m|J{fy$f}!0e)Zv<94o)p+Vw5SQoL${4(upgEvU=T4(#OY`>lnD zDEvG+KQ&=50q^PU$t_qNIlTb82&R;pcTEMDkG2W~PMDY3>z0XIzG-iE()qiM2uBl) z{Ci?%i_V)yvu2rD2^X-c2L>B>Xd4r(7U8CK@wa46?%#6>Mhyk;=3mZr?-?)=6`l*k(?h6D~Iv{4M z!~d$A$Gsh7gCORJVw#2nnq7;jLYlIr{bEM~vlWt!s-4-}LUiGM5Y}_L>v+FUI32?atmM2R3Tgk?(UNN)04gBl&X6kdAnkfxqc+9bEiLs3# z8{ZriC{Nv(G>+titlaXXH%;Z+1dmORItx~!;h((Cji__`Y1`)}6}I01dm|erijgH$ z^TBVpoI4c)>e;5(3EuZpFcD704C)qRjGK>(0#D-3yv@=#KG-*k!?+1qoQVEz6dj+v zM=|0v;AK3QroEbi_)@-cv#2vl_tz0lCCG{%WR1*HZqpfIW&O+aFp11PElaMECGG1% z`+NFDdf(RCihE+>wAyZYRsDavR+Ri0%zh1T1h`C}QWaoOElz|AnJ{O&Sjk2#UGyIm zd?r={OO~Iv%7n@Vb>IpuCcGH7Z5$AL-A=PSSygg!%;5Ja3u$X#q2F2>2M$g;EG63W zvp;qF{3nDO4Mq%Ye|b4ac3}>OZ5%xbPAFMIR~a+wuFydIYou+*a^w75?J-YF&j#b^ zdfn4@a4_olb!ko`dy}~sF*p2NqU$-_WYIQS+aJ?Z^N&*7_P+a;+*$)IByc484XQ%# zy4uy69s#!uC7qvWJ9fndLiSIPrNP%P>UwG-i%I8~Ol$X+YPQ52!aHx=_I@7fwT(BB*Z7Am;4qxvCvZYkk~BS^ zQ#zHalGU&sIlVgi#|Vf6#7ZV^tdb0)Gb^5Cmo*c)IqbBR*DQiM+~H%LSVKs8SG5Hm_{r~&H1(d7i=yEAc-m;|I?qg|iIws~361-5 zrwNDr7t!<$^?ZL-={dQ~6P|PeBKYHT64GNHjZ2Dxz!I5t_^r(ZHAlHZXUZ=Gb2)k; zHOqZ2)ahEY4D%R7kf&y5G{K93)aUSgjX3GqFsX$Fj^IUuy&_OLnv|S z`96u=T%#7jY8ftax+>hL644M+;}X&`DlWKd5=2|m7;5AUzs)-^>9i|6FsaOu3&*L*7wcnBtM5XY?J#rO|jFgFA>Tyk`|d>(q-h|S$T7d+6W zW6fOZvK8^PBkj;^Lf-_#KgLTo#Yh@;n%R*d1T&~8U95%J*w+y@06~}NO^`12YV_Pm zF|8?$NCni+RUu(DH+?x4A7J^hGGt+xc7?w|q!F)ja<%fYvnRt;jue20oBjc(;^=#L$xDfI$y7S!e=ms^d$GHb$-4;67A$S@$h-)+q=HGCb%BfPgm;Q zws+Q`3IIym!EJZ0Q!A?q`_U{6h?t#2rJ~LsED%2V-qTdUo<8+r3dF)(z}m#3bP=FS zm(C?*p;>yV<|G{>PfYZc^di8zPicNUo9d5Td$!mTWZ;aMR@w9@G7fWP1>BFUo4?ks zimvQtyEf|F2HsS9c9GJ`EZ(<1(vr%5?p6X*-v=qU&ikOGm)5}jn7a0P#!*VzuU9KZ z(Z;fASJsGv3u{CUpGa`&eY@|wax6Nniq94slPScPq;a`uIl_0e+rZM zJbpWWF>pIChJisfPyg4PxUU{@?**v~P#4aJ(?eXYD>X&xrH%IQE(LC6q)zTUeq7lg z3NCGcQ|z=dtM_eyy#x`Z#_d+i2~#jlxv~ZBr`9!IKlkLs`LXumi8MSVWj9k04aBV$5aqj=76MnfPc-mE8p(h?vQq1l1!`ygqtyzNlU?zmQ0O0rboquA%!>htV_<@U@b7m+4gmyIpYy1lj^1FF7~ z=>iD?v?k83D~#~jIODzf=gZx)(^u3VrhCc)-NslInAQYch%}f#u1$OoCrXI08qHm} zPOb5RyRrOegN-V@kRfMp0%>zZciYH62Sr(UZbvRoht&ie`vPp|SJxIqPfA^ZMHf_` zU1Muq8D20rE?v|oRmgbJ?s!1d5QvZr_a2|dz6O5wTiQU{Nhg19c*M-H&4mcwfm3_j z`>!^i-34+`S}MBjqPU3OG+jjMWeE7_@L-E4WBARJopx5;>bW0%l&>kmZgy2abdRi# zJP%%P&7P)YRoP#t%h1WZV$%@y6`H-ZG$ecsmY_BlSgZS(I*3VzvjZ$HmmxA+2_{oA5h8Dy4k`zc1)~kW1xdOyM?`mr8|44eBS~A z-tRwX-&66DYpAkv(T$Wc`CIpS^~#LJsij{A-BsHCaX9^+-qO-^7Y-#DZS5_$G5VSQAaf!5`; zien3Cbvb`}5&}t(qu(cI(%uA;1aj|mYgfq-5+opiZl|7=HKeuc6PBYvhU%5%p9xhj z=Qm{qV{34AiaD-szMn6XbX>@%>8j|2RjY-5(C{-tUWYRPd#pVy>6ANW2s{`;S% z5E}=Z_OisLnSOody9YGXkrMibS?|9+zoj0UO)J)^HDOuM5hwS4$QC8VrYOb(r&XFT zVQI{I>$A$lIYS(vsMdZEn|}4yW5(2N%R>9Y8h9x)mLzg?+%cLITA(GX%JgyxPimo~ zd6#SSvw7uZnuOq5**m<^=T(sgHyOe01zt~PH%2RW;>a1X_oXTQf!(={um zf9-}hyG&d4fA6C($I94@z0vm&K{p{}m9(__VUs=S>m|ubaCL~lt@r!PV@BVz7D3T6 zuAgBa53NG+SLxwT~bZa@g9I`XdWJ2t{2t3&F?2(eK0)FWqcWs4B3Oc!7G=WwzMjh0m0f zaytA&mLz-7-&MZ>v@1hD@>TtQS4Kdu8(<5GOBh0&n;v4gHZ7C6iWJeD6L>(i*t*NI zPg{RAwKsN8+MvMk;`U`uXGg*cT;PK8viX4uE|Nt zJkldJjoea5rj_DOzH=(7_ce|xSX|n)(%!VP0?nTulXmu4^^-AdTYZjXY^eYqdpPo@ zx(&BBPZi`(tcrC2;kVF*b{-KhN;sV>E1TNC%AfZHuql8SyJ378Bymuj6Bd z@L#RpKdlaqMm6R#rtAeqjad{0R9ySj@#XrzygOC>8-m+$O&u)$5aoaSey3~B-Z8i_ z{|?hPx8vY69C%>{F*{S;D*bqQ_y1RsxooKIz9jY{xIS3n)uX7G-xAxy-Zn(|9}_18 z-*K=Zj1B1mUcD)*l9SYTa%<>x!*sy4;8Hi`}|x@XQnw zp^J!4vaHwE*7x(rLpx2|-%gr_sUOOGRDlecR)2B+6T^+N|6BJoU_*s}=(RJ)M&pZd z;15zMTCeSRCgjMuYRUkUS8<|h z+ERHG^}(tNSlR+~F^C0%UaceZmP-49#odmKT(X6yL`^dhA8FkDxE< z1l$x--YOlMdSsKm-u@xN)tVzZWqkVXq!qX(kUt~)Ztz;_0c5m}L%6`3E(3Ebiwhqm zJC+~%vs_JByKv3GtOr>KZ1((zw(H_V|*ZGvk?K!tr7GOv_p9rO*h5obHy4dd3b*La7uTE=9! z`Z0<;b^NOjyt!WW`$vz{+Vk1Ha8829r?S*EttGx(Q>7!LQyHz>o9>!izmKKAS|ce>ZTs6I(N#q`BF|AQL>(Pl}1r`kqwXwn08hBNT;{AW44cHoU4kVo#C z@@08EX*1kTJB!!S^9sL&rNh4LEL$a(+grv9Y0)pP!S^#WEO))QUmpEQ;#>@P#FQTvigoS$<8D9D#Cg z*uBXTyL|0CB!6snu+BBF>4toN@G{&srAWC&{4P4n&9Il-@;%P%5fQe;_rihT7>Vyc z;G=Z%06c3qMzsX<^uFV1D?@7Brq+BI(M6t>AlnJqh-r;xH$F(*ZXXybDUI_(D8)m> zxc+?cbzhtK`+-%BO#SZ2sADjR^Y0?D#k$1>=GwTG;OwBZ94HYFR6zu^7AEvuI3`r2 zzGcvQy#DkMMy#XW3`7wuhXneCJl$Q%7-K}<6_T8F$$}pE>uhV*h0Z3UTQ|JOgBX~q zW6g}RluX}YwgX-ysMi&~5yC-cQAzK`679u0H>Oh=!}Rocq;PXJclqh_Rvjg-lW&)3 zpZa(@9<4?2cDL_BXQa;-=Y5qJt*No@35!-y1S-YH<6zym|mZAKg8#tX5CD zPtX+|FDlMohshl}S(qQ^Ki0QT|69O23#N2_jI@~N!6{r`Cb~xBi|aGIet+;vU>b`+h?O>+)ggHHpcw)0)u}Xx+dj+W z?{>j-E>tQs_blL@srws#^OH~p`q*z%>#Rre7? zF+BysJtxVNtn^QBLmHdQH9xdZ5{wp%_7$&oLqMEsK7deE_yd-Q1tj2&o2@{x5x7I% z_p-}j(zX4Yo&B)QX^XKs=P{q?xWvmsv$TqSiqtTYThW@*ugtuSiEW{!2u8qq&S0Wr zigU`==hoi#iGi6s$W8T0INRPEZ&Ma+oct9F0l9^2u3@>ep@0LB3^<$po=C!J|BJq7 z$2ZCoPpbIbG!D#a+iS~LBKxAjwzNYj{5fJK$?n z*bhE@f? zBxY=NQx>+QgWWE$LSN{=4hGH&!H+Lq&G7Vr z#VeHu^$%CEMy^Ez@@Ny7<{Uy&{ zb*x~z!axzF`$n4hT){SeD}_w0{Sni+9OZHGmch^Z-Rq5FP(wZ6jVD8&gr2l}&@d;P zke2DRw88OR*9mcG=f?trv~Y|Y6ZdK=Y1!6qk2_^=;>0?KH_$SIGq!y;)nM4wA3tK| zF1ZRou9(57kc$`j?%D=&EB{zY9S%8MHm?8qQ(oo^OsQESc)vld_m5N`(lXf8%a-HA z`}26Ws8UBpH=yU=PSkT-ip>16#-Yq#42ecg?;4Ep`S;0l3-T9EZfA0XZ|m@Hu>g(C z7k8%fW;2~g3*=E^a0m0npy~YXUiK8z1!gO?s_XE;!VKwPcIW^yb9JbjpYCcex%F4a z+@8`OWy0OzfOfl(KE!qK40f_i+wXEe)HFKXzTQ;KcYoOkYMW)zEHsW*0EB)LP?^=T4+!is8)U;V;u5GH%_??2z9 z$WVt~b`ch1w|!3JVsJh`SHMBcP&yJ`T>G4}`*hDCI9Z;fLH91s^I{2vjCh>AwJWcCi!JBack~85da= zyP=}kE47Rpg}a{^tD7-bqaV8%!K#u@4vp0Mv1e9=d<>=O`qsTe9}Y(Xd4(}v>Q-_$ zLksf3y9W3bCdV>KK_)G=s(RLhu@sHF2J8)uA4wljbxX@=Cz~d?f7EX_ z5uD&n{Of!sUE0U;y+iASPrBcQkS}71rs2S#oJBS6_0>y5814(;y>@9WuGORkc=F;9 zBTD`5l};AvlHu~J7X$ZQ!_Bx+zk7xX3xkyDgXKa0w`ux;v4z{>(9~T*sN!ZK#qYlz zN~YnpUnv3-$C=_92j5RjQtFjkVY{E?DN>n-VJWZi)i+=G3 zc?RPV*^vGKg8c9eCi?~Zjr;4kzFKf((o4);c@sXM z;;C(FnSCOAx=NNCcE?oX>_*asiK2@s!j|fo>_e^%i=FGD*nOCs={juLRL9|U#sT@u z*i@5YaA3#ybN1OM=}|AfQWqa@#ZBmmru4%3sxE9eGO(pfe8fx|Eh>BY* zh*W6w8}z$Bz{$1Gg3S_$9R;jkNxlC?TNQBh_tJ-!x$NY*=`5`5vcj z#0AF>+-HBQc0XUn{nGz4e*X4SI%f0+Tb!J~pMxZ{gs|OFg=fKMd}J=a4>@=!ccimb z{0be$@S><_t|X@DVVUh~GRq@dky0*+or4-14KGMtIq)`n`)X#5dWhLT(|%4ZYv;CC5F%{z58#-tKGg6F6vexQp~PZ6!IKNPO?EY$gCg!gZ&oF zg#&kSjvbzS$($4#f(aAbN3jV==Vi8^GBxEu0FIDF`4b(RCi6j!1T^e2G%*Pa} z4FxGM<&M9MI6x&@AUfE=pZmjg!hY%QM|o@MQS9F>1un6IyO$iCX_EX;Z}5I`u@^dQ zo25Yy&28i;;^e7V%^hDz2_@mkJptjd<}Roo>l8AD&H=5VFVi2BABiuDsbcVvpRX;3 z6k^|7B;eo#Z=+Xwc3ouRiC42EwZ6u&II`C8$7|5OG6e(yM=pZG!3q)lQs1Q0G&bpM zMel#)X9D#ww8g9)s;gxArqMyifWv&ov>-(Cfd0!X4PZ@D15s}yyAgaiNP_o_Kp2ZC zD(2b0?z~-myZ*d|V{d`(#2)jSaCjQm4erJ~A0#ZFPL~SZV=7yye51|BL%(77cObFK z%#ClU{}&`Ne$hdKiPKj?qJ6V!?!jvz>ld)y&v3|G<^N1`j?n+A z`R0Qk31;cT?>{Bdj^DW~tG2W{7O5dGR+R5ivCi4AB0R~Fj#IBmJjo=UmyqhaAPBYR zANx+eZ#f8uGX;4l1Mj!bY4ngxck7Uwv+1BC2eyamwc9DG>6H$JBsBUxEX%$_{6im! zIqB2*8>9TPk5ZQy9c0QS;@9Y>-yBbkzTrQ=nIymHu0C7;k>R+dba~aa=smuY$p{V4 zW(z4g(07Q%qPqE4ZI*f{*9?u{U&UyT;K*JYJ)(+!8c)JP?Y^KT=+4SCwF4_-;yJJ} z#;SFfJI5B@OgWGy)(W8}gl}ZDg2o-*Wts8Z_89J>4H3R{bom3{1-Jdsh-viUJ0?;x zN4)-ZNn#Gc(;FeBPv2A6M4C^Bo41`qVwiZZ1&%rUN_PhR))1)FX@hoJYLhEJ}Y^ z^gq+hSYvWl0YdD<|JJl(UZOnRM@Lsx8*l(8M(Ou|r2kG)=!|1nMx7h5CB+VAV zZdqLSCG9@qftQ3Ue=Wrpo&MHyGd}IF`2KpmHsGLmU2yKtC!wb`sn~tp?aJS-_&(PFIgZ* z5p+ASC}*0d$`{X}YINPP+J?6wVaSZ{I>E$|G8G41)HtLi>v3tQ=m01}jXTN}=)5X7Ec%kK^J>6w zD^BlKV%4OR;gE<U?G^Z zy_=UL`txDUI}HC%-^R!V>U!-abL@1iK^&++-TPyK|t&!pm9T1 zM^z(qf|fljH`Yoc*UBjr@OI6p+Spr++vLKcqXgJ^%oEh?)ZTjgF83N)**RL+Y@9R1 zXotzGrAuu7-4{)FWa(Dy%(*KI(z~>>d@@Ntu(#lNc{lHp*Dj=L`mleAV!^P%)(Nnh z7qNWu^pau=D2B*;abG(wZD4~~*3uqEL$?M!uQDmz$2T*j4cO<3^RL4%vdT%g?a$;ZyjG&Dahun|c=PfCb7c2H z0KdT18NGla4wfKAg>)*8K>LbSd`n~nkbPa5>HN8kI_f$(%|{cfoloXnPz_WR+WF;K zlh6Ib2|s5Ychpd@Y?ZM!6*2{o2(3c>4=u|=JTY5g$#-|g zl^YrG+wt9t01M0@|oAF%O_KP+~~QhT{B?x$HI z_d*(?wBrZQxl-)hUo30>-s8Up5bp8w(0n;h|5$Z*x+u7iw4ds9y&fc+&yBc|0^2U_ zg!trP=5Fa%h-=-Sgwx@gM^Ww_T|nj`r@Q4g3w->encOrjYMW;KVBU@HuepoNl`gOh%Qrg?;SX zishjdOzp9dcQ%|oCpc@0l+;U;19c*@#@%&?Z_12?Oov6FPd!H)e;W(+JBY)%v;Y=B z6&DD@8P)k{@McDQi#@P*(aAp3Z_%jfT@_LF<`9J}g{|jxHPX@+)?6`57Z4=9ceB_e zk^z4Kx&gP=0FUAvyr!GMub-Vhqj{nDWsM^w)PF%yotEz)wFi!T*@q`%gLk5Dp-v0y zC^_hy;k}#`LJ{s{CkmdzFoWL&zwjJz_0`ka+`*`~lbz@h$%Izl#dbc!ltDJNoJ(eM zv*K`*_|L(gYk$fk~=qv<0!zBZU`;-|xCRg>7nm!*o)2lS{<7IBW=rH1?dz$MNDAFKUR^bo=yf+Wl4O-`(l~%T~0? zX)ki{rz(gGkfh})cw0S1ul4UGW{(lTqqd+YcdsV+;7G-yUCqc-&pS?zzXoiqfde+) zubh^LI2rsgyU>qc{u(lfNJJr;#}|kCn|NA&&R-B1mj(Fhf4cfA17*M8LX><;&Iw(2 zh0fj;HoQH%G9CcibxU8+R?Rc7dp@6cpEy<%P+p?zTUHQAN{DB#r9>72dX+DIWFy3P z6{IE_{+E#YiRa_!VC}Z2`-7_akWe^ya5Vo<=_Bj^Cw+MSCw(aYpVCKMig!H5*m)|5 zd(rUs2a@rToIbJDR4rHLXz85Rq3J7LUaaIgfsy zp>kMeMYz|`N;x|*1@qUeCwL$=OIZIbYTN>8qaSZLD9W(VDRkP3Jgrus=zl~ko>*o6 zH>N39Me$&w#&btwI(@5jviv>OFCU4X1g1hAEQ^mX)c3zmRB%=#tbW^TUaT5MP(~%B zMiBOqoKN}!&K-BoYt)zL$%V@jm^vMRHryGh%weRHp&D~Pa&445X~GZ%!B*{b;ehti7#{DH~uHp z^fr>WxM{(|D|xLsviQfpCT$X&s(KCJLmsat^MP2A=zjGdg2}7B!D>HirMYSjqP>vn zCfR5ar^LzKXc?@vd?MUeT8DG38b{E;m>qVXythH;3j>bt%DNzh}Kes`|I zU@PuhI8;{peY_*ODwlYjjSvQzl=)Rn-J z;>T22uVYzA11I)<5{o09j2a%}!V7`lKO4GVeNx}R=6tTqa7fFlVx6sI^Nf}%JWbbs zD=Kp0&8%&tl1w-+)g(7}4@(;KmF|D$2Tnjfacaq<>tj|SlVML2%hqC@7J{#Ib_YDV zdWsuZuTzM;rd4Cyf0%*L+v;5*(Y{I~7|=aFX5!vz|Mp#eqoUu>I4X-^8n?7rK7tTE z6jx*w+!mi2@C%}5^At?18)0rW#Z~tCRG25a@{xUsW;6BU?bVDWoo+S(NPSxN*6vq{ zku4PL552@Aa?!qm3V#8z63g!nW^FMTL>{s*_^0TiM5_W3r+s8+aZhF}h3}m+)*^2! zwNW{Ojp)~NxzPJVhdugNRqO@45LOYa&=h}{;WjlJ6LRrRl&QtrS3t(z^k4?0H7OC( z(>RPKZjq+_%OpXq7NX&AFO8MZy8mN-q<*lsnP4i&zd^VH=h=cSje;%9o4^lu(fXP! z9CvQ3QBJoyfLoO`Rl4;IC47OEGH1H#CGuEt3Xi_hUWbHhg}KE4*Zd&5_{6tPrpu}y zHk$lCx9@+oj)8rk`yQmy=z+V-f z-MY*V9cu1}(MS$(Cd4Ta``UWf2=5Bxa*< zc<_qx98xe-EAznakER4-8#5F?M;yF{9wWzN>dVAlo$A%y};m|o_-dEn<$iNH#R0| zr#79GtjM4_CK!>ZWWilLLe=3gpW$S+B_GS!nKT*eJniE(%sWB_-toEdrnZ$m3d?MM zqhMiZj5u~#2cegvtF1#aZktF!mkZ3@KLj5vN|+u~%*Hn@`^ zpexw^Vfu#N7y~p@4GVH%zDpY|xX0Wve|X}gLf-ErwIf-_m^&7+OpkQRA-9{%tPD~_ zXP%}`4=$2&T(T_uMk&%W^{ejMNCh0s;nNo+01evP&i!d5us;XO52@Sb}PsG2Ho&{ z*7alDvwX4vuD~mgTizg!qp#1$MI9TA&)tL-p~;qKb_lB#1akU?b2C-X-RJDz-J)TO zrQ*igqg=z*Z^tA@>yc1K=2us%KUKEFjklw4nswa$5}nGB6o^4~#31VbGe5?2%qM%A z!e(ik(YDb+gCjB2+!^@k94D?0tR>eLd;H zAixoSK-@Z{%Qvp+!>=@@eZEG6vywDicef;+aW)z}cC4?An3g@*QHrORpUHemDI27K(6!%Ym0lk>Sks%m z1A_LbA~6H>{iFh1flgaZhyycZ+A>Xp>8nw7h0C>HYC~s zToJ_$W#4^gTvlgH9NnxH{zO*%la;T5tY;|aBz;dL9Qfv(y7AqQC-gWQAv>oT97ftd zw2ZycHS|Przq=AL;ysfC@gFp(V>snqku=+#BUZ7CJ!z_cJXXV-OLVPfmeyHmw6IHu zApAF>XKSmAq22!WaWr#+s$@aobwdSeMx=XDNv@nE<9&*9;U};;!4Bl$qhn-zLAI54 zs5bo{u|<|!S(ophTxw<>Ob=g&$g>C1gWu)5tclBa8|pc$#r(!fV#8#|$hm0In!0%B zbW!_G`$)S|VncN``Udc~dgD#qi+oXTSEtBzK*KxD@kt)JrAp#&4|K?K!@CpV#_*iM z@Q(9XQ30{W@RyC@n^L5XI9_GM6MA*Jfytr*W(_?;)A-xu6Zm5W?!{M>IlRHXT~Eul=E;CG6Bgz(>?i&ul_XYpQGRDdt8(a52{On9FMN ziduCh@ST@Fn}5$8)y1IDKv!d8@V>{vgV_NO?78#m>pEAd1-e+t0T?g~ee>g{HTTQ^ zMZkWDuq%2o4XFjnCfuIkVaACuyFvpYP7hJXZ>wwJfi#$L3)np##%SJ6M(coj=>hzJ zgq#Rm#8V&0i5*a@6JtE9?!p7^&O7czFGeA?ZoXh@A)h9583-sY81+8^)$K#%?qMxJ zC<>znP1?HqHnwi7IxKOBf4!H}eQ;r#KOOgqe@t@tydntjANnDE@8A)FJvxzj`av5& zSy-ew=mT?xNV?r2%@6}uL7al||EV8y7)sv*AB|cDv$+p;=FRPU9j|Mta}zs>80!ud80SLLa;ip`2s)y#vKmZk{0lVLc{m_0!jHS0&%1 zY`)2yL0GWIEHol`!_JqxmNztjWa+58r68_QdsjKQMDu4qC)n%D=U`{GU35MwY69H>@xYX)DjI9@g@LZuH4%J86uctb#?`Hu!}@GTukVu z*vF~bD3`Pjf_itc`EZSB)bvpRNjBGXtd!2zwQg?O)1p^^#eJ;%57d8_+E_XZ38#>g zc)S1Od$0r-x8?g35*oJqyxTvKo(P=88#krC!Hhq;$>8G_^?6sTMZMgP{~c+J*6>;kndZ!ws z=Jm5VoMTo8*T~N%Zs86$*u2Zbc6&P^tRvnAYjF~sY4HVEU5zB)Be^lU{Cu````l+i z6sa~i1l5r;ddKPcqF+2FuaK3+tE*wW=SdP(Fg*%lRiFL`@m5aiOhM9Jwsb262BY))Q>61)-5N>p$gFK#g7=QHk> z^!Dhj+FHA%kGajEE?>0g6QlIBKCSYemMWZZKT#qoGT1XD7@N>BCL{vnAo%{dMP(H1 zqp38%t4p%5BQrQ^j!(xfJr74Sy!e~NUDFC&<^kVdBh0ylLtV`Ab2uqOKZmoIOLMs# zJok#d`_)F!CrKR|0A-3gmha{o4KD?L@UX3O?| zu5ROZ|4`%N4u8=+8Qw};b-~77su}trIS-ZNg^o?yy)M^OcpyJCjq+dGcuF(0m^QD? z?O3D1^oo9cyXO8Uk}61;EAWBSn|@onn0__5#I^AZve&+K+d#!LcH)_>;fp z-2G0sBTQG4eh+&8!{1nQfA2i7e?Z^e8L;#huOYgRg!5toLYSB`lP)=CO0WGxBF`^ zB|vZFYc)M=o)V}TGt>-7-W_UoH-TjbSc$jAcZi<}C-1Q>x)2*9RgR|i7Z$q~xQ7c*Tv9j{hZOh>_XLCB>T4=F{C~FnPZgh;VAD4oJ`21>KWC4|mT!y1(t`UfQ}( z$F8c;S?OaLyS?dldFsWFE<$~dm3&NqCY|Y#>x&srV-_qXd~IW1wQpK{xgIKAWEOl+ zZ?c}O0*CY++kVLXsxJB7^LI<@n8$eggt&=$+fNz-1>ZB?i7QEH=(^(AcrXSN{ajf*f|>9*%}IK038ne9&Cp<>Xko|iD%7mz+eT{otGa05J@FFnShs(-M zVDjdx6G-8VI%A*PU6PTY;9~m{+hb0Lw;YH6Fe%8}t-Y)~POsnrwR100TeG>& zt%`?f#zj}dS)<5rt;+x_<}A6NwfAAVB_rXrq*OiIs4173`#`jdqFjbkjzr^mgP*LY z8`zn(j2~Nv240WK-u)m%e6~d(kSx?u3%kxWojz~z*8LfyhGh-wH0nbMjh`MYjDLx0 zneO?}U9Y`^bCiKltTl{f`A|J7JxvPrR#g8%dp}Le6O~y$cg&!S&{|cd?h7Ke{$9LFvJbHb3UsFN!huJRrPR;P%GoF#gEuL$~fr$Hvfp?#kr8F&pM)uMYz4m zn|RXd=LnflbpJpgqo7q-6J+%@y;uQ+mwWxWb9Va^8sW#=t=^K-`4+N}@hL&{O2Sva zM|#yRv@Y%a8$LqEFIJDErSQwaMUlQuP2??%GD;c!PJq+pHQe}v#i>T6=H15aKC!Hk z09h%s5-XNZR_N~)03dcE$GP!=g-|l`!BcXT@D__g@bbc+{>X}uH z^f$)4)A=Xo&PxyK2d-3U7~_{jMx8{))4KUJ0Tz5IhVN`*PrHp#8@a()of^6aFzBZp+Mn`YG*WLU%E+r`V?#Is=khlf;s)2o!{>fv_m-k zcWXVSYCR;`AM&ZKF%>xBJ*w7uAmMSdt#P>__sC`sa*mcC{7KmYVAWW%LH7-YH{+H7 zmTy2gnBnyAr+g72yr1TTZ>F5+;tn5SJJAi!HGEwJ;m;V0#Lqn}7k~Xge#B*R_Yk4s z-9%)pkFxUv+uL95-J@V7TX>nrU!D4h1| zyCoK5Fp+G3@u0wlbaZC^bD^=}C9F?YO5w!cEtJ3y_J_F=l|cOfO2YQNjBStF2=4!! z#9VS&(_LL|wXMRzH!c(w^617 z!tH7CgJh%jv6OiJw;f+&N74pWmT!lpGe^#i@n70sHCNm6dWA&8Zo#W-qS0b}%he~O z6h}P?&Bo0mTxznKr!Rl1FBoQ?T&}(&=I1gkM^ZEdKydwl=4LyD{<@ z!p=B=ptelMenv$n45QJAFN~iOFS^Qk6f@TsSUOU>A$H<7j3NKK=W#EOwmtO;5^GK5 zBtER}JYN3jmw}exN`W>*y(H~tR{WTTH6A7TWTSYPhU84WeGQ3+Z!^O^NG< zSw$7Ggjv}`45X5m6uG#Y3M)+Bw$~r`dA9#s)Ld43dfObx6Oc5&(oTlqrK{T=&0kYm z99t{DVfyLQu9GtOzxtuguTsL~9R`=G`%Gf+Sd7wFM;iYlQE$JKbn}UF@Y_dzFh#dF z{q0F*?FN{beq?7Ol`2e_Z$958sW63AC0U~gvWGn4>PtcY+`c8{@|)CK{j;PblL@gs z8nHO)?r3G|$P$RO7T zkQJz%(?z6+C}1YcgPntWz$LnLD1kikz(ZwLk_YyKdnEJENJ=AXeYoBqfb$ML(Rf4_c*t}6EKqe;@_fT>&k+2 z%*kgFZ(N4D7a3N##vfy?TIv*`;@1j;B@;lN#VJ8bH`pDWJ)ZdVIA=iM$ZmN_(}Ym1lOPh{J*Qcu#JyDCz>`1( znRLx$N8b87$QZfmb93`UEN8Gl)5fU27Q<@>22WNC58^jVmlV}qW#H|&YrD#%_9_%C+VDt({POKE!e7=*ek62U&RJ84T1dAHcO?%?!w zrs`FvZd6^1uJ~i`baqyKxPT^;2@gZPZg)!o99BCiY$<pA!F9JJ&$^F?7Dsk*@I5YLl|KPeLOV!iA^2+*+0C&ZE#^9s6@ndxBKrZdHi7& z)E|j2$3{8m62e323x4WF&9aBVhn#9jv5fKEJ;~sr)xCGaE)ZO+K2&?RE7u+!)=A*> zSb8{!xThwXVW+TH$oN8&!`C)oBqakMe+eJ#2zYp>v{(g^PE?&ly~SkKI}OfZ$KM9e zlL}u%svZpY-3-0y3HeL?dl~Mn_9L#=A(V{soxS(_sBeew_S}Y+6l+&rHagutvk6J` zI&>Slp=%AP2`QHMj-q;IF81^ml%LOr6`2u}6otfjRSxL{KZjc}*vY`R0I$cty1=ah z_?$6J!(J9kmozqA5U&UGqfDY;BuAr2f{a0uE8;ZA{bDqZ(JJXLBnY5(JcW$+idd33 z`Qr87eBsd^b)7I5gJVOcsa*G6ptTx%2xR9i$m$oGc-#-eh`Lw_fpi2n!v%A*=a5%# zLX>k(l@;wP)(M-M)HYUh!ra zZwiuI+g=>W!%rSyAw8j`t>6^g`7-8Prh2yR zo@?Q_UosCBg&*(PmO|)t1uxZ;nxn|>hr#p*s>X;@0(vA16Ea^McA9^Z7JA|j!s=Q} z4`u9X?Gd}H1uy*w>|pf2*uIUw?igLYQTbGil6-G}`0rsIFgoaVG4TFLd0Nvo0&Xvr zRUg-3gTBfl6-{FTteVITO1Yi~Sznnn1l1q)2}(;v|ABCOC8RKu|A82PEvAYjAoVz1 z$c>6`?j~oA#Sws=0hn60><|YQ&W<($ZWVCkl}cYT;X%v`T;fu=Rd~n=<>C@>LWF!O zi+61kWn_kM;2eMFMYNN0CV4`+uml{c9*=X$O=I4Kf32nBgAw%Z`f=Z@{ehnZLzRPm znKHM1Nj76XLmce$bDv#uBtTTqFK*TTSS5ag$6ZO8-taLY8=X6mtq7DtpTv77?foMX_B=lbrK*Bn+HtE(>^>C7YkJ$3C#=u zlLR+#>KxO8W@W#Heb7+P(c)-S8rXmly9)WCd9u~;H%^{)14QU*>Bnt0#)+x-MG`B7 zwVqbBlojA0-Y4gM4pC|!%rsXpOVk_=6^ zA4pcPpYxkEJTxomzvwJTo%eGKLUcYk+3Ec87qEdjQnk4ROXv-D9vYP&Z!=8Z_08p= z8wKtTEH~7#0goYpxXzy#-Hsgyp&vYn*0*W43iZpw7}NSWVI?8|jxh85Uk#C?f{SB= zNo%`;{S1YtR;M8mM<$_a>W;`!MDXP_VB)zKBaVR2X^4&2Gt$VwnG5{$GC~l6$&~-7 z()3!x$x~U^-#s~Z!e`N*H^plgdY8bgJaf75ri}eSKP_J|9|Ig~2(by2`DX6+W9Pi6 zg`TOfb>!q9!4T#BKE0IPcJxm3fplBi>ZYSVg#O_swz=5%%|&&mSFIo|$gW58gnPg5NH&bQgOh_TO9=`zXiA zjmB8*ilC3^y^??#=`xYKjAxVXCV|tX7}9+V`eXUbwux#q4wWi6k&JN;t_o8%OKbz# zASQhntB;~nl+sU^?HvARJ~=*9lF4MZow)tmI;pCcoiqCEX8P`k@6-0ltK34KAB=s| zR_h_!Aqgpr4})LSHcjjETBewDHVGwr=5`6CekcTG6+2h+c@Ia+4*+el2~AC=#=xhx-PG-9NyL?NxxaA)GnZ5!7Udn z7}$~CaK|@$r;6S>i<(P+s7IFKI()+v=xo~DRjHQMa953fBg@5bPK^Fjjy`P&IUNY{ zTQRH-zUUgLx<_bh)?Tk*&e~1x*4N!M)qjN$+{1Rg^r1#jBy{AS*`M3|Q+kLNvT>xf zD_F{+3)FG3fHT77h?WR<1Jz+dPIFD=1}GZgDlw=beH+0%4e9Z$ZRqjVFHv>%-NC)# zW-4g~8K!O8Lpq=?C}3)@T8$e3OiT{_ls*FOG;A0){Y*cZ zD~7M#>%{;Ukrty9J8D{5g~nVdOPd(|QZu_ z?{|?&;Pb)uHSe>%6*mVnKP#`_9^Qfzmt20=pS{XcX;hs4v4_^oP4q0#4gau_ zk>0p)T5ySFha+_B`4Ti^JDOb58B*ys$63$hlWlg6o~aI&3?yltaYFqxbvS(`3*;$uD-bCxo!!!_(X0*p3*+uSUsdA zaC2gKejr>t(wW(kNML9Nyt=GZO>j;A;Wt4OK#(Y(;8CNc9C@N>eWZRg0=>d6uMFVS zLW7s5YfJ+`*BAs=28og}NI5D8cp^`L6aLmT{-T9XL(=`A1bkMlZ|RbreX=v->po^{v3YKJEij+K6?cX zxrJ>_RS>5CT_InCq4&by#K5qqv-T$Mh~mL@|E^m!HrXKe*n0LCo%H!AKkW$tP-rp zYV(jW<`-naU$V{pk$l|?&MN3b{T&w4Q7Ho!n$}Nye`TXcU#mElrFtTc<@fgqCf^7) z5}>;sEi%^Bp|lEw%w)iTeUa&KEIk`xA>cmq(sz>68q9 zmo_BD5C=R_t~`T6DA#cP49T*c5sqoIGaSE?{-NqPL+;f7G-!z-W~2-EOw|?ZlJwF^ zZuVX3gP8Hqx-O3omf@QanH-K}yZF@p}>(&<8?UnN zJ*yGel1pJW>>yz)UX!mF+@3ldLdWAhzF@n3U+GGChMJ=;m5h6Ykwp zTzgMk5oQUF+Y+Z%YzvQ5gXS3@0OC&kzmn?Z@xUw6o z!7=EMhTI-~2J^#HuFiM-5<@I{_1SC5rVVDy=eL*+CcqT6l4nzP zHB?GNEc1q`4c&azo4t%H?roPsQAMtEP1eBNTfi2(glt$lmKV!ghJK$pk?NxJ-|>x* zhWjF&V-PnLwq0Y#d*Yy|D3*`6&_$?0eaU4}!HAJ}&|of>liIA#6_b0VArWlTNh(+=;ytt4hoIeh$)P?V2kC8;@hn9F*XDQl863Dkjssas(E}b zeW#ruH%Yd=5=#`?zdpW>e0)+uboZ@`I^^-4KW*q({MvX~H*@n<{gssD&FD_n2x0t_C^g^GcQU}(GUY*#q(kNRn2J>d`Bb(T^Pb9nCH-*W009`2 zF+dfGaC#pl)a%={s9PPm^U-@X3tkq+w|-Vz&ye~NFe3Aq3UA5HZbZi4{9SoVOrrq9 z<+4A(@ctdLF>4KWgD(t}O`i?YMKNY?voTin9UgNH3IqEhP`0MH!6x1!bwTR$fym;f*R^ zILUsQ3)UWeazfRIXy{xhvEzy35I*}J<=68@qC<+6$3a(rJ_Z4{6`6cA2 zpyK33fZUELb#PvZz_h)wdgydf%eZ=wt9@+;-CotN?J zOGdU!4hcRrRtU#-R|U+L@^a0PXL$J6iRsVr+2A(5@`N{|>2nMsS)@k)HH6Gjwm(uI zg;$z?z4=?Cy!jJqcd^(&Ce0g^h(Jqi{6B=x`R@{n~;_mKl z#jSX8C~l!ZTijiPyA&w|DHhxzkN_cYa^KJQz32U8o%6?DD{E};naRwWnZ2*;*D>M| zq7-+xw&VaYs;Y%x1{Z{lxnW`7aj52Q6gyey?Y9aIFXin0WC(PYG=k*Zudyr!Is~7| zo(pFc{Rz}Prz%*-xe=AK*eamg4?|N-m;nW61k7Mz2dHI>D?Uc9&)=Lku4Ohob}t4b zO}QYM63k}P?A?~gs5O%PSJnFmYnjT&$XDN5$&wqtsKtomdczsV?vnWc6!U5OZtl@$ zKnc`Qe3MS+cfgKK6ZLZS4Q1XE(oUIm5HEJxf4z_z)kVTQ<>aq?oEpBU#r5+>J8H4< z#;9shl($-;VWnM`xQSX4Swr}um#OrzFfr0fY0|Iu{cMQu`!RoB+MTv^SE`yB+mP!P zV#rnYJD~p`wEwt<;_?7O{Q&_da5mwUNtu< ze*$!msR|bd!WILD0@|l(;lx||$NnXw=4#KO?jJwqz>1*~>u`$ZfYRn@(Rk>I-XNv( zrQM}((5=kyQuwDH62(SDc*T*<1n=Vo-{sQAFpcW*klW_WUbFrK6+QC82a46oaY*N$ zl4?f*Q_ATcKmR2WTB8l64rSS>McJYZWo`QBx|evsD!(i}-rKvyfr7bMz-nETkFscw z&;Nn9=m%+%FGp~0y`bk=+v%4hzGqoi><>C8dOuD=YT(kxP zi|w|OwUI68K(>JPvF#Fg5&k5{fyr?e+`tF@PE8gIJC2_Vj(&KBl1KtQc7helSe~T@ zuKd2^)Bp$)o@bFi2S7wP$A=%CPtFf4L*p)lpd&cm#zbaB_1Xl!dVHo%a?2sj)6%yr zC!0aQl>?{R;Ez29^djC<09*~-iJ^{3Q#9KHkC|xEv>qyX`ctK>)e&MX!3{LWOLI;%9NvUJKnBIjRo3 zRB7@@Rw#P_^`mqL_OnpMGnFJs>wnHd(RJIXHI0TdeRXaLf^FyP)~SpPx9&MsU-0-poJ$F~N9vrI>N6&*JB@Gx{Nr%&QB+%Pz&YJSa3(w{8BT;{d4_{6 z%w_$wF30eqjk)lCztMA z&|6d-9FPoGn7DRWcgnw1Nyz|UyiV`J_iFRi2^!i-Y*sIztk=}M-mcy^5`@Ed5`}gm z9AiH7&O90T0$Ks%ZU8lcL?upWqpVK0`a5xho~Y%;{tmEItPLEDf#``rTK`}x3SY&) zStJwHDd6={zcW|segV}+gMJ+X46PGba*fvMjh^m2ygIpj4$Vharxhmd`k(3su!lf0 zZC}JaFrl(2fqhEmwE;Br|Jg_C8RS|nTW}c9Hdp>?aXslU2xp#x*WWb$pRHb6%#0!D zJ8iYmm39~m0>+%$MeUX!Wd?m4y7_2Ux!4hj)*5nCnF@8bPG~EJVWEwNVZ|lehGCzq zo1Zg+ZIdToaw%3%+qUa67mgXm-%P7aGYSZ2g%EIMz%70OV~wNd5%zqhUB-?N;}sqG zP{a#(NdLwu;svqKi$$Zt&*>jG)L#90Z;<;FMkreb`(j(t$*%V^A?pYMnBS1aX@Z!% z^&meBAst-|ZuQ=HiuT^nQD8Y`C5Q?J4$^%mH$Ahl*ode2JWum7VYGwknZfN09Rg9_EjP>t3 zG}K9_(N>OCF^STt$k&y?PBm0Nr0JZlHWrO-2M4|mX2kz(ZS)>;&|XzXTHj1s-R;K@ zE!JjjA=N3ejV)U#EVbtP1&1&|>DHaNTo?C5YDe#03G5GeE_-<7%n8#}q(H*(rtYLH zQYY}n?m&Gu_JUbOzddty8%nl#Gdv86@USXY+?e-y)6ZMe+;jZ!vSLk)f5BUfZQD=E z+SvJxNl4nN9L)-FIlbbHhYLq+y22+YCu}k&lA;=Eo+-Z=xlJIfQso3PTY@hU8o^>}!K~`^yS+Rm& zI%v~1X*2EBHd(&O>-x`J0uO^P_3IE7x4QxlgFiijZ;YAZj7h|jC&IBg2{R|yv#4;h zJctL4Nr)W3y#0)sRm7VW^-tyP$jU>Il?!lsz049u<5cpJR4;o`zQ=1kIg(6rb=cm| zEA2pCBCKb6j=C%+pEu&i@1J0ydrr^30GHx77DD+(B`0e`P0zXr|J^JKfUM)l`4QAy zdF=|6GzpY6lP3?`60s(@4A<2O;wHg?6zyRMyqE0%PM|wXJdfYDeU=#oY_;&PYJtX; z6Z@AqPW(y3AD>MJjsm6vRlQ&j?@6fW|V zjiI@yja}cTM(HpkUm^z?RA}a<77J+2{IQLz!QLNl&Z$ONG%sJ;^Y!X|p+Y|Vtk961 z0Hxx-6K<;OIPmrSoPzFuIr(iXg25oF_W>Dn^Qv+xNj^_licSRMg)gP?Z(F)qTm7g$ z`W5B$W`m2*E+jiEllg45PZrHN$h|9>dS>Q(UYoSZ6(i~B&{r) za%yZU+E40@D>uU&B(1iBGwuF7`+)O7FUsrZV^AKdB_d&D$4(Y`DC$VQ4bB`KG+z^y zIsq0w_xk1qo|u`=xW6KAyrV(hLz0>3lfJ&sdE3rJ4+qb^mmkkn7FS9uH}P=zpEoGk z5v(RA97>Jf)mm9Vjgiew@TwjY+RI^*`9Ai%ccSD@$75Z=bObD%%bxJwz^BGIZMh4- zax6(9O&BlvJ-M%^N_6>K*0-XLC;7zNvn!^QZLQo3Ro&_mm~7G&ekV@jR(e_D$tH=D z=j$QE9Z&@jiq5Y#t={aZyE-yaBvlkMNJh^)l3g{Z|7*-Tp}ul!DurWZ0Y8#1|72!} zMq=&d{4L-9+x~AWI&=3TRkh%+K~&Gs6nwZJ%3J% zuR!U_FLbh=_9IOqukZYnLL+)uK1OrqS<|(3XQ*zlu-5zDyx>hu8i`Xb!BDU6djO2B z(|2mFSut3d?^MrpHz07*RqDL|R_(7qRVrjSQ3(+cT0XK0J7{>CNpngdH~Eu=&ZTtp z1iAl_{4VY0-qYs(60z$|r6ulj$Rp96=`H?itc%C#CgV8i%i@|O#dcnsp0dT1PI zdarro-d(09&-wPjM>@-UHexCFaEh$WO$_bK%F8WiU~Tx|IeI+a^zlTG*~Qjz zu-OkzFm3{r&$hr154F%j;oUn?V@>J%vL^)K-tNA!Hrr513P8<9Hh;&#u6rNM^E<{9 z7nBX126zARMzl#SjlKT3?=`xd<9{wUeZNwOQpf>`wL4xvSi6<}%uywUUL5fv4pKE; zH@0PDNw8r;e_61&8_RPXO)YLL>M0AZLbh_oGHueIrkG1Z_F7QH+MfciC&&)*vFqFNvo=d9!9sN06 z^DE{)*1Q6RRl(}OZnN1!ciN4@Jh!ed%6Glg8`wD+^bL>1+|h?}YfwUQKvHN9zHYgo z@y)CJV<8j>KX_CQzk|3!g-# z;LTHs3tgHw*-yI0u(tV=?hHA0 z3&Wm+Zz+rq7iPJv)#)d&tN#>n*tmqKTlF>UFJK3&x^8iT4Z5Zp+Xfru0*zp&6Mo{K zmN*gTgFT>zp+4Oy_ruwIh4%u7w`ZGvV|eiB`q|svS?z>SpTeICf`dfvzj6xU9k^;1*n!l+35H{6Nb*waaf?reA#UE7o zAy(GK&;6IZV~L-KPY21U;E&ug@`P*!r1rV#X(ncP#|frypE?sZA}C2g_8^tX8m+F~ zU}sC8%4C&EXy;?Ybslk5PV;d-y$Vpppr4)7YH_7Cln+j_XOH|aYq8uzOa%F&RMq~1 z%6TL1TW}?BR}{a{XpgrhT!4rUWVbjj7%yUH135j~ z*FrZO4lcRirP*6tlx1|_`;~4Zx7B7lqwLeHQ$s}~#;)qt)0IY!N$6#?i}4w%(EJk5 z&9>V$!gaaXld#bM*pQ%*zs1uSY~u=dy_#jpa@nlmxp@3o9}`Rru^RV~%ga_Z9x$PC zpSiyK0A)oey*m@QTisO6bl0nkz5Jz;5HH}tQ&YY~^tW|OGk^8?5DG}{g(D`#r; ztEDp&^o%xSCvVmd`-$oqeQWodQxdnj`Vmg_8?TjG_=FfInFuJg;8jF@B{&>wQK%RP z&vVLstf+^Enx|Jfy7leQo5kB%=uXbRXOFSa$ytb9*##`+8CK8V!lUX8c6oXQYFyzQ zrnKf&0D%*b6E@%c4lrIB_ak zw?;t+qX@X9-%I0CTbWkvjod=m@77xM5Y(W*-z{#|=G&ijoUbg*KNhe+CRDQ*?s&hG z$8T(LrYYFP=q56QtZgZ)f&1sX=UAT+v?zYZFUo-q+t?=>!Od zsbVJ=MT7+kkKz-@k@L!tC8q~O79WBYADgrQ1#yNtUzbS=H2hD^2=HgG4#t*CGCvG5P1`&Pn`-<6g&PzPFzR+TLkM!Ikma(StVF;G zvVgPx=wA!gWjkn1kGHLDtSBYIM?3<1NiHa(_9WjWJUYXQ!vt-$IUkaUJgPiNL;Ig@0tbd` z3e@@*00HslyY2^UZ^NukR#w-|r`MLWd_)UX#WHu7TtnTwoU6Ox;MGnc_4@8gZs{w# zpw+Rxdf8lz_5*i<3W?>-Iqn5xikg80rKv#OR%emgt8+T%&tQXG1qOo`_cK}FBB>a; z<2>5)tUUTiGj7su^Dm}DS}qGLR%Un#R!3fw7ZSL8f(VS42!D&^*L?8oAv~^o5Xc#x zewyieGZ)a-*BM~?Ai4Foj+%P9lRG9k+E=H{UoY%an%w%3m;3xH+d8-Q~xA7}v zvyY=YSll;fc>E=4u(Cbh-nU(fSxk-}_&)a8L+*GGeCGPRE}HtkGpcX{x=_^0azsMi z<+~`&VoPUcqdc;KFP65JB2jjqn}QJO`l=|R(XDZ9j}unHHqH_x6Jv|H^j~*{K(qcg zVW=0s>+_x09UoBI>cjM!6nDtaso2P9mgN(6j3CS;rK3;XWcl zI}Rs%ubw0{ruEm~OD}l2EM8T;W?A+~?KE%Nc~dU0 zCT^*MhbfS7B1?ez@=4f?!n*IthWVw&WY({mls#&J8>Xb1%8{S$;pT3p+kZH^XKx_i z+QvWly~$Uw8t;-D$&xnDxsRh4ARA~zelWx`At>j~l7wIl2-lZFSoD@}9H{~r1BaZ( zh0cEY{ya{}@gufMv-(pk3dUJ*$!-fzTzyliWufmMZ8vp_@YNb-`K%A`>p$k6O#M8jWfQ6%3n(&xDLo{jrubzTf)dnr zBTkg1r!oSGEvvp)o(X!uNWFoHj@k-8wE*g2Kav5CVBh=@?!2^1!SONmXBJxc1dmX@ zVf*Ky#Gi{kO5p|T*%w1-VSi3l*Wvyr2pTIwCZKk}D*oUW_yv?&T&*5fwjnBv=PgYqzRSV8;Ve9KpJu*x_J^3wX;627G zcOgn-f+xz?FYRNm44ayFyOdoxTK@S!Fg?LC?wLq<1G`o!93_&Zjzw7MUU zH8x7BX5yb4Q?8lyNtk5uv z>Nhe}P#sWO{itPB$=uSB?4p89fbVoAt9zbO?K9dTYCTWYu#A^u8lz@y9mBpx>*O8>*u~z=T8#yTPXoemq+j`Cy$r5_)kFDrQ8L}_W{ zg46}MPC*b-akz>oYjoy)*w(@w#~0EtNZ+2FQ7i|O>(wVIjk+$au$dmd0uz%^vB#Wq z^q@10Yv!I9(O~@AB%RodND4weot==`<)iZAh+fC~k({?b1q1tuJRjRlSL3kRlnCmk zMO@HV#o<(C{8k&1wo7_PZFi?25JWj+-61Pfqd$GY+{Wi|ZQ6IEzPMVg$ogBmzCnlu zEE>+l@d%LlW$f~hsQ-k?%$gT7v&r>f(z%&4zn9LSHOCOiFy)v_$!G!jg39oNRth~U z_;rnA!RMRL=;yUSlYt=`y+TvlrJGjR5!xepnO}P(hn{*WgLv`y*eF~!1{t;h`uN_q z7d){n=Ns4JXi~e0@5UQ6Dr3vt*(K%X-c)n*qKo}a$f&A17d*v(U~E-0nJ8tVQXQr@ z)^s+liTgF{h;SJAX_hVoI7D`VR%c)IsV|-dhW4;OPowZO+{j<*{>gm;H;2jfeCw!e zOVI$ZKmLq3E7JZolyI(4AjKp!5CsA=OIG`cN*Wq+cf5yN%!ZD3=R*A(rzf zL;Ygq8=J(--&VhR;{YY_Fc!x9&H(IVf8eOZZUKR(=#{~K1}IGQ^iMxba|53A-?aFy zuIRNWqrY1a$ZQL13T`wwo_dHi#bpzOUO{*sv&<272*u1Q6EyYJM(*G7p1%^>cE|I` zR@QCc%Y++uYRL4&!TXD)y2Nr{UIc7mT-@Bx55->(ZX~p~+g0>4e3u{zRsxxX);X=_ zV~X6mS=gh+B=B(rd}uP*xS|Pp7S@}<%Aor`0v2P8ZW(#^H+5)q#>~y7=o8Ph%is8I zqNdf2+Jzb|)KYxE}Br`M)O2l&JOwP9QN%< zv{s`Jz`K_C(!P?8{(7%BfLlA<`9-kMniVI;OYIN~su|v}8R}8-shy zVt~e22yUTgV9rXn5GRqu zLUTP30`w4ex`QK{k;8UQMGNfCKD6GA3}66v zIrhz!nCoa`8|}Vs02^z}%HAGlow zeQP`KuL(DfgM-e`PvMS|8=Zl75`RZv%YdF$!P(&JF~I#6;C>2le*?Hjh~MZ19{Iu+ z3eUAwu-a$L6?RDt^Uw$MCjJQkkYN^PlqQ1$~=;{?K{ba7zz9534JHE*mb+=EL z4L0e6)BKx<^S{F$E_Sr)9sB>kut%?FJ!SWzWvo(!!33pduO>?tHshB?7un|xZ$E_u zm+StCPHus1<@k%s=pFaf>sVu|3TqdcQzJnX#tuD%pC7=m>B%6qylSFYUapEd3=$9{cIOoa?EGYs_y25F_jQ z%im1$3Y(d?9|?QpV{++FqVbJc9D3yV^LyjiiXBqKy@TzhAz_b7d!W)4<2g5&z(a!A zuKz{ya#&vYHgG4Tu%~g!K`c~qe4(qA=yUhMOAV33{wUkTD7z|3!L#C}PqUJ+CMf;y zGlJX+DX;H;7QVe)poxCeC^`780AiZ8jEJ2B!9X6M1Gz8LXd3yRk)2^zmDw7~6pRjj6(3Mpz zr7FZ)vAw<$Iup|z#*?Y5(9tasiAKlZw*HRn7TbU&(b9Un+-1aV>fHGBzzet(hvj?i zcjRA&I)?3}Iwb#aiGSw3J4&=>Jt+9jlb&N|4x43+Uh;bR5N~U5G|AaQiJ>#B{Isp; z&%Q)a0#eyqk{}J$ij;k&!r&pi=m%=Grp%A~ogB2y_Zr}7BuF1ciiVN@T*9(jj7Y^<~bOJ8V)aS!t%c zllBO58i}Qd`K?PWj^|Zti`o`8EkW^MlL>$r%-zJ1t>$zg1{GeKXPN4UwP+;MKTs!s zwdi_UbB3;iiAuSZt&c%0dvz|f0t6@g2^|fwetUrAJ(x^sJ*KB{QEVOVV~Hz- z4Go#BL!C~jIq#_bx$Bt3)I0j8$cOZkQHi2%LSpsK;yx;d8|$YrCaeZZ~St%i7&^5OAF1Bo_>A(g^TJdKD=iG`pu&X)BM5L z-7HJw5AuwH4(T|l8v3ub`hj#S01D2i_YjWsGNCVTJbukf6=n~ehh==+cY5KA=3nM4fh z5T7AoSo$y2Bc4T_Cv9MZTJmb){F@OI1kK`?dVOhQ{&k(%8@y8aRZ2s5t63Xb`g*Ri zuMtwp%8tC&*r?voKY@D968`0%%n&oOmIuA?Bb zs?M*y#211$Yy|yLzQxjPQN#ct{>J5g=0mxpUca|sC)+W;mig~xUyjmht~iDSXy+9& z7gNysOk32aDt+!{YJ4F#bWbGAWH;0qbQUZl4mAN@^Hv6WPl)O znAeBMUBsULCbl!j8LJZz9vd82d8!O9zh`96Y+)Gkc2y~yNnD7W@+ziR96L3(kBqZZ z_pkhluSfRB$pbOb{532^cTrkeVjwWk;cuVHh+@5#8@0%}JgYqNiGk@NzsuiPEpd{k zVPIyh^R{JZq_9W8P-r)crWSZ|2I=%uTkZRud#%hv>%m?+sEWU0=ro5l8GA5v5oGNM zzHXa>%?A+9?H{CsPB*2Y)_S$NmM;pEW%nnA9}a5o1IoQ{M_8t*XkLn>1j?;N#GuxY z$A^7Pbbx;nwWmDw5u5UY==T48u^x3?&}+zumi0Ady$a`vnh6U?^W<*KMA`7NPts({ zySea)`lB;nhS~NSe(FS6$(8jpkMxAQXT#X-6f#U<_+08I_bhTnMD{Zixu`B{I!jXR}wQ7 zZAQj364=79W55-Bk&=CeeX0R)$go+@g00xiV1=#vc8!N`P|NA6vdZiQ@gI68F+wgg@HFNl4p+wBB{}#U=R5aNK@8rHhg63x5=< zoXq`zjuz%SKm<+~5y*d^GKp#Wujr0|gz4AI_-eQH+hgYSPafc_d-{!CxY-r8#baG` z>FH;oeEkVBjW!Fa3U1m3J~npo=YsKVLl+J&GbX+>7^k;Q7S=YQgbzrWu#nL+$OE^%W#s)gY&YbW5+!l%y=#M15{DF8ul|v-L z`}OBx3HSc1r#tiL**-rsGx`uy%GGX1ZA+!0ld}n`=Y)o7*v$sE|cF4;DFT z2D;#zu4~<7O#+ho>+az{!DorhtKc{*?U2WEZvObcEXlH%nA?Ou&O^JqezzJbktsSB zD@niTa#Tu_h3sqileZC!nZFM6RktEFv=HdI!vA`8njgy&P5a_z>vBNKt_vfn1X@IT zfI~*ej(yM6RXDlV8sLg}5!VPe0%Jh}c3;0?z-qu;-HC3+s7$``7T51JWP`wM6>TIqYO zwy@O{9AZ3^%MB`fG?=*kFd}-1H@wn&wq}0|ZF+ob`qm9kibkzD0RGIf5lrPTm+#22 zxffYjW?U=w!WutdqIN^)VZC(`0`@qle8APeGw35Nd83SnJ*`2}mQdQyw>y@x3aTFb z7Et($G5FncioFw}rd~?`%Ql+Ww_q9oHrGeJuD2XB8IP7VpS^3mIJx`cX}$Wnkdc(t z@zuQ4uNQD*r@Sc?EvEq(uRV*#m_CwwHk1tOw%_-6kZ=4HjSoV<$4KG8+D4fl0MMW{ zug5HR69LTMqW8>3g0wY&5MLfwC9 zuQB~47fqfBpSUfCY~GFnHzgb=(dX*~1@6+_rI;)566bt=F&kW4Jv?&#?cD4N&cgr8@Ouu5hwb^1v@vzQTtoV~R>?d57eGpX<@CURSWbY3}Le^O=zhUqc1&6B8 zi?k<43YAum%Osb|K$@D1Cl82#yVjL}lE4l^L`rpQ^HIpd)bm>6Wj<_3BFp*{;@fc8banz z$4^s2sTT<%ba|Uu@3()LMx{vyW{9Z<@4@V-74CvRY!TnTCvxHAtsC-VO%S;)sZ_Os zjox&T`e&q!NI(UTbx8KLc5ieLp0svV^Oa>3zs*i{&W>V_VXP{~dZs@^K*mtkP3Cxt zW%g1@V|uE_@$LyyRa)Vz;D40-Z`#jw)n>`Q@L8$yvP z>mEMaLU%j{2fVFb@#7rU4X|3Ax4e>%hpNP zr&^Ayxo4ySr(Hjm3|RqcZF+E&KeTBopH05hPc#z86S@<@GxEfNhDZ z70P93V~Ul=`JA%}DcI0vZ2V(F!X2%a42g>^|i77?T{CGUr%pXwZYhJSM6z4qCk?I@~=&@KqxPr_;~53XQhlS=`z~TwIqt zwRL9gnq1MoYsAoj_xs+rIoX;1*Dmm!KaXVKECkO{uxp3p9@cFyHck9}k@!#rz<6a~ zkPV(Orf9eL6q_*uoHuXNjMyTzuOq$gtNL5G*0|qLJPRu6%ga^ja{Z`)3|FgAvh8RyuNf*VcC%tw(Z)x|$Kp;~SVw7Bu~R$Lr#Vde72C z3UvD`B)U*flF%+uuxLVH=gzEox@s}tFPwiD)_Mt;lrcWB=_z9-ti84tU<=^Q)A6?b z?ak^!=0_FL?;%juPY_jc4 zNH!|m2y(5xYV4jYY+{Ct-+&VrM<1^NyvECH5j1D-28hLNhy$t`N?%HLm!4E#!`zDP z_P8zt)rLon&Y3HRKQ=ZLzI>rAhiJPSz4w5O-GD#gUSS81~;y*2i6N7dAQ#&ktnL^ z3NL{2SC+Ba;s42K-0kqZfsHLg#1S`7vL@{hr}wtrOE>bz<2p#uV=iR3LMPq@T! zTH^`$amaVPL?NV9EFcqBI}UW)>{K#tPB!?n`Y=c#r85oE$K4FTegDOC!}AW|(s3Tj zvB6?DakHZ_Bsg9Y*rU-iG+AZl|Je*mSGZzx}{U)oMrxq;LY)0gNZl$}H0TU0G3DkN9ENd_1T z)?9Oh9=B%dJlaGArXF8#?RIz|TkYw#yXNuI**Xb=_eNzS){$J&#}=?7`CxB$ms-NL zCVJ5n%EpzlW@;yN`zm`xcrY5mS#4K@%0&Ud8a`MiB+J7bPW8{XN!kwnEO&cbF*Nc$ z4cf$^0_Xa_+mZh}?P2)8(H=qn&>k`WEA8QbN&;&K{kT(aYL-o<1mph{ zDNTvSzh4>7Qnc6Vg+K|B0`DJW>~n>RVp55luj_fr_IYOS>UXXiA3$&;-;O1H$Fd-eO4>=WPmZjmc!J{ z4mQ`L-tZl_KR+#Av12X}Um2nE!=#7bStMeI&dcpFMH0DQX6D;%yBt>=<+oKsTIDqE31C%4K+U>+!S2-KM1~gV%J#HhGE46eeiDEGP#l{(;yw$Fy<#6N3!@U&v-qoD}|Obsd}ya~7yNZI3dHyvfk6DfNPiYIaGU9zzE zxw8Xxs#eX#LFoHo0@^+3(=qt%hX$GZ!kKo4QNHSB9>YDB-a2AfeY^!l+}+NY``br< zTFvio_?o=->z?3lb@&KLpLLo@!#v+oVK=Omm@yxNQ_EMMo6SWI&|Mt4dldAyb(u;h zzcadvc-*V*3DZr)TR1&iaacQz%I^@`^C4~^n;h%f-K7&1jFFZ&SLv*Oqv@(eIUX0K z6*7*I3H=$^7P^Olvcl|AQZSD*XdWj3a-vAM(zn>3LI3`DF0dXMsogL2?h*pq==s%C zwEc-<*^`nN^+GUqsio>zd+~kLywN!^y7kpEZP4<_r7En~oFJ=>W=NePDsziWD{7*w zs;u9p>ipW|E{k37GF=<}Q20gq)7lwf@DH`mrD~u5F8)yVa|Q`azU+ST_V@{ObOVev zI7HB-fu2=#W~h8q36uuNiaC(!@GEf_j&=}W$~V@S?GZ-wn~wSM_OlA%*57&j;1f#q zI0Y*<-Rbu8{ASje85ZI+)*ne^2>($O>1#gjS5U2)&l~&0#u)SDVjsn z?!PeslZ1J1FuTdwuWJ#|Kb3i)Pdr?&Nk8Xm57w+k^yv@#NbsdxGwdW*84Vv+?p1^o zj^}@}kyHXOeD%Nn7Dx7qM_d9ct<2-9{t=m}M0c=)x;~7hMv8FKgV#4QfC7EHwsIie zKj|-(&R3Pm=&PKb8)~jtCHe0o0c5O36jOfqee5o_e80tYzY#J!C)fbUlSQps9hgVN zVzI2q`s7Pkw)q^r7Wthgn`5tN2a`-k>}6XH{rj)58>4sv2qn9JzGI@|mSa;OvK`9! z;x@neXI~)5nJaY5E@v!$~r;`CL44Te<{tLWsUm&&u@y?Ar( zKdJ^fMah~RfZ~a9rp~+l> zM2ZPhjLfOV%2(OVi6JZc6S<8VnnP=H8^km~$;ZWWi&abyrAd>L-}v4(;BKNSpDLvN#qrn*U#ge*%}yUJWrX5Vy|NO#4!bU)~l?#4yk_k zuWnK(%8x|G#x2Wb#=5x^2Zg*x+joLrv<9IdHegRupY*L(K6JGV)Wn~L74iw~R9mWG!;)bk8jCDG`i#iUZV zdMx30e}-tMge&D)K;n|YpJhv@2MXqmtEgB_Qe}J`FbcB_4K(*Dl13gqKQM}tr`dJ);eV+V1ygH;1!Wi zis)M0KJQ}TVvmnVciP6N-RQ{KH9>3^cCHW6Rb2Hxo#UIkGxW6buw_b{x`cgCWjAPq z#2kJ=CC#zE3&R>Yvj z1Kj$|yrDiww~g;XMq4TztM*NPCv+_cr~8XSdGZ>PuPw1mDd6?1!mWyaz zmjohAfFby?%CV=J!s@#PWVv&{j8`;T!wB4dcBc{;P+7}C$@%~nRwR79(gM@OYz;a| zGV9e3wDtfredIVz2_fAxVltSHDvKe8skrU0$~`eAw&`y;uS7e%>ldqyvZo2aF23YR z^&AD1|I!}iMu&&!`%0s;dV98}|Ii)||I!|d>0HfS|Ii-8|I!{G(uV$_JxE7K9+0#L zq==cjLb3w4!O0~hxKLp9hk(9=`L3O>L&V8{Xb*8D?XkcAFYQtJAKD{RpzaFt!0CdN z6wqhX-!uX81?*Lb?1V{mAOE2}9RFY1qtoaO5!cFQyFU;y?@EK&$QI5J9By zJ1}U5W;oCtO(Bh?Xb( z=yHDqA@J=$a8KDj>~BrMC^EOr?oDoH;0o^0eSYu59+LJbXPp@-_!E!`GMNbo z5F(Z2m{$8v-p)q?ajY%=!Oz-0owrdx&Gv{m?jkE3dEI!+(Y$2QXttHqjmMe^p2(di z2c6c4a2@u4XYP_j41ZtJRJA;kSDE~tFG5Gv9uIfu4f!#V1D7=9A? z`2(~V2hhzq3Ml8aH#rVp{M+&U#*f;*`ykw|7UvPM|13nAlxVf%d)vRX$J?|2llBn& z|DZkYk+g?oIHJ=0GBI>Il72;M{)jiaptIpNC^Sx@4kW_o6)Z2cKE(U%)c$y~PV0Zr z9^r5Pi}pC4&Tp=*^l9nO$BBW&ehJxo*?1pPt9DR%m)=^oX|A%DM3y@~5{xo8Lc$g* zs`=Qm8(64oMY_U=l$h!n@zw{91s<_3W@e8ghB`Mf*J-)}yZ!cotK+q{sluiblVbbk zwgK#(x-AOa4Ptmky#-@Fa0#>E&hW?Cpn4i(n+*v_ZM9Elc=|Nwmaf4xa_}}!HfIMV zuhTb}$7KFgdq>F|yShI)KalvtTcE?t6m@2Yb6};jM)HvNvKrqsA68SV|U@4^31d-oaCRQEQFUI78=iu5L+ASk`p2ndK$L_|7B@4c5K^dePJdJ*Zp z_ud5p0fEp77$x)op+mwO@BjUrc|N=!&dixJbDlHrOx8?h@14EY+S#*qy{=!qxNGyY z_`Bxan=y6eJX@O6<37n!&yAIei`9e-a4WCk%UjHPAloWYN3q;ZZE_ z+1B?%(c-t=32Net7T9jWaq|KJ|>e{qldINalluE?(* zqu<)4zqIei(Z51N>M54==HES5< z;E07T8N$u3;7#Smi7&|X0ihv$+1F-+<&d+9|Au>52~;krCxA5=qoWuEk8oiCga6_l zl0+k|befE1&JL#NU6E@P3Mf|WA2}81cB*Foh6cd=g>ZtZKCU=&ZB5^=Hbm%!2hc}Y z$wo!o?-Mgq;~ZUDQ}_9FQxVXw5JU98dwl)>8t&ouKMVI@nGB#Omc^(>AI`qG4s+uf z1SoQh0M2E^(j@nMJFuD=fnZFLP?tGk374hurRb9sJZrdF?UKsCzRIr6J|sru$^~G{Q{* z%t*%RI@5VI(jW%PZprbL8S)inNM$0Fm`$VLu72cQxARdye|>_xTilKXF6=rHc~0Ba z4n%|9@>y4W?41dk!%bj0n#0|iYl`b1JD+a!&5^tAeuS1N{aNZ9_WEPg!jBs75Mo|Y zHq8vs2L6tBZF5-(VjEX=2^2owzQ;1_YAjjZm9pL-6g0T;nZmq_4AAWmy=aui$?6;z zi7p|xBp(ixKzwrCNKi%cL-<_h6J!n9`h9b3ZG@P#^q0O;+hE0PSi_PvRzVc)tg=z- znM1~a*PBTRJ2_I_SkSQzEBQ)HE38cd2JKs(3v$~TopU#9b`reV?NW&{or{Kz%bEGl zSnB1M$feahO~+t7=~%9_I`$=ZkU`AkIbH&YMHZHcsNGqwdA}=zp6(OZVoqtGZWQVd z27H-2P&QK4arl8sd5=9aVS8F{!QJW7LC_Aa-IAo@`>oo!!d*I>LbaOA1vP}J>Yjm1 z%&6bcliLO@q)*5;KnnY{vNxruec6(oVkHq}ikRFypDI&Z= zwq98(DOB)s3KiMhhGhjl&MFcp1UPS`gIbE7 z27H8^=YsUvA;yi7NJ;5jJU|=$hU3GqAdDnnM`JjjNgpuDae%hX&&8}rg|)kr^P6`` z3KN@I@ssvg5xpOv_(oNldss#dIJ=X#&{*gg&6;eLkS6qqAGQGj*>Xem%i!W7EpSqEuLfb*E$(qq=@%n-WUQ4-5S`eOVn4fT!L zJ$su%eUD6+l93eL`c`u(Rbp)#)naU2Q&tn`g$rpGd~L?C`k>`=SPN#=GP%9!Dc9j8 zs~h+3D4iiZB7gV?kA*7pM;7fK3OI8Zz07az-GkI&%@W%sE}u#Ed4)T>Ne;Uu4!cRI zgA`G>h33~=;#fM^WLkn*PUwBIUhS5o4kbJ{wv4jW?n{s*lc@`4DJGFopz+DNA>VcT zJ{+Bd=TpMOA1dd`XXPR;-fL+|{T47UC*J!yF+MpVewux2o&X|e#X?Nx!hyan^vCjo zvD%SL9r2k@dgFuKm&1iz6ysh-G9i=vX_xS|udfeb8ML}?_bTkQ>x$M>O{ZTvQBvto zzih%~|HX=Z+bA<=SRKExy-17EfV{YCGkHU36HR<~p1>NC)VU)PBV?J=Js*=^5*h_c zybp;^ZN3woV^81|LMC!82syyBX*!o5CMz8x0~}|u@sNIaP+Pe<% z#CP{XBM0KfdE(+PBLQzZ#1Wprn{3iZhsp&*hd}*A?caSIEJK#}eB7SXOzpMIu-aul zf3T!oy0YLvSLmbbVm5BLaZT2F72n(MOy+9bVuoOQvK+?X+Uk<7l@;{;x6Y&7x<+9H zsyB?$RDILcyYwAB?8I}X3pJ9~%6Z1?;mRE!au#(;7eIYxQ4-)cCu9)Vd6wruZb!yN z=iH;QOj#Lq@+RGK*!34G<&68?ECL&KJpOy<+{J@QgK^O;aJ@BoU+~0JldIab8tFAz z(vFf9@1$=z(S9eD8#_0)Y$u;#;#D9?-Spu1bc>pY@vb^#k5d z7e!s!Rf6x?U;)mZH!9=C8F`CsbDxnqKDITlI11b=ZVeN^R=71hnNaV;+8nF-#!1zn zJ=n)~J?f9or^fu2><5>wC-0A#YukM}PmM&arZW}#;~TR3^)BQd?f8^)CI4qTc%ckE z+d@z8J`3LR{JieUyIbZ*_L)9BX3ozAk$4%5x8D)FY8CCvqT^eCN*MzWbmYtEus5zz zSYlS?R!U>ddzCl~U(t%>K6yNT#iqIcy}C!OIX*x*aeO(we>ue8Q_fG$wIkmfh4)4{ zqfPtgoF+f7u`8{fTJ7y_5y$9h1>&=PyI! zwJJq7%w@Tc7ZVkko#Or9q=~4tGoY=;Ck^xc_-L<)ECJEAY`^DIg-&CJ;t@&1wF0=? zyfZ143>B@5&<~OnwNKP91fEM)+>=)NbDGAcoYWZW(O$nmfk<`OB$l*N791vS`AjwJ zW*uAguX~}_P-w}!nl=PA{(0$oCvHn}^!KQ@YVsxwlfO>>(>5`xGkdsTk1et@;A^GV zR2o@_`0HF>ap;;pdS&DQ6k{*92lkU-!2h1V6u>zY1Qb?>Mf!WmwE|bt`W1D+$Uc8u zo`*6(-_^p2O4XPOnwZK23QL(8Qh0K!mn#X>^5mKUj9NCcoKRG!%k%Q%rg~W<^iXiV z3)n*fHeq5q&H;DZNORpb&P*h71G&qJPC(rgKNt;unE^ zV7a(a_Sk$5$FuK#wWC!s@lU;tgf9k0xL?UfV4b}6q?`7vp(-PA;h=5Fnz0Ys9gHjD zx85BmDzw2)xBaf@rQPdK_oFT~WylXC?aj#a+pys$S$dyQ`&%P*IL5?Zgjs99OC^59 zxd~QKt0SkkF;`6_XtpW@?Q|oW)|M#KTihDl$yPn+Q9%cMBw~@#5>*QhX~eH#=$}uJ zu+(s`adZ0-5k4sP!wIg_aajaotEmN>$4{cU1raH6v6e%F$j=`p^AhrfI%-u)9w6+m zh8PvznrZxHJ`Tp=sW9Tn+`%197=iuV$Kpzwx9w%ehWAE)8LmH^H2EC<0oeb-->cFM zVt5-72?`umnT{r3$sBsFq7J3xh`?j12xUQYGTk(==*EE;yMzGYFd#_s7Df0a*yKm06q zBw4rzUlb10T;L@X*x@!gACh#8GVuJiIx1l@?^qa+q#VkL8DK*YS?q$-7jIg*2JVa( zHyW1R^>vU2%z2e+&dY1^M_1=dF1Raq1}g}BdviZVMlr-Ej8Wf6#Xa(!0UEXzrv1ZwVLKS637qheXI2`qs_5w^_$RMG--9$S^0XeRB4<0wV zs*xBU^R3_c+4b1A8q6q^bzaPg0Laf_EkAF(>~(eD&gE}F&vzT!sTTU&-qX}~!i~KI z7@0?oiJ0lBA~55yJkRiD@y#wH-YIJZ`@u7`7(qXy$G1chsM~_-*ZK56LRuD#^iE9l z<$Hg>*|)QzMa7k&_m(=@RVz!^1Wf$XTC?}B^zr3_60b`?_0T;;svF;Pv?35No0mvmZaR+)Acw0x-9(c0NgcI%mnp$0TTP zOUT0ad?8E!Wqf$K7Z+(Ihs`o7DumM4yzwDieaJWyu1qS{LnkjxP< zmiF`PIGZT{*^-})a2fW8N)j#n{UrBEq7KEJFPTLu6QRDB%)WM*Z27_!`4H#aw_ogt zcRa7_rIVO)IfFZ?3#8w4=ekFu(mk8@xO-|Rw2m*Da-R=LcTXnxYz1{!phfmt(yKR8 z(X-;B1;#&g<#Q_mTmBiJ@tf4U^4GrcguT-tQKvJu(C>~QW{p*Tj2%)%8!$gen&Em0 zJ1yY*u_y}Yd6(c-RSeRj-W>>*9GH*6UzkS8*IgW^w8kq`JWh5DEKB)vBw;#yBv60P z-{e=-b)M6U@6Ipk>^T{4*i)V}vXisc-_zzfZFve6+k6=Hnf}H=-s5QXb)E(!@Do!g zd6Eao-K;P8g!_BfCw!R`Ay2>03#6GW>G#n^sii{ksmy-w$kNJO3$vx5{_@N`R#*MOWq{P`eU)ngCf6DX z_v|q?r;aecj<8>TV_`!^*g*sa?>y2B>wUgK2tOZYbXDCx^jTZTJQLVJi-(~_c+w|! zi1QjbmA-WDpidlkFx(Y}iyOJ%{5`t~uA`JKgroete!y;sFXj=dWfuKu-FNC}yp3}B zV3+PeGfNX9BVFkrhu@M);^R8t+friga*bcP=fSa%6K)}h|`s(g)lkikQR*|jPW0_A0V!R;k zUnoCZuyn^<-ANZR2TDzjB(9u#oVLYy)_Ha=o6&yQo}&57_x{`JrzrEzNk_a_JKr9L zgm*=q?a&u{eAem5XO&idWAc`^+cgh*4Px%!zb(Mj|rMD6W;GL zvxB~LVk^vKcCyzJ8$sa63C#dZB4%-9SN%AU?FuNlaSar(2&*MR##KK~YP>SInZ`{h z2Z#n5?Tl>%qL(%*Zsh$>fduf!KC|{^-R?W0Hxz^Lm|woK*n}S6T1+;9JTzOi_7cmhzeRQ&V(&d`%_1C8te8PtEA39%GtQi|3Od{nX4{V8s${y=UO7ROq z(f2c(-ZbYmXbeCv-yWy+lSNrj(4heSFPKmePu0in5Qj@bL*UG+3&lgveMxNVq zedqPD@qoL#?94m&YIwXmdW-ptIY)$|GcCU)T2$is=-`sJOb=a(aRbZN_wR+d1r3=8)KZG%^#$!h#iL zODLS%YdNRrd&f1!xDef=K*&&=z%~cB-rqw$;8zK@1ujDcKG`ooP1$sN;~fK! zOn+Xszq^vyN}Z-QG+V8PYPRvA12=2^S1y~R?SEc&Z;zd4xy?vyCRc5bO<#`Cp;x>e zJ5Lv`Xxp*5I?96^zNl%G&qZu(x3Zk}CChbSG1T0|)dUy5dIMg|3+6Go)aaZOMqZxo zg1UI$tBE;?HAjjm$SAs@WfT8yW#t(-QsF=M+iv1hT>Z9?C^)Q-Quz9 z!trd!;f~d0k+&-&xw^*tmR2Y7R{J;(X_o5(XywH&&alT;6+3PPFd}`Oq&pckWyNC% z$)y?RxKWYQQ{}$hg}{~g@tC2h!RPSY(Z6J_&vz=Qr%@xNQw~WaU*MhhQeEGH5y~;Fx??lgwKdS#GXd7Owuj3bX zs5_HD7zt>ru1gC6B`T*{kY-8R90ap9D1FMvqI@j)%JK!@WiYhsBjsZA@j<-&%g9E| z%Kt;oBj$e~=MmZ@pO(fF=+`60V{2NTIx8n8CGkk~B#sQ0VdlMOYl4O$+wg>Z8eIQO z*GRDSEuOs!PA9){v1c2x&ZFJpjX^nFJ9dLm9`>+^*CQ#0fLxHh1Dl?)Ude2yl|yF zsAL5nLVm+i9PgA(oU4X{Cu~Y!Wn+sLq;Q^gK?qIY-{Ia#u0NOdLDK%NMc81*wh~%u z*Jt-vuxal8%pG!wwXZ|HfmY;bRyI!5n$Xc{g3>6$NtVT=C79jd9`&3fTt_M?Y9sp@ zRh;o-Z(X)NB3iD-nOCiz=Xob5VRq?hi}=6~jkx<+#XDr*BNC%IvCpt?J_0bBE*}9v zjn_VkdFKXJ8@jrCBwMZ5I*NN~(OCXj;AKVy#(oc) zUk{KPuEmtX?`hX!)Rcy2%Aa*P9=T~4;eqeqiAsfLBxZfaPB$8d)JXb&$L_dp1Guq4Mj*QVqok1y&WlrROzl_L0uu3=X}_$d>F?Svdci7RXd z?Z_((A=7nX>z=TQD}SoY-fKh{=I3(EIEmTf`y5Ll=pWKbiT2_pDSjBZey{uDt%Rdd z9drWQ>G7GFt;Zx-is~W7FX^3(xt{@3gNv4nH$QpL%^r}3)Ek=S5y~qnCKX^E_jW24 zrmud!+2E7z`mGr(#(j#+9X&(~@KK9&L$=eX+ju{8H)WaNFcTBra!kdkjPzbHyj!`X zUt8ho-U~WKI*&PN{z|#d7{J@1+zDkx{cv3Be%_(nO=7gmi%5XQf3nc)5Q3HAqyPeN zM;rh-cz}GjmS}{NVsHo6Ji_s4bxNm{8s4kvhUoe2%B85I5lmp_sANJ>hY#$Ei z*8CL!6tCUG0H!@`!nIMqJ6pHs@kcEv&6xv#2wrhpP_8>5FyoI-gPnGJhgcK%PH(l4 zdhIH3Hx$(pK@?xnCcH%J^IB52z zFxEx4H5suGW@uTOarJw*g9f!8!R;Qj-rA806PrY7B*0Sq4ow_;p-e1DUywoRr@~Tjf%ny3{>UOD zaTgX8QkMaB=t4{fk=TzH3-a2@*O{R|)othqvJ`v}j_a;I^WFC@uGWcz;M zr-qgi_f|PWaP(@o6K~@Nr?Nu zrT7Cy*?wkJzl%D((;`r@CZCD0XhqSt3XHhBlSuIkomroVm$y*P85)=t#hrZ)s@k9S zHn9F;-_@{DG8HucFD$~&I*=jo{LVNxU4&t$ZiZG9$%+0?jCjrtDsG2$_=1mT!_y3R zEUoRD;5_ywHw{|Zm5UR&&xBz9VzkVL5EJx znE>;YrTerVMp;S?Ir*MOxKvRHOcyo|hM+N|tQ!7@)6m?x6D*Z~()VyKAYrlmBslh+ z!p^7EsQ{~Hn5UCz>}-H)@kw-5_UkvQv`2m0^X3s^`iOzHiOL8WhyAtjOF z4$aOV>8M@3aLY<$JV%(^-T8iYcI(yH#VbFQWGCjVr^M2@n8JGzySxMI&0>FtShrV&=Izrf^4%$Xy`zEtDG+4!=kLT0g zMr&?S*Z$XeLEVJmp4X+5e`%ic1MY&M+^Wn>gur}a_qRB}p~pEj%{l2a+~FpH3M@Os zCa?xw=r;SPGsFgOH5;uz(5p53RCh!|Ytq4Z#d+hC$Sy?1@^eay$42*6uh3wCfV z2tP**-Sm-S=^7t4w49Ah%!dVhc(htA@al}=NQpqyaK5^FC6*$lRdwH93EBR_e^tH1 z%!b%+VyEQ^(^Y+KcYZ8}rw=jDCNSf!9i%<*R(aWE+^>?x`f661bUnW&42^NfukJi$ zzp%kQO%w|he__B!*WaxeEx1yzu+Tx5dFB!BFYstAkUgS-ur4gcLUE@4s;G7j$OwF|P0D-x%9Spx+B3tCp+st{&~ynp$o9jeeBQncoJK z-z2=bVgGJ{DJBs!`Lb*@tn*mRWdD0X0yqEMVNe3`L9>k1->+Zx4PU0STGlH;DbBDj7r$Co#jX40oim<) zM_jy4J+Ddjk{;l1!F^7Kv(mqgNN4OnAcy?E&ZFp7fhWH^k}!dEpS)1t?ao$}p&RnW zp;s;cLL+K&CLE;8+!P4;Pwr+1ipzBG+;aZ`Mu=MzlLa@rYToQbd{a)EQ!o3~)dG9{ z&S2+{!8z&EgQ$P^GtEdqaWJ5xxr%>{lJ0<;9Q(yj9J|rE`3Zw_pq`y3PzJtLiWocq+Lz>S+x(-`@qO0y+9~e$)>4cg`aypFR6PiPJUS+&NVo`e!ah zAaB2EFMK3SsfO-B4Yw&?;CH;hkbmV3NDUor4U#!jt~gi@dw;%swf~0&)B<&06ZIgW zHi{G_et-$2KlGx^FY%zv=eA6I_d&~G*I<{0{q$v|+}j>jDT2U)V7Zg~^Ex#1od0n? zIv@6%vNtEAm1>4b=RI-NY2G<)`A>C}PajxPuH&5!u+LN9*}WqW(zy+c`?rs>e}5H$ zg5#VVH<#EUQ+i7Qb;lpS{rUc`bvR0n8#li?0`W0x+vZ*%SM{I$EbA-Ed+?Fdi6E!$ znq!I2$~0m|ti2hPGB+%s+Q+*92GtjUR zTYzgOM||LB)Zij%Z)=FdOsc3rte=v=BE(A+N1DDcA+YEIf_h>F^ zk*|)zN3t3!KK8;r)pdV44$hxe%*hmZ6`w-6%F9yg@rQqW-TO z`Cbp^GUCdEwD`PAxRhGCNOOxv`bab)|BDjoO;~MKmAa$xzR?vL$rXFHr*`~R_Ia}N zEF>RU*JnBaGi^BiH8mgmwshX~T|~y??+)Oc&z))e(B%18zv|8wgUp={4y4k27Uh`r z@Syc8WKfCX1d+5T5t9mF zTt4pU`%C|LAHV7*-3;{C>dJuL;w=y!4+b!6>LCfg=d)A;ei=r7rO}vH2+s_yg6I2wI8~|DOQxAnxrJ(D=#i3&@|I8h*zC9EGmFWEAJ7leUwd&-S{=~!JK$f4Bw?$o_ zzuwqK)Objj%G2OY$?ecdcH_uVV_NyYm4hDQ%!1b4`4)(f@y3IeXXBXXdG`x4#@vM1 z0ERz`ktAcph5m6H#{Qj@R%m)>R>ahAp-6+y#F{rK{3*9}f|ouI?tS%-E73yy@^MjJPA`+EjW_G*oK4f|UsU8TyK&nGck<%^{!nv+ z#}ld@Wk)QsM_zl3CXkILH^lh`V9=iGIxF@;8kGaVy0}`Qc5@K zhCM1niHb0B5oZQDy7&Zq1ST{%bOY^75q%=Unw)!YiM23X&cz{|=}3?1d+A>`Jk4g0TOal!rQ-Upr;TEYa#Ne(L3cJ-GEEb7%If!)&3`F{Mgl+cLwx z`-pdL$p)k3IRBS{AjV3>5ab zz1~dSR&fPFF@h(7r&WKV9N1nX@HRdy(^ZyV1~_+_bsb`^9R1%C@%+@S=ficJ`&QrtsmrU1k>NK#v>_y38&_U_W-`C>Q7xZ+$7dP3C&opoe?IgHbeo`JOkt z7cwX9^nk%k3z5Lu0aJG!>H#8n+}JV$5lkE6Ds+PSUT&slrvC5s{ zJ8haN&!uyfCMF<(0v@nAEZMnJx|XcbnF?}<4rfE&5vF2!^d`&JJ5qxJT%8DjU1AKX zX~2DQ$DchlZA~?xe{u+TKK5e2jBdT;kGTNq1gOF9OFoEtlqj-hP%m-v*>TWIS@5pT z&8CpWSuXa7;H;Wq&1JzP{lX|M`9$|4JYK3RB5?*uYZC9mL_L=eCfjBtqCa~V+DayI zSHO5B;k(+3m|suBS?{p{3RqHS%M>=E95~Vh3#ZpQ<8}iwoO18Q-d-}+3c6H*56j6J zz;K~k7w=9OZv!)Tcq+8E&^cC9ajwWKb;NvD2h7H+(T~`D zc>iSpVNmg&&YDVvn90+NaPZZ%wQE6bb&W^Mgvh6GE@tUM&JMTt7bpF#nK`@Ga}l&p z3lJaEU5jIMuD2N#YMx1!#GH3Lk@0Z(b_l9l-9s1t+HW3tPMkQOAd^y%_Dp<~%{4z1%~^h!&5e zO{*KTavqm-bB|ujNuHfOyvBVsJpC!DQN&(r)efwkvh14wacRLP4u0Xp5hrs$z0%vm zNq&}&=__uY4z7p*YlZ%r9MmkOd$lIm`Au!GlNF{G#&(6cu)Lj{cRCz-TNpQa0XzQ$ zJ*)yf`lm2HyL|kNkuRo*vp*&iXLPvd;;@i9821(DrB(LxZiy!$=&S*5COIfK6AiF# zY8qGSgX$P#LHAue+>~02&rA;mb$Lf9uZ)YTfmiJ zf%4i-*AGI|MOk0nTl*!L4B!=me-b~w<`Cr%36NGqc*wVS7gsOrc~KaTagkD>AN&ye zHUXmG!!`|Z8Kw?N1`#A8PJ{W@q)5iWZ|N}$`^xyPkP_o_7M@@FfB3QCH}&apdy5wj z)b~o8iQiL1b>ZEY9IEQvBj11k<*b|0TLYE`puN*G@nP6vJD{sG7N2IRorLodc&Its ziS>1Xe^M+3UEX#wIX}75c;UJOug^0%8H9<_OGynOo9 zb}3rAAZ-Ic4D>E)*Om#+P=sNgZUsL3bjWa(TkiIF{}$sTq)aWvm}~Omtcx2y zRAd9I%RyBR-Hn!?L`75-njf;BzivX~u&Vp*r`0Fl!>lQ{5G$g+xGDPU$j=d_Y<_O9 zUCp2-MYY2H%52n&ajjOZDx!*{TVX7WHbPnb*Zpd{Tqsqiv-)XJ$`5#tg9CumDd<(+ zmlFD=5g6By8};k|&oCauZy-(;+`XENJ3Jo0%$Rq0%+a;_TJDt>?ZW|hf_&Z;Q3MJ| z+ecHkeCzz%sowPj&4JinC>!8&pNln}6cN&*KPSE_l;>rCL4OtTN6Nw%rLx;>M-039 zwyrWc9D1(r_2oexRiNL(LL57d--3agSt=XvaeZ>?r*&)QvdRwNBd_uAU%O78nYBR1 zEMik5{#cKV0SE=6q;Gh32`n;GFZ%8Yiyo%jl8Z?7k4X*Nn}0J@JgL$kVrVHs=5yqs zkSxC0GwV0VSRFzf|DJU%OD2Eo4bs@{Zj_aKAxnV4rr-VV@}V@2oHXylu%jqM$H(pKj|5E4 zqeb7q5%`zQU#g*8Z@~_7ISW0p;wCiJx|ZsvTqy$1n!j#5yF`D4-i&F|e@_$8Fkv5; zbK2HmHqlFby-v`(+A&aW6p+7zeC+-;>_A*Hap;SGY=S^UkMIeNs*_-(ZTqdN`)wR= zt@*(l)RCSRT1f4xx}90+<5#C2=f1cvYoK1uv5Oq?4si{aDf+1xpEZBDvz<>vANHXARcod8TfOKX~SAu*l<1Mo;A7^c#$cXnOCiZ>9s%r`MO7}LO zW`S)_N@nu`1e9ToB(l$H=6|mj4}#vZs#vpb@PG;NM#xz=xY&feNZj*Yv2rb8tYp>2 zuS!9=x7@Z<-7>nh9^(A2ZfO*6W93xP(y9tf%Ly|8h}@qI6njZ=K#uS|6qY$GbB8f@8rFwNDibVyeyDs<{`E{lS6B;`>kiiTt2lr*5JzhqXEfGQ&9T z#PZ94JI($Re*aq9xS>|#yEC7pB^aHLYUg{0`;Kb=AlO0^{Yx&=5N^qdxwL4ti!`Y3 z9C!r2H*&7uY)%GA8xCu_knCiAL+KJEJCQIasks#8#OU0N`u&H#8g#chGS%Bm_b}&J zHtz6Qq|xQRB<6!SH^TKxa^9`JB36#;J=?e`0xa*Q;-_Hd%c{v2NTvPqrRuWta$l3JY_t7#<1$-O6kZqY-XVWC;)EG}DM` zs814J5wJfwT;2WJP+(@*J!d0rV|lKNu>f((e0a3OMj*cVh~xqs@k+?Z8hvk$FcXMb)duouedIg8KeGM=&vr+I=iK~Pu!$J}({U%$tM330`wp!)_lxE|o*Gr8i<_`RPX65x{`!wsY z$N1K(G^NiPQb>5b?)LUPKz%{SkbRv<5iK9TwW@aVqvEMLPu?V=y4b6tc@N-rtnk|Jr-(7(9-knpWx!IX{}HP>K=l_7KlyqmSan$8I;4F6tJx*<(E zzI`T4itidM{3z+&7x5P|L8Kl${k+9!57!zp zix?2C+}pOrkiO>^!Y8$wk^zfPE58{K|GX5A4r4#=QIlJ1TxVZn53$WmH7WGj+-RzDw^FE}ChePRUS4 zna7Kp?vWwPMm6^p1+BK45~nED*u7lC-CtT}W%RP?1Uj8)mQzw+h`{n;k<3Mb+5>eV zqIVQ>Q)-@6AfEf^z5UINrlEODX@i`o#q0~Fptf~(fgWfOyG2A(QqGJ$zX$C0b-Tf^ zeU0c|>*gPxjn9c*o@acmQ_Z=L^&-gmTv3B8bl_RfZhzINNw-}65um}@z;EIb5zPh&p>4y<+FXM z^vO>paZu(BmwFzot7%TWY+&>=^_0QT$p?&0H-6#0UrQPuzU7JAW~cG7wiV;=TaW7B zH?7e=^>l>xV@`cb{1Ki{UT_(jwO;gflEcRtuLDV9TpSSs=a;IIQzN2&cfh^Xqj#V= zGu+P@>!mH8mC+$K1xdEKMV=2h5IVW7*!F%G)}D*wKEUqpuoz=OSBDQ<%e%VfTn}<1 z-qL#NLrF4hDu%s;q|fA!%+t`K4e4D}5BqmUtbOC^cy;*Jd|gF@q@&b7cmQKyYxcV7 z_x#j^ualTL&5qa)BlEjSJgY)X;Dklp(L=hv_nDq|d|{iqv5vcccxJYVFNLpQ+xAAd zxU_n$n+*)OCbzWLS_@xKb`(!oY$l5BH&jt}PjMhMHW9JWpG?#T8!LI7osg@;!BWyT zV#e5u3sl%^w^Kvlkm{%m=#O({?tND;5f-l1!zTU|7s2wy1HUC@(>d=?lk}~>LWBFHQLh{lqK;pW>obIymS7-8|iROc{mWy|NpM0ro z3&K0!ZZ*`rOR5O*({9AP(l0Y{_Cd@1azEjU(!E&rxu9P9^LnYU{_a$cPL?upcCYHq z*q_4{Cb0L$zQs7ti2ab#Os>%?EP%sYK+kz~lfiwA81CB^^X|CHw;GUgwNLI+W$%?^ zx&J!bK=Yw4$cO)^!4o_D>V3YUG6|B4L{?PurhAJ4HqOS)EoQ^<{iij;Pn(T!YMSAz zGJfQipIj+77fDZAyM$TtR_d9Xaee+66x?^)7>juX{>0|Fan5ebKPQD?=m~FAQ_&Hq z9ahr3J2&=*U=F`!dEjOicHQB9Ate;zj?|F~S|+Lzma~@31RtrWvQbc7t1UC9PFg(C zbeT-FmMPy>U!8k@&i(YY{@hCgKzXO1>6hT!bi0AOgSBTXBW|^Ba&2}mR4hu2C%F09 zs@}I%6$za4>NnV?Db@CO*Y}TW8?a~G2^k$6RZJ{WG&-r7cJ9KMi@OQe8?T;y-euDw z@e`}s^N-vMy=&*J+EL}M=%HcD@Yt;9=6vI5|6Gc-{^-kx>btEC7yZjfuV#?JUV}yV zgVC3tCr!)2X1E6-?yh5*%#|YqbK*LWl&`aGk^bEAH~M1^Ziz$Q7k!am;HZc9ZQj$+ zvs7Y<=Njlbca^hPx3|A1@P=zX;4AyU%&g+_-lx@SON2>v8@j4k(#Qrl+$My~{*L4vTg=;*oO!Yn6>dMf0lH zm(54?nsUx6^QsImD>;jtOs1%+YK!a~j>^HvdOGBhwG$!V`@Cmyvr3u?&ESO4Z+UlK6`MFvty(;Tj zN$M1+jbevRcMElgPcaB&`v-YtPzD^E?<~v?3oY)LI7>X8bDn5h0P5%+Oz$g9h6E<2nY&ov)y3Ciim{+eyIuDWuvPkUeF4xSt^*8;pspR}! zit{UD)dSXb)CWhr3MK5i1)Siyi_(IYP?52&ef?eUec79 z>oES=`N2D~{<-9g4Q6SUS*k6UJF4ZIq%@#@bnsPgocRN^PPVNvPspg@>&LSWY9;3SA8X9>KF*_-8WI`eG;)@JUl zWIM5;EUv6nmsZXuP0kk*u6q-%PZF+Y6Rt5V7j!a5zP`WNP(J_*pWr~>RlctFLn4`@ zIf0A0#_DY3{!XWRAkzdaQ>NX&L&E1w+!3CA#&iI(cymsICt~El`DW7Uq_xCVm)x0-4)RO-dfj8{IW#c zL+Ofku2{`l05vib?H1`j(b$*c;jI4KN98D{|9DzR-CgehOZoTQ@V|Q@GmW=Qns8po F{{oFy7uWy* diff --git a/impl1/synwork/s1_impl1_m_srm/2.srm b/impl1/synwork/s1_impl1_m_srm/2.srm deleted file mode 100644 index 1d388e775cf3e5c732cdd0c22c16794bb15422fc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 573249 zcmbTd1yCGa*De|YfsmlV9YSz-XA+zQ3Bf(+0E0UW5`w#hkYEGBLa^XExVt+uxWfPg z49?~K-tU}yt8Ue)`cGH&UcL5u*0Wdd?$uVS>7t)M`Okv>Nn2Z+m34qeS(Q6zyol|@ z_NQ2p5nkCp#)pRkBL}D4##i@70rJG`OiG5PuS*DMT9)3vhkp9PYd2w+pF*;hktY~J zpQcmTdcV-+18QPv(e=7=*ZITT(K%!RhLK7VBR4_CXz4voO`HWY6P4o^(-DS&VozWZ zeh9Q6pFdnw-5kwz!bjB=)mtYMQFT2W)fuhNV9MB;HAlMG^VOYjRY@@SIh+`Ijq%om^L3vN~P7gDp-~Qot_i;=hkanKpE_ zD!?PL-uf=*3-hehjJt{;a6w}Jiwi&WFV=y}`)go|AgJ|1M30T)6Pg!q34P^GH0*)UWCU9 zPqa7EVtn&%CuyAly)SuYa5SR<63-EOnrVXd?yR|Sy7N^=w*kj<(d@()giZFHa}x3W zEu#uUANWZ({$;^=Cehu=(ievks7__aSRRwNSw7@TesZ3X*cT4_pa9iiw1zb#!Xdk% z3BHEX-CvYEF8R9syBYUfh!Z1jjTnniRDlFfn)J&LBF;jJgM(QLTZSD{Wu1Jz!p>Vv z-8aX+w+mo5pn3#iFR%$S;04p$`*kYfyDz4J;qOVw3#9g9JS=z#`73Emb1}zDW96op);oBh_NXn&Pdwrka)C+)$c@vbZzn$XHc$^Mq#B(Q?X>oW`54p02Cgy+zq}Adsst-RB)c z_lY~jsBML^1;(I{B-aG46&N;8;e_gIl0L3QHLnZ6x)bX}k1tToM-=7$8xGXo@Hp?2 zL^8VLH7OInFx0m?@P;v+xB79`DR*3RcMu8#!S*js{rDFnkNAo_xOoQ$!S*j>){4}o zF||)LIszM}X>!xID0-Z=Vx?%}**19LJx>ACgdHV%`L9T|g9n;KPf4+0M9qcG7m0N) zEB?vSiO&O-3T9z278P2?fu&$6E|28n=Osi{IA_#D*>4)KeSaoD8Dhv8?-OX>-o*?n zP*l{gz2@DZaJ2k18m~gz`dKMbj33%ZHhu;H-#2VSz^~zK#eRbVW8W6=PtI0Zo`si= zmQnPAdO+(;=uP8--}O6vijMq);>Hi=T*h~t>{mxmb_fuY#A#l;4_9z3ntDu{-B+^gV6zyF!I>$%NwCAE;Kv2XU*GgQAQAF-ehA)UVS`VPc2p;&w8A>8G; zrd5UAMd_)8Bm4@;@PlTsV&1XDFt)T??}k?x7R&XAuOvUoTsbjMW#VU^vGQzEEfdX$ z#^mrk$?9IFO$Ii6Wgn#h*-x}drwQL4JDE56*y5FaR0b?Q(Gs27v(jP&%2(tmePZ5K znUH!gn5fM&3Pisy(i2#6(%N>;zp-bwn6eSUaae-=3UqI_3Npi^%$3LENQ)e_h(AQVu}T_wbNIgTdo|at-bA;C znh;j*+#wevef6_eW}+EpnY#q8tQ)p{28(QPg4VVtrtgNVd#Ib@2jLZI+c2U%Y$F!5 zbC!Iuu}{#hvJOTPL4Ps~4E|7&8BPk(&tZCp|aOL>qHtu9M8 zwA<@q6vURHEJ>psI^=XbJ*Ruox+W~V1Y!79koxfzhDrU`60vxiCN?Vu5`7ib85MaQ zUDX)_c^yO589n(K8F?K_3t-ud7X}sV9J{ ze}h|9`g2Qy#bf z+y9876#n0+|5&{KgF1WmzYPY{WLgz>P@as7;8hXuP2V;B^7CKuwRG~t5D+pn6Nr~6^ffrGR)GiAM_>zcG7vOGLe-XJTQ z@%>%NT2Ft29I^If9`H!VM4m~4;#N*!^bVGZFIh@rD%RZXdDX&X%Y^lgaS<+uby>z0}&RId9KuDtG_w3W}zF_Q+o^YCG24zwEc# zZOHd!){y0@Ix-7*A=wj(-Go%1C*t4QqbK>Q0Yplx@l)#WS&8uFIAZThaYD-e)H$bg zAUD*iu}Y564&rK;jS>00L6Oo8kSFyV-s}t~7y(#D(&chP9DH}KN%%6$K|j4O=2yvy zPE@7}mBn~j7&gQWb1(EhvwVIQ@?+KJt&~wmj);@o(=RuhcXy{H<&}G*p~iuZHLwDb zPd`+S1A)31Jck4K;HFBHr^mu9`}vkN@qt6Mio1BCr-!b>w&#U5yl97rv@vjczwe9o z=)u)}0+;(AV9i1@(H=&b@>>r8rQGF%|WSGSLt0S7% zv&lQU%F1`oI~=FgZJXUkF7k)Y-_A{bXxkT9pNkg%^81>|!tr<*wg?v}ISN~{Khk|d zLsfgTPqd@T%tW`sxOATrgGmxFe0O@~>iFikU$H(u#|3O`hR-P@lZ+!N&Q7C*5>}%p z$Cfa70SWqyXp(eZ!^2nUl~$+a7zj!w5O@KVRS}J(Gk19PN)l}Svvl+l8@!Hsv3P`xOhO=@PRcyb(P~y!7|k-^S+Iw;oq}2 z!X-O$bZZQL=OzsVh_g>S2*1{A=zcj_KrCvu7=Cd?W8OSvbYima|Hs2mNj}a+T(8T7 ztN}q4ar3qDWh3jv*9r3q)-MIWgm3b zray-k=?w?&IuyI>469$nXaDp~?rTyG$B6}s*v!aBr^`1UJ4%K%CA(+*VlLlOM_DU{ zg8|59i7bw<#`Yg_e#5X4Gd-o|#h3pCR+Bhe>@{=rsieOtUDXSe9OcnbDC8y#r{1%o zd0sb*z@lq)5Bn@#BfNO9pXOfDd2mMcD*0P)dJrDqw8~o~d>JL{S;M=UbpqA859?6} z(LS(e4Sn{zz>R!0v~A=Uyc&*lD$TKdK>O!i?LCL`aDT;?tMjveU)}rz<0-{zFW{@1 z^bvxg3j1{*Ic47}O}6oe)&}+DiO(nM=vaimJ}PKb&Y#RZSVr8_HU%_f?=WXtI)&{+ z8)YfUJm(*;dp>dMG?Umgt>p4&rxR3s+>6N+G~P#lOu zQw^8pzDr$uk!jK##jPk}FP?#m)!F~qR~EXknNRJa0~&24OJOT*J>_nGCzzLOD0!&E zEqVP%`ZL*h9~G>?!#j89!di;PXd*%q|LvYuk=c@V-v3Q z$XfC=b>2NAQ?Vv&`DN3S{0%z4C|>U7bgz9u&}4ED|=E z_y&SB3E_z1_G8znmUCu%=hfK7p!PX>kp{;0cAx?0sg*XXk` zj*JNN1KcxFynx8w->1>sH%$_y;AAQuDgn;I4w9%#ORJs+HWGk5>kVE)sCBFzk zRqd7+HK@|-Al+?OH)|FO(2J&a>K;N`Q>R;S%Yz$~1@?{EKae?lMh zwvj$oAjy2@49nT3WrqSG2t3}Meg8F3uC zpql~qYb32E;X|Sk_I$hCi-p#kPx<@BTn2SJw=E|=s&!mseANjlhaQMq{zhtE;W*6g zY`0YcHVL^;Y#h+;pCV~SMi!|W&1n{FcX1(WQF+lPbkOHpGmB#>T{H|u^vg_3 zURH}xDZ`0Nc;F7Ov*~wLJMXE&<#$ghsjOLa{4GxdFBZ*Nx83Ym#vfj{i%u9G*#b1C z{-0w4wp&PmnGLoUL)Lf=@6O`HVyyF&Ye!? zeOcX!7f@rzRUduNUApUepvkh48x*AHwkmeEr0l<^x@5aZ^TQ(k>G4O?@9=GT2aDrAdO+SUL?T?==*(cphiwyEG;(my@Pa(()2UpSmJ$vvP<}ciilGgJfX|LfSmKoeBDX&pRv+=skNBKN{705d zDi#Qp%hFQBzhL>$28Ks)H75KgmHW^Vy@liZO9A%n(H*Q)7KNO&bb@t1$72__;JWx_ zH(`9%lfrW`!}wemgzl<3|*=vZru-HAbqwgc_sRsBZS+z zLb8@B1d@_#-cV)89ksdY*kJFVC3bz65o=9I)i`?|6jKeS-e@O@6!3G3&bjhbeP4;{20I>g_@7d_P;b1IFZ@$Cn<9i|ZJ?qV7 zubK&9shX+kA{qL3BgJ6KB@nr3x}TR~@xFna=O`j;b)^mpZ9&4zc6qvFwdNaAzS%4uq5 zh1Zv1{^f)t|PaIrV8zvVL23AmhBi|4tVV9>0S7poB zkQ%h<(N9j|T~@PGOC`6){PEzH;oaivXH?ZyK>p{e4eDju@MYET>4mhdbNs@(@jLhT zPJ6q^)a#l;k?}LTV^@7Zp%9|ODtLS-HmR|UQBQ2o87h(K9bB|f)xLG7Kxi0e_u>5{ zkR%|rED~>vX4RblU;I*6@A!P-EujhF5Z~AHR00;`bt-S9*iuWUZ)W(mLaB&drjvgX z^!!&oBvd`c1LS4gH%k%{oaDh^s+;6m!~Mp9=~H88Gg*ye?G7muM8@CI=EEPC_k8rW zhh7#X=Pl#;`*BaKk02gS*%vrd0$;+R6QGGxuTGQ0u?0U32wt=B2S`3I&et=8J7W*; zx}NIqGl1qywIh-dv~}Mj(4^UE3}#mN&8~Gv*vAqgul! z*fmF{qYBA=Rxco10=Zc)hkVx;^QePL zF{{{yT(wy7Q3LWh8DkB{oh5!%HvRfeC1ODemL&G4H?^R;V1)8orQxnJ+3i*V0@?FbA<3FVSSwCs!h88o zt(MD5&Q9ORW^rlDsT6!%mI*!{Vd(!OIU0frr4ybqTF%C9ms15*5(XPn5r%Vowah*V zKepIcxQvL^8w=0_0rWJfH`Q_dEmT>@Biu>}C-+}~(4VG{*NZffQbS4K2(OPAyj`n# z;w7gvzFPC;4d`9NaD;CAl7=uHCw9ZIcfd=II|QSr6x9slPX7y98kSlVa$m0B9$o#S9#_r!& zA+GWAa_*3>T4i_J4HxSE&u?b?Nq!b*wjPKdeo(5Hb=(>7EAWU(TB<$!HzkwQ^(@XV z^N|-|Rcmq`m*h!oH^n2X4VcP4I%3qmtb>-jiJ7DP9L7}fkv5te6L#qQ&CHV*YST&G zb3SHpVWei#4KGFf5iIFG$6sw|gemwO6g90gqenH?KNK*RkOuk$dWn? zu-38lS_Sky|G9Y+(5Lj{pOzKr^bgc<)<4fdDI`UaUmv9%GtPHk@I^ohQDs8Be^pU_ zApL8`0E?i$X-lFf4U)PI3eYp)elNzvHVbO0B^{8rfGZFy}cOCT1!Sa z7ad^FbDcr6pFShq_gdkDUjkFDNjuih)YKb#y7Aa4viBp+^tv-!<2AMQ?gJ1ou2T$)EQ-_z2B`~6{G-jb1k+#fz7xIY1}EgNp}h)<|@1*X<>Jb(jUb2i-e-^yVO#(jKyjtd|>=IWuwtYMszK7MB^ zBM;rf+4tF>^bO<@{|Fur5caa;5ueWTHHo$|pO0R8;!SU?n*@Bf>bC;pG==@0e>D?q zlWPI21m76MSa5F!;;#SQ8cf>&ko1TR)%J+?I{^G7d%W(x&Zp7EeBhG~z*t|GC2u`4 z#skWFYMNHI59Ct`t;$Fh20ctKjWT_IkUvU24!P4>Qs<{i__4&pXWSmx#!c1{`0Zx% z9ThL~L7Y8~vjQ#oM-ZncfJ@U8B4MI1V48AZc+@p?b9=PgmjB{B#Bd3;T7iLwd#eNep38AL-=hfXtA=;bveV-#PqA$ zHS34+_E6A34@sTIDy5chEUS^GaBcnY%h}@zkkV>eNdYsZ|>LLF4u18*USdO%eBaW^>8p8P|W!Up;6wtqdVfOebO?4;DKEfL)%5uK5mtY zyRGbAnp`^}q|YXr^~wQJ@7=}&Z%p>!7cR)s8SK3#b=F!stKvkv@E#WG!0;i2+%1hr zOSICJpI~k2N85rZ+>?s7CHEW|e5a8rdJS$;)# z0&+-S&FbY=OdDMq7wW8vZ(pmKu(A;mq59J|`*M8YObgb+1_~w|E(3DkTvD1%W5ONK z{pDP!^5!tp{E1ztRs*PR&pX&0WI$?-DKA4mHL+1qi_)=s9<`i)qYkEp0#8Y2`?b*9^t|-Ox`~a~W zu*bL0(3~2`a|Bp$Lf?8;BW&J^`>L)z+95=r%CZiZEuM7XOBjNqxxVD*UJuy#UJ=c6+&A zoW%cUsqDk`;270Fe{o}a?a2pmOaafAe~Z-jkA#+IXtzq6?1nkhD?jj1er?H`Vacx1 z4wyhL?4U|$Qc~S~#hN$I_0~tXA3xQAjHhd>eLQM1y>1K!oo0svFN#aXEvJhWYJ9Qs z>CaasgiQV8g>Opt!fO8DDucH9PXvT*TWg9g44sN&vSwF4M0!xgs;f4ZY1d6xdACr} zmYN6^LyFT$9cF4DN=k388`Wbkn^YZ^e`^DF5oHF8hZ#_ZisC>a8FtTBaC(3)DT~!T z>ABph*RfX-+|3YV3|+3gYBkWsQ7P(hvV(qi+(&M+Ypx3e@x5x;r_Z%k7r~yh>Met= zo7|?j!0B56}jMG}$ChN&~ThE6iM z;xXGBwIv6vkmaGt294b__yE2iuh$=LRJM?0Hl;|)gL_KV<#8jLRaN9YS338DNja_! zctyVI4VFV#17Wc#{x1re`$}rHJY7Unx%*8kFVBT8I=6M5Kz;hIbK9@oJn3JZ3s+}; z7v@uUQpNk8!WOyh8?PtslJlkeM@z1+;+9c#E3_|1m2=Yo$cH82*;r}KKmpd@I(4c< z;n!JV<<^YiU=8$iUD%!aL-3p++I(_5ebj;-v~<{H!^gQkE_a(|mtG}6{&2)q%xXOL zG^prKu5)Jgh6<(o)*AIB6Q2v(T47W>uPUf5&AW;2aK2T!0{OMNPx4dZX*EWw5<6ha zPZ9oo&tcMQBapbfrnFq<24hxC?aQEV1y>%j_bZg_+huC~MekDth|2V;MoY4=Fa z_I#Dn)Rbsrc14criQ@WglO7f8{b=j@iC5PxcTB6>5aRZ-iT(j^(;@q|sRVcZ|6OAb zBogZwP7#&DF^{XvL`E>_CGYM07JYP%$Hl>n7R%L%fdVUQ1}V+_D&! zT)T>>S?zVexN+F=A-i#SUgW3Fgro&sEc=k{Hb+B!$WEG5YudG`n2_9Y6Z?OU231Vg zv`l*tQV~YMrw3^&g9YN;O$z(5 z0!LP8>JF*;{MXMc_lC;|217os^5CE47dq`__oH#1rZW%HG}X4l>GJ3z(;JUB;#oz) zOxysC^J4#nCS4aQV??Suj^n&NCZi}6Q}x8TE>pLuG)>=AEW_8H5_iuXBW=}BlnN^P zAmsoQGh_T{+IfAZ1DWMR?W7H-m^b{=t=Xy#6jDF4`ngqPbv-^NnJqnP^$IanE^O%k zw@LqyOWSl`>Oei)41{YSW!Q@>4SC zE~k|hW-CrqnVHl8I~QC%S<8B37W)?bZ+LXZ)>QLn-pzAxy?_jlvgiHM=0Z|guEPV< zZ*XU_z2ELRf^-+5KN6IO-LQfUc_-FJ8QpDiO29W~H;TuCc96kV(~lmdr}}s5d*zfW z+_|2Dyo2p?zl%?<;!k(I<4dSu>-YQ!o4}u_JoTXue$w{*RL1q$xtl?#VikDTw%v)C zGUUpEWNQloD!6wvs@S_ITgcFLqh@YFhZb<#9{zpch#X$YUgO0Q_}ke))VnCPf<=(~ zW6#TaNOXzRzYU05%Z%#xzEq)m(@B2$M+CX%$H{Jr-u_0(%~zNs`sTNY&IMgcu@9CT zT%*>y{DDCNQt;Y@#}`#PWKG@5=PK>wm)N7*TEsbn55=<4s2oT?|8-JSBq-;1q*M%E zG@1a{gau~%4`bhqj+{mUf%@K_0oH+bWD4l@yQ)^uR&FoZVFyU#a1SlQh4TCLRo1DG z5C}raB+VAR`U5)FZd7d-zOh4t^AUAoU(bD7{6GQ}IImhQw>G6CIP(sK{Ge zfMu|gWRCK(#p6M(x6`(S-E^#e+iKgL;2h72-e=|VeWy?_>SSIj`zjB<`a`_()NGt* zr;+s57>oGpu*ohLY=>OA#Nv$zd%&mdr$LP{$rA7jlrMp2qq*c^IY)a=H4tiJF zrAt*E<0IRLx7xwxw9R)u$F%d4$F!M@h&i#-tgLX1!m%+7dxmL%KB>iRQGr8G`Nin# zGMLcY=1#(%)$*MjWSb3v4NjWageM=l}$>s-zb!X#_#YcTpGlJaGP=7kvVkZ3{|HEYCMcrd#1KoC1oa(htD=G(!b!k(aj zo}iZYAWIVZAWi8Ht_D&|b$_!)L8l16VjgBeKfWM>pFClI z+pc9x0cU5oISilf#|UySjnqTA{<0C0qPd7K6$VLKhM#_=*&Az!Ty(0E&78s`VW;zO z40i>E8%Uf@9gKavGVl1sqd?!d7NX>!SpeKE@^AlM!NaQeq2DDJ*f%mq-vjmut#s* zD3qJ-?tAf@9|$4NC0?cAk3DRfWFSu?MYsQvqg11(3Z-J8>w>8nEh{@N=`W)bqR}ko zc+%5pvCtn+>a5p?KdcR(Ul;UPDwys{jJ*3a;8Z6YJcT!mEU=Lv)|Z%C$SJf57dM*E*~95x!qc{4Sku7k;=_tt zJkWs#=9u?y)*YLs^}cUpzwpb2L6s^>PQtnFIq%h81qQ?b;B62;%D~D9z%BGR9DhaK z;8y=O^Yy*oVfYCyAg1+2R*z|$A5q{Acomnx2ztBW*6Oq$>loM@wVPStZ(kUV*rjTJdfj<5e9C6 zSL3PMOl|%lOu9r`++Jbc_f1|h%HM{r$_!sOb-nLo zdx&&e2V`~PpjE&e9q0!rVBTHBdRWvL$ps`dD54I^b+5hu3`z;fFN#&-~U18*wrj5zV+z2j)@X`^vpnC>iv%=*U>u7 zEB2$8tEOzINQ(w_@}=!Sx+5gMGvx1oy?4CH%)6RIIf&gL!G7jh-JfE-Tw1`*(OWI_ zThgCR!e1r1L1H~Bmb}cD6f5-}v5lgFMw{CNB=v})6=@?|dHoiq1~1GH?r;zwwiVoF z+Bxmx#h59fy4T#)FQ#G(Gu{p|OZS@HT9#^PZj#$xW(sX?8kq#rqtRMsAO)fv)SCnG z^j+}|lf?kb3dSy`XO~xsGZ)ph+t>?PITuYo#JptxK2%nzug#Es=*=IxWUYn~O~PEz8GqRq-h? z*^w zajRu#g+kG^7i{ldEJp0K!wxcB7lnBxc*5I{Br+CS&|l;)csIzWGGx28Hy!HSMkpvlM{aI&GOq*xX6sgTfO04)!}VF zmf>ycF~21{>EbIjRb-J-2Q7s7RySO^_YkVaLClq_uFY_nktB*-4G~=u3Ho}NsBx>C-$>>*D`D9O> zp6Pb~l{k7^#)U@|J<8+svz4=YQF$`U373Le>ZS1+(5}Ub$9LoQwc~l#G`O%3CHl#C zbjV^jUZOPu=v#hp`>T8!{5M37y_RWi!!O-d%F)8GWJW@)w3ly}9)_*_=iHlm@w9qo zJuc_`Nf}&r|Kw9?FI-e-U%%ALzyP0@43hb3>uO!LCw|=5kC4(J-jA$QaiE&E&V@^7 zKQntqv#YR%wmocyvDZe*+y;6Kwt;p6N%c#CH85;DsbA}2k%XiD@e)<6v%Xe9QYrO) zF|6vWSlbE%#6~r3yBb!a+77vaI(6ZBNY42!BKQ0j-9TOMA8%V*=wG59F}F_MNnh4+ zUt8F>U;}DEdxIY1+5s?B(fh@rS#NvD-)Qs@N zb1Nk_WSGOqq(3=v3LjUg9xi);U>*+mgZI&z7YA@*Mjpz~+q;Jc9C6;95z z7|EBwjVB{A(E`y`L>&}(cjUkpLc`a1n<{K8F~lyU(l3FlXc>h6HIF)5X9Tlc@`}*`&%3xOOV(M-b~hn?=eNlW|KX=l4V&^2{vu>%!=GWpPaN`5 zI;nRqIv7nd;eBeXri7*fYYl}5*awdQBw&z!;%?tV;H|P4)7OXgHE*Pt(la3&P0Uh& z)b&eOgJjl5RnW`*HS>alo{FvZJ}af}0P@4l3~LJjXJO{6!e?odm2>zRy#e%`bgP2Y z#A3Ko@skPdwtt|K_|I!Iti=v3MRCPmZwZ=hptZMb2^NWBrn*tW`q5vvgigv0*(!tC z3Rgv1HU$T5SvqZHGUXY?@%TiCPj=tC-xi7vv$;|R(iXa`2nN>lFATZ`>8Vv^c#3Ci z0W+*Op0=;Pzg*SK(CK?7^GK#8sRT0_u@$E6a$VSUrqn&5Uy8s&!$}O8bSA%yccx@> zHMo>id+DY&dAND?ma|Y_O@c;k9WP!img?#)ujy4w!aJ-RLCHSbP(S*SI_ETWaV{sG zZ9zw|Vb=w0m$Y25VLnk+>R#JleYW>V(P2QFZHH^xW;M~8;BLZ?$%sTEjNBA)1QJ_~ zV*>;GpLk;ajYr|%cr^H4cSR7k_x415w(mKNkB=r~>mgyjvty`a~db~U~)~Lca^oD zV#G)-NG(`G_yC=IyhWCoIPsKE#_RzW5h&z$s>J+ zdf$1ITjWJlegot($~fI{ru6ALwpp8D<|-E-Jx zL;bv48{|a2pH+zYJhhg3X?t$@W3Z$7qAQ3xez@O~TeJ-Eg*~xo@qTLYJECGmpZuj@ zPts$A4F84n@iM!{n6WGEBquHD02Pc<2IxebomO0|4z)$G_+M{)RGIcqb1S?q@It!o zTKlXk^;I>y#F(Y0k8fE^W-i49{B{+%7ClIKBa%z(PVx#OnU-GBv9VS;-DKTq23FH$ zCWS=33?Mhb$N&7nz+T@z6R-AZ5Y0UH-yMt>hU_h5_09^=-S-1{cN2)*s-}i}oEuKd z#Znyo`V>P2sFi!?&ZY3vF%_VRJa;X0rclT)iwWXywb%~)5NOUC4;W1v4LGGp9VNRv zZ=N;fXhMDnbjvpn(_T*bS+^sUA2sa-Bt)iZGN-3JQybJyFsh53M%GPNSbb=eOO1^6 zVD>oRH8y#Djx&f+nCeV8R1?Lg#?Au?NXPIn&|bMP=$%lQozy)3M-b=$-Xza9ouJ=k4`&wlJi; zocAacBo0B9y*UaK5|F+)wI)^tacg^+Er1L6OU_|5QPCm2H@~3PNHJ(qjRUzOk^TNZ z)f~=&_21_#Coj6c6kX()t_m;hA-2y__Ihbb%RoZZN2O%@X=R3R{3Rry?2o_7PnBNu z)Dou0GBh;Zs&O9-5Mj)*&6Wc9^vTaNy_-wl4(2bT*i!<>3)$bk&wA)l&aZS(p==#s z#z1eR1bw?-(fy(ePO~zOAG2&BW5XN&UoxcQ&4CIxcRUeA6;ELr>uoD&VG_`By#&I^ zA5^h5(#c3m_)BbJ1UR$*pL(qE{XtYpK;Srt31TRzHY$VEb)yqi`y8Tmur|-KWXNNX zat~hG=ebVNIh{ug&r;l9r*s#fHtiG?T}d3jq|mG=u}ve=vkrC}nWkcc08H4Y-UG}R zN#O2mY?rtETomhOP0`a;)c8uEPUDi=PtEJZnv2FIN7EJ2(>hV8>Ntmsj~Ny=ts z1Wj3DP`FylZWQIRyJ`9NI_p7vi(s-SAdlZtRE3ks~(94w9&fC9z6Ww{Tc@;#|yT89pqsWf`N4!Ycm0NZq+`}*K zXk>~-)<3rYV^1^rc)mzW&JZ+Ho+Jzn_{jo|LNvKA-i4VcqaOo!vh5iIR*ti%INfd` zs0@z4S9;Q7h?1^(0@mw3tV>eA1WOyD6!vI>2*UBgYo5JTbcr4 zMexV`@#fWgPi@X;$9J9lnb;y*iNws@oVc6(Ttd#3zOuZHb%1vOHwIINI#MIaTjPJC`=H25M zQs&I+`JL?+=U>LRmy45|LZ}6l1Yjg!(QD$2iNeD>Nrmu@AxJCaA3|50t>5w2{}i>_-WhkYe?dbbuGo3$Ao`=VuT zr})t-;8!tT#`8Tk@1jUNXCSbji3#IK@x+)InTgTT`9^8<$)_K&z9t>5-txkqYp`6n zQ~#;sL^UAn@kj4oqm&oeKf5%I`UAn+~tR7Li3W7fDd$634NwD`h}u4&djAKXUiv23N1 z6o|Sf`1Z&SDAS#{E{$LPygpzt`px$OG<^D4X@fE8ZK&U;&(r?Z7i$^yF82lG{VA&= zvo|SHFie%6Vx5A;y9YaKU42YbN{p)LhV#6)l5j>;==x(9+b=3ChQx(@`HU!%h2PXo zU29WoXN7HSC!OSld;SJQg%RdYM_G@Y<+{g3<)3Aok{AABJZq3pT=|wKN+N@yzDmp@ z%7yH&B%Jt{u8<0C!z50#@)cEHB|tyJAmg4`l%$1deTq;%<3&`%=(NC*rn{h;JX)by z*yNXM#nmZg7s}_WfKbhEE7e0hg9XhjUW7;LIh9UEGqu zH(IQrkgs43-wRFyhwQpfh(dQJDY3v$jexJwH~$Y?XB8Dk*mY^#H4t0^BtRgzdk7Xh z1b2tv9=vgPcXxMpX&f4NXx!bKMke#k%)e&M{1;VqQ>&_O>eO5NJo{{#vYgKYC)MCD zn_^#|tkIyKd=|Sz+X>-hzCJMB+Y<*XzjVub$y{O$@0meAIr>nF6Fi9i#@J=Y*o6z8 z6b!2af8C^H_cFV7n%Z8vm3iaE7Ax-#A55_A7CqS3H#1tL zdt-lVD67ka$Fc0CGL%uois(wW5^2p~9B$N~y^`6)lyuY?^t-yBw;Cn^r%Xt8YsJkj zPSWwq;ZKM%Vn6?Zt=%QZ*n_YGNlxryz^%s>KnU7x5GCJ)WWS}P4{0QeH}VcFJov5e zII~Ud{yy8w51%U5lMcT={=AZi@vaZX#*~2tbAY-XRw|mLor;Xf#Dgl z(78VMgWu37grgk8xRz|zW6UT=vWxilgD5L#i9X2FZPQqUFrV~u?rxZf7Ni-Y>f2|l z6E`vAN`>D7K1Gy_0}=_9sUAkb;I+7~4_@$|qk1#K!E+v`vfLVdT2V>2E1_T>@88Zu zRlGW|MDk!%-rmU{4ji8dOrdSz8OZ8v;HlNf@C8X3sjiyv8DWuIZ@@uv4wJ|`!pk=@ zAPDZ8O660U!u}W`mGq-vPB>|@vxiD&?K1`4zG-IKR=xZR24{`EilE_5b>x9OchZUS zC5R!iMc;D5)Lke3(X4p!-NbuD1hKmHLBv74_W@A{lcgr)_-({err|Y##wd^_WNDyg z^)k$3xBfNz`ZK?6k9l1*TS{Y??8Cp_V&ZCr8D+-Y+~BsKYtgK0;o0Vy{zUN?0}F-> zf{C7~8s6TN(gH`oSLiQl(+FBmN>5%yPgwhMmlI}%1wGKyOjkBV<|(mA`%=Q9 z(~BPV!#woj*1CspU!C0b+fgvhhU9m*QkP?w%isGrDxUh4vx(ux4FIj`ChjxEzNWkf zwxHt9lZJqgFgG6dS~1I2hrasKLr@6_g>$%m=GM|#O_;t;uzm-~_!_Fb#S?l>dbUGY z^#gy4v-?fsC7&7qd4uv015}9*{ERz6PB=Y~smW82phpBAKz=UfSljRq*JXd?iw4%v@9?aHW8!d)S`KL*JUJ0$eSW#pn3^Z> z5oG;qo;&O4rF?$;Z7VAa6anjPNM27Z$s)9hPIZ5K0G<`c|orjt}A*ISO69Wmad$C zuxy7XkGUjd>FhkTzAJ0Ig7>lILCOy8?dYIrVs*Qto26+fp>z1w=Rx-qp2%p&cjD&v zwM)43?b|w6zwnpW6ae7}D%?HuuUw-vwzrSlQ;ES9FJ7S~n;bB6@RYk&3S-y@I_)~7 zybK#leJkD3{jtKsM#{Xy`Fud3+}PqtZ!@Qy*O~)iF+(XsG^(seIhf(j>9!F z5e9VcVkN}4$N%MV-EsW21@|9&D?ALQ2CA{19UKhhe~mKwKh{?-rE%K=R(#!IeZLbK zIfAmtTC{SWf>aON!aBbSj4`voo!IdBzkl|E=^@YQjaf=O4Ojh#4j}KdmUA4Wrw^Hj zHf_;s1Kioc`=4+WfpDLx3w33iJ<0s--yE@a{(47#*c^l|7^Ws~k20FVM&QG?WH$Bz zdYzuw^^t9KY<-6J4fze|6?}sN5sMM*n#DS>35d#<<(FwE=lEUbHyCM+C;uRwRdhpQ zy6w^G-zosN68ene;S9-X@L!&BA`D1MjPHBz3 zjx>ljij_Mb!~Ka&>dKgovP`O3*aRu4Hv>mcScd1P+Q}0PV?ZxN%(D?oSWmjYO z;tE2e9QhXHG=`*k=*3=p`vV#xpMUc0=li(DF^ryNpU!r#ACcE8yXQeDAX#Srpwhy7ZU5HRtP z_tE8iImUEM)!VGJ7qf3u;g$KE>vxsqDZ3i+nZ@nl!5T|U0Jsjxpm@Y`rL7M8RQaM7 z=A34Azg_}2_HqyNzjI6LSSjwdlDw_Igeygg&-`)pH)^uTmnq;i>H3}Jt6jcOF11(; zD}#nP&q_0S@$z`f-xXVINdJqO!(3#dXcAcWDtvj{nUcuy=E)Q*$bO#JXoH&zKPsnC zdQ3CvEXKGaN^7x)mlJp8zt&-9f^Fme=~peI{Npclz9ugMoFP!WGg130)jk0l0tp_m z1LlAbmis$(tl=Jdzn91!p*TzQVS4+}fY@m)^^PpbR^;KM1i{Cf*y#yuf=49~`&f=x zk0+M*HJRT;YA!vi1bDCAMoNrS+Q9(nw>qe405^e}_CuVQoSE^NMktj774C;Y?ypO; zUSyyDrs@|&F30z4BsAL8swZ^kcxC9(kbj}9!a?Lgg6SrXLw>du=v_mv z3~>adZc1ChmVKZ(m*n$2+wA1)>$3--LhLTjVau zn{7X0e)&qr?V1lit*!O1Fu_)TOssxJdux(NM0$zduEPoRJ=0S?#reID?MvPt8@Xkk z=Jl5FHs2mN!cWpB=sg7Dkb7JM#5WdpqXgk4v5m)D7j5156>|=B!X*aEG@x}@ii(wL zv^#VRwYZvPAvab>Ay6gY|^+3YrpE=KW+984u+fGcP zb7~8z(8H8br-Pj=H^^i07jNoRVzj@o&{P-SA|x(B^33gIzFLC;AS^oZF?6c{D*9=N zmW#MPu|_;GE!$4D|}Pewz3)iL;MOEC+GhRg6a@(3VuclcL=rg2?4 z?MC^KVIM5H8PX&9a%2(%rZCm#Wpym!2ErS&{?Xi`5%1x+7(iOa`!+ao)A;w%!(u6Y z=ETFNS!(Q%c@f!~?hpr6c!^Jb&hBLldO8rAL)J&%;;C=&RikRxSTGf;BwS@Ij2QSfuB+H7Jp`T2^XQ{Ov)U}*Wss5(1vhjFXoeUNevP+c6O^{27i38l- zKg+yN>rf~!4RJYq|AEkHBAXySey9XM)xnMLnc=X#(^2-RNzlAw>9#;XTkbL3EHS9nF9DW!>pr6fP>DSP`HaQTLN)F@KiVoVbK@T^PT!I>FZ8Ef?Hvfvlw#LX3{^c8I zIsfDDEGu3~z(whr6`_swXAf$=>}K1>i?>m|wK+i^D`x9e0d?*yD`(tU;+Wf>0p0`G zRqC(Tf@CSVA-vQYD{=h_#DvV03_1^HBvtBRm@d{i;4?qW!7(JbygOZyJ>qnji^QJ9 z{ySB#gken?WtPQ}CZ9;stYukJ+B)$N19c9)qEn|L?1`l0Lzx8~4qOR?uiF|@FQ*Il zGsrDvEYbT*6rn^Y$w!|!Rqb2+zp4cI48;$6EtLSut!>%fY+><~PzYG4Br$rE1#;Cb z4d-V9z{!vP%J~D|4f`8)vzcGt2Lxr+-3X**4oG-agfmgXc-ihF`S=Ji@wc-K5i>G( z2abG2@6b#03@rT0jO6ATtx5Ku_-2H#@0wpSy@s%cuIL=D*!~J5iIp6!Ij&qrXo?k0dT>mqZox3pHJ|?SQNE?q!H7SnL~mHHdkHzDX)O=pcJ- zHat%36`x&xt%(qur}dg11~)+LdLQ% z%v)m*upxWC+7IxViMzzoaQfs^j+o9-`p57uGGZtKwfb92e3YMJwRWe)_1gfi+ehVP z){5j28h|R4U3i4{Ia(FT2AvV|Y65qBAD#zInK*MT$Ww=ZwLJ;qIm%y*2Qpvbi@>Z> zg4Q0UOT-aeSi_JHM*Mp7=8O)iE0jmBhe};{+ez5_FXE z3uam(mx+}Y^4p)}J9YBAB_$;v_f2=tLev7QhgELt(NAn6<~yZ9Q;;uTug4WXj^iIH7mcduHS~hshuAMaCo5&f53>_h zXaqBez@7O<@6r2=kWzOe!}q+%>EAComFtQ?=KJ4gJHQv6W9mUeO&FBhmu2vn*`+pk-{H!E0Sm^8}pPW1Vgu!d?Jdhim1wsfShR8OIF_8D+EP zNlg~Lo0e6LBvRV5cEEd2R@Y|vm&C;#-QALbs$PnQUnAt-y@LyPD)+Lg|^HVZtp!S zUaPTf`iM{QUxMlNIzltTg`8FSYrH0DAwl(1o>4!_BEGowsOo-FKUFc}V)q64I-D!VX7AHxPWGClKB?ZEQ|k}VHs#~~R(Lmer=dP6z;g1g z>uNfk0;+^%mv>AtE@qcG;ECGxQ0=+Oz57Y$!eZc~kWGexd7NGE;{oZ_+zzEf+xvU$ zE?`bDQ)~BdQ5wF211pW`ODkfcQg4*pCXKDk{hZBqv65egTi^{P7B=u)pyrjChxEtK7cch3k12)ToK1ecbo+iXkJ@oSc% zNItq03<-7RA8Xb8F&@yH8B(^YwYvOW_Ux@w4IZ|-L||goczI#8>QawP+7v(C=)!*3 z(Yllt5^1eJL{@)zNo>@Gq&KyOMyp+E5)%r2l(kdxtQzY`a$L4*>tJ%2tGFMs3CQ5~ zs7X}oR)5~P&!c;c-D#qjl~lz(t{mn+pVdR;Njeb)>I|||SXK^+W!%xeWTdQpv-POr zpXS~vek|T?o_kNIK5cFMFySKkUJFI=8Z!db2 zELHb<*Fpt6Gae$MJvv$!DYBGDDYA^u`?HwP{V|6bj@m}0*L(AEy7giC8ubuwVVy*B4Abz6-M#t^A|YIC7=R&yaQuc`L2nr`qj$m%XrZAiXG^?gNh{cg&6eb52J zx-j|{mo)4W1{ojVdC~K-_tRl)l<>ku=v>jX2**Ua=zULVmclN?ou>AAE_i|pIF+HMy>IQ4|FuZ5{X zgyjIzrkgantGTLC-Z5Fg8*%VwzCSqftPvR7p2S=`BQyrh_49Ima*Ze$WOb3jMdm2k z-``s)GsXcoFWn_)_(j|Ie4XjT*Kh7=cQpC()V-1;og>fz!maDKr~5y&(EWx*I^1lS zkMsox&o4-XdKh_zp&}4nx{|pI1G6s%ca>W;YZR@m8AMya%BGxNZXc zerXJDRoUZ7w5K;NhP?*vCHUoGVOE&mQA0z2!DqM4MxSB*BC3^p zk|cqZLf=RB%e!Myev_t;NQC0f8uES0NV_3bCLs}yN*%=iBXNtBbg4)ed&r7tBh%0H zU76!bjiXkvQH*@)C(%Sf8l`94%)w_F%w)Z-kmMVSG-ck0gzMRLk+?%Z2cb!k((Z8+ zaBhxRF^=$!3fA4Pqy!LwnjUr!B&B|E`$K{mj8lv;+c>0%flYZ82m^*t73eMF)(3l1 zKJAwsq-67_z+%CP;0eKZkM!tNYjq=$A!;(|17;?nEc)Sk1&=Sq9yA!55F4hxPt)<= zc+w@nwYLf4q5b5T#Arq$+yb8*hQRhuY>Eg3tJ(e^f0B&~BCt~ib_0X+6=*eZ#GLII z$go|F%S00XK+*6>{I}>;QrCi57lY;X0^kDs69=a@>m@G_l?5a|X!sTz$gVHBlAg7y z+r+z(>i4ZV7GRr|QByU{cs(3SkZF>DBV#tz) zz8v;AwGHa%-ntS6B|`F!+#1bW_^*o;DxJpw-;->nw1pNO${{aBO*|5Dm;1F1^ZbX4 z^y(C?jOs}JHapGCxqH}6c9|Ku6&mykS)WFA>VJH}ex~1fhT%S_OtonQrs-FqvW}uw z#x~9zh>q%hb=7Y3tkx!P?Jr&%oU$}>9ne0h)&z4gvO9`&C_8zxgZahWTof1nRd|CTfsR?sG|K+^3A zF~1*n%loHsHRoCZ3Dl4 zVo4vlV1|B{rOBdUS}UiP89p~>5)ze_+Z~2zI}*se(k)MA*}z?#*2ZTx z^VUz&3iy9=)?K4q*{L&GXT|MYavSY;!S})Ahtti_&4Nu*cu}Gw5NcNgs5aGLmEF$Y z?QIoJ8pB}QWQ}S$2=DeKFSS<0sOY>A4C`$RjdNCIxGVDbtoM7$99DHcs=w&&K1q0# z|J8v&T|IW21hJP5Vlm$~1bO)F#+{UFuvBHKS0VH@rCPuBUN@JLI?wgb^$^Nfh>eij znrPYw)0ARD<9|2U|uFL?|V+jTe)5NCB1Dx*>g_$W_jtUb0IC^ zsOpkO7FNT~gI){0?Xe5LtutV(!R~=Up=`nf@FK;r*0fSN8uT^9>?3-c)kmIx>ITAE z=4ozBuY<^GiSD_`>id5_wg2y+PhA_kRhgF8NFNC!_40zFCw@btNTx!gjterOI`Uv5 zatWO%OM&l5aIh^=^G;JfJ)TH%7=D4>g6i^OMdgT|o6V1_R_AHg-{Ee|fuOJpY&`yX zd2rOk@}xy1XFhUui7_y`Fm_LsvLj&xz02Tk@e6=`KBQPdm*Zxm#ob!JSE%&_v6~c! zYp#AenVGeWL0C1|mI4=b#qi$WSrR}YN#OzyLLVJTT3SttaD)U!&}Hi<4iKWbbdf>- z{1Dgf6xlXmjbD1ECiK3(mHuA0bK1Cz=gvEiw^3xa_iSc6Trd8k^jbcazU{OfA~A#Y zZd*vtxA2jW!)bFdqx^%x38Fg?STC(JD93bK>eGtk*dQ`{?fxwFAf+!$EDPe|IqNW^ z9mkmRCzx7+p80Jm~?`Zf{?$b;g_~)Z4!gj8^QxOj9 zV*>K3#&@8C*Df4)wV8O<$n_@A;)2*BC1RLkcxr^8)b=(J(i5!>BW@&ZH`OoOAO;>b zRFkuDF5LlCIMpqo6Z485U^@Y=S2W_zj$o=|oXQ@nU}dpaOAq4Ej8A z`_|@gVS6l%w7D=kx&HBS?W4PUj&>exT5J6hs?b$jEeQ_U*Zgxn+pSx1SkIFS8SSYi zn&(_~Cs2_e#jNkHizC+2rP_4mnv_eIHdjGtH+FyTxf?#b7AzkBB76}^8Z#njG3%rW z{#*eGHV+OP7S`7T=7V=Mvik>>DWUnxsb4MHHInVp14rIlh|K5CwV>CuVL0WQcHVqZ z)fr@VRS8Nc{Il}&&x(Mz`j{cmNr55W*Go1t+{24gSYj{hxW4;C7AdA5usbsuy{hsu z$f{D7jU}>jKQ+6~b-0kW2wShvy+8OnDgMF|j@;}TPc5=Y4&sckFh14j>diC%0i9kE zJab1VDj!o}jFQgTAop@XdZd(Q5~HgE`NYx8KG!??tR+~A8ix`XV##!@5bR1nd>2<^oBT*|>yg^Xo|vDgX-qRUQZ#StMo2Y8i|I%n z`sL1Js4BhBB?;&a@W$b0-U>_I>hQQgq$)}YcuJTTZWFfTjW<@bMAbC7k~CobwfT!= zhyLazT>K3yA<*sJZKAEKgRhUcaSrw-07XgX@-qTlV8~n3m$l@#4bpR;rx6LE%E6(l0B9kXuS zxX^w)`i}@kE0G6e?ECeW_)G8^aDSmAWWM~@LdNeO(7e00!+rb^v+=sSZqh>62*3ZY zRI69RZ}OG=d|!RP;dj%g>KEr%{UJdaU*-ia-yk0Wa_JHLP|xqg*2OdWmDu4ilS7Yl z?T_^lhcphF+%oClq@LAcx7*@nomoK38P2a4YLVK3b`8%b_(bQO2 zUL$N83h&bX6-~U-?xWux)wYOo93)k{qHG7X4gl*7!82qvijea~S%pADwX5b?i1m)33hWcFj)#JTQqOd@_$lpVBoP&L~8K*g=kG z)g9AY+jjImrJz)2SyleJJHABQ-fwZ7+u?r-9fln0N6U8-iE)O}^Oh(Chp)HiY>px~ z?Q`jImrXy~mg3+z;{48c0joOt5czfQ+eAF+HG-Pdwmr%Jz{MhLV0-g@I?N4cq@40@ z3&bT6e+$9_1zU}@4dJxLw-_o!GmJxXDXXm%e$u-Nu4SBt^H42+gX31xF&Y)^Q`F@= zb@fwhH&cz-oTGORfaz?YAwoO#m-_A`Vf3wc_$K*@<;faX%v`SFl~#$}7l zt1`~>E+^rvhUTVi--jw6K#^jeH@xanCP@na@d{?$5PzL&qcJOZ4`Ve7#8ruK7ey*= zR_*xEkN2rgZ}mr7kVblxaRDX;kF}sZ%B|V`nv0h%)|mIl>uzD=o^QctpnR5;PJMVs z$WeFQ4+NgfSVbvqdjhq(=?^+~XiTs&&K3nhK7v!GR|O8c=0j0S!@5r$a5siTCu2f! zCCF7Bs~&RL36E%hXy<_LjnjRdHhp;#Z--s-oxX;^nTq_^7W^6m0{Ep?PHcE!2oZoH zTk0eDt+vt%?iu~}cm!ECEG`6tc0lkbP>0c*H3b~TjYn;F=nUBwh8aS5p4<)XwM8Mr zN)LadA42O6`jm^Kj=XQ)rf08roX`A^#3;|=VmRt?T@f&`K+%ZM^cHJ~_FiCcEZ2MR zZK_wuV0I<}H6d^>Ioy-kUBAIphpu*TRa#F)kmbDPvUScM8%P@KU6u@u&NQ9#t`A$S z$Jhl9t>A+a%y-=DKY-A^{A_ifORr8%xE?hQDW+sof(|58dlhTq8LYp|gRSQBy0A>Qwztl9yEK8heV5bX2~NO>nZt-l>|#&#!Vv=-yt`^Rv(VSQ^`}!x9IFygn;^!q{P_a8(Td{t z)HuXT9=WmZ%pHzHhHJ00@4OUQyxBj@GrChI1w=XzOAcn$kME(mj7^4Rg&|Kz`c6ct zy>&aj4otVe@bcEKe$Vk28(WQq-sdjnb_rXQ{gh96ieKe{|Ji1B4vI3e^-s5q7QNpN zOGW;v84Sa?E64tGt;Z{{ZH@f^>3m$Wtp?shT1l|ty}j-AFejVi+WoX&((#B1(kt({ z5BFjb?eOBZ{*>mhd+)%)27`f*Wg4^&me)r9Yoj{eRq`q7qxzKm*;rh6zoHD{8}Whd zk4=wdV?i~-^B$&MUWEBW3K#D!U#Dq{Bv$^ESM2fjt>mMB7>X#5P5 z&vW;*2Z00AA<)Qp<9(;x+P{;s$Hp7I^&Z-9*w2?H$LHPkif=ltM>)J~i0||!>X&~v z@G{>nJNFqsp?_TrG5b)_GO0DN%W8UmPJ~L5>Zq6FCw%C^9?e0ZorcDQDx`TdD|_oQ zsgJ+gJSjx?de-*CR!Wo3&uVhX)m%3=u2j3mKeF(b{1pYeL3ahbD?P}(^{=z2o})tB zVny`%$ZSVuXTz@{hkjnOXeKet$|9BuFJ|NQ2o9VOHs#$YCt@Inu~FS zdJHX*4I8Zzo?8SqJhn4~Iue3_aBaOPq&25;9~Lm=eJ8nfI4OR?T{~g`T$VMeFh1 zg0?GMc5I7nz~vzANb(y3V-QnKtafC|7*oeoSQKTeX(wq*q-!c3>1Eq~lH>T(zQeeY z4>kwJzq^*6uIDd$z9y51OfsD~Mg@tYXS7LdIE^#z5!{>FN37iErW2pUUo@P?9ZUq6 zb-2{2&s(Mbie5N`ifHeBu(3$m_N>yv zD|Aw%5G0mO;_lr%-QxqZ}+~7}WWOQnRKfnfzZpsv$VNFL$vnPyUWF zzl3PhIIoz|m;wnxsR}yz!fdEmU4x&x+S+2{m!sa)Y~)YrK)QP0b?_k_{q;G0yg|;* zh>U8ZUB*L}dHF6nQ|iDW=Mrk!Xtn-M{M7R>2sqhq9}j*tffH%e&bcgE)Efp^DrT?Q z_mpUzl`R5*LJRZ_&s!7zvMRgF{u<2ms3#r|Sph$Iu3a15->~p!C$mSu=uE&RrNu|D zv;aN;^C`6}NKf{nyLMZc(4EhU9-I(SSkd&VOwU?wEKjE{(XY#U*mkQicNB0PQ^BpF`3k27V? z7v7^jQD_U*AU)Q;9#|dGV$Q#Cid#yF=&W?XZMI_W4|lr|UEO8-s4o`6`yKA1(fd|=+8UD^nktJO8vmIv}Kk%Zi-#r4u>ca7MaTOwU?TyYH z>W4=o+%NY$?b-E!qffXB*%|_dYl{jGyzW`N#P8j_O6m^z!d-SjlVB-#26LrHzHtfx z7K5xHO|3D-^d=3oBB3BBI?oG;JHrXnCooG=_b8+1M zPTC)uELM5TBrM~Lzl;&843L&^ML6(^N>v^#zn88m+r=3cISI-RX3G(}C8iru_Btx| zs~@LXJ?G zn5lPb?@lXgU~@$m4_dg!Y&Eh0(90UAhfVjP7tu?J>1 z<$3fh1ZSKuTC)YEzCE?GJ!*|fb~!_!l3PN?vw_fY^9o-kV}fCWQRj&!yuZnpq~Tpr zyK0#qO(ESiJMKTu$8VD&>H{i}&WZP$y(Di1^%ULZY^UDeYq{+b7%A`sYaQuGkUV_7 ze9w^5T#c*F7Ro8X!cW((25(oDl9{wyZ_XZQ7qVC&vROf)YzoT$o}1%iN5$M)292ek zRmLLCYCE}HVmqA|zvbFHpwD$KYoDcDr|uYEQ!SAn9}(yve}1ZEql$Bc<}ZXSb2C9G z7`*Hps>80j%tjyUJy>j$rcfA?pV50sLeH2m?h^w)q!2* zR=>XtUm5z_5!SiPv%*?WH-I}lq6)!F7eJ3&;t|rdr1E`cg!*%1>g_w3Z6pO-S{r%*x0(YoFi9cxfr@ z;Auuoo6;f8N4DYZw6s1Ec~jEWgNF|6@&zn2WKZt6;}gN?R#Um*FS5-JWq(v9I@Sb2 zG2dmYwO=-ZPg%sbVtRaHzm56fR$5z&ii-_PTZUz3(6>M7s?^{y(BoG zMDbP2SCgK||E_Ok9am>Lz>4$z@Q4wCT!o2tTikSHcBF4atjv3Q>q|hXxI}N6L~Z2j zz02qafkm%QS4G0im`Ed8sr>+0Z1!X7n&n!l2^rnO(iz>*5~`gMEz?qDb@x(!inw#+ zDAQteIaD-4?_8$(8AeN9PSlXKn(t5RKn?Eb#T)$n%PKR)++OYf}sZ8 zfX7?g{g+u6eawE2WgieaTBk#6wxhI$(cS@mmHKU$$n-^lR)7T%im0X>kw+g-SmQ)a zLB4}Z(L(}!x?v~Fa$qIh3Ime_zcsF}couzSsu8I3lE*b2#K`I!JCzj?`rSDO4wwOJI6;o^Vfe%>XOD+7wFdt z^H~r1-Hhb&p8ee`xue6TtBfTv)lq{R2DKh88#Fc5^b|mTn!5s>^Sj%4TDl zX#M41eukEV)4WZpJ8O}-aOxWgVkA6HALWnx)0I#KpZgMDsc*iY;G!t!p~0pO^<9$rI1`($&(@)`KpO{A*q{BgG7CR(9A~k55*% zgzi&7I`VdgsTFT~)Bp!r`5P8pvEAKeIpAJKY;N(QaHSPPUSKG}Z5nfd7aQD|>@ij1 z&1R_wJ$RhSFcrKjDegAoJysxTaVs6VU$9<&-d3-Et9n-xb$=)?0}#5tAN%ZNaCiL+ z!xSaUDRUs=GOxLDwA4TfXwa@CnLWXBUZW*hYFM$q8#6fmJ9{~`^z0e{%f+%ITFSbX z5Ao*LxAKzL+g&s%JTP)2&~HRy0~V-Xsl5shzq+LK51+uexC~lSh>N@tiNhd$Li-d6 zhuR$?YTkk5`}|`|^%L)&D~gZyqhj@<+ZqJ!>T9;ohQCV)8YQPkL{%D3fJ5bK!wtfY z-*?Lklui_oXToVjT+COUK0bWd8P`CKts#(uU1hRRIMC8KdqzT|$+b=OvgvHc=@l$; z+E&+-9At;IRHad)iRW_y-FAjqAn_%=j_HfRMS=PJ{Qmu4qzFvL+&v4<&PROz)V~{H zXSxSHnL8}Ekbmh>J-=Ql9tTdT9@Lx)|9L>-)BY-WYzL*6I3r$5e*YPZa>uw;n6(C; zQLueeq&??+C5GT2GyZ$9Bhv0u{jAD53iOSsDoeU^m>$>y;C^$-p|clv>f5szf=dQX zg&pXY8(mNe=caN}gomI@)Qh{1QwK3)j}LRbYlGRrwd}xix6>2a@O;U-jZdPF(Z9Bh z!jszvb*WT;wcmlxN%N*Yn?DQrL|(^OUcmVK!@%NrVZ&wy7%&0yG@{xsWap~Sya8zy z+3$|es*gSa;b*!xF8vdEp$L)ECI{1?6|xVEtzSYB|IQ{YWA&xlZ^E2ySw&+U2#>38~msHQMG&h!&|M%q+3vw zi#hK5y1;p}7ssMystp#_N1xKg!8{QQdDRqo(2L*2@RO7^k_Z}{lix1@Hh15!G9`Vi zTPjMw?5%TvNOo~5v~=wV@(Z+ZeQ(W)D-1N@O3}`__qIvhoKRnIEqZao?P}^A0 zei0NdXi+{<1R~W0df52W#NC0LJw4w9o31JQw@wF0S=z>`&NRPmwBU7iKc`OO3MqJC5SG?W4#S*9_q7r8WJi+L4V{~>l7cOn zhw%Sc*N@Qb1l5kx1jtv{e%+SBNd*kYR#i4{WO<#|i0Ex&3M1-wXHPls2U}}L!h%Ty zZmrifEY|P%odk+kqjMRfdE^kXKgD&KWz)UC-X_!)3;{WoxAlkxUL4Ns(FLr1Fwo9& zwa#i&h7=MF=@<-=$%4rZ43QTMr4|j5Us-Aga_g;O8|&b)fmn^TG!=EbLZRf4*=0k^ zenhfb^0QE}TAFWXZuiSn_siFM1Ok>iv3*#|YOrH4k4pR=(>5uRX&MhiKyNm^5A> zhMVR@DbF?%N9bCrXh;Sf&zHk&FM#^gJeY8YY=teI*E)k%mX zE+4>v>Kh=rdw6xSn>`hzZWEYIi>0pY=8|z7?VtPNb13-{+Y_1j2BisAv#{3yEiZz`;i6Xv1F$)YL{vDD=Ps~vtLVVNH z8=0t8Ep3`B;gPMo;cc7=7peB^mErqm_Y2P_k9H;Qhv6!UoQ|3&(k>%|KGHQksYvs? z#YiRm0PAnLktn~7^DYKngrzT>Oz|`xMFHT7PS7pX@f}dof@}QU4jgr~=JwNkDIl5B zib5)5hkUl~l2hCx==fuy`exVpw`)mgM$^(G^r}+@>uZ*$=D83ME(bll(?u)nOAf<$fXnF4q|xCw^F_yMsw*zEGxYSw5ZO+ymLJAzMU!L!)&6uS z8go4)<#Kt*FpyRB1pNeu6hSdSsM`)`r9&uao)4*@}G~Eh>JM zT>s!tJS%}=0CEF!sLimBp$Fn|Qi=M^N~**7^RbQcPhyG5`J7h|{=B!5p2*h>3oD$r zV(+o-`5vM%ib{qAu-$|3VwFTy-`$SfHcuHc4-J>J+{$RiUd#OkYVu^^TV6V{K5dH! zb7P~TE@=0H^)^Vcq~>4Ji`%s2^W_iz4x*AryLIxtd~;*z)%s*JbBX?unJJtiOKqmJ>O}Po$l7Q{2ksY^7E% z7yps%Cg4323HHvfQ~X=U!ub$a?+VkeC-fi@{_1k+B(?H6i|uS?rfR#DC}8A@5(id% zY>M^K&pW5Gm1Jht+ZOyN^C%DnH2e0!_Wn=gwoDr9PjoEM_``>G@>D%hkNxM>W81)s z7%#Fyw+!QNYf_OcQantE7%yv|PN8~u7b$(pB0b>O<;un+{NiGBLiqH1*ZFS;n$K(G z!kRn{&n0%j3CHIttz2EBOA*!}8~!M}Wc3>4NdkbB*n2Ca0p42x5qzH(yVj#`jeU9 z0mO|Hhnu&DT-k|on)f=Sl+Nr?6wvQsuU7gv}2hE};mIb=#5lm>h& zh4^M=x9~i8^J@)Ra{W1Q8{rH?_>A%i8CEIS>rUv2AhnJbr-pjF?t1~>8mS80>8TX` zc1l&9&*Y26_xfKiT9FYYj|KRy^i_VbA&*NaX@;Gx`dT!x*9(akDT^p-&z_!92BRc# zEgc#(f!d7O&1&Mm5Cnh!HFB@IQv3O8!iu~lW)+lD{qb(2>c`C*ZdW#@c3patM^C)i z=Y=O}{J3yPT#SzcrAoAqLl39O6GOTu#M={Kf8TD3vkTJ>xfVD;=C}<=It&qX z2K=EkIBYnoA|x;P5|x#D1Mdcnjy7W>e_pDBjkM_Jpil`e{Y;>kI2Kk&_Ce=hU&age zYRL9~u=UnqZ3SJUZ;>K}LW{c>DefMq04-YF-K`LUTMEUBwxtl9;uLq60>vd1w-Ve# z3IPIyz@hJZ&b{Y8_xod#{bbF|nmx1k$}_UoFLN`x?=o!9-EExoY3&sjR)>hxSF^{r zA8$SoD->RUjmdjoBa2M<=keP!-doIhw`wl%aCu9A^0%m}pk7mTd+>-Y@3SCL=UOlx z{yv@(zT$n%y9ajrc%|O*F}ON(32KeL^9Oj!>s?SQ@XaXl6-UNhQaW>fV5k&qN_Y3u z4D$8y1bHI7t2&!YE|;q|9p83T>w8O-Rr)yjVdw!@&GE;nkbCNg;2+2~`jZFGYNkTw z=?$=}X!k00=IqJm@;gHbhhtN03K!Vd5{z`xWyv}=4NNEND(N?kov_Y>M>$s|NVHoP z8d8a7>4wf?#JVQh?rktjYf{B^BUok?rS%G)JOb;fWQCf(qJRi>MhTIOx)R8ZsXUw( z=Rj(QM5SjN#|MZ_pu`k$hgZ|cT_*}r<7p+XcyDjU0!$e$NCyCKYqTC6#o?l(FH_cE ze#4A319t@JR2I9qv4lo28vP+(uQKb<9l@~WPLH!!bzsRkpiGlx-&J}}G5bBcLM9yl zL20d)_v>HWiDwzmh?lGZPAdrr;fau>O&6GLzfo#%Qa|SY3fR4bN*jN;8x%|nvjuS3 z0l0?NLE#Ia-k@O3qXcPxyD`5V++_@UD$DASgQL-*gHkBj#BA8f!<$62!FTnFS|rMR-33z~1Nd0j zBtjLh$auhLy|u`Lp82!jCCQlD^A1 zF6=LRela_-Kk8Yt98-S%DIw+&{ZnrGFF&3drfo&2kPZ~XkK_&dTc6Xfj-GTQ|HSzu z4W3MuEGbk0OeR_aM8Rc4@NLy zLpxZQaY*rOwGLl^JL1JJbWLGamdnAAd_RroSMsa; za(}_|{(a5iKK;y+t7YWZ5JnV$r1a84=%PpZXMb4)xn zHNH)7*Y{6HiiMdvGmFp^sm4_#nmSuNPx*HHpJ~&+|jY zZJ9|6#;K}T26O8vhkq{)SbP}^>k>=NR2mHN^*|Q8K!OzEQslBC-}8~5*&=AnBf%a` z+IQMfh;NGsQ~zP#k(yW$r;@SIyI!?cU1fuBC%z*`DB%tcS^GCi>Hh=@AG1U8C^5vo z*R*=$u>be^Omt!2@!fBzRY~p(rT;tA|5t#_4&9-|j7@j;k)(k(wS>A)wj>?yqR4`D zya9z-tm@`V%zO_dufLwD*?GmcvJKn zA^7v^ZS|d6H?U4>7qcpe>3S}DI~licMONm>>CT!DY~BN#gzlxA8FqKMob;0>bUA^A zz{?hA3WXss{DbBh2q? zp$WAIU0f()ODrer@gAEPfVhwH+H`Es@bj93uBZ3L?uTuWnlfT;2$sIRe=BkI^S%*# zBYj#ufsbV)LteDT`UAX>ld_S|UbH&;oX;VjE=FS>A1zAngj&5sCqJE6)lHc~KJ}G& z2MS6BktiSG!wuQqc-nt{Zt=t<$sx!2OiM`O?zC zqo+_HzDsB6*?I@j`0cxBsI@`Vw*5N;iD9BcpYdTzo7v#UXSeTZNcy)l zMiCyzfW}vv-MVc)Kagw_d+@Q6O6Sq;f#n@c2gq-#0im&PPeYoLlikFrx=doJ;fTm6 zXubk@PYmyG|4nWDYKAjHqUgM=MK2Q4tqbj7-p_Kd&#zFY<_zi_c^}sA!Gaz?n*~Nj!-K{h#xL-y@K~7kh#wKFXtcj*FC2q|p zFy+neKhCb7ETNn`fNTM2Fi71cYs@2R-CUnt(&x6{7gzF4k}a=&HBRy#ZOm2&qH=Dm;~ zrz|%7Y*8QbyMp2W8Mh%bO3PxSg`YEiB#j6qv{{?bk7SB}Lp2Fn_=fdXcE%*v#<~wF z!pEE3p!A=w#akrL=Kd2gv#RaIT#i?&scLgBd&y@+alr1Aa z_fG?q(dBA(hfM8zXbNFI--qd-sNOf54{hAloemOhzE$iY&vfM-xaA=62w92s===1t zsTxGx{8AyO;XMlRqZ?o+$UhU{c5*b^tx>g-A=kW!F<>C^zAJ6q>TXNKpVI+p-SKC4 znly!GkW6@rX7%GFs~L5gb&;4iD+}j5?wW?q-S)Oi4kO#w{Q?=zOn_>R^`q-zh133% zy#;SU*YEF%H-RXLd!UmIlh`Lgylc$sS&Q{~PCzSKwR;7%&j8B~F5H9VB=Y|qWj zTARKwgaeMV+~(onbFDpR(}Wzldq=MKxoKX3-@MhsbLcZ1GphgU5J%r#&2%qMN|53w zk6!XI(U2T;jo4DNy-{yd*mzb;g!*g2CDG5>G`3oQycXnt8ws8PjG?P9E#48NXiR5D zI+I8wFH;FX$*o45^4YhO~Q0T_X6{7~QH2j=Cq+TNZyma|C|K5>#bNV-OGN@Cc`UEXs1>tu) z66myWXzGnQV3>mF1}}e&B`?mMr7NFXNk;liC1%Kb2PK_>>O3}o?82XC=7vtK)y*W0TI$Ht`$ zK>E7mPIlDz5{lm@fzpcN*y#If?6WR>R2Vi31t-)XDol)N?N$xnYvszxCVCIkIfZTW z)HiUGZ$9U$m_mtDA-Tr{9XBDWX~>!*nhmE5T!NiCFYul=l!N^mU|S(y=yi6BgwdLG zcYz*1P@(Q~k*M%0pTwotwIYesLH;m#JZ^$S7#cyhmm0Y{ znMr42OLxY>cgybIj<&aXucxh+daaRs7x?unB%1T@K>|H~IQ4V;(wCe;QGij!%@*I= zLX^PlnKmDJGv2f|C>%B(HEnpmSd&3XWAnDE9EBI1;G;9>^-?7k6J7bkB)YI?Z}&ag zo3xvl3&>rD_}dmxCoiqFq}_>c@T;aVGgpguW1hI$*Mm99oHyy!<&acF5s-k{sINDA zkXz0_zE@?CbrUF)o*)n$$*N7BSu)>M;>8k&jb;D+wN$cm;sSaPF#cj>RJh}B7jl~& zk>;Nj6s$$B{cV$!`zCCbfhFnA;wFq3EJGsNm-~J?qiY`BpBn_9wrs<6)efI$-Gna_ zl0N4t-pO9Xes)Lx(MgRQ*B=8$#Z5E`w zE}nmcLisHR6n}KNzq#P}-oXLZay80y^Z17GN|=`3amryMKb(BJs;I2wA_R%pO?wci zko_Wg`jQD36`@Rfx7bSSdnIV{S=n)g2+2@kMbhzsJ=ql)Mh`!M*f2-q65D8r0r;=w z4;d1aRWP!{d3UQLkzK>J)dvCK?&Ez4Y4r4Bu8JdABvRHE{LF*c%v#ec%vcRJ*O{VKTqG?r?AGLs}`75bhlV@Cv+|ob*PG- zx&$gT^VS+~sx6~edlNt1#%IEh_e13xkgy}P2S9RsDK%&R?6OteSx#yiMk8v~B`mSa z?_^;*%yHM44OK^5%G|?Or``Y!xYXU1G4d=AvI@lTy*Eem|J-vg((8S8!UJ$!G>-%o zQcyDreq(^^pu>t!36YqAz>}_$D$kJxqYyw8(MTXi(S;d1h+=C;MKTwXn7Aa=n`}( zD{})ZO`gG5H@e(>1SV!ZVY&6E1CQ&~K!OxE7T=rurC&)zLGf#y) zeP)8P-_<(wAn6B*Tc#?Q4^H@(Yb2uGpyu+U@YZ&DRKYTcn)q4Ju?*L{rd`dUkvhzC z)XK2@v+Psj3nbT|DK#2ye9YbTwwr!JTF)7P;VZey+L4tQkH#);UY@-xFhd4>W5~aX zxm|6Z3_h|KV=kWw-s;>H%bgBZDY^Q5yZXlZvt5SPNxa+}1)awfo80ZJWguN{3HaCog1qe~w(o%;lq!Ka#X2k&6m?6hQKz6zQuhyN>)6aC{ z`2T4pfjF}j$M0ZVqkFPO#Z9MAhL(3lFyEDN9`wwQv-NZGWhyZ;vU<9|S;}(v>9x$K zPadoW!EuoO=DnMR^ArA@6CVd4&pxdzbS{|FQS!~1MQXk5Y|tutXkWerm8gkOy3WiW zx-K4SFX8yJDe7xkxr&S_LbXUkkNo!Jv&j{b+=sn3Tq}257pO|k6W<*w1-Pl%^*8xP zJIQMeHf@<`?Rv3p`8mrQ6rAe?WzB(15PJ88o z&Ng)pY4P$f;9l6@AXVw-Z9oWURCFyF;Mb;TKr-`J05fP0d5;O1}t`B-Uh6 z>J+b?Kr5w=H@Q>AibmO@hQOya4HltMD8zK&@8?StyCKvjq*9f;4XY>4@^2dE>XF-l z(OHJL7b~NS1<^$7^(kj2(tL%y-Rs7X1{$Cu3)o{_>PQKy(|Y*?-^gd62Ao13Xp(RViX*1 z1jkOhhbVh57P(S_NKbR}w>r9{WF4KDu#^hs0zw=+FF(tp78Km~{UI$enQtdX<0*3D zdu`cvrhwjWX8+^qyxIOp^bAYIkC>Wc4Y%g^HxR$)C+~({23Y^m5b5 zv?iEfU(sfMPhe`Xk1QoH-Se? zuO(fO?i%U;?izIx^VfVgJs-XHR9j-E8QN?VqK}hnRDx=UH+fu6{a=>cW!=iY#NdBc zKg(_KYI}3y#H5wJhB;K#)q6_bhh6#*5FNluu zR|xk=D{03Q)NHP41OrO?SXSnkd`PVYT0g=6GU@)eI#Ark0VpnKJf!0*dNOF^zn0T7 zL#6p|JGWUtG%yzeVh&z*~sZe=+Eu`BkT$VBD1E_%4%5DqdvPFyS>pe}%#$s~Qkvi|_D8J?UDBls3 zYuFbu_TSQ7Vz~ljRH&1_mZaSk6^j`3o5v{Nf9~lsnkJU)IIhA>kf7qt7ttSy=&xpi zK=&$$h%dx( zgZ@cnj)ob6QoEDCysA;*J34{@L=rR@ zEze>dF7Fhw{F6zcFUH=HroYjVMxHjP6fbDX8fuLosEzhIVkHXNd-Ct|^jQs;YfUu6 z1;a(+lOT@49LnY41=a;ys*4WD&m6;#@;f!VHGUBbAIUftbU7Wv_{ z@G9i&Ela>f2zE7ecuF87_a}P@o*3hwo!aO29W%M8ER046b_xvp1f_l6tSEqJA4T6v zj-dr`1RBdDOm{<1D0`$Wjw5`IUoHduVh%yn0|pb{S`#2;H&fYAS4^k*t)$crZv&5% zsDf?Se2(yzSo*XbSXP6INA~wU52ZiH6QQj!FujocGP#z^Rm7lRSZ*Yn6O?h}B$f_n zQganyF|Hcs*p7A*>G~YW`3gF1SE`!KbE8@^oW&{2rZK?s=tD1EotUwC*SCA@ikk*! zZqcw^0_Q8uWN8iG*BS9oD~Hp3sF*Bk2gPZZXYE!&V(Eqj!)eoYn#qg_oFB=aWe^*m zux2sm5BnP@f4OggPQh@?f23bHUxnG3Bnum7{dh<+YxjN9?)N?9MXzA^!~YRaPVZj4 zflk@^>|Pu>)orch=vjWk5nHsFkdvblzhLve$gihP8nB?y;k?Li@JjvLh73@>u<-?G zxd`^E!2AEKm~CdHksjLs7$A()khhFT*2*+ePp2{b7&ie~j-7(=QAKe`*bp#%v#wxW zBpsBV5{)~P-K^_L%RRCDwl!WMdeom1vfsuCkrt4BE)YiyQKEv(W|!CZ+2@Sg9|f2V zxU`Ic%ywFioLY$A2(F7jNBFT1CZIgPbUqMmAPGc&AmjlxYQ5#CrDbdy$ecro!XimP zKN#And$j?0-l9I|N$d6B;_+K%4%a&<7?R1v<8+*k zdEiN`T{KQGUGH3X8ECa}n9CqYT$jbXUtfn9{XTlN-X$noh8Sf_MzYs=g(}{Ev0>q3 zujaL7G1r`hqz}VRetB3@NF-k-of$v=<|Mkep^zmZE8tGGf0;BCd-o2s!tUSiBcQ|0 zH0dzO>neKT?LP2Lg1ubhwt@|T@4YnUTwn0pAvW-92Xju%X{aKf;p^XO-wUZKrX40H z(0L$#IjzjRlobl-NF(hx%}i-`U$G_PfSnsLt#L24%sfg~v)5Q0MsqHrcCMmVX6~FP z1Azv4<7UUCCF6-InLNQy_res7S{1(6-NmeNun2wiS&D}{*ALn%K5s}*#2U`EcNV3_ z*=Sh&?If!8B_o`LltDh^bnJT5389>I z5p^0gA(RQ#%k0lybuQQz+`x9UCH~655`><^R5VkDjLPZT9#RrPF&{d!YE3fGc!;=v#Cf5dCv98LOWwyiIn&d?_6#d^3>(?;foaeC+FDk#X|J@hE%VoYi> z$bljJK~a#y*R_-xSdkosW6Ccu#XUO-DbGbmZy9=9F$U545qIaAapW&Xd+MJ*EcINB zHZa(-?S-~+^04E5fYC<5gsgwYEk=x%R4!kf_N1j~c%eYpz)dSzp7##lC?G}HK;WX! zxz2XVPJJ*`D0%8R6yhPa$R0GcGH187m=RB-(bUd`$&uCA5nFufEHco*d5_x4Am-Lk zrm$d&uU6dv#L6*2f7@y251%?xW{mZRNNM=WWsD(>@`uw5okY@t2Y-Yv4BPrxSP@Ie zNOtyoy{?8*bV+^1ojt4-Y-MWiAXbs|uDO{7Gg@DMT#Pf2ixL`xZbVENcsFf4U5tG* z?(yMU{D_-Uo|{tZ28ZHaj~P$~G3bNvDvi-zOa*-+2o&=@xeY4M3uNw0Je2D6~x;KUPxvFh{9=+W*aN{9?oILK| zTsAuYEJ8+SQ!6ffVFS#uK+~}wED0Ny9&^nj&z7{RhcQ?A-8rc1N0wG6mEEmVz`?fT z0Y0;{rI&+nbbVSBoQIO`W2Zy|_@nuGy~%QO)H1}MP+ZzVnLZ;#t>vray)UK65bUGey$YWO(WQM^0@dG&L<(Y5L-Lv+*_jRF@DZO6aB!c z)92PW%|i;^9b*Ch?cqIj=t~@QCGBLVDK&rdhy~!m_x+ZsvbxG7(`Tyu8Wr4eobDLq zJ-5Jj4RbK;{H?l{5HV#N=wZsT@}BQk3w5#2p}*aEllF0@b99a4(j$G-b(ex$4w2v$ z%FDf)a^d;A-A@@l6doC_qTovDMYk$R2MhQFFrkq#m?qn6AI&cAj)9r1TUGh%t$&Zs zQ}iPv{>$~g>pNu=@+S+o{ z=F2rq;^O)1{jOp4eLx#A*Zhn}g1|TT5BQrqZ3@jBj6SO#>kpZtC(%rkEbGig+cU)Y zu_Wogh|gc#Ei>li9=a-QzbqS6P1rx>Bms`(d6w4*9VR4;uK5siuwvt8S%ooe4gFrY z zvvQuoytzuNw$->j!lb?KcCRVMrPI!5L5O;~mibAAjfMKwyFHkrGa#u^)0%`G;AWznfWxu0e5al((4@%jy2L)>Y|eP_N&!bR*o{EAJAtH4wM)<89DFB()8*noYmR# zk-JJln!-OS4uAYC|1QYX=)5^b-IgZN#3ML&YU={YalCMj>|82AimP7~r02^zM^-u3LD20AbwzDyQTL5ju47@~Zn@Uq2BTq@b!kz@$Tf>9g`ettYWtGc0-*_RFXH>Bh`%BmKjA0qBFc;(FQPth33SY`x{2Iksonc~2z-8ewPjZvFeMm23`utq6@^a}9 z%sjrb-tUg&qAKD#Z9x%C^{}Bc6KV^`xBt12^Hk?6bZ4qmi#=gFMp+uNYK07$i(lpA z#k9NVe-0$oL4Tg=R02hbVzY^~e0!iUR4a6%WPh&M&eUS4l@j76BoFKHc3~z`535VU zn!ad_PpeJB&xcgMaIa1BDH>mnjb=b7Yk%@9a5!^3dEbygviXNVvcPuTJQDT>`Tlj` zhPn2JdF0~qdf@3S36nkQ$dG$5PDj0}tGo51q})p|WN3oZL>P;KMm4MWW@uQdifXf~2K= zPdl?H=D}wc699=rl-E(?4x$UP`BZRm^hEAKKWdG0XqW$iKP4d{&JVH8oLr-XjM^za<#_cY14lA4;w-+P;O>hBZ~=L-vq+rJb7s~t%*N#W-duH!Ipbu>%o z{Hq6#B32KFcla$`+(%xp;BG!Sa6%$ zQsT%Ld}BF}byyy^Oq}065ez~Hy^$6?407_gIdn#(W$uoH0hU_l5E1oUnqA3RZ zDHcH&{(Mi-gsAgPb(*H(m~L@#BF`C9k{W}B1!;Xq%Bzj@6q1B}t9(qyk|Cdv)}@C~ zB3D{exs`xabnim3e(g=dmCSa_R=SMAf=hMJ_dlGjqS(R=6x zqW|ManR*v6?)z2F4jJye%sgau5X*#Igh_~L7{_fn_}0~euM0%Zo9?7vF9~`Nf4p96 z^htWM_F|+)^K1j_%CIibN}F`0y5xD{iG%b<*4Y40WXPU+L57iCRn2>NfOA3_D1X0E z%?MC(>M?lr7^-^#uF7(yj@Ne|CR;n1S3ZRUAk!3{NHcRTswTo^xxbF zQ47}K(IY74#A`jvoG#Ezx*e7q`^fz%JN8n5RKW*PvSw|C6yiOFJgx2PbE6#3E0Grd z0}c2P{rkN<6=?w`u&kR)=zbSpvmQYxB_y15g)RmfUdcB0bahsSg4*V}F8Q?G9tIHojfQQV6Tj1I*c&P{N&`>kv-gbJ*;~4RryV;4>&6N z#-XW{i0+zakSQB zJwK6P33?GLcu&+m`Y1%9 z_`CHg_QNYr9-gOko;(9lkUX)jJZ~NweF6cxaGvXP%C?4AsJ`v%RV8I$zU#V0f|T!K z57h5V-SeH8IPvdKUXUc7F|phCH|VTqSjd%07gL%_6!Fn~`VgYbaQ;+WGz<~(ZQg)0 z4*+6(UGr!_=k6L~X=#a<_W|;Df_BNiZ$y#n%O$jW(S4k2zHv>G==nGGBv?29GpaMlfHi!8?beL1zewXRjDay5(o9wfMX*!JN=OYXS~y9{;m8voJqI;w&`bBIn}wJNub0ZFY0BR$ zkI1Y^|16|by(}YN8mMBH#t$bO2%w7{Q=q3~lkwzu^(JzYhJ2m*r~J#3>OCb6XZ5{@ zNiqED^9j)cI(4?uBk{qT9|-Y(;PiUYJ;I?z+2g+I5gE{2>LpZgISM*;*G(cCX3SwxBGAT1I_|;De>xQ<5R9%Yf_xc%r5Bpb5{Q}usUD-X zC1^w0&W|eY2t%EM55NcW1%ZFc+A+!!>0+_cEbB*}0)yFcGos-w5mV{s-#5OUvc3^C-BzuF zf89C<glYTn~NqQD$nxZ%HPseBX$-pB74Z*I>$S?XB1h) z#YX7R&g+~N1_|e8Mvce%(W(uLJaePk)yb)KCYp=yq0^PhtzFSqPg@}w41^oAWeMp> z=nIgq*l{8svwr;2*dy-$(Y5X#sDfX>RrzV?$|eM(SIyvinY1nOuaD)yLkp*f==trmj#@0ao)!d@ya)h~#GEDm+< zogPWD=6_GtLKKZE#ZnAMgG}%2n~{{lZDI9zSO&O`l{z zqg?K8row?|l-jr=5da5)Y%b6S*|W80EE}MooL)w?1}&UxyTP{tl5HNAXp=ZLiA7yZEE(=5)hAjySj46i+N7sanbcuI1c4ah4@?zf6pus zS*xDV;6ov?yjjIRSO_yrYtjAEq)8ur?wuBJesoE!=rhe%3b%Il_(= zsB=V=jSj> zJAbl5nuq)jSH|XcMwrrgO*47PWu+m)u|@KUZfE9cmI@3O;^%2+!f%Wo`W6&^e1I=t z{k&_u`+8BSB8n{GQ+OIogBwco$gRZxw#p9BZk|L_8v8<3%o%bzNe2Lp|hcecQ4 zxkURnmtkJ+Y>z@6lE&iP9+t-n>3OQ+8YTF(%(yx%g_C#9C2+9sdQqSAmgymLmsr2wjgJDxRcnP| z2Zo#1VVb$|LWZUxYui;<&RrY}=j#cLfoW2D;cDO^H9Q$ z0S8~0mM8r6(0HlZX3ZSNHdHXd+W!eY*otU_%A`CzcT~E^OvWP;71t{BJ8`SlLNt?T zdQ*De#)RG}8%J1fGO(C^GsaUBOYUJ{8h`6Yx5}_b3=g@&ekhKvLvwYHtd9cv6$V#T zT(1~E4eXOCm|-w4;=6)j9vgbWn8Tgr)x0!?AR!IY^`FMSFyC6v3sQfZB_e;s9hUF| z)8^=n|IjnV)sIOjJX%r~lBo-Vw}yI{r=HBx^C!L43}O#K9A4b6eqzRzNz9ZnfGWNF zbuxyd^ziOhmt5uoF`M2z*qAukijE#oqa}JJ)|daA_tL?el&2HmA!=89G8AhC--f|(1ovwaF~gdX);j#15rdt!F`Ne!rtx0_E-{BGS9z^c z#nl=vb+6cPGlujfK8;E}mlO4O!yK`7?LgVwiTJk-q zcZ857GIHsDpU`SKadZP)l*{4C2Nk{CX(%1rU#|1N!WV$3)aI;R$${7%f`U~UoAD+K z=u+bAm4sovnfdcYg1x+u8Pnl{N@w#KEx|?!hMd`?diIzZ&xYO?2oh1D61Mj;y+FjY z2Oty>LKQaq^UVCPz7-M(3~8z;(fm_#zbQsFeI38}93tXSxo_OV{6hd@v0%(KMsQtQgjDiT(pT{jriZY({@CE#`nI%2 z3u+v=9hQoi8iO^K3WEUX_2;Z+o`}cUbDtkx?xzGNJnY)>TAYth420YBPxZ9{9NbNq zdFMS~uS1RuEGs?LQj~*anvJT*_~+_Dapxl|`Hhe{>%jzl7`DHHdF*mIDHy*1Vfk9L zA8qMzOBS^8cll;348%YBjM?4f&^m9$#h-zl4Wt(P#6-R_Ddx>PNukFKJ24#%OtJivv+1)pRU@8)cqS3!Q&N@*1@zJD=PY_4yA;l0xlAFAsEbWc1qkK}?V@TmC* zSM~Yg;lGFInu-bAhLtY!O>p;h;AM|T)%9g!#P*9{dIIbYZq-g=lTd3p1CFQd-+rqP z>eLP_pIxTFDBP+^mFv~R(k=INEjH7Xm2$lb+Oz@^A!N+rOw$T;3k?Paw3dj5RI~Bw zWu#cmT>Iz>6_zab^S1;6-Ms3UZ1Z{IJ0m%K%}=B+$C;ZBV6&7Tp zc!L!};}L`O_Yi~5uN8+WUh$-kK?R-IT-QO3s(|5SS1`C*r+J^IhVgtl!_YWWe|FrP z;mhkhoVDRazihW`-9;^FpG;VH$7_wFai^Mb^uXUhm{CES$Jpn~m~+*}4+Gbs93HTK z)f5u+!|uBC)y=X%!^LUCnX#PyW;a*n(?&T=(}kYI+1X-S3G}&K$c3m@Ze`&0`E5<_ zv}0!Ab*3L;e-w839ySeg8=p1|$-JQo?9VZHH8JNpWUTa9y1hFpOMm8b{oveZODwf+ z)5llxRtG>B%%e6c-VrP>2qV5X?EYHSX^nf;46DnQ(krFibss{o8N$^J zW=C`OwBB3P?{4qV-n=!G%9Gvsq9^-gUs|V4Gu0rJ+92o9bpL6Pw}-vKqN#MnUS$Wf zplfGJUvv;}bmsiG@{L3Ni_7NUqtN#jjZMKwY?w~ha|cyekK4@MSN)4_JAI6xUkKWy zJw+aTQL_t`IKAWc;`Z$ZX#=FM14#a+~}5! zeu$^3NXwXgQ!+IFsY@W+-*cOzpIq=9K(gz~(J{?8-S$xG$|OEx{2Wu`>S28? zrW%nk41{8?lY)-w$i3(1O+5RVE^kq9hDERb$Jw;Gwa3!X-0i=B^(tlT4WZdZ^x>fA9tbr9OOs#MACcZ6SEW()u64o z4x>#(qT`l<))su}jn@i8fJu`Z*X)zwWs(syQX)D;T!QnjLH75FDo-kZx^8BDC;rj( zx@Mlbd50S>brR6?H8*)^_*sd0Jfe{EMci9~x4(q-A|8&QzYcvu7<@+1NcTpSo_!Q! zBtdsiT7DIqdyIitJfYhc?35A?2fznI)GQ|YAeuwJn4_=kS&F0>AMIaUen;_kjEjou^CPu&{(-U; zAs!O_k00PvdJ^=W9vtf#nJR94V`TZH^J)Cr5v~@W%iq8MDfF5nF!h7sVXa$r+GBjd zd4F}eSu<`urw{y3QspGW9calw@dI5Yb>|c^^TSWJDd6MT{1ts1oPw;%&KN7XRC#Rr0uzo_V%eLF=-^O~3+XX6acoFZ z-|2e&Saaml`2Ioby}%TLxZ_-b#*+GF(Qi)_5FhJ*#w>^fc4kq;8+Q30(eKwpmM;nB zIUo^CB)legcTFcMnISow83*mZPV~vvKCxe?gNj;HGBf*Y@>XZo2DYY1gG&(DRM$E9 zm-hZuVdkGAf@iBj8uDOnTefUN9d}u!Ray)w=pXD3q1z*~QIc_)CYw=}u6vevo`2v$ zrO>%Z*kD*yu;kHs!d-%4yXOMiB&_`o>O@eVLic3D)ccf*~=F z3SlZtriQ-EuPUXvIYKpbRM==ux;|Tnyk6_ZGH`7@d}8@HMgfc7-Y^lds@I@|bL=!T z^Y?2+*d|&)Jq=1TIdqJ}`S@yO9biM^`lB->^PR4?x~{HzS)qfzN5KPz=%4dhax^VQ zarU%U^r*j|Clb4s3ff6qa-1Bqq1~IhD_3h1haUFCI3_Ru%J;^}rc>dEa|_iR?z-Tipzl5QSg!Y`fO$8crT0$gy@lR;3pD`(1PCEFzQ6yv>wdVb1%bnv znKL`d$*h?@&u$h1S$Nx;|G0dnVfx_}qG?F!Y1hJ5EXP*;p-oY8r7-tb6SbYS^oNZ0 z?{&%IBv87Y<*Mh4@W8p_O~O=ejSboj(TvBiRov_22ZrkqCXS+{b#FJAgz zake>Xzf`Ou$aYX#@5I2TZq=1O2Pn&L`L1A2Ukus zDiiaX@v61bynYM{Vk(@2l(xO8TMoBOk-6*SpQvegb`fAODY?SjM9 zV_V3Mfb+L~?7dF*dWOzloY&omcC!Z?0PN6%r=-0@IQc4B7sFEzIo~5FUH&!0 zW-Rf|@Ar~cI;QEJ?#hVlX!qEYMbPvGng1NcmDI*dBF|+xDXXLwC6Qj2tB1~SX13%x zr@m9Uyd#m}Ef-2aESuu2C|V2t8HM>3v8C*)t#GlVsocIz$5LNZEX3 zJwG5A4R>FeAV#Nmfq`-z*%V&Z9{la76#)J&N1>Sdhc?;!Q)!m1xj{r13B|OsD)oo+ zs_iTuG5cKbJtMWA&xSAZ78-VZyDkoJ14*U20*q_>837%o8EfkKer^vZxT38^AFR<{ zp{BfAnvg;=H;zLDUd#DZ^|5;ROmh{n&|&IUh{m;t1uO9HhRk7I)h1f=x?uy@ZaHMX z6#9{Scij`{vrJw3*On?_|DNl@F({tH8^s4Tfv`NpA%h>wuijs%eB8*sd z_rG_ag`Z)K;TF^ItJZbV?nQ0?AWQ*a5n}VuGKTnATKOS+EIrdT+Y?%3_v2QUZwJ!` zLqOJR>lpoKPxmB0=F0Gm#7S3O)q)7eatVDWT|Tmu?%ghSX3>^qkI7&k^}f3QiMo`2dtAHI%SYwN6(ewLcsek4A~nq>dg;OI*{~#{@1v+v3aglllI5{J;ps!0PIjxbUJ+ zeZnn(!J|xS1!H_Uj-HfwYj}W3w%_2mbu2lby*?@1$kXBZnT%i)l%V|Hw}|S zAQN-F-67SI5ON#->XMpi>DQm8O!(ekIEf>fbk9_A^-n3|{gs9uY=&nxYCKQiJ%YF* z-dw~)84O&!8^fhl(%f(BXi#AijK6-~7QlJ0>C? zk>*3;7rSQ`MgWCu59ZjdCs&K^4;Rn|!|?nPeoT!kV2Hr%WqLL;V92+MtXU;{`(x5D z@A$CU@P&~l1;wXT6Q=AY$>g{h`OdSJg%>7FdIZ(?5{Wb1fU~vEX&hQg0@sS7^@+%_ z7s8f1rny@)@*VC`=PNLNnwD*8@S!cT%ZCP7Iilt@{d>#~DbCGuU!=vW2@JD8jGAew zX015yc5AC#eqQB^^c@}w8LFRU$lhw4@&AH;ZG1FuO-C!Tr<#=eG`GU$U_t*h&AwIF zt=QhHrxGV{gU9qOm6g~?5lT$Rb_<`eg5v5Z`(T)+S0TrSDFw(3#ki&xi`Vu39MB&R{CFF}!9qsC(G zq!WZ!Rg;9uNZV9=J_6zH#EVx0FK(MFV8mWs6_OaGa=n8_r#p9Mx(qr87gBFr?T2Fr>#nmkIS-LD*R8A?o)`GH%?g<>a+_KqWmY zp;H)uZ%n{9R+`x+*=aTHzG7h>D3)yb@_qse8?J=fTp8;_wGd^6k_ z4vM*C6gCEB3Iq6iuTMV?spFeZ|LYBruSBXivb) zlLRKIlwVbHOBTKO>fOiaueZx?1%z))ND#y7c*=+Ej_jbeLR9v9SsDSoZrwqiEt<`C zt^3e*>$8InI~Ks9sDsg=9n*y(Siv_zgfQR-H|$gwM~%$Hdw0!=Fz>jr&kE;E%tfdq zDS2RXqPo}A352aT6Cm14Z|oD`M9AHyEJCfU_7mV=tLZ}o^JHl3AA`+ObnSB*QCrsU zr-*NmZqKSQ3|gl}iK_b?ws3GC%vK(v54CT8GWFf85!aIRq9hM>O1@#uUQ_S!bP5_9;4&GVp5t)BJb9vBd_yKWb$e`*L zJZNo6nPn3^nkqha?``nc0-+UY;;hb*!0=(Z4!#9ro8K!1z0gatkllh;mI7UN3EZFCm(*+cAa%W+ z?+UogwcP(OPC>cRJr#A;9bza4u5&r74}s&qwyG@5Jsas~Dc$TEUFD1N_*R&CA)4o= z=N_RlCA-&?;BI3;d{a}?i(bkTu6qBx`q$x#+&Ot{8N<7AV{+?YI-iz#;e zL0H-|eJ0E}VA2H?XG)k4!nDH|Y3^h$9XB@s4XqDXuY!BfaQv;g=^_F_divH<-*Qb2 zOj3SzB7bAPv<*dV;WxnYIvYo3%pXGD8>Z!}Qvx&30PMU5$?x7^vyzZLUyUcxP zmF3++^KrDsUlDRYSB)|j(PEam!j)*vk{4iNN!8d`@HfrzFXH|g0u{-R;kFK!jh|NQ zC5hXXLpCtAXCZH+>V@l-k_O<&(So!f#JP`e zFw3UU8SGsDO|oy~Q#dhNc=tINXfrH53kHw0_Z%~8AhI~p&0oyvQN6bNRcxO2vRWWD zsXSkd$QFJR9jZm*ryK}1f_?sJ+Tm)SG~bivxUY}QrLE_mS6e1s@+}~ z*l_G8IRxH!uc|xLwG`?)mRNg6ZzCtV6qf%Y1_A!g-59}r9%~Q3F-V=BzO-CO zo^8`?oU66S{^XPwWZ?@yK&33g1ivF4H)AVH)+b;1nUojO_-I~b>C#ag6 zp~$c$g^V0rYM-!`+UqfA^FV%qR0!)SGQW9^zMw!TX$L&{uns)mfb$@#j9sTYL$SYV z04KGanA;z#Po%l#c}IRKe@GG*@Oja5*v_U9 zYyK$cZR$$XmIuh=TTX)gSUm4ljTME$CDl(Az@n{eM29iEN^dfM)Xorll|J+Cr|I>J zXY_Jw#w^+Z5*hcK4*XXM8|b~)<1!?b}AjYGT+P}C7F}`ePK0gpP>!^68dU& z625+UIkG}%x4+$k)ON%PDCkD<2;UAG!|GWaB*eg|fLr}v-53(a%FVqR>&W7ofB~_wbOT&UnkGZan^Sc^YVUCW`*&< zx2gD7vf4!Pd{I{yO4m4MBSzy()-u!P81JU1A@vSi1&L3;RLutc@isYsM$V+&ai-33 zKJ#c52KtYF|NoxdRBF2p+wl1RJG<%dAJs-m(8X(=hP4ol6nb;UT4svA z$!PIjzoR(tSw`c?YA3h+$-W=ja+fA(aY{>m2WWKqp03N(djG5^Zc5SeWx+F_HjM6( zp3875=O@`RX(oRyuLo}yZ?aw{D%4$qH1~>SDzCi)sMdb!+mA#d{$uk`ez!nGy%*$} z&pcaTSx+{9{{;O1!udcD9?q{lUpdRacW{TpyxgDq*B?!KBJtXp-xU?iW0vzWZFec7 zY7Drv{&VxaTJgD+SRqT5h_wEUjN`2X2Qe|*NSezdDcIT=TgK>dk;dz?((AF5m!bn( z7LqPlr$NWj-Gdmwdqike`;n&zv%wg|-&O22AY-^ODdySP3K@5Hd+>Y8pSE?byAu*6 zl+H_JKk4ze9h?qxLK~SmC+6ZQ@Z|olW%ATZAcLwQfmIq4>H9ii{Po?ZC>cWK>Hs8~z^9N;*}^?_5~9@>fs??0f2+4(~6JI3MRs zoe(2*limYcmG{LUWLRw%m?%C$Iac|iuIe`a()>+Nhs%>2agUA*XLbfMBHFQT-3hj< zy4HY+)WxIz!>{LYZ>o6`g`dl}uGf_Wuf$voci|t&4N=4d z(FE*Ix3PL&#Qw<`yY9z%1J@~*dbym%!b*m`B>xDJ`?ZP@-S;+F!r3I@EyEi~` zY`WT#F-M?W=&U}gRqtH5I>;lxqm$BiP-iA=McRKt@9*W0^vkc~r%J<&+8}w~s&}D? z)95SZ3Ff62Sf?OzT7?@safkM6y`wdkX@-`on&-=}TdyUeraxlk4MCggPK{2QATXaI zV(#mX1l67w_o#$1dKi$F1N<>Q0YoYJi)>k!Cg1R`_@1n`h+&nJ#1%)^sg22;3@=mn zr=2cMj*BqTcFiI1{fTLt`fpZ zX-Bu!T~?V0aH`K0)3h$tiv7~IGUa8>A?-I64BNuuP61J8&stCL82-=n2bT_$=}_Li zoC6F(+suchYFQhMzY0 zLq*DH{gz5x!J}vJ>SL90Mv7Z4p9N;FSPWlhwnja;E`6H>F2dd1y*e!NaA_O%7zT;f z+j1VM=uvs?HQs#v2IComZX%agI5ydaCRzJB0e*CM{m)3u8@oPqq3QY4I_8*M?qb-fHPFI z!3SvW<2x!R8O!K0b*;}aA$xG5tA3e2$5oqvnq6w|KVu7)k0sx>jxeH@b14*n8}I2T z_=K));@;g?7*E6f{4he~zdKPA&+_XY$}2q|hmAsD$h|HkjxZNbG?;|X)`&A22)b4J zR|;-~yHJzn+;rKHu>n%~_WA1I)`(_fEC$K_)q{C-D!*)H{x3<(o{X(-G2fKH&Tdd3r;;xjYNC19B}(A=pO zN^Qe`3Nx+&wC8k0`l1_^3U6Ws3AUq$kby)?;4KF7K zD6~~YA1iI{!r!_!KaSo4PQXq##0)3I$2V4P>J^ilj)}k@iSWul7aqD7jLLZEt!>WTWqGigUlH`+pexR_x1d|?dVH3W=kqK{ z1&^r`ODMCgNpC?Xc~NI9sx>ep{;x25R~xxUHm9Fi>DxvAo=`b)amoieXS3x=ER5W& zjKqoc4i0o)6uQL8J*rud)=3y(Sss_u_F%bJ_2-&mi=iJM z7)5`<8QVkV`e7(MNQi@MDBf=9vrBv+{mDu4*z-1Wt5LS(S439p(nFFS$q_gSAu97x z@q0}i7&N~K-?gn@Et&%RJa&cfzy6C8Bwk90FYC){`UE(M zEy2@##Fh|Ztx)={PZhet>4D9Iyd>*yY1Pd0(Wx56`)bQMkP?Kt&Ekgz)^Ul6vV^8x zM-j)%YN>|PC0nm#j8y)_Ox+Brw2jyjDFh}!?BxDya>Tl-by1Zj%Hj={YsyhPjL4I@ zAg4KqlTS%#WvZSd)~23Ng;eEnch-?A(7vpF1Xr(NzmJtDgpV_ci9=(VU>6xZyvp$% zu4IymI`{8LhPoO23bSoEO4f~ybi2JZA`(8ZmBpiEDX{I<QN( z9G~Id!xmUWOSv~$#wMw+@QdQXbngglG0-koIBr}jb2{L$X|2TeP_n3Q0}IMw_@iFu zK~(om`>ge|^En!fNVmL3y(`m+mHj4S};n%9x zC_)4>M4rtkg4*qxkYh_NqX18ie%VQtT4^r>qd=xD<%0&@oEIr*ADVHL9)#H2afy3Kt%jJVuCm!5+cboKrD!at#o>ZP&#JwZJKfD1SBvyTN&gnnL;XDK0 zDWGt-Q3_ha6#M$VBeD?_K98K?5#M}XCoWjyc4R4i!B0aVCI%NIE=*eicMN`2xvp^w z4QOZ}J|{+H$u0|Oqu2}50sDu}<^O^Bw~RksCg!x|Ig<$fIN_I4zsjfVO#w-d-E35x zuqMbV-fxL=$5m^v!*?L_)>cWAr=R@FT6lqKzi*0h7YgzAw+V%6eGH9xIYgC?)`72C6G z2Ju9Cv8rT_l&J}?zKH3=TPc^M-N=NIv)+8lMz+1MgDPH4dqBb zK3E8F#oR~W0K<~dftIXo=}k(dssK~D+NzZ+zzLtjNZH#%1>Qrxd) z@ON*j-Q$z{6Tqh8-jS)7R&YjeP^Pr~X4~rn`Kb(7!-|W+q1R%fHio%wYbv1E-$}1^ zWAK96)XIB6d=@s#)|i&Xmw{`QDWx0)<0&!cSXsXWVk? znxWtLnUOrNM}P6n{JJw?$s=66^18hDJWB+$k$ucZZuYc}q_Rftx%u0ab>ifKh{&_g zNQv(mec=k#8ItjGX9y1CA*Y4~h8#VS{e?I? zw4W9jm+vgZo!lbNz3%kB!O)orMj2g8abJc9nTwjF$a;mSvMoo+D<;fuiwo zl_4(`^zNzXfFqU(GqBBQv_v-L-O0OsGjg0Lv<{l}4uVFcWnL%5NT~FtrEKt1FgRZl z$KgeM#+J+8HJQna9#HAAXAXliF&G+vGpmr?Z~+N$YP&KYO-?ychEmG|^Eda!4p+-q z&8`}<4orVXsGl~|qlwYdZ2#W37 zWY_nwJeSXxi-NrNRwJct^2rPTa(M2AM@p}$Wt3-;&lM=}?sds{tVc?Zs4?efkuMZ< z^6tHn@yLpl7I`THqyHjnU5!dd@Bhh={+ks$Tfo7)7cAq^5h-nvPhRks3OO0^d{0uw zBRx{uA)mbHFV*2>1n*wo%L7?!jpOu?S}N-4)+dMR->j|tY4RXH4n$WoD9j6_6t*4N z0)u^N4?6RLXrUERntmE7Wv`zAArJQacN)xdnd5tMPiU3nqa%ZSS-T`}AO1lpOQukK z?mIQgY|++n70g1sAWD-<%~^PodOC&cR-OIG;LE0KF{I^QL)W4&{VaE2|NZ*F`T_L*Hz< zjmwjDQ~Lx|)rn|T{C-m)94xGb?lob3=CCEz^OwNCN-OdAHwJp{63u|&^4>(}UA<>K ze7|NM*f05W`YJk!U20uUkmLs=K-gF_z%DOQD{BhY0(aQ zS)lHm`DQ>2X`+0})E-sumB@GTdD#ssmrUgvq#`DfE^6aCkWl=_GhJ-jlTq|4D6h4$ zP+qCYgZGMWrmvXF7UPVhM@$wZ)7sRL7y5?Ec)XbsT`ZtN%&_76Y%4bF=bJf6{`-|^ zp+xgC-D~f&ytPJ;&zAdg!T{)0h8fKr)cl!$J%=Hz>9}xPo^4xlsP&e0|S*lR$v7Qy1Fk{-N_G{`@#!D-YkIORx zgD1 zOE!`Z?w_ikp1I?02yD7S2K4{BJwKT%db`g$(N6DpRb}x9rC3XIdgjm(R;DN#Fu}n2 zRs2GE%j$E>I!3}apr;f^wKEYiuidy&r90@6FELC5tY0DIUQ(OjYhq9X%BvFbOQ*ib zr|q2End)x3mX9J~4J>4-&GY&kQ-<(M+iB^|s6~h#l_p?YY8mjQv2ylT)nryC9KD1` z016AR)2cl$_4%v&{$!4M^6ER(tiz#IAZS)$E2$LI4TUU33_yKj;`Te8lc0*JuRiw_ z+lpIq+!6l;G59TLbPOWP;~$-~j*v+f^8!0Rr(YThVE8!IGN0y`u%fV~_yxA=)L~sh z@8z85v>zxg!QBqz2FVv5*byis~@JmOK%Ix zKg#6lR)-%rQBA{T#&8~8Ot9<4) zf&W*wCLN4@%jkqS+3H@iJ1DCa^m-wGWm5bdJf}e#D+q+us;f^Mw|K0|7bSRLqOOWJ zCLXjd``438<5Ye0+eBwC4}xxr?LdtL?p$RvK}gSsVmCLhzG`gAKbDQKU%q^3P=`xH zOJ|IGonB*zuw*UA)D)$xCTinOnsulch<_8@7;`1s>f;fjxb7h7SG6-zh?e+(OPtfb zP_<&U!3;jbj>}(qRw6!%vFz_VXAJk>T%1l>XHW?N)#Q^ms0fSpA0Q39B&b_NK_c%E zL@!#o_-FDHni7#*3De9T+z}x7xRx7Sop+FYPIN=l7@p}k3R0z&XTE`bJfA^B)Pe2X z{ZmiYf~vA)j|)y7nbjnIWyEPY%2p=siC~vNN8OKGW+t3t!M-7>P?@Ag<9Gx>#};D7&`kBhI$9cYBq_ON@H!ep+fnS~w)2#EWwR2l;~3 zj~42vmRoTHNY?KOR2PgNey*;i5})1>D(;;&q8x#4?iGazF@=r-Y%6Q8FHG_>+JI{Ct<`otw)Q<)6*tyeAdakcR45&PsXSWw$P2fh^h3|Uy(htuyaNf ztaI7y-u}h&v8%H~?a{1(UTi>`wHmZD%RJdE@W+WJdby0{h#(0mY%C@T?o8LxlN(N$ z*j>&L*wL<$2j*e3;h6%!vgvJf%#{3$m${=Ca2H(buK#MQu%(evO`lB_Ej8s^Zr70` zrH;{nYPT$r$~gwuY99pIF?k`u%LM#!LAWl-i(J>f3el#ZFv5Fz_)2+4-Xbl%n${w4#GW>ax&#Yd(%zMKq1*KuYje@oeSa!n z4&GNu*`D}B*N4W+oZj|oiHze_+*xA;#xp&~&Zk{&u;;V1KOH~`Wr%MZ*EJLoP=pPQ z)gOQa+$tox^e_CBFiJhh82|74{5QALio#gF-VYiAw&Ial)P(w>QR~=D?YACN^l4G; zT}Fs$Dc>jgj7#5=%n6Vfje=ei&8{0O-5rX*Msrd$f>yFL6=0PD5@RO!7RjhqEVnZHAZS&lxa2h~N9Iw`GvgQ1 zNewiv&OE7CFAMc@jk1d_^!XULLg$dbOIse3>gem%GC#5r2^A34I#fYbLuvE3#l^~4 z9%oxc{})-mja5Kp=w)2Y56~#xC2@?xz(y54>jSQ&h#O#~2$A|iBw!#=_!f~1ZK2oA zX91n=z!#BU$t6X#&}$52Cf7Bnv+UR=pKuoM&mF8;fkE;2`jOqN1IPIr{O;GsJic+- z&92h8aV`11Ulh`IYGCmePvjNpmF{qpL)p0YK5GW_Dk(MJ1Ac3BtE7vSr-`)ZdIe;~ zkC8WaUM}O6QnOzW%>O<6p@vwev$~;iB^~a$nq7NFJ1=`!i*_`&go$%|g&ok-;&(!r z{N_gT@pl=lHvw|wa}2j6Qro0+10cooRJid;dwoyO?g_ZM z1!g-ljFbEaG5$@{MCUMQ)Bov4)LrP{gmptBTLO8Jvh>$%CbLnYGCeY;45jJb%Jr3Q z8bcffgRVLBh2cvEMO-c@;#8E7RLv4@;Ian?5?Uy<+*Ce#XdW_sBP)&3ghC?AX+w3v zzTNgd^44sW&&?)}2|hx0cIa}6ui6-YXzsK=JZ04*`u=y)0PqKQg}D+mfM3oK{%p9> z1nM25{bL!8ee)01mjaA2e<#zg->Yk??SQmUPAksk-W|^6vuBKac0hutPW-phG@@HG zAjt6MzP_%}EIO4yTkL#mDd}!9^C5$S*2Q??a*>cZ`X=o@E=F&m(mD%M z^Uc!^K2A>z9>c9H7zxko2lDIq!lM6+WUmG4Kp|_DSqMXxr&oeX76h+{@gsA{640Fc0 zf{C}?VOV@7wol~s9k_HU4XCRN;wz|~@!=eEM9X*)70h#_#COAY6Z;V48VHy`KVk`O z9qodk*e~4ej%f9+b^r0!7CfJ>No-fu`AF_>C0tN(-OP%RJv`n-cCv~d^}hMMs;=|D zejRr}nSp@n7t3SC3w|$ip<&@fTvm`)^uq#Z*gCf2aG9XekHQnVc5%)^sOd*>N7Nko zN|>5*J}w1fS<{66HUSO09(s9Z6zY#?QMf_WMrOJu+5_|4dooioLrfz_XE>F_6czcrrG5)X&Xxss~X~`YXDChMXLrf|7 z>k=&Ew>p$L*l}L8k2*ql^_%-D0V6I>Xjt_+kbvbiFKh$a+GzNhv1$ zO*1dkY4O;7%rF2ku>UGtcW5hx-8z7c|A-Us#bW( z#L*LyD=eUHBhS3?6H5Devk-?}q@8ks#JE;0dPOhxenOZNp)G|4cxSAD(JBK#ABX$; zL>2A2fMU$o7L63U7TFb>%u5F+TKs_3QNq6$?v@9V4RebQ=c7)i?d1zztcbI!v~?km zyb7-y-}4g zBO0a&_RrB#-+R?Ygdalgx$n7eOZScX?&>bJYVNtip63x$xfyVMs6-vC-+fQcD))$29u^|IC|Ksr2Xr5zGuUvVL$c%AFYPjti1 z;*9F%FbHea>8^1&4ol>D8Oz=GzYmrXyZ&QZz){~iY#lj!#4WqE(FQ)L*t{?gTaQb* zpb`uLXaoVQ{%tV$LQ^Tk2R{S!b{S)Ro*gd=AJZZ-l1@Hce*tShUO+|Srx_|x3hpf( zoSHejb+&8e#^)`pi?skh77zSbq_0ClaGWp949)IOTezMpA1*6=nDhZE2aLqamkD-k zgZ)IL{Cr{1B^5n)?Tn-p2UNWfR|q#@Oe9LgJgv7Ifn{D>HvW53e~TOsIVZIoAb#YRpgB04og#b9u)h_*l39 zouTn$b+b+P2#9Bh>=w2vCN(KzLmL zPvN(Ahw30?X+)4+e7f5VIa^Mv1pbTxjz z>e;G)AU;Wq+z)d>|JAWqv!omZemj=sVZ0Tz^OCet(CjXw;tE>ES@ST{IQm&C!5}$} zAUUfF>k7P3ANAs#oxpFzbk?2hAVe?-x+fa_nsLMI-@iKdmWU3z``VUGt?5E40-;#Z zXmE(!ry%I88O#h1;w!y44-b@cqr?A%URajX&X~Y@>U0j6InI-NSVYTdSwf+sZD5qh zth-$~t=@s|0WyTdzL*>k*H*q4+K>B ztIT03pfD~Sh*BEL>_?L5FApE7Lk!6|Hn?>WL&8q8hb3%Foo#_U*>kH*r$KUu%W@AU z(^l|4on7CmK!H)nCx2E8y#m<<_Ezpz`m8uEqg!>Bz1F&S8;mP_5b=L3Y*#sDywYpsfdP5TL{xysw#rB z``^`YQB_P?X#LadIb4(ND&y%=iv^6|D<}M@6)CH-@s||9W6K z#pp?Xb8$$%z^m4J37LkfG;&G_Z^iI}{=fC(Ie%`h0xpi&%>KQR!)LaY*Nb5Gq<+m* z2MO!t*{#YRqpoSA>T^6I9aS-)`-o9W?^%Z;0RljlKe;Ff22+-sO3-6{ZG6XOQQC9_YvzOV=168v?+2d zD?l}65SqLtGH9vPX{pg}`J>&^1HSjGe(0II?gf(oseS!Wg@IMWL3sU;M#Ebsj=Fn= z0DyJapjpCTAF95X3qdefPcdlO+iCgK^OJykbUnrC*G1xaaDuzbqSD=@ZZQKzzW;4| z!n)lN74qi_<>Fb-_o89Qhb2i$%z#Eupz0rZA8MZHM&C(<*ZBQ3*F`k8Mb4Q7%*712 z{#%$`z?_%(o~YZmKQD;;ZX1Mt5QqZzT8dS$_Vonl2*|JqxZf8LH3NKPz)t?8Klf@As+zk7w*(~zA#!Yp5y%yUq{H;OG3{~m^@cw!OChAkAIBh4op zWCCPqZ%>PxdzKMBb5OK(RJ0dm`7umaP-V-$;lR)=mqujz>|M!lIEN?~KsSpuj#iOm zU`22OJ->b3c8(RnW1eHp#x&GY0Co;Iao*Ut={w&iH7-jS%h{pJ%o8tJ_!8}weZ=&F zAN4%h!UaXqKZyRV>o2>izHnUI$WLLm+;Nq9y|gvi8;&Ym2i&eIzBI;f3*WbyRV$78 zhq$|}&I%1Rgd=%q4+iTeA99Cl$|G&(Xkcn?NlVYN28bamc{Bt z>6BH+q}4&ge01(SU(<|M+T8WOK_`fJW{z9U_Td7POa_#RnuD|PL(Y_Q#J>^J-s+`U zqD89dEB}p`W86w7lcY2tGB#PKueHm=&9sMEY&r_>VY}g`bJC#6g7be6s~`L<(^gKwNh}a^1y~2#xI- zl~6kQK_jvn97mJ3lc4lBktS;^^iZrN?1MM?CqJt`4eMk|sCC{6K5_sCYw94r{b89c z0~S~xecjWqj*HLHTmN1f{jtgkB-FUuIvfr7S!VcX0yCa_&3arVrfbk3hz0-O{3O!; zi;F6mI+aiMX%BAJd#17eDW`tK1l~m?hCvrCBfGqAK9>b5L(=f2*5N zfrs@I?M2+x_5R;!&i!?6|7&jiG<8R{hb5-$wO{JNZhhQ)e9;lr9?y*;hsCfdi{706 z*Z6uDI_`a*06o0mEgkXEV8GnNsY{4A`oW@pGS{^OJ@HG$;K|*JGCYg#yMnr$dIv%t zmT4ebdwxq2YGaZoli0*Q!K||;eH!Ugj$chT_*M4&*fv0w;KW4 z+Ob#1T+2r~C&|v@BAKKhf0YJ52^D|&G$#i40y7Y->iKN&C)1n+!%U{4eIL(5>zR>r z52IMd&0u6Rf1((1%p3z~q5yN0Vp(K6!olSIqT1jw4eLC4~&c7)gT5^~0;N#t;0 zw>I`*IU{j?Y46+IFkuf!B^N~e8|u%bE{t2biK z?;H0@&t&hHYTu5v6?JkFZ&Z6&T$*VRV>@9`q$E(jdsr=Y1R{_Tz2`eaM=WgEzuGv{ z<=XG`zErX9>z?=*eO6cXx=W37yP6eCd+B>4^>$G`!`>51In4zvUhGJ1x~rtQLX#dt zaEbTBQTxTku468Y0WNk5OXANe;ng5{Ygx;&===_u!VxUNKEmf%w$U4szeJjB8d;^- ze-~|7PGOy`^}2@0W4GOYc-TfH2=~BX)Z`{cPgYqEs4Tu<(x;ZQZtrPYdYo7t^j`~*a@+(NGhX1s6i?xQWPATDJ9q=fWb z%?hd36}T!G^KHrli8+go-4rp}p!;n4F6Z+K;LK9Jjz80pjEPsd`V0g%1MC+?W_D3N zyB6;aUs|;|gUJ(L7u&d(Y&)+y!#5in29EVpHws4thuAKHIR?{BC(8TV7kOPPTWwy{%xB{XNlj0&;HkDp$@2pcK& z%jV3pufpZKl)1tLuR^B#j^AX;r~}j2wQmKCxy6JhAdJ6qe$koR^j45s9`O=hSXsYg zkJ}Znl8{=ibv!WhEQ`UL?oI85rx{|iJTd##hADM^yei4vmUuk9%Tm_LpO;jAs=iI% zASd}Zm*8&~wEiIL=4`g4md=lFQ@r3|sq<{RDldM(H0JC5#eU#o|09GOxciH2l!~nV z{6gcQgWSN3Knfs^tJkl#er0ied{rZ6c$!&mHm=Ej#idTHk+6KcU1vdRL5?7CzKGYl zzN$t$DctN1iq?-U>-(t&4kPzqWU2;Ys_D)Xy}M4Ml@RUzqf(c&Ipo=LF!xvTFDYxP zR^AEp%SVaM%JI+{uHbho1d_e+nks>ij@=91u;)=S0i${_0kdsup)k{i7xj<&O1suJA~ z4uO-7;(mB(U4;m-DS*g{X!@xdJt!``ToqA=;kQ!_tkq<4c8qvU`uU*yaeec*6v#p| zz4-3`!`NK_wGqCJqA#Ubu~OU%v`BGx0>zyccZ$2aQ{0Obhd^<6cPK7_;_jqqfB*qP z;PU^zb7syx=ggfulXrJ#H?y-g$-cYK^Lq*c%`g9K0mGch%t1akYDd^0L#8}Z8 z9V9AK!A9s8sqGN;K{7%1f9Cy~laFAw%>X{1JOCdjqJAt9ZkA$oZ^jGG(wS`jNKIpK zmZEGM&=7qyrUyI)&M{1g?3mDthU88%WQ$BNWT*N!jN!t~Q^0rTghZi~EQfyCIv2LR z_E#CkeD#64C&&-n55Zp!kbh(+>S z-OE<4a$4NI0!1nQK*x6xhwfb!zUK|(5KjsQODb;Vs*-18MJDcC z#^KUmP^9+-efj*P{^0gAN0||pZuB9%uY9;_8zhFS)lg^WMBG@cxH> zs_%81wKYw&4)!NE?u50+*Eipu8~1O<*Ee{Xg^8A*ZunD8gzriad|u;D_|h;~JWIcN zA$P?H{@c&m9nkH3Z|bQJ-WvKSvl^K?f;TJ0X7S3OQa;2vXSX5E%;h|Ge64@Y^CD1K z^VTKisPB)vBQ;%lfK1=m0H*Y99<-cg@qxI0hTa9}%>mrwq zysF6>92w~3Ob{XUV@Ve7s&uCN8dh;@{W~ybD@rz;`YsKJXg#31?uViny~d{7SFsY7 zKyjd<;?KA%(HvyN;LxV>Y{If#>EA$=da~5ItQC;XeRv`7526-7VdNF&#S-;N3tKZY zIG6hy=vvv|nM1^m8#(**P{jzPq!OVG>YI|EFS%0juqZcM)TbuopspWZ zj(96O!Qz452UViW0ShA{%`O%ec73C#M5wFAAAmHxi{cxeyzE&kM+^@5pl))a%G8Mw ztgacs$??&I`*&4VI@D7iQ%vWF=YXIQT}g98e=fI>QX0*CFz@Fr?TQuE_i_h6)G*W9 zfjn(0F2cg<_dHAAgp%4z&A0j2=OzmlCbhVqF?igHcBATJ=n@FtrCR2({TlJkhV75( z#0_guy$9s{S{l)2w9n~2^cO4)p)+s7uLYbb_8e~2)_+F^R(rWNF~(h%H~HI`y?@^G z$H<5wFs=Xu$)Fq4s2&jhUFW{}b#@%~1?7SpJl6Jy+_%`(?hf4?YcJxggv$c)LhnPD_zootjJ@y3J#gLpCVrmm*6LNV!Ch zS4)p~En5%-i}*;*+|8(26~Mv;zYKn4mKI*wd{<*%`on66|1vYtqvpt-dUd8O*%e7= z>)eMa-uIK={pu$-;2hy*pl222;&D{0#-{W9_@z1mwHGMydRfeIKBg-LN!#yxE}8Q$@5xY%~7esE{Gx`iFLRX*~&B;1}lATk%a z7gZmr7rP6Hiy^zxpCkRvk2k3|U`%xYVoS#+fy9u%aE{Mu3f)`dvqQpS3YOJ0?)E?b zJz8?&4a3Eo{ZBQz&{9dP8ukOh_NryciAlSAjN5aIJ79AE&VFWNi>{w9)Xk+1Z=t@Rhua*+(a>{3VNoj=v0D$gP zxm?JF8z8$|?iFq_HW0agHa%{)_1vykEO^TVWVQG}!JbSrP_?ZjHgufzkoj#(eaa{? zUbo3l^w}kwICP=Zxp=w}C4qoj$R8!5CLLIPAH7+7)1GzYgV*bSR3nsSEJ{J=z)Xi5 z4XlT~6;L>s1%WWJ#1O4w%yp`On;@IXn-v!9JMc5||IYetSGci5DE~i|`xSrbKAN`F zRCMe%0<*yhHL@+W4ubm6VgGOCzW=|J`y-=jf$RHC5Pwp=5Yc}t_hOW!A~NISHpK(Y zp>0cUleR7P3c4Kcks@;hj_GVIU#o_trmK_`2)g{2a!_X6%i%Jy2&m|*}t%PJcpa0qy1!noFvHC+-XO#cSNa-!WS@JI}!S^8NcqNTCf|9)XR3*Kd+rTLy7nW2x*;2K7Uy@Jhh zHiLO4#*o34_D1Apnt==#-jW|d6RI1=0ehH{F-d&!-cX`B+RbTN+Rg=L|8N%l(+ioG zR6S95ByUKxk$GKH&}F#F|Asypl~KQ?aQMCDoMN{K&IV?vSo#mkdDDpPemVB(u|{`Z zHc5)Q<)0*GE5$Z6+ z#(HV5;15@ayhP^Fk7v&^oP#@`Mj``9)si==y_Vi$kF(hvx-=O;NG(wDiil)HB&OQa zYQUC%{-U=pEQE(Jw#Ov}yFAJoW&P!2`@ZoyQh!$IOtc8t)MU|zIB-+OMDlM^O z0Vd?ovlJX>8S!7wh950ZFD0nn&*LBBpG&B=F$7$TzC$K3jp*Z5;FkSX!_AyguJfC- zHB?PcN+^{(_c*h(ejux5N0{Y@pPj^?XexXF0^Z@`@{2=4_Prw3KeeUn0hm+-C5s@B zrAeZM0T~~mgcPmD-i6;VLLKnD-tejahi-w%TRUA`ZmyaFY06BqPSKVyeCaCkFEd}R z|0V@^nErH*^kFFS!`!kK7OQa)E%|){zxz3jD=N))@iP#5K>$%{Q#8tPV4HsnRorc$6GD0S`%7-9ruZ@X@o3YbY0`NJiN+BQ@#vtMJ?kl2)kfs)dJa#82vPktX@#- zI<+z8Ig2GG;{-%yqRZ4Rk$fL+j!wrmJ0E&iyXpMajtbm`AtE|1XRUN6((CCy7YwAa z8V*tO(-)v!S>MKQ_Cl)FMZ!y-W!X>HVXpy3rom~BUaz5Wsr!D|_H}W%LO_Dam10N~ zkzotoM_K8EB2-TmE(_B_!_sssQR$s0?+0-(IWG@lOAj2%E@i}73%=|6TmBmX0t`WV>Fs zFWiaV|4DR8e0sHN(o7{W=3O8lc{4}eUwz@9=54LHy>mx}+r!uPA=j_xC8~3t-byRFcAT#>+P_4MkJJ_51kNw%b_SfyrJ% z7Hj$~(MZCs&4W0lROKB2SV>9siew>6H|~UO!WlPdl_Z|{unp%8M_}9G{fB!r;!mT} z6G5Au42P55iBsI*qxCtX`R3_-%{YuVz{`h~`hng3uE1oRwnI2^?h&fdu`xJ{*XS5N z6uS!sqOcdY_Xu`Xxt}TSg$w^sI!On})Vx7)|GDFBS)hF-dw#ZX5O;Lm$KB zq#~;N$fV6hYqfYvnWWk^3CH&AP& zbHbhk2QsLKxF2A=>ih8Ky;!JTuqyx#~9xI1>@ae?K z%44&(Ts%2jL2Q;oD?{r-odkD78jri~Y4;c&y#w;~Q{^NvLq3K9kdiq8p&NhWAs5A= zV-y%vU~`eqMIteS(D&o!MclYf1_`LN)0I8ts>b=;g=Y@3wB>fKS>1!VY5tq5lE0--yzptzpfrhQWLY^=3I;!aG1{w7nGYJE9G7R3Hmutml^MEfF95kof zR6Bn2X7EU+Q+QfT^)O?p43lyC9*2&cqVTw2o{SPbR1j~IVWi8%ujW^<;F*ESF``ZTj^$nP4%^2<&S}NFFBk-{3s0UZ6wJg^gT9uz&^XxxTN)6!GW847- z_9FKFWz_n2UA}G(t?w@A}CA6lqgF!d*_j3II~Y{9@38 zD@1}V!_j8ecaZXbzl;u$cwl3!xKnOV>b6s!&f~H7X7KG)U3Qbd7`WmS7DT+xw3Q&9 z1&CPJ`h5^}o*Rng&lrRQsJ(sAO=d064O;Nh%JZO!I-U3S_gUIvU=i8wK0EjnybK^| z!Tu_s^9f6H9$0|3w3t7#wD_phqkFJ&h62q3?VxoHYD&fwJ(8XgHVP{Jgf~!|~N|tg%tn!~)Q^5~c>kWmL(610sk^V~~gn&fe2p4m! zbqongi}VXJfODGu2v+}cd}!gTjA`bF*Kl_SXgYYpu~tuSE*leJpq5MS@;*?}TfhJ? z>wscve@8HDEG3{RM#ncEhGIl7>jv)#Ts`C7w;l&U!rgMl&9nlc7!L^)${749F%(lp zLb8QVfpT9fl|Aj6$Bdd+B_Hd9I<)+lj8A3fY}xMvr&0of-6zoGyzXAXd?uT^4JA{= znj+`}+_9C5ReTB|cIVq^=@ZYrIISXfPrak8^X{=Oa7I9I!dZOA68%}o!ts8PnIjFO zZT1Z|w$^n7J#Os~i(Q@7L7FJosAab|$FF=~1~klxd%tGIp6SO4t~vQV&trHkreNTz zwa4U@-sSR;^bENb0LQ6M!O%*dr$F=d9qgH%&R`J8{CR zPg#HU8R>uT`&u*?QQ~U;-_WNQ(q7@u{~+z#q8drR8P$b27BSIC{JHLze*Udjx|h7{;Kaabs`C;c%jgls$1JYRP|Un^@-*W?TK8mtkQUw>TC4asgQkJx&O z?A{u@JBrKtToNe?I{}=R6IxjhxfQp4_ws-4EZtA?|G##fUr77iw#BEH0&#rhJmoWo z%CY2M-u?Y)&Sm6~63k@HyZeh*9(7}}y$yW|6J6C(vcOW8++>28yFAd_+;l=l&S`>hp^}8?KYtnte9t=>mc1siQflIK z-u=$rK4bth494YV@0a#}h}#3szbe+###~l*;DAKd=FHUt-ZpxLBqzInD4uv2ZmLw0 z%_PnwNLf{N^YeI#45>NdFC|b1TUBL2JuNJ7_iW}c0&hp0DE|IYIqbPC*)>uNERFMs ziv~z{8Pk0mX1lS;Z=(^SK~?-~vBg!v=u6P09u+rCAUiK@*2c&73@jO4X_NU_HK^u| zOJ`WE7Z=tc-|va5)Lfy)uO+uKMY~Dlh_Mpsx1J_IYr#J1&d*&y%9YlgB}KHy$zH3g z896!PEhW0)JCmV-qHprs+wsj%iOw`S)qURd2yTsRM>>j0Y#dxpIsMZd9S+ZwjU^9< zp~2t`Lu-}P@ZlI%iX^jM4=(*i)8m92t0I zxgFy<@88CE<6wjCa4ApHu_-TQ4)aQ1Nr87N=BNQqUhCvbKjv9OcirecN*W|P9JgK9 z?lMvd(<7)bRA&gDTE-Z%jX`p{FvH_JA?(rRBt*Ge=z2=tZScHNt=?e^?tqtAeu8J` z@}4IYNv*`l(^(GD@H;5kq4Q8t{WlKNBl)}ToOYa>o8SjC>%r^c%Z*J8U$vw~W^F%z zd&y_RZS|2e-?oX7h|kMQxecUO9g)77iyE`A@9{W&Y+_h#DjwFzBPXe&?@%07sMK(8 zc$zC<`6hB(_aP8>!;6&~Fw(TZ`8dbZZ$~{UoIbI+0@X5ebYTk(uLA6jD24=)8&yYx zFkf6fLSM(Un+r;8l47kf>)ltc zq;||yh^`HPm};WH;)Tuo&Q*I?2TK!+lJh4P_iFclH1$*k^qeUW_KJPM)Q`1`$X1JE zlt2(^5a{RXP|C$Mo!sVbP$}@$%p=???zT5ROEFo*1gwq}{mLg9npB8a`QljYx#56H zlD*B}v6s?!Mvl)L0{?u1b%*$_=JW$a84D+=Jy87U%y~wu7<4lctIE3;!5RH|8!$^* zZ#VlIlz}>rxpC2o|JsaDdeS4Pw-Lf{%@yL?k(ntt1Yc+Hd3@YU%=&n|eHjf8nDHpB z|FTW?#-MWm=rIB0{n!c;OaJ`w5XLqJ#=O{z8u^;&+U0@FrTLAC=@MlF2vj1|#lD%UZ*z6tlXSL0eXhWI zNN-;9&PeIRTZPfnr4e>w)`5U32ZdkQ#y?zH2NiTg)P$>)Kd$vu;c5L?ZaW!scDK`Uk#joaq4+*o775`9&F*Ys1erC)y<|o%)*w z?>iSf80l`dxmw@KfJ+<*v$^RvWK z$sc*2(|hTAe=hC~rQ_)iSs#jNFmHqULZJcK3;9R*2<#+Yy5pTsCgo`nq&ZT>gQKnH1z_~H$l&9 zdrihv9)m3T^mj;p&sWR2K{%_20*3_NwI_?~?L8v6A6n6my!IGcpS>1&Q_DMk*$EKw zBKm2oR#i33vOTj{oA5#SI-Q?2Wo|rJTI8rXGVDz+7Rzg0gAJEE7ErcCL9?u=Ri zE3}J>zgFiHMk$vlen#em#tdN^BFMqPhI(c>jRIsk(tCT5zmJAN!kf+ylJ3zj zJ5Vy>P?OC&AobiqhfeoI*FXIr(?HPZAHUyyk>uxsWK7Uxg7T1w5lkAZN_eDsx|(%&Th zw$J*fUi@Sb=`M&9^7DMv)371(?7<9$SxnUHab{8@CICehV+hd}{{EFoP7!73UVaqA z8}BUp-6KyO`^r(mpATvXmS%Q<;k?6GjWTn4U<0JBR}9u_o!Bd#{nT;}<)yv27@>UUZZ{Wbj81tIyB$RUj2|+EcYUinXDw&)aXBMy8(@3I*y7Foo?^Me^OkL$YQ=6;-^l0F)8+VQ$lK~Mm#0q*#?fBU@I zff_Cn*ym!+X^zbkYKGS){ZG8GcRZ!_K*T>#{>ws(c6sghdSeua*4^4qs8eel8M0Sg zLSG(K>{;C@eQ$hJ#bjYlOD_M=j@z)B(rX0%BqRJ2lqc6T`=Q2M43_DDm0-jvt558Q zE8JkaFjVfiy2EP$bZTpeaf|nj4bYAG^Gl3txoQ03YlB)fCvOsIM^G40Tj`5590fnTNs#`@Jb+P zv3fgx2ghCsAiMvqV>xL~Txrkk(Vy~@ams{`2F|+K6YUl88QLNHRw6JQ(Obz@zi7r% zkKUnZk>5Z6zV4^fl*`q2hAAb-k(ba<7LSb8m5P3Edi*?iUnkV3Ee}H;lPAK=8;zJ1 z`aukL=15gMxV~ua>yXGRDmL)(8|r%GZ93z;H4V>6x{{}Ux7QTNP!XvEpV7an)o8y$ zERXAW>NPIrcm4b9IjMttf37=8tC(sXv+)#1R&;{@xT?IaqA3^?Vmi@@eyjREi)Ccd zlu~9MJ`NsA;}bn@q|RG=mJ7I5R*{3}?tjY3cW@mze=O?5AOnXHTmf@)oY4ixlki_o z(23K2n99iCWQm4!{A5CgkL-J4VQyba=a4Aq$>cqqzqsy)A@7Cl6S@rq+l=uG(roUB z-F?b=$1X@iYOOCwBj!4Q~vhlP*S8j)WX%lb0zO74M_T=Emw>?v*8tjWN2OccGYI32%~5m&)3*h< zNHJaSqA!}!j2vRst}S}}p&)d|Zbrfqbml^RmbAGkdSL30#6-5GC=7GZIygb<-2ASm zuf4onnq+1s=X5kEe&F$R2AM;Qc9Z7wzR9y&2s-mqDx8F%K2k=&=ndwcG9i5B_i%y= zO)hLjZ-6$y2dAzbC;~#7WH)c;tD6iDc_r82r@Hl;eXIrHk7*wzA|Mznviu9|EoS?? z)F^YY)D&be|8yyKM%^n1ACWx^5?=*~nV&gTH9fa3zR_CUTCPPHKl}E5h1c2y?Wr{f zb<`l{5UYTVO2k~@Er8<;*z@HK@b5I|8Pwd{QI1&XUNxRXc+K~(t_OXESH7&!di9xi z3f`D*7nBBqgTX&9p(u-cqWWFhb-bI6BAboz-p>#2VsO~8f2}|FTYv5e@m(f$ERxY= zRuYrQSR{=b zAmVNm8!a*9&Y9DMfYZc&D7c;&c^D7*WtR5kW}oq(xZWS}4nkz%CDi4b<`6nm99-n1 z9aC{uQ*p$i5k`xS@iLIEY=mNGD{G zcucPP-sy9I*wA&fNb#(|pq*9N*9sa1UD9|wi;TZ~DVE`0);uA(D&wZisOftr@8SnK zEisO+^(iX{cX<+qgm@|>r3tvpQZC*8{4G*v)PD(s=jfGX+_mbW4IDoCeTt?>U4ieS za{9g!%DboQu&QHH(5A%@P=>-rUs$6e+d*yG{i+^8FxI!$Ko>EWR%vc}hP zci+OoSM{yK(}?A79hL^q(6E61jkR&E5T1*;U$4@^5o#s`*BcJ0MK!uQo z2Ts4``?4Lfux?3Qi+w3PO8? zbaQX$lUCi+)+%XkTUlTo{!xc*GaGm}orN>VrET=CLu`iWWJ^{>oXkm;jVqdG75_qQ zszNBuFn`IEANWPFy+HJAyL%6;EW@l5h1NmM>JK9!UX!vP+WIclwg zW(CmqBr~M3^_&!c=fpen|Iil6et05SFGbAcg)? z%XwIYLQ-D`5rPxgcKZ;BrNnCaP=ocg#@cH$1BtRP&Z+USTW+scBe^cTdLO&QTKYnG z61-MayFz;>0w1ehihIqac@tP*-XhCN47n)H&`$q#iKCC@*6bzR^Sq;Qej~W27cs&e zytT4$3UZOY!md%<0ZSXy*I>pQ5Fdgas`iqA5;LFkBVVzp48I<; z_s5&tDY{WC3>ZVW2p^8b4aYwIF3TlfJJp-nSbOv;@AUFVqe|3eZ7RTSZ3aT8ypFH9 zNpL%n22&HUsS^oNzmZ`7>E(PSBN_hZrU=(O6H@*x_0;?6c8>jm;qYct=C?ue7lW2$ zf=}{eqrV!5M6>D^E%dG7S zwCaBE>$1G!+kRi$1D`ibb2vGcXd2|vzCQuPAHWLzMWf{OAlCuKJo{q+?W zMc!MUVyr~80Kh5FBU!G}R@mUaC&wAC<8aE;Cj=8gy5#lTQInfd_RPhUiO6YUIYEw+ zP&4#rj}4aYUI$Rg2HT6?Y5M43iX&4AtqMSeMSopl{8IG1GW)7-OF%VZXS+p`Qv~ve zjY$sv4j`S`VO{jVIm$LC-8_FhyU3wu>B2_1gwF0*l-v8L^fs+k-B*t+Hr=eu&*eKA zZN=$^eu|e_hN%i`WP#(!YgfGA_585PGy3ZrCvf@XIaVx``{Xcy(fhd8dGrUKouNcK z4+w}nd7tSOgec+cvE0iZyM{zttFdTmJO++Al3{dGHk|m}wW@!HY3ay z0l2cIEJe+u*Ak)KRI2Z{tOk9!N}GDjOK!TIfJ>}dH**(!7$Dj2LF>TvnI}~n;6fmm zMG%Z3-q|1D@!>*E+l1MQLcxNZcL+_%`M{8t@Fq@*$rN=G)iyvE z6>b1@lO`9=5j4qxB80rfJy-8z2Vb)Ip{=2I2M&aQg3WN9j>GPGU<|C zx+F9(;Mwvii_1q4i+!alXm4++w=e;=590{}$Ul_&7(Q&xLYDoeI};*Uj;=>keW`tg zr{NEUr?O%U+aZPdj`V{+; z`EBpkUkj(B2ik=s`{4L!ym3fWiM*al(u{b@vaj{Nq)QA${)i3Zv zzBcxsQ**3iP-+|#CUO7g0GW7C$0fJb%t61Gu$R`}{@%!$^Wp5D{lej`q2D{GBCdsO zu1WJ3U<`Y8fZ3CGHHfSkQL{!rHKUw)Fi||{^D`~Kir?iNxws%Qwd+1 zQP}_zj9}6rD;4E;cfNq|KE)%ncHoXPI%{hK{m6}p3G>m1UR9M#_R%>66&Rv@>?LpY z#_a1cZ2uZC2l*p_dLjCmp}?veOF%CvCu&KAl>7ZPl1h>U6+ZWAEt+& z>E3Epm5*%cM=_3rmp8^>n^${;hO_h!57mN&Q;8+5jR}i&ZpobG)hFf0wrsG7hOl*|j)EL`jEu&U%~ACmO-G#pv%Ao$%4)>K{m}e%NX?o<8T!#!jng)%+ck+v*!ccFLF5<>m+Z@B6|fqcL{`DNQM8ooPNL*-lsV&>wdB3<0<3X z0_hT5Fof?oPE9a{ZK*xG0+zo%W1KqU4U%J!3ty?7%3%r{@p}G7tKaM9@$|O$&O-K- z3(1wP0_$CG8&uxc^YYF1)JMkT9en9v$X#6+_jmfyF;-aajPaQbua0cV*I9?8n%-IN*kIQ6{ z=c{Ok$^1}`P?pJ4=YSYeh{R-B`fyxKJdU=-19(leK~Lik^ncu$Kk^VuK{Qp%2CF4nO^Py9(e z7orR?BbI$Pc5qRGL@EFLZ%Hx(5(<@XP4I#g;P)~@{HwHUkgy*tU41vLRswixB=t3Y zoo?4CMRgaU4-8JIdt+xyMV##gW@Q1pKwQ_C+MvnnleI>$6YPhC@Tc}IAdawn0K~s# zO;}auOCt9?51^Q+ei2cvAnvEGNjCc+I9;otD_N z9_}HI-*3BK{@9Q5lkNh{z{`;QrEosOiPM-y=JA>@#@bD+H*E)qk2VO0Dif*_Gm~3N zwtygX$(`p}boeU7pXvc$ zAd!7@hx-C*QxzYG(|Wcuj(2Zdd3t?{k5KVHw0RaeeAD(G?-*||u}|_arlE4QrjNP= zaOL8ypN=woO$9ced@KmcyyH)i0X!D|^II6wgb^IvoR0*wd@BS90>U}vPYP~K^WwLP zdRZYVWfi42xF&i2lv^r}$?|l@>_VabKwB=K05{%Jgv>?|al?_%RxNHycb8LZ`u&)H z9@cl({QK30dKcQTq!Q;hGK|ZAwY|1{COP7XO$^;I3W*5e;#*nFaSJ2OEfSEPS;%Qj zc0jaaCkgJ<{jE1ij$N;eRzeftV@#M~g2I7qsX^*^{Ir_%{qb*BH)BlYQCcI1)!db) zv#iM)fzIEjpM_e_1Pvtwt5Bu4M(@s0fxgdJ+vc~slD(I*-N2gWjj>nS8|tvwt3*;u zuhXWn>|wzZAkj(U5c6Sc=h${pPf_**TFTlREnnZc(Iql&<3kQ(lNy5?V-PvSq+1N8 z8zgX(QdOfMykYBY25{S|t0}U6 zujfr8x~8Y5wcHw%m8|W>7=|js`guEPEKk#VE$=$5Q55tmowso_gLdKRHH1+cJ>(6o zW5LR`aO`b&R1xmEPPSk@LdYbp-y{D)nd{3S`<^CWWQ}=h;_RNrBru<3pL7yesy>?< z1f&+prS|6r%&Q+pazXbL9ai}CxEk@X0UX!otmO1BH=ATy?Qcp&_T*>4obh}j^&Y@Y zh9Q${V%V?y*R1=tb1gsEUtZpf;`*)`LnYrtm_<{g^9l@vsO2MWuaL*?3hJH}v)+NT zK-SF$)Ed?unbrRR=iPvB{E+Z}ZCRbX)P>>Dt19~Fl5c`)fBgeWO7WXqisBVbUj^2Q zr98h$&j-0-`V#4a?hYikVXpvG!ad_GYObZn=gWH<*fcI!-}g%7t7Tr`Bhjg{E5{qwIApCpa@w2y`>kZpfO5R?@O z*>3CoObm;^BFFjYU7E;aTM${{JRo=fX%BDAtjMIkFFeRsecJ8W)hJ>7KuBvO<+9}E zS2&4@A^RadNQenu>T(QZ+w8BV0U1g5ZDN|Fp&J=VUPy?2&QSE8khM6StmfQ0wfR7y z9d~c3O2@opmUpHcFHT*1+9GgD9f2t83p6(~raILgZrImeglFrm#W(dbs=%Z6WG zUbFQ{?&aN6rPx>9-cfmtG@SZ1jWY)%YWWmHIDwecu)8mAv^Sz@U@7;DoG1mi0Y7(@ z(*!|Z>q)P}H|);=J}S=q3`Qm@!Qr27a(;eUb{mj%|K3DeMSa&VnDjuIf{aLz-|?c* ze4vbV6|1-wCORgWj=o@&aEsXnXKum%&rKuGE z)D_+W_eSq2o^x>aSHbAt-btt7yrB{sg&COnuc-#}3mFd)2EJ~ey|?ixA!T-ds+ze^ z^Q?-}&L+IH6(;-kBckcB5&9o%{&NP6jJj+13(lg@PkLa2Gw{Gliw9^T{)7{4MU$kx z{KnTI5vl_kWy6=}g3aluvZs9w7E$;nd|9#vpLSObCGV75{F6{70}< z>JME6@8*PO1O=e-s0 ziI&h)aF+bOiVW9RvFtcB#5NK#skhoU0vZn(K5e=PPGxY=`== zix|JrMbS>g+K}xDm8MH#>&v&OyH6BSVm-?M<@1r@ewwOV+&msY31{l|{( zSflDC(ffQTTD>$nh{qw?y4KTW3GrAk+OL7%YvBK{x#&rs(ar-<6oA`Xu%15WP~z$5 zwlSQ&rS_D){5TBV8tux~NQkuM=Z1HiiewozSczoGYlu=^ROtXJZAF|rnLJ3#*#i*<47E7vXSSxy{q+{MroIL77xa1nGoKtw5F3*Zofy3V?OYw+3#YjmU0-;K z$fzR@-{$JaovfSU{SB=7QK%lc(Ib1h9_o3%BMghm^&6cQ^#@ZmyWy_1kF2%Jo~`4b zt?#`IA?x@KTlf>Xe!IDT&YIK;xoDq3+>z#wv9}De!-a3m(Hi_cW{1<;?7+GBeP_%L zH^#MzO^-WBdBP!o09rhumyP2@W=b@nkkePuhlAdFwUy^EPY&6*Uo0 zmxqWQO}PWORZdoS?{8Ze;_~gUE#tFkyo|KWBVC8s{z1_N`-U zxePP(nt2RH9@$;W*IUn+nHH^x$LwQflm4%6#ub%Nx-)kcm zKNTxVdv`PPDd!Hra$fWHO=xXkI(R>Uv76?mm1i7uP0^d|BX-s*c#T_Xh23L*~?g@+c+0-1wgVJs-|pcisD8XU&>Dv-f1O zW-{g3zsEfw-f6R)1couO!rl-1n>mwgFk^&}$j$s!0UKl=VcYPMc-mPy6{5Q1DRBXL zgVOQMHOw=EZq?>iW9-#)#!6PV`>;o|64{Gg-i(X!E+g299g0_F?8W9?GUuOe%P2mn zRwZMyFhUOqJ#LCNVBiZ5L?}mF_EkB*{RPC!xGT2-p}Oz05N7;+_{(`j^56wy#lcM} zV!y9xz|)IqVt9K!Rn)Eqn?A9jEz&iOySA2UOFAsAEdv_oAJVz*CoY&o?ODR*5N6QO zDF)yg1r@q~L3(J+eEgoj%O9SNVHPw@R3gx6KV-704f8HBC`5RfQ{# z+4X=jijfR&j2YoDen_@HVx9NTfjC}rP*mTAeSP}no4gEyjL(wJg>3F zG}>^@hP!2l4!0W)bC@+A$3}S9-I8S7a-zHS3%696>S@WXIj+y8TdoH?SJBgJr#B#^ zXy_j1Ha-?R>f(5Pk9+aX?KOc!*(H37m}DV}mTX1wFLcJSN;LpZ#y-ZByYSaz@a%!^ z#au6DzN_%|WtYf1Sz1w-5?R$=!(5T1B{${d@66LD&e{ua0S+^K zC#;+4Mu<7adVcrPbqpC|VNMr)$8q4yho~Z*9eS_KlC=@9?CIM7@zSi#9ctK@YQ1Y zc`(Db`@+l}d=)X=qN*r#khhC?vedMWp$MUvDP_mW2z~ijXEFX36THv?B!RL5 zs?Yg%fySR}%ou1dhsz55Es`{04YgNPU(LtTG_=U$h z^=~clg6{3Gj>&g0-Fc8|t1tN)Jq_=e-T}@{$k>O@J&Ge+c)=YjcQGUuwggSEh)^kh z^yh|dF6+AO{IFn#$I=TB)7uAn73jop+Pa>)clp`!6+T4>CnzUd)H)Z$CL!6oON^|9Ekpc+uv-s@O((Tgf>-c{f8);qmuX@gpW zgUwHx*Imzfp0iQcnFg}!@ON5pSw-B^>|(E z$Cw8%o$qOtxXXl zg!%lVi;GDRWO^fGGfF2%!`D?$Cb=Ez18Wp6HWj9poyke}4dA5+m@W^&2FjmHtpIf1 z=;WN`iS`^_HJJcHthkr*5a$8N)hzwb1MW>o-fW$^Cz$~zyTSqbgrR6IXOLy1cNwNo z-~5^m(CB%6k>lad(5pE3oGUie*%a?0Fks~m_()V@_bWdU8B_l8l=~3mjz|tEIHVzmm78r!~YB!1F#LT1kNEs{K^^eJW__(z2&H@ zZoJd?w-C;~E}>$?h?!|f{?7whI|@q#aQ74Z_j$pjFL+m`*;Ys=dJMyPnqiFr z`W%JamCay8niyJ9fZ!Q(G!Q`l(!Rm*|2()+*AF<_|IYTSqIHQ7cW?EI3%JIyF-{lUW0Nc z*BqRW6&WxL|A6|}1G#X(2H{3L@EF!XiD{RJmW4Z@jPu zqymr)!KIr!BJ!62lP!`7cgFMpWb^sNx7puLERWUz-8A_=0dvV&1q|rrpop6#7YeyL z0hkOu>53b(&oZnTanT%4zedb^Y4TEdjnkgXxig>JGgrB#O3c^4Q9Sc-xE+|god*s? zQJ3MNGn)mQ5bG$$IM=ne?m0)2yMaQNopSioV9rg@Yj0C8@MdEWsjvV8+GrdIYo8V$ zB3jPu^6wG?djO7Hz_;_LQWzhj?;9+XYF`qAa;dvCuYL#gi1jIy9HO@X7HX8je|^;ktYu0H2$hc@p0e4 zjQIBk$h~F#mYrzoefRNVJu63<(jO|0O2uXy#IB+kunWzUb1(8 zl*-;V4cW6k;nqc@;JSJy)Au1J z2Pdy9igAJ0IWqyEqVqeRiE{zuU-%#aKl~%?q!I7*4dQS7D-=<7(suDP0jdX#*>iI5 z9V!&@><1eBwjNg~a#a+YC>)eX8-TZ6-3<`C^-NPOo*%@0E1TBi9i?6Dr4fboIZcWO zEos!n=W)shi7c)>iK%lG5%$vN_8q&d^(OU-2M>$SahoVoL74W*b0c1LAXa@r}Y}0UQHtA`;M z=@$nnClM8aC)>#0{|%_sQP9HV01y9$PDr;H5bV`3C<>i>iEEC{SEuQ%3 zrEAIF4q2uIp?KnTw`7pKdd<9GnZ3rr^xGAGPRD+3 zolV`M3s#)x=rHo9^Xc*<+n(Hz`B@k@QDflR{ zp2V5*+b#0_*@j!qIQtz;tQ6ov{;F}jMSkn?(Tlwn`46~SFib{$Jm{sz|2mt31%qiM z<9Xg7+>ekW%OKOp>kFnM&r4$lG~)|&;iWOxk!FNPZf#3^`(t#X^l~u+TKu0JADyt% zIV8bJcjs6Pmm&mRLbKU9QWqT=?eD(q8@5bC#m}2ah4gracF(+Sr`eQoB}2P|g5s{@ z;;$`ATEG*(joZ# zRO)5`a2)YJe^5Dtxwac*wvDhC{@%j`jmPZXCdTKs$4%%PmQ4#|22|W*fSF6tbUWlEdh^k=viN`-md5G`6MVoQBEa%Mi`XF}J4z#@ zIJ{%`^PxO7sz2IH?XbsWs~T4QPooz`Sr7wO^X8FUhbJ^WCfl?M%LC20b)KWXoJ_mY zQ#M){k@n}*R_l6ypPH#rM473HABz90jvQpFsa7N%zhH=QY?Eg5u#U zw(Dqn0rmcz2b`$)48MoN;-rVqsX}tt%EpRWm?DMUGsf&|yMD1jpAsk)^Nk48j=6g$ zuu+W6S#9ZO#ArDPoS2BK>&dWHfWk&hLdUM&(v&Q>rcrgFgt+;#bok-y-3pG zFy_KW8kF+kyTw3W&Ze9CIsUZ8k5PANH&MJ7z|N$W-^eq;(&Ed)b(+BGntp(GKd<;_!wO?ZtXw@BnMf? zjmAZf)&@S$N#Wgk!vm$~LFSBFuQKsK|Lc+*xL5r;XotSB*=emsl>2%)lN;yDPgqYe z@lgEF0`l^t2}2`yJ)Qyc9sviy+qL`iWLp-pxb39@`f~vNse#rt%y=aiafi{jZwmba zGltl4QbnV9lY%TKxFXc3lZ*!BXXGAp74x3b@KWY;2I2)NOOyrc(5je%)(AQ=P0%st zVue^Wp^-M)c3ULhOC-OJHh#z^Cc4hv;=qZ{$w}emygDJr{Pu|C0HcLd3 z#d&Ao>#V=*9Xk0{vNY)H-^2v%Vby_eGR?K;Y_|3mW4?$)Ql;{7`^$6x5iu+4o;m=I(bumdA>Cw)|_H$(j0Y=a;_rHwHL- zp77^GT0*hk4pkzY+nD2=vT>$0){-P zqMCZySjGv4iMR*050s^n@Ab>+kUq}Jbwu$^SUt3j$hxi#6_i?}A>4G^ar4m<`viSM zG7;HBYh5!Oay5zZBC*M5%vDp|Rd=2{WQ!#>y?#UF^qb(LWkeII*s^&1za9O(n&`2a zN}_V6Jemtu8(~o~{WRfa{9RgUPMKVm8r-`oTO2}9b8qt|MseHreGN*Gg@N!TQZRtr z_p;?76*0@^LS zD*shR3Z-`^%IGde5A7K3$yt;)R}8n?Ito+?42}#0i>df%WyEC8lU=O6OO8@bmTqSM zZ?iPc7*wd8h4k&!GWa+CJM-iZH-j`)1}_zoduD-&etexDk;)&EaR;w@-mpdfaILMr z|HJ?KvlF7_-IT$dzp5|eC=L~!U^Nn)<|L+PODmZW&s=WRJ+3D|+%zgcodyA1hbAVd z2xaUFf=Qt(ZJF5}Uya41&vO1G4O)}G!M~UI6BN08oL2DdPo$I=b+Pg-6EO6kC;w@k zWf&nE5-L?p3j48Td+#I2IIb-&vh5C0j?i);crE7S0l`>THrw+|)tAQj(j~@>c5{;X z9jm_ma~~^clN}xbTM8aNa`nopl2y_3<1eY`QbKZ%>ifWhl2%sbtL7#u57g$3z_pIN zZH-9m(L}1Wh#^b&X6f~9>7O?3wuGzeG<=&n6E6KvEEkV}A$>|!@TAJ|n-2V>vb+iS zLYBh{5nrI^Lf)(GH}+y~alC?ujfFit*`^l8gsT6Zq$LbREn_>({c_MPKLCyAjRU;nFRWQ0Lt6IrtUA78UR>tx6BCcZwL3`J7zl5>z3iG*BS5Lr|t(0ZB zr>|_qUU|~DW(%%qnV-$>q|eFb!cJN0>h0XB+xkTm z_gzUc&;7FBBrCy^+H|74NhqLd&dbxGkc_?ar_HWX1V@%gx4`k6!DEK|(I~}pYgZjN z+7n7QS|tv7K2)#*mlBNcm=^UjNnkzc$+TPt!q>~Es7iWZ)&TGHOs^+x!qu#1daZ^} zHqo(ruwHU8i}C56;57a;zvk)YSU>dBq-}>9ADnk_=LhfH%EpkLB;!4MA-X58RzxNH zcG|!$xO9Bn4reVh_C8JYfp%mE_GJ$ClkG9z zwhrDMG)^(E>{b~h28#AsX`ml5@xgq-JrUY0?pY)_KvgLd`#9{fBg{FV`9P7UOk6nzpk{7@Tz#r506aj0tyGP2VwEMI?T1gy@CZk~!eN&Hw8A{KMeYq7E)uI9w@&}Yd?!9;^fEnyy z5bs?%T=uJp?6#m1c=IypjO0Rfskl2<&#~3VCmfrj0$j-(?Cc$ZN~C^zlHtDllk}w5 z(0P#z>=IsUSWnEYql93m#>`MpoN(Uhs^;=*iOsgKHeTn3F4a9*4PZ4gtD|WST@dE^ z`_=cLThiOfoO&)F-lgx|X}WzrQtw>hJhu77M%1rggh@DeL?G8ehQlonk!aX%1?4%T z5BV}D;K?X9V^t(NrTx@udppgY#AKMmZ^myGkvz$$^J)QHI zo999YRQf)V^6O(Ewr*FBf9AaVU{hW6s>gh`LnT2N%lOF;4-G@(vre_DJ8hAbhbTvY z@9d*!pC~H4Z)}$`7M%SY!5@B@+VKipz?DjCY9~&xMoT; z^0#S%L~H=r3$zZTqZPzdZhlXkSB|-E9*4H|p$6oN%>^$+R z4&wZXs(5`&J+u4ldTtcHq!+o%e@#sb@VSqA_3$z1-5R!|sTJ?gfv0|n3|#A^FR#o0 zL=4Ss@7&r`wF*|`f3~#Vq#)UJVBCgsBCPAEHO8fZ32Qp9GzK(=E-c9)u{U0!^(dN96`9c=YoG<}1+t@7lRtYP>3VB!{@rTu^Ed>iI@wQYlO zjQEgMTy;%hEcNz`Ic+le?k9XvZ3_VtH$Fg*hEJMT+6_4$ZI4kuxt*x;w|O&x4?)~Q zSzO&_Qr$%=9;SbKEJvcRFZnxitRcn#?>T}tdZF?hfW)c-#5nW&VplR{@WR7n37tDa z`M2~(d|qBYyPYTanPV~eNc2s^jdbEfG|L^=w?D4|V+^Se^NFnJs_(OF$m}C2RGgeZb<)t*)%MiT7J<1y@x*C4AYR8*-_Wk$ z4@jjdA)nFQrK#CZ`gg8+-&PUa|+#y4dO~Xp}orv`noP*8?mzy_$UeavApke$$~B! zD~ohdJ~*L9?E9Z!!+fCufntbW1{u0l?V259g4ZgG?a?p^MV6$yrOWyJ7qP6-p0aM( z?->X#VI7`oxaGSg0FQh*xyt0biEh%^Xz8rJo4$qB@gk-gL$$(Nu5;t69(^3PfBHpVX3nn$kf3sNS!KdO|Ygi*xSD)*q4UTp0 zsQ5b2zLl@h694f5d2z70_`5^YNZak#T zyiI)|9S-!50_LxD6P3>iQT8 z4_f(dUQ7?X#K^)vg>qde-gl4D=oIn~7eZIti=CYL|1cur{lOIbsl7c9BB5yASmp6} z^(x;=S-<Q_yrr>T4ImF4adfm_NXZ6a#$lt#wfkB!uuVY}3>YAz30>)2GX-h6OW zIHB)|DtnsAP)1#`Z2Bv>?~t=uda3IfnS~ni*`Udl^!WN|K*D09M^EBZ82?>ybec0j zW#*C>R)|>M;*xazHJ>T|3H`kmNw3ZoHCXTw4gw*ooc4R7yk(3_avXB9C-Q7nVtzJ| z8QW<+k3}@kBS(ZBYJ3{3Hau%XBu8BRa+>1}=PL(fjs{h4s*a#XSBWSD^k}{#WFyE3 zPnkG?m-O-7e3Y#hV}V}aJ|=#ksrgJ={Pj(Td}qNJjqtQJ{;=5Ej6WY)*eggVJfL4y zIwcrNSzPx-RdkJH*Rxdw(KZ0l`-YnJIb&VD**W_&lP`-;7TQ20#Z^7Ovr!Dc-I9tK zks9;F#Na0xN{y*VSsdzLzXSNE9nNVU^DR``V$t|tX7nExXCfZr<3d@>pp_m=bmP8o z=dGLm3AG!`U6UY%(5<&5r!+t>geE%3;}DYe$|IkH^Zx6l2=Px=z>YR~E`LcY$jsXp zcO`qaMEc)v1H{QrYnrYZKlgxgwtZC(N_H%N!lADjUh%YK6DvTCD)EU5;$jt+0=Zsa z=!wbr1m4IU^T!J_d)`4(Gs`-I*{Bg zHRx_4V>V;e)Sd*?Y@hh(C){3su-LSgEE~aZa=4KiEU7A+7Cn4HJYe-|-71-k90RwF zIl(8;n+#_m7e6!1i;9Z~-8oy{O4u5RhgRaj#Mq{?KGysClBpJ(p73Y zzBcrxxay5;^jp55LgX&Yw)=+nR%iy+6?ml}>=HbKvZ>H4yEXlP3~trX>>H(L`u}Cl zvkR?j#5@}Q|1jsd8Lk2mFnX)$XhECscXx|{f{{>r`E zcL)66zw6~e^EW;DU*`NnF6T93IMY9K{=O7)f+99T+VFE=hF8>^Ni##j(_ZcD3Y&H1$Rem;eTqvE_XF}zi zpE+=m7Hg2bq6gz*n*>O?*k5V^r6xhCAYnSMrAcMyFTqP)#Un#30Eb zfAy!nB9=&{Fb4+AL`%p%&6;83OFceLN@a6ygoVO)VIh?S@p?nKPh#r*63?G<>+v!^ zcv^QSx}IU_$FC6RY;6!Y!XGvUQNS5~isTO+_#wl-Nte11ng}5(WzuTOd5%gB5-`FO zeM zz1X@A4+)Yd3kj;Id*m1daA&>$^Q&4)T!1PL^l$00d@3nUm@g_Nl}VhYIOV$0)-5xZ zIA2ZOL{>>a8&+V!y`_jDm#WJwd<1d+H72aK+BTvsm{{HNxexHgUa#?B^vkAe# zd|$+M3X{nenqEx7dvy8ybq=2VBrP6U?Xfjnxhq9vneJeJAZFJHGX4~EV)l&Or%1{< zTR3jtKB?vWa4YM2@r1yB&9b42vFSMzN7mR;M`bwcF5+b`~odZJJ=h;UjdpT|_$svPRx9!r!$H@o$8I|KHGJLwNBDy1J z4>pz;Pv*qxV_c1}r$@W3C4&W(UuRw)(+@J-q6>Q+(V&8>1f2h;&L=`pwq?p^qD55^n71(+k;MT7n*A_YZz0ZD; z=sSu?mD0zqZk&<_71opWK$b{y)aU1K`-303f9n+Xb6%c%azjCIj2&&h-ODQ$IsGZ- zc}K$mVe2*niW{pjUR*YSfxpkbO-Y)fn`-x35Fe^Ybpsb~T2DJhT)(Q^es(@|4<%qp z?WYTq5>292y(TIS!ljLUie!sw^?@=nX>CTY4w!IIg1IdaBkfGR2}i%exh#TTiVU_XPe`7O6UUg5Pp1hw{b8Hb1mz=U<(r^)%b zDCfR5nLXQxK6%yUJiBhmgq=6Z=#jYzIR6Z~djvBtBkmb7Y@M~}7KmKGiz?KY_$%6qOMns7C>zm$ytzGhLF#W29QON zN@*Z_Px9+mhxT1OdclJ5&3RWx%0l<9sr!KS?D*_O;QINdEh&|wNm%PiarMhytiD?iG?v{V*y#L~4<~|0MqT4_Tz5jo9Kn zrx7Ky(eCBH3sPN78Ja)q@9@t}-nV6u;Ii_2ga1b1`QYoFU(Hz~4MEqlgg4qd65o2O zKd79%3*0#lhnv{mR3&1MJd;D@Oi5?d2yalYup`9ns#AOf<%^@>qKW#yVNc(2rxTN_ z3(Hiy%XZo&M?Mg!pyjw(v2`vzHORZUv(81JY|L%x;I-_^+tkJZx+ExnCDX21{;I+z z3Pg>X-e|1L!g7Hx*KT&;TcQtoiOue3KSN6kuWSbeY6RxV0a$_RS;G#E#Bh(-uN=~c zS#lNX3;4>Ki2 zT`_QZs^_np>02J$43v+Vj{Ue9Fd8*YwTLOPP>yO!*XFkohwSD1$M84(of= z3Dw=3c7N?p-#d}oK32YI&FOw_?Vo;m*gh7B&)WtmGR*;M+f6Q+*_EbK(bc!;D++$1 zs}Bg4BeitN?bBKSL;V(93q*A&-|o0pWxGe(0F&ebmU18x~4*B*Nj|v?IlHK{K)n5m#yNw;v-?r2vYLzqXMw zIj-yMJ&Z(iy60Cio@RzV5>HrEY_tliqLI~p9| z9+XnWbCJSI@<7%SBaii&Z4cIs*th%+R}8GMD_#Rw=e zBs`YN?!Ql##^m#Xa<(;OY)NDOdtBO~d9 zktHb4<=$q1ATXzjYcfciAEaH&!JC9Py9d8@iU@|xQ9pQ!nzc0>5eMn@_}X>wYgPHZ z8;{QEZJ+fR{a0H|hsrKW;o0?cl4K_}{@ie$i+K;GKE`@spQ1061E7!Y_}YK(as7qA zQ{D%9Fyps?|9TwFkSTBm^cWe+Ejc(kp11vI>bG7!1yACQ2v4@n<(XIHX6I|qnRZS4 z!%*j0b{#o&>gwPHJxCt$#P_)gH@bM)K6@!guB+m?-yH(3fQOIZ4F?WdXB@|M@XJS~ z5?%IMS!*}=qN)H?Tx#!I+85CQuuM|{9K!`+6nup zxVF=Oz(iyq4U}bx>Af7Q8%!fIc9N&~Gd-6RpsKk|=A$2hdeXXJC=tCNfd@f*qRp zP6U@q+8St#zlQFj^C_&IXqhVvV9{4_`#MS ztxxgi6jXI;GOjB0we-f>SJ<|R_t(RA4wFXjAe%;=+;pcuV686oLJ#bd%A|(n+&GWdf z=8!;~8dh_b7_{Hwwb`4TOsTRw8;0uT9r+#7cu=pM8G zznSz7VgF;&dnL9e4kf>C=1_R|jw6<=sF`DP_Ra33!vlr01If&9g_E}(Fa}p+D@xl| zhzsMdr^s?+2_-#x&i-*b*2mhH8t8L7%|`5QkyGyh}aePSgu0UB%e5Aiz(K9Mn+aH zS4Q+3rw=H;3-FO?SoFVL@qgZ0<4pQYr6vqRusmMkM=Ne%KSj*jRJvzgCeC*NxLiIX zy7_k+vTH&uXGAo7(OqkTmU7jW>_;w$woD;T?G-vOpXZJ^Oo~j9A^FRVEf^ei6mKap zr?M71R+%}&Gi~>aoaP{h1!v2~N6L=7Z?%}Lf2R-#h8+Y*6(#Onwe0x_|7e|-yfDf1 z<01Vv%brnD^yJ}^Hx8vogUCIiR#M+>LI5qI4@+oTR$o3a&K-i*Fdgs+zkrB(wsA)L zIF~n@#03c%*K6*l?Ksn@N#`mlEl0=OzZ`r~6{na4pL9*m+T@tK7yhJ+y=q*Y)VU-` z>F2ZJnoLgIX#O>GN+$mnV9@(PLi{JV66 z_d`?JZ_|W~5`#4RQX9u;fBcc>+4#^`vScYSR&pGi*O`+!0*tU=Ck^F8Q)<-yc4fS@ zpq&~=(NRdX1J7UzBq*lXS@cGY&mWc~;^T?PmZgI9UbP5J@w4?%p7_UpU<3&L%G;E; zi+{>BKGL$SrG6$Rr5hQ;MhTjgqquO=z%r{OBBNArB)!H3vZhjmTY+Vzz^qMNvx4m` zmP!MCnid~!_>Od)u8B47!wQ+_%BafI?=jYEsY4#p)NtXly`%xU_>w9^&)5$t)dXxm z5CfA=Ken^h-PaESZ`YA}Xyjw3M9-M{R<3jzcXK-z$>O{{bNarl_SPqsvbj8ngHcQ4 zz#|BBc}6aIJ*%oC#$2jV5RV=jQ0~VdxtS4vZ%P!)uv3_s$3AFIc)TFwRzM!Z`b>T6 z62PC>AuF}Byt={w{dwP?EQ>&)zbcBKx64+;_jOwVES#xH<;w@-6T7WsJ2I7xHPXwi zW3Zx;}GG+#$abvuF4 zJ>cfGzvj2{YxOd8--3$rzkD8k>@!kw)brGfT+PUz?$Frp!8y!;!p3Fpd^bxWj~<`N z>s0{0*6HOp`xjG9{J%X&9e=ELsiha%r-lnf+ox*_E{fq3{yr8KB_m|oASF6hX|)tpjx-wu>CzN2LQ;>vu>4%v>xPs%rDx)1J#*48{*Ts=MS#A;aK!k7~ zp5WZQMMbCXGh6_!faa?;Lf-^N(lc<1;&DbVxJz0wO3UqjVDafzH;Ga3t^uhS3ot6S%*$;R$1n#&@hIwZf!D`yC!&jWI^K3 zXcB3Tf|`%Fi7@t$FP$0P29#^ZQhIH-oG~vI0o!OZhDt}(53kTtONLvZzQ<0~Z)bIk zEZ#O6>`*6GW!wgb0FBmXWyRN-F9D}axQtGCywyTN^(6T=R8ntQ@AZ9bvJ6xX>=3ur zIH-MoWjZ)2Za)5X%0IFs&dXoWLHxLbv*-Fxrl(2YeHD+)QiVi{f~jroXxLjOR~QMN z3(^|ezW!-cjEeKI`AU1o`naAOn6H;*F5%esA;8L!>j^~em%z}AM(*2TOQ)!}tiP|s zW>WwxV3ee9?D?Sf(g_H}98wJYqjiBJ%?mQu5toUwPcWcp3w3JRA7*rbN~u#j-Gu{S?mMSu; z=F4T?E;k-8?d1c9vt7W$;eO$DwfGwzO{HE)s;AppzWo}1PX~8hUIgM$AL^MiCaX-e!wIKZh#D1+_`zoKydJ#cnTD@Er>gp z?BI$r6-q1CQt$zWctGG~23kxS}ikxo~g9eBy!+H2&Cd?P+6wadr7p48JliUl=qTGS8 zhynbHaNc($G?#Zez6CxWiWVQP)Zd(r^(=g(x8a^$b&&7BZoBgp0#hG!Iu3K=;@rZx z%q=w0mt8@#1|NSm78kAIRJ{6;`wDOj5%aY?o#RXCbTjSDB=?FlGiR078|8;*wc?@o)TOn^E{CLKC_r3O9oA2^?a9SNW+obB%_%-WSJ z5`27Th!#S1hJ0p-Xdy&55C6^>JO|7WRjF`V@v3oB0v2Ov2L%n@8viAF4Iz??L>V@G zbC5Y?ed)POK__5MgfR5XX`^%BiHN|Wm_wlb( zuI;}WP6Z=#rP?m!{1e%E50T%o%)urnrr$%f2C#EMVR%?O!kez|(qW=ERqMEL$^-Nm)76$AUEi_wKd@)wH^q|cvO#@V$3ATIJm-bug<9!_T25a` z?LADg=nak{X0M{bDo|k!(f5gN=q1;&!iU7|8zBVP!GnPioq-S(1E!AgIJaX1+pr-E z_)NNjdsOQFX5q>@b zMAgYTUFP%{7#9w7(mJLBOq{&I2ixY^xAl5m&%DA~ZCRvF zIUHKvpJ-H{Ou6EEzd&Kyag`6D(Y+Wh@bcWO4hg2~a^4|93b%1H>dCVH}x* zn4{)QEClP8XU0v{BqKbC{TY`Tx%0VioR=mgr4IZZ+JkwCaQMds6XKidi4kJt?_bRXu48>zZ`&3|QjTJ=X5 znO>E3WY$sp-9>Ze=VYvni{KuE&E=7#cX+fnHz8kHKKpUw)qZFGLU}si2bkwL&|4H@ zeZn|gPV&VMt>3fP&IJz6FHHzwckKVx=-QcJdw%M?Lofpn-^rs5=x_sy$tN*%WwOs{ zP!|?z9GLsOa>TQ<_VM(5T?)*2+j7pS%Fu4hUTd9D=jZlD!SQuZ>Rz*(Z@!n0xVY!x zSGT#-n;Xd?XuJnxcAQZ&DUZO}mKJQF$(I2=MAD_q8mtPhdNS znO@pMW#glccxhG^T|5T#&!idF*iU?UuUZ~QoR$1{3_tr338zcKN4oXBtE7i-c-Doe zV;#`iAxDiEn|@)_Z`QEg^~lFP=m*P>L#r-n4L0Sk$0BiKFX4oRBQg{m521I4tgmTN zdS^k`MCJSmKW)Iud2dSCXe+8-<=dkwOZfebX47gY*DlTL`XAac3G1HpfD|&1Pk9gS zicIM;#$CI=Yl&%$Wr!l=y0rsUv&aDEV8pg>exi2;lYRGI{IRfHk00CUsNDYg`v2&hMiq)VxMx1$U4N19~KTp?&q(P8#?m38qg_J zE0iwt5sfkuolp@CtTM6&G5gNh`O>a0(T#NU4FF~ip+R3sB@B#6RraF4RjU8kempko zXyi@jD3@6}BeGL6Bhsny)1_*$PTRpr*WIWlD-d_-2a797W9ho}dk`fEy0Csr?evsX8!o1Z!2xtgipFbF6N#337|m*EP~mM%i-v||#-F8rXEfDmxu^HAG#PTbcFy4x zSPrh1p^j-_+&A#oL=;uu?s?mJoLlKl-+g2!)wCPmsY}=uE$IB)hLbY5K)!|kfkX`W z!6{i>RK{K$L^9e1pyB#C#{5$lyh}$++Jqhav5+GQ?%PRf)Js}k&LDBdn>~I{tz`9u zk&98KHj8kzOaO}KuvFAKjQaz;bR+h6>DS?^Ci4m^m8y<_>kOSx{ZJ>vp7+hoZgW{+ ze$RKX;kJpr{P$X6t0Fliv*-vCoD~_c#BLlXS~~q1c%N-o(YcyF#O^i$T{B6q0RDo; zdS28N`@*o#Kuq}?FINy>pGzmr#(mF@M#4C|)nGifYWNV@4r!xo#I4UDS#itwb3Y4h zU-KDyemZ!uH|HGMBN@6R>7Gf8*4h|`f08k>x{{oEiy^aC`vmWD8$kWyJfW{*k@3`7 zg`QSciCOfEu6>lzpAiY+xp!|b*#pCA1Xkm4LU8*+RY+r7s}mPX`greWUdc;}F1&4T zc6rO*-d=k{{rC;%9pi_DeRWO=9@6@fnlV4wst2@X6&+wkFVVlz07-j}Yd=!@;V)0) zeTM3weSN?+bun8Mdz`9B!P_u<4R!JsVxMIWJ6mnv?hH|uzRNuyC1LsSZKK=t zIFSJ-WWv+|YH|1~*z zGx>?3{QpIzuXOCjOiseK*>P!gIWhUb2IGGwge642M#+Swyq0Hqc}IiugUx=qo65KO z0j|+T*o&+9r@gTnV)6voN!z653k?dx>^ipg@QQ%h@h*yCZ(LP| z@2lj<=F?Wauy+)#`GC=UNxL0eq)#S45h}MF3z8eI5(l~-s8UxMv!P5N zSa#k`k3hc#M1KsJ-Z>^AwQ0(Djw^nuBBnLciW2Z0l5wFbq&t-y3m_x(toIo4gn}&d z>b{>nqdN+=Z6OM5wjLmiiy|VFy4McbppFre<&c0F zMZXKjN6?`m_i;<}5BN{dfWh-+mt+#zEf4XIo1}Km++IOfSZ-LXQ*e${ohI9gqCGC^ zq^M3`z2*7RcQB~%2{L;x-)A|Bt>F$BT2FCtV*4nLEohSZ3}qEKRct%Bqg+c3R`r)bPD=`kDK5#^i(FC@zeum3JY{ z)?w6U>Hxv(^Rtmp(@Mt05rFoYzAgzjU7-3a^igtvEy3!`pV6;EPz<1Kn%j}Q4}O>6$NSDFZAcm_dhbwO!Cs z#}6^xL3wxyGzA!ajgH?tg#J~@TmNVxtw z)vip z0M2vV^fX^7hhdgJTQPCrt+AvbT>~$!e8&qkgEbLIXv5s#?&K{|aO9~dT#P2ZVVN4R z6Lb`iban=JDF90ah^L;i&FK4aU7l^p{XXWVgXB$c@2@Ry-)6{G34I3ePoB_Y51)Xmkr$cjp-9v zrg4Rf`oWSZ>ON+*E`&Ym=_Lw)-AkOwe2+IxGo-%O@!>3b>%y@4) zj4ZS#4%Za7{?6@NpRuxCKbtMou6S8STinYG8<-Ko_{<6ceqGObzE=y2ks`j69eZo{ zs6@#muD#w|J87g6Tur~c31e^R@^(kIO7@*F6D5D$m!Qt} zWzFlXjl(yVpDN-x-(#G(&V%);jCg3u)3BlICxZNMmfEbbL$6%!++$2~>v(zLeC5RG z@$5&wi$PA=5$uY#!&?Gwe;IBVS6_A#|+mBK-5SY_3hLCXYIz3&A>1kUB?k%m03`aHL1 z`Vp#UufBX|BzWeB6IKJ!&c6!qmE7Y4C`yKaYzf&PjeN{-CX}`y9Ic1;4L2yvHlSx2 zq25DyRv&sT$>gV@y`sTow`gGi`Qod667UuQXP@IeF;ZL8Ya*lsF-&jom^DSyG{+|8Yw|+s#Z!_-qht11iIQsiV!ORaV zu*Hu=_N58LPagTS$jv8UIC`zV8ERf?@%6X+_c0v3=zlr-=fV=|WIkH4S$F5WI0M|v z-UPbFsK2v!_Tv+pSeciQ$^30TF^hYR02-9$zTWb23 z_)oQmwFvlG0^55D#XeD9O{N}Cr*0p=Um@q;7a8Uu;NRx4-LM$`P61N0#A9%^xMT~w?{hcM{N13O~Ce^Dab+of_q8 z)d%}_)4)X5VQV=xeO^JyER8Y16>u9%7$m}aPpnJcCZ&W~Hr5-Be%bV_Hx|%uqG`F6 zzL%JKirzES?CFz=Z!=qQiE2S|9Ql@zyINZGeCY{6@vrKatKQ_11t-=%zw!sr9? z9L{0`G_)Q);TJ?P*C*_k??{iLKo8G}(t(5##dEEW4?`GoL)MV2VLrwHk(`6`QLD$$ z&K9vQ4{V6#Xz_dIYcdbs-+yK)VWhw3erDn-DOX+h`%HO^<@@aH zme#v|bC(J#t5EXSYj4q|(vBF7-adu>M*IHrB%J0<&WmaGZ~VSV_@8t^j-*3KBl*V{Cci|k8%LHC8l(K0xNHmId@6M5;t%|2BlxSmd~0CY9?w-^TH8)I9=ePCm#^8Lzb^UYbp%$`#Ct{7>|ru zh1Xw9qwF4N*m6srI)&&02MocKNQ(u)8!7JFOiQ0J4eIt%lXz2hvk(qb-uC5Kl-&%= z$}EJw+^TjGnqgQsn|jHok5Cv%E?(L5KL|4{=MJ2tR=XA{EuPk>U!(?EOBVf3mh29@ z`peNPkz+Xe{Cz(nH<>>iy+u*a2Q2KU3hBP{Qg*O@aAXeIb~L&erYZlOPT0w~yoXle0w3#q(-$1}l;j=kD&55-PCZtP-$Kkaf2wL^r zZP>P)A_`|8RBC<5B)Es|=U004wf0W@StPbUJ#t{9Nna;Z`zdO?T@e z`keOG<;V`ko7N~x(%Av;E zk&P;tVYM5`_ld3crq*!NGW95$ElCn4vUt)n8WfQ8?d*kg6!T0xTn((^;oLDNtr zTjW9j_Dip)9D1@0w8eKj^|(cHI(eJkA4`*bFif6lG8lgt&-LihQcsPNyOyxD%68k> zck62cgq(Hyt(2rxPv_-YpsHpz+vG5*K_;8C1rm*ekVhS49Q$Mw@=Lw1Q_y-ga?v-= zrFo4T;c1=%L~Rapr9^lFxYzk0Upv@Qw3%)@{%tJ19gFq(_6i$qEP{s}7?Az~1JZx! zk)pM`fiezS=1*Hu5 zJ!hsyt=qTrJ-ORnwE~%5bS*+FNGwo94BGZeAcPGzwb$LM1`TqT*uSw|F)p-s%el$u z8@0bGqtDFQc}|P1*7I}Mpa5!-r>5vGcxdb=Fy4$s90S}1Mo(3Wtpb(0 zSh)FcHYr^PLEgyp6*he)>1PP9es^A4 z7NO@K)#e*b0E})wHzQr7g#9QthrpiD@92DqJAKjHIOee(7#pI2_xiv~_w^(BZ$!Eh zfl2U2+3m6%ELZQg4VK_Ll{1&h{=X?z-`xnzVMKb4&-xi#$Bsa%*Uuk1jM%|61F{Q} z96vr)S7r&<{_%p6CH1A3Rw;zT@;bNmxsRFz!IzdL)^R8CF-rh*b9C?VlBOj9!1V*m z?1A_uvWDzf@L+vsjGZIr0ZGRpeaT281N~C_QdG*)?7J5Gw#=KKoHC8Y=f28=Zr;$50 zu8?=AEUkGxQJp>>xIBz}_j|MV_g1m-VA?9J$feS5aB(-docZN6$-!(Va(5Nz{m%Sr zVMI7{B6N%P2@A3#3wVyI#pxUceBYp}^BN0=_%JLtMt=K4oiD&4L`mYv{;$B6KcyOQ z^0I(Gz5*{s0W4@jpDW6wQ~voKJFUqv^THe%WvQ^N;CugHcQ_a37${3sTf?<1XzfE} zPpF52^T3e!%Y&(c7Xo&l!ug|r4PuQ$KDd}8bU^f@F>cDBTKkY>Ep+LbB8>DY)d3ct zF<)rfIL)a;znF@6564tND0TsFakj!)wf#V~)(wa52}hcQ>NklY{;?C4Y_c6Y1=N@r zJo7Vmva9dCu`#h_?&ZOSeVTXTW=*i0%>3R71?>9ORA1TN1DcMidqPF`3y|&y-U+K?R#f1kXm$82FlYj2$>^5 zo9LrUQNyRcfE{?iBEDX1s%C9OPjF5E5jMeeCMLCh{m@j;^qFC)DNgozfahn|PJq zFtxZ?CV>Bod=HU%ksN$7=m0o9g-w)*MQ`c^huyW#e`ly z{`+SIXs`0AFEDG4NvawCmIv5Z1_|gJl9WyOSUsGZ5);{)3z>p^7J zdVx|oPwR)%!AW-Y^5?CCr@KGrp0}Qq(6#C>WkMaOsg~z)byD|KnnW{Jglg+X2D#X*)w+U> z_hRr=ih@&5LFFqUPdCOWt_3tFwRZ0rU$+fy+bi_uJq?jFdO@_W;HOEU&*xGitnE_20z<*!~H+iY37wRjzD?-MZ>89t{2$q}SN8dZQO(WKk}5Oz;<^FN3bo+)fgsEKlpU?8Yuw_QLQD zGy`8#&s{sU{94h>sJDC5?5xJs-Jlr|=HYURt?wN?Lp;-ox)v29hFw&(7YJs;Ls-51 zl1Ixo{*U|R0$^HZ=M5?e+IF!I=N4maYV#qKJgeK4_OTp^?B*PSHGkpa>K|#s0dn?z(20nXs zb}_~LuiITRT}G)IuB2vc<}M7=m-`H=o5i~GP07~7l+Xdo)vv07b&g+m*-An_28@Of zc;p#^>|jG9E@veUH*L9&rY1pddSmW+C@EFMFu(Eb>~))%(K<${Uyk-}=o~55q~=3I zw#Y2JIgr7qq-(vpkk(&|Az*aRUQEo}o%HT_M^KQ)! znk>yykj)zakqh)eWi2iHCPJz(AbmZ0U=1Bt`Uj*(kdA`CUm-JgORkXBZjSwHJV^=&2_^e|1BJT;De&K>O($S%o}_bfTYI_ZI2$7$H8k zH_`K%&R%?`<~b94`wMviLzi95xj^^6#3=buBG*^)YdMK$rp$>mYV%Lvbws!#E#H1u z4fJ1gQjXo47N5HpQ}iVY5WBSz*@#x4+J{lhB(qI7Mu=-OrPLm#qFT$U?4sFd6yR~3 zVlDQezErf7n(4zuIHGAb5uft(6-A}Lly;NdMOJ1|JB#l!aORbu>gY5Eq*ot6yPyek zOaw>U*qv8z7X-eYaZTK+>vk?I6udtRqMmH|?fSKGB1D{Wb)eWWWQC&sb~o6j_@m*$ zt5#E*dI7vQY~^*lgc6gKPei7TUb&e|AHo^Q-E*ym_gnW+>~{nFe1nk-7kuzF015wF z2O@EcbY@Ub>bBdQ+6|ozT;QWGZS6{&>`$4Ph%kWmrP!X2ZgYRJa{KwAZ$ZtjNqYAw z)I9^w<)>BV)6mzbN~slYapVW-hG+Bx(Qn$ksm{1vezu)0=FjDcFY)Z@G^5To{EJR1 zTW>@_LyyZ+77wq4Ko5KWiuC=`rS|B>w`VbY+%v}0d++abo=CVT?wB^U>Koq9&V$)X z*M4^%^8)iDFk(7oq`NQ8+JkiefEQ0h4BlMEi-Zd(es676{OMBg{I^d zQ0-Cq*QefLw}YPNm3eb_Spuc1SbhoELUtE#lQ*gz9chGK`u34u|AyHN7Ur5dO^cms z0#Y#Z1qO|ynq{yU!}{A+EABC;5X@{~1C_>lcFscQ!eWpKb&ua9N@1=Xwt4{GpgcHA zAq3%VX`1>h&_{}u10NDUVGG*UyjL#SGL~&+r3BrxN=N)gd!)_edbOIBp`cW~e3c39 zg6BuAzpMO-mn%z9LIu#`4=9vt?xV+u^b;77zRzRtvfd}p^ou%x z`;@A+A>@6Xb=+hZfq^E)8u0qRB7NLHk$x77 zFP)Gp(8enY2e=jBGKJb~(u@_&lZ6-W#lgOhe>VK3;ORPzse zR(|Mx!Vs618MT-)>#($m64lLV!2-0lAJszAkZ&L@mbDPbuUpsMpzt_7jng+&W79q zvz*baB4Q3{&FPTk4>ziwS7n6fXTmCJH##m%8_=&o#luu)yIHP3odR|752<|nh>b3P zuLQNhgj1!~g;U{|54VUf?`EYcjZB7brpRhE3r%qllS)x4eN*I-sc*qbV(fxV3JfihX zqu$|sDw4jGpH0tbpWW1W#rF_@ZPG!i5Urt!!v0=MAKEb)d>^OZuK-H4Mof0ZcASKB z52MLjf0Qa{pIKZd{-a7~G2B>xkOCuRroKd86jDrIegziREndbL$lh={;^I35PmT>iK`I!KUej+%GLq_PEU;{A$kTL(##;1n z1QKYRZr2F#t%n6W0uP^mmxVVv*(uk-=o0Sd_0FD)SHS2-eyCKt7obmn9nXT%=NysK zAJ&p1P-+MTdgi~Dyy!?FLI68LCfz}@mw!bY1JZkrC}KeR3D5t6^a1I_3V%WRGz>_8 z;xWRei~;FSAEy)3jtA}<{59)6(}}gx>?QFzMj~S;0*k(1ZbaEj`b#4i|5hP5!iMv* zb}R8gSlU(|$WhYKNfK@&kmD=e+z^vC6qZeY#>}|cO>qe6j3qRX5xMSQZJ)54vxTSOu zESH$|*+9xIuU42xAu@AC9MB3H5ms3G3(||!qlhpdy{+nJ!=(x}D7d8pfP48c*VNHLK!7f_?Nw{tF13aeT9OCvc-+00(;4dDC-q~EBan{4#b z=EZ>Y-!UM)<3EtzSNb1Fuc5Y=E8)iV_}i=%$N^yc52Sx5y~q0(q!%nLKQ?fVFb~UD+hsZ%mB-kFX`UlWwD>`GsB`w7a2+!!G%9T7w z)J~Fn@y~IynLag)082HlMc~VVR_&%!LUz~V{tDxN1a#bEyd(@rkAnf}IWQnS(WRk0 zcE}M1q$fYd!+`X?|3G@oYt0A3fb>k4U1HotPeS-&oCc2Zj;3)!7cRwe!lcaCG;?OY zuEmk={88gQFQz1k!lYO^t`$J5+%H$-S_yCFv9A^WWUOHOB$W=0GrU010k{>`#@JWm z4s%jYXs&4`%m0e(r$-c<7uDC?C&!2{*1@LQfk!PrV5`Km9Xap*eK)Y>Nw2ksZkZ;! zBvBh3D`AY`2pk6SFM{qnd1qic*1yWE{Xrj+S690%Sd}C?S;o4#-ndo z_@(c7!x6kc%(QdT*pNC#8ht6R3kqan&xw*a9R6|VW^jxnfc&PR&x{UO-An&BPlwF4 z0{#sXLCDcDO%qS2S?1O_8Bp|H&c{}cxWeZ{&=)2e6ot1MTDJpOETSgyHJ(lVRwsTc zSyK`3)&=6&I5v(0f5UBP?HX|{{JCUa{6*mbhlyK2W``iRaPn)9Ln!XT5*`M3R~h4! zJzQb}1+n!9nTCG#ib}EsXB&mbu1O|k8a+wLHaZPFwAx&X#FW6i<#8wpsBa}=`{g!Z zG{`gowN2nb59kQuYRBZH(Aj8v)*jUxbn^BvQ3#ofQRUx-qVl1VprArf5Xtxwg@K&{ zJC?*~P*H!-Nkl{W=|0njr6~;(6N9ecKdfrq+d?xCG`%GWk7yVZ?+BXq$bq&^K_$5a zkPDaZCO%*)Ea?xLzzF)7(;AmiU|I|ck{CPdDmCW5uNd__APJ>bmU7`lMCV=2b1lIrk^5Dit~R z{V}b8W1SauXLqmsvd|0}EUd(1>8}LE_R>{XP++Wjl`-BQTy?z`aDmE{p1Qa5I1hk| znO5>)#z`MU|1l~hInimZM|?(JVQy74N^ zE~Md&5e(h1o+~?yl3z*FL=BN`d)~d7@w}@-$CJe#f0u8JtZ1u2X{>)~WM<*{#%{iB zPC{C*an}x)DN#;j8d|+2biluclDoiPbVpG;J7p>;XSGf9f*?4D0jIAf&?SyhzRfy8di7V=Y=krD-&eZ$>t539&R-Jz&_#4ag z=*>#D;V%FSkUd|4l_p=1LQdg;3gTAORlSRJun~s`3UlyaduDz7NFz0p+uzS)-n*3sBaM zc3GW1Reu$gJ`Aj4MG)EZ?fzk%+42Xp=;%L`T*NaAQi2_;w*Avf1m^I840Jtz+xQ_} zEoT$w$!yWjfew#!!uj-QDb>VdoOD8wKNdc|1K);&`p55f4pnlnbAf#?Af`4ibym7L z>t;~|F6FnysPToUQBw&OR6hwuWK~;a_ur7gs@{>gn~6xF?W@0LEKHzixS9{Qu&$- zho1Ql8?W(s$gj(0X&uv!T}(T?eHx-Avxc^@xezpeFndNW#K{uV`K73$XWEh{WdK)7 zGAIa(0{OS%VSW$#Y%(NvY!qsKt%`YF(x*|4Zk2E2k7MuPVUW(kFJ zHu-Lhx!B{-SX}4bf6kkh;+|&bVL*lI4Be>56SmUp7c6hRlpOo0L0R<|~33sCN^DiM^0oLfRA}g3@&VX!IWJ zFuZ8;1W<&AQv~BnbQ|H}#yOp?WgEXNqE_mdWEnEJG1l|2Cq?`=%7%F$GA^J%6rRg0l ziSHxdIUM;<-?@BD`lHeRIUo^N?2kr2V9y^>zClB&`4-kMJxs2RtI(nSjM#}^cii>_ zqtSECJEBTT|D(~k3DH!0fA^PuX4>d=v7z{6pNcxZLx;A%5yN zJ!vcLP_1k{=SGxQ!p{PUUJ{#g*Ll#~J4{{v7K)pcB;+;-? zu$|3+GdPv#znY>W-=E67UJ+ijf> zYuJtv`f)7qTVcs2?Wb`*iw(CX?lXAvDYJJ(mMadn5iQr3k|W8E*i?Csyr^wX2p+v-15$MYSNv5&NXYV-=dRXEZ6BfU?n|2ud*KbLGM%I! zn@=w@XozH_ug{(l4Onv=F>OCM*u|PU6g~6_!KzB|l=~DKlfrDtMBOo92vF&Xzv-=*A6x`i$l|A>Qbk&6ni@p7~yc zYSCUO%DbagY}J*vLJRc7H>EkmtM;n0RKI2}Miw02R+uou&Q&j2O46t&R7-XH8S>g` zqs8X{>QLJ}4FxFR7i?j;S`wNL+_1eJ11%Tkb=unM%|}i$!~8O9o)V`&VZSn zU>4nw97)iYrH=23t9wA*wPK2~Ov0IBat9!rsF*&m_MWS@=d~GGxt{s(p6B}_+Ise>QO|1K1;eCQ6a||{uKZ`Al zmCo#W&@B2#0lLJY%)M@h@Z&4+&Qqnl2`rp}wgpiENRUs{k?K!ymUsHVn^rltpe<{1 zy;I}EPXk!py($lO?tXY+ebdI+RpXkKLgZO96XQO+t=3gj`l$SoyaYH*L}CBNs!1Yj znf-@*y>t0rjov$X&DSm#zQ&Aj0;PmyEY1@j)3^Ta!w#oSv*ZG)4`MX>FhAq7hja{w zfkNJT;yJ_%)wL@ZKWd)=on${0g866KXi(5ug}D7PHl1s|b`YnekzTRZ;epY%pzO?F zjou)n<0~MB_}MA<^@{b84DU!p`Gv#B7CxTOu9X2OulODgK zAhN%{Thls>zM-=ooF!n@sH1^Xa(qkJn_SIh_Y6(js1#UP&3ukx!W5DccRF~QJ))cYq0sR z`6A3}IsDRMvdnD~p%0&>0=QR8jXLfM0N(>smpf!>-P?&8^g%?nGXXUy;o|eS;u6z@ zn$pTBgSQ>~%_x-m1L^t>=Lm(H1{e_;5GcBKAo;OCW(x zTf_^9hTZb!cm4_E;zthzK&oomHiCOMsm3q%@3d5b%MX?<*oMKqdeS5UgXbjFjA}M6+f{^OhPPUtl zLkR^dAD^3(lk@KFgWFSsinr`7A+K8OA$)`m@^`0=@5I)*8FaQKi>`>o##Xtt4!3Pa zE5t3-cg$Do*u?$7(&|4&OEndb1v525hm~h?}KY$z|?~-T5!YL$o1i0u|}1*uiD|+ChR`E8FTDk{K7@) zyukX-E)WyR#my?(r5VhcHOliYCq??kb*050@NqGsktJIjF|S~gqGsiE8Nq-Ewv(@wvKQ*sA3ykH0$my@JoWx zTCGpiT>tZD6s^0De2b?xec)NZaZ>Ea!TA{={Kf3^4uans>1$uDf}{jk9}tMH{2+AG zf+~U&VNAUlO2^+!h22xLIL)1*N?P}FdFpu8T%bX>@l_a+p77V#fhW>ds??k+Y++2S z%s;u`H~o5&7$}pxP|RTysT?_wgPoX=9>w!|@!^k9YPG)4<#!{Y5qwYMDjcB06plx! zN9z{BYGtq;Z-{A@PttPf|0Lg z+zC=%jQfF(AHk2|Ke?|z;eS&pcrp83>60QF;Bg2iS%i=}X^`Rou z1>8cN>ouXhx{8j#l3{vksqMI!EUDQ`s}RYMk}kHno40h>(72eKgSZ&45a(--zgx+l zLlp8@I<3t`Jm%P_rS=nJvNUHetwUbrlu+!rc}1*CaGwqIjUfj5>NJIdn=soqO^h(_ zXvGT#Kf}2y%i^tv5${&r{MqoF>{^P#@6;~_^54d04X zCmoe94IIZKeVC>0?w8f;k9lKM6#&>%4Vg&S>j5WE{xtS77UJhd?tRbLE3*9epi*I{sS4@iRBI&f`eTb`i{&MI-2Q6pIROtjGwQBpKKiE;?xDrNrqFOylFS0cQ!m`OfiB^^#Yz4nyx+rm3sHb-Rr>>DIplw_@F zhJ6K5tv%)F(Ot-ufOLzFN@X4{JMUSb&XN|#WOGuCIvj1KaO?wBjPIMn4>p`g87n$* zd4Xbj^jREcQa0S6uGlqB>bcvq)=VZL`o*DvxpdO`q2up`(A~3ND$?-H4TK(4^F4KX zs<$#hu;q&S(GdO^x<^<9_FU^oW}*l0Zp}lk$Mm{XaZmR6h&|H}FanR%=$kd*RMlF#7Qob2rlCmo!P<0s^GGGQ|7=K-(xt^X_1KltB7`UF1C zGgIO(KUN<;s=)gYxWe_+*0Ig0ow%c<=)KN06*xd2r`o?$k%gb0%qp5K*n$_=8f_uH z0t&K0BOQZFcHe$~Vg3F|H2*n9q;LKw(u+kXS$G&}zTn2`9*Q4oZ3yc4C(=upHuMiU z$EBqG73uM~y=ZTH!af}!_)PrN+^Zpv-xnV7aUOZrvOFjyZ1-EB*)Mr+e$3?`Jt-n{vXdHUkzy?UJUJXqP+n1( zw3hPC$#z$udTLnez3nWUhg=!-6WQw;+diwx3PiR9c@*Q(MbX9Dv$A#fK!q~L_Mfk!HR-}e}6We9v_B4(MpQ2Nj=bpkAd#tis{*_N|!FM zQ*=yY>-RsAKFdk>r&KLm1cFczbZqkxlt27K(hvM4=`+A(my(CG|44dN0uhF!U-(PX z=cnrJ0O+vtqZfr&#gr;8rqT3KZWe1m&v+CN5vcr&+p%cq(IW})ACexIeHP~+VBQq) zGZ>0nICV#({x3;i2XF44(|UgJ>tI{80X?##U8orHfKG4r_qxTs1ukMK7dRW#LTke! z{n)N2bbigkah;^m?tp-H!=lDabF|yOKD!%2`aDyEKx8>sv*Tzm*o@XUd12PP&CLx5 z#^w{eo+F3c<)^}Z*zmQz;yW;>37%*Hna^-=6>#X4{)ys&Rc^-wW9gp)zW_&CaUYrQ({Go#3G-j7#Kn5V=U;M4Pi zK(TQl4j+D}{B?{;uZ;#%-(P!* z8^0DIPa<}1lw0}Fq`&&FNk2Jx{78pUqAWY-qFSJ^V>ET!Y2EIzf#gkVE8X^az>?{h zra9uC)}1i+M_2_IlRiH#EaK4u#-!)QNS;+JH?!BJd{aQ7k7k?YTW<2-r}RUGOX$^1 zcOd#<=2O(fyF0{r@3J4^SE@ zu305KsIqW)#~pt$R<2yP6;^!jV#bm3WkDYt68n|eALsv>q}K#1&E3%4ei;mt*LoxM zijF0=R4LhRJu8_{h>+26d9ZXsj0+dfGW|tqO*0yfq>K#j;boC#;6w%56V!pSQ@pag zvYbYB-H(Bsx=eM;xt=DJKVnr}UN~zMjl|PaCunK(E747TIvEOL+RvqKo_wR^EeoDU zGQ*U#x`&I|pdVi;wau-@0x zPi`gmSvH|Uyg)v6VhC4t8+7|iRaJER@fPR12--Lsd*D=nZGAX(pQmwsVRlaK>hiGi zqnRL&yE?Z07k)x1!`jOB%_KGjk8?%qf-EZJUsEv~X4w9k`@xi}+gJMpuxm05E3l}x zM$L|G7*lId8 z?Gph_F=HJlXS=_|M~bE`iNVjBo@|OE z6%+c1YSMX(!Fu&?q98VRQ^$P2ryoHBTmg?B>i~7Hye#Z`=HH%1^CnJaf8_gg*Z!!c zcDE3J^ng>3tO9l;=ygtCp{%z%Bp>&~(xuIu_rdYE`m4tQeZ!*}%c&bGXtL@+w*mY_ z+~V061Cb0~S_vFvY?x@<{&~bOb4FEd%&X01Z}Afye=d4V<3y}V+WV~7kGy)L779%6 zY7{NZ5oD%;rkebPGFM>4*6_UVzF1|xlP^pAA^GcAqoz)Vpz}sfC zoR%=R6RRjNqP;D^{vB!{LG{z(zAVk56^bl~I5$89(J&i@lxphoSWLJ23*(eoYrIFY zxxiwS&}Bqt@7I}DX$Ah_XrLRGlyLjn3GzDknWO*8C&Gw&@)fJ)lR+BgLv;1sUnR5c-o$P*WDDoUCZ))8Imi6^g$P5x zCELt;ggvF}aSL9Ay|HAzE(uj<*?k(b8t^wlP+75va3k&;HtK3z3%F0t8ij%sUVGvk zeLsFYBv*mak$x_kO*1$Ek|E{34I*nC*uPv!ExNiSTF1Lw8$AtT1@x1@w!^)xL17$Ymq_1q4l@HeYXyGAh7`txwn*d0j%$0+a-jh zOqbwqK{og#36?_f3Nsr7vunpfLM5-Ijn)X?uuQHCh9SHG;R8+^;c#SW-{ILw`pN4To6Cx<%Q$*5OVZ89vtAkL^Nat+`IzNi{e4@Y8l}RZFs=68~fsNxM>Rk#kSe zBW(!=BDM&)%s4HPKy7RQ`-7Bc&UuJm`F`e`E&H-BRDjOxXLz&Mh?NS;hmGt z?T?M$kWsIs`X2n}sp#QkRM#1}kq8wu{|(fPWoT zZIq?(3ennJZ6e+XLpuXROA!ta^Hs@MWnC3b zUPL#ay21S%CI+HKcISo8@>K!7UzyTF!rCv_o-A78FUDQ5CL?l}jWZ!@Pz{1v_ySHJ zpF0kB!yt<~>a%QI0sq6!(WgynhxHGq%5YHSQgO*)X%BeAsE87dyIZ>y?XC~}D|Tr0 zQi;;PE(nY$uUGFn_K%JJLq+(sFw7(3+aBcrm}UlgZ8K5-px3CGd}A90HRt={)6 zjc*;9NA;OK{NLjdURg=Iwj@=i6-2l|DQa$)i*O&K< zN!k!_l0)3Jb|>-It_&9mrH&g8X=muK5kIXo6ix>&#lpcWEE2wMUKxQLevcELW>#8H z+NKaX6XaS0Ejz6FU(+pKZR9vT?bfpCnnu3t`QrE>usSWQ4sC@t8$(yVFY&0bmZf;5 zv@&AwOWK^|8jrv@=G|?71Lncw#$lQ)(1w&*4lJAV{8h!+v)J$ErIpUlGeiyRlj}8} z0L|PpZ;;JY(japtDO@ea4yH&p>h(;;=8cZRb_%yJzDOmZs$__jIh|wCv1wisZhe?2 zUacd`D~VLFi?_Q}9+CI^<IwN+ARs-^LdT6_-Fc&1}I+e~j;lh>>H zEcI6y<0L5m$DsZm{mAc8i>gEV{iGa&>eRYL(;3J&gcb3J4*!hI7026(>7mp4JZQ&C zFPYKawUrAg;PmQQD-%FKm~)$CWbZoSXxq8a1M|8jLV6?dA$CFHmIcF=}LmMT%YRNcLv{asOXwr*r-S{kDGFl5q9!R+1YjMLHh0@dYSjk~Ph1WUyg z1&gS*A^Atx%)>uU9W{^bd(S+xalXIFLrSQS*DVO(R(>M?_-+M`N`6&lurT7C^R_!6 z3(0-uQ1zwzrebMXK@CS3HWI7>X?$MR8q3^mhpjaK$3Eevdu5+~azPf9tq|I{=Id#s zG3bo{F_w0y_r4^XrWr3FrP{)}fme}jwSTnqe6QMkS1*oVqkr@%%nDM8>zv)YiMX|K zG#`cL{K|c}VI~~mc4SLsOr+<qtnqvq5oaDXE z--Q=+i@AdNx?Z|2R%3CA-GwXrdHW)PHLcbBuouFs6~co@2;1xMKz?H_wL#;lJ6N@)1>D<2l6nx5+1X{2=eEAjy_^b9zgS*U8v0?z?$*BSa@!U# z*|oP%oI5$O08g)aJD!RKDmKrabB;~eXS*iRg5=L z-9_KmuUcv#X!o~teCprkEUQun#dc>zPnk>Y881&xA?kAU#7Q(6kCMQDt9A==PRFbp zC9|~GJ%8*hnUg=i-f9vQGfF*!jrcYuW4LKm}+}A8dQRBKb`M!T>DpG(ql)W_iXa* zw&nt1;Q(rgK}!rR2#7TrivJM&1dAscxi2yBG0xXiEK9X(E+~1H8DVSJ33mSRnCGZC zCgsQV-#Gx$#(ON`|Gkj@iCjO2ea69Iihp#!w7%c)Jl*l{cXxNeN&TOO{@1T>i)p0Q zHmwhLE#Y968M^HMD6B0eL`vU8T*z^~=snSBp zbB|_46?twc2@hOyoB1ZKGfWEQ4NhU+Y`w*i3rDrk1Hq15{}<0)oqq=&GMmL!G2|Cy zB|kQ3cWlz8qj;$C?&bqAAO87$>*K8}N^6GZw@OjI-Tfsq5g(rWCe}o^w%^Pmv9r{P zV#YEaq3ymrvcKQ#8hlOsw7BDTHwb~5qnZpyvMW5m7*ul5;RV0)^L_ezge0>^WO80P-$CftQojC53&|~87|gxrjEfC-)#BOv3iGH z?2B&SsQ z>KG^p6mw7vcD7o)8u7jy(V90O3SRf+TR(k6}6B{mK1c_bt13VrPERIof>P57U{3N*5BW0!o?mH2I(npW!MLqbN(dl7mdcWV{+w7QacDGABl9}A>Q z1;5dx8osnh%Dc^!Tf1Gm^=jk!f^>(F%tnH>7oSH>Q)i&0eBa_yo&!Z%*hr9etd_0| zk=Egi=T-qg>W$f~yf~o~OA`1}+qVVQiQs4yW!gY5H>!UdXxCKQk-1#+M?$PcLAbe= ztmcxSu|&`5@>=Bj^e2>$&X3{mo`>~wk1w62=y$9Ogw3{Dx)5;Tm~|T=HGz`NZzukI zBMwStt6EO}Ih7X?rW&;sSW39$st>Qldd*H9Swf3Zs`+;pAoPmsB+AADaUCL(Fl3>eRu4rA{qki1byX%-wUr8SxF*lm$Mc@6p;-?)5PN5q|)>u z^-;-wO^k(&S7jRq94-J;G?tj^(ADdkh*UgSfS&g&jRHm}_lEVSXX>C;+_TsY4PpnvG#K^iSU9;Qv$cpf6Kd=5`Jar-${kr41Mtim+ zSGzor@bBS+Jc~uEV_%we`2o=W@&Vy&!^=<^hLP88W$CnBo>}jcMWwFp$~9x0NQY?d z0^B53mkb_44{QT%Gm^a|JWp>?^As0e?ylRJ$PN+W*H3`B%Z5Io)kdM!%-tau-SS1u z(!Pq)`46NXOcg%cXMC~r(iAcJcILOE&#B_&MRzo}E z#-!~b3rz=1v`D2kV5L1NiX42~s%Rc1Z-1n}t`b=u7JC49$ni{A z|0f%Qr!rkrO-nY%(N4ah+23%QBbPMx6&TRjqt1SAp2azEwl4%auAYh_i~rV`lU$|? zj~E6)N<^Kg*S)G}@_K`r4rMUeK#)Z3*4P-FG=u2o;act4ky zayFc*ms$rLASIoVwoHm#Fjo1_j{I=7h8N&T^3?dFl#WvVTS;w?z`4+Jct>9{F6~9j z#M2tqa^em(K7f|rbu+wU>%D`uoz$?~gX0nThB?DfjBrAgMUJuAgKmCh^9 zq#M_OnmJ^aRcE!T-bs5XGq}pk+6nVDs9G6&pDj5d|Fh%%SN*3`f^E0yU%JZ|%@DZL z{Axmvpytrc3y;&92MS3ElpAmTZKvDrfqr_|VU(L!6&zlfYsyD0Y+FCwRYAg$iuR;) zP;5&=XbcdaiCK_Jo3;3~kvzEjsGM^}_M}*3D>GR@1jPNBu6Z=a0Fq3c&nT!D(mfpD zI`OT|15e-Ckg1A3Lv~%YIt=0!`mo#kffjQ->W&a}RC8;_7=13tvE7F1h_v#;R?lj{ zo!0l;`PTY}4?to0kIOW?CR7KE;b(>u2%W;=fa*QLPv72AWHv^qI^tpjfc|t?TKFiv z@FfY)OK;(tO@C@u{$U!Ar2QN1&9ob-x+dZ0uTj_UU6`^Eh~PHM50oj~Ut1a#%uIIN zD<0g@+4z3gF#l>*LlSq?%i&Q6lljI!&6C95z8H2F2Q`bI>fCGJ6U7+HP;DdI#ttoh|#K;ao93t=`4i^;fTi%Jw{OeB$YHMg*-bpG+K+de-Uw#j%Mkm07k6LR{63CpT@kn&Nps9v!{%!J1;KsXOZc>;;<=UYSDTq%af3jM1VMKF*YNG zWU)I*;VLwaC~fT@4?4^~=i;xX)^9l#O$T21)J4}usP&kF2~(pan556ekR-d44K>s& zk3A{VqSI#56REsNodka#S5(|*A)71^{#5=h%OXa}w2Fu>o}_^E8M*H z(Ub3R)$O`jR7rYne^GcW$1^cvEz%k694n@&TU!tNT(dz5-4-RF_H0bA);3DMK`1rt z2d*a^vE{A6E`qKcxS{-9r@LbHmy+o#9qYe}*tY{1GVV=w*5C3jUsO$4kZY22IfxWo z4d4qP^!%2SI)Vr08{2r+mr}FfybTSwlxeDZ4G5pYj2qTvlIz>cmtB+d1Ms+?q+7GY;A3NyYg!q%LvA!YP?T!Fyn_>Vcv{X z532=xx9z|lT~DJqAniY6k-L)F*zF{;G524=Jz1TvMxBCqp|{dmdi;e0=LnLX)7ECw zl71!lvA0v`S-p-E?Np{**BnDcsQ$?1{P?aZ8#dfD3Um%zNIB*XiSG+139BNeCGHFV zocJKRL2A)Li=D&W&{Qt>-2!Qb6%i!D>3v94P{C6=dp(Ait>c1&YtgK!>J-C@?CIj| zJ#Q}_UJe#f6-3nHE2sjt1vBN&Si7j)dER;PoW4-$nF8V~qd0S2XXS=zI8kdENN)+J z4_c#=@|`8WzU81TX17g?)5M>gT(UpD_AM9TLvpuTw@su5=d0XoOn70Yo89$tL7$rt zdT!@~-3nK&(AGGFU%NgaBk}D_!fP`)v_PzBBb+OyDEv8~kYr(f=6ewcwG5j{Ymv?i z^*!KodnLt_kP}!dESEUKwIV9~Wmmlf+EYO8Cl>XbxG0iGe}Bv}^sU(C4F~pk=~Zbh zBW^jf*yrT$@}lav0p6-k?r5Ix< zsJ`^%{Lw{+()V^H8k`Zoz=sBA)eQFT_%f@9WV`oc8zjC4(=f`wwirR4$yXn!tD7c; zOg{fB@c)U&yZfPQmYwHlINi=Gp5Aa%TFU!2;u#o|vg|)E*UpIYlN#?Sjjk&kjFI^g zF8|gM2Xxl*BFv%xX51&@+USS?b+RU1JhITdBaxwBdv3WvMAeS{gXuf@x98d0FopRO zdb)9;`j-I7S-W;O&}J4;vBvbXU3vwCnQ3ghJKIH_e-BHEbmGZC-*;Ekxbgxt+#l(k0xZ^m^z=xm z7qW97qqoMB(QXC-VLbaW5$XX`fC%*7{ScWofIb{^?$s{+ZXb;(J%kGiVS50yu=9J5 zoxzaZbSoqT7$&!KbA69!IxW&3u$zwjonUJzv1LodZefJ6S$aDl) zfXPoP8Vm%yxmqOGw7MZ$`$T^3m&I+;7@{V^+x?^_!Q;iAD{J@dlwZ76ypxCZD{VA-oIW!GDCv*R|20Cn!8NHkzW(zOr| z$3+(KeB<%AW$jNdg&XY0`3wIrOOQXYTHaYBg8tcH(6y9XMx45byD>Yil_N^09N4r~ zzzUpyR=j2^vq?{CAJ6nlljj{t)GuB;00DF+;;yAZ>;(qeKR^1WF`zp7{B9!L*O|U) z+{#>Y0Z4mL5!5h}0qO&iCN)5T3!HETYgo|z-;>WaCBu97Nm3f5KenJE@|+%=*9eB| z0nRRNWjtfBn?^xTxiR5g7laKR=BZ#W~iE1F6NA1iwapRbVxJS;KCpXa;JPg=pnEn zNAh!}2MAM;GB{Cqr+J^n>=@ym1zqJsLI~j=+UGIt>px)SL)`_I>%UDu^YA1c>@|G? zCznC@0|H=u-!*u?X&R*>y788Yau-uEPOE+-8D-v@UE0h$tn8Q<%kG1QB^G-P%z z9FgXAv3CorwBt}k<$FDddgF)rQQ0w6=yP7=XhQE*rF-{4eUN4n-AKFh##-s}+@44M zCwn`i7nkBNBLiJ~4TZ?NE6OnAji{X>mk=wBuZbPScqmi_kflUfR2iu_ubd#rC}0}{o7CJdiH_#+I~jW|8B$kjwq#OH zFDa${+C63O_7{S}!>eEzZGj$kX)-4@?#H-^3qmE4&B@oI0 zhkrmh3haXk4Vn57Yr*Bh)pRQUy)Gn+V<^TNjQ~$hVN=HVS=gY?b06O=j_{OQdWm5h ziD7)UqA6dALLb$%^E77%qoMN8IaZ80+P$p{-}Bn_e>3c@sdy^#%W6I(t$z5Tupuh; z`-uG#5Oy>bfFp6bz9*Msm^#a0pG8_9DEUF4*t)AQgr;)XdG$ubuhC;-z~p=fEfC5Q z3P+x+xct3PGZ-PxrZMY&J>eV%|ap&6{DhlrvX`%+W;8 zRUk&3`G>OA(~-mZ5B7pp_dDF1HTGMc8TsHS5+oZ?bnwG2lQf!XzF5+NiE_nZ zV+ui(#{~4WuMAK!h*I*>r^Y`0zoU@W7^V`t{|{6z;}r3pCJH=R`{?-l-Yaf1{colV z`mBs2ml2daR^MK8Q5+Ku$6!%DmqiOf{`tt8=efxVmMThn5x69L2d`?E>XarvnUs{z zHkwrI5(-x_l-N!arY<@Fv_|N)j>wiZS zqxt;eO-~&;^#Xx*-OmF(mX-tC&#mgUXf+*Gb^WFJO`p~nG|0z66`~`+hlSxWXfujY z&o)==Mw(bBqXAaDJJx-yThMM8(S+-w5peOdXO#%jqM_8CciQ;oQNXWVlK)r!PzbxgkG5^NowIuXaq81l z?c~HViK2Ca`R(_S4gzWcBK9V%#qR#A!}omlHYKqU_0~(;?HTSlm!z{wYf8vzh@W>j z`3p!CwnX9lU&H5?jy~Y3OCYLQL-_hQ)uAlXth*~~no7;E+I`cnLq8L(X2^43P1B=^ zJoa`^ed;ZWA#6YPufGPR`H|8?v!s8<7I8q#c$+5GIHFN{tOru>I72US9;7a26rZJ_ z4t37NH(x&MbCT&OM0F49RY&HtD6^7-Q#AJJ(0Ck)rHu^QtX>tV?Rvkjf6qMoJ+I?f4_xa5sEq+8=3bw z4|}T7PTGGoJ#qgE;cpVStT%o!T%^ry(*5sn;*Xn<`2Iv5Q|;LmVg{~Iq}djgd4Ljzt)LqZ-(=wp6td@pA2C+7mXYPEDj5^%N6OWkl63>qDyS@OD-2uO( z0kKBph$V+5<#&d^IV4un{VGNl<-sS)cJg109H(0TJ>^$&V-I<8|5C~&Y(*$k`HaVr zaX{qRSDL;}yEj_|4>?x|qzEj>6mWiQwgHeQ4{K|L%;!gDGG=QzyByGAU)$}S2OxWU z`pxl#sjuTClH^~`NndyI!c4yXHd>TQID7uQT#ER6pR7P2d}Acl`a=e@DHN%RG4VcE z#MBH2pzh`WwIze`0Vf3g!OIz^1%cf1$Nxw!#j*IlMxI8GGbgo0e>HY#QR^W;C)*j)0xbm(T#9~u;4ur0>VxmL=4Yp;x+iAbgmlD@aJxEpv_hZeVsC^a zqR(Uzp_$)U{NsrsMzuAB7DWru>C#!K!el~*%s0Wqy|>R_7KA?0(qO>Hxh2BGsAfEn zt5Fm>%D9pIfs!|#jLh7g_m{C%O>{2Pt+e*Ua9yEaagB!>E7{vi_lyh?X#EAu?;g|k9oOzBPIo#WGi-J(y3#exmx~b z2M{mKHamE}-JH#n|MI-Cidh20rcvMi>@T!OzU|*?Uf+f;CY4i?ZJD0eDkivm#N28G z=Qz1PfY;SHnU146njuj97nZ`_IS`jcgbMsk4G}*_!{PiXaq_sml8!6BCuGnMQF4v^+*t~z z^4*nNI(MvR0n&-nzfWW!2zV^M{rGaav z`zlLAf2b-L=`Pl+cJ{1xDqg>%qm#wRE#O+Zr)ENVCg2(AiJvzKPIuVG+*$G&ggxSN zXkF_uh`vhrtZEwa(-X zbd`6fGgFywBJ7TM;w2+zV|oT}1fvO1D~=X^8}QmT(d+hxnaD(bYU@5cBQ;JNB zXp1O=%;g<4x2>k6?GoHl5%U~uP7okudo7c>MP;igX!}-Vbbu%@bRv_|oREK$bOPro zf5S6=QwH1JI|5tQ&nt@KGIacBq&cO12}n}gkKDFh&{o`%k%Z4eAHr#WSlTX@)y30V z+#~tW*34K$=8sPk-=V_^sMm1^1$?$8*>=2Lc>ThG!)f&ub1$}Ke|piE^+f9k3SDsC zhHZ@`falkRM>y=8pmc>N7LtmwwNwWp4Dlji4^>LWEh=*DbHY~l3O=8n{Df<_b7j;* zUAzEKAU%bLTP;zGJ*e&xX>$w#Kg4oYNH5bw#&>V|OVgt5tsJ5tidyHkl%phJ$9CT; zSTs))uxrMKooo_(bT=(E?0#rQWJ97m&+#Xxo5aWIgVX!&e{a@GPBv}V5`I;P2mB0e z=@9R4$ZC-usx38RYn{!pUilk37C#O2jcx~fi-iPuHTOm6&I0KEE)Vy)C8ey~I3qJq zW0pS>+?R$*C-Ie#?pSw?IeyZ}Ia<>dv}(H9{1*5d|2;tcRVd3& zjVkB^48MF2d<^~;dX&76!?_ko-F-l+JMVx}xQU*Cb+uBdnKi%rS73Fxb)c!1tiSJr zu=AVUQuc~$Js~M;9itvr7Ou7xO7=2q%NN#*$cSGsS|j42_@u}$J+|_D_f=)DvMhD+ z{sZbI%?*C17;2o-MbgrLtxZuMh?wOZPw*cFA)FpfERdea=^R<1`30n!|7L;?a;Kf7 zW0;reyeucPs@4($T5RpBEs*ypw)t@?1=>134^2x1 z!p$BMy(7cfAsFz|e5Y~qBef_uW4wFaQ!unWN}VFQip-kyO^y60zwz=2-G65Ws$;~Z z5D0o$1~%T@r+aE;%XI!1sWiJga#u|G?81&Dy8Dkt<&JE_H0O(GxwbAZ17Pfdg3`?E;tMsk2MS` z9$raV6~Q5Wy(BVCLOmiK;nu%SX)O@tPx~|({~Ml1v?m&Vc|`bTD~Z2NK>=OeDfEzvk`(Ju8|OVsH?9w?pkKNVzU8j&*>kY0S2lI6XV!vVHJ6d9U7D)R zz}|gwS#dS8{-4Q@S~;yjm>TIz&~ZR0?(O>-sW0){d;dy*eTclH*>!TMeT+QXtT0RS zlNR7S5r_miKrKJO5$vw60k6@=&wy3g0q9x1!LiFLmA}~#3MaK5zY6G|?ZdqflNqf7 z_l3m$&U0$n&AuJ$8wy2?OZGDp=hMTJ#;K&``Z;fMc-2q*`4?zXei2%YL>d|^TcGm? z5PI!5IEk3bg-4Qr7}{26V+sCuWaN+TtC`^UHs!*jEGr3~4FeX<)5@{&`>!o%%-g%3nS$n;orks`*wUmsS9V!L-1{*k1UAq3Z)tWm5kgi|F2C~suAE%ek z8_i-LX2b=vR%9{_Uqkl_Y;WNgc{ha^#r&AoyU`GEtJb^LY*NE)4X0*fa$Uy``^p2) zygD-tF0B$jkGQ}V)38rGVfrr_$eDk-Yy}f+l+m@l!XKRnFfSbvC^A#2gi&a``8*cw zjhEZl04@l;ZH3F}XW#K;G8H+7ifsJV*^gC)#;#3~*X%zwbOmA};NNlrQYb>ddTghJ`HH4B zAc>8f0jna+go0UIbDzZ>?=g8|NJD&xN2Zy9^%58%+kg;Gl_g0)aIU^$A{0v1bO<|h8EQ@#S=}DS2-?*;6p>oZ&q)&;n zZy0Ao7Ce5!>LsYJLX!8|>tI1#;K+~-EA4AW&=m68*h@BBlv%~=E4>)|#{hNzhUo;Ek#vM z1h@m751+WEr>r1kT?|KI66Aux2{R$mxT-#(rC=oH;VXb}-5bI$V$yGqZe_(!M=BNe z{F@nwInph=^T1QUO98bpiWb!_7Q0V6DaJaUF&U~KnnS(R8CT-}+$NHYH2Q}Xtg($Q zTva7d*km)!eOC9bDhut^T8@1fFuD|rH`5u=es*B#D~DNlIiF&%(W9sGjWa*M#+EL6TTG*NUGmJ57#5;(xTAD*+pPE$f(*93#4}|RJ`S(bF*<9 zU?Z1a@=x{dij{I!F9mH4k!m*-89)If|>58M$(HEY$T! z=wmx^!=j>dE16ys^DBGD@&N0L)tHSfQ-(GjLftuBai0$g3_Uv0dUF=yKKcp_O*({M z=6;C#SSv8Nl_lwEMIX;GQ~GS@iFqh6kcH<#iQeY(F9l59VHh0RUu02DBp(Bkq>=w_rQfp7<``r|t3oddfG6qn5Wjz@=sic7CvVsu##(6K%4 zT;#R#q<=1(2g1KRsGl{Dy1aoXo6o?2Ks8IxV5AbX`&k-R(unNRKmw5t`|LVkv;Y87 zwhWg#$uprf32rzA`UZ}@%+=f(oHm}J&FZrJ@Zii4-OiP?;8S1%s;t2~7Axs^)_OEF z?~`ewl&JHC!Fn-#-lxQb@blvNu~=8fv-+dDL$P`j!Y_;A8AW!`%+&Ek|LQMnyDR*U z6Wt04EjXa`R}`(a&6MLlU#rrdE^xr?T?uuXX*`Q|EPm)tizTM#^VfAl0v6^&4C_qU z4W=vF3P&K?8#>w9N3ddbxBAS#tej*nO;Ibof71`KEr|UetL3H;o=E_I&QKJK)TqN009UU^FX7Ww!mx&+g7f}hj`Trjrq#b5qur7;3WOQ8;CDQQAVtE5C7VoS}ZL+EleT9lNr$Xu$PJCA$v(c0$& zWbxg5DMgpNJs*87!abjoiXE4u??vhmyZlqP_^TitrB#t-$O3xJZ9T;8HZv|YUaY*F z1um9fA$K8$A@{<}^#;`n?8-u=<^m`Wj)#j7N8Z!@lkVw6s-~cY2fev!|IUW(6>E)( zAA$*_Ig-d%GJ=u6?_z7g_QJQy2aAyqzm8vx2II)G#Yw83-c@<_b>G={o%HH*dC?7# zN~!yoC+z~OI6X@`t0rLFqOwFhVpzL1O)omso#anmcbI)bLm$5Mx|MFTFm zG5hY@jh#6I#$vCwnx{cR7z`}Q!Ja3#t z3@w>M-AUga2&vMoB-e~n^Zcuga8NloQ{N`Boy>!-eo|a)1QO`C)*??$_mI<~pAr0R zdD8|?ikPE{jSkS{q_X$o6fpT+XKqDO)L@BVW>Pl!t*=mSk3Zb^^O~K!kNV6wM~_Q= z@Ew2W!10p?ryl9-MY-iKwt76BDaS9MC)P{Gc3^$DSyYA~&*As3BwD&jvSkS~YRu^S z?$fVx)Zi8$O)aH;pL_7$$=;M5M#6&{gk#U<*qcsBzza{m5IUHtcsIxW`x4YBIyhNr z?=`;&_9x$N!~&}SEgy`H9Z*UxujS z^bxu0MrAT2?wtTO7kqvEnRxTCE5y&T2k=z`+;ixXa;5C$b7i)lU&btD0Kl&3A`SAY zG^CHfE6kAT%1Lx(Ic6g>-xERPD;4A>Rk_mZS}B^kcvJyv!EM1}^ZjJ@q<#iI*K5K^ zb%2bU`q{B*nT zEYQ8jJ-;`sk+{H6sX?HIMo)g#s(vyEb?6l2)gUbuf-ykLX9=>yPR?VC=I5hYYCCeC zY#55rvbN&onx&>QZI8KdUZyG^QK3^=yAU3n?ZoUqZK97WW*jp28;9?*-^m&SVY)xr znHNmu%NJ8zcceQK2^X|=Y$*N^;=#hqF2|c2 z4B+oh!D1Y3cb?jTO(xNSxqyorWV>`~{Mcsr@g{i8t@W%WWVQUBMp>}KyT*D+W7r>y(J#Bh%`$Z ziw8^7n6Y*D>K#$%MxW#d2)`abkGt%25(6Z+_yyXTU95GGk)tN@Nsx4KjX{WI`NBDM z7Xp36^QqF2>AKT}Q4Et5AM24q|KJ34+HJHx81xn*)8VKoq~~SmbR&?g-We3s(r0#w zx_pdG&X4Z6&NI!~5Y$B*Z~PoNMXgDSPrBgesh}==MO=7uPa_Ty=JTIZ_a#o05T+>K z+RLh&nv^2-jYc<)j!M^>1=4)Z;E$&%l1 zbEos8w!7b~vbQzy&iZ!hk8m4g+swktXG16N>nBu?Q9U^EW*IbV+B+lM64q~lJdUr& zrvuIz8qEWJ~)R_=_?e(l4Yge5}rLD|55sQCt_ElqB-0?_U&8 z9Hb1@Ybx{_(cp=0ZHOdRL`anP)qZZ7y=-hq%r3j$4Q|c@Q3hG~a;-w|6KPH9b2bFJ z0yT+p1pmjjPy8R-UO;h6=Kh`v+}rkGTW^6(W7d6S>>nCQE6z|J!cX`#k>aHrkLTJg z1qruBghaQG^&x0Z8=OI&6CS4fhL9n_8avOiI7t#XB60vKz)KJ?7Bq3Lv~$g1G&8b% z3$M7cC<~rm@Vclv{}r@qwy6;au?fnuNZ+|L3(R+{4nV>_+nGkKJX03)4d8rCxN@p( zg#|JhjQ5N$=J-{9O5$I+f*ZUR(m5%tvRE@-cbW1MKa*KS@w?{xXdqq8T);x?tm@VICVKdl-i#Kx+e_Cf!+iM(>DlyShp`);J~2e=ksr%r3R}F zjbamSjtdyb{;@(&?bL%eFY&_p#Anw={-q5K0+|48hR2$n7Gdwu4(?O6+~$ z%m%#s9iG+Tmq?3?GOa7%DqTwenD~#C{pg&XM&le587bW(9~P^04syBu@j4#o$q;amss2pK-*_`w{9ear zV8-f)OWSUda8>(>9Npvg4lw4CABoFlFv+1nSfPKfb0-pK4HB^$B+}DOsD25-iym4D znpTZ$JGa`mGdVex?DK{(OY3O%wle2;z`pmcR$JM3?HTs&{O~H@lKR&M_ShivWHRU4 zld?sd4r%w+rdd=Zp;g!7eNH_u*)2^kkTpJxxet*0;s-qu_pZI`#@5mm1I51*h~M`F zO7t_{*EHOc`BoK*$R7b~_HN)pf~cMR-!~VzdSZlGk?3G>URV5je&?!}bcdv09^IpY zu-N-^YdYIoHWujl({^$`rq&bwlVWyQD^#@P{hmq_WV>fN_?yTiRAA%WL29UJe>Ncd z9|}$BhZcg5MFp5DXMzt+|7+HJXD7c;bCi;A$xa?s5(I858T<|YXCT1z`)@Gn ze?~ZGYY-6GPZDNw2{4I$hBF(%$DlL84T}HE+KWxH7v3A31x*4>;;Qg^S$F`r^rq{@ zBq(>^D;st#0JMYfUR3!djHXD}-1r;7e?X^$OBCTA|26MrCqbDRj#A(_4`zpiah7cG zP@6RjpR)b2&#zH@+`o;!_YcB5)ayG%AP;!mOFm~5b zadT~>@C&rKl;RXA4#kSQJH?7S#oe93ic?&QYw_al4DRmkFu23uoT2yqyyrdkt?!S_ z%u2Gevyx2K&d#-e*Fn@2K<<<yh~ z)Rdn!INq#WeUDF@E4%Uut5nIRF) zC@sw>-o#llHq9uWS6$!UoKG2o+e1nTnzyPmVF`8@k0l>MeLc)Gb$^j6#VL0keHyJH zveO(hZ#A6qKy);3)2Tr)ANPJx}bd zRlf}@T81dI6{tRnkc_D3a0#EFb=xO0dx-nb3&t!4&Z$n#k6wLytJ|#~H}>s<59$t& zF(T&@R*&bPPU7+oV*6L3Uifi8rxV&_W32jI%}4iV8i4(Ie$|~uzFTj{U2HO4ZTrkM z?RMyqahbb(Pw-Ldqt62fix1tW5Y~rb7P2dQXMKn-NYw^9CzGNq&HAjJCiqgjNu_2i{cWrod-gSb$9`|I(pdEXFk3<8w&xr^pu!}S* zY!e^$tg2mcrHvwtx`#h|ik@J{m`|kpkz-LDL8R z6cM!zv=o9SsRR+Vc*i|&#+#qK8NZpM3Y@rf(w=#QpQxPWaPU5T-xsh~Ad;uql}hNt zIDtfbGpr#UQ&1*;DjA@l{!82opTtS#FH@C*BNQH~!Px-(#0E5846sV3R={$jSmZ-w z^n=s0_WHX*&U$!44;ysScVLw?tt;}AEw*I|YKLV|!|7f_6ba)FKTj0H1?mQWdAHY5 zazoUNUFOi~X2U6NV-)TQ88&zTk~s`}IXENqK>-CU^(x~-w)}>a28@1KVio`?r@YC3 zC$p^P<$~_O#Q1kM#;FM7{4uJSpaE-jiAe&Daq;zE%p~D4)d%sWg*eGuV!p z(Vp0y@`Ma>2XbiTJmKL#nQC+rvfA_l}T!uwgRMh); zPsCNgSyoUH+z{MEz6UISj{?mbf?4_D0d$a2#TjsbtPgcULu6gsNz++?|S_l0Ci-PbYz6tLJC5XrTg<4=tmI-LE!x{ z0MU^<+q~f`jxQ0+_eTGX;HT_BK5yKchCsdx-uYtwz7WW*F1R(Pn}}uJ5c>v|r!R!h z)+($+H+-%;?2>?4>!`5-vfQvc!}N6@{n?miOpT9(yn=8ESMotT&jCvqnc!DJ9&Qh~;5y_OF~XFpttu(2^NeD0|>mk-uz!e8*TeDC75lLM`Ri z%?ReiR7L&xA!NNK1g zyUQmV=gyWA{&yG9&6#tzM53{XJL}I$qRg0WESWFJWmVG;1Lk`C|4R02ig6_QYwh<&Gr$|FC>zB4HEt$-NomsPu8~iSA+C>g!Dh6jQeG^g z6+XRn@2H2Y3I~G9k(Q=Wv^;xe5CWL^GO4Pc)}d}Tb!`}U%R=wg8FnG~`?(!nBJ&RO zD|X*!$lrcLkl}C0|G5EK**@83=~a%;*L==RA4j$v-9Hs}gI-lM3AQmI4ZQw=4Q zCol~SXnn?gUB;3gG>Pu2%W!VICoooH16-UZIetS%D2XJmkbdOPp*!Us%nud~-<DT z=R)|X2`_0X)2!)K_v`|z9e^Fh*Dpsi6}{I*#=Gk68ZjgChiIUl$w}?V9n{K$@ySzF zjysT!!NI#*brdaRD^J1~K7QKI`7}|82NXQIb{_AlS5r=*YkR6<#Sfjb^pOU$NL_h_7qNA zS|(synh`<0V1zu7XAzlCER`g0@aevT-Gk4i^vBo zdf(UG6WE8wJfSK*&DM|?D^<7h+_Y0`W0hXgvEUH)8v3COPUS@sVY)Yt8th=5P~T@! z_je}ukFf!8O@D`1!;E?rwQCp?z&qK0LN)CRVzII7{T5WMKERUxauxHmuZa3SFj1m5 zxpUh*XJ;&~6wN3c>Pux;^TX7s!C&s4)EYK-*5u9L8{@_BZS5O{5*2(H#g?&)T!K%Y zRtBYz1N`hMt%DqL$wCyB$)x&*#asNnNQk1q)?}Bc-NpKCAck*1*Qoa;W`(vM zhcA%%FLobkJQfZ|G!8InpE6A%sW#2OM7AR(4zG@tPPpDZc3_C2+78zuZK*r?^>Cr{ z7(8Xvmpjl9`J$jM(nu-7J#x17Fq!vAd@+zBqk8fcDDsz}7flJrC>`J=52Q2S;irTlEh1W89q9)xt#98W$%W8%eqzw{G6c_wG##yn*oESH@VeN$`S1-J7U3#& z|Jn)080B}m*+5?iMnuej&(bf;)JN|7l=XZ}hp=z;`HXoF=~(XVw-*BN!`hn_$;NEu z{)i^Jw{muFIfnjE8p2(7HI;XCGT~3|F2_EYtkz^UvYp`C4mk44|IYTpU z?yG#yux=c*QU{Um!@d?S`94^;x3aI>e5{xj4|phEIn^!&S}$R(ELAJ61(Z1^)I;QZ z_Q3#M+Lb@OKD(~d_>E>d51bY^Y91{)@5}FBcpLqqH=P}g&#F2n1j^;^-z!a6mCfd- zQ)}w5k<1z<&V`=+GCN=z*^SUBX7uvOH5+-20U=%1?%4YioE=`K8WYVoU-M)|rbqH< z^5ZGLj;`XqV+h>wZcS+BK>eB!`k z)LspbHJ{>e^KAfk)GQo%6;_-6vTE8Z*;`GC-rPSCy)JKmu5o0_YCe<-(A!_L50+OQ zp^OJ`E0?4Hv7REf^cu{BD;Y1eHQ%FcW&hZ!BICG0>z#HN8Wo`vfwpq0pd_2^!20bN zxid25SJ+_!v+UkFDFN7?<)93a5F}J4Gt$1L`)3RJrCl_0t*ja!zBfSBYxxEHN3)|> zUY2cx0^;X=6S5C2@O>Qfc4q#a?zUvTi#X7pKL?mep>VX{Y)zH#^fMh9yGPu`QiuHt zd-I9(tZ|daI`gwlfaX+fb@4rbRqI+D|KWpl)V`b454+xM7GA%vwynp&Ca?yzhZwNk z0VUe>_*+^B0Z@BGjUGwY#;`zr0n-hJ#$@cP+hL*|RD`W5TJ=YD3z(C7DDdKZM~P;X z3$XgcyLoU4%Y1Frg$e0v(#j_KqT96R=Rwauce(9>Wn?aH1HC$X_0I~LL&MHJ$w7eZ zy@AgeBV6qF-xrUZ1(Z*r66~l38!!M3v~JiZmvnUJCDyiwb!0JR5_gMvFBuCsfVze% z6(sE-x1k*TR5u4eMO0B|TecHxBW|$&@+i~I=Wp+4Za!ayRH?Og>dx@XLi6SB@{9Uz z**@`e0>g$?Zj`J{2!3{nIf&Q~HacdVQF`>;$>FVXZdUfD_McHQwoQW9_c@!w zTb|CpYk@c54!#DK}zT#ac1}<@1)=Rw%CXmC{V+H(J zD!ryr%vNn*yCXSul1#0So$%MYPk#08E!JWitkxWm@${iB7@**m>RXJ~2BB@4DB%|B zb#2yq)8hJ$w7wrLNG{}1zd?4;dC~Im%Bv`D96tdzB^nP&w?sk(H`+>BPSJZiGr+xn z_3qj2z%JFca~Y@lb$WG{?`#s!>i*^LgL&%g8&P_aV^)JJfH^+@c=uX0w1aK|?}(88 zyLVp;yFtu#^PODDdzfpqF7$kwWBD5DMkbY5w0ssAzh#pML^%;fa7~a!cC|JzTk3Z4 zjMPm+ccR`vXSJ#tYrs7e&c(4g6uSE$3FcvPsX4u-}u# z)%#>pv)EhTO>`ytUc~t5;5Gr-5_z3M$zjB9AiIq?K_M^@+LpZUMeyknOvt)IoB0>E^)n%r zRE<(Sklh>cb=JzO+Gix*8O0Uc8DT6@rFsJ8+1+Cy);&{IWzwnjBzo|S_d@P0V=5=G z2jjScTVpot96~zm#rO$k23pVR(902S?dQS< zQSB|oZ}RPI3^@KDeQsh`hp~TJ?mG=k^Qvr1SAaQ#7uT%Ei)Qm^P>I{Oa#^yzUK2F# z3Uov~A6>-?ab~O2TgE;!{NgFs-j#PSR>gIds7?M6)!Vp zP}1oS9-H6buefFOq3^S#bufQ`-p61ik+jzssT{u$!#XzNr&3=S*op$eCCm~JE9MK}tat;4RhXx}Ou8lzehW6ZBO(ilY8K_`$Zx|nGnZ4m4d zkKWkS9iKh9d_FdX`b}7}d&A<}TY!lKb<~<}VEr32gGp#4Bl0>tGNBx3`XB7x=T27+ zFBR>02h(x{{bLVs5MJMfMey8r(E?2Y4wpCZ{O$Eb9_nTR7`*X z%mnRhK8r%PlKMQXDY9byT%11D+F>QvIpgXfjs9hJD-odduKD!(y|Ly&E0L(=8OwXS zH+}}I3|zbaX!k88KUn_J?k~j#Bq$t-u|T{d#XbzZzN>A76C48y8ZZ6{nT70-epKFQ zzrHkq&Y{&4qS&6H)mX9jG;}sgMcc;T-SB!H7;T8{(gC)mJ|5_d+PlVWeM8IVRa-m6 z{)vW!FPLxvrGB^4Y)KJzkvjD|e5C_LsYtcC)Ivcmv_? zlTjetJ;opD%5vrG#Ku*5XijL0p2Y=uW?<&zsEoM@5mI?gLHt&tilxc!U+&%)!ri~^ zQtv~jg|zg-3k=LbeC~AEBJ2A?=UwL7VqTtNK@q6=EO|bS5bmBvH&YJ6-Sd7AL}@u% zuU%1taQCU)f4O^*r+IYVGnNp6e>|hCF3AX=6Sf?maWkxpT~xHh)(1x0v)WOZ)Z=1; zfcg&3n{!{gHc!*#8_`;Rzb zlK`7eGnIjQ01Ie;b$q^{3Ar2ETxM|E+mrWYu#PaP9>#U4Xm?>jm`?+P%=lOY2mcq+ z77xQs3p1p7sAKy3jB6p2aEFI?tuab#zO3gjcmEY^4}OxoerN!=oUXYM#+;}?>!5R~paQS>d z?M6jo!HB{I%(f}eqvbrgAQFi;A5R12v+VGH*)>5%_ixoc0i2grY_$A)+FDW4GUx9? zeUMj%uA1HGLVi64Qmj0*KJathT;rj-|Ml*TA>MuH-b8)9FQu*cl?S^O#h~1mMii3R zJKa%#&!b}?obp+v>0SDi%bz=3qlbnMu(1dxAioJt97|N_Y{Q%m2I5OZ{@utZLgJVA zp2G$seKJ4XgQI}9V^ko+y28Z#{Di-UesKV*wiS#v-TCb`6-H#hLIF?W+cY3!kr80_+f>`_C0g z{ZPHs%>HbV5DzV-w}LOn9|U?SlboG+MactjiXRG|=|*TOIP&gO?vq6`qI_)2;hI{B z>gO(D=3AiR+t(4_`qD;vGJV|qP9qAD8}7H#xh`!31?qh)hp#gtHq`FI?jqrx?h(&e zh+(U7xTBuaCC8W_Y#*5>K}lYZKiO=&r*2GgmdqX@gFOE?@gAoNDg}oK`u_s;IgM5# z`hUR`oLKM_YbR-lkB3KTz%=X{QovtRXu_=g9Ke9@M{|FT)l?$_?%KKU5EHlmZMm;o z%6WCSI>r%G$&DQn#+LP7h@TLTSA1~LJg>9XzhTaC*rLu#TI0(HsNgit12PK}X!(Hn zM7jKIE_*`J3dCONm-`jHwKSe=Up4a%yhY=#K|#itf5rPl@w4K0SfBIz{y)Wg+r@tT zS7~o26!Z6=Hu1XldEr02{;sM9R?JW}O`8@qb#d?G*5l3VCQojFYo;>7?Maj*wz4h) zR`u71ExaJEF)o%MmS;=)XkO-YQSL~11vSe2b;_>p-2Skd=&!U{oKcdJ^LPBaCYz#> zcI2@u?bA1{;|Gp@G=}EwET^m!Zu9kT#Ux>;`g@lTyI7zt$p_r2B?AVykSYh9`$9j! zNlmc96a{C@7Ay-_MVZS%mo4--niC_)kfR)Vo)gR@e925Z+;Q2{#l338WG$c+@q;7t zs+G?uDs~~M>@y%|>aFs*M0GwQ(4>_KFyEzHtu`eQf2Us+RCIE-yZ=Q-{(Mh~(Hu26 zGj?NtzhEy8om>AyIx3)=+MGR%|C7xz6J`F&B|LsuiWIvRzb*Ob2EF^Ie5R-EGi4pd z#=rq;JBPuyCsTTaLXGUSi&)#SH$Hhu8)s=-kW7`-1Lb|qmO&v^jwyg;-EeR`v*_ER zKy>-zU74W-FOf=75{~93L3RpIC4Cm*OAIKeW}GWrYu%0|VnVMC$-3bU^eG19 z_)4%5Mw%x2Jecl_iG)-8-zK1jdu2(~?l^zJ!sX!#4kAG-wl_sA_$KP7i7vs#bK?o* zl*^_01P32DlXjR?p=)guWqNGH>q5tJ@RPbb9R0I+&KuH{6hDoA)<6uJM~&yoa!^LE zGO??*X<<}|#OI~PaF#JM9FTvAs7FK}9*IxpT_VnJ{WlKclQHUrj=HjXy1|y68(gz7 zxeZAld(8vh@CfBP2%oU_t8 zFOoa~mpQdbeg_lV{_B&@_IyX|p|V5+F0IkTZxojZoJx|%&{hXNDi4{*qtl_@g`TN! zXH~x0E9oy>or>QJ8cv%|d)5elIQGwcP*T2v1f|cwhP->==EuHWCI~BT?ltJXR-iI6 zq-&rQD9E&~H#aRyZ(69>_eMr`U1aIOj1r&hjUJajFpq7#wsISM8WIpV8#rCVr{~$x z^KQQ1T92+K09z@3i~^bS;A$0vM{8@mM70R>9hNc#heOZO3XbD;HwIa1b66%dc7Zp7 zJO@b~%HbYU=rRFuiYrU@ypmFTx5(mUQp8{LT8A#^A5p~EoA2k(E=dRR0k zpsPskqsOhkMYh9YbpK3u|Ew0#_1H~YnNrqsaP7{9^O*?f1FqS`Lq10M<oM9olC9G!)!5l<-r-nZcl^l{CB=esi`%S$vKlZ&jz; z?9({r*Y-JY8Fld(Tg{#a@H_g8I{Y#C!Z2Z?cHto8cfLKk^I;Z0z(W@r?wFx(s@t4o zhRYib$%w~mptWi~XtBPv5(CH-GEK>jR-{&IM$KQIyRpmlT3hm}-f_d{Ki0TzuuOPY6>raLS#Z1D z$PzYr3}{wE@)VC~wcnT^KDzmbc50$`wLj#f1yFBPZ!UMt^}?Q*giu+aW)rd2Z)|#; zG~cJXVnMgu z&)Yoef7X7rJok<|VXXZ0+e}or@C~^*?{|-RvTq89PY#!Kff{b;Fgn%_M@9!vSl9Yo zaC@|Kr8Al}g|(f09i(g~lv_;zCEAhR%UnL#ig0?tu)V724RrKR=<&i|kaV&P6t8>g zBfZRW9)|^B6cM}MXj;wTdON9s_PSRI8J!C&HGN@(^gm0=>J!YRyFXNDyWW{TPl$dj zF)%opzm8)EN*<1soKT8*rXoe$ zT0WLXwCbVI9xX2iw2cTss>kRusY~CD8-K=+3Y#b-&wy`<=;Nz7=qSpqIk!Em^ugkR zz5KIYK*cSEE}a>2v`J1UtI~bEJo{nQg0t_te!?Sbs+<}Y9l|gupIH?`P1S=x1BDB{ zZHpmKPzm2wN2D`pxlGvB9<}10(%A4EZMQzSof}b%=|SYpOwWh(dd24RodXW8P=c7?Og>gs{pc7F903E5_kpe6=<7f zgm_Om9HnWP1-=s9SIvwR)`v2L)tC`YYUXYZov>%ljKE4>o-6p3(R)0WiIjfY6u3*= zL>w`b0!amGP;zJNizc#>qpXFephZ|Vt7rIu`sA3#B4?hm6Wlq)!#{_Y*zaB%bi1*NLl<+PB$H9Zr%)GU=^HhPb;X06M7oyU zKx4W3RhZ*B2bB_LxH%>I;fN@P%9cq>i^FEb@BBwoOh+P!0dG1h^)Qsic9V4g1D20U zI}$G#l`6Z$TSSkJ%`UfBk2x0Aem+*s!vZepnRI+*0(W^Y55Wlaz*>A@p5E=oOb2li z)6i*Ak!KDhrRQg>00J)>Rk#GckJpAOSOUNMcVi1&w67?ncCl&rkqP9ToP z+VTR%7j|B#oIwnAjWIgbkv|;yCq);jYKLt*+!2*09H&1C@f-)y+c0>34pDk443HdX z`}^?C{|=qjmeyar@0S4{Ut+IR_fE-&lGLt&N+Fj0G>4@nYq9;EFWZRlTFEMpBldkz z%7^F=-`0V3i##m*x0}>U?fplqxXFAd;wM9lr|-yYLrq;e`dP{i`2*p;C-S{%?u4m0 zy?Aqkh}Pa#9$D!+!}RMgIj`lxW|l?IJz|&Z?DEh3i}|BzbBX>D9hcm;{upZchwp z&rRwA*2Bo>E17F=mWPgqkw12qx=&T~x9*j-!v*bQy&UE{cYrX!$PtQOW21F>GUbu1 zC+lfg)Nb7RR;!2c=?^`Z_P(&v<`Qq>F2aZB+y36IqT2jJmcXc3)3hh`LsP6KisnR{ z0hc-Y9b2unYu)6CQ-7?)N#;cURGUT**cHWV>kIkHxudowisDInjX;}$I-j{T9iO=t z?aQ%0bB}rmRJJCWyFBd@QSX#Y8RJQV{~&g1d+?U-rvF((yhUgm@+3bc$7+eQTA(tF z_d)v9_+kr1&hzjFi|GdcT63mp2<^=1RJB~E)uz?u8u@y0rNMpG!YJ<Y}_sHz0GTbqXu99 z0_JH6zO89WUiVpUmgRQ9;#jP-3;DS3c3>etGfnw^psiB9fNq1V5r;pvpsTOdZKrj8 zi~f9w;nuC}Iw83;c*CU3a=z$%BJgo^CC+L9FSzf8_O=t$_v|C2RG1QMX>XsII%>kg z;ViIdF1*~+7J?CHx;!Edzr7ORV_o#ZDnIr7S4R5pS>nDzI~@E!aeIq^e{p-Km?k_@ z`9JIVxCjV&to%uvChtv=15itYzKa6es%g{_SJnWd=d-Vm&00GNL>DAqQyT*V*eXS} zBUGWkVG&2FN5xcGEK)akOI=#MSsP_CpZCy1%yIgGXe~}~jn2WY!si@K@4kr2I6f>T zs#=B^p@5I%C-E`806#gvZauxl?h^Gks&oRGNcF0|aB;TarfWo9@a6L3e)IFyJ9;#Z z=rlc>6)h4Y>TW4t1jQK$Za=kZtAEcb9gs5c4{m={h2b82$wz5fNb=Oqe}@Gft_`?jJl8vN&E@dwc&9!iXGYtp>BGr17klcwOZR1i#`3-1zf z%*IDGl^hZjr=<}m9%X98z*pSf-s;Fb^ed*4+}q813(T*IyQnZm7}XTF-KEYfrrSzX z73ndcB?k0h5jI8ZKX7%$rY6+8$C~O@>B!Ay%(hfBUq&?9GdLO06};(J3xrmQ?OO%> z%inBi^;yu3K|iWCaZbWYp$+d^U1gxn#(P$79yj1L7mdIWW3p}+XqLg9_TPjVBoIC%BIY&%mC z6&u{}w}0eFTv#YSqHuB~NRAAUuHq0OO!yn}CUBCn&5bEjO=W*1#nw^!6n36euNEF8 zyKBgsTV^qgNy+*NJ4vz(L#P@7o5e3UqxhA#Cz~1Z{10#6-2Iogzi;xFMFwwA=fXEH z7}@Kn5&XFW+0YLX%*-K--p+^N-WzJdgfNwf#dcN35j$2UW~Ta}g7XgA;=o;3>(!yA z2rzqL5`OLWwCL#RKmwBp;*&8u;notQ0cgI>z6*ZFwgM#p>0<8TEoxLmu#~KW*?Mf2 zALW^Cm}kW;2(PFpL&RD>j~{R0H%Dc8jM9Ejb|T14B=f%O{x&O5PGkHCW2^Cj9qkR4y8 zG|)?u2vM(^1$g=%bBI}x19gB9z1`fJJnQg1M3%fD0>IKF3RD5#i^z;c#Unj7fBx z6uF^3b-3ZeItkB$@`#;-b5-rkIZlMQxKIgy25mnBxTe$Q-x6goedR69E{Pz-y#S9NONz(C zCfpi!Dx*-pF}RL47!UdJGA9@U`bU}5^|X*bw*wcJw&|HMolHNOESvxQW^E1&;vof} zs{g<{+!#W~TjtN0`6it2<9YA7NJ(JG(WJ1}{-MUwQoM7Mhs%gVw4&r;*VnLW-E_6A zJdUYZYxn1uhW+iN<2|SMlcJo>cWxGJ0_vVevayEUA5Qd3a#|AZpz`H1l8??6%6s6F?JfBn@Fs{d-RwsnD(EOg z&wtMUr29NCDfg~&D#}#re4x+wG66!Wb;YIC-?k=sj9%U~<_-rn)bDCS3pB#DfQZiG z0P5?)h=tr&D*G`ZQ#m&x>2vSAk^7_T^SqrXgsjJ{)82(Ob(N>jp(IL+@F0a;QabPk zQG6}kne!1j$FH-WbG1sj%h>)P(Q;Gn|I@NfE5q``+v(a?)%@ZcZQ#1;EMrTpcSq}N z?s|6)ugPy|-lZhBUzTtq9<4Pv;QtW!Eo=&%{}T785fI{jbof)rD{*hzbMLdO4g#rh zwHjqiB{5~YD-pl{4Bla%40j_u%nbOr?kq#%{ln_eju`iusl$3wf?7^}kSWv5E)w;> z5%=tBUdNme;{NSy0~8&5DVl2J*K8ZPl91(piTe%+aZmMM#67})5%+Nr;@J$I>iS*2m_^{o%`lw-+2pg^)a=XpfJEc2ODYM0{{y zGscq%+7mtalL`5s4=BKveAin7l+9c1+hsWMHsq3=C2n`o7p||*oD`XhC#F?F52-;4 z1tT4VbBYw@t=&GCN`zmD_$pfk$BcgRA;`n`JT*jo_`+!)8-%}CBd4K8VrrUEa%YG+ ziccJvT8&m9`?X?NsrCrJwWH(a9GJU)kQM`P#>3#B(J953_ zgUe00OeXtBzUQuVZvHB&=d^pT^5>2!y6{7#iv1?uowgF%wMi@M?!MC2WvaK`4p#=s zg8xd-a#U_H+ebKeBCq%KmIHe0r_Xh8pLaX4i9+UxdJh$5#vRbQL894_boP3qKy#WG z%tA8fv(v*@rvB3Xm~_xZo+XQr`>XJ~i@O)E(R~R(Qf&G2jOX*0%O?K5V;(|&CDf^h zp|zc-UxDDc25_QJ5_m0!O1=enaqy&923FHe14F`cfxKWrX0YJbbdzBt-C*H_fS|O1 zjXLfCfw;{^34XM!xl~lf;u0py8jjkfM-8ch{w};}0Ot!QG6pt&D6-lhD7BG0;Gr7F zarEVvI~xXby1>i&*i+r^2>HEPM!L<6CxMy;y(9C1fzM`yuS6n~*NjtRzM+7^)H&z# zRNCNbY(0EhKOruTh`4K3_aE^eA{v=xXPVS&_bQ8@-DMPE zee@!EBRor7fG`*Vw>o-2U)S^}FBFj%(IvdQCzaEbE(Df*;rR5X7dS?)3!xi;YV z0)D?(!tDnU2_I+Fr#SDjOT4KXJ|ZDqFg!CD-qrU!ok(a_ZLE*2!7t1D8vX*Zt_G11 zKXOzSIPDd>zxpre{!`r`6f9S}%l)=->wFb^eSh}5=Y{MoVkftg#NpmzqQUF&vBm^1 zSv0O7R5DnVcOQxhp$NK`EPO=}NA>tQzOQ-MWV!A>B`^2H0Wu7o>vZ&W;3WfQyCHXTr2Ny!?EqO&ogK=LQ!%GzzRh ze$j$~UryxFA|EarA9OCCX-^V|mKjgCyc^e_n=5!hz>cR2$SR*s1WN9_Z?sQLdpv=w z$}rF25x`TuULLI$i3*X!3ar&RFajrQhAEJJOb>9PAaKsYJz!<^)xsopTW{58Yt8+p z*it+Lif{Jt7~rGyB6DF6a=i6?5~&0dttn-x!_-fT!m~~^l!S8Mf6pLJ?=^V(sHykj zB6&zaVDFs?JZP%7RCK(~22CB2cio5%y4jEi-<7os!&Lt7*8M{L?)^ep<8#*(&(Yir zkIk{i9>60ZT|q15dw&GoLKUSlR{&e~mju4i5xX)^V!S}S!7?u+L{B8CE%8zgXE~No zO--CqYRkjlYHTD6dKj_(djC@Q#&bZFavjF0Cya4ANX{~sSi*b9AEy^^=S>13nYaG8 z8qc4+ui+S1iMtsmiOo`<1($ZwYMyEZ0e@!_v;&}h#)xx`eWGoy;dn9;Ds;x)>OOT0 zUBc~?-22-evov18T?`WUADntDR*WG`oDF z*u)$~cDL8?nB&xQ#R(z_i@^QV2gaxu$0QjZ6Qw?+vc|;Uf0gbf?68K{Ia5w4f~2k2 z#=xY+HS^Y_eN4PN2rSyK0;=6Z38 zQ4Ar)_i&=eMi2%VQVX1fZ`564RVMj)yL)I4efv0te%v>-h6Z(&yX|1;6LMqV6T%s( zqzhA_;-SWAb2a6XglXLvOx=s&;P(^Sbr6NE!A=6%MvpxA7#BHV%>GI3l99<+{Ga?W>Ly@9g?YhpSsjyZDG8BWoGo z5nnM&TAS2_ieSVe`Ww&wN>`0e-O0V+|Bh?rtfQ7Qn=lJpnLPyu7^f`r)iR74^9OLbpPoe=sxa$gYNaV{}<>!6ZUx2YH{~e zU#`A&ZD20M>bqkj>f1>*vhZ@W8h+oy#ybUDO^$>!?{R`*Mze1r~4&@qL*gbo7t*ZNHz}Z_iP&?h+&(?KIFQRW~I35KtidlQ!o& z(*{%}U$P7&P?Dr`w=H%1gH$VwgAG88zhp{3?405Mm3pT>%emzoaaqEvJw1H7p0$z| z896^n@K&$l*mYzNMRUqc%VJA4LTy_7aH+PkjcqinPRqXcVOqi{T>2gaxbClX`zAn% zgZ?ITcoX)1Qf>zR3aiGJ=P zWg$4kD&)(YlY;5^t$UB9_b+o#?hj$^6>$E~{>VY;{DS`%b6;uE1?i6j?a{s^RHmog z2pwF{i}8;MR(ufhPgD>k{|qfh?`M2eZY!NIKfo~B2%_O6#_Nfc8-#-)GMbdot!5G# zrq#)ZF!v!4=DwTzmAMBL0*GRab9z6|QRKf34C5b1UD(EABUlU&(KC(FXVWEdFN(vI zYPe*B)m)eV%iLpaE(cJYHmsw-=3+h7+4@#<>xLSt91wgfu+3=jjbWaV#caXzprPyE zo$$(N?)k(K@k`!A55nBTR<6vOG@e`jW$vXj&b&=pP_>(lLNVpTP~n2_APyt<=as zB7c;m#C~o4r-#b&YMQiPVTNO)D ztvP?AppO+iUd}%lZN&$i*mL~{>^OTk{7t+w#i!zf{b$9P5rgY>kY}D4bSEmD(NSYb zh*pGGcHx22svF0vt`az$*&Eh-@|u`Y3}20lksceTvX9HXnmP(HWq9Zx4|YZZ>dYoB z0%2ZC!U7xDa<60Mf;Nzx$Exca@BmZ$OFr#1qWuqW-)+}=Uy^i5pQGlt&KGu&FLsxH z+#NIO)l$wmIk2QZrJP|03CC_;e)X7=-a8J_W$g4x(=R*CTvzko*x5V!hq~v_A+dRX ziL80GW0Z2sPe>p8u6G2Bt@YIBsfMd(!4ZFja-)ZnKn8Z|BkwJZmq|pX%tHBd4VIiu z=P^qQDpe^7VO!GZmlrs4ohTe&?Tj=wP|gcEmA(lck}Ej+VD%Y@?e@#bHYH*R9ku8H zp9Pr59VC^M&oZ5H%b1X82IyyihUyS29b#I2g- zB0e4vHfuksELFe$M{pR47t_bOFIY(21f!Z=I6&7s%bEJKncr;Fz=>(%z_`P*HP%e3 zu$ZRfFIJSCM{>$9!c)LAE8zm*gA#-288>S+B%bYR7&Nukb0|o#TyMg;zuDXW*w(Y& zi^EuCejJ2~4SZlUP9$6wnBuny$S*Z#=2QY!-*PM8n5m8zr%c2trcvw9M$aHrh^YMBfZ7|ALJ=bu(>RABI5m zc^JjVXJRvA?$7AkF_W%|uy;17FMOC!*DD26(Nj_mT#|e1!+))NQzyG6f_0UBtEYn{k++HT}xG#xJTK z%3|r3q61jy4!^|-Z}7%HGdtkp`w}y_Tig%|94Jx0t>=|`jFzTFUllkBy+u7Wx2bce zca9VD0j)zrl@>T?lwUF32|@)6U%EgM?x&>6D@`~00g2Iq*XF)&v42mbzOZMI!!#kE za|449PJf4S9JtbtPWil;?DmdoV(S)zB;i7JtMfNRWd(h*<_5NL9={?(Uz0)qW_<6L z+3`7q-vBWYS~wO=`#_Jb>-Bh1OSlm=@pDw)&~c@im?4;RljsBUcVx1uF+0}Ah9C$l z-KYxmeG82+fu#<1yrjAxxW-V!fzLZBaL=&AGlYU+_#)v-wRT@Tf~C8G`sL}!O7)GR zz-l4r59rF5Qpx>>N2{$D{oLSiAtRL^X$l07*e#p+5qd0c&BH=du9Ho77rf7aU*Ax< zznZ~lcYnHuOw@@q^PvABa-E*t&9=3PC?HgmSo7KFAef&htwVH!_IW4q4b-(#h{pl- zn{`v%J<}#kTnDx)4dC!;==AB`1$w>x72EIPDAE`DJMJF~hsFf%0ilA3LDO;cyU_|> zbxXAOPfMhydXjNr|AV&sj%uQN^o6gYfJ&9#MWi19=M)EH_kP})F`v`vT6QS91 zVHP2u{vkqWtZ!ZpGgl< zcY8XWkf!fF2OO$|#dIz|zHy$GZke$BIzlWE@h8#&Psj%E7n(AI0@i=loH!BSr{G#N zmHi-2jo0iUcs;ec1ei$86s}fMlPc-!9cn$^#xq);T!Vj}Pm(5x`J!yUd8r~MSaEqno#;) zf7K4fyhJgU)=+|j;Ma@x+@{e5F<+k)42w(0X zBLf``w0hn;sHxNn;!B;UMQ8=yD-pyeb6n7p>coB>B&s1aodN2k6X=Xdec6L|0sV!y zUc>L`PbIKDenwT0!UxILwO}b(%Y}Z$6S%o_zMpSPt<{LJ=zS<{Qo>UuJE0cX)0PpE zyf#z3$9OhhY%L=g!l+!#v9&D=KZSA)=fJ_S`uBZaVG;bstA53__X^Wo1+=S~f^30v zJ#9T77GaJ3lVLwX^N1;n{y-p&jKi>!H5O?KF}sZq;7MBwF}V%O4;YiGmq1n0i|21L zTx|L?g@D6Sq12zeN1P}qPgj*HUAcmh=c6dteK*jqtR~TP4F^xyCaChTlTZCko&Xfr znQ)I!IjBJiyrb89|E1mwV*-^;`NfAzJU9g&u2mVygVrrUl8BV+4@W3`ZNetOcGNUN z5Pg47IOUi;J-+2HjFA&k`Lj+4#!!kQ*q*X3tj1_fD=feO8`=rGV!Go$b}g)Ua}kMR zkN9wB!4_Cus{VcjGoaEC%OG^8FST23fxxAIL@%v1Nq5J#tc`>#-Tqqc#^K7^L%ic% zA@@OYJMOK$Z_2f5(PXl)?o$an!P_RrOk=#8Ew++Oh!3bFn~Qt^H&V@M!HIx-KR{N+ zpYTZoZOLUNm`*czUQ6FVGg!~#TUD9qqN6n&G`HPwcE~B@X-`0%ZlV}#dpcuA#w-KV zwa27p7!yQ$R1S7nlO_-OzbBaRuxfzrRP<4fEjBS-u~1FSpXF?_ zE{vLEFzY`v2kLVFQqPwcM;}yaUw-5czVv){Ohe^sEruPyE5i-40kNDKf?nh3t?{&P zt3_hA!6fgXv=tEE(O`E~>iq`CwvaxHVEXj4wTUjsN0=__wXWYH+ASbG=zWIQq=OAo zNPT{yh53$_A33Q7oP)ceX{_3^Jt)oBW^Dd zfBuX~aJ6n%#4jiOajDl0Qa)00un(MZ{u!f>J5ZsNUpx3%XEFu`M^bDZBW9?5OleVs z{Zj90G#ck9*ini7aq!&88eTkRXDZjbRV+)ab1NBDAnPWQj=S=^Cl6l<|> z)EX8p>Tz<`d#O8_o?H=bV3+0!@Xpp>Pe>y?0*;$Hy4LF%deGq9`}vRt=W4C{!uE)} zx$RSIKM}9xT1~Lq^FvJ+P-7P`_!)4XlIAoX(DoCb5<)iX0+w^{l%%JITh8U>E!NXw zxekz(B@c!e^PCU07{~wMpXg8?5|6tK;L-|wGA@spCcQoUIaPSzBkvRbPZKi_4G<0C zeRYZJY9SgO3whj+H=+K)FC)ts&#n{QJHlOM zmA$-{q%GhIx^fUnT>-u`m`t~*7&zxSGtxKepe?>U`4NE*mrjXmeOEW5-gMojG=)XO zohC}(+MMe6>;ai0iM2p~37u;{wOs9~*>JOF3@5u2RLBVQJ)LlDuFD~A3>lf?KGfeQ z0DHz4lEa@bsbT478}~)DA4Ad$KG^I`YY(!GGi!tLRuC(L7H&sp9-z=l0S-Hqc7jbf=mb; z`lWfHsSFFQ8&Q6SCTR>t?zluXsSNj8FOPdKe@9>b-oIod%x0JvP8fxMAOG5tS$w&6 zP(j@%%oHF=)A(%K@&IwFm6gcG@pcjug5j0>~U_vWxdXjpm{-IOk*0)?BnaR-e+$ED2j@0_Z}6W zKKT4-f{$2ho_y5y2+$hBsTFK=%lpu9`4?NS#p5sQkHa}GzqkZ@>Y%7TCfxY|aaE9a zkC1X7M+o7D0fQ2WI}(YD{@v3OZ-x%)KyF!X0vcbtHD2-DJk;!O$-YOvX=QZrxZFeY zTj2N2cDCf}%>a{^-;uVMB#hCf)7Q|i@$V)(nSbXV7=BX80jR9xq3vbNx3bk^@BGSd z!E6bMTF~$o&;o~T322@JbKcDY&ysDnel{DVo=;K# z%-Zz94{^X39aDVdU0!sMH@H81l42W3tvN5`P>%Xbz5g?GmI4p_;HO%j-LkDxLoTu} z9Rc`Rqv2D-OMv8z!MkoTQEEgN@?qN~s9ncAe^E33_;K~nyF=H7AD(SXoZlU9zmNjs zYEZ&tz_<#a8?aE$D~z0I&}HLFx_5&3N$8ipEX`~Zu3d1)8v&?gD@3gFMDho`yYv4K z-m5-=!sagNvmMoy1X!)?)xXHWAF@LpBWgt7^KIn-htJ^;IRVftlHrjkcp3?9w9I>H ziUQF!^SqJMtK9u6oGtk+UsZxrah4XSo6&*q(huEhx~9!(AUMcHtP6&`pqn1Xt+)O| z754H>Tv_2M!^4NGjBT2S7e8YGxExzgRpC!b=$Ggaig0cFr8k?+ZSFv;jCXva`INR+ z81}xi&^X&N_iU|s0P#tBfKmI?u6YkjrHg?rxAiG88U&UPK zU=1!Ag`8e?X3K0Ku*o-bl;MijnWlE&Wxs}E+N#Dp#y+j`Cgl8OQdS{*YWI&Q-wjoJ z<*$y)1jk<=7tgqkV)Xd;sa?mv{m2Q4zAZkSUN_)`@bnl=~}e>Q~><`7SOPDmy0 z{yadKmqN;T*rgasoo~Ruw|MUGj&Y@$g%p$;_b2UvPamN*(+g*&pT;!f7lgT*`NWnd zU*d3;0~55}D_`EDS71lS_-*WWP?W{;21GG%(maQg%C~1=VWUUZH!(w6Np)YAm{xBu zo}b*alD)B($ni6M{ph;J?;aH>=c}&}p$t;9CF?1lza8NTQFh{QhejOZ=y{&+$1AdD z0;A5iwATw;G$tm5XMSbc!*@wA?y1jr*073wwK=PG92(cJ@xnD=L)zCX>%8;`+h0vr zTc(k&Hb?lN@?%sOy{m>~AQIhY;jS=!TSD{^>|I<`=^K+{ur}$d+-bB%aC2g^u0dB< zxp)Sbt>}86rV$oFl9c@@W|qY@Tz%pvlsRgPjuO?_qPco{K5G-}O&?B)TNk02vxGh8 z7`o_uG$^Fkg5NlcUArjr-T99PjYkze#HFXqDfHXo^FZfb9~$?!G%r3CMx-g~18JId zaSo?K$o@CIdNa6aXfzzpCkqLrtNwuVacWK6+wU!17=-J4H+k^&f3t7xlDcbtng6_h;v1rJhl#NXyOJM*FTLgsN(VJ9z`zWio2MLQJ;0Y^;`uw;iNU&^#7 zA^L_p^!hr!bW)TyCvzP#a~^IMoS$$Uz8&uPbJ)>)`L61&1}c)8-2+5e-nH{dU*ZPb z`gggnh_C(SYTN+s@`Wi`NmP5Ri5{y@be=+?fZffON|U=$nj$3nI-xtLiBJQYZd)on zly$4%wQ%X_0!MticP)?w>@SBr`zT3&pr+_>-Qgf1ad!K0NIO+(@Y+rF?QVD!{6!Ru<tj16f{nU2oP=XZ5CNJ%Tz=1)yQ?P}r3) z8W7X>jYU6dJ4Z0zvv3CJ4O&##!)-0ptgXLW`IN=}AJBcs@ITN!B={fbUb^QPji7MU zMBggy-vY<bGiK6<<{0}w7>Rcj?nf@PQHHm+a&v9bZJx2ae$fgEK2(? z<34NLa>waK@gjr6d3b*J55>f%tOvo9lNRLCM^ zxNg^1V_~cG!k{7bN?yBa+fFFsb`O&gX#9EY2)cV&zQaz4lQgu!MK!l6##%6QcXz4L zWWF#4^fK=Bdjq0VHB^qwW=5OMEctgy~{s@fJ$|u+$!n>40<_E6gZ$ za5o#B)u^GqpnGcN>Fco|!Iw=19brH8ongIIzYbe(Qe&I~#kv+wN=xpX&a$R->N0eY z8Qa~6W*^%d{-xY|{;k|E7MY$2y@Thsh~4sfLVP}J%w%`@OaXLQ_fWRC`mDV)0S*2j zGH)~uCL;}E2CqBcsw=(Si%%2q@5s7x!7YW|sdKCXS;WnVSP4ge2# zRh4Fs>$d(JpYBLYYF>PO5LCcwir7x>yyS8+G5JI+O*3l3-CDPMOSpJveXf1W(ni>P zdr1m%$qtg#_pPQ+IGdgw-Lk@TiMy&BjpBDyUs;5aye%ukKQQtZChKf)<5zOQ5$R&# zmhMej)Y)cDn&C#VzVq9I>3Gnna|{v8f5@ABHDVicCukhjECsFL(2y#zt*KJKHMF=Ln4z2|vGkmk?^gX>;l$ zRFG`WpC3A2FX$hWE~blI+}c(f|53`{MyZA!`Vyku(Pevaw)gk|3dr?6A0LRiQc?T5 zjgD5hIFyf@+R=vZU2TxMqGKwrwh$x>o#K-3|7hk-wfv+BYT&y_S<_9kJ*sY@MD=wc z)TJvf!y=Lgo>L8v{%7Q#t=i~WXPqzLt^i9^>dq`E^%QMVVd_Tj6R@@XjSI{6>w*5&MeGNeQvc!-Jg%pz*y))+Olx`rUQk0B7K=-hn4Tm%44w^SnND z@rhXS>E?mkf`!O3&h*~z(h`;t|AmCzj?)8^9ebo_+keHlSO0G??g=_0GylDDU;l57 zd+~k{KhSoQ#>n-!s=B2WQKJ5a833&qgZJN@TDHx)p2l&Txy?!5S~&ggXBE^XXU`s$ zt(#fh>7tHdtTc{M^)IG;Kv1pUM03Z!I5gQ;Rk3w18^7D?$CkY*siQAY>i1DmpWBOW z9Vp29@R$VuDXs1ZLmO9n27x!h-aE(qnc=3%raFqe!}Klsh}OB)z0Cf#CtaKiW1_I4 z`tu4SLQ;E>OEDSty3RjQ>Nrzo*Vd7JVZ>ld`pHF z%%Ye;?{Wn{;3s0M6BuzWcN+40r-iQbe7%3dkn5f&j0j6zF1B3M_9nCzrJyn0DnbDX zkhrg}pT=l(tV_gQ?kU`Pg7=x)>pXr|aqkQ3Ablm5i+p?Mvq#YqV%HzKx}KQ*()$56 zK^kNsQlH91Q~LN-6(6&+p?+|EL0K~9-)TbRtomBzXK zTj;o`L(pMnqqNU80G2o5dGb_BO*HrJ9i$D=^?RMT>$kX=-mzMLO{FXV(H$SB2)-((*Vnlh5B5BdI=y)Pf?XT>EK=a78g!v0( z)+3M!K02i*y9Y|VuJI~sJ>lt7P*Bu8l7#hy#S11C^82Kpr6Z*+))J1Ie=+#}gIw1< z01bCD=oui~W)38SCsyQQnP}=Xpn;#yR^*O>^FE0C%^f&R=WaoPgc;i%I0R7*=Q*iQ z++pBhNbACKVDQe09I!A4=qe}S4P^v18G^_Bh8lpFF6Np&0E`0#>tx!H`lUAr7)Et` zE&!Uc_h`|br#4gUEp2XV^tNvxjQ1o&9vzPOP5^M$P;^V3Jv9g7Y-8^_5YMSNQFIo{ zuM7etz*=#KOvvW(`7AknJg}rTa#OU*i-7;>`DK>4KSi6QZxbBo6?iBnOeAxk1T(Fr zsJCaR8&$UK$!aBaIA^<{sIlS-@l-M&Ovc61Y0R zg4v2u6_<0Kc2YWdms1^o8}!?+8O+(HgFZV6G9)HANcAPu=3kE0*-3pYxIF!5j=9&_ zc$8ylgs=4Nq`Zo^vp?B00p(hI{s@Vpvy2&Wu?h;gXTf^&Q7tncf>;PA0rHVB1`MD z;OhpMIb?Gw!WIcUTJ-t6qg`z_}z3*RaJ!~SN_)lsKrd04m zK#c`Q@Mqm@fmy5{Gb)f1bdmwD2_oY<(_V7*FH9d?ct*N45!7Or&P%~j;rq+~?Fy}s z*t^6kRj&6B-xIm|^IlGf2WFgio*KMc6uvA?xiqI3Q_XlvF8Nju3kS2fsf62)%j zJIT#qgi^$yTjQJG5~eoXq`ullow5IIi1G;Q`a84tNg5<;UOoB=P;n)qm=a!ggm z*AmFk6gGXWO6BDP>-$Ly9XL^^{(yJD(J!J^yb-9ZKz`A{AV|luih-wTc55wPtGE5$AJ~b1!@zvr zvCX@pS(o}7f31x9)lK+Y&)$mj`GS~0cXwVz%JWaEOHXUpO*Xz-KBtr=+)UCG+1yEG zr*cia75Fe3Fu-_?h=RK8%q4HE3B=^bTzc_g+&yH8*^mC97o6EKK{vxM^fUCoO=any zlHT-*qHE{UX+gjK$q7+>a-%Qm#T@iHva*}uwWwDTS0pBUbL`e+pUhw4tu?*Ijz_D= zt#872dwMD}K zL6dv&{!s4xHIF-kAIo8xR1&A;g(HQ+=0AR?5WlR2RTAxefB zl@jBLQRkKS--Sxrn9zv4^(=X8nJ zK3lw(&%nTMVANQIJG<@IS&Lk~aHB_|ypRd%LrCF;tjg4Qmih;7K(LEURK*F6p(tw-lKPh2#2Pggi(^tv`6i3h$F_(s4nM zQPMk%@QmTWlX4x@`U@tl)RXAqSmeGIq{T8~jQLF!c6Uf~n=>R)7A(f0ik< zT^l&iH`>=!>u*dO4oqV~I=rUx{HqE~6IM##$mg6=VXiPa`f;nJ8LN%Ikp0=mRWUgK zf$YnvI`ThEEg1L(OT*iDsJ&oMhi-~U-b8lL|TmNN0CqWpmq&%kISmIV9S z}cvhVzI#S`4~kjUggX>c>_@uzuQX*ag;@Xl!ndqZ>;^kjwK^MBNF6qXU?$bBo;d)s}GF+!-*0edN%WQ!O53c{AaW-xAJTR+6XNlH#M}0csw(_#xV4IkEDoDgjmWsgj5%ZVqDLi9ar0r?gB$Fg2b4?qOb7?&I)x%6VT($*{+dZya8rjUJB8 z#m;w77gtk-*HLAT_{j@dmO~1oD(dW4QBKsD5cdWlrr3j&8>`2i(k7HIpM$!FmmJfP zSgq$nOV`$lNT9ya#?9x73F=KS)>8#U3&|;`lbsJ@`1WeAg<%XXKW>vHC5^v>oRqM# z7mz>Fq5?e_Op(YL(bP{LK+M``*$dPfQJgPqq22zP9X4+B#MJ(fP(!ap`uWzNL)eSY z#EEAMvES?G8Tp=*Eeso;oS{q%owqDx{+9W%C5szUDP%aYAA01CtlxXa<=8;g)IjB5 zD#TPGG<4W7ZNqaHIcWpVA9+5xfM;+iy{eV!@rljkQ%(7#jhRMzpT@XN&A82c2bVK; zhLGpN{^xqCDcjCpzmQzcKe8_$SX_>EQq@~l^s5{<3pp}7|2Gr&R&C=a@PQc|{{DL@ zb8E}DJH9oOHh*tpEGY~YD5|4gNcQnKELBJ&sy2rlOa>B|83}P$K zHA-U4w7ED2>}a70FRj#AIL`~9j70+(EaETJ`lDv7XurxP)yP?tPs}BJO3M0n*F&QV z)_cEeA&r@XUJYCFhXX%$Q(A0M+J3I&4mKv^Lm?}FK&f(IU(){YKTodz+7tB z-&mLk`*lMk)lhy*iUlk&4J=G;$J#uH|5Qj73}7qww`*f?UV(jkaZlX8e6)g6A+9C_ zlvnsz(r{2IkyzF{U|*#Y%mY1>4G`srT6PW1UYdAuh0HBPkIhGq>PS!&i`Xuh{b`aqGjeK}hO`b0o+&T7;> z>a8oPemA@ayU@|EUq%Zb@P>Ad9m*4(LEO9U@WeNq>(d6vT-{TQu z-`>{Xs&#lC$RzWWvGC`-QH7fL`}$S~*>W&X70DXs_>^VZ2u+=i=@nXOJnc@AlUBaD z<6F?gkSa31Hb@HiV6i>5S&r`NX3r$BV8 zer_KsXS~*>^s#mT8P^wvZpZFkTh4z=KV-Qzx{D|AYx=Z%Jr8i=5ppi-!dGA|1EF@v zNH39gTFu}|b7V!;Ob({ENcEl0NYH@>Epxw=%kp~YY})*pygSsYusMOJdqD8aFz>0L zp5H5%%Byjq$fhDl9+Am&;;?cZ+oKqh}4gB}=&B5|TO& zsuaQwH512YQyRSr=9V)wMR3pEW^-%rPr+CnI4oQ6Ejo2Rgkx8GtIsgmsBp)4vk1;e z?-mxpM8}S&-HPJg*&0}(OB&%lQFevjv7c4vKR4#t!fL~Wm+Z)%Pl3zwd;R)BU=~z#5O9p$!Bq%J-+)8RaM-*T-qjtoJ~s_@s5XPigrdO7!|!t z&P$(}B0OdYE$qJ^CYfqp`Ae<;X|iyh)xs%0{qsY>D`%lVhTVOA=5(G>9WPfkrDHGO zpI5qOpa7r$2I5{okdtDT+d6IR_gj%en9YHkQEFNUxZ@+33LO$9)n#leNEG`x z>Za{WKaO8?YYyaK<4)5w_WLSql7%qlN8MDBqer+r9cPVq zyDLSx+hn&7h6H7@8Wi21c;0w~n>KLywZvswSbtc>&rgx$U8^wde)PICQ*zkFtOUOq zioN7$iBsnwiRmTNdVRp*s+$iGU+&}LGWUs5w1d4zmarj9wvrxDw8qb^G1K_wLa*fP zxdmp)Y^e{!f3lYO3Bl*KL+$HkZ#6q`^tv#Bh8j#5C{ z!vLibz~_5l=oP>XNRe8$Uo6C!EHUl&y0B0$E$o?cJ&kw*!IA&+{vRogw_?_mU7_gem^c^xo@8Zyx16LJbc(t z6EhDKHu&CIr{ib?a~Mi2T>kLBn~TeGX1)m|aIG^kKGn(WKHs@X$>05O%IE<>qpSZw z=l4e|7ODibt{qFAaiXjV^G(0z>Jn=e-`}I$Xhk=nuawPoJ#&{q-n>IUzWdQ(5qLts z&J-Hn>>3d~*ZCuK;kjd+li56h$AT$Rl-mOTs z>FirH+Ub5f#(gS5-dHua(AgGLKV&W5?1mZ> z0>lnp<^jSRXcuzsTCu+#-NS?O8c<4yhQ7@t3Xw6f+-mMQc7*Jws-h(jACKXVdQ zaQ_b>gKr}W)~e46ctc7*Mh*B4e48)hvW|QgIlyo~Nq*!l#&SiF(WtVNR6UBEEa0ak zthP^DqHs7$IkAwGE}TW~x4Kp-NLu@H;+Mg*Rwieig>7Z2HG91JNdE`kzQaxA3Om4K%$#oZ zX)hg}bNTx*YMmJBUSgag-GYz9oNqF5fxZj_*b`n^lE4$Z(Q^zChO#3nN05_h@G-`< zM}b+wr7=?d-;WtHOp$TBcduxu)R)c%SO~AJNZ?7{Qu7Sstb4?jfZAwe`!H*|#0YEp z97e#u2GkBD1=Ui=B*ygxxhBPnl%s}N8i4b?m)4nt+lpuR`CwQUMApFhjdvLPej{0} za}mSc_wkn1P#&1oj1|WIaMxc;SIcmnSvyheV_v6Djt+QG>E1%QbWxXlYSXA`q*A0( zxK;8(_frR0bPDYfs@}k(=6-RHp4Aqs^&=$F5lynR4XHEX$7Lmru_ndMI@H!VF1q5) zjG3x59{yG$`83(;fNz@oO|O8@ftqV|4tj{HLw~rCk$c_oT-ukfadhSO_`q1n$^oH_ zn{z?6^srBYTn70Zb{|%=pGU_NXE{=E%)-+=)o$x8XB#7S#}lj|oCSB6zrwSvjt!H! zdZ>o0Wu)WDRUh>Jt#~Tru}))M0^-5sIQgXEwcb6LfK~=APR5S!D?viI;}^Y;7RKCN zMfD-*yRBtPVHn-YG;;ke%ok=8B!Vav4SLNK+m*{M z<2nRK_+o3byNH_8)9yOu*I||lv11rXHECk49L$0c{_4)H(YMYy64CU*UivA~ftg@a z_WjpV1$wwM;4y=rAfj_6zJGQ<1vQWKbvzLfdZ-`*(S9RXU}CnWrqY~5s@N&2KaQ5#@B#* zTh{m)YqN7RZPY2e%2FJu*To`mdy`vFKI~J}!RO9*5rbC@^*8bjHS)w8A*2#pH^e3= zpYtzVCa51=pOnnq7uA`0v3iDH{Rniw4&GY|biAF6@mu5PMM|1%#V6D8-ch#G?p+j# zJP*oFo}Yld5W41m7(~ch_l!5`wj=kGhBnp2s9oGh%Ey!1f_H{~s~B4&PPf}K?>mm$ zQ09PBu_aH6rgk)-;7P~u8SvRJVolDOQQ+6h+izJT-)y#Oj+6tHMS=PaHa6-4;v+X$ zb~XUnSFzr-HL}q&!+sn;d{&ac7JLu0=t-qB`n9LPx>j={Jzj;UyyxH0+vs8WAq8EEwlvQht#nP%A- zdt)l&b=M!=mb?*Ka7KY^?QiM{+A%tZyk=e2D6*xj1Lzl=+#-L?>;b!#A}UM|w-1Xt zTvV^pUMVP#O4=-%z`W2gZ+9ex&Ff1y7CTarUaofgAB?drLSD02J4j1qfvgt^h8IKH z4n89HopQ6vqY`UTxliK;!;k4G0!>mCxMwOqyuZlUhs2-IWg(Wp+)lF=48D%6=z{C! zYheBrU`ev=+_gO+#sc7y@U{3JdmhTxjV@pBX62S4#?^cW;GuaD7!&j^mDizsh=|C& zvj}NMk89$Bvv6?K;lpv;&#s>LOuY$#=XM~>14Iy*%H`GR zyb_W54Y`kZS5&ehkM3{yu@k?E?Bsksef%Y1^I&x4+JF0&!IETn^#72!_XYl+6Za(x zH1q$SxbOZKai1f%{UVVR-z%{&BKeIf^f`}~gCQ=DGj3eHsq62zIDZlMD;TRUUuDfC zPQ+_|R6{timSgL4-9N)3yYdnhhDZ-uHXU|sC9 z85v#y`fRbQQwkCOz=TEA)(%d_iIpk8F5P8QC&XYh`^l8MSd(8e=&tb_?EuaH%-b_E zcU^3*y>+^cmc=8&d3#3sx!U?M_LIaJkNY1yC};JIEZ2& zuYca0e8COe=&$r5)5;tZBDnpt^H`Y@ZqLSlhx|kI9+HU1NTzO~8U_uu4I7miA5xk~ z8B?JrHcY9cNifQ{0uy|vx>QJbj8j5yE{Y!>5(BTL{~E?Yz8-|8l}u)1FiqR^PXUsm z!oG6Z3Mp!ZVR?G1bvp0*Gy4A`$;V|ZZSspmA3U?+be7lK8ijhUJ|BI#S*nn-^F$&# zPb_MZ(0%4s;_6lR@(#|4IT3)Gi2p@zpK&s&qfEExs*$=_GM_5Bpu)V@WqU|_Skp#s z#>@RsPAx#!GlJaEu@S1|d@#_LnWVoyMK^_W<~oyD{in(sfvb8eHS&1tRt657k&IQfTz-I5RWQ**m;2VdsrjQdm9eoG?GOMY?YSI-tA7UD$l|M+UHJjXR!P+q5RQ*UOhn)8KaFuY^tT;n3>ZteVG5WB^c zwrUD3(9)7vsb|3)Z^c{{waq7m1-XCLZ!VnJP!K1D6GNK2vp<8=qh<#lGmAg03x`Iq*YWmx zoHuN6TObi>*9U8r&-b+~1u0l^+YQs#%sam0M^;*b>8KRLJO?+-h(0L_7<%B$H+osd zNwbPP9bOV{Hi16fD1Gfw-)&nRf=gOmA=AA-gR-E#hO5XSuE3CJqA%6eX1W_qrXLsZm zZtU(@Rb^o(M!Yk=+s_@?qY@bb^FmtIeuju@?a##q*$!+SGITD~(5)J4wX8GqjRKImc-4qsI7 z^_O(aUnzQjTbCF$>El*YpPtyLegJIyTvj6KXv}@sP=48Q%lG`xA;GHqLX{OLW7ifa zsGb0cUkD+-@E0HkJ_y{$p{T}*>KPCDMx4HActgS*rFTW7qH=wIR{OP#C?R}Un1da_!Vd*)|mQ20{6(Ci?+ z9w%qj_nn3<{&+^&wUpW&V4T?O-XXkiF$++^!6kF;rZOwJa_BXdX?-WLmFtzHt60%e^Ahy)= z-nR%=@**NB`SQFm)wAmJw46i+{vJ`ep&X9am)LcJA|eP57P&(uj#CIXZF1k+B`JZ> z)i+CK>(TxGl62N4lGmsD4`)GLBrxeNI$?K?&Kq~+?0D3w=#GT}4S}saC#_hSf zn{-Dtx97yZmi#34d+qMEC#ta1PmRf~xzkm@7PP4x_bz^0&L`KA78P;B9Ir3zM(zD4 zrqF@+gT8T{8GoER&rTcjYo0|n&3fZay5F>+%J`)e?BX@@5b#_1Sj2B7v>-9KKan9< zp7y0t1eWy&()*P~d7@ImzGX-EQIp3B-eItaj~t^XN=DB-r-h_Uu8^($*5L%P7DDi! z+YF)h&OSr<_UxnNv-by;9DU;$VB*8cQK1<_lzkIf@mh2=eCxGyo+g9LR%vPmBwuCKOm{^$(MjOqga zZj(-5r$KvUpxs}(sGoH8$~xXh)@MxLI*;rsT-Ud3?H#2TXJ@}|e@z3Z1P!W(6F;Ol zsOgXEmyFGh5;NQ1C9rgJmavD8lpqHAe(VevH>oFd(l@_c#@j71dqh4f=qw>Y=)&P;VK`(i{-^S8#+SVe zw`n25b?ddZBlS7|eE9^s+ulJ(Yr^vH&XwK+IF0hewXEwgmk0U&x1&Zzla`FV%*7;c zJ__oWe>U!)c(~J>LA&egXxiqpg*cyI<0!(ndzh$7{8H9M!I(O-;m|e4)_%ARPdt_QwG^md3cxE>p z2ik0)%+=S)Dr2>;d;|H(@PT!p_R8N8-GGAylRds_3H((2Q z*D(vSAfo|_E9xUdYc(0f_h&L~(x|(J_O2&#)XB;$@{ALcQllKO`+?8tUyaFnQ4#9g zQpl%pv;2{`L~Skv%^JaC@>#@R%6>|%tbJ!RW7j9z&&X~8%rz%R%r;y+!p1pzV)oZn zOPZ0FCG|9LFJkKnG}!7%pwNDTl%<*BjQo6uw-|Q!11IeF(+cu_ET$LRuhOR@(^MNP zCOM!)7ceksO8%Pvy~Oh40Zg8n{ijwD(=AF+%-$-**D|C_FyT(A>vK|iUf1Uo*yIBa zPlFzk-IWQ(QZ9iyiN79{B}GKSAGckIzw9(q=gi>{YR;w#&B{?r1ynVY{aE z>Skzml)jH|CSYW~v{=-Ta5|%+Ev?R)!n=Mqpi9h!L^(W+$7&UWnlapgf)C1nekUyuW|aAu5U z9x0V#X<~_LwX%F!`9Q*k*s)QQ0f!frJq`|@@P}wjKP-<+3)a>qVS@{oHSkFma&+mB z6d)#@+AQGA0S}t}o3_GPJTpf*`e*zCvMD+2Crzp4$ZTI*$5p#4)NSJj#0#WpcLnvP z78XG4binGao-{U`GRnijcLuFEW=jMc_KhKlJ2RB2hd4}&Cqst6|2VFv8oxT}g{SB* z97R*hT+(_j-aK;M;uXMZQtz>0XZ?MCKC-&lnOZ>JGi`u(7e-z-s4FzeT8jMMao)ca znuuS4nv)2p>vB5miWErUA!I##lW$dtizTevsf5|wG>(A7x>Pc{#syv`qxKGho;`1Y zKibtZ=F9}YwJ(Q^O$CJ(if*-T@5NkQPCHcOFvQOuU3~Qm@V>mG`86#BSmZ4nLG_Er zJz24LI#JJ^t{(SYL?V<7>iYZVhYwn8EN8QZIkNp7Te{lCfa9%{a~JatBbyCUzR=kI z=>8Gb8v)5tzdCTs`*GL}*6=q6$G8fJ2u)k&;>T;f+AT}h;-<^Dp0v(;fZ0@2YT@f0 z;hywcn~M;jfYG>XMALzAPr{*a*%X^=y@?MYqWo;;cDEflv?*}CE!acjz1a`wu!-nR zzp!(PN$58@I@WQtc72n45S(Bu?mI6Eg$SM8mcM{PfEfr|vP)p2c4ziM79zRJ8L)T> zyu4n8kDR+^J%?6Z30;aJZ?h`}Y_%_eI*AC|^V!rok4(|BN`WpSbrX%u%QKkewV3Dh z9p|byAUV|;m@Ha)!Q<(r0ZMJyAELc2=Jl+11cK^3fp?@CCz^;89w>OJ-OmJsob(55 zd$AJxei!@laC4YkzChbHZLlc3fsU~$N_ZX@B!d^sz$efylh4F0NZHmPnT;H0=Vi&oE4KO|vX=YsNp zkO2Z*Ir)0wr`GC35hO9~KlBmSbHWd)b93l8f8O~NAz|pzKQIq^+KJn%f5h;o$Gh@* zY(6EtU~*?lrQ=+L?!D`11HAE1STa6QzOUtRL&+UqP|pR!f69i#&zI@?uR8Y%zt#Aj zJyW(1det}bTpj=ahI0@3H_p8W68k?p_d^)xKJaemsR6yqbJ4Dq)>+vrFgzeZ`6Jm1RF2qx<7#`GN@-P~f%_R#-_xBHG~>wO%C-_~kN zjZ$h?RcTRs)riqjMOE#+_uiYT8ntWh7`6A_qgL$Ln;-~+AP6Gy_(UQdb_8L6CqSsf};L`;G2 zgASv_As)YkX-aZ!RK=_H#rfJy)+$3-mWQe%r#_07gj&zlI`21ski2T}0)~1A_MKxN z=Iym{#;atS%qFlo`)&@1M|8faj|ty0=db4*a(IRjEtQ`z$&`QE;Qov}XnQ_>_cu(f z+7eFvI%sg~o;%{}O$H{T^24L)03_o1K6Zzl?d#@9wtdFQri9pDcua>%oc`rE>3C5l z?JP${-*4}SSH2ddrgm{|&W_koiMGyve)F$$PxY^JZ#{Amh#ElHP4#%}w7X8yr&*MuxaM*NS*Xb;Ee0l%RHWbCijWw60~;%{=fU|?4I5) zTq$D=t7^9@)xDYH5mmX@Yc;wV*pQEgT4vIX&UJ$XU;^rn5?_=){dK% z8`owobyQY6V<7>sAe)6Kmy6-i15m}!4{lhORDrZL;CiZ$Hc335Phae|zd?Xn&?j3j4aOTB1DAxLa_+;_}vCFa_Np3yhUn*S}khs%CT)|gw=s0-YN5WzMowy_K7!jVNl(dmFKT(^{9FEB`*#%LQ}G|$gI&1~ z&-GGbjOshmaf9s$#58SA<09H)6NwN39~i@IqSHM;GBz+y$vwGF{p*#7LYP{xMHs*6 zH~MU%)sSnVF;PG6X@}%)-)G^nHSROn;cIX=421)oZ%GZ?v~pb#9}o+7nSQ3 z!o=Mq-V2>7bNU5hA75nZ!mlFem^mp3e|1#@jb;5`kbCQK-5Uc%aoE+3-Zu-G65r=onzJ$@>(^pzITFbw+N5{4>_uhi3 z!SM&1?S%BP#zWt1ug)PV?VU8yV~7uIBl43OesZkfPczOWG367PpCZND8_fQhW|HEL*eO>IgEqW7LUAE7hJT(NYtN zb6b(7Sv%j|!0V1LuL#a~?=4xEa2acQT5=fhnz?YC*1h{3plf)K1(`XJdDt&J|Kg`W z_VH2iUa5@FM;MPu*1#o-3E=;tUAM-q(eB;tOCRIMsmeN3>1^cGn?U8C1&466m zJknXRgXCH{(zjBTbe=;!4xbJcGX6EQxcBOL_0FEXioh7bdTR}kGoVX!nU%4=?C1MoiUy)hh&$e8$@nxaD_FN^{!2V zlsvSt`@74}6E0WJi(BQj0s=e8KJgkoT%HC{08eZqp4BG6M5Q<8GyGf@dx54w!BQy88pw(Yt&9`y-wQR{a3TwRR$-d@8=Q7wwNBs$; z4sAfSjZ?}f`m#4#y)gl^qvB;5lVm@Z1ek)=qeuMvX5%18b+JFiJaSwHmd}v)yYf0w zHu(l|S84KQ~>JE z8Qs3IuI4?G;+wU0^#a*`9KBHo3-*1+MZ&c&OOG|VQ%+U4$@jzAM@tn@L3$wWueW5n&s4#Ku=ML<0AeJn zNI4qpc>Om7<|SxG;*sJCh_9Tpt7Kt{b@(`jk$neQKjo}maHOU_i@wfr;xSL+Fi5M~O&7edfk~1IixYK>HxW=QPtq_9v76P3; ze$#iz_cP|s^KnoIPhI*Rp!~@SGmu~ct`wG{K9?%Al(A%gQodC>*emi6aQ|mHT6;d+ zy!o31WOSBk1=x}4ime*uN{!pQxgrQWY7%gqI?nfYX;()&>yyDnxZip=OGjf67GEQ{5#ea>8|FSH$#n#Kl!V(zC@2`;Jz(fhRy^ItdHyhKn9 z!wCh-v4*Y6Fk4VEkADUizD;=G)YaylZU4(P^XUBHWWHQ@HjM1$5n1y^E1yY7pQxDh z*$$aOnq0U+libAc9c`a1H<1k`s~3trUK0CpaVjP)wqExhEiPTVM-~tB`uWrMXR2+L zJ_D0C@?q5k^DC}#=0USKxZeQ3eXLyEy!ek%@g903zaqJ~a}W$lqbD`d=!1JT#@zlc z_C?n}#C?_o$OU*NMI~;NVc%LjA$7n*par#sduyJXjL`JI3^N$tN?d57iV{oRhiyDp@qRZM0G$=%)7rVF zMcwwn9|hh+vBOuoeCel`kUy(jZzBysX9E~66V7Rpb!_t}=0xHs7TAyBy5sGIjsl&* z_}E7%Irs|WAq;E9g_3hzxgBl>_*AS^CA9>?>c0O#H&{B~jsy}P4`5Ii zi(t&q-P&67ZIW}~>1Hzk*ai_m+zw(~($L%fD_m47f%BZ;D@UiUn*mH!INET|58(R_ zRcF#^=vaC`a9{w%!v@XbgfK7Ux-T%VEz+zR(tzs>Ghkfeo_`pxsFnC=m*dmZUSU&E zOqZV7nEmwMmiK1jv7IQPbMPxhPl+(_Jb(fXKM}`^5O9i3e;D*SJyBpXNkVT6q;A@R zeNs^s=qvw^Z}0rCZ?ACY+yB1v?b&)g-kOUEZKmA$_TT;+-+ul-zI{rO=R#GP=gQLd zAnJ@mG_NtyZ1oKE-5!<<^J{UYyO9C&uA;% z-u1eVD?rJu64@63P0_ywAndyb#_Jqn`~b(k@Yy8Ev%Cu49b;_w z2_)_K9GGK&jbonyn7EjKaQN?s#}C%XFDzcaQPrF?QY3Kj2=YFz=;ABFBTkxbj1Icw!Oy1w^q+ zQ6BBbE818%nL>Mgd>m)?s_*F1nd|eu=;MO$XzM4&AKsW!*nsRz1AhrZ3}1d;AC04e z6?jG?-91+wQa;M!#zE0{)K^9q!gF3hrW*N5Sr@>MbR;P-rZx7SyE24T? zTrqUbVBISt#kzSsK4uBCq!a;EjF*NT2cDd{ zZF3=urQI3^i(7xy37{9(Z*LE$MKm`dJy(#8^I~$z&`6h+FB-x; z)Ei!zoX1|-w%1cWVepVU-k$8x`ybw3j5$n%>R2l~-UdVT;4v`E(WOT-P@%Z~f9LH% zx73YES1IoUNn9HbF<&}m&2Tcx++W0X(ir>s=eQGA7P;y=>d-4RuQjG@oB4B%6p6JY z(Sk|(7n?TT{Az1EPLz}nAkNmJRxa=Uu(JAJynXzC&)dJcLB58fVzF26faz9J5UI~m)PbZ(#yP4USdMPA+tqvp8*|{tXWquZp%nQLR`pu%^+T! zbm~>cph&Z>-@01MuoA%8J_fSe&byD5=okcne#DQ475VrKgZ6JIwytc%B-3!ZBwyy( zyr3P=k$%oY366Ad9J~#%fq^3^y}h#TeEU-mXA{YhSF(4$Jq^{JZ~vV8zkK`NJKtXG zzwzyHk9S@Fzxwur|C?{m^8crA@B5dQ=o9<3KIERId;3#R>5NF;m!|(W-+uWY-`@4V z_3c6b7vEm{fAQ^&@s=1Ow%9QXJI9>?i}3&W_Co)+zI`l>$lN((L$&_J6h*|GW3E={ z_qf6!mJmTn({EV^pV-UZguOf(;8)!{V{1dNLTu-`s3=z5lo3Znv7Q1YxK!^<(U&W( z{_ymez1>;vyp)u+>i)?@US5VX{VG*gb~j#s_>=rGqb0_bC{~QZbpnVhY`18x-c=>- zE8@^d>>##e{eGI;TPg;BUE10ucR>2o<0Hj2gNcz0WBxQ^tw6Eoin~f(=@LcXX15Kx zJjkAO{4JE>5kqWpB5kM)05lUD_+{_I&g|aVnONONtA_0t1Q@*E*q?rvBm56f zwhdoD)yJ}I<;BLGag~MdLa^8N_I_gnLJ50@%m(>dp8)8a_|=)0jnuX95L61~_Wl)_ z|1zTt7!FPaZA(l2e-@8ed*0p`t#@Y{=CkC?xcPzvQl#G!Is{RR1HBk zx{*FA?z_=dq7LeT44k13w!FusWb_(UtHc#vgo4i%ZG$!Kn0D{&^sUcp3K)13*dwj% zg|$9#K38srv@wwAW7@=9os6+w!5UkW`_CniV&bZcUOhVRfH!Z~8bYvUqhk0Znc;@s z=tuU*_fVT{m*PM}NQZWNp`spfheG2nq$*3KjHw<)#>^H z6nw?wrK`)PC}r-ZckTu$28TIPO?GGPHfnU#>~pQgVA*JTZ%&M`#5t?kO~24R^ah%< zFv4q(hY6N(Gn%VzccZrYMEG{s5%U551gNN@<5kVxH}q;$!P%Gd_E31bOrX9jrWjz) zqpl%vWSS9B#;8(UK8J|PwQp!*p#4IidK1ypCFC}nu?K$UvEa4P8s09kZex{L7qP2o zV|wi)X3-no(7u~z=-VG^qrY%A;1;TRaPofQ@B2L99+=4?zj~Eeg*NQ@h>+FnnxKB) z#J8_O%X(kGIDiArG?v+0^OW3B9TNFthmVY@o>jsj9ys}T!5jBdH;+Cd*e#WESUt6eI7vJ6TEC_!QR+Mfj&O_qkr8r zy56+npX>e}En!;5rG<(4i#a!vO^JEYPLCU3?BUbp2AZdmN#Skpv*lRoyv94GwX&?k z&>wDG{Q8?XM&nPH zI>VesCz6n#F#u-+=Q!D*6ci)MO)zH;qrzUf+he5 zE*G)DmB#J)W0vLt5q$b< z`yfpZndZXQ8^MGCR*5tBrAEfHM$bDf+B9!x5Qb2THO5Q0vdW0L|2FEcw}gXUYzBDj zJWffFlS;|N?mCE^5_XB`e$8qV6&_Vnf);n;IdflYTsw^AYi<2z?&hI+TR9*PzRIZ` z8~Bch`P;(KWE8j(V7xjhyGWLJV(!cNW8x&zcE{TiIr2k-KvWEO>pi#Z$Ae?j>fR>@ zxW1-w#$j{=Uye5yezl~8eLTnk)dUkA#D!HelbD3H^LubVp5c1@Jy7Xj9a5(;vfK4NWu!1(J%6E10rAly6fqidr*@H@2iMZP@_`&%brB zii!@jvg`4(yXmMoxn(wm7S}k3^9atIGwKug?Yv$2P7 z%Fj0r($BMTg@|2a(=2PmN%ydzwuSKVk(N(Y)+)7y8!7tJpKM4-s|h|e77m%teQ!}q z{YC7AZDHUuh)84mOXOoc%65vI@tuN4hQScX{w__9+Tv2eBF}{(;_2w|Ew05w6{t)^ z>LZ4JMI)oap9t5{xZu=B1~h!cQNL&y54KV_K*pi8sZ3!!%p|6v?ZOr&qTheMwwO>! zmBP2UXqFg=LcXxrQZSVbt$twiDl+vi$OxY{^=|JB0De-#072A4GLHl$$@on606(aW z?@EBVj{eN?9^rv@@msu#lBadORC)?MesVq8+3~>1bz=X+_oUw6M5+*+n^Xkw??C7B z{z=P|0KJ;Wo31tXZ+*35$xKvIV?ttOw3*yuBDYVpoB`}|{VtYGnN%a&4lP!d>LNb3 zK~IXvXq)F7I>YM&U!b3q80Jq?3_WAjOw?;>6%@7I?z*^_u!fgKRQj!*q%3y^Q|veK zE~9yJ`?wIFUOo`6DV~Z5j+AeTKp}F;h1d~(mC2R&1+G1&T6gQVBxp2pD|kDFt`3s3 zD@v^~2~EK#X0BATuZ4!W_LNp4rS|!<6!S9rXW;=2vH)&yhZB0*n6;E46Kvs2MHad1 zq(VR4JWgCuxZqxGmAAQ&g=gYHv?LbwfmRoBR&W%;~@7H~#Sy1G$N zE^j21HhMPvWo_bj)62>i+|zC%f+InJ_wI+dm?b04g%<@3-+In2ABU34;OT-PG)?tD+=@;TmeF1>qO9&mRc$3!E%$<2XV+)9S_PV%S1&~0+7a)72m2ausn8q=otG(F6r=5m2I#J4 zt7u2V8N0<=XdPb*P5w!)q{@zA!b7Vm zC*16Z?CBVd|FF>okv(oan>~zuVU`-IP+f_0KYu4-276;*XvzU_OnTyj&cYgL-p>xR zX|Fx`n&}u5Hqdfv`)d2sm5d)SW4rk4JJhgut{$8yEvX8o^!r-J>O=Czdq+=`X+idv zEt^{r@$3k@bi!5*U;FC8LVxBSl!(MEmZn=C(d+AQ*kl7Rux(4Y|E{fQ-(nj`K6vrj_j|%!8{5)jjy0?Uu z#XV_hPu4d-oHJBiYfn|I8&&`MWckx+qs!Kn5h(1Evf*5d%RfSjMK;y#WpMZM>YZjMO}>~R^A8Ln!}jMC z(4r06@IssXKu zTpXC>D)EZx{N_?aTc9CX@!-Q436Z}SICQdJusKxyT@Mdf_`#X?Crl=*$B`=f&+{nk zLFY@uoB}PF{m5m{X>afi>5r`9%fAG@HQgjXZRj=xQ*toGr#SMLOm(+}>7+&J%C-$^ zjEPpQX(fB#vZ_6S_k8b@r>$A;;}Pv}>r{rkFxKrM8a)4TPED6j>$QL{{au}UZtRCc z_uu#zWG)4huih8aI(7f>2TBcHQtgC&61WZY3kVNJ_FgAviz)xfW~~)gzMMKh6YTst zT^7ps%Z~a62&(-U&UJn%yTB2P!TqQC5Jlg$9VsC$0$h2#koX*1q>vV53hAfN-96ld zTmO<5@-#|xs*{BPa0DD+yHJ)Zx%K)m_56(%htm#ld?a|LD>FIYL_`@1pK>wakh2~& z(y7Eut4so-O>f;UXb)&k4+L-zIs`|bGEmHu`X$Cb-g&xqqGB!TYB`D&fAX_8o(GKL zk9QH+8Csipcy_X67uk<>UO@33pkH6~PX?HCJPt5#=qjmS{d5)C<7G$@JodSF24a?o zuIU>UF*Iob)d7Y1Zn#rqDHC;i{k_*EF%OMbWHxZ^8wigl znprzRY}92qoghpN$2CLr={HEeiow3GBJ9Vxc;`fBxPNTF$OfZ0>rGFl6GIj`+BAlN z2H7D(M$u)MNgk9%&c)5z-SgDu%fs<8k&PFvGfPBsBsc4s;h31o-vJ;tq-e}%OpLZS z_uF$(i)}x(eNRPL;kjsM6ojl$E~lJ;_#zj0O|NdJx*05qtJZht+~b$8M_z}jqDhlR zsmd>S==xDRUW`0dqt0^XPzTUes`CZZ`C`oZwcJ(u;J7fAKOS15X!jHFo7*4dH^Y80 z%y8Em|M%QqCFJ6M3<|luI6hYCggqwoz~BncU-5FBkcaERK-<48I3};^6k)VWHLncp zll#jKtv}tTnMwuE0nfyg-WZ2kDN%ol!f2_UexJNIDy7xc0`3jF$h+h@;pp?^&5*1( zG^T;?WtfXaP&&}T_kQ*`GKa-4d}-gipc?fTHy4VeIc)o^U}5iDnoP7txI%U-PD>Uk zdGp)uL;PZRUp<-WEt8w=V9RYzba;esthsY#Ozj5w4XfAKny>r_#ZFL9H~vG_FDJib z_zBKFqILvEL;BA`KTb;>P$@25s4;YJb`(dfcMae?$X%=MZf#jhyUfiDHpv z;Fm1m_>(%bp*lJYN70scr%!U%Z8`EN?eg2+`Of7{`7(N{EOQL3QiU$?G)M#bZ>+Ah zYwo#&C87sZfSlr9g$|L*zDZa1D0mV7{A|@TtOK@Wo^-$M>)dWY1e!rYri80VH}>%2 zy73nh{Pmg|3?Q5W59ZM(#e~_-k)u1z#P+|q8Hw%xHk4pEF8?ZCW+&!U_fC!a4Oefe zVsZ+T`c7hsv$_WF>j}uY)yi8q!Y8*2J^?8Oy9Lfev6ZYC{V;H+zO{aPC2G7CQ!G%) zt&HZT&@65@u{veF}L6690Cv+KW2+>x;tmMdft(4z7v&AsAXb zm8(5t>pV#o+dz;uxuaF`qg80)dG2wmcZ>+*kmoS)z&7@29R1+wdHXLeXQ2@hR-8V*YHF$Vx3Orm_YXV2z!9)a_lu6Scey~*EK$_AM)v>wC^S6x z<2L;-O`S;U2ySPWR{e9U0R1TnyD@I26QucHS>3wVujBVFxH28sb*g`TviWH#{7iPH z&JT$qq)5EQa^GU^OE;gPSToaa0-i5mAhGksm*`-O$OBi(H2cTH%Rk?F=PLbaSCXnx za_Lest5QNEahG02BDW+nGNm(yVe&l{@)@5N#U6Psf4G1>f~2)g;F;TR?yRspJed-7 zRRk^SRQ!66y@mmz{8ZT8;+7O3qbwjvV#?XlqxCB4#2)63f0XPxJ+ zkUM-PMCCU3S4T*2k_dzj9-{^yJ(}_j@08m?2``EV_$U`6$oMD_q5_uMx=FDrkYE!f znk`h^0Ylmvbl3OhCcA!2Y!!0k7h$^6Jur#--Vt|Q0eAzj@Keq~FkOlBwt?gkC$r)m zBnC9p0a-{X>iaf zOBZITO}`EwrG^DB{pehaTC5i|KRWNLSe@R#u=7|}TN31K%dCBb#8;^RQ2+Rf;igwK z=(yz`&E_+Ei`v@$>0l!@b>S28%DzeggU+lADt|zNaTLRNn=#M&i-m*uL5J2bn2)ccA5`A?W*m^9WGTFfom2ypm0evV4`%m;yU-eA5dIwn<7h(SWqh30u4N&Ghjus zcb;z1ywZ%H z1(EV0E^`;@kh4Gu?}`7j&WoY9_Vt=$$ZiZPLg6lo|KUsXcI&s$96P*-Fi@vmUYk`! z&(OM|JsbCD!Q(WVmgNDO`9d)vGo{bK* z`>drB12*G4=q5XMzNf+dM`n)D2W0r4e7vo<5^p=G~(joJf>^k~^W$>Dd z#(M8_>k*4vD+3;bJ6fPl`NYy3J-=LfwfgRDKvm@MMakVY0Uiw)HvwC0{>Z)(QuKv; zyhp$-ah70PmkHlv*Kf1P)qKk)$l|I$7nWnpzuikTm0|5}Y}?R6Hv?!jhrbJPoX|c; zSVD{j$IrZqCEhXu4P5=_Yy;k#?p%&mYVZ}xHup8{oP&-+FY?cHkSkVt%U?a|ylGSB z@}h+bRmRSDy;L`1`bU4Koq+ode@+oGk8y?Dlcg8k%DYBh zM|RDX`Y-MKPVx`E$*hpE#=`$9NB-6FYRE=w0B%`#`fDCmYbXk-T8)`aSWcSh(N0O7 z_ipu`%~m5N%53?vYK;T^$o3$tpHW0zb#;iQgGx^l`=8n__;qIP0;Z^@b3PxBSz$Es zLQWt=P~)6I_15C6lSiZdS9eIVKvk)3`qry#;=MC<_v+{2%Yo;er|vi!ZO&bcA36J_ zX7|d(LYdCg@k2<4J`kA^^{Kbt<#msLFVIA-4BRkTGZ4d$5IqHabx2ETze!$Cb2t zZZAdKJ+h>s6}3pJQ7>ixz#nIaW%OeM!@Y+ZFnQ6>sHw4zsq3bJH3{oz4S|^0MP|;Z zVAPTp!kMnE)%_ccu+pgVdCZ))eZ#>`r6S=wXP@c^?x;H8x!d2A|Uer zm>@BEs3R#(5a?K|%%LXh@ywMj{H~w9?mMI5s{iV$ksp7m`JNx79X*=yK6E$x!M&Q{ z$(ghG%&=?vnYcK9Wz}tmwYy#lG|_wHLJ>D6wgF;((vY!j3+yU8>lA3X-7;+i{oH#W zqcVS4RldX6W}|;^1Fcf2Rlswrp^2>$2CA!WRI9X1H?C_6aFI)#&*q6Mq$q{Pl)(-qe$CwJx zUfed?ETNkdc#r$#nmd))(BBIv0qTqEnFqassl%XeD`d8#x>kr@3y^|pqHii{!VIf+@;IPmJhw($D%HJMztCp>z8(CP|yX6Dh*JEsmVgE^DzT8fny+DJHZ?`;xEr> z3_UaA#QBpK9Rq*NyX$?_uiEDwj_UU85=l70jd8+~*IANjPDamRFSkRq)?Rmj#ze8& z{o5;nMJOghrJFl3Y~3U5#^EOSd7!+QMMT%J>7d55*D&s`L=w@RU<=D>tqIYP{;K*S zSk}_W&+HjE1YoElpqw;!qgl#_hK>|JJ0CkOCh2(OG2b=2gqEADrN36G5MpF6!=Y=^ z_Ji~97c8hDr7I@O-ac=KIg2vXRnX2loV)O>hMy`=KzB@Mds_5-fWwo}_s@=bkW$$N*va%Fd_19lI zIKQ_9J4p~}z*AsazH!R!+gt!DeN`nr@)@UPxUe2fPpz}w0s3wk{AlLaqXiW-p&`NQ zjo6b*Pt`+aKmI%XKH>6hi2pO0SxobkeeFe213-BUi@Sn1j3s(dj$B~B`@1W5T)zyW zeq6WGfbvutwMN#(7=QEQ_f*6bxv-Yv5Dt=`8&>7qZf17cM*E+~d@H@pQHt`{8*)tY zhAMO{mz~wez8%nqenA_v8*VglUEJVD%H1vEcM?7mqwmxwjAc` zIBJ}kmiU(p&(QeY%P8oqk4L>5UD$P;mG$R(w^X5XtMuzuw#vR#IYtEd#&=$L;!y++ zrn1H__-Gjw73z|<5U6cX*LORmh~es%t9_Iya4zfJY5Su5dtXZqZPJzg3_XkG!RV6k zG5y%Dj;fH3bBC%D)U+I9G#~4n$VCv9CTi7pK-#(iI2%w@gdzR5q)h)K#TFn^sMk@J1dY|Y(Z0!gfi;T)OrxICg>>b72fzxBVRYSwMkkgh zo<5gQ=?&#=&XE()o2U1^i2~cd1AyaqH}FM(fIukM*^?XRNI+y4d7mLEl#BZ~%<6&| zmfJy~w&MF0;h&!Bk6n}bG{1v3UtGhf^(FB@Y;0XHs2vga-RB!v!|~Yt)=`v$Nex3W z9Q(~gfqkAPq(ZaX5OJN$6{c2m#L8gga0`jQBUt=pwfleorr$=)lx!q#61)(b~Jh3qPYs&egiM22y*> z($V<+m+k`4ysT-ilM-USz5(a}RUpYyy6pn;yo z?a2JvSspUKMYnK?b^8kr^t(XbxB#nKz(UPj(aw`C!X&Q180R4q)vZxjmkg@J?~h4G zLM;EJpJ3BJnH62#a5O~%ttEb2b@Im|q{dj^Dls!gN|3C#V80}hQ_H1Q@r`w5^fhT2 z7M;6iXIH5{*r~6Y7TVO!6z*ghO3>ejyTxBpG8ZZMVNdx43^O5g)*UG(64Sn4tj@D% zeT#}v(wHwQR_&@=9RBHx{$Xd?;7moti5lVr1{cqw1^lv?cZIU*fNN?vHQ-q}bA;-4 z3RZoM!gm6GuMXImsDg?E1F1Uy!CO(ZWZIBD>r+&Ce$TaY%17cm_pDF62*^sDpgPW0 z{1n~5Ad+*QBd!70uJClxAtB4HXRsz@uIy*Ji(+CWe#NV!%rN027#KP0!&-D6KAfcx z(c+qAe%w4qNK^r9Pn>flwi2hEHfdP-sr|B(V~A_@CuF zkL$(5MnC49_Y^?O$RXh}#J1vQRvlX$2uS|5yNzytg zYxu_r-*4HH;oWRlZdPgbF$$jcQ-KNVF6%Bu#czg)0%i3giBblDKYd`_gZjf!e_qWad^UhduMet5_z51<^WF>N9m|}o_nXMB!fPJ z#+=4`&)OBOky3JX}^H&{usH?b`ef z;tY-&2-${~vT?icQ@wZHU5|tKN5}2r1dsX$Ix>w`2vwZ9`oewhS8jyA!;$U_zIr8` zaFX_h$MLGbvhYKN914OLv9O7L9&FyLu*!vzTr~ed!JT}s&7f@U+Ny=| z{Bf<^D4#hU@`<@9QtWkXk(!9UmeA)@uT5zNaM87aph~&|X$tIVVvh@OyK@>UQ34T) zA3)2RQA>>bGcmtL;Fm?OM$u?(4M^a9n=y_(W2Z*ib~4X|6n&7x!p;=B>{-^K8a3EVQ%5#ZUK8U z9k~)a85;d3r6C&yD(%W`C>}8G-#+M%C3FS`en;C?QjPetg8Yq>;Vk?v9i;nQ{Omt_va$L~i`2LMFsyZXe?;dE@ z`X}i7$)+dmD?t;zn7(ZOYE6&O$>|z7Vk2dp|D+7>Vc@Bji|N06W;Mk1J-v5f=NH+( z_Qr%O=8(UdiY~IFyE_~Ca>13@h^u;`Zb4MwphWYE;-dNk^~Gh)0u=w^hU%}uo``Hv zw0+HjsM0}y4JZBusSzUFHR=adjJ?W2BvhwII7~5Jj=S2K^WSO+SN3-^eDQJ=sw}UG z6fZX^mCHE0VX_oq9#~8x023;7k++odTPhq&(nXFvvvS45F1p|iSC6SzO0FeqS4yTr zUy3lh3TayA$CdGs?njOC?>q&2oVZ+yjh=~4J_W%h3)@q-wuvMnPTMmtFu3S|9^f$s zcX3B=NGQhpBH#faHKD+G$86)8$Z8iTrqSO$A_EgIg5;9D4WtSW3tPjh^@iB5p#b`8 zo^Q@u2)_$JSGbP2p0q!Qz2mQSrSft)ny@h2QcR;3w2%+jQ%C6{^H1oBDGoU13!~FA zdHP6zHAVtyvu1(3N&|HZF}QbQWBGYH&R-uaQsy2dqekx*{-lssG<_3ghE0H0Y7zZ`lwAU`IK3oN_vzL zXu>RP{LnfTc44JNX`ZeqRypM1y7NfzZ39(J164(bm-I#6s7rDx3`u9r^%{m`TP9&N z=1Sh$p`j1IS{K~uby<{mPMhIjoC?2^1oivnyiB1dL)MI#@7_z1T1_6|NXdGd!s7ku z&mDVD-)qh$?kML>9r!Ng}m za!K2+CEw&_9pN;|2D-jV8Oj_PbZsdYJHlCPCK)kj?Kh8!K|4h?lep=vfQau3M%@*B zdM}0S-+UuS;{BLnesgVodPnH;&NX|)eEj}9LXH&eccM)1RE^d5M}_R17IR%4X?9wK zMD=z6StB<%dIOyQiGZx5d(rtD=Pt2~NJ2U#si!eHqal!EV3!9n_dxZQR+T4p3CYRX- z9YS=n8ICM@X_SstN8eU29sH@+E`|c6nXx!r^!tQI!3Iw+;{;uwuT5I~b*)buM*kLP zpS4)n!Q4gtS)WGU7&45$KQVY3&`p;jq5pZEm!2i~b3>Zh zf(>8U*caK1`<O z@t~zqP_EdYvCC{hBrt#MMlGYnlKL*we=3()PpxqUa9VyuWFIP-an-G$6^gyv+-D8i zmu~iy14|sfcl#l3)G@E3#_<8%R#PInK1sV&!&>H;0SP0I9IPbwtNQYXewC_Jo$4I#ikY@ z`?FV2{w69$IYn>LiR4fT1nV@*q!0rc5Xmmx-W|gRDr(n*?6g%r(KKvdeDsu=a>5YI znpeA(>pzX!Pkw4p=X=ei6ZwG3Gaep|ppv0XOIzL|{(<3v04*htZ|NKpHH^oWg+pF> zLkuekF<}28;i15o*GN|-jfDh@DBXYBy&Xp8iq( zhlCKF1Qsyw=~J!$iuocE{g6m0^xQYIIU3LXF$_1Gwx;KE!ucv~Dt>uGBHvNdBM~$9 zwSvaYZP1;2A9n4#sR_#($BM?S3!UJ(eJnO-Y5NL+%r6%yXmoN-PgYT z^YId;_zc=v!4kH=l%VL)pIlRssM`(M#HVC_rc9#aq;v8bd8D!HInW9lYGCbD^Xc$z zO4Dl+?#yPLH*m2Zm{)h43%OmOQ}@w?Gp^PjwP;#LeMo7^u->ZK`%oR)V`Tah3Fh|G z_?-EE1XKMi8c3Z9Eg}6LC2njfal0nLS_KZ( zez&Om8KqmHlSu$f&e1<SKF?jqcr^r3oQ>GKVSEdkD9N&X0ErU+{5lEc*>Tsi?!{KOTgc^Wr4RPC@(n^ z<~{;TT1$TnSFG$ej_vB6cj)>wmTJ@}&IK*u9ZTN$=_Jh_Y6N!rh-R!BY}D;XY{rxy zIoFi>zAm;Q!7SUkhx%$NVsy_52JB*sfKKGvZHM{l}fWrIq5q&({!bQxG+nC)O0e+SICFf3ZeOPBe zk_8z*Q@=h8G0MQlNgW$y z;j*f+GlDd*iAlW&@P7=VR#OWWNu$ThlG^oSETcS9Pr1Ijt5| zZ-G@a7myxGewBV}vbOuBL&Ya~Bi-m}A)4rk*HJN?#lBymcHj^F0Cw`RxcI??9ju4@ zT<@`N+3c(iILYlx&yAt`98Z8J?DCz&H{kLFUSmhv%=MaMcYd8VmBpFjK&pas!l|^I zNP8~1CUk@EX#YJR@<__}B2RD+tYhb>^c5mX-o#FHs89m|>eXwMH)nUlu06{g!0YJd zR=BFV?axwOC^-zSy2MD|j&O7bbPreh#rE#vAobR}_NpmW>^0lYtN@eePGTXqsQcTT z2%R(*0sK2-xa)mh$G%+>`W1Z)eQH^16a99A;w6D;K~0?9h$OCfo}v;zJZstjK`^B^ znEKVU--uUsrfrfgf*D_H!6S_MP)4Pt+QjgooHSaR*ma9de16Dqe8!hg@5N!h*zNy8 z*;@d`5q9C4L4vykcMBo7dyoJL79_X@cXt`wWe5b<;64ys2X_nZ8W`MV1{s$B-@9A2 z_wKFQ?W$AVUEN*XT`gaKr_cMm5sd*Wk0I@yKA;(;n$9zO{$iQ%0IacCv?#nIz{GEF zks|Nb$rVuEI-b!AM>prrFkQJ5Y8G_Q{gk#}gF1PRUUj z7l_J42VI&xqsP16*A4I*0D@iab{TYf*gXI0fJxV0`+twT)+PcIg-W{&W;a$6xIE?8>KXlX}~Zwlx0Zx)0o&uD2Tq7wjs~cP##upo{Zm_j#%hHJ`gvGj}cW@75RBX|#h38{8Ls z9=DgVRo&}7fA5hW$-}7SkxHT8T{wfjrCd{!ho>z6o_Mer(DjvKQ#HK>iA2$)C*?%od9GVQ?2csiOPhu_@{$OS-ymJTw& zI|fzIP@e=B>k`<0J06swPhs>%$0krSyisVCL~|oo;2lm7kr@Qr^pwG!GEsZEBd}~N#Jf(sN3LrRanJ-H{b1DImbG_Ag$!{n{D%s ztNg`br&2vyxDnC|oXVTrL<;NU?#8i#=X&E{Dy69_l(HjAC0yK>weV;c!E+VdGSivP z8E6wO7+z;w2n23e~cue$wsU*9fRn z>mi{KUw(}tlFC}4)gIFdh7@tFBVauB)sWl*joouypip2H&5@VwTieGUJHYtdU0{3+ zeCeS4H8S8!q_Opg?+DqWiC9vh=7p#Me}3MM=;fWzOtFl4$m!Fn=h@}i-`MBb|ALtp zTK%8F|IX^|$D>YV391TcxH#DUrq)>C4?y=A>A~zFC}athD6yZDLVSvoA_K5|aQGU! z09`6Yb5ric5(JK&KXZZx4do=iIYb@LxJzITG*ljlV|D)XJuwTQog7D1?tlx`z zZ<<06TC-5hjf1;eN7Fd?-~UR^2_E)S!b=_O3pAlr^~g$YzwbVbLERSKiUy%OEN-}$ zVji%kfbkYcd#H@PtBQj%N1NosU+vUKaYD62R4^v{ONa zEeTtzYj4)~I{?~V0o*diw;b5Iq;58(mIiIFijUdF6Sz0sPk-+^z+Zf04jg+z$TmTVMl{U8@}5>oxLb?cg*_w>1P{Q9yITMj!IYUAVXKzdY@da9QXTUZtnp@ zw?OL4;=M1{$%)HOU;wBzY9jK^_fO+K@|~~0lIBUL>KkfX5KC6`C@`)CZ{H^4{^ol}u$XT2pr;9pGIc3R;_qoscqMw4S}SAX{QB#}8IMc}Nm9m8V? z7k_kIgkdo7$J3D`8t3F$Bg%ZETJiD&_m8PtGwD7=f#2sPjCi!=CnVipL zR$;(k>kY-@*W$-7**pzIyf{0*Tk?tkfyex2W2}av24VZTNx_@>n!Ko5y!sPQ;KgyF zIhXz;Sx4w51>*|ghcuu60`R+u@Q32OJ3FlUk7Lim$}2~0 zGFG}p*t}?ujoPBlXdLzi z*1Zq2|Un{?w0U=`Rvt;EwA+lxMtR9s8g)r?aaq2?q4sBIk%H0Wf1hDZQ zW%l0V^q?Pt!4MI|&q%MZ#Ezs&F=MLyV%esv@46vit>07m-bGpT65IjQzhDq=0Jb~b z!+q{u)I{Uln8J^++VG4EJYxn*&tA;e1cvq>|GmGzXND!I8~+k%RvAz9Wno^Q^`XT@ z-mFH2++IBUj&71|)l+4c0L&5y!7f*RUa+>{jHpvg~{VgtqdpGKTKh&#AyZg*Rxik0ZrrDDiLKCkPe5=zvu(r*r z;?L!Uvi=P@t$RJmOB(5W6rDpO4=ow%S39AzM}t|?M}M{9c;;EsGJBeR1KB7C39RKu z>o;u5;QgbgDDwy(eM>)K+>5&Ud+KkKLn`}TlSiz3W<@a4*Wc?BUywq9tyebH^G&K0 zZ=>G{!qU?&xSRd$VbH*-p&z9E{*+;FB>+dcz@DLEnDLBwIwFk>nHnb{+ zOnHJbibo^guLkWwpI1i+G*pTLZ`!3(&?T6iywm~EXBrDau7ylQtE+E9AENjwG26#4SgFC4y>aFj6;Sd4P6WKH}K~43HYQCWVbZ!@c`*IiYrO%h8RlGcPs++R7>==cv!kWVUA@%t!Jm486tuixin#t;b~e)&r&YgrrT7jRZSn+ODBN>weF;XNCH}1 zQ?_1+J{DmtxlvKL!3x5FuB>!#O#*kboXS5mdGbG0IxBS~D~2ju79Y{Qj{>M|#7fd-)OlXh*)ke{}~U#;hCg7>brlp!>XvQAF*lm*%>fXsE`gEM$IGz~kL8aT(N5l9rJo%3TjDtF!B=_I)4127@ zEle^+t{*9vQ3^x2bbBf&^q&sBA?A{Qc1N6Obij5CwT^z zrf*-w?C#cJy&pMSYsiQOG=09jErn&K&+Jvpy9`}CwWiX)7 zEd*x(DcMkH*E$CGRa?^|j^%vUs2s_mB}lH|ck66GUo7#o$K!t&sZoylOL^b!ivt;I zDj`9IBJ}~`*e-eeTe_c8AL{vBvciVKqRNs;RomX(rq}551*ZPQ<4aj9P-8|esJ|&+ zykw>E>s{NWY#0(gOr8oR&Bxf)j+u#vjrb)wRp_M zy`D@5#nZhb1JV;{n${$rGv0!nIPCcFm2hf_mPUZASe#uDwCtV$)I|5I%gVJk*Ersq zQkBOhj>f3h+6z+9UH8pnoEGY%uwO=L{j!?$rhHcKB~?!RRYd%AH~jB82RyLxBoh<* zVLnEm2XN}=UtB&5iS@P7v341=k(0qlH95xoo1#`>_qP~84e2i92f@XLyJNc?N8RK0 zF+1*jEY}M6IUiq5-AQbfzNHZ%-a-PuX zran-GByB4Vi2k#$CW6S@JID-HfL}iDj9k_e%}6&ilf~H@4s;&f)AzPNJ+}r66(U3&~c2Y#5hYj zaPPxWCS)r5s>%84DgAmyHZZ*z^3TULx$tn%;E=(sn8L02>Ae{}5B(2i=`rZ&?JHs3 ziQHD{h?KFK68vLL;0@+0KcQ`E^=QMV1En|J1l=W&k}y@huleK&J{0160}!Xr|A@gI z9gdZO|3*&aRjh`*;WTDvp~i?f-ZoRmHRY3emQHa1=E8Ot?BwQ^EKVrb-6Vkx_2UY#l(`f~+)!IpqO;nsTnq=Vnp}5{D-Sq&P z^fTM4>xY4_*_%(d2|&q!YW{D%;3t=R$Ox+y*%_@m8IIK#UeXmiA+@F7@$WQRga}aF z=sO5KwRYc2)$j9z%Svwh#VNi^+OeKDKJ0#vE2uk&W#zeklXM0H9nX=hSsq++VKJ;Xsoj76Yr7T@EHp;++&)ZR2J$g_Q8pQ7|Q)q zXn!ayNpoO*2R`&6b>0^-R*tT!ixCm^caKOA=5!;KIMl(19r|?+d+xf95;*0d{qtIu zopl>mZ?c#ueLyJYO*6_+YA!bk;X?VF5Z8&qPel#N`m%JEao;|vy-|(O6ZZT?t?m(t z?NXwsx_huYgxreO>ImN*4{)lH80zHa>r-i5oFlLF=XU#cTQH)UY%5;fR>%t%p6Bob zC|(bVS8nPZz=pUOWCPfoYtLcjk$?V=CR$q<Z8|_>!TPL*Q6!nh*?s$ zcVcTi(4Q4W)$uuNU!t(*umzacxI5HTX5&f6T}1!R13bGHg6*n)(APu>;9yTHBs4fT zPy$Cq6A`aP$d4R7&cz1b-D@{)g)E{tV-A~hJ#kHwoquXHf>je9u%#1x#Ati>59#~v z3_<7jai6b4e?t;5ZxJqsDdpvZl*!PsJa}K#$7T2thgikRpW^r%=rW=NFv+O#5E9j* z>aK*}OQ_$5IORPCfy0etg5CvTu1wpJL~)wkGw%h)KYQhoKe0WiE5e1gy-Jt!#DI!kVYILW)|LV9@;V|Kn8cvw!%(o;Vvf&~{In3md%1{PWtjdu$r^bQ)2>W>=n z7=`IUrHf*Gfs;k2zf3WqPsS%5R3}yQB9(Q3Z82=oN(l2LrRZEz1|I(RT_nK8?%2EN zDBAj%pWWvH3k4N5#4$3#g-JZ)RYqR=@zcKyGosCGx_fc{^?3-C(LpZqPLI9tdzN_R-_g#ojQp|;32W{Z&N=be_ zCDm|Il1j^HKjv{WHq^TD-3$ZXxwegeoVBp)c=*#c?(b=6d6qv$-Eo+v8eL;<7%A2j{7UtSuOZ51OZHO=oexRj zW55}I=U43;TW(cOAn16$xa&_C!VT}X@eQanKFjMfAUfVNimGN-!L%}}HTpNX(M4Tb z^XQ`B-4mQz+-N=ui9os}d1(t_wht#dh9S{MgmJxn_IO6a^pf6gV-273yC2VP!JWE9&kfSOnLVr1=%3X( z`6zZ!p5iv0+BtbxZ`(lCSr7iXX;3kNbCB`eCV+V|$!MPN>)Q$$+1s_@e-k?>-M^1$ z!YTG8=1PNZV^cDB_t%Z#&|{Vjg>R>0>oiYcdGOYg6dOd>^v?ZQR)_h->PP@HyTgY~ zpJl;f_vHvxle2xobU!Gvh0lG;oiOe$;V3956}pT$eO2SXs7 z){Jw|%!(4SX8*s6f?|-vv)pTU+^N=vCSmBtey|v1hTJMtW79Lf{!o~t4tyxg>AQuq zqH)crBGtFu513Xx00dfo&!f|9Yld}mm$lBBACzWdomP(Ay^40qbkDeJ=Q&r?6pfZq zp?ki?eW%?Swcmyrym>O{h&_{BPsB=w-gP!aPMcMFV0le%EM*|5|DtBQK>Ki9tb4fn zR^^DqmIk?T>elvj7I)AN(9^3g^XO|w@!bBkx&QO})zk%IjQDiq-R~dOd4`24cgElu z00jP=ZC#&N|EihN-MsnjHW49k=X}(DzCD+h5^MB>=7u&P8&tJw)GOn6+Lc)?ZqvRX zP-g#9V)Q5Qns8018YZfTf%-Y_qhHSPw~z#z z*zfQ3Zl`rw5efF`8D>7qBcjviv=kq+w}wsIpy$f5jZ}_RFfO*k-S7Fa$LTOhxo2rk z_jT3)K@)bPCYN!J$8@LS=GJ}^{cGgWj>gin*AH$y~un-o52*I&Ba5F~A)&$A`=MN4tJ z+#WPGh1V+=IJ+X@xVJgyMzdaBqE+Vx*~i-f5cX$Y@UVCx!5LYK3+@4bJrsU@zH+ALY6yNHll%HQf8zcc+Nvn9s)>dCx( za_ZgRqT&F)STCfRM=vC;8`K_WFIS8X1QM3pQ(=)^U|qdgO54pVVcSeYIP(hKy~%j_ zaoc--Ws*)HL7IW4_vpGX^`zwG%X-efj?kh%*bBbdVJxHtVbUO(%x1PeVm^EP8xq^< z_p{{4=hIp1-tJ(vpriHw+K-Oe2v27D{^ku$EZS>7^mRb`zj~zp2|c!9TtuH2lR;?i zKikOYRV%hiNYT-Y`6SYJEb&TFq$3j|Ok}}b^{hG=>zjU)mkY0cas~Q(snl0=idn7U zVf=Nn2Ju>mYQ%X7I>4WQY**g50KQz?zuBDRwpsEu#wc_T#&D3Myu}w3_%7~|$nLX( z!}-5q;yYjC{I5*>>sKcJBlJH^{F+xLzCnBQf0+2m|AUEN+PT?#WAO`(KY2IT?-A&C z@`up9dGY^d;`9D*nD~KCuS|TnsDBI!eaf&NM>Gp*=turfhgBPI?iic2Qb2MDwxVXJ zFZusr;(LLu1|v*{RMyrvyaa8uD%$vSf9#LDP5Mw<3Na(VZo8+V&wyqk3(A}E<26~c z95dF5_$0@<^oO20z$nQHmw&BBTM>jjfa7Cdv67#M53Pru{4s4a`cR`RZw{Q0IhM@o z5(4y9j~HU6`yqVS==D_TokhP^LG*Hx)(u89!@S|$I_hH%euhOsw|2HzPlu`&ql5rH z!zPWR^nC{sRq;Fpg|%3q4dWmK2q>R)I_;F4y~DbI6ixtUaT-^{aVQUv{Y6_^m&NAT zPP(aP82m2TK&{N~C|yBmP4TyUuvZY$;yCwTb9N=o!paP=Ik@Ocl0gypM%r!Zc|hUY zFC(rAk5hMH;3wgNWE0B0a~URv3NtQC!z@<%qU ziM^JqHsEE$X#^N0xtYVpOz?i=LBoZ;3arg6GRT-tF9G5%Hv^*ZX?CDd;e{6K3O8qe zh@p-=C#Ek%AK<>7MwZB$dy&`p=Wj}geq2igH?68vj{T`1$hzd%qgja_U=}{tDYkF6 zotlW$GUyO(rheaNaPLYOL1(ty%=AYOXyG?u+h*Q6Xm)hGAZ?~jXdfKC>1kg;QH<;C_nf9{JqkVibdK@$MkL!I#)Rxb-X_TRX*#}DqS8W+(+fecS}uh z+D3u7hEi!A^B>jCGGZM7tP5$vExbqYraHZ?ojQFNB$MI0K7fyX6a)X_Nhz9GB1@$P z6=n1lzc(O1pu=Y7iZ~3X@P0;WFqyXKT!z?Dygly=YBQP|67Lew> z8d#GTpb9ZW)N#%^;zBtCY0%3MwFv3tOC0eo%sozX6`Y51Ir~wYG(jG>tk%wtYT*S= zdNkNQ60>Tb%FNM3_cZTKu-c+nYQ(T{IK;vpFc-oyvOL6nRST!F5phL`#1TKh{CgUH z9;}k82}kmOKHn%FpWz#m&KzhMuOM@v3_((ZW@beq0rO?QBXoU9!&*L>5VUglQYL2= zIrN9cQzlO?Hl7>%sxw%}{~cY};q6momHU-1g(~v3%CP{4NsdE*GTu!%iE_>Qt-L1s zoAnQ}tQIjyBHcyF1;|X}qj8R3Yl_BF7jd`+5Cq#O5~nFhn{6=`zb{Z-9T(QlqhMx| zzWM1VrEoZp_C?Rr=LuG{=kIz#x}a;jq`|^07?elqe~G3=0II$98-J#|TROpoFn5ao z7LU?)%+0b}^!sf^$oM62CGbk(6^FulpJJp?@)Z#pM`7*(V)OGQPX3#EZlP|fDmnB| zR-{RWiCNy|(=#;`Od#DoNwBR-DYzym?6@MkFQMo`s*#RLeNXZ>*0c5agRo7zHL>x+ zepp^QAwY;_e2Dz7O_2tZ<_&kom{-o=NxXrQPtG}j^Dg$y@ZMvt07Ay*rc~(Tp|f~T+qL4?a2IHn|Ou3m0OI!*uSXnH^Dz;5QMuu9#t|EZJe4|{rtG(&}< z0kmN?~5J2t7l;Mk~y+0BmV{?T#N+fUc zjoNiM_Fa17Bz=ah`@Xs6Ignu0K=$7z(s{*z84QKFnWEW*(>@X&-gaOp` z?F(PjQxi^$DYNe0*KOV_j=-eC&?`SKoJIap#$SH9r|j3eYG?wnw6<&hCXlE~^ zcE9^zZAeqTt%IzQ61tJH6)-m;4Ehnu+^YP&a2S2&;HqNaniklM$!?Z50g1m3;jG@# ztojt@aebF0Xx1a%hZd_N)4R!Z@-wGS!2maSloq(ubi)FyV?s%ZI@tsDMQG44a@t%86(LXL{Y9mu~P3bll_$bIQKYwiC&eKgGV7eTRdJF#If zGF|a>6oQAN6x7o9PX6<{ApPS{~T_H^MEIWB0inv``a`*>~W7|GQ1|n z&oG|apOY@51?A~5c+&#o3v|U5=gf}}_d?V8;^-+*D*^F=8_iF65sBGF@?=8)!)Bqz zqPt(Blf@L_YXM;&gMtEvi-*Z$>NH+}3bb_&0d*zv8VNNO^YLZ9Yi|AF2Ycy-f0&S$ z-X)xjVN-50>lmd~=0*5RpeVDk2wYqJ))*O9D5YOW=Uh{9m*~imllm`?L*JNO2mRnD zg{)6(eqomLg@7h+VO39Eyly?UDN-LU5uN8?Hel4KBJL1Z@G z=>Ym)!t4v0%W`cM==uHc7akVP`@OK07((*GoT+L!J}DWnb3vhserZEtHjK$*^@pn6xLv?d-OGyXh~}# zeBd(MlXsy}J;iS(H+aKkUDhO-57IUD>}9VtHOBjfVYJl{cxXzB)RlQ6kNY#5LtH5`UV{^5Mh z*WC%1c+4^@je`VH?on^|Q1&BDC!cb!5S97X(mxc&W`4@4p|r`0v_AQtG)M?jh6>gmJ0d`HrHT)Wq$-W5($Vnu0o6JZU$p;R5raTa6wdKP0KSHLXdGED2+Vq?f?V=rF8vr2V-=Di;}%9<39 zr}f+0?`$1h)%g;r)myrj#!zDKc?~O3G4-un;Z)P1q2PWfvOsD zz~eu_z0R@c6XYm#UbT6V@jyzb#3>ffvQTz&or<&fLB871Wj? zu-*Xpfe1d2_|oU-fop>Oa>NEVCWq(EUI#V>K3NT1zZ6K21>)wf-4j?vE**)7#4m<+X+UQVk1@?5lG4&bI zXv&G@0uunMa}TfUT|XO2p!1Kp;k}*A!o1m{Qg)joI0a=6kfAkrqU;FgL?ewyw=PZO z-JSG(-U3b(a+S`m4d4~HWfe``8Y0$nb_Csi0SlL1WH>=E;Jp*_)r9`pJl~MRs zLfWE{D{&nVaz2Ot|BNi}|q#onJm7^)iD=`yJZr`eU=`%e?dGzg*C=g_~o%CYZbR0k58 zT{_ir_!kr(mlCg|%iuNNgmA~NbvNG$lzXj z1dK;~AazN@9%_K+OF|8nqzg`5#he_B1ieLDBt{6-?zw-^mL@ZfcxMkmQoJH&_wzAR zBV2+lc;E>El@Aht$iN1g+G_^euUdkiVr?J zyF8QL59xP^l!s!LIXV2ck(8B@kjC>t)`~a?g37F*(_J@f=iGvS4trhtpWi9AjO#ZZ z)!i;?f!)gyyN^xr@hflb93-_|{M!?DU+qayOd37+U&%&xrSY@mF8$ys$Rz8~In1Vq zy!MyY1A-|*TYZl+JDF^!IiW-QIiVhvVuwE)O=>oFn$G$SIsV9N1;mc{t<^i`(L=&R zyRfU5b356kAlqRG^>`&oJd${~gz&E^avb4G7yShlRf@=e$p3mVrKMB%iXM4=Q9(G`P`t1!~Jv8_l5^ z1ebvK7krLv)7oMjjvz^ZpJda7P%DE#2ptX>Q}ytTN3}gk?w^lctEj5>RH_|aAs2Iz z-qQM9brGfZoel$XDQn{>ho{diUi*pcU1(j+siGB4UwOukLV9f9k02gzJE8i z-XXBSVF2)kNYikLsCwsP4&ySs8g(^LiQVK^nZTk{y?fk+W9?(i3z^Gkzv1!z5 znnObVmh=5nyR^P`#X~*xO+faVV$ng)zam9!wm1 zpbnDO8HI<$GiZr-2Rs0EIgFgatEe;n*ssLq>!yL8%#ipn^cUmU zZQREQk|t{1M0TM}R(LZdSp4Rd&FS*qL6jTS6ji&hJSeWEJ@&h|ID8knHm@ad5MXrk zm9+nd)$#2ha9+;hQ#q?o_oMEGp7TT|le!p4gwkKj3tM&#UhpYZrWqEfaa1Mx=gA8| zxSgbLHyLx*fZ(9&bCuF%%;UW(L3QidHB~_SFC|IxHF^8;@;{dq1vogZ3N7409<-4? zgVnx$qBI;Xh9yDlDhL!=+Kd^LGZiD_S603nPX-RmM2u49 zU?M+bv-B??Bvk5{p6qSkD#w5`ICfFY+7LO^TtWVoLEt89%rds+3286H%)HnVxENwr zkxwgj8^e4kUf&17I5mK%W*xoHfLA*EvZ*p|6cv0zG7f=x)F4^L@B>%WrwXQ#YH z7Ct|f!d1o=AzYN*o_`TIfUkMFyDV;J=kOxpIH!;a-VU6>YC4*(bft1Ag{7e?5x8;w z>waJ!lt@tDpLz|;iEFX*IgtHE133?4 zP0Fe01m(gn5~S}YE}t|Tl#ta^=5v}gB@cp(Oy|9(8Eqa4k1eMirnmivjg=zVNB6RE zBWD*b20(_FC=c&Ca+@O_1T*gnP5jqyv-YpeB|=tlLM^33&qyCg(&2AQ%_Ly+d1$Pn zPKdmIFz;T~0B+d#uEUefW=pQKnZe66OyGlDAf)i093 zp;GXx0%pcZoQ5To=0SXS@YP9d^XbFZ=0p1|eomKlFXZaX_<73Iqn9)E(j<|wR7Qe| zzmzk^)BnMgOQ^GW`lpsx{-eM`OSVd6A&F(edcxznbGhWAo0q@H&IoOg@bb=p4>bqV z_~WJG3VGl3#TH+yH8w%_5vD(8UStFK#Pw;3|Jyo0f%oL)l%$s_ax(Xs38fd2Z@B2` zEdkw`;ujJs*4h?^o5w$a?u|vqciOT*8>mBkssl&B+`+_xwSYW`9_PgGA8p=!fvd0Zu!ADMWc+mc~U z=#o^kpdZk9j!TxBz@g_0Uxm)k3U6xg)qWmAT1X7Kv;Sc#X%m>qnajT*XWqFzi$1W9 z(|kBB^~tRR+E~&3a7g?o+IehD#a>R0xjw~zlid7sv-|SIb$!-NM40N$w>p2bT)$U$ z=k~cN!kYJdf2zyHH(L}SPvxd(|1sEtk8`PqbP=4FnlKc zmIE=pZL!Os=N364)&s2}d0p6~q3&!0&QprgSG|a!%7M~z>io;q>Jx|%N?iNr5pGV2 z#hh91ybB3~V_j2mgJv)Bjyihrjebwo0Zj^cKG?`_Pz9WGYHQyJWu3DDs`A9M0(9?F z>pgevmmg;q0_>QE;Ip~f_VD4s7Y02lH{8KI_Vi(h&db>&zM;{f8{d=flf!4pOo_>k zLEjZo8rY&)S0W#g(%uwuE@T;Y>&`bQ5os4bPVKiL3Z8!|gnYJQDqJ%Aw6(sO#q` z5by^F?}&iiFih7;gxavrKo0YrV{Sa)t{GzBR@K8iPNMo}X>d>X;of*$$9`G1hd+*l zhH>RCqgypI`vK`$H2Kwlq3(@=r^)w|Hw1OQ;aWL2t(<7=52;gD;>^pG+-3^?RgeZU zqy|wGtAQ4DamR7;X5;SM)*R=+5R+U*5Ft0Y(>_#JLJpi>hsKeA-^WP0z3SglgDQpi zw0<>2D0y+X)u6M9{zNG*S4)t7EADsZ9Qyfhvw!Db2%m%`pl~@GXbCy?$C9zNo%r4FR}4y3y3Sc(qv!}g>%7{mckiZ1mg_@ap#v3t(BnaSrXn6dO0gi*E9cov0I zfpA2ta6~r(5k>L;n#o3mQymRq-VGbXwi?G_`&rwYlK(lX`!OXhU?d?x{n2H4iRbOHB$URup9p5}9rg$367y$RSQdYEWL0f2G z)Sta@1KBV(qM}vV6zR;qJG$i0->%gCQ?vh6Kan2oFwRJ3IUR_|E8CB3AHrifTzJg; zh1)C_T-L9o-X{ZoUD|)WiYPn9huHKfIKx_UT=t!%ClnA$rVh+F@Zm-R_w%OH<;IiM zkywU>lc~pNVBq}WlF6mvwS2qOi?xEvJKP&r(HEy3Np_pp9oL)hfX88ma&9(DlzvIw zi&Z%gcmE_1G?T7of<%=5lhtyGA^qp;4!i-O89G3+%6=?Aqw#J|gpxj!@%QOg++8v` z=T9FH%?Rhn@d+j|$q9J{hPVWdDBud0D{)iv>-P%IbJkM}>Z^UeaRfB)4uz;-%9=$ z)o0INrzvDFZ>Z-kOr89;X#6Ql+QZ-$&aO0s}D1 zbF+2wX>uhF6$HUU4{Kh>!O;dPu!^Mq29?^p5=gQL#9}*nrN$Lr?K9vXnX z7v~fimjK3GBTo9oa&hF54EX%YWm&jg?MxAqf4WKP^z-iyYZIryn)I|C3gP2kz)Pg(oP>$(nYzP zYEU>K)m{x`25-K~X-JOLd>{F&6_^}0B|jm|UW>5FYZtXB_0vd(K7VtDJcM-+Ke&+u z|7adWC!{aafQ!8_bVp+EZ(Ga_oE84P2p}?R;@uz568YR&H>G}3 zk9}tm6Hwr?>+|o&iDKw8XS{_Uie1eeFKL2|ShO453~dNo+N#W7Vo$y&=DNUtV^soo zH_h$nC5OCe4X}mY^k^od2e@_88Wh|Z zA_YIWtkqs-mV9wpvRhdGN>V*SE3^l@=GZ4|;LoGNK2J>-xIV^pVln&V?mBB3zH$}a)g?6}0 zVs(7gBGDPIh44u2HziEN!8P&Nz9a$Q9T5%$gLX39Eq^~TzR4*UAkcC4n#czep~^@E zcyeuf-%&f29FE}unz=q5wD;i9@Qb+!+Zm`h@S@&5XtMC^U&gnP{|!7n`#Mw~y0iQq z*3@14>h4YXZeZ-MGUlhxffWDj96-@ttJBfO+2;UztreS~p^?LZAjq-m+SVmclIaO;U+NcBnjb|~w}RvMCn#|Z zSH}6#`?^=KUj6YJcPDf-#@|sVFwl9-mDUCTFORbH0{aKy;r!B5G?s(x6eLq|ilkpc zdJ^x%;FIWqLy|^IaTwOMkwdqwae?DdCG}sZ_y!ZBrR{cFK&A^9!d2Tq&N0S#0gH^-m zu5@ewU3`+r&S*(>88m3^u*-fJKJhifA4ud%AmBZ(G_R%t{S7|Th)_>Sr>IB&5g-@OzSUyO~2nb^pPacP;aAhb&5(y&Wt^MdPkOU zLl_uE6IJ(O;rQajN7uxcw_w}KTs7yuEjPO-@}oJ&An}{LON?ieQFlJcw~x{NRKL5M zoFzhOX0Z_!5HO*Hh4GG2LM5)jXcx%&U&V_kEd za?9Lv%O=F|xm1TuuTN;QS$fBli!KPWNdSmdJ8P;zvDYUZ7lb+xHJ6P_G0vF(+%>r* zU-q7K9RQ)P+fOtjLz7mT8Q(SqD0&AsIF0ztNyZCJKFvm7(&X8_aF4hZZM6&CtLj4v z=fL(k^2Pso^V9_x{hDNG>5`ARE)Nu0zEj2yG zZQgOX`L2^l>2Uv20~n3)9Ysze?W5S(vvSsTuf%!Eq}_8O5g^{})ak<$ImPqVlhWe> z8awTcBEdu8_zZrK6y-o}*c4gH?e4}_#yNL< zy)N^JlHnQaRFyiQn+d%p}Y?gf$6eCQHqp%-MywNpX+DEjGHI(0ux zK3-t<7NO52xfYcGZsJ?Y$?HeZ_of#E zq3$|lU1ZvT5-H}gD`yK z*`}$w=?7@X3`FPmEnC3Xd5K`dJoO|SG>F?%rwA91ggosn&X`9&K+=q6(~aoTP!d7K z15h&M^^D9j4_oljEWYmhGs)So>)EBJGpW5gljusPodr92`l34f3*ThypJ)skAJZ6r zako4E7p&uEyjRAE=Dw3ZSKfe3+&=-SrY0+hj*H4QlG2_m#P{f)qDRHNpJ7mia(H86 ztaS=9OL5kWQl2{ga960OKH98CI3_tR7ne!kwU;;gim8!fToov|q%lP=!q>P0|2ydEO)bd2qXY!wvtG=p}$_a{Vnl7n9rXJxVKZYS@H7Rw~W4Nf9FJg!3HdrY||v z)dY)3Ta*#ssEvVv-8z`!pfmy-CQdt+j4$T96El~Vciv;2gZl8E-DfOlgcIBant;`H znP=A_UOu!MYUQ*6PM=a0UdvM)@i0Oa^Ppnyt?ey6|K;CV;P7-CT9CJDY1q6v#aIRY z&Bu@G%_YFE=RScz;7gA}RkF#1ZskCEBXIle;@_g+XNOqQFZB_TW&YR=ZrDGJWi*Xm z`ML}%ttfRMsSlvvql@1}7cWliyi*oU_UvkN?E3HccVg^@@v`1=0hQt@U~C&Uq0K8> zF#^_=*cH|cO)F6`0)Mr#$_lWTZDl^JlvN8<6vQ{r4^~?DHLcXf2wZAqwG_l-{atXA zBc3925QnV)|J-t5!R;OKlrE{Ln%OfZ4;doG`Pxu}IUy|H0T>N43>`{k~8Nw1vV$DK06{LMiSp6|A_sySs)!Dek4X7k77eDDLhA zf&~Hu2oM5?=l8y6jC<~V?-=Kgl|A-YbFS~)JINkvti9%EuE`Q1REQ84GeB=5gbBpJ z4ry=!Ena+_bEF)faOy&o_%EbTfxdJ+lyCAMQ-v!=`}tqz_|MH=1%AXQ&QyApbY1Yc zed;<{+B3(WdL`!j8`1{yz335EMQL9{7i&QoV*B9x%r|EK^fQyR$8|w!u|wyr74;|s z9%^b|v3VCFu=CjOv~zxioul&~!0q>$B>5MVy!&c<0%jB5iTmHKQYer2Gc!(wVNa`( zpp4t$EpNd7B$6MvG1L*ylouJRfdZFT{yI0ds^q6CXc!>vb*#^hBxCy+WA)yh!mcU2 zZ1r7R^ta;D=<3z2Bi^`mEcGTD4+`aV$z}W8Bi^j_5Va;_4+`~l`o>kSdHb^hD3LqF z$ZmP(wZ3(twQ!8GnJQt|9Q3inUy|@){|VZ_80m{;QIpyPqXykBfNW6RCSbM8P^JAAMQUk_dX?zk^=$wq zHTC_`Z_Z%*f--IZHfg8GWyz*oqNr@1{p%wl9D2>Tau{EFM94T9pC($OlC9;Q-R_dT zvo2b5B5JHXU(_tD=%k(>RitQQd-}UoRH8t%_(BIoa@=N|C+NxNzJ8xQ>lAg*3yl}IQu|N2$>dm-AVzgIpKuC@7ynJJ)F%} ze#uj)*PmbTj@5_P@fK5!l)oN9u1E|H6`ypq%d6GXcvG0Kc%}1}Tg4-^^Uv*SE`L4Q#T>-dAQFEjM&X(T8To6hAZl9~u9|NFJ@v`$~D?>PYrLx5`o{ExWyqFj@un<9d|Qd_po7Dt4^2Itdm{HT4LQlwCF z-*(s5ZTU_33oP*HE;rfIen7dd&f_C;b3LTx34neKhm+jH0%dUAZmf6k3&$(=SHDXx z&Sqn&85$0q8tfyc+|{nQnyKK{wj-$H@Xgku@hfGo#fj`#QBQ&37_7d0o|LFG(>n*j zjCL=igW8&9zdO~$=*td!3GaI@p`EA6v?(=Ud^HYQT$`6nrR@;~KQ>#^GoRFg8-^q& zeq5<;k0zrSCs-CXBtrdV?>NexBLUd2{K}0USxpfrUz}=}-vB6IO6{TuN))YT0dW;1 zQz2G{vR)0ix9Y$S(VX!zC(!)jq!-mx{KF&j?eO{Z^f{53&L&kRckGzupr`8>HjTOvGb5!23g!9 zd<$@$1plC}==8Pi10_k7f!XfrJj568ZBW~v>>k)nC@;3P)T(0@Vn zSsmmcP(;+Yxm^c-t?sG6t&1}lxa%PfH=Vh_5bU(a^y73`SMkqy-Xv=Op{b|&Voj8T zNA#s!#R?W`-;8={yDOx&s}b4O4#_JWG*gf9Z- zD;fafiJvu^$|!XAg1Z-AJ;PfZHd62>$NDPZw|)UfKIRX7t|C(P6UsareMffDV>LtG zl_#%Xb*t}s+1O0XooW!}7QNAKaOE&|w%SCu(S;m=o%ZF?-H^!rK6{7=y*zy(d9+)K zvUhj;viR7S41&Yx{CquKp8x%!Y-4!N)1gD*D|cu+&gHh0fsec}^km4^G#LvVHT#8I zSQHXiP8q__l0wE6)uDON={m`=q-xXCuK~S#u%*E9xt_k^yhVwW8+sAf10m~g4=n}g z-}7Dp>pNzJZcC4;;1c3}(wgf7)F*rv*`Xb`|16x7>R`R&R~t_*%@6;N3Sb+Z?NrH zVZbRy+!+LF204?G=_`18MFBF!A*J+C>?GH%J|}~W2=C2W8!eCv-ddW9<~P{J2>{T( zZlUuWdw@61f!>^tz%qe9MS<^93$Nz)2Uap+%Ix>nqLib5<`IVJ!2ABdXG7}nAyE=N zg^<=tWHZlC9{Bq1`sF||vauyFhn45Xr^>lG9~NnQpaY8^-L9}v4pbJw|8!Q??UCk- zzFO=p7dw%Z?yX0FQ|G$e$*maUd9id~xIN$DvQ+N;f|@MU$dd9W_Cobm4#%r&@;sv| zXK8O=!M(hm8(NMoMGeRSneMrifD*b9nrECJgVJKeJf$>vX)dhJ)f-mTjW%ewYABZW z1g5>o8v1ZgL+6sOhy^1ye)B0<7{)Z<3+)9qX2ml^SFNu;WcV$> zStHG{d{B9_B#(3OdWWhX_r6Rou~trhay%lkwMRQA7t;}=-($E|u194)@T#7mFREh46wwhj3!OhqTIcgmGmcHD#XB z=F<-Z5Nh}O2Sv1T=FHPI4UBbhkFO-1IG*276KU&-92tev&7s$ERoLS;nztJo=cKA{pk*^^QodLHGPYuHsanI4!!|N|mQSJZ*_63ZRBQLH;DaT^K z4C)vkHyRYKm=EGupg>8~E64OVL{P40L?kLMmXcJ#qvG^k4Fpz%%|M6qj? zm)(((<2;WnitVKL@y&6{o;TaaBmGDv$Lh~=ELK}B@$f2<=1qPy18xGfqv64Q?XI`F zj(uJ3!X11-#}k2?Pu2K~-u_+CLs5Z~{rb%wYq94cMbmySp8o30Chwgp!8YeocK3$} zkE>JjE`0xyUPI<@0b)C6`)8g%Zd5TJ>^5cV0S~kk{u^~$lVv@IyZ_Y_A18gzkRL2o z^X}vC*d4{C8`H>--}34F0S_s`V)Q%D{Cl@2w_#}KBt$on%=bCLS9q5CQ1nC-e2&-l zW1=G0{~RxUJ@;Ftzy6^I?HQoPW4nHr5+m|rtb8fZ;uCEYfNS&EM(Fy-?9$iHqCb9) zUqyLNe|4=^xLUOjj6jhY&c)lJ(B?_!O>`GPL~a6-b`?QOatA8Fm33dUyf7#SCHHN{ z!GCvoRvd4=ZRXpQ0praKQ0c90Pwn8L2^N6yK1D<{e;p(HfTOspRXPo_Bj#I42NlO{ zHy7D-wnGvtKU-{z#_AqOJ zsK7?n;;&pi=D#+9$S-gX2zU0ZZ)nl2bUsgZRR%;=%l#iCCG9k}6-Bs2Fa(|@5BKItV{=KHe1f{n`eu0#{jJ;J zFu^%*h7g*M4?XGEkdHHDKwQ&cXgr2*y-OhQa!QgUNV9P6tz3-kwSkiI=mWylP_GZf zIyB(CN#g>LZHd)hOWtcf(8;(GU}Z$?wJ_Qde2T2|(?X>BP(cF~ZPJQ?y8%oI9^r^i{F#lov_*6~4I*o4fLiyiaO>aDW`U-Lgz9dOLM0XzVtz zGj$DcbxyP^ctlst&fc;}u)Ih(ZGfwd7agbPsXw(?9dHx?n4!o_7^C>+>HO)&9AO4+SeN2KBKEk<1nQ zBC!i_oBFI#Yv+H5r=E6qm1%LPOx~{-&c6yOxLR_x7SYJN3i^+C(gK~txZWFW9sGcW z$bgc6j155JdidHpZ0n;)Pn!;}h6b2t;nlDI*rqLDj1^qD3>O-(VpTK^`AKZx@~y}y zSIMzThsiK(oEcm+c;4~DKqn2qO*iMt6pj!~&+d&w#X`Hj_5nWmvJ`h`KfkXLykG7l zwg%&i5%{C*@3-3x?uj4t3?lnBX?EDgZEMa*TpLPAVx6cS5+-byxA0k%!rEirb&>dg z9LnA(`!JN{)Ci{V)x`(X&MO5#5@nC-=SA5MPH@vk68fA+?wazgDJ zxZV9cEIAhqhxj2k6Qz4nQ@IWy6&^}1Ne$cCY zilt|p?bAJ5T;g%=N3HmQ4TgpqY>7)hkWA;~ujMMXL60#JvTRXmSFzI%6{%H-Q8`|B zJ<|AGy64f6D9*$(@Q#T;HYqaFjf$k(Sa}Gunf{BLvQY`^DYbLrsb>0H0k#*B&FzNv zE_YU)+B2tAd^!)zjMsK&7pPoJf(0aWWUr&SJsD#RNJ9?`*79bvq51fmfChg)9xWrn zZ89OMY3VeJv8cl=`v$lJXmUH1y*SH~7}@h}&6o@vy?vfiAduZ(x}QtEStm^dB>vC< zBo@K+caG^|M$iudTy9)%gv9S_p80FM)(-|$n@nGV0GtxWA~q%w8*tDf(Uaz6>1hdF=J@3l@xcqbmE);@q2r7$hZv>K%eH zSLIZ70V(<3F9G>iBvy7UG%FlgieRC2*rXi-VgCiS`mtUJ<}WpcLE9V&j4=`FP~FS- zr-VFfL;TKb`^~VeW;R-b5s(L!{?17s$RHevXkqm)C|ANMx0CmlZCqtmp zEzt|PH7T2BMS)Y-HP0Vwp)dY@QUE0gYw;0rZxAI zF!djN*-sbl1xdRa+E*kqfY~a0{`bxF#`4b!7Hikk*Z;|KKODSLT87NK0UABh?zrev zUgNz6ema$=g2hvr4+9?BAg5qQ4SP=RPR@N{#c59eQkmR-0)k1GeadN z13QjHqG*%BJO6g|-K}G-DgW)=@B@-cjP!1tQcEiKQkV2(xh%OZ35i1q0!2)WW1*o> zpNb;**J`h?_533HHfT&@$)FrKz-hmwNM@+_lUfxPFs?7FZ==T;-+1kFab9(>NDbgR zC|KlLc&Th-=%Y&u3my&Y6mbzTzs2KB}Q zW(AAr#jAo;2B{Z-VdvBKt&d76Cs%sA>WeUvB!7mIlI1t^do|5E0hJnChSeH>o-rF^ z4rZt`vHxr_+$vBjgPW#s88=~3t7z)@#p%y$Gz<+}6h&)>np$#$E;@fV#qUtmK0zKkEe(;+vg|BK3k$ttRrbr!V>XuHuCfdvt|nMR8jPFpT6^Ge`A){ z&}1ukBGqfhmjD*bN+sh7iiR`jh2F^%yQ{U5WUW94h@KMEbEE0uS%t&x;rQF!Uf}-@Ax_$s^Cz8be9jOL*~)_1xhl7|Uf%Gp z|JH}UmEj>ff6{MqRFsL|LtejakfWY8TjhaIfLLvz5>TjwB^&jxj$*g*H|F!q1XoD7 z-E!pNgK+9eD59Fg)5digo|b{X?IKEr29-D2D5H4$csxKsF89ACTZoX@+rxA|`(Ax+F*Y<65=C&t{ z3NyhlM6wV8yvSW>CPKN#yfkDq>_3AKm|L(l%Xj>v)&-a#PL|+J_ErRQR)vhx4w=V{ z;)RS>n=mGG*g0#jck+E;B{XL>Rov#(=riwiP6gLu>~I#^{$MY|dhy-%2eilhFQoS7 zUu|T7-syj7S8Z`JAutMB0HuM?qh+X)jfDV)X=`_Y2_i}Fj##LHH#MEhm8c#y`12me zVBv<8-8@qK=`bevtmGzU?&+jJSW>kOJY-8?WXffMu=&+%kuYK5#tTMYj;h&6r*FJ2 z>`Cvi{wL|@+)5OGqw7UH=H0okal)T_6sK#I{5U>zgUuC|Of`lycUFeeHQM+Yk+TVh zm|^D=R|30mS9!$TP%%aA$XpQ1xs7Ypm-MG{UfcD{+g5d210}qX75Dg17E(eLn~tEe z2C@mb7$=g=r<6DHV5C*Ea=f|>`DBZ3%~gc~NedO6DMbd5L~xcoKll)ST%Wq*C7T{s zWX1JtrM&sc7_D!_nyY9WPa@sh=aD-Xp$HEv7=Mw6!~XDIg99j@9#_k&DpooE){3i9 ziwLnY_u#ZLW?k1eZSkY3{yLPQVg-=$s+zn8+87j%Z~}H*6kaKw%GY z5zpWiqO=bYDQ`$!?9sq`K`fa*Ks8oeI&aatU;!;zi7HrOZd;U0Z@B{~q*MLo?TcHm zSSo!CATb(|!D!-~?aqCii21M1 zTz309nQXh@mGVSNB&f~{GEp{c^mmVJj>8vu6)}c@BX~QvEPdY^HevG1vi0GR?)*^Y^*`OCc`LZ=-fLF3b!K1;fua|w zYuhI`m&m36+%)NQnt}$h-qNp}_Jc00z>kZc#?cu!EWMu`ogG{%B7l1jz7zU*VQ?<$ zm~0NLA7o;55gha-+0NU_^q4?)-U{zRGd4-ZS`s?&X7Yufz%#J$|2#Z?(G$wqat3JU4CjJe%4gPMf5vC2J@yGzP1NkH z?fLP`d+?{>0+maLY1^mGXy?uF2l6TO5_rgfzv)d|=<7^pdaXI1grwsosMu!Gm@jB$ z<7uYMpgs4W>hp%FCy~W-W;F|Dc0yevd!VPmq|=yZya7LWV(oUOAtDMNgsjS9=2H{< ziaB`C9F5Y>W`kb^M7=1PH8pe<@wn|IIU9|;&AKNV9iV76F<@4fB62UU26GIVV)vUq zw~~UVJP)$>l4DI#dQXdgI>6YlY3k)IvW8(Q5p(7a^J^xB@VMuO{WftFPX=!{AOC8O zMDvvS@k_yQZmqx-gtG1p90>Zp5(k=l^poo20zsK77hJ|~bxL@)9Q`mN<0jyHew_Bt zYz)>+2p8)^2Lc5+YIW-T2nEh##wMJ;Ck!PH-sEjHjgmyJJFuv7f2R4 z-BgJGp~&z%+X^=;13Yd?Dr)PszIv5mWBAY1^6@CEgpWcN*}7nnt6Qq;A8tzN{ba34 zTN%~O{tw(g&leZFg%-P47rP5=w<>He_qpfzYr5baU9Bs6nn%Z3yP)`6cg2WfVo?_M zo+0)J(-gzNt+#5h`_}oQ@#;2iFcme+BRnw$~0N7*d%V; zLn4Qxn$gw2XAz}^I-ZO2z>3axvJdgyj;IC7sWTfglli{0lRcs&k;Luk8#Gps|MTk0 zuPb^xXQd>5+>20mF%2Zgc9Wa}+Y{ZXjIl(gtl>~s+VB{*KAmS?7p~rjSI_zbdj>gM zXj8cef$tr&x3~35jei)>pI_TH0i7tRtOM?1oxFpPntG4AV)#+Fc#0UYm?WZ3D|4aC z_Y>Gz+4K)#HvXTeHcvYiqMkMembW+_Wq(QcK3>`PuOY*)!)jNbmlvkmm7`M(Yy^BV z`|@L5=AS~#=+wE}n?IBJ*JO=#;8u>l*$wa3qN0g_=g}d8&kmc(vNBTqXXN`2`81Xc9oE0}b!Uir-cPuLU#=nANz6d= zz!Kw`@LAGtfz;F<=&p~=f=8w|72^;WbI5m52IB{|wz9WftFFEjfEGjGF2?GHoKD~t z-_|rcv?mHrJ)(t@Pk`-xavp`?`D<#?ovap!)N)yaC7VwCXRi^@h3BXaI`5|bsV+)n z;PAlV@8m_oo3;Cxy>$X#0ACZB*e7~wk@u!Q{fg0_TECrQ_H46fq!NY9+oi(yeFEJV zCn}k0BHbJfp;uN(yHr`ii~wv@2F;nos5utjTCR-B{p+8FwYfS^v(DIFG_sohT>S@ zLJz4JG|8wNR8E)w>u*2$M5mEy_O;lyf&YSIeVu6+32TvCeod^gcN{^SN)sPtL=jyC zNm=eAWP^e8FB0=c;+gk*M79Y<*Uw7fpl=SQMP9m&)jwOCEZb5}_M5u}SXW$d9EBE_ z2JOU#pb&ENv5@+%wFkWWjd6E##C85$6Ko!x$NWi zobG{DX4G@Zd`0BuS2xeXSjwx{yoquG+&S>A`w;R8d#8MRjlibAy}HcbBKT6bBbvgEX_EzN7Mt{=aGJxOAJKsZZL4Imue^&}7zF@Xia7)XwEWwVp0 z5md(O6}jwpU6H)fl#798j=$PuG-;DH_#CRd7XA-Weofj{mtqxKTX(R>V^2~dg|5c_ zz`I{l!H$RTyBYmDD7!d#Z%)3K*3@p)*iJTbtg^OeyM64$aIU zOH5k}u+3^^;)k&vP75629ZqW3hmUrf_M+c8ba!gsoch^f22ujwmL<3Xn@8v;PPSvo z7X8W*Y(&lRZO!o?*7kTgDr>`?hv^$#u~kGB7U@Qlq_d^s!I|wp|FrZJn8V5K8XXQd z{B{qoytvWmF_FoWf#*C3-8>vLCaMfRW0s9MCWM>3@FBW1$F%{?hD=Rk*vDtb9Q(gP zATfe1d15b9#tk&Flvgi#o&Nia>!VoZSFkrNG*l%C*_?2)pn%B9x2iWx!j30Ybjc%=%{KN6^RU|U zQt2`uoW2DPL z7YT>Fw>wmfnlgRJdLKKxOa43dedYB4eM9F`|E&oX?_>GWH!V}b2WDfq6sSgKm?Zta znvK^xf=$DeW3AVulCD8S<1kkKiF8jt0XV*|@fY-Gp5>w4iTOrFZ27RX%lNRA4~>=g zn**c^PXp3TIGBw&W`9e&nglEIdQUN=^JkaChaYZzYkSpdF=@?vZ_MHukY@3{4C%td z|7o_>q)F9QCg~=EGq*TGe#^VYU3NS7wG-Hv`A}>44&T) zy@3CRbbnVlUBHNUe9kYeFqD8Dsqitlo4#ou*KR{ql=O*ok0ysxVw$LaPj=mnw>7iW zz}Im|nUz#|``k9_Ej5?Uwb?r$AKSiYwxT0{HkO3n30kt4r$FPx28wB^tu#+oZ41w$ z6#hy^SUl5&n(e*BPYKS`u&_@mJ2NRmjLCz}Jq7TdXfe>R<8J#(SJ^l6Kxk%x_qXuL zD}lGNxy~gYY4M$zCqT;S$6NP;UPwXpn++qudJcQ2X^8+?04OR7L>(_phP)}%EdN~l z>X_jTvHmH_aDUy4%JH0aEbs{#4^%GWq{mLlQ9=;9T2C!Df-{ybYbN4ve$1Tf= zo{vUFMH`Y52ddaH7^a_PxS~}QnFw(eqM_Mk@a9IXk9ireEM z7h%Pxmhbt}H(2PlUBVTW#jWzgc`C|gRnhK@LY8{pZ>Q%q3%^Z>9Y8Gs`R5S7=HyYM#jLZJploY#Twz9m8P!q`&+%ig5^8Rh%8RsY@!l=;u}`-kqR@oh%8OE(R$`-q5(Z&`-()a` zP;a|Z?K>(0B!;C5UUgOf;owNSxz5OIg56l9o#ptilmG4Sw+nmwN+rs+zjmJyYL6l8lY%E%>AzB>E=pU(h|R;S$7Ld3?0@ycWDChRHTW|HvqrJ2pyi zR;%|yaUX+b%r7dLE z!To1aOA$=!gYiL?0q?(}@8nP_&U8Iqe%Oy>)c5`}=pi@U>!?`McY4HHFwV+HF zHtA4hzuzbNo%wQJJq6y%5W8pcgOL_7449Z$glOU>G4d7`wTiMF7@{t+606vNgq5+a z4t5S0>EtYBD$z;tFHdELl35wf6}yvvlxX$I<~9d%8y>ZONdx{N@#VNO8!AA^A*x62(hsLp zvRz`@`a5j(>v$tIsmh5f!r6A6F-huBk>`I%zzNtjmK#Mar+P;^hJrB|Y5z#*5SH@$ z%r$nj=iJ^W7a-OysiWnzIkM`63r(*b-%Af-#gFWM7S{1MCj{4226|SiCJuRVW%j}L zN$pPLDOY^h#8WbM=6p|nx|f^@B#H`+d3yOV$D}V;dQ&bo5>Z?xmY#Q$Vjor!-_V=EVKrGHe}kOgLt4BV~%@Dw4{iMpeP9!z4!fz9e|v zNSTTemy$qnO70Qk_X*$+DN|2+{|c4475qR=FSJxrkTE3 z)^Jk5Y-g)x>_}Gx%*?(~%mLDsyF2FVS2doZrkf{uC|{_joo z)iby{oh7l-Uzi0;!}f%`hc+gF;uNCSuew~FGrx;UhQvDCZEUM@*WPGZWiNaW1qpr} zsc#-1%KaG|3^pAadIX8afIsemKeC>m#}4{3i&mCD{vI;=?u)x0=9l^|5?lTJ+@0-2 z(RKnGCp%=x#@`|nJ5f;Y{T{rbotYC*AFMg9d#6*>cjTq$m;E^J62T?Mw8_jUoq6kIn}az@E^_PY`qBZOx^d==0eJ=J6-c zJ+;C4gC{J4q_ZeZD|S@dttRWSb-c_Ei#s6b_~3%@Ad%FgknO#`+o@SA!!i}Beg+u_ zx|O^_9&{a~L_;+1;gjF}v8@W>ujqt{GPievOY$7Af84rBJR)qZuKhWhZ!aU4(+kcY z(f{8mu)*xE7!=gc{s%yx+eFQ)UiP=*(=E3V;-O0tv{gpk5^3bWKg(^tV^y)yeZgw~ zBD&ttu}1MkNq|zx42ktd%iZ z5T$E=sNj9Zb1mRJC#5#_JnJcAS0g`1)S2j=R!OJ|>h8qQFq`ik58Et;rPV%>Y@Sd+ zzrUY+EiXWCzPn0eREd+v_pvd7a+uvDxGU=0P%s2;3>5{K-Wk5Ify}WsNijB`Yv+O@O8xgE47Kv zuV1#s&}3@zXM{3e)y9y@rr{Ci1qM{1r&8NA$v=tbOhUGdbE_tXo7{LLc5mHTMs14k~(^lahZKILhVTwaZH{b3mN%(pTEw6LW8+ zo>Egw+UG`S09PuR5(XIg^?S#o1E^u9n8@UGzr?nM&qbT-OUb*WB6YErl>Qup_%4$@ajKF?|CDHKqv z@TOLMXfP+&arjou>RqhJoNdcZ6x5GpJ$5m6{7=>!+8s#?;Zn9EF8w;ImgJg$xRcj% zooV_7G6i(7ArdVFztvi+7mprZro+U1vwpHjBs4!!?t3iV#xQbHh3Y>G)ei&K2aAj- z`gv8zN1l;87tXq{Scj*oy-uPFB@px%8HW0-lfg%Q+i)8j6u z)y46(4<5rs+1f~i_(o|w_<~60%})tc*(cCA^Y-8?e-9_}gWxI-o+14qvcs3>GAI1W z9+33R3m?*WEypu%hTZJQt-J5_a^ecK`r*N?5WdSjP&195fzkS}x5>ah{^-};3ZzWg zO3$NWL2sy1HX^e_?%iaLgYs|{$R1$e|>IR?;^(F^Zn<2_VL2N{A{_qLD#~iBzvk6W3_H$ zTPEzLryTi{^tzg--uiGG> zm+Lwx?7(;Zc2ha+qJU+(yq3-Bsc@t4Tggq|aYTb-Y3y&p9=;El;kelt{v?NJ*Ys3y zbYZ5QBeD@Osh5m}Sb!2+mWNxkYr1tX7EbVms!TtQX=(I#Lu@mhyW8Jw^gdSd-^2oH zjMgOz99>VS|JNz^RL~;FC_^H%aGL*b`T`YH>w4Q2fp2rN-q?he4Zt<4& zpjE)J_w-Jz6sxr=QU{t(S?q3n`CSG3wx`Hfj9%mp(S{JxcDpl8+9y7cn|#QDyjdzj zk5YcBbP(680C{2%jKw21N>RMGsbKRKZ-=a1|MTOmNl(+5&PHATr`N{Q<2@v}F?rJr zA1Nk6JS>}AyFU2!dU(E8#qWtFr;9T7gQ;_I8EYLGH1lS;!R+j|BF^QaYQZtrEvtel zt~zmziR%VvfP&E*)=!|p&DWJq)jQxi9)Lek|CW7ksEZM*=FGtfX`aLKH9|h!d{3>3Mh#0EBX@=(1(2DrvO-dg){)?z{aRXGmQx(Fg4^(8t5tHFCc! z#Umj6IW_u=&~2%l2`_+}6u8N+xXOq`PFT1ejqsC35q=cQ!2)U6Pt^dPNX(F%Y@i_1 zT}qrW#_P;wfj@=tEib7%aw&kA#ow=g;UkXiPRO>V$nzHtUf`un}=vt9oXM>Qyd2|i8>@uBbh{Db_* z>y<&iwk?Z79^0G3mSH|q_S@5Qabv*@`ErPMsG+$$gQHI#p!vFY zKACCWO;;6pVRQAGr$b%j;v?v5=yh6>@_Fj~Y0_Yx3zS%Fh55?Ly(qwLSo4=t_0 z!iZt5w+PV$0>YyrVCyYN?L+5>^mYM zlX{&|;gzlri~L>)%XEKF*=G1lSjw07CGG9F zH2xDC9tDc2bMlZN(kQ7|&atZw(m`hRVK*NZ zG#6n>w!E$v^<%nH9GUwQxm`S^F2lNZCGFJbLGOBH4be!oR|*MmY~N@PYF7IDc)G1u zn!NiC#M)XIP#bJ&IruOc^lx1ZkM`_0Nvd?!(2HB-&q{0BSEAJSf;WhN>^cEgV9A5W zMkvnH{3M0y`(p1suT*;+V)e}VZXMJlz}=9&mnONUam+B6c1Ucwls+U{MkPKOyL zj!Rfa?M3F^Do$9CF01#EC69k^t`A^e!zLEW7IbN zl@QUose=&%Wz~Rd(-OyGH5lHw^FzGtM}r)n-6#DT#=616cfN5UGgGqZrAFf0rqy8x zEbwbQ@^fqN*Ef|({&NQ39dyfXw4&KSmnbdV@yQI2se1^Mtsi`tr|Whk&Cs}L?!HBJ z{ysKrV5~u}t~a80(#Ap7_z3+*+lqAF?={mX|CnBEUwxzDbH*+uVWnurnZ%p?)``gD zr^CpHyljQ46dn$SiouM@V$CtYB2&EI-+YP_bUvadDmVQmy+;sao9#GX)oo%TU;|4v1-e$I`$T5zQuzub zz#H8)v|U_3vzI#Ma#|MD?iU zXMC-LCw~4-*8_HRw*@n&Y>d;b4DYjX9i63e8FlwV5KR~v&^GA}6|i|*Sc@t;v_v42 zMeEwDBq0W@pWQ8!iXmff?5pBFCz6xRce-@?kJ4E!QZ7FRo%);O-5UE|wotVa62EN0 z7E&cuahBDXWN~b0gyM?a$YGUmrOr3L7;hN05e`_>IdSpKDyi0(e>ezO0h|=t_NyPu z_glE%?%LRC#K-&D*l2V$?^V~)9sJXQpg^-G&rcnZ^psd8ndEt*vO@L25z~DTlT`^$DX38k?5kHKjmpliNnEslA**Mf9+(jp+q!ad5XR?ZalN_JzJ_ zMS3O=YBE>b!9ag>vpvP4Wa8@ee1eEp-EKqLhpK7j+Yk#Gw$@0*ylnZL(McO@2v=#C z@3sud~QRepwn|N_D-MyjSyD39vMPuBT?&nq5Sbr?yv07Lv!SyP!32 zXv^dMA&*~A$0&|O0(>4G2_a}tSv8lr?r40Izc9S)SyTo5mrEd=RTV9i^9y(P@O&9=aWwZvYdb!}t(1mc)}S$qbU;&Qkmx%KX!+ ztRJ7sr~RLm;a;kVe_2%fpO{hqC(+)S>syvuk37elH{Y#&*$2koDZCECtN6bp+5`Tt ziT0EKPog~oMP?CsYLL@bX1fa<>;Fr%AAKU)10Vk-+B-ZE?KfH%|0UYj{WsBm=wG6} z^?woVkyil3oVn#e3|qrigvc2RCOu5}|3kD#Ip*=Vp#<)USk%Z%ty=1xU(!Ty4q8=q{u;ZMVR5GJQ zxiWbHCQXJ{9x6Mz+w~bLw9FNzoNjuba-ase3LWL57dD{xEk|wcX`GzzTZ`C_8h0Cb zNBq=Fvy}#9wZl{~7vXoA32#4gND~Dct1_tVEO)&1*b%_oG3NT9mgp?2E)a3vQC7T!v4BU-VU(&>7tESFv^12O3;-w!!5n%^Od6xB(b&>{yb&M#$M^5FUJ zHL{emW%y*qH)7v-imtxPveNVkUO$3giyG-L@VkpP_d!z(TUD?GY33+srz=HS2tvKb zG&9hMihICj8;uE!5!82@uM($!#QhSmLd$;r{V|WxMX*>U{9uacG{35hC~{VukF4LJ zSH0}nBK<2C0qc)Pw6rupC%OLLLG`f8-TpUWTXR zSt8u`IHsR$@yr+)8LcNcs{ zf4%LPF1oY>Pe^i`G+vrbRm9f14!I#02yWy!Y?MuGJP7S>yATPG&X8?;k735#1FdzN3szP!dEzQc7uZ$mC-6sf=D-FH9BLv-(y2{Qn<5&|fzA3Ys z3&-Czb|P0m#e7wM{!P82Sf5?^ z3PJzJBkrv)ar04gmHmhE<9_vyKELHhcwj+{)bDhIaSL$6hXjLoP2T2&>4r~79agxh zx*mzr&>Kk(QD0@ooaYZZ>FteI@^8Rx-9riD#s8=d!O7ZAB(e+A>q2MKSeECF1@h;W zewtZ{eZlQxu42!YtC4y<>-*IiBhSC_it*RLXMgnq8}&O`y|26PdTJJ?&J#aH|B3yg z`$;pj>9)fG$Tksa^_xlv<%=Z-`gBC&1#ZeP&YhCpeHK8rXj~!{LS~V)%8FDNR8+T(-7!44u zilyKWQ27Bsy$!t#{7T8{l)U*EXq7${_2V^0c7yb*b|=t4TS&XoS)lDQio1(ASNqt796#quc5YMbEe4Yf2^N%&^$YvML%?@9aj{vmx7u9G2zZgDNvK zMb+$ejq-7CX?*iN79PK-zJS-=Ju3fs##Ytn=%KeOk+ba|?x#DXlrLAqux`N*{XF)S zz%@DCcjMwvNhZHo@Sbvp>#+WaiALn52&7RQ_!hvP{!P1FB8H&#or_%N$QQQV_Qxci zY&$!Qd3*_t zeW(Y3i@3zAx-D!XfTN#{{ix?KOkJfxEqiL2C9GL!gR?)3^?T-?VKxtD&9eTH!&o^P zQ4m=5tKJvT-CC(_?rugG(DiyP@AW#bE@*bTiEgFMUz8~?CC2~p;;Np;_vqVBB1Mzl zXeHa3$T`(UiFl`abOyx?I9fj*x)JTIJ9_^!y;gLQfvCHAB-)D%tfY$KJ*t7W{+hK> znq+)H6%Ilm+=iXgAchCIjI3IXAGK9;J@5#R#G6$@ygFw>4XFMoQr< zj4P%&slW#@nl|)dbXS4A@jrOo?KsvkS(T!z3;NRlK+_yo+>CdG!<_Z1>9Hj4T&nYS~;?_@TZZF?f0 z)1u&4+M%*{!=e+eg8i_UPP9>%5+t?^pQx#!tsF&j*gqgu~?Q%GV}# zaZM+h*YuD6_sVXuBO0O(2aODpm}*}g`_O2NG_zpa#QcUyB_UbXm{AmU96|a%)s~AY zKM7+|R4C=-L0o@X|0x{Q=e7gJ)VjL=l$?KShvv|rSh1KDALA{NaQfgJgzux{XkLuFW|0eIG^1%u;|uvteD8s>)Syq5f9&N{7 zT0d3q&B^qE_5)_gE-05})tn<{$)wz0_xstdYk|vEVdR!dzYv>BG9h z;@H$s68x!7xVY|__-Zuv3ZC#3p70VIwG}K8d%Uny+$A!`2zQpiP>|qCCX%8=h1j>J{r8gMxIhiR4_UTM<@aHh`=Q6O@A-cj!Tp~)Z zCo2B_SzGGIxatl>?F8J3dKooRHIF@Sux^{tP7B?rmt4=_x97Ij?B{x@RprW|tdd)# z@>YF;?|N5)4({2nTxt06wUgDyCQVkTRP=V=psLp| zOFr#02yvl*`qB)?)j#XvaJ5BmZSNm*1+SG*iBl$P`>y99rpeRl70eCY^IcMudS$WW zeu$$Nyy{QcZ$i~<-LRJv!x|HfsrcF~#h#K*%{Kb6L!AMJZFK{*>lcgF9DV!BXKS^U zEH3x`Yl>wi`g{Q5pR%SLb-;(nCo`GvWFKpTHEzj%h@XD`UNRlk zk-qv~`6m~@1-Z-C=E%yZ=rkzfMUoFl(qXDiA9mKLjxJbTrB$eO11av1=Wg$Su_b|Y)ZkvyE<057d8`!iu*No=#`qn}Ydj2)2uz0-d9WwSlCWw>JZX*P&a{Ut~bl3kXFAAbNZG z5;=%a1nyl%25o_CNR3u5BkeM87i4c`J<*~thy9{0)kGOkf?EznDndR~Ir-AyRi+TL}&&8f6y0uS>i#=atW_T1*(Y|QYCN)EgsVt`0 z`sE3xvg8NLWrOz_MU2QqAJ1r#s3nQM^tG{%fNfINp1hKYAo07ee^EEY;P^hA_ZUJf zjidjzvWEH+N&nc+#N6gGmVP61)9=(yo*_wfO#?{f+hhrY!QLs!t&(n^0P940$XUuC zvV{r`(H&VxF9onK&Q0u#JZx{cSL!2|*I#pUMpDrVsAThJ45>W#XO-_t;9Se7|Cahi zNI>^Z4fcGHqj(g3b%0u6V&CE!r-sz-*sAZ~!xB{ zwyLkzU`s0ymP89Zb=Lc}1zkhzUP_mRPXDOOQ;5-wYpJ|0c z=Jsn`nSmIh55er`AHeaBF%KKB?S*?pC>r9hmDh$(82BTn7T=AL1661bn)SjQcvt7D zQxT75$k|P4*a49rn?KbOAB$QXPe^{mWqmN%zgVGD_Q1>b5+#v;Os^S|H5y& z^Afi5*ByTjfyb{6!)Q0cA2fMNxBTi}doKx)l{M@!GSQC3W0fbAr#O?TeHi{IyF~C4 z*f4S>e{ZAWQ2+?!HUC$Qp#ppFH^O5W+xww6;no(g!9-Y>;U~m~Ei6ZV-NOX7WSUg+ z<30VLxIh{N*I^ReMtIEM92&s8VGi^VofO=TZ|thGYGDpf_mQ~qt?>J;1eaHFeB4)( z1>a$IveIthoTY{06m_$-S#^z61NH=?*xlv9(Y33efbDMlRSk*UNa}NDE!I3#gf$vt8Z&8%h$&WDYHp!D8#WuTN1P3^yx{nI6rfz>gBah%i-g2 zZuzOu;+!-s90DJj0;p<0<^CYLxkL}2~Wt-u$pJa5;_ zku{tGuns)-28{FL2{q#U<(;&`Vga=0vYeXrFT<83`pwOd8 zNzNez)&&aH|1n@zwZQa9h{9yUIrOViuhAgt`IlAOu`~HY3*4ccsnuuaQ>_%O9GYo7 z$76{X$w~S~`x_p5Km4eWv@Lkfdd;FxyS8+`X5wr7NY1ckJnaKi4clTdwRM-j*6x=Q z&z%R6^R%z2#@$NZ=C?Q=`+ai*@B`BeK1Wwkl3Au+GD&QorAI|w6fp)mwdce6OkaHM zUb7qSiDVX-dV{jF<8_EY6z{)D{~_r{?)&;ZdJA~-x5DQmAfHz3x|MNk4RPWXOSJ!L zh+*ys82sw*_2rcvUv0hTTCL}8c`Q}Q862v<^e9{;d)US_7Qo}hZ-RiCE(r>Wrd>Ao zSix7`BR(!4e;%rO^{eG{C@F1K61k9e)U@98V)4NnNezckn#FRE=G-UHiHENj-749F z3wDF(UYa&&oe|5hly#e^C{$#k;yX?O6VK9%v)0pW)=5=>PafTE7d_PR3+Z>G?jQH* zNT@rf`+DX-jYvJtU!@B=p&MJ=5<2*H`~Q&JQ;7F^6#swZ_6qAxOkT;YZJv8fRD2vO zKl+yQVgq7B)KRYjlGNm%a^tA*eK+4Pb5Kg0?&Tk9*y0jrq3e!P>BGlmHXBtms1lSL z;L*>=$nBwba=YZ6+z$K=WR5k@?ctt!ntv}S9575evra9_I2$NuXc=oPYQXAM7*F-C z9wCZ()vW5{ei+_Ny*eNG6b@`>Ab!hprN4w_>DK%Z`e$4sN5xRa37g&gPa3DE@Tt01 z%wR4`+9UjxJp&K;wA2#v5U*lx)}rCqrQ#!Wk4!pCnuNwU2?Ie{y?!U%&DFS>~{Ho*S*LqZY53y}=tm`1hC>O6dQ$+z!IX z?X~AiX9WcNIP9k7KGZ+6H0ba+YM}`gHB2Msvr=vMDdPXH+`e=ZH%_Ke`?Ee}zJaN= z*~4QZSwtb+=OTUUXq#O1=%SmmJt=8rJ0gHCf6+|*sMEgRVR>i&v$&FdNLBlhg%Fe8 zD)_aZ1deRRU?XiL7pWo1v)uN34~B-T=jsWLizY*BOYwV&Ul@5@?cx|NM#SydzQvDU zaSU_78@vWY=5vwZmxP;9kvcRz`h(JM&N1F&V|*ef-5At3Na2@I+%X4%NAWwp?wlJ2 zS93D!C-!}zy>Kazn=?eY2B^xWxa(X@^rsQpjr^J*!bfY$4du1<^Jd13gI-wXQ#fUDhssq>5*@6cZ_-t6mSp&|2*f*A&o(%lf3;kFx*n1t z#XU~_VgK6?e)QQUd+V(;&FVX0M$s}~#O3w`8{O5IFe8UD$aR6Zi9}kDcqe?OJg87> zc*Sv&zU2baZ&=h4R7O*hjgHJmbEfNg+~i+MYe$URg%}IB8++tj(Wat#7QoJ| z->0%uAg)4rmH;rC-vB=ZSwg4MST88l>L6Hu-2L8Krztz28;)2#>B*1tH~pYIiU88osGGLg|!iVm^b zM+QIm>|>MJeP*_v)6W2earL3BPYodMiV9 zbGA@07BlwFS>o;X^1#oO+DdOrSI0TVWi#?x*Ch`6DLF}om6->gMd&C;P@XL4hc4yW zw3TO~UiBvp&uTundSuy;%(?g~iqCe15_35M1B{T2Q>*Il(RJ9?a~DtBTm8lTofz*4 z`nSW>I!Fkj!&gEXkdDjC3=cHPLMC zw1R|POfC5ylufw&3Xm_;9&^m$$dVo2Gdp>Jev0?)iUNCtmY^MGL@m!E81x>SwHK9e zlSoho@VlIiI)Z*x*eb7RI9wo0l4EotBcyvC9J^yFo~oxO2R5nKD>8hE^DS_js2J67 zNqMt=^`q!PpgM9)TD3l+!XKM9Ikzd^;bvl!sLT;R+0R{!2dj|9VcccH#rtKvmCw19 zPD>BPvB};{W*XqZ*cJg%mok_E2Nu8NZLOoyA!@LR+~KFMtFPEu%oK3Ef-ey>cRZLt z89$6#<`eUDfHX1({?K93L7VM{0GQL;t>Si&kp4 z4#0nm!!J)L>YPqRbBdzbZuu@Hzm4pfGkOL7cu5pI9?!QKqvl&X$8&Wv#|Afi8z274 zQ;IRKnQnFOmuQytXXMS!6UGmshSV<1R7F4cp6t7vg6>QI-*3gulaT8lrvxqLLS+?c>AUpqdG@)Kuj6E2>tSx;&s z2HBz&@s75zzLOa(z4i>*)zMP`GiC|axC3C*EH}f@T zi%0v7Jc;0Fb$gNVybhO7X zhs@APY-`4+xfkl6)U)g(WpC>+@3%LyQ&P*$Nz?E4GMP4MYQW_NzLXirboftzKa#8H zw}huW z=_I~bY9n5)5VG;26W$&47fr8r{Y>q|TAUzYUh7yzEm{gFj-P>M{; zk_p~~X|Rld#kjyRu|pZ(^#%e)avI;Ar0Z%gH;Bk{4pdZ6a>w&lC7y+Jw%fj84s41C(24k)Ih2I(Q zg{KCSg^sq%x zRu}dYEjE49_Z#wa_vZQW^PC;Z(v$kk8+>Ho$taDZbCSnn3-DagBgzJsJ@f*UK3WYmX(v7{H852U|}-qf*X=o4RWau#O5+(Ct4UYcHl5M|q0 zTT;G#@7M3W$cSnf3-1JYHUAlPZ5=g#E$5$QMTT=W=3AiY?V7Vg9x)dyQu;Il#R$vO zNh9i~FW0oV8F4wq)y2PTlyh2INsxu=lZH8$_Cd_4lKQiQsFk@HcNOhhW-ZOrTHJ%x?=)^Y!YF+bev_eCABjiPKPX15J?o3#LpFP0u;B zqj#Fm$8^^*YYT)pGHB1sMbxw5E2Mky=ykT42qM0?M2WxhD(#7@pf$haHUdT-xg zvZYP%B)z*K<2hLm;9Z4k?KCadd2CPQR(42*0P(r(i!T`sIxaQfc1Omncj*Wg?C186 zrSUgTezHh#^?5bS&+%#A@$d3Zf9YT0eOpxul?^uC+$(=K6{ZsG!4sP1 zh3cH!k!O``u&Pxbcu~-4Yp3-@b1W^XBuM9Ls)Mf^SbH@(mF&oG#L&i}T1(fN0Us;p z9s~Z>O2>ue5np}N_lO>H0n?QVf5*p%YWASoRzLrTelw34PNRIAa!4M*sHg0qa!xHW z%=BBP)492G)r`0fz0^fXec$x?k^K$&QHesM5T$;p$V+ctbs*7*JbZ%c<}hbG|G-_| zJ?Ot(%sAA6*93J}#jYxUQ-!b`Xw+~TMA_>QeY%K#)iQaW>exz}d8Ocml&cz5(eO;q z)F=Mhg6DNxti*p7b^u*ji>EC5z0(;>Gb!ms@}KEx>p>WQU!Eie-}|KqmFHwr4*J~hxH$xx(2B%dQJr77y%xu@lJqm54&vNzhor?vy2Wz4{ark#5H96 zzFavdq3?dd?k&Sm`*7kv0X~+K10%psjG=y!_cmt^(*EJV>vtQe<1-ZZ^9*G9xx?fL zNif*NuO4vx1-_8G_K&y`a7KZO2($AptH1P%8t3JQ*QWAM5u(nz9x8a#7W}r{yZ`$X zC-nZPAcgu2&5-4hZ{s%}b$`7ZfqS|OZJb>ugfXjxLEM)y_Wmwk&gniy-@5w|yhq&L zN638|B-_&U?vsw)k&d17>X?vz)qhY0a?ErTR*maWea?SW$`4q@&60&C+M8&zjIy$ydLmx4`Hso6t(+IDJm$ zhC9hOYZ8fJ#rtl>1qZo(`vWJ*mOy&788PePbEx#(*x&xMp~GyVOVd10!hZsM#rX?r zzsM3lN56bI*FYNbKKu16*{)FvqJWt0Of@hi?=BSbN_fe%5hhuBB9pk)(E_iKrakwK z-e@R?13wTgtxf+E;NJ>AGqX~Ok=we*^}hmqmfrvp1H$_*Wl|0d{@6;T)N6g)jmguP zO35rX`=N}b5AAKFV&(^3f7xmpha!Pa_(ARN7qC%`lds&Oj_DpTb{49FC6<}@|g56eTr&g*i!6Cp<4S8=JaM#Tz1uF_Dq6C zhb4-~H;P)Pb+q8q0p&E3>uE}`BLFH}gqw0K!L3gAwiNdaMHh0BNtcWA!%5z~{s4xf z2<6fCMjuK4xcYsXybN-mkJJqBJGPdhSLf~amI7zU?pUS9aoMJLDh~b3f6|b@PA-t* zZ+)|wE?rHVaLK?DVR?-8szEuXvLW{YKG_Tdf*hauNf#BB*v=}iy80!ImX~-97KdkEJ1N9n-4Ac^6(D=b(Ph|! z8-`TSC}#=Bk2%KY_Oe7^iI64iHIT=LoIfTzrlTvi01oFRAE?v8`98_6%}>HA%IsQJ zHqO+d>vX!WWhEA0M_w3;E%q%24)Q8?M++}LVRA5ut`o=LhlbLNFn@=$!B*0xfn^4? z*4hD~%wneZ`Q}Y{_iDr+lm_eXs691ReK^glntuj-LkH8v2BZrti80{!U_m;dToEt< z$ukbw2Q+2Mi(y(j&u{qOiNM>+>jr~x3R+vmOp6hmT`!YGrExaI+6)-x?E^Gx+xzUw zA!0ELcz`%dQCAd-#+q{Y8+-FN-N zBz+1<%YJvd@0N#2ek~yV^PAmc_ivcwq6$-44(Uvx9QSUQl-p{UBpZ$tjP8@PWjP`p zx#yoDnUzDjRM^S0Tb?0VoI^TW7{I;zH$$>AC#p^ZTJ&4aeK#gd@>nIKJ|`;lV#sBa z8kWLv2fzzIN8dXeD28cW(e(i|nh}1y#FnAWd~MiM@b8c%S4^syb7N}(Yea&J(P0&K z22uu8T!Z_(ejLq~{UmoYYY_-g`RV@r@=5amexHK3fW=`q_hHZ}M6DZQ<|Lr)Bp?7u z(sU9qIaF|mKOIu_zKOo+>Ahw=2eP2HA}@OthxcHpNW>!H?esQs3yyjQX%|m1qUR5I z>llXt;L(Q~0x-9;E00C-4CE4s3S+=~UM>D-z`w{D8v?sXfeP+TgO5*zEqoKRc8|Y0 zNUG1lKd-G6!V7dtO{8a^6w*bzKh%s4X{7xy>h+DgKZ`3q!MyFKSAu!7_lMaluV@h8M(^ue+WE7o>zD1%d#49|LRwL{8_iv zUCFjm_Q2vlod=TTjign3{=1TYOFN79-ZqgIm9EXWskt$kOvO&PnKVUd>f;-P8N`~Z za5pshL{90Lzb=)DAHJaRCZCnqdJ;ulS5`ya@Akd;=YvTuIF;9uboQEY?3ZE5$iz(H z@~TCzNdt2*O|eHJ@Ajv8HB*N|c#1Ern}Q{z+e9h8Sl)G*ezc)r($5XUzwZ$==Bs&I z-9qlmXjp^1b6eRbt8rzb^IO5TAXyFJUsp)zIo$Hm;jLc<-o_HFZ4r*2A<7G*_#$B` z@TyR?xKhN>xAQgjvAhxnDRS~*^@>xF|++qpLhXAUT5!O#AvI(cP&GD(|r z(GY+p*1!T^|(|4PaA+QhUOLAd`i<-Uv zpY~45vzyf%CF0g>$D}^qiy9cau^aJn*u`k?b93HcR7n#&l10PG`6E8Ho0$Pr*zK)B z0m!5jeB}X82-e%450NZm%YbNA`(=<0ISQvg#f_h;sA&_xJbCgFOdZ*q3Vf^49yC8;I6K{JPE?VB_7_*}g6$@gC2;Vd!1q*)0e? zW|u5h&7z+qU@&ZmKbAPUV);WhS=1xbfrm~X=0|U|(6ZPBOjwfJQk#G+yT7(9p*t%p z@Y`d4@#5Kt{xcAuao;&#lAbhv(n!);zVb2KvsH>qBfdzO-osECm~7c&fb0u94T3Y4wX~g6RaMEGGs1lMgrb82 zEj?(+(r5MyZoMRYJ|h_pUOvYF-pZpAR;4Pp{qt2!tMO-BWlV11iQdK=ZO|m)aj=2i zqM<^@ZBO;!gz)s`KIF34`nEB5^MgTILCYNW^c6}5{=Lta`|L^S*DYVy3ADrPo~zQG z_g=JXd74oA)zz(R^U0x@vXtRY@08S4o&(@PT2hix7c96+GyJgF`?m8OG~@fZwf7L$ z9t7wH&pk6#on$J8n);sAR7uRRfLqYTE;$3K@yPQF`H@{~IVsHrP9{;4V zHHV@_>La_G_rzr*K%zVCHm9iN5*1hrS5c)B8s~H?-NrMtBL-MpBy7@2+wuqd9>bf) zRBZs+E9OFP@v4M7Uwt8#OXnDfAPiiDEd%Nc$ccE90^$4mOQ4;XQ83v@h8&Pq%{|)m zkc>>P7f<_-!%mxQBtg-&9^M6pC-aRIlvjiI$&d^P)y_qe-x%M$`3$uupj2eda?xbR zEO`?Z{=+Gb5$6DU2+>{W1adFFY8*XwwN|m=18@4Ft!?E9>+xDt=t zX!;0nQYk$+wOFbD+Ys_N3?Z#t5P6yO>%}CRoHy|!7Tqy1KMEY?b3lUDxmgfI#~(}a zEG>J7gMtPpd{y0uxOY(Y3V;`z1uSzAzg!1f?10Y09a_@|Vt~Si%D0!UG^sUss<#tb z#7+k~W_@zqjSCm5GX|Obes-ex7q;XaRU)dW9IYk zWZ|@`&!~*S`oyejk9#kzrJ{MxJNC6|VS{7m28?M-BF)}v#A%|WE9`6Jhmmp@ZS*t% zkvA)^OsSYfNV%e67Oo=6dQUcyKl&cYnDY1u;49sK6eN|uL^$4HB8tB%E+(F-e?SM071u79v`2b&u3dCdpgx>?)+!C69Efdh$D!R2sK*3H*qbx zC<4#b!X3ZFC`Rr0} zSq&JzxB^RAu&iVxQ2N>#w^pRK?(F~|>_ceR^R1B?@YT&{EZm+->GRa76Cao!mU>rt zCs4sxTE=68d1>s;KJ^tQ#1%i0LQ&Ff%453~-GVmVla^(`XS=iBd9I>{-mSU7t8Xgi z;0!DYnem24R(*sws@{tSC=#0J3lf?pzW{|22P3C?2czS*S%~L=LwUbpal%HVucf%- zXH&yPKLgIHT>XGSB14@CAg#M?b;q88p6i1b8MpZzpxmk2{S-!LfW~>LAp6T!n}Jc` z=)+fz0#>#sM)37J<~;+$yu-|Mg%5)iFc}thaK&PJ@0WNUx?blcZ40|o2@pMe9x5|( zAp%c2pOo5lfPfd%TC0ZAwP>d`51N|{&s;I7bX;cP+tn;;chEbQ)+`yHX`AsK^d9mb z^iF62A_a|h7!G)Sll{lJ2VTVALGKTwi0=qzB<}^n`UuL1W<*DkgT5bAf%LR4*52Ps z_M`&M_poSJ5@fx+mbj*P01AZON7vs$&=jlD)EA~S=(bVskScpP_Rn)>6ULcj->XHr zVkC1IvcDEc)^;FM4+&YD11`(MWgOoYL+}Sbg)+!m_)Sh6F5-SbGM@>l+)(^|L!?-@#oE^)UW)&BGxd@!i^pTZ8_l>1-<$SB~N@-f?yDZP|dvi)Caz2HCTU9sSjK(268&J07i`+P!h z`Tcx47=n@Bv;U9u4$Z$bYxAG<@$Y?&$d(gjsT2kKFb_Vn5n=g9x#y1gJnX~bBvyKl zsOS`7;Sm8NZBt=IBR&IGfP%{?RfN|j6FbZs8p?aQmKvQT%Hl;jsAw(1;&JD|vyb~k z{Da;f(Z==sgWeRv0JW_!a8F`o$;Q(kH_!bD!R@pkPfmOppArjLlYIs_NDY{CC;Nllg@= z@ItgWWb1TsWJkuFHQ!sHc9HAk?`S28`z+H#^+z7k)30wFdGTAJ=XVoy|QIzW|5O}Dti(o z9)UWlZ1GaG3C>&I`{X6i{|mi`-$C!&)y$(_E*~WvN|T^>(0hH}*|qz2rB6zUl@vTr+U!@D z^J!4Cg5VDEoNShlybJR&H~GO9`rWf1*qgLCv(}8vn^Kx>>D9~_2W$R1!e_cWX-Pm? zM>YO9pw}zW<14W98UhB;(T|Hg_$t}v<*LWg)~XJs5CzCeFFdFNs`slzHYv3)_14!c zX?j-&a(_zRFRowU-Zh?LsI2-jtS_5qC0D|g8lBafon|KCsvr?^h%_nt zyT-+h@Kj0~>)vT)9|x&#xyEASB%&$tH;#XrWSV(NulO;;;3tq_0~2S$j#Rzx9Zul2 z7WQ?(53@esQST*!?r3M0#sa4ws5W6I!?Om3zZtsg^>Bg))h*b41OG6W@Zsz&8dh~j z!|nzJ)m4B&r*9wzf{#K)MWG&@s2^4#w%Oq1hX|#4C^J5mqqC!^yCQe}K z2$Wg7?{-Q(*@Pq5_0ESUXdrtW=gd+u6!vDD{7~-cVLXOvpRlB5rA4gXEsfqzrZwqq z&XR-izb?i&?^XZfybJ!TGzN7qOaoKt4x1kV^7tV#)^Zh~j!88!6~5N8wg$*}PuumS zls1Ux<&iq{&Ut@{ao$V+$9Z?WL-Su>|L44Wsu}3to~%u3tfr8{vq|K$%YgGCOxdeBiVk9`J7mvm`NQn(4#5-%G#W za6uCSG3{a&oMxvvpEjO0r8#fjYR}aCA5`9T8kZao>)u11>9r8!Xx(Y{J67H$A{o=w zO-m{53kJwo7{kk5BBl{Ncgnk`aQa{7!j)^FPYF7Nv%-P7m|AW$4I=oi|$T zXU3Uc*XJqlKjpo5rek+iORw~063>xCGLITJ@2kQH%z(eg8ZNDE@3}O$cEmIbvIf#) zwY&6QGtPK=ZA)X6ckyqV(s#;xbNYwzjSW}$vw9>Y+8zGPvG)u`NMz%Kd7fL=-|MW? z3~ocD^P1{({mJ?oo)j_!9BRd-`lq~W7+{q5e$?Sf%kAI^X4pagmft(nJZsd*Xvcf^ z!w##<`TM0XrW{B`g7DMI@TxgX$*EE!1UA-EKd2i_nr(BX z5`VT4;>RQ*Ox^z~LKnw7VMeT-TFh^#^e#TTk|Tbpq}MEx%cEW6NOe94!w>SA8vmDDICkeQxeawoXUQa?f)@nJ}RY%Px8dN;>r9fJ?B2jV#=%>Gu1XfHI#JXKBv&uOd+d3}gK z*c@O$eHxz*AD#&xGLU8ie%wueI@+h*u?O3lsh}N0cnQssF&haSZftg}r6!XdngB4y zJ6Vzwmj-|QmjQfF=}lZ)*ouVsCdPPwi80=5nUW;`!EM_f_DVWaUomCd3}xIp%P}lY@jo?m#U!u%6 z4d&8Wh9QQVivm)q$o^HfEk)anYkzSA?|Y#y-|=Z7{phM){I;)|RK1W2D4o@_bAuqU z0Dg3*Rn^*vMMZ>$9gXfW%dqalj-X+0!Y?+$$xx8lIScTQn5n1T0?(Ai@Wzef?0#r< z3N5G0Anv#F6Th~+F8Q~mr*Zynvmey!a|eets_E4KBi^Zk^TsSNxO%u4;`Gw$Ef~DX z`aX^Ids5#8rCQHAwq0=F><7PAv3RAl*p0^eDKTWozv9ti8W&0~AkU7z8*D+%FYHvW zB0`I&EQ)^(lK#Lh9JW}DE2~4!S_{+Su2#<+e-++-RWjI&r6c$_hQW>oKgLMAXt2Iy z@UKP<-MboXcMM?Ry2 zoIe4^(%mY$m(3fTQuWPerpyUTCCUghd%lFHV5@?Sg9kEGhJ@RG_&gs{;?|x_^XO}k z&WsVZ|8X?isCn4$am<2AKM~KdCW)3aCfP_O-Vy1HhQCib0sVbuBc$CRa6|ep!vuwu zkV-YjS`4OhV|r+s(Bnsye){X0WwBneCrq6dwIYH!PD0xipW+4UC(NWV#{0p$7n}k% zLMKm@-#9B z8)PbZC}%tHuOcBUiYIXXAN~MW(JPS6GCrJ&Gff|?if>Ybb~I6ASpB( zYDyb|oa&TL3=>q))Akcz*_X3qVUG3vowfV}i+=NpuE&uWXLo5RE@mhnMf^D7!X@*s?uC`S_baRM7%lucXy( zj(TBkOnoV^)Fri!hrdp&FVKKz;ZF}}6I>|jJkogXG`?SU>Z!a8LVqkMhC_mR(J za&-D7n4#+BR;ZabEw3*IKh5NR9B=y0;+h8GInG|>x6}VEkz5;;R@pF<4AU&j**;WC z7tws=Zf*_Iug(wHj@U(+&iqU}z*GKbr^opKgv}I8(&*%1~ zS0iE}bp^0oa)ZYdm?x(Gcsq<=eDGunk!8tk1ZS^q=a`~~&T0e-=Lv$OWxiN{pnYLo zF?xJ9uG;m+*mRPiV9RB<-k9w^f%q`c$i&ZnafJ%ea^7EL1Jzsc8DoeHcNzX*3s`=< zkOm0Z^sP2v@v}WeAq<{D{wxjmA4;T!kjNwfO~g7J8xmi8e>1{KfrG=I+vq~sJ0IEk z3OoAErUhvmvKp|5uIgzpv%BBYm8clqhH=lAG};J*N+f3Vwk{S@)_@m(-ISaq8m*LX z$ZrL|S~I?!j;Grsnm229^b%IeS6*7iUR}f=!wBQqLz$l|cUEl`kduK_svgh&fbO3c zSkmG)Hf73RB%ql*F3cuuUpExUozZ8{irrL97F>I^5k+1l2DgmbRE_9%i_o^LLQ}vO z)6)|d!#AX&6I9%aloLabr8TOYofg#d37PZ)*8ui!7CvXMN&ihKr1PAA@0Py8lDv(W zbNhnZo*eT#8nwjc=uuimbxK03^y=w?t^9Y|l?yxuQad$qxLubP>b1YBp!S<5%ikXu z`CQd7N(4iA%LEM{npZeeV9DPDX!;Z!Xmm%a*)*!Se+DU5eRlX&A&`BV9F;^xV96-i z$zFdtIfpI+f`fB3Pap73VR=n5cXJIK_fz{#R4#9bxrZeve|r&Qa^Cz;CLg|VKY!lz zEl+IOkHN7ll4;=2*;l00-eFx)vwrOPfh%oQdEg8mb9SWSU_s76L8>Z|-nOJkNRsV* zkl!9zUd@1>X1Y~9ZCGaU>P)(6E+!|i0aEUa*@)01Cqk+sr0Kim3INve5H@>WYcKV1 z$NOiQ{uO+nWxA?6p+sj{s7sf5V!A7SF2MH#^*KpiZg00ZCFMduw<{P-6vG8FSL=}B>$Zz<omOV8{2lr3s?FMs#ebKvR#4a7Y9Ve6_vfmc+SlkaFg2B?)xJ2?zB~D zj1F^R?t)EIJ^U7^g|DBlhIC3&B8&JGQ{7b+2&>8?v@Ms=gZsLoiW;cIE^}0(>0bg$ zH5Wqh>6VSBs4q00;erx>Th5$OVwj)_izOUW*qc6P1#F|3y{o0GJ)R)_K@8?T0pZpC zvg$@GKH&RaC(Zu2$VI|mi*;_f?psq`ns3v&4_Vbsr9O{iL15iri$1U=WCk!_5!r9Y zITUdU2*eDh1|s)$D#B-S^gs5n^B!qUx0u*quJuRwlMa?kMG0>IR^YRzoR|(d)hb66 zw5*hpm0QkUKlZLc=P`OTUE4W6Q>w4BHL16ul$+zIU2{22&6yL^BdV*FM@u(4%DO{4 z%#9JXaa3t35MU_FrME~*;Vld28^D9I8r^1vXRMG%BGCG!h%a*&iPHg@1SY>D^qH38 zj3cp|&6G;%_$9`Xoe%$%t1U;adj`h zH^W6Od8lFa1|>Y5x4ykU+<5#+EQL;S3w{Z_1cnYxwNWqP#G!x#j5LJZ>b)Y}^u&b6 zzgwSiUCX>i0Ur)pv2BPH-pG*q;}h3oI3Ii9DgIo~2EbUJqAJ z7nsC|?p+-I&&eM@9`4yhUYW#K3W!}A7}}o58`_3-{|@Z_plA&&?!&hh_0ig&=khX7&tA8Wo0kfA{aB6@dAPLhjRcTQhN|DGc4dAFrIQI(caZk_Q(n z)}Qxs4su%7!HVG%1?mGcz%#9xAwbK64~n`U91cveBVccxoEaVSm)ggr z)5~6&eEi{7bDcSgcX^xUVLBh-;i(A=zolG^Ogmm_F4{aAIVz11g)8Na1`akkW-pc9 zW5Y@Sir}?YWH}w;GtV!lB|QLJ7Y}3~nBp`6`4x&ORNB<#`$!|hWzsvZJ7*RLYnfV> zRPt_kUseZ9%=_UDU;H#-^@r4H6f6Ji&|v#LGggr~GIDZ;+~3fe7Hl?OyAoLH=Q2fP zL()x3B)&r!$-E^?4Z!*LP7PE99YoPo_1QnPlZw}$MWML-OzCO;RvGjhsW>mQv~~k< zX7OkX$+*K6m0VNsO%ve@jH|LkbKl&hzLsV5LBLc+9|?tMINMEWA z%sqwb4SF0Pv6GWT9fJ)`b>Y@VEu5FX%?@){(+j-LVE-r9n0pU2d_pXRh-E?o**D)H^K2mnB+KsCS!44R0}x)D&n3&jHuQh51Bkip1c) z2!bpt<&3cX`J_`95tokeTA|jgmnw63H@T;`+O;FS=0_I8SmQO~v6Ru)d5x<&sxsAr z*M@G))Q-6sk6mUAo7YSqZkLyt%Uk6x6=s|0IiUp@yQx0f74LH! zF)Wc2P=Fn3v^z~f-e-gi>}!6Ml=;G^)6nXFlQ^U42&@IkF$ZRDzVhYB^#WU9(l>pu z)2%RT``Yn{O9Gi}2aFuM6rjP#?tvqJ;vA3`Lt~Ka3RO2cOk8R5&%&DvPjrHv)N=>? z!&;5Os;VIGN{%;uvmyK<+_XI&di!4H^fg*dDhewum9kQO9-b{OEOq7j;lA@F85c>1 zYlo=VU8ECof3fu#z#n$jAfuFn^DAN&-0l`*atuU*cw2(M$cNyopOo&%BnUN(iDNEIA>LJ0mncX~?vgmPf$ zey$V$B;&o;&^H14fK6(j0VWnH0Gjn8xjQvF1qVUO0$R#c9fI0^%(yj2*{ilg8;M_c zN6g)1`2vPex#I!g$q)tK$hBslx0bzrUQY!IJR_An|3B*PGOCR*;1_%;6fIUL?ocSj z-Q7!(mKJx4yL%|b9ZHK!akt{`S|GSfu>=ngAV5g6yzhJW>|Hy1_sj0NpJp;AIXRgR znR%Xh{=dIaSM_@3I%FK8z|L{&rk+n*Mn5_H^)bPczj*g+D&a@Oi7oaHDMs>Mi6RE= zL+#AxQ3dI=R*66exBwOsufZ!Ze@T==WLkZm|IjE{*0=TZ*zwr*mA^EyyPNLtHekaP zNN5hl)P5euLG-Lv^lI2CI;@1~zCGk5$rm))`x?1%U&FT?C>&{azyp$CnmOX=0|rq{ znjT6%_%ccTJ?*_5Rn51$z2sPGyVqFHPH-u@l=;tW=dOqLzvutChyHB3RGNqU{|0oI z!~4!l@omQw{u-TdP@Pk{AT-@gxJ5xw=50rK25wPY;*NYsuzb3>SBRf~FodZ{bgsm$ z4)fNe1v-!aNq3mWy+v7Fkt;9pnvU6exJ}zlgAnErYd;M7qE?k4n-Hu_b3^=EAk+nyn%KB|4RZob~ zdxCxZ|FHJnbEr*?H-J3cp5(o!m#4_&?jtd7t@=+teg?{U)R+Dy59=6U$m z=G~W(;l;yj$LWyx=jh76p)I_1KQx2oI(1OTyL+FE)&1Z8Pn?aiUh(f9&W24KV{gt- z@A(FI-i$^CQ)>U%PV`-VNo<`i2y2s~hu~O8V}HV9&Rd(RNaKP>zKW4|@$n9Ide2Q_ zBrAb@!-H>Mpia@+w__tn9C|c;oVg0pB#Ken%xO1WinP_?kW*|P-uZltW}SMk|4E%S z^e8<1_y^X*&~=+KiJWS$pX29hIeA-60cJfZkAeV24FdMYx(K81% za*moP)D6v9Q-)r~HO#R?GtxYN5Pgipb^w05>+KN1_4_=(MRna zFv?$48!bOcQNWal9&P7I3{jckT=vP)J)P*2$9#C#eYK$$$KCKolNzj$chMtl7brS2MHo3~Tyo+Xp zC7((96PW68op@5gqmLLbd_v28%u{etSt$|y71vc@zX1utWkb?753EK`LEw=)!GX4% z?pbJ6Hs*hvOMzWQ2$cp4cdY6?sG8Zg*L}VbBL9d%`7Y-$I;0mF@YwHo6z4hIZIU9( zU_pDui+Ne^loZSHIV^S;*wq1^SieO$DQ>Q+r19PJ3CvKy;5}^854UlpN)TA z^2vJ!IiT~82ddIr(mK_AgNkXbuOBOzj> zoKgV9+$=U+o?1)RIT{-t_VE^aa^s@r%I9oaH-`tEhusodX#Am;CijGSAC^cZF^)c=(XhS$e4Z8ycj=y5xS zR4{%dJ*_H`R4~Tsv*@lTUwjTpKWKa=$JAHNLrVfRnriMZqV|{T?W`SA6U5MrCCJdW zD$UNZ5V38hYp@;M@mis2soBv!%8K?@AUgWJWY4+K7WQ1^7uhF$aRIJvsP|dpembCS*56Uyp*zpN6gNLTCa`jIkv!UHw*MFHZc;2zvn4I| zuypv%CwtTbuSt7==QAgV8G3hF>jok{76otGxRRVKn%E(dk$HEaeG!9I^RcTa0n)FS z7X+nJp$-z-ooBN7p#F;eC)?KvlG?9Q_cF5{W=G7yCE39ySE20M z(UUl+$`BbBlaLv5@IrU;?yCiS#;Rk%A1jX+az+^V5u=+qe?K2zfOA}1h+!RaEZ5j`8QRrc$kwYSWRAC;b9*4Y zL>*hAo~0GMup>4h!wTc3l$E((enTBkr3O3l7L}ed=mUOVG*iXEvLg5`&twLCQ~0i5-4kph_?~JhdWx3mozoY-!EO#9FsXOs}|m ze9)|ZISqZdQk|6j5g((WYgtOV_YR2_w>DsIJWhU0b75qyAv^VJU$&EQ6qN<38%Q1~ zA;n3~jUXp2Ax?`${;U*w1>tNQP`6Xo7 zkmw#Amt$s^F%1901qkh@Fh%1eoFYWey);!ESmWuIHQS+1{vfvCQ&#_?p`jn=<`+9|4A{c zYWU;p+FKqhrVEqffkG+xDtZ5mWCG)e_r@u3s<&9aCjMj)`l#7IICf1(sFOF3PuN(V zE0Y>E{z*1z&PwZoS9x`i;x*k!`7N*S+N51RM%c9BSpqfT^0RQOUe?mv37OYI4S^@q zaUE+Yrk06EE2n-LU&kmon7(8R7uj$YdRu@Q19U9X$};A>V^G0{Jsh2^JmBKYO;y~yJxbP*%owgRV1 z*oQ&(7sUUQM&C*~4#gLt(EY;371T$+tXD1Zl>yMobEDdMijy0Vi9cBA7K0a23xwU} zH3y7I->cMQK8-Q%u^zIUg|Zgg9%F>22DYoWB)T`X6f|&DW8T`0wydG^p5N`VtoMz1 zImUm0g{3$*uLkyy8O_;sn(sel1t2wO3-|XP2}mu#8477Jc?PK&aXr!l1bJR#fjqf& z)a7&o+bUCSvhV>tU#_6H2)NDZda!^x{ZnNt1sq2j6jA_CrmpL3bs`L?8vP#QN%THN z{R87<$>{uq_hdp(&-L15EW!Hf;0iU}NbLph?O?O5(PEx@pp%oSOt0alRikbareqIm z-j?y%DeXUp?BMmf(y7}Ki7DJIdzUNCf<-6ie_o*NlqTD$gl_&;)86)~<+|8Rn63zk zUV@&U z=keTB4J=20$+8taXlAlq<`A#or*NJZo1l_t^tkj z6RtE*tYH_^aW&TGVZKOrfDL`%)M-M82ehZ#CaYfLa(07^eyaQ5UiTB<6~?`eM$gl7 z{-<#pDEtV}-GMbmA^vky^9X2pira>)KlC5~_waw|H*gW)KUh_d22$lzXnhG{`vo9V zbpc;Rc!R2qZKo?wChNjeTXk#!@Vk|sY2%yD=UYp@Pxt7)nMJV>ewAO_)(!*uNbYYb z2LH+)j3#Gmkw_cc5EM<$)k^Ev&LDbE=y4AcG<++R4u6>2#*nOMn+H5!UTMuRmKMY*>Edc!LcNa4mP3X{IJ>-qAJU1^bA%`%r`K+`<2JJ>kT7><8`72^|J$7gM#!ec?s z*kSn@Wyu6XWP;`X&c9{>r#qrPVN>GH;_}K>20WaFh(2&l<}1f&3y9ISo1xr+!AtVn z(#zjDd`6Rc1K-n)i~Q%Q_&<)jO`ZsI)m8*0>U9ilMdHkZn1y9L@u$7aj>ZQ|>d0@p zueFNS2pBO>zpX1DpCciV#C~(^pI)u-9*wMDmCk%tNsyetbFsY3KI2=*;qi>~cy#F{ z4J^0~p>0=`;Q1{@srW~h?xV#ZP%-5V4lDO9tJCAi?2Y+kFo{HFOdyqt)DeDA-4u3d zEw$JO$I6tUE}sM)rSY7GBwojsH%Vg60A*G>HfdIp`x(8J?1^vIQIlgI;z}2*9SF$Kf6m8q%C5z zFQ3`sx{xCzD%fW%f3V|@mTG2_f|ozt#i+kq7`9Q)e8;QL*My_8PNpQ zD{}b6eP~VM>4WGFH9>Nm{GlnO-0G!+yk7XN0_U0G!t5I)73^rxCr|-=4if}7r4YL<4Ix*Q$Q~1DEOR4(mukjMP1K+leXc_J3L!|+afsiC)sA$(DF-y@C}2%Xb`^bRx&SX zT(EEsZU& z(h>T;=djWFdQ`=F8Upvi^;S3_juU^=@NJ6={#0cPzWN2NPE@OVC?ybV8v^8rAB+bIw2B0x@I`9si!M)LAfIdU^IvulOTOeDt(= zT;*L-apQTJPN%n3T!ZT$8s-)+EGydm=1C|!+v`!=EyyQXec98yBzR+|J%&HV8?La* zPU&+rA*O*WjUz3!2NFxF`qaJyP5R@g-IABQKTWaJB~9_B35J9er4Gx6bmY_aM>S<~ z&xXn<(EE)Db~4rHb6SVGIUV??fF)lkcDGFJa2^in4nqTfC!Jfw;0=QxR_1?Uu>upt zVcs9fhxiy2X43-uC0;m$#n^**P7>REOhssF4u z=2eNtkLhjwGIP&@=z-q{=S!?O+m`BJ?>mK@$3dKgn! zVPDN(QZ@I_J1(xrcQR0gF<%E#?OJiQF&OBRap%lH@#WK<3k$g+lniTTKiQ^V1S{{6%G+E1Nu+ zRb1IZVB4LPrM3Wk+xUJJdCLC?9=pp1hOR$cR+5n2HOg-30ckRi( z#!Zu3w^&^k5jC#pLyb@ptWe9VabC;0BShX1+)72eVLl9BlEQE=%q|}}R{eX$$%BSn zB`jZhHIDB-A|I^YYV={Q2yK%;r7k93x3tm;aaIeYuAoq zhK-~OnHJ=`MELx%{JQCYdB|1(7b<`!>`=ivpE#H6=P=Fg=7Gr#=F57tH5DOU@BLcG zR+hj8p*o{>A76gy#2bIBiAV=0MMo)bsaLQd+Jv@uSNHA9*#qQ=c=6Gi1ULZXPSVB& zKzW_%1Q9+&He`NxIZb6X*k8oicLjMq`nnN5K3cgY(e2Ply?`AuoX>Kcn_-{N_L9Pk z0R9S)Xj?(mf1XF45UX47uk^vyjab+Djfbr|x9xjD7SwGJ;bL*u1eb`kcm8Lukw*C^ zpWW|qe1ZjZ#Jpc;@oPp|U@4iq4ZJ;~{5@a$w*xn&+yBo_Qi`~1(2ovVkuol$KiT%( zeSd=4>L2yXFtEJd*VpI>Lkq^`QH@J;r$hQYer zxqOSQz6HV9ILEHUuPWGZyJBL0#71?3cjT15amb`Y?J_XjjF%FSzugFQ5X&d_=UE;v zfn1Viw*kLuvEm^r7rIDPKSx-YXqs?@ED6en-81khJ}eADHGm=DSL6z}+P3$nDttFj z&3t((B7dCg?(iNr&2D9f8|%vg7;ZWxlUuH3BQIo+38AuUBvQ$@$DyXRSaYU1Sp0yW zSaWpta%b#@+7jh2n)SHuX8KhqQ-=iVdHV{k0Bs!$j;-uDNk&mZt=jcEAW&&t-R^pfdCja z;n~dkS(FdO2txQQ#R=XmNJ?yG(p#Qh8!GdkYx8)s@!M2o^f+`F&kxIJ&;N(tZuq0y z+Lc%|#fZUCU8yzA;&aXOsLJ*ki;q0)ZiaaZIb2{OJuA*f2|Hd-P0ZhT)PeapGbf8V zJ2?d-yqUL5yf)qXX9o|JV-{?W-bQ> zocDd>P#w`s`rQ){o_;{Q0Nx>b02#|FKNM~Ghrd@yW-zQ+TFw}-qa@#y^sLUwziy?{|` z?IOW4gclPC$8!-=ZWvqkMm`M)xz7M&d-}S8HW`1PjeMETZP-T06v81BzNoNKN462N z&LIQc-UZzJf}0V+Wa_|(OPzKZ?mSpF*Cx5A({3<|e{1g`5F@Zjvugwnl12k2fcNsV z!F9&API-QmS^^&$3T-vW5QA{nM*+{?Qi}sh-e@fJf0wUqd~0F^dh3HWh6REekOeDd zTBq#V)uBd?Oc+^qhD(aeAiEU$<%EL=k*0R!nOKb{!_}^I$db3KUNtDgYI$!}P1(Kj zE0ahe_`bI96Z)_gtoObVP!Jl6U>z2KYfRCHoEU_3K@3pPd5KG4m2b}4;)>@Kr^JrF z8vDL7*_l2`rBswq0dE?5|CC$pE6?pQ*IdLF{a zA%p|uM}+atA?Bx7SR*@z=3W1JFt0!GdB_w!i*-oy=`~g$7-Kis^LZWe-@$#@zSu*U z>ls(m71r?@efa|t#=0ydCuK~spcir>a2FPG@`$#wJM#*zJ;Hbw_SMQvrC4eU1>Zv~ z2QIbeOlzLOFHTgD7Z=H2Ie$-o?IwQ%iyje+W$TK3yDOO}wvf2GgnUKY(5slym&wS( ztq!3ApPUDDo6;CE%4(jnxoC;Xf6j@y^rP_B2ENyIJ}DOpt(u`oEE=W@C||f8wB)%u z3gGdG5t?89BdnV4-&5lOQK+Y2%Z+ber-vtMZsM^npB*dRTF~!;DVC>kDRm&WM{Ug5;>)&Xit{dN z^~O)}WG8chYDdyM>X!+MLBl=RO7Tw7DGl)-jZX#IT#TabsQ%tLSjuR#+@hPbAQ)~* zb6w8aJEE7XGfl}FIJ&plg6#q@ygr&?3ARhWrm70~*xOcLHQK1IE7kM05ekL!W0L&E z6~bnG&k$>OdX=EBh)o+`@K7%j**UE@WQqB3aOuvh;ylI{v|@w+VE<;bNH>Bjc%{J= z!YwkQsbtUQItMJQGQ0vl&g%L_TS_vr4M8%(`BWPV&khyh2=RrvAVTf`PBQ=P{~g|5 zc4W^w4f}`j{Np*?O3$}q@c2q;u}73lzXtgtCz8+b+E!xZ<5<$l;H+GZLz0ISnSOk% zlz5BB)3QtBQ;uitJ$R!^>kmtL7)H)APP={`BbR1l_j_^TjXaDHpe^{BnNN^K<6r1; zb-+thIuNLb#e-t1A2wC!=2DshV1y& zk&I{AXmLwR8^RnGgs)eO&hL}0Ab-NU%lS^duV5jrR$Q+j7qx4Vooh?2Tkep3NE_H$ zCYr|J2?%qSFxe@l6bKz%eV&xwUdmJBdsjabrAQC$Q4cn;o5J(S@eGYV5UX0^VfcNq zdLYae1Z@p}4=;8ZZ6rV)Tyk!mU^u%6h#!9dr*Lfz=9~re>Qoc24uBkJv5V{aEgPg~ zdeD~VyDM5xYq^3~nxjs#x#4tA;T-26$J z%z2q2@R3^Il4kgZ5`vQ$N8qtRFu5xKw~xM@_)EWIpTo8pN8x6(JiZu9T0p(7hpbli?0U$+^6ri#kt77d13{fY0CAGxz#7j3h9 z*$9V25#nr3f146)y`C#d5=_M;tn>x}?GD)2?bpAtQRjZ%C-kK@`H=ww_ zy{#N@YCTL}!t6ZuDc@JfA83T<)^u`Xgv_Q z@Vb3R^QLuh)!a`YlYskDi?Np`G=JJ=Gj4=5sxC5h*8KYmTe~%9m`D{LwQ`4$GwD$!^Yi2heg6{0Qt)EKcm8yl=yL@T1{RqBDhUw>%EByelXH)%5Q?O zd*AEsoNf84kc$@VI3H>mk|uGhTUX&dw$B%w)dhF-m*szu;Cehhm;EG_~cuVOQtoAH#Jz^n*5W+ymJ=_{ANqsJa)XZ#J`S_B_HBDj&phAD)^` z3b3E`|F4ccDUx7eG}KQ+QRH*4?_Fi{j3xz2;s3*uXwsOL<4Vs`{-JH!kBXIqb3 zn3OS4@-2BEF#%8y*Q4(Za#p#sYAWNtiN%8coSAa%?yS6}!&$xDx zhapr}-s{B@V&gFe;DH!gd?8-}x6flU9?|dnhBrC8Io^tN@Ql!FL;oNnk^TDHLXyaF z`>~kR@A1!hh{Uuycg3!ifEI8maNt_(`*ZhsaAY5Jzcnu_E!8a{{XV!OZiLIl=|56( zIY_ujSk#654Im?&*)I-%%c!mv%c5{8DorNyp&$v%miOabY{>l^Sy=>WVV*edvpY)6 zhfMAlk;Vy5OFYm(rklW?pdn|P;Dp2DqOlP59!>M>07?})3#R1nj5lB7#8^J(pWVg+ zP%UF{^0|FWqAdaycGt)|aeMr7!^PkbaU3k2DZSwwtRcMTS~qapv42z;&d|rjcL`xl zbtfDf$mbu-mYeV&F@9~a`<%Lfe2EU%n&PvQhNTrc?d-5Yy|5GALZa1A3J~~? z*E3+f;qni&=K_xn_w zil*GIB-Pm##pKm}r6d*_QWX)_D|#QeXEY_{AZ3E-*l(FsK3o#mIX;Sb90&dw#r4+K zuibRxF65uf3pZoxk5e)-OQ~j>UMXfIlhCmvETIe0marfsNybYonx` zYE8ky53AdW6(GHiaK9Q*9GmJRrz1A7VO+!qk`bHRjYa%4rR|=b zPUPbFM7$bxNQ`vQ@M?}N^pcex-IOW}de+v^?GCR|DQjIz{H@QqjAmhKY$^b}=?w{d z<!twD&|lU52M);1L3>4^~lfrUQwhFC_*B67`~JKSj|(LeM2%9`VVK4G`S! zz48BAJG{U%5-BMt-0(-~X&yonw&Hic;^z?acO+69mF)eEVuJ;Aj|Y7$v1WeV77A}u z1`7Uj6=# zYUbiVa`m$(^4@3ij@#x*s{a>)E)YFBQGH-N`CDb#_NV2DWQb`@W^rT`K%IZ`0^Ir{ zInQ2o_4x~%6^jguCu9B&5ck9)Q{HxEeC!<($dJoRpac-vv_(*UPRPV1_`@5PM=xOW zVx|A3D271aKz#LJyj~RLeQziw&aakPkC~B|l0&8Jyn9mNl%L`#A@|PDD)^Xx;cJ^K z7iX;Au%B8g>u0R)-E-MkO4$^@64>|WD+0t=ikHVzR)7p%LS!!zO!=&x-Ze+IX&=yx zRzM1BMw9^&^t>Axm+c+!5z!Y3(?QHlQq`kxFBh3;%dCi>(%ms$Vw}H7oJrg|X?{+0 zcYBz=OFy`}>9RW4>R%W6EVZ$8v8LC%e1}!NZ9Zb;Bo6vda8a@|c6u#7q?~Ty!ZLPS zFyg2C#$-@DPZ`N^(&OKu-pm%v9s0F03Qa^@!D)Y`xRU=v?RagT(jP(^o;Pb>L`8u?3y*RrOE7y>AGyw;#?qC(`?I_>*Dv~^>(C}58p+0 zQL&HoI-&&dN1uh6M!3PgQLL%{1c&QD>g|F@F{qQyR~F4i-P&Fb&2s!>Pc6W??pH3# zqG)-kvucwo|5M%3|20^cQ*t25;3M{SqWv8#?V~X_ zSV>IvZ^|N|td-14)^$7aF#D^j?Q&RJzMVu=O=~ZsQL6-giiw5Ki`8Ggt`c}%x(7PV z&p<%6A=j@Pzm6ylyPq{bW+F0YToJQ0<`JD2g(9>AmEsz`Z&Atjxv-_eqpGDBPZzTQ zKk?7=%xV56h}BImzd7R_XZYZe^OchOoJLjV)ZPYpEqH42-$CIGnaChs#E;oYtv@aA z+Q*Jvf6NS*xA(meUVu$f?Y{VSBoxm6z*WOYq%f9j7>G7tilBPlD5MCVS$J5vf0>|F zBM5RAXS-e_v{bzv$TnTnxk)eRI3`?(Cnia38P>JM4(T()*uAnyb zy+ICBivY|)_iwE3(;*mrZJ`%5KmY0g_KV+w4?J93jT6jj3rL0;9Wf{|VmXMfUh4T= zVA|*tkg6)?myNIyI)j^B8KbodUixtPE)%WBz zM+}lh_fT$7W~HOF1m#u@gA3@4(6x*t;&8uo^*!Hq4nbqHMT)V8t7!|FLxFwI&0?@k zjEsYHA6zMn!_l(z5M>xf9JUTR0>`35u?usLfaJD5v#}twD)(` zR!%b#w`Z}!=8}5GowS6*_qTp_IY|~ti7xXVFT398Rhz!U@@e1T0sDv4(aX|z@ zCk?7+?207adOFvgai6kV)`?eN|JP6S>2T~`CL;qX$BMj=z5z68Ef)GcWrx|dcVsZ{ z4c8q95aNEv zT=2AZzw!7D`fEh>K#nvQK4zUVl-N9nFnuI+YO(|Q9q!uHs$qYA3UW&YXOPeVO*`$gdI@M$9FJYordk0eCL;8!AQ=*<=e1KhV3fr!;zdgWhm{E4f2Jq|< zG)e--;s9Yaf}L8y&P*iKH1L^jEgI{$6&*cqyZH9QS8|I|$$ z{ws@n?P=zn?R1$$o%F~gr!cRE{P!Fl1DWcmqN=r#XnsHJ2(wld&Euw*$jKYMh$!xj zY%CjT<-S4(+O)x{t+o_${hpC?3PnCi_)$nE$MuLEs#pqDbOGb&K{2>mfyjRUfhkEf zT$%p13ldpMFyOiV&s6svw)zRVkLO>~poPZg=_mdvpQrP0Zbd}5=jMad#aT7rX&6y0 zt~lJGw_N^74`pZ(nIYnQ$i0SJ`XWi?_rc^Kq3`Rs&P?wo^plvX6(;m* zK_>U~q0Hhq^(rUi0a(j8v8Ce}9gwyzgi$H9FH8S=p&_p&>0P71U#q+`ds*66TD^Gx zma>%e6FwlU^diGf#&b5^lFMx+df`sBb5>2-{Xgjq@pw zWXsC4&~j1^kpThX=sxsFv1MeF0EO5@Nka<(-0wXH29>jqZWLC{2q$AEAsIA>z8^e# zciPqWvEAQf0c^En-=Fbh(%9I23O)rJmr9gyqR*4$ z8Pnvfl5G-ONz+wxZDAAczI%^jqN$cSYJAgURA7}LjZW!N`IABS5@3V;iQdD{%HZd4 z=@OQCqG|A*tv7>!w2IO(+PL>`fXp7zwt$t_w$?M9-25YGuuSOKHa_Qs+^^}R3Gv>U z#Li2Hk7B0IDhjbB`mW$cD4Udq4u1p}31lpD?kCIgPnz8~B-%CGIZrTrA%DnT*d-?& z!`oJzKh07c%u1OcETLZ{v?mqYuAhCF-P zXuL)8Q>O^MIE|&BP*z-1R_qimyrh>eP-Pz3XQU>6(ip3Djn$q>#(#PwzZ_c)@+!7Jm2FPxi9M4)@mT@);KBj(^9Bdz2+sm+ze|T)sO_&J`~%)a=q>t1V|{>Vf9?4|{?}G#B(yFXLt8 zqy$a`(g2ZvfTWNvdb~kOCRaSSzMD>ShzM=lVM1`mTHIRD0Zj(nNfsOoq<1`f_L94~ zSM}|9xmYZ&xWh*W-upu^(F_`D`lVQK1uDkJ99dhtxBQ7H_Wiv1a znre!&>UHOri9&3RBK@rZSH#y3P{3Z7?|_W(1L7WzRCDFkWX*{D%kV0vIQXcy7ryY< z)1(`jE20TT!003HUFh?AM1Y?|(xl)ChfPrM#`HEj+O4f5;%TAMoALn3wd}-&+rULX zzhihsS`|f-u$se2QSQ*!t6a01)U#%&5txc^d>*!Kj09)g$TTmB>48#Y- zrUUHEecHM0TJN6cD2mfsLfjhgP==E@1W{yhOe?e2Q7|w8Y7oX`DktJIwIq7WXg;)P zN?&MQmP2)EDP8R$~mfn6>AX3$d-g9VlRyX zmj8ohAEPqAt<}((H#Jdd6zJ8z_V&{^>T4DM>vHE@x|!)mT}53=31&J|?L; zCHZ$CU4W2o=$0O@l>P;((OYISIM%t5L^EyIdJPRfy=C9}57NG*9goY&D0ugFXDoJ=>&y(EL-Pwwv*}LHtYJ`OHj&HG6;MX!s~c0xvk6Jk%tiM z>j>`lg}v*Inl7l!?>`HlHWWBE(?TpsxwvQ+c4{JnyjBlBcni|7*7SQV1}&0yL92 zmaaTJZxMLNVKRGoY&xa3;hg2uGnZQDd#%15L?+C`(;uCWZ(B#U zX>fy#Iz#<|R{~Nuu{MxFu`;b%J$cm<`bnb?$Bwp7;d1F0(A+pT4F4Qu39-8*|;m)fa+$ux;)4U_u;uH4!dczn1C zzlHS7bixn!6%i$@YF;5q%t5||%E#B0Q14)mSP_(xUN97fhRZ~QYYGhE7V0Y*D2fJzg0`z-4&2??v zAkqo;?;gXR8mQrc&47OYm7`2woj){ns=b}1P?%j{neW3JU=1~2!M5>*TQ46<@RTdk zfi|SysJ9nc*i?BN+Pe-an1{4wP_T_N&HzrgIv1t7%64gsIcTjaKut?m_H?f81nj)cvd_Q17i=NGx^4_7{-&U`uNVaGS-i=R_Ll4mM6 zrVl=K*G>2BCJkB+ZX4afK}k)L|B0}tjWCW*pXy4nM3@I{Iw-@kJ3(q?;j^)PxP){? z7qjkTe41>HvromTEDpEdZr)eHLT&_R5e_|l&AqK~rcE}R27f&b%5(9!m{m4m&tUes zAR{Vte`8s!?ZIhsq}(XcX2>w?yL>^DtSeb!TuvZ%p(t?PYb_&0Ex_uGu-}rBeNjO& z>@Tv6$t*CeS2x5r9`*HcdP1aaYuC)e(|cPd_xt;Y9;4xWYUq5@nQ8B=NXxf=3)ppB z!wc&C1!IHaAaT4Y!>}@x17~EL4;TMIfhD$RpUtMrW0@0=7I|+=7J85{cB(;ES@6f| z&HHQ6^!_x|xs6&CqH`6UJqoBB*bTiA_UY&h%d zMJFN+(_E+TMD$#KJQBNqkzblKgDM7Z_H3J9MsJ%poQUWzJYbSV!7<4Qt2g6DA2B;0 zhYbz3R(vDT^@MH@&cG4;5^F*$)fXjSx_vE1l{vc3hm~60=I@`zg(3mYfAhu}!2;G0 zDuL(MoguxRX$srbpah(nsBi*U#~U7w}bO`GS4{A zqSE;O@h-bJ-zf+quLC5W zo6p?u7c0Zf`FQ!}`3K2Z8JE2zP6G^Wh9^rqIznb(?|I0^4sZv8eL0Hz$cGnVZr?p< z&gT7{a&|NH`3)Uhl^GcT2aiHF$X@abK>9& zK`RX;ywCjp(2ak&5FGWm=|Zcp$F=-Go0Ow~50m?EKJqgwb{O9}j4ACQxa6g}_lE7R zX|-p1kqj~PN3U-U^dD)P$hI1cHhkUJ4NfrH0{Jb=cGDB~wR*)jn!Vrd=#oZVs3Yku zr&kMD8-37S>j`b2=Ex1390=|KYirk3c8CP!%UER&>q~&u!o>`DPL3&F==#ivGJBV2w;ywlbXz3_@OOutf zXeaH>Q+A&Nk`SL#p?EJu&tx>EvR{;?by>t|FMZ9KMfk;DI{3fdAw0!~j@bl4|3H>S zNLzWITywt-<68KaXydEkEW|p+5rFq!thMr=z~1!^4zL1jy&UNFwwW8K zMn9x%m~pw>0@-9FF4-PBPasKyY&v1-fTi7^!eA#o5CAa8mQk0Oa1oZw#8TU zN5Tj7%;2Udm%;O6>kf5N=z2h=5^VpKLI7sXx{<`j{_wfw?6sIAHB@`^%adILapZ{* z>l9VSXitV63HfPU_U}p-!Q<7BUt{u4``28mCn){=xvWAS~51%y8Jep9`nZ+&@NH9 zMPJd+S)r7rvY$Xv(Vsa3Fgym;)3CX3Gazf_)SH&4V9>2k!-g+E|GJ#0YkMr1iJ29L z1=$$liu~pHYwRS$n+43c7Pg1N-|bVonkEQG#;I#>vLnamWQlr>R#ZAJMrmN}-0iv( zS85%51rKcu;mCMO*on8}HA;BZ3!-a6jNk&C;KnM2x$97kUbA4*U>*o*XQ(t1^FQ&9 zy;j*UrPPtbu7ye zXlnL7o8NMDKPI;wmZdsM0|mIizt1eq!mOAVCAh-SXZ+1#=N zn2*Y&TG5+RNdH;;roRo3eftHqpBKLQ3;2f&6J+!)(y<2qv(vC87R?OgPBlnRp6xN%u4!;=shchz_d!u$NM(P2z1rJxF42wdA}AZZpdIQxccY-JKes5|x$|}| zRB(*<4-{wCP`v6hXM(e)ch*By>5)8>~C^WZT1 z)5WWUT%?vCDfy3q&o?Jeay9np@B8NYM~#_}kiI5lMaHYBE}EL^ew-efx@wpt?o}Jb z0q@@``8_nBd7jXH8|$W##`0h4rtzgY_>gVUi|p$DI{ZNL1Kz)&zC~}AaAV&`Zm`38 zpD#`-=asQBay_p(g#T|FyV6qjCi$*%q~v3fPiW2~^A5^k43#YpZPj<;Z`DRgbV>Wy z-CwjAhXnT+hiHF#`Oa$Cp!r#98sdfNyJj(sre?7hR@m6de;++h?clim=MB|f$t1Q59++u%{nAQSF)rVkQu7O8*hjA4d zuM^^u+wUf_#oMRb@}W&Cor%{;Ro+g+-t2ME1^$SPzdpT7@gOK(a!vQ(B@~<`Q9cN= zap1dprKX#y5kA|OCZe`2Fb~yEX1yt4me2Y%xHo$E+OGC)DT^U_&?3!I*k)y}C=YBJHfri| zwT?d@qYdLo&>bZ(4VHq$x2I%566b?Xp7^_Q3zO2!_6E3;p09xpd_b`(sqU%u=2E{m zcxgZS<3PH2X^D+dOF^nlhoE7%c`dh80b|`wdL&bSnAD7gmp*ho35wMNkkkD`$zvz? zy-4mONuJIu(^==M8n!xkZ49;t4Fmon^--YV$z}x!_9paVX=$6tp@I>s9Xn%PLikhT zrO1uijWxbk?MXut>_;dPH1Ma5uuUo|xK@`{ZN$*G4ZeOWr9P`|4vJYks~ zXz`p28X03DQ7QtS+eAcF1knCQe!Tr15__y^(t)cPZ6VMs-XTr;R6xkWs|uCPQE|;t z(T1NUVT5eI&dz+_kpd){jw;ioRWX8YA&JhaLO;Y2{v+B|u{FZ1vZUi7;T4Uj-yvSeE)^7;9Yp%d82NinN*M7eaN*59ci zb?9-eexBEkf1q9{RQCZF^u92IE;{)m$9_He+@$rXPQ8I+y@40EO8V2H5u}FC;Dmaa z%FS~kp_0C3)A3nfs@?_lP`~U{TcUEr@aB?;xt+Ljjb zH=1{@zw@oV42k7^!tCYa9eitY@Nd%o=cxrO8S)&}^n{Edn&^gi7BbOrgRCT!FrZrb z2e+!FY>kqbr*1*ujZ=Ow#z!y&-5gzO&&Jp<1znwHDcxDK%8|R4Wj<#3S{j*I;VQ34 zbNgy|DQmvwAocV&iXQ~a=N60K@@m*4>#6!?sGF|#VC_nq&gj-@ScaQQ*z8QZyIDuf zqifnhiU9fSDJ_Nr>#U`65qVI6SxeHRyp%!W;Ge)cF?ntCINi*Wf_t>4%RRiIOyMt&%}xj`#uRfFH;t7XLJ8(hb=lnuQ~! zbhyY5bvd%1XZo2&ys;D(D36M2gno@l2@H&3dlz%b#z2#f{qPHS%Z|vPAFc>pL&;U)SR?KkE_1VBg zZdNyIVRg8ffj)1pa=(0Gd1jlkZ$s9@i(VWot|BLvj?sp7E7wXWJ0;zJ{~#gOB<*#EPQN>MgeYb2_Iy;%kB~KDEg+e>~wQSRTD*^4^;lxaMTBw~7=yiH}+)cnGTl5jqqXL9~(kr~0Rd5iC z8ZGXS{;Afy>pTIuJQfM@W-so@UhdyEpY*z2{OD18Ym;p%n;;Ej4)>R!7J}Z|W2Z4a zpd(zShi4ypwagDTW;msgGL4A_5nRnW8nMHWVXV_B*rFL4j<&H~O6vsh@xPV8SbISr zyK|3a`)%}7pUqgJ-(&R4SWViC&gHcoV>86}KXIA^lNP_g9&Y(0?9|AS{x^<9Le}kW zeo{s8l+4k}RsnvOp9Xi`uyoQNKh1lwSL7; z>0{4{vRmx-gRDB=xiLU9i!~!wvcu~FQgr5THxDJ~b&Z}9e6iy*!YHt!c7v2l;&s6< ztfPWkyyo!i@xA9)RmI)QrL98evuTMVp7GF3(T+%0G0_9xiIirykyUw|XCg|3kzA(Uyz-2meVS2tV==UXv2ESgjj4e)HpRQq`&=rKlww*SE)`D8$rC-mtSu|kDSlE zVYlyOp{}_^?(HAC%YD5EY;OWY?#0E;hJzl=}84M@>)R3v*rN zhCr{*x}%`hKa0e6P<3x!OqG=7b^HaNsQ|V=0i`zuzr!mTy?h42COb_JnubHeo_(ni z{<%AYY*{0sLbo3m4m_pbA3y!+%JK(9=nrD|Avrqd;5aRJa@lWWOsG`4S@`uhdJrRN zWISK`0vSiVr4^?p(JVRF|NawHQ!LFmwnx?(M&|#6HOk(f*ze7Jndzr0`)uYA8f^eA z!|&6kAleM5!ZsV?wGcl}-x@=6uE^GssHP8L`+7hTmJ8LX{)U>R4S>JjUFpNKP-x|E3ifm=7rOq%8>DA%WGs{a$(y%z@U+p%g0#-x>A<`Z z8mIf~xO_To9<<wJ>~1kSU_z1Z-~`<>6?!D0i(nVN4?A!v3}|sl;eeqPxB840SRl!6F5{!X)D4p>SVz{7O6?LNM_x5+7YZgU$?*&p*m=Z znp5*Dj>M`?i#+kou1XHu2Xj7CKC3G>mHAH-pU#wiztRHW6MQ=J??X*|yXVlg=23zL zMsZwt1rMi?C~VV*0Cz7XT8|dXv^3_I-}US@7r`$)7vl_y@5SG)C1+~qZb<#Gu9prq zp`gvAHWbeK!_2?2b0-a(R5>W9+P(_F$|g?B3125aPr zsug4~H*}&sJIVP6zIWX}etIGstWmqSg%Ajj2>YUoFi(sOsQG%{C+7GNHTN73_1W|1 z3v+i!++O>tj~Tijqn5Q3qgF%qqdH|**$MdJ#v&2z9$CI$EcgHj1Ae%UZIBjX{(Wtc z$bzs)>_%Gmga0fJ)yOKg^{-Omuvm_6EfXUHYrmckie(=FcM>nrXQd4Kd`-6#)v}O_ zBhtFRmzv*vD`gPZHvl&8XnLzerHimiH0*R-zpEWZyU4%&oO1e&JRk>)Yxm4uQ%~Mwmy1_g!!D*9qL>R1_qi&Vr1wobTpU{P>Zl8ABNoDdWA?G3tff4-rigI*; zUznf2<|-2$joGaT|Rrt&9L zXCdnGaeJ9ec!PRn`h5K{%zMK+K;*boG(ez@-D0FwyF}pAIhXMcoIM0xW{W1S%Z0-> z0}+BIe7(KZT|~hSutlW&KFU(TcL*b_CQ7K4-!R98@jSXVde=Ec9yjUONn_$2eiUrV zekvgKOCSB?@gb1|;jfeT_oj747Lxh-Tl>fJLp9YFK11M3vyNmP@V30aXrCeAxxXmQ zg@dCKr172-Igm=D++{IJyJqF$jXSt* z ze|h=g*PLGI*pTrt%TubS4d#ajEU8e9-Fa0zYZ}a|`l6(bdQtG>7ymE`iew+(&?--w zIY+ZCx;AX^;PXjW@;6@qtnOxRa%hB?j>*wwpwX!JltX6MVbhYIiZ@ti6@nXZ+KD7v zHD2_az_~nW`0C6Qb}#fBY_}esT^U)Mbsf$>VEf|vrJ-G>#%>3ut!-WMG&uErf13Z& zqF{5$qVZ5r9oDIzv;rVhEPL0noGz*Xj{r+eTOor^Ewl@-Ha2eb8V`TBQG*uM1tFs( zdxL3YuN`Px#)^%}pl&s=A9hpbhhoIxkimxoR_NNzXy8(}7w45*lh?Xg3$XQAsTA73 zT<8A?Mu1pnU{|bPF~0HH2cyo)M)w^rKh|86{9Iu{3-4?iNKU%R1Giv3#fSNe;ckbl zZh7S_<3JsXCR{Ss|3T?TpUehrtiz8^1c~1H+l${4I7AZYWQhj>o>aN1=eaQ}+bWV5{oQfU-pM_5rhfN+Lo>NsFLd!NP z-4`i1t`416?|Mfy?ksjp3!!}$vgMoH9J?#W%kaUPDv0XK*O99hBo0#67{lTLcY*#=qO^4io)5`~t&%Tj_xaF?`JLgRS2rTZ zKyBP0Lt2tc!T9qt`b;Lo){nM~bwReZ>62RLGUrZ~PTXJRb3L4aUKv3=q=~1((SzTj z6V;^NTvlb%hw0$S#3vKrd+fBz=}_a|=&u|dv}Z@IJn{;49jNxpzmfB)X$jtgOk_Os z*D0+k$$q=!eR zVog5DfXBupssYNsQ-J?hZ0{fBp5);_kb6epe?{);|7YaB@$o*(O<9>r#}>WX^*B;H zN^-+j6e0=%Y>Rw}fjZ<8)Eveq?f=2^oMJJ;NGG)C-|Sa>l|;z*y0~I8O)BA?{RVfPYaTOMNh15t{Mgnm6Ef`*-?09r@He37{#eN8>hsj zU275fCpI9zKP>b;usS26`?o@8dE~3y=x~v2cz!>@)&^#s1kNO|J4^HX*6_A+wCl&p z(ZMD)Nv>CLpD#r8Z!Sq7W7#IZZGXj~4=vpQuBdub3yi1H`ArgL25r;4T4~pP7OJIU zmlDS#!DxI@E#pZUZ%)5@^094y4y)^L&hX$eC*!b>t=+Bd3~BpZw3(an>Hy`UzT_t=t+x(Z z9NJ4M6!Y%RtXixDUj0ev{C)`^Uv69{w^S#Ea(!Hu)0;be6VWJKX5*y-`ozKF>A!tr zfO%`J{-u~EhCPK(9?WvyU>W~TZZVFP{|EZW*F(%urtcGE;|m-r?Igr6fALlR+DX1O zmlDQKC-x^-8RTPfB!OwG&kyq%@^CY2DidyXn<6LN26P}NPd;lT;@x9oR>jG#sX;IJ z-I{-`_MYS^#mAB88tSs`E3lZ)G(D z)PHbxp()2r8>fVwIXgu}PW}|6YKf=zwxq%zeVrI8i%v4)I7n@|I1wlKkg+Pj1Awmj z#V^M5^Px=@{n#*GNOft5-v6X(QOEo}cH$V;HT_GX{)s5c78}E*V5c?LF{9vabViCY zul4~pDTm_cOr9AjdR!10f^V_KOf1UwL+49U0o2%0dvsE-VFlizHz^n5BVUHf&gHr0 zW$+b#*X?>O6rJdc+Vgy{OzU}SoPeML2R@tSx`jr6=h!}o$ZJBp4+D27yv~@JDwAmv) zPVcyxZ?dac`I-ScH4clqt%jxd6TqtyaR>}zY*VX-cvzOt`ON5D_aL6R&6<)Pp_3`-}SP1s#D3zTZ@?*Do zn=iggUV)JCYn5I$aOFk~;8tO~nDCN}fVT^mkPdg~)V5Vl@Y*F$nc?bne(IHH4D7ha zkEfmH;}5sz$~y1A^T@SfHe#KE93nb75nqhfO^a)6TRR4#Z=7yZ>bv`^?V){75^TAd zwdrLY`C+DOWsyE2l1>Rs8ms2o!@G}SL0)<7IwcUL9k&*AH+gn9y_ zd%LXXd-H=V_{R75>amY^esjGg*LVGwW@t)ZUS-TykuE+EKW$@j2jMG?zah@^J@{>JuG^{-E585BE8 zLIq6HM#gBYj3di}L9w(vrp#CFToyzs{si+oWjxZI;w|>}lvA_jru9FxCS+HSO}gI) z^c?=Y#$Zard*Nm$ohxC%TAjImgZR#QijT5ofhXOS)m14U^=Y}7a#rrK$;#|A9XY{@ zPNiBeHf$j(pE9Vct-XpUQU5vb>y-`ds#H5n^|p-J79vPQ&+ZsSW5$~1d0L7$1KsZL znR%H#Pc&3#2d;t|4}0+t+7z%7lhiYx>PVRMN@#MnPgBszFtN&F`=4Iu#_Dpm+9`3c zlg`lr0NL=y8;wOpua14JEBywexm2|=0+qYa!6CMb0_!ZnEW#>ZCB z(wW#n{?*#Ye~|lLLR!WAjd zGA5w5D!anz@K35V)CN(;>m`sh@zg>fBa~9+&(QS*0Z?rD;{R7#y5vyI7!Ch+4Q~aMZZOUXY|+9n0*^g zw-R6TWlFm&+gKpNp{5uJedT--S9PG=ls1&gwL-2(`6L)Wsl%?aaVk_}csgaP!oAFF z-QIDh{IpiCPGC_1$C`P5s@jk;E#i_LWc+&cL}>B`qXdSHSfP!xno0WwUOP<=%?YGv z6H+e(2(tq!V|mLSwiV%b*@^c(BII!AL-zz+(CImR8wCVd^io_B+lei-hi(hYD7_*PAPk^6UaeIJri80Qq`3o+~ zW5!>FWm3Dduo3wXvN;q$-odB@HH!ID2UOE(#Wz08W^+4ZX=;&TDG~x2WdZW5Kw6!s zSJ)7gD9bp)FN5fR>N~X1p5&g6ak#N#f~LpWn#81W7Mhx!Fg?`GfV>%Mj>{di z@ry%JE*nt|BuW9}0j#>^Y~_yEv-af&#*5tUW|fmSB|mRGWA#6f8N{S&#Nh9blfBG5 zdbM7uEhDHkD$`SZfrG8HGKq~{H;^fv5b>9}-?jjb@#q@#=o3?bOJ{hRmassEb1qd| zD`A)CRG&RgRm|;+PKy{=ylhr{6Z8;fy}F_g`nXZjO*WCOKjj6$}KTI@i$hv?J&x9-ol^k$DX*yr&@|>lKEC`YLt^7peL<=Yz>iODA`Z|@p`}gnI)Ahm~jhzFca1zdWCRZJ7V1N>J#=FxRbm+{e`l{|Kze=Cznf|@m9`ew=DtyB$S=RH79cQW1n>gOy)}w+ZIS z1n70UN}V;VGb)`xvEI~fp&I_Z&wVD%@Pl9BlC?af`qZ#8=X;SP!%EvAobNbV9P&Z0 zF$PqZs?iZNew;RL!+lG&{al(kJHu%ksodXe{!Yu*(e2GdoboPEOJ%hy-Y}h>ruobZ zUHg=t|11GVZdqm7tWEhHhXj+Z7&OL`D-}JyURR(~4-F2*nKhIpdpka=QZ!kT?04)Y zmbW4?lQqvkXeuN_cMM)v(Rt(#=(*>OXoK8WX$zrfGtcdNc6n3;^Y2nMDZ5FrO)pgf<=vnIdkhUdwg) z`?djYN2-N(-DP8vE@cQsiJvyVa`rYiDti-5teL=$#Y>Y4c^kN#=d@t61 z8+oo>5nB@1vnfV+wRaVax67=1$H}9?kP+VSt4Y#WF=JV`pyozyxl+2#w_mW|>20_? z_N++%zOZY+BG%c+LR`|q=d4+5q1o(%f~^|}s3a3`^M8Bi{l8=GISas9p#Nm<=eY1t zgjO39T3R0wtrk4I&)>Bic2vEs({A9jJ~+(;KqPG>Xo^*Wt3=2@WV-zZmmbY^tTgb? zC}030rrCJrord0bKg7ifS$K2%9+OdonZP0nWx|SjAV4y>w5L#O>2&7{y}GA zq;vlk>D<31sPp`xNk3Y}R6|Ir7v-=|o|{1Cx6lA>oe64v7-{UuExc#;_HW-2h92+9 zljG01({}PbJ)m)jV&qYV%7y#4B&DNW!;%RJRPA zuPWch``+ky?CpI9F61<~xsFTR?r&T8A)xg#*E#w+FwQRS<2Ij0w^XSnXZ-ieb}QBI zQ@>lk7e_J2KF7*`86Z@04`lc{-&^oZ>l156pZ*U@Mb*F$Hh8TH9F*81!U?w6HcyW+ zfnht{yfi8VV`&>!Y@;4K5z24+iFWKIejXC%f12DP1E%IvU^02XUbuC!0ey# z@bXq<*tV8bCfUK4{t5TJl+2tjv7My3;sM5~*s668dl#F@zP?+`qvd$;RdgtgNj)qb z&L=eT&_PhFy)!d-b#Ist>F@Hcl1QEh!M@P|855(*76g~Q>1(8l1&8X-g5p(~d;UuI zY&s_Cr%Ufj(8>Kx403`dG;agj3vcy?;f}L?VV8dKJz$;%XSFY~je%M0g1)_PR+JQ# zdT7V{6AY2l*Ea*Ff|O|mcPvmhzOHn{nagWop}bZsf2H`r0U!5!WY_G$Fy+T+IRn(4 z2oteb8zr;y@q1)=^iKKxF0S9Z#cbgYXqViwQ#^jZ&1q@`qat3u?N|h1xT0`Uq@1d_ z+WzQX?DLqZ^rM%F#xjjqSWLfqtx)6^@iDZ>D8J6c?Zl1Qt^ZVt!b#C`O7`=~QQJa~ zA9C{^00P^rG5PZd(LEwefHmn_b6>-OBXyIwg;uh6U&LZnT$MQa^|$yw(EtJt9u0E; zO82}E`=e=U^9IjhyH~&PBpY2&f>geG)lU-q~f(gDC(+Vxsf$c zS{1a10xw~sRxw8eNf83~_AT0+G(YJzvS=~v@lZXqNJ}WCnhov~yK;1T#W$_rwt?S< zWfgFp`@6nWyd$5jF`)Dlx@Q;tSo zTc-+}CHZ&h9_s}*HW8(~8gD7*$ZCMnRu>N!kHts_)%f_~y#cj?$3uS+q{!(H@634k zEy>Ru6C?gS5vo7SAo&+VEe`P_%$Pyjhp1wi;2zIP^!!n^_<73AICByVn@nJl?s;fm z|4MG{7@mfy=K810j)eSS*jT+sVs!GCc z?u@mq<(G_9IAv*;QAAyFH^(K*UFmOBsr^emH2Q9|{B>cTA+#ubn@*{u#&0z#J<=^7 zN{>z)V4gjnCgw&1qM^^{;=WpzG~C^~kj?)V+V!2YPKCY0>058`KGdT+U%oXiIp**8 zGD@vnP`Q`O((fD?y?p^UOuQpZK27<`=IO-f$v#WQd3#?_bwSzi@Q-xgA*dM^n@fPw z{i8J3&cdPu4HcWM-!KVqz)@(XI5X~)xsrclaMAzze#%Q~(yg3}!t*zmbmyO4CV-m- zK5ehaES-R}#QL(^q?Xb_1ZTI%k-)>_jV@@gMrxtw*KYsktd~VVKra%hM?UrbbE%R0 zOC{xYnn!AMDN89}yJIrga0!t41!P_FMPL=g?Gf>XR54!TRiwD+gS1LKw7Y%mU`i=z z5T!XzfN`n!ktG+!FM=nkgnLnJ2`wbJpg;``JzOipwGt>G(vMxt(NIk4e_pV&k3H(p zEf+;ey}DX>*=1|CfTb1d?+izP$m{lGi;!{BLW)lmhoCncT8t^B^7k=A`#t0?>7 zN81`jq60sEi{|PW4qwR&(Jn;q;t7O|j-wy@ei9RX8OScO!bs$d!IUP&=Qyq>Tp#m3b^r>z6$9S7u=*6OtLe- zUv4h7sy799c3L{;2k!oM+F70y3_g|INq5?Ref^6@=#;NYoi3O^dmb9EFO)D8q%crk;%~aJ64nEh(ROS+|F)@Q!DjI(+NJ@~MQ^Y6B z;Ca_VF;$lC9w_VMlI3`9LBvf#8$LQ8Ia$c0Z*9n3?YQj5A-%o7`os)vF`zvaml@kv zDrnvF$ZR0p(}eqiXp@Z<_jNueWySW2kUg8Irq19-T1zD^TOwUJ*n?}OX}>Q2km_Xt zJ7lIr`EFRZ>2g`$oo{c^<+?#s31UCApT4Qq4E_hlZ+t_|S~ff9%{F@+4LGF=#cVbh z(k-dzzq_?C1hkuiJrmUry>BED^*_(aN#O38`nNPHPRmDH9eH8@iPF6N5DL z3(>wO(Iz;vlzj6BxM`bXQIg#(1Egk|M-W)hjg2`k?V}lm=2W?Hp!Le%u7Ona$p_jF&qi3IJexI%!eIK-YnF7P&I?agiz#VdvsjqC@JSr6`@JW zU9aMI7x{*L^M7919-&w;W(!n8HETwTlnZ<|E^!Xy99(@J3z26(tiaj#%1p3pBbCqgJXQHtN&c; z9X)=XC46{tq$kuI{3uo!2YYD-d$8$@-~EBe?lUZ;{e7>MipZB=qLuuL$k#gxmR)*O z&BDGTJi--jmX;X4Uz0t;HEVthcMHDOZZ=~FJg(Rv9ejts4*nz6>JJ1h$jrZaDcjLK z*gXZ27`l|*_79rBIqw!M<=yGB@)&~H;)4%Gg3P!;!E>CD8yC0EyFd5bQHbo>fZ)6L zN5Ghyp!Sm6J90{Be@-mi=aQz2rh-sch`va5nwuVy#=F^C*iX$0_}sR?j8G#&PT?C(!p$B*8P~m|52c zie_dT)}0J-wsv-E@KNB|oK=%DomY30MYEJgpqq2VlTXFpAPsz{j{n)fZ&`MxqM(kPAqJ){QX=BtEn%|FRQ$`pHytgzxbq2e&Ps-BV%}WHp*IN5FUiMo{`Qqz=&uVD zZKXOvtsz1fI%s!F5B)oec02$Y<5q3k)_w-PmB`6rCo2~` zJ9$|cw(f!5g1VP^L2jQu0Ab1XegSV`$d?rsa|Avco?Ma)(fFJdWla>G7@7P{kPDV~ zW>r)l)y2@phGG1|H?_Hspoe=r84Wq^rmINXs;fx!9-cM9&-%Z-!+XGVcHa4UoN&B8 zA360CDDO*)Z`KNn;|OL-TMxq(fXm=4V018fs8hQ97tgN$=u5J^rStyEJ%Y%YzL-)^ zx8WMYdo&Sji~0kIS8V<_>TyJVsK^JJEx+L!GGc!Z$E_CaRnVN?6Zb&U_?X7a3dxs^ z3mwqj(~GD5k905~_uf=XSetZqHcG(mX}AJ6r0jf;_s&d0+6*xyQHp26DNw3z?s$?@ zBNN~f!N)RUZRWf4|>Ur2YM~XBgQg&VX*cV3p!}vrR9F{Sz}9$a=f_ z7)eo`7GlWUuNT^raqQQbSoN2{_xnrWD_V3&jom(}EIQ9!sTccs5;SZ2b8@7egZ6w= z-MLMI1O|;LdbM}dqw|dE=Cx1skWVzG>YL?dAG!1t){WQmmeStzLqroj>teS{yP+H=LXlMH2WmNCICV-x5jS zla=*3&fbW4*S(B_2cB*q34ErYp}z$FkG}*yEzi}paP_sw*}jg@CKW05CWtzv4)ilb zT9dIfWA^iON4xHuR)=sZK4p%Zj}<=Um<@8IB>osl=e!1c-I0N8P3JY`ZiVR-u(!UT z(p2bgS%fGxb)P=~FQBUuDriAnpL^;x1;8dZ%@4_|o7#O!ZQFEW%))&}2KI*355pz$3 zD%H`e9xk0YcX4q>HTJpYl^*?ARG?o)erggmX!|W!7#p9V#MfB^vVphdy zdj7@!GznJuV76JN!sp>JQe!yto5X@t3t{qRHVK~uP3e705{ce|&IM5oS2Y5>j$+z~ z*O$VWj%~Uqv6R_w|3C2iS@V3poT(&TdEHpc+x?bD!&|LNFyGAf) zf~}&=8Y1dFCp8K|PsJ1UlCSr?QdA337HDx%2?G{gwvX)u)O_b$OqhFItB*bwuXx`? zM^p?|XJehXVtb~`-?14)>}PgTo34jN?2pklvC^1+`13RQTBlV_qw``1H9Jt?u>Pbh zxyfQ7?`;|J)%`gR$#&qzjEWdd826Mo1meaYw2>-6d zCn8Z-qyu}1x9w$r#Z&6G6jk0w%2(7tQs{y`(|M;x09HDu7_JLi)3?2qhfWfoA0E!> zab@&4C3`T-^+%i#8Mh}dt*fdc)`%~stJb}r&||F6hIz_ewukCfG@CLG`bPDSxX!hm zjvV*som;MIjJl-=+^?ze9|)X$l*-{Q3?(TvS4RuAb2wRt;{;dSl60gsq25xe-G374 z*u7Re_vfQ6oyF<4{?aq5f5|Oyj|u7bIBS(&lY3qzU+1^$BL@kTx-n_P>Fo-1h}gh! z#u|Z-AeuUS-l{n?)k{Av2fr3yU42Nsa$^*5Qv3eUd^@_{84BHUXuy$cz(Lz{>2?jw z3ImDGSmXz1Z|KQ4praa?jri;az4DlHiJg{+1PM|h=UFVo_Ko=Lq&MKNH&^kH;7nXi zx$NJN;Sz15c6QpHf*n5C#1>6D>DB(8g4&1wgRQ%OYHJA_MqQ*xX^}#q6!%ix-3k!6^6NssS8*L5xtpq2KW*lz5K$R!pQzqvxSxLVoxP*JKWR^` zt*lKB;jV9JGs)??gpO>)BrA7=C)* z1z{_|d%$Jcd&$eow+#Pl8bEVQMTOGK&UybbbaRMgSK}oS)75iYT-mUgjwVpr$u7ez zO&K|^{IUvHrW2kS5(+E3j5~vo_s|HB;RY}Jy`5vyGj*|*Lcp|blS*Q^@FN+s;bxde zB~KmE|CaBox9ZEjByBo{5W&0!FM8kc@n&50kQO}NKgsv%SAKE9k`29RCx5j0?%CDg zl0y_KcVm6`z?AnsJ?(d|DYHaF3e{wgo{4pd$L@VJ?w=mEyyslSFFJwUA%Qk_6{M0W zq#jscqJe)8q)9!4!^K~GpXw*Hl`RxqJbH8gV4n$P%Nwu|)5rP#1mDwJUllDN;CoJN zI6eZt|MmaE_b*TjEblN0`DNivO}z!6z`cWrOyqW?fy2rC=JZ+;qM_r0x??>ifvYQh zTRUjc$lvvn2PG!8FuS56=)KcKC`9MTc7QD~^FhEW;^$NcZ>h_!nU8f(p@J`HDFj z8{l3kAFRbl*pu0_R26+XVFupkjhk}TsmjVv^%LgrAFX}EZ2&Gf(e@HiXhr*;Tl5-b zSX2U)arR(0M~Do^(MR#`H>vHp-Abd_LWFxC;PHFrANSt-KllEd%MuX=k#95p%|VsB z^B)MU9*re-JkB(!-7smuvOvT8o#+EknxFTl>17O4pl8uaY{sa48>tmVZL%Zro%vI9 z!@UNr#%h;GOl=1SAm)+u^bPPhoQ+@a!j5-g3)sN~bW$57Sxl{8ZE~raaYpSit$cxT zv9X`&nf(ZNRO!TqUXpt9y4_^YtrNP=`R+eW%AwPP?L#Uw)*0i2A+%!nzuf!3|GD?|I6~$WZY_^!Zf_@m!EqsEhkaP* z{a+%BjD}x%eswUVi<|<#@;q)lJ8wLjB1|56mHj{kf5y=uH++M|^)QhT|6-}bV2PI4 zp}TsMUKxPT)LPLI?cOh_upLNC=HF0VKKl6fZP+)U0MUHbg;1SIdH}@oO#PZY7gVPvW~4$gg&dCEGN4U4jM zA}-g*&h*bNuPF~C4kW{ivHV*s)0h-zr zDsUw66}{j7nBCzO3FXJ(YjqcKSmw0TzGia{>z8F zoS}Xo@Apwca<Sd#Sh6_*5ZWH`8-ZT`f z=FG9;7W9yXm?^K>3+(qDcGAC(Yo6irIo)N^ z#`1u_KIFg^xa=?B*!p+mR6X0A|0=Qc&llFJ+ca7iQM*w<;HxWlOPn+0j!W`Rg8R?c zxM5W0vPZ4YOdKD{k*h_d7RRO@<{nU^mHu!-08R9lD+u=9Z6{sF7Qx;FGmnVB%vQiR zD*V~6glun(M4S3q^|6=c7YW~OGPdhs{>yH?fNisx8e#YR$Ake1XA}+Jr zd^Ma&>Fs>4zg{=C$=S=^CvO6ox&vzZvJ~{ zCXXU>(x)ZTHGlutsxq3pLRgw7Jm|{26gOjuSC4TgEm5M5Z#eN_;Am(@-=2Gfugwe0 zeHJ=`?$N$mzD>e%ouuE36!1PI8U-=-`9SRR>bQ(5m!msU$Ag)YG)(Bn5U9XtMG{lY zG3upPUz_11T9j3U?GQ{g-4Ptx3&U{RbIM3ETVrW3y^{t_^CBoRzR6yH zhRcnvr@cHSB_AhFR6;ZI8nu<{;X*1?0k0q+H9-`L{QarG9FI_|uatU5Iw zZct5QVl-dXXt<^3JIRjspC-?q#o@R}8i};pp)*C6pp*5^>^+?!rvgSnw)MPG2km)0 zVKd}^>mJ*xWZvIT9=q2uVAN~-EE-bP6v>~wsjPs$z4!iCv>6L3UuhSjZ_*EeJ_fLHRKMX=M61-AXjN zMIY>WoYqN`b2Kb%6w%sY^2l+BAMINe?F&dT&^4a}Uxnn=@I|w;i}KpDeGBXUq#_$& zpzQ3ep*woyT&`Yr6`EIJ8&%U!@ z?pI+du)=@TeHOLkuCff5IX`MO~w6RCSooiSog)nZZ(=#lk0F z$~=*o)v{QTIBIG3^fS+t;{fNSSecJp(A4GIr61uEH^>e(Qo87huNtNR5_2>0G`nl9w#Cr|dxq`A}#K?RN9dty9m zVm$kyuwFlm5bEf+iJ|6Fs%IiIJ&g&^Jl_7kVcUqW1|r;hkUPHEXU_lJ`^)=9*pQxJ z1{1=)Z$`NHj{ms#lmE-TzZUFPD1DaRcH0zE(#0QIK(|^H-$rGP9_2%zRTHb}yA&d}xr2Zxm0w+HG^KcIC z;^VscE;i%i{SjPW(7Te}o&p9Jd5OLGw%>rwv%jE+I*kp=WQ6%dFP>fqg^SgVv^mUz zFl!$_S&QPmi&63;WHwA|c~d#jb*Y>1b>_QC{cs2}Lwh?fu=L`6w|I((F!D5Shcd~M zL(pv9-(vfU4Boh9v|@Y7&x>(F_8x8|hV~?R3uyD!G<7MlG3{sk6F$4<6V4&t&Qv3@gR> zvr~9@tM9A~xki`z!`~f%0xB5_Ija54_8i~CmCi<+w}(q*IRdax^H!9 z8cuC6K{{HjP!>*_9%K)&JJ!?}BZJk6dC*-~&(v~U&=XZUhwQTS^G-~63`%zlWZSW( zTNDUS5_nF|C)_=GPN;Vb%;5$b8+nWHG28TER^xJbw)=QWhR?I*mD1UU-ON**XhX;A zGWUt2*aVLJb?Puw25Td)lVef03w`Z!e@Jw-?#VK`$wM7FcqNr%y4}L89q(w;Ctc-& zi>~7#x}cropdNJ^+_#s{QhR5}N0E68*Gw)+jnzmvOpTqSEd$|Pv8Lo5AWtVrXwcgZ z1u$ON40+tAr|+LBkGl85UEEt#xP(&QoglvSRjSWKk1`ENT5rs!g+xy1@0}E*Ur7Rc zU}IZvG*}{M7e=L{-VksO2bZB73AVIhR~%H_3NDoe?H{l=$CQ=_9SUY@F(fj%kXg@C zUAYQ3E9)DD&bj_zH_~RPJLtF-Je7AjA_WTKOv&4(#@P*&*;oTtw)<61L?}$EIj8)w?dmBEftrQ z3@`)tfV>pRAIgj#n-lGmdW)L6ET$J0>DQ}ilfd6cDh^kxVQ=ia=5qI-iRW<4sMM=_ zb@n7*e|?|!4UKPVuzSTSmvW=P4fxMeqIUYK8$UF<$yJ;MChw7tZ1lCZ*Do}0rEK7+ z92^JvJw?Vg}o`_eyGq!xGg?vq2eXC|!rLGVT{(_co zLapyc#R7w4y^3*9{jHSSZFh;S_N&QE(aI{7k5tudD*e5Q9f$(<1@>S--cilYKR;oG zy{itxs|toQ4Xjz^Mi=G z7+bAh;R_!<=J6|k)jMAb$G<*YS@0;|z>Oy* zSP;ho3#V^nAnmWq&BjPM%zMX7Q1c5ki$~W?q&@$np#RdKPDKgyhRu5(nz1jSe9)bb zZ3o&BU7f@ZhB;>4jYMgc1D$O$Bg(bXij*|3BCrdB_Sy}NmscC#zI^!8Yb6c#n4>VF zgUGG2&I&NrK0JaRUEbxtvX`0Nz970hxtCMeTZe?Nf_UqD>wms<%on?=bTEP+Bd!9C z320uuE$wqz_@(}6xlw-%00Lhx*It~BTWD)ck2}TH+$Nd;qgEBs6N%c}hzU=K)iX3M zZNAO2B*De18J>P#?>s!=_nDmDUh|3OVE!lk{sW2Gh(EF6=axdrb3sc7ZW;3fAFWH8 zuFGN+bv5C?pXrG;*-r{K~Wwd?9#EzmV` z@D;c`Y1V>yrh5WX@N)BVcJ@+I;dN)Q8o|Fvt6WZBH}rO$umxqR-sLj}--?-~Swlya z7h0z=^G~K!9Hr3Td5<#qxE0eod5*UUarpaxQvtVq<&%TwH44KEJR#O$DxX1ZHPhZn z3?-8)xAksee3xDq$AUJGIQa$o(SK(gPlg>`9}eoiaCx?t-7fNW%(SnbVHaL$6va2> zAGwcT?LCe;G#kK3svp`4{XQA(CVZNO+9+)(Pu5(7WcoDbg1mR?D?DAFf4}o#_vJZJ zJh-Q*yB|6(xutK$xw)JqesJ+R-!`A_^%DI&YqXG-xD4CdTU}s~FBR~#0;>?Pl=Id2 zF3(TR&2$39bfJI;#V>wgeFvX+88&C$!8d93;SE1ay8!m{RH8hBn3FzrH%5t`VNgi3 z*0x+&?Hj!P*1XA^SclEP)~O$G=X77rup8A4MDz5HozaG0;u# zink#rk80`q)6KEe$keSwPuhI5S8XfkADiUfWCgldYQn?6-TD^l9X;PC;V!BQzrk9$ zy}z>hU1CFWv&e~)A-ZX5nob)kzF67pm<&D5jHr)eb+tR1Kb$O@S)W|uvTxPS;1PA7 zX%%=Vgq{p1kyr}EJpT5S1|BW9Yh<>*xDuv?xOp;R!o8Mx9wuSn*x_x*>N|;y`k|Ir z8Em&UA}KX*lNjs$1(_N&A=R1suV$)3beo{X%g^|d-P0mT(Q%GhKu#B>z@|vwXvmI- zZ{6E={~~+A)4Tm}h3PPy&R4-zRIawSMucU=V*0ogymM3CyD76Iu{Uds z9FO5{0vC+VTeFB>EsUkN*cC^^sgGoQg%ya)oo4P_zTlS_H`G-72`gs{;;hqL;C|kr zf|T!ld6lrxbE;HAyzF@Vi{a>n%FM8u$0=z@?5JcL&e)lY#~u?ozV`*}Ise6LN#Tsn&8AXlO;>ni*vvsd?_O}>S`Mf-Hq`WWWzqe24Ecgh;I$0WoP zCx4{JK0I=!)Un_Yxh3@&4Qx{R4yM`k| z@i0byCl@Lf+D_9A5{14J?+6GHLp}X=fQ8DPbe;~e_rX~N!MuHA4j!=DWVjt%td7{b zqGO_w;`-hX!Iy7@g{sXWQe?8i0jd6ngzilvhJ0S21^T3Idw_pPHUKEu6@vwcD+Q z9+D?C!C|7qob!xxgV^xUm-)EV?sRs4)gE7x*UNS}v6@p9x2K?T;mm3Xek}5v!y7AE z)5m6bR5abqJ38|$H2>i2u=*^NPqetzEAy71Ae-1<7^ZC|+TnfAkuTgWhjm?fW>C~v zZfwW-=v^}32eFA)nr!|633>d`p6hx#>BCNFQUYn`Jh=(~{v2)p+Oe6r<=4wg5x>nD zT%2Ey^p5##-!qKTgl_hYyBr;_+N!%9Z8`FXxO;7GG(OxZi-uT6r|UB-kQWKy7=s}9 zQ^G>a0z(IU(T-a+6i%s|G13t95jBr7;k>sQ%6k=JZHmLt@CD#t zuhGLFKk>hpx|SU-51hV6h`GxfDQvjL)P3qbICHFb0cTN*q8L@ic;bQLtJ^`8NjTpM zMJS;XPVY2s-7u|k&WgOlSjghTCd`nck_9BX zL6a#~;SZ*`pm5xbtgV7euDm1HKmI#+JE?E)Tj0Gl`70%&=>mF9tlLu{1ToWV*t@&o z@$+F>wK8+=7ipb0h*ca1)pg`SPnLt$$j9cEjuJpu3z1^Rn{0lBcRd0RgBLky{vA)} zD*u@b_Y5eWe|KTCWL&6aG$nO|Z6g~GSU5zahY3_K_tn z`+tDwf>Ua4C}S|eQXkH?r~{C~ll+(lu~g`3tAdvx93#Hu=7dlrJLhS!ZePmHHqK9U z6C58_W7|D&{w1P0He&N`s*hN4iC_ZIb(}9Z_>2#EbX=$@EC4*_*dj#DY`FAB-OOMrqM(G+MB?eAf%JLuqPAp z9~E604h;XpPsA1r^u+M)?j-kTJvlWA{@)XWI zl-G|;-Z@j85DFvcHI7o{DQjveaWm4tg5)iW*w@_Ys&C;DU^RX?QU7p`;Wf66=i-SP z%Nk3mx`st5j`YleT;k-cIjY6`!-R0A+`CvzKrm&*g^pcDA6N4ttWr2L+<#%>E?L+o zIUX{~(*S%W<6ee@`hH|P$4O_$IbJX}tC4~nso_LFXsS^^fjX8_Cji3(iR}V|9@Gp8 z?FaqYn&NBRO1yU`mUB;zAENUQZroBMb@ENd!%+n!#|vMw(pVpJ%9A$?y(b2V`6YK* z^I4DhWGIMks%P#b@Ldz>>;_CAjz8JydslIXL$;-=_WqF2NVwwlypiw+d$PE_X3}Sn zT@u%hl``!9bN%yYcxw9r6F|YNNu*e1blR{2K}v?-*zdQgHz~hKw_+E1sDE}552h&# z{sd&cctFiz6u=))BwBBTCLQwf!v(y% zN+_;P0qsvaShi`7h#`pl_sc=WL#%33qb({Z@xX>?uK9`YCzW+^@J5HuK#heTQD0yT zN^C5OTEN5|D~2x2fYvhd+~LPPX+IV=Eh9Q-a5of4$;i*%+r1%9gucmt`c?p!SmDJ+G}cmK8MwJ> zp~aZ%M=%3^B8cvmT#SDing0$ZIN{j$Z;J0h;dmJP;2vnKA z|H`Ke5ir|7Kjvts@;?COj>={FC9g7*Kh21VD%=awrQF@|F+U%$7a{s*9(WfyK=LncDnu6>hnX@~&>sNGtS|d7f`se6t2lRh zPQixF3|t&+(#J%v@g78)R#BiN9PaJ$lkgbTlSIMQ+R~k7%g|-V?ia1)$9}nv)9@)P zTF(}R(Z-O`KK+)+Nmz^uB=ToV(T%bRJFBbcj!5xECG$$pAS_`g9EP0{do&Ic9!wvF zxU}U?!m@IN5*O7XSqa4LJKEUPO?>T@Zw5s44^{(EJO;tZJAG=f@}!TMKpjpkW4%j-XK# z&H25ck)2E1q2F)ezLrh_r~k9U7*;@Mmern*6Bzcrx_A`bD%TCbD%;nf34VUG?+$u5 zbZw`ZNhg231u((c0szi`C$c>{pZ|`z=RBvY-zZF-!0TKN=v6$|s0_~*9@!y6@NsrRWIxR{EEmrt|sr8{lDNj}R^;lr+ADk-6 z?|vJ)G12d}XQffusJgvlxC^{vcoOCBw;Q75emE0XIgdI!VI&8BNbXr3wm2haMft~@ zCrS4FJ|rADgdKUmHnvrF_kAulL*LMYb{~idXb|h2>)~s<>225X$z?uIk!6a-EFUrP z{2cALB^WE034ilzsXTr}A#}@@oMnwXRgFJ&d?2cihRZpGjfP9!a4?F}Pty_=%I%=- zyc8&7(RhI}ZQlOyR4 zZrn|&+FK-Nr9L!kxXUkheP|l*LNklgvcD|9Z276o2W*-@+qIPSDstGNQs9#e-L)(% zP8%rLwRDbk_@3^t<5HbFF(RBO+1!M|Y(S~qR&0C;|>kzM)k3A zL#t^zQ{w;;TyR!tO2Y0)iY{F`bPS&lqm+iaCm#Si8{(v+F&I`Y9jR~7ktg|avu8z1 z`-q1(#W~Xh3pSXCP!d|1`iNaTpNe5xRduBPL`QwyWfi+tnt&cG_QpzhyP7N=FO(~^ zdh@TY{@QR;ESeYA#~U;L3%m5nf{iG~^q)^};~dDJPKGxcV0G+!j%>1x9O(Qv+~=j$ zPkqYWBL2xr%I#+P^hTY3T1))F$+G90xcLn;HsxPuw$Zp~E|_Nezz=Yh`%iu#?BDk0 zAsT{%S|#c9c>sMwj^O&bOojrZ;@{*Q?biT&x?UUJMn$Oe)ajMT zR-ct|F$ixn!7_+dF<&FLK#)AoM?0L02xr5|O^W~GMY`@8<>{FRZc1Met*3DRt{gyn zfuU@ZBoKpkHLX&*oV--?t8hi*FtsgILHH-r(VdRs2&!?X!bOKe6PY=$v~g{(%n}lS+R3Qz8*9ec+e7Q|xJwh^?wAD4bY?jxDT{9(-~% zbuxHzL@RIS^3>TBHZb$*6GHTN_NEH4K9a97xl} zIuoPQCCe#Zie%ydQ%jwRyH_0}H!pT4E+BxF4>)R|S1I9UR(JFMSVAF;=% zLBkdkPPz|e--h%_!#1mEHaOLth#4EB7+E)IDcO_YjZs>ShnNBq1W)}#mHW1SFKMy> zs}L)znIHoOmT=gh{%xoeaeZTyaO#k(NHQWP0V2Odx5cm-V=~8QXJS?TPd7A(tQY!( zV&OxkT^94r&i}i^X-OZ-+Tc7&{(OfVa$2nKrgr4J%Y;lv-(VE zcb!J;wqVe7HzDQ&)xHAuL zVTwU*Gv5mZ2%e!6Ev8pk-vTJpz(_ADufvCB}b z>urp<`27_(=AH}nDfKR? zUX)BV{A)5q;hpr&7w#*s!I@H6^Y(K1K82m-5{E$hp~k)6m4Vkt>MG5hyni2=s4j1s z>T!R|P`>rzrOXwKVwOQ9tf;>aWv0K&@#`+rypy0$?&r(j@7C9+RDA4Q)O_B@u14+Y z45XM%D~kzh|C+qZ|6M2k6yhtg6eT$H(eelG^N$QS*XpU`rNDSqW+K)5QhphXDGggX zWOt%lISH__@{139mNc)0ab)V}N_|HF%h7N5Za%GRDE?qB@`#jt=90c)$o%2Z+_Q82 zn^Z6m?-?p(+t=Z&Hi(7^u8okakaw}aOfEw3?zNeL3$`9(yDAG}{_d**=~0$e3hsZ` zT@)16^|jZZ`#Sn@j%?e#Mxv(@x#xSA5Hbas8_$l{BfnZn%!U@wdZxUVK5b-su(afe zr>wFr1jh`&;ru@POWgy-p9%^_Vy*S8$ZSQx5{r|Wd0BS(9MsM9bgcFJ3D;fQYB^sW z>-0)hH3PGe^!Rcuzcni$@ct?dMW7Ja?yx z=qIc~IK$h>Be0JOadnwnR=^5r`n|V!Sb*HHD$Zrw%KGj{G4H2D0i}fy`H{W5&zP@o z@1hbs*FTw_m#WOnr;%^zFG#*nCJlUr2(`&zSs7`-|XeC3k+#IwJCIUIOgk z%4~gcAlS7YU5wkSRkuDvbehj4hWr|l|@nda$6XHJ(B7oKHak_c5X|iH> zb`T|i>&H&G)=dbV9}Ky)Mhunsj@QYmwP@|t*HZmM<2vm%H0s5 z8g>rXtl8IPKEi@d+TdCz-P5m6SUO;r>UxO`W;vI$8E1H%ma93+=pvDm#i(cqP&xQU zJVO9vnYxumGLD0enK(1a7IuCNkk_PbMIJ5dg`Sv?1w!E>)AIK z4d&ey7aZ%OT>GR4~n+<)Bkb{=B#{Dmjx$t)G)o-*gwnL6z*x&8zzYho^ZD(BJ zrTZ*yvYEqDcUm{u%WLT^U^&EFoD%Ki*m%#k?`8CZ;gLa`i&dxTj}5fiSB2YNWZ`y`C1$Wl4IiGvy%JUXT=YeH%gUN^GUXBA3P3@ z25XPVh8^m*7czJe57)ewKMyPJ`ASA-4} zlDKED-saA$R2FRMbt$O2SY#-s4|R>hf7lA09N5>tSqlGf+>L$wBK7U@V0Q&I{-PUG z7l?W}_PkZ$QE2kHo81>jr|J%iFojfYGyK?DbhvHr<)=R|K)cu#SS!Qxptrz!vAV_>kr4}l81VY`HB%>#z_s38y){5Y!$HVI-O!H}G;f1lynVR(a z%S{ue9nP8JTSdB7?Heh6rUN{q!Xb#o%^WBm(6Fm~TI^H8!t42sg}11(=c9>T@f(u3 zaT@$C&yS0NrkcIyd0yrT&g|VxsA}n}L|d1#p(BqLcE}hgNIwLv&G6}OV~QufJM;6J z1S%Qt#Usa|R1PTEy*?`>Pc^MvAujyg^4GWa~3S z{R6IZNvBom_DssNTm||NR!qV=vTc9?=TAl}ag(w!I$i7L^)s3#^MpmoXppoX;A&YU zb~k~M@W8(6JN}X5Se2vt&8JJ4VaK$CF`PGXiPi2StoNBALEW&Vy#zDVk-mp) z5Dlmbf7=uEFhbjoGt)mH#g3irG2C8M*#PFnBL1_H@ZNW_iboqj%$D*x5M|wI&j}W^ z_CH$wlofkE+uo5&SwoUCq2eEn95e5hK7px+MYN2st=v89C?2FB=-$U@n%O&sD5K|@ z?umZ<`G}zh@l$4ptnXsekCUmg+Y2zw@P$byiO=Ml3%iQKG_xyiaNvG>`otm(k$<7H zY%z3sF&PNjZ_k|^n|I5&-z_&4OIYxuMe!xT`U+QDZO>?L`90YfqhQgo`;)`8DkrU1 zRK&bJkQg){wko;7wLW=JGk>l5tg*A0nnkAKQ*;PXN|8%1p~30iFLxxF&KGOG*Q>N!0U650Bp z*$d&%T{jZ|n)#8i@Q}#5GT{L1YCNllv?{W;Mdd#)S;X_~TjakZ_Ag4M4a1wjf=MGpTn&I(c(`XhajIr}sZtRcAbrPOMuLduk z5r_pXX6fXL@6}hvvB$~NErqXYUF2Qr1wjXYq+5Ki#c7sT^^=wDWfIqS5Rc5`b ziD>y;vAGiS1IE}@8r3}yaUod&BBUAE#{5kz>p4O{#7+YJo##p>IF!y^;YPVoO@5cpwJ_M_AgI3%kst46AWK)qyOupRN_my=po90T@s=B{M{y(BPUJ*&q z@`sv&m`lVPhdo$*3u0WWZf!5snpLb46CibdVxKc=+*pj;EoK5P)*qfXBA|RMD$T>( zMs}mV)qR|%zl@_jEzW-WQu79=36gPprE+d3>8vP~;z{LS9aqp(4%#e)*ej3AOKLR0 zwa@cuNG2Q0216=o4hmxe&X~m@sSWRzUb@{$z}_+v8_CsZ-WiDz84tt@-EM%6Xa5Wq z;lNy(+=|<)jQD0C$Z?`XxViiyM5?8FwJU+hp>-n|QRMX^+qObNBpoL?<5t8{Kz@XKQQdY{K{XSU&V^jTc z8%UPeFG1>vU<=bUU*d!N@Fu`D=fB0O#tu`7!@I;5@c-fO#f;*tlh6 zz-}FYmsZV(N;*7HIyhhs9ai}}KzjwDJa{?I$^f~ahdd4pp}YJ#Oqzuxj4v_gIF}DL z>efr|!8A7o2o1OG)WWUmf~+8LfX9Q$DRcCROi~-gjS}Ln*hUc@4GhWeA&|KiO*q@h zL*I+=YgOLXkKZ{kvfnD{T`Qqpb%W6GlP>` z^Kfm7W2b*6ocY^4&ZJoDzf~MG8eT;>`E>{E~)st*VJnS)bAnS5KvS6xT2@0LN1Ae$i+n zeWbg})m-(vnB|MZDNuJFQGb{pZx{Ne7LM%K&V2`gX4CvA^+x*t)$wf|(*_Ce?fj&B zq#|;Q^_f5MqUjdDRfNcrJJDkom-+B~pbrniPxMOoyuaDLD$?zC*P*mQ@0#e17>RiI zcBgXI(DsP9llZaVwJdq+wfI6EhN_;ahIud-K5Xix0n3X9I+|bjJ8-IYN_Zr+X{W8X ztE|W8MJ(zbr4X?BOMkp{4@S{<%941LB3%KKH**Xm)RJHCT~M+usQD5j;s7L#jzi0iah&Cz=L|YHnk?wT#it4&yj>$dD00_&jX0!?& zkj8G_Hk+X=TAAtB9!xt4qS0Qzjr>GpParQ^W)-CCO{CZ@@R}3z6Y_#j!S9}XPRdHK z-7k%Cx=RX^W*_~_NHk6cgIn-(EV<+pe4~ku5l09~tz_Z^)_0&`ROA;Ls+3q`HzwB@ z4fphszVC60Yi=>Fw6DF^jf|;SZ=Hx6auOXL_T%X++ zW|3B>gkbYnKQz;zk9Ids(GyEaKMoW}e&32PvYXvbHckK$ArdM+Mp8cslzutkM6S)t z;{uFSeAwUsEunTrDmydGvsb(7vzH-oDP=oq0q*Z%L;3u#sKq+pU_XvFx^KK`PfJ2A z<>VrG{`mqstKH~tqMr@-NSlRB{MYI@iLDnOHYjmv5`Vqa4H!W7&ve~DB6p5`W42Tb z;+U0OhAO}XBCB`0-{x=!Y&aZZ*RO2bn)Kjzh#v>}TW51$0>(R7arFrzw$ ze<8^~S0sQ*{O-pTxTwmWYg$%~^_^w2=fi8Gplas?0ID0xdh@hB5?~Lpz?1!i8Pr6M z_-}JPKxt)@mK%S)IMSJquOlKFbCy09*CadDxi zaH#dpTGM9U+`xX{sGelcR|fJP)Z6fqyPD&?`L$B7bl*+wl>$D=n08(pib?R@>CPHf zuyBcsPx>{3Z^^uoSDk=d?TlK`C&imW>T8ThyPIfj6?IbcL#RPW->eQL@p_p@<~ z6vKCp`0(h-N&0rhlB?4FmoYHi{8zDFEFEoOLZ{T!N92TEnwkt>7K8;G%4!LC@pW+i zAYCM#0^hplc+ds+WW?Ni=ge3&vF^#2j+T|ws-6|zyZ9ILUh|s1lNJ!8;t6~c$S zam(dYNSdhRZwx!7a3xtkQsItzWR)2-*P`guOPv{*qH&Ji!~*ez&m(G$Ye4#9)xpIx0X~$Qh3D?c;VP+_68*M9)Z`6NZE5mwg`d>YtTVYl{$CkcP~ zBEWweektO%|5o*f;5=a2ljQAap;-i8xYWw~$?TiSf3bR<`uO~%sW^`f5aeA4E#O2($dmEzEi+K>&6Nb^aqmKwjwIu-vwp+%(E{9F@BORaE+!pUuwT2~ z4`L1vua}IY-Z-3cu=b5`L&RS2O}}2!90F{Ty{gSz=A@Yh@8rE$a%t>WYBiqw1;w0c z)h3G|IG(hTnMF4|=x*K)_#R=UA`~hh|H26W(`8a~*U6Whnq4#&ZGD`;%t~U-j;;qh|o`^@6lUzH%`kZ`iUKp+~-f9FyRna^1jF4=tGJQ`9idfWj7Q>;GnEH z1QapwW`lV@i$GR91J%ck%Zx6+1CTgI6OHL;jTyX}$&qh=5psrES(4R^P2@TYi=Uln zSyvlt?n0%%4%SX9xEit%>`%9G^FfQ){n}8t9vp2%=b(RQn;F1QaZ5`6zq$Os9uLkTy z{}?fQgS4Xm+)*y?qBDlMrc}$~;^Q6f+7UMUnj!zilFB_DCsdPtd+}F?X!O^w=k4zm z-pa#4 zr-B*l=G*+$?X*YRs&nuBQRj)je!o{i zc}ffQgrJPCTBr2UGcBKrh({XHnAS6Sz-;doD~;6B<-M+_F0_+H9_upcl=%btA9FK* zGe6ju+$+2+N`KjaDji6BLg>vk#}lxf$gq(i@albm|seM-(vW_&t$uR_MY5$n|b>` zzT~Mi%~)Kj^53=~kBp!Ga&>t7!b+6nQxrpoY^YwKh-r45_t*ic+_uTYD{@O$rCE{T zQnv?Tax}$;3A6TXlPDe>vmYLBbBDW_55wQv*QrZn0BdojO($sISp6Zt zZx8$P`hnwk6EwfF&UF_1Q7wBi^M`*g-5r-91Y|OVFEektY}Zo9z(pX!QIv1ivE^Fg z=Ct9J8L|33VjOt<=B)WRF!A{-yB{8F<^w3@rp5t=`q6egF%K@$!yez>>4rY1@n-u$ zjXo2Ao6M@hck^!3&?whs4^+k@nJ(5j`*tMDk;O!6{X1{c9h?nNUDYn&clxm7(R@Er zMVemf9WYznuG?A8VQ}RR*1>1b%%!i;J7hj~bTGnapRq;$WUaL3Acp^-vIn>eVUcdqg{VFXF>?^0gI#d@p6SpC1Iz) S9dkH9zE#a_nGWWQSb$uifl2$ z(9NmUUH6GP#r#3-x^ubz4`Y8F)YkU}jNWZ&k>aH-MT67g6xYyFTtZ86*Pz8UNOAYJ zIKhe(cZcFmaCi3r0YcE5exKhv^WK@~k2{l@%*n}KJ9}qxCVS61pJgs+A~75& zX5`GN{wi6kNWS$k*E#z(dMCXuIHhlz`@PRw=^ju}9F}F(jDH+y-dJsWAL7{LTfyVB zd9PL(-=C*;lJMbt%!hE`%yh6VRVx$L7cW}W4JNGXsIg!$ zzL{Zv$gh#4VHn0_T~XZ6-l3u*0r)xF_mqtlF^$)n>7V;--XWiU5aJVx+Y1&;A@yCx zOUw}HM5YOJGVTnY1dODvv5%zM{vEb1Nj!4qM7%pe)S;5|g{*^T4hAmHs?2F}Nx4u>pFq*Z^K_3C54^S?G+l*-G5qbI^p{81?U&Z?2^?-!eXwEybkj zrEx4XA&3!9-_I#Ht()?96>rEi&EnZz;Ch)mMyvbq`6x;#)H9?(AF}cFMM| z2z?04g{RYf6smSV0E)(5Lx=N{vhs$4LJPR%Qq6qKFOpvXtG=?%W=_=h471*GRJ{cH z?(5E}u7Ybanj3x0E;gIm5-!d!OuN~n#K<;E4*In$#XMBBL9drbHM@IP*RI}(z7lt} zm-YZ(xy${VvkZqevqM2l{`b8e5mA$FG;Ih~a1YtT8gocEr*f-3yl>*ZgctPQ``clz zvao9p&D=5*M!sP0aGXbqS#-FVv(nW`V|&Odp!xy58vcJTi%lH?{D`lQ{x8d7uh@30 zK(3ckGYMtb&T%8=D*6SF1-fNr-~K*re<>i9#u7-Tjo%*XjXF5AZe7kRe=9$Va$kXfZ_*1hNwn{ODa>c>H(}^*Ez%SU1ge6 zk>1vzn8ND~BJcDsKsR^PJ)A{mZ%4{nz#J99^QAO4i?XP>tI3lKM^meu!hE!#&B%3`%G znVd%zR5ly4)lrj6cPmg46UlND=Dlx7Z*l=>t+mgv?uZyNE!pU!=-Gi^D#;X;jC1jR zDb;RP`UKItADNR*Hm_3SS%`oICIV0)zavG_71#dMQ_ZNasr!CM`$EqPjf3r0n_ZWj z%9TU~GD*%Q07--ZYz>{PYxD!LKA;EVix<8B#IrUDAp!3>2%8(R=?|Pc5p4chpv3 z=17G|$-pXMqc5kyRzb*;bAdVT`m`(O#V{kz!k=&P&U2i5Ngr1TGL<~#yE3Q@uG$#1 zrkf<%Ou3&Q8F=9bwc&NH1&L0QNa1-c$80oiMimO21|U6{;)W>Ax9)Ors%?J7IDEPY zyzPM19e9A;s1#eYZZvFE{auo41{p7!qrkIOz8C#nJ_&WUqE3qfhqI6`$ckL$)wjg4 zdov5BherE?U(e+1zrSafi)fV_H82SOdMXyjl}+-pU5g}zHQ}KMl&jm7C-For|9hAe z3x!g8L3>i;pNd%3EF5IdC&%=+Gg<7$$|ti9d0`p7vOd(rV`=m#xR7mu%@r-I#&qrtHnKJ$dvxMA%H})Myn-YbM(Hgp?%q! zBMId?@ApG+Ww1kWk6zEgiF=dxB_vTzA(yMf6^eM=uKQoQ$~&Vy=(dsOZA}+%-M&KW zB)c;9aCnTh=`A8O+%TAl2xWf=k3a>ckA7q@&0cyoWGwuk;vwuh6TSJqZ)zT)40Ch0 z5%tFi6UO@XcNum#PyfsCbj9h9Fm;U@?2@_bHF&u_C?Nj+;~p~A<&yf5K*q*g^-L#6 zM2<{FZjlQG)?|^wevO4zbNX3mhp%_`v{N5D=mK4;aW3dc=nkWLmswu*Xy$?@6E3z= z1tI9J-f4_QYF^|DZ$5*)(gyU8ZqN16e|_VV$RGVlc++;W)qsM}!sI@>SyJ9OSC$)3 zN)DgBh)j8*S2JI~be{S&-7j)eP#IqcKcuVi&Qn%e!z~~GN9+h3+Lq=ld*RjY*0>=( z=tN9q;)2py7a{+R?bi3GyAtmmafoTsa{;{~M$MdWgI0!pg(eHQ=el{b2`7;%qM;&h zxmC!SwF+Fq?Dy*CM=7Yda<-#)NIbZvA{nAW9FrpGv*#nVj#4Wl0Y0e<= z^x9(UL3GC4$Idh@;)cgwGHi+7*wvC4q>i^Sp=-j9;|su&R8voRh&@0Ac2TqOU8X0! z!(iLskh=HNneG7B3Zh>z9DJe^P@LgnIl@8ze%?`^scZXC^^>*^drXXsX!+Lu;uDcrZMK6(e*TUN+{uGUxQui3fc|o?qv7yIW6(V)uqx zE=h>e=?@mf1pIX%e0mlFkm^EB$d&9J4Zl;SiSeXi`HqU%XbJrr;WTQHXPDA~o@BPX zVxM#KXwKxPT)Yt+WYjX7juS(A@_lT)iBRZ|KuAhpX zGQh~n99=8P#YF8Vz(Wk5Y(n=cLPib-wTs^DPsiVO(j}{CU-w?sz%8GyW114E_`NAG zgJ>?r608C@7Nh$puteT%jI5*V{>)y|k~oIUmvVZLesU(bUH#|`{DJgW^{*Xt{5{Hf zm3)C~S7tD(QEz7$@RqLj`K!O>RPgo8nCr-@EWC55UQuXlo5C`!{=0CrMTq=M%R(l@@ zZzJEpqgp5>uDe^&!|G@nzo*0PM_&6$7%%;D&uN=OG$6rcQ6TUe?p1Q; z2doo--TDI$rWl5DX8>C)_c?~>6Dq@TIhDxo2R!VGZ)WNw1QIWdH8Nh>{%-BGev-zV z<_b*LEU~r@+rsQDVqBCsr0Y0&WM@(cxdR6F(TW^U1CJ9j0w_BwFoh5_fTZIq%DA4k zH~~eI(rT^3SB~U!4W@N*N>_YCgCDwg>QNitxfTz*ruGFbo`zW7w`mf*n#DJN{LCRc zzJkH^c)M=h$b?-c8{>NUlF?s^s)NeLiu9dZZ#zY*Ny@?cI;tZTax@ko^GN3d!dv6K z?^*p(03m6qWWJ2qc?W`4z_DZZ}h@twzUPFDa7xT;&|Lmh*GBZ|7 z@7XI>Is2sKE&$rg+znAzJW}_?aUi?-2MZA-pB#_H9LPl#=n}7wslA z*&b4G8LAtjSj=BP<-^jJQI;>Gb+(hHNz`5%?5L`o55iP>Uot6ZG}*G*Aj2v1UjFrP zVriAS{!RWQ(&P*BR)564h~x&tvvj*GO$J>14f&TdEV>gR|L3MRwty|#mjbDNH$T6X zSkw&bv3LYkgX&Bfw!I=R4u?GEYs!(1APCN_+OE;KvU3L3C9x7jXG!ckMz^zXkdQu%4)V^UK4wevR6d!axRe;!@o+lZqlz zDDt{pywW(!D>z_1-fUoLPpv~-I_eSv3kt8oQo;d~ldoL;5~eE3@&`9v<5@y|VcWOTX5$?Ue?k%%+Y)p`M!0R8- zqGvyUzMg!}{??b1y+BkIm!(YG9#oTA3Ds7)5!Y7nD0uc0Z24h}o4ugfs@;3se;}sd znb5IWXRHSLCzevo*}LAsB_~NACs*&nR+@%1+;|j=aow>eDK3y4eE8KtZ|LXhVC6mA zmFCJ1v36`#q0Nn9eO%RFGv5~;=B_%-;=qYHB^UlwA}HrZKHzNApq!oyRZ2jg8KT;l zSXI?`%2{{f_X=pDLhyb<`;3Dbj`vjB^liQ*Mn7NQQ<&zuz0tw@38Oh0#ph|I!?Yub zPNCf*($`-CE?kIAGI0T9Bn6uUbZdqwAJXMIRJO05#|((hr8+zY>GpiB_FWcAx;V8w zmy8Atb~i`bOqQGf@EV@>4>VO-cTS}~lT8+Qo|@yJ?b+5QG5kAZ_p4Z-*;2LikoC)k z9EoGaej3H9uGlr4#X8;S0Z}cK_m=M(vTa9KP$#D{e6OhPYGj!XYwHB$?PGSYr$5p* zXmj7vMXQ7L?3zijb5teX$T2m(jQ-%{&xhmDTVB*%px5y#XYLRMt)=UQ^x)dNxkWLM zmIa_MJrL#3g_lLm_+0K+Yi3`9f;XQ=a`RQg!27&1YClNeCZlH{!_f0I@ipT0KQf`v zE#mcUnpDT5XZND$GLh>VG39pDw95uDnYNx!kA$c{K*s4U%BYP9#r!W{h&>5S1$zYA zEYX{SJOhhQu;s3jWcu{QI($3=56wKEmLh5dmF#MmMg6_t#G4)Tc%8kX{<=d{xzfdP zUl)#vH__3-Xb&HU`f)WrC#OAUHa^R|c?1WGGm#Et(2*wSU|h!Q%)71$7y)VD^RSsu${`)PRT)z zdPB8<6J~V%&_4>_VTQzq^jPD#!NB7+5~!PS{{7~s#_ zzrlB<{y}O8|CaqY2HpVld5!D^Ir*a9`kU^%Q+>y_+WxzyohQ$aXEN6By_2xqx9<6l zXD)x;R6&km8Qpht6N}Im#|Iw=-^;Ul-#5pUNX~kL zbH{1k47_`N3`*R%vhrINRw-Qb6GzMyJ%ElJ=w&G@!@_w3B;ng?-v)p6mt1jN+O zDAcS>xLsKaSv5$znYw9ylIuP0>qwaTWaV&SD|lJ^xUBc`<=g4Mdx;84UE9y{Qd4#v zyUOzKw$TK>w$8(4{It-cx-*}YVW{iULeNh1g$XdfYOzNG)*u&8iYk#P^c&wntr!LN(CU<-ECU=}5crLJHxq-$-0{{^pj&ZVq<)&>(SDGmmoNbihxZqK# z^uNzE@DeG;`+2lNAd>sntz%lMYNyi9Kfze9+W4*YL3Tt+tY{Gv1E-JDx%|#u^})*G zb@wdtTog;|?J(D-LPqnZho9Xg)@chcwC*P0>YXo9+jT$-66^H-8pC!8U_of*cUkc<=Vaw-;cVdQY>kO;`)V$&DHMXW)ySW6edJV~HSNHzKhdrvQCTt*LBQ{LN(y>Wc|(jD{@0M@|kCO%+AqF(a3pP+M+h1 z?3|@_@c0-z`mFz&+J6+VOY#TAEAPNES{c+w~I%mbv;k^8-bSjJZbMV7|%;ULWG=vG@&kXNyfJM_yat!H+l7xu3?I zt@=FEZ!F|OY9I9S367Me=JG1PV?oMzbErokiR{{idiSG|Cl!l4j@rj$D1i#k^XWfS zROvG`1K{6;Pk!`Z%2?rvzg_5?*`j_jwdi--%9xJWyX|U>YSSNU+C1T6CU#{u#ozco z?)>qzkvxp4cRM7?dO^PW z^+TkVHIdqi=0mC&5$w$F+NP)K14UFp`-T>Z8kLJ!SeoHfz!xYh-Prv)<4|m(%Fz~} ztg5uJ@*zOkq~giLlO3PMdt`7P(v~DtD3$b$hyWOn^V?h{o%_Ob$|BZ zKk!s6Oq))An2jwtom78Tou#G|RRyf$*tU0(XH;HTvvRXQWh{hc^N>f&kx>`293PLT zMra>sRAM0rtQz{j@3uu$^M7131>dyCkoRj~SWBhRc) zRR_E_XVllRBtA?blQLhy#^oY2gB26oM6UwH z*1m%{aUTj3W@qJg_AhS(6-&wx3#^QJAq-Mu486JJA}X4AVlKRwyYuic%r=v11?EJd zIw{CYp*jV~j~V{jo@9eT?ljI4go?b3`+G%$#J@H#%JII}K@UOI^J@?kcf zVN8CkVUF`8$b2%s!;QowHqR!_U-pvuy_MH{8T_@j|MG4A|Fd!)CUETRT>o#|k2Y}? zR-If#5<9!BPpQ7LGp&6xI~nh5?~^R_9$o$Y@^jep0M!UXvYUg{ct+Ps0DP$lcSJ_I zBERaa{X14NUfhh$01-ky@tu`3`zi0IG_5kci&ZPai@)@hHshLGja@%7?Z>d@=~G*> zgC!H~-|Vx!FV4ed;B<+n!x3ohk-)n3gK>DrxqVDaDc|-kbI*Bf*L zyl$q}tuqgMxu6yj0J|>r3q9bJH+_~S@WAtP1cs%4yS)6Vesf;C{LE|ddu=ZrN`9qV z2e)CFI-~Na!}gsAqwjx{C(kN3++VT%|I1xE^!7!o_qCTR7x~zSPjU>)yDcXU=~#bv(Uq0^AXC6zCh!fCxsJEMKrbuH!X?i| z)rXk(IzaHvI^U7*?hc>+Gq%=Utb_L0>GDFS`se_&?v)OBF>&M_EB_*gP9%v?vn%PQ$K4?EF<6ej^A?{;iFZimQ0Ob{*BEtYr>o$rB12hC8qp+pLGk@qNWnkbvn^cHC{7 z?{*h@G- zW*NDYyG*?=8VD7h222~^-Oy;xBDqXrg<6}X@H*}V0rf}eXxDi0041gb!GCuzhe2; z?Tu-cPI__MdXGDuec;nVjO9I1%Z;Ch&+pEi_T<-e3wQd|uXH&R#m5+(Ni|QR=6Z1X zhX%LeU3waQ4Zl^Lmb+vf7(1AR8mQdeq;NoZFzdYv2+k#_s$V~h-!p!+rIf0VqMPag z)^X2gnkC2q#x6fT_hUrK!#!u173LS&#@^kDE_h`rOn>sh?;k8uBHbRgphOndB@v4y zhE6`X$yx7ge6!E$O<*tgA&r!zTTuDrTcqcDljE+aRc=uh51zCDwwsoCtG)U5J{|nXUQJ^gSGK#Nv`@&H)xwqPs2IvLtUQP(iQ%Y6A=K} zff?p)jphqar0Yno6V@$gO({s;S-_7EaP;&$HFJ*^dA)Nf$fx)}Aop3QEAQb6zcP0( z=u$j9Rx(I!fAK7tXIU#O=pN|bzmC!IuEpMEfs8b&rn>D)qsyImoVEG#xEp@hpxf=m z7^Zx4;v;FmrwJsubuh^`upB?TImtNXe91&acjSsq8aW2Dn9K0aROC2s`!rp8?rrXj zT0to36N6BZg#fU^H7p3 zoPSb1;oR|DCsApd-9Y)x&j>YBP!2G00JafnHwSz=aJ$ zGjs8>-5XUNsG2R$QFQSA@N6*&9bO5_Q@k;mptld)SgK`F!roSKY=M6(PZrD$JAzp(y2gV{O8@B}7c@Gon&81E=fTg{!7(Be#uf zC7gfH06@WGRfei>Y&zapo)qo!P<==lgt?M;K4L@ z!y7?3Y%FYCE);Z6li0@Mw0x5<8K@Rp{M6*--0X)CV=S#%+Ns&kXcu2pz}4OKD$&je3*b*>VCSnUEX) zTR~is)LnSK--cpk%N}L;{C;8HMVmzY+PqJE=+IsznCuMDuK09=60um}GmPdGk(pU;P&%@u`;_^d-5tj z--+FgH@Dx5ZmEPBwCY5ZlJy-trS{bR*345) zLCAEV86(^mxNZ!?GT$x{BoUW?qdn z{m-7S_SDJ%=Eaq*s2UC@uMVGc)1lie-&Z$v3DUqTdIM`UQjMjA#F-{Ia?Ud9elz>` z%xW&RHq689mIY<&;r3BYtk5^J_a5Pnzp>IcoiakR(3GaAzpM|lZ2OE{d1~W1hCJwW zFH8Scmxwy`qV8PwjSl&k5cvEcjMyrb`-up3kFaTyG;Z;h|6~hb8xmlktnsD@Nm1?# zZ&l&({RjdHzNqc=>jqde$26oAZHjl|f;Y z8_s@Q@GAs8m2VNHT2z~weg@!UBIL6^`q`LPBea_S9oNTiKBC?}_DKLQh)+T1c8L5= zZ{9BaxiE{sS#(v2J95HVbXAGbd7|11bMlE4@W)qMq7@LRZY`I}y!})XyB(VEqu&T`{kveIrz{8MP&MF!x*3P zOX^>1K;`rG&caux zWAjUBbyrRC$Gj~|Xs-+buX-2(YUbcyy`pmy66MPwpSzPn=F+&g_L5Th=uLCFU}?3# zHE}5~0o^_p<$zxmoP=kr2SPM;w*wB_oZ-@M7f7Y%HHUANJUj$hZk41O`UYE;97hSw zAHHq!gici4k&nR6ZG}Hp6F>PxA31N7M^E#suakI&34<ZpO>f{&6;vF-mYv0-nP9eS^MBbx0p<_9N?7gIW#6|qMt(Ig@hjo zwJ)W)=Lyj=4B>?Gm2U^u$<~n3VZ+l&^o5yeYS+2iOq!K@?P6BOSjx^tw6}ix^xAwA zZrgCWqPnP-y^Vgde%Uz$FL)1l`T`qhO4{LuUCYT*L-@JdtG!=5xQ=HzX1M6AK4;&- zZR2)UFobKw$Rn*kt2K`bYLazPX;iXnai~V>+^JP<@DFXt>~0n)Yy^64s?<-r z99I|goL#99rCGM3xnJ{idaDKUnU9G&3XHSRm%~tjbEXNyKJ@#NoaAN#9Jl^>?VVF= z&@!ZacvFW+tg{iGVayz0hWr zeJTDjRec`9)?2YHo)zoP(CNF^l=vlicf>^`CsI{3R7h6HaJlUwpL6cWc?2^esr0bc zo0Sk64$l%cR;U6jxP=PgiRS(ot2Kydks@x5M@TT%@AQ77uvOn62tKI0C= zZN2#Z5VTQ}ymQl0_fr4;a>l2VJE0ipboJdLpwpL-dbro?lVq(>ry0*IK%sutju)b(Qj1Q zUqfa~1K^YGZU;2Kh5KBotnvwJbV4-#bS{+AFBZ}-me8|I5!=rArSgy^Y4d{fQMN3{ z?K;TA^P*NP+ob@OW8!}YC9NTLOP#F8wEqsuT4ijPa#)T}YmevlOuRw$E+F)snAI*Y zWnfN;kMyg%$l7Z%wR4{NeehTG8m0*PS?d4WiK^Ls@aHkuHFcF6_SNol(_5TtfzP)+ zRV%XQAlH@tKps=|M2Xl-g@rVDbqUTT-N?Fjti+QH#J7o0h~qw)FxN-A&;5wJm}`lL z-Sm8UV`!mIEmTkZqqCyBDM0S`9MbT1nL zo;x*z354|vO@~t>P0YKJB{NMgcbJ!!Lo!xYDg@ zzN;^k>CW5R)7;qs?&$IY>Z(%=B={TRz=*Gr)NDMT^xehmr(<<|8U;{hplnVo`;7W) zV~EBwy*x5@0OGz!t>!`aZfQepIY%BD_!H^=8d?5CJ*xV-J34Azgo7IOb=m(5xw z)J-r|@cDM`^W#A7!^LJN(`@U)R2vqUDwmj|6>Q}Zk9kFS{?Ff1zKf|5cTdJWwci?? zEx~(y?=^%v!#GtIs4`!HtHX@S3WV~j2$c6XyTusVWXzBZ7s1_PpFIivTcn)`<>$lA z-<}FsL73V?z(|H8wQezeA5hX#LXB1uq*^boyP;+9l1BvoVx^|ms1oAtL)d@J?fs-y z#ubE(OdDMmsb3yj?wxNM$>q-H%r{BUiBsD4wVS-Do+4bgj9+jdAa@d`!ZX0r+QDnH<_aglt@I4jT%4oo>$@3L&^D^t26l0^_iuaKf+a}Tf@OBJoB4FY zQw(;zh7x0FVs5X|SR~m-njR5rL0&Y6W{c6;#mG+Mw%ot*9ki)!UM}Bu@s@;@mI+iT z!>*SF7+_D{(H=3X-cVK6_e;}08vb~=>5t4V-Juhj5ArfN4U{$E$5p5!d6~+M;`T z8?MQR4-6GIf&rtajl@@{^%Z&df&|lQX6Y9jH&*0XO!-GZ1C@F=yOD)zUEFZYb6DHM zQX%8b2gvkzG2XrFz5iVc&~h|$IsEQ^a!AUW%Brg~br0m7U`Of|QdYS$(e(0YG`+~X6OTTD+IR(`vP<@7!8{&OdflQ!Ving&wT z6a)4%+_?G!sPY;7@oJ?%j3`+U^GbQ76ItNRN!CNFCy}OQ`9QuR0Bj@O>4AEH;1_za zz&x_tmHZ^ZgwR;F5YSQ8FG~-frQ}Wh(013oVW4X}r`Xk8E-XK58h)7HpG&`!TW zbQmcaUe@yiB|y@K7J(?DusShRYJDU91A5*HT2LzL9qj$UzuAbGZH5*v3S8y-SzVjT z8zj4p<6gBQ*^OoE730-9+^m;jyRF`3`Hj3De=6(I38icIPO8>Fwjm@GkCF=HJji&P za@aI7!!Bs!`f)HDb0L>xj>eLuTVx@J6SFxj^IN^_00oj;7Q2$>mZEbAQ|Qh2yY=IR zEwSlgPu95?Jh~!Hx6aSSYZ#zvB->kBM^50S)QOnhZ@8_)(`j{sRFRH*xQsu0UazCdAgg8@;5~7R0K3@i@cN=^CNxfhnM%XPEw!*y+CP=lKF+=Pg z3t1@?$9uJs>x|LKJ6_Fkrz&~Iq(ZwPvxDgEPB{JRIZAAy%=05^lr);Nx2JhRfLCSL z&O;EnEd4*up6#*k$<+lj+%klAe*xDz@X&^G#y2!C_hOLFUg>ub3T4&`4A0hUDq z`?5k~iF~PjMSB5WMPFC{4`wfY8-#QJ5!ZL$;kNMoeP7jD%wap!@gH;l@s{@KRe)U^ z?k#b6dFXq#WH`@pnWgF~Y#0U~uG2-1iO~P3tEl=jaQa;s7o5z zHks$!Uo3h0*7Az#UMzCGGi|3y{4*zyE<7n)Ma5RnVHa=?Z0XH<2d_ZNF7|%^eD9$C zjBs7$^yEXZVCC_a&Ove7tFE;OSwvy!&e2^Z1g6zByTI7mRRdb8njlQqhaHA=q}?dO zUQk|&cQo@s!fjqK+_0ZR6HsZ#D=}kRjmXtOCOn7+*Cl_?{m8aw{N;fI>+Vdxk2u`u z;W>eJpp*8_dHx5k*bNPQAfyLGhIv`M;xYHBEb{dGMMy%=6@Ce!zG9x;ey4%kNjHV% z@k3oORw9I}_MUe}VP%iQ*Y#ycgXwnPwy8(PsqB=%<4b{-6p&l%j_qjUoQ~+G&hoh6 z)0jxfaxsE-4E|5$Zjt_-y>H!ZC@UM!*(V}s?cbn(K)32-mxFCC0F~;7KyQiu1jM!> zK&3p?@hV!4Ns|SR!H@9%tIcpG7OJv=$!?xTgaRXJI&26(Zg37=((tZ?GeWG-nD>x@ zvrDGp{2~WcLU(wAx3UoP<>O-j3@``GNW6@(jZ`}%h7m6R6YYIqfFgLK2!T=V-!b+dQUBPw|R2Zc^ z@A2@&1Pr?!)b*Rc~qk)lSIiGO#!y)xMgL)%siaD&_>x zO38QRWD5rM=>O80-VE1I=E;mY(%Jn_v|l;h19o|2KhVU;mp*JhX(jXQdU_;Lqg z98i^itzRjMOY~seT8HNB?V-+#JN0nv2Ewz6M^|5ayw}7c2-aJ<2GHa@1v1O(7?-}+ z8?DMm-!L%aAc?i?4c>?kc$4QCh23;j*+UD~#od4XN7?szKfUGXI&0c(IHv0H)*tb{ zovV+5uZhDPpc}0@8?9VBt)uJWF4)Mz7sxp9ns{Z%&5!>ze4fMq#WtGlm_Eb-(BA+; z_gjco@Qw8;kyHTWJ6i|xV^#Gbg+9VHas731xK=%Eq0@WuUs(E0al%1<|9~X+W0DXD zXkP=T7ymIXn%B4gH>TbC7$?p(@fe-Okk_$g_r%ANO03dmzj_L8J#M8SCn1#gl=smD zzDCi&1-L({di03*Rp;yb+;->-P>(_UAYYhE|Jje%vrZKpXl_14tgG`WB;JfAdj)z*}q@12FAfD!UXAx|Nr|5Po0b-;Z>*a1?Qym9)gNxH)oMbs#yD!{n&pCT5&F0U(4r$rwq=r?1Z?s1{ zgrN|?B^t74Y}c<2RoBPP?A0S-Z{f=6!n)$lp(6Y@fY;gnRi5hzj~{Pq1Q|?TFnn^^sp^QhZR1`H8*?) zEBd~zY=@*B$InQ%_a5k+W~0E%9pbOVo5Z}$LGkFo?u=F49XQXc4$C&)iU$eZXn;`i+-T0ETx3sL4ihM3{^mFS+m z2x`DQPjVz5wfvhi@jY89p69n*oPs|0PfLkU9~(dze-zBDC7ytVEXEmp)iL4~F*>y5 zlQF+?l>O_a@UhUQ%bKk}8@?=&9`*~PoSkFS8hrTy{!lQxb4Hv$B61yTgvXN(%aaW2IW1iThTcEQzPHcs=~+`Of81-V=fi%e zxwkihDnEpXj16NaeJ^%|xYz`_p0g7;J8=DH-t(EhAYiBkF!i6FsZd7BZx}iP6+eNW zI-tPl^5NSdaxm3_TdqEoQ5s+y`;LnN*%`Y?7?7N8`gv1m-a24iJHch6W@X%@J9n)i ze;#^p6~`0x1Fef+!LP0eiGQ9zD_h0B#6T@`D|w>U_j#gPf8Lyv|2TP@$9gc=E#B;W zbMg&vkBwaW>F@0xq}ECZs%B5#sb9)}pp%w(=w`3Yuy_%y%XtQ}Xk%;R_%l$ZaICd? z%Q^Dk7uzM;yxjF^wzcvklt(>U+0D{CG!JJ0FGbX2!v zL%+VR|KBI*mHS}<6q(`hxV52=-|`JZZu@$?c#wiz5enTq-MXdS?mYfy+OPe1sH8N7 zpa^GDP;LkDBQ$nH&{1Ef5)-q$yI6^iai3XBVE$dS(oJCjyU_}$_Gb&6S@nqd=|@5f zAkI7|?BT`8$5XHu^mGwsqCcJ%60|bW-7MI)bBYpE(|KMT+mqRMhu+iiczizxKy*Z{ z@C@F);4sfJh`h;rv9DZ9O8v$9PHB!_x}8i>O)wFeDM-WjJ3G2 zrTB$SiXDthW^u~{efEmipuj#Gb?Ak-J>`jZckTJyjEu~&oAz3!9_~%wc1nR`^8vi( zu~G>8%0iulR1i1{h#*)tszWRVBsjdoi~f?u1BEt|H5SLcWUX7@4wh9KAZQg3Qkkd@ zU@Xrnz%*EuV~+S2Au6Gdt_ z^Ud8n<^q$3H|>m}Yk%y5uP}CA3voEJ`5_B-ewp{s+u|M&Ad}ZMM9jyKU=4 z=KDPHsK0`ay07BD_JloVx{`xw+(q>+t)qUrdC$@Q{Kosrkip9g#?5~n5cZobcKx(x zE&X&joaJcV`_slD+4Ff~p_uNa1ZCL29)Q$|j6(D592+5yWSsRw5b{KHIT{;yvc!LU zeXOoDmwobmS-07`0|&{1?rZU&!OKk`G2tfgKbRkD4Dze)U-588Xt7p5`bp;{B;&vE9@sUnN%F`vA8VaW6Rw__@|@h(v+ zv7WSC=>QwJ--O>pN`HIoiQ2Z5j9pF(8n_qXL#EFYBGXg8u%MKcv>N18>UTu_t8PX3 zerz+nb8HBImaH`^O7pO30lLL?^A0|~NW1*x)Sy!-G&Z0z%hhr;i$UIW`>8IxL-sKOc@r#h#=ABAOq!O#8(aI1^ zndgq0?-$N19*voIS@Ptg{rS|O0fp*hZ*|J`5DOmtY4c^(YArK7Y)5XI|9Zz&!jrY= z{+`)sEKyrM_n4bzVV-RGAD5O>)?(|~2RZ#%jB2vV8m)6)+t=veeg6fQ zPPO!61TPkh3U4rtncH7s5))eR=yqv$izi^M9;({THB-KtXUlur|2ST(=x_4iW3<&S zDj0D_NfY-I2QkpGz6vTJzJF4uCQ3V<>lDOQ5F`P0Cih+0;DWO{lRM|Q z*Vx2jm?}qd+P|`O^g3++wC{li^RyBbl|KPj=Ps$VLQ z7ZhQ5o%;lAnx$?Ow6tsd0S)Ls2g|XA2Jyt7k^MRf4YUG|$l`$aEd^DBVU^%l|FiAU z?-3`$1>dTqoxT`p&R-i^2;e!k-?n$<73^dRd{b8uQc`6?(3Sjljm?XEq(e;5N$7u} zmC?;)H`pex{~yloI;QQg{~P^)AsaSe!(|NJkm9amxDSR?q(BG7-8+0k$8cx3yA&-B z!-~7RyGuFT_mh+JB)=yoCnrtQ{?X*R(r?my)9dqoy${q={}K-4{lYA4)2+eM?yi2F z+Ti|d>t}c965^Y#;*i{f@eeiD>8a_XFvaMp&6u7KeAS4Te|}(i?jLyBbR$Eu?9Ou< zL7nQwxVpd%Kw$gFG{4_k;7+{vTBmUM2H)2Rrz!^P7r&J$ay``x8{F-JG4c%VGA^KB*5R8Q5)ZMf>^keL^AC ze}7>b`7Cwd7}GXCR4Cf|Tl%)Edw&*?G`>GC_UPx=HK6e(WeBEeky zuc{w`R@o2^=uqn`h>$8OY6w5JpN(w3j^lt82{Z383H5$>o%9$uR4)rml8H07L6GAFk-&Sm(bv3LYY8Cmf-O! z!9y@%)!9f-zUJMN1F#D!f!E;iG-cOfrpam%8fYdSi5mDaR$3*nyVz#L<>C*sW0Nmx2%71UA}c{#U;uV;OLup<}M%W#Reh#XXjf7+>p zgeTOr`ris-?^In!#Xx?M8BQix09kjfWy&3VvL_guWQWTNi;9)O8uc!{lZPDXFMZeX zMa#j{17uo;B~P9n5$4*t2H>sb=h+`#&BvrV`O||&VK2MA1J@<(`Mf*B|IEAuH17TB z@aD2f8Pz^>FvWyEIpE=ArlzS**(G&en6TUR z+KQmas9e1Mlavk42t4JNam7*fx^{4BR6fe8xKO4EHZL`v>E!RrYS-2PK3Lwun<3Z!(~w^^gD$M-~Jw%sK%=;t_3qbZExP@T%zTbRnenlq2+-i;PRj}Xe^_4W;po;)a}D@ zyiPr!(--PEs#kUPoF?Z#u51<_g+}eq>%E=ADwtm(BH7oNqM>Ro)_COiyu=*h3tz5i zo37h*p7~jLN^pB&EWBbNkiPeH42iAxr{I8)E6p#GJl_4h+N(DIyD8!)Dyq$CZ3SUV zaK!6b0SAIoVH={TfAEGpw`->FLrI&(L1XsW>CcX=?JABHO|KHjWSlBeX@Rp#Dwyl7 zO`o3eS_mSylD|px_V3ibp=-*nOMvW(6oFXwswr_@&|5+>@y%N%>*3`?pSHy%^YSUB z@|GiO!Ca{}v8jQuI-T6Wd#~x@a>J5bR$$55RSG!c-+M?x4}h?bPFIAd?v!PxUrNsY z&kBG0d|un@y%K~Q=lp=ZAGZO|Ch?N%-b{}*pwn7imaLk4PT%$^!go0fIIEixHy3Y8 zOp?g9NK5BMdT-8t4yZ{@DAr`QlZURBV3%BGZlKaR7A)$4wX4z|i{(h_+%RGbuQN9{8Tg$3 z_U-PUgH*rj7fd&oTn{ocEA@0Ajm@h;)9H4gI_)a?l%~YRgPGdx`NYM-=PrVlVQbyH zlsF(aWP0AUl+}bdfiq>DAmKFeRMz(1_FUb6mM|gC{`z_P5ImEu!;m`P{f*DT0w1p0 zaP{cBY!fNm5GJhKVQ4|L{wakt!P<1*F7Cvkidwhs%NUJIu$#A@WJ_DF`8l~Y-_*s5 z=;-c{`^>ab(V-C^eh>ek9S(p;#}cYJ4XNC`{zV8^-7q)fiIzH3nskB}1$t!;d!fVZ-v@`MNkDyTsn&7kdf4+RmdG4J-Hk1r?4l_NJ*qwIU z0<{qiRuoLyk9dYA2eZ1&g46CDSO>G3VP{;7o#;liSxK&#G3x&Ek9lJzVq~W=b7w>$A}H zXm6G}>-5(LnMw||zKEaE3g)6@Ey3&_~%<~i|6tFf96zK1f z;;{L7XRnmy&LxW(V(KYE4P(IKywV9H#|pz`E@egiD~HwAzAHYW!9pCT=r^l$UMUV+ zL_=44p9w@8>tE?CY$tSg%+xYKf6p!}&12lt>4;}H!^yy{tKR}&y56VQLeITsmT|KA zdUMz=l^A!CdF>QYWSe0f2_6N2f*yebJMzIG^etGMj#v$xZ2LZiVCEm~frlKH5!4LI z-ELZISJzV!G4RIT@-}$@7QPeuo}KFX0VgsbWaYV=)8noqSgAT*9yVI4+BK*a&{rx* z&-WY-8xj5?r3m#BEVTJbDHhmEydUKv&d&4n>eU10T{TU8Pb_-amC|cJq6ppg3{gJ) z{)MuZG*uE5Lx+~gz)bU&uCgFIg}nbx0-^T2h9B9~i-VDh=WaxXYu-)6&v7u!sh%nzD?y3gb~`1OE>ThRnTrTG-;DJY5%GtEL`+R z?;_0I7S5IU?EO&xf1Q-Yg3s12|8{wUBWPd=DYpX-6Zioh5oxi&S_*g zoaOn{1sW3s`8b<&%UJCdd|oSGu1mg)^JKKWR6rdEf%mj{s!;c}j4}$5AAJ+B zQjFM^vvmO6=rDw;O^PW`fCy$fKc+_jZsNC`s1qKP3Yw2mee-zuXoI=@&0-JNDR=0G zukFq}yHrHu_;~)TtfN!t)inH!HJ1XN;L5V(K$x%G?y6GCA>c&$8!=pc@5t@mf!XD? zfGUTSGt2v!*W`E*SrH@+rsia3AMDaw@-0AHQSp>11W!%38&H2+N4i(lv zuhJ!#uk0+vwgJ&C<(+O$pk@^fjPPU;g7x$4u8BZm3Ql`QHiebrpVYbjRRv5hn+ zMa*r<8?JkSXw8|(fAuhuZ?nr-kn|(t2dEE%sn_PYC&zdLuy|fM9ou{5{cP%^9pC=u zP`dK|JY;qTcAg*JE_kDtt&qta*&RtdwVrdR5U_2-W&rwd{jD%m=OOx_iXYOoW)z}_ zfeS8_4?niP(r!NySJgU_O=W9x zE=l&hL@s-S*N0{&)CTL|#SN}CD7yMLU%C+)HAIqBYtL9wQn|Wx1((@nD7LKjo=9V<0 z;^)jx4R)_VlR5WW{=m*5N_#JuI3LN4kmDuw7Y|J%^{v3Zf)1~5Szvm|yU-yMI_IS4&swqL)n-FlpPl{4c zhNfr!+Xf=ee4NewuPw)A89m3W5v@KSpAwK&a zLDQw?-S6BNG*z{Hn_^~u8Z?e~t@Eii$LQw!??5xVU-K2=nC!%FRM81Kg$=@)JEH$F zq_c-J`=S@kwHeJimI!^m|@;gWm59F6Gy?a=u{{Yj8Ir z3j4NFJA>&jk~i)*%i?r5eH#wPe;nZ4F%sydt-1u*(-3|or@<$T>M>s!F|!Tx_y|s( zdyJRu`B}P*Gh2T8L)q>QciFpG(ZZ8g{T4WimU?iw0r?~_JK!_oAv(GIfmEfAGsUUu zhe&6!_Y))}M*1BScJIH)7&xZN)*Ep5yn0RNztq>t&L@Y;a-;S3TnItIlAA52^$m{I zuQuI!_kvBSsr6t4QWZ$8irKU|*_~hWqmogoW zEy6N$uYR?JkDO|ud0_Pte-0b!X$+-Y37NV(IWBgyOx=f;N2IZYc|R6Awj#MjMw6#* zGZ*U7pKNH}$`s+As@flw_QWNQwTA`qVN_QG#YURq1h>&!za0aSSB2Hq}nOA#J(y&EkFGis{7w_v$aXW7}@{tn*FSZ zbf(nKhiD3pl@H3e|K8WRy&?Hni~Ev<;xpah_`I~*2se}xx#Dg57E_1>IonZ3lEMLe z4|bWORf*$$J=)jwoNvu4A+>nj>SABo8#`^S7h4n__kHBmnx$MpQiM19*L0zz?yWYL zK%I~0%$M~>PnWn@4y^C^S=TeD9-HX&TE^P!wu7G@mfQmWm;?Tg=~V+8)%iYRB;`|R zf4~>DZ$`4z43VXBeW2#*uRX!EUy51EWcFb^0&m8ZEOQqRp>S|8J$K&yd3QuJq{Vd>a69TKm6gqn~jr)iP{rs!wCOn_wgx- zyG9B!?C8kwuzE*c!u+#93TA!TpQEyu%;m5zskhF&68G*3ervw(KWP04gUtOBw%?4F zi2i8v2*f#j^+&;3i9ShGiYi7Mi@?uXWzj$s(*X=H^C#4bu^+4v)4hyL>Q3slOE{=q3un$!xE z$)Vv&Al9TLx@)rc5t}-erqlfmy1RcD_K$O!>2FT7(LyP|P^gVUIVn3Voy0}vbH$tX zy{TkMFj61`flHgzu}PUCmvix{x#P0|?JdAea173cOA-G`p{u}FRV2OMW|eW&%xrod zc%(rp?5tL_B;6Rx9V4^VH`PnW6!({^DOF)SQikyompbon0R!zBqi%YgM`GZI)Csk# z#7d=pZ(B9}Lk8u*3MY1Swm-iz<41#evni!bK282fst~5*tEK7J5dOo7Ybf9FZ-tcV zOoDWZ_l#%gCizwGc?#5j;GmKAE|%a!E=4FkSIpdl zQ1k?r12!HY*gNZ_<8A97`fw|9Z1npbOg}Md1^tv;zgcw)dol*OB!>&t+@)BuH!u98z8{7xu)Kni5E?}fh4uEK{2 zLAb?mIUVonnSY{*INs$PrwS2$hhD7xOu`3qr>4eg%$`fiueQNYfgbigPP3Wu##O30 z@5{vasbrtvEOIDFS;A1IHpc7)Nvl$0DhCvC#I<9S!~M$2r(RqS@(u)VIHQe=*lJ|D z#`ipv-%n2Cux4aZ3-*bc=3F4mR-{{R8!~lAeANnQ&+zBhzD~k+B0_igwZX_sFnXNl zE-6Yf4XeW^z$q=Ng)JJhnO4)>t?ubjD){cK;&^#*4~Q;!AE)Wk0jgxP=0jTO7P?7v zTau<*+R2_`mz(cdNPX{P>bVwfyzeo^SD1{#*ee!2a8>7KZ*Th=;BISc2Q@Y|Iw7AZ zU!Ro!3xv%|r)02(TNYQdl% zbk4Q8@)rwvMA2&Jtqo#s{n}b+6v%mY`@;I;p#{Jw5q%o)-)KD^X``2db~?wpK2X)iTwQW138HvHfw1_mDHD8 zV1FR}OL^ZC-k0Af$pb2tIWOz4(jX5@2O@to&znydpUQgFjCBPs811F^)XXJ z!cML#i`Z9jsBl7(1HS04^cK~Q8Xtu7P^)L%7&-s&;<--|EUD;{^~;|hG?^dbU!ML< za^P3W(z~vo)j=P}H$6+7N&P+~$?_nn<;SKM#3riEv_!#s2( z4VIq3)1b3o%kNzKVWgSD2IQjfom_7i21R#5EPps!g`eiU+eCuvPt&$@_e^Wq^RhA2 zP&Yc;;prjzBPm$Ye8t<3(LX5zeokMP49AIaXgBg`3#CE6(xXa%&I!0wTYXwNmut7S zCt56(DWgeIWE;j9<;gVUWU|dNzT;-v*gW5TJW&(*xW9Z)2^5c1>S}4cX;-`b00i>taQ5iwn;kaR&Q3dgu0-mzjd0XQAB)0Akf zZrw}oh&{R4_i?q|zqj??Ewm@dFkpW4`n^z@ttQ78fk`rLQPdC>s6Qmt3K{lx32g%r zdJKY-;XK-RZ3esj2Kja2geFm@6h7-)+ipz!rCd>6y9B5>O@aLz?7ox7*$qO3-@nk? zxBHS;rDnCcUYuW}8+Op4FUkallZF1^Z*<@z}ra)r1Iw#;!XM(x3h-~bE8 ztKTWPS|`8#tm8a}7d}2v;Y8A8@uulY0oMOQd)nOKGFbCga3)H$g73{mSWr-hxfGqv%KwMuYY;edOQm;kA~z>-o}Q z5&l+53EmlrqR*9=za#3AgxEQzqFwvgJl z+np^$omLrRTHsgQ3sy!vs>D48E5wj~wlJZAj<^}!F;UsfX=frKd$Q3ed`6aZK!ttSW z@`mnyP}LT{mC*OvIxgF3Zad7i^pvPJ-m!yXRknq$IiM9D_%2PO&X+OY0Jtr?5t~5^ z^ms!zzwxJ(WSBu;^|#`YBa@>nE3qT~QlrFI6DF_c-BCO}y>;z*H$zr#3Z8k@W!aht zpeP?;ipoedisu;+^7W8vs8j&Xn%EwEbk7~gif$rNRR7UUWTuz_hL}S4%|TG_YlP|~ zUuoRj7A&hyu&ik4r*UFJ?VP()>D33FyKgmf6rB@%-sh>eTMVUjq}4ze#deAd&EQ(g zRE?OFjV@O7$W_;;Ne;Geod%(|t1}8V!FUO4xe6_H^1clUojJwi79_Wuxq{jb_}s^j zLnXtvI}eU=?78NKcj33@`+{c!_)g(-2t)hlu$ei80WMP34?sBUpkJ3vm=HTmJLS71 zo;p%l%l zOn$yDOj)Bqjvde=q&uM_={cKpSz}eAX>3zHC%#m6Wpvd0*nK_(NLJKW} zjGF8BBHbCT?6kU&L%fyZ?7hgLA<)xSU8T59GhRzwnD3SqO=Xi1Q^{paFE`8mwZh$? zufG$cO!WuEfNw301?ySx>SQ{MG- zBl~C$%Yx(BEr|!z?_}I&^vASZl7eIGww8c)WWYl$ zBx^Y`()yLKYk4+Q_KPjVr!FwY1DA1`kH)phMeLyTqF3|Qe{rkb7Ak~KEV!sXXz;O} zEz=*>*6fPh;hcWiDBhmCpl!%_=sICajdcoyvA@q5z_b~s+)Cvob(yFjHv8>(K;z^e z-5%#RxD*KNq7+1G7}f5+@2LdTjUv;W0Aa9PCN{x(^d`Xp%9pc84j08c)%Ah-HtrVM z%R|;Q_uIvl&{pz$zyzyPH&d>Va;rmz5^_f@=~L6KIUJr-515m6y~lZs$9EiXnz~b5 zsOmzG+KA_hVzy0sjD$7W86MSYqi>5WfCXo=5RS?RRp-7NpXLG6z)vUV^qhlbo_*;b zf^|zP7g~)Y%&k!Z+-J^Mk9{z@w3_;y?0QIOZlNkX+Aq@E@}5c| za6Lt8RQQ_2bO(YhCrz%XFqp2`G!mwh&5$)LChCCl4A)nDJvmIx$qG>Wzu|i2VDhy0 z>A}x%eQ3Pr8>i%n{~fL;YmW&NQwvaPcVCHUbiBu_qO9%r`d@H8yA+{oWLeO_v%Y$N zb4d~L4A(pOw(!~|X@VFLga-xAv&+Zghu6=+D6N4?v!Z1u_|tkixdU;;3*;xoGMXb_ zcVGHg>)ZchHJl;TZmw?%DU5vk%djwVgi_m~ zO#hMZwU9IpnX%(s|sCu6li|CV)rb z&1(_u-nuMB`tYI|1QT$>bN#)u&zUdJ7-%uqV&l#tQb@B}_;|I|g7>6C5mj87chXjY zR=p@O@~ykvM%GAtvfMUM#=JU8H)2SM$*s!9iu;9 z`>|D4ypbblm+`sixCiCi_cG?0N#&FZ4|uHG+dJ16He4DXjB-qh9=pOPCNabf>3^*v zCpfvT^O-fJc*z3`Q^~Vvj*ApHvf2g0#kP_@b9wz{+t=tBsgf7#;0zLi5?(h=Hbd^H z^V)N6xm`cD=k?ET##k+N5mCa#L(C3Z5h?8H?np1+L%PCXozY(VIJrK&Vr8z^9G4_2o3e{-4E)W4)L`WSZ2{Jmq$hc)sf=79HL?pR5o$g#v z_8R@IjNT4}Gd}sJCD9s8{9hnYMWyyP(<9*rz4st>{-=fVo`(F8EGjO%1Bv7}^JJg( z{flTkqP-+Q=Lf38=^xd{2LqiL>56M370mn}G1@eq#2QE^oGmP&Az81Kx$UZzO z*`lt=Mc#5FU2%9?Sor(U^s`PubrUs8AbmicZmD4>~Iqr6cd zOY+-j2-i1hIHuHVaj7hAr#7q15KUtj$5jmA@r$87wQSwV>?oesi!Xko@ZO10nHWx> z9W!@$W@`SW_ApgMVUR*wQv4lLMD0F->)ijSgU5J;eun4SlB6~5HB$N07pJ4`(DQB4 z2Jc=LbzA9eoElSDRfJ0U2ak+nx9*UK z9z0_!z>DMVxs4H>RQwk6b^4podwJ|!VpI8KmvFvl_D&fhPmn)+r-3B!%i%JaR{tNr zIgG-p1mchED@w0WSad(w5BR8cS)8;pMr+?OuCeF?$R#>-$Qf;Ohj#&?}0>v(KHgZIj_ zAnhSpMSg$a)Q;BDlaOzIXs!t0cU&Z)p~a+*Nl3R+U9aNBY}gp#VU1@wjuyFF?1rXg zy!q7%pG3^75YO^T*D7OylHYwWdBXIAcbBVeJ9Xs>C;1xl*#p|I2kIWqQ{+jalN;2_ zU!zT({%-;b&Tjn55xyG|u<=g{H5n@%i_{98Y_L}UB^gb8uPG6>{`{K(;X zAGb8%u_vV>ro%kRnn#PF-ehXt(?>}8GBz$GnZFvV_&UPI;Xc7*Ve66vX_&!TI9i7L z>f5~)HknpccyXlDJgIN=Tx}+byHP5MoYG#yN-l zJaeURa#fp_iye;aJtfmi=zA6D?W#jEWXJ#7?0X0N9m}Hn?*KVeaSriEod;%53A5r6 zVS{x)Mz82#)a5_ekvWnVLjsh0->ixiDII-HQX!w>Y3=)XJ>e?x-VTVq^%245vS>^m zQF*8+qmdrc&aCS~w}r8m0wVCzaQxFgxu1BOGAP>VSE?yR8Eh-5kPI@Ni-?F>rH?DN}c4he#6ma!ycqhl2Jclj>UNZ zF&c=xF_w4{=pD-p2hpXT5(fD4(^Av~Gk%E`6C?^>F4YTI@V}%}*BwFjg&4!dKV?oU zlWeOOilXX^eUq`p)7$VlK*wQ;1inK+RZj^iM(O>h0y7_-PK;=r2c+EzsBW(E%?*E0 z?=?ws^SdO-DP7pbVlMvPCd?Sz1g|A=uGm3Re`g$_A;SD2Er{CR zbs@K?a!@e%aNu1t+lfE&Rr8FImAFCnDP_xw*8Kds>=kU zO2uIOkWetTr2#{$h<4gwA#yo)Idma?Ta*}aoD?r<3t#J8cp^YdPi`b3?{ahC3L<|c zAIe92MrMR$E;r3Vnwtw4XBBsgcd+)&iUln{lEaMl0g`l(Au*znQmhF;n*_t~n3YjF zy&meN^@-Y&=rN_N8Z7mCz)36Px>ben>Pc|2^BB_mfX9}S`r77$b3EPR=hWvE zNQQgJ)vxE5+J~TRJ}6pbd~53X%+R~~Uj|hZ_{E-Yk4LiIrK93&-~EtfqLa22RXX16 zoa?`l@Rks7{QJ4Wx?}&>RAuf4lG*b()Ejssed@jYNW|B8f+ZouBYv^@!{7_h{baWz zL6H=r{whUiCN=3Ci9V^$-!EnLnQ}xdy4xV;C;C~P0Ie+Mz&v0bmb(bK+mH*iD$No7pSoyLwV!4x{M|HP4fefr@}U~T>@~B@&$gWaq9jFS54{K4 zFP)Mz)}T$ohvot!R|4+(0`9qu1)VPHLL;uL?+v>p z8;LM2{Q^{a$HpWZ(J^>J*)!lAUD?|{-{E&EIy`fZ$)BpeZ^)~!UtV|19xCwQdzXXcDhmWoPX`qQd}#e zoa!KHsbtvm{PKtXl+9o>b@Jt&^>{L_I`w6j2#*)qKA(sOHPMw5!u062+lvvI0^x5v zpS(@2?B5O_N&%oq_&+yuLP?`SF?hDR-6lDZMM>FlIes|Ko|Ns=0~}rAk-20s+Ma&p|UvL6%(&A*I*1O=9l z0DUTf%s!X4UU+5EZ9M{o_4$p) zIsESQsb$M({Go?p@?kb+3jxfztzJwPpNAmpb8oAs^KQEnAL~w$Ohe`IyzoZF^WvZ_ z8s~n{BP7{q5rX8;xiy*;5cf*j0_Qp)*H}4yReG#Sz+paU2#_dC?_KRVFEFDO{G{gt zl`Lu%eEm5YK2RyF?pWqCHtnF&#(3C?488J8xt)FCS!&`)MCYSrG~gu2WW5m8%>0~M zKVz8?JXkJqk|FW^ow6!C!azjDVw(&fZb4b@K$#Q5{GK9Ud`>EU-%t9Kj<)n3^Lu#| z8jppgu;6>2wI7;*O?Yx0?UQ+!D4Oue@77-rZU}5)_tkGhm=EYcxhW6Y*)HsVwv_Z< zK=HNwp$$VZrGZLnCY6 zlld-0*HP1@O-_#9$4WH2E@!_*Mcz4gdZoza*jfi~t(`H-pqKA);B_U(l2Q&=p9AMiN?K~gZl(sVaN=~H&#a|t1;(3) zXyeXl|1-P|KNG~rTRd}vvgb|l-41W`HiBdLnd4_&Ah3`4)*}UdQcoq z{Q1?VexT%R`|pGX{dA}A+#QF!Y4iIAgW&irzVa_8U+BQZi0?o8>*NTsnyd?Y@bztAg{>XLnalZza)7mD@2fq! zF$Kk|na$#vk1Zi)lL(0LQozZ#fQ7>4-QwX{^-W4-I<>Ou;rN*#67^8No2zQl>0vjV z)**hAP}l&wuIv~Q^)KyQparf%_v@mc0R5JuhM#ZJ^pdn9SHQDS zBSNY6AW|5=+D=aXp{+ouD!k;Lc)fDOfS&`fc&ejhU4Xboh z6u*tvk%+VcgH?j&&tf&Lz{Y9>`l_m`^=VC?S~YSjl$Yr?kNtJ(!MI2)FXDRvNqtKE z;L?3vSH!iU3jg8u21IJg+o=JGwgP$619$3Zh^EZ<(SQip$TrShh`w_xUe@5et}GN4 z1Uww}}5kmD=-)h}_nVUUO{XWT*THCU` zZ;nmzw`cquW}|TEYfG`sqT~EYcHHT!pioHcj-VTTL3NNYj=~@0!+`-c=2QdPs2-aP z)K8drfy07l)&g$&bWeQmk~pVZnW5DIQos7wEA##DYL^#Jvu3j_()-IOW!Nq|tJwB0 zy4yj)4`BbWSK#pT{)_V78s`-JqLXci*mvtQNl*ZlmUZIf{jNwJn+=u+kx?~+yDYyr8bpL>aNbUw@njR(&GNIf^O6f2U;qskQKLKK@??C z(RX6*3R5oq27;74N|Y*iUq_F4WSI!!cQ)d z1>+>D25oXldls*k!UNtCn>ihe0TxYTn|k^&TM%KuSJ^Yi*40a=pxSJ%%!yQyl}A>0 zDwyjK;m33>Dm=0MCX5edaOUWDBX&ser?l(;4X3XXx0RR&MSJHSuPIBE)raI;H`(he z0RPeaAIE$C2TpGun<>hNqhwt!+cV|*CBgFe1<4nsDaWM5$m0Kn(<^=zSDO90mNz?F z2&kN~`q2MYIz0p-7!nfV?%xZL;cRVuEn|ac@%!_EDu$H!cV}?z$4H|H|8@($R6M47 zaom$hX4o3{2-0${)DZ8q*qDnfoOCNIxN%%NLEt;j&UaTL{6^BLlZ&%&-n@;u!g0t0Oen)wFx&u>_vGcMl9s4+&f3d`R`p5b~vb`DofXA-#~;TtMtB{SbH`P$uFKW z?a%iRG}9eMI!01$vYrst zOi{pxYs5=@H-B*+ z8emBapG$Dy$aDai#f>NLs8A4hu;6(HJdwOdR-_+U1L&W2DrPN#(SBGCWk3;slEc9@t`T& zAvBenm>+jdvU@dI@9i6faJXT}DZW;N_MRXuNY`?i-W+o({xmxya~ek9Qj3-WOaFxA8+mI<+$;zF81(WiJ)WHj;*he zna%P#F7IPkgx@MAROl6k2E0^ocbfF62p*8Bf>~&HM}|u3KdjI^4Z@2i*BdV@zbS+I z)OA>i*x%efgxy{HM1*5z-f`azrAEq$=1{_NV_F5bo0KC->e2xDKGIaqJ_ zR5)eWlWh!>hjF>{!YsR9XGHw^fF_=Zm$}Al5C%PbC^DmR|MJu+bOL7Jfq3G1GcYJJ z(8HkDmpJ8R(>Ef~E)`<=^t;!pwcjAf-K_fLdMkLw^_tAk(^X|uRb|wlN^xlY6zG_s zng0GUcVPH*`(%;CdQK-`$-DV*h%uXjA;$Eh)Sv5rLFCJ$?ygcyVw#RhFIV}NcAUqr zx?@c%4cxHKv&z~UpX%g|fFdmb!Eo3eWzxl_@S@RJNFuA7jpDs#LeiVdO0DS}aAh{lX;%O`u&|Eh;#sE|BCAzpWb;8dwuPu23MJ}9~I#2P(w34%kK%ENo$ds}YYqok*uqOvGqiCtr|A^JauH$Fblv^Tohn~^*dQAO zx?v@iw38sB-AdYAkW{*lb+ehZ2$s4S-$tT`u?mmvTFz6@5!7;>@%fZi(Sax*Mu3Q- z$o7LQWK!}g9yUZCsPcO zP%>kayuf|8#M4ilbQu)fZ{#A#3a#zUcE8K+@(^1zTMhoU8gxg5ktOZE_%okKfWf^% zFo^ZM$p5nD!(&Z?MffdpxW-_2jARUsuDz{54V;@lQuKa1a$VWh*2AlJVGFGR7Ty#5 zKs1>K@{B2+i=FSF9_F4ld$Eu#BH9m?A46OPbsckw-uC+$9#O?RH5m~1>(}1u!JjTM zMsDf}T9R-nD#baFDEAZ>?)4{HIogRpNzcu@#vZok92KJgRvvOwZRO4`I^3+(_D=o2 zK3}_4Jh`VHNfTk5`52VoCmz%Z+~wB2Z89kb@?skB?`Z#&d;MfrnbER~KKe zd1^h`bEkQy7xnMsmTYjtN>oEE7V^u9PcJW?v3brm$;a9~zX9EYs6G5Xr=_Kt>)r1J z0FJU0p;KoaLeQR`PE$ed&D4#}Or7BfRra~Kb5p@SZ&%%h@1-t+H;24b zL#9F(cI0TJ5a@)^Q!u;2)}gK9|NSM*?Ue;lKV$PbH*7_+W8r>RPxsDy`@BiP$uCc7 z0z5N?yxj#4Cs$Xw-S@UP7u_z$8VdZ3l;;!BlEp%@8?B0!(v^=FSF68?7DMl>1d?pU zdLwpAukz)iGvxkOVJU!XcqMgA&e);V;_*Hn< zLOEu zn9K~afW$Ysin1qo&aGn*jLAgFTyLzA)t6yrxH|^B8E4quA9itCBjHMM?^fe&3N(&Yc; zHgsIP9%E50w?cA&;x32mT%y-C$|Y5qCTMQ8E1|+RIR4^i4O&;mv)mpYE!SlVst}yK z1RGvVrpp!2VU`%}e=U=XWbv0d$iL+Gh?ofKCmFtJ=aAXCUFW;AD^EYnh{h+O%<2I@ zBbx3w&&EaIUT>Im$@IOG$bmKChrfh4SgNnuYv^hKAW>+P2RsWZ#+&o=M6kt z)Y^x;8C68n9D;Xi&m2bYL;`U>>Z83s_}eM?nUS=tF?QEMZG2(l z=y6I*p%iy%i@Up2@M0|mifc-7_uy{D-HNohyKB${w*bN2EkKZ)e&6@b{ATW*JNJ)F zlG)w!Jd=~`&Yqm}dAwEF)&FWOUhG(Rj7xrKwTYpP*$NH&0Su#CI78RCr%T3(@q2#} zc<+ZRMfTteVGI(>P?b&otZgzC-254^fD^p)@to?l-Zq5z5cBULCLIH(=whH>7GxEA zh?OgAw5&B7Qa@=9!yLw1N@XOk7jlb*bo{;${h`#&OdNI0Vi!RsLniq z>K);xG-DgK`ET#hZlpK=3&-`wOP4Veojf0Om%WgegJR*@Q4PU=z+kAoaNEkA2IJd^N!3y-t7yRLO>bj;^Hh6i)6uQ5z1FA7dllBGVtk{$C; zo9Ah|0&wjeS<8fukX0W2)8?Ns&*u!H|H3&-Sw|gE??DgS5=SA%=N4EWUimWo{&JOK zlSeY2sMO-6Czl13bz{SQjcH!11sLK}ezAO65mHOvZo|H7wC4+R=Mz}JuSImj`0_0v6ykO&jZuupziQCun^t%ydkYT;n7XA+pYZZ%(4rjk7&=zLxZ)d06Q}N zBZl#9B+@L&p0v+}|DsdPcE4~reGr|Op+2m_`}!CCXpSC#|5vDsd$4HRgXo|P^=4Jf zUp2WpLu~6{2JU)haFM6#nwVj%fB9UM(l%KeRUXu5dnSbPC#)Jo0t=K<&~yRFB{J_;%QAd3v2tS-`uFX&}ed z%MwIdQ6LZY5zvQ+m8k~31@~XG9;#`KTN@5E{lps%D}f9wAI#0USrW|6=~ym?hu!rg z86PfOxi}9_E&?AVRqxGqkk~vE5}RM)cXjaXkc@-&Z@2+xdk~n{Vjc#wruQ7EEenj>nuuSR|@+M`JL1Vga^`eT@e? zOnLX+Dl(~*DeAuAhGNl%%lwMaJ&xcy4fD&i>=COMbg|u*Ih4E}SG1M(52coz&Y72=JcIX$3+AThC~E$dep0S9K=SfPSDv7! zFXhiAmd!zM6Xw--RV)8qPUU^GR)E@L)M&QC{<~Jd?@RLBx#weibe3$-WY)R9-pN1W zj$|t=vbjOrZ~5MOF&R3- zj_)EWmGK60e&p_}I?{m!OJYJ!HZo)-+F&a)knh1Yt3O4l#@$6NqfV zd?7uw{aP7obrby--i?1t&Mc-sN`Z&#?gb9bmge zL~8*QIbBK4d`!Kz5b3*rjYs;y0bcot-C;Y49E&9DbAWQ%_4yCs=px+Uu$GvVCZ36{ zhz`=|PE~9hb0x^SKbZ9UE-V9iqg30i+5&8UbcM5e$O+xB90b118vBZ`VwV{0>)ZGe z(o)`{?<$aqB?>n}k7c~tJ6N;6T)(ng@FF1;ZHag=Hf`xH9xeZJt7o;qqxH+6Rseh` zl4xM=c{RzVP^s>C)Ps>>pJiD%Y1Kr8LjXkiwUd2CyTuo*QaJ3(g$x53`Xc5+ z^>bTEjtzwK`1>7v2UW7wHrq!;xAF98I-~S5YsU~QSzMGo1JOFDJ!W#MtY0>mnuVU; z-TSf}JL)vSUEM0JUoJk{;5!*TRcP(xI+yQ#mmr>O6)tXB?KNFSbU=k6=E6@QTFIi&6sjne3MbkvcOJAxFKe-U-VgjE~O1BG0NTbDyG$ zF)mM$W|wb*k`J{OrImMy*RbOOK%s1t%jd?cgCl=mYYqJSZX-ffd&eu{bfInx&`YVV zgwJnIHxx_*9~7vphlg7-Ky&>>?>|>8_;z&NEd-O{Jr!9Zuw*{K z|M~Le?+!$Woh-i7Q?*CSI(*{2cOo3cLs2{9iDmSWMH4j>=>v$!!g(wuI{Y ze9l%<*^#E#*qPGA!Y?V`w)4Dvq|rcybrEZZK-+E~+vX~-#xl*eOKdM{vs3Qs@%Is= z;Zm+7WEEXgzOy8v*p8nnOux`D4+Wtw9nC(LH}6)CZrNRCw)NPZi#mh%_GawgP|lAc zC@#oTV*Y~P_z3i8gnYf{e<;{qxf79W)jqO69b7suUJ;k->M#^?mmKD@js8zq$KLq0 zUdogII5us!v~l-st^3rEvy>)(^)Ju!7z*q!a~6X6`Q4kmf-okrbRNRH)!sVq&%%X-8hweP5Tl#wyYh)KZTpH zkCuqS*Auph=ey}}AII=`g9PEVR%39cEY`Tjpk?`(rKdZ@XMddN(7JBn z8?jqAQ(n=oHy8iNX%zzBx81bWr%be<9QJjjvi+!r`B>1K(+k5{$47~lYIpMrl?p=L zR1bMq+leeg)F^zvbaxLv>~D!ZX8Ad@-LCU%U3Q%tjfyvM^VoKFJLjm0ZZHgR&-;M? zLX-+j(Mw8ebx(TbHqw_L1v9I@aa5Qcc5hb>8?K>^|rxk z!I@?C(=buIG9h2nESK6@hf8q{?~;8Fr_TLlJ__|ai$Vzd-LzG9=gBp~LgMSl5@1Q$ ze*P(UYqpGK((+eXPDVxw-&YcqJKe0Mrt{?%}WPY zY(CF^OX|A#`%++i;PIF_t#!LkG|n}71dkN`w1^6I=1v!6L>h26CZb;Yv=6R+T(j~{ z@J=4_rjoAt?Wy;leRe|c7m}1m;^X3u7WNr7;%ZWXUaA%AQ-KdnFZG11B0-1!98v%M zln@)Q#B)DjB$*OXNy&DbZv2`lq)F3{;Sb$AAuRNYzVf_ntUy1sazATsF)`AtA z+7WtKy9kY8K9)J$pu(exTTmaz+shdTD6-`@BSwmDX{k9%!qv8B2oE*;QZi=3mR)2U)(=_8sJ&<_5o z29&Z_i!vr-6IBSe1`qs_wluF-)gM(%@=u{ z{dNMRET0*xd)-{OmQbCt6(Z1_J%_wV`YkT_a$*fE`2GPrp$@!8sP4!N9Z6MBdjVVBEB$@byy-H5rjU?o57>)vqsX#bzoPTb-$}fa7ko=`&ngea~p9%FPx!;+Hu386L z<{in`BF9ckZjMV#WQtAr;nZ+~b7nY8R6H8|45`B#4EWsX#~`TSS#)svBR833*r%Zu zH!8S?2)r7wA^EM_C;J~B&jj*$yCZ4hkRu*~F!M)@*V@yTtV-@RK^$N>jyXZO=w_j) zk%)1JrBKJ?1jv9-O#nh~G;*V3YD2P^U!~V)GQxxYknGqL^Y|h=7}56p*z|v6dZ;=3 zNy;y*O9H9jXPJmWWXi>>lE?oV9&(^HHR$o7scph%cj>s5Yr?N9BTM3rR=)+_ei}$YV8RK)u8^vl@ zbAF@>lrT2N-v-F~l3p8OUI+DN_pS^Xt8UNNdUG0FGGDiOQRvL0Ljon#Vk98_&BBLS zG}joBuMaRJWQ3ngu-WpHzLtU46gVoenjvc(!SFV2pB z(pS06OXDLO`}*5Br2apb&U~#bDeu+wFWYZ)t!HX%u&N%f)t9B z=so96|C8voky3z`@rjP9E;8YfA4dc}Xw>Jwf{{SLe>=VTZzsL)J2(sTtyNXn3F6rf zu2||}bPYc|Ak78kjg|SkqfeUTW8GMoh89raO3(^f+ zOZy~iSfDGW%=It${jo&n&6*2#c~xaCjd2>E|BS-xSS9fw_wV1p{U&4))q<0888$Fq zJm+=)Uhbbifr@>vsS|aoxz7JyL={Lvn1QR}`Am+vDGqcy;x)qKTW$_i?h#aB&Op*> znVxm&3Sn+3%EAbAk2rJ}T-;atS}=&e8OWcYT6ny_TNqDV0`KcD1>sitSzd8W!Zlcn4kcr%yzd2rk>Hv9EDe;46lX-s_R`gMga*mfdVw@YDJ| z7t^kwb5$HPwy&5pU&StMzY@E3;&bl)9-gIA1~M+16iKTMFv@K z@n^r^cDVR|$P(HXJM0XuG5utLK*eh^N67paaoSpn+$G2WPDpK8i3p#*-k|cswwB7X z=@fr@frIlz0|T_3UZke*@2r7O_Dl>iVHcP8*)?y36QzxR?EqDi``dmz7RPuP51gcJ z0qIA6Y2U32L4o^xB@iK#WA8Trcvki@Q{j*s$BWyFg^eA`>O=4RrgQInyBY*Z`}~fB z?FBh_xxbYga3PX`>;%a|JK4qUNFpq^GtNV@jMzQ*l%?${5kpsC`kzJbveE4?!tl&7 z=e-Mhwl~1rPJ+nZ^hV*$0vPa)Y@-ivN7mf4&Ir<0S$D`o zy*FEJI-XUQUnIE-(%K8=)ZVI$Z=+`yNuWrKYzGn}DAUC<@EHYR!Z6YTQ@t`D8S`uX zgDJ%g_NSLIZ0Ai?*yl~c50iT-QmMcpG2Za}i$h%<%F@b`GnHo+|u zi1>`QtKU}`dN^&(XSps_K>UOn6ZwSl33?cI6YB$w(ww&_u?1v^Ko1kG`BZl(&&s^t z7^T>48bfjAp@JV&Ysb`@ZLkVz$1-hPc^lGtNGBV}<6HSQ$EzF27Z)tfiyP9)s>Xi( zw_UV>JkG!*V*${Q>KbJ;5YdnZCxVvoV_`Iry#i!prQ66V<36i4k?wNfq4R23AmE`x zG>{ipjWzvu^!Enx2@jdDBvOpG9x^diV}3RnpOE2yKZoK9Lq``Zm`pQR{t@%?CRq*% z^A>lfFZ*b###T9JS+9$Q(EvF=OJ}{?YR61)hn)r#pTSuI@TAIpqM6xgqI9O$?=_%JE8gZWbX{5OTsReQ+? zZ${hLK;+II|Jp)I^fbQ)htbjaB)!N01%7;w{F!G_kZXHcDll?04q(rNKhA~bWuLbK z4Jb{ki`JRe`FfCJX!L`IqFPTO@?;C!X3-7HO)taRSA!ujFF@O1Mq`ouHd7c zb2S|vfGN24ElFPwx#BHugi26Y*#J4~s2TIN=S<%(y>mQD0X_w=f)p#aJ@miO8^Lq6YK*KCG2< zz6#Gjlk=1Q32(3nREA5({&lV^@=_+v$JTr zc&elG0O|jVC#W)ZOib+{*XSOnrR-q(D;T_TI!;S|7`~C!9(=)T&|??-2Fp1!^95lX z9yV`D-dh9O7AIr9wnxkU125{Xygv}(4eG>!1362o>K-HHm|q*+#s)Id4X(C#5iIG9 zypWToZ!h{!z7Q*o(z=YePY5Tk=bNHoBr%`&BgQmL5uQ!(32>cFCJxjvc-8)7VbjhA zMgE~0Aj~Po!x{OSGt!as;+cVCIiKX9xq<&kOgN^?5 zCkfKkV@$~$#BNrmu}4-GNTF|QSV?k76C)jPSg>>;mrEZJ{wR`?mpGCeB`=VYhn7N3 zi0#<*?}W6iFUINQKo>Kj5-~C<{3>H)KK>QwZ@jnK$xh^At2Inp7!x7~v$L&8uO5l~ zr(_}3-@nbu4;fD6QV}EW|8hb_=A<$7Kf?T;J^6^KbZWo3^n&@O3@1AF{|NIoDRDmk z>)rEkUcBbKaO4c!YjJ-2yIr_6QvW^_Oy5Yhba#|ObYad+ATuL=EwWQxs&4=3>ZEHV zw$sdNk~g9+288?$f=vJPn#xba3}LR*M}qp|?Ze4DxoJzr$tVq$ad~XG%m)>)^W-3c zt$WM(DZOv8OAfh1kUyW9eox_JQI6yH5v@TYQ|yyV_2g4&B~BrMdm3SQkBcXPk*(u; z<~fQj%g+_IzFD*2k(`xl;0aal=k2lo4Zoeu>}J^}-K($U`CY-`6kH)}g$eOF3>c~SXrRUacW>oRB2-8M&br>E*mGLitA<3=VvVA)xKzU z(YOZf-&ZMiZ8=G_;c35{w6yebp=*j3~i&C0xR3Ya@@I}|ETbl?`QhM{pLTnlHyUlp5N*77G zH$(2CCkiRp#mVNh9=IW5QQ|&~QR9{!^p`-ax`e@74WnI!_LzPQ*}wRAh9~y!d6f@D zPG4h_D5m<$H83<5NTG{*qn;bf3jrUIUXOHTutZS*gs>D-^s^o@KlC5#6kNICJ119b zi0_?JC-w2AcOg`E7r8~|%}mo@(NnBg3g!ru=`IjO&n8=fCsmDuT&t5QYHR6i*!rw6 z)Dsty{)8?229@&7cNRT&D?MHutbCVnd-xXlbJgie-i2P^`*{!}wy5Mce6`<2 zY9i@>J+WkT6}Hxk^1f1vHsKEV=;61PiVw^O>J_I^$9gG5Rj*Nz9f;q(axO4ZmY)Va zRMI!Kj%z)?yF(Nc;Rp@56GYkZTnW`S$*#3E5^o%4^4H)hgudYPI}?Cb} zY%{bfoI4`BKIhAkmlr0b_6zGGtryX|lB~bmFS$5roGiT)%PjYN6YYaj2y#}z@UP3U zSVnkC^uB4joNc`>brV9L7=dCYTltBPgf0e=1Fvq?e||qzi-2LUL82Hqnwj~&gs}+(t>Pu6qFlm=1NY!%CjV0jcJP8! z$wj57J+3I0)ncVWZfN4+2aKBu&jTvvws2fK_Fl?4ge%d?#|WXg^)WqSSWl*1+_o-* zd#Do?eLnPO2gj6+TzlH~_h7YL5d)Kup9daK2Z!H{NmuKaAB#Nann*W~)~#}%i8ktI zpemn6zP>NHMhk>hbWyNDaqZ}Okurk?LQGG3gLV;gD2Ob~9^*4gGhH3K02I`p{-<7BA zH4^M>@;s1``3Qc!W8O!>Y6coWe?Mskiw=z%{&1(MI$zqMDaL ztESckn*DlG?9?ODtMC50m~A%rSBsJ8qt|QMwt8hB94!9A2NyagU|zX%5k8~aR}l;} z#>lffoLFqxEhqN6*&5$1TIN(PM1pKMh?Xy=*2P5p>ZMzIpv0FQv5C^lWs4^0j$NRb zdRJBxk&|8&177nAa?ZUMN8d1wpU~h4L;r5Z z!k*n$MY1GWpw*=*$(Id;!kH{@n@luqxvD`JksU+7uIKXmUSstlO2Tg8pq||U?wM%g z5=y2yAeSDC&$omAUo3oSs6U)7O(Sa-{)Q?1K2*x3VeL1oGgCa$Ot0xJ=-o6#P53y( z@OIcWkolh~zyCj~eCnNvDU_5l1^KiS>C&$A!Ef08L7Wh*gTXE9qYspq({XOL}fQ2 zG=YXXvI`ocX3$l?Ar{0Tkuy#J%unk8XnQRp`Zavnsb#X1ey?IHUe31JSmC4C9+ZpW zUcA#rZzt{BD_605u-YxBoAfMQF+I@nWb+dh%XGw@F9{(^7S9!0c~i&Rp7)RrX+^NZ?U zvEp{K9L>&nHwWjvYsUI1y?BGy8C|LxdvYGb*;mqbzq0~~T%|(L?f`wa1G(?DmPFy^ zII`kK7RL{x>*&8CA@=Kqo=07s`fY86wZSzse~;#7ygplS72i@9f*TL+<)k8>p-EA0WU-t6NKbxIFuFnAHe-AKuX@};JHv!m;j9-bzk>^@ z4trc~^?IY)58sl_S7gY0sj~6OoC{A43G(Dwr(L^AC!B1|2rr4EZM1+ez-O zjyV>0JLwngCXyG5mS1-Dy2nrtx17FwQ7d%)0BTpHu|AI8pYV7 zqTQ~fP6IG6;j&hANx*o}CVo(V`>NU#R>+?j;eaQom8768+~W*la8d2zFE{5Mfwb-C zyu-pZ8AJnADsRnrhe;P@w-i@h*lFh*gQHcb!!aO;hSN-F2dl@c$Vzyi#_63<$zTJ| z*Wn&I5{o0OGx5hq=o{+&>30=1bPb#s1ij z@xiZHskW_D8jdI+A)f7FI9KvCa6=QJKTR)fmWo_!Z-I(XK69}PdH3L^C+iMV%?3WF zhT7V!CqzRn-kA_$i@~RYCFo24C>7U*-Uqq98`YiP4WH+n*ydcO$Ra~cI2^@;z1$~( zdwVXbWtLBDZAD${V+{i|@dd9;W&ZRy6h#)_R61D@xnO*K(jtqL?n%??%~(sA4XUs` ziw46Bn`{JM?y8?50v*J=`L$i&cZ(3E!Gwzf!}pbc zqnYd7q}>IZVUOeI$1thS8Fh*zyyW&)O;RMJte?lH^maepl?^;I@K<33!CGh%H}sq~ zY@eF6hx;so<|In+%eu3>&JR9YcYaIJF zi>|ge@0BTZuZr9XFY<_I1KG>i;%p~5F`nk&n46wv9Tly$q)*c>%O51_J@w&Ts#oZh z2fqgoUxbOG$dEnY+KPrR^5^<;U&+KYoZr!swfp%BdZaN<-A z9xz%jX6S(QOFKBceS0X+I4|Vj;K7-~?iSzQZ%rONKGl}GZQ|({IU$2rq%W~sm3=OO zWpOn3{SO#UW^c4kcX9IBwA$6Ze%9ZaW~vW>oB43yJ>ZLp(8__)X)|e9aI?>MM!=e0 zNh93-YGi1mM+VKrmbJK7U|PS9w!%NfcC4UKJPB&>ja3nprVSs~YNk6je7mG$@(R68 zcT~A%r*+m)6=4c=)}QM+wBFaU}19lr_4VgGRy2U`*c28=OmDWl<39V zg{T7T*3B%Oco$$7rVhLl2O@*tAtI}0BP1O9Pt^|^?qnw^TK0T%OV$w0kc`TT&-ymX z018O<3SZ6Fmm&EM>ykz1|fIaEX^hkak7uBLfozSX2=pA~Gy*I#CQQDRme zEgjuJ7jqXDk=8}{YJEDAzYek7OyhBZr%fzCJsb@v)_A`I z?_f$S^ZI|q@${_hHX0@$tsf$S$>{J%O11o-=_VT)(etvtNR96mmUUP~|6LO=>}X;> zW=8s>_2~h3OUYX2n9``5IAV2u?)%@5)~z45T6jOoJ%>&*1VF=h z#m=LJiDDvjRD=uTnivqJHa=dkSL$s1Lo0DG zRW{Ku?c@9hA=kpvU!u=#dN1GnVIz~#C+1B@ppkAUhO|U6v-Y%+$wAEf93}9bd}xYn zX}2R3`kIzg^6Wp0xrSDV#xwIL>5oR{ODMb!ZuuD3FLr6SkE}=>$B~+`2d7&*ROcjL z6Ts|Dn=qSadfOuW;H*yTDwzeW;pD7QxGt9L>x&MlcG>@aAwbs*@(}M3eINHaK~_*N z%B|mAN>1b5ns!fWPE_5G%J-9hmdr&G^m~9w6YRj2W_cnFk+2U;>eDfL-HDc=rU|zpxj0Gn zsSI}M779w^sfwcId6zt*UV;lrao zfnVa(SU0{$6mk6MHQm*HVJb5ggtcHO6q+)}l4@h&s>iT237adw3Vyr`niI7iT~4Gv`Jp~y31iho8~Mma7&R9VayB?tQB!Y zNx*zW+hIo$-$dn_ZJH8C^h7Buvh6fi)y__{W`Dt6`l`pb20z@cT%Bx@O!OJRQ6CO| zcs|zDV2urx3(I&R{A`oZM^F!uCR}7(eu^W4UlX_Fu{3!2CFfgAhPj%K6NdglZw_|ZekzR7`l?uR zNw(|t<4~^&Y~F?W7ns0jzK@v}G`8*r5$$CT`#yDb(XMwJlKvhM10E9fypUlPu8;N? zAZ(ty2dFXOpY;(tH$(gwOo#&Z)S?mhXWg|fayM%c#)ppd*FqAOgEvg4Pk{huuKvN4VjK1$Ko3U+H+E>NrG+4HjBN4o`cSfe9AY(}|6v3Q9z zm7;Rpjm^`;Txv4^93jFrCVLW~J&sor5l~;&x`AsQ!mQADUZ(SXQOLdGbvFjXO{?8a z$C-X?o(F67hZ%@vkT(woLfO+uZb<%eRiCe7T9R#l$~&M>O-hWY5xWXDlr1fuxCns1 ziOUb?392<-{d3ds@6_++K>BDi@;E1?M!-};;ns>g=t{;uOu zu3RaQ;t*vmMv)=!-FoYI-))y33HStilje6uNO)h4$C-RF;Trz)w6dBZeEv_A#gfeR z`U7H7>)-+9Z9joK_NR9^Z~DaiI=>USjh?1#X^+1>4q5b_@4DdYV1~AfE3=*Um7MjV zi2UGU)S#EK=G&pkYx_dE>VG{GC}X8|v&k&Eo=CWG!dF!{j^&Huwbs;C>B#}Gc!jc4 z0@(u`3UJdgUDZs5zs)%$Z7ObG{C<5rV8%K*>#^Z( zuDr1s-*6&Q0mv*fe$ziSTQ6J*h@KXsp5=;C&aCsw*R;2fu6v6KL|9sT-W0 zFSgW6&@o=W<|L+<54R=oI=C_63P8_6fTSXYt&dx$UgvORTOlTI_&N|Uts`hM^ZRRU zZ=OzSAv?*`NI(l0l@6K%i+1>s$*049Zxe$X#3#wBN?5sR5GCLmm~&KVLgX!)5XT@N zv=k-Ek7t!-NMgFx=1!ocZ}LK;Z~xH08nZOQKcZfAB73uXg)ig9lVjFOw8$3FKxCbX!iN4A?H$gq`< zulEN8fe&ZLgz!YFNWbc+(AD#fg_slp!^QO3PY?H=;WLEBmpu~{*9C{sjN@Qo@n(r< ziva%yEkpi#ee8jEhngBcP}N5*&TKFL#O>bOM8>ja%e|U3VSO%!2BXX?INdR(J(nih zLOYZ^;iy`mv|0Vh%-CNW2<=r=wuGwpRDWP4&N*N%?dSse#!_m-CwJJ=UIojO5~|Nb zvjc_Qk9$HM%Wx#X-zYPr=FVEd=p9yv?AC%{Q=GS^kvzPyoj%PxQv7pOanqXw;jcFB zDryw;w&@Cb9NJW$BRIV;*B=HRB|zSq8ZL_IjY0STiaDFv~CHZr)MO)89TG z)g*(EF^=1pQ{pdxrm?3t)#A0YZpoGWq<15AE^*(s__ib|-Hr1F4#&>oE7rC&FoLse z7gf&Dp$g74ZFN~S<@gi0Z)7XGMt-~q-E0gO=EoCs*j5eUqhj_7M=u{MEBjNG^k%K8 zR68D5IdoR74Ma-yb(K)YS>~%2(X9yd^u-}I&>wY%KDxHhFcr!ZQ792(efc@nP?8G9 zKfmoc3P7H+8E8^hdI+;7K;Idb{3^ms6l3Xxm(im zSngrB1Rv{zu0PDCEQan0E1SwYjinu70F5Yel5X@qnz~=d#;z3iOB5Yx|D*{dJNJGk z*m8R+$9;F*`lIOPbY$6XU7E^Q|ED2GuF&xkJnMC1MLo()gHEQBM|aV8%4Y#1*YZ0Y zr44FsY!}G_xSIXOG7OycN6Dr)o7gdtv1R1|;DFp@d+bD$N2l)-ZD4yAnYAwXiP>8_uzS8awwt5s)`G>iF?Yd%9J_l< zgH)hwHhkHN6i$$=zxkA}Szf*~Jn>b9y=%b+ak@H+k7koU7U~pU&zB-D*QOa97a_h~ zO=Z%~8>+3^MNdr=v)nE}M5ThQ;j|U${KB=&EjL9c<2F(=u2UO&#asHGtCr?(iq6y9 zr^ZJKPo3Mxox&^L1CPs^nof5<&jk?@C20FlA8r0>@5$%0m%bv(zGAQ3K(|`zt8Nk4 zU6LGt`V$Pu4L|@dqbcb={{+Fx?>B@l;5Sr3A)S;11W`y6!#fJFj3k<|)Ldxq<0<^W zmd{_JYz&Km^_#HI(-r!ucMA4nzF_4mJH-qL%#Tl})(zjEr;~Zaw{(%T_D(2#Ss4c9hn1c8HY0>PbdFjF-BQaPSxm7~Z8iG= zTax$_n8RlaADsP5wBId6X|BX_su72Fm~r@BQMGg(YzvmU@r|B;bBdEYdqF8|praHDY=qY4Ms9*yI{ASI-yLSQXRl?)BMjz}FBE!sbYJ-$jLWLXp!>9J4TZ z^rWJtyNe#Xm8vy6ll=z%Wc=u8$b>j_OBLJZYRc?fjkw>UpVyfl-F>tYMukmgL~TxY zl@kt@LR(Z?R{genO?W(fZtTXh3^ggIyzT=;MoZVXEzcicF7dP4PtC`}H|pCut2s{W z#91oEH&reGB}`sh?uWD&3Ub1EV%u?Fz5LFpSg8LL&NwWx?cA&8@odx#ASdh3Zg8*3@fXiqu=oA27`gv36!47WPL@Wqpv-@O;wf&u|Wsexg&9UkqIN z9R9Hae7g!X$D7iI7}Gd{p1vKku<=*brmKyH?{?6Pw77(avO&QZcUOx6(Qp=k>K7!+uoRZ5J z07E5C$%q!^=z0UpSw-*K5^8x;$PFV@ldsi_(B(<9o@=W$E#fXs&Jv*6v0+|c+safK zUHsUJQt9N@?DW~G0m#Ky_Scf;+Z;dkEIZ8b$8c|X`uVBC*;#JuNY1A(DmOl|r6mGDCEy^1xS0&G)YyZ#QQ2fZ21}8RC52bdWZ*n3Wfhdu8{2kEqxh1}s}4(z7|ulL@Z>dtGVJTMYi>1koGpXyexzq{ z^k@!BA1Tvw5?Ru468VXJ-pA`%c$a281MAVIwtMthsJir705?C0Jz&*ppt~1)CI1;m zSJj1;>MWqd=>%f%v z@;NQTFQ07l>;?&ErM}$;7TH%X$e++rP@bOt&s$@07N1Yh|9=F%croh#67({W88Vry zL3rgMMjtynT-EKFFT0oZ!4l%I)RBzXw;_t%+;;-mmyR1gM9yF@w40wm-=e2YDwM z1x{|+w?0+DPK@vCzK6sY8$%xMV!eJ&=Aif{zngOt@^x=xO0{{|vzyOHP;|nPiqpKM@tJ zU}^anP!-i~eHaoWc8QLxLKf&xvxg_}0mR2Q{rh{l3mQZ}#fMa^4<7&Vi`ATlbRusN zIwmU)HPLjzfgp>QjG!|$MT`FdzImwogfwlcsLSZM(`H#xO6!2i_G>$KBtid;$}`Jj zo_g-tYnL;@mxwlra}BSb9BDB40C~~#>np*lLFsE}35xM?=eAMj@9}ys60IDmZuy<4 z-o2Tty=E!!7QZZh&-bZ2#&-5u#+8yt(Rd^JkA#Icj!G_*t0|?g>Z515EXzXnxys3k zJN2$SCEnnuvs=aNf*f?tu%~IU)2Nvv(yYfin} zI54dKfFr26!Wo-bYb8F=abYDL0#G>ty(6|3@svf)U#A00QdY&$1~dl_?($J^q^URw%rk{`@>Om3O8j{Ubj1^i+BA zZ~V8d^P6C@7tf3~n!0OI~+_>UZ%ZTcI$iD%+gq~`v#nm*2i>*Kg45(TRD z%vCe2bW{uQMJ%Wo#wNHJG*hW822j}mr8y=ZG13!V6*&2v=~_+dYV z_(7$?W0Tq#+QsFAz&#EC0xy+}%QGphwHb~&R$GRA@ zpmSkp{b;Uyp8@j8Q7eXjSe#F>RIQu1aj@afjb6Y$N3{&^|7D?*KEVElL+9AVuUg?j z+0FZPlRj~=!zg=Fy=Ncr##R2VQ58U(_-nw+2LJ|j?Z8UBje$j6lfM=ww# zh_WEkL=#i7k7Lqw(r2nd$+c6bk&R5))dBq-iHSpeLln|$3b+%v z9KaaeO*_E;coc)nX6&G9!vlP3F~nESZO6mK=Y<_jQ7$SMg6p-q&xF|p_HNxEE+FY|SGs*(?P!m?f~w!IQh>aI=UjRZ_7gHl zA^!N0x9xoA?$5;|W5U|!&YG< zl4~43JxV@37Y!jBzpx@I68ss2vKjHujm;fmQ=;*9<(Sl-C4au@Tl+1+`BH*{hB-~> znJQJci+^hya1X--ixFg+6Jql>z=SlN*1blxf-arfyXBnZ)kBHr?Q1>pLX9j0tXk`@*d3<3bJMJs1x8t5x5eTTE{g}=W*x$t?|U#pP*QS z5=zj#1Iqy=qCA5@@qG|k8|Gi0NZ{RE=VY7@ItZtiAs8J$H)U7V_5;V>{9laSbyOQ& zyC`rdEtH}y#kEk}p}3@!0&StCg<{3s3GQ07#oeX2yIXLFP}~Cq2yTHOL2laj`_8%d z+;i@_f6U5Sv-i$3YqI8wPokn)<^htEh$pLWjIb&M4TT4@a1l-63B2(&72~mA&m|&`RfY!HqUm>gQ;J z>({|%!%#{57qX{w(4lC{8UW4Mp&YhjLpr+PiHUE%42+uHwz_-IG@ZrUyY4<3A*;tKqV=8Y{(ep&G1Hxi*s8#c7#s#AT$VU z_u{nM1ci6d;hkCZle68p_va=utv(S)toqaCzdy%563X530@-vs2sP;(=VPQhl^Dep z_C4$SW%B`e&FXWc0Y8~4hs^WeU<1tLFIK_yUDmV#t|Z<5kh}p#N^90btlR_o#3|G% zi;97p2iM!)lW5fI@S_iB#FfPA@;BNMkecjJGi+j{->@8eQww=R-#7hl7V%+>xDGcA6DrA1HOtfwBzR8CfV3;B z14P%e8mEh_R};tWF@apkm|T{sc~8nNrjrGEbu41JTg+pnw9NzwT{SwE%$;5?M29%P z3wyOEbZek_Z|ZsVEPBX?PVhOh9tI}ZihOVr?X)g7!vRckrn7n(CH#8M*HPjO@Mgnl zsXlm79QM4b%g?sUAw;arYIc9Vr9%=`Q~f9c0B<$19_!c}brJ$AzxedL?yh@HsO8>K zo()?RIhzO>U^VyDUM~+Q9`(-q)FLsVJ|whdS2%H_1lz}neDR)d8W)58B0brBd2v6JZfNgKszNvRg)H4LRI{xC7+_{f zbfUMB$*;@c@ERDv!a=|Epzv3a zWA}STrCwu4-*HQS_Z+&KONbRMS*A)C%xaJ?Dx>K@T`qwApiS6)Ce#)LHe9`rQUtt$ zWJJ0gT)_>m;ISKkh2a~yMb`V@I$)n#uRHjsvs6R^oYo0;BbN#T^z~KE9}W1_ro%Ju zC3O*3;6*4{G47sB{zR^h!->Y{bm^@?0ST?VW!Syt_3HF(T;ujjW7Lp{UpO*2@ zN`{;?88rCu{eZi7yegjjjy>wyeCq=0ocZ+uh||5K(>p(#=J!ZPwyIrCTA#0QrRbhcBpgC2|lsfjP_Zt+-VV1JiB|4bp;s~6(qKgGwL*Zt}-2x=t= zR>%oz8wUJUOM2Z^v!jhD31a98V$xlsI*_K#h5fZg5(F`SJH<2%V9*daL#4Dfq*{px z)@8)!M*Lm>e(Pn~sh*Iw(Q`Mw{T>WMEN!EGx8pHay;d2TeMy}-61S+s9)HK+lWfPo zz0WvLeGQW}s-%*t09HqQ48)+)o$&Adb&f+(SeC>v)!Ia0l&=jZd}_OzdmA*tKuU6 z15!EV^gQbR{Px*IcvAl%P(78`J8U4?vDuFjovS7JQ?I0;uHMJ90@Zj2T$v}H0?aKL z2YX%ITf`>`ZZbCpI(89ajJelzrn0%Ldw^a`Aq# z=roG-v!?1*=hcPx0qc2glDMr7W+azCvF6&Ily_lNAk0t7dG*E|ZuUl|sOfosgQT_^ zFxt1aW1AY8cEdUZDQD*gz~JO5a_N?<2BNgb?~;*bLkE{Gu(ga?jv~*|n4wvYrUYzV z+*Qbql{RQChH5zU>H%WG)6b2+Tc{Xy=}&Uv?_7LjT>kn@?(i!qnSHiG6Q(#A;jx}* zS#g|Dr{?N(Fx|z?-b{mQ6eupCKoMLw#Mcg(c$}8cV9MmY@mV(|Qx$(TQ)=t&Mo%vn z)ROx2TJdKUBU*_Gms9KOlM1vJEGbt;k4%!I?{Zz1k&6-#!=J+kewknN8lb6}r;iT~UvZGy0yeiH^(Nq(4-XUScCD5(LNHcubTwPP zCds*0*_hMFt&A?@x%nXWxV_iU<(FWZB+xrZ<%gj8r`vMW6UpZH0(-p<2cRSr^PXUm z5+p_SPOw~U)ah9!sk(MaiY2O`gMb^>o{F~HOlI4bkC?*)NZu9Hbd>fe_X=vA0$8!U zbIHGgUKC%2XKz7-v7#)!4M|bhV*mX`3hLD&$|EIsK}iZ=x%g`G0QG_DoqIJYRCslj zbjuFC4L!Lv9<8vMy|JiUq%101SNHh>FG0!iE3fWT$zi5GGVq#tVUSKy>QbCSrmC8! zMCuWx`q7?->463Y@FS$gr@kF@+UDm*W#pJ9LY9?0{jORTS=o@|HD|LBJlcQQgct-* zL7`{EZd{SrX4Vs{|1=0l6IVu(AwVuCwft7iDR`WZ$~lH>-6qNY~hiaYg)e6A~a!)pVCY^>zu zYE8cK1yPZ%!x{-IB5_WfX?l>2$A{22H-gZvgryGkQM@pxCci39As$3iXGy)N8wt1QndN_(Ud0mnKeisz5Fp_t6=Q%V)$(kqsej)Q% zd1&sTYwS_yZ-uIi!rqCVpHSh=J;vkBp}T9@P;ik{87oYM8ty@RSPG84%;$1KZvyF>(&PY#rh%R1V?H9*)d#sb2w(1A)z>+1)^ zm!0+Mw@isd_KsYcncO!|8q)JMZq6CG>quZ3zdNQ&S>5eq54sx``?h1!Br-gAr%Qxk)S)8{R_4xB`gNVkt_c%}GM&gcXOwyS%Rh<7sW zEb(0XIQ9>>*tKcW701A#WMRq?Qlo6YgwM;+Q;_!hI2%kiE$tTF1>ZJoVs0B)dlQJi+ylP zeM|ZDH#Ld>`THRgcUvV&-7%=HoutmS7LJwzrZsixdT7$VUi-{f;9yscthZ8FJ;8j^INw|c|wMheL0}u zRd|MT=i~>4HKYM07`E{IBw$9*09$d#e*Swn$@$Zv=E3cz<&yd;-8FjK3P1ux{S-#+em6>35YR;xI{mu)|zt0_) zV%V8wfoIe@sg^{rwPw$GGJ!2EF%w7BB%eqww6TpTqP*@s_WldSj5_N3Wpq3Z4zD}w zful4QD;(m7&$j=gClpEH*XXX}e zkoDL|Tg;UpF=n?s;25%Bw6>Ux49O99w!gCvi&m1+i|kiXN-^&uPFE85P`{!1ItD67 z7UNGP&0KSFVI+RKUj~X>1mB2P4hoKO?$i(CRXO}3oxL2)MywcJ^i?klU4Q4g^H}ht ziNtn`=%**)_C&u_TNUwq{`HB<@Bs~>Z0S6zfV1Z55jS2{&?$blA^fmL9Y%Iy|K37s z@Rd~7c&SnhY`JHbudkmqWL-SQd$Ve$;@v&Lf1TKCY;5CG{QrR8x#`#58Xr##bPh-t zd5y2;J^%9K{{_Df1}9Bf4H3dWB(hpK{vYuBiys5k?+xSko+*FtlA$#VwnF?&dH5}( zyQpH97@(Y+gd6QPG1Pc-M zI_Y^77FT4Gzd9=XPG3s!;t)Q;DcfXO>N$>V-Hzw^c{?V!M-5OFW5f6`dV_vs+PT+J zXPNNsq;}W#SOX$JXm=~~qtw?M4p81{1yrtIAeg#NEG;{S?i$gpBOl#=fb>!ZYXJ!q z=bhK;<62_?{{#FUNg+~?fUGIgg}j=kD1%t^^5qgv2v#cm!W&O&j1`-RpN{kY(Zc(Y z?R{i*3*@#=8>IEwF*ajmIbcuQ+yb*jn+qxKJtiV4*=H#3&Kq_zts-p2&-3WHfzJ}{ zrG5>6*+<(O3o?YzWTz2N`)yuiMbH{?>URWp?56{JU)?~coe!BllSLuFo70bOlUV!$ zAv=)2KAs|%Zm(LmrYN}r)@^4aps80My88rIqlMo(>2$bqp0;O=(8d;~)K+oDmV06h zSi%iz#Qd1r{gJAi?N0UnQ|j6rD7$;Pn)r6f;&;u;Y~&)mG@Z#yq}^K3a90TV%Z&NR zhBS7$IyFTT*yWI!)mLPh_Fr=HBKea+@Z>?efl)sa_t3tn^gqMD(9+ z0UMMB-hGtKdOm;DVCY_FKHC3Dv*1;IRo#jVdOf`t6KG#E%KxlHXOl z5zY_QH}tc!JWob^Gd;W6Ll|N)L!aYAKi>0EEk`il%HM>N*NknED$m?3_7HS0+6e}& zl~8`@_s>tMBPF~KMGpL^x(P5cR!-;&^%xK1HY$)U)K9uN=x*k;CH5V zBBBnQOG`zHtEBOIFjMARI&r$Di*H`Q!giM|$yc~S2f{t!Re;vtP$I75lC_rzEIY9t zq3~b2mX2NMI=GmQ*Kc02(r{p&^*WAw-u`fU^G9jldgGH*4zLO6?h6Nc)3$%>!SI>r z(_b1PbaL+o7n1r2k2bT7MI zpW(-}@19KDlHr*z?LKod5vhaONy6@b*MyDFQ`pJL$YSb-yL84HvqV<;O?n0}ZJ@ zr8*uP2v4goob|b?YC18E^3I^Dsn=4ojR@+F>+5i-*7B=DbBt3Xf)C`UNy1a5FCUaZ zgj}anzl5V+I6)(*^|L(D^#|D#z8=#@Ys6ixK!2!NY4K$ZgNoyk;pZ&iWx0#C?%Is= zqp{<}c?7%8Z<1rn*CQ46+MGf;c1!&$_CawRFMiz#p>TCOq1LbP_lcjqZ~`8(7OCBL zgJ!pu?^tLIDY*QdP9rD|t?F@>GzyQ3wH*aPB|ZctGklK%8|Q^A69DAFw?7~=dmFlj zH)srEPd()a&Wjz7I+0cVLK}+YOG#Njn7rn$wCB8Dyu7MCfn7udOUM zi0WwXHN8VNSzrBB-)gPLYf)1>i9!HAE>P9X%1gpetJ+wuIZTSd3UvvHrkV76n#e`3 zX514|4{*M+rsJ{dAab4l>H>mCV>Z`{i#&PFi#6p6>a0kqr47Do6#0_*${gu+n|`8O zMMCHM-FF)+U{$U1i3u$avHZC%$DZ1?1b^%G@#fyVLL?wPbVIY$>CG^qngj6*a&z)) ziNqIvv(6r>AfMS=9F_a)Gd`Li|Bqd%YbAFd`DscBzAT^L+D-&p%WwG=i0#Y#7^&Dv zrtzu%>K}jZ6b|;?VOP)mvMw#)y$Jr}!e3>#{B_}-peCb24%9luzXyedqk~hu$tF*7 zcOr>vE*l|1Ro`YWb?+%`1&+R9(h`g5pf|cFkVp_<>|fyl+ghy6>{42qQ4ZwA={3K8OnWjDNiX>mBFw6BUQLJ+|_%@ z_EvyGh^2pY!b5A!qFpEwE`WDfVQwct+Pjm2c~5Og@tum*3r)k406_c$r{L)e z=ROrN^ho-lJmL%M!&N>j+QO1j)x%^=awPhv9uVr1X$j}Z^-#GQqA4=15V z8epm?6|G)B;9rp%89>E)sAMSnMqLk+CYanzzfUZT+@6eo1#Tc~BI;`-XcEwg>-Lbp zt80V?%$&3~pBBwF5(VoE`zlMJ40-8BZ|d^9!SW}%CSS-)Lch0RrVb96v$~rIiC6HP z_7jS?aYa|=;cpZ1g-jw0aB*S$EDs_=dh)3jHjM`3K7D4xa&BtS9ox6pU;|EXS>E0W zQND&kg3e4t&HB6{mstD2arknVX0)XK^~0Um9T-JJEl7k4%9D1Ph~Y;GvKutsm7i)q z9E?9AU_L3km*d~J%v?9#R$R@})L>@!0c;E6m!T()z6V$-D_8J#DA{LB3xKAvT-ZY> zHIV+JMmNUU6u?(iG2r8BUh*Wj%+_x`v$2bbqcXI?;X)PesDd0a(PeAH0LBozD07Jn~>Z^C@-H14?+l zO>_0NE2fpjCahHjFO_}R_3+k2I1=UZ)1q6c;)VrW+`p4?6HV~XbbJ+=+gCEp zi)9G!e**(7I#BmZHW-JqokRfcqgLS8a+!}e78C9JleIKkc++ahQy+a=y3bV@EPYNb zcrvWodqxM#5Ji+CW1ef@Y)EFgksq8_#>YWt$Vq)>8>$WZ7EowXpKGI;(cHKP%MQhQ zCySmATJ|Z$gT%+OpVz?B10H60zb!rYYIr1Tts5SND_Wb5xz!_x(A;{{ViioP?ImDE zUe7EwyAMOV@9gH7MG!y2Q7U}ot7MOr?mtj`8Mx$|WqaTPI7@^J!K!{5aIc3Jm*M9q z!V=H!{W4&Fv-Im>{O~M1VZh3a%4689Y!t7~y@*_~sXFiC^$1a};>>(4iK{jdb)Z?= zsQ)U6m`wiSX@$+XWDMjc=eJ^CyBK*#u_zvZ+b45uF{AvI+jML0t+V7xLRvE9kjdZO zFfbH>75lN&ga#s5b56hLkh;_tyLUG%0}oFD$!8*hl>wg?i#NPVKvyef_4S1yeo=gE zUnTpgfd|=+=J-dikHdB3K97=r9STN6XHcih@yTGlRrU@%;$5PkKD$2D>|vdP8;@dX z$krH0#(m1MlT4WiXT31Ua-w-;(?YeeSzVpBxyiz+mZG4uvRmHE5>K3aVNvS+mxp)j zI>Vk|md~`f<#C7)9|hu}c=#hZ#l9)p>pwiaIieeITBqu)uae%{`rFIrouVazInlZf zllfp(c8ndWHV7DYgSs&K9 zV+&|1k~CEP=oaS6@^2nqw*1^xVm9E-NaE*YoHyZ;gBO^fjItMTM-AWZ+mJuQQFTq_ z8{)yCGq4w7QPl!yT{H{23`XDWN?KcGvwGAF;}d5?3U4kp1?az>I{iNK3@5ZHyUeKj zj`e!G?hT7fR;{Y*(6i4>VO>-m$H(8+@+<>0gr2P2$i`RAQY{s(^qPQ_SdZRlMkak7 zkQ2RE6)8;dDQV@PRfzWx=jI;9()=m#8l4pPA07Uw`BjMXrZf#REnj@3%7w%5_79#( zqRz+Tqp2@$IcdgsK7xv@q}##;l#^7&rC);G3_uy`+2lrkBYX3nzr2E+AyfdWVS+R> z@71X1H@?pSA;#Ysvc_-d0Ce31viFcGY<+$Bdz<+HV!>sOh8+&EUtbkpo=55NRj5^y zW>u5=t}-#bd9d$^2{9Ey6R;h!(fj$_z6D+O)dN@7hwBSYm^8JNdbNA}bE)^#SA>D1 z_q0(2Us!3!8qU(~=^aF(>(h9Qb+-)fE7L09ep*++mkrEBE3O*d$YtTad1x-elIYQb z$`xEL!{I>I@|aAgJ3Q3TSCD5=^Zs)Guv zYG(*tYa^d@#YD1A@((*??3<&ttq|$(!d}LbD`$)~Y4AU$X7t{w&?^k#uiDk28Enwe?qVcrlWF8F zmwZKshH?C&?Q^DdrPr4t@5gK#kC>2TD=VG=CbdmBtZDe+)>V}olY7Q{w~XIa?fDX! zhWdMINGd3U*N1pXzbBbW&lUykCHnz;4q?y4cpePdyxZ?!$wtxeIbHztk$q3Y%p)ZB zTN4=RX4b@5=Df4FiI{3n$>_eTz+%wzp`eGuPF&!z%rm1@zKN5FFC8zdtUmPiTigb{ zDPwfkmTV+d$=UzyO7aYiAm=UffT2Xw4Auu@tKZ>X=k&!>_jjD4+24Y*F`okxB0|CL} zFA8%aEzT5&K3D9g%B8B@hFni3o;f#X`5TALIz!qMu^vAE?GuHi_p*ne7vrfkHbE8( z4872mPKm#KUm}m=80&&A5=E7$3wVr+@h+;8Q}*HjI@>4CQRnUSqkIp6B>Zh_2Pvfd zJ$Te5m+1x|40+SB9h?G;0SgVnG^qd(xvR&SmhG93AQoNs{_wISSbtZ8o(>-*1MT`o zMogW9=~a8)*T>Yezf2$U9n23}-*X>*)76vrezoULNqTPiweZ|!X8P*w^WfwgjtamJ z4&Wow*Jct{&W~E0xt=$AmNl+Sp1fE}lScQj_PrHUFT$%|l&zhWt%YE+)%iIuMtN8d z+zPfTQLflf8dcy`Lom7PI$aih%aR{|WdB)HB&mG){_B*Vm=mH;Wg1<~>9q`Xy|O9L zN+sQ_;M3PHSO-({l)5T%hf~qSPOa&p9)_j6QR$+&+4zv68lf>g(=@4GVgGbHOkyam zb07KFF#b7m)6cyBe+?tfeaR|eHN}Pqd;!U3Tr!{U*Wtty5TfZ_B$=E+ua@FYg!b%LHwq3$1tP&K_``gKSMK zT8p-oH0`ODHUbHif(x$0i0d`=#Y6sO(rn~umCJ?A_(yx~s;z?AwuKw5@XV`4mo^7} z#2|2RF4J1GX=O#ie;$~18Ey=c=>@V#^3a-Am1Yo}Uu4v87H|32jx`UxD$0oDr=d-X ztl@h8p1hdN|9x^P8^-%&HI=^gU6Gyix)!@>*UW?P3ypPVv6_A)2l>%nje{ZS#nzs? z=Zy8_o$!=o7`uLB7pk0;POb?YF}O@n-}-`7X!x?zbH!zSEMXHVB-WrfUl=9{`9+T)Aj zKD0UeJ?f}fE;Q%N$0SHE1Iy2cM1Cq>KldeBf0rG`GPXQCw$MPYUMhH^ae}z6^Y1TpJLY8Rjw=L`Ep296r)=|$=p86teT)pCtR^hw5Y+(R#hatco^$G@0~erlPS!8 z&N_-UzB}^vI$(z=7d)jV7COQFA(PL`eJ3_o(I&$HlSnsfLaeq-xSO-^;^#LU@x6}R zQIw8&D#}+9TPy!lRJ;u1Oed!ZBc}a3`MaC&51E5|Z#B|$LDhxOO{aIN%zOO&PH{TX zy-jVy2!64nXOOxH{c6!KI#|X|BS~h<3?7s{ilVGtWq`Jp!@+;EIO-Czx_KCrD z;HWHZ15#i7qrDhcZMaA}eh_z1t=nW|f$Q z^~21zNYou%MVB3jw%@u%3zjz}>AL_Dy`Qjd?HR4&Qab~g-C0in*)=^WExCdV8r>K#C^ZrSJ3m8%WpT zIwj>Swcbp&(C~L&5-7R-+pI^Ki_=fYtEtEbDK2SVlKmyJUYejr%N-B^$L{vJ^{%en zX6@cQtzyC@!>i0kRl7`ROm)v4R&!PM7m06~KcBx>TGFpRTWncxD3-870$Y;Mkw?vV zm~0otr=;F_=M^=3(_t&i;9a~Wo&(R@Zv|~F+*=LojPQMn z$2xTd{(T1SW&}M5zxejS!)}o~PgOOBx$EZg64;em8})Lr+NffM_sVV&Z(f^A?@j3x zZbSJ_yQs?7B<)ib3JL-Z^lAdxS|+gFqgoXa+v_t@jcs z76NbY!;`p&XC^2Y-jaIORCnj+SUD;Mig}isn0wvU)s>Yr{c+*%y_`SpEw)@=l}0#8 z{BhwU|G4mdtC<+TH6dQ&1mx8HYPU&<#r#rX=KjY#cDUDRX($)omYXHuA-7YShWS0k zN<(|ADQRD(TjY@nXF4FCI3K30kcKVCGQ6gY%pR!~2OTQBrSbdbvcoCqT&L@Pydx7k zsyo~6X+sXUToflwAN%zt*B3oj{p7~tu3rA==mqgHr`8wa*I+Op&B>!KLnC(N+qB4i z_H3TcLC*D^%sMzd=zRus5MY6mUeU~aXYQ&xxS&$HrN6*6B+Zyy87Y>&0D47wJD_!^ zS~19eBM6j+g=J{r30D6YZLZ+WwA+c=O`B08YBm4Rs~8KmIIvDzyY4OS=wz@QhV@;| z(;#kxI^kcuoh)g(tc!m40U3*!2x~$=QIay#G{0hc@pe%o?QCF*#G28Aa*!Jkob+>tS(Q4GK zWueFG#h62$)@zMp41$GF#NWk6bNp#TM=1|R2$b?AOlAHP#J)|@HC?7 zx^+V#@w=1x7APd1@}g!&+bfaz0>&cl9MRPed!da&;`=O62N!d(0k5Rc$aTWjl@Me~ z_^d5_CzL~nVZs!hf$%X)tY`ZZP0zttDsSfzlRrp2DMIIH6E&@Qk!GKY;e^kkvMdc5 z^lOvAf0%;t-kC%k`uZ+G>;~n))7@o_UrxffaBiaePvnL!4Z%SGXEdLlHSpTe^AnW4 z9m;W&=a%VIyY}M7&G=@A>L(fx0(L@*LgG#1pWL|p0i+8;05N}1?$}7EV!}yq2AKUc`GUz}vykSOL#F9D~+_=Q+Jkr05_GB{gx0GX0=xm8YWjf_HfSBojCI_9cH~AG_NVX#Q`+` z=Wt37K1Qde7Z;XWJ8^g}DM+B9Sv+)RUx<1SE3;6%r1WAK}OaI|8brR_t zW>2-_P)gsaV+EmLK;K!ulh+VnWop&AwrHYGMST9)+gm297ph-t~_&NGstgsmO7j{7deJJKGp? zgpD_rvFkB-%CUWkip17$*X7k^mkDhr+K^1ol=W9MS&}2;#V4SqXvb@ zcX)Aa_1Zyp>@vSn6s$>__qIlDlO2YBSc0LVx?weP|0^iipC0X+-Xs(`hx$*;{*VDB z%Wt4v@csqwBaqnx@{Qn7jzbLj^oqNuhm#_+r)2RO6gj7`lYW9#g1@yQsP5iH02YrP zB&tS?NniSt+y!)I8Y%Ya#taMma2h;~Bbh__!+)`M!sv${JwKgZtds3y<9P6Z9Ih4h z31~VpZ08*2#6DJbt6^H<6JBw@r4_3|5(5eG_-XMdSub zoQcm#WBtE?_)|25mgir~{ts5~#rd0eE|g>64W+;zp&{slC4$>xyE9(%bkfv%aqg4t z^Wu1HxK+yG>w$YwbvIFneKwUxeZ?b=GGr6Mzl8V`MqQ7$5Sn0dBYkjh-QP~{A|w`P zA0*Cry%9ukaqM@#j5JMKmU<;kXeU;_&|ZPi(>hO7-Om(oqUltJ89sYY(|N;{#}P@F zn=#C=efl^o&>vbk-8~14Kfr8KYm~<9GSHt8kx1m8MX2B z;Q;%*_etYzgtl>* z#RlM>D800sF`aTJKISl3!;#pUZLB`$JJH)LOnH1})$zEh2h%9wUdCO1PcrtyeW-$= zwml_J7k@sX8D!Ho4sVWq(Kk9?UI$eX*Ow-K4AW6?b#UI7;zZM7ks0~_MSa@tS(6Rz;%!?xG$rH zXj+s7bq6VW*xQb=qqv=gb@;yt@y{7W&5U~62Xas=uO)LX{g7c91AaPveqp>ec3Hzm z>%zy+MF@9pxL97Jg!p`69uVawAyzdX)-D+t-IVUF8~)2jSoQ{XS)u+YOx~TUkS^Ai zuKJeeeMDmLx}FgQRxDCqIO7H355QjVS~4wDn<6W`8x0n0=bc1!_J@b}w+G_Wf@Ku@*sRMPzKY=jheAPb9SC0-?KeCMeo81 zgfuX(<`&iGdp#}s0)l~1y`I*62_bE~s3;kGz)UdbJuvT$0^X$-Be(hA^@#fC8cB$b zAwp5XJeU^2VtPoKe-rZJ<03kGbk7O-7bB@Hk-Uot2Cxy5x^eMwQzNM~dL_W%&LX?O!4uiuK#X~BVz$=+6B5Nzj4!kCWi4-voV z4Q2^-`+egeyv4}p4d%GO(HINKzi=w-NsYFsf|b zUO4nW8}Yg?IZ+mT|3=`i%`)q+UR@FYMdC;PLE<-j zNBjQ`)uV+uX1I}S2-1EQqy?XrP}N`g8pG|Z;n4tVxLs@gp&FZ&u&Ww-q%!YP24)YhxdGaG(nZRjy`~{8&=tKsWuD~L zpomKgJWNI!?x8@lN#{N;_OU7_z2$nQA z8b|Er6$gz+dP;fNO#-P$ChcwdODp*j{R(W!3%B?Xufu*q`TC6kw23>M56;2ghaVgF z+mffoejlEjYz$MeBX23_u}g+lPp;s}>W1?L3Cv z%fHgQr&hv-Swka-Xu@#z_us@@_lV%n8cW|RpRh~a^wE%J0b*X z`RmB@aVc9E#5kyuT!i}?HsLdWjizClYw|I_*@bhtHOSUhw%;^!@o7KxAIe!mSD zx0GCbQ^40nEWC`?U2rWI%x?mg9mw?cj9c=~c?f zW14aDz)AA-F;_m(oG#KyQHEH)S#ps_{o7%BW3gKC8e=j2j(tB{M{*boM?&#ePW|n= z57Sb_3J{a&%CSmJu&Lbm)Q3?R7f;h*u&LK6sksB2LkVUk`tXpO*c^=i-ibH<>%?m> za)|1s7S*R)Z&}qSSC5LP1AA&t!+q%?1KsuHQT5hA878T}EKp?pUrFA`ia(G$*P8!j zsMud8p3RE?>g%Ec&3|>`U3&dciH?J9(PTy0s%D6caMj>7ikY{lC+Fp*>-mX}-rwuH zKW8G>@wQBvLHy>I93El!6abBXHJ*2vEL zK*N(^HRcyR_hZMCaIW?fqjgFNucPGgiwrk69m1rIN4ysq=JNnD$YXgoDOvf;Te}|L zh!_ujVQjLf)}R)647-jQ({#$`JN02T zjj-Fz^H$M$XpyjTF$_E1m46@B;s`-ypf$dP{_i}Y!y7SAujmp7CH|(E0Mu0i%5}f! zLV5F?TqwVU+@A%;7iUi%mqxY4_jSG6aQ!u+QGrCuWJSd`ITXWA%UMY)q0etli-Z$f z|2tNcp2n#0Z<<62R_2f~jfTJE{4nK!<;fQ`{RC-zHYSHES}p`MzyJ^xar^qG z_h$;^i$m5Knm)8&SPq&yT699oC4LVMpk(q;vLlEy@K`TuvnGcAjoZz-=9+z0GgV7VNBn$(>D4O|li6F7l=@7TSH?F%zWcWM$PHG6%)?j?r`tRZ#htrymg%cBeB zKd#(d__HmT;=WOQ8vB*CuXURqq5KIcztgn-dS>2=6a|9tjp}GS@r>Jh==WLqk*>1U zzyhjZ$Lmilnuvuvd*h39H{=@7FBW`TtUHt_Z42=7z+pAEC=>wjO0B<+}<1A_d7k7y3t4~{VP&T`A zIsd84CQ|y5ich|yl5or6*h;EkOZvrhbJ2Cedt|kulO~>Dop^Hl=rQ}Pi%Vm>#j7j@ zUP$X#!H=ijOHttmGdJz-0;$W|-R{zy7u54}HSA7{{C-Y8#}LyJ(S2>@TZp?jU9N{< zLG@slyzacIvTpJZpr>)oCqti*x`?p;)EqZY1z^6Rb^piP`r;b1mCHE%{=}Tmcm_EQ zY==6hQ9P!i=gaamRDK-;BKZcazs~5r@-^rf*(Gf4g!mQb<$0KkmVR>fuFhh;=#cQYqOyrh%4occB@v?oHuUIWF z&nioJE-v=m35tQ%uT(7=*pn65u5_Jdu)ST3JxOVk%lOXXnLPeJTM`!`n(7q)7Hssr z30Ek2j93>Bc+w-}>Ppa(KYEevF)rjVpLS+y-Q2*m4Jrw3A^v(hTnWk4s#mLR%_xM7 zx|AO7?jGqI&XP=92G}gF5|QjF3(`EzQ@a(`_4+qKLG2Tq1>GiL;gJLVa(n1P z-6vmfK^31@@PW18CUZX=weJhbHqIuMJ<%L999OP>a-Lsby{R+=g`He4Y#{V+S%lA|nyz5+2x{qovC5A~kwyFZUg&O9Ijc)kd0pFj9P zP^SZ2vCac?Qkl~}fwM9VlVd08Js<;Y_L`as(feld#gf4RXJ5V`+8+b=a3J zU+Zi4hi;CzT@%u(xq7ufMa$e?SVq}QTYUf*ErjUZ=%*Ve+VfR zgOoc&C|oFI7zZ?}$>{D?2)@ajl3y=gNpy&AE8sa<*{JjMLrG18ce(eolQtOZBz{>G(w`|H-G}$O}?-t)88(igOVYg!7 zHeU{SEF^?Jkoj?~Wa>ip7xGvm@-lQKg_hv=8G1@yMYc(fNjEQeeuRuCz5Jk~tZQ|n z-9C2-Sq%*=;uc&%Ir1v)b8}Y)>E+kTJH;Ou48N%vKcvtW@UG?-9P_F=iS?{HAwn$~ z+^Wd0o6Q>-6MwjPMV2vt6c$sM zi%_JF_c0CZzsqvH5VoqON_`kAcQEiUbox#`9A0;e_YD~C&_>MBNwE#5sb8TmmDJB` zc(B1+&>-4&9z3qu)K&0X6J61I@F7rsR4NM28g>wZJ^^hX zpYaf|5yeVzFE1(__ht3T@5+l90G0a#ksOPQ3OvmGBX)fQ3?8X=TSTLXZ;zpoht?Jx zG^fLFOwJZ!00aBLe6L9)!{@e~RuH*q`^0!EZm7pBrUghzH>7`WX4}cN)|I>t%n1%V*n} zU!@E;Zn%cOeo4he&E-R=ML+QT`hhV&=4)v65rj);Wn$+|m9X}w${1xvc$ll4t=SF` z7P}zWyC&^wHHq50P^A-EqLlmE+xf^vLxpZ*9-^?$p1#smFim>d+w$2JuKZ!b3WmA} zLhE7oA37!AI0fB_#hvd#aU|Z$i#9$e9)9bHskrCLIsJay^q6*V$>*iNuAi?L;ZnQS zr6X_Kv|W)et11*dw31^nKkc+fa8tbDBfnLM%=;r^*`s)lD2{0{?ils#GjG$5M-#5` zWLd#hs!2Ow88KUdDI|`rJK+6}~ zO(L=L62VssxicJrjzf194&1=wXBYNMtM>wjDtvA)FHSiDK;FTMu4>r9>4@^H85*cU*`L51OjzvqZd)_kvgAeMIi=;7r zd9{8EHj(OStaU`G@!g(yUvYZxKIuBboerp!et`?5Lcwe6jv`18&(DH3$~q&wr@8VD>w8h;D)PUm7BE{WZiWYZWVA0}G z+^x75clW}w_~P!ixGf7e-{1XQ$&*~y^W?shImu-Hn3+r_GbiVK&g-4$tDF`Uh&JGZ zRZz>GFFm|+XCS1M7>Np5>^xc9)Zg9fUWJC=+_=>?f1r?(6AsGW9pcP>LTV#EX+(*1 zpYRh%68=(RiWNWyd$g6`twZiU-g2bPqfBscVlA2KLQ)r82{?X!$X1G3@_`h04})AG zLxyTpOP33Mk4o)(L6|Z(K4B*8=UsiQ7rGgs`&93-Jb+8Q0BYnQbc zzL=a#{gGR=2V+&tH#U5RuF~2FZ(vG2c3d${`3{3Fo zh~Mdk?@IlnV?{_vaawfo46D!qR%_8(mD}o{Or8|Gc1C$Rfk81>rWg(b`GMH(wATg{ z&Utt77$Ppa>xUL+{X%)=J>YIf@~mG{1F)eL6##{eeKuO)r~Gf%Xni7};JEwS2_>dYu*t|XPkftKlyOwoza22l4Lge~HjiZJ9^K;unRuy7jf;OBCJfC&i%P9H& zH1b$ey1qO;3Vi7&CNv8ZcW)44vbTi1Vr_Z*@8uQb@4ZbNZG3TG%J|8DXD^NTNP8C8 zN#wc^eYy&e6=)cK)8oDrAR%Del_g7EYrGh0TdB~3m)0{An&}5)v0MU*E_h3Pa&<4Q zlLMi$Sny}dO5wnq*t%aiCn(8p?gN{f`BUVQ1wL(UN;`d=5!Pq@?94{FZlXS`7~!D4 zFdo2xjsrRNwLXeM;y51}xJ}otK&~DT{ylEWPnp`mZu!iga~}KSSyFka>wyZxeyJ-R z{tCbM&hr)UB}EaPsTNFBm}%ww{53WVX{DWXYHbrKYxOFlldn9|!kR1Y-f$8n^Y~=P z<}>fYsPBZAz^vsv9HymIFkjk%VBe9?^NSX*L&(JOpB4{7Rg7`X)F5!|92$9N5wU-@ zKpxn0>*$>5!d}XInc&1O)2wb)Gv_xh%(RE#`}>@bGBn-e=jFyi+V}DgNOG>TvRPC- zufT^8T1LJWl+y5Y2Lf;*0MzWlRe0RZD&FI22ldOq1b~b@v9UOU=fti5Y8-c-^EK53e>V5AIo7>GM z_SNhVct*Hb&a$WCa|aC^_dTb#eeu2%hutnNFUP8@J;R^> zH!0rV7K=Ck|A!Rc@w)dL$xEti%YRb51f9|UlH&b>nxzkvXqxBWl37)+vIGWZ-*23G zAJOIWP8B*rh}^|HucrywHHU;Y^+}oEH8cyD2uc2naLQZP#cuMB&;jpijL4D)kl86x zT)!ja2wI(-Ot%(R{%8qc!-CGWwonlHdy!Q04x`V*Pl|Jg+ zBLANZJAFHcrRFKbixe-0^A%6DwOU`7A||-y0nWIn z^!p+qQM;Yp1MTs7D3Sz(KMcq6q3p&jhM_I(xN2+vA1XfSf2eqP)ndwjRD4BbKIID) zj~hl;XSu&NgC_Q!PVXDfG(@y_Ay1#Z_seTP4ktHPpE;qv6V`%N7^uf61~R^gxQk30 zoOj-`zO6`Cy!GG4-8(-sp_Y)1I@AGiuc4)^P{k!H#iJIgaEL|HLO@ydrC`K0|GO*+Ej|3Y`V1L~~Q+*aq&VR(7{@bJe<7=n}@Ho7}N{$D2NW5+Fian=ic}6tcFw!|~ zoe>+HXYfeHAO6RE`*o4L07d#352`{*ML&Vp7N=Z#;Gp`H6Ivl&+NjwwF?!ugX=+WP zJ7c1mmteB(_7>yIU10rrFd)7SjlyGsc;=0s*h@2qbm32Guq5c0&i zLq}Q5b&RfA){sxtUs8R}CP=M0n9;O2CC`iqRwdO^<+Se=68u$@^o?jn{^xImi-tg# ze2-n*>qqj5!s;~a+mX!X?^vlg?{bu!$ObtF36Ve$3CH&YT}v^@70v?jXquPYxm{X4 zTdSBnC)rzrHOqVNFd#|t?tRL*b`~z%uNbi((Z*$7c@Co(9y^u0xrdOZB_>z7>{^0r zH1vycgG-xDdSMH*fSwjNodkpbsCYDBh=qRI8pbYtKNzk3g^EYmH^*=|$@j^=!*`}K zLut8gk6S1dX3pY?OB@W-9K;9g#;hjjypxeU0POY5GL*|ywSJe`B-)Bd?UguxuKK{& zjx9m**>)f}=!(qPR~tSkf;!dRbj#FR@I3Lgxt+gSD7vyvHDh>`JS@Rr=d)_m<(FL_ zhXOi-IDGt1l10EDY@g?7j4MMx@@G0Gkr_a{Ni=qyx{yHL;4VJ}4m_w3>wuvq;6_+) zQEF-BM@l!p1fo7&H_g&~$da!4;V6OR@jid9yY%j62z=Wi-s3VgSU+_XJ#8`X^2<&S zSEi|auwNlIUD9;^^+}$s#}8k#SFoJt@(nIs4K{{=>1&vd&x8 zH5)HYC)j$)H1gP}Jvq^f6#tu&@6;5Ld8BCv>&HVr%PK&E@$wM|X0X(#@^9@okkM1VmJ0f8%3HeB9HoIBvciA|);P<6h;b^W>b*qnq8U`p99zp#W+_juwhi9qH?o1 zXy?`F)4X(s6cE~wyj$PfME=&{y;GI1-cb!^;3lWVW97MH3c?cVhBNK7e0T8twMWWm zYnqrcdNziw8HL`<`2>2yN!6ezf2{20LYCJ_LI~5oJf*zrmUuKZF=`FzT>sGeR{U~~ zyC`z+slCEUClAHEpV3MEk&;1vtR$N|?B-W@Gbrf2Ctf6|?A z9WHG!b^RExA~d}+ivBIOJXCKweO@xdg8J>BX#LkQ%7MD2t+r==eM_ObO1 zg=Y9>Bk2=&4z_(bo*2TL1B+H&qLR|LK;H+OnkK zw^`;C`_rwdpbuN=k$a&0{8H*k+_j#KtjGTg#qdAJKZwr3yxb{p1)nM6XeErLKfJ|g z={*txXMpE&=tWQ~MF>`JL2*~-bHma8hi#yP0g`1ZZq?T7S9w+$3;L<6V;)i+Z1%`- zK^iUP7w@5h4P{JieTe_*n0fG8%26pG<8RIOQCBZm5Ti5JrbxH)ppzWMJ&)#y2m6_K z@JG7)>jO6_75Ps&JxW>jSYR^1r2FUBDHT8VL5oKUKdZl@ahGn{Dgd)gRKSO&9?R9) z2Iia9qGtz?Uv~jrvr~YZe(;Yc1A;q>t!%V)SE3=^w=nX-$(Nbq(`K)aihC|(X%new zP^mZASGtxG)jGLQ76+$Awixut2Bd>cMGy@wq$X-{^4f5MAB*w4E6-Q(+jx&w!ln;n z#6kf&DZ=hUYmsn6SA)s(CVw-})Pv*}#-nw#c>Ubrm~+8+Zlcr`SGUWj&MN^;WO>QL z&FQ*I3HZI|d!~ahfMFM5)-a;0K#(*D+DuM!HbsBK*+DX{1MT$wSFKepe@ zEHLLqV!T_WyYLgPtE2OEwL4*l4LDwZv!ikM`0%5SYGfCo)9Gk)V zY^l*7?Zv)fNkH)Z$@GSX>Fjg988wo{e~kZ$cp4Nn<6lGgw^|dB9To0M){9G@`d(lEo~|RG(Rf7< zf5K^_#TuC(I_U**La=cm*>o@(C(WTIUy#q~@C|($aUeRv@UUu>GTs{iBD;d7d$S`+ zT39JO-kC-UA`(e-r;8lO#chNHZOD4sI~)pmFgHW;Pna6O@_LS&3MP-u7z9D0G)My? z_HQqJjjhDmXpdwmmpH5UGo?&-``wWN-=eE!eVFIbl%DR6DfO1yuI1MIr$Yp{52uZK z)`xQb#BDA%WdQoKc^`#g)HZ?qTjQz<@|U9G4Yovksxk8c%4v^W zU4KRPtjSHdq*6teI}Bbf{#TG))7XR+a+06U3sbehE2+>d{w zvt&!`F=zFR%4>~`%Dbl24fc$zHr0y<#acZ2vcom+jssxXYQXy8$_s-x93 z!V?XnBbV%L-n-$``UqI{p?i;joMrl@pZ|k<$JmbW<%YFIwXV_}w_guOy2qNsFF82) zObB7oT(D*6*I2QZ(ygR#}2b8I=dVrt(u<@io1N) zKh%U;O-IsWeG}`(W^$3bf&0#L@G?2> zr5y90AdI6?^-$D@xOg>+FnNFvJoBm}&<3qm zscvk#Gqft4M4zYs)rI}m^Z(?H{eQdgCfW;#%m4o_{FWAKtF$G@N7fnt43iHZ5~uEr zBVJs1GE7R{H$7o~zAFS2uRD%LTSAX2BNNx9=cd4v+d`v7e#O?%MS9qrafa>^=`c~-^PNu)@VXw>9D z+J~?I6R|+k*A1q>8)nAeg91Y9KJm(n#a*EQen+kq^)Q}%~E%?D%<)>UF zRq4YI;d6a5uRLOTvy{7YZR!kuH}J5>PP?8ywAcRh9f+~2ub`~CJ_$abv49$GdCsjM z`QpOs0*|Z4V&QcZYG@eVu@7cn;jL7$R%We!_N@jojpBt8FOa^#}?8_DUvZ3HT)y}dV*D+YYclUJ6+?#~7@Uhev z6=kZs-m8X>o4w~dW!xn?Ic*Q z_Hs}(cl|Qk%-&`uh6p|fQ^Q5dXf>~}C>Y+?_E|?pp~wrxex?n_RkkRo*v~*lyh+kd z0lY<{=NDzmN=3)8GlGiY~3z^Z1-_=;$C%uomfpzeu-- z8jE7IR};Kux&jeDPUB;Ae${o)qSGEba81T>^u65_P;9EuRcEUis=aPq;rVEghPqc9 z8&p#{x_K*jR6W(%&tSis}WHQG3Pth?wkpfmV2% z)Vz~Tc=mTJPF4NJgny4-E~8k-r+oo-OyJjGVa5;~Qr^7-0qTzYdE@E*Af=~hGqWf> znQyhS(J+Xq{ylh179tp8m>HkvU%e4)^^v@TFR<$8vbp%AreE5<4uT^|=*-z+0 zemT63OjZVd%L>YD967vK-FF*okX)zdAAHzs;=ICNL$BrA1xLkHh18vK(`w z1Rme8?lER%Pf{%pfn8iqc-P}xim#dwJY7R!W%=r zz3r9nvLyH&bNUUb(A;2oAOj_pG3Z)M`wXy6f zcA0u|evp#Z%?<`DmN&*QbXWb0nmJ@VR5n5V2HbL$oGM(>K68=Qqnb$z;HRvm(_$$c z{~5k8YW987ved=hck!hgRX*_DxZmBLhN`B-oU>nL`yS){Jx7%3CSr%p(i`aVOKmux zD(toK)21gYW(zx&)i5j;7z%hp?59yeD3!goM4*v&*V)Yjnr{ePk|m68^H3S-D-@dr_n`#BNB&Rb zd7vRe`W}8I^xmhEHqty@?IMJShpZUWI9~U7^&!r!<~YR0(`_nKr4ww@aQ&{ja@rtwu`lB$muv z&uTw>+5fVjZhTLz*y+Skf3aZj{79PTZCmP@2eqW9%5xu}aGqY^(ue|21|m-Nt{K@7 z*k6+g>gq3O^qeakCbX&#inKhpgdbn2#4ylEoYxZV%?xeW<_&mN8qAf%bGVSTwQM&2 zmh0!zpGLmKT7L8r;k9?)wDzKCp4wX6bI4{zQ_R=-9#G)MuDN}Kc+?cGsN50v5dk#k ziT$+|YtC1|)p7<=WHlpCi%}CmQWU9pn=xYjBap#(zI-&q>-@OFhIbdT!jm)?di?Du z7Az0M>O&ov+LNdhe`C!`NhQE>9<%g({2w7fjV)DtDB}lSjZMSlro$Qxf2t}Hx*Led z4y)E6G@*yHenuEC%Mhq@A6g6{Lqb(uA#+ZmxaWecbLBB7!)RKfET6qa%)X?y5DyFN zy9jB*`l1c1&V&7sli1Dl0eN}mB!qJNe&DilGv!S`y~>UIA*Z$d8BI19DQ#cl`q}y! zebqe+RP+4Fmap|~AfCB}T*abN>qKwsnHGW;DOM>gagS@Lp+j=^R`Cpc&_=!UUb!o)|lvmn@*2I%^qdY@!K9D?Nn~9#^_0aa4_sK3rKln+?ZA$4n zhZ{`LJ@C#X0qG!kOHB=63al->*ZZQ=177tMv0sFul#*&PP>PgHSdF!vuF5>0um)@v zam7yqEnmUbQJz?PBlo+T0Liz=DPq1nKX-~w--m}kMPKF;J9nK;x<(2|S`MzexI1S( zI#Rto!C3^aGAJjXkXu=3%kWh!vjr=o<8j!bQmpZ;1Aeuvz27 z#c+%Jc3>9`@pClBd($6l>j5(<-ZXXx0a3jurE8-oR;*Vdiy0V;YIp@F#Te|Ju|zXe zHlimIy2?OVY-w-z!pvZl|(`BMNagS^Lri;7EU1xh?=ci4_ z`j8?Z#}175bn2`+>l?dE<9shzsoy`ty~dd};d%_W;-?w{>B+6`ZFhuphv8^&*ZvWxbgy{5mQe84GNIPPClYY!UL7fNR zldg^1u04HTqx{;agN&xT@l`sEoihjDr+<%at*Icb`$u57cqi`bD}@xdw&Y~oX+6o# zn9RO%vKFb!x~p5Yi^Aw<8uL|Ys}9pSGAgB!dOxi-E@Gpf)Wcbc@Id<}?CX!S(yeD` z650CcuE9U)PT|iT+}i^1WA-8kDpAkiD=zQg`V2x|-$D8hzOJA^3 zEGTxf`|f6x-mH3>9y80~L(~cx#1r+phrT34io`wV0@Iq!qr0M?W^DfS-3(9cUrQ=c z-#1i9_0b<$9a&9qH0!}c2I~7X;mpqdJ#NQXIgiS$RMlWEsYr^}3f7m9dZDL~m-S)S zJVGC?CSqHXeKqjXe(i|9Ug<$RNW57mS>;wVdlE%8?CBTwM84T>7v0Eds*2U!omw3u z^}L{it~Eao87SQuG#dfe{Z1s7pFI_(=ue@m&7iJkqb0dhC7u?5Z!&y(uNmOG_4Kl7 zvGJV6HUqrYpSC5Ia|9uX5%OCY@huZ@1Tn~X3(Lm-*u3T$1Hb)2wH^(JHm}X=okFOZ z0l;^+mJk=v%^(6kfLJ)%divq9*9_`G95UXPL!7%vE@5ST4Q$UEr&?>xpqHDPjk>LK z*zjv4fkAEFB!tEvcwE0}uiNoJU24ERa#&$nC%h1Zr+NALY+$sIQlYRyTq~Nbo^n<| zTL9i$n;QuCrmXI$6>IDIokzqN6`ta(a5i1~b7|5?r*t*EWAr_+iBc&%0WzgFlRS z`G&>Jf6*FUTya6Led++xRF9&yE7Tt#_d(lW>f;W8^bM4n$t}s45R8PDvy~pc$ zTczm~^BI;-$nG#cGTGweXE>)xC7@7uck;#0qVja8SjS_3QaHQGsCsdlk*~vT*XTgQ zIcH_y!uOWml$2ic zl;dL+A&`(|tGs5%FBdZj8Y3JoBvD)rj9}U1+B>&qc|x4|=Dbk}rMP*8*YT5LAL&L$ z!B4BS-DNe79@D7M%T*WvFd8t9cfzsOL}Sn~j-FJ7glW^T?!c}`NLJU%1xzuib|w+8 z+g(#R@yL#b-tdlBXM9U9AV`AecM_Bj0HquMGwO$ccj~94e9X5|kD=N^-h1jXG3kV1 z7hVTJuL{E%ey986{o}rHs|oG4J{9p>i+6Y72e{cMRBK%c3ki5Ot2$Yu;zDU(I6WCn?{f7(ORM<1H_Sy_E+#qnI_l|oBU-|eQC+?<9vj*Vv|T`qcs z@NPb5xL`c_`ppPF6X7c4etLA6F#9bU%ctHJi)ZzRgy>PO_J@j*Y_ zFVH#7DlSb&J$-@u`oWrMjZB{}#1tbiYupW=iA=3=h>g^C*7}?aJD>?7*MZJE`_^*q z^>?oNxn~Q!{<_Bu;f(W&NnPfuaL+2ASf53Uu9~HgUm4X^TR&f#_E3?o9|kz}M;I(u zwD?>*02JT?uzLoIPlq4UUbB?x1SY;0hk2a ztB)!t`(oXVv$&=@0?P43f`4@ctTAT|^#vjpyDvr3KeTN!-DJ-bc5MRh8}6*kg(GaV zHZep*%VBI1a@mCmsBcu+6>=a0m2NLcy|)jlMz58au>IgQT4wU;CTCKab%k(?~g9qnl*@RxU=uuuwt3S}UvT=-;`gWPG|H zRi^WrgqvBr%S8FC>dU1s%z2@~d7km6wPXUy+7v<>oVfdouu`Nh(|S3k6uu@2AOT;K z954|&*Ep!7KWf@kuCSILbFnybnPM8HZjB6VuZsUChHt-50Nw<-L|W;b-!?`(l6xv0 zibPwjfD%W4%N2*_-{j2+?p$xQWa>@Zfhim6W+L@Goi%{42p~}CRG`J!|2d1>XwFoO z>aeC{fPwf`msob6oM@7CLwgU>kAB^#6eFX!XT;P?`ZQFTQUIFM|EM@tEysafHKvOC z8eCQo0%M%>XA@QwCAj4vofTfnPrm~FZ`C%-bl2k!{|}6MX2$|1dfrk%n0L z^Dx`G)pOH^eD>U#Ou==;S5L}jckug9*_xEN!bffBbX8p+;|M1lo-99S-C}4yuC9J> z-d@!GTMMukSu&0DDTHl;#j2V@i*4H+^<)i4sQ=GKy{`kAKdQ81DvwCF3|@0 z*JAug$+(Niq-w<-QmwUt2EX`wf;p^QW>$P*fTc@+j9((t#|vszu$2|7zvm=N)SynK zC$iYHvjLhxEv=sQ%pk1dxA1(!H9YGR8S|(uXi#ob`qdC(@`P2$hYPdn4mI>3@%MMd=F{78;s#@h8;OE}OD=ZmM$J%1PQ5n0Wf=H;G-grya$#Y0%FE3JT7=eHt8J8|jMc zQg~~+pJm)}jw+%v+tu;QsEZDlU}`dGtPYex)KCw(a+i#Mvu8QAYSJl=u0Dd;Wk#ue3)AWtHTD!B zyJb0NwHRA0H!hO{kTl27DU#_h}_`B&J)$FQAOx+ElAflt4{Gm+?&a*EX zm-l1T{ad*?^~J(^U`cJHm>UpCWh;rNY#dXG5z!M#T6Ob0OT4nPvM1Sn@Uio7px(p& zpS+$`hs&a#29Wm@jccVz#oq|};L6^eKw_NvJ}PPM zEGV;;O)Y8{!FDkaZ?Nk@#CGb149pC717W`4=_tS=-FZp{f%{sDC=oC zrTp{Ux@0u{$v^<0EPA$)OZXP(?GOPP=#tDW^!pz9pX*MjUEiye+S}s)+YBKKk_#iw z>GY`#y;Ez>Rnyj4bESH?6vk}{4Yp^wD}`GP;*ZmRHIBp{n_O9FIyLc)CT_-(2V@+f`On18S?gb?pH6yyg@8gYd3Zk< znnj<49MpaD#my60zG|U6<9w>jPu}^cz3Fw6eN$1}o8$&`W9u8~0&#d^vS`3K6tQrM zm#+e~Pw==v1@5xcUw8*!8%Hb}wrT{nhQ!4R;q$oAV z^i|Uu_`F|m7`eg1SsTlrpqH;NFqV$C?feydShr%h3R|<#d2Zxo?dEZ+v}^`b#|Ey> z1DfUpX$;GEO8vS5aacsl?FVy=1N3B!QlQOGXsMknR+M*y(nYsN<0gw0`d|5P6;_&b z^>45BZESB#dNn4D7&0l_PgiD4LWa}Rz1Q#tg-V*=Yi%0oSv=5R0&3BW8ffk?lid#Q z-zM;F=pCu2kd85*OHB`zYUwEP_XU7Brc5cE=}uaxSLM;^I}AqzKUhb^+1r*`B)R|k z0v56cWHluRN>Hg}$N?M1cM+Q-rX%zr{3Xfts{rA^WKvd~olJby)aO{JXZX>GcNIwg z@cQdD83_&(kE_`Y7TvH#2QDjr!sPnk5W$#CGby>y&6fd0gwX-TW}z-?HqB(+F|A-9 zqtf3NTZS!RDPGu8R`(jwO5KYxe?Z3O66RB~Yizgs>Ug|ILfAncLjLJEbkCJb6B%b> z{z^A$U0M*IdzMwzrQq);F79b3E!NaMU-&OrE7TI3gURiY;qi{J*d|*c^vD+1^9L>q z_vN7b?nx6aWpzD;XiX}sUa*&n6Qq6O`RPPvej_{kMYF*L5D6^z;x1(ep$hD)9RJ-L zirHATJN7sIi}Lk27cn0PuL;T~78pCLPNzqYoDT@CL18`~9{Rg=G7#fqf9%-J>7E)t zYj+&B^_TwZu_yem_|1KbP71S zxUt#Q9`ibO0VAwO!FJFn^*kjxDsc<_bdyohi9VZ>M;GiY4MOG!laj62 zkr>Mjf^*1zGabxHF=1To6Ym=MWN~*niY#5tSzs1G!Ewwx_6?guz^AJRXEB!arae`q ztDhrPG&`EqkHDfigj78y?LBVox1ell4hxL=UL0O@j_%&5X_rn#>3Ss2$1 z(h*PUJ<(Co|4nr(<@{;kyreD(I5dhmUn={}9#K{reZJ%Q9T5N`gg0&Jvfha=5d_tM z7E&m+HJMne-Gxt=P^>%7cUpQCrf{nyXQk6y^PwY_k!>7b%VprckKT{w^<-;;xQoN^THy}1B$&bWH^ ze&VeTJYVR1|3@r$s7~i-SKl#hK(g5S@TZC0dejV8HK%X3vXK(r04Nixa3t1uAN1AM zEI!=Zp;l|V95>|jGiWR5a8bjHg8qTSI2u(fgeI2UP|^sNE%jX9NVJ_s2X8#Z+M%&3;`*(RdF`W!Q#9e9wF&(X6Aw)et( zpI>pkqUKZ0TIp#*5{u22p`&8m`8YJK%tlz?XpNbs%Hrf!Yb#F7)km+AA+jC{e ziMi?ZL2!&>-(*Y7Xc>mUY-#97JbRFDc zaxKR9cXY>|uW58r|5vM)j8`4I0j>m{5-pjHk-{pBTh?sRU9CVVRao?4`(eSBwV|4M zct|p$iBGrzv{Y=Z)=suOM^JJ`-CrMs6qr zXzR0#w4Qsqa|3Z2`i9$VE%{WB_@sDOj#U}m%y@fAp*&B)6wptaTeTFM-~y4e{%rl4%j~o#%qfpsD}J=ot@-gYlsYdCG)t8S#bdin9*?x# zWiUe)WsnAD51!3Y(Q-st?&twg|Jics+|N<k?(WS9DdEY7F|yv9kqxS(+a1U|9UmS2sT22CHW!l& zw=p=CoC>5K+5AK#pNP{QyC$*n3NNh;n5VJi+*%#;r_H^4?S=2>7Dvua96wCGQAO2^*lG8Nh$7alzJsq^L7#p)CBIaZUR*>sd*g z`j4$I@6wdoT)6yP_;Lk4<(J6aj2e(@mSdgb=Cb0qu@h8f$+WCjyE|s7OIQ`ozf*vP zJA$k!Z9Cou{e?%CE%$H68?QK*;$vi{8yR}??DPU%a_!_+Md6&e-x`#L2K@wIJfp+` z=~7tln6O<^U4N%-Qji!QWb^34+3+KV%$Tue_I&Y{9h_6%RyDg$>3N^(&$duQXi3fT zF|G0mt<+*kZp?MPoqB1ePUhuIF;bFk{;svhxLS^+X4RhHrNRd7r2B3=>%HOnUl1nz zyJ?Q?i&k%`MfB;0!rmb%8=QuY zPfa$qR~VL-{F1Q~uY=>sTb}T0t}sJHhv}3`AXr53y$&(8CDTny%H##ANShzf8*P2; zw#K1N-T4Ng!Il%JecM<_17m>>e(hhz;ToGj0%)+uPld!WzIni2n@u3$%ln44JJ;`0 ziG?d6rve}j;oA7|63T-RA2Eup2%kA6p|_H%)+9p`_NvE zKv~k{R6MQa+xY&|kECF`w{QK2w#8b^BiS!#KkBf4(_xkObOd(dRh9R)2Tgf-T>2Pi z%Lqe0y5uNyV`$_QWg{c*&(-a7xK>1W`fV9u0#rx^xc!xP_ zj6kbD+~6B*>GtB4nb@P1V6LZ;IvU*O{MC!ORJghz_zIls+(ATlk&1Ugk`dQqeHg^j zZ%h2o)3WG+)V$X3moM|>b+!G2cjqk2?(@12HrEzt(dUa7zGm88B$!8LH)H;iIVRoV zoC$Kvv99NP3F+hExcddFyuS&~c2J7$-~+K`WT{>IeMX&iqO_iA_=QGlF_IR~3T?*f z^7(z|GJSmHjwn@zJEU&o=k*M4TlQ>5kLbPoBqX21fK{wO;>z8kync84lCR@N6@rOb z7aE#7k3Me|v}AWS#jRcQrg0j*c1fhrZrFs}x%dslzVC}&5Wy0SfZca@aupeJy5OQ; zx>Af?(RY-mGXZ*T#xj(DH82uqHuT&)WhfgpLX&1h_1u(YC|fk7l4s5v4?P*&hBYZw zRhbsc@RMfV(aw`uDzlFp+hlqi`B(Di7T~Ux^~oLnt>mvLz+Eg0l06)*>-LFC+~`5K!EyJuj8-bMPv#` zU!vo_RxHb`JUo0amB{K$l*??cpMLvy;*|ogg5>O2-^-fMP|VzSht^C{$_rz$HUv1w zwMV9T)WmzxB3RTfSkk)WlG{h+R(F!xBU3%%PCUXR>lAO*nw+^i{8z?{PbJK~Z?Ifj zr|ozCxC{a`T2~H2Pj!lUqNGyMFEu~%$~;UV9B*3^c3QnJ1*$oVR`7Cy@9l}Xg;UvP za|%tnh``?5bmF(Xe^S@O{yLgX-S{?%*6t;PKT%Taqo zJN|9pJ1%Y}Z!NgBU-0)=iT^wL?w<7%LSh&mlVz$nwzgh4#~wWp$7ZUxFQPrnSA6*;uQ1t! z&n%un|F66!Qs9@KqL?E+sC)SzPp_0Mtn={w ze{tue3=nS4Clh8VCVn#x&dxu|r2;w`cEj?N^`-Qe{DzvLsr)Ls7@Xp9b4WTyOWpIN z4LGT@KfEXtXXA=uno7kl_;qr;Hn)htcttVEE~?LSp=0hVPsX-s5h<7aAFJu>__IsJ zYx!3=E+3aW;JH`BY2%<0mlu~l@@4RAYn87GJ)zmsSzylMZpZ99oE074TaCQma|$kT zo;h)|-3DEO_$=g}i0r+}vRa#tP-NslfLa9vsckx@mJZFwL@ z)(6^}7JwG?{L1MbUEGF0gu04gZe|ZG8E(^-17O1k_@Q@90)Jd7O2+jVOwU0))fb&R zC#~kN5puX&%B$Cqwqry&-BSR#-@~qe3*aN3x@PXaS_NTrOltU0-5xt3fZ}PV#LSsdARqm35RBSMt5cG}C{5V+-M_ z3abB=BLMkm!!)qVPH74b_+*$YSpD);E$lg^3XXizZs`ZEYTvvE3NFovdQqm$ve{_E z@^rE)0D>?)$U`4~+e8sSaD`Q!vfzYy00QMk z({)hLN9+-C9dts(R|#XTL|>oN8KFMA;ME5s%< z1e9=vFKJAVYkA*X$M_wjLuwy~5FNz@nOd8%1vWn}e%$!X#=D#?9sk?Cc8wh;{|1J4haCk5_f7U&aUC;>X|SiP@xepj z?497g29u28hAnkjhqSXX5=Z3SP6U_k;4P4J+5pv=`a$#PPBz6X^z6W=oK{R*n! z{q<2Mo%9`Mht_)DwFoVN_Bhtsg%QBVN-Ty|m<-71>!}PU&O`^t@a4qsdPzJyrjKvr z?_?=%$t4@{n2F^Wo;fzLBbH%f57yM69-FSN`#)D2b{L?p5s6|*ODZqZ2<=4U@i=?{ z#V2=Dr~tdj>~!#|v+DZp!?U~^Oe6YV%1xO-U(WSY)}l)gC*&N!RsFN71FqFurxlPL zdbi9{JrFSBVtDTXUjv!5fO2-OjiA0%-v;B99_5|U?f;@2<{RrNPyt(8c0HdyAzy2gL`lY z?k<7g!QI^*1_mE=a0X{5`M!JiZtd2}zx~nGQ`6n=d+JnA_f+>e&wFBQu+=1}O<|%j z0jA-9i`@kg-o81vde7qxsljWkM?b@&P8c`%qd1p5yZmRl(He1kd6CMUyN5;R| zq96c}-K^5t&xMfPZJ95&Kq3XPVH0g$PV}e)?>2h3ze(WxP57d_zv1bdW zg~$rW#y3Ukm{jv_bG7FFj7qyq{NJJj0xx2Z5uM+W=-!17^k!*dv~|3Ovc9Nv=_utm zT?4K7#PwQN4Q3#H9_Eg>5(S0s`O8{ibx4jfczrnCQh2&Wc@Tf|F#(V>ZjZK0BTo6u zj&%faqSh>O6uDz{@Aq$3{R7K0eiwV~bWkv+ta(E>uo1I;vo#Sa){gRzPEUVk@uP^_ ze1l`;eiVs1W_@DhYyj`Uu|UoJk@!h7M2rH>Y-0j&1Go`Vc)$%5Gu}|83>8b=!WN-= znxuSC2o($M!0*i#y~h-ffJgU5T^CqLMzv%$^O#7#f#>Zwjk#l8=+Suav;4fToGuYg zMnQ#09rGdWzUAC(xe7L$S1usz=3?+Fh}84SG~~y{RYxnhZYjgn30;ieqbi>8G!n0(OD2hV8$e5pjAy= zu4#~6WnQ%U%-s;i2##2fNjVr&24s4mQpV8)48TsMuh9YdyEI*UrjoFmqnV9QHj_x1 z&BG4p5apF}wgs{>`0b3Fxs@1o^bI*Y0~ag7gWnhsoA`axaUeB-5MdT?FVqXC_gn&} z4#iXyRfSFw#Nk}gey@`M^mFw%O%thYw|!kUpa){nX6N=eP>cAqwN(G?UcVq`Gg6G= z)mtlfeX>OJe8$_Z$<`*d-L}!yM;TcTvG{seb`qzmWXv)=zPV6iyr4Pj=TQ`KWb4{{f!NcdB-sWB9Z|fcxty3i%WH zlM24C^cJi{Lf}hZOUT&~B){z@FwuNNf8})l3CfE7y?sSBdv)+~Q1=OtuI5W#0~aG_2TJ#$0!7juufe|1x^ zD>|e(?v49;z=0}NmKW*|-VpsT?7i*1{l}O`bE3jayLTSXiM&r(c1yWOea#C!1Fws= zhu+V&kV6F^LIMz}rd6aJAedsrJ8R7Q$fGglctdpJk8iKGE&9WOs=85?a#vJqTlA6~ z7<&ERf%Q_n$UpcSlSDi*bGcsKk=)8^^r2VM&iRL?Qof9e4-zh}8n3R1Il76GQzI?s+*` za-%=qIzGsF{@b~@zVuz$wr>9X6H`stzLVYA@~4b!sb?)`7Uu~?)$CeX)8wA)^Dt%p zRkfV*FZ60-J$b^zbK>iuV38C@P>eA)r0XA|Ugl`%g(q2hM6qc{;9^8cvI({@(X}}9 zwJ;HQv&!wqVuW&rl4)O)yH>`C$s!%$^$ox%=A?_#@egk=b5#ApbF@3ljo33QSmauF z(ZsU~Y^+Out%B!C-$hwn#fWX9s=X*R5e%D;;W=$IVRW)x73yrKm#{s*YKTqIPgzsN zn2qk~g#8auuVAdouvlx$cJ%f-C0OL7sS14DMG5$mN#aN%w;Bb#p3sNb6UOL!uph;V zzzBXen3NwTl4LkhUk8@~n(z+2?yGm7AYC!8BHDO;M*D@zoj4csT2~jw-zyl$(Eo{z z1BRk4Ew(WA*10QCPVhGc${S(Gq7rPC@W7+*4loFiDBV&4sun*YH z!U60t>q9%ZFJ5}Fp?*O3drv8Ga;hi0hDh)yNZ3FSzch}F7Hj?ZR_fY`7gLPI(Smi_ z^X9+_*Ez5W*{xz@dz{CQP|>N0iQLYqNj_6<5{MfE2Xw2DIM8Kx%#y%&*5;Zr{D|0&f>+0Ss7UJII7O#D!hU@2^R^0sDwL$IhzVvlkm7$ zO?afoE#z5wh_p&5vu@0`=gsoPh=LTS+s@+ik_!4ny}w%7@h$|uYrmZWUytN4B}Gr95Dl3ua4fv)%TzVcTzRgNlDw_rO_%I=ZId|L)1@#R{|$!pP9^h`t`m z`7n}GmXZ}Sz#yh{L+5jY=tioL4DLGvDV%4&vxq5hxrS8)D306ca6ieE1r2yRS8)ly zOm@%eSTW>1>p=&Hy7}C|(EG#IX7T#i(T7vmO`kFgEMNyc@MTJ4d6+yq0HSOK!QA`% zDV5e?r~ZVUg(xPcYa$C@0fGC7gMB*VDKL6nK5Vs%A*%sq8 ze{6b3C@GB&bfs-!&#IY8<$aLDwwtMh)S)Kz5HKt}_;~6u4pEK zZ@_hO|Nm6q+^~6z@4gQ7kjYZ{Zd}>Ov zFccjP?HPCVB2`}_&w;+7RO=}vi9aGQ)?*ofotyZP}rl#=$ z-PVYiTNPDsL_+J&8x^Cs%X?m1PC~;?spM#P_|XfFl=WM{~D+g%>jX^kNkkGO}Q$ z6OCb~(Ki{0#TNpZCofz?;o1m45MQ!pVnYN#lS~I*4uUqj-~i`Hr8C{h3Lm#WFQ+WXuK(sYQPM*%XR)I zw=XQW?|N;x9kn`YzNgpBOag^4Fe!*JL1-o*X^2Ae_-7 z!jWc!HbSNU@vDBmC|ySb-NJ}#jO9hbyO-lpr&=N`PlnE@OiZ? zwRi@;u-{Jceyn^$Dk{SvndvW50AD@WHKPB<78}}kP<=pgXil9OQ&HfH7krY^KBHP+ zyun^yYF^?zqk7#;@@8So5A4ic48z^+c6V-Nh2MZs`DOVK1wrx*&$-11<|Uu`5Kjtc z#xm?&1)E8J=;x(-3{HU#g(`ky+1y+v=oVh2qajH+k5w)=52AsL; z%V8L1Wx9u_GxzS_3`usf&KRiG#^RmToYa0RuqJR)!6y+)g|LW+zd2xQa2ds1W=;kT-sA1)?>fr`(my6RSgyt1f8h;Krx`K{a zi{6)~V`B1}WCyUK$lq09j_YFKgx2DBr^bE^;J#;&N3Fqy^CPkxh^7U_S|IQhf; zdYo}T3yAl*cK0w60&Mt-2dYJ|F7@6|{+Vj(zdITK@!wG`m|$%|M~K^~EkQy{@^lQb z$rvi$RA%r>YPSyj$Da>!kafz?x)rAuLbeF@qFz&T+&%6h0sH~zDKaFm8TbR|S2<&; z0=ezBB86eqsIbR%RsQw_$%v!*&I^CTij!MmzgkI^*gx6N{>lDVpGUROkLG?u`GPVU z#a~NUKBF%XBm0$Gq4%a>JMQ-+X<)d05Ie{B2z%ko8`;V8AFb4sRp$YnM{C@**U(-* zNgLLH$6g0i=T@ItS_J7I`D1NwC;JXt+#ln^7ND0D7P=tET}PNZFBd-TOkUlc z8h{B5t(DZrIW-kUB*{*NxzaEQKLhBl=#+mcPRoaYMx(eb8&5<}%T{-@LBS&Csh-;_ ziqGw(sE-r;K5KR5Cn#}sMIm8v@6Yu@!BNY!k#)Fnbmr$ra1iKyni?&VU(Xui2;xS~6$-23JmF z-N{ys!cIxtfnmA zvLrN-?2!*>-l)f0)f^--dTl2!F25SWo--uda|yL0xMxX4e{7!@Kk?w8M0O#7DQE@&=7NMMx=U(dFJK`<^A5@u8N*5$4 zFN2y^Sf>R(xBx4^0s;chbiWfm%^wFuv`h+{B`Y@Tqbuxa|6;~6KV$3b`SMFv9&L+& zQ_n38ihk89pRE^#du5Zx_<3jOg4Wx0#^MvDN=ro5jGpD~g^rs?`Bs?AN}|Hs<9EFu z#)8GdtR{)oa&`Cw`IQ-+fGR`8VGxR2cYet-b&-QMwBEdsA6VtnLvX~z)adc zLAQL@VKckTOr&h}hW}S-^(Sk3jMKdPm|E+r`?H$nw}$}#9$(#Tm)vE>vbnzL-}oUB zhb+BLYztbMI0g|1+QTl*jAU(F!%!5(&zH|7NNpcB2tpPpFwETBP=k*;OWU51+m~tV z1{4`Ed&YSlN>+|^BVz8&W|j+=LGkqtU(^?@FK#zoh}ZNYY7Y>4>XqO6YLP*^0i~cA zvo94ZhueThq4D)qgwm7Zlj-G8^&3mdY+z&pC0`noNc4EX6y}w6pc0Q(Bi}Ff=3JK|HBei@EOQw3r9S+! z;{2_y;hutbQ7T&G2O{T=)s0h0u@>gtlB_p8#kD%GQ46dMe!WrS+{cL5?UmgBDh#keD@v`x4;(tb#^zZt+QOzl0xh?!RG4#rr~q7ELzuRT=sE8Xc`NUZCR<-r<_Mi z&-`XpdrRnM&^htutAmc3bm;Tm7alC?qrq1I0lQDBhX<}WF=g#th`pIHMPpyVTcRtG zpEB7eh@34{lK^z8f5Z9787v=U5VinoHK`KCcvs%|9hXp|DP= zfu=e&1XoN?+0{M6DorQCsO}dRzn@k+`DuTBnHU)NwU{WQ?2AClPv)tRYxY1RB8{GF z+JznA!NioM^Ty;orx1YQFF>B;T^+1dM`i14 zvGnAcS@-5gJ5N0)I(o|LI_|RjtQSkTSLrSNKyU?Jz57tV-ul8*$u-^)^Y}X;x{O@X znN5H7hTM#K@nf|vFZ;U6D@R6GhvW-Z;EtB&x|UAzoNXxWQcO*o(sSl8ki$)FhYY3={`%kEZUL2I0Z7 z$>rs%HR%w(q>ZS|#zSxap zW3t*+O!k~=Y+Do8%njR_eqM98<;8xR1`76-jqq)$49l^Bl%3Z# zdvMX4wj@Yz1kwYS#a&oI!oL5~RvpO*is04)^6O$K>>h0S%E=P;Fh4lJTGW3XzZqrf z9!M&toz;r-w_dc7O=U#JUK{P8N-$-p|#;TZwRu3#fv_ zCt>%dt3ge`+t1_}V5O_X!TmU_bYCRC!96dd-3Bk?d`8q{_lzSFkJCD2F|MTsICvaQb8@FcUXj$_sICA;p5 zwTVESB0XvOWAk1PyOpV8?EVk5UCj`IagPK;yGnKvi|fhJ2|UMWton%NBqAFh^e`7(VkD%U}#YyrQ0@o~)`(j6fnQ@~1+$1gU^;a9s(&kUR?GorHa zxA4#A!zQ>`VL#%HA|yupXr9dj`kYo+GrKX_6#_yfpt^YbbKP!}92UUxgpjDcMaA)km~ukMk%Ran>uxUX z*=NEwzq7qoIj~~%RHjtG7T41eyP)D=ZmO=QQ0i1?2H8hXjE!EU9c@6-c9M#@qGwLM zo*QgJ1|!GMTgt-m`okkRv4}@`hHE-B_*a#kwq<^;L}NFeQW7PT|l&>m$f#LS&A<^5I_fAStvB6k^) z99nv12(bSg^`rwVTiE^xB-{Av%mRF)Lq829V;1f}$m?tae24!o{WF^(@1rrg`bF|m zKrIip1(Fc{;#CX1V~b#N8;e?{coG%3Dr)f@WO{sh?0P*o+1<+(;B)uvV@P3mg@y*)I%x zYuxYTuJk|Kpe!HfWV$Nas>6My;QQQyKRD4}!22f0*Z%j5PeY6z%08-^Ky=p~dqa2a zF}nMXt4Ee?X z^vO=efsD|>x-qpFh|zerp^nkfH`bbw-n3;tFy@P77k#0>9wmtJ|!7L;g}IMD24H=At8Xa?lS8T{N1`6cx*<{@xZse#j7ZEPM5#=~{C ziF|fvVL6=5Zds^I@7EM2w2s?i26o5SE5%d_87s7a)_Keb?X#?pXcS&@5<0VzTQsMH zKMPvOepC{_G6=3lrO)t~>)00?Vsv(iu)n1E9KOP^rf(--K2f6|epTSJB&&Ho z1S2>Ja6u34F8jphDqG$ZL!gI{#h*UL9qi$wO@1XvI6+fy9A*^f*)sN9)5U*Q2GG!8 zEoZTg2M2TSrq{yXHf7F+yqh&c{XV$p0}nKjQd!yPbIn=B0$CN$hKvSR(||qW&7?x^ zSjB$>AJ*8$>%ApzedhdBI9$H%`({VD@FL@@7CzPW^@%$=($m{0Ff6(`I(o1tv%3B0 z>$9N@o}6h-*){$a6fvcORrFrSvLW-F8@V59ef#r*8<{+XfA9fXRIN$Ys_jFaIq*C%)pq25vT+A0?_8<%b!Wc?{&Z_D(|vHU_)+%bWAr=6E~M`eaN$(5!{oSPUOtn zscu$b3u`-7VAN1k`xf&kG%k|Q$U^x_ZKR1d5%9kK$&ALp*91doaw!M66!2V+`SR(m z%%%?RMP8u;(t1$C-35{6y1LWCNU^mS)XWOv!D%sf;(N%-@;*=jb(W8S5#Dgytit^u zc<4A`&EO2}+1?UTG3k>we#r+An|?<5BewrnYtO{KUMu_mLv(&E`~Ml8=db+_biVI^ z1;=Ov591YW`3^!+!en%H<0+!C*=v{WUd6EjB-e)LN35O2YO^K%NGO}OQo`Uy zhJZy#K7sDTNA$$+wr&Nw8X+b5Rcvz74rCwA<=SyWyFYS{pcTKvBQo{9(g&^aNjq;l z3>(U)MAu9_#o?lDzZHw3|{9gX}yu=65Lf7y8zOR^#=0l5HN=K@JtfWi7^(~n%b zzwErQ+=SVvlL$7zo3f}~Y?L7WyQ3$y)JB@?QMB${+#hy+G$LOF#?D87r;Tv?FYNpY zjGfPivGdk2c7DrBvB*VO(KmfF?kfF?Y`j_PrSGlqS7}VHC`UJk7G!!Te+(lL#Vck` zThsi$3-(6xZTV9A40-omds%H@r6gAl&`cm+F6fa)&phU8)Ykb)pZZE{&?&*! zh?F;lC32_0ZbCS&&St-V!^U_)M}L>wo!8|<9ym{zp>aqOU`*5zs*+bi(GvcVZy9$cMcE*W?PD(krzc?ERM>Fj{lyGv_w${r0nZ?@`U4+N5kIi8urKlPD-1Pj!d3sWEnX z&3R$P!)rPX)-#a(LWS4+NZr!F;wfeJ%&$DdE-(4_SJTWEncip-!Fr zG>T1zm6MUyBln$NL5)p*QR1Rgo;@xZVJ4*W;VH2f)MO)>*<`7R2Q$N9h9A?!Q_D7x z0pOH1mo@DW(<4;4vDq~AM;ZLbAB}yDv_%ddA666TL)$(C<#wwp^UF`b?}padN6JuR zdb#=1D&KL81&owk^b}XSs9WKCcpy4D<><tOgP^V;N6V{NErPmlIsPAF9;^Qg4OBwbHI47sS^s!s8j6|3)REe%=V z>OMY7L_XiSF82PsIR}p|1e(Cq`M%%0O7ifMn*)Zsv-6@d2eduOV4LDe8Ub?D?X2uisOM}mt(%=T~Nop z>{;YrbsjM-CiagyfBD#&4O8c@|ElvIIAP@PqvBxd{N^P8DP6+%wxAIQxHB{vamksF zxLYMPh0!NzwUS2c$L4qq-!Cd=a{pE5n;B(BXHGtI(Y%bKQ_#I4qJj zM^m_&lH+2ryvGW+9J3jss6x6ittR|_zl-P)c)0m%qi|^t@JN5J15@X{iP0a*J#H-S zWXM6}UPz_ub?kln4!q9VJ$2Op@^@OJuVr|e{C68BER_K{@ob-{JEcdZ*1oWhGoi4ibE?f~W zz`)JF=j%rxPY)=0B0y&||HDZPrnW~#(=hO3G&(@VcrK&Y&wEl|xj-^t(R^G)(xZX5 zSE}6YUC>KC{5}d50r(f3r}dM_PHeQuSa4-}CdkFV31MIW3liurK{43f3WkWMrC-R^bVEXs?fbS|z0fv&9M2U>Jj zDzaA-vJBsj*M;|@qS{yLO++TN7fZJtEoF!Yc%m~2(U5DyFcdD0~HT)jo6}F=cWAu7}Kv zM@AC-MHy`X>*wbOUPj%zF>m*?)xr}7d0b*A`j?Nryz|2ltv4&0hip_in#=KnvY?>b zou0EVY7+_uGn^l+E1CAGJDZeJ!tF1DUMES0F-ZHHuc~vv%>EcC;{UI(n}DSW|++ zy7}OJ1;^{GJ}@5nt;~XNWrVcQUq=a3y-S3wDZJeoXn>^zbYPjiwupoJqa zJATd}sd5rFg!Tq*3R>nSx>sEq=+NfGhus+a2-)d-GhN682;w>h4;jlG)yTGp3@k33 z%#-d8r*?oW?#qZ@P$KTCy$Fj<|CrowRDOTIsg-8GE~86gb*awNMM5}2zQuy?8xx4_ z%hSjAu=DouLL5jAHjwe3AfeQTQ?YRQ6%6(mDb3cgGh3_q6+^0Strnw&J!djs@oltp z+GKrA{xBU{Jn&1SB2!DXVxaWkqC@`p2$$R>(Ry56W^C!sacoJuT;T9b$LUF(|xD#+jf9c?fra*^hf12MFIgkHBU-Y<(^BQ3KCN<5kP7A+^#Tvo-7V|K<>PsBx z*F1K;Rekn)CeaDn@n^%t|z_;OTspZ2_M;> zHlYr$+0-H)awm&&hN8O9YIU|Sn7+s+WCJAOutrJ7wbDCynM<51N+3&FFt&y+yOtum zfrk z491_U+qIa~O(bRp3&fOjj*RqZj6HVsii{7XzsCx0gr60ddI9upnpC4NZrAcJ7!E}SaGp%%g^S4jZ%3*cmcGD$;UxoX)qIB4I^X?rH}0cS z$-{D~Z6Z}U1|SF4-XCw?mxbs#Of0AF)==eC>qPxpwpi0^yZzz`L--6%BX`H3=^Mj7 z++M03Bo%vnJ=h0)Jwli1wq0YM<;h<*i)VG9N?Tx!5sR#%1q}Q7M6$UybLs+?(%N*&}plybMqMZPm$ij^SPxPZ51u1 zU>VVVB5v9u&1xsr+@qZ1@qOof)~K8pepMGwez-k?>>TI?>sz(W!YS+yD`Ym!ZQlG( zb~Cz{`=Do$_lYrWEB4%F?$=13BX(K2MC&k?{+ey9G+RtPzdU-(t|?@RC7H|IJ*mF* zJoP*!+{?UNy-KF|c$DwtvSn0p&Esc#P4RlBlSosmFUMnBq`Ik$2+3CF;gFV@h{tCw z)ugUPmMxP@2d~JimsFLL`43-j+?ASbh`fZiJVs_OSZ&O*ptw5BSJdqh-1c20&$z_{ zX&fpY;W^$Wm)~MI)o()tz9dS)Pi(mWxBD=JMXRkxi}k} zq|NXDJCj~I>%W@xwByA8JCoi!X?Be+qv=8$77Z9#%{o$T}y!|7#8InqRYQSR)^^m+JS+>XVuk26B#b6@mjnUpOi zeD=SQplG=TqS;s++}10pFyQlivMoiaF9S0bgp*`-dSo_(4b$E2elXQ6;d;@|ac0V& z#&*iKGdtfEK<;j5tF6{=qWK7HH)Zi%^2%oC5f=zAsv0W-kAXCh41-Vwy&5YQ!m4wtmXJPE*3G|FTNIUt=)+4@rNCi+iOUv14Gm4dvb;5*xp~Opb_%I3m)C>7k!} zr!$MU7PHm7{l0|nDiGU)A#Rl1Z0E6n`L|7$s)O`Z&_nk`!=ZKEx;wU zZsheB*7s^?R&+>+H%kbDCUosT>&^O8jbHJF>D?7ps(XqcR-zXkd5*Hube=ul z5NTi*GN=5$<8ci?Hv}ZiY(F_&bbo<@=Yj?FYs;Qju z5&l}1b*vi3Hr^J9j`BKC=pFI9!y^$mJK=#^tBx2wLb(`Y1&u>qtP+jnS?j49ccC55 z;O9H(a&W9p)`41<&IS4k02yV^E;gq~u;freT+F@Q0!k5X1#+P|sXkC}8AQ)|^IJ42 zckH5CuH@|f9O8G1V$3IYK`Y(UHbOH)Jdd=5VuyF_6pkV^+WVVq{DXMj^ zX(q8SbqCMHXhRMM73`mX+x=J~Iqva35?)w{Mx-Qhd+D3%TkT1XKLlXz@d7adn6rB9 zF>Aif7YcMl4!Vzcq~fGsOyCOOtN2UNjpy1?IlVupF{nuaSHzbkTyW1uVBs#@^*0fT zZR)o!F+M0~pKgg7&CmOdBN8;KequDGS#u+62sL($)Kdx!l)qbFf&BxGUHLkd)ww00 zJzIuHhdjEL!L+okl4MG-DXIOKfl zgLfdyz?3go- zv9rX)=Ct!^FG?e&?S);K7SEbb4O=SzUo8om&3OAd&lgBH?8zqYb z&LMW3jOIo={mP1)C>A;$I>6mxQ`g|Pzcn7ftseKtS{;dY`ibah@D=T$5gX?IuaAi) zG{%0O%l?kn)S>5$Jr<%#zO~?!gZrHS(}T2p|4x^J+?!2jc$D5CD*hv=hq6@08LM@km8KIKUJK0?@HAZRrD3w1~fD; z;r=IJ!3MRBa6KW%h^UIv-uMw6Ss$fu2Y%BG;}Nc0IyA)@{}o-QS5Yupj~Du-R4U(C z%O$RA%a;0*`hk!z-@5R|FX-*;S3Mn!WCp9Z58B# z?a>TbSN0_eQ+yxHnctmWPomFcTJI~obF z$*ga2C?>J%IdEAIa3F^9J%zx`7mU0E?-o${E`sAxupm8jIeFq2-Wr#KNR82fF+>%b zLyQMVc5=aPu?Hhh9#;xtaO$)0DEo3X(~+&a-&+pih{+Sc5-T=3*@)mviW#llInM3U zS08jfhgpy*VY=`U)5l7U-5KTtxS+LSe|WShKG_tV0qGttQip0%>Xo^S{O%1Xqb7Pi zN0+xTc8tDFj*&uXjkPYzvEZ&N=C4Rns4SKnmutlnc<9q-Ic%!=N2NEq9dH00@RX)B z(OCgXTy_d(btO;CG0gJkT3{-@C*Q{zqxexgtv6S*jc!AL82#v-ckR~g*WYT-$;ArC zQ)8RKP(X-I<|38BFK-s`R8#qi_heMw)@kdH15x5rzrHj3t+i4E9S{n1j}tN#;SiJ6 zE%L4BQFMdy@p~iaa^y=}ProHx_CG2;DaasBHemeeVu#O3vALsiLtlJst#K-^2Y0{1 zkiN2OOP49kS6^t1y?)uumPo*wYS7k*QO0Ffr( z*1C`$3~q?J{H=XhPmtJyo9h>bT;>=ghwu4@+S(@`y5&~c??$sp{3n)%TsC_=#D4=U z`8;EUE4@BhEasP*;!9nIR~NxIDqZAk^qbh%9Zq!+R8Vb-}6(sAd%6o*P!e zoJ73UpdGmfE3qrCYMnrzB24VC@1c1levGVp1ke~vvuxP{!loaktAA6#30 z+qI^ra!`6WNiNNvUQ7^?l6IF~w3WvG=#v)Rca}Z>11jKQPyLpbPJn_$zCwb*y&o^s zt)88mA_=pnpmTqjeA8GURI}BjfP-gI9EB6P`815vUlBr$hh;%Bn@W#iR#AD{I2zwZ zLUh_|rYv(0&J5gF6_=GPTFH8<-n)q5<>>heuNW1_K*sZnZ{90mPnCZ|9ci|TN?l-blJf_q#u=rUhtc%lH`+ImCwtVK-w*rtocK;O zIn>LV5zO$}pJlemU=43%-#x%k`qm8JGkh_fB9iB%B9eIKNGjQ9sE%`Vy&UJLj)0W0#%l!MtfN!Zvvj#dz8IX7 zO1Vj1k$`Kwm>d{B{~Jchhf+#-Mp44|jztJd)EJP&L-Gk`8hUrZ0DUCW{GQFS( z!osa~Mp45uH>HHnDXP;3uIz>yr3Cvf)+f4o`BGab>NzYrcMNq0atz#ZNHS3)(NqY5 zZLJIufuOv6vOsLN%Rav7ZLYqsetKCZ>@_pu|BkmL1wx3Mn@8d0+#5|(!W6=9} zb^)a7aD4W0^leQBR@yo}Lz?^o?(1OMJk>5d%(aiYuWQ?RI`Y4-C35t=7KU2b13L_W z*=?c_s$ijkM|4OsUz34P(*13UFH_8X|3ev&0~W5`@wtrTM71OMerCtLW7%?_HR0#C z1z@LV^If!I%e(@L4iwEjSUCG>R9LLZp-mSWNjjo`c7uX$h`>Hq@Re};ei&&z zFU=du!`_^Zwd>jKmG3-#vr+Xo#?0_(nw7TEH?02|#y;@yP0+Gpz9YBp%D&Pn6Vc(# zN%7Ky)k2$|J49OS8X!1fi*cEePVbQjdYM4VYI1#;CblXtpDp^= zq*u9{Imkr+hX z@0}<6Jp(`Uyv&=BntJx;611U+uaf5n3(}R&YpN|zW90_QUaAv-*x+e$srKz5>nx%h zb6*^>n?Uy#vG3UzC}-(ni=Mu)lTmDP{?Y%sgwT?s6lwYIm#164jHhl767~DoHMUQ% zNlfB*y&0XbO;WzGZHm5C0Q+1NUuum<|JK8np*)5`j#9Mqbg>(Ohc0XZ-_Glt&&EC9 z3F`NOca#ZkpCxpzpWDBJT*G*T^mJE!qE7Z7y%XXx)~)`S^sf{TnKM5Hy)CqAUR*TD zYgsm+joymfL9)|m=TS-PsUizmf4}~dB;D6KmpPBQ10STuq0j>}>6a~OB5ybar3)gG zJonE2n)DOHZG&S8RpdIX7v*CYz>16yP{j1TzSg$nfZYQGSULgXDyFt)Csa@z~bN9kTwBa<#HkiGzSp-}~uqMh& z4?^={jAHOaXWDjxuz23~;VOKMF*H;ltV-y$H8Dy;k(xHg{hXSn^2o{74W+4#TeUHE zlzOG!ZI(98M%741v5M@==Xqz7=O{auXUvk0Id2T!%Eut>5ikEFrVpN4Zqvkhsx{90 zVT8M_ZKb|*9v&O<`$9P;cP!F<=x=AFquk_zj9jNGGWo`>dpDm!`kJRF7x~w>4GxwV z?~Qx|83HlBjphz}JKqS0zI6HhZ$&LRzJkF~bm!54LjkRfba0_QVg}21PHW7(1F}QkT9i$#r}x=o?!1=y zxIFH#SweK#uBv1|>t-Dy4g{m^Tqp(vd3Vl*_TJ6Cd!l%^_m1$*DTf23_}JIp@_Lfj zKjlKkzq(%F`4t;a;DK_^8XR(<+%Tf^gW*#tE=N7bGG*hqrWO6R^GfW3Z<8sdN)w; zN2JFPad~$J6Y0Z{|0j{2x4u8sV8r+zk-lbm=sejda+Z|b^H;@>KP+>5u;v>1#^c-1^#DD506UZ+oAW(<=`+ zX|S(S7B+vN`x($oY!v2bQoaCZw9f+j!+T>AUJH*<6E-OSC+Boo=>*?l%o zGMmlj^Ub||Q0=c$;(1Xu{st-1|7Jjn^n+X~%YtZ$r$F!CK?Eepu zo`DcQ`g@Q@j0qY1Br}P@vyKL`-i8#mWorw6UiJiGq+cUN`tjFSim5EN?o2y2QG&Iq zWXC=8)W3IvxAWB)F|QQ}MU$2@YDiLc_xjE?HjJH-a2{>e-8if`@=U@j%L1e5y|J{_9H~ z(yUi}+t?a_xf8f#rC3?4&4cIbYey!83&8zKDZvOgM2TCnv@3S?*OhnxMXYQGO6eyp zdA|o}7J4H&g>u!dQRdDos@$$PP7DG2wcKkzgu0WzROsnU!hzZ{2!BE3u)3bP}rxiF9p<(9Isa!YyC6n{lxy3&3`*U zn)IS7XRvz*2f`YpNk5PEr!*O`Mf*1^_K7y}G#s$KO^T3tl<`hY{W&}Pas??8z zG2L7(N9T!H%*1s6q7tSva(b1C-_~AP>&@R{$tQ?Vl1YOPg>F~?+{xF_u>-e$WH;GZ z-y>1_i3cP~Z;wRjnH@OJbenap;;PFz9Wt(wD7}*(sOQ|0?<{-PSUI=R3BYa9*cFd> z+d^g$K-%76X+Kxp^Sh(>n)6eb(WAbZR{351g|S`3cPAY#vjG1Wx$Er+z;CTMrKfSI8r%shHQb6r2MY4VrYx-OW8$-E?eF2 zvEL0-<0C8oPeMl2lc$S6jPD_NPS5oyuB~d%$bZuqB%lWt+luGjg?dw7tL+A9$(`%I zPD>w^HS;`yE4Xd75^B_u1PPmHS>AgA*Up@x#>~K`7kDZ+_L&Vy?74FjvJWdW8m(H);KR zGvGtoRG`NKWE8ORp_2{mdeLGn#_y*_$=Dw)G0#;I@Bkrs`OQip;m=S7K!~yWEsWjJ zz4X9M%xT%$*_RqajCc`UOQ?Jp+QMHzP8XV%jUIHg!fMGCuu3(}VpM~0$jf%<@0u~D zTl=J5PLxj^&!y!wRnTaAAC=!)^rktiC}b_$|Aa$J+g&pAaN90GF|!=)(|Bt6sEiyi zGY!Yj&6|1~pG6bkxyOhf0?wg{@RMay~<*3 zu&x^(nyO~yEgjh4Y6Dtj$2|^Pc}c7*K?>ulKs3C0TDd1Wz@^Q9 ze8D(PL5jLw`es&WA)pKr$W*_{i|A0LDVeQye+RI-a~fHQz7r9~>5zX$Elhf40@apr4e26nTmmTyX!nf*xlk(kYGIi=12FX$i46IpX{smtxO3t$1{6G zpVwDff6705I@LXKkG`(w=$aAULNN~eHDBPiDH_^3({6ld6@&0)r#ivu#5wf97W?fp z|3A3>JmS_)88E*~P1c{kKv8jSHK$i6e8~bmpvA_zy1pVZobe55y|=oG&B-Yb-QLTH z^T#x!QDj(X5k66t4YlJn?z3TzvOmg?r2c!j_FOxDNc@EXXREyrPptI}fOS393J6w0 znO&-&d7gP=wtR1YZ&zi_+_!Vfc?3fKqhF%XBD>679Iu)wG|`Bu_l~dO;AFXom-2Rz zj$f{(sRAwwL!2kC#|NL+8cDSiDMxJ@T$-|#RO_88uCWUZ@2*2hr z-ep`saQ=MMmRai`N!w;$>t}J?Q`%)5btdRJFKW3+0}P8Qodz#mOKkMZ`fE+fSgOR# ze!%HE&5-5s3knkZc=_4`?O&2&LC?5R&x^sAFvN8-_E3|b1|~BZ3(c%7785dpPaqw zX8%}DfTc-su;l-WP@B=xxM7dh9qu~1eb>p&; zqS#~5$W~T7{42wz+`N2x;9Q_lZd?G^uUb-WrVI85WgPZ+*P=17>T$RP99zvTFSh#_ z*GZL|1JltpBv;nQ zL}THG@dxI|`(Oc95~YAAyk;)H4ZNirq@In)sdYQu%v%g+G#t79KFg|D{mD4Bp$tYB zQjtqv*_l8%-e-<|Z8Us41H<4VeB88?RD&l2UjSm^*)zhrcc8%1zjo}x)p343EW9^= z0{&ab(Nu&FV00vM}&!vR0}=n@X}R|kyMSYR0Ce6Pi^l?X_MGN zqAuLDf(s>no%)I^lea{a%B|iqjH}U^; zUKx23lT3{MneFexZ2Le-GQhkmLAd?n*^{Ku=vZG7rF=gJiBD^@;l?Rj@$^(JP;^Tn zRtTj^I?Q*(==u4NR^;I^!+IWhlweP}p=}Y*-2oA#<_2sT4?a$`EMPt6z&eh%>V$oK z8n1j(D>YBzfNG}7NuJgpa;*xR|78>q{P}~-C`e<%D_p%$5v{T~k!i~Xx5f=sJ5^aW zXqVs9Jm(jJ+|5h2|Ac`-7J;If1HK8VmUd$+gP8cT8NK+V`6f!n>jAs?eS8_A9uo|) zdh$H*E4zT`+WYny{=;?c`#3`vfBd71(IF|fPBCh9&`Nb;3LO{^Q_3{8@Kfu`dy;V1 zLS9Xy&UWk3@x@POJP9c$AXSGIOPLbwEF*PaBJk=#EXR!z1zVl&=I|kcJojkhazAdP z^x6(k4NYon;yv4~6aFf}`IPm|b4-<@t1`QO!>035r~R9F8wE`557uADE{V=K)8bNr zM*GSUByecZdfbsSFW&7Na8|!zvNL3(U+nq!ru{C^Cj#R(XPVv=i)DHyzWw#-?aR&l z6tWW^dG08*Xg%5@o@I)PP;hzY4)B?<+0*eI0Z+xy1UZS*VsYrGWhX;_qlX`yomNdmT|wlE8zP$Y zobLKsZ=1mm?OQVq`f0$L)z1?n9Kmc9pz=)>R-TrO{#76KlZViIswa;--@up5u!Gs* z_syWlpu1q&A68rvuLm3hMFD~5=7Hxo51%)AC6d!=V83K$tw-im`5wBbB4PHgkr_&M zI{V+U&SRM*bLIF9uKH!gI@G@R90E^>?w(KVyCUp`j0FR|lW1sb2tG)JnFtc!27eBv zTYK}WVN*5mEsMk+6d*~kqkKhHnQ|2RMn$0UgJB6l)3HJg375LAm_DZoSLC!m3q!Qt zE6Z*@PQl!scYh_N+25k-{4!lDty-IY>NP z-zT5=;HTcD&>OCF_1vZ8fb^fEFLW~G5v9XZOx6-F*nPaa0OW=J5>!@?yYEK66`9m_ zw*q_(CwZS-wc@|;)5cVfjmp$gT5yNzwqB?W$vp9?KFr=ZIol1_FTSpU>2WEca#p>& zeM>_$&d|PH$m4l1m{twrdmXPh=-*MAm~z6c1}llkOGt&*3!c(MAh?DCt<8+7Pqhc@ zwzL=EnR=@@ja|%&P~;?C1>fj{ik45>ZDxh5Iy3D1esrKb6mmF~d9{yxPn=+Ytc2y| z-V(TAim|$j+NT{wy&M!vqINnm3@RNIyAc~a(gB}~IVM<4!>oU$-cwgze%UnRC&_|b zgda%n__0k!pKl4_6CZ>%d#Tzd2>IHMHy@yK26hQDwPX@-axr!HCi$w$zdIG$ekUxj zg1vzEu$LwO5PuOII3x%Y!Bs-U`v}pb+*4h-a<2up z-~DQD7lkEQ)IOL+Pv#y7Z_dOsT-eTv8aXIQDNg-Z@b`Qy0@)~{@%CFQR&n7HsIUkY zQjSaNbjdImltK&o-(9fLU%O_0tOlzSpOCFs(8gN@zBxIP;jw?0kkqf*espa)4iGaH zs3!;C=_wrmp&fcjU8ybXPj39QDF%<}_R>kKQTx8G(|r)NW31*Ch>lzG3EEHAY}^Pp?3akkpBHC0wk zf!_lht_-2oaLaat9wc&5e-zd-x(~2#ugx*IRO8>sCxg^*ZCp-WY(VJzM=l=K{oO*H z9%%XnlsO(s$sv5yhVnC?eA}%~32hUc=*_-_K$$*egy9MLl@=+`P|qgBpi(n5jaN!sbMP% z6*#ts*_5Y6r^-G6V>N7yvWf9a0IFg|_!*k60~o9a4p$JQ#z)#NXuvznMURcz z%|wq~bi}EhtK~P#?M0pIIXuW%IQ#x8|4Mylc|c(%{0A8c@Vipjw)|f}!0I0Y$9c@=V`+Vlf;#bJlsRE4(#b&+ z%#PW|y&s1!$q(7s8l6y#zx9DFainyP9~6}w%Dz#Vh9-IK^Gr@$&Zu8Is;21G9*2or zPVx=BA<4ybfPD}pkN}Tcnh|eW>tj9IT{2h_jeC$Sv(cUKH0qWtSZr9PH*;WBibrk8 zth%8dOAiRI0^`01V0tuxUe5I(Zz1o@`<4wBdhQ`zI|-!>7H-$E@{9jS^`)X-OfE0} z{Up9FzuZ)Da}J&BBBg@Qhitk!`*>+3%`7_Cw(5bw_WgYz{izQYP+BopA#aDbtj>p( zKgXu6OQyEVrR5}DemlKj!fHl*iN#^`f5xh`9hcXNGv$iaM!q<+cFB!}u;@%)VF$B9 zvP|pmKRbF3H1|Bb|DpA^hC^c~VY=DFbBP+sr$Qe}@9J%z3d%y?h>b3K$Q#L7c!+8+ z87z+E=$iYjg4GoKDV79EaF<@C1Mh!AO&L8}%A^)NG>wMFj>G<{HU}ULB#HHa;J*qR zQrQ|V(C>&wfvV{|U-HniIq|_|J3We93PweF3$bsXKl->;l{dmsT80Nl1JpZg>*h~4MTWMgduzT zX&VdP_op|n6mmPN#vxZ39#`;g;+I##>R;p*T(ly1jXCQiLOYKq4;6|XtGvLR9#iwY zyLcA6COk)YMqdvl2J6YdPxYK_V{M#qA8XY8mt%Axe4GhZnvnBtKqD*IbKm$c4p>TH zA7D|>o&0roHcvbIHvDlOlg>kYg$z+lbG?7)FabQfP+Gts@D#bwbuhT9KKgSn=&+Hk z39jRA!`=};!5M6v#?S+Ik*kSoVnD9ohyDe-V~_0B)BX_N^u96oKnCqZBOhOeqp!u< zoE;HIAM~2(W&_^L4y^z-1_z%C?%2x-4m=7PaCzKXqEnYejgePJAI=@j54fE5jO6w` z+AHGI`+T#<1LdHiv;gWvv4r8{^LAXDgi;j4nxn67jeiTY=Li4zefaQrjc$m*(|12% zVu~v#(CV_ws!%0wxR;ohS-jQFSRYiVZxhY0F#2^FsvO|E{!_Nzug<>inCXwipzq`+ zMuU3g?9cjv<0{`7zD=i(V`Jsj6UUei?oU>xXFi`!U`TrXCt4*3_2pPKuQRp26T-DW@!_e8=D z_uc~~ga<{AAiIxhXPtGCLyniaDa}66CW++^SS>VQ8MyKwePtE&*bzDT2O!oO`A&p; zHy{4n-~aE#zC!ceQP}b>Z-<_8I`#IOF1;y=yXFQGtHuA|diEPR7w3~%J%5T=YlEv7 z!hhLWMXV(p-lQ2cxj*1_banAARPD%z!`jhS1}pEPNjUqvlwyL2A84|KM16-J3p` zUfNCt<~DnXq}NC~xl?CuGAY5Zy6S#bd!6RPUjkp&@1a_b?AVS{LynoQ_x`wC64gjP zS=aNcDO;4a6Tqukb81;*3}Ofbo^7 zdf@^~{dYZ+w2l)=M-MynHi{+9P`Gn^qdBns`P6P?eI#%&;Vz0My}kR_K@CCCor|)6 zbfDA3-WiHtDYw7;<#EU(DpsV~@yKXuj3Y))Oh?AG9pv$Ko(9d#LorR{38l3X)h7LG zt(8c`h0C;0GWISSeAr!e>^?y11V#^0t`AsEo5twi2*@|A4`jOQ8j4_jy!dWwG;II} z##;Fmj@=USb$+FWnGgl}z&Iyl0G1q1vkAT`k2<>a4&$=+&&svB_#?t4(>h^iy*8mx>#|>z?xmqw2 zq&)cZRJ!swbyClQ0pnenyQpfD+*(mW%iUY?leD0rYE83GkazBkJzPM1d9LU>1CzMX z0jV{z5}}k*_HijSyI572Qcv^D5r3S7#qIRyVjH#$G327wwbuKzTgvoDI}OQgh~}9{ z+&u*BxVVJjYa~7u(PP#IM}B(rj1ED;Lu7`@CYm;2H;K@yYDhOoa4HKMt7nHTAbv)N zSVRkjtBt7ibK%#%;>dnx!ohb-ytq9Fg7gmqj07LIZpmw&yqhy}8Zu>a)+h_N&bePf z-i-fz`NBRLN0+h- zCZWj-66)_=Q-itQ_z%%kw^&q25T3L(gjJ>FcuQ4 z)+BeN2GeBX<;u*q_ua_T=rYifNYl~W!aull*-!jsS=Y!_2rIXvEL@& zg&9pHuWO3%qY>R_(2|aU|EYB+VtDxz=)0Z4+M>sUF%M0q@8pN~c$N|mF*(ggIp6Z& zxvEA8sa>1JKxHkXm=|t?w)@6lfP;y>7W|~eOR>C%{_Kv-vkp;yvhud%=LYBBfC&^Y zr=NZep~gJer#f9%bz_f$Q&zY0hbEd-fI~I(YVmg9nc1$=)#?x*2ms$LAT(oC-Ri6z z$o(VhQzzkXERjDyuzt+8n^@_Ea_Z#+u|eiRICTw`!-&fZSEV+#Cx-qzuAqXbYD=$s zewq zhP@>`C`dznDfH!0@>^VE__SCQ*J^0chqvRfw>tFVJ7{#UUonG_|2+TNS0n!RqG{e) zqa-@zR{HRvdNJg=60y6i;n!au3XQT-tJw5hK11x%cCO5wugZ0tu^kS5i9O@$33?G1Pz~Sv!RveFhTUSF{^A5xzzQPPL`@bqwdM=7 zBYFIc0+?3X=A5}5+axmF#S?lEdZ40u?4<ZOn4FU3VhKu9AnBW-$I#*q z&#rjd$+qMgNrVtAnq*g8eKNrG@ShYv?Lq^h-xmLNXZQ*7`t0h}+K_P={1*4@>Oa?B z@eB(G7ETN+>uXWlUz0P6g%9JNX~e@RVN_JGcU5oBG=_J?U0=cypTo*Xw#6Gm;RfR| zyPalx;>Bi0$wXJr-Lh#014KdMkbxH9YEQu0|7!L~M;Khx#wAxU3@#lE?DM;sL(mw)7D$!$d28AEvXM+f8aWG!SdTs zG6Ajzi=EYgYP`ah`c@W0^!uTWQGGQ`Y^ULz!5z*RPy>6UN$>J4f#P(zlNfbr47k4$ z*Fh5JFukO-qemOiq9k7@8j=%Z=dvWCbsCQD*Hn!b>7J9zq}jib9xhgK62$bm=|FNKK%2L@7s~FrbRORqBV_^n_~1mn+U4F)K1|;J&L1UrH8TH#PNE!dvfonP{i_<&do7ZnVse5Ks{i6_M@SBWD1{#TgltkCo zJwuMW!Z8L;J$j+BsFx>fbRNUHvWmGDgc2?(>JL*wVtZ_n$f#%)j=L}=nG_}JV6-fo zkNe*Yv(QCVahMyPWON>pmVJ&-GqV`by!1)Nrxkr~Sr_+tKq~raip@tPc8~FhQ#Sq~ z@BUB-=a6p;-}WQEEe^ADn%&0_+R^CPXi05+dEZ7Cf~0fzgTmfQRG}!8piJm0wxVlt zRL9H)4V9wcZ%3o=X&I5o9N<5$fgk^62TeKYrWyQvc?d8&~)9MfgPU zc9vQ`)mXsa!FQKK2rhg> zJrGMJf@}EBG>hioC4#H})>OU+uWTH`am=ed2Zb*_tnsst2Ml(T(umVB7+=~ zA;8cGK(WiOsKP5@F5ilr#RnfEK6}{KlHjqUKT$~PJ(tOODlDMPjV6 zbl_D-jl#C+WSP^e-PX>g0DH85_&zv3Xppi-U<1Xp;p>BJKr)RC<5cO%r=15*xkJFk zo2Qs;Ou!ESWY}b6)pt!3R?m0>cNjh z+tQ&gj#sM@qO$hjA!B*?uN*sRgGrK7M7##P_|9Vy@-9&d_<{EQVju&ETucd`NVTHI zz0;688z@(b=p~lagTH%ou#!Oe2N6|?n8UJ>Xq1BEmm;#DBEsO(XI`@K@C6b1Fq#5{ zwIcsR0H5y(%AROxNHcIN_Zs@6T$ zu!OGd=|UQytLabs%MT>rEeR6X&Mk!b4ybestiR=q^P3hL_8jVDxoRIUh79VJt^+#?f`=F0;m&p;odrNp>|Ko%l+eE36^wqB%mwv+>lG3|) zjjQ6jgRj;$oqdynJ8Lukt5%d^N>@H2e7P}hE*TKg54rpT9#uZ}HsZC$SC~py;hZIR zy;K=$f)gOV&1oC)s?P;?ubcU3G9rzV_qCUc?|u~D6-Zx&OBDUP*axv%WZ((?dn~@K z_}rJA1%GN2u33M&*9atE^t~O8yg@rzRSs-y>gLi(PVxVnD1fmNJYMT z=@oHH03!b9ze9hzqz{{Eg%Q=$;%@UK?%61KV~Qn=eI`qdX8NW{nJUBq7iv{zFeq{5 zAh>dtNDWseY*iMG9FrDGjh=Ez->oy-sgrlpHFrt(Vovq39CW~Kp1RPn96_bwe^1Yi9rLEv?yYP|deItN(W;EBdk&Xl zl}zqGdmcDqVcKhvKVac6k$R!Rah20&v4P9sx1;>_pCuj0!$HSLB;sf)gKS)+Yr2k` z?yV>X>jZ!{XZU~F^&=Kxb{uqCle*k;@K$UGSKVt$ju=m8GS`20eOe1!9OA9k=}@pi z#Lu;q$icwmy-V^*3mcAi7x<7^ZqJK2j!tAYlT)%H!$sWas2S~EJY`CpXs3FSkMcsR z@kN$0yFK-fYM(>i_CCwxNlSPBUG?QyMe9s;)5O)-m#1AF{AT?>qPKw#vJIP-YvW_F zOEr9)!VMj~j!PY-2OAo2%uNjqVS(s6*PnSFj!6?)$#K1Yw!?djBc~GF>wCp7F4bnX z<8Sfyb|kX+MW`K0E^qNH1^{_d4P=Tt5<8*05{ivvob#54g`kG?S<9iqi657591e8v zWPhxbPkhdBGOwH%c55JGnYH}uP&$F!#(ReY{K^SYWi|&{s2y)z*~ABHoyZ;d$DtEDq8L$~+TnYGZbC?GJ|4>|aRlXCZgG?{ z?&})n+}`xH-sMNZA8)c4T;3jauw}I(ozZ%_zI1u#ruY{Kt zDfT9}+9001b#pFp3*Lj({SRADMKIZ(BE2*V5`Twf^~$*ocoI4klDrj5npMW$ zHa!p`m_G{sX1tMZ$vz4ApT!tbI6L_SB}_HpdcNik?|0!U3?ueRv46xHaV5yFi}V-_ z7tdXn8Sqi+mh42LU^$5Xm3`aVmbFg*sNG<}Ww0<()c&%iCgu zk~bX4cDkg;yg*iJZa~avKzv{@7(5n~Os}Qhk~!ubJeKo|pkJwlt!pu344D})WHHod z(Z0_hBq{3XlD;%%@ht|Ktr3*$s;e_9vRq*Lj(~&iO zDJB(h@@N#h>=KI@Itffk4RYgpJ?pPEl`|H6?3zcdf~(1Ci(j$H^#b}miSoDb*tx|5f?Z%MV`z?@Gs2{;>D_m zjv26#d&ZGR_|FqvUvSByr7LowBGs+hYVLaZezWQVROYh{wngM!^G`vOpS9*Vg|osq z$bWmAjdM90eUqyys--(ReRJf)dX(NX&+yt9jZCZ*Y|q8IX+*A%!DYWtPL{nrHb-o@ z{fWZ64X1q`oudh*%i>C84BA{?VVEweZ)PahYc#WL{0;jduNI;++%_i3XHA8zCnX>GyRuZES%*+=d!X#2Ls zT3_|Ou>C*Y{I_%i*E?HPM4MEN$Z+`RYw7o|rjG-up%lW<^1qe97PFNHHW3kr*{hWn z0Wpie?0^2)&KohfX#pV88|+-7#@~H{`tFWGR7$U3Y2RciNeFbAxp+O_9GX`#6hg!K zv$_CQ;l}RSRIQ@7^Z_(nG#y+^bXUyW+r0*u1mg*2V%u_m;IC7|JGeOMv3~vpxig_d zU-Z2z=hg|G^qYSN)+&u@M%+ODg4dE&-fW3pDQ4`C1sf~a zQdaRQg39YJ$+{wMho{J_OuWF>m<4EcJ`8uyfW7v)*1ohN0wMcWr0=vsO4Rs`LP4Xa z{npz6t!y(aIeMU)PwY~54%_2`MNlqsF8t;p8~sG6wSt4^f%u@Msy;eFv)o_tVk0cb$AFh5i#knVxp@=Fg~)(rO#Id45AlanLf+b0dw%MgBnHOshk#K z=uP%X&GBRv-ca`D?7V6D;&NZPDr4oP;r7+AWXYC6!?CD`t<%)qn?lXsGnkcitCFw! zeMY27a4*hlOj9jwj-n<36uB>U4VJ!!UpdZ;c$F_{&&EcymtKD{4{Icpw4zEnf*HWGjrXCF>c@7(ekmKH+HFQ($2 zG2Idc8S@#_c7T3gtfpw1S^V0@vG5jI?YH-e!?J%6$xJh}@YZjxjb5(g=jUE^P$LP4 zu-U-$_ut!STY~w`QR-WwmMIfjqK1;yEGA3QNxb7?Q0r$7il3i78e#d8L7BD4S>M#? zA%7bh3S4mTtl9&uH@U=%w8n|(b{h`Xx5Qex1Y0?<+pVZB7TSZ8bOD+@$Qi0uNslXiP@5XzK4}9%5FtJDKn6{-fKT$Aopk4-^TO-p*pNRE0pTWCXYMBa(UQz zjr#aoDhJ-Xm>becX^d1{uf+u3NhdK~Vwd{2IjruCJiB#1RtTV_ zOf^`1S}-(1@${e;h2L!(#ZA%==i0FZP4R+X-4572B(>_$zI{OLB3kJ*Bs!1a)0%AJ zTAgqSCK%^Os_{hUDNV@k;oxWp7Fc;UnPppP4Ul`S~+@7jEPVEZPPa;fa1G#ZU7dPEyGWv1I{T#+W)t6 zx}ev@D_x?i)l15X`8U`zaZjTJ-tK#V|0i6Lt`xbunMaw}#Be<m%JF={J1^h18=Y#D0b)g2g@AntIi=u<|t6Mr2)!FgGHuy1?j|< z*e!7i*(WH$@7agUrBhK+Fh!Jwl^-#=$YdFZNUWQG6m>4$wguE)boG$LXc*hKLk9-; zJC~O3zGYY5|6KlKiiJh_Ji#P!<K%^j$lu@||{)(Rz)^rYi%F4C2m-vvLDc{VZs zE!u>po26s3B70?eMDQvgFvFjP)nN9j=m;9#-f>)TFVqszR`q}IEOtt#> z=&MAHy~FjVT7)N8jr223} z%Ok`@*ib>gDz1mHx~bqG%y}}^&bU5qjJb#5LGS1vVqe-_{8AxA ziR-q;JJeCHgY3#!ZE3=u2e%>n*d;%^Ilnno%E@}WO*WNLa4l}g$X~dCEv>oa%S-#6 z)5-1wF^dlTC2qIwhAI4u;s+sc5LI_kt(}wbPqOQjKqu4%QkM29>t$IrMo7Upqd=_6 z^VRCrD<{ipr?fk2w@yQl#J$af+~{orVQ-$==GH=m*RGmTJ%!M$w~WDwBGHA419@cu zQ4DTgea>qVK%EiTc{AM&#m`7|4Y@r zuA1J3xsW6jONPOLA21bIXT1);b`QkHT1Gc;+PT8iK-Sv3}kmA-_2oCrE%;LyPlN^`$RD<{4SOa>O*TnsFb)VP1 zhOytc@iyA;_b;G&+SN-r%W7$Lqu9+jo#aD((k|sqOE>C?S8(BWbK{|Yh5_+e3(|f| zYPF}ZGlo_0Rs~hv@+599(L(LbG~o#G=w=+ZIBT+rf7$0SaGHONpL#lCg4FiEF7Oj4 zc5L>(kmv-}H=#kncZ5hqA95Eati^)biuF?;a<}KE3ICb+W9Am{gV}ofcjnR@OO8Ne z4fE}vIZw7n@Q-{L&63HR`c8o1$;i^_`sF%yR*G;Fo)>E+>mSqnX&PRAp=A$1*u$=+qvLdEx-=eMA zuCKKzatRArXpX0T@lB+HIl1s~&Q7k`Se0f!VXu%O#{gDThS*Op%$o-_CuEjrBL{9n zg=n>p0?#zye{Jq2bz(Mp2WK0Cn82wi+1#_*+0D$m6SIrxe&56T<7-I;iguMrG%hwl z%FEwrC(`eM0x!3f=Ke1DT;$XbkonJDPvscCaDwJf;t0uIId~4 zoZmsY;y3b6w0IJ_yd(}UBP<0|!(l_k3l)lxf%i2(<1AGiHuE{?l z8$!XJ=UO5bE^&6sYKv)28w9Tz2L<=0$U;siTQc0>sf&mSL>~6Z%%OHH>)sR852cB! zwT$Fx7XDY?^BCC=G7|H^_G*g8*VC5lGfw4)0qgb~$9Ej+VX;oKNgbV~v2GU?=kY#| zjzKpYs#*K-5j=#FC%+lo2ct_}rJ}%|&i2`>U#+dQRY`u5`297?GrY(BLELQby84Rj z33kKjB%^a;9Q5%7C*B^xikfYgYK!H6ytE7O zt}(K|%t3yw?kLF4I{me0_q~!=pNFOaISOxk`3Z8el4jTy^DN6A0$9#s8x_(ORQ1ey zu-e*V-oa$L`rSR^UxHBRorOfuQ3m2MT|H-t9PkQ!m4$85zXD|0-NTk^g96yPGy&8k zV_vTH@`&jpyNMRPB0yaqBKQUgpyKm%tArks6Xg$zAK7-a^$n<6*^$XD zZ~&rx4WKDGIDJ*Gb_I7j@Glzu-zodttY-wN|1Xq%?WhEeAxIq%#7>Ku~r}MkXw!L4vw97i4^=Qt0c{S z7O#_#SobZBrDdVFk=jhF-bTG{MmA42lRz#&dO&##^QFtNGI(s0sD*FP9y}dyfsg<>W?ks>e;WV)-PJR&b6Ra_`adaq84ru78VgMH z=jzkW&oo>~SDA5LKgL#+#AoT0EjM&4!#9D9W+F{&0@0arv#n?=>4%chdq#ehh|hw% zfCbtSf>kPoMIwCRq$OgN-t@RnwnLqX(rbyB>@TtU(u{u~=IsLfHn&`WrtiY_3+$5t z*M73&iBbcoWx<#c+`dw0(zWd`qvd-A%}E%yp~ET$+lurFw5wc*r6U)`&uX%KZ2s{# zEg=Qe3_N@4`9tauo|151JU4`xvPXcX{QK7y(9hCqAHe-ot(Wq7!^us7oDon|1%_jM z1!Camp*^%u(r+_01hj#YYs*;ad13SPl)RaSUR+TpMR!#c2@w!k2zqGMexQG3+q;w>`sIdWrZ_8| zkB6yAoLZ<18@#lync>ODUFLMog(Jg`nJ6%J*)Y*ZPqSq&^d$mhVCO6fP;g3RJIVSz^u;caruBNt%yQSJcf{(TR;4I&hK}V4nV!!HQ z+Lac1if8%y5Oxz>X|RLHV>-IcW1yq&NAjrT};ey_K_TSCXMt3 zla^w>F=ba2JXK1pD>l?!p(b5)lW!#p#JbwLJZ_g{@7enyFKH0qC?5X^(EjoKA%UJS zJxE2iHFQp|M|kIXpwZdB<1TJb&)0a0OTMsNJJN}jWB*<%vC=8!zPC@F^MYLu=^a?- zI+`nCE%u^=dLaFUdva(Xb5CxFfHo|h)r|nnC3=tX1O7Cm#9LB~WU-|Q4?ni@Ph(5x zkY4`**LB}SqhRvGR391i(lW)b#O(l^c8k-gk-l0ir7%FFXX?9eEwj^L+9wZa4^JbMh;?< zv_dPF1r^amN3T<|!vRb8QW>``R_Yn=;By_K8mfr7T^I^A+ah&PFAaqJ%x00e!GIh%NSj z_NV}opO6)&31%-2s9AI$ho4taOrp-z?V9Q+EI(;`<=G zvZ!Dh`8|d#n)9~5-B4n7V5PZrQk_{wdiRrEaATvoXB6|MQu>duwD;MG|qhJ4l zv>mSAHeTH;`|0=gN3FsaIVRD1yqPYuW@tw{HR!5-p05Joa~`LA^7P!Mc?;ccay7?u z3y*p(;*DgkA$Y+o!9y3@`GfHw8%mt^=7nSGivwL`=p1kqgT}}C21X(Ncw$!=&ii-2^mvDwL$PR>*jX%Pl8W_u{FzmUK(EU4226eZNmcS_cO}rX7?@I@XaGP9bAKG`Y_6fRJPm^7^KMAz( z-3Lyq-Faj2e+RNSkz$yC&W2 zZy})xB3*h7NSEF_p-G3(d+$9!AORA><$1pM&fNLU@6Nq{-Tbrp%;#kH%+BskX3sgV zH*5UaeYO_Zoz;z?#cV?hMyR^Q4LK}q5u#Wg%zc(YTx#(0XVgQKYW?Z0SVQGtPtWnd73@Knizhd}4NK=eNW7y<%60&wYX}@15OcF)?xP zxN80>?IZa5Uog0i@U8iY92uMEK-a3V-oastz`rm?pwnm9*lMByMhW5{mI&|f9*#R{ zXywLf$*q>1F1^Bsl5BBO?PHkyrU{9ik0Lwb4OR&c{hluFafkrg#M&zFRsv!knU0g8d>KfBoQ&OmMo^y%f%5FpF}>XrerY+ZiQhUN)$)Ps{7yew=T-Q9 zPR55>HXswk!ET{io!7a7!}d!`N$_tewyCsKVVfQf{WAKmW;9ELNmUw*H1Z5pDYBnA z0`5=bIXXD8(k~voT{#?BY#4@uBLk=V+pvCc!^#0umU(;aaY@FV6xj-9dc*XrP!Wj@ zFlDATy?V(#@YzVaH?%7vdyT&<&DSO>$I<)knU;SiABprkH&x~c7h_Uu#Ww#3!V9=7 zt!H;!(1+Tfatzp@BF}4&%AX18rcjX}X6YV0(mwO;UN#}-*}e_bMKk=Zl|(%&xTp;j zlKumdE&we&hDjUy|8CJuZ#@zn$jr?*y@%y6I34WL8 z9=?kygEl=hsAbwW@LNGH|jUygX($Z<7dRP5K zBaokZrI+6S{@ynS-mj@xPCfP0X`inZua4I}9Ga07FqyXU_bP8HT^3BPQ*cXkl}}7N zeCukiLsR_gnz^)YP|Pk7mAl=#N@>S+xLY@qN6)w4>zAEOoc{9nfZb8TJ<*`air$mg zg}H-k=1Vl`$+WP#VWv>~x-PoZrcX<9-Ice02uaQH#)>83avVt-kBKoBVYJZhno0_5JxHEzqXt zZ+#R>n}QxC!L~t8M)sd&!y8&dZwD1JY&^}Wp0Vr!nJLvH6B4!gRwlhD>W9YS$JPndI0MV{u5TCBC>{+3bWrI91 z5`m%vQJ~_Ad*8wg{w?#f^BTh*wX)snSlzw8tqaTnv-V-^ZVriV`5H%INuXP25EbUq zdiZQschesk&TPsIWWj{?P1R%~ZQmk0I;hH?>dElBd$tZz$@;DsTfp8ola$p^lr4(T`On`q}N#$#5b9-O#}R$6l6}+o3R5f zdT&!*{%$K`@*|ZF&p3HyU7kSkHzz1aJ%0XqCi2hah~sSvdCB8JgcUmA{$^#E|%YD+%y!v3iveh4Yd!s*4rL1X#`zA z6AM_)ZXk6=CJB}J4J9D|+!BvAwfZMbSd{qGE;8Nie2KX$uNs1zRuuB(6o0AYc1qi3z6y%cIx*Nz$;tE}yav5y&2geh zBVHS#3W7_gVmkf#0hEia&F~>mFwJh~(s=?@uAqm@-sn`u=`G^tM$$j{&q*mxj)jsS zx090^hT}1tx7-!ra5|O5<79hIsw*GOsQh0%kcM8@TYRCUL+a8hRW36Ma>K0cwvm82 zI~$)9uB#2aJ9yO&aR=qx1=w9}lXn_rHCaqlnYN*YoG~ob8ilo*k6Ju^xpE_^3--su zV#xnjX*a3BoDY+qad4O;9^T`U?mu|0-wE!UyE|ZPr(Fo|GlkjsiihrTqt==xGz235 zl$GD)pLISHQOKbC-y!QGHDO4<6X&`|6LYag-~8mDABq-Vb4wDw6_}djd&%+qhvJ(kvCjCY(N9sT??qpg zwX*FzmZwVKBn-8lH+x?qt+e44T_21p#%`j{4ykJ;mt@!mE@#?z-iI0);itUN5n6&n zQ0V8qJh}2kDGbOZ_+4XRlIbW{*p|ZQaNkDs`hJ||{}ZzQ)_Fm>0V{^(cq*aIm~-jT z)k9;b93|ypbJ;6Qid*)wT(OSvJ>k~}P9oY~C@|E9P&Gj2gO}gxvSslU+rO*|0hrsU z0Awr{3#529MH>2uKFxEj&$Ew5pNKZ{B}Y&D2cwbC-=67x(2R6B+SH=C#`PCrNDJQ= zkU-+K$S_(rW_q2P)X;t1nB?u}m-9;hC|~!^T<$S(xc{@Jk2NYKvY#U>VP6^6zvtZu zDu?cj38y;u1y(%ImxQu@TZQ10WFM>4ZKuTK6%JvhRuPlGS?Fk%54+_T*&fZwkaR^3T6&!0z+b4St zXFC#UvbV_T99CP{0IriWr=r2{Z7p{J%O=(hfccx(2j_cFiw#~ax)@D&v5+WfVRHI~ z(pnm>UjiKQh3Ki}e)CG?0tQgGcH?z;s`{c%SXH26cv*xmLG2g8fs_y|>qv$P4CwCX;Dv6#~caQ!*M9W0AXcAU&^i%Uv5Ao}~HNAXQygJLPK z;@u}k+aDi|e)JZM;81=lm+(kWJBuYK5SVV#4r_fh{UGC+@RS1A8`{vow+@dW?ADs{ z_=^NNb`K#0(wUcioNb-Q;)(tY&m6v`eCpfws3a(6qkHae^+~%3_fc4R@gOYX74PxG z2-gQ5-vE$1zHd6Q#{;WijOWl9F;XSG0Ie)6*IntIgQpo{PE;=gs zo;@|1ulb$Nd^FXF9TcmX-aT5@r2RBYFJs(gN3p3dmHnvi3MBzw&&ss!A#eF%e5ESs zMn3h=4~tu~Kd0v+(lsH>^17<`RF)zFOS>8}^-1#Dr&E=If0gw1o4mgV1C!C$5Z_6Y zx)lN3QI{*0pxs9L*z!Hfa2u#y9}DY3l)E{t-jT z`W#gLDtk8lPxE|m=)WU5njau)fqw0+Z-c;qhU()|@yd>Ze||Siw5i>3>!P8Zj2soB zjkHg`)>QJ|#ws>euu7>lsz7dhE?d!l3vWzG|r6J89U~{SUE|{bb%umU51fiiN3?qrm+FIj}n!>b2SQ z=pszpt^V^feD!JIK0YFBwXNj{o8ZC141IHyxEr9bE|LgX0?0G< zeI~(UJ6(y|(^tuf`AwIZ?6DnP@l<^7)TBJ`6Mk3`YB>Vy*OYL2t(2*#a*h)o{ z&`!%cmv``SF>m!X48v{UOgTT!cHXKcKP66$9o44e;-v?6A$5ZB#N60HUd7&4IRc{D~jnppza0U3PO+&PdkkV+G zxfqqoO|#*`ETeSyu-?s@zc_>Dg}%h?>-4dikd0M7)Cu#6`UgVEgP?4j3R7t~+cR;pT!7I(kHq^q?kafc>E0(g zVMI(r$FBDv2G4h!_~;kEJm=45Z&JR`UoR6t((^$YPa;B0srVFbrj;GPCeBUtMYLk_ z#?s7CsnIWBi!z?Ifu#-Rfg~e>xjBEw`@%jPj+GT}3*0AQtH{g+^x*1c_wM|Werf%U z=+r|0>XCogqn)m>q;05SuP46hn+`Bx+;bCcDrWh!d^(`f7C}YNh|Kr=DekQwRS^!+ z#$&quB1l;Zt<{i++x;mMl(NLKn)_{%>TNuGeneIeW{u2RH}q%5Qf-4lncUxRI`(G+ zy{?KCna8&T(c2*)TLS0=i%8*R+Jw_jj0$kJkO5=aT>16n&MBGMbETl zaajQ89;&X}7cyox91iaG?hiyA`aA#&1y)JyliSdd&2c+kF5*(9EZYrTyPcBj_uK&R z6=(P|>@LF4204Md%^%J`;K7OcZ3~EGYdUSTRITY=-KepoI9f}uKg zkzw5xD{E(zWmbC^08>y7d+lY(Fu0thfViT8sE+XPu-1y}kRjh+1V_)<9&Gzi;elg- zd7KG_<~vK$?q(3jwoIpbn$0hT#ZDcI9It{W&o3KcSqC|!3wj(tw8ZrWsQC7D?nN(Q z062D7VQWJQ3=#yZjues=VXhlx_kc9NE=>5JH)*xad#kNIIzkruJhULZMSB-PGs3=& zb{j5CfEmcgNql}HC4t?N^3Ks=4X??~Lx4jBM_JLXpisXx!$e z?tYqxpP2Z@MENhmwS~0#l2T^>j`NXNm@5h7{rxnm7rq|zVoYVHqm|xyan8hSqDUg+ z%kAqUZkUdmwVO^5^DixDqPj#;bDS*0A#d*8f}@h&b0hm(kU!I!-HR*MKGbD#PDVWd z;vGe=u{M%F0reYXT;uTBaf@e^7P)U`dwIS(xaqha+MPyHza81GiH8-^i?Q6O4BxBs zQBkOFOMVrDbMWd{_V5To!-37Gh9xesM?ZrtUz2g8-ErDJgrzO`W=Ix=)g|%)T|1<& z;uOQ}+Cn0fF#!u@divTcJ# znxyPa^%*@kUw#!noxM`tbzAz~eIN`fIqTezDoTehTF@06OUAUVz3GTvJG`@7%KmsJ z?H7}`!XMl1)?JLBR1;(#2yTnP=}O07!Oua^DI&tG5j=go;#`^1{6mDHsdCv9CIPNm z3sd&evEEmf{tt{~-#*CN)@7%3!?AaJ)LYXuZ+6-v@_hZC>uLJ*OM0TmYl~3+Ies2q zb?KHuc6u>|9mF*OiLzi;SsT~CvHPXO3&#G^O@lEikD#e97iFwwg2Kf2xOy@TRlMHy zxPFZ8uWKhemJ3)jAnHY>*Xk)hqI3)V^s|BYq-Z^qYu2${h)6Hmzmdx#wtsm%C&Y*J zODUu^(MPn3Q0%@^Qlov}@zBDR;)qA+HhNchZv;#glZmR4PK^)W!BxXn=8PZJoMtR zT?Mv63NpnQG==Ah&bb}W?*&{8|K=X$+}{{}>gn)AHumAm7G%lSW_=P0KV1b=H#0S4 zl)vB8RRjOcEU9p+nGzU^#i|0dy0Rp4By`7NKzSvQ1~8t*?5mGJP9`w>CJ3m|2&7$W z#JS84du)$GGU9wZg{c5x!4=oDg3wDvAuu-Y8bNJ~1vc!!P-%CLwpdJ^ElA7;>eznw z0dY8#X1bbxeW{ID^-S8mx&KM~EXG+G0sZR(!t#&6l6S6$T6%i?2};_tV6exMs7v7d zEJDZh?&d=3ZuS7J^5yZ7IZf3@;|r`lM+kDjq|cu*y_Wor=@^eEq6K&OOZRg&#hu!A z;ZZ6+^G%;EpPML~-=;aE>vz_f0RUEBs_HV`Wh~s3zEW>o>7lWZ|BxV`T}OZbFaaA0)SG4 zTj^grcIt4jQFQ_Sq~5`NFTlBcGT>jh%}w@>kuVs^(OPgjGd+fWqYL1%{DLa@YxlbD z!RMeQgLa9b?*)7FQhns6fVvZ&y@6nn>p|)KnCnf}*B|)4w810zqG{x&pI}rPyS&p? zpQHTLinZXoWzlO!gOeF1rI{7ZBe2;*+cXlBs8+(4v6Q=!mtu|{nn}sF3aallN!c}- zAghzV#$Fz;eOYM&LV>&Ik$9AWh=_T(h9AF?FV|6IXR`aI`M1zl*+Q4C+G42D{qcVx zy4=yDY&JGSs7bnF*5eez64a!6YM}5^B65EtN1+WJKTsG}vCrxURCWEL$^WH&F@hzy z>YWX1DCf&B(grQ@1wsI~FZJ<8obw_jD2X!l!rHid`O5UgpNPU12Wn(lpnqAD|Ko-C zH4?Ly3--!>9B{`L)1}27*LO!ksq=^L%Wb&J98F+IVsp3tW|nZZs!>mnNr|^oA|iq~ zGvGf?;bu+Bg`gJq2 zLDo!dp6IP|8(Y57TA$1ON|(#G;!dH|cULKq&AwihZRzk(rUd48D*S3Nhm@~Xrh#I58Pa?8^ zH^r#2bGR}1BeE*O+b?q%SQCy*yll=OvpHJq>u!>}qOjfi09erhSK4K26D?7Fr*!H@ z3*|Y>!C@gg4W+ml4xInCJsF9KzJ?z-5RV_jUFo!R_5&X*spbKVB7qVQ9 z+e^^Gd!Jvn<3%n_VqKT5Y0?`vBc3|XI)%vcc&V8=(op8yV>6hFM) zr{kI4Z1Y}~5o^pf#%o@^HRp@CfQf*%?v|8jX>V`O*k1d4A+6Oc0 zI;6~^=Z6cq93F16RoSSVySlgKS%|ioMlZrP_Y~8O0=!JeJy&nqtF1Ee^?kF;BG3cj zs94Z#Pov9E;cuX_fGS?cM4NZI_l_Kh@~{aU&zJ)xwZ}7VprqJr++Q zR7_)oc__5>moOD_F$_H^;{NTT64TAsrcGfJxgsl8EA}5-d;Lu7|4;Tj+T@fFZ{indR;0s#v7)Eyokw)hWZC}< zd;UoHKkWIY|1EpI?|)^_`~Bb8^RD`V^qt z%fg384|2^afmR9GQo^LF4i!qhGoJFvws4&L7~70%YD#oTJ*~SJ6s@8SP@UJ_D43rw z=Bb*qdpY<_Au9|f78Vxf9n{C8$k*OXtmsH){qy~i2B93_o4ZZj+i26MpiXPy3^Mix zz~j^DH;o$tV_4gTGGnr{5;K02?$~%5GwA3`eg_6<*n=?eN5qj}Vqv&2 zh);R02DvLF+7P9}{D+A0E_KEOjg$x;pxqT}U)g+Y;r>eqlG6 zefHH|&Sea17?qCd%k7;0K0zjotHUf>aLmnCK+YDGJO#ONQKinkd9XQiKzZCSYKs^` z%2Bi5K8xHKS>vZ!RWAru!Nl*^ob0fFnz=$xkq0e)mr0Hwz0iR zH>ucds(QE5;o+?kOu*P>=mAGg-{D310vG?)#W7hNG!%ZqYI%azJNkPQ>ixxT`(?xK z{e$!tu-O@?H6DlX}$3pjvoLcVY ztFQy+JkASmx?sJe_dPfr1kxr~yrf@UVs87=BL`mSl{Km$qMR=8sEr_`oaVo?2qSU1 zBq1wmUd$TXR|5Y%agTON_to>CDob^4$qy#DH2o!WD?~HCm`rkKL5=-$BkW!GjkGQ! z)iW|^Ky9`n9sL(HtObi{*86$u?siD&Di6*OxjE1P94atOx4a#uXZ8T7 zS|2poz-ZAwA8>AmpH(xR=lP(0)lnmZ8$zJ{2_$HjuNv(g| z)>#7jc4F_7AFqYxCnFSeiY#^gLb+^f5hNt6$md8zJQPJeW#%&pS)(Z5+w=$+6u%F3 zS3EfiD4GnHAyT9mgmnI`al8%)%I|pauCs$-In)2RqJGxHZV@;PP=}%RER)qRGi7Z(%?}yWtaxJrDHiw3=0P%j+T7_!3sG=e>ACsw&Z7 zHvK1#TnFmpC~4+Qt7y=&)9A^!PmuhvyqFG3A=@9fxAzj$a?>ljlx0T8DPi9!_N?fX zk$QOq9#MMi*P2rRY2@R@tZA@!njJI8D`2|%QAA__2w3Z`y+Vr*x`4dM5IA+F<|%VFSLVOvf*P(?*FzQ7-Nyed(yefU zX0INfa!fZ5c|Ri+d89{JK`0WXzh1+qWw}N)iTj!1hy7VarfFg+Ud$d?p9otTVyy-X ztjM!04#7vk+q2fEFXFITKsiOcnG(ChinO*gQTRh@c}n80e(888o~!8kf2_o0+$o zOuFmXLOEcR+xIHdewe0OerJT{w41N7zc1=IW)Z$AysVn|wD%Ho;z83H=bd!D{Au$~ z-$P%5qtngGZmy%sE*kwgS)DoayC+BTzL78KCD!zha7ZMI7$nYRkFs}r$vzE++>q9X zF?y4FX8&L`h+?dulQ{RO>K6YvC+JDT^HoVQn$g_6&+nl`-cyMcHw&U-mvM_ceOjxz z@S+NPR*l<@5z6%$7-1+dWKaPPL9dbL@ zEg-MGSJkNVn)*8B3~#vSt#yZ+MJUJ3=gr`RtSk${*C{>@Aocq+g1c+kJJSS2Y^Q3* z*H8eDwPpdy3rmYo#vioS<~sp!%HeDxzV0k~fj8O$0fo}V0kj}e>&73npMRv{kqz<& zV_8$eFRtVjh69xN@HmGPzTc7wn7p>$aj?E!>BX zRe({(m0qCBEL1Y+9!$RzuuC~CKc5oEKODQ;8~It0PH**9uKei9+^qdCTvOMduP7M9 zy%VBF#Eigki(X@qF*m*T9dGnDC+Q-X7#)Xc{?X8k?rOTflz%0>J;u$hQtlq~UaWGc zt=rWpdFZ`QiLmJ*3c7+rcPIQuq{f^TNz@B40|zs~pRfG7AfDtlW8%bdeq{&B(Pu(ChJuJ&Wv+*7JvM$qOQ4Sqeo!a0R2l3C_lAN~X`iH@U+i z`D}l9;0alGKK47htSUk{J6{(keD4o?y8NE3-$u8(9duo8`kXce8S$+Q&xV@rg#ub! zO*n~CVcZUGU2Y;yEp%F9i*}Wn-2MJp&oObJ zX1`4WSpV1NQp5By`{c-OBVXGz$ey*Y_=vN1iL>04Ea9lNAP~GyZk_97RI&B4r7a?* z*SogJW^U||ZJ%L7c4pm#sB(khLGnZXqSIZLEh)jUJ+b!74>ZgR^|L{}h4mskTEZww zoZR1h?5V?++rGn}(646dLzkb2-ELNDxE@i`qr1$QZTV5HVO2b&NJEHj-3*YV4kGJj zbo8k*@+mf$G5dlvZ%8)B=!}(RiF@~lYlVJ$R)f5?+~%BNb)B%t)KR{o`#uBZ~jQ=J(oH1I=ul!fj$;{^kJODi4H7Cr3P($XLcO9;TU6m}aB@Viy$~o_nlaKElrf_- zh}QK(T#h+7X+Z_V$@X#bxAq7q|G4izTnQZ2^Bu{i6DUd`#}&^oiz~&=)kt~b77S1sgm^U zAQPt_8&3slMQ7hOs`H|{Y-cTx$q43Sb^flYp;@B4I%^8>+2YQpdVF)We<$sP*H9u; z-E_r-=QLXjWlH4kDRz38+o-M4u&8qDUG?+Q7aSdysrLTW=OEdHQ5st*lNg~K3MG}I zVS*fANVY2K*0nuUvwhL-7Ii`*e4cyD*`_Pa{RI*h%VK4Z6C&je63n#5kHd1^IJ(ArM_yvWZu6r+|G8ul%4+pe%Cos@bS@-zS1tmJ&+HQ z!^r?j8cU}n-Kz{UpNn3{76VItAzu_VLQ=CH_69ha#Oyhr#f~}=KDMGiuqxFw|8hne zr!`6$1`B^peEHE2n=wMYVDqhEs*#m_I4??C|`WK5RT87BGEa1<~kvsPOus4b1yM{N4VsT9w%7*HV)jWuH zu)ezYOLiAFqRmVQ&foTtEla(21ZCcKw*JX+GU98~5|2oGexoXA=2}E_bz%~zB6%S5 zM%<_m?>SIKGxaVUuq%64`}=jaN2vEMgvla6H8SC*ER8$+jHhpm+ol(4^oGb&%v3Q) zk8{_vNn1sZr@|CnxXFK4yFr7dUt&0~6$^1m8D{y*QznMbbetPhxt2S4F}#t&Zcirz zL%n)O>-Kvf@~uYS(lBjEG$p`oA!*rYt@7>-GQ3mz?N?KVZ9QH77f8&Y%MQ=4-WP_{ z1Ro7XFls(xv~Y}Ci)&W0U)c5ni1*OT0&*bAxLC1{xi6VhIwixQ8^;ME8#sE%sIt}h z^KByTiW*l<;4L$-b` zepxchEMsuixV;k7011hE7urCz_lAv$Gg(}c@a`fC+~ z9)8>+U^}E)>GTG$>HTvd+TJ|ry{>X$^Ue6+k}+P@UVsPL9G&4oiS;VoBz*LL@LD?m zRlVa8FnaaS%`%*^KcJfasYEQFZz(*L@#c}4^)5XcGp6x^UjnR0_VE}qR*w)^ta@d_ zRl7OuK(GCV{we2dlcWTABHr<1!6u_Yn9A4rgkLe!n8!cTR4!VLnx5TgjjFFxl$XB4L#&p^oy}5=J6-f zl065Sm^ycPOLzItQ%?f-KMT#eK8p+cI!SCF^G|eUiCsQ6j2}adYZjS*A^ak5zUv*{HAeW&G07)Sw{${6m|$S@BghxSc5d#A0s{SrQf%CGrUm%O2f8 z5qq28o4&QFc7FD}F9xM0-L*>xx9M!4I|aD3QXw#Pr(BK6kqzttE8y`H&gY-#R<+-S zL?4c^K4?N7ZPnlHHk83CUjtHn+M>K*hd{hPRB1q}U)`$eNv6`oBLm_ZvabTheD%Ev z{5+YSHDX>5*yARAEk@-81dDf=Gq!3HtyTmxPIZzU%KQ)?12LXwllka}=@oS^Rs=Il z$&wxZB=(R;dvxf&dGIM>!{IOL8R*$-SVx-;*^Q1A9x@B}HSF|154uv_$Sm{MuMQ?#dsY4RVnJ|! zKIgutXQ`}gZ^O?&t|bD9l8iB2Jn}Am;j4wtz&|jc{U22;)EV|vd z;7<4?il|e5@g&EIWZdz34C*IwbbQWpX^$v403a3{ZVUF&TP72z-9_E<2GppzC;8FI z*%8y?vYg95?~J}`pyU)>%5f+$ipVw-m0+ta&9tj!#K*KN_2xJKXI;X0egj>?-~1J& zk$u}1698w_Mm1I%um?x+gTR!gVSFg z-uWIBEo82mN}o$v-<8M>C}qj10~4To-a0|}dc-^(gAAJD?5Z9~TT)MxE?ZI&i>%%2 z2NocMKXvu`O}<_I&Jh*nE6)waE2R3L*S7uKztH`bX{ToRu`U12Te&c+HyrU{R{R_Y zvZ2<}$gNc}>GN~vm{R9m%-W)?J=gu06h@GQQ7~rF=ZEA4PXFS|p~VN; zzmbSJki4tUH)0E@wG2vZ_*b*gMP~KB?uWjkxfTBt14nZm{!Xv+fx*QtlJfyg+5*`e zu4+~3rsX8<*0(Doi|_v~1Rd4O|ESMHUmGrK=Kc3?h?;*Hi%P|tw!w>oe7)Z$tZq~+ zsz9HQ&SUi^KMgf2E^F@vgSzt6>-`9~Vf{y`c_!6wBe9@@a;;v-FB)QeQbPNs`G}Vyr3I5sxZFyA^BlNVTBEk;_~V_ ziW8#+yr*i>8$0xRMSR&UIR1sQy7Au?;<;^i6X;$1h9VuFaaJ7jAkW($^OXgEGsWJt-VtOI-9l^uGA(^DFk z@A-{iq20%H>n}K&_JBD*ux+-HUnS`=d55!y&R!M2z1)K#)zWig^QxC?7mD*&D6hrS z(#5}vR(jpG*>2>*r{A<8?M$PJ_bQA@Z8m&4xg~SV!UgmhgG=Ixu(~8hH-dd3!_DC= zxqY32dqn*23%b{{+^Ut2W@(?#ytssPl#X(%o>J$-zL6Aj3JQB<>HB&=JrB#1M`|S)T3bU?8s>C#y;-GF0FC(3*^$!8TJNbtS6%IoAna& ziL&CrX0axsB?)`$696kuw=o@^;lcneci#E$UMJUR{4KV*L`>h5q6e1j9UEqAFNIsB z?@WKS7(G8}TVCcc46X++b~DUD52wZ67~41NYW%oxj4-)_i=EUFLqBZsT)l_2hs>75 zt}KVyco>OX0a(O!^|HjdW_j2*s7olW=6SKYc$b95!~s%1k?I3N>J%;ey204cUd zM3|^MWhO>x+?CEBlt|~_Hnf}>6hCn?o^-tR^;=_3pTYz4&h=1c82SI$QRD4&=_Wt5 zoP3D!o|rQOKP5`9u0Gj0^WgiT8E=n-@Kl04Swg$P#n;wq>5??6OUoidreDXW0i*4x-QU~LpGS9fPG9Q?dyNMV&A^&uSf+w@SI=Z(^sShUgkxlr%L7%0pq1U7PQS4x>SynRlEu|aE3u?-L&)kG$!1JzAL`(3 z=3PEj9$G~;LpekdJ4C)KY_nTI+W_!Odw&7;)TY0Sn9|*R&~fk$R$(J1 zlOUAi^a4`%V>Hkx?r<)F=p+9+j#o<^*q-}_!|j@0ioN1Ay_GD}&DU3Gsh?07(cTN} z&1e0KP&QRND`24lr~!(b8bHx7Ze0lmN&W`lUlAC2C4BaAR?K;X;UJrpOUgxHj~To#68%d*9aFsD(_5 z@^7^Rf14H9TDx0?ym5-;Cj%q3X14ElO$1_2Z36aaI!Ymy9oZ6*QP!8xEbJ>fcE>VM*NLxNeK^5_(q&p=pv1ZY{EzHUA%w0hICero8Av z6aTf30oZkEjl%G*$hg`1SBtUDykHJni*tEM*2l70k*Y!e_lCZ;Y&EQ`rN%!?@}3bt z$4AV>9OllX$&*&p^brhs6On)QSp;F2X1EIc)OO%^SVL{lN-*hnO|$p#O+2ub*l?Wx zqwDEBUosbv+z@gt(e~W$j$lmv%w)dLW~L4{>%^ zV*p8;8gQY7b(q_KFwzQ`IDBwV7X-)vuKo$QaJZ7Ax{Ch~KA!z207npev2x6ar67z| zqD>mc{zBU?ZJfFtA|z_452c$$4$*A}u^WmTybl=o6ShvAW_BRQjW7Ct+FaGvky)K-cemel0Q>+ zQ;b3eZv5nOuq}h&C+l7OoDm#SM2Ceft__^m^*KpFk6L-|J7Gd^1Fxa0YQmz#0bDIh}#<5t(Gw*hJ8E+eY4FPMZ;by#e9wG=VmbDbOgZrThHZ`}|++N`G~MNQR;<1JPqO-v$G5^RF5|WK)8HO8y z9&=d=b3KWN_4-!_{SPXBa#OlkP`%rK;+GH05zUDO!3iSk2fCH`#Nz)P(?`=iKw5cz zLmI?@I?F)!-@9DACVldsjt5+rElj%nnQ9uzIX&91l^V%wOKB2$qqMF;7zL^;y#H?G zFu?Ck7_y}!KhdIw7(CVm;k}B-3|y(WRjS?YbC@}NtFq7a$N>8sCPDZgNIX(<&Vp*rjgOnmuP{vNw*~CH z&ikC^=mUx0o=;`iyGnLOBm+{N%nv7Zskwh^W~3_YzQ^iH_WK^IANX;%|1*bQRIC`G-vQR(G7XCa1k zFeTCdvTLtr4mYqcymxr$+wl|s2aM;jKkkeE|7*nhUn8S0yN~AQS}H4v;w7_OJPEaa zzW8<2Xoqf{A8b5;mCXU1_auX=M*CjU@O7>a5z2$i#%Di%(DQPpNqxGq0#x7 zoDJ;6X6aK%H!~e{mQP|J&|uB`}Iq_DB7e&Ix%b*!eT+QV6+k+8%NzSKGO0yUDN+1QY27!T zl`BUf-On^xet)q|;ml%_%FU8I(Rb=GcR0Tv-F>i!#{n^_tf`r{&ypdw7iCL@JJ}&h zEGCBVm9lP<1~T}}y2f`#laFm=JUPR&>v0pW5eyAFNK^T^`n!$$Fdo&TLnEFI2?r=A zl>5z4MZ}5i7KUf^&NT>|EC@Xrz58RC$&hGD9p{s=GrJvj?E!sDsCHPnfZQBJB9aa< z%c;joZ(QpkHMi=c$WQkiQKUuxkRu@GkA(w35aqBKBNczF=TiQ}Rm?Qw*vq$`S=Qt$ zdj8sDd~=sB=g26x5o46gz6dIsLdrSk)!g3O1l2R+E+APc^y`^@mymJ_iyG4L$Lt&q zfGr1r4LURXSm}c4)z@QL?ds9!np=G*v=7V@?L$@1?Dk(T#*h)>;(a7X4+(mPk(+%B zpr!iTet~%ql?^@1Js92rI$3i|^Xus%Y_u+d39$Ik>e_T;5W}Of0WAu;3)lqofeQz~ zSvvsO1|a3!G%2|B_nlc;BHWN#bjrt~y&G%zMnc!Jo_Q_6u%6ldzax$yuP=D1Kg_XfziGb-Zhxw=2^ubl>*t&WAKNrBp*42_EX z;(&?Vu(ddkNBA@C3PaYHj9W?EgdsK8>Z3cKZmjbh+m+3~Q^UKWtFBX`y#^emGZ9w1 zg+6~r`UV}Of4ITsfulPTvgzapKuXQxjMR}rOJgQ01fT6ZaL>m<`m-H^kNR-Kp*_C# z`o)AWb4Y*n_1LB`bG3u?wS%zfKU$^XZ66omd%uA4T|GNBh>@B;nCRDeS|yilTBTJ7 zgb$T4^Z&Rrwlisnt{o{HaHigM%^T_CN{^9@7*TrXAbsK>ZG*_n9wEBlpF6K>9Hg@y z+V9t&wj%;}XeXj}M5%poC*pKL+|hONZk-O0U^2;Emne>Q_N?nrg1iz9OO! z{<7k|{|94l9TZ2{t^4Ax3GRUaAvgqw0Rq7-kRZVsTnBdx?(P;KxH|+H++l({gF6iF za>%#OsdMk$b*uItQ!`clu6|b6RCV{eYOUYXw@CcW6xsl&_%wbFU2CR|!StkwiI`%~ z^0^DxPidn|;I|yAsEgFJpm2872NMWJdsuI<=Z1l?j&Da0b@w{}}h1_FD1zD;r!cEGadVDekZ8RsX_~{!cg(PfCd|E8Av_BPn#3>-?X- z@2mcQG2~zMDDya5QSd3&iy7|kyGIRck*q4Bf=3Q(cw=VIz+zmM*}`= z?BW9jErH)wk~sU>Iwtz~p8d|ERChV!)T!Qfi~wtMdTO;o?Y0oe-)=X4m~E-<2m&R$I0flarDZFJSyq-a>!&H6OJ5O&gn5;0rhdd4m$WR@H&qnbz@3n zya^1?5TS3$ zKP_P;Et!f5E{!gjG6FN0yx!SlylWAXz@fCt$j!20$g#{A!dSu*_;(ZthLLC!&r(G`cJe; z27VTCpr*UHSUm9-+7i}$qt>fDOKJ6(U)@-yjSE*}TDOKnf7JU~Qob;oLR_fWBm5H9 ziBW}7PBX0d(g8F){ z-=O3j_^@(e8jj7n5PK;M{!Qf`Qpl|}u37K;==xD2C^=jDt=8^@*l5a@eWp8dW=+w0 zB|E}7Q$Iz5+;&S%lnwas9L`|ppm#7C^*?cQSMTT7;^*UqRKCC zB+inVn+W-}CmA|unVE|){_0=KfSqFkTU;OA{;z!L@5ER#Yk>Cs82lI6!Q52{W~2Xd zFb1J0qH!LH;r=iipa|pE>m+q28<#=;FOYmfw^sby-fmJAe!5|RCxO|oSM`lobt2Xw zkDE%$aUJ2%o(0);mN3*B5Q^)e8E%DI&wHx(F{l6rsx6umxkzy$C>rh11RFb=(|-&S zj5o+dyid~p?q<8Y>*1wtA#?6#TP##X+64x+(QMK`Uh^A?4Ggt#;O~QI^2y{ju5yKl z`}+=a)Z04d;3+)rBe_?_E!un%`|+8v)Hg@RF}VP2R9k)!zdo~jUDBMd2OHvNT#a| zn_R@G8_h?*Uo9mNYg!^%(bs7Y#D1Cxq|_j?d8#VmW!2f*v@>sVrM!KWv#=)(NFSL7 z3#6RoH%Ah`=0x(E6J3(dj*-}_7EVfyFiN174oae~6x9|NsMBO(s+ncdg>+$;%atwi z-*s`ZuXC~Qa-~+vOZZ=3cj+8$h&ti4^sUX>fq$p6ON617?$kg8VsxW^GMDiay> zYbONbg;B<|=+HzDD1{8f=20eK_DT@Ngwe0R;k+~ee9PtJZTmxNw5T^6n}G8A}Uf+1GEFluSU6=>P{$8r#XE4pK$*6$W8?n3VGyI81G1$dN?4Nz2K*W8w2 zK$24{Vf=8#yeb9DhIRpkt#wDyxrL}sJciewj|`7)kh5-xrtLPbCqwUCUPqEc#`q9J)kzX8rtqxd zMVgKz5TlBt?Zogy&*AqE#<;UKcjR}L!OdA4-$k%I=T5UK>s(n^zYi$zvduhZPX`^= zcC4g7lxY~cxw4KQ3~#}PkuFlA_Gzruo_tsi9hO!YZmwK2yIKjqft8`aT}57JMkq>8 z-Hhn{C0Tg6=m7!M);FAkD(^m6-8{A7i?f&+nOXjPuPra{tvOZBih@+YknyZ~1MANr z>?`toc^*wSj>@Wg!)#X)_j?7B+$k@Ky(cVl#<+`u&c6vBlo9BWD%6+Y)%DZQ`VUMy z#Z=5Zg%R2XXuoS;n>t%kulif-ki*8a`uz1UJ<%fa?R}KU@B>}pQ2+Mw=!w0BKo5Iv z8hm_Lt>`tbumx6k#1%&zl#5GH*ydDas_0V1c5W2$e>-CqF#}R)urq5 zdfoSSoNe*Q`fR#yD}^GnkBL{PEMYl5iij_h)T2^WK%SIaxtq+pnixeKC$DmDB*Pikw!i=Q@LokN7kUWsB#NY-NcgsdjvRU-7nwm$#kX07RNm3 zOMqN+s|YTyZq%6G*hZewl0c0P>`d*Wy4~%V`xgW(j7j5hh;`sL9ouf-M|LduvU@za zgJZ$+AT~ibe1CRJ$L0fX%d461yHL9VjVo7v?JFs=hc|LD`(%CQOz&IQL}S26XPngNyv>`n6mFFuHo9z^d5Kg$RVzdt@E4 zI@lUqowjB%BGoKB?!kOdd3wyXZ{3Mc`}hH&>{9weY7p}1$tjwRuqA--3t+}8e)F>^ z-L>0LzwR2}b209lBc}0B%a~u3lh3UCYu1I-%&HzLb@bDIw)=f`D7VxwE`Y55@9|P`{oV;I4Eh^2|M~%zc?PG zou9wsMvD&^C_eC@U&h9Jhr)^eu**UW;)`34GI87VfJS#`$eb~#wxyMAXs2GVPI}2B z!9dY;#!lK}O(uVii}|K>%J48g4akqG*oeSMxX?G; zH+q(O*kM%kaB?vLNI71wzNscy(I-JBPG>Z-FcIA$`_9E^w4|fu9VUo>96^`Fu!sV zzL9uqpyy8x+C}+{8d-XYGOfx4^A(@vUkzc#Z7BYBldsY?=Vuvq0@9L%sF19X6#n5< zaNgWngat7dKrGuyxJ($h;iA}VtiSS-6LQKXdZSNE6r@HbE0na$skx*&r9Ltn#DCBV zlw7dID|n^GYrj(CeLIOUU#aod4@R4+`qoEYHA)&!HBR4^e$9TDMLqwf5tXwO5oM!q z{doKufd2aFB)0M@ZN!yXinAYgzdyngX+>L#j^sg==<5QtsEdYW{zJy6bTYiB>0{s|=w-ZYKu$%F;7Lm6@Rv9QP@JR%COecR5q#v{%LULs3q1Y83 zYEiY3?@tr`q-_?)FCDWGPZseVpoNCTNaQ7MYQt@lp+^pXK-t$Y#(#lX)k1rQ)l*cA z+1fBhZDx}oNr}@Qt#Y(oV3mPlCp_!6aHmS8y%c%TpjbJ_yLps(hUFM2jazBcf45lJ zq-_;8m~WMVPBijV8_t+)tb2;Oe>K)-W9t3>XW!KrQqMh>DctvrmHR?%=p%EvT`i8d zhxc22(^?89!~t50HwBD6I02~<1G9W@ zS&|=2_bE<5vTt;DI(9^Kq{vbZfRt>MY%gz`C5I2DnzzDzeNZTH#CET@yNeaYxW2v5KFA~H$gW3qD!C+C;eXHnYC`s0 zT9inUzTePPhm1YifzLC5r_}bXit@H8BBjZxQDqjf;pvY@)zA?=4>*7N&L!(*Px_2{ zsMq)XJHHJx&=M(2@r#3$9WjD=Yy26`W}I-fV!q5$;RNrn%@hSW&qs%LjrSf^(;n=8 z43#Ie5%h09sXr2794jYLAOzH4WDx$ichplZW$c;sz(^pouR&mki5F&;}E3bIZ5lZ9N$ z_%4gw`jEqQ)9o*oWwMi6&hw&&Uy}mcXw=`}FGQPhho=A^AepsD^|&8XzOr7tk^DQ@ zV2u30doU$)IL?&)I_@0dn1&kUOzF~Gnb1$)_h&Q!e`I5yy593^4VC#^0L}r^l@@%l z&9cgv5)G6*;lAAOdDR^I_oVW9>Z5;kGcm;hwDYu{O#05(b8Mjh7{LC#UE!)>^?tl^aq&;BT#*aD=%cIFu#Bp&}2pvHgTK*YBhDSc*C8b#Ve(O#m#gQ4T zEIg;3`n7nUgL=Hih8lG@7gVZb_kksqn4&^d7;V{o`u$CROnTBH#uXj z<-;zf<1Q|Z7rs!J*>}&TV4dF(o*+8lZ40yW67d8^EPLPh$DKF{U!2Dy^P>F@UNC_8GW-{oZromz z>3?TfJ0|Wr2%5$U;YB|B_;N%urlO1}ec%tFy&xZO;`r*_`dV>7xNy)_AGqFqHoQ_I z*%LWAY-?YnYJVfrswe=_?Rt7BvPe)L`pkf6i+wY&@wouqBOS9{CTE7Ei}~-+)~)tj zfJ3I0?eZ}-v3%NmIi9S6^{m28AFzht-QSv<1u_VtJGFu7gXvYLuE=S1c5QP%#Z+$8 z{t5s-dJZeqRWei-Shjju=>(|n_J|E~rk_+?3_5?g@9@)!8J%->z23{UMnU#bjL4gLb$HkDGSSOq(j??Thbk1zV>V z3SPX~W*0~lgunORw2*vYiw+E=971|vU}J-9$8RguHm9=Y<9VbLPw6P&f;a^SyXwnO zDQDF>20F{1ejHBUQ6b_eP#C{9#<0xdRLu&;jsw$gBmL`qvmm!s1}_H}!JsY{)Y#Q+IHcZy@^*2)h1NRvXGS5h(|5WyHQSUd^VhF z%NWL?uQooEy&a%*z_e=|TY2~+b>;ZWntaV_h41mJBf+-u3IBrqxo=JaVRQn2S?IAN z*QOg&V9`ym#HnKDsI?NqgQpLR5`%{bs@9Tb?M`~eamz61 zVy2;_ENWk2b79JJr>^}AQMMLS_R3;R&xJl5giHS+ZebDkai@X$mc>dGg}km&V3#&W znrk(%ooPm+VmJI7gy-&lF39U?jOj>xH^9LY^LYvI;r6hqb_yOZG`gG6k9(DrP2a#@ zs5`Uh@|g_kt(Q@kII4H048BosNbY)%bdVCBaOvJ6r@s?kq?fv^w0}nkJ9`O!MaQ=* zO=Y}1ca+tSzx+2=-e|QjmfHW29dGdeX2;_!;*q_Aj@W+w%)Z+^^*p4_=l|ORf)Md~ zcU*6ha;XonZhRwU#cya9FcOg(4mT`Z`+=F_5ves+_+?0r+@H)wiQ)>MklUY;rnly; zh55A(GFsAfjH>s;j6PJ%M>H|sD)}4|{k(!7DMxU6Sh6k(cBRZUUcme}xclGO@iulF z{7X*?K7Ai5zm-mG;e;c!t) z;IGG?ipj*GLvxap0iAFcFKr_^p}k2BYO$5RGLdnZ!F6n)F8l)+MPBz)X&sQ*Nq0HI z(Xk&DH^oFfj$Hqu0R?7*lShZ5>{^IZ0T zv(6`nYh)9%8qd4F(pNfi3$TpOuZ|PWN6bR_4*(_3VAF#)waHb{ogG!@{d(vKFPNmH zLocv6q(t7KTPXB#TsJ4m87%X`Vfr0de+tcc{$2OaKp#Ms9f)EfP)9A5TZC;RlD~*# zaG_$FRN=|Kk%SzMHZFzR93eZ_$_rZnjItrx=@95^L)MsC%CVDQDsrYdTi-$+k`SkB zrtUQKGG;Y>7mh!jWb;!w!Bs%FKzf`hF~)p@(zFO%;A$ zZIKK8Doxz_icNO3C5y95mP(nw<+7rXg4q6z-%RW5Tu5MaAuNaA!NG>FyEoBptf&wl zkN2{rp+^K1;#tcGr2_^G&Uc0BzGI8#& z=BhS2FnA0JbwRYLp)BKDu#NKIZStP#?r6cGTeQymRBJ4noN*9YKYuVG!^^l9h-z=M zk?y^E38j71OdIP2w5n6~Wzurddmswvqd@nOF6HeirUaliOwpf?v*e7Jf7icPf=WfC zKkI%0XliVvvj}m|>u3;QO|n#@}!FWj8PrWg!-}Y-@a79V5S_$luS|nG}YbaoVb&OqN z|ItGRv~}>{q?D`h0^RAYJ=4m% zNr82~8!qMRK<3yENL6Y?O)iG3RPDS0+X;16ME3iHh88?7 z+^#D9snGyuhZodYDf73~VZFG~FlX^8q9jm*3OEyy@Fk;Y6fM4Nmi8r!H|nIA zaFK5HWQa32409@ip;fl*s{8p1ohpz%R6c%x9=;SbETA758^by z4;F*2SvobH%3H1cAUJyA$%|*#pdoh!qKg5m{bA3vERD1Lo#$O;=wBQ2=Y$rfgLN;s zRN-Xq{KMT9Ng$tqfnTuB_O4#90|zgPk55WEv6P_#=8Lm@hPxsD8 z2=fU>nt0E3rQmQ@XQg(vps)`DC|n&n zl9IwB(1QiR>(4k+GJ`rUsRrrzc=ORd&+iytE2Lii?kt{fhbTVMVth`!S^O$g8Tf1$ z(ddvSAt5Q$-GI-{CDOsO9AA%w`1=!etc(#2;Fr!=ngw@wn+2Bg{nJRtjGf?9$HsLk zm2@KAGNx=ynY+f_qO-Mt6T-L+<0<0Q?Z7+wQC_fQx|NZXDC6XNXLv9NC4-nl3B ze4|RSzpO(dMhueAaVC^%?FS+9o^Op;Q8G~++%`%~jMyWgSeFB(&nnm6g*lA1jyPU^ zu-)Ng$zh^{Lz|sg%pe$$qatP2qGtXIOj5vKqLA#Qs54eLLLoIn{E@4ev8V@ZpFR zoNsnI-doJ8+#_WrkfNm7;Qm##L=L+By{=B4h@?oPN1f(uMtARaz|C~9we3gNCs^dv z;$2*u!0Ck)*EYOpvuaJLH&V>tC)64+{YdqgfLu0=UIB$PI2`!xgtfmF@`>mV2Dikl z?q)8h0huz7i)+1qz&9#_<=Gz@d3)(mqalx5t!iUYF)ON6Tyd>~Gi5%pjP=SW0(p?A6VSGguo0@fbhKpIHN}&OVeBZ>&+QNE z9wog5gd{gnK+An<2$q_By^VTAeW%GdOrX!rFFsD)JDSJJlcw{o>eacYpUGI0GCocs ztMN&_1g9WSf8V9x-pwbBjyrZ-rBvT`mO8#X`Cy)fI`s%uv8N=_aHx#uX^$7q(=Zmh z@tnipYbD8{a7r>Gx;Hy%S&3P1LFjF2}xf&xjBKO8qM+Ab@97s7`_ z&HtN``W@+47f}qw;l)zhb8VqdDb@5$?~dlrpN!cuX4urdmE(kxh~Ja9)5N`J*=5-o zLj`btKZev$IrMfy-FSImimhO#>E#P7*fmk zeR;AxlLY?V$9M&nJ6AlNhG5;z`UVQj@2-<=hQw-+PsMsM= zYZ+<`m|WB^)4QXuC~$!l1Bo)Jqtkn1!jb!*DJ3c$+e#SVT+bf+$gVp?z*mCVP!Av^ zr$9A|iQ@R+u7V3lW|L|d;dTX;9tw`(xk zr|;thGjsZd^HcbhHTaF-@mERRckkPOX389eUS=7Y0o#udYQL=d{vNj`JRAiMkw^W+ zA(y9gQQeAPldHH%nuhDwo`vgY4=>PfLQx4X5t)U{jw!L34Y<)lRLPc_gQH=ov_C0d z`dvlJtgoh7MWO#`VaS0}YX-@UV^satv@OhT6^V{I%ML)ms~2y#^MHSyJCl58SX0?T z4`qQ`wWxKxYaA4a3F~#LQ^+8MEflh;T=FhWBM&=0lUD#wir7?k)@3Go+KqHOJ)-{j zU770|)HLlR&6$R7vp(E1o?-3_G4sIny>-cNn4c^19uB}^o=%=~)^xXVZCrcw^C~t7u5uIqUKEX@@=n+eck679}cWih3<(pFWIYm z!PWs;ciE)QzIWMN%}d!_K59$u*cUv)&%oRHIQ`Z7%JLnz7^)pb`wOlPUu?dsH_Ov} zw?54q4~H3EzE5A=O)_}KV(N2_qORua?tYJD{-vAy;VuikFm`E{ukqh98S+b1x$ed(X4H+d5#ktn$m&mY7B`R^>5!ncbqkDacLkPmnjy z)y|iv9q|WQZ(f~BY8GJy@0lL!I?a<$~?PW4Y(T9n5nR-7g+200HSdihe<*|XX% z(|TH8Jx%BrnVIMGB4D;rE0SPch6 z@oaZRoDZv8rBD|XwuLEUTt&E!F)qy}MgYB~J%<{f+at>_Z@5tC!6}@Y539ZhR^`s# zyz{C#?eNh)gx=S2r}dbSqr;`Nm7781Lr>${Nf9n)59=8rewW8z+)}tKK#3!PD2TyKX?hkIM z(sNqF=LhVM*rr-+^GkvwPt4_YZ8g_qp4rG1qZa@P<~}{0q4^-bfo|W0yRh!AJ6EDi zl>V0z=O|+r=)8Qp(@_+C8-Ni}c^41mD1znU+mXLeZ?G#iZ{m-^Ti^c%kHW?T*DU=H zLG#7%|4-2T$3PrP?5R_D%LmWo#5;zFQgGCNttGzxN; z8g*6?O4?7544Jd+k|&0c#JTyWT>MCb`&(7y zcaS&MDt{;!^4xWCrlKD!ZGV&!uH1qHFJmJT1q@761ysw;jF!Yr(kLBNO>j|^f1T^$f zz1oZkKm;y+Y$W6;w?*!)a^y*@TxR~Y79zEwi+YoIUzxv|o+tkvZDf9g!FI2iP81}3 zZpuGRw~}kR=Vltb_^qq~+Ud<_0`0>&Ykxm6y%%XwSc zr0L%B^`{YPLPsew0&-B|1a9;A6`%71} z?JQbGle|FD-^RDa2@4Dks7BK-OndbYlvhQcc-5}e{6=q!q7BJ%6Kbsl(7y8t?ho6cE&jHHySE;;vb|DCzAhJKxu zgUIEuYRrd|-MmWfb1cGysyQJIN|GriO0*mNJ235B@+S5asX(gxypiees#uuQoyb>? zJUW6dUAlCOeBUH#Ifl)2$*?!204Q)BG!@b^2)nk}H z6G}@HNYpRO8XS4Zd}|pWM%S9vNmz4+jzf5m?e^{kkl>j!AJ6IoDL%QMp73TQ!I#dy zWt?L>a5ekUq|JH(gKIw1h301AT)RFOLnU~|3e_9;)9#>B z>8coN*lb;S`|0qyp>&ls!%znL;16@s3AY%y@Vn8xN#Z*F3<^p{{W$H;b&8&JFZw$g zG41*bWfZlBG~z*OI~^=GSrf}5xxiwSYchU&6^SHc8sap-=)a^EM>a63s@1A|G*DG! z47zdB5=XaqKEE6Jl0X1UL1^MBpZ3O`csIKXruVl}2?r%ys+5=No+Y)0cfI(6t`Dsve#FfK2H#*@r($ z!QsnZ>44#)q-`EOUcp>gme@N@-u1U3BlpdpF3sKYj8{3lHqk0Em$zXltA3^i4uCU@ zd4CO+qt91}%GX0Y#S23rR(5ygu}a0%9(;ci1V-OSw7vC+jWOYKSlG0?mf-66O^Ftl zV8Y+6(&Y_4xVX%!B+ins+V5W)SRN9I*58K2~A7$aMS6iBdc6 z8~{?F-Q;k*Yy;%7*T1`wwYzO~&-P@2K=pf;wGCIt(Xk~ug{$8?5^UT#fR2M#hps{% zwJ0)9X{jImaV$risY8Cn>3Hf0IM`e-ZEpAQ`|r4Lbutt)ffs9Om?W82iKJl;5RbKRJUo!&m`xy*Q3isVoc2Ru8wEE942 zLzjf4`}}ahzV-7HICPi&R3t&Ofv0%dLYZDMKNVIm+w;p-K52GW5Hh+h5SmzGO2WmP z?bmnA15BnVqbv$Dj!kye*57&3T08fMOxX26QzAGVcKoDfHlwV1c>bI>{`%$~b}oG1 zS;OQ-g$*M4vl=Gp6U3sp4An7>p{8cDM}Qspt)plp>cb?FI=5-FA(oRc_ETLtgohjf zRJ#k;6&&7kKYhei+tKw$PqW|Uo@`?@B+F{UeT`3QEnM$SME8tO$xidfL#T(SgZKrT z8At4&4inf89KeV~rL9en5gt`^CNGu^q1ok#u|Hy8ut!N$@c)SAzEE|v}ZYD)-7ne4b)Gk|1P0gU%-7p^u6QYqd01b=o9Sq$XDOLKKB8QhYO z(_nHKn$-+Hgx_x-q(`{$%OLi4>pXt>Ec#pnl=pF;N3Zis@675%E&)={)l$7Gqa|JYnu38?X@^*THNA z%4Ct+JySS9Iz(F@5f&xixzssE&thb76*L}cVK1$*H<-^dR^JOSDsUq!fOR=Hvn>h9$-Du>+kh4Sk{Z ze!9Xki~HHaVqd6!wY$N2$2u)5bqpaoZFTvdt-+S4@7@Xj4Hy1IixY{u zXtgEYx?<|hJRwsXfhrq^I;1Bovv%jGKW+A-HVt(s4i&XOV2kJ6@36~9I5a{y^kzf6 zZ93psI5b9>pM$EmDhc)Bjy8V~5y(zO;(1HEIT(Pr>3>G%Uj5?s^~Wn1ofvmgq(5Tv zKVth6{)&)JIm@z@J5n50ISW>oai^vgd8pwc%Yky1}^PW5(z-B`xPfhvAMZ zLdVWtK+B_I8~4w7Yh5!sQK*@!8N$^LR0%{&W0IZE6tj6V-Xl__rFxf6pH!vg!1}g> zq!YZf(&E!YFOZyafqbNWfxL4}0WJPxuk>RN^;jL(q*AP2`b0g2#34_i1zs3(_ ze@<`<=BqZH440SQGJS^72Sz!{Mp|z;^40`k+M?SDQ{8yQFtND?`$+k(MBDicF10~B zB--4e@9KR4cA4Hci(oJP_;i@OYDK(-Cfk}%{{+}-Ec-49jm2u_?vF?=V(cTh!KH*F z=G16q^0PFK>G5Qq$iNk`@8*@f@UAw|<{h+JE_i`(Pg-{}%ku^Mu+I?&&cs}^O5Vv1 z_Q!dzJy*5^2!mjjSA8E7!Pl=!r|9(fu94leyLYD#$?VKIe>|((jk$UKVuMgqi@f-| zKi{f|fWKZoYVX21K@5sP37;3(m--LK0_b_ zM_|rXFa=cq>hZu9Ql;+sRI|tyeMKw+_PBfu*}2mn;}?CP%gz}axVw^D*~;BALn+_( zXq@M(7MQCOo~ujJd0BiEc`$o;u!54O?}|$?rUk&KYel^$Z^QKzSq(Yf^`196%J$58 zR1g6uffpg$>3+P|jth>W#1&VL`Z*B87oD8Vq^b~qJ5y38yF_#p?7{fCKYVM-7Jk>| z@QbF{^MHN`Z_F7r&l(<&m}eH*FAM0jpRpohZz|x@m&eqC{2pvwWA;jdkMG%gp>j4% zVQWjj^Ajz{JgZ~t&2WCVIu>wSjEP!>d3HD*MCpwPY_~J8J|HJ)y+`S-w6#Xepm zKQdv<pSzocgvvwp?ld8Ar@Y&C~S-^u)-|C}lU+PE*&DvezkNs#0^0a`*NyE?uT?PZey5DWGue>cV3`eU zm@--TS`f|gX3iWpj^Q)s@Q6=f?SWqkDdNEHZqf|NIz`6#-7KCLGYGc%xYTkV>*7Um zK!IupRhPTg+PBGkI0!UV*HtJ-3!6;0xV%IBHDc3juU4xePhBZtSgjIxS(|I!i#aHcz)Zs1mUcG zC)H0Y75ORQbEKORH__S5{6@KUV6q7+b)S37=7xLAg`1*#8`%X|v}(UpeA>TG^88eKP&shmG)McpuStQ=o8rHT7nd>m`$b$e2uEJHA#I|F6U- zbN7YH*b$r4x~-*F$x99E-d3JStay;ehI%gn;iJDX2f;0hes&d>t)+~ejN!KRU$7a z8~z?PzX6RZ!S)3UTIoE+QIJV|zZD2(;@C66naR$ZS`qk`XAZ;}gy_#FBi8@UL0ew5 zGUFo{R>v@jLa@E4&5vOgaM9@vwJ6{S{bOV?x$ZKdMai6Pi%`$Vfm+G?4ot@P& z;zP>mLoE#|o<*7PAlogmhiBz~<>*U8-Pmflei4tgMpWtVJO~uAUpunR2A3ONxIdu+ zgWt{i`YCVL)WTXI56yR@!)J~w?^QDt93y!w6JjQox%Wus*T_;Wuko z!oAR_bhhtf9-B*a@>+z{{KX+)bf?msi^lkz)ZRchhcb?6L0}h=Gyl@T>SH-+3l7a` z+{*u;9ZC&{Ob7=4ByvxVHky{t^{vT>Ab0+mi7o;_OsXdD9Jp#eiJOYI5l}2BB`bk; z|EeJk=(nT@=Tx{LVK_Fyf*t=^sV%_R-5&TEllIVirrN}}x7VMVNJDjgxv+Hh;wmOV zB%kwQS7btgx6kVR2FAw=qar6Zw)V{etXgo2&|`hc$4W3d>NK>!Oq}>z#0+Lcd5oUm z&1u_OMuEjS+GgBnCRbQT)_oWOHdQEzewJ==ad>u!j8pw$5OesEX-s52U70CcgymVZ zIMY|;CIg@X{PCb{PulFnN%@I79_5B)N;gyc%qEI;vE?#?{M>lL(=Ni(k>^C)Q5@Gd zhfjZx^Bu&4rQR(KlLm|cS>Z&m zL8hNV@|UQSlU;=|sK;;ul*9>k-;#a<%%BkNga2DO59ec2iSqxD1#j|yS?~q_VZrN0 z7?8deq2uXYYN=r>t(fD|QZ+?&=UslNX;^V{*28!gaw$xfPK+BCq5O4vqz7FyR0saj z#tXk|hMmKh#Mkq1>!o=;zhH;(u5(Ol8EYyM%jg}v|MJGxE6Shf7BNTnp4KjCFTHxl zyUHye-lDIXnry8+nt0<|lA!eTe#C!R@K@Z(cKzZQn6)jguJTPJ+m$uv;;@T6jqVTE zLQCbYkDABDSRZ&8aot2Q^>8b7>mc>i7>wmu15I$Ti^s$}mAFCY+E-q)in>A18 zhwdUiJDgOT6A^}yRh4;$5dkH6cp;n5G?8Rk7B)XOHF}D{**FXVXUEFkUObVNw*>V* z=}wl!h>su1Vjd)dTgr3Cw`P!|$*=`8S9_muf_a2n+z9ot?e>j1C@)brpSOslugaJ? zwkpQ!ZAaMiq8!pUg!_HpuFoapvsn%Wt(Wglr@?Ps4GVMv^bp z>SUEY^#QiywH{=b+qaDqp%(Ld(zQv#uaoT-Nc)Yu{lKd8oac?~)b$(&M%Q z4wY)!lzl;XF@7kodmc*Wc?O{8@3~}N8D1U)PoDkCl|Dx9_1(-wx@+yPpFrD90P}$; zS0~MtP*2rgTpkWy{G~)Xj@K6dMsi|nCxqQnBEdEES@j=1rv6n&V*p3E_`$tBYVd)| zfMH@_bAk$O`@q9ZkQ?xxG5z%~k)^=dP!F^_=&4qRy>1ApvGy*5tW|_larYwjf1TaC zu7)`+p;VDMUPSLa+l!FR+I@a_IGquu3QQo1-tZ71JG}nV=>3W8kSG}3)RL%CWiNSE zRl%9{NTqbiejKn=nDd?5#q#>e*1}h*CxvVBWrlikDdpnyW)6X38KCByI6G5xCfR8I z49mL`DsG>>py`fUH=xR}P>Hd3;%@W?`s9T4xV^!SZ%lvYIwrxkSl*Ah;+L-4iSkdo zxYp`1_nJaKymozx_Gm_F>=@U4X{0)|r&J&hAO^eMT6sfmXF!6fv-)c-6j;w!HLgv0 zX2J(CRU7KdMTO-TdD+l8UvX`>l`6iCV!I{Y{)u{VRQ6!CfC6W`NV5hLvq=(QfWM)F zc3i*pCNkyDwu7t?a7EPAcIvF!IrlKn9*CxI@bo~&?#XQlx>KQC^A`lMJ{LSiz}b92 zvPR5ZJl*9*BCobqB}G`)lNryI)IZaO-5ZBxWYF{X<(Or#yUAwIl*7BbH|(dobCV5t zQ?QuIK3h2E&bud7_J|U=gb{ z%1%}u=>kTR-LCI0Bc69d$bwRCGET6mu!ziwKnzQAT*gc8_)#I341vsTen9myE$iT_)tTL-w$fLv%g8j2fAx7K>mpzHigKUvCaRQcXU? z5|TUDu0D_cY_o$z@Q$R}a?dps*i<^R`$h~@0CXkYl0?i_O2&lT@^>E|h3{^lEL7&x z&7t>aV%(^o+`wH`WcAe2>&=`KRi7+^yf3oP*yj~!+PfRVTEx(NP)4qg5DOi0Un0zo z<)CK4DbxU8fvmLWq7*K7VzVp`N144EBNY%JpR2Tr&nNU*@MqGe&{R)98Djh$654F!O_RleVxO~D8BSS%AmkG|X&Q9kFXt~j^wgFLpwU@kF%hJ6B#G5MxIH+o z)je{+H3QV+9-N051L;)GH*7AQx%2QiE-E}O(*g71kSIz9mX})AqfUuxM9QP$r+M^i zptK0Pi>9_RZvbWg$b4K3P+D*vovIsWAtGz7r6!*+qzflN=EW+UQe1+2ZjjDVksl~= z9TUX?l=wIhEc`H!G&GNdm*-_Y`0lWip0hbD;W?%7B`G3fK9aP&S21%#3Lt75=uRH+ z4pVgwHhgFSDP0Wg);7oIq6tU2kBDda7P$$kHKrs%% z8N0#&DT?a~-%f8-?p4LMxP8LHS3-D8OC@OPHY1-iI#1S(Gq(A;OyzSyhvepAwocGG z=nXX3_fuZS8IzvmIug#Gq#NUH80yM>2hUm_=e{(nC9Dj$TJ^K>%_39@#Z^A^Q0pn+ z%J|VekGYDkIy-0Li#ON*V(dP{;fmgd(FX}pLPA1xK@ib<9YjI|Aqk>)M(=$XK?Dhg z=v|^EI-{4-dl|hm7)C@LZHzL`jfE)0kMBwy{L>ekZ$_H=76oen65a=Ei@Cdsf`h~B2_nzD2DBB4}8^e zF;@1IUx)QAaaLaUh-&ZClOd4vR`AMP?eu5?!>tsLNimTGE_hM6|f z;^}y`ou68hmzBSE>WVj3PU>X?t4r~8yy?B(gi|~n-zX07mW7C#HKa)%@1z9D`>u@f zwA{U%wBRm3*krG7J;u}VQWd~CArQ|t1GVA|N{O-Zh=Gs}PsgL_*dEH&d`T6DVbu&- z7YY|Y&lJ^(qu7luNk9Fx99EM6R(pt|egmRnX51FntAZb&sl^7ZTbdc}awwye4u#GN zdcen%)iW(iib$Xk6J5kZzL%ZBmG^40LNug#k{rRDpPM&ZbXXFHKBj1<+1oLZkk^TL zC|8&Ubbly!N|(P6y0e|+J2N6}I&H1W!2m?E^;F#Hoe1hKF@i!KO5lEB5?}{!i7WqR z2c)L7Y4thx>7}|LUAGiXu=Mno{VF?%1bf;8YJNl4+a{SJ#x-E&u81C8Yl;d7T zc`)6RJ*pxLyc|Dp`4)8CI_~5=9t?D5njl{2AD1VOtSh+FLbO+LlCC6gtIfztT_fE= zZE$(4vzYUjJP@+hyO2BUYnGNf7M&u>V%=fe<7b!AyBa7~;Aq6s-99JBu;e1$Kcs6T z4Ig^oE&C8e(5vLU7%TZI6T!Zo3m zuU(63d92s*6}83WCHn(IJIk2M-5Ql(kMRjdxA#=#TP-5sq^r6X*^Xj79Y2Pr<69)~ zbo@;EDBEIlriST?Dcrs79TnoGSHL*cPM2Rr)_z^e7jz&?M(Yg|RXEoZvcFMEH6uLH z%&xuZ+L1kk4vlQy2MK|$heO+BFHXT$yNG7NxlvXma9iToUHDAyGlhK_!F|fHeTE;@ z(XyMH;)G9O3`H$1DwRiwl-av=_e*{*V;P=Y8>0Cg!|jOdXUKlv3z;x{VD~ilX>>1B zyW5T7gM7zudP%aCt2ecCjub9lJC@C6zhivur#QGC9dj@T7cuF?w0$tmW;ISBVHXsH zQ^De%)BJuSeY+hFDS}hkqDU6AS^rjIe@tMjcEJvYvJY&1*dG%#fkpG%dWmFOwYi-on69bFp3gaFF*&e^P#n zt%jKte}saZmY;~$x)Vz@nF7I7P{v5Y&z8e~ZoDyzQ_8VN#_l^*#X!U~G8 z$qjbOJd4J8y2*Gqe(0t<=Quam5dPHM=}W_*7DPxE)|18hZ-%SuX+f)ME$dha&n@Nvey|TPr z9rP|YW_lQrn3C{r&6Ri1-;`xHneo~jbD;7>++C*Jtm`rjrm1=;af=wQ#!C!%ea2J% zx#kPjw<7ynkpho3gCGNd=PbGxEYJHU(D+3O#nmmT0b+#+;4$hsTa$Ls3soH^_0OEy`78pC4Gtj?-5K zXHR~m3JT5l-Sz3ctn$}o@zs{!2WPS}0xf&f68q?x|2i(9rD+Y@7PcO<{`pXRLaK9~ z_C;`+f^1IpX!@Y*r8>&_QjhW78$J7*YgMP0 zt&~+ViHMY#$kLd|K?(NCtm0Y2*xUX*5@j_Q{aCA!pcl9A@N@-lH>bR(KN$6vebxIc zBue_VwE0Tgy&}QwJ+HSU-yT;i)dfALdd)L$)=w0thBZOoLh`H;bbGLTN+(HWaWBKv zRI#xvg~@dT6D_Crm0WwAWNiW;!nND;9d-Vm`p$@BUy4P{U-4B0rx>h|JqZ!>ncF4v zSvKZzLmPSqnXfB=G`+y`$`h?st;Pa;~@uRJVzjy?H zk1{A;H&DWr=B^uX`qMsB*x5KTK5JqP*s2{$psHMK-klz8=3Z4Un{D3M;$B{f$c7bR z1omSu#^>xXY4+s8&e*wTkmMh(#&SO-X0~-KYR=?xBlRN-r|u*DUTs>U4v8ku~Ht@4plen!hhB9#ni! ztCNIo2+#;9DswTOMij|j2c@46yj{itG%qeMPKN)kuWbJ11nkw>1vAmJ_9oRBTO5CV z#x~qk{YKhQt+zCXV{>+w#nhjQXSs{_V66b8y(wSn1u1SJN!lmnJ$P3Ddc7&Hw9WF) zpX%8@>8H3POyq=ofBzCLY% zRvV8o7`l*X+^*1+={&WutEaHB zaj4g@vFUIzh)a4by>-{3ll1xaSqOD$G1Vto*ZFM!i95MVT<>d0 zUo^iJ!;(4Gs_jO9bD{BEP_V`SB>mPuZ-9J(mk#bmTua@YSp7j+nuw3(bo(108YS|AN=|uU>&Fe@ibqCvut|YUgo9@>hW!@uT1L=tAJI`1kbL!N< zSCBRsGPtky_i2wjdn-w5s|twf^#YkK8(Pu<#MKsIgW=rM?U7dkQw{77EDZ0-FO>JM zFRj>Ire*m?9T+YO&CBz(k=S770K#>uK2*Y(%+(cH&(^M1NUd*{npLdX+dheU_N?KX zm0uY564stc&U)mM-SD=TP@r&rOa@r4CoBgQRu#?AdN{p2-}mSyN~HKvPu z3J!b?$tN(fwN@<;dgO%`G2um(=lshw8}qKMG$8TJveQ$!({C#2%@KYV>p6w3VOYhL z>k>?S#poYhv3(4(VKX_SC9#)8`_gv{Q5c)jAS|(&j@yc9)4Jd<>nU z=$e~^--unra_gJy@hI@%g}G+Yhvl$@i~u48!r7KP%XXQ+nL&eHChGE@9MdefEAiyo zH_0|zcp7B;ke8AqW`Lo{(*-{RoRlVeh99vy)%4|v|2<%wvy>W@zp=tSon-kqy430U z5K`RB0LWV82}@jU9uc+1&Z%5;#3m*e|9|qVk~`JF!N5Wn^o-MQ?G?xmKXqJ67jRvL zOP+V~Z~ZZ{b3vSAV&-a_m3>;`nhd;|l>JczJlVK7+1PlSl07xzS{Mv^0N4@N5)04H zd}AEU@xcsEzc2ogyA{<;^A$053ZY&AW`bq9hAswB8&~D_IGk7~_biax?5&O+Q?Mo1#t{0k zY&#c_v%g5>9%NqN>#^weMIkHu4~rAnAnVW0JROvIS?)JO&dPuRwCFPNY~>LWI>oWn zQkZdZYTMT)QLbvy))w0*)%b;BWXCQVsq%OY-Si+F-B8uLCKWrQYm;?~ymVmrAyKra zU}o-lu##DC-$?uL-lW0}&bKIemt@aC9V&8Me@u6BaIHq9daB2CR^%ffv!l(yvZ4|E zcQLTJ*Y}(k1l}u(o!1U%WSQJf0)IBeuB!x#ltR#q3HWsBl3gw3&rBxKUVabGkgz4F ztKUyxNH#$${Xb1URLj=v&-c;t11($Ma}CJE-wSn5&!2s$;N+<*%(l4v{8Cot$lJ!)ATcu7pQ;t^qy0X?H(YGXZMhhJ~A0Z{YVkw;2`-ByZ-#!P^}N zf(%zj-h0PIg{NU{Bc9`FOuR4E=1^pg*=DA&y@^ZE>!*R_DPrgOr-+D2mx>vv<9Cx1 z8DP#x(^N^&)PaK5RpTVjfTtW5=r6TKDznHC$t^FYE0d;>$M} zP$1ZGX5%S1W7fh$MXQ|Hak|}SSuz#g;PqPb?M?})sbnImXn?!*Y(@(`fUR!t;BXu& zx|rXlJnL%eIaUID1DSrR_C8slk9cSn^X#50mj#k#R+51#nM7kAC;XL?A@5JFd!=_- z(Fd7bh@j;qxY`4;nm}BC(0t|P5a^%=C@D-!0oKB^yj^1zSep6I zC5${*1bl@CE8jRFwSY&_mK$xJ*$qn(T}E4)XL#6&Y6Q zB_vw8MwXI3SW|gnY#Onuc@3Uvk)1~kEaN{nbKW1c`|DYP>)a~SlHtpNV*O|>?`Bwm zKWp>gM>|N*Xs@|K<*k5TXESv+8D5J5*)5`rU^v z8a!9V^Yk?&!GlOR^58C-u~nhDs8#*-~aA zaL|lNB-;qeT_FkZ0%#X>0E2QB=S5xcz&v@KTUAXT39o=bne<;3Y$HDX-%CdJj0#iF z<@rCJk`nF~>5R@^w<)dnkTw-NnMMYVe{Uq*t(S-DM-8N(<8z>eqdu6x7cXrv+3%FL z7oWCJIOO2JZnDa>W-n8Td+v(@)ZOMT?NDXQAMz7;=3P5(GKaVPZott3v#mgwQ>g91 zV07!ZsaUKxFE2tlekS#jYVQ8{3jSPT&HGd3-v4)^UPJK9moEIt zH0YW%0>;+w6CFt;*s^L@Z?s55srrAn4+r+~((ol=2r{q$bIrp*s!+S7Pd(93IB#}Y zZV#NXiQ!(?k^I0W3vL@ZjIvH0*jxH0VCQyA;iz+H$C~OA^w`Ju#t+wzL$}lf?^>2x zLj1soEaYQAo^i_w#grP)u&zLdi-Kf$D3i4h0# zA^{#+JxWWeFGqt`=NqVWJXs(7r<@t1_Jw+1xq21wf@KpB^X~mR0LQn~SJD8N8}iKA zf^lpBtgi(6(anDvS(ti*ltzPg=Nlku_hhN>%@Um) zIpz+i0ph=ZyyW|NiB55z7{z8Aad~dB)aSX+fq$640uDB}s7=-MJJUq!rnfZOz`1?Y3@A=yCTfGE5#PH-`jOs>+?ooyAgu`1-Pu zuB4&Lm2^^bR(S2bjsyhg?XfyIuT;gi2}@RF4wc_Dr;?{S8)Mmh29bxf=5?_sO4JKf zH+p;S{!p%rVA}n?)sejrCeMmkuksC?`yhR0Y(_478#LTudMGzXer68w-}T>RWpU%l}_gfJ1zipKOQRDKzeGE;kmJ5v| z20(J*9DZK@x0M(P5>)TA#ce%E6qDNE%UgXvlkT3~Ma>o@|R;o z+uI$d_FTe6$N~lEZcMr!fM-9wWK1;{V2JP+p!3!WAK~~VeV4FO0g_A21;e?+;?o zHsSq9#O|3K#-(`z6lWV0%avAtHu-6A>t8QY;%uULSe}tUm5BWl9TTbD=~7l{ozlB` zVsUrDefrnIoy5zY+3`nJf-A)G07jiB$#c2GQ98;K+ z#T-PB=c=#=n+VoKn^7%-s1enE<&+r2)IY>zXKDUvD)@9uI_@D8Ph?jJfU?(f744q; zMWZvM|Fnx!+LYyM*gJbBjs1uReqU}S1kX@$h$v_TWWPs65Uk+A8zI#{5lW4$#GBy9 zuOF#=V~3BMGCrJ1uVJj{N@jV^%MX{I#u@iPGVSvNv+3Z$eSN{Vet*76Jl=~Bz{B!M zcv$}9f5Gyz|AFPD;R0uC1&9dD%!>2SqQ)VEKJ+p%6U!P?PHPbkesMEW8=I7NM#SW%da3lEXeIWF zUK*tbDa`Bb!*VogS+{P<#nu@%w2;z?h!;#0J;<^oO zf*7UjOL+s@W6N`3@Gv$*F$N{*m1Xiw8ZENAR7-@3`%lXOU$UyAW@ zTBcxl4(fM0MAse=bKLF-sKCZ*A1fue5;`P^P6h^)mxPJ2euzaW!}GA(1t=@POphZh zZz}LU{Rqhu4>8sN+1xOqK`*wgMzI4d$c;M212SCuTk?r5ZG(u8?qA>s`U8hq? zrE5JNQN`i6{WdczbnF1D;yJT{s=u&`=5|!=?c;%NaLhemI4Ud(#kh&MllGWyt2vi9 zX!fc`Ols(cxDRyHP)Tys;CG2%y`qpBG_c4Um8Z8PJrt?i`!2_MF=e9r9mMJCX$?9> zR1)XWmwYv~D$hB{mW0__@CvTHqSnG!`Be44ZfR#R)6nCAIy+~<`qC<68}~3F*fF+7NDU_ zxdZVus2s7`eP&$8-A5M8*7tQw1a717I7Rp#Kd86VauoZ5#3PNjfkGaCS7i}c1SQA) zrvhh+FyqJ0%m!+hWW-<^HT{i9iN|Ec;Y-`o+Yt>#o4=RJ}h8GW2X*JQxO7B59SCm#xOQrUJ^aTR5W8Tp0oi5cln z8gy1s>Ubi-(eUuUIe7`ISEi_OLY;q{e9uaQ#Z6ZF&D*_*%eR`(k^+kgGnY6&?Mg#d z`EK6c%WqWsYFr)|VoNDO)vqAEKyyP7coi{g+gCV}7;~fj_KHM`4@Z<(J5PXSU0jIX z8@Fw8sTgUIkmYiwO%3D-NpQXW5Uav6W2@M>Kq0T0@x#HHI1&G}dy}1xjoYFQ?{%||*;Yo@epTkBYM(D!sP>oUtucsJ`cA|N(hCvI zA?il%`nho(F|l=r0yQ{)VzV7a$^AD0|`VSro8>&lh1r$I>YLGorkMdO<`uL?dJ1Bh#^D;@c* z;%oV=mv7v)M#m`f#C~mI8|#z2IPcAia-|q<1WsgvXgBpMb2001atMROS$2DBaRrG?j;e_Ifq`Nc%KI+Y4}f)5VpB z4h8Z>;xFGdk?g)uw}_#sP?}S=l;6w(%J^gxpFfU5MFftwI`J(D2q632=p*nZeWC}w zPU!BIhz`D~bw!^BjYr0|Il69X5F)g(kB%|^3~Dg$rTy&oY$48Ecf`giVkkS2rhB8* zNE$xaFuZjeU(49IH+N0s8lE|Hu4LS+ZtU}#qMtG)zSS6Ir6`xeO!Xf}UfP(rMu3CL zgMMyJ1T7{&qmmNu{NKTd2#`|?kb4M(ZNqB5n?J`PTOx0Sq&HC4iwP57Nn3GY=>vhg5s+)CpL0~!mI`r&tcktge$dyLh^m;e zu*NbCfjImhTZ&<4?$HJA(fIjDNk5_fBZFrH+AMA7dKXN;03?6W8;bV`r(BfjQ=ucd z=k#M|cFc}-Gt3c-crff4MQP-z$ z-P{XYCyx832z>v3TJ&yz&+Jx0=?ovGAZZLfuB~qp_?uL?0xfkGDZ%hnNY;O-p$E)3 z?&w!6U;ld5w{}%H-gRmKwBPFAwZ=kNTEDnO?K~G%06s81!?}C#Kj|sCm>B)`G<)Pw zywo*u!5Y&)FRtfZyY2M1e7~WIxi^8w>FUSU>282@STXsjnPA0_-QvWZ-K%D@t{-0< zq$VYvWt#W`51g}>M=u=~b=rpVy~m3R%bU7w0rPbuhtH3Feb228DwLBfVeUV~HID*~ zKc0^C;$VT|8OtVJ2~DQ^vc<5x=bFo+QJSDb1=}H-x#mJtn`W@$YhSUV8SC*^zfR}H zrbN)1zr=UMC?n?P`u$n}seOGXwlWejE(~=i^2fcJueaR-g}-`n&wz&3cMEQ*U1}Cd zgPwijz~=&I`p~GYeP=juk}p2{xx5=#68dpkU8v~SLjS#|&gCK_zRXDL@6T6WT~2nKtro zwKbZv#?Ozcxo#9w-8?JlIi7j~Ow1Ou=(8jduL@{_^8(ix~ZttUqlL zr_THiGj~7K_i*#g6qPE-xP2`8;(GGeRcuiRtemI4m^^90(L1C1a6N4AQ^uNK@eN{@ z$MuzDZ>hbuv#;674#!dnJUKj>T#DkvINbJwkz-?`Cz}{p#WR{Fp)?{op9s1ly?+WL zbXduGZ{PS%tM{>LJ&NM*{azg_i%I5Kr=_Z>2+r?^bpwXx$Ow2rtz@%2_Q%YQiBHD1 zH<4;@M5prC0ZWwyV-M0&{9|Y|HCqQ~fOeOI>W_|vv!=dvnd?6~08>NX>huf5Fqra> zX3g5_1`Ya~d-ZTY!n+xP7_)YzPt|^Qf7Vlwy0>ltc{*G}>or3jjTz(|Sk|Si5!yD` z4f40_O;yFrn|_)987pE7Y^YztF1yEfcE8b<~U$nnrXRz^kTYN{8#a&J8 zW!Ot{!_ttsOmBi(mc(e~Pn5Mrjt}ix)V@igRyEzSS2YX$5}vJm-?6BtaG^3{R+x$qZ2?!Q5pCwZ#ytp%*T+n8)Ee`c*b)FrhwzZ&#O0!td zL+FDy>JB7WpQiG=8<6_q*C2ww$W!QcHk#<$&;ZX4FB2UR2bg74Lqc;y!qX)i3E|S} zD2o9upKCo*R_>j6D|OE6cSUY}MUSS*jb$V%dTgy?s8(pQR-z+6o(7yLTFkB9=eM3F!DKB#n1KT-=p71MvPiGFm_Ezye+?AZdzJ^in7yB z`h~X7L4VWQ*l2veV?>aj=0lRe-jNUfur0hTj5RT*eqb-8b`q$GXXPcamdKk=g0zLO zIlo0Z#*bJ_tAlT+b$_XBN*umLGa4n)*f~$155VT6Fg?9mNBGxaPp>RYANfJIQWyt2sS-QksXOy#%d%IGdq@~j;VORfoSc9p_)k+~^@rvb4LM?+tTU~=P z%*$1@gE4|w@VDURr&diGI+i0R{GQA~A#N#d$gXp5nwHq2;}c`Krh5Cz2Dl)3W38h) zj;*;Zt!`u&qIeyBgtN`We)&k~_6H+*jYDB7+tglWC`}~?aOHUgPp-%GJcPbl83QG!tRN%n|Ly&VB{bKuSHS5Z#*~-MWF;vP#qcXcFVAPYEsr^SmTWjW}3P zPOEQceNC)%={F5xSHKgXf=kT5=L*s`n7A0Ap$Z_cy2M5kkZg_sdy8cN^AnXJ;wTeG z*t0ZPe*L6$3=jWRQ~fe7^NZjfLenb>vlnnP4p~)r-+1%7Hkg?DOzHA$Q!f8_yDUom zjxjXd&hv||K?WHwwKMO_a!paEe*b~}q?vu)mNGvF-)!!xm)qD;#n;w{#X^cy_Ij!F z@K^F~8<}QC#YKY%ufED>40LuaL^}u6k2-8%0m&>K5%oG z#J0FPM;7tTY~#nNS5crl<=<`?Fn^`}*)U&Yq!{*fwQCA`p>ak_j)A4rceQJ^I0AGY zgQR+(r*{zRfumjDb4U|0Ceb<1Vl*Q)=?ULkUrLc&L>^yfw6MTFXcgSMmybp>Fs9ej z(+yVr_<_Fn?a`R{!%Nwq`H|UL(bol7z&)8j%B{YkdBl2{hkM46Wo&%g0?B6SGstD` zVCqd(kaoza(j7KCb!6BeiYN60AFZN&(m<-tBD&c&^H&^cb_{IqUm#|LzGe}7yF1qI zYEri3!eJq6ePY=-g5_^@J0Y*+?dr4NuAkWsE_DrANp2Y)qLNE|ADL=w9(0+l+roxMmOPKwIh;K=|*maw3_S z5pevM8XAlleNp_Xk6vfl^oYF+ZBy#HZhL_n636`3c6uSre{Z+;IM_s%yewk`C8J+q=t^Il=<>x&LAZ57=vDOkz6T=b(U;Vhfm-ZESiTO0IY7J#z zy4e)jY}`m2!0Oq9KFAw7By@QeARxN<2{rP7d-a~} z2WvPtO zLNzuH^Oyf^My5COp`-R$A(jxr zoJG{)r+3r!1lzu{X;h?;XuaE9z<3qbUsJzdx!i@BQ1Sg;Yd+PvhZKQ#$p>eizxgp+V44D^G9K2HONx5DvS#^-;GslLYUi#|LxW6;da~>@q-CM> zLk3ot_OHeopoYh~(+TU0x--x%Mxt2YKA`qEhM*oj&~v$mJ&xg#USrmgp88d%}mj{{bXF_lmv#|A6ELBtEMw z6xDyr%?0A5u2!1*c__UEmZ0IzIj&cJA<@(B5mLJUAiVupeMo$@W$Lqrna)}kD?O8mpvt-T%I1NGJM8@Z#xdo(=+hJu4Yk5nHg4UT_7?3--O8M}6nY z$K@P;5TwduaE6ck{}Ym5Y?!!qy8ilt;y%eMZ=1+U8&YDjcjF!eA3W?-_2mxlR8@bM z@vtngogi#pyundyrp#4OaJsA32?sbPS=1J331kxI9(s4C zMFl#1DW|=&^!>pI>G5@3PQvx6uZgD_(gJP?2+^KbP3v<%hhyRFRHnrfuP z0}o^2N_vZli3E9&e z3Fvrrn!Yb^gHb1jqZ_~*>ayC{xIm$Cu(zi*+_OZUH%wv1NAzI*|{_T=l9{(htM<>|7g ziD-w85+|3pC+e`&nM{_c#Mf26`@ENxhx%W90YLi22VC zACchoZ-yHjz+_vsjLUezD}#FlRNLxB!)pw+|ihSf1Uj> zRror*>||*=6;6Yod&mC@D$&x#Zf8W!zP}T7U~^+EF)HxhZBaion5bz=G-yvgo+jfp zW!97R>N{`4`XO#HU2UHGS$;hSg-;1ehACc!Ot+B#VVya2N}X9mjaBEpW~z=0*&^dz zXS+|6kWOLnX@D>|+k2gW#RKxlbICqacvg8C^SrO|1bQ~ilYL3+^x>Um1Ohq~+#-tn z`NVSYZu|r>=uUu+Q7Z|GqkB}E@3u#jA!FfL8qZOfVHNkr@KCSi7Fb#S%%rUv@$ww} z`D$UfXK%eRJ;4;IhPu4T^iQFyd6F6(^{`uD;Sq=o*@JLa^3W$&rF^)mvYa_k;oEb z4EoIq3`VOTz^SZa+v*vD^Ubj1ryY`R{(3tXQp}@Y^gs>cb@J-9Z`)pRa0TknfIh#H zxa!?0QY`^o8Xtd$jyl}z)Yo?8)1=aj$5_0zwnd)Qj0jEyh?dCaS>c{e_FgNIR0^&O z1V+9Fed;;a*8mzW?6Vq+%aCP|mPX7FHb1?hKxOfml3KXadEUsr+kxt*)NGUtZ8`8K zDmW-Cu@*z*WA)jlaEuXhsvL&}-J3**v(~vW%lDrK3R}27{gD-^8)nX0kym3Uun-scvI~Ymf|3gloQpr zYw2jpGMFpTe2BPQ*He02p6dJ~_^pCfQ53yNWC`CHKt8Md4ZL^27xrEW6WD^{OUY z{KJ-?&dpDo76f`!@3Nrtlk}g5?r$7M7wCq3?^)sY&0F@ZUQqN-p7_ncCN5$U!eWd3 zT~^-sg|N=begHS`sShy25)*^$Cov|btCqQkq9`IsgHq`Fwb0q|v-LZ53|D`134K2} z>y-X@Xe%yY41%5Ee(>v16s&iC+9?qqkGd9gF(q{o>Lrsrf9$$WOp_t0wUe8W8Q^mj z4oV3QT16_fNg7IRn%y+ueB8PX-Zsru+>3zLFjJJB)`^y_>`&@N{C<3&9b~I&-Mh0l zi5fS|F}!i25I}5Gy=l=UiEYx~`lTeaUy3nXEyVRVMA1;@Z?rvjNe;9$icr|(d`X_2 z@R@A@6z)=B11|7AbVSQhUWPYc9vVCtCJDpK_QM?W|tNi?XM!4IdJ+W0RA4bV@xK;56Ojkb*g z;0>92Jzr}gA9cxhu-k|xxGx)A2y|<&GK%xndEKTP-8*^f3yW9&`Y z<%=9fWU%Vrxa==8aRJPDO0nLxz&lO>GV>6@8DeE zzQg(uR(A!f3l0l^3?S(LvKA3C>i2Q;EqI6cg2A?eXEgR!G9mvI-}x)7wJ_Zn!3949P&q;F zzMzeKp4g}e36Zd|iR=z2i;@3VHWjbf7+2dEn)st`uZ^q5kkfGEn<1erUPjVKAFdb^ zT1Qi(8AhAT06biI%8nek_e+*_G9^p}7m{{#6$&%NrJhJ~QOl1k{nY63h2&YlqpFX|gc&>|X0ferh0W}bhoW!9&j45R>j?C$%0(YR z8(^>vO_(DpCw41yCcuaYeu`_#VLW3FKz#CZ*8Vz65jiX1;wCe8fjrGjuSA>6(Dv=6 z{Sd$SNMgFxopEr(zlqHDA%>+t+!D2Txh36y=*s_2`ZWAH=KJ-xt<{y+J(6S!s~?S+ zep;4wyyv*rn(>sR9U`qNkG!K#_ zGjMNKhW(hU7Ckpc20xwERa-V*Y*m+?Z} zKcZls*EVO+C#B-!ka*l)LGG?j}q~vxf zK}c2)mMa;j2{HA$X1Q0d6!o$bAr$3A`JXuJcKN+W29nQjwg62SuSpQf#XtAqdhG&&3i^q^@-<*t= z0@s&1%gNc8A7u>LWsjBG{3~=AZ(oKN>~bfLcqNFg4`a^f@ADK=5>RVX*o8$h6ROiF zP}=cLtrYsbvS$fTqnSK1)|v&V;~LHB}}c)YWfb%0s41}ixS987!s{jtB59F$xoS=>r1?7{tqyd=3o zBJM7h1TM%+tJ|(KL!V~)$T$j&MR1L{zDF{|2=%^IvoYZtbu6^Za0Cd*^C!D%sl>I3 z-vpZ73o8+$C?6B@GwM3e@^=aAh3d`8}5 z3+a~~AzQK6L&qNW`e_$$JFVBsjM&6F)2RBz)7b5&)BHNB!lX;m(8bV|lOw z=l^&M2Lh*4b!+9sIH~{LAc}CvgUxBTDbCu|@V=4}=JIEJb zQ7WTf8GSBU;y7}6wN(8Xf@(b+50ndRnKhoz*h(=uL>q4jG$SAbbq9Uck1$r%i?!go zv5OtyH$K73-}g$52Ju8{$8~klB>$|Sp)ye&IB@yBwu|jUy0OzXI`pkSW)(y!i(FY$xO9RiH)_L4r>M2~&K=!+4#QURm9nkL^Qmy@LS-xiCs^v&MIjTB;xvK^ypMQ+k}_##^G8& z#VADH;zt~4bx-;`?^dQ>_CVs+g~Q)L7VU(_9`U@d>BHmv;%O>2ny5dfz_h$&xLt7| z-#mT*JdzDMpu+rH<2k#fs0-3j5ip17#< zCoRUfgWr8&H1PQCfsNkLsONN&Jn=!|@xbOOX#Y}#m;L$Cz~h5Vtx?|NfxN-M>cd_Y zde*#4q}7T3d4rbRndu=qdA%Bcggl=)i zi|n)DH_ti0`F!B^p7<>qez<2P;z3rv*)KODqKai{Vh;?QUbiaSbohVgTk}YGnS1;{ zAmh_Ua$B_T{6EQfhP%v${|6ag_APq-_3Xq5v$ed|&hHSK604Ag$7Q#F4k|ELv2fUI zHoSLR&a`bIL1>_Lpf-+Vd0w$({M@k@k;fay%fX0k| zh|zc<#aY(Eg}V3hQ6eAl7u$LB7bO5yJQ-gXhWU*{V$eHuHF8UeTmz>wFw~1L#>Tf( z*>uI14ixq={LyAAQQE@NyN!q&cQ}6=lM&^>w_nt!ZkVpg|9>+6z%}D_^EDIh>uvV% zenWw%qQ_x;;)>g)E4R+1^h*Xm=H04dc0$h8F#c}7#FO#8U(Ea7PAu;SF-qptIf6&z zGPmTmhAC*)_LwlO(_%kGMyWncSEsJiUFO`b zHk%L*hcPQ=cx6N?{o?5|n;2smybv_VKC z*3-_3)36BISszRzA_}Mjm6|{K#`$g64t+ z(tYaT)yu`tPB?7ShS3vIFJ z#|!i@>4s06ir!zgyG2w^`1evvZj(War?c?vho`z%M6G||CqA#H@pB<7!VxB`t_H)t z6+Ws|mm#1Rl>jpex38?14&~boA`1g=FEs3&T?va7)fi zE7VxE>;c!4V$v>@CE?lOk|rDe!tV=Cko6c}WkJoX-FY6eFu%W^ZM)KAt^`!3?l*cn zf^UkjJcpkQ)ZsD_M3|+&Xf`OP*Di1vvoRk2W4eZOrC+?9bRMHD6e-BauKb2Ur_?>l zX}@`Onu3b0;2;h}=&&H8US+Und&DDOlrfkj!9CuhD_gDfQ5o zOZ`zcAavy0Ps?+?(287l^U11r9IGydANmhYUB66*sclV1x|Xhm>L>XPr+qqTJ=y!X ze}@bEt4) zDSn~cYtn6CIQNPpfgOhlXKkNVb@_Eg>BROC3d1e9uzcbGfAZD{olyx1ZfJpDvjbRl30%Witt*&CPJcBR$0AecjYZ5(}1RklqO!QiE`EVeOx z@i;DwxxI1EGOvlMloQ=s;9InQD`8u~Ym4eSf|sH=8}(UpB)gS5bnhtXirsN8BE3Er zh~S|O3BMYq2_Pl_DKRt_dp2A01q&Sqmp(aQjYGUcW1SQa%m}f55m@V6lU{c_lf~a< zM%Xj`sm;WTGJ!eidzx_Q0(v)SJU`B*A~#{GMDTp%m|*v_rWT*$jma88?WA|^##o%o zpO?-?HrRJ9_}3XCTN5J5E%E9LG|_~u-C3S^6XDvFyGsH21d$Z+{9?~d@>9>gyGsfL zJ;t~SzGJ}iP#w$}fGU+O!)b|JB37$dz0`Y)c?Z0GSV-PjPFL>1(QoJIA*`G+f-R3`?a4_6dd zzJJ1c()}3mir>ug0lF)4#6L_+snuf(;7h%Lq(yS2PPOf{zKij2y7+W!mzyIpT1!^Q zXt=PG-L{uPwXU&9T$U&vR^No8eq|iGmcTdU-N0p0 zk2M<(V|>Hc!Nld(JYZBrY@=T!-XZ2%8WxE=mS@e#wkkL-lqkzI^CWcVrgsD#6R}00 ztdf7z#q6_3s6X^~NM5UAj|hg=T-hrq3p0Q0xNRYQ!h9SQdPS#WEp6!9Zvd0U#T$j@ z+c#BC1-bgf9esixleuWTDE(a4Umsf(u6u=)Gr}NPfRq~>ph3{pMc0m6TZXQ9mjrl* zX;Wo*Z8kVQ*KU0rmXd=-T6u9I3HdSoi-$7(TV}?%sh5=URl}L)l&q|*bSJjjjMy_d z$dg-unzq^x?CZ^Ku^%l+-rM6f#APRE${%jV<=Zv1Y5nlGQ(fX`JiF{SVhBXKMU_NxKbjumdqw1Smxvfud`EiVLJb zXx{^tRp=|T}l%aZqoKT;ln2bzi1smpW}U zxVI*S{@m_Lk^FX0yIvO%>}3BO{XN6>w;uR=^HK64c@AOaQSyXeWRZqQfb|`-x7y)K zip5sz$G=(4P`HaezUXY?HTmZ#8takQ9^%oZrba2?C_d5Cb#5Nlet?Kp)`B;tf=Z(QwX#%!O14-3ycSJn+Z}1GDO;wu7{V_;}S&a7iNz ziwOecL->e5acJDz4>Z=4EWc3jHkdzD&WpA4`$w8zB@v# z6E7`np}+K7gZ8i^yx?qQP)ufhX7K*>? z6pFu;z%T6Z&KHJ>jRyFREPjrV!}%!sn`Eyg?WLsQcGt9Z zT^CzA0Kf13%h)d;wlndvtKE$GA+>KXr%4rQE?Y;q%u0Tqm{dJ8N`XZHh~BHgpV58W zj|cGje*UIoi0<%cyKAE*m1_{&w20$zdIeosyfcQdFt{(cTj9M+o0$74^-bYkVa{10 zEkIOZXy;nVb_AK-!TX9V;a4`^%lAufiG)m}`hHZ7eTy&;Wn*$`S?D9w%yIC!kTbd3%!4<`*vB+JA^xbTB=FPi zUBSdyjc$;tY3YdcOIzuYCA-hEvKaJ=%}2C=Wbc9?R!6?ioj{}fgIP(pGV0zs2R*t2 z?w{)_Z#|36UKQ(@44*#(>s3jc=T_WxT>{UMKv$ORN)?@fs|h_nOUHyzm+KOdZjMJ5 zRuIsf=h1K{zA_ZepQ!k|72^n7tNh4Pg1gtoTZC0W>Yc~eF1K??;W!1YwFgXkY@2CC zpUZP%fOHkph2eYGTU^OfnJ9_GB38!By{{z&@fLSok3d_=uKFn!)7t}r78zN?0vXxf zik>4*YT7EFuxlx5S_iy3rX|CzsU#|D+5jjP@_=CH9)`7AEHiDmL(pI;90ETefKSs| zRnO1`wRk7UpwJ`|@CupX7l8OMCGW7)3A)oXnPI~cnJodM=(#IJ-$A-zd}?tPp zQM%!Qb#a^iH*$?<)Z!?0-vffZr7Z%nwew3f#Jkn}-}X(1za=oSk2o+@TUh*i8ARu! zhiqM8GaM0Bnap=3)zpvctWoy|S=2i|heP^fh6|Ey7JTs%I4wrqrB8AD)&`@lfY?LK zHkv}>w|gDp+j-4Z0NwrB&2e(R9gZbn%j1xN(zQX0k@r@>zSR1om%=O^SZlK-u)D=* zMINlg(<1NSQ@yAR)6T-Up|0=$!u`+eU(?=NgilVFKZJrDo*QtX))^;iGWJ2rAVr!S5%(S6o+k|H{>}=&~m_y3a@{ z$Qr5>C2Dnl@F{`@til`}?p;oOeR4xTC0meP(kmH4J9>DLq1S(D`q%Eo@3KWBfp>p5 zk)d9J_rXnI6f3z=%va^}^ya@m(mV53W!&>|vVU-`NH$|Lf2r%JNo z=;-biZ0n~4ffU5-JyR+}I;a#X>na_Ey$fSfn7bK#Ak0~KAatg*{KR@LwXe5Z$d4uX z9c%MhZf5OGGfC##%uB%wVOS#9_^2&IEJ<%9O#%8B0jt&s>TbANE9p(cdi44??6KM# z4j_wHmxc>u?s9|wI2|rTS&EAZ+2poaR5{y_iXCS?*gMo05@oezj?Vc_b_(a_%gHMK} zV}YW6Kud{v+6by1Nmer7vIv9OSHJ}uNQLJfR*I z@m@2ojy@g8#ck&cI*aXfwzWS6DYrJMv}%@bHMMwLTF07}Xk_~_lTt=O-jICvb7HT~ z$>WV17M!dEnFToHrun>dDtkMK%Em5ptazNDjzLlsfGl2_AdnwxfZw{sJITfNSM!Aoxmk$fsR(U(>%fH_1?j?IIeIeT^o!A zaHj`d=6Jf!n zcUW<#+3hrVVp&^h@7Br(wNwgQav`be? zxcGc;*FxW@$9jZCG3n1InM*aY`6g3kJwV^UU@m%2tT3iSMe0Ih7{=I`(rc>v`KY-% z2gg4JdZwzOUXf5}B~qf9+w{zlpO%BsosdHCNFQjBo%jdl9^hHoe-&TIn7Nm(Zi@LL z`d3NZAhiKfcxKBp#^Y#@1Jq;%cn9*Z23)QVF7iQbbxu7Rk9_APO2Wao&a;MU2!Gi7MGe)}cX@iwyvN@`td3*WM@|`^Og46LnPq#~ zZ6x4VafeZ6iZ~!beFrSN%USfK=!A&bRWTGf}n|PlQ^CoXXMe$vMf;I&Tsl{} z&9XAqR4=6;{te#$1+w>dd?Sc@SK8P3qI`r~w%9G+`0a&+z|&N`RWx$7l1`bnx)6hK zfxls#)~@p#{t(eMXb@(&*xc!gS`}nt!@A~zY>g(cOX=Ya;QV~x?Vy&{->vM>C>dI~ zOlKF({A$uD*-$m6xFh!w09mkR&CE3C6kk#F#G``Y> zLt_^r#44HQ`Sqo{A9qX9?n5E)1mLr)N2y+2)f1H0%%GtbKtAtt&qvnt+QFy{v0#YF z)ph#3{NagKzO`%3&rqomPZ+3yB<7A;V3|d48flTV*lr|RO`#*mee2?;S3WRb4MTIz z?SSl`tTN``tK9u2RiCC=-X>d&scyu`2{ZofZ198a44kxT>ZX>R@l+hWYAdM zSMI)+X2^}Fbdt@11#I1{QxaQ!GG(6~qsA7g)j4MDCHMxxa=~gbzFKbdP3H_^DvISG zvqFYZ?Z`+4v$a_?e09gWVj&a=xV`7ppz5=UoeWuf_*{6^MDp1E#*3=iu{?#DJNe4S zNrW2NEs6EYPCR6VLKrfym4^mn`ttcYyv8Gcb0N?m>!@o0^psj7R2(+Qn}=^WwbLak zG9<1K!{lAaH~4$6lh>7gWt;w!{0za+_z;as<&HhpJNMB%Il1A2Vg5ZVKGT{2*}Ph? zMT&C|iu)GclBPdA2hj;UY|yyU>N=v;`y5$)oAMVy<*Qpq6(BWVO55v`rvrIUHg0$5 zxhpqjH%~nu=^cG#5K|2R=3r}EO2p&>Wc=~$eiB#;BPfN;Re}8aX5`YOUnolo?xtMtS!5 z@OzNiQ9Xws_uFkKDX0F~V>xTvSo>6L(430jLbNqxJvpOk)(6zkTn2Yq$FXU1EO^pg z1v@eeVqo3+dQY_jmI!t>0YGI@u z+s38e(`O&lX@B=-*GPOmL}lJa>PeHKIQCM0W4^+c>DvSShPQ;2o{+Ab?E%=EPnmpo zs*i0wC&l=T=|4vW4)qOQYP7fTW)@8E$~J`Eiu$Q!c(9-^R8r7{d*NZL=QYLmNT>_U z0mBPgWI#_1Eg;JGIgJ;(_f;!Wmk{9iYQFdx$Kil~W9Sj^&3dVGVJF|YOk?e8(;z57 z38HXOeZ7R$Fb}XIxL2<6eNIw&PE_o~^7g$>_biZbXP|`D=!EuxnB|aIbCEYE;-Lc| z38tmhi}`MLOO7j@#yed?Hko!z8lNgA(eQlnUjI={w3XT!7NmR}ka-aX#ll(ML34HU zgjcp}8|^-KK%1L7@Ok4=m0NoB18BVEI2mf_)k(9B>dmCc6 zcyj)mll-NF-?zWnVOg~^rroOR)z>MLw1#D{9c)73G3s7UyUS-;W11Xb*Dz?;2KJr( zjBxv+Yho1vXT)%X4c?*!UJsa3e-Anc>qzJg@KV$=rSEwXt57|F71z)CUG4rIx6F$y zRZ~tXPgsceX0zjUm9Kvjo2%-OQ7^#Ax$R)Zt!45ci1c8~gwxT^ax>s$`r_*t0de$A zom4vMYs5ItJp`B=Mg>0NzqC6&H?8gad|GqHFIy8zJ%HyMa7qT=7{uel5bWv2TLnSA0eH9rLk7vkYfNR%2y9U#`dR@S|2qUAy1%8%*(L1gRw7I#0$ z1Fc77`5m@c9CnC#cUGK<=v$(a4byiA1ub&uFU7KBMAuj5c7*i{;SGEnb6c(uYsLi3 z_|-Y(u9AuUZQ=Z#G3yQ%&|UOI_J#d;Ka)jIAR1?+%-4#2sqy?!B&Qrc|HXKetzwW=ds{nF%N4iRPKWDmlZY+5Ku|>-da`m_j zLcBV*&|Df$3(VzSTs{oWp5B=C2y#ani#?PJ;l~Z>@=zX&Ep`rtIC2R4czkF2MXnJ> z{2NZykth5XUqUkMvwC?f!hU2>fDdE&E#ubM%Ax#`^c%zO?8XXtT~`^AEWinJckk znYhEW$-hlAy=(ed81vi4#?+6WS|xDHXyD`j z{k*H3k{UwGRk#z2!H4dbD?4D^F`L-{nr`Yq^2)*HinZls!j;}y{OP+9 zm8R-|O4gL@M-;7hvAue^qKK)qLQsJ{dphOs$DhH2wd#Br%1(t&6{Ft`Clg&Z-+7?u z<*gqP2jA5{fxP);M-vtT>g$Om#k3$8SN7{ANm+&yfX3{;)GS~;cx~dRY~H_NSSvrk zW!1RRwhvn2i#n`~S>?zGod-F&m)j2ooB?d`nb)7E|$|lfmQ_@t8 zdE7g>0=p9tij|nd&#;&&H#U)7;v2rmecHu$N)zj!Xq;zP!%BEc7fUfE2{1JxI|XWy zO#E4OZOr-WM49iLd_nV+t?aGP^MT7S8vc7A@l|R_e7|4xo9*il0w}JB^hCJ{ZAX8;hO5mwy8Pcq1 zY_)|nd(N%{>Rx=DIW>9fi4$3_gS=nxDttwST8+m(DBlfe;~n2Qxi}kJ{btX#;MwIf z^&XD7Amb$paXdx3u|>cBU4FBfIKubjRZ)#|J|?Mjbx-r+2Dcekh!-_Bpb-mm2haS{ z^8Q4IaXYOsK^(H&Y^xhQqwaiWAwmpVgZ^?B38NCwrr#&?a;?(tRK`1XY1NxNbKy$+ z1=djAtoW8DnJ}ytIk>8oglLZ?%xKymJ|ZesiWg}O;8~MDv&FfrP1v!IQ#u2}|Ev;M zV>EL=|9B_Ex@Ie=(V~Y5xbNt=uhson!Xy+o#p=to7Wn%(Tx)g;e7^EKvr#l)gCjAG~Ar&>Avz!5*Mrjr_7x_Oqy^Thw5 zxVt(xi`2m!dJ39djWRW75K=f+QQ+#mBI4OL{3m3MIgCf+sPi2m+;ID8kta4W(-Epr z8{);(>1&(Ko;6Q5wkT_0_aE37ySo%wr$56oiHWd;sX$FU_;?^nP^4jFm}sWBqei4< z=hfSH^&(H)PIjYCLibNXS573UyG06hXeN+9X6QNjRiJ(CDVYP!=suiBOC}4Z_K+*W z+yusV{7R?ua{;Q6W|~t6I2uHuHyn_)a8^oD$}LQKpXL^iBGQ|u6Ka%41c5O$@d=Mo zA08duB&?47bhXCZdR22+)(_n>a%=RI##Kr?`MibojDo%zJxLG~_#p9drFR9lOUZHT zC-GaYN1VUXj>g0$?3l6_VG=2R-yDO~G#kj1ryec*vE)IIM2iuOdNh+wSIO@0lHA|% zo`jXVha6$a!+GZUEva+=3BHc#G2N=?_L1O*`Xp(7}3RxK$H~h5TZgXJ=|eX{klR1n2ap z-CWKJCnKZDY9bZ?@~(iPzlVh(qZ73|;moC4xe6A+*KCX1*vZsvYj=fdX(=ELn0^tK zNYVO$Uwei1Lwxw1Qt1>n2@=#Pp|)naV@Z{|LLF`UeF?6ukJH{Xw4=M+C_LDD=6q-e zm}>k`s6$j&^I^EwHiUR7%+pFCd7OV)6x41T^192h8v9_e-?b7OPfA`zl=KJp_VgF*7sue6tnVC(bwS1M>4`w8v zuz&R`XlPHO)jXQxl9o}2l}(5Bo0pSs7k*WFZ%62?wV2N2*#z{d-dxiJ z`x0!sX8u6?_et7n@~AypJ5Lec0&Vuhg$zv0!Y=OTyx#jcbl6Rdsohk}jDg_OZ&!Ef zqQFL?$WuFGL%h+eyP8rEsBPDyLsvUSYi*WxK>ri($;wJnZm}B2kIzJq;fz@(xneb! zNYFR2#z0p^YN%8Zd{AarM@UTh15u%`udehZ#{|9&(~!WTTAri2%R6yu4i^(8HwU9h zKY^_EV@_BUO9uSR*IkZwv+g5tU}ns48CuhT(O2m&y3$|PIDXgCNc@te>)m4~Cm{9% zm^)V$J{O81yaQbfAGMN}$4m*-(lC*~-6j6g5rgjYaCW-?IcJ<$t3S$s4YG!~d}1bX zXDyWPWu*QbX?yX611?syxgzvrBHyKx(orwV;#+d_x`1&1 z&rn#k!>v!(0?WbUmLCrHZs4jPvp11u#&z@ruiQb_GW2s?rsD;}6oPY0&mTI~$IE#g z9$0w;56g8_itXeNWY5Y`g9Utiw%|- z{CRiZRds2XDi0Fl>F?Qb@+aq8tfw#q#7AHgrntL$IAA&EaNj|M2qEC+!JT*wLQm4d zEh`3E38J!=+VC1q&MyUes`^GxoZ9g|R`;C>)OFz1op|lL7aBw)FI}7psCZMEED=0O zU5GjrsOiA#Afyr;qC}M_m#;K`6HRA2*fbqn6Yq-WI&dccdBA1(y?l#t#<}9hlOW#X z*T!96bVDtaIXW$jU0b;q_x&?bDJ4P$rq1%Q9YtM3LNAgy8q~rsIa<{|Ksg*s#>Ymh zhAnU-6YIu?-i{85jZi)-*kFGpZwz?qC%HFC7IaWo;~*^ib?NLi<5g5L9Q)iP@ArmC z?U{(w?+T?KjX2-cHyK)w)Cx)Dz4L_Hl~h)AX$AdP4VcT6e!!wfk^N_|^4s_F$o}uO zN`@=9`+ENG1pRmPPIyKUQ3{px{u$v_Bs1h)Y|bEmllkd^(|A=q|Rn z#KYzx{TbcDUE2`T+`aJ6uKjU*hvK4T?sbb4H1towe)fDfjJDpOS(Hq#cxS%@Z}eoi zBF^$SzCsZ(E+py+5n&W|DTdM z&%Fvz5n^Z%z5%-Wx= z$JYjd99|b-dwA|jBwq5tMs=)~_EhzeFI7g@n8n7Gj&pt5LswhwZlR*tagT*C6uG$e z$|5g#!qTFm?X14d`{Sghy~T~zkQ>{P(!&kf$;0HA?nhQ`5&6|EaYwh;c|*eO`kt5SEH8`=S@+BJ90G;A>b>spJs-uNhk0} zp)`;aZj0a2CV~UWT)951D~~$1ng-Z*UgQh(LfirtnjsiBz8LDD*PU;6HDb+0rmwL7 zc~8y&aFs{QmVC=IynTPfIl3xW+xl%t+tv7I8vWEsd_`Oa#RS2TfYHIdEPJP2Xg~E7 zkGry=jD`F7n?+wMO@7j)kM^&F>8Z7je%s z4XZ`{WK5y9Ll(p7EVebJWrb*9(vaD=e3HYcQScI!lun${0xV7^PXuGXHSV`oW5?O{4g-4%o+Z#47(Zd^!=cBcRvxRpv zX|`s{NUkqRn|dD@@iaxM2Fi`qbvY_3M>kaKs||kFVMBuD#87OZY~a@w?H0!CW~S>iLJ~ zCF1p_lO=`Th6y6w#je*@-X(L_iTg`0Gp0*Oh1M&-i6R8+yH?}9^6d2~BWDm+vMk?N~&-*D2tyyR6Cr#ZB|0QJVg8<(sR z#OLqw(^Z=QZn?u~$Gx^@_+P~36l|RfJ&PL8H{|-s>U)cb;^_YC|C+bVJ^O%}xBE{U z1fj{m$^k^111*xVffj|%^rn}4CB~DM1Bud1{a)ZN{S4YpJ4ge3;OQ}zKoW-Myq$Vo zYUV&y{oN&msk4y%ZZ^ujYX8+#?1vCxl^dZm61z_du;!+6w_-?TN2k1h?nu9XsmG@1 zCjtBriQ0U~pGonG#q_2>^fwimXBwvA-Bv;YgBwX{&)2RyH(fWiNZQHl!nj0%j}dE>7MuR6Ayu3P7E*D{buLL5hgasJwFR3GDXAP`MP?=Rkb z;;?+0ayf36IfbD0$ydqjtA16FO+$R=l^FQ&RCM|)@jhiKR4>FED}Jau8oj-p5-ZhO zA0UF0>zofx>dWf`V(%zLWeZqy5|KO%J73fBKU_n%0g%5m&eyKjf^v5mg-0wa)@6kBALL!$niKm1HDzuA!6TizWISnZ%#dxAHe4s*OIVE?)P`i?0`O}y8iGtrKLiPr3aEB^=)p)Zhx z`d|TyL+n+t;CUWp|4qYUo@uMen%E*$iqc*t+mD->&$4{I-}TT+%5~jJo8QudaozRF zP)YR9$uDqOJw!nWP0ecxnCD!7!b_l@=l-Wy{4W>Qg&ucDJHMb}*8Q7(&*>2<*1Kw* zbCqtfqFg$FSk^%r!Ox;prbifCQisTxMQ+uiE~U(Ztx|7UHi3+3)YFkX3&`+w>LW$q4dV9c z^Ept)(>ea}s~nwG{75oCtJjH3#I|;p`tz8lT z218#2T7fT4!3CYyp(z&IhHK|X4~S3rkzH#_c^ku5!}^b|>}-mUf>QT@3^KAD8S{ci zY`aNZVT(Y5sC)W$pc+V+K&i3Q%$vmRE}GZq7^+DgH+M}sMwpL0o{gM7ko7^X-%f zey|`vSh98F`TjbHYRo@(!vEC!A6mW0lyly0m)f34q7zMRixTyLh|ZqK73F#a+$qm( z9n=DO)~eJ*HocCSKHiFt>NtELawD|PfN;u-_I6(P{JGAcFdp4tVi=kDhysK#yW}A# z*Fh-Rga3>vuQz&nz2p@Ng)f?lY?<)iLz$j#i-7;zI>d$Wj@MbotQpaIBtrxzBYD_A z{)$t%aYmI@`fqRv0^k45v-b?GT#~`Veh8;K0|6%ZU=)ac*>zb^>U89pFGW^#iCK5(a&&2$DZUUX zT#N}WL<-ue@l0Hf{+2CoHqh#&lRaj-Oh*F0cKwc;kEosh)3+AImha8=B=gPvAq>}F zHubFmndno(6$yRc|D~?2VZb+4(p{FE`XSta0_1<6`VQHviEwi;NZwoAFvh1Eq^_%B z$iwkUvbH|R|*&Ym_lVel1o zfZrw*!UEVD*(Z4R!tXPdGER^JwK(M5KzbAX^*#Z1`Roi=$+(9H?U0N9_9b8&vb7ZF12>?&lJ*&iz^;w*AWnPVoV|9=K z_XuLT-6jDEqPET(ysdk?_nzc(o@ohV^noF*dn)rgw=8s<5;q3Ym&@%jg{@oKC1Kg?qUw7tm}2%!>tieTa=J9B<-*0U?GI^N9wZ8fZ${K zjA`QL9(me6n6vmJ`TGcRIa1_~*>qB}ct(`}cg@pip#u@R44@@3q;u+!iSkf~l8hU& znEw^IAnwQI@3WMwfT6#{r)&vLeONzwXqx-Jtl}jBOB!nXo>)dWd!!RJ^yT;Ch1vinCGGo2NdBMa7}d8chb=&))YT}cYYWwO`QwkcR(BmGG>0fo4z<+ z$J`AA<(4656gx&;29x)fVi{fFq?UpF{K)9EH6xxIcWkMly(Os^I0~^@@4H!8_m=KA z$++nIirZ-N3ib~+TEP*KbNAU`PnR|twHD5{ydj=8noGRnfS+`oA>g50IRta}5>{(A zt0F>BZexlQ6n}cxcG%(@8()b$+qAvn+Q3ga3V3lcdlY~=LwrLCwD`R6M^F*+*RGpr z@=3sDhMQ=s3_?;7;o1hoJ`Q*<8v4a$13*=dWYKNi$kV1(#R^zzzjp5Nm0V`$u=AXWOErh@ET5)%Dca z%~bt0Ym~2?Yy8=+C=tSBKZxDiG`H+=LZFs)M<20E8KjR0{hyKirYGvoBW?vVsBS3b z1-=e~EZu)8${6}8NqMY&L{sBGNelq7vkHKInIqiTStr5XE*?tcjnCBO4Zg=)dMGtT zd9&ZuFM&tCjmzgEe}siSMuHK;_tN7Vj(b;KMDxhPNzc#GH&rXn2#Q*L2y;8|&=)2G zD!h960hTDS=9T-BkB0VI#A56FH!oztMgJG1>Q%yX?OUnjC^3`ca!J zf?NfFBS(J9GdUx?wBM_sa-(rGH_Pg}0yI7(IjHdajiYYH90-@Y2$l+tm1BDm6cv0C zvm?JtZ?~>X!MOA>=#E=g()`Wa8G*bU$6PAUp&4lqbNlY0wLo6849L})MG+(@oTG$3 zb?Em5B`Yco+D)C5$(01r`MQaK-9$>DIr)>Ax{1~~fDwgU?|io|EAak}2K?BsXZGeD zWg^Ye&AS3<5rWyA|KRmx@Z3%Iq-Tf#O^_iDBd$;CBqk!;(TdnzgpY~`>MAZUSmecG zrPbYD{V8*9`{0vG2Lk}d_dOswi8aUXW^N=+06sRHw*Irg!bFMEy)Tt@!a%zGJ4qlm zh_PW(BzZV7deR@-38N})im2n1+#&Fub}fmeAGDm7>~g%-=`|m3Gff>cZTUvhitEpt_Dfj*!+-ml3RH#Z zIMe$D;-!3Mk>p7mVQ|h^?=wg4%Kq0oW>4Q@-wJd}#$qbP0`1Bg>k!r-{HG0NEU9c1 zVW}zs(jNruayYn>d;jAtit-lyAMXz;z2?KC{9}LF^)Y_xlc2n%d|Pn&SX}izZ1fMv zS)iX#9BX)}WYXHDpoyr5i}&^~#wq&#?FTYbQsChZMPS{vbOwk$L6e%uFte{tCB|`2 z03er&e4V*o{cA#gXwQ~%pNM zyB>xIzm&vv4Ba;1T`k`|6(@4kkW5p50j^1O5c7-8D%Z?~4oUZKcU zr|D$zs3DxrOtkzfz|lrN0u6b^%sQOVM!tM#F{9>QZv}9`$aXkztDi#||6nc1A~=bo zh+lW6(+k?gI-8rwr?RF0wm!eh*Y4;+GFQAf5sr~nt0bO^{@#BH!;%FvvTp@@``a+% z-wgk>cduM`q#~R&ho7S5{p5^HTWsgyb9H`;XUP!8nY%mw6FpdtGIH9MCUqCr!uc)J zWRIG2>cLYvV9GXbn-J=>k}%GU-SJU$w5aWRbUx<2r`t*c>5!jdk)#@=WfjIe#D$kq0*Z%^1Vnaq^JhqvM~f@Ov9i z65;3R|x`c?a zEg}4bd&@~zx~Ak_vz5GVtH}o1;k_wF1oB~Q3q*(5KDT!fxAviHLj_-r0B3O;-P)z0mo z`J%Ap6Nf&Dx&Fb?e5tDhp3}cm3P)Nkzmdacifcynb7y@I34IKqTqkl&3YMhwLth~p z5Qokl$JKilNqK*O-)&XQSm7?mka@{~xjqo5Pmg-E1-D2aLyB4A3wXCqLh;p&8B0?5 zSe@s-{=tqIWm?Xww1n)j;qbBa9S%j^XVNaBX|?atglQQfcQ~e;bpFvx|F7OR(6jHK z@qa6@+?%$d)vrA9Lo~{InoR8%jEm3St?psg zcs(ed@Utm)2aoOfS0=mH(}o7)HPoC^&ehecWbbdY*>2Zy4U25sm~dHlR$kBB_iXTN zDN;DKztpy(>)#lFdsd|ZdCq>q%Tx}trrqD@wC~u^mBbvzCYCQyD&Dy^R#-Mt&_rl( zYudzyJvDTDboQtW5H-{!weV+gx(1xov#2A@8r!rpJ$jv-4Sr}>?F*C>?bxaq$hRsY z%nCg9Zyv;=em>AN=97Nx=sj->{e@di`YWDFyKxEFqb1mXrae;leYrK9#yu;?_QJW_ zPPbhh={rkOHG1r0FJjbz*Vk_AtZ87poQi$GYP)Obr3gdTR*bs)=J-_w4v}~0iNWr# zgqsYlR}}*&aHmKf4`*!|>n=)FTMAq;P&pnu2)R@I8dSm$QEa`qo!Q>%3z~`Dq^yM5 zU1_4Cp&1>vwqF7EPJce&Ai@`=EqMnh7hH=D+&s#k1-qR^yPJRfkn=q;TAR@z_E2!1ZyNNQrfPnCb-};KH zM|?-LJ?MaCLyaJvFjl zvEWj6LG0NsiH?81v;s!e`oW^T1LUWMYCqbge61I&8$Xnf;dblU`eD*!R1q4zbg=z- zcuvz%ll>fq% zhJu1XL=#V0Ug4Juo9fwBh->3VOI~jJ)#*)hw$mM(Wy8I;Y|K_dPCaS_p~0jRUW~h< zI+m^~+lTkZJK*M5>jsAm&kgR8e~7Vp2fave9ob=8Ni7oF4fQ0FRGzqgKSzY#e`aZU z@?{9$XdQ>n(L*#!(Q~zuYYyatC20K+Ai_Yqt>5tE9h%YqBJQt(;)=R>(Kon5fZ*-~ zch>+R2^t9Q9<*_Xh5!MAh2Yw_1b0ZFfdGxWYXgnDThnm(zFl?d+zGw?*GgcE&A*!Lw4^#niL>@HuU60ENnxjfXY ztzs&&osy;VB3)Ga?xByIRls^@n%DE+bYkhwiLc3hTZ}8MdQbr^!S63uwhi+|#t8}U~P2S>{Bu>Q}nCNunVv(J8~ z_PwR@xQ@Sh{O~J)?-wiL1YPCjj89uspD+rCEhdJyvW3R$Fe0YV@=GtN16(l;(H$RX z-yusE&B-W+&~dk@hyKeNID-hZy9MRSZKxIb62Dy=(LU!Mx!3Kle9h<^lO>hNx4kT| z=sl6~wOR)gEfdCKTUMX#-Kkbh;*DgwgaDNJ;7Q7_@q$r*C~ZipG}-A^i&EP!IY%Me zS`apFo`uiu*3|(+i3T?JH9b|;-A3R0{0@D+0?%Pp^0`1 zEC~gq=06V~49RpBW{tnznsp5SvSBfOAJQ{ITYQEidUq`p%oO1i2E~5Kw*BjV+=p-b zSE)^R-4+ROXwr6LiP2!v%0fl9teH*WU>1&`K?L}08NS2`w3~eHWg0n89|l`8!CfvV zMbex%s$Y5u2Wl}CGR~|ZZq2H({osx2gj%bmM|Oz-=N5{S=KJM!^*63|gT1asFJ_dg z({j~SZo#sMF}7&Eq6n>XtK)RNYsPSUlUTPc$0;q0xPu~=_24<+N8)%Gm2+;z2bejNrY0~ zr}xb)1Z%Y?;sP{b%EL)yjD1-j&QoRPUDH>^&8@8%$s;w%7s*TN`BiOTTZ_lxI4t81 zZR7&Qtb(uNxSTydi%`7b|Ck(%^`%%#^}R<)uPMu0NmU8eClbDop7Fc|o}y7&Moy0% z%?o$3<}nfF+#=1+b#5<712= zt+~#q6>LWCmV<`oT$UE(GOKAV$xmc7Gc0kcSOO*j-PFT;{o)BkBgeBWuo2qKdjrO? zNd^-wD>slDDRNIVn$gd5=aQglFk#->=c^Z5-o$s1B-)N#M#*5|UIa)BWu4r`=t$K( z+AapGg^AKSwmUh!jSS3kJ6YaZYO&{I;~pWTl|ERG^?;VNoHr?M<-JJtmTe}w=e^ln zI5+gi&=I)pBNHLlgD5fX;ic}Y-!hWVC6|CFlE^fA{kLw@9XLkW7{-`#wEvRa(zDriIc564wN7szy%of-3@%UHQ zRx~^`JkLa}ik}XrTep4yO_A^e^1R^gJJX9>sZ$^MZj!Tq&q>`5Sl}P8ZvOL`e4v1S!)!m>d!qvVF^q z9mkSarUq5*31*rP$NXEKwpfIrg)@uZIfy;GI=aE$U}lDpO_EmUYug#1cz%l@Qlsgh zZ_N3Jlf9D9MPAciX}15^$H!rlw5@Owwdpyuk;xJ3`6Tuc?Zb1rrQR&%a)_g%TLpOP zejOb5lPu51Rasta65a1W)j;m+pw$jQlJ9LeQbSG`lld2}g_1tj&&_2VLs8twaFsFg zp1}K}qnv^LOF#(Bw29W~B<}YlFeczSQ|dH3h@ zd>wQHQQHDSGa@!2X~>FQH>WG!7eRQ~OMJW2$y_<72Fd@DwvSHh|L z{0+_#;(0q~LmR74s_|U57W3m+?k`Q_w0ij{wp~LGH_A~$$1gc zhPHks>p5X0XwPV6*QmAV%T?AFo$sDqt_K7hFk2iI;g!o>u5ir_zFYCdKaNuSjzB`< z-=Ao2%?d70z|oSc(K=zNY>RHry^>C-j# zJ2Bmnk#l3lZ}D;GbQ(%FIS(GU4_?#cG5wa@?ots(zEj@&=U&QO_P12+CB2)Y9&ysl z9~mIu;v-gQ)9_Fk7&7@9l3eF$^Uc63?ErX%yn*sFZ~(cE)R^`=jO zpNwIm?lvP~H?f_7Z#t;Kd%c9Fby?lO*eZU10&=yJ{iZLLLZ{K1wFFUk`a$>(&ofmQHQ8xxL-z=Z$Y;GlI=ZOyw=N?3b z^YHMDZ~xj>uWwBsEqv{tNj7b)n&8U6G}zr}k8#|r9SrHZ3+9&f3WkKB5MyLKuL+Sl zhUpCx6kVpXidd~*nb`?Gaqe|K&|-8OCTfLQ$Uo~mLLy!*K~R$M{rPy9j9x63ZyPsl z-;TI6xFoJtu_x}1<&K3AhLzqN9%H&6hcasRKC9n&UkYz$9~p@373H|AqnDe_|2x{@ zLI%ZbL!O)Z2HTU9+F;iGgU>yQnT%*#wJCzRzK#o$eJs(!+ zL&+xdtJwAt5{(YNwwx(Ar_9DP-smdHlE!q#lkJJ}!}I@ZCN_U^NE!5h;L}h1KYV&# zb{;JUD$M_#Pp<~5LHyUJkNH3L>5pD~dg=e$r@wyj=|TAa3!mQPfA7;f0+w5w|7V{b zIdRhUm9{&%GCB2D2)Th8jd-0_Lk6 z^c{=kGR@oh6b1>+h17mUSE|pp%3#9Cf1mj|F-wJrcCCHx4WVnoibAepHm)k^aTgj- zT~Vm+>DlzseBFEydO~&ba*t2es!T)UYK%vTRDY**KG1|WTRbERzK+cc#irm63>|i3 zQ9ybBhQ#7?d?D0k1RFuSa}bdJ@KCF%$_P1D{Qgh)c!8$vK(1ioi}$@L_3?*a976Oz zMnL%qE87)Q#-s_syy!)kjQvYob$)Zzbo^1M} zL%$4Lz`PT58HL-+lm8`BIZgq%RfMnu@6+8=_Z_{M*LOoeuK8bjG-6th3^b zMw`$Q5isdLZhy_L-noXi-_fqc7xPX6L~9+{mRh#$XFYJ6P&O`e_jKw;v5_n z1Hy4;M@kcYK~~KV+Qn%j;j0;ERB#K%CIu4y0}fVI{Qd=f)T!F$Rt$if#?yKLZ6oUn zJL%zaj?GyEm~5RwR8=h3?1?JdhKxIdPd!SDC&le6B(Bd(z~%KODY7ZeIxJ}U+vBWdKvw)xA6k+ z2|c`!0(Bey(A`SS8*A?*qL``uaBAS{$6!QZ&iT2TQ44fQwX-QP^|P8i>SIz=s$)M| zOkzV&T7tMTNmy1sCnY-vuV&e zSSl$y3N6^#yk#?(QE!lX_$Q@0z6Kb`Jj_UqC4}?i_IG@QrV{^R#wOMq+E^G`CjpZy zS0w~=bYVUgBw@>PyLq8ss;fNnFnK%2Y=YR;`l_mINsJ;cIY`#?F`ss*z<|JMtFPcG z@Y}av!vpz|jXp)1*X--#ZWzpGV-?vbV{w;!h`nk{y{pH7r=DQ;DwHF>5Je-a#eLpC zOl~aSu~aYc;O7U-k9)f9FB|WMa8T5ju{U)MEq#?#R6Qy(=6Ls$C`?O%Z#18fd>OCg z>21(1O)wys_O0$k`}yc|N&mztjxNPAk zoEbKI7gmXGREcl2ZJhH}`9i-YV>Dv_{M!}3bI5dVP6+hn^jT8or<PL#0H6 z3b0BXv`8)9-QV@43+4;#?2X?|5tF!CGa3$HUMd|O8ItCdePaGL+zE|72bmesWJiw! zjS)>g>^tK!88)kDy#@uZ+fA@S3xcai)rT{8#WpMP zWWkEw{WMd@)6D4~jfKZIxMF(CSMgzDN9y}APxhE`VUlh8JMB9-$HblXM_=6d-_5rQ zeGleW?YqNwdSj+FDR9$;J~ajIQCxhZ6tcVjVOf3fuOZIYHN1#6ebJ=W+YMWbo=+u; z3<6z>$+wl`DXW5d%>sJfg7d9WEFln5Vr$x9M4&zRkZWu|VEVfhJt1QiL8q1L?R+P$iR(U_X!1gY^qNBR+)$@5s`V^eJgCs&9Rw4id{Zl$5b>96vk{AEN|IJsmZDAU0Iz@e z^h$fP&!;AcQQEb0SmDs`O|y)i_qefvS2d0iI!-hzE0GzmEFJh#a_7<5?=)1k`z{LW zyj~r-%JsEFml?5=R-FpPXj9cFsPk`ZKjuV588gG(lT5Eb9Q#Su1|X(x{g>}+hrs1( z-V68OtiIYxnd)zC2l}BOB2eo_zXjN+27N=~Qp5bMp)SN~8T^Via)Q}9dM5Kd%mnt~ za#VR4>#?gc4$$gDmGBBo_Xg@}C!9Lz`&l}xFCtk@?i?$(hwbN)YS`Ew9n);x1&vI(6aj1O%lN4`3fNms z!@f#5+saMMv}f{z>aa(EnPC(8RC7VNRpb|r;3R-?t_O{}r>R|Z*0Whc$2(~V7r-xp zwwLp$*I?4rFkvxgjZqY^1w={L(pKHyuS~T| zNq6rSAZ+UQIzhj}PXNaWj3TBVKg`{F^g>CjbEUlT%@VQwK5MeaJIv!}+g`c+y_(v} zK4m`Cyhl<>ue*taUteaLMK~@J%^M0E56?C3;fdzyFC`7U zH;cHxU)``NrJPsZM-qs3#nL|aLOhWAM-V&$9& z-%&#o9^9C&fJU)s1HTwHP_~y8S7z8mE9~o*3@Kv53-3)1gaw_uqxH_-gDj)&vP_~L zj)^hQ6EUPVne&PM1=CzFvj82O_I+7hWzf%Xn|N>P=4@UMCR2_|1fO!BPQE3@S?(C= zgTmHVK{V$iKo=X}QFKMmCNF=Dis2ugw!qUjW|!mjtQmir9*MWC43c=WT#|XSo<2O9 z!Ai{}o`Amt4QOsS?Z5DTi-;xApqon~CL1ZX|w@%qzhu5`tPAU5>U#Zoa)^ z9bYmnUlxLLUG|j2`M?HXAKFtsBN8o0rKF>-Lwf2?dP+K7e3ct6Rn1p0k*qG7tOm{D zo#kEnok7Oss43lt+f-nyUl#B&#VYsuvEB<1Y;d}pw4HW-O(&ad);xDHJpJeKqLpl* zaD`m=!J*{R@HyMZvkFMz6O-NLDa>}3dZm|x(7T$a{2r_n@8|q*2!2W*y&|hV;59Dn zJiCQkow);J!9W&WBsi_1RrIx2RUvPH{Hc}e@vdanPC78UeG#YsX8d=zsl6G6%a7>@ z+6N$zL=N|UI9tj-4q06_*c>WHGLV=K?wYDIt1Ic&&{t??>o9c32$Kz z)omSqFOPF|Mw4lzX+V6SK}UiwSc0wcy0Bl+5q{h5_MGFlL${utF?m88k(1JXrrPKj zAh1m+^4(=T-b<}q(h)k_^2m7S%h^^BLL$qW6A|6W(1V(NpWg&Nc036fPn&%gJq2|e zU5!6#`PH}3!kjKfSC$XCdk#Bnjvv+p6gHVeDzDJKg4ssp*eBsqT-ZP0{0MYHu-3DBn(MI;Aw_2TA48YTp9CwtttY zk2~b|dx<*zqMbldHEUH3qjWR@#fi+?jVBa>lt3LUQqDbsysry_to1Y|pg`UhDVwU!f83nLXL2s(7g0N@_s@iS z!7*(`9S&lg1b2*w>RN{ z`Tpwguw-3x&%|s@+Stx150$Mx#e1KDYN{yLD9WA&yH|&EkkIDIo(abH+EASeX_@z9 zD*pPCc(1U@E$h72Hv42zA`8#@`_g(g(kT{|r46(Lar_T4It4pg7PK3SsE1MSIJ!Xk zY}KlrC^hYG`aXQFk&NXO-y&}dE8O1@mhKigDx&lXm+%=-_>o%TW>yg=w<94~uh|z}PFK}ZKRIiS z#M;G=d*tqp@J|1H3Vi)$2KPG_Ri^iPzjr^cJ_bc>fqGO>Qfp@U1bg+bJaX7Ve<9xm z%7eF<5b?B~_YsD7sKkh?Bw!<8)FCQbqlbPNch#ALaQ1gNo^b2Oqrw55OcO)A0?Y6q zQW$0=(`>1{fKX)fV4x&^VAEdmc4jXxA0DKhI$vkhZj_PU_ehKRlx0bXGU}#`^Vm)D zcPniy&OafdOcTZ4AHf5{nSVv^3uK&8xv9t$e(^~b$_}2wXA2xL(raB;9y9J@iHyjOvA;Hb{l$-k z05M5iKuOg=v2JI&#sL}?gp(tL#>Lp~g$_yh3jg?Q4HaQ1$wm~s@Dh0-6F2|t?H8t~ zI89_IW!*n=gqc?n35OdAWtIpEDBXRve0e4|l8Y~=d@My`My-r=y{I;y+d+Pi4_DPf z_?pNhlkz#rwSiawqtbp?jd2KjUF;VQH)DfZ5y zr4|Pi?RXOU=Pno6Hn<%}>xoVLtTt^b0VzPSl_pZMy)J@DagXc5>CrRE}b=^}{ zhc1!~LwjaApu=BBO7E=abhwX?fIzA+Jw0DH!hfc&B0LtK%a_MOzQQ&t zgDz9`u8uMuffG*P-%)NV8Zc3p-a$|}acYUK^Mg{&fM8wsCPxQ@bfM8#8Op%qAtpfG z&(~_TO@blH^v;Qtw1jR7^VX}V^sSHQT3h}aVqQVw?#@+9fx;Q_a6jx8!vi#nb`8*X z3`femmJdu-TCl`TBt0(tGLM9BAGzkb-Fz(k1~B2`D~#;x4~wib*^3RQq|koN*A1r}}G8JQ=~ zsk3Tn(a_!enU%V<38PvIMps-@dA=Bwu3JF#**@we9NMvbbQ12BPut0UlybNp!|1{R zYz0P1tZ8!Nrk~xqDE1p-kF%Fg-goe?Y8%?Fr3U zG+10B2!ISis&8XV4Ghxbb2hUL0 z`ue7V!Ms?qC^p0Utk>s?M=bokZ$p8VtP8MCC}?HPW@6Q4gN(5t+R*{2j;tdfZB^`F zg}A#5?r^!jz})Ht_~a~OJh1q7t-l9JiJ&RTtO3jU1t}w%WYvvYb(zx*!V1*e)!p&b zLcHI26L>S{NRX`3$saRH=xDi~4i5I|QK>ZMIPPAtI@@}Ks;wrMDwfZ8mOkv@R ztFlil(`fO!0&Gj`4i;ki=bulXG%A^*i4;113fTXhEDhjXqg#ow8e2WlO;{^SpQSnW zynsjcZ6oVKPzlq(w9HSMAo{}~{ksU;%t_7Jy&go7*WTRBMJ5+KmxbO*Zc~n3)5>F# zwwq!J>5-f?_#M>pTU%8AHUi26_eTA|P9Kb(NNTD{LZ^5hK^dq&gJu?;725Tw++;wo zEyihwXODA+3QiwY20&I2|E2AZ`Qa0W*1j~TbdBUHCrqGc1AXQ{Zh9?hVT?}y_*>9hpud=3{ zkM*ou=^1H(#Q5^>`E+J=UYNn4lcRNt8HbU1WI%}>sKPD&E8^S-=4!5+QNioVeiwmL zT`rc|n?JFKkT5yxlP)#GSlj5Q43bMqI-0k7Xd?;CS8!236fR!X?_t=>oU5-+yhB+L z+7VA1dE314>1*!W@Ca{{`x!BDu(!0vnVi}kylRG}!5CX#Z|SiGg`?H#P%y&`BNy_{ zCyb<-%X_FS!Lr9SXli zK5t`sM$fzzn@sWE$uGMFm_F@Ii3bDj0rT4c%Sv>rigG5;nGu*fXLjBiO3cR}aG z@@0YvvV(DtNypV50#W^dkLX11wS^8-6F#=$M0v_JDBp6E1bt^60Y+oBM?D_TW^)g> zk!Bs;J<5i|6N9`UU~zxrwM_)un=b$Y2fVq?{Hl~d1$!vIoWSf7h>B4#MCNW}E;Ohs zvOl&Um~;D8w|b`C52fX98!JL!DdGEx_`j+xq~iT~L2ch!#7!rlp=7rn$B~XgiG^t^ z2bdO*~8{q^cA z_y=nBjc2c%8#3zpm*3c_u1bx>iNFefJfxaNTEF66y1hT{Bkbw;qgAbzX()2jjZae^ zIrsYWodW%|Qx4=_IQd>q2SB;;(Z6ZnehB#3r<}6fw}Csf8stSXs{)v-B;EUwuG%gzCK=M1LWy1IU0ss=sO}@f~eQs>Cc!h;SV#K>Pw*b z4oDN*<7lw}IADnTPVa(whgH(ja-R z*A|c0kB4K^ap`Z8WkMBYOnR$yXqhE_e^#EYyQ^Z9itcM_8xbT0T-P@LN@K=2>Y%ev zE)$W;^`#*;B*cZafJc~$%#v^Q)?^+$$y|^yBX*QSDW_t{l`-gekiD=1*5l=;QL|nm zygF+ojvz|CPF*$Up=156EZ=9H?{r~deYbheU_ipl0OEOe0E1=-4a3~C&RX85bDn_6 zqBVh^Jsv&fsHqK`J^!AsWu}H#f`m_=>!aW*FjRr(T68VtP<@s8{uY@eL#Du<#)tN;G`038N@U(bSVKQQOJn zi5@{TOBmnQ4N40EGo}nVafNE30EW}DjqiBJa@T}_@QPrms_m=ha*JrPDuyp^@+A}O_X0ChVLwKXp> z#xH{0&@fLDjD2{3w)yIT+m%WB2sz3UFEpCf$3u%vM;V;p5?Y6E0W`g<; z7gK>q&pUzLE1h&|0*=WP?U52F!c8D^4fnLo($zurGu9txVEgnyA%^uf<$pu8pIv#?@ zBUU^t9*J+cqSJYAKJ8i7pn5xX(|`CmP<{P7oo5HRH&f@lQaq0p4*4U!4>bsaWlHaJ zR_cLj6oyP6|8)2{EjT`r39y|>XUdwqKv>YZOrB@O13)3TG5> zJoCsK{0OYMpBL)9{v-^1D!ae5vwsR~*%`mheD<<`dMvgN7PswmZh!uKc{rSD1}(n7 z*1CjxruIL)yaJwotod-+S>_h}BsDso2Du+@=wzr~Y^yABketI4T3zqpcq zon(yT0KSsxxV7^Gc79x@Z)Ug!4;4?D?tqI*EJ8 z`GuIAll|Ht(jpUv^^Vq)BRSQDnG9607KLE3VgPvCUK>VcIuqChT95F|A)8Wb|9JwD z|FavRH;%JE42!VaMxSHi)z9)kany4$KlTXI8%N@`FzdQ?l>?6<-Lv8^NRf4Q@{`r> zhUg6--M`d(L?Vi($NUO8=#*?B6e9>k^+@Hr0g?dx{86;v+L|JfLhqA0J|>X;HWO6y z(CV`Jbl5+)DlQGaWi?yuzhVIT<}ts0U$Gm+4Y3ycIq`w9gWz ztN3M3Up67GtL~p3gw#AjD-!4BP#re2>tsr+@P{tyE7zG(TQ*Qn`geC585`LpTODe_ z>ZhsW>>vws#>dCN8#pWzH_a4F(khB&)t5Yz0qd)pbj6pkc0qqnnf#Q?!s)^N{fqm? z_Xi&&cjgZ68?|lo@a&3%q&fkgPfvU=&Yv6~x@c*CWs@eyrjFlO4wzRCEk-fKMCEGC zjTPCC-e#vFn0HlfMh_6`71M8>x1t;7cSJTH&$*T(f*j4w99_)9nkSA%gbi-6ht>u> zmQP4`o7=Ln1JrD9B+@Q3R6Mfu8k*iMP}jSBu+$!D$jO=ISo^$v)c%gmyth#M`pR=7 ztnI9OhF|mGMbcCtEwC}N#;h|DnMsPQ5?T3TW{)#*np8T!+iYI==2|jFa4&beqSweD zfB!dV-dhS|zk;-5`njOS-%dHj<1WBoNZd;!ZTvj#s|II$N=+_oyo6fZOA(H9gvq_| z;0p{^J#DW^f+rXZ;qUiY2yhGx`90wVQu}Lj!)->K{w$ob?%+xybaiw4k*Ix5b5D84 z@)JFda61_N90X z*5QCVKH1hS_O4^ET2RaFj+Oa)>K3l~ZC4`u)^wdJ+tEtPR;h9*pLr|-LBtB(5n`>P zntMs)4%9MC-+w$i#~^Lr<78RNLHgP{GGdX2?L?*C8X0jojy^VX1za;j*0>+H0xXfF zf9K@*kys3C8}uSZc%kK5OC<^W7k}yJjt#&#<%6y9d+l7W=6hmI_a|zg;l>-&2gSL?BaN@KZ0$`Q z&_f#)s(c6x5$>G2gqRUo6Rq9TiD%tyboa!6JE?v0;jmK7=IhXl?rOzfJ92 zF|F}-CV$qpbZm%Njp|dN>TvUY9zGDf9X7{G*C?`J(f8f212k&6^zZvm(P&{KqO`&a z7Mh;@RRMtP_GFxhc;p_q;23-juD8iS1$$~3?fN8Hoys5{65U|0NrV`>qpBCw6(<-f zTmk_Z|0dq&7+bnz-RQ4-h25|Z&owW!aY?o>J@N<-O(d*;?#@w0{+lvAO?j8&qb{$l zpk8$-TPTZWojxLtJOYi!X&X7(@p*2?Fu zpNEB$X*+JJZGFStqq%mi{cw@-Fk$@S7!ct&*G*!Kp-& zqmr*|>3k`k?>qiJBkD|eTk}5bsd{^7TG8Z`J0Gg^j*Kg2%kI3|&?+89H>twI?4%EC9F%tFUnGE6uy^DbjAEUcWS#Iw7EVG3F(bE>);! z4n4&>qTw{SoWAaUv}SmKeQQ3ND-77v7AZzk1t;HD)mWqL5O0`2@HK`)D@rOFS+@7S3XT6_O&jHgw=MMR=4-s;W zzivCEYZ6c-$ol~g@>LN=MG1!V$iOUPB!(x5)W2ue=kIH7?!qLdID8N`VZ^al;FGsh zi72o$=ePWC59H#3;7*$93a=c<*O= z-0bJiA#n7F%^D6^a?G8Cq>b+4t3%$BLk^#8`2NsnJfz)W2-@ac6O>dw-A2=)w!oZl z!!D^l^@sh*Y!ZF_9OtpQ4W*p+Uj=DAnf43&s)UKtbQxVQAKyQtTpI>1cc4*NYKZ0ODO|@qQz4g)zPkGuAG_ z?KkMFXTQ}Q7@0r353Ac($-+sz;r<%8za9(NiVp zB3&O0aG&Z`Dli7gmP9Pc)3aq|H|Pd#(bm zttu%iZY5!F5_mYi-<}-J=KUGQC3!)5Lee@C)TyCqSl5o;gEph=YZB{K;>#fZ*b`(>S)hz(k;Vf6COHz_AajO6jWfIJO;<8V#PDbnAq zjAu?)j-n+9x7vR(M>IKY2LPLC1GABratPGXCvbH&D7^=hrn|N8WAM{x96agg&-Noo zV`rCQf}h&(Lf=u?qm;>DKVmL}{;`h(dzkl|yQMkNT-Go?rHVgegXPJd8)c>i$DfZsNMbs) zBtDeTF@!LD5fIy55x zr3xIbnQN&$0(`#9_Bkv0Hh*a*9E=iJ?e9ZD5Y{cRF}&Um)J`CgIkZy34CdQc=+kZ` zdR}=lsPbATM9|HBm;J5OP+-@kS7Dt`igmIYRJFN%jSXUPq^TTZ{|G^V>z&3wouJSf_AM;_${db z^L@H;**#5siKyq1LQ{M+{R)ICr_uq0?57_H2tIQ@o~s`7yRvd-+4~4x0U(s63~aq?vhPKwH^|EnVO;+Lov!}m ztxg(V{)QAA4s%^Z`4%^g%=WVfx;Le=JYp{GFUjFl0Bi~Fed8{Le~mFLIqkkW8tqmR z0R+ld`c1bQb5guN=QDZLZdq`QMYQPn$aoL!%xu$~cBQz2h5p*f%dMdjHfyBAcxsjT z3=*=xM+5@&F29YejU_HF>m6IKkm2qI{UshWE!<^ZbsV9tw;s(BUx$0RCXQ1r=d_q9 zbN|U@mybO}tU3yQV>;)6|1I578YjHMUfAfjh%{QTh!C%>4a2vHL@3u1?~DI%ItsC> zL*Y8gb3Ynjs|z!wl2pYaJ`h~M_g?2;2qpF2vN-aMtYb1GldP;F&4S>=l#Zfy>zKHX zd^Id0se9vZmlot5Os}Zl>b|G&W;{4-dY^0Hm?$i|b+)4D@A6@P<)Ov7zHrD-)yNh`Z~K?Yo+(COYb2J@?o7)l)ZoSUqEniQ$v$e9&i5BEr(Li!>s4_9zc_FKk>ag8s%xW1$>fV?W!Jb)iY(;FM;JR(OgY+E$d zoyby1!!oU(evWVTof;B*`zJjy1DC!nj>3XZA-6lWman1z63e#0Y3u`q?SP}zdk&Vk z3c#<=^JlFxtQEG(w?#7AO*(mY2SPLuAZ>VY#QQ zYf=BhKQxxrYb`$>=_beM?(L+;G={VMO01k25p$rr-5R=$OuCzU?x4MD>NpcPV{@J0 z{tp>W?dceK6EgfzMAukWu1975wvfHTF}MQ%B=z-t{SC(9;GIPQWzB4zA*kENS%B|S zMjX^XpS0X^?MH{vtVwmThMP0*P}sc zJ~DHkZVM!2K#e?bp{mHj%!3NmgObkGjf48sCRuU1ShmB+R++Y0Z^wrC=_bMXL)&0P zbIsh?%QR?OFi_&Cw<*ln`qqbbnw(&_372Zg=hq1Xt+n$>6B6eMgKH@L3xq}cZcRHN zY7Lfk`)^@FWR+D&q$x){p}qt3iacdRd~i68_J;)338q$d0P)7&jAU3Hqj#d`9Pl!eU2nf{(rZgAQxMTbwsJpzmU~@~r?3 zW&hf@s>VP0-n_!Fw|XK?3BCVGLd@~h#i1(!!tgO&)S zDYSum{|QVeS|bP^zcpNpu<^RMFua8^h*zzFjGJd@vm3)4#cN{6lc1?SI$Vw);V8nl z1hA&uXaDATPxOpaPXWJx0O@{&|0s}bV&4W@g9i(9|MQ=agiF85peJ$KW(lmsmm9(Y zYsiP;bN^~DRfWcoPbRM&uCRuzp}cmSnA`nvslZdPc|&kxPVw@{uF~-3OPqiwUPx`^ z%`Ikz`3eW`2_bvktp0YN^f!`caI12yQsdH%B$O$9nGBKCf2K_Y<)u zN9;f9uCp`KjpBfaTv6;b#JiMwJ-U^$wZ3;X1T5`1RnnGP^)gfUEkp8)k4D>l*WEg8 zWZVB)$t=+{C5fn!*XR0&=P{-a!;Y&7{8k=*?my^zpJu&R56{TPd>>K`#oOmS4^am^ zcokDQi0YQ{Rr!7&VBd{K_*;g)JGLJ`Tnx;2{_YKZ!Q+Ps2qzz3%hzvX6y3>l5m6&W z?6BP!3Vw#)j&Fuv5 zL^_blLbd%-^oo8S;{E)Le)bOYjr}x*uNEN0Y2LP0^jY#y!O81M)*>is>UzUT1=^}^ z4OTDeP;Z^$y{rTJ=bTyR^e#$}JHOEJan8-^&D%zj@`f)pW6kBIU<|LiTN(Wro*UfgB=;HjemYU;fw~Qb|w^#(83xVGv?LRTqo7cjrbF|0_&7bA< zYd_n#+q#VrgU~17($SxGvaKB<$)z4HH@NSVqjSWMhrM}S7l5SjUUSf!I^Ott&I)0A z@1r3%Tize<=`UlDSt@OBO4_qyn{P^-#mE0s_^V{epH~M;CDi+y9mOQ4TlNXt@j~7U zh2*ITNWbeR^5e7oWc?~CD(sS$KXZweSeBDEWrJ@Gt2^+00FP6`EZ@ zV3ROIk}$)uuzb8Bu{A)=SED-mLL5V5)Xze#7SY);f^u46HPvelvalEcy`6|Cr*4W7%rMGeu7tvp)c{ez7gXGW% zI+9q3#$dz)^*863PumKb^`_>V{bx5j@HQ`|%v)eH>=vW4TwBIluOOmFIST=}Q!ES~UR`@^6Sb zcf0-QN96kQxH;65R%v^nxpF+H&H8Xl`k}YJFO${&s+}2ywLpq z{I4zT9mVOGj%;D9wiJ!WPxr2N;GqU|YI#2!pOoKp@#UMeuQh9B6EWzCH+lO|Vhh7D zUJv`d;-EEmfTVy+!z1=S(rxjJ6uzl|U~~{SIH#O{mbxWA;xv%$0jJ)({Lu^B4_TYr zZR|XIUI-Kv-T-a};vg-WIeYaj`(Tp53an@1T_gT+GaTr*fWg23 zs+&NW{B!Q&cYCe)(o8=cht;d$vVmV^x=J3MZmvn!=H~Cw6$ORvIo?EOv~$TK zScTXQrO*;zy&JaJAURs{(_G&yWv)Tf{8lUziF~v43hsRNjw-MPuX!GQ8Gu5vB=^^O zphILUn94LC572^FKaai$VB%;bJZ?tH%EwgY{LxS@qkWgfUXJ2(a1>YZ8^!w|Db!BZwaSTe9rPP@0X35-%LIS1HUBJ)N?xcb-f1E|EtEAH;9gz+hxlSiiPF4p|ikn zy&)9Iv4RT}|7GO=Pc}w;AQ@?~4Zp1dBPr=j@MERr5s;S7x+Br#!K76J#tq!WroK@1 z+hXf6f=@491dJn_hOaP;J9m3Zuy$4x35ZtZVZS_HU5VG>0fP4)3jHcCKYm^PvMh(T zF6Kw3vex%$En?)a=HTC=;5073w6xA)PCv4bYf3*(e~=JFZI41Tp;K1qJxfp|3hW6`R`3X~OKDZWL-PATsyd z6z~Q$!L;SSc6@L=Cm?JQ-~^}oK`_#9z%{(9faoaoYOBAeA8n}CQXATZas79P>_-u9 zN=kQ;YHCVo(Fi9e%r-%rUZEzNu(t; zTNp>X^mVQ|uceIPCwT?5?BQ_}+!lLn%_UKye9Hq&O6};!;`) zE$+qL-HR5N;#%A(P~07ggyQZH+yVp$2{--9`#blXbKkY@Kgn9NGkcyr*)v%)dFJ!1 zIz6qceD6fr17AXF+s05p^d|VFv=WzfW-}kLyy_Bm{rzzGbM~J%&jI10Th>_Kb%4bW zkqO^`th-Y|FwAMMZF>wdlz#SCL+8H@^?x@+ZfE5{9NeW6#QzBKybS|kY<~GyEYl^a z;)?gtV;@7fYOh&Zq>jGO+Dn~aSx-1E1Sw|P>Z0$unQAaurP?0JSW)HqeJ#dSxW|-= zUm#3wPncd>&2%e*BOXNLFli+nL_%zAG!U<>OM?j(lWSR-$C{;hrCS1iS?N zc#j_vyDU!ewkxiU)Xt1}yC`NvdHpn9*A)`fBG5a5bChZ2zf*smYJx=`!-3k#|+G zfHQvM2E@}@W}3l@c`k%=7mj+F?G(!44r{Q)4h!+(zKR9F43kY(b&GndxTg0>+8-ny z@4q7PN;y<%MugQoY?W`U4TH2ZsnRw$m5wamD;xz@0;uARGHMV_fBF3cdOpj-3^hsD z;TAB(^WG-drdNPxonfAO;t(Hp>O93#d$pb8_PsZuyZ4}dr#3&lM6<{ON2f!)LgVa{ zRYNi2PTDe-W5Il7wPn3GqvJ`of}Ie~icNKS$6olWfivqvdE{}CiBk$s?F##H5|4K< zhy`-Bfk3%oc?BapSH~p16MX#k+Q6+rM?|-}JlhAX>r&rRJdU?{z4)lMvRQY&9Dd?p zCT z&msS~1pSenTa>Z6$G19DE#Pxg@5Fu%g}I3ij!bJ>8lam{&cl%6=C8ZshOYT;hMazI zupU+BLNZxGGW32v`UbnLwvb}Oi*7QB?9THfIwN(R);TmWrS;>0U5~3}4DcKjA1jUG zM|XG_yhEaFJ8v!$);SVGp#}XQM!lvSux|phx1$gRt{L8aFQAfhm^TsbP^6EVKC z$*b&2mKh7@){bnGW9}hpe8#UmxM(hCqjzwpzS!>N#4$UTBE}J(9S{M!6NB$u(IL1^HvTb ziFc>7Yq}zRvr)Um=)hxkNWAqwsMYrwQ0Ee}>bsCeV6tCyjE&D;k4Pkw?joV;qVv+6b6cBVoi- zC-z9X$EF4#Nc}zeZRmVjDF!!I#;R%x)@1)>-tf-Dl($sV1s8dRm^1!H{6Xd9WM9Xx zV{j}^QP~M20*7y}xN1*~J(`4XoI-c$KdpLm?yG@REyqrQKgZcdG-qdy>QueC)2gW;ZqQ-pLZ#(<-COnz9`22ud`I8F2hc5tn@U%ld;}a*ENlJyf`ZY3ixik83iSRDMe!vUzfP1}N;(#5mhXgwKZN+9Bp!;tb zUiJ?JKh|rQF|RF8NZp&O*`GU+fPn-GpbTIe$`z0LIgkrF2c3IF-qJsVM}$h;iNa0s z1NLXn!*MrMgdc<+vT5K*leg0rZB4h*q;IIrw0J;ff{uSrBGhLaC24+{{QM0L7bv!qK zYT#;n%~(p@s=N~Yj&0rqnzu9mhq7+Ovj%T6L~MWJypXpwHaQ5yd7V+KEq#v zkPJxZ87yK*#^K{>FW%i?wF_H9YF6@@?5&?r(e5JA6eX^8 zxq4rgJc>YTgA3~idhApF?DnXzr5WIS$Bp5^TY_s?h08-94Qa%M*D7%BLOLu61?pkI zuPS09ng`n~6!#Ce2^L5?Xj?i@74xn2&RBj#aO%6r(N$+4>m!k65HQx%n?0Scu8f0| zhngkot_gVjN_u*v_9B(4E(|!( zEeJcix{~PD%6~i%Wodyk5#K9M^4^gA{&{v5f@Z<_hlhWG;NgW-lD7pn#W(+P)F&hg zdYE`m>Em7tM?w|8xd1%*PEmGOO&z^Q-Ij+gESKLo^-y zv*nOH9MeqXDCnfqO1SfBQq7>>B@(114WZVT4Ed=kW`#iuiNI0|+$%$vE1(Wch!=Wu zoY1MuipQ4~kmPT)`+Tz~=&jSrkjp7OV%;4ih|@nIlY$9O!D$12M&H4|CHnmGtOiO$ ztfGGbh74Vi0=oZHc-T3YcYauOCu#oS>`2`U_<7ER4QB}8h9~M(DOSEs33rVWBRN9Q z?%oS1(F_ap8kJc1Lq;lE3&D5UQvn!0=SVjpeK~z=BgQIw3-z`f23Kr1?egT>3n(?g zVjp6~fCDXp$Jx|3PooHqWi_&*)FZ=T{qVpMn*Klu6l#SDZh}dxgrB7oO zDn}(W#P(Ppu^aw??rp)$2xZV+ufY#+($jnxZho9Q>qgz91u`K}r0#j(C}NAFDa;wA z-@nAj(W91}lzRihe~Pi=^%V6wwqr_Q}& zjMMhL<)8=dIy-^L-=FKDL@vDnIjahexwH(+lc$S*i43Me3I}8SQUKw;}i5iGodgYl|`nsq>eRpr}i6dp?F&^J(y z@B-Iv166cW4Gu44g=!S#Y}%Tm-um$~Oa zm(AFZI}Bu=M!wcpO2=i^Hy}Y!^2NBrt_CD?a@|wN_}y5sbe2~wBB~t0`T5x8+XlxX z@$f)w?+tPKgU^Op*xueer7~;@lIcWHy0})L!XY$zi|Lftn-<-h4BdHxJ_<$OpJXVg zWH?9xUbalb2O>ry19GZ{KV z{q3B&pY>=}SEAj~-xCxrAt}-RZ3&O_`xxw8VI zeSd9#{SPUIBw|y;i-uXS-KQsB;6btL&MynQ!8N9P2vpEeinE-l=aW*`Hd47PnM;Sxu;>bwXJ|AH;KzXLA1rh zNBKClt{)uuW6OR$wE!*20@v+A>K-^RdLB4Ax4QO`9+8IvVjtfpJ&KM884>w=qppOyuVm{>(<=pB`GLOMt8|yBH_?K3*|iI zlN-cc`7q z1TyB_6)&s6=5>+jCUH#`ekSnw)StctlAW{0R5aqjj)kD&!3Zk;*uUU*117g#2pMmy z1#atsc(dAKJdFQE;FZ>*e@>9FVB2r&FK`P3rY|^JCQ4j7ZBJfv&faOIPn0;G3S|Qi ze3?qYlGzSVUM28O-_7Wx${+YD|MB9f5MKP@KVCe8n|Q>}33S>zSMjU%iEy@TmClR_ zkBwORy~}n4Cx7KCPG_7CUcB2|1ba}{9>*f$qLN>)1bd+)r22nM_>#CAt8A5|b^eK6 zh3q(8VSpD=b{ys8UGx7T;FUq?sbf=jfm3(+Y+b*Mv+=Zq4GZ1GFT>qBF={HI$&JDQ zN8#M*yZ0YJh$C7IN$f2s7=1$EHDbB4Yp1F|hr&>^7U;{btF}Fu+BVxG1tnm3yEkWe zdu!({lcB%GsZ_(Yy}84+Tg_um ziynh!%95ii+^p$tU6ToVj7@rB2sU{iDV3`I?Y}XkePuP)(0eA4CXI+8`Pebt_gU%) zir$S3miJik_$eC=}IUT~o0mgM)>=6n2%a!M7!Im61JM1D(y#TdDpE;9x z{Rtod5kSDd0VpXeJ5T&N@uT0+;y}^mh(ZML8^Joqjv~ltgm(Wd)r&ZliU?}l%mzI&G%#(+wpqFHxhdz}jm5d%UHi0Z?E5kfx8<&!nH)Y3+n*EKHf$O=r zFsZ=tL|KcA_4=w1AB&mu`*#RE9!ba%AW1J#f;P3nu&h_@8zhC5DZi6TNfq&k!~yR^ z*zv`giiCgL@p=#F%!lUk{Q<{^=Es5d#Y^sg+3|`3VAoE3;4gtEjdyZ6bK`+O-FUBf zR3(`n>$k2 z5J5jt2Gv7<)d^A9xz&>fGoUNnRI^X$;XV(qpYGBA215E;NlAkwj}<2x#jD!A$n8Y) zQZP8mvcYej*n$JMfAhG|F=a4FMuQS#>=q%JQ}>c7Z@qEO3QFC?HuW`MOWyvQj%Nz3 ze~qVLx{Dk{mMa#+tJX~xKsMnyXdxmpv4b}*1cFjeZ&JRe2%GO+)Knngv3rS^sQXFRJKoj|J=BI2Z8Z33*% zo7hFZXtE+wGSq`)uQrrBu`Q;~wf`EG_}`yN#Ov=R6Ct*!4CFmC69nV_BgbP;oJ!({NN^g+%SIZwk-b@D9h3u8%pE>07=agi=_NOCsL`Mj;J_e<> zC7K;$lg?WDiig%}_4Z~RtlK<@ufS>1%84vEV{|6Kg=1SDaV|u3#Es}k z4%az73K^l=3+oMDl0G+gLj0#j=9M_wO`R&sxm~AlWM-QBPc+e^?IEM>S))dWsbNn} zvVvO{1_Smfox$*`b?>*_h9Ly_u4#zGR_Zo#G|f+s*^ry2T%O$5Aquu$W4lkBMBRl& z!(N=E>CsTvc`CDEq(*#a0)NMhsqL8^N1C3K3d{P5?|oxmpLx1%#I4|*_lw_zbXVwu zer5P}_4F1;Ve{KGk#V|l{UiMBa{dy*G`0}S?V1ki=4Pz%k2j@-nKAL7?EAyEjHuUN zZ8}m_;AbcYN2b}0QDuF0PZ0MZr$1bLty20c2_$=eTm&o>&ALu8ZfdIhzy)2>)juLN zU3E7jA8W<=es+CT!i_^t_{x>~v!IP@JpzuO3XGQ%zERnT(GJ!Gx#%HhUk^|oaesW_ z;Xm6$Gos0++_@#xt~BrZk<_3c%v!n}2(|0(;NP&P_%SIL;WN70)neec+Q=$=B=_Ax zYTnB9B(lQpVI^%%dC1!#`<}g_5_FA_%vRhNI2pr_tULG3U!5s-7TvvrRCfo=+K4@+JFFT&|A3NUvZ#({-8DsJ4?;Cr`d>0F+JU?R< zV<*91XNvS+&iOZxGMWdmEVu63#BR%`j>cQZcgi|xhnCq&_ZwD-tSf?|l3z^OU@^wu zLBlYn8bcFRj6)i0Q^@P5X--)CS)ZzYJ4h~xSPcjneRZslaO2G^%>KCXHWk=iA~wEw z0BvkLU%vJ#*8ILMhz&XVb9b}I7D|D#F*i4nXePe(4dks;`Dybi=*5TA3-18uMV+Y* zG1{JKef4Y3A$XzNVo4iRF#>q)v4Th$(g=3ul+!uGFSnZp*aZ9l1tBMEd4BI%Bl3>|CI4e~vT8m42g zL$L9Kd!A05(d~;+hSm=4nknVnO#I_L5AlR}M~)>V{2Tk>k)LauDvrN2R!IITXxv(9q-9+s7CUC7DKL>&#cVfD6Oa-&8fV8zX zv~^Qw?ZW965lK{UA4QTmZ?5!;(D$0L&r{_2_%A&DuI|DK?!u-vZ=GLU@d`1GcO6O^ zPsANQR8Ug}HTGmQ+7Rs1Hr&uYd9ZA8Lwm6%6DE+d8FS0mt3qyT2e zZyy(mjZd)STTdBj>^uGBQYFPaNy*7Aojh9!ar3VFfpz}tG(ft;25|$^|AOel)9j<_ z7$nA9*=PRh0YNKep5n8h|>Bo*xF zawa*@PmH)+vU6S9mLlrJpni&zFdWks3tsqd5_btVp+vl> z!|`Wru3tMIZ6NVUJ0aTD3Ccumx4YS0iV_>U*@(5(vz2x-F9i-S1{8F8s8kcRrHwBW z$%^(;#~PjqLnzcZ4(lMAx?6B8rb+eHpFrdRP!7 z>gN%$rXPY3m)gz9K-0q*C~GTayZj+`fRW9JkiomKm$7Gy z+4d4UQ~2oEWkI=C%Q~(|y3|GS#qpc3D;W^GUF2@N7PlzlP9)Ym;1|J`*^#OMoE9P( z9s5}eTd}wHs2_%ki`>6aduyb==6N~nI`Y(ot&b8UI@02-l^V_KW4UMXRZt#ykVqaC zZd>=9^gY|cmuLsxlgyhKr0dvx2i}R}Ue;;_(Y|w*U%eAecd%Q2#hJZH8>|5XgTv+5 zp4+v9qjM>jS%?q%W$Hosw~uo!uw6prRqpw>SDFs&{Mhlm=9fnp!y(e z_&q;fcmf77Ec02|HPzVvi;jQyU+H+`zv%e!wExiYuFUsI@bPa$bd&@ynfmyH)1p8R zna_wv?do08nwlA&ak%J$aXIK?-d@+@rsAdsJkz5qy0+4D9*~fDf(y;_gSwwi-(96l zS#e$bW5{svxUqs24Du^b_avF)+Umr;QA3MIoO!IF$zQpCf z*zwB{2atoqfot_obn9ieYwe^1U2Ax(n#Ho)O~KiKKLa5&Ap|KB&|}voQ379P>Bz>) zyH*-pj+S>;5s0Cy%9P7wo`2_J`>Awz*C1iILv6GJ@r&0Q#g?Klsdb^t{8LQb83TI| zcfWEnF&FHvCPbFfSnuF4-EHlAMg2ml>Sh9gEZ7(Ew->iF`NHL3_0ZUdI6DZCeFr${Nn%m8X|`Ylz5`Lv4+}@ zB$Gd*Lin4x7PaDT)V60aBOLrC``Iy6Ke2iB%0TxT)AY_Mr|FL!pWxIodRj4i4wq z2P;9o(c6AN9SZ>QGpj7;iMosuO!Ald#vJl-N%CivvD?PL7Dpn-=w#+pN>N;g9E1p?xbL)1&GO*F2c4a_K9tm4L5n zSzG)+oiY!{_n<6x?~?z6$5T!HH$0x?z~>!p7BeDEBLPG%Og9+7Lzw*T5Gb}k|IUOh zC$eGq;>GEP;&KtwynbzdN6mSL9I->=>zjCnP*N;m{8(On<$-`~-hxv0y!(LAS`3CP zFTQ57_F*PhwQzuA5Jdx%AMB4$m zt5HlTq|(yRnLts`1961x!b$$jLtn%^q~IYL49hxumx4ofSdaAE8rmU}We5Fo2`fj= zHaNVRdK4!)vc+c1d9~H1hy8*?UaGgz^ot)MNh-*B#F98#K^ZRC0AI&q&w(q@K~2X%)rvt>?O*9Xz|x^QbE}KV)P^CeNAVV9?WabG-vZD6Kl%6_ zJv)c3W@5Oq{{VCKr}E!BXais3F|1ycXxD@g9zN00cQUh6&?VQI>N$yi-3DGitJP%= z`7y02%nLO$RLJU|@R|UN4l(UUKN>_asMvb2>1)dDfB3AMg+F2YLQUi*hG8pK*-}!A zbnxNJaZS$AG88S&2N#P4`)i$({~jbdjXpe*1(E$hTK${CnJIEtRzZefkhYEMS<{gH z7N#bh7wKZy!O;7-k6*lb@{KoLDr;Do4^`=;sfq4|549P8egGO*ON5tA#9=C;=8sWF zMzj@YH=AfuW4=hAngb3@=FpVMh|!H~Q6CC;1wF?f-kTYp^?UAdBgM#U%=fG--80_R zf_EzsFP)Ft*V3P~e>F(=k&7BH!zuRYIt2S{FR-85WaMh=`9LBtXm4GLv z_(}C$&+ye94_#k;%g?-g`Teur>pNu$k{DA-?<)uvaT4`9)Azyz!#aHfUV z(w;Fvq@#iKqDi%x+MY}B(xLv842B3uZIUh>%X<%RiHq~FkonV@PA))|zr*iwCTO5x zRj`n;oi8_C?#*34$sFO}22=D1Kn(43u#|0xWAs#S^0!Ros-kE=+PaOWkX*nat>a_LfZKo(p&h$ zx6I9TV`@EvYykuFD)28p{8WK>rtqm`nK-b`p0j-+qn^QYLPe$1Jt@M%+@QYt!`tQo zivgV#Uk~=MH;fcEw6u7L+@1QBzIVXUAE^T9Yd&uWEIkCN2t41fiB?%?oNC`~M5AjO zu3wDg8j`bTU8n@C_=*c|Rnq8F&dC*c&Be-1{IrQ;A;aCxYF>0&wtOd&AV#!GD+)+& z6BMxn7gVl|9j$qG1D&@Y1ou~Jbj@93p;7JS6CIyGIyptaY)XhopcnUXZy)}_dl^Gh z&$UkeSPCZe>_5JIva>{}$0j=Hhep}N5nXZ9QSW2q^f%6RzHy}^v>~%!Eb>nSz&Psy zonf}9TYJv>@3yR|7j`UKg*5N8Tc$4c z$}((d6Q3@+i}K+=I$s~`XRq^+3|%cqCrF(W5?)pjkc@&3N}wXL2Ymp!)PR_&Iz^KM;ZdzqM7?&ezn zPZwoF^;&wAi8Wh$-3wP1nXih3ipK+B24xU56tJKP(IDUa)zZD!r%#puj6x-g&|SkmV;xtP@1 zaNGku+Od%l6`lz;8N8#3ysIRQ(**JgWXROhCZYR)1)mv)3vLL=4_H)Rhzu2AcOO;8 zR!J*2A>n=Lt-!EhUNk8@omiGP6MYKmx#-_d6)f-E$VQb<_9}@RFy(Nhx;<%~78JY) zely_ucHl$^&sF(MD57Wix7R@pxu)PkM$>65YpjOe<2&P$=qT>ifui4#DF5`e^NM7(V37`&a@J9U`sP$+h?;;TY$~ z1h0}rx_;~wDde#vJYR=e4Le6ZS^f=KCvhENRZQrf?$29%c`o@>YkzRHkofM;6da?c z>-C;$cqZU1)`gSZoB$nzf|W9`_6|!)Us#VTXYy_lRnFn`Fd(_2J#R;%niPE|5^^lv zYb+BkRn^uTb+qtxE06GxGyhs#39edzwhrI!5cpBN=J$}(sxtJ>#{eBRt23H>PEnIf z&DX&O$el&M;}-a`(ax*tTfl|04Qj_-arFYebF{6CEbD|GZJK@Wg9llp2pL9xQ;_ja za}+aoslF0%DY9|Vk1?Ym%T!75y4syizN>C19+=7yWZ-`CxTloKV1_Hjlfej;Ibz8! zAb|+noLvZp=pxbgZVx4lcxukR^FNZ?!<dy?IAl@% z>a8*rCL0}<2>8>A+L-O5;5-)sQ9`C)=w~mO%K7Vga+M6UclShqV7m4vQ_oqlV7={i zr8e!tHC%D!g2cZBg2F`gf6Hi|b)qG423%@{QRLdgH_#vU!F4yYXy(QfumvF}^;3tD z*mp@%5xl~H?nh3q!piAazN6$}-yF(Pec#4kx)8OQ;pFFrL)?7Gt%ev=Umpl&saT#$8@HR#U0ADaHCx!MqH(H3t8_A+b8aC!^Byf zzE0^#q#D+iKm5wr^VRSAEVf)D^WKA;S5qlZ^V5g!*fIYP$L%s5W3QlaZP^an#v+3h zm5|HVMdUrUebX{Yd~9pRRyX-tOQp2xCI>0Y_en~2#j#X+0fV}Vp4F92t@gZ=vy|Z`+Le{YlFuRwMIL3DXd4OB0`=NFRL$Aitf?61=TfqDd^`Z zfl4xkALq-kK6y3k-#pQ(Q6>4Y_LJm|6;BZmZNW!{-C=e}BGPbwSi1t5Ip>FNwwYlr zw`I-Y4>dclkKyX`DHbZF?3%l)t7kpOrHy(6MQtnfKMjf+^#)b~-M=h4Dck1DV-fVZB6yrZ1Wmz(c6`8m76kNg1$OKVx?^h)GLIz_+c|nH^j!`PitVWd{nsB3=Gewc4c|Ev8)WLmsvzFGrLXqSE zX1h!JIXBKL3RBt9wqKhXT|b_y{|376yZR>9TfbulOw{yDXm>(ZRpI?^;c0d&UU zb9C-z`er*s&-LAKj;<$nsjokBbTU=^qG~%H`D6o|>foLYAlb0H;mBQ^&T_bU9mndO zF_hWPd+>B?Vd)mv<)QnGYe)rFZM%KO$P7zNxgM?gJ*t;Y?>;YpVgtK0C_X$hc+gun zvUhy%BVN4#q}22ew!%1CIQ6(%XCPnJsaN;&xMRHa4AoiixZ7EejIt8=JQV{8B*e_5 zOB^Wyk5zYOdwItxcP`Q=Y2FN1TGhpnzX@fms6^h0t498G01rQXeDviDjHImX6A#SP zEJbc_NY!2r@cIliGdOLbbU0|yv#e1AyeYcT=~yGS_o{wne*=%=nAk@0r`!5@^a=o$G9^!H-Stzr7_j;U+9yDi*rrMl%Il*=50w|sx zDnmIFw3Le_UZ-UX((@rI)w;e?FY!#z7!lR1o1l2}P~u|F0<+RI@|u?QN2fR{2|riLDGTkQ`_sMf zAs?xc9K;<1q{qkqq0-wqWGXDfZ2e`QBuJSiXZ90D*RsvNIjH1+BZ@m$ep#g&xG=FW z$oZ3^tPQ%JYjghghY6E?6L8IDJ~!hD3NHyr4>X3&%gAw8v{5MIc29d!(Q0z%ZB+F7 z4d%KN712rulY&h1oO`-B)2JgI=X?VBoBP>gP?bb zyfSzVRp+hO{8THuxf_w;H;WSqRz>^VRutf4JR^Z(`KqaxgcTAWMUfw+ni%6*-BFd= z(i9cNM-NvhRwHvy>)6q5yqb5E{6d5O#c;Q+B(Xxo=^b&}UZDp>i5(_P zMSil`bI@-OIt0#Ai>XuRRldFTuSU1p%zDzjM#Q{ zo5IoZ^&qJZS%1+n$Ks_AzmHd?{T$=c)Uml6->MDQ_5oYyCQirWM2ff?)Hy4{BUZ~< zqZMY4CG}Slx0gG$XlUzCBmmO?3tgJ zoGCZNH1x}!whuQ;y%i%n6g_MS!CVEX4dp1bX;U=-H05y)(>j^X5(p@;S;D?Ek4+}# z8?Sql9?iT{AAOm#nvg&#I~K1!`Eu{}=-I)lgno*uGI^KZ9V}n+avm#Z^*Gh0I@l6W zQEyUfVe^e{g@)?I2+s#POoh~EaqsFG(>lz@*-SQO(s%E@Uwu4Q@|0mdmBD#I5h3eD zVEK-2#j8QrG6pwI_2cq�r_U+*p1!C6_w z%7ZytQ2t!}Nm!qkLC?(S4~Tpa(oJvGLRPMWWbf`R^r)shel-|GGr?VB7DxBBn>!Z5 z6EH^=pb@vy(TwY?)eqE91d?>upGPZHOA9&ZP?ITseQwqgXcFck+!xJM{Znk4i8FO- zQt9Opu{Oi@`Y8XVz*30jQV7WHT3-B`LH(tlqOIt=!7W8Euh>)^tgGN%#ivoi?Vkg* z0h#x>*H~(YS1=dWZSSzQ0dT0xB)0N|9LKfpIYy*iX(uRxqXn6d)wkU#1#)>1(c0-! zp;I>C$^#VXM7h)YDV-Vf_!_Xi`O;1@qVo0ZUA=4%NBc%|%6|H2LkVA<7|WBd17OM|HFTc>wjopR1S@g>?{}UZ zIJYtU8>x0$?JkC>RstROEk>L`uPe>hlQ#LgMfQp_Iep& zU6CzKz3tibhtNPTBSmY)eka+p!JF*f@u7hZLHnUo{(8%g?>n}yGona9A3 z-EFS0y+*Ze#!?muroHL{`nOFwGFLLo6Q5abpw7?)Rax$AHd^14&+VT~zPC!Oc} z9Ge9sciTrvtEhl)$8!Yd``toCy5s6HZQ~WR*{4%q58bVv&F`tsY+c38 zSU`@~b9q2koGHGvD~Wg!m2z9)y^=0x865r4Ck0Ck#ZiLtdPN`*ggkbq4W+S&Wbw4V zg8Pki7m=bh6BRSasp|G{4N1^ZrCTN7%Q$BZ9cqD=`=lD ztklN;^>Z%CVok>9;9ckO-n;vTvHGB%w_@fhtbLW#P8xVY3Far&sWnHB(VT`-YVd%` zFyH0ahr6DKgg}XWCB4zKYl>pK_!uN%TpEf=eaI?aUVF-_vttxQh_~v;oA;i8ElKut zbr*Neh&Vi@%hh|tRo4R&Op@~&{iIN0-wh@y4-;|h z0WvI`K6zy7e0= zyVJ@NZ&;qJ#snDJ^ivGdp6ic`6(m+bHTX41@a_ns14oc)S{7Yw(k^dQ-*!oh2@`3V ztq*0Ua^GtYWkCyfysN%#Ycb6Y1)K?9v5H0no61w?iQ-MZ7k!ibo(FqN(jttPK89=uSE47w<(QHsQR6GiFNd>F5^; z=;(vNo&c}zYa;<_882!Xkqa7~!yb2P8F^|-QoMY>-5&c+g;DUE<*(>VxSa|jmmA%l zc_;LE?f_1uOHl>)Ey=n*PgUogo}dewMR{sRHeUKEjOn$Fpe#_(nAh{+)p;)(P2nZ3 z%x#m5L4NQX@jo5VoT1|DuH^?DAp zGA3WYNO*djv1YHLTEt_4_3S`g8uFO+-}n; z$(KaI4=cVf?VG0eRroWRh%$zR)GQa2@4P48&as@b?rL(5#TJaeibV|#B{ zP+d*WvK}@=(`<*HW;qx?!KuXuaSjD=aK0@+yq5hc8p9NmWbH+?4zR>foF@24rJG+< zJ*M&&^|mBehgPVmcKo&pHwtllGz{e;l+E1S^Nn{GVfBCs=YnYF1xr4=Yq;)j)tii*;q**JKfphNV zh@9#?Hie_a?mjv;=SBLXy9v*uyYyqWsg?%PsM&YzQCFnIN1Jty-93B*-=^2|3Bh;n zR%*hYuIuvGfzBL*#X?$};)0ywOF-(8fpcNg6aJKgbEggNYtIf_|Se{NIC2Xu5k_iat*u5(#07-BG0aWFn`OBPuBg*bxuuYpM90qul@P-os zYp4oADsy51m&G8JwVQ{L-(WyINabb{4CaPv4nkA6p%poX{>$Le) zUVVS8;F4aPd^7{|p*Wn=ibuoGR7uvRLOas&Zq4;0a@=T_DzSbqi$=sE$_KPQKPlm8 z|1B^%2Sr;d?hLxoSbrmOgM({;a`Rcg+r#S3WhL^6InIJONjEE`lz@VCmq^1P(j5Z~J@f!WoYCj`z2{x$ zJ!_qH{+hkko_$^S+H23Ay6?|-7WooG&5Akpb3_Pl*sjy=E)51mH@t)`+dx=IF2&aO zGq(2=e!?W%S^1_&zCq|1G1G$xw6%`H9~_i6vuj+aY#PLa&)D=f1oSr0B4tLFa=x8A z4E3}Rdbop3c|Mi&>;`;P-y!o1U^O%4J|O_-e5SfSS7hf;L*?p>>c?}e0og94M|)wF z$OOwAK>WynK>&j^tCkja)OIL>`l7Xgx)ygXLKQ3F^)U9}C%@`?b`9oe%KfkKH5%SE z8thSifu~AyQcCecYk+t^&GF5nH+Dw}R0>1YZCb)}+ewzUNO8NPPltY!_93z%<8R)7 z!HRO}d@+P*DT||fO;H)w<8<;VTj3)1Y`lD6@(q2s&JX@CREp%R6=TXL0GVZbp-sfu zB$bTxfQj{1n%R#KtpMfePF`ToBR_Ho*cvOCFt#|Uk)t4>|5>R*pVz!*sgEY)c>hg|c%p<@7VH5qR0C#$~C&ehMe!%JHqw?$B5c^$mcHSu< zwBvzM_vQ(bA>P6G{08?zh@SH#4ArWYh5Sk@Gp)fmIc5`972ti!k?oH&d7#@ciKM%S z{*Ur0X~}X#Nnx(T;^?qx zX}5~se3i+)(h&DnJ})#dnR4!-T&IXbl*lwOc~6|w_X;}Oh(SrGJ_Q;vk_h=)?%>%g zq{~q5U5)9@hzc&rjP&9A6@gaAhj`yrZ%y z+=d(kQa7}NAB4}@5jmE7^!M=@{p2G~;}7C=pk&A2BV3vKIcC zX|t!))QXtWe9&m^M#YgPxaVQY+LOr+ zIN`W#i>g@;H$JSi?%2V4T#UWkW4rRZ$GXy^5^xMUVsrCw?P-{7cnkl{>)M~}k7(mQ zNSJJN8@W$+jcmOHfbspOVCr${P4|vD4{6N^o?lg4`VvGuw66ErSf>H9UJ`rPp=<2RTT*2O{7Sz(%H8X16pii$hG2#aigyC!=mSTRc-DA z^zQ^yp}dm+jb5)d535HpU24kq^gaB4)9WC&Cz9=V%NuWAYHt&jO?AlEsS_wjV5AYx zVN&asv?(`NzcY=L=!y_@08T7|5VG?pp}3K9<9oBZ6^O+}hwn#J^9&*FTDMQYhlf3k zy#@wdE7{>HFQ1+(x3x1&%q0&}^;P1^y9sZDQ3dnn0T+&>fFpddJKKc{!1>Xxh0x9e zDm1-52b)e8`!cy@;Yo&^qtZXTIQ9+_ZY+Y`7B26C17Ie!dX*KOp^yglH@d;p69G43 zRGp7q&C8IJX1GG_d-uz4?-}Gd0MVJuiUYo9@LG!aYfgz79+O`vyX2`BbJ(7*Wqx_h70q^oVJSa5!m#G5#?v!q)USMlr(=wkz zlfRaQ1U~2p7Jo99)v>HO!8j=v_Sy!roVYbvrUaW^iCkN`{)b)|4#7bD(pqT zQt!|Bt}o|FSJtwL+s@iKmJ5J|an~A68uMw$ycl(f1!-kKde@u#Eq1(w}x^ z=M^~NHYn1Zq_=8W3+33WhGZ`8HnT09(h7A7zvY@5QU>>oyj?LU+dRpXjqa0|b!*C(;-*LTgGyTv5WGGYfMwg9FN-n2A|ek%9{dsQ28B^#uZ>BECH`HhAl(vKKl z4^sc3Q$bH+d^xh9Q5lY5W{1$e$*DUszNwg1JVq=J&*jPQ3vBg(>cY2|pDcXwC~Olu zRIaOrG%uzk zCT($mYS&|@9y@QQlA-P^%kigFQQ5Bo528eqyIxfq2#~~lvMQv>Dl;m|Sycss=d|G8 ziYz`VPi+1+`&Q%M;dg9!{3@TgjP)B549>IdC43bLKG_ zXdHbAMftEFHYg(Zj7L?Pm4<1V7|O&Av&8SU{PoqRPm~BytKy~!srRsiMA|5r#U71D zXq?4O&~iAdCX9G3OcHMTFSoC@9GuPm7*?SR!Ius0+5TidzABN0WtI^hH_}>_@|b_mFR+RkLL*7bmq3T(k0H4xwueV3 zxg@jq0W@=TOEzQqYV@H3h0k|}k%6!}3LRMp&GF2_OH~RE^u_`ZW($Osa`WWSDBM_| zV_3P9WgSu4T^F%3Z#0IrG{)#IMBDdiq^z*LBi(2`N;I;Mks@V>k@%k1`jJqUN^@%> zg)SBXpQx^56rKyEARK`Hek5NmJfBn!iQicX+6U1Hdc;y6LOO}oK0b2te<--MavT3> zIO7Ojlo5kG{N;w;dwX4d?>FZI4kN}sB1vMw;UB}q%Wiz(=hl(Zymk}3M?`iX?5!gi z-c!3;;-p#^M}%_?=fV5pXEEyeuoAn7zVk67Eqmvqs4pR%@e!&GV>@{X)PC{m$=1Dr zM1nTFcIYq27=^v@dIEBZ)E_PE=8M0hjdn}BD7a`w%xU(=*TWy+J@HqpvDX9--zvJk-Zh+RQ>oOs`EpG9;+76o23PariiB{$=zjXvC zbqF7EedLLH@A=sl(=|O@p{YR^O1M#N*q$vif!Z-TJ!zd13r#M@Q=*aeAGQl|NW@;}qfTFOeRLJ@a#0+_cGo zq4FFs>O9ogEy%yZJ-If#Tt`^dxwBw;z&@@;kgHq;1-cHnwyk}#+zb0uuV#jG+qgLD zTnsxJn%|{9m@K<(3Dx8Y4E82Pn2!2{lroIkRn;S{$L;FeET_qgQ;~Vv^B;{70ZSP7 zGe%Mi@86GRQJ!tTs%zKtyzQ%7GC{Ok)ua{YRUZiTxGNaolt06H()W6mO0MhUkE-WU z{^Dwb{&6#Cof}@ZkQJpgo3<3T0d+~hC`bR70_EkhEi}l{GQw7e4q3Avb8_~@sj_VesPk&TA^>Ry zbws!eH|jm3R=*Z=DNl*}db=5%LPWC@Xh(8n9J(zX!EwdC_muQS|A)Cij2}z4(%8j; z(e?SIH&y;52^!z{;5yZ8r%NPEuY5MM4V~DyMS-~o)W*}_QET5rgw9pofvUUOUwsD) zxk`~pCxR@$hnO1)l{k)0`rveXg!bz6hG2Jod3Q)oK13G0&cX}t@pNkejF=a{=!<=k zh9`hWZosroUE#bYtPWuWdENlliqH9Rn6u-XIwu<_dTSvzK^v%WkD%Q<9m0UwneO0{ zT21}is^!vy0Ga(9`VvBGX2X#o4E;1y)@jWwe(5w*R<7gyQW z!0RMfH>S6Ixg(uC!=T5odehobg&6PR(vPm#3{+!--IGiC(Hlk&plZWhHujzVFow70 z&muL&L>n!cG5|TNWXO*&pHjkUvtF)nxUZz!QSykTez5ZP>?f{rOLC01n8diuo4Tw@6#qG~heqg$wzA%j-vuV$Tj>ngeX`;=lE z#AWJ2=1UxPTc0dUk$*X4XmhUI*IRX^lR7^+KJRlZ%`QF^lj+zSbH0lyqcKyFZRxg; zbDX-p@D33&1I0MO=7TB+g3<%N4Of_-PXzcYW8M8mXyEKOHXCR*pd{laLm${p5|PXq z-sO?U65HkTlfp-FW?cnj!yV$RvIKGztGn8Z^#+lhp=O zp7m8=Ztvj~{Zqks`wf#o>_KN?qsuA!uKEu18RnE*2c+a8*&m|at&((3uLv3YY9{bK zZpsp?c4490J%(jYsTzYX{#b6yV_hu8pu6HJvZ^Bkrmi9;1{KvQWtlr8@fpE8biu1% zKFnG#vyOjUt;D_vjUK+b_v;&&y@DjIlEki(#Q*y0gB?f+L8+8Jy#8{81flOpu}r)* zQfMCc23*%RuI8uoIeJ~HN>>Y|@-)dvI*V6NgJ^T8)s3dz{n|a0A!TcEZ7$Vp9al)p zqfq&pKUhxbmNN6YV+=pP=)}R4dmLZQyV<>9+&18ct2DoI{`uPane$(u{Uzph241NR zAzEmcX$#|g9SXSN#inTs(~0h(W$Ym%cyr9(hM{RRW~VK4mv#1(E9Xwjkm0j4NNoPM z?o^EWRLsIxvWhAEPj0=pW8ObTBw~P)U3?8>a@4jym>KEGmagpI2j$HUQqxXa0S9Tj z-Vf6&ARC*a=)=dI)g;(7=F_mF>Rs@mVfEbpxclRwKPF`8Xwd7g=fOG@%th^lf~eXz z&_}51H|Y2Sskq9aA^&_@7XEM}e=A60!~Qs5m5M)9=B6MpIte*J|GC$*CQ7a@iq@gv zoy635y-v{|qFon)qgS2qseDmf3-rXODfeVp^nKLJ`OK5{^}w+1+oyYE383l(kVm$u zQQ^$!>3ctGwLC$k#*bigkb4k%Kyv=#B2KuURQ)rrESX-#zpExgGsHhra$j;fO zl2+g(RdrpzlKuIcnH=Y7oK(IHyWt)LNuc2Zj)8a^+68h|yf>Y<_Tb)|qmOg4oIa<5 z*Z1YuNXtxr`e3Kg|Kk&5Uj_ba0NGN$u#N!S;w~FefvZEk=^ChDcYly>3Ap>Wlo)y~u9Q7FcoX!a*YkZ-b{Bon!(om{=t(sN}nk z%{O+UdlNLR$yi+z<}dzi{G|JHE@U@x{>agi-^@iViX2$A@YUX4E8vsn0C~N7E3>_7 z2}`Etz|&kojLF*(asOe;)Hxc41pA|V@|o%%4)z_W2Zn@XzZB8#8ft;sbp~Rv{rmf4 zq{o^-;wRhAp5>zx?9DcF4TwqB_kKfV+Sd*OOyvYK6d@ec4;`o zJcRWD|ET0BbPc5Qc(1YttA7S7HNgJlo>2JUnQ?T#wM@UYvl32uDM>SFjp;L3PUen% z%D@%%dEM}INAvdXrG87sUHA$2MEsq@$+vY4L)$f8k!6-lH>=SGF~{~Eh}80EsN30y zEXnfl3e9cZ<~&(IyR`86=5>#=kLDz*lvJ6AGIQR(sWU0F3SWSbl9(qo#8H ztVChI!!k)L0*5&naz9R#%}ufJln<1~k}YESYj#~B47R+SAwK0#&crxOPyfz}#-ikb zYeSdXyhV@5j3!OLD^_a#(>Ry@91*FO2bHxCUOR{H)jphcdCBS$P5SAHBVFdT$eM4X zF0Sij7^`=uKAraKD7VQ~R__^oI{nwUE|c=C-s}2wMz8zk%V4P!PffgEspPyZ*VKEh z9AV+~S8D&}vGfhA{;%?0PRv`{UBB}^N#boe@$*vVhQGwSK3!!Y@od=()t#3n-k*~s znAS~T!)m>mG~zneH}q72@16+m3Z?}`{vIVq1W^%mQ!_acx_6!#eJ9yv%l3|xQD0Z& zZucY}4xGxn%!iTG9o!@0scU=nEL8`H2CNu*Rekv`Sz0G>1{IHa?EVt%r+c~5w4lGyEB4l{hi?>8}w+i#dPMvqE{~@E%C-!Xm?g@x<-(-^ERFx z!oOQXl{%^nT1+tx=FK9}0?CeTsBRW$u1TNhfD4WsD*5+Yl$)hDr@7@ zM^#M0zCrDROJ|Em6(v3b!b@k)t-ITP(~=2J1(Xo(ma`Mh1wy5X89pI{Y?7o_E27V$ zb5L84+6t_Fi7&0h-*@|uB^D}RsneD|bg#{DXT3ikOZ={2&f_YF&3aq-(^*YpY}5EhWqK+S`M z4#T0b7~)x?gvw`nJDO8=Gy=M~E<63LiRqJ1i#1cGFh;Zsz2&B+MfiM_xUuZK|H9yf zr7)MB53OjkJ@=wf@g%&oU?Y2?k%HzT zZzX?;%h}H%YdtASD8oH_~m0^qD0}HNJ!ho;#5=Hp>tqKFwZi zRhP%?y!{1sYCFo4_<`^Wo@_wiTn6Ik!5_ChfxStvmHG8guvI4bznkrYb1GF$>V1Yl zi`aD5Q8bsIm`OA8a9hHB^X3(Qn{)V2`cV;YZ8K#%@8Ks?fp7KMcS%N3-8Hv|KY41m zNwm<*w{aZ;)%@DgidE)%2Bo#|6&knhx&+|1GVo8qvR zkqx5;BiVur(>Hi$4Au|_9~%3SgJYs`lAQwI&kqtb;Pj$9j+m5`BQ1g_H-Z4Spvj7) zO(XBI3x*SDK1(mZQNInG>?exLsivvxaHb^E!)(I0NZyY1k)*m9a94i=!{~KW?89>&sO1lw0T-`^1|k zB!;t;aNolHC{}L7-QM`qTDYi01n@c-+Tk=! zP;!9@F5$}UC+3w8WY{k1HmMgXp;x9yl`Xw+R)(>a=LbD)15K-poQY3WlkAkR6%dd8 z-b!oZ-A@DlXt7)Zf!@q_ExUP+Z3B7OpeoyBa`V-a2uhN}uvp{=9_;(7 zcP*7p(lP_G;}d~z3XY4~cA$s$Z6PJ+3ydScYpoH^Pfm#2)Wf|udGMz)4MR>I7RT8J zw~Mz(^UR^;67h&R1f>y;g#GDcnQR3=7ny5^+d7~OXbi5r;xy{!nhl(E4K0srIa7=b zS4O4<0$gf$TV|&HDiZbkW+qSk@rZ|Ce3v80tVk~GO7D&`-ovHk`QVQ~oxb;H-`5)yOm>i2j@k-Sav<(d7-kF7K7^^< zUgBQMaq6T1^Pq0{n@{EF?|6v!4m=qRi#?>TxcqvoDt$Yz!!`=nw)yH(yH)bM>q@XF}WQQxC$k3wC)8>(BwNLf03+tpFv z1@J;r<@#Z`tktR(eUxk_j6|B@_80xN%0D_hL;y05d@c>&Rw}WxZyk2HEJb zOh>oET2cL-JILNV;(6RQiWuY ze6JP4X|Zfk4W<-;1k@EzhmK1qYSI_xn@ou|6?TZ*=VlJ)1KSW>hp5-_+X4wyk8V>4 zI$)^IuODmTdLoroq1ZF_0f_R1E2zI&hhtEja?VEG=2I~~k}jweHn^X(%Nj^dE3Dk5 zbMnE$OCUddX-hz)Ln|fsjmYgW;tY$RcvKLp7?`mwSyRhEsvMMfkBmBv;4j`DU%YTG z|3RD(!x8`Vg$$n6C1dm)mH-2G37WE}l;}f(N_6ff4tzAezB2=wyEAuLB5TYVT5e&p z76l6k=pfzal2OEdPYmYIEp^=v#d*)%E3zDy>Ga3%)kycpCu>W+t7rL zEu%w9+l%>ZYT*m4KbLYzjO^zlWv*-a_p(ArKOf|n*>#s{jeDibh1XqR8t%*G{gP2v zn*f`NyCy2ClDnMGw|(kF@z8?mu{&%L`$+nlj_9AaNsEZmlicW%IkRdhLW$d+EZ#H! za-u$m>o}OqUnHF%=rs^x!v$}TPO@$Ut21YzI#1jgo^8k+%Xlup8xhz|B={pB3485c zkm|nVFeu_t7U}}%&am7K+A&Q;(IU}nobwkB-gzFJByPxzZpxfXE%cqcL*Rdeb`DPl zl}51P0y_y1!sW>jKz#5buu)6mAAp_Rgy`)7mip#G6#76LAS8(XAUUvcw5L_GYo+iHf4^b7L?I@egD}z zYW)c%)z5W+HM3qG5|5G_1Z7dBYWID)7Q6i{{qM<*mQ7k2t#6UbhHouI$-Z6HV!238 z8@^b)5cF3aH%#Z!a!CBgZ;zc}W}A9%SjEE<=j~4v_~Qrta3eyw3KwaiCAKHNm&0^! z^R6vnq(`@US$(eMk%N zzsDNBleV)Qm5i4j{XrkdvsWcO1LWr+4rGs!PO<cbMe&v5Z72 z{ufRlPsQKb%8&lkjz0M-xRb9Lx3YlkvlrwG`EZycVm&6aP>#r+Hz6@uIRQnRS}-Ya zUdGVICQlK11J{&ZK3(~6{TL7Peme#Bm;0S;;5=V6&yEO-{Zr(pwE`_u^k*Znxj z!dE7xPw;$Kcq9Zpsh!&Y01z%Y?d}PGB1g#D1Ry6CZ2}ZRncp5nE8jbioM!aqNf#Ss z#@l4XHj8sR#_KhgfcN!7>KYHS(181GOMGF=Q2$1fY!~48nWG0N{h?d_H4n4@o~hFB z1zU1i&vYFr3E80Z7j0zI#qCg5h$n}Z=Ku|gaM)XJ+sZVX*e^+fQS_YBb=G`+q5BfV zhT7w$Ppv2JKQ$!|1)k6=l;T++Ve z&e#H?Y_(H{@&sD6xZ1F`qilX1qv8wWKpp~HDua2$Kil~@&lTx`kdMO%!C2&y{V6%| zDHm~kih9ccI+E*`$I7+`qhmfx2cd#~FlEea5Kwe5n0Q?rHz@)OonFx={$ZV#%F@as zFD~4J)-RSeI-U;a@gAQ;VtOCUg1{%^)x2ed!U}lalF21%0HHfKV;Nf0EhagPKWC|J z6(wI!hXeg4rHr!C{$l&k+KApQ+Pm`*+?ll%_DK(TJRD%pMJNoeNDN)Docq(pVHHd(V@%HnhV~T zKo#JJeV8m6(rP1=-`_g7>~2J&igyiwgwciqkl~t0VDmEmPVi?|vJMD&(*gVIMJ-6k z<50x(&C8<9KGherJBHf~-$77vFr1%P0-kS+^y24*9{79uXi?W;>#3Pqq8FoT)yMer zU)M|@45$yQ<)Yq4MBGImAp38Wh8Nw|Pus~RP=!!m?l`p8?t#|Y0SL~P<*mRonKQvP zt|eC30swB!v(&R4R8n%HsJf&VRKiE)g67icCN2%1AgnfmRE~dMheG?#w}R+x|6{sq zkL3)AKDDekQ5j4eyPVPc1GQ72q4w>6p>`o}89W`rw{9&(C+L$eW3wG}?C;fnESZ>r zzUI8zlP4}2$0Q&*Zn<>6ePc>+&KB5~g9M~O84mQ|(S%D%=V)P#ZUx;#mz7n5!_uJ2 zxi8?%fnG8P|03?V#z_u2-~o+X|2(huw+9=SZ_amuI)7g>(IzoWUosV(6d^fn#Wx>A z!~RQkHzRyT6p#kRMP|FbCHIyQqZ2s+%1iVX`SH9p=xC|r`ZT_}$)(fE4kkpu65^71 zbAm3%2ht_Zhx*eOVhil7v}nD%(|AWrmC7wCLh#|wYN0YI{YmJl04Hr{bYJSDss&%H zJ@o(mM`?$A7-~%XtF$jeN{aezrK+2Vq+*8TIMR=lt@QpP=-Z9zn*cUZK<|J&kFFt$ zA`fhN#5RZ|{ox>8x;T#{H%}Z7CwqCX}ZdH^;X_ex*_j7C3f zhnua_hO8UaDVm5tqUrh40JeXRwU(%eF!Epx3L#GA=6NBKKEUpgxzKHkg1!2;cl{j6Yp7Kk(EDc}y73Eb^CrV90Rr*XFvCOf7_!4G8 z&-c8{f~xHwspY-2?XXFN94R~(!ome$K4zQwTJlC_UW@1Ljh4QeBRRS#j?q$;D(mtC9T{OYD!VUQ(E)LiZ2O?tG1V=)Aa>aRGj` z7>}mcJAr>`btTc0;~?hTR5xtef-H<2HF z+jd)2i$ssT1uw}L)epu-K8%lKyZXFt&b0T8p7HGozw9^GW1ga0{A?%HfH2y6h&`dpW@{W{~w;#PWcxKCPOxL^SE%;xX zeH`8RJ#RtQ!`(!h4+|d5CZRCA{qd1JIww~3g$bBgi<=L{c=6OoBu-Y9mV6o(3uqe0 zo(C6=qT{cs_dn~(1f?^P0@oCy-1Yl0Fd?ym(dknyB4R)fMq+#R2*F&~a4c4s3T^Z+ zCx$c_k(~!42eebyBW)8yWjS^AADz7WO_|8sSC zb7UDx$sBa=~EuItJi!bJ<}3S!LS z(62#^ALzns6l6#drD7-N|MKj_&^%nSY&6bJ)er8XZtzgbjTNlMwdY~~dnV%1BlLVH z$2W}(qVF_%ik=RG?(X+b_oIKh^Y&#vCcz}>3-9EjXMwKCM{32k{Fd>cTgH2-#^l-~ zs({wddqi_JgP7m?qdj&KLw|V-A4H}RDsYV^KZnw0OZOs0%t{Pf!c5ljAqLaH*rplP z*4mkA>+QhL-N36v!3u=fiI^(vj9Jk^BGGUa&EX$(8$IR4^AmuC#g7iR2*?2cqU@|q zIsuFyX~H5%Sv?B|2p@e+Grm3~PK8L9Yg<8LsAX7rqkpiC9_&vb1`qaGRGq#4+%M2Z zx&VN}7O=TJ@dc)?$o$6Jjoebfl>@`0i$(+ zQx={VY9MgX6TqmJZj#R$JU7;j@$&$s z++o|o>>&VAG_0CzO<=PsVu)(qomv~9bb(HQP~?fr{b~DgwffYQIvu0W7VX3*3`up{ zq5~qdJu=VLlw-}mbFDkJeqWRIB5ukJDNn4V5siQ@^GJ2w+ zjZYA@qCc^?s_9--+>Kby3`t5~aNZPWwE7-yv6W`yOCsq{^MmV{+vba>;7&vOKEHAQ ztx=RwE?qC*;E54_I@aWdoOC|z7c)ZtUu2uEHLu`ulO7#qBlyI<=vj~#CJlr<2MQ-C zrq8znxLH!2s*1%jdK$<{462?yWsNuZ>9y#v#5-}q1o9D9ny7Ke)lOv}jXRyyfT;M3 z?eqN5^v&NGbz9u1OJtvNF<|Se9VdMuOnJ*vEN`v;erkNBc5L8EE!+c3?s;uI>*3tj zF3zIwZ{+?=p$ix$?`dmywEnOK{ILZT^h>SSF6L{Ewl~mj!0??9m2~Oc7qQ4sAoZo3 zUv4rBp0DMcEC1g-dqTFrXHnG(eW2LU=wx;7q-zkZ{-j~4@FN_*v75eG;Rtfxa>5!J zO0ny{Gb73}P_?lsmxiQeV`GH^*R*HOB>qv|mx>}lNnrJuWJOR&-b=+hu<Kq) zbzJbXve{0PNzjyr=6sgLQMWfT$cba@ZnJQ^5zwe3+5^BcCsMYX8iA=0Rq{64UI z=QEA5y~Np~nrcoG9{NYnyl*x+qxU0oC+t6EcH()8>S&vTvFf9ZE8# zCf)jvL>@d3;P#D}b6g4HczH; zR1mi#tx)H3WxcO8>(}{6`i$;DP*IHr4#KJ~{X+FT`=Sb*kbuX)iTkCfSX-Q`)F+^; z$vCwp>l4~%M+i{)cnCZ5dYVGR0Wq1};J_FjdokQz3HImM+#FP7kGwsQCU^%tr^)Xs zZg2ErBWSFp2qPOZuF6#a`R;Q@arudoI5Isp^hp$yfP0@|QM?E5KZ>?MUY1Di>wnq? zN=M`fg~&pZ(MG%RU!z_33u1Y{tfXE`1WmL{W^+kkC4lgY`n+0W3* zaEspjCEAmbgv06g{Pm^0uSgQA;V;ubEyhE(@P<<+m`MlhS9$rJKpLl+B4VYpgWBVdkiU zIkoR4V&m?-8HPn5P3>sNE=Y5{DjiHh{KXYcfOrbUI>Gqak_AaLS4RoJo!7>8-b(7m1ijd{@De9N2d*b?il66cH#44krYWH$wfBAxeWV=Hiq`f)F#Y&M>c5C%x5e*Sku%j`ZPWZvM)U!9z2U=)@XU4 z)5*nUH8s#6n;BF-^_FQl>C3ZaPaT$J&JE9|2^P3kT-rFN&Gszn2^(x+Ry47K zFZScUcNBym5&@j`{8RAkm_Lci0-HRe2Gz&492V9v{u0ub6rNy|kq%P@t%}1)ODy8-J7Ci8EF{a=F zW;Rf;&!}%KS_gd=4Ig`X6Qad`?C)MM0u+`Y*s`sZ__^rVI5PucvPQ<_J@VmhA;I#4 zrZn3%7IM}aJ&sr;T-XoB!pTY@U`CYnd|^2@VP>ewcrvdQE1IoBy+Og3>yY+t;+H*J+5IjGon5{>;v_1H;c_$5+N|Ys>Z&|3k*Ll;AV%u6L8XOLLtrOA{xHmrhhi8AVS@>T3M}aaZ%j01FRHQvE zn)cL%&5)~M=y`5NvTYZA;Z2tRa(oEOJHlvlEE^YqL}E zoXtMW3;x<&)V*Pjnf}TF^duc{G|Jg&NmA=-4h@pXT6isi-5Bom2Dj{UGXpG70Y6r{CqGcZMBzM_WVhU=U;a|X*@NFsnikJP= zhb?r9liH1+et>RKD7M!1$+rT4=tz}LK2v(2A`?=T8;SXLZHK4YkO|Zwm=UEguger>9qcDy%!+4%mw6MsR9 zNQ6xC>{gd%yQnbsdq)!Yh4QKJkv1LSD>siyvt(rtw}|qwQuj*d?Sho=k2$0|Fh6&; z0i!XZUzS4HKI>Q!>Yt>~zN--?vA-`#Hgnd(;?W|J-u7I#QZ9`F{ykylc-dzEaNp;= z|JRS70+FHHH*!i`>G}Ef99XU7jF|Ny@cLwg6G7zzpp3@A@5@|84k;t(Ej>-jdy{Tc z5v5x%8olNcTFda~7PssT^8Rx;8=3QIq4n|`PI{I8_)Kr7>TK@ci0u4+H3a3zO$ZK* zI}s)!2&SvwomPP*S($EjMcW>of_K`!%n;Yk%S-O3%zY)_6!I-!#9z0!MnmntIz){z zOV^X7*gDv`4(_)ci}Fc*v$=N^G7q^ z;X!+2VWd)%=G0AuHW^}3XaW-V)NU%uRiNnvVA@fm_l9qX+jl3tfj-XRjuRWO!Dc}1Iva%XE zUdzV)Q=uoTw*bHw7I`gTe#z|_fzlyCZMFAx+ie~#{1c5RysrnqCc*jg5mkK&ajrKtJvI7!6gckr6bf~G>F^bc{3 z3=Pzp<>%$D&1ES+41H`e_buSPEe&2Y75DBi_wCa>BSU%X*g)^UXTLJ&oraF>gKAzR!iGWRZvs zPy7S%OB7}S6%6fCJNsnJ1Eo->$T^Cro2lQSSC zxot5>L!3P@?SX_tNp`aQ&U77Li+Efo+^Xp)#Kl8^cf;mDY}VsA1d{wXF8 z^W%vq8I62#Xqr9jtjRWSAIzo6HU|mk3V{-{n>4>Iz3Z!2TMceCZI8-o+O!L-6j%uI zcA1mt^ZIxm{aL%Q{HbjpRRn$V|0)T7^#umi~k0o%{c0^V=t1FR=hIsLzProX_iEea*Mzy zbaJHo>R^ii{XX@P%VbW#QEWVk-KXxJt0D`kTcQLdv7br{(r|6RUP5ewgA+`P*vyJl z7M^u+yo{i~VqmzsV{bCLUAo)(74kIyi}&#D0(jmT^n zYMh5&Ij-B~a|kxIYb$u@k~5kxZzDWa%qYxe+n*7FBbtRIMDJVa%?-j&&%ID1n)DK76o2f$_JkgtJ5?mJ)yJuP<#&cF!@g# z>4X!mdD4@P7t6DcfM0*&k=s)o+Bfd|UiocWlSq^NC<#<;SiC>LEpo=zeGke=$S2uG zViyWAxd^*bn3b zE`hdtnU8v45Tx35n~O-!qlR>$z56I zfv-;-fx_wScH3;+Z$DaVl`ZAi`mOD7fJRjtkczyXkF2GkBIWs-_Z081_a5QmXy}Vv zY|}o`nHoi8`*$rj#zB%FLt3+Y)HVGx@=_|0bk z_GZLd&fCM4l}Q&ql>s06)8}{a1`HQXr#W;_f6n}N={OO`*Y5^#`adNPr;lF_=@wWZ@(-(RgO_P;1cg1Mq_CNCLuv4M z68tKyT|QuD`NpqGI=%S682js>w!TI2|1NEDD_$H56e#Wv#i3Y%;ts{#9opjVZUu@J zhvM!YTmu9T?g;kDmut!eyOK_ItE1CFVJC;4nV zzu~@A8p$jUjE|U}_o&zCrnPs&PxLy&%*C2fD?MuNEEYb!pA?jNaVOLjR7J6ghOqxA z6E^CP{^%_*o`E*@0_c>^gu)!c?(-$d5v+6N&}|_foR?B)Li%Y)19&IC<)@a4j$*LL zMSz4qMY7+(G1bmpg+_gyZDMhBi^+RHYG;_E$E(-%8(SH>J@zNqVOH&Ziv^Rz#D|!U z&P`4^u3!ShBCNHWsg-8^v6fOd@pKnun6;>O#tOVP9Tj0`e>OOFM&F?vV2U@2qt* zNVQ1OciK9Qec6t;N#zNxi=#NLn8l>mY4=P|v6+GPsHdzrQ2lMUvGC5W~ncDet!oOaq{U3m@s4{ zQrSvjkwI~%Hq-KqY`gg?Q+m`u!LMP(DqKSN7W3v^ao&lfy4GykX;9!8e2IF;>1s*6 zmbYG5rM}BQnREU1*v?_g83Nwv8A8I3*%bQ`>Ua|0)JurFZr80Zh6lcq^m%DGAwK|t zql`r5HX=FWCDOvgDqv}zd1vy&L)7g`)g0f#l}zImJI(5$r$f{@2j;oqnbh#j6^!Lc z3QJXtI?ZI5Sszl=Z8-d{@0IS>c3~KrU?fy<~i4k1jrt>8u+PmJ_QgUAz z+`2|ZE9nBN@MRH!K&3(cn=L2-I!a7|@^DR9e9u-nZ%Ha$pZpKhtE%YqkdrS+Hyqfw zxT~@pwHXJrsL%KVIP$NQy-7m%`WJ3=?R}&pFtoKz;GtSwqx5YGhV^G}jH4%OhH{v* zzt~|e3I?iu?!p>TV-iE-vD`{_I)Q>@ri(HSee8*Kb@w=4@dB}qrT)5}ag;gNA&Pm{ zz=|aT1GTDTFApC2R{XR%ZXm;!@MC3yP8uZsF>#Fhf1WTWaO0aRMdjzj$> zojlX585oLIz4Ol#RIsWso%m|^v7{Fp{>3Stv?OXT1L=+d{be#_6Q<5&LV# z<+>Ttd}jom^IM{^z$okWS3t%kif_}&nz6seqmP|Te;*OshSmOgb?})mV-7_~D89RUo*x&{$=vkrSftN-U!JB~Ii0Do} zkIO`J;)m3Q2AjK2-_V#`cgH2`n8eHP%HYY^;Ua`8`HR#`63=!gP;=4e+LQ2_C(eFA zU`H9T%lwiJc58JN8%1`CL1IRKnaho4d&oKcstYNCfV;TBDR9&gKbJ>YLZAT!SE-4p zj`lsSp!7suqxHC-!_O}2py$x&TLI$UUjq?24;7BWff!f?C*x?npVVR!;$?i8=iT>* zJhna_-MnkolXhC?pRXtSFhMYSS{)Um9&hkAb+f2HO#2cFa zvbS%oy``4P8CmCjcy2VNam6T351{O*xb;1pIIjcO?&7fjK#ETiKbJ3f{272Qti5{K zsz8@O>)dR^rFFVZFqQX}or-XJ^0hu7#lN{{100E{(@iRG3@IMC%n)xvT^!gpdNR0} zx>xbrj^YSxFnT(FO_uXX7S}#*kv*-G2J^HgGF_Ym+0|&ee`a#<#aRkvZSBwn2m;Z} zW(IHA-bw~m8=+pk2z=1SSes$_4qfj9F?wjU!*Jz$Gn;4<(3==TY4*gPE@EQ>AJ-4J zei%GoUc&|&_S8nY;>EwZ$%EwO_J`Ar5Z{D3WGyn)4Q@EB-o%`CpXnvW_wUIBIu)9| zgjWN|9zgt@UIKDzj2@)NtcyDPamQxWy`U(^%FgHc8_w>KX+$y0W2{_ybq;o<_=&uO zNyQj2p&v8QWqj0Z1rM8}V%LI+gbl?ry zn0|x*l`auGAR}@jGHvEVcx85qAau!|SdL<*Ir22+nFwCCaM0n=yM<=msz_cv`2p}r zU1gev*n|0vb1fe}dkhhpTgKPWYWAMU+v$Na?tpDaLsf@H4Ri^qyUx&&mycNaoEffJ zGnKVCF18Z1It<+iERmhZ-tC8h5LvuI~cR;LNy+8^Ig@?6?f`ysqpQxIifTL9R7k>ftX^3B_D z)Y`1{h>rfEEzNR-=PbFz+N*C!?`-s-63;D>u)}4lQCg0gZy5ZjW=yTG6?wOIW-!Fq zU_bN{%RgTPV|v$3P4cy1&>ZwzeuIq`6Ef0ft$}iXp;8SYEQU|oIzw(xu>&6-wH8>;XCbp}$MAP@XQ8zki>Y(p%B zbH5+dbe*}b2kefq+-Z%u*`GO36STOo$gC(Mik+NA?G8Pj0hH00MiOGY6`Dv9&XTZ6 z5Aobpy-Tj~9t19j8E2ybltU@uJr6(iSnu^L(?XtGkIkE|d#11F>6(f)M;=u6RSlpRpY6T1NN`3@=Y8Nf_a=(BUq(_vI+);6Q8{V;b_e~;E%dUb zutC_jD(NcAS!ZWM5Rr&?JtSp+4>>mJ4<%km?f89 zk*?_LyLseC-wEKmy-!XfQ#VYcWMw-Tze*f1WZJ0M6`pXpWEwG}|7qvuyXF=$oF!Rt zX$k5&ibDVz%;cRItbcpB7e1)jJLz*V6o+~7(04`L@q>5g_OBP9((MaLy~&QN-^J>P zd@+_u;kPJ}P|WcU6iBhT2d%_ik$Uq;yd9ZYr5q_0_F)KVIF(;=hV}hVpOZQg#u&2s zEo*mDXz?W)uC?>cv;`wxaG>_T17B4bN*WzgI}Cnk;JZ_;i(_T|Bq#a>OKt0B$pBKG zPWU_3sV)35?#Cks6!f@a4!VG-UyLF8wkii&maiJVjBPUs)a3fyG91_%%j{_=n`(PB ztgh@YEa2|FpWWJ$sSbt>mu0o>%uT>Y#|7N4Y6Kuo8S0+U6m@LR(Xz0T?E7%n!_7^X z!)YI7gH!qvij!3JIAsCI#ok<@}Em?O77}YllF1( zP~TDUpOZPax(A|_L~*Vi;bL5V!>c4p7d8}}E3y;?_p9cVQfr>NTofmnIFo^SP^!Cz z`!(?VV+X~$f5%>}{@r&&nNj%2lhO+|(O&Qg)MvxXcM@4aXc+(nFiZDo{r7-|1CzrVi|`uu`E~N;^9h} z%~EVd574~H;fGlXkdj|^7~voJcM{Qj39VM72b7GQZ2KHfyKs^Y0q?!jKc6jM z0aJcuzt091RCkfH?{aIM9k>KW5Bld}2XAh3ob^qqMJh+=}+Ls~p8Y;@o%7*eV)_Ur}T_XYRYJXUKD0E%$r2 z3(TKveCw-UaX>QJViqvj=tyMMz8g=&O|X7R{lT@HwEq&bJ!H8*m!EghZ+Q2OD|bIe z1OpZCH3k-aM5bOSSNh#j4sXcX5!=Jzq35_3K#pMegk^moXDtpNx&Uy|_19YbiM8{_ z3{n}i>lM*((OaJ0jjp(%q$nJRYB(fyam@BmK?ABPtk;ljQId643QMZpB_7$LgA#UX z`{vROYWcNXDw2TTY^4QUmDVpbMxs}L9Bgz{8lNQI--u-rbQtoF`&?$qjD{|oGk{~meGh&qVwn2qI(#)dms0A7I?F{x$##R7_t6_-St<12Gru9mII>Xw`3H!WSk z`aZO3+dr!(K?&ql=ii{<6+Yc5Cs&L`^J$OeEtX}!HajrOvP+xY70dFb$Fge2ap}5N zq0h3eQ3ti&Q90jNTYpHXU1fFS7@<0|jlV{?&$6IV2b~_cyy@$aA0*W-r~1&`8NTCe zY%I-yp-6rcs53IjDjq>IELEJEtih)bsdmIMlt>b&@|dGEg@KoUsBv zso%MM&{ljI<=z!DADD{}_=Nd?cN5jAXKJGS_TmL)6bk&mcKFvT7biscx98^y%`pcc zKfZyU5l%S54s%7_&!08Z7H?*lG1HS>5m49giBbsqQ@B0wlnwqEiTxr2tN!^olMzDn z-WvqYE(ab>hzfjXqZec41BupN@%s8gAg_cJs-TG7H}ewcFDBZQ-2BmDNjsNgad?e) z*C$8b3w7n#MmLsPBc9J{71uw4LXVhNvR6;V>Ck2Aqpw^hBKib0Vp~$CgvxTeR03fX z^~~mTDDphs4zr^5s(*TPYf{v8PpKF?ZO^|GcGGAZo$)o%qs!sD;>}418WWgEj?BYY-P}49<+piMvbet3S_{Jc-pEl^emTbMLED zs(_rkU1viR`IKUbY-xGQyvK+4G;Q}jje&>tLCmcp<31c0^$d)%dVm=2mq)tg6afGh+He*oAiVLstGM)48`wX<(JXourM=;pJcNZog1FK5YDGF za^;gPz?F^C_$tn2oy_hu>tU-W#e^BnK-=L&CzWwi`@`omAQd+xVWyXAtAqocMAlf# zt|%g2x!ex9(5RPtefx5sey5K3DxC5vJkFb;iK{fCKwCXLZ;J=ZJLe?_7U^a<-N&_`<4A$LHGJy0 zZJV10F|TyCE|)B+*VXA`FrNvKb&;42R+ZZJbGjBkCfkuM3XuyRAuG;M zOFLCn=+Z4$$9IM38L^s?r|vySOGh0x(vSC$pA7as%q^c|qdp8UKL{sdKR~q^2-vj_ z*AgsIHT;7_c0VPz<6@OFE4{S%H5APuQ8cAo=#kw5CHriCCWZ5-$82`q<|7kjGiYdX zI}YM4B#yP>_U8(p?BZ})aEoi_&vaYDjo2>N<&1cDD>8fjhpNpCi=iqK4iYaq5?ReH zjxMJ?B#B@?3}5!!ciqZGLnQj71)G;0nq&imdVFN3cnnoLCUw5VoaNv)aGPwra&NnSL&Pz371J!Tam}o(X(p{TS0M-3B=M-teFlXd5Yj5SkI# zVY`Yhm9RBo^IwQ)y!2wk_axM+n+kB(ogjG^6dJdrxpIwsvN#U=wL03JlYpEHOPk)) zXy-(KfjH^Oxq7x!(7yPk_9`c}u$TfQvfW3r!a8a+h)lld{#!R-?rHJ3I?t|80G`9e z9D>_0pIifC;UA_Zn;hc;2K~1#z9*xsT?`o%tCH~H2=0B3$nwc@ywdTgAHTE9(HtYr zTXWLeTjQSa%Fv^rl=VMShkO|LOWMM6{6(56bn6(l4?CJX;-r)B@P(^I}*WLPQfm0XrzQ897RQ)MA-|z^($_$bR)rMA!s!1SNn{qNGb6* z^~f$ysWHx{11GkGZ%Cwb;!Uurg9aAum01)*lV0QP8IW?I1IsWdOett-y~0gRxn|{Y zpBN))5|OemxiKapDyth-t}}6oYifGo%PNen5Np=~>P@ZX)B)Bz{k0+|1nJ)J)s|?EqQ{WY?@gDZ1tlO8rYH3;vg1ps zH`9rYiX^w9t0J+rclxkzCFv<~lLHuBIU{Frl!cT`(*-RE#i9znUY?Ic(&3r6Se;RC zS(`g&hzI9SV9VrJr%_)EyI4uz@#N>VY}W$b5$t#C^*IakY^EOO= zs@@k5v=XZSQIq%u7|fmN)mRoM`Pq&htCTUrA#k0LEP4QcxAY*Ag4I2X!_y95B_xYa zmC*@%OM$u*;g7iWuH5MOFcy8WU~a9)TLq!d{(0%&Y-bA-m$}RMiSQ|cST@xqqO4n7 zh2FeM@s!5W#Vq5oE!t%DD5`0vIM z{pqJ;47qAjefJadOD4A>KP$yE^z5#Qek1COV4{^!b$$(b!@T9p23C2vwY=bVL^vER{f&{J zznOJ6kV!@SMdg3gBye!u3cY!18iFk}b}Ar!ZyZkTEaZd5!k7Q}L?iLb?PYGT#f-N8 zP!bZg@&MI&s;tG$>+5n@iFaEhC&lZ(eq8S?+GhDLe+9wfKwjmyyGy0u1Lq5iw(AI4 zPP#-q*&Fb(VW0;t`DEUn2zntnXOQx5vj^p>prCy}9h)&WOe4hIuj%T_$MMT!PViO;XbFq*EDt+M?w27SBa zM!g~b{EufRPLr-IF^AT;v++9tb96K2ploHb^E|nNmWhI6<_K=(+kUmJ*lZ>c zVa)Lmbi7M8h2rNY*Du2IREBR%bm~>Zq%}sn=-0U8fe%;Yq=9!Aa|4KNcP9sNQKUI- z`Sv-p-z8(7ejWvnq9<&+nMSoyv@vGpAQI*wRr1vey19;LlGX~IrP*9%+2FNI{WK1G zI`Ps$wi%C{{&TbT_D`qbwSV8uZwKDKltmx4x6l~hjc~=IR{nf0!^mgOx^I;+8KRW0 zARFJjb1&3QHVK~ac^$!>4nt^XqhX_#)&%{UfKUFXTfRpGP=%=7!#nwf#=dW3;hLYu zvc@<90CDAy#d`NjMi3aW(7*6mEd37FmNj(xL1z0n3DNK9&4(mQgAzYm2h0{8YFsCe zT*QQ*sg6wz&#ubu>smLdUr?{#W1*xue+~IIQhxivI(U7zpc3s*fLwv?!BQ}>1PG*o zubf@4efbF&jXj=%>AG2&J|Q>)^E}e^fFnQdBr#3&6Lfk&8da+Nwz2=Lwv9}SgGK+n zkEg4?2pSZ;6nIlK7O;_3vekqRbxV5cNp%iK7AaJ?SC){F{e7q5i1wzlO?8`&k|!)u zK@Xr#S*I;mmA|O`ae4m~=}Yxr?*hP{`~#0kUs=iOW-pDfIC=XkZVHGUaiD;Qz8Lk; z6lFM?iBepc+H9=9V4we&oBC)lnW;RhwCD~k1!u7M*Mr;?x~wZfW7@Cl8sP%y81V1} z7eH13Be0@JEMe)T(vDmfZMl9Gco;0T9leq;p9|BvI=u7x)Pwky&^m#io5rJP&mm1K zza^Q=D>-=Sk~ z`AP4|e*eic!fGtm$Vtc+v?i}#N>^R-8tHLimJGJYjg?L6!H27~x#hPs#}7Gs>{&WD zhc71;buMnY%6jF7qv8u%GEjFz(~6#|11yNPkb?-#L=TnF;Z7Xz*NG$B^0aM3`JN3o zm8u`l(*b+Z$85$4|gsgLt#C1pLxgDB9L1H2wemNgF;0y>e1`raW7}FavO>lW@3k< zE|{DiVX*B9$9N^$ktOesuW%Yzd{3YKbY_RxU&SNPo7hQfu?O1qkE9SAvabA4NId#H zfn#S`CH`K^gf{0EV^G3eJqq7t@I=)&@jdQ4gnUNUph3hINX;d=r)4AQf<&@SctPdYRwugIw%vSH2IoaQ3 zSz!xvedbDQ%VEV7rv+tU^h*BYnLb|HN+P;ehb~5$K7W#mDRQ_WIJSq=o7_A|4%G*7 zdtHl^zb6cuN#g#T;Z?=qFH(rwk*m!=8FCLhQIfpoYR5C$o^Rc@?(`DAl77)6-r$a1 z7=lH7A|LiKOQ=!e~w5z3SY=3Ve6N4tWFeu*!(*M z9vKXN5Vj>4uAu>N4c$EsS|AoG&yIoiF6WR7z`ocD+W=0+X&Wuhmo+fJAmTJ7a((ie|BrY?g#(To?S5Z z*z$fzy{zx{@xOu86d>w^SvR0nD|M$?|@vB8DEq-6@|MQT95R#o-{V9+CrGZ@w4Tf(Vm(~DZ)q%KX}^i?dzzMB*pj}I#XKq&afcO@ ztbF!W|1EM8V;qmzjT+NC115xJMD?D0&)NC&=|#T;)bb3Aq0BH1I-L&R)ZzBqqjR1a zWn2pf#qBE5V{H$P)1&r@k)*(}VK!1u5yg-+qX_U8A7SEoOSV&Y$| zX9}oMuBXM19eJUX+Hux$Wt|gKZc)n~ItCNx$D@%O`wnb}nq%*AXr8$`-Pbp_&KBS2 zdfLZ*>E7IGYrgk+y+|6g+mUSpnkVNEJ&S{F-(TUf)%LKZck?K2m@6{pq8biJ)pozG zf(?VNr*+N>^^Xd5Zp4=^DMkuHMd-~03EA7VPG!y73CFbfjUux)=O$UUdq3KOc=B(E z_wgN&le3RJ1WTpP++*F*enGctPVL^OGhO?7?G53uPd}^)*~B5>69UMH96QFOb|vVu zCo(eMd2-;=ZF~jD3gbNv_{wbDmiuGP7(S=uD#d&klsOJNu9zIyB4^oMcAG}}D{OfzsQ8aa%X8OWr*1Fg?v#|<5|*@suFIh#MzXxjF zmI4X0?5-vnbCeph%t981(CniKbScYC^(rDEwI3P>erx|f?~FDLd@!Oc_tUGmgw+18 zJ58?qVPvA<&pkB@O=Ga1;kN{Ni?@S)?x%*0(m=Z?NaGzZ5a0uJ$+CCtIC084vFfN? z0h#j*%?F-gI>N0%m8C>f3^Z_d?ifjQ3*fsuwSyQqKs%@{Hhh~$ZmhB#X?gEt^w^=F z+A5ybM=d~i79dh5q)sF2%=w0g33x8-@7S$di)4FfV7n@c=Xj?f;19(r^2s`U6sL$F z9BSI%nsLYZWxwbjhoc-%y2|rsZyM(6_t^UcK9D(^xFASA*fA+f^4`|Cs3i-eX!zBe}lb|NlQZ-C+NJ$tmvtlGD}y zkyBU}gjL{sTN0(#kz?MncTz{!(|tk?-C`Tr2F#@j@!Q^sU~5a*n!Jnq&3165SRl+N zm*@C?dvR^q{c^1fUqJ-?bMt-F0{xB9=aJQEob7gP=Pf6h6f+0LYt7$_XS1NrA#Md? z9tkxiLm+px9e!mkuH8X$s-E2C8HwLdfpZj1zBb6?2pR6cs@y#J3BPm?I$b(bnl67v z>B*R2Ntoc8e$4681gHzzc2{ZSW*%ytQOnJv_BrRx{mk=i(X-0&-u>d!SlSa)QF*c4 z-5Jce?QAG+=k)MuB+~%oXS!%K>A~jT7%zPT)0vbFAVl1?ipofkG1jo2&oAg2rSlD1 zo3nhMo-bu{Kf?=YG)59S_h1?l_`vB(JTUi*iaUk2pv4@qv~o5Cf4%(VJN=&xrc(>K zFI!ff(acuwV{nlivOLVMtjfOQg#5y*`o?f2n)(?sx-3z^uBN*${lICVyp3|4$ijm& zW1V7ea;}g*D63EL5Ujr-NpayyaY2o}+la)YiqC|0q0l}^U9Cx$eR)xHA)$}$T>{nW6|nCKt0TXY;$3)7D1$>K(P-d)FUXea(?aY~Wi0tVfPrM7&-=vJ-d{vnd^MzHf#g?S zo8Q}ny{)>5hB$iSvc8J;SM0T#&az>y12*(!kU!4O6-rnM#R2Q3==~dZEnby7^=)27f>f^m^1U2BMA&LBNEfS8{!V0B_HpdKF z1sg?9+7{Nh>@*@4(KsJMEXa8J#v8!jJ_yoZ{=}rns!|itz3YEu4ImFJodlxREfxpm zlx%#{np{B0qb_M!$7+9O%=?~(^>RVv8>)sgVl}sr$L_c3ZYEWsI{eAI5UxeMckL!i zK|MqW9v?bTP`EDDH!dp4iR|m;>g6*kbtge??N&4M!H)d}ABN^l8*t+O(rLkwC7e#z z?0As_J9=ysrsn_Bsr(l#IGv{an@+K|ssEwVj#^XHk)PIgyu_!&<34-Py`RpR?r=Jl zSeeGJdk^{pFM+pgp2_OcjVpbZE%$W}*AqBgy`L-iepSCAjLKhpxr8j+@m4S6Kp1T$ zwiAqfa(fB?+x&}8&o2Iy>zcUCa#WsW_V$Os6?s+g43y%#&42bqM@_@ z$Y}^%PI>;3Q>`|(n=|Zy(0|M6CHNmX#TDGE85zB3Znl4KEm%pIq+wGZkrQ41K8IJy zHA|^PzaKf8G-$1Y%`Zt#-69L>b)2T+^($4d%Th!CRd)4rPx%#>Usv06qU1x~Z9>m4 z>(PtnRv`Bm0xc`b(uqNPZ-I%GiM&&OvIOYcSj2$PGj2Am{T@eP*dC`N+xjS8P8R=f zVf`AlA5e&O>`5&dI@!mg*J8aMlv>!%;KAALbOR6EM}kN6|FYvfu(|Hv!6~A&xA}k2 zREMhIFPaiHQ)z0Ng(>e=EZcowI|&q%yr+YAoa-W@?6KA8c1<`u+0*BnT$0LC7s-Lv zw2_v%Y}!!981;9T+3)cZyzIZTZ?n{L5Y8}#2d9^*lKm;4tb{QIcpqn_l+K1AkNduA?6enBhMq<Zo>a=ZittWeFYywjL|(~6Nf=ZntVi0T9Cg{q zJhEh=*XVU_|Kab_9CL=qA{BkMx#E8m7;jb%i`SdG4TWzoNv-wFYH3bnS7PjoA)_t` zA=vdeq{GuQV)J4$8I4L&@wQPHLS?DCaAlLDZs(HUq)!Zo)l0zIFc_EcnzALt79|Fw z33$vjN|($;OGXzS*#v5Co8rxb`#Bl8PIF3ifrv~flS~p}zb7)zUJqj^t zc;ylL8e0s#B22lV8t}eve>qjQ1=lST;q9+2iiu*0WH-&zl{hGZejx|jmiE_}nG8gI zkDhAhz5bXC=Af=!KD5cvI;jb=AHPW5@Nzi{eyYD%05w>T)0pH3QUyJKkACpw3}%vj z!v<^XL@ngt4{t=HS1yhuiKgY|F)OQ<6w947EfiDST;YzX;8=>kWR6Ob={dQr)|LTL zoM!&PFB^@(?dP)}To~~0q*Bj17lv<}LO1{LdKmm3 zk_F^mHit{oMCF`T=!W@b@4otgQQ%T4Ue__d|$@`QmVsi>Ft)7KnbDe zcgai6fUS^ftG#r~?Qb{M$(POy=VA~@IlsUXYE!k_0&zr{Q6i)!> zpWAC`UvN&>V|P9yeT<-?5P7(WjSGC7KHf+)dcM4cC#Rcgbe-`5HtuqhlX6>3@2gD1 zC7VtmnHBS0q&M%%XXAWg-_c$L&mV!((?52WUXymYo3~+n)%&Dy8E|INZbKSHYSK~~ zc+s&O)hT0w&|D+90saB%xxyDj;(W2ZmGQ)U?bZ1sPD3a!A$Bzpb2!LeAte zSOR$SU=aL(#IClwFK~wcP$4Is_$rJa8&`->iPG$d81}a+nFvw>>p7 zMUEk>_-5sK46JjWo@zpzvmN?qO}uV2p5bB(NcTXJ3^$_)T~M*-b7c?<3Z`@A+*C>j zKWso9&#EW|TLafpi)1uwwvt}m`%7pvZtzwDjcITI!3^ouVCii5a`lE|`(i|M!a)EN zP84hW2kBtbvZU_S&aY`YG^k?L_n8t^$??~p?kG0V{}!k7vQIc#=Ikgh^)-Sv{J&ku zh!P~Lt$W;&ky%klBDjWUOZ1y zg|0VNuen4F6we3xA(p?2SktXwJ>m2Za2-p)c!N9~3*!^9M~u$;_OplE!jd)du?o_$ z*nUeQlQ5_tyM36zhZ)+puWUB76Y*oZMddcHg5mZ^Gzi+h@nYlcGX_ggi2Xyzs_~V~ z5y@3njdpZltR-_?NlG7PXVwF30DY;tBA-}{P8g3!z4!FHWS$>cowuK#1)qPPL#zD_ znb5m2vPm;M;HDTwKwAKj2QSCHJU%=)#jMR*%4q5>+S4q72d4~b=U3^2oc03iYR@gP zuzPrL`V~X_Hvad|d`B+OKUl@YLpk&}W)idF78l}hT~-TO58-+mrQ&3Qg^)J0oY zFuf$GBzGBXmy=D~xJ`3Imo!*EY`*b;whl##dyBme6S&R@Mcbj-7LH} z#s8-_RpOFvw`a}c_ks7O4Gv+&>yoxrV!yyge|yt;Tb3~TvI*90W^4TbLuip162qr? z0_Ly?owON+;kZXsj3z<#WJU5K?{;osc2#Svdi`H{{=G#1>P`Dk_Qn2BZ(0YO6zu5# z9y8QBF3WfKk?#Stl1@PV!IsU{eb@={n0#9X9ShLp;rrBx_ zfAh%Xc1$t$Pb{%aSHRW|`MM0dr6PK*>o?*^)IEhcy=HyIx>+rvpX{7srswZvxW{7L zXA2CfMYug5=5Ch;kEb@TvY*~(ujBhYpgEL)(9_q6s?UX@tt*60pm%CAE*q1(u0RT| z?b}s{`_MJFzEgI{bq7rL<>Mb!ER%?wONEZVy=m>D6Wa`P%cXG)m4D|Fyf>|x(>hdqWBKVjP^0WD z?_6`#1(7=VKHHCX(NMd@v0C6bvtbiWMGeUy4b=F3Ocr-!p5(&WHl}$8aB7F*2OPmy z)Ks)s>o|uv(RWffTtFDv1d7|gdNsHI>KIl?^{xC?U;NBJIZ~Z$9H4l&4_(3hMb`SN z;tI^rdK7~IB%jGT``erD30u3~K!G-Yds7kmE)&z}V4?bzwHW_|n!8dC0v*qdxUFRh z$%{ew%`VOa9WJNe3&E`pgKS%xP2ZK+_TKv_5;%IxGk^J1(yIKmTI}YZ-jqAz)>1K| z>>a!}Mf0{c)fSaU;2`dQ_k7iED4BOc?J)GA1Kyin#38UU$%(pQscqiyYu}V-r?kR* z)96R+#AlA!^~aS>v2%#o-56qEJ0K8zv}%YDD~k%Sy_Z%Us+^jysZ3jXRdG! zo}Mz6h^}Y*xD98M=(&hIJKZD%Zjjq1$lRbV4n^3GT!>#CvJRG$eXS`WdwsteQQdGl z>vO@s7L^67iav!Xqeo0H+?Q+TbKQok1D3N_BD2f{Xvdt$Ri_~DhPD-^*t zu6wyq2~Y*?TQ2;Iv4O(6fWK*Gfxi>w zCh%^RUx3ur%@`nal-&V`PlxOn<^Rb;tNu?Ong)NmC2;-J`+TiEw5wtujLuw(l#QyKc{Y_|#;0dnCJk=PSc6Z?~Nm~6_7d$r|GhV`a z0or||vG4!0OD7-HkoLfP`_8*pqmT5y8>Q1_uB2b`W#KL#o8PH*hcc*M7-1tvNtkF) zLgglZvUtw<@zyV2U$IqFe?{1!o}FtL0%HD-jTIvJtHy}A<~3e~Cs&oe4QF}BY!l0b+nfQU$rlEXOq zF-@BcdjQ*-eN2bM#I@8XeK0^%)}4$@<>gOt!_`kqt75hfzmr2;a(rGfwKT z&xsyhlq=FoGx@N`6xKS;mxH%ai8G6q&fV#tPwr*J~D0vOQa8rD31w? zZ!iU+uLM4^B(>X`=0|kBQG=8j*q0wd)BIky*JUbX1~yI#?2nw*`w_B#ts>Z2PqHj% zdXO0#7h+2D-+z$4zv6v7o8g1ml-Hj_V5>&B`4WkT&g_d|L1$lkyBIOPuIZU|iaw>~ zo})T=SZWg!m^<==>BxNgsBTxUu5ZyC=s2=)e~1ZBPUlBkA)PKq=KpR^*W)W8^Q3hR zoxfAa=U_IU+5UHsnmfWO@RdOCdvy`O@yc|Y48LUpoCUt#z&u?~l!nxq=N#7v_N<(J5R2*pT4LG_%vFLmt06>&eE@~lyn)@5o9aXN#e0nE ziH0<{xI?!i5KrZN%ppf(PMh8H`lp=J&3}^9M%T=fzsYIPKgp>dsx5rhRpsPC%DS{) zV42F}<4?%nh# z-Np*4rT|Lj$xpL)Zma?{wS7XMq5H0>A7alh|8H{I@bu{3^k3lAz;Q+JZRh*0f=H$i z!+38OskObmQr_Hz8YLsfX@~c=@*lJlU)lQ){&~DN3!9m-P8tP>Z@mPb-CPN?VS64K zxFFqFia9KRM3cte`v$@wG%a!to&w!ByZW3jm;gg~2 zwkY6ETi{5li?VpH0b%7Ng$Gq)OCOCySs9~?M`#F*!^lo*)IV_Aq?C$V@pcHeqtV)M z8AX3NF`)=A(UE$jOX2+c-bb3!GmoRNdI8!W%?YJ~tEzUyJU?)>nCV=Fae&+Zg45{J zk+pxr=~3i(v9!#LjB}{@kMr8+i`r+Eom1%IQrYlSW0`a z+6_(^8eUH5huZ%pF~)Vp-_*x@WqR~$bKG}cWa>4kt~y`694!`jOfHC4AGO$c{!as- zu;}%VU}ng0dchDb?P0CA9PYDZ;+Q=2V~Va z4r!T9ZAL4I7bkw@Mk`H3+RYF~7bX2jF;}nFluoMm$3)8k8oCcoaNC%)MjToOcCbu0 zx)u~@N{BLs-V~VyRD5A+($wWmBW;}=!=c{w7`fJmpaxmOi&G_w(jm1UD;D`xSm8UG zIx)>7GVJzQ6R!4vcfm{|l5Z?KQc`wx&L({>9imMa#k!d6;|M*R_qog{YqmdyfquN? zMNn9b+vaV(yupp%NGWt-GDEIYe<^$6WO!!?*E+m6o+ec(uTQ}MO4-tuRtMLEZRa1q z*_qB>d|{Se-Q3iVA9bz}vDYV4NRgzi&1*^-T>0y!Ow^iBidCC~G6$4PUjvO@eH`ea z;^I@kuwD;pSYn#@s%rk?MF)lUNJN z6xsy8O=yO~B!Y?H(7)UizhnL(17`3b`1Coi$;_%+30X*`2cbH*@|CEhvTX~w*R#6l zD>m}i6}~TMn742Ztv!w-5emO+Rk&D<7+#`VR>_8Y_thW=vAy2O_Qf%_*(v$B-B?Lv zpV8jU^Ta%1gDj5r&6d8_iS!UhoDt9ZB9cZO&`PxO()55 z1-$acB?X?GM%&T(u3IkD&vi(eZCyS|JAO9O)n*PgJ_{PZw5?N3&QAr4m=heK8GH%PeS{LMFxi8p86w$pN5uCAa) zO~LKg-5CEHXxl}*PG6jfe2O7_zSRKoiW&)tYcrex%o=|anlxQwauBxyt4&p-k5@~b3N?x{At5-iJpRzkmkMKecjlv z-O-rzXhy{>?#dwxE{;}Zq9j3U&+1>Zpl-)R zlV1HKLS2^9`Uv_}&$WDMM9|06O$Drrz%5y%q+-Uw=Oc%tOuAH&@}a$>da_71;f z-#4#Pi3)mS2QR5<7qJY)1lXy7;@%lAJr^E0`#ON^Ncl28?;gPlnT-8qej6lmy=2LpeNvZG4{cy*~=2Ouw0z_)gSJr61iG-m# z%&*Za*tsp&lAY*h6|xWnaV{yujp9c#Qp!51*99-SQ852M!rn3{uC3wLjRC<45ZpDm zJ2U|T1c%`6?li8!-JM2*1$TFMZQR}6p^@8rzwfPc>$~UF`LU{c%~~~={OUR8GseI} zFF!Q*APBrn3#A0)PeoH72$!+zX7WT#boGRfO)hK%gBNZTi_OEQpJiXi2!=ds-l`ykK zrunjxk&oif*@`6zWlj5Bvumb1N^fk*1lVf1Nbn-82E5q_xAn%KNJc==}9s_{K->g!NM?(l@L0 z_XU>=h8i(TL*9K#-JuFcApHf6H+f*jAx4D_s_Kr5IQBi1b8-^cWDra!XmEAT;K92` zmt!YGU94f3YF-KF-yFmHcDl4E_Y^KVjryg4?c>oE^VKerLOSl9+`U92#xtVRAk)l{ zcRfm6f>^&twOhJ<*MY)R~}{m&sO0TDMXZWg>fZ04;d_ z3b9*1LNroi**T4)7uBUDWzF6lNs zXe%*0-@5==|I+X1C#%LC-v+&~F>#||J4VO(v{VBVp>4j-$9muts7GujK4s~hCu)^)G&tAJz zbo#v@wabcAoG6k38GY7a1#Ix8^jh!0AFarY?#^i9D3yAJ{)1kwo&`Fwke<2^?wgog z52BHX;#OKZHUtSVSdfrWB3wt2#Z+1QuOVrr%4OM+*P=@(^B>64^+6 zu$hSc7+Df-tVxoTkn>%~zw}RjyZ*9W-lsFFEWttq7oMtM;?47vg<-i-gdf~&J?tYV z2qyrR@@ z-HG6II;55*Lc1Toj+&SaO-xEGN%NUKJ9N$_iF1k{XA7Gs38 zhw_ybDF!vA6`|r!(79IW67BbG2zz5vl0;Kd;)KiB2gPHGgg-F}?~(F)zz#YCiZQJh zJM5K=1euBR^`TN(ly6q?>~MdSJwfr&y*l@noKn`APPWO7?t>3m823Hrgs&Ml`-irs zo@>z^mrew6LaN7;nO_yw<1DmiGu{W-LM+-N`upYW&B1B+Bw>#?c<$D25z)4gpbTSj z!=Fk`$7{D#<($8rDbQykY<`cF0K@1Xo6`N|0s6ayWb*EhRG9JggQj?gDDM;n?!zIy zS%igVRGzPI2_;g*$CZDKEABvTU|W^LdtNNxQW=1#`x}H9^(lC~SbA0lZ!10MGkYwh z44$=vTN5WBpK?3}H+ycnT|a*t%ZrBTii8Nc6(9489bz@{^mtp?`6HERFHX6>gS7 z64&w6`RZy|bmkZHW%Pr%9)Hxf)F@e^5KXMCVXNBTr*map?5)wXCPLK7jO32VUa^_E zb<1qknyYO5uDCZzbOipm%5NHC)SwU-@c?tJWFE#!8kLP@US02CJ4#p*yKkO_{p?WA zeFd|!mf@x7TTi$=3fHY_*6IEMN@bmTI|QGn-ZmVI8wIeLBfre%_x&YG{pu}_{IISx z9gyWdI^u`LntUfW&*Al%?%g5$QSi4$zgt7{h;qj_gITN1i)bqzt^SfnUB!qX>~a)g&i0<=k6*!n4;= zCuh7Dty6G8b8-jx^?f=B)4sSh!*3_DzPMFLCP-k!JylJvO=MI*t8)e|>9x=7m3eW!$8mnQ9Ns4N*GDmxx^=b9+DChg&YHEc$m}Y#@k>qXY7kCU zJJa;cp6n*ov+SldFq+iO6nZobRE93b1rw_M1C&AvE4J!?5@qZymMr~T<7})NFHF#PgVA9G_GsmD#%4X5 z#uak@MUC4Rf#k~kgpvDgTxVJp_TqB|cYlwHA=~b<*OBkFmX+mY_?)^7oJ6pYvyEkw z*D!)R9`tN+GSbl&C*rszH9zvqN?ZDCb~Gh8Khr;#w#035^l^5kzn$aOPFu0TC8sEO z+3aXj0ZM8^$x>CtXw@{{^~3@q+x(&daT%}9H1}3P8JXY9bWc4G`%fZuO~|V8&gPJi zzIh|Ib5|`UqH*^x-z!zES1DcdMf&-sNhkMIASA{6AH5zg08iY=hQp2*y zWV&rSPIMko(=aNuWr%Y1o5y2=co`7x9K?tTxbc;&sOsBHCDLL zXr953dnW?>BwXAcaL`d>6m()>4BYsl$C%KT1&V`edfR`8Mi)KCg>3BZP#j`hM+hhY zdnBmo&}aAWoh8^Q=l1yTP)f~xy8p_?3E}^^WvU7=hHvY{afHCg9r_rwriC3b{sfCf z*743^;+*w@dj*wbx8(v2wl$;s$LeI0eq?9_j#wc5+ z_)O&a;abq!Jy}5@`cMvgT|-WTKeVPea;k)L$#!{gy;fhz`mYOqVis%dno9AK`ztKJ z`mDtK@kTSRdENMxR!~IfzA0`}mG#zVttOXSLYD)d=7YB_Pd_J3x&6;jHS`$CZ?+{g zmlPNG4sGLZYS_A%JCz(`(gf&s$W^eyHD*MMbv}+#MRL^P=+=&~oAdy+hm!eNKTsN0F8}Z`U3q{`^D$P5MJV&-XC{j;T?)x@ z%FpB!5>N_Gn{n<-apbc#em^39xJxWoW`1wx)#1{8JRMF0di&XkOuFiGy+VCdIM>9u z+LipW%|}#Y>lH?~pMCZ0-Ez-ymzogPZ9sD5?5z{guc=PSOLS~wEu|{liICXk?eZ}H zq_-PB5GQB9q!i>> z7Fp56`r86LBv-r zK0&JGoyp>{DG=xKEvN2w8cSmvxk-RUGb+g;gAfthagm2A6d~z|11S?2^^| z;^=y<`OGrG+)`-|T6qteH<+q?0Ij?a`dhwij2CIMVfzZ$N)T(MY=b(H4IdX&u_{oTO{6LH5(g5wK&;D(B1^Bx<3=c?`s#rlg>)ifdso(GJc(g5ezIQ z0Mg~S{A%+Qd^zWql=sfka_6 zQfYQ7N)eM^)vw7QKQKOYNnir#JPKx*IY4ZAfy_59uW$XK`<0GG1DX>-Z+K$fJ z_AzSU>gZ?6+)kEEmI3T`R17@HM-vYvAIq8II|CuHtDbEOf&*5hk!L7vIuV{s4#QJ> zK=R1W>X~8@QJ=3;PY5lzviScR@b~K#Z4pf>KiaDPYrvPHk(EIfR+J!1Q%~|=;>nQO zRIox9zFT^c}c zkQnA44HQG_TKlraBh2yRbR&49DVE&&lM7zIeT{U(GFgVqv;r=WJN zEI>O2@a5ufu$}2*`i+t$a|`>s4Jn zfVhz4Ojwr=dHP;^E&Av6S@BryJrp7puHb){qE^zF+tXx_7(e5_*vLIc<^NN0-FAj& zYcg5&VHOSFr+^E(9S?;_p%#1|fqIN%J(AHp6wG|(U>@vYdj)A0{-Nfn z3+m%P{`;CkvwceLi`f#V4bu?wTo?Z{pD@$OeE&`-IXz)zt?uwt!WM%Kv&qE21nQxM z58bK9@L$%LPr81K{?3pR{1kxu$avwpT)yni!}w^lI5$R-ReQYaFh+gs-apV+P2a!0 zD?%icOLhLlQ-w0Oe0mo$k5BLNNqd*Nc;H_-ltw`k120OyfNVmKzxS&<-ky(bshSY$ zXsuN;l8cc|n}Y{1{XZC~*3uNxG}Ur_bkmnD+Bbsf6uo?p#li#SqqP_op!yrT?N41Y z`eczZn9BR8Cw(j9;+k)x&Nmz#wgal?&uw>)KeIwA?tP)xWdcW1(qaH8Y*`oqu(z<&jV| zd7r(pD;pG?k-m${rhMX=zssx`eXetm6I2jsQUUgl8gYPfq`UvoL;rE$hyKTb?-q(Z z51DYWjpptFTt0u746u0wGlIWG;=>aHE1g(0uN-*3)HpX~%yc7kboAEK6dc+kfWKOj~>K-iM0=eo1Al*U*-~W8`|M^}44!+BiaWC5yw022n2PiOwA%AU9o9E+yA*=acS0w&g->y%(*q;k^=Xjdxv z-OaiMofhFC;{Ah>cHM2LqIzTZk8CGsJ7fJHG1C8~hteimuxtHMOZZI|$t)u9%eUWr z@<_6x6sABT1FQMcQG99j@%(;4=2u)jdka2|JCJR9T$XuY|KZ`1C%TG-y+D^QHoNGw zn&JgLn8ie0><@0ZRj@i`L6vntudF9Sq?ue^UcWsK)eTBkJ5_GRlf-#gP)ctVhQf|! zl308R5qS{lAN4Ti+ltx%u{P-d7kETPg0(*Q`l7P}8VEWy%eb(Z8kXqOsLDN_fP-k| zXLBWTC`LM&>ARR1@>30hS@a}9anxe&A#jz6gA{6&RJV$KJI&2i{Sl_b2yK?J$bnDhkG|MO1OKPct8qJQdLo6f}EJ zvl(gML%<;@HO7pr3vpuiB){qu*xZ1NTFjA4t!-x~;vR>}5vkRLLO44C<7M+x-}!OiZ? zZkduYTr>!#r<_)?p79KbTka%X!wjF#P!%CJ*)d5-sMK?A>;p7pgmB5`AZL8b&&dpa z|8~52d6#KS(XaMdb@jrMN#5GnJKG!s%~ASbiPc;kSI%4zcybxS;W<({XXBXZ7p5;Y?l2J_Zytd>ceEA4YY*hl8KiQ1 zEfrOrGp(r?ejZfBa%LA718}@Ax8nB%iH;8=+vlbtU!`CmVd7QJQE)b4D3MfMuMj{+?#1Z)s~zNwdek4 zi(G=Av)8YH7vkPh9|d)H$hy&I<$RpKJqYMNf}BR`ytNXfbO+m?9>McUgtV$Xu5#6t zj7SLc7RB0-TPNAVjhg2GJo{cF#vybK{6v+9+xv9qIyONT2lu!E`eBlG9C(WHV);w* zPk!01a65}g%$U#E8fSe=3bv()%icEG##zwwXAFByo08G-DmJ;C&!)cptj+@rOfHT0YG~ z_~455|gQ zy80LPAN}RI{Pmz(9)X?Hnb1iso*0`B@P&Vo=ALE=xFO_V@jYZe3SiQ zjNH2d9p7(x{hFPBv82WQHwa=Z7VxCR7jLu8lS{94=FHvVIa(QANet%|#h0cDy#x_q z*FS`+W@Sp9IM<1XeBo(JY+ULUdPPCGO6FeZHMz_?);MZTdOTA0oO^_txTpsFP7G5O zYj~w2{8YlY76rZ_V8!M|og1B))tW-XkM2ki;q~N) zWPGcII_p&vMj`u4W`V{Vyuh$0uJK9wWc!AaNTT(S5yPm_xyII7saZGM4@`IT2%B!a z%|z@2=@AoysrMb0xo6M-C;E%y>t~vvr&aOLy6-J8g1Z(d@p(Hms#HD}O*^Qzy>QBz z-{;&3pIy*SNJ! z63dM*Sg@cgSa;$OmEDuxhbK3>=fq_xqG|5$+bGLUO~C8Q2XEGdrks=%L%<)6c`t&_ zknoGIYNtT~vNk~l18(|JvGk~Z%UzhvsJHxMxaIoKrTeJr`!BTX-yai@G6zou`z>0uV{GrBG+qLipLfjHuDflnqE?N-XUZ!aR(z?4urHSv%NPDW z?a<7Bq@V_0r<8bofjU*3Bpg=Wi;mPz9sy*D!R<_arrRt|p!kPWu>d6T&@Z~e&!-fJ z`9#{KM}C^qB|rDbmTzfPPeIyZRd(?hIOKIQNLmO_jy|?Y`Dm2dc9Bj(*b`sZvTWsL zJQ)SaLxB`cNW}oMEdhu!!1TZ)otLWw=jmcITJLFF)m`V$z~(m7O$3UMZg`W%B60q{ z|KRUDO1EAVZmA|hQ<{11kuTt2|3ioM6vng^v6fE9D#C(r@&Z&$a9=yiDLaex=?Cz* zbBc3R3P4_(57O^A+w0hbD6P7z-^^?9^qocf6d!DY0q$dDwzdg2zYaP4*jL+RD;*6= zad!4SymU^1#w>Ydrx2avgX5_RO0@Ods|gFJ#ifbA6;ONhI}#Uh3@Lr@k>)=?H;{on zTG`{_n0EDXyldn8+zvBvoAOaJdK2>$cit@U_;TDXvc89dck4;sKJqTg(lYRPXxy%C zwwY|Yl)N1E>-^lBy>_`>Bt6C#K}=YGgJRmyon~FRsWIXP z_D(%rOqFvZrp576XK^|zz2Rv6PH8On*JPZs$-zo>uV zJtqazV%Ig=kBqXrYaV=$^eBi5s@ZyRbh_8suE-dN*bu36PgTh&x3kmELhx`^NgL3r zW~eG$+s+DT8ReyA$*&h>eHL#R&Baq+gAvs>>%RRkScM8QjJ_YPqCO_@ptg((k*(ia zh$kNa7)1#z9z$3iPHl&(#=`aWrf#?8O=qvkq|Hk5u8G z^YHR*FKnN3-~IE-iO^RbucDTT(mwSwl&jxc7`P`yO)-?a8>%AhuK-$IuLG@k+UqwL ze%(W-pdVm-J98^BKKvR5XWv3!I{b7nWc%wUO5b7ReIhs{EK0lax0EW*mXwhu($^7N zjmDWI_sH0?MI^r~PZJQ@He5A|+gvffqTsxkK3=um8jGZQJ%7atDEaCI58vSHN1{F} zfc!da3L9(e#Hku{-S6DWFY_PRjXyp_l9bEAMZnD^yq`dUJ@S0w)jjg&tr3JLPdv28{a@cPsC*938P+$Sc;CP5!_y-_n>WMp1DoV``Q7~TKA9<3(Dip-W4|kms zSm_wQQN>WPg5p@i=`RwyVQ|}?RV3zA3FI!J#yj($a}H!tK~WY@R8 zYq-vs=A>;tP*!Ev6+S%>@}rOW5xU|%10)Xl$Z6H>yE!>`jBe_ZQ+X1Mc+1aY^EL_U z+}}QNsXdqwa~dm<2ernC64Z@o*p4Kf4`JDk@SYE;*p8%~57j>vE6-WnC(bf1ACuZ=vGjz{)iCxz%QS=@uaBEA%)=b=Yi?O0d^}2~koUY8}p4d|F z=6cG?agRdtM1=mq_L=4F-q*S+C@#&jQh(p@dcct7D+S1~PurNx-d``g64dnQ|8{Hv|R~1+}(76o4%o|Od`6a?RR3kbf5P~QAyu0R#pHfXX8oSoZZpVtCzA4 zzp9xf9~_W}kE?k2CxG6=V5YHy+{TyVfksHyRvZ&sT4HL-SeXhze}v#b7XQGT$jaI? zPKRfdF7Dqn11cY#=+i19-2vhX!SvJKu~Xu$J#b$Sa1^U%=WOA4_uI{%jX15U$|c%j zT4qAr*Icz~)rB$hdWCL>0$;&~3>eK?e?r)n$mBRA&4&o^=(xiBdHT&J445?kVBwPA zNA3xRI)jlnhz2GnZtb!Jev@$mw5BrxH+q=I&=jSeCo)$j(KgdRDM@7TdTC} z99KjO+J_jTBxNYtwsbQQSlYMCamu+0D4#$XW~mROg}WE+SG2XtOSitiXVCAiaFVfM zH!4+Z%pq0X)B?SH)L5na@61ruM@vNBr_u8igj)q%*Dnh0?uD}Gw7~SRAH!Qrs}qmA zUycOixBIxODom)<^3JLktvAlk^}UIaF_9&gpHW+10aiY;=2|jszAF+xDBYCcO`p%1 zW8B$BF3>))ME)zXe)|%_abB@R;3vqSM(FYN-DH8@bQJ2o*o+Pk+h`k%X%z*3F=^}P zXLc|`_xz!NGrbF?f+qC^5p<%v&?->RHP>a3Et5c*W5k3F zWZJNsUQ7X%7eqB3Fg zR|WUJa9D(w>oV`#x2&JbxwhpWbq>z!|A8Gfhh`7_sDMUiCc1P zMGWg`FTm1-jxDhpx`hSiurTf+VVM((z7sDR2iQIcb%j%}W%~r~3v-hruZ8KP(B!LA zwMTsU3HsE=NJd079}g3eX)$krogake#^hj2lz$okxk?5EwkuxFb*ud=>%+iFHA|Vkzs5InFIYT3KdJBzoL8jX z%|dQtuVIB@hvj{Au2s)-z&7RYe2c%?-|rD(y)Ys_YAwzm;W>b)hAK>l1pl{iX~v5! z=x4)#52uePOsud{V)$-sq)-xVP+Sov2@zav^K`C)FDzVP%(7YZTgJ2bCf6jaXfW`xpnflx7B01SV3R+fyf3-3MKp{^(a@%=pZw)^ccCx!M9jB zK7KL|6n>_>=!dI1*5P~%XPcs62{cEqFoGU=GuLJPAK*s8P_%;aGW1^^@pk7dMmhm) z10=mv%4OdSi2ay5LkB)fdFp1QT&b0b*ud`*-CBO~UO``)Vs6<5Tv`N^sS94Zy>PGT zL~~QU6Zed#T#mZtQ$VvY>68hYO``%x;E?-%4ce>CB0owfuEjOOju5oi2simCDK_?B|aaY;A#+=yp%lUbIGCF@{s1@2Ercf1<3o|{-XzLG|sp%J#jP`32jX0halVA}Qw`!M3MD?f#t zeDNS~k(&ayDDg9ChSK$O8ism5byqKoaucDSfkuwFlC1H|NVA?{NP!y^a6MA3DrGZD zN)1*t!WJdUEk?bhMAJn*BFU@g&au#Y!cex7Gao>0I)q=RrajPb`dmmAYSAzGVNB2A z;cKjc#)&p+?{~^5;kFsWvO(~PxlV!Cktor10RzMN@~&Ke>ZZd7)u`rs>wXnIT9CP(_oSLEwBH?*0(ba=(KB ze<~A&PPZ(1RIL+Z6t_N4F#PJOq0g?&Ak8(0+K{pz-`>VKl{8&jVvqJv=0Xg4nB{2IXu-IM^|^ul8Hk+Vg2thu5Drg1X=u z!Go`auarQV*FpbGR=girSn!!{4WvyC2X>wcxkC;5)*<$^h&&>qg)yFmNo@yjD;ZxX3Cc}+;Oz|bA8UYK^k0Y|F4 zw}dXz#6TD1-R8$#h^>U^Np&TKKCMxbAiak=F3m#)!|nMga>B59>-%1AcoY^I*0A$K zp=h64odP)gMc7ujVLfo&Xj4&197(M=4?~8~8*(k-1=c*pFa~2mev2TVXs-1B!v66< zcZ2XE$2w1$)J$!X?UZx}Q)nKb^A1fEK1Hv08xO^cBb&<)rrh>fSv#8<>&I&u{1Y8R z^I*>ye@sUl9H)8o1HD>AUp`Jl^S!%HLcP$46Y@A7p4L_JuRC!S+jnKB{y2+ypD6IB zJ=#w8oYM~je@#zi3)FZ{DKd9Z=9qT9{+W@&H?Cs5Z$UjXD{Uk=V)0!Qi**o(6?~?B zuis98M2~2wUD1m`qGIBz8kKspdt~Xc;q9ESlbEU4pva4{3E?9 zO65GqAI?x*&v$5bm&v-FPpD6%Guuwk$$Ni|fumT5_N0_3VRQA)hLY_gx$v1<1_&YV z?MK>IndoJmQKFaY?~jGq_vgTzYlOv1%?De* z6J@PJla%EA)%nA=L4Q&6gc+|V2r{A16X$VGI?7whixWpeI)amw_o-YgE6#0_#$6!> z#_Ihc^L$H5D<6KH?$}6G25GVF*oaiej||-(89~Tj!(Q#Vbk2dSf{40HxfQBs8#Qz{ zr<0k3Io8Io+g6gq0VsW1l%Mvo4R-~FTR>Mm7Cz|ielQ8=0{QbL!Jz-XUYQe zhpL5Mw`3EhwQ<(g&W!`9a^1YHnA=ZFO+|=U)(CGWZ8Nxf#jp-plY+ChJ!@dl zzPqgcYaqjc?U#W#k-#7!D+husGXt_Hrawfw{MveqJKp5{O=v8ac3&bQb( zf)3^Hd0aAB^Z?BHVsGtyGuNfHLX$8QwNpr_rJo^KsEcKAz)cS?wS-DR##mWx;~Qq! zfCJw>Y#{7`pbK(`QHHL{b|fp&D)Jm;C1sT*H~mg`H}+22Y)qMmM7AisBKS+{waG(t zoV%l;cML@2yX20-5Jff!TLa4tVq<=6^IV+S2fzX97-LP%r8`Tn8}gIXHHzhyXDu77 zU9Z?y_t;)_p9hZDhNQ+%&a^AsPH^=Ut^oyt58;rXK!NblSl3SanihkmOP_#)Maf0j z2|s{iQMEopKMhYvCMTG;^|K#id~CZxe|P!jOPY_q830ghnkd<|hp$`UpF^F#IH&-n zNp|gn_Z&v0sNS2}?QvI@6Iu*fLq@sQfKO{;ZZK%%Y6Zf!v28^24r$A^C+keW14W59 zq83}g?Ex2i`mT@G)FSg^IA_0~g6`p?|F>SPc!JB8(YW&wdbfD>@iYLX%>KZP*L>C33Rrqih}T( z0y$N19}7oh?`_Lpu8X>u?N=qi!L*1A{dp$~C0VHhIbFEZl8LC}%y~muD}jEYU3;g< zIVVD5v3WBl?cADjIraI2#%9hrCv5_;d5=;$zw*d`2gS7&e{5;2{hE&vh6JlIo#%SG zooBY1?#kju&ObsJjkam%rrfkI9UplM5B}ai-zrd@`N!QilhZF|TaWGCzgzQ5P7*h> z7o0h*9=*W{<;gwa%@V<-D?oeKE{(%dKqlUI$0iztNq`X!ozf?@!3I zUVu(6K>YU}iE9&a)S=#zhDG08QIXh$<}M znATE<7BPmfJnlVC&>pJI-=n(j1F_o*Ri`e}sWK)MU%VMi@u)wSRY&K7e-#%bTeVrrFKYE|@; zRxW8KwHj-^UI=taf$2&z(%8!BfSXilYxc(eL}gU zs&GR#XPt7kdhgHuL9cbhhW@9}tEmk4=Whzv8`2hevVU@Mu`XAxt5DUDb;-}PGf8E6 z@0f&Zs3fT4nG$EqsAJ>KAXUNv25ogh?1z-Zl5ol$JClVLv7JI(%EDZZ=+?g7W;4|} z$ed}mRkV(t0ur_(zKfgY?f5@7yhk9LchWK(h27G=&wjl8O^O|f%N#PY;=rtu^8SPs z>%6dHEJ1R4OQ2s^kmi(v)x@d!#_(0=9<#r~C{s6Zed{G9YAQLc(EJwyvc^nAFBkU{ zSnG)0S2#vhg|m8$vl-u731oGEjQ=N#VNFDr@pu^9>BTje|4D($Hi3mRc?jQlLraC_ z&7QG}V3}ku($IIiA4Np!?b?mlId!zovYx=DmDdE^0Pj6|$T|ti#N8TLM%dGlX?tYg zO-(5ZUGz*BXJPB@5K1=qAd(M*N&fI-YIKUVf6D`TPLD{{qd44yZf^b2@;3_pxhTxL zL(O3`fptz-HzT2TLe&1TJ6fM!*q6yq7G@vHEDdI<4w|U05~<|DVt2)nXD0ZwV)*W0 zSfoDIOr~*|TGM>TTY%loukA>+_Q^+$70i+*TW##Hs!L6D2iZ?OD%d7#^{c0NiI*x- zP^lz@C&}4%I&LZdd3@ZVrAyxB(VCEjnDu!@<7lhSHt}U-o# zN&d4gKlC8sJnGZLt&OiS-^i1QIgNHiaYnMS+T$-NeMhdd6ExJ*g z>0Z5(8#ByFVW-mt7w2xJ^AjbyUn4oSm`e8lu4t%;FAukyZJR85YA#xNES}X@&)!u( z)mJYY=G#Uox6-Lx?y2>)7<~QTpL}gGP_~LvuA)=v+f)1hov<6$5k%ugY>p6U{Gxbt zeo2db0Cd-Qt_^abSnQqcpFgf?aIR}{E-Tl!G+EV^l(sinwU$^_HPQP$&R(TcTUYO}%69QwP1p>(|LXiUysoHc(s-TEb@uPQ8r=UGa9Cl7Of7-x7~M7i|=@R_D-93d3MDH7s7? zHSU<(pTh1H>mD}V&*I)EynXziGAm(-V@Uk}U1lBRQTt!G>Ss|XuIizVL`xH*Iz24Y z=rr~EM7hgNEQ(0c;&CBFu|GEN!PefgcovWG;Cc1p0J+8Bv#q(G*Y!3v9l8a;J=CjP zzRz}Rh_pG=^NG{)e)aCI&uaJPnb2^4fh4~`V^7CAF!9^={)s)Ur*`p>A6lBi-Cp5L z=hjl#OUGg>Udri%7*h+d85Y50qs@@b~U?GN66ZnHNY7g}H-B_MNcc=9-hbWOXJM*8In{M?G*61o<3;FU&XkAqGZ=qhO z#>yU*y-*oRCCpn^O(@+MVD7oG`-QrY^++Ll%s- zHvZqbsHlJHq8|ULi<17QE{gN)B#~)bi#|=1k8@>7R7J_N9c@=F(lB0I+0A*dD@Kt( z+IF>=gphvVuUjvEC0Wbbzmca3ve3v=PtB&q6Zu@V<5=P?2Wj)RpU6|~($Bq%znjHUkzcK#Eu<9AJ=-k^a1Md01H6cr zvApJC7iHY?_>GSCg6DrwUv)kzR6A>(JDz;M7n}N)Ic}+Y+`Yez+3R&+Stj(Qi;+e0 zEl}o;$!d*g8UJ5gl?XH6DLU!DnWwgxc9RYJe#)Kcvn{#f=*3TX9>a;1t(Yhy(6%Vk zy#0UMqQ-NbkDBiAr|-kx@g;ggGf%IzH|)8H zK~qcB+9CBc*t35uZQW)WPG;4jXeMlG`T;v%*e$FCOMh-|I1>zzujy4TeQ~VI`bz}- zk_h%F{6Q&W#vPOz#vlBMsd`|Z^5##|3ma!%u-jtPOkUDW=fXUITc{pwMp0Fr!a!QM~V6BN<4jd^`>Rg;m-A1FQPhhbR35 ztCr9zGfbQ=-_N7gZxV!Z)(YQluVTFc1P5wHUb0-yqq)KVfmP2Q{)JURP*@eMA+plg z6x-nBSBqJ3iN&Vi$*(+5^O~>*lbhe6H^tU$GvP=%EtCkg$ul>7mzuyTj| zMP@>9_nC68SgSxyS6wnCfp$f4c-{Wf6(#B4Py4gg^%@1ydmcfXan#bO42U5A~tx9|Qju)1yhk6C(Po2%;}zG6f*Q`wK|(Ob7PuRkn({1Xzad!fhn13eMVD$*d

    bHPbtPxus?I1+Xiz2J2}&sI=Se)>|>bF*?E^FV{&xu=10Lwr?Y- z_VQ@n>~DKP-TS=SD^XZ5QEJ0Z+}Ucp;A3vb$F#DSQ5b`DoSfFxAu{}h8vc?({&*84 zwuBDz65NApcakjV72BvvWNOf8J%aKa`RbJ^%tw5#qr`^*8A6ae{X$Vm8&KpsCDUJm zNY1zDcVWu(c@y9pvmDH=f^Cg6mc#79caKBsL!SBk;^j)0oyKR8KAa2PZdDLTR^f%{ zWTIH!BB8Tm51)Vggatnq<_o4>JGM^Qys@k-98WCBp`jTXGu+?9y{uJ+Z{1>?UDPL_ zK(Q8Ne>BY&`cZ$(Cgai}l9ydeY!W){$qe=slvN$c-+gK8uw5!OimhGxogk;0F^nwZC16OfZUqIl1Nm>T&`--;|)gX;mx+}gGzuOCDZOYH^SMvYOPV&rh zQ)9pb7pIT^G5p(Gl};cadlc_=-7o6vk0`aDh+LlsN7cWuWXY3#T8?e;{>j5dX-EO= z>lUIGt(KitYI+CcwYgrjd9uC#VC?f9EnpX)4Abx$NG3E_f`OnIfzQ&{ zx$pl4f%flsm$nQ=rm{fmpH)fK@I)2S-DgS>FRqaUbIx$l{d)8|W1(O2m`3OfT5Le= zXUr735!7F*R;_+b?5%&YcCk)>6ktx?Lsn_4SfeXc*bIXbqhCLNQ6~HJ)4G~rW!?e# zvopGyGQ+iVe6B@)Q0E!`?3rtzi?1C_oE=cq4f8hjNd~nXtj;xe?PrpNPM6^HkA0(r zrHK5QCBIAkV3kC7Q80sj^UX@$+ZZ`giBlk-*Lk|?e&x>IMOR(1i(RL|B)(`~RmE0M zGGWwilqFT~B1(+VWviwf`Tg*I34Q=2Mj6>BBju1eO7*eVZ@!7OIpVg3`5lYFL`0UJ zbZ65Rn$kQGFAOKM?;=LpC}_VFG86`|M||>X*RAIy#{!qBfi%fL-aQ}q%TOT$0z=F> z2Ll4f@0Hs*{{0~YA*TFe$xJEy%^KPHyOD@mRXq&n@w*B=896gyA!r(FL+4cSg)8c& zWqOJtuZKVW+a^aGq4KBMzfD0uL_rG$5b-T@=(YZ{VXG^G%-XZVLk8ZMV8d(~+)PCd z6doEv*etG!MY3SwU`D}(zUONggB((Pe>a07| z+~4Sj{)8iz`wY147cLVs3yFIx+qpK4c0?v>V{7yw#aeS!CJQTJTD9#aXE~(Yw@$Lz zAssoaljp=;7#S%v2ev7dO8oY@Yz4ye_L<%vh+L-mP({Mv8_RKxIUmCB-v((iz#gTU zU}XM)Ix+% zB!5D>hazT(MtVL`PH1O-8_8U{izp$1I$v^Wj7y1sN1nSSD+)x^ywR2fly z=6?}^9|t0pj`G$&tS>0`y=QFGG0Mncm(~w_7*kXV%y=m79mmM! z_r@U}5#;vFxqcZn6a+?|Nk3mQFquo0DqnqEWIf)s( z2FM?y8V|%1`{sUfP=+eG;Tj*R&*JwxH2zoaZwU{rF5|_Lh-05xX`;w(b5i z_HaduiS9O%(wN5LD}VS>|CJ1ozG{Ra+iR>#IHY0>-z_ZiaItCXn&RZ#>}wP>-HR=G z2;yN>*NKguq=he6iK=u&B{(B>lg)-C!tRrDM2UM@&?{QVdHz-o-1j9q4Ky%YkQFwL z^iuI*2L$=Dxwt%GwtC0Je8!s8?14>R!{$Cu$4FdZscu6{WuS8(jaG(&!>GWV81Gsg)z2y% zA^(yF_K%3FFjZG*b#TRr?Eqa3lh)#KD6>+f8W}X1dW-BZdse|gQ9wxKNUxv@)WluC!oOFC86rAn!9 zZ4#Nz=Qn~svxrXHdVl;pI4F{e-YJZERzDjnmA&d&GFk$zS%%Z!H)fT3jq~mjQFo^+ z18MHt*8WXZc048~dH`}7GqfCsFlqSnry*72_!rhN=7REnhSJ2iZR)8i9eO21ZG!p@ ziNne(ze?NWbFFZySrQ;XV1>CkN)MDbFiuw~mwL5s7nevIua^DGmmG|79RkTapXq*z zRtpI*)ncelbBryobR4a#;inFMMqE1*or{r;*Nn${<;XDW6()lO}K)-FTwj7y*^K7~i^dO@0UFUW^E&AHZGyL#(l z50^-zSlt!!yT{mc9R27$Jr4kWhtzO8pt0Bpm_3ZV60Z=P*KBs-`RLer_>qtYA|^>; zh1~r-G>qHgytq1g>2X$76K7?I@me&r(C+$e-StJGNAL_#;kR+GF&kgmImEqAl(C=X zRC@YdNBk(Tp;i>%yl+(*pIWv_n`mCz2DVAVlUSIzbUozG&82!`D@^JTa7;eQ-!sXN z3`IND#x+#s50pT)0}KSQwF3`EGfYZ&lrN3WOktZKXSQ}>ov8_-c0&E42jvwBs7@oP z(u1-e?4*FLd(48=XoxbVO8dp_l?{Fm?YR{WFg(TOUoz>`wZ3IqTG`TeUNRwd>Ah~( z`MyvgU1@jvO=iDSDp~`}l6`rlB~#Yh$9e({laQHZ2kA|_gP<6QBxS>)9YtPkkzK0;|AYoCd6VBAE+UAFyR>s8Mft zv$1~r>eDW9F8AZo-_%!8yAUbNq`>!1wAGXC?ULeH;)(r#xaR-CoHK)0m31L}c-teh zYRr$>Muwl&d^{C@Op{NU7v(rhvTD36SW$c>$Myc1$UZ-SjfGz+lya^Ghb;iKJWY}3 zkmM1N>okyCdKHXjTsPxkx+AcGj2yi7L%LH+{>llNA(jtTJOAqNxJ^YcROUb zyrj9FmT*pVad!_bNTF;ovy z(U>brszBEfi`)&i-DpChq#lsX?=X90lka|>&1Q9ku>!-Cy|Ha}=jE4qiR}#$TqLG( zhiLC&MLiGH(%MDVJH_=kFf=aI&4%r5CcHQZscCW$r(u>g-#Mc>4os-uM_-~h44}Zy zyS&wHl5f5mH$hj*%itw3S7AIqo_KSp>D8JaQk0PR^8a4zeA{ypli#TjSGFE?M)|g5W^H`@A@qllhpyBwWg!6PCwZ~@5h1Xve1T5{q(5sO^!8Uu-4|2Hq_>@p`A0) z$OSI<=&pR02bt>u<{PK+wYu0V9R6*NLny(Xsd+H`Hl^vZIq<|72@U>Ls$h?5HnDx0a_Z_wdQ?P>40Ckjcb$HYD zPhu}HU$-DI^|Dj(hBxskbe%%Iy)H*G!0`2=g*xb*;!-Ib3pH(Pz)zv$# zoMf2VLi|wsBiE7AQjtuHkN?;44>q~+PR!6&7)Qhitrj-|N%+%(O+K-WB z>r?tljZEimKAgdAXj6sNQ$G68XLJVC-yy{vVF}QLl=E#_kL;V&bDCn35G1fP&&Ety z(zy`Y?6H(sU}gXNpRWvC+CEzIyMASN&|KT4*Nxm0hq>dKHT<+KeBQN^dCXj+JxG5P zd&QGlXYF3J@+^L?kFi^0_tDY+iK$*j6P?f5L@2Z0I5+&?SnE-A>lQw62_Lvcmy2HQ zpLpyKv`wzBtVs}AeonD4UJZpgGh38}GYWTZy#|{P48M~+H4m8E5?&=phuW-P%@rNh z_v})iT7w?w&wZ2ZLeHv4I-_g#Szf(H=jKn@JHlh8XWs1&kByOBJkp<|`P+N8dZrMi zxAx4?GC&RjV~V=>`p?*&xvKr0SG(-`Ok*m#g^XWpjzfXdAcI|Rcu9R&_ z4R@DrEsd~s1f^H+4X|~H<@lR$g%I-`T+s*$uG-%I7DbCv zL+|Rv;|7|eU`*Y^)ylZ7idx((cf}wmHY^EN61ul4Ej&hbg zHZiv}>D%Bpl>3@_u_Wi~z}uYDPAT#DwAU(bSo1Say)#G0c$aL*fA#reP2RjT9aV~S zuUP*6Oh);B29qkSWz`Wu-mCW&GaO8$7>jK|5GW316N73|K_`H!*9JT7-?)MkL66~C z{JIBKJ1l$e>m2yrAM8x+hqf&m8f!QdA&Gx`|7+0gPi%jaC{}#;9~w+J&Bk}dSS9<< zYn9irq{qVj%~mPlW`chtqBeF$m9Xc=Kc~cX)YIeg4@1Nyz8; zk=!j|@nhWOVWj&VrItI&wvFDv!oD}GXyVgur07(Sv6Jg*%Z@RFFV& zn`g@5$#+@vAE)6g50*cens4hb@v9p^k&16464ShHj%Vq1UGc9KJM+{$Xupg zXh?;8`t$qOKqp?&F68{1va(4?Xe_|nfN2t6oNQISeaN%HLWhw%V2t|9t3yZB^~`n`ky6 z#sDY!-e;^&9Qj#&@4^Gju9hpU%fq7pJMaLPjgY!!g%Lwl~*xE+(Q#GX`ETN{I~VG2P5kS6*i4=H6C37M(mN(8M|_%+CMymvY}_Ts$=%QunytC7pAY0UnB=Ud~P478U^bdKZgU=4`kja){!cp<4> zd?GGC`S94r7K4)fd+4K~j+qpfIS1$aj4_`>%B&?JsN|)6x!jvB#-a^B3SN9W1=g*)w&zsq&Xc`-kAxrO~m;3-O~y( zksM_BEek8tb?Nu`x#$f0tPU+{vv)m?wxie^8U_C9IJ=s#|IHv~BfBlfqrBGQfOCO^ zH}Sw?I(uAu`U_XtV4qNXSnbrUCI3*%XmA?GDz%NWJ%sq?6!H$gwP4a0*zYwit(Q}7 z$Li6fKag(Z(STU+qre9}c+4WQ?e7GUle3Yh$&CAwSHy4gA2eaM=l}RDNGUvz-l41z zNE*xp(c%XstS9#(@lSSc2z4H%39?6^|27atr=l`A*s=3_B2i5EM7R~nG4<){%tH*0 zPEYLoE)gzmfQa+(B|GF7CZ8Ydzh7eoZOFJWkPvg0Q?GdeN6lbE6b^tTciJBJ5V$ny z&$3xuQf;q=MLlq^v<7rZhSwPqCJwKiwTs=ln(*gsuNsNMkLDE(NiOR4JkVua{sq(x zA3AU~0rq1De!^48x;g;o&8# zEMCK%J$b-=3^=hxSHP)<^Q!2cIMxQdRLKZYCno7Es~ zBh!@|8PD#8znV>PWj|a!7tFN$=t`307-(i(6fvd#YNcoVmMK;UFM=eB|AiOL#^6`K z>3}rfY&>rMqw~ajM~Dky$QEk!UU65XaCr~%CVbeafvuTkB%i6d`1QnSU4O>aeW_@h z+QDA;cEt7OpogPbB<)|ynb%9JPr}b~WTn%S@3!p8F+81u@=d;Q!1o?r0XwtftbCKZ zOw$Q8C9f&qzUvve#5tUD;f%arJr9BRIlRvC4O6U;ta!-0TpG4+I&NXq6(ncq2v=21 zN|VNx)x{3THR=iOB-VmD{u}FP@-o=ptmC^3!&p9E)}mhCV`~yH*x$#9B@S$m7B8nO zU)ucLa?=izMcLDMQjlcY_k*3Qjkb16saLPVf!)_F*P zY2+SINmiT-MLpoI6+W!Vsh+sj8fz1d&Jor>JJxj4FWSjHoV!|9$M=y#d&4)m^}g>g zq3sFsy!4cuBBQQaH}k{h+*jBW1kjZF>2(_pnU$f(Gf%O_%|7a$mqA51_w~W22l@Iv zyx_Fc?Nz%(jOC-MirGx*q6UMamIKk4blk#c_q&GN+~x~APhCR|9$Aos)j^?D^}T6k>_q83g^z^spR?U$WMru zUo|YV562gU1DHx#h9gdLogT9fbMG`l1}efve9+?aRR+LMWUwBhB3>f+Ohc#cBMU$) zFwIkPfcZHpGr;&db}%LNzs-z{A=xecaEgkEzEPjqOLD`$s&BJMP37|-2v?)~?$yEN zRsS?$8KedSmWndYWLn()QmL7U^}4>g75A?C2M5#Kb+<K5g;e!DMmoY)k3Zz_`7VUQk3Mfvp;<+RV992 zDXSI_4+%SO4*wi#tChR~@^iphqK*%B9FRqW-Jm2+D&a@)F-2@AGf^w-@_1=$ek#v( z&*sF$Gg({)C^Dpc5{$=CS6nWGbc_Y~;Ii*#=i~W!m*PbL_@`nqbt*lmU)7jepf>VJ zv@E+DSgQWb?@`bluUy3a;tp~+$E@qI{XH0M7)+bo=ek_Ba*d%bu#Bd;=|q)E*mGn{ z@{09RucfkVcZV0$;Gf2MgN$S3FnaH_GTv8Bp+?%jEI6A_l?=z0#61G( zWfDVp8D&nHAq^ezfo`HXKRb0m?Kp2I9Veyrb^gxhq{JEmy>*4OCrlN zG%_->XBqPx>vy;DN*Lug3+SY2-d7+F))EVCE+Y!7QS?uz6RKx8sINPlKa3+MDwhDV zL#8e|XWnP2Lvwi&HheQ5h11-WY0Vwj{7e-*49nUQItD(wm%UGmdGi);;G-nD7_ za$qThfJlYrlX|?$*%Llt${;Mg$F#hO!1CSLuKW~vHy1)ox0mKX3Z`&oyP?Vy%E}{$ z`qo?3o4tNkL(wM&(KA=6i7%3nUx~{o_?S`78Z)01)lVW)$`h8daxD%EI)+45@Kx{< zLr>W_r$K-jftGNX;=_h#Mxr4MrS$h3W+%;jJj!bfF^pt0Cq9v}Wx5XRC(rLak_P(3P7RG(B@RZPiTGa3aOi(;<74P)tIQ~-?XX`5HW#{Rn*(RAfC z($o`&qToXO?=d7+6tT8@WM%siYx@zd;Sy_m)kHf3Yx~~0DJH9dno4EU_Yy;iscm5S98#0VECWqQ zcB+<5h)ajH7-wff4OaCU(!NLAGOgn*ZOutx%Tb}Wn{LZdJ=If_|N*p(N(3tlI?>Y^gNS|x36wBOq|i~sZdaOhNNgw%U7 z7V~r{X2^EqsY#%PjiECcR=Fi2+l53}^GnU1H;oIGZbw185TEYXvMJ)!@4iR~ism50 zVv)rgE3NLb$eh?Q3FzFr4(XG`8n3qx*c2=aCCFUNhZ3Xv1TJl;^+9$7jC6+NPnl4R zP6`BeSzdfZ%%13um86I-S_sI_C>D!3ukSjv$gVXI)4t_|dxR}%tS+DQwc)Kq5c}V} zdu+-0Et^Zr^OvO*4~c9aeedHTy|8}Qg*^6QS09yo)3?rsX#Z&0ylv|RIc~NajxNz@ z;chLmz<6YbX+a6|-}Ut#UTq>B#p(FgPx*8pZ);+tJ=_&aV#+jxETSFBI@S5gLXhO$ zsB3r3k+`vO_3ygv+F^v{(C2@W>KDXedJy@2&l~9b%yt~&M7&X|8p7HSBMFS?dmN!g zxQ8d_4u(cf`NpctXcjOE5Tv=$K9*Z3o_k-ULI5dM;|nse!5rnGe5j(mW^1Ydz<9+y z_rQQ{P@5Ayqco+(*BP|&S0TDk2zk;wVSBM%>xwEsC6nIp{bQdyT+mbM%OPi3|9b#M z>BaQEGn2T{6z_G6z}C>d)>gV}wNH!;CghrJc-g$dUGy_s#ge_I9iP@Cq1_e1(jI43 zU#4m(cY%Kn%1`rhG+kQ_tz-xtuI`wauAG$CMglIs#SogVk5pQ>N}5q(ljEo!zeP21 zeM%IIMLtVOe~S((*wmsXNbdp9)=9i6^tt@!MS7!CPjR8bMxlbik`!Q83UE~KIBQ|J zC}lG%Rer^~^j}jZpa8EslxRc6VJE;g^_iA+gT4F+tK|qQ-F;TyZI-ybO5aUa+g(l1 zZEV_kYxJUx#+E!^BE>QW53=r8HU6gT5y)?c;HMeA%GMpFqYEeA4aj95R#Gl+5ZMyc z++!(qAuF`xl4()cCODqBQ!wxTUSUJ^G4muFkx?}HkV&a@n6a_wlo<1&?!|~YCgbdB z)yntrnpCi}xg~$B<6#~UZWSv+XJ|AzcmCt5hIrtomDw>(77w(Tb&Bq>A*pK0D3&f& zXo4kW3n`f@ey(9)e}8DdB(xa2urNPRMQ8v*`HYe|^3_xvExu{=4CA>pDh{0e3aeuO zin>CeD@Al0L2kPHxH(%VY5%ZHoM(R?5P#eJI*USh|Fj;!|FOoT+v<$Ftr;w;pA_9d zEBNg8pwDQ;z(>l`VsQCUbz>%#(nCIZRX?w2K7Ef?9b02(s=OkKu-4a75S-K-+LArk z4S$JY0dJDVs!B`;u�RsC?d7wdJvyg3VZxr(x?8O`XY+E&nU{wv_JQS@3tFQ=LDn zZO*Sfhv!6^n`Tov4xOE49chEb{utrvG4x;GN6ONRApE3l44Xc|&MA1O*wYnfkf(Hc zvWu3U0fy`zRk}{vZ92`X#mAdq5#xu2=->QfePOb|rcCxxtcQhN!9+?qmo37N=G3*1 zP3s>8lhCt4x~Do+_oVBu_ycdjEw&*GO6B1QSD`hMOwD>V+dCU!AIZhvxzk~d53}=j zT;ZSfqjhk2cVF8uglp=5%<_|IU$?SarWQlrU6wEwQ3x4gCcNb$$qDOlexFVnR^z#? z=DlA`>1@nmkZ-cOgd_n+jS6+>%p-D?n4xp(vqCVwk60H)QyxG7`51QEVTUcazS!7W zqrcxuf;dhgUMyKwS+)8CHlEKmg}LNsX7A@~_Y!hmwHElTvUt`Wb;ufuF@Cd-8BLc$ z<@%Zq=j?UwrEI!$NVmw81ONu#M1W@)f58$9e{6n-c40kI>##&Tmrb0-FO$bPeb9-^ zNzqP&p3VmMQVdB2>Lyv+d4(T|6KG2l9fupq_2=)(djoFMmxwMSRvW%-k>p zfbw*UY^%Jb3JA^1P|dWr^U2Iz)TmEQ(!UZY`@y1@Fl?Qm7UMe@j`}^#^;V4Hod=u#@OlME#{X53<{-@nf zeqZ1}=9_j6L0DnO>}>6r)}FDLGzpkv)S+lxN5d5IL0hnA+Z9hltC|kxiq|rCcC_n6 zbs&58@v-+g7sUMW9odB$jmU#ppB*h~y5XBmpsW~K(Ediv!asxX*2(9u9CzBN9;Vy+ z(X^TR(T2}gKB|~)*-eUrP1G*Ft;nu?9n`{_oNCFkW8a_#Sx+#ihq!&t4RYltRVlP1 z?E9=wTUqY_`y>idrS)1KwsfJ_|NTfk;5Sf?gufkfh32(3>I;@hD33jCCzu* z$tNV($!QIb#YT1y7aT40;x}22Tcw7o5Sdt;+0O>(TnP~3+Q+tZMsJ(KKO^kJX1bsS zNb1<>6_c;{RyMJBjwA;j(e;X(abP>)VGdcVubM{EOvd4GVd-Fek7su(=hafC1 zSvnW$+rNSDVl`VTi1!UCUt4~R2hx4F64Qg3?aa-G&naERRXmHk>Tx+Oy$m|>cArJOjw{r!MQ-l{{W(K|C7)5%{;_}JN)-$k4#d|O+z zw=8*cJo#L$$9(8KmEX9$WOY{H{nKHp@4 zgzNp2b&(ZE;}5S<3&Yg=%s;W&?kf&j;jFdLT}bd|j+{kR=13iJM74Bq1|7p%|U&~t@=xI-q#Z8%Z6PxOWL_2sIe0lQ_XP<`tCyYis znz|c|1<}4(yfBRr8Bg>rU%yB1d48${Pra0!zO?eLymrd({O=m)k0vR7F+AtZfBy4~ zH4WU516mdnSnWRUkp)I>YsWT?fN=p}?zqX=TYA!WW-S?S zO7W;E;b}{|`7cSotiINU=Tz!S7C3x(=o? zGOFo5{TgU0Pc6Ok?J;HU%y~?UouPT(KN;n-Migk7gEpvzV#*40~75WY)lw?CExz)Mn~u4r-J01klJ{D&vr$!!*|o|Mb%p*yQY)-(h&J z_B~QrWiS66j)CIVuUG+_x%#y4n+<7w0{F6KhkJf+M443VbdXHGEF9mn)Pt;vyXrPz zP73UY9NBs2GWG`go2RTGmqZ1&GC{g;*5wLS&( z&!+gsl{UKal!O*B{`ZKyYdszUi+pYsZLEcWE)i8K&yVHB$=Kc->jUw3Q1&$3<=Cxc z>rcU^hrYU?44&OKC@UCh4hCT5P~1L)>*T))$x$8*Uf_xOy0kAO23iX*}?v67(SNK<9zUN;Bi};+= zCCsd!wYv|@;$zwei~t#{pB!db{e^q@`qZIZ(mos9>-Wwq(7%#5v+&NY02m|QqYW59 zsQJ|J68pzc$mp^=bEUG`S!6fhYDZ!1+G{IGa~}T)Phg3CYLN z$vNP=4o>fjnh68+t8leAlqg>xUtqj{aYsR<_s<*>BXp(2rD?{=L9OKF=j=!U^1 zW}@p>MFIyK_vhU@7~W5T8)W^b?@`*PVK%K`-=HlH&DXHPu+Z_#VT#nb_eG`veX^D- z5B0}9+Y)*6+;tAL=u76w{ z>>_pol5uo7jn_~7m9snUP2uQL^g#xrFR+{ci|HLf{(`B9F|}E=mj`Fo3U@~&Y_4N) ztM|+6i}0XJ;=DK8dI-RT+^Ib{z8uJSlTo7$GieXX(R_0(BB`A4-MR7`;cY8KxF)9L zeOt1F=T^_Y6Vo~wG3;h?xpj(&ixyd20(9hP3|rbq*^>+qNY_5n3WTczNV-z;GlsZdt?Nzj;-mTz`N&lgi-p%DLo4ylN zcK<5YOH%d-XfS^{byx>1XxgiJl61sCdLZfaGr6hV!LoK#NWY~IzW-+w@1O00`}wlX z&4`Qw>E?C|p0i|JwuKa2gm>SJ^yaux;Lqa!UjxP8*L7_e1_Liu*3p6x)3vCtKGgHX zgwRYBHqkV!6enj+q9>803?YT&6g#iO;KCj46yF4#=dAJo^KNvs?dRuy)9#?vU-&TC z8DgbXo;Q0Uu}eJG?wy0kPlE|f5<_*wGefeDG&9p>$J6B$V{DluEZ-Aq?9=q%@N88)%jne7T-6S`QPm*oY^E2^YVzD@FGgU;pr(YzgM!TZ@NY*LAzJsBVrKyQ;oQPp- zArcc=$w)BK0wE^-2xt;)jUXhh}=duE1$z(y;yqs915nM zlSd0qV{wMU*iyx5MtJJHmUT$ZF-9wuJzwaECR(B6+h#|*vH^>PgPyS3QMf>W7qusK zPONWrZY-Y=sR-Xq55`sH!_ULGLD(~f(`!fEP>NAEYg<%V22Camc(hWpCa!B_mTL(r zkxbf5?u)X4y`Lb>6D4wqe@Ru`WAGwjhpmzOVk%vPdg)VG zhg!}&D3;aPc_WN~6y zou`OjDVB!1zsv`ne_|bn+hRQC*g^{Ha&^1^TupOXs5fyBR@9Q(q!vop^6SJviYlqU zN{eQFSi|44kNDYth@gz0EsWz_BnqxRV5F{aCq%-7fM>^v3-8ei5o%Xf(BY8Ja+TU)Wareix6Vw-o@ zIEa*tur(}*g*`s(-Fe>JQ3%B4pzNH-o_&Rorp#hrWo)Hm&1>Q=)lSxCzBJKtamgg@ zevNaVmZ7$f$4MYtDmgSLr`a0AZp?~L$cJ8^kX7N1L_$o{n<^{ppp0u>^#oJuSqc@9 zN+Sukd5g=v&H&oMC%@0K$qPoi7(butLN-NM-X}V4a z9(NRdjL!fpl>;ar@FcrAtFCE=lot>`4=3{Kru#bg_s;{i!OCIY^@) z`*aqj+g>Aqc3T)tJKsU`nP)eah2lff-F*y{OU>U`@FxQVV`!-2Jeg5lolG6L%biVs zsB5eiX{zE%m>)=-*5d&17uJ7k_NcF6KN{v;Yh^p0Q1D1TW|7G!{@bAbYVIUvwoFJ) zK35L7o(~Al;pw_iHz;F-M9p^mMonR5kmA*R5}2SQ6$SaC#?#YenVD65>lwDCq- zh!p;Xq2`!0kqy1@tM%CZ;+Tfb1ZXeQ`y-UWp#N+uS;?$bCY`=vTq+EFUM+ zLWcU-GV&)KJzMiJY0`GDo25n;fxleaAc=`?#R*UH;RU>F0%)3$mYl?TjfCbadMlZvp5N#VQsT-wO)DdSweo z;nbvG z2hoo;w@SBF03yBs8gfhvH`|v)c%CBmX%Z^g3_|-*J7rY72bW5cj(v z7xQcay>j)j^YTb$`NgU#B^TLMmo9!K$DjOi;IotU+hxodHwtVE!x0}IhCh4)6UIkB zUq54#@AM(Z#Zu3p-8y>LV}@-i;?L|v&bW4*Hjk*{eW{(Wn3uh#DG)w0_xYKM1=jeu zi}76B(e`4+b4K|mP%J^b$=dB{-UgNON#j(L&}OP-?Y%88FJW%8a#M@-Z8OSrK*N|n z+0ciTxYF)w0Y}tm_ z;>j>aO)@TnPqRvFrR@Ea9BVqvy(~4?R7rI-mRhJ2C6?GD*#}^?xsKx_ShPKPVCAkn zw!itD64ffmvnpkcyb@(=HqmieS#v48&B~hIrm-<(j{A0Vc1!q5b&<*G53~~8I##{m zRRyP6c#EKfVF%k`go_~@X>*~^POOb8^T42)oz=n# z2*w8?!o0is9*u{N*?oum?`H3eo&5zhL*r(=ia_VqDR=fczu294Plz&Z;0nXTazP=`g8Ee|_cp!Wd++i98u1{qhbQ&r zf3bB|QEh$E*8jIqoYLY>3lv)1U0R${pg?hV*Wg-;I~3R8?hxGF1H}mtJU9do5-#_9 z{q7k1agTAv*=IeRHTRmo3C+?V7xjEVAY3_yPxm@9CX3U4$Hf_Rb-V?oqft^XfR-m_ zupn+RO8cfIaG%DWpj%lQ7hRn7m$~bufj=wM?lB%AI0Ur0i|QWZj$Qbn&av_ibcTcd z1z|FaEu2^X?IbvKpwO^xJfsZ(e4+KXsE;Kis7v?b`9o_@?V$wk`N`5T)8+;*>3cTn z()S(pr`W?kfqc)m0))Ev4)iLZT0TL!2DF*(4(KPP@)huiU`I%$dq-ZqkBWNg^$P=ma}aFLFFx6H`ad7dg(856 z=1Rvdww`M>Zg|}_ZLQv+T&T;$L%=u6Sdyk8ml>bv9=R2jj zbrwM`?dM|P`NKL?{-I}6QcRSfu6tU#p^Vca4d~%VQ^g|Kb6+;j%g-&x?_N`+fe_R7 zlxzE;y;gP@XGV{`#D0Ik(~L{`V6@OQDtDp{QoF>BcM8>tT0iV}Hd}d2!PKu;-^IEc zf$!uRp8qqkuACB4D(v|sqSAXnAmwHErFS^eK4D<;;`7orsuz&=ZxlRO~@4J}>7uIM5rPI3CHroyo-@BCm4(3m=_^+2xrI9OZ<2j@}d=;L-rz~&&*gh&McN7+K=_P-^Sk`jP9vS5Y%)#GTLMo+N9$BN%(u3=um1 zY@cFBx8#2Jb~D!!|M4RoxciRBXPAiT5az92cQzUwq&S3G|P%Bn?%~XE$AwZ=s?W~uHk(kq7*@eB<>ck5fVg)3z z?`1|7P44HG3Mnm`@wgGZ{@3q1f623mdG*c4L!NH>_tM+x@7)WHD{cPz|1#WFn^J}E z=w(^iWXI1y=CqtGpEgdpKK(yGpWUW z=rAea2Y#aTQIolB^Zar+zATd}{#!+omzL=li3gT_y{`8DxAGa0K<{v(}dTBp)b zo3jveANEHqANJLz+di6`^;_$+5Ti3r!$)#o=N@tsZ#TXQTe1`zmN-+0B~_B&LeaDs zS&FMUMQweVLd>J!$D}h7Wl^H6AzF*UuGYihHIwH*AcP~_P%Y-Wbtp6OI9_c@xZnm? zXZpL4v&^<)4{RQoEu+Q5nym{25xwf(wCnycfROgpPO;}le@fTWTYgR=Im?`~KVr88 zYRhxYYNJZEj$KB64NKck&MV!g9iPXi6Lw#D&=&{WYhJOjK-b#^zz~zP;Mmojf4^!+ zFAKB3h`D#Fyj~Mv;sZm#piMMgzSYXw&877e4&mj<1lO4F6prTolYI6q%Xk#0KA=qt zs73#LlU>V-=8_YLm!kTnKlCBizD38OAGC|P15{w$Ke#cA!2WG-3x}M9h#+k zgSt=8C`*xJOMihw8jTTE`{+$wns(|#yq*s5A_*;}9fqcLn7@T!T-1p|A{+QU!8#tr zS|nxNcSvOt_s|xlZ+C!{#!25jfF%V`)Qk6&ia@Ps84hLDFn~P=gS`Ud?A;E%=>>yT zz(rEpgD#LoaykB1{Y)!2%VMHds!FAzJ`ydnuCED@u*&S#kIC*Ci)&MYW`d*}0S-IZ z`2hs$?#5MVi4ITvcFzYPCk*8tBR0cCvRnmb!c(DR&P_L{bGEvf^M@-%+ZVp);Dbfg zw@lCgp`${<4~SbS&||siyxxNSUR%RmHAH{h_KEFSNRwsn3YrX+@uUIw47+p5v4n*KQ@awC16 zpxt%MV9|70o?v9R9`wvfb0@A)pL}f-2jTJ zAOk-YM?PU}-=BiYZpF?9eif%vZ`j6zJZC=j74jY5UfcLcxwm)2^Mcy zAkMDTYzeb%F1{UI85M$b_LFQ%=%lS}CaEqDDd%)qfE4^BlNWkj@8kSAOB&XR*<$`^ zxPnMBhvE%u=J63+GYQlEgintLjYKh84)-Ke%-~&^)?B8^DHy!M!EL`F!vo>B5FEAF zToY{erHR|UuGgXLP3#Ug7>eoLYcOC>yHKt81f(T>{+0uP&dCUSM!;-ShYb^#?`%)x zDrQZpa!T8^bd?9Z{CW@THkvhe##1~a1~sGf?qj@JlXmmfQq-X2*0zA@Op)duS~c?> zW&J@nJKqmY(I~4cN$78y?td}c-0?j{Fp<~Z8u>;|C@~-YO#gANK8vO?vdyM9wR^4b zk9VRAtV6RG;T2ocC0Sa1p5pMhgRl~S>7gLbpqqlv4lg7E0YmY5X zi?3xj>&bsJc2xfrv|FumI#s+i6EoudD1-j2*60v`TQv>}h{jtqwXV_REw0>aoVHi7 zr3d)+1k8Ms2giJ6Gg)isktO@W0a)}%n>uTJtMyGfYF?E?e|kVhMR~@e^>zJ1we9=K zqc8s%Dj#;Z*q_i|YX6FG67Ada>!~T96w&0~6e~!8TecF%#fQ&NbNY2zD5uyI_2p|| zxk@t&C6g6v`~4al|GXH*ab)upizlQv%)Pc~y-;Vxqj2M*YXK-x`KW7|>9dgOU7KZ# zQEy!_rEucbyIngu9z2Yap0!raTR1b@LG{Fb+4MNy5hDhMTs$*57S!z8Uw!I`K^k7% zNM+77^3C^|tb64w>7F$R7>+mpB-Zy=!YiQ2^f5@B@|BQrM6WU-Zr{_LBE$bPF;oQ1 zPXg|OR>W>B7kxP=JZ38RFTMGvz>701|EfVk8NVqNye{nTv@`i?oGl(FtSK0nnz1*< zYP`nnaC2-mm;P*yo)^#ZhK8PJxNb-MWZvsDQ?n>2@mw1%fZY5m9P$MGL&Ix~mq#GS zm9kc7oLa@6<-*Up!et$C#E^adCP*xCe%j`T?=HoWZ==BjgW^p{Gg8bb7pk5y1ACI2 z!^$1QTFS9s4#j>m@esdXj4GVydxkq*AC`Xmisdr9Z(+5(oU}`;_BWFB1FYiVizNe+ZIQ1mlVvPZ1Y4t@G;IuMj>Bd!BOfqbUbnM(>s4)1}ItNK@=zxLsVji5bvbZ}*g z=;u7=jL_GM_nI5yAlDDBUG#)pzcjD(mr<>FS!0P^;rGb ztf06B=89;wY<$iCC{mT|sI#Ov_EvO7cdo+p4HTasAwu7pTmKI@8wgPgA@OIE&7;xe zgT9!ukFcws#Yz@UU3jdZtkJ*3StA=PzjJkWGF)1kKX(r;fLyzz(-xg(KVS1>i^gB> zrq01(Zc~O_H`AUxT*8g#F+N9KaGPTluj9?3CCKysQtzn|?{(r&1x~|MNL~eJ`#z2c z0NsVq*nxDM(noLw2{WuaSzYI!hWo1@sw-knKkWI!tyW|B z?G?R8hNer;8$RRIyn50UH-)7Yx|O9IO+p#}dPJEzbM%-Bkq)B}ZudHF`=J<1pg+JJ z(a7kMfXqWv+;~G_#h*8^r)g3n4|KH3XgvfwKmeY z#7y)4=J;nuO)~M6@TqmZ{-wEO{cf$hRk5C=@h|pexva3>m+H>R)Ao$WbbPmf$+_Y- zlBorIs6FC@%IHa7w&%eGs2mZxE_4*i$>RS;oHX1F-s#$6)A*dNwR&WF{`)VA^F!dQ z{cqK_o{SAB8eEKPNJKXE#5wejJCBM9Q;0N!2-HlHlLPRr4rwCd?ArPdC#0NO5-Q4x{UA2E{~}z_Yvw z*ul7FmS5^bIisRQyx52yG#3|tqsEMf_2q!AJIJ0nhn6^~cl&an(Gbq3xe{jakkcL8 zw!uXrZ{r(W@4U#pp}SLOg*|LDzGJ@qrYzeM=Q0Nrb+K6r>(e}2uS?YF-;SRW#!)l= zv6f)BPnmi6H+@c|Gri=9XRFoPM?b*j7hfxyTcjSIyntkaXT=f~v?!LYeYw^#s zz2Ci4y}0w@UtZR8`9ed|7);EC_?b$VvGPS5=gONI&1S?1u=S*O$>QUi(KHgcxoS#-MxD@5y!SW@oalhwR5Pab`>JhV;^&_lL<<%dOu~xw8-n;r00KQM3Wnv zDEjG_UvgZ*Ght@8H+D`uH z+%3Qj9(o#B@1HHh|7{>=3ckwtP0PWmWq90h$5Ra$84O4#8G z7^<7IfIW^^AQD9*Qou%X!5^Em!)<0R3}%0kIxMTJyYrI~!_u0JMHjZ{@%rA0+0KS{ zQv9uc{JN9_B9U1o)`MKGMmKx(W(8lb-}9qQ<01-N{pp2uon5%oG1i^@x~&1v2dbpR z&JE%ihkGy+tiN29rE8_-uqCe{fB(=Ae|g7H!`W>YAf3tjzT88O>v%2Q6Hn=xiz40Z zo~Nym)YRHNM|c9K=a<4EsSkb6ul^6ig;^pr3L@}s7`WY?uNBzFg83R-LyJ&iCtQ2v z^C=;0(;!r6iebsxHSFee6M5gTdh+iC@vZ6FbngK%6&{~M%!WTg8lP7etUC9hb2KC4 z``5-(rNK{6D9L?wr1l~|i=){ogx2-0!ZKJFKqZ-z0Yjq~UR0G<`9VUYs$_^_vv;^l zT8Y?9gRZ}Zn1i3Q-EgHt|HFTiDBPt>fXgbpV^tMCw*6IzOd0YYGbqn^D$Hb5 ztKVd-jCc3R=)u@+#z&p7V#}3sWxhzDOugopj|yYeWg@@gp0zd>C7C0#HmWmipvIEA zSD^#063p4A#2v3)1rr&zVtg@i8W}yHRuu~>u~2=rsto9Z$SQC@$dce#1d?)C4}ZdR zjiwr!L7ro(VFdn{U-z-#x9|}toMrP}8aK!0n}ZC|3@4ct z3tf~P_l&CekFWa!aeuTOs=98Ngp*?coDiR3UYhQ8DFy@sBIrCxt%xj~b)6xOgOJf9 zA@>Lc*<8vZic21-%7Jf^TcqHgk`gEbMB#7RH`zDR7t^l-2WxT(L+g9-(tA=*>83H*?uZfU%A`k27(Q_8Fz;Xk9CiSv|Bjc(C)7_n~;Q8E8 zM4qu6FJ#u!m1oQYM=sIfy8mG=k*du~HtQ_mKOMGs)@7y6`=i!6z}bT-m0W4l38bBD z#cp=S0)JYQvFP51yut(@1uMNA2K>(O5oNjaL`DGr-$49=VW-^fA;-h<=50n#4X?b8 zU-~JtGQR?~*!5N67SFccz49< zu#%(oR&B445hOkBXXf3_^nEQSPpl9lY2MS3m zDk636-(*iD%erOHY^ycipg?X!7^!or_m?Ys`*3T54}3e+?z3*Q2YoahssL5K9nROxu+;oF+y5Dv>F_DmJ7Wl# z4Gi*f(o{%aFIi0{E;@@!Onc(e*&1~qNe1_?A18jh@sQ132PRi-)?$uCCn$*T12C-C zs=@qEf#aB$s$%^g8*uK0d}uJowQ{1!K_|%H$6Ln^K(5T%X zme`G?80{<;p?c-8E{`3@sEpodFAK}}5GjSSgUKbc59AoaJ5ZnsIIFHVIEoP)dto>2 zZQksf*x{JiVTBmhQ7QA@nD$i2IyW*6Q9aL~)hWE~sw8KgaFjiBzQH*&y54MQcY(>` zidZlXm7IPl(Kxet*v&EhSVLmzaO?sMY!Ui;TcxaqbHXkeqzmCGZ?gUslUj&ns+~!} z$yjCYbL8emay@X&GF*`vdSn~rsppF0%J5hQYDd+EUbFDL!me@|^pV(R zi7ita@c+Kn|IyxCj9=fu_`7SRscu0Nx8Jm3YA1LZ_FbaO|T!7xOtW zcSE6KW<&9G3GbPu?edMvzlhh}Bnv7FxkNV&{`Y2!Q^|VoDq3@^7bFXM-pC-c$mU@` z2FICj#{~L+0(yPN-~8{9Gx>m~e=e762;IsNr)^tajlMeCJdCHX`?Q^xYT z0#Ja-XAWxhBfm!5+0wCM6(WPbHqoq*M#o|a>^phi*X^uYXMHWY; z^uUAU%TuH8oBHi=zOLeu=3!ub+E4q9zB^y%_2VoO4iei=mG+UamBEpN-MgP1+-#uC z*dft38rv$e?FYQEn!cn$DD5?D(g;V3K`XK&`7^Fvg@SvyDS+gqkTNOPP962eXR zz?{4P(b_;(_!S=*Ofop4tUDq$0yav1MIF0R{wtdfIgfvBd==lmH&F5=ZQPRoqrKJe zuKSJ1zfwRd%d>PsN;o2-H!b}@mbhW^>I8X2+*lWGSZM*>o#^-f&gLfNahx!y*Fp%8 zrxLyz+!|Q-<|*|{c*1CB&@{}Bx-$(@9B>K;Fh5f|Wexr{nS`3rxY)l^KuLT>^CIh1 zL9?4`-d_ zW9~1H?o}D-eOGmfFAz1J9v9SeZA1RF6(!wjxHf?Bberknq{|N&O~{1x!TSh5+)Xaj zyTP1Z|Cj|H{9f1B2U0KD`#rJPLM-$CV^$7^N$?ssDbVes@4RS~ z*QZ(H`FlrgJBt-vv>CG|zy^xiU+tQu%*a!IY%VA|J9W7<@LlTG&@0PERCmtbdV0N%Zry|WKEoC5YPS7| z`6;(EsIGSCegvKHh?rmH=Z<_&r?yjYDJ4ZFD$nBf_~UxU3zrC^cg5tstAs!ZL$CYB zV&gzCnhW1kQZ1`yAfLi7^!&%+*u3tka{(+m^Dl@Y zKZ|?gM77Bsb|vAWt^({k+gH2s-D(%~W4h3%e=KqOKJ4DILO>RPAmGnN$q==j&fLbz zas4aYX3|HW(6rZR?aj80TEfL&3Ipfkp1~xHx9lEuiAFj;lD-$F48xwJ{eHywkv4F6N)ddXDH^tx~M4R4dwSefZDoG4EGDv&x^1s zvBc8_wmu+X_^~SN@bXo5SG#Sa@sAqly1$TE5xq3Z3oZ^!;*1XD_t>%-^>}i3WUNV; zh2cAnrAfaJn!nv;ym#G_xb=FJBAUVy((gO$GD-Qv@HoR6l^3avBRye4XhLjC(Lg%S z83o5+ArCO0FcINqBo`l!aPeyhlx^9ip&e2qKp_Nx{Ke-|e;NH+cqZ&BR2jJ@jns=% zNj^es*WOpShz@bXyrV_o#dD|8{9vO5eq#x7*BbnLuS3cX+gV}HwQwl)EM)eIK$?wg zj`)04K>Up7QXr$>JUV-Erxg@YxBPi#$SXDpv}ID6T|p$?2juyM+=;Du9zdF5+DZqg zhAjFy!B9y6IP9syw|~z#-7iG}(p{EsJ?gBk7kH1nA_&a0L<6L|7*07Hfi@r7wWO)$#Tr5v{??P~V5 zBi(HukP?YO_$m>?vu@I`KK3{skm*j~nH0mEV5f zDxVA{BKE5;8CM)@eY*#l=Bqxn$fGt)V4`-5NW0(XfbF<~$14-BG~z$fK^cq&B#Q z60|0cCeiOuw1V4LSkHFkS%_WYF4}$lRsGrS6Khw1!FV@}&fDhj0wx-RfkN7n7g&Rs ztzEwu-%SoXco-sHyjZ)P&ChSIv1H3!tI@Z;P!jwdh%eSxlEmj_>~*0Ub1p_H#xSH& zLv~h)&|I(|Sbh-)a?4k?=-|t$8*2VA0g}$Lp$!JjiQ2-=DjQtK6X|}#v8Sk#g>&eef`?Ks zN%Khx|C&8qB3?%={Y&JN-xy;g0Eq$Qs#$*MHC2ch23c%7JMvr3jh&)=d9Jop7TX2v zjRAK~2f2qK-EHenbmZBDyh18guJ!-+-Nd-Gcj=-|BD;3(kzFYw0_d&}{0sQY!w^^u zz~S~+`{?d4jb6LF`=xk9zI)Qlw(MLEZP zu-hqcu(aNxq2D=f+985@Q!=HtsT@KoOi8BhY}QB;>-)v|TFqt0F}T}MZ(C`M_jCtI z?vY>W%y>Ib^!y+2;>+nZl2dF~d5v9jgR{KDa7sqz%Nc<>%+Eid%QvzkZcN#0MP%nh z8Roagb!O_C=&<-ZaK=r1t_eQz;BnR6T%yf#X#mKYd3ZKMq;kw6TCJQGswnh5HO_`= z?rSqQm25c4CQvCpdKuJrBut27u(ssQ-o%L7+pdfT-u&NF$GT6BD{bV+^hY9fy|Q1k z`5#y?q~z3(EyVDZ_H`qRD-5);mt`bnbylnYi6L)o!{Q|H7u-x6n=NHw`xwJ;*!Ha# zaQKVUUCEXLhP~xyD%rbzEfd|}lb9ef7fHJRv~S7eCCPvKdwuPp7RsZejM%Ajq(FE0 zdG_j4G+;a|0?zp``3~P-AZ6f<-Ph@g@xXvDugO&<1TooqIZvj^gf6r`K$DsvYEQXB zN1U`@?!LU$D;Um=4d0gs&bZFJy)^e0#0tkP-VT;Tmv^>%_&0a`=`OnH54PFE-UoiA zS=^s^H*{?DALS(C%=|u-o*9<&2TO&&hd6&6z2CGlbQ)u_5mCa};~+!b;r(d&&F$Qq z!)7E<9VzQrI_vD$LadBGq-7Pv=mJE>(p4-T612rnDtvo?FKpxy zbD(-osXzbT&5Ui`u8@O@7eYBF$L3q#-)oP_FF&+7R=A2YXzR0+MVJUD{&Qz20(@S` zJ~=9E>C$cm<#iNhFA!Rq7QCPLl#GJfnhqBI?_yoZjsX>R@Y|D}*v%68mA?M)5)W5V_1> zn|4qe!-+Mo${ofbPP{VRL8*Y{cOz4=sM&H6RZdZ(xdgE^(?!0R@U`J)4PkAQdeNAG zHdZtSO>?_0i?{&v=RV=l?ezqs1|FioT1*f5@|K`^Iw>N14)io0zoCZf>0Pc1d&XSt zOg4VpxL!GDbhRv*dG5iG2KRX}D}S^1b5CDae&M3Fj81gxU8E`?T}BPryr%SMiBdNT z3R+f%V%&v?PHeU-pO_3FP*kzT8vHx1i<@=c&9{b&Tg_okK7akuiul@+zlgl2i zu8RFNTbd0xtoDLeRj^wKWptkZj28Ke03~^o;7j&AOs@V1KN)oGtS!dxE7o*E;mwEN zgt+r7Qgr+6ZPg1z8R&mrDKcWzTk^IDvUoX~;OMir21z}0Q!+&Cp<>!-m&Rum=~$*! z0Nmiwmiu*dTx)|U`3TQXH)b9A4+*ri_zBbu8}+SkO(KUL<3kOZb0HD<-@ElaHGxvB z7QuLhVo+xACzXjJftv@9#gUb10QT%p)R89R=!wLae^NkAt8XzhhG{De6(j9HE;D!> zzJL8oH@r~%ZL-C@A9rTKeSScd?)#vpq$sD{wx7aA4^X%QX)bEkF<$e zh7;Aw^nuZvwK5vDFTTWukN@av$bJTR}(=8BcU60MN2z+V9D><8E@ zoX^Gao63U&ucv3O;o2VVOfNQ>3xa++q){3|$5!iax>V{W~xRqL!5TIBLy zKrW6UAQrKuwO^lWTm}@qrQ!6AM3Mo4%x7!s80Y#8H+)^8iI9FUs;a?(s$I4+_^9f# z18DB5lqm@9>u)`kNd z!<_l0IA*1uRLa<9z)9{*gB37xk5S6Mhfq7mleWi?coj=tELk)FL;*miLaL&!L*pSx zumDt)Rkt#7Cj{j7clr?M?gF|Uq*&_=vWT`_Y+7&B-%q!xxqgH4}57& zQ7F~|y*fQy<|no}!ebMJbl)0tWkHG9w=3AE(?;Iyf0Od+i?>{CK;oh5jvJ>7(J&FC zQ6j!hI!xm-cRjq+dSq@NV+SKu%%EAspiN~`^AtBPu_oXWxC<~a?9blYC_Y|=Mo`et zBf&3{+wY_ZUk?F;rh1PkV-#H9P90F{6$6~grh2<`0Xf&5 z*OD0zB&J)5-U(Z3C(R-sL^ZnCsnAywRH?otaU~m$c`86PHy&?^T6P|=j+0Dzo(-07 ziS9@qzjsC^hp~ctm&(tyMso`7S&nR=6GQ z@PgQN0I6Uv4}ZZ5(HNR5ZZU66zU$kFPh#G5mowM=Q3%rIrFV3OAH+P!={!oCf&HTV zQ&8ruu(MX@QBnSNC-4*P#hCsod%5RzArjFrz0#5kqR4FIW1C-z!PRMpTUF^d(I_8$ zI~}?7QUyMGTu-`pjVfMv@XC+sEB<|8;Q!*En3)uim?^Rn(D6jF&X_XkWqH4Q!{3Tv zJhfdAxsZh}(uX``6z+5t6Bc|DV0$p&@?vp>ib<}o4?;O>A&k2xke4Vn+knI?r?=@l ze!vCSQqT`2C=Q9v5R>QMepO|c7FHaw-Dc~6l|+`zO9#P+n>g>k;^)8phZ0$g09sq} zZ(%t*rP~o|74PW6C`@*u`eAIQJ8#b%n~3NF&J2XVSY__?`kWN*7zi&r)jYj^d0$`U z>g{T>SCDSahE?!#3Hz{7{Y-#<|&GZT>DHSXBx|MT|pSl|AC^F@%9 z{?fQFR)zNPCDZ6{8sxdI8vMVx-7D3TD^zgpvp){jSyO=8AE0Msc9cEa?mo>gtT;^{ z5T_$-VgitJIYE~8=@sIs2OM!)!kuwgd?vG3l&LoKc?M;1w$4OWRqmoXZcTb8#J~x# zgCCG`SXQRC810+7m-<7fzW+4blkM%FCB`~e?Z=@=iKow#`k5ahf(snPt{tuRrE`wn zICx5`E-zkdf2W(h2F!LQ?Ogj+bB*~OvyMG{){t466y0L~X{A61biEWb2;Lb=rsx`f z^i}eWCgI7AJRP5H>vr+Cj>}aHbdg)ru8v;ydA_TAlu^-ZNia%;TYf3@*?&XW-uvzC zu$e_^UIy7vCX|ic^d=LYX^|5qf0vnH6_MV-Ik7asck*-J_?^_jB=@HY`9EA$zUzu# zORz)sxW$XkC!q9IEn>H8Wh7~yfd?al-DJF8zJ$&FVQ}eAP%+&<;3P|FBXZ4WX3vX_lWvj!GU@)_CqPmQDAY9brgm<;U)6;ZzZv`Z;7~gk+1vRHbhPQ@y?Oxwln*cE&H&r}CYt>8Za-Bc zOfY;o%e%~88`e`9{t9G2GEH!Bd0f2DonaRW=`kqsuEHyS%10l#qRX)HUUL8${>Ya- z5~#fXR%O`KHSpSSD}z0>hos<8f#LiU1TIZs55XlUc^Jm4c?_`dS#=6OLE{&eoRvGZ8 z^fhNhZT@A==McDas`xslT>he$Tu?wUWOpHF;9dhu9;XX3xcoQlv`n+`-TdBYEug%s zJ`#@S>{0BAqzxN)VtWvfv)5;fmAsgpoMz5(M6WlyzZLwi*62OoXBQzifSAQfj|pFB z$BA1q88~c%64UH>yv%^|w!L9>w!iP~Rl_j^p9UReGyswvp;4XY%LhGuh` zd;Ed^OpHht)KWyIM02lfSd#X%4jK65)P z9tBp}`Zc}2f!5&pOJbWnR{AkrkZ=CU%D;goav?hFmG4qbf6J>p7d2R#h!*Y16m>&K zG+6n~+nc!Rswy26>{nE!o939H+~1~5g$402U8u`phKlh4ARVM4DuTc49v|B`!o!yn zwTslvkSmZ~dy+(bBT8q|>qq?MlG2pqpRBM$geJj`VO2^1!8fF0`Tr{vDnpz=cA2%* z9~%l9moJ5qpVE5elGq;QiiJ%p(o7*J`W`NtLT6>`N=_+`_a6S70K z`Mi0T&j(GEaLl?1%fB&}B{u|z#m>Ns0#g@Y6B=gP;1j z6Dtg~nr1!^o-60Qzj8R;og4lbU3dIfN7ue)n!5v+TP)T=j5fCwYjWC(1S!#euGG#U zsE5jtUZA^lF^ZTy-b(LIx@)&rQ;8QB8LI zHXfX54|$@CjB0{s$To)eWKILDsnH^pMGzt)ac_Me5I5RUpYyvYqFvNHFgI!j^oOuk z%{A;Qoo`p@qqUB2Mj0*rZ~tBqxYqkVqYE;S&_wzlDQp`Pcu2xl$iPJr!g}CVNudjR zyV$TqFK2LEShhf@*cRzXnZZ6Zf1PNIPI+jr33_zRs5b|+3XgJ5906|P5S+2c2|7B~ zC_BA=;&lTU3^IY0IbRtc<#pSaSt$!@@I(^oHt8S}D{@?yTd`mCL|1L-1(b4qAL1Gbh->pNMTJS-yzSf9y8$`^-=s>> ziU0PTR?Or$uvW^^`8>m-F3I$v*xuaPX8w>(@AAxLK43vlJzF?1<@MA7iI94JxpA*Gm}T~Z@#}w7lUgT8vg%k zHm%*i0$cMWYV9OiWOV~X$Pqk3KV8IQV)gp$`;9)Y{S&MClKRO1hJes#!+(GLm0(=Q z`39nuUGrQnXoTi~O?IJb*~*UyYq#q<-4hdg_Q;*uF9plHL87= z*n>F&cgR1WWiqN_dRxmm>u8g*mZx&c=ML1P3-Q8x_Io@v8?h~IFcI^>^%I1|TrZQD z_$@?VYbOAVkb?T2c_xWzrtY+pw;L9mK9)ervsIGBiLOM-`d5SvrW#HOsYglRRIka_ zEC@2#E4G<^GU!V*A#P6Q1AvCc=T6jU2jn(BQqp?4V-8%++m*i<=JX2K4EXOoMq3K3 zTPXG80l91P&cyJZSxZ&mxvfGDlkNOjA$+uA+n6)X!(u1n65UW4BQMcQBw>F8OjhGI zA>#g!3drsdeU-9DnUx8;oJJRceT6==Zsd~k9N8%`+}O=Jc4!bNbxIe?f_d31!e zQ@YFYk;TKW39=HaPkngsP8V&d1u=(E=LImiXzSaNu zu$DG>r?aB<8q1dFO)vvKrkp#l*k30o5&bs$o^r7!{d^-&V9LF#y`Ld9q;h(wn4>@> z&Y0jcV9zWt?bvSnz$aF2Bhn)#rEtnLfVXqL8ub`-3EOQDkm>yyAE%eyGN{9#B+rjg zBAC|8;0!ESO~LTK=Lw9)_D3HLGBf4#z(IZZRof(ec$tMhL>9?4h}} zsS=3%dAE`%Je~ox7n^$JzV~1Go22F(l%%J^3?NV~W$`1RYI*D$ry4Z&sC_{m&>dvU zEkeTwJ@dp6bfsXA%dnG8EVETCc2R6PVeFbhde=4&>G*Yr!KO_Vt=xF0%daEx12S53 zOjEQ_P7Q7SPljh6A6#e+0nmZ*ZC?Ttsfr2y`FgZs9eYY$2ql_cQ?q}dc>IH2D$bBa zzzZCrQjdl_mT{hUPXfTZm=;h;UeOXuGjimaum)^M>8=3%bu0pHwJk&r>M*a*>%a>Z zywh};k$gJiRyM4Xr68QT1ukmPLjSDJQ1h&gwz{o3ZB_Egtj_YwMk^iWhZG%!&PAO= zgQ}v)#+3U~5Ow~7YKYEw!;h~cL~U(tD^bjs{ZGOb5WSJ=1yF?|TjfHlK=I)jRee}I zI(AM<4O*Nh)A<0BH|HmTvRp7Dea~#r3nFZ*ER^x8242VuFN`=Z#5}+Hus}ouzrtH^ z?m|%Rdd6X`PnlfhqR9@4owmP83(x=AKqxKkHg8o7XGu$4v+8TYgIr?tn z;M-ggHT+k9BD@Bk#0yV~I8VYnPZHfa=-vGCu;{6p>8UF1srtrK_2mg0=U2-wFfjZa zts>+v|B_bS0F&!`0w1Sq#vAVKFQT_Wt2lW28SJi=E%Hc&qkB28D|eGf&r&4a3AZgb z3hrPaTrl8p;bhfnV&Nl%yRs&V=oW#SJ^A{$}seT)tBkD(G)z zFn1g(qg$Pgg8KmsuEVC55)4o!;mAZeAv&C=dw64sV#2(zy<*jRQnn6N=WIeamG?Vg zwd`W=cgECVN;T3`8_(J1vTO+Q6{1UhE*4(2E1Z)a(xka>#T?W2^Y?4+e)$*_435{?jKVpJSepvn{9j|Tr`&RbCA+P7&+QDDSBd> zpG|yXew?~qCI%AXxLIIlwGw|_*=<496N1*_x%Q2!et{t;=b!a&y6mGYYU^ts(GtG} zYj)wnwJ@lXqt`-cceX*h+k(y34$bMjW>m-p1=$8-y8$8H;mx(_Wv;CsKo$$OIYY%8 zo?;#mNfv-UX&@(3rfX2^)`x{|q~U9)*&s7gi)sY>x6AHV3lhFi{NInQHbo6zek=ES zzRB3aHtkqmJh|KI-!0iTH^=+5PGhPj1PE)D&|lkms0&is7EBm+p22V~v%RPA1Mxww`><JYUAwH zxp%(Q@{RLf-JKIlfi2>_Hup95ljn56SeC~%gep2xu$>+TxB9HwJ9T1||5s3jU9O7G zv)hU7<8|pqsVqwY()q2%v zGljhzpz|Z;DpX;;?WLFgX|=6k`<_b!%mMlARCn1>?tR+Jha2L4{geCBA^ky^13jk; z9w&^Rx{=+uKC0&1i;l0ptY#7?ZUZjMM=iO;pVI6q5VscOjR|P&a#z*+1xsm9N!lcS z)yDp`p+lQ4eEJ~CQr-P`gi-ET0?hry4!WDYJtfsHK_ewxWj>ti(che;f=GojMVxn%M&u@&FV~3jzKu8 zQ$ENYMu4bb~3ts6&@`dVUo#}k)`qBS$6Ss7rx$Yu*(PHES|A<4blArt2+YuKwln{Q0}tiqOE{S&~WP zoW~^!c2R*{E@F1_cx)nrarL5ahG$|cqA4S2km_p7Hy=vWSbmt333F(om%hqq~ZS##C|5(|F`}O^*ukUoh>c>RN z49&R6#iU};ESSzJw>kW6bkK05AabZWaVSn}-pzFw+ikX3yX~jf_?~?-y6oXlWN1_~ zEf}9^s(lSJjJC->x?gy~6D>$%|9ud>X`vu2)}TI7-#)ARD^Yg&AcO6~FQV+aK?eJU zaw3YRK^cdIk3`uegA6tc--swG24yN2>P-DO_(=WSbT{5{IW>;m(35MQ)fYhRP-E|r zv*25LedD-YBn&ekP`otSkF9~f@GTunK>Yr0E4ZwBe>Mr@t_1ub*ASNtkXOr(#CpMaW*&oeq~O{QRz0_H;>a)Z%H(e~XoT_X<<6WQDVO zg;O)Xzg@*-m9c4pv1wC%=9<|C{!!C^6oFMLv?ac4P`LEgqE~-N>2Gp0mCQWI9__X_ zP-OY19S+c4b{FEr^ktzS=E+}v`$rs=YW;bNPsML6#1Ic!jTUY6AHI$aW=G(|=Nj)gQ35?>SrcqYQFCgaCPNZxxpr77-VyDn;|74;3*)`w1_3+^2$Uf+}{@u)fAiGze{f0Dxq!`fc-qn5ym*O%e2{6 zqIR8`XdN4Ca^xcA#K+$&I$=|Ks^V_ouA zt71;v`8~KGtpUYaSyQty052mk?K{d<=XdQtRe^tpf%G(&9+eKo;AYjP6Qw*&8as-n zzw9l|?Aps~=eg|*(>2ImQ180#_yYZ@IFaG!0BUt^{@;QCin%&TcK&ixIsy9~;_ON% zRUm_HeIyIN36R0Q9*dRV7AWITugc0V2V}6Rmt)~q1IpOeC$ik9@?Ei3?P+UF)Rrf1 z@A|~m?hKc+gJg+l`b+Um<}sQMLzd3pS0KKRM5<-utI@?bSW;U|h(=X<6E^L6wB;@D z`Z&ffx%$qXGuy)n`Tf`UA)X-SBi3GE0e@ZpGN`R212$XewGGKTLQE9`pm>XWu5 zgL6I_OpQnW;IJeB%ni%E9Be$eFG&iV3|;Kc)&MtX2pW&$oy9STGEOv7dg2QI$oq3v z5$?b4ar^2rT_B$T;gp@3?^qk}{OYKsSKd37wugE=Qr4d0!3;C(JrcOQVds;V9P;}l z5*@3scF!;OI1Yir6x#Eaqy`k)7N~HDC@S)D(f$Z)scO_7D$h0^vtOTSla;Q*Ug|%D z%WuYSFL$@LRNRb@{ET(j!;_}(c|wVI$d9N|N$-|L%~_gr6`dBNH}svlQt6oNC}O{h zlyEl~lP8*>RrE?u5)h6u7faNAxo~t~yMLgb{o{nrOqkoLr~5;66{7fU)bJr}${25| zA!|U9K!(qNaA9VW@kTGKE+bdvQg0}iO9bvLIC4n6mtzp}1Tbp3cu~!NL$!7Gz=sid z(l+7v#9v#iBKw92CN$3iK_&e}O1DX~O|yo6hMEyx@#ht_Zq)nnKli~o6ju(%24y}! zyA-993`IV8hO>J_z9DDmU|b)FDBk`{s$osICe0n&)coK1>6)^EU3=SvO zqYU3%5-UIaq2@f_`Oe*}mcM`jShmpllq%`*gc^k{dZ$3sd0`)2n#U?UaGK{+_LyhZ z$-4A%;5*2*tfExs6GhOhAX6S;Ui*?svs&!xLbcRP8a?_c4l z0Ev(JQ#qU;Ek}Js-&rO%D2H@{dzHFxewUbFDNX3v2EjvXfoAu zU&2khC%wX2H!lV&D0;uC!g96xl78{9$@yfM>#&^nK}u*qv7NAG{xeN54ke91v0O7a z|9#)5TE^(9ejHbmMj79=V5v#f8@_?5Uu~efN=ofGv{sA)6~&RcFUx#Rp&=Inf}{dM zt;15UiNsVRM=E^-`P=>HCu&{v56>nBTk?JY;40k>1+IoKC zkG6fP6C1bV`QSq9pTE@I=n3a=ik?DgP0Uti57k+0M5j#td4$Hif^Ik919F{6HP4E^ zpezsGa|PFbh<6X7H1Dn50eAW|(e4MhUHkt1V3m*GbMC`mZ5KLXuQ5nN9#YfJZ-u?N zlJ&_Jiq`FQ;>S;X${-s~gEPBhX7?JxC9xNKFYz>l%oo@T#1%;xOM_ljmrkca(>wvL zA1P0JbG(fUY()aqE6w=|w(e)J(|Fhlso-6~@y*C*8xM)SDM4`F#0B@4WF_`#LQ4pC zfdDc1;_hcI(VnfM( zZz$ia!?Im0Ch@4X1G>C2s=1&4T5)^c)^)p)Bf#Z#%El0D)gwW)My-pn<01xGLXGE) zFlm>(tv5KymE2Ji`?7U|83~~?@GoA6q%nw!Dhk?IlBZB=fTAM1 zLJhKiqO&@u*gY6jU1X6womzW%S}TiZj(3VOlw57^?Z*WnHak_EkdOEL1a=sM)T%?yFfSC;3r@ zP4&5~E!&NxS%nB++EP*d97*iW^`|uW_9rbhu#Q~zki6a}t;?eNywV~0fS94ALvjV% zc^$Rrp(LYEVD&j2wW^^8cU+z&`u5Jwl}wB#&TLQo#nxZU9&Htx4&0hGb{CX7YuXot z=jNUQ7hO9&Lx4lq$61aOg*BD*9ajNaqMW~f^y@8GE4?6@SINy8DQo`z@A#_Nx=(lS zLbG`szdZ2?jJP`{Ew{?m0FsgYN-A;LJ2d@D)2ISpPgV%|+L(PdOBq2*CruS+o27M= zN+uKnq3({ajav^!T-5KRTIKvV7@Bgk=NJUUB8BI$1vFdb9%|c|D*);$Jk5eBe zR5pdi`Ma$UD+^>fLwQxdng2Dn4g~dmg2#DQH47#Ai^w|KsgGK#9kZsV$BK?LpXpn8 zH@Kxus*fZe3qeQj=3LY#mRqdbHR`Ot9&Dd=rmq|R`ywVqK2;DeYCOq3@T}PHpe7Eb zWjS+TKh#IwyXL7h!c2(8*7wjR6v ztZl3?Nfo$lLA?slW!>at+jK5#&DT^jKd1GlRI4cqUNoPVthIa-2Zq@+l~m3rdHhNH z)TDR$9FEjd2#C>2&eBt|wdSi(s*>Z>JGr-RQhVmlB&OuXr7Gya{`}f?j;bOAr@5eFf+G0rD|EfT5Xs@mq&~-XvQC8H8s5 z@q~T`K4|vn3op~|l>OaT!(6G+nk4z`x@|b3QYCf8kMx;uV9c=OF6_hILIiAU`Wmpf z2fpPy@3?rW|)4)N>yCf5EJia;L(SaZnz@Y59?j1P7o#u7voT?f0Xmkko*G zXRr~5{6%?1R1(DNsaW7>rb`_8uH8N`U6M7%DX(s5mkJs*J#Xk2e6y(;Gw4RfKvo8}G?{~p}Ec6RhrIrxzQ zfAQZR$zzch!|x9~Xm2O~9lL8Wb_KMoPu<U4QOlc?K4#vKY;EKsP`;Z*OXsM$$5CruFJ zOmQ^TokkBvzQt)@l^Ufhdkv;|_Pm&c*QbhOXvF$i&bDqR({^b@AtW`!-Fp^;22m{* zFhhnbphN%cApjZDjjRbzjN?ckzrE%^^?%jUF&X`evPK^9`a|663^W0tX;J%nqq!M> z^I@`)=_wwu9S#tbzyN6W^GF2tjO*?jyAn$T60~+wJ|&ERYRCL0pnM_c%dTKdQ+i-B z-uK&bsULZ;A9l~9gFb=p1AAXUIICs?FpShCDo(ih6!N{P3OD+Y$Mfv@bi)uH zVQOmp#iI{axHovgJv4pYSWgWX0w&1D6VCey=oZ)`1p~_*%ctKfp@!+JKTVZYOFS1Hx4oRrfbq{ zO7O)H^$8{7?dHN+Uj}T$DGqIoq$^HN%Uc|J#JEO6iDp|4qtvV&D6dtuP|*~FX$lg; z@e{Z`GvuhPwZTh4!rZ1XmI)P~#glI-kHDfU>jy>R}% zpWR&(l$I(HU>jIO=2f7TD&^4;RyXP-K4!2gufFw+29iH z&N*eM`*1gr1F#KtyMK8xsOnY-l&9=!5>=XGGS<&;PqS1vLhK0f{}^brPmDPwM&@70 zd(j~||5y2dXJBoa{~1_=6Gjphj5c6J0T-fP6~~s8vsudVQ~7qFqJK!zt8z1isCKNm zFMIZUWEX--P~{g zo(XF}nUx|SpH(y8(2yzI|rH;~EGbYQWR*SW+;g@TopjmCM-hG_L za_T_%I<4a0KI!J`iU>61m?|~DpMDG3+^jg3JoY-s!_^l)OpxPZ=)P31hN~jg&0z?M ziNGkgd1@GHD3b?eJmkdp*|v1;mAJfxX09jrM(G^a!D4eu7c+1sv3=&O;zZHFALV)G zeuIKa>LYWf@#%-q5P^StW{y2NvH92i2G?Sric=St`old@JLqz=qZRNkTnzU8=Pk^V zM|E&dCrL_o?jyFpY9p|Pha96ULzO+SU$C9R#Cr2l zD7Jt7un%VTT>~}BVH)Z-Zf;B-SNG`q86gASnYi1U4nIl^#1RZnuH}+l!PK(17W&}1 z6_-<##zLijqRxutS7+RQ&-OS$-NlS|QLt4XyNjOWN1U-jYz*?hQ)k0^9F;G{*CW!7 zOf)(DCDQBJu*+fZA?o~$=c}48GrAW^e-XgZ$Qro6N1G-13#2ojAyTud;oMRWkHy}T#q!r_S_+Rc8wLxH`kE~hEp^dtHd zq!DE1Tn4t#l2o$%FjT}+CtF#t{yBzGb(vL^8EY@l!gj(PSHzRFa{fLP!=rNf(PUn^ zgufZzpDJ4$%TC?%B)L2Q@^VzF;voF1 zKjG3otG<08c5~AX!d0K;a>V7I##84aP4x2jtfl==&D@TTW*qirOLJi}|76g7i6*&; z56>y*xb4k^C9i?y!i>C~pZuTX<;O!$-|OQWWH-yV@i&i{&TGfKdx28ZrN4n{=lAb^ zb9FH~>yITV%FC7d$7c?^mglM^@9I!dd-2Oh*Gz3Q$XkdQ3HVRMA+-Qlj0kLa4cLWN zT@)3C3kYIbWtjX3js85yZ5P6it2L#)K${{J{7Tka_tF35X+9LrcHT{1YwkfyvyRea z-j1rf?iJWOK30#;)2+KzC)_u;4_{hU8g>{Pmoj=$$BJM+qOz!#TB30Mkcev$)RJ#1 zfOD=i3?DkuK4=*)Xsl3bDx5e7<1aI|OTI&4Q17%6ZFM}box}a&H;aG4ma*edE{=yu z%UyF24;Iy^i^31l&_TCe#Ojm&ly~^1)}1~fm-CS!*Sf;a%4J(`&7OI2Eq8_A&6Pb``G+^yX=527zvRJd$t(rj2`zgzMw6ixOd9g72Hy=2# zqv_81`bYB`NYS8*IEXCJ=Ljp?pvi9T4C_*zML!PrC;6-!O$Y8c)YywL-DWNptV~`7SUu8l+~&>`VI3XL z9c4idxA-55!{1fdeZdHg3km7c>E?YSWL#S%XP-0c@{>o{eI{Yh@tUwGEqxI1BSP6w zVm?PBeAup!_!Iqm8d@{G_}*{|PcuuA2lWVZ2$l^W_JaJ|9B*A5%%blAbsFI+j{{z7 zI^i}4rEt6ye_w7^mLy#8(&m9IMTyMvJeAvoT@nzNkE4|%q~5iRunWr+Z-LJ4>Z{uo)kcXI((g4E47}LrWwzUwI$Wo z!(0uGWNQ8xQ#@}b)x?*|5+_-HBbcS9ufH466cMdMC>xFD^2ubJt8$bjW>aHZg6gLM zpx)rB-2m{@KwgRC>&NsD33hBrb_S_-Y^1=7?_ha0>*q?h;E8+DMeY&A#F1Ou!otn= zeV*veK;1WW9ECq7Dx}!&U?Mdz5#oWmSKJTZNL!*`xpWA7RE+0Vj#K>{S4|$j${O## z^PrYx8!5xwAsCTU4Yw8z|IiwM>EgGj2r4ZacE@T<~ zQ0n*GYdFVdq;o8gi(x8S!6#ZlmiLZ;b`P78hh>SB6^a zW82DO4~F;;eZLHPr6d66V8L2f&2c7*9lvG6Zv<(9(G@hWdjj1f2wcXU<{1+7Np#8bzK$gwznkpjYw!Nemy&}Mz-BGBc$J@sbNsnPEeP)_iE@J1YtuzaSuwr&=!8ymvdxK~v-un?kv#VczzbQYZ zX}hs9t+PpKf^c1cNqJu{COYHBhwP#WO-ZYdIih*tUWMLso(kBr>0$$ymMgj$KE0Op z(lp+e@0(%A2~f6G5ULz^DZ1^&=O#*p7=`+Q@;k?}+tW_uY1Gv!v^rtb>ic~sxq9>k z?wFKZm_POkh;-iPIDXD7uz(n$Uga{NLn<3{=GRoXnh(AJX=k4H z)U-w;p&{q@u|6O2IVzyV3RT+6zOVXLy;}~bT*b22_3bPCf@jUSyLJ_j2ID2Drbr-Ss?|?TGtp>e|cTQOFs3>F?O<273^Oz%o zRM!e)KlnkPy7;#5@^1VKMl}wVG28Nqhh27i^<-bA_*KJGia3QS*Asg#kH0c5>ISofREjTQ^xk{hkQ@8DzjQai|# zH%GTX1OcfTXYK-XDGoQMiqxyOH~LQ*NjCCNb;1j4*wKy3#BrS2Ohs41=5`duc+)1| z9H1ZPDHqEeCcPJBuXf6BjehOzS&e-8h~SLEjQ1_w*8ouE_&9GCQ*>yi%+6`MTxH>$ zv-0#-;w0Qy{0#YAI$!}#nug+!ZFVm@>{=jK6)54?U0Rh=9Yocpsnrew1>21+qp`Tt z*cieCBB@Q!{X>d)%``+CUpKa~6shdhNqzn2TyK#D>#oMNM@7b1=rvZ$6{Xn`-)hya zqmmK&@7yQ~jlK7g|JXzR^3!XTvjgTM$k9=MnJ&6?hvW%$`!pl)96A%Nuul`+Xu2g=VM!iFLCO5qOO*F z0c2m(nEe^-e!Y#Vv*v@Ts51_7T$8LRjmaG4STG$+AmyJ-DxU6J(W74=2o0?nTEg5>VG>X~{Uxx*E^^oG_{CiLH*t`a6VRXB#Z%aKKbQKB} zEi;6Jkm2)vZeJg?4y_4j*v-?*-Z1RTM=)!71dCH+tz|1D+9Xb)^*S`${INIwJr{VF z`Uv!Sf;7tjc|uok*!A=ilIDLRpn?Qb9)F29NC}YxneTC<^o@TJ_I+hOQ|57 z+ill>aYo&`ZvER8_|41X+LgBM`O>rYNw_xJB#D3LH>$o=^Q1+7q54#Q$zQT^It1Us zj)3lQ!U+WgxmVV(ZtlW9L@-+Kr3wEed{BWEw?U|ICaZN8P%DAsW(Mi|1mr}O=!gpw3&w* zp6wU{L^+Am@Mjt0_AiM=wSOvlhoBdshFyE-U^O@PxZ@onaE}+wz<6v{ZKJz7xgzWE zzy7RVvCR$8&kng+%k8Gh2s1FgZZ5renHuFO@+cWr`$GYN7v%D(IgBYU)a!3xtlcBu z+C2oiVcgOPbH*!L>8Y90uWRZv1HY}Fl()yL6N@vf-mwA6e|Xj0;9&tRyYzD2Jf1HW zG?X1a5EfB}T??&h-O@5WWoZi;UVAAE)Vj9c$IXi2E4SqOWA@%+vgFiUSu2;#3FbCz zyG=c7EL(AIQN|qQI6mqq3)BGGFP=|!R~A@%SC;)+DEE>{S%Ap3{opz1uiTOK<`@7g8r9F-zgF|9bHhh>+Tm&R{i#pgF- zB5$efz^UHm&(DX|3xR(LbSuw4rRbRDfL4p4O?Y5RAZyfxV23txBI$CPY( z$j#Q^AAZ;sqjHLLlM=0Af_U~WA40pf8~{RjQy<$22t|L*evQpJt;j82a}nk)i*6o0 z5WWpVjL%`Xbi_q0i#1)%i8wOudE}k|MDidhgA0|Oyb>|n6QPu66}eSwE~4C^Y^U69 zX45zlv5fz$U~`k&XM%ap+sk`i+YE6KZ%hz{fNN)&$D|MFVt~@AQ!`Frb>LzTf6Gh# zEy&jv`p1(}W&EOa8R~`1`8y0@!M|?$I95@$Bzie;3HDsDi=j$(xavH{X&zpWquFw5 zTtS)c9#kK5U;4wHHK`P2S@ZmyC`xD?cYFrV8pM#M-K#$N6te3%1mFK~>O;W+PSCc6 z-mIFur}pitRzw=#kpHQV5F;&uD%#!X1^PsHvyN)?}?wVEM zy&z1$hDiph>G)5oy*#wN?!F#z96%)|;1I}F7R6n5$^~QNf;jh#^neUj{^ofV1jY`w z`pUGStn;1n@1P?^R{X^THkO@9B3)o}r-F-{$}t_*%dJPBHcx*BG}8?kT7`F5{p^@* zb`fyuH$-x+OboVWpE<+WoFUGT=cKtazdH6!TGa=hlY0M8Qnde0%K4mBfOz|~V%4(& zm`m!p?Xc~*^sD0@=qy0A?br@{wq;m#>u9B0%oXYPBeY13f5~ONlFpuUz;NGfZ?eA6 zyf)ZvW6ZyPgb;^Wv~+5t@S8XxX^(%RAB&ac1f5a%-sho(<_Pn78AX}8#c|SwKzY&r z8_NWABG!ei9+>xJs0#Iu#x8+3Wf9P_@j487??b6z?o3lZ-;|BFiD^pr=UvlZXWIwl zecLI1-Ida8>2m3&npC3~w?68t^{5_)WQIq#Y5v8K`}Gs61iK`d<|zh$(kL&HM&mr` z5l!OF_O7&9kAhRsEsB3{KyBWWR@dU5kSt!FP4bUD8)~;{$)jrDpvh`8HUqG+SdtHj%2(;@jJNB%N4Hbs3`~& z`)D_KAMk%Z;k{3b!!3XKJL3NkrFyiw$zJ|d6wuh-_k^+9;MW}|kHg3RZH_w*QLozJ zi?Ug+njhT3&J}b1!t7fbt~bj=w9y~jDrb)svODJz1;bhaR9-)0iLZ22(a&xJtnb=i zY)sMgE$Sj&e{(j>q=WgFdIf!LI_U_CSH(rtjbGm8u+*-W2w>+H-u4Y%=#o(7=tdmj zQt4Z1SYe!4bSRy?%s)C@pmhOlz@v(N9`V8W#kf};Y1ss-mC=m9zGcL~$9y>ceFd)4 zw9gmgEHq&--@0Qoh;!9U9%I0?gFYm{%h#jsp2hW+0xE^Bx5@5!wJO$_YB29NkAKTF z4c57X`7^rlmd?KE^LgEOU=?P4VsOC9?3TJ;mo^irL@{q}RH*-I;_2c1GYxdY526L? zW(SnCix%jJSX!KTblm(y_;#1}6iekW0plg&(`M9YS+iT3MAT%$lLlQkGV{yq@Z%Ug z0?Q*!!kGK_mKJ|?e%g1NmCk6h&Q+C}gsQk0=~UhfntInXN+gg3tq{Mk9SjeOb#ang zn*qyqMIYCuKAczvrWg42*hmY3zV4FsKnOpb@Op4cisci(5)HS%<3G@)Q)sAh>d`n! zI7N`-HBsb&W<}o9v$;q}_t58lCsPip8y7{XGVlW#m*o4k^C#&8OwTp9i+`;MP!U*;h8qL^wEzZGRehV_TPD~JL5 zAPm4Gb4*OzF0DR6(*R#g?VFkIf@Q7#BjtbR&?A3rS{yybr^b81;jxaq19ufEZB2l>MgF8E8Dm81;gJgh=H z?_IEpb;lM@kV->6Ks4}zIrV`exg4nA>o!Y8l#5 z1g&~)-+e&{V|RPP+0|R>K1OzPf62;02%lyyO0{boK<@C?MEL~uhEIAtkWg4$YifS> z935kGl%{s=N|RENInTPwF!y@@lJ-A9r}N-Np<1V03WF*R|E{j_{%0ih1*)*7>6a5? z>kS=oKJO~;IihX;qE@Q7YIA~HM_F+CqI<2d#Qf(z<{KhLUNz2TbL{%pk9G^ko#<4J zS7&utLqF*Fdx)&$!x~$DA+rAOP;!#g!fS9%NVUrM1xgp_(lB{wu4^?i zB9D`tt5cqqbW~wdifYtVubLdAyKz$d$zb~8F#QXLp85R{_zMzmn3VU(1KFalky<;2 zg??vA!y}5%9UN0aYfok$>Bn#dJnOO!iH@s7nXTy-|n}LJ5-vn zZwdSsAw3m}D?fz}1H6u1aZG_f%Hp=`$w46Wn;vX@Aj$(H9j>!+dbbNqtwgf5H&5U* z{~V>q7T=&VO1;1js8-+aPh0$6G6cW&r+Sh;?i3Dzx^LiO;c{>uAi#bai|)LiPu?uDb}25sxlYT~5BP zvyFW>@)GORg!O%u)i3`vq^jJc(GXRJWAJ?D(|{VmIH*r3Rmy{!bDnwLMlt~Z{y|XM zjZ(NbVqb7P9v6Iu)^yVr8z}XLUd~sq1Vb3CF4X15H|i}4D(#GnLr(<(Z-Zk)OXB|q ztwM+0>{ghiMb2Cn#i9f(T&%dBa@Oz7Rt7(c_N+&n!N186H_sV0BoXNR8Xd_`H2Pq| zWomZ3ji$*R-Ex~zjhzh-AeQ~TZYHdDC00flKBu&R+6=knqZ%lXaxZvMOi;xpPPxx_ zzv^5%;f8y4$F2@XV0D(#5EgWVThE z3oH_^ERtD zCv}4auXf3_)NBUMbV2P>Q9U+E+Y+G9;usB$Vt&*M#lD%^3#yR;-AU0t>W?*9o8hMU zM<14_{tQMU!f(W0=idH#=gE1Z>*e-J7Q5Y4-X}70-miz-+|0TR)nhUe@d1MMEM-;q z)nR{p8&+9+OR|UFXi+JDBUf+O-eY!m>)E|-TG#@1s#@S1G`zE&gyyyPQ_V{-oj-}s zr*9v4n6NQ4oGm=#X%c=EAETU2!<-M5y8dOY9MP*n9T02h4 z>>!&iUF~Kd%47c(lE@wzMlXcB+5ed_&EbeaG67Q(DAe{jjmdPDYS0H&5=DrFvEIta z4CIWvTIUWW7fNjoc316>T2_^5p8m&*?8a7@i(TN^B<16Hg%Qd43|hI_*=KwU>a+(? z>TgEzEV#4jHSd@-UW+wv#%zm#Bq651ecjL7qMvl7w9lGCvPY&RV9qfAlh-!ddC68NnY(hz% z4nuMDk%3xnZa4P@V@DL7PQeruo0I-xdP7TSYw z2xAeuiLB{E1f>lFubvV6ll_T5fI;9^fJo(N>><5t31!VU&~tvyHnhP`%XY+foB-k> zJrYM>tv&ROY=D8f6|!&?Q);clI4UACwAVWb37K@;k(7QN5aK@LZ52<54^jtw{zlbB zu}H-^6orL83m1{L*Q4f7_4=NVKFn}-dDa(aH>9p=%t8?_D!@1T#Qbi)tKG6a_WDlqqLAWY$`&`6xV7P&pQjl!TuQFVT`z|v%y4B+IzBekIQbv0i6gI)P|H7^o z`jUjQ#2Piy40O`+(}C4EZ6z_~bvSKxG36yOwkBk%CS>zTJn&Ep4eYV~^b~G3wqj$Q zp}N)>VMQ+1ray54mu}w_ur7929`NF(DoPd1U#B~N9UJ4KUi{M&L^EH)_kwdLie`)dd3i&L{cpK@c5{HlLECTa}LCD>!!`^gDSjN15%qa&ss zH1i4xBU`~qU0-Z=-)+^2qjhr74s`Es>mrsv3*(H=|s3e{*BK<}T;28+?p& zw~fcG9$!*kpE9?;K*+fU{<1o0RK$wUIGwqjg0moSrSZ=!9%Aacx)%Qs~`0(}<0e;kYYlx>JWVG~p5_tw?Rw5x#|P0ygSA%U&5iM_ zqI93)obUH5>@2n7EQ&ynlfRvxSwZL+snF{W-HPxgq;L*&HtBNgUXZy5DZEhb zS6Awn02!ngQF71@>nXatx?^j{J5&$!zkkfS9IKtZ+`ZWyvm52?Q67s2r_=oT&sFR_ z&s@{P|2d2}8au1~?_gkSH*z!U63`rWpPu>HPCeObf4bPYM%2~v&FT_qSi+e(l>)`z zcX@p2O_9dQd(}rsvAdoRiQM8R+7Pl)Z>upEG`3IfEK*YS&MqQys7!0FXfIMiBb8f9 z+2A}mQ%C|sq_Hq8Zik!R!tCyS-(?S704f@Jf_Zv`lPyk-dXPrm7e;N!HS3GDa^%|K zR@eNcFCrQyzHcR4l5|@~zobQR6e*^FNWDR6x(@>iic!$*3-U{^n(%B}aAhv%S*UtS zj|5y*^r%{rT=8=S=H4=%VIPtSF3?$!&dLvw1R#3nVKwvD-`O1H*?9wlq^lZg%lz$*ndeCrNUZ48E4^gkN!1?HSd%V&w9SNP56>C1 zs|TWH&eUHlwVST57l>8u${)QHi(yd|@rLodR27zOPSXyx z1q#)_b%$`)Nn^W+n#D+ClDiH(jG`N{t9biUftQ%OYg!xd>@3vV1C|&CiGcp{>o>u^_9H(cTpM|!d3m&8ntlO>8?;a z8h0J`_7-RVBD`<~*vks@hZns?zR}C*)JqKYLPU1QrGWi>3KJ#kYyfPVUpIjrm~NJf zBOUT5l65$WwbUY>TrKp88edV)1*hsAT_aBt`8O^o9L1#dA7`D3Dix3Nz)y>zZJqiA z!}_~MV&e{~fv}x(*gu%|cv#&(<<5mu;d$Ta!!F4qQ(ZIq=I?`+Qw{4F`vY#KBR|dx zf6IOOZL-H5D*MhpWU%|iR3%*slhf2T@#TG;)$lZ^4l{o;GE{n&^dC#yVk3BX&%wM0 z|6_BF6Vr3I7*Z_SKej*=hUfh{pL5JwHEkO3+{~S1apT=^%sJNZA0^#Ys4INr-Z zOr7#un#kVKaeSqI;`*I5(z$EYoTD{t+#AbAf2Jl5Lfc*ks0FfB zpSeEze({%C2op_1H~aj8s_4TVbjvBeh9+9duaiSr&o5x}tuPPwEa@<)$@^tLxOhn# zG#%QlXsRyEs0K21H-iCZd^cyh3a*XLBYZ>peLXLJcihbw`WmW0L99P|mt3rWzY){{a2ul-UjE(s{ma1nqY0Z0l$+~`?y|hRegSF!ZMm6xpP0D# zd*K@My8Ez1JNY#KC>BH+-`~K>LNIq0r9d33O4#f7gBYV5dk`sm5#FDt9X`7tBsVA;DaxI2}iKAv~F+9ue^DKJZZ7j z3^pQyMJM45L9!ahjRCc4c^r&e3 z(ne3>osXvn;MHOl*)GLr5Lg)>b7?~zK>Q@j?VAZ=(?7eau;&OhvgZ3Q#@;e0uIGya zOhST75`tTB*93>bArRc%eHh$bg2NEp87xR}cL?t8?(Pf>GRX4#@9u}K+O68E`{}%X z-BtZwzgPG6>2vny509pWd5(Ml6KQ1MhxCFJegM&@ycKZ&C`@y%ytInW^r0j6usy@2 zTiQCM0{$%Pm-cu*dzR`@3^T(zUO34F1)}W50G=TU;Tg{&8!&I-gO1v@A$o*347|dYLxo$`CUY5zB7y3i%DvxNe4;vS(+0&QXqn--03vap8qj?H|UI`Mao0nJOvaw+EiyLlrblS)|Q8b zBuDC$jWI#Hbk=FyfjM`5Y}jOgRC+EuVyrEI6fMEE&WAi{M*h4|M|pjpz0vgJf{5@w z&VRb_h0yo2mr2iObBFKq^?42SEF8QY>B`-Zp0i3{H{D2+_q;EknD+Rsb~+lQAhz$8 z1X$-xaM3thdyHG>L&&4!Y8Zc zz?2GECh+xwM4tjeH%(HJH0|S)kWr-5*Z5$5S1S;)SbvpCBn<}xN#S-o2a!chbzga; z+-iFmPDrP?5Pv>OBS`%tt<#g9#A*iSVb^i^bIsDI9gM8&}s7AT5>aE8dQ2&})7 zKbJia?Z7hb#lPe^c6b(7@NM#6m&=zmN7OFE1;6O~G?jF|k$ZNz?H6%lkuQ{A zJu|PU-?)|P(mO9gk>ZN6c>5(2v(x`U2ohz^k%cO5+mRl5$$ev`hU}F*+N=3BM9W$s zeF=%Vs%44R+$|aYzX^?e;Q7NyB z<`m58)!rN1fL9>SJ!_+n@c5IbE(NTWlSvK5pE%QRTeYf``Z+T+EJ$kNx>@V>prW}M z!e0{lv|S~^Wj&WbYrTHlx?A>`ZPFa<G)q zvfuB{e!cU+1Q?M62yETzeOf^LI$rRl$H9wQ9u{LSZg1O7)gjqBT<9hZ6iq* zd5Qy_BDta(vf3MpknvDKvfrg$=Ffn>%*NCc6C?MTbS${$dqvh8PN z?tPlo$a>63{GvM&TTj)?v6Ocf-E#kT3Hx2*$rC_*JI-91cZJIMXYf`F%{Y>OvH!7( zqBUgyR%!Ia$(L+)&fcIvO6aQ5+&t*57}5Js>mHvT8?rP$jDI1-NTfXSzI^=wW?%$< z@G=cpCu^Vl*aPeR(GYLeqP|SZh)@BX`98xP(2v|}nYzxMd`<<0@7+4uj`ML(pGW*T z=^Mc^*-P!fD;DF^SI>(=i*Eu%?*G%mXC!-KJQ(X6I`nxZ?OHRJcTAkuMd1a+miE`u zkPq%P*7!6o@67-43U$li9``um9^>Xxnzs*lN7Tpl$0jFq&sy6Ee;CuTb+K%V@wdnww^Xp<`J#V6LMFyTOMFlQqnkl2E% zd(ocq1$=`rjF5P_RDbU#gbHDf!W)RVH~N{0JBmT(;sm8(!ot+4;0e6-GZej;%FvDW z9q%i*83T__nvI)59j%@-$_SFxr##9*WbrHy#u6F%*Ry|gf0;Rb9U`+lTwCe_gm}yU z=^sJack(smrSdGdFa9<9$4wdDgrgb7_!IO@&U40o{5jYoa`OtGvqMtp8a)7uJxJmn z`_-9w#rptji@HfN_*>jxTS1O2;xQ*FKgdeOwI=P`^?_3#}7gRAY*+~dqi@Pr%k+N$Ih1qRd`hAds z8^q>4{ny&d){VF=E$_*$bMgumoYX-fH4Nm@UURs{dIi>pCnr(C;C2crDIgEu(*MB8 zhK++GRB*Yk1h~9>^WX@a=Z6d~e{LgQHRzmtdL8Y5-NM8E*DZWKFfWvm$MX({*RwGs zufg>E5}Y@0e{C-)rNDlI*P}WPBV)}l=-jrw;)PEUqYGH1IC6)AuJ~~)GA9=$flKAw z%Q_m)YXfs-7Tm2Qw*W`xkAJ71|F&g0H3keHFIr_$r=Clt3JnK`<*iqYd&=MY?le`S zd52uvB!d={lkLvIDr8N4x0dp+d-8-nIPxFNGEiMJntL;vHfUuUg)`8t|?QG`7%Z!my!>cBI!`QeU<*f@ z@eYkIKRJ4{>CP8JGEnw-oOEF8CpZo|7Un}h+jHpRN36UfooFvpo7MRpmrBqeWkWYv^APpO3=-xWK_(CfOEbg4xoj^i^I6s!bT}$ih)LZlPFTd(hjNKeWV4} zW_l1Cub<^qPvH6OQkkg_Pk%6zU%tBi8KQ3OtXBIVQ^7vSwO-1f=>M5UrK=o}l*A1I zP@Y&kj@X~DsGTlCzUMB~>4py;emR{#5Q=^Vo|4If>u{HZY>72U$GTBW--KFk3^OQV zJ$2oXz9#V{rpmSZ({JxaPBYYKd+#yhc?##mGE`u?v%AgOjkJkLhnOgRg32fRhUhC< ztgXz@?qJWn59ANKUmkJ%xpl$69y12c^O_Z4G4x-j&acm7kV$D0BFzA@l3*7?mcEexE2-?TiJ{Cc zJK?dg2wXm|qaD67@dD`_?-nKwjCZmGQ2qM@^aHpa)-_Nc2l{~3QVegdzqAGjb&wa5 zdgT56jB_ZJ8}}5WI~Q#-MvF))oyA{Gz05J`yIboTMpNhG{C83z+PD6|0w~I^!wbmj z4Q5OIYdBDO49_+d`mTAEYDa^#ROaVb_r**cF23vyh3fkH91o>Ce#$imAo^+ zUwZLbm8sEJ!9%Cjt&Y7EEiCu8!eGFcM(2uV)@SI0YP)i*EHF_;yw^j9osYKrv5BaZ zgvmAXQhRMJ$zff%bKc$AJQgj=s+&%Z#97E-)({IdzLMAK#($z~)PBG|siBDpQ3{^T z{`d<(692t2vF>mN!A`Yt+&RwPmLE2BC;O@_$VCqvj`$|N_aMaIk7#miNVrz18JT}3 zZuti^VM+851$4CdE`ALW6HX&~0%2{Z=e6%WrCy3J| zKolk~pG~v!xCLr#%F5oQmc5IqQuA(095jqzHg8xnw}8~W=F!2{UKe=4Z(j-AM6KiH z1rv+x1i~FD>Qpu;IaT}3_$n^B8h8ph0A{*>Nyw_#!H0K;lNRPA*+i$lj$SVNUJWh-fzXTk}*ANvI!S$M_Ti1 zuV$D`)xV4JhnIw+-&+C8fhG|V98660nS+$QQlw~af6tQFRQY2PeDUM;dqX!sR_Pxp zN-ESXF9k5+vQ_@l(N#Ikpu-J>)#h5r%>QWY_?+;-cr{`m?XjEiDA0dDl9crq?te(Y z#{yHUozckgoaK{@?-uXC?5L{vjPt-Ca#WIV9~z-AArvy-@O9 z3oRtw;rYXLXj0rhr;TCE=_c zF*^Gro4jObnRN6O$A?d33KuYCDj&wSYe;!AqrEcxtEG0+`mTj99#ao0R4WDj=Uvo8 zRT-}kj3~Nog`sm@TfK2}h?fi}10M9;d*F8n+omE)bEu^gWs&<)YNY;^^I`pgE2}YFkM+vwL!A93;PLqSyF0?y z**qVG(Ua7n#?(5OL{jD`qT&bdX@_WCK3v*f6NeOVFB(K^K>@OV-9T;fH9|yamm<#L z({7F|M14Cy9=P zDXrgb8KF1y#H<0-&}^lI;zT_z*s)x0QYsYa9U-t&?rUk`90gJJd#c~Y`Z~UdjZP-Z zpF0qC`cT6CGNN5nbd>ql%uL*l&}tmcx#K@UtLV;t?uiVb3w^j;)zz^!9qJOtF7k&VzCBLR824q!Ml$Pk(q<{$ee{Qh0iZVcZv}W@n#HZXNwPQOK<3 z11ajv#p-mGW|0D-QLP_SG~8 zR$OHYP<`{X*;+ONv-fl6+8#ae71d$n!D?l5)90UkYUFItFRy|n9{SL9jI1d&ke{%^mW3h z9jEv2Y3T!{(m0%LxwC20W}ec&YI_s!)e?`5d}XU8vF>?Lwg)IbZWj-3KfIp&*ob>v zY@};YzuM49xZ87bIn|iW`78NkSfosJGG0bqUUaZJi;G!)yT_J4WP_>n3}8a&^2m>7=V5^?57szDbd)222RgEFWn6T&ZRpb_sk>) zB&npNZ&8vSY%_%vU9q+^oB>4x6$Tkyx#aL)q$un|zge+T4Z zNgw4+juu&1AxUo-HmX7mVcDmCzoDa41igvU+1pN! zYj?2s9-E8TMKO!kS+im!`kw-kt})OkCjn zvJ%+*=dg9$ISXu~$i<8=&TlcNl{|TBK9s5Y)#GlnNQX;ZVjOet)x3J~_uVIQ3$ZEu zEBE$N-Oss07>q5z97T9PsSmcKSE3)8S;r({P7P|To@h0(U@b3SWML;$2y*yWJYa7^ zyoAmtp^9`>^Yks_lr3Ym4ycDD12orn|FTeG9=C5Mzi552P8x;g%Ik+=g<2d^sNS^t zzMJ`dzjbiq-n?j83o5Xr5;>xhM>o88(=E8yFK-r5MM^7SLt? zT@A4uB8->~7iv-VFmrI}aFRnd(#KnR>cL+@eoFclWb56%v-HQZ=S{W8nrP{c$)Pko z=|UZ+dl)_`>SdO$&S*e42j)ossU>yFSt0Sj3GsG|D^CoGv_l4v2_q%C>Co!-wB-Ic zJFDREUB)3 z(o-nTZ*FGa92!d;X)c)Y){nS{h_Fk>k?3rH@ylqS1HY0$dTA{xMTx<^r7Nf+FXbmB zqc4bLzS}9(PAP&-A4!hdbSUaVnYi#O8~0-_gD~dHe;2F<@vc(>{SxaT_fcfX4XkC? zDnEsQhx*=fZu|fely$pW~6bQJ(WkH**y&>@?$WGdF#d$TVt-0_K8TiGUZJHLX% z3jy1!`+4|*c^e`_-KuqxSLsmm4}$|m-M-u3Ni6@}g2v(_&rNS&HDZ4> z#0I+&^G>D(PgzUaG>Yx8|2Q2V6@n_k_Iaq9rFR%4-Q@#|J6E1Mw5RO5@2JCSc$Bww z9TMD=fRuO|%aS-iDwo!U=_ca7gI{e1Q?JSsOSGPFw_7z?A6wJoj;Zx_^JU>FuEuCk zko58ZSAFzFy+n5zkSMCKJ0J7}ve6N;(s3bLRyPB6D~T`Y2hlf^i?%u2MW&xIS~rwc zVKbr*vyPm`m}D{j2uE|;F+I2L2?ufYgD&f+FcwIOY0}pfobehAFiza_#jb$}C_(EK zfaHHkQd-2OLjJR2iT74z__I>3t3f6wR#o-#=b;_mvTkGv@}!0u5C<^5 zBNGJGS`Iw5(fPN8SYHG3ufwplSpEuJPP(EJaSRJxUf}v(8tTIY6>!=y*JfS*x$i5| zdIoYf=H2E3{`?INklS5R`e8kc2Xm_DPx?M3$SU8@X;KA}K{(`GhxRWW9d$GyRoIut z*v#DFpmty^wEFcd^=vOASa;8Mo05uj#_@NN=xCq=xQw01Q*R2&cFbxn|IQP5s0hkG ze)fPr##sxLnS2=%oxxv6pQsf%`osG`Xsdkduxw2WLbXyCG`W-s|mx`nGfIV3Z zZfYZwdrgSp3^>opi(fZr0tpcIz$*9xgG@0wWnMWOS8PS1QoB&D&+02+j%tjb{al~_ z#QZMOn*Ko)E%&gDPJ3h3;|yZ-`Aju0=Ev_cs^HALz^8}Cp@*pV-lHR8TK#;TJV~C0`btmfL1lAl8`)7A(K{%R+7IoFjQ29U6ctHW8>-V^rvY{KXvAo!_p_8>a81CjtuemZXZiC;jxrg7B&xu`pJ|>wJyZe01 zTvK(7R?6Lwy0JUUZ|JnaTDg`@s{Y#4NH9v@xUH$pTjU1pvI;I<&tn`+;Wc!H65Na@ z-eNrAJgBp}y6AA@04!pA+yX}T)9@b4ny%UtJMe2{BeUc`959Tm2M=a^avy1RTw9M; zGAnPj+pSQ!oNVZ;-#R+XAQ9Pca2jyh#%OzWuzE?heKk0b!z(9pW{NBI=o;M*>5y72 zqA?MnyEbUF{fFH7QNy6sc3?!mJGq=_kdQjTpw{+%s_h-C9`~E+=>DEcA4v1t#f7`x zW6A0QWbT;M7gCoz011bzpa=Mczw=AOX4i$;F?aem>y6Rv)eZ##i6TOP$?7iu1W0S^ zl5rAk9>uoh!+r3v_&?_^zfHck3lCF~b0{eXJtoE@9a5PaToX_-S*A3HR>7M8Z4Cn2Iiehp5eEvMd+=%y}{%i3(*1wE2Qm1e{ zM2xBC)$^59ekX13a?7jr|0IK4<)w(m`1Rvo2^c1IR|{3z;^tg!;Mb2c ze@NfI#_E;3wSh1ufsXbU%z1xVu9`+pI5Iub+S2&dWJFQfRC(vyba*b67S~nJhIv~ft~||dzThm`(Ds2EcyIOW3UPq43%khjO}$F<&aXjKU(=nl{F1`X zY(`I`O3Ke?csq%9HQH$nS4%$fqPlxdPGJ=VwCzq8R;#=j` zp8+y4QW$($s1;7omdj9K=x--2{dHX`G4j z4>$@0+dVA>apr&1hXYcvXt}@bz{fQ$*vlxF95aO*$8>RjvGIf|xl~dm!s*|dc zVE&Q$6G|}J95H10`&f{#TJ|O*wm#>Ve8lqf+vKKaK)|BS!H_4=$XMub)S^rmwnNLx zP#T$?=8!Uw%Aar}0R)f@Et;+!*O`(^pQ~)>AKX}+nbP2OHxqA#HTAHzsgDnv{d#WY z+uKsI*_TzeBOZFo$KIC~xc)zJ2;4 zQzfjgBy0!m+}9R@e;fYgkLt&86K7rV__yJC=%K13>i=X&`3uwuOfj!eA_Z`Q^bos%I9ceSiR}pflYp%`gX1r)ar2dvrmY0X z=sX|UA)z91>kpbbDH}WcStmezEs)2ui@dgrnMM0bYsh$15XE4wNIy0XXxHm??9F|^ za&OhE@s_O2X)$71eCkfRd=fKL7Fiz&`e&M#z@r45G)8kBx^H`Z{$IbT&h-S{i z0+)NW>68M}X>^r`--Q0AQQ}MRtWf66GNOVJB3TvS+iLfR2vl9#kbD?tH=*#?VLN&2 zqg^0IWfq4-RhLqY_Y0|J0BN3AYdL$YGDX8l(x3rN!Jx5h@*Q698lgg3U9}SpsgW~^8-51=v6|bxC zB-xQ5^apCK2c4%yVg_7@tA|sDf0ajRdaC3}!P4=R>)QBu{G)=gy?!qC)1UQRuhBO1(uyZY9?D(y z<$rA4Vknu#S_Zm+@$pMd41ez_c#yr;P9_0m3W03m0_Hh4pG*=#y$oKYB{ux(sbDoG zPP~G547qjkN!^APm^Updnlo-A>DqZ;na&`eb>HW8T{z_v7vJB4(b57z-j&4`R~<8X zqJ7c{Oqcz{1QuYK4(3ZtgAZH;;%{9zNfD0W3{r`*pSO5&Yf%J7puHc}Dz#LWOXr8J zuL$9+*%K04SqqH1mXF(0;=N{$zeL6Rg^EZBbcW?e5@|8(%KM;iKy?4wvsnt0%Y{HI zN2Tke3QzH4WgTOa{EkB0O$H7Z4C_`UPx)eyc^8WbeS_(l8z=o2iQ|Xj+ee{!PIEWw zqX*Z&$DU@;lBQEAnG5K0Qc~`iQ2!7=a~t;6FCv(80FFOh52#652qkkl8BLWzHMg0) zbK?lhlr31}HmN8EhJ>;u2NokmMSmqArs&)Ha)b8?$BnXXMVpy}r|xJO8c1&) ze9^A?93`o45myxm_pIjE;OR zy+L*5@;Lb8^?n+t-y~Hj50CU*$oi#?;QedjI`CA$Y}sQdYu~D-<9+rxZ7Klav`;ya zIdJ-6tlilz_#$pCC7_K}61J`7n&(!X*%lAF9>YnBLxrPLV8|G=l3sZL-7koL5;Wn? zyb6%e9SNK(QHSGDUH`ak$t!}n)0`#*ddZN;$S~}^Q7hN4`9*_g`8nZ>)0#oiqGBzh`LE+Oiw>b&r{##vY$-cT(vsZp{Wl;oj@;8#}wrEEH(*7P7_&Gu6u8!4u)q~SGIcGBAEdvH>P9xT@xp_c6hWE zXS+=LHx|%jUJuusF0Y+y=><&qW{hU5Ctkp(hbtY2tmgB_tKP3JtrDq>O#)-TP?dTHK~*G|bYU$A15>8l*mO zyJem^*!Ycs(ZYwn*_xt~D2sLEhSnZ>1VlgC_5Q4W!2Kmx@0cnM9{x_?Z1Hj%lW#lI zTNUrovFIRmZkD0k8ty&DJHAOy|6QsEPX)}vx=K%D!*(0HofdC9OzdIDGSTC(@5Cly z|HU8oie=5PVR?6&k&MsMdGc!FdXyTX>*c=1AAj7mubT`0$x=Ad9|Y#M)@wYFOE%y+ zbLEg=E;@2%ZC*&VcSCJ(AbA{}xv5V-1_!Yeo>3F9oiy-K+Ia@>xHgpYo*RE}JIVJU zz9(5s#%MpjybdFgp3ZD>=h$Z@ZulnbUkx3w*s=4^ zf={l8VH5i0`L$3@{;NWUB3)0J{5{vZ-rMyCS3LWkM#{UA8;SfbFc`nwt&hC-^bC&W zztcf0g5A$FWsD%@PHVPaqhn>`H`ij(z(zRxiRI=q`D+g$o6qi{=U$l=_dJcuX#MG< z6$ZQqT`qS!v(Ef!4fU4a^f%PMFM;Z99E|Cy4`LEolg zDy;s-W9y0s{B=bii5xF|B%l|{yZ`oEVEO^gWhIJ- z={lO)XZXnYvXSPTgD608R3uF(CBV5o?!iKmufb8k+)-eQw`X5x@&QiYenqQii>g&V z1Hw6?nQgZEV_R8ho3c&w?;D9%O;W5-&CvLd=cpt|fTN!i!6%=9#P+IImZTZ8D^4;a z&JYMlQJKjv$pD@lstAX7Lt6;yS zbyyWOF2A^^?r?68UeHOE8vH%eyH3nLX(zQDFq2u}=1cEPyRp7Dfu#*4t=$u}ydo7PL$Pr(i=4AGFK8ai zkoI`PJ7<-YobOR4x<)q+H1$A8b&CST?4G|bqs2by$X>;d2lkAr+Vx-I4VV3;OtR8K zl7q&H>NAcLnR!HixBI=*>%Fl(h-OgGFe&C03NJ|~dETtJXlP(l^jN|IwH}?j3SEpI z5y3X;RI4ximqD@3T_x#c_;;6@LL*8o>wWyKORF1XjAXtDcEDrA>~dSS+&Y)|=H{|C z7pWT;qB<8O7ne}@Q9)_BEnnc@Gpu#Ce9G)6xw?*UScBRr8nk1!K6OU#%*|&l?UE9H zHFr(El-yu`66oUrym))Ng)kTMt+W@Z)Jv!lj|_fP-isu=HaUBLi{Sb1BS(~w&6n{E za_&uM8Ccgf8lO(ymKqY57dUukecEqw+}=O40@iGW(SJKk&iVmrQS&3Yboq zSYOr((k?8K6p&f2w_YA&Ggx;0-5|#Z3iVv(Y$O}iTyo`VXeOignRPF>`anAsGqQwu zzfuTrILeEt7a@U3)o4n+!5|8*FZ;rnU4E*o@TO#{KBqx1=w*`W$8td(D3pFq_*3DV zBc2b0NmL5RE*XgUxWl4itZ1A}1Jz0TNvcCr##)MWI&s6si&#dT@;DHJ`ob2-XjHGYipmDaC>J;+wq)zO19_9mRSR}kwPiGkxN3f%TB zZ352lp^46qpL+yDynljSm{W|E6c}sY4&4N#aS6{Mmeq>@m$EBUlE7B5azSMuzt|*j zI(LZXgS54G4!!~J+_X~3)-nf=w+<{PemLn;YRQcWfm?e-J;eMbfT-l$$p9 z?f3IW5{+vGgJdG*Aw;{#V=lW;o1J=r?;g{7Xj_ePL-PEAh|LUp^?TUUL|>EL_|Ck4 zX|voSxo>s+Q()r8c{v%n5za7#9b8>K?X(P}th{mRhX~byG}_LiOaT4h{S1XH)%Ngk zPWCDqnz^2yv=mKjY@o5RoNVd;Z}6mo7+WVs8~OPP%}9)cSXA;25yu@NW;|5&${UB! z*XTF(ixW9b-}V`A8jnfqf;iguwShXY!Q4SIIo11!tLpN3|IVL0s{3tw3#Y#9u|LND ziad5XnYBtJNiD>=Xm!-EQk|jQXZqw+vkYywYuY1sZL+-=!xzPGLrmW+w?h@X2qs4i zO(3^kt@n%KZoyf~2Hg4j)eAqZBEGSy)&p84Z~r_OUkc`j7>kHKQ$M?!djq;`(LBlp zgbK%8at?8a?ly2dr*X`7y}Zs=t`Q3;$Ez<5CRjgeihUGjmwkh7Aod2&urUBqMNEbo z`1?t?;nlGs2*Ao^dHHmr|9Ia<&xHW%%H@O-}%AR(q&&QAg z-#5qDkXdr_4kkqeQs=Kcq&+Qh2pX=eb2=UV3Ft*Q8Sw!Lq!3~O+@IYwyL0|TBmL~_ zMqbFeG#nlrW9d22UYPF-5v(BVv$rhr{pgMmVsX{h@m^wtdfO>z%y`5<{Tp#gr5UT6 zTbZ1n$L-h}6THkXb5Q_bcZfSKIn-!zJDRwSs_UWWbe38kp7B=J0Zn-&5Wj)DTfspH zJzVEqZ08qSp)$p}&>979QR>u?9#AvQ70ZjxCTHYrRpD(o=37;t+{%T*149T!nS$am zHr+J}phV&O88$O)kZ*zZ=P~xggE*ScyYZuVoZCSLSUB+s_T+l(DX8Zt>}dH!u*?6%M?!+XuLWpnLvlqSrLQC9_L-GGvZVjCrP029MM9(Xc%xi#ses#!WSltaqs>zn zwZTV*c>J7$WFw4CppmAU*8qC^$KuAE*dv?Na+|P|^aH2tzA)fJ+-nFK7{q;9r<&;> z_|Z48ASBrrXJPU_S%8SLa%T{~a~~Z0LCk2&&><>U%;bxe$@^ON++cRkkn&n(8y!_L z%Hs=sttEUVP}C1D$?HWE(?Ry?2orJ4=ueYMX|4Q2->;#e`CX8Q)F z`sjxG20UT-!H!W~TlfKD|MeMB%g%vna*a+x@W+!s@BzQG+vI&6J4Y=$YBf7Y7Qf^t z42cd)hbT=BNyBw~c2LwiP*hhJ{)chGyfDm7ws)}`_2jJ|y2;!ngh$>Q?xAI(@PA(I zRzN;WVAfiF{;GPH{j>`<;$Qcp@_E~WRZ}EU7J5>(}E_tJyo~3{$A$gmf#0)7iLO%N0)Z2e7|%aokw<2%^XN~p1S7<@gKZ5 z7JWp6{<-@UrC90LF1+fk)q79j0+on_et?bR+3b~Y7>JMI(T^u@y#6mVYW>;`ISh#4 z<*Yj$en^QgbbIeioj&zJCD5QawGS|i^gowD=JE_qp9gqRhMc-E$59wZ2ho>2h>?E% ztUO*`^6eMi&G95P8GPV&t?yU5uwiFA)U3Mj`2x-b6ZU)DQgaDHue8s8a<_E2X1IIX z*u6WxavnLkFEq7btpDdV-S%(nD-kvZ8pG*adM!Uu!o1LBz3vER^O>tI`$Rk%>+1fQ zo|D~ftFGI4FTMftA>?7phYt?Qo--J`^j!K>6F(C!-sD_H?cW7Q3laWkW=3f@7=x2^ ztoR${JXNANS|Et~cJd5c)%6OgSx+QTjB{;79;WZet5Ip~CEN*9-RWl-h?yNwQ1T6o z`u4v0vFN5!>X zySBPJTE)xB+T?NSLUOC&F(y1}X4>5>um}Y|S&{W0^R4w7g5y0EX}<*KUyZHzSfwv> zMesR1VUshi@9WUBt~x(U#cQ_TEkX75E9M3cT}Pbo;CSH0)T_2uxpP*od(Y8AW7}^} z?4r!ikvEY$NL{19zMzXC8r=~-;xpVU`W9q&Z_LRwoi9Go;&-0&_xdH4)@4s9UAiaV zLNs;<8HTWn<7u^j(=H9DC}nj;QT~$fi1;jz1RGXK7*HXRdgJZ|=smxG57&^_82A)Y zOsux2cGaXxGpmnclsM%pdEygteyz{%%iDH_s+en#Im5C*qB$BQ@XZVGFjK7Oh35`K z#KV-|IF+La~2{daP$rotCv32d&p{bM9HmG?{N@Bk|+ga?l%7 zOCHvYO(C6jeib2A%;`AP^P%UGDvF1La@c-4<97-3BvfoFg4=>~BJ`97O26Ye__-n& zU0b<@w6oft$ENjbN~T1-O>icWbDPVEpHckNCE9J0=O{*#5vA9m*jjsv=jPKjfcr>QfJf48JHi-{B zqBQaLJSYa~O$9kEg46C9#_$q!b^C^17tq#yL}33On(F>A!#G~?7#{OD-U7ctw0!9p zo)T0d0{S85vN$2S*@V8re+V3~rAyZlsp8WfsJZ`Ve?IVk%czJKCBmr-oQkcU7H_j| z!t-%o=GcMD%o`K@6c!Z z;m@;X;at_KvD6fMKL$Tjr!q-|Grh$Zr1?2Xx$>$~Crl%@iw^+^Wv4=h9^Wti7n*~Q z#F}1}u*>&Fm%kj*S$7?AUXpN}^|6l`4+TW30%kn?KkMy(Du&|!x>m}RGS1XUgXHQN zSLrRal=t739bY~&DRx661Y*RMtC6FevkK=(L>bv&R|07lt^Hg6hosTsSv!kQibs5* zi}S4W1xv$ru9?;CCQ&m-)i10M@&n9=!mz?AH(4GjnRP9uX}7PFZj$%{1?R%j>xtVt zUlW7fA*gC@jA0#r^oPf)kejy5R{OqE`eoY&{i+g5w5@s1tH_SZ&Yfnf;#K?(pD^Z# zOH=!WrHp7qxP4vah}~m8{=5a)SnGTb!iLgqNjf}90mHifB6(WlkVHF^Y z7HO4p1odAG=1)qp)A4EaulE(2)j=ZKWy-girj3KDyg`bnr}rY3uZ zo41}quryzc6ED#%)`W4&h&uDHv!XODL#Fx^bD})MVXRC8!(oU_48vi73^&6edlJJr zTwPIu9dCoYmeEb4_%gTD`}Nd}!9|Grr3?-W5?FaMK(-S z22rSSEzn#W_BzY~X{?1;w@YkSlzr=ro@3{}(i8Atzlptt%y~wP+)#7*#otcn3`V{T z+#Wd2$Lf~ftWWy=^f7RIIpam>EcQN2v4T7{{lzkHDI~rhW7L{28H}`%eJne$pZ`9o z)==ZVu)b;IlDxD|A3wrh?94{^MyT`cGDg4J-gGi)=U$C2H-SLTMiJAqwy7wid zWo^$UYPm$8Xg#ZL`BV?OD*6VBA=UCf3%uh+jJ$^Odj(u%C)~R{IYu8WDMWzKW4pn?`Zrr?F$qW4` z?xXP77OmA=HxN}n#;_lx%-+jw`7C<*{_b|7(Qlgcc6>>55fO&G)w)|bYUXJ&igwd*mPaeGz)oj>W=vtO3| zuzS~=fDkEnq22A&PDci;befh6VFOXscGxsm$Hml3u1KK{5P12zoQ+v|Z1xE6Vu>?v zHgKtxCZXol8;z8t0>=66tsIdbJ-pv=gGs~pTUYw7q>A>Qg1*y#-m&Lv_Cz%yXOd5Z0K*fwO0NJ zgka{KkU2bSxk@r^vt_;IJ1<`CZm)LoAD4e!g{hg^T8cuvAc$kZlPx)YvpPf=yR{P~ zduIf&jWtnQ!OH5|&$Oqm`h3r_3+*>9cu^G!l;*x|Is!ka<}E)>Li@kFvx)P-IdHZu z(!G|&n4}9Hp|&Lbi;cI5xJpH{C^xdEEIGRMM~q?xX85!t0R`b>sb@*@j9O`jV^?&I zL6-)T>DiIj@r1)%KngInF=F1|*t~VC`F&Nx7S9*}&IbS6!gbh>}y6FO*$1 zGbp_<`n9Y;=p06;`r+NN?Fq8;JWkr~D)L8{Fuu2Up3|SEcJU-f%tS@dQ&icMgZ6U# zvC-CdydWD>^AM@okq{v3ZfS|p?3+TqfXPsKrBOP(d-l9`;&y*e-R*$HKChi+OAFmf z8sV+3>$qE&VgFti5H+Y+Sh9d`2i$k_0c3LOv7+c1hbqJ0(hX!-Y}`t1a^1XCJpPl6 zaIQg`s!Iej9D7cAuANMs6=ZOnwU`mxokzNjn9?QpPq||h|O88 z0?r#;O64uW=X~pFtERq2rkwt7l#gML`qGyO&%-d*^U6@Xpyt)LL`IeP&}chbNr?8w zFSXV+vf%(+>GCO?I0+}@Tp3&7v3rZwM+3XN?sV3-?#SDmKRb2zE=h>p%;su3t`@}k z1Sf!~uJA6m(1LkM>>C%dpS}*}5@70DmR_mCb6$TJq;-4uSlT7v*N{7wu}qugs)MSk zHmo+jz3ndYIL<-wmK0v;8ymtP+O|PGe^E6{6q7k_vJL4p<{t(@KZ=jF0-p6@qD62X zTTZ@|x^?*y2q9UrbO?oRoZ&&3; zF9I?c6gayeZM#|`!Yf}XD0>QCyoi|lZ*=oMg=_k66$9*I6BK$Eew5wwIY{{&jkoDY z&krzO+;4tw`f?fNqqVD#cz&8?8Ru@3kXAkm;l;5E2apth0nOQFh@yAK#o0Jb#9Q?Xyub1vaN$p+~$8Skyp{ zHThR;`?x@L4mT0*PS~_>=S5oicNWPXQ%_g|ZWud2T@Cs{)ibCo>b&9;ef2@xn&dcF zEPClHeeUhL(4hrHogR7~i+>`NXj>}!?=^QU)SX`nn}AIIhMRB_NJfO>E~tUoGPXi3 zB*ty|Eb_wMOR2!?vg4sdSP+w2Zo)|Zyf9WNl@I$&QrP3b)b(L0mH1ok`V)PsyzNjR z85+Oe4Xb%3^u@>X61a*+!^s zaNrTo0gL#AtuoS18Gdbkx|%)M_`Y%5%1I^vDJ`a6OJMT#o_B86I-A!xD|e0K#WlR$ zUo2yZxhI>uej5vOmkm;R$Nb^;?YEa1Frv+;4DuvF+w>$uDX*-LXSfsl_r^>6pkl0hbp!oh% z`ZMD7XMacBIGQD zH5YcxQwnc;7Oe~$pyGdu!sLgPnY#=akYAvI zn0RHeqZwc3%PCVDCn zy#pGp0I@b92oHrhjsS+ei5 zp8nw_6fJ6uv1;~CBf|^HLvL!-rjYXjd*)fPf?4iX) z8R~D6?w4!6>e(iNRlH3cYB8NP9Ho}pKdc9Y2Bs~}2YXOwxRiyvi}#98E-kmtWZF#= zLE~LmRv@IuSvl9$=Gl4Wy;W7wNpjoSxYsrcvuhb_2NSv8=X;Ao@-W`MHH}B#7I$(C zv6(lO#E0x(eFZOt*rB`Q{|qwCISFHAU3q~Pc5(F=D{x{Hb>QnS)B)*Q4oRNJaT09u z-N%-=JgU>3H#(gTJg)_p{>zl!6c>~}=``@`?%7J~8fe`RnK-d*YB7}b;H~Jr-5dC0 zc`eHvIH`0dQ;13Psq@2g+{=?N0>u+!$&;&qV2PyUAZoQ-cYc(oll)5d-VUV-11h75zlYimbBIh3_8+P#paS!Rg9bC&SIkbs?-jjcc*6OJup zq^V~SqQp}MLn8}}r0Z(aTR14|Mz1J!lTiW4=qvW2Q}fta`#5d~0MLcX<$T5s<#{M1 zBe50u$m^+i7TjdKOjAfvarA2uoTeCtvl`38&3T2W@VEd zobt*#9r6jh5y}h?9ZV7}NN|_^U#-HTF|}3^K-T{U@$?%uoZMb4v>alglf-c1PwGk; zTcJA9X?lS6j~@t+w?jEi68nSuO3mKQ@?D1_)r2VSGWe7%aX#aQ5b(XZI<4!V2&KY^ zi%KhZcHytwsESN^f31BTZE+`0^{^mw$A=60r*|hq3o7q14UvxQdN*jAz7Yq+qKDA? zbr*zp6;325-38Ntww}B*RQ2R_(?2HyovO#ufO=%^(5W8wYOV{#9&-PUcVd8~1s=*N zK&j!>&+!k)Zd z`q&di!8@5qX<4lzL{~0YdVv>6pYY|9A-T(Tb@QaDa)`Lg%PTX0AhSac6Y8j-)lSYe zJ>f{idS$_tMIGyr;HcGu`w@M_cA-Rt7}A_u3=Xv`TpiATZjhv4kDlv(>G~BqcbQ% z2lss+3D}~Eqv<)>M82G23t}tV@ReqRV83D7@eOZ;1U;Lh8WlzPb}9dr-Q0 zJCQZME5c!f)&_yXP2k5lEgI;wsEOxGNVGfHR*l9cQ3OboO=z)tC;tu9{ta}ov$04$lUM-q z?uPQ+f4!~LVMc~TZw0#Dh-#QOEiy`tSV(2&nMYKd-2RaybeY^*j^;7$tmtqxXFcUm zAITk3rbh)$J)&!rJt|DyCiso#9z6z4L60nHCk-R~TyNjD*c5@HGLNC^#J*s zi>;V1p(ICg0P@L?!#YXfJ+u0NTf!&Rd6M~JB zmjU-f?Une8mwBr`lKD+|x5Vhjw;!b&)k|9x_bc?kKzfaw8}zS82)G3atuE5Apu7nL zVPHfA5}EBuVTn$&F=lAIh#6$F2PP){Q^s)|+PeA_T5bj7A~a$b+e-RKK@v!WP|E9% z3MA6%JW-~~+tL9NS-xU?zZDp%d8S+*A{F`NT=^$cU?Tg4a{2%I(LPcB@!T@+r336c z##Xh4tb1O+$TSL>nq@PD4tt6-0@-LXU$UF-H`Bk#LBhRBJVHktr4;t~l z{;t?;vT?WWGz^ZuX?Uh`vzBx$?R2Skf8%sxY9IH7c}wo(vr1bjA^)%nT6Fh)d-8Tb zxeaT$;xYa68_M2NzznOFNhJ(S=X#U{pA^0;C{R&~a!}S-P}cBM z@)gB|#$ETFqK?ri86i)2)6%ISB_<{|7A6^PCK*;HOnAsCw~mYgSVDT?MQUO~+5aRc zE8utqY2H2gkKkJ4y-APJlc$UXrzD7^+6(ee4-F{~zlyXDwc?k>8-2ww@&iyFL$QD5 zN=0dJwH0dB|HHa}$SRaBmCztLVO@`M_&C+sswg30CL!UQG9?znsMVGkj^SV)HoyDU zVh`D?nKr8br)B6MzpMaduowSnB?FV&{`nCi&5@WFvsf|(Ru`bkS~5S7w)@rh$SCV! z^pHAj+y^5oFr{zk)#kMqfsEb234&Mk$k`G#!B>sReMN4pUdj5}$GYPwBwBkdJ?p44 zP1Rt!;1zB5Ka=9Fg+R=L$v$oxs`oKhtHXirCD0nwK$4GYk4{e!N_^1l&XW7$^pMWn z1M$RFu2nWzxyS9cZTWBqv0S2tt9v;N|CNLSDaVV)_#}ZsIk{R&}-78@zeQaRO)D#W)(ZQqnT$mQmifK6RcgI z+vRKd>LPLPpK+32O#?C|ZqLZ=G#noB-=UVR|~^rh(#)1XH_;4F^ML?#ui zjM*3E>?Xcj5-*>ZCA*v#O_><*qr?c1cT7h6*5lzX@L+7WvzpEKXriimF~{TwmfS>n z9VKsl+k2KAG6S)AAA2e{jPTdg7M-2Xgo?;;FD6lygk{W1BYGvjL_i2OCYyWWML_V{kWb4KOrU0EqrbJxJ6EG2-2=b?!fpX3YsnU*pL0MjCM z{;Tmul*MjuPOO$K-;$M-);kgkV$G0A3aV+gPfmtFBtib-?Gi;Sh~b@X0N0Gf^yRJh zcg$&j9|#E>Ey(85SJdSq3AT!}G;AC{HywoeSM+@V&VO`M@oF3>42M0&x)pb;HTH>Q z{kzwwJ?q?i(OBeC_d;{p`TW(Yg1{;nZRv7MNGooCYiz2QVKPFfaLT##&oX;TYwT-j zxq0WUC)DfKw;~EnVNdMgZ-h`HqA|aGxmTen=cfx(Mim3pIU=5|RqeLygvxSrtoC|s z>*RGTMEaZ9Ob8*&-PGSYM^dth8LhkjGJ zhMgTtm+FwK7%P*WB&u+Oej_bt~XmLBK79`3&OG}iufwkBQ9+}G6mTTq=ZcX6Q@ zCQNn)CUHE4Mc$W{tK}A|+XNUVBb4kxQ@{XEnqM{**zo;3iyg83%rt{t?5!IE%b{{} zGl~23L_7um%~LSe}&zZlOqd0IvAB;eybpht$5oNf-FGXp3pf`9)B#-^tA$$SEAXujYfxlRmWOS0eUhYAZf1P6QRid}ya72b+#ch%u*k~CFwRE8-@M_S;eA%F zbApCkZ8#iOUf!a8UPOJ{{y4(=hCBQ`x+d6Liv|qI%{eSSIX#jH=znKmTXJkZEbTjr zCz0w#EYpq7+2t0=$z4iuBPRa^UUy9wZ16~^M}(IVKX8k^PlnNwJn}Nw*CgVloEUpS z=?YUQet5*y-k8d+dZXF5X=ew^1p!)h)%akxkiVH`77+78{JQcuiasZNRn8}lWRvbC zbTh$RZzqA0=fRGS(z_S#XElw?3s#)g4C;yrlT&(bRn>FxZbmxg9`2vboCB)nx#r!< zArrO-xKFxHod0TorUf(1C*+qi$y9(}#)2ixX|WhcF8wKbe}ju4`%1qNLrVKf-xp(;XR@5H~ z`1Uw=E+P3`-jAV{lR6?2{20!!@b3jfC(-0C({Ww>M!F*BgD$I{vp}zq&hhC~?fnOp zwk>%W0jdv!t#Q`2w*GYWiykL`4*}OOcr<$#I$lLQjw#wR-kyJ-g62i_=M$s^SK-=! zJh=B;NBIISTO>VJ{G1|kDC6e8J5;khm>$o6ZdN(?idg-6SuDX@2y}`$>p&%q{!wnV z`FrSd-7-I9Z#U2xE6<2y8uG_HCK3%HO{u$`8=((?qG=qzvcBl_t~JGJTq|~zA%Hpr z9yy8+<`4a;9=-duRnehhQ_7!G@o3a5QBeae{Ugn^Ju_5AF7FVRULwu4tLY`4b5P!T ze;)~}I6hkG5>EK-b^fx=lirpDPo+^Yp*Nkk#2Miz9rpgZ{JtjRF}^Ym@i0!`DP>{= z^>YerU%$$}zV#J}k!7dJP`Z9!U_`I6OKM&{pVrc@$YH~UderU;f0c7J)aiuCY2;bV z)JILcPzo&bWGXvQ&@7~uDWul;DomAuv`F@1l2jMggv%9_)CSJ59mj)6+ zCJc~bt!S0}jYM65vZI?awNWk)PsrFV)<`omWFyh48D~UDyllw{S9srFV^Fb0+Ry3{ z{R@D4{|bk7gnS;L?BKRoev$o-r%%;1eBS_CNK?Dr^O)2?7wH&-8B}|G6wBDzBdyDD z(Sm+SqS(Jy*J57hvk98OWy-%JdG|7@;8Aw-Aax+URX)#^8Na>tJ zOHGnwpPV6az0P++syA@kb7WX=!L0t}sp$bv_8jlg+#}kvXOEAcxRl3-Yj)h-(En#v zc4++Qy43vm&~n3Nz;C~QG4bgaw*8w~!QpAuH_C|AmHnb&&S8uvcEqY9sM6<&=ySrP zFvB!jQxy{_$?|>)=Z&N9x;sSxoJjKV15Ci13s({}Ev>|UGGH20pD*%Fy-8eKVnGDV zbR*@uCHemjUZQ?y26Vg<8*2S5yOq=55SR!in|;K{3{q@lRmloR}f$d&^)~18-{wcD?wADNd3RELmon^FgX=W zj4~>#QoibSybuNs<@FM*{z(bGuR$%WO4H@vu2!J|?`wi04nl4>P9FFwAN>Pu1FgDh z+UPM?;rEI~MY?)jvS>iz>x<*o2g3a1zxKDn6>;*Cu{^I+E;wGaKw^A8t+i33%Tay;DR7vT|6>T99T=OiU3E>Hx4|@{E9nn` z9bk+Lc;7wz#1=bt>33((O~-FBy}t>rR&a^cXDIdRv?SY<@?sgb-=Z754eU=Zvbz_F zV2sXd(VnQucZe<5tzcU=Hc75%mVc|&M@}Xb9mKpF{Mwln=^1e3P_kc#O zb~Dg^S1t|eRtR4&!oQE;V!I<)>GGOPL2exzB70sZV-E6R?wZ@+Kda?hwGDWnKFB8V$A_UV}s7=$&tpkta0yra8Bzc z?OW?5K8y;yAhD2i8thn5_K>LO*X3ox@uCq9IGG%-yYXzgxjOYstc}P5(1}x&$m=um zpWFNhP^a0ol^ZH%vX(Pn{Kl2_$5KmZ{Zuu~y7XtQw)rB~SMN7G;v1*sSfiDZBb8XA z#~#*K1J+k95`yN7nPpCDdftwy5%UqoN4Ld7^$cH2Q=8S_R+fXS)oHbI#D0q9$bb!h z+QulJ0SDA`dl|Pz$R!b*hKamTjb2NzPygJjmRB!t@BptB;Q>_A$CSUgX!B&Ha%I4_ zKW))5u;OIYGuYN5OBW9e>n+h z8L=%V`k@=!Cl9-?K2kjE5!uYu!ujCCULR@utx7O%d@QiH%C#Ft;P%u%~nD8@aC-b*dLk@MC%_JK8djJ`q6ME2R^F- zS*&`u2;oHT%Af6_vrjS#{e0Dh-}}usIsMj$?s$I|%4V6dtB|^Rl0Db=e0IMo922)( z5efL1N!MI7T|U4fGn=IUyAMjUu`f!T%%H*~63mXQ>DW2N*p#AKgl4qM=q&Wyv?ooshuw>qAfUSyk*6*xJ8ut1b!OA{%XrV8 zQSyK=?8-pUOfyQljmulaS;gV69}IC3w071mGhR`F>;uQB^;Qg_0~M$>MZ8Yaa4=9 z>8NAzuoP0oB1^3b9g@^q?o5-88TrR4nIn0nz9jm5`9qM&uj}VMGo}l48A3Df%d6xb ziz-^zH2d>R^NSv>}_`2l7ICGCe2r>w$U4oxOl@oG@-mSM}M%Byxx6VpcYP?&om;3(wD#n5# z>PP^`;02Cvrxwn~lfVRT_E};|jPDd(O5!AvT<0886ZlVoT$qJo0~GiO25vK?SQY{p zt3k85*jG<>`EmuhL+{1bO#W{zy1&i$U}0o?E4^EPT8|y9DgL3}ef&>}x?*&U_E?hr zNF1~^@Bb54%mPQ`D1P7XMOJ$1;>QB-rr%yNrr97I>cchP4M%$udt-@dqcRg`d9{*hwxu!CAO>XmYr`?F&pOCMYvGv#|s((@m*580C6(vQLCV9Rc_T+Dj zDM@mUNalIAwai#pI(cWc%t)$@>3)=c-J>FC&tTbPT41bVU$1GR4=*gQz$usEyQzG%3dtvtgGApMyed_9H^biso&lGN|*A2OZS34JP z087alS;@tuvjwK9y6~CCk!kPH)@)6=u;NU50>_~5mkI4*Vh$DWk)0y0GStdzvTqx- zQ?G_hJTmi|@xu%N2ET7uHrvtfl}^bH1`O=i-U8OXcdDwOYW4cm_ZjecjH`b66DM6z z#ZGBdS!b`jQpoGlUu`|*QADaPM6lY)lw~kDXJq=lgozgvO!KMEnFL!l514#BUj&X# zs?4u-iGMUbO6!5IYJbO@x}X=}dx+sK&SI;XZl+X4FmIg=T(2e+ynwm@+j=b8<#?ek z6UnWs*H({}EAPu}0OlP3Y+r8d=V7jwo*llQm{8NM$_)zN)&Cpw=XI^@ykdtQn=a=M z;1)V5>in5;HXRKu?r(2WTu#xy)UXZ&8gb)$;>@?N#tL;p3U1cA!JnMvXZ8qDTkFq$ z-R^P=B-~%u#^+d!l19gMn1>CC}&?W%gykeuLWp2kMrv)sJgJR5229lvtOm%7*EGahFi zC4~+t`+lt|s>UnP607*?THEWh3YeJWifC>Ap_BUqGG3arO_KXb$Fup1()_4Njd9A@ za0gHxR5N_+5b!u~9MmBf5qG(czRIEjqA`IY1Q-U{)RuNQDxxp<>*?gBmdgY44scO} zxiky>ui&!q?Hq= zeB|zFa`tkg&$>acraH7Kua=c&ijhg-3302Eys{gnuV)624v`Qzuc`KQxrmQD8-FJV zS!h&@BsLt8u74;vC=|x;Z_s2azmhc$R7mN0xUkIG(ddePacM}?2>U~dNeRwVWKv5{ zrIoL2+BI+3-6C{{HLfz8eKC|a-|iZaf@2IY`2SFHmQ8aP)|A}R%`_KSIx8PlHo@<| zI?Z0^6!ygApma3l#owHab91w=w!INQ$8(5W6jm#{K{ z8U0%?A3qSUX^D$BYU!I7b~eXaXvlm@Eokz9w*`2J->6y+&$`eDiMwb@wyEv#j6TRN zP1+z|TYff-iv0fYdf9pF;mGE49>NO=iVBhNc0Z&@LY@h|k=%RQ9S^&}91hw1;B|Z5 zgZl-W#R}{&lkQm7IF;r7twUtqSdjT?rSXB4!{v^Bunr8NQR6>8+9m5N555Pc;h?t) zfA17OE_~frxVc>(x7Ri&g;zt~GG+Qi61dt{qOQnMCtOnMfowlKn0!jQptPpN$n-}! zg!C%3;5VYIRJSq@GcM)+c1!$r`I3(H?03{%luYYeivX%Uk$iY`H+0PhgkUfbx@glF z+~#ua@(^T|k0;FfqrUg$#ca%q8?ts^?KJ8i8r~b^C$<$Rj!rUYI=WDzAA=J5k4Rr> z7{-Fkw|59sIwC%#FAf$xo8Vo>UnRs6=v5G5(ecT%}Mdh=u^_Iq9JX z;u*Y=uTBGe?XgcVC;XwO`pfDPo76!qlB8z&{so7ir3-7vvW_nOv*=wq`>3gZcTZ6f2Wzx zXAal)ap+F0jy`Hhyl^>v(NX41tnWdM~Ah zznoeb0F(cgA^x(`@yEfyEn4tVD z_J%<6G-u2{9;#3X_TG&z@fha>h*v$aa=BFHrIhihe;yCV*?wYh*PoF{1gU!a)U){MP)p37OF z*b(Stzw!yHvOd$W1#AsB-ks1YUOK3+n&&*bFreN+966aq;yP70pjDv@RWnrw(<)Od z2?`ts8me{8I&Gj9a!Vy4~%=ls3vb_}L}b!N`G&XoL@&*~6fhT~!^d*$Yu7}sow zpH>-RKHORQMHDM6JJfNzNb~WVxVj5I+t=9-pG2@ivtK%HGZO%a4nn^vvxtxGq4V=gvgMm82f5@mJPH|nhaYn;^JUdy^=S zl6{CRx@gM9hI*rZ>65)er+zsKFj~JDo?a;!?UPsb zlfL0ejj&q0Z?z3$6~%F;;~Z?FrhP{k&>*ody~V*4#8cU`{-z@c1O~bl~m1 zK=9MUBt?ICw%seP%ewD>7?jnM4NG0UCXd}mu{rq*UGC+6@pjq0u1vA#G3Zc1H~w(F z3;nl#N0L4GZ-oXHX{q~Xi!w$!3v=RFD7&eZx3Gg)NGFQSQ9 zRC`kTFM9`C+(z*Fxv0o2eqNWh)$s(|ak<&_)ynHFJ*7(Cre3?0bKFTNUKN zU!*wzsC?Z*BcM(llHn1&V4O<6vZ{PJ-Ilel?_jmYY7ffmqplW@WVpN0aC7rlhxBRK z05o*JRArv${tQ{TGaCP0mabyd5drUx^Yr(g<`AnMhGBc#&Q9$Q*28Sd9|TOxvf=h*_^V%v@$ zuJ4Kns4Oe{f`4O5dmknN)Ghl%_OC|<5&^mUqs}ra^r@$LsVy;RqsJ*lSDX)Kh98h5 z(!?to&2B5B3mE<`hQlkvBStoCb!Si;L7paDO!B>mrSM+cXDcH6#@v^bW%P|JRYRX@ zo>PaY-TFIyrgSpn5ZWI!OKPXf`iMcT8KqXsw=ioGr>2IHRZo(&G-x&hk`xN0bV~f} zbo(Xgf+v!9^%Om8<4=5!O znj;V2K7-;XZdB%{it^y-fRgCvV%I%<_7a&OQ`L6z&2k8_L4fe+#w_t z73MkqjBFvl_@o6CiTk@_4nrpA-i8A-jehsb`4#Av>jYC4>yaP{tCl41A$+~CA}Wqm z5R$f8==@5m;>(G>@?zd+paJ!F4cjk3X5gOZbEzEMo`~G&+80tE1|!tT*5yW5Ujo;E zUvtkh>fimup>Jlq{`TcWpH9P?FNPo39loAa`E)W_HDv<8g5YH+uzaMRGd(oE|618) z7Q9h=!NG0Z6@q(`)AOlQAaxNfSiBnO^jFBr>EbJmA(10Cm6-mzxGRR#lEd{-`6{E) zx41^e>w4WjwuBx`?(WhC#%oXAK1G`&yczUsPobCew>(R)ug|UjDgVEUeY&>FR6Q(h zeDG^2dF^zRah*7NnV!goCvX z15DTP6J;Hw0vDe}3|>pVn1E$0w+$|x2j=-yDJ-eN!rmz$xvRZxigM~>GxV=LS%P>R zi7%YVXSJ?P){~(lmnC_B=B6WUPI}WI|)blWeEmE0X zp*cO?WE`CDItbWdak`uI1`fqXoJxvS5;659guF2J3S3o$%}8p^x_v^buD5x9 zt~guSLVZD9QWPs2ZB@J?vFTmEn}r9&X)>a0k1z0CZIEItUAt@gBPrCkQiCRFilTv~ zj7xo6K9x(e`^cz!8<*Kv!|5&-n^)6;4zIy3?0LA^;#%LRwI8d_U2I^a_F}lYL11Y! z3--)ZM0FeAGG|-#)YG2f$z8r848(rDgh?XatG}LEq^5oUKp5Cs5_DZEO#ml5YV+Qh zzY4}Oq`IMHL23O?@PY=QiE}nssue08CWW9C9XK7f0m_0rG_MS4y;52))EB=dKVtqL z=(;TP{r%B>aP+-iP}`FfT&R_-M;wCQy9H? zaj_bWci(~;P7S{E<`p6vVYHjhH}YT~nmACI_6Z7S6iEh;W~dN)WBs$_vZ$pcN`{E^ zo&)jugfA@O0*HqCCL1pA$|Nl)2tVb-k5@dB=3zaPh_NNQ!7<>bYS?C$*d+w>^^(Z% zj@7L$s7U$^$=IpP)Bgf|$clNDm>wn?19beTN6jFW$k=o9o1SRo4oJnAwwOy^N*8}O ziCbI&OXFr{-c3dmu4gOuTMBxq;3QmN^yVcqb%6y=_fp&LZ}hZh1Y7=6!~-HEhwf3z za^nz3{(v9q>yIX-fThUHsu`UhdtS`ytW^{4yXe&%Dg8Etzh%Q2Et#{cSlk&@QIq}L7% z3Vd6P6 z5gWNQ=%m#f##0e`jhVHd``TRd3vd?^!|U;pbVDTJ*PU!gQ4_&{t-9S90Ik2x(^0Ls z!RexAaquM7v4^|oHV{+i>eD#vS6)}0B&gKoVf1QN9LTSOPg1huCOVglzCzTrD_A96 z)ne|94RVnxZP~~cIUU?juG&$y7~!+~XZ+E!sxns0P_LK#{UM|`V#lvLOGI5pjMtRXqVo2r3Hv41+94S+ZQ?6XbQL-<)+thE9D!x1nH2cS<-yuED zDKvjR7gWoyd&c7=+*ED6kuRw3y4Ke7eToj@TQ#dV9G)fx3j0coDdIB@Tg(K7g?#D+ zjv_C~&bFm6v}*!QJm7wRukZctMaL1qLT#kRA7`^jP(cPr4Oq8bIDcojonLV!G{3sI zW$HWHmE->)2pEWR%%r~;+t0#QzBkvtfVnr6r4DhP^oU)4 z^N};A>(wS8?6wm144CGSCp`>!2~7QcraU;Ov!7iwDZ25omExnrnBU3awCmB=rDCUJ zQ^V)P2a3Z~8>I%1@j|IQy!B+UnnQ;dtxj8{D;o{?HCv34?*1-JjV)gdq7#fU%C@i) zpT#m*$WvFuzKTnJ*MBmPF#~6Q0e7|S8BkmsdG(X{m$Ns#<>SkD)_JgtRxf&g*rvn| zp_{P~+U3+mDRw|w@R4c^g&aO3qnP!T*grQ7(+ADi z);wS`c2-BPuTCWQAY2g6myxu_M<9ifYAQLLx|sp{HXnnYoL-Aa!x+8t`YgIQOpN7O zy$+iCOBhNfA3&&Q%NeAUJ}6H@Z0&45_OnX&=e;{ar*Zv+ludF{q>kg4DF6HHcUVuK z_7VoLKh1TYrRmw6eqVA=1(3PZx~jfO4QUDT&ZtgpFb$bsH{b>(cksgLhKTf?Lp%gcuZk0vigZy{@m<&INPydc@kk9?bkdnIF=6(?bNue zr`@X?_M_2oE8L05;1re%3U+he%t{s>hDKqgm17)8-F)yzFR%*;RlJnzg z_aStp9a9W%-ZQZYpRC;2H9y3>A%^WP=$k5)B3S$T!Pb!%jTnEG`EmQmvfu|h8-(o= ztkB2wTHJhEOy6VO)ggx)y_2Su6puZ(v+1?6)i^RFn$J;_M}9aZ%d`&x_6fE2mD^&$ z)7F*%nse=naJyg}~RwYvfup57a(J4AwI{8aqsEW^3Z+vdcSOvqf2{_Rjzu z>0cP>(Zs64^?iKDowH1r^s^k7SE6$P=16bf-xR5=2YETN<*w*)4U$q}i`)Pw<|?0l~4p+``~8Pc$&1T4badCz<*> zX;cwNNc(PFMsR|i+-B&!{_?MfRm_3o_W58jp}5)jC!(Jr)dhe*f0YrAkGL=3AHGo0 zDm2v5jmAR`j#v~k>K}j{a=I$V#JK@yAsTDw=&dVZgUO8n4a15_q*r>rShszfpQ7!=ZY5#JGW1~)OBN0ih7?4yZWT{!SVc$nu z2kzLGNv!fb%vfpOgA`l%O^f~1Bb#>GJC#n@XPlPlP8J=F;@JI1}C|Ck3D**2U%oau0l4=QB_(SD8}j@x$8$!0 zWM@)3hb&PcjkDVRBEKyMDxV4dewm}MLpeKwXZS)Ad5)*0EpZnb4Kihfr{?;hIysO3W zRdYM(C?q&n{}uQY-Kpd3w!4-A+hGeV^OsSAVcsQw&=P`nQvTfJ2QF%f{zUbVIe*nN zR(^$idQ~MUb9-Nx5cCj$!9zM%`4JYA_qbQqS!6f#VU?IMv1e9-aTbw$mC{21{->^* z`_kMihOh1553&ExzcwfO_KqvfwJ#*k5xOX!tbmO4jg+IGqi8AfT`?F-|?TOQiyZB@tU7eVL_`%VP=#FRR~F~z+X zN+`pchVniLgB-@k+^uq2Onh2Ax*x~8A=*=SB_Lf7|BVEdWvp8RQPlN5Y3yC|x1*5t z(spnUojHhp2F-{xh}=Tjk{E62Z>+lCAx08hapT1I{swsOX_cI9zKoFmpsy$DjsLz` zk*i66THD^rA_6_0yXWLVAbajvol=heO+o!*kmatGzcGQ(LW||t=gCFUeKGk;5)R|jUcZMG z63W=YtZDceC*|uogPMml{UoqZRY+2)x0zO%J-E3JKDZn7n@}<>N6kb(7?Hg@YBA3d zagf{CjyrnS3scnV3O~SlpvkKnagnAmiQ@}=W075d(qi@!PPKrJ;`DkR-Fea1v}%*) zukNMS^R5ibXDmNb8M)FHJ*TiSTP;-@<+w*~vCvP~dzmY_#2cJ)^Ww(~QSmZsD}JPO zvM5xg{;L|5=e3}5t4$~^_tewWXJaxHtvA%{WG!o9DAS=U(;1Ox z+79l?QN*)UiLoNmn)uh@!c4X+JW`p3jo#u-@h0dKK1|!8Dr_+aI5eHstJ^Pba@ejn z-7aOlOkvfGW}RcCg#6Sa9qD(3`zAyDy?=7iSR2){@Pjw&jRkwd@ALfLyN_Cd^b#P?5CkQ@ zo*ynAy#KyD%T50M^Vhf=ZAz9M#5Jk7)^H`BGWvNF)yC@22V{<)#=IC~>4+_zCsi*% z(y^}T&75BKLlm|>RXH(-ZNb^j`*nV zHOBw%$&eZE0-K-Xrr#!`b^E}3CLEd)gal7+N3`91^PJ8Vr7i-%0KzxIBD`Jg;uNn&k?IUlX98<59K)(hYbXNM{7 z-Z;OfWH*6kmNi#iDK%0+Q-&_QOt7^I0PK;{lsWHp-@~vhUebuCb2jz{8hq{!oQ~h5 z8ScJaegQsV50;D-A&16nnt=|@UNle3h&Cw69QG~E+l+REo+&e*DSvbkqDqXj2P)2O zY&!T|f=)|!8@86X@IJirDh->GMUPGv^$U}*cTAsE*+zy-{sF1h5%y;)ZoKzb z^v6N8hXCn`Zv#HxJS!j1wd}+7df&80wnBz3f9(G53pb-}O+2$+GIPgfB*xzr?=nwR z1T;69%>%xonP+%kvUjOLTo>4}PHVVutiP)3edX6b4AMEMb5hy%!z23=S39sXC-~1- zhieM?WP%=bQ2afWb}{)qV=(j+lF#`Bupy8^TEgEr>>+M>Bd}K`0ei;g=p9Q*qMlNb zlxfipVr2c{^^azkvmf_@H|xG9y+HzE@_s_UC-8ShBP5uU>iO#1o^c(qMGw7~?~-1e z)Hgrb1Z1OQ#AEo30ACL-5|6!HNJMsZ?@x-0z1~xpcurta+)ISBOD-zBwhOg(D*b*X z0!)QY`n8gE6J!#gJkdiMohe&(=>tourKs&UxrUPm;m7Lr4clTjWCeT?jn?}{VDu%E zv2a$>Jw=g^i5nZiuNv{sYLBE#UCy+HF$5fvr+3Gl#SB1IwMWXMa!>2J{elhTs%zY{ z_E^V4V^P;wKZQM~%ZCev;Hr#wTxYz=11#W8{@Q~q#y*_NNlgE!0QD&__9~#g#$>iUaMdf$TH4!}x zJ<(?L4n>olQUMr;d0fyVY-ODM@6pcMui;-fE0duE4O-hIHY6WOk){V_nH|8mSJ^G% zje8^cuan}I<^g|2ehK;moEMUBWV~1k2I`o@z}yG~ZOe{Y z%Y{ntc|=8u+H#2v8;PvX1gPywbj|R(HIOP747OO!VZ5GU!2l09-^+R-5y(+KbM8y@JSU}we zPGjjRfrK4c+szqlyZoqKbaDTj3BC;54)5txK+>7aeJaa+BYL>8UO3arF!9&g_%bh9 zror#bgXG0yqLfxGGA1Y_k$yBv7dtQLjCc%xn`1-KLpcT%1hCO>2w*&SK<_N{K10Mm z?IM`NG5)-w4#GeO>4#D9{<#zMz-3oa{(M+PLYLe*>Y{r&qFkE-m_yiXo^Ina>NxC^ zIiTH}dV)GSA>$jBy1`+=TBX+Mp&9{y1IrYY4Y$~^?y(1FKHK)*;d><|T>E({OMPY8 zA5|GHLwU%yBf0vuWEw+#ZWL!bprX&@mts5Mrq8tQT(L0Ju$8){J1@9Ud(@KBFy2s3 zy5OCyKk7|bne6CN(Vk+vd!x?;d7C)caFx2PJI=W9bKbdP51?PxvaMScZOfCpsq22S z5gulT4d8r0)lcS^&o%w4&m>=VGpUiSU|JfLy4wo24GW6(^A4rsU_Bh&7}g(5Yzd~T zLsY5y7t+u-gPk*$+LPEBLkC1v@kYg3-h^+!-m;^?w;Pgi8q{{BMX;Fj++csJ!+kO zGi7~hFPxq~E4NEpf{QHCb25a4I|PM+O)p7)_$oF!{*DQ1lre!9HxN3;r)`1oL=t0heIH$ zLFG)+Inu$LTLv!Pjj6rYX~#RSGZ~|NtZm&f(x$taN~T;jvAR11uq6pr0pV(JfhAjz zVOuJ^P-AsYR92$Z-O!>@%6Z0+V6wg~D?}q6Rx;AC_Y?Loo#$6#ojmu)yLtzkH$GcR@9OI5w{T4Ko95#l=i@1i3K>`ySTCBlUf4^Sr6u`m=ox>Z;rkBFcHT3s zd#_A&2%#0csQJuFFIgFIq?avzW@O#N`DysrM?&RLp8Wc+DYhk_07Wn6c$zI^QC!CB zed?0-mPuA8U|E_t<>?bKA+g$Lq6AwqK4m>XQ-$cmtR-2dvJ0V*B~x8ig(D3dSDEjn zyWhdufRUK!*>2S!V_SHnp9TadwC0IFyh7kFuuhqSDthtvo;K(tk>Rm`ZzoNjd9+4x z(035@c2B!0yJ}G{*TZ_`;aIqWCZeWt& zR~=+Ff+6|47d}v;(%aV{SBsv)Cqi_Zqm65xDwTn&9(|{t=RvJMkE=TIzwDk7ORMkk zyq^4t%RZG#vKso`)GH$u9Gid*tv#f!$!{XzY9vIl=%f%>D8;VB0l#$v9%UV}C{`Di zhcO(U=H2Ow;zjtDvtpJt-jK-Te3KdBnejxaix zeIn3vMSEX;JLx^&QlB?yVnF&Mu7P&;55qicQm)PsXN_P*x=Fi!YX5)x>BdjRCmxIf zT^s6m?5FE(GnIK+?W!;6{~rmq6Cm(SSFQ05GFQaD^NuS2O;-*1KV3CbFMUEi1rE}G zYw&oIivQD9E2}4T_2`1pl<;wF^w0``Vke5m9KV9_Y zdUDJm7AQnOwE5nk;BVKh<+k&$vks#OUJzT~#uiGnh(9kC_WMv(yFVL8?_j6yf-R_j zLqoKrf6?Oe9o~y}Z%-0KCf=PRri*r@!_|?Gz)n$LNA9LMGRi5)&qrkN?JfbCdnfT{=NkG^=5( z7v1`a#zafdH(7qqhLGPCTvZB3WQOU&(UuN9;P z$l`khf7<uY*wdtCX`>2uMVzKOf8mo>zb!}0kv$n`9 zGQ{-gjJ-f~>q^Uu{?nJ-b!)Y*K26ba^>pKTHR^3Wwr5>WwAKIhcnNtzOW7?NXQ8-x z4}hXV$4~0b<-C?VR(bX(I+V*Sy4^;Q*wjehp9~Vc%k#|^vk3m!AIOxGOYu6AvuYBA zzHo?kQ^N<1^y~Q8>EBVm`6)CnwrI1I?xoPZhy|9R*e4`hmu^j-ci7*VX@Y>UFhkhe z)9P3US9bc#I&{j_{w~Nk?C*iCH@>nZcka1&!~-cYlm{R9yKXo;yX(9@b^*Q-L6>;6 z1VnjLlkljmERfP5qL~+iTVkfuP_y;3yqJJV10u!(5nJTh3cZeDDjpJyIn zMZ2(~mGj)v|Bd-|v5L3R<*)1iTJQVndi?xAG_nt;ylvVsKu{7LfMs#aqw}`8BVjz; zfPSfan_BSa0HNI{md+$%@YZ0(>`)m3R)(0jIqDu0lN=Bi@{q|v1xB2iS;ZTCl-*+O zAo+75aS*jVREJX5gx`xm77tyYjCUgv|)D?ZjXgT08~-kJVaNSG|r z=k%{tqz|9I)s}^4>`e7^_G-B?g_>g*XvtHJgRJav7th5IV83)I7ZEy!N&y}0Q?Xxm{k3QM$RQ4>>0YKc0Kf;3NM({{6kzE8A-r?62Rq`N#8 zpKcL)^OIRYwDcWpR)tlnjS9;y=h%K?h~g75vz^~c?vi6yFJPYW4)@HMd}Y&-AFX}K zZVV|g|A99LXuonzvWzw?0B}(TGYB{;&+7mp!0Bqf7*%z3_t-gxfOUNSDmHIrqn-9n zB9Styza7uqI@(ZYGp71>G)Qmqe1%;kl5@hVZEGgGhEY^W z*1lYpG}0j!7vD_7H)H;RTlImv0&0_YWuv>VCbK(J4=#!sDYD5{Ax&195zG~2%q?^i zbyF8rI`%y({tqzwKR}7vzFHCJzo`W~0zdZEer&6~nK&i<;Um4PmT*}T;e(QmQYI>& z6~B!!wI74Qz>Z2DWH`7)fYModpDf*GmSCrdIwN9cdHvVtS~f4{@FYs-l7*(tOnNEJ z^*qg)V-MpTFYRm0$4Cx^C%7^WE~3)K`~<7-Q94_No7~$*)uH}!Jhb%Il~IRDW`X7& zV?QeIqHS=^&Muq^V&ptPQDq$8hCSYLjMu|Bok1T|hOCU$Ma@jK->N=|My*J02!Du5 z98dgO<|-xWk&kJP*YJ}Waa4H7rtc!%1VYdzmzHO)Sa@?|0;@<(W3S`~b(sNcxH%xc9t>pzwWA>(Qn3hi( z!nqYzQ+&lY=(jiMBb{%Nw0@nh;xWZO!i^ZR8a>KW+Qq~$kA&pp3cJX^XPI|#d6x(; zjpR6CgN=sX70n7dblHL(`yEjMK$mHYLU*YLrk@LL`A=a7;H;_SnSYMBp&?jxN<_lFHPQ$Cp`Oe|&;0oEc8r=Q+-DRs!Rkdg48)obUpytAddAVyCOgTu2!F2RQV>^f`NOx$Lts6gJAVbV z7_E6SP|5cpM}rKH&MzH)vQwB3caMLi#9Y&^{7m`bIL_ar8Kaq8fppM$MI6$4tUz9l zUkUTTX2*lp4J}ekvj~t*kGdMowP-oQ9zE^AGMuJAkK*JfjD@ul+`-@7O&N;Io8+aG!opZE)p( ziCDtC=5MvHm@Ilg8SirIgueQ5vg->wt_qn68{T)d)wPw$?O`K!4jHHdRG)-gr$B~` z)h6Acn2(Kgd(;c>(BP77;fq`GE&#s1EMFS8O<5w+Ks2v+$zs_2NzY(^9~-gAfOcPH zu<@sGvACJ^37eOXCb#Le-}=*nrDMf(t=)uV%2ZrLeGM)G35g*UTeOH6$!;cMTu4lr zK_4i*wp|f1x3Z~1L@^1*JkdC47xp&s+&bZBzd_G2n-S~~q$7)>+jOs^Mw4N)*tS#3 zLX?=pka5&2w)Qr6#tV_$KzmpK63jX*>Utp{OPcvL5p5$A-c>X(6r<6O-ZSVTJ-L1A z;T}%#VC8AsBWa>XSCOysS`}>!Z)S9hPhZjBW0YW6<$^Jqrs@Z{?Bmk`+KwkOZSF^W zWkiL?uoihg;8${?z#_cxnvZK}=K!x3W`Bfjj}yk468z~1JYhvHGCu%*rce7xUW5 ze5-MP4jI*6Rk{4!(66h*_||0a8P3=)iDT#@Z%8RNs_+Bb5&D^bT;b~`jm+jh$z7WL zfp$qmxVM|tV1)~6wr|0ypMz7&iP&h^_GwVUHfY}2M5it?7@DH6>7cMlxf#~_MWlvN z&5tc`R&7hOy>6MqO7L=>%>*XKp+M46qnxki#MpN45?wm?d-_x(GZ1V2ZKB0dg z$K_Z}UBUcuPw*Q?pgb%y&yYdb*dWW7T&b*}gAmD`%5x8>-81)I*{t15s=XBu055!O z{D3(OWRAQ1u6tMriS*>TXCQO2K5<$z*r(V}ILyWRH-n9+*^o<@- z+Ofu@HwSND?B18x0W-ztmn!4RFI{4V`oBkB*xM#kiO05ZAc8$!OrJ%!QCynJp_BdvC>!QmzjrS=GMz#jV;;MzcTlY2O#rG zx>*vnvwnT@g6{SpuB7GEt0(DL=ZAJcUG)9qqn0Imits0W=9!g^7dM|n3W%>G)VX&y zCr#!+70lOQFRW9j@LO?-4h3Y{Bc>Q8T=0v^0C}4a9NV+aq9y)y$oHMe^#KkiEvaYjBIt9Mou_+jN*|K7<@*J`H8V*cczWcTUef_k5NNs?Pe`c$;&bJmD>Z-beTKTAdTjv)?nCVQp0%onX zEgQs>A1i<5XhrTEpYH(@)uS2`#6&^^zFj=NxQDkl+H~DHd+sjnQH#(|9Qj6iBX)+P zbe3GlO1;Oa{X*C;z8<{#743I>-*3*MxV!Ugq%#%2RpfO4rPTO0dWifhCd^foZQHxXOJ6+- z>xDQKQ{eK>s@ZA zB4%x*JglX7DjIF1s4HZ%HHQW2-{QYg~Ak!C)LK%=*{Hw;sy) z3yA3%SJF#n&~6TW!A0>aBG;P6gX58aD}$ABY*vqA2%KS8?uN%9L8ymeCTulLF1JlM z6TA>h9BkUj?5B0vSo}JmbGc`@GrD*xrpQ)@?!X=bTTXNLdNl)|3#IWkTN{~F8I4q$ zBJDN|8n1F{6(9MNl&d+UPXgQGW+-!|C(q}7I_$dkZ+9aAo76k!W@PJn-}f>LJq0*g zEEqkL#OR!vwYc2DeAEqXTIOUpE(Y`T2YjTssKY^T(j zo>S2~6v#V_gA_;jiJl)9e;jLA9P3#fr=@WPB;p%YOQW~y!+u9c@N4|!ji8|YjY<=0 zk27kY#Lre;w!dY+EZJ6Hb5vi$ZLhxkYuf*lm0eyS@1;O9?@ExF6svx{0=aFb=rAiV zOAtt+l*{sH?i?Wq1TT9G-EPW1YPVg>H6CuCOoz@MN^k?!A1C2)1?{@&H4e>ooj*Dy ziE2vc0@IMr@==Rtg6CJh2iVMz%tQ!lo(|eSI42>C#kjnFVSM8Mt#U3v{eHo25}Wx6 zp*qyP`p;;iQTF-Ae-BGuf1Vp#A<|O5fr)exI9)74W$q+{5!#|6aV4 z?65EmCw$`B16Pn=5Io4&iO&<# z^WQpTnyw8+409gVTa3ONQ^pUHqk4Oeu>gcl8k>}`K||{|FR$X*A&RErw-708nKK6d zEJPHgZn=zKuQJ?NH&l(*?>?IO6DfV+OdlTdCsdM^PR#I!Q<;A6FlA0I%>oAO`4rM9 zIi%@TUH)Ap0q1YI}jm?{tVZt4rykf)jAkzTKoZ z8w3%hK2T7Zma3qlGv4#9kIXU%{ z{UmH7LigL2-EF9n$_U>0Qxm2dWiG`Mm-20tnO(wFx}>mKxK;U9x~wP_c%Vs?!=s*n zFx3Iok5fATL$h5=z6w=-LvsPu-HdhrilSI^NipG|zgVl0XcA8Z+N1lW$*hG}8*6Ue z4zV9PPV364x$x4`wXqvI&Vu!S`(|1HGMAY%ZRwPD^iAeL32u>+XkU)p^i?N@y48iT zBdug#qEK~o%Mni8{xqj1-Fa{H5@wY)N+H!cD8F3LvLEp> z?r$ZPD`Is_-JZjuuX1x3@DV16j9)n_sOt>H?~Gz2so=u~20I3iw+5Ys3o_MA<{R&k zRUKPbH=!>3IH}BOeHK0yjmrlh7=7dA+wWh6!v!c*`=HCcj5X|z5GgG2Pu*yt1;n@S zKK`CKC4yQpU!t{J)*4VR_aLP~BI|s*lN(YB&gjon>Caih+teK8qK?I_ib4|jLz6G| zn`~JL**CqfdXCy|h?M3fctHlPPaOlg(EV*}?s(gAvTlZqAvXZLuxhSsB~LQ~-JbM1 z>(}#uoV3gWOaYFjf~-t{se>kO(@y^?r2yY?|7yW{wDOqJtm)^|t(j97!AZ5#ub@b} zm5Hp+=%kV&)8{2PXVE?T_eeEo$fKHjulq zNixv9tZqntn z3Fx}nsQUSbdyvZDDj&)+*BM>3(T7bRz*QxQ%&ZE!1ITt-`e~U6NGRgo4;9F{8063T zb1^3-3A=O|BYPEi6en+OUr68oXJga>Q3k5q>wvmKUK#hkoNZss)jsQO+_dE473P$~ zmJRb3Hql~@l*D}(ati3L{ji=<*MaRrAcDs(9NPwv$>JV(mGrJFmz)neUu{)-=KuSyE~6?PT>;Xq<2`wn3p|yD+H+Tg|4hy0wNv8&n#VqQbjHB?O#H) z@|DZxI_x*WW=#z?Zt)L%0G@gpr$1!E~Q(jII zV_Pke8d$Y5W$NY7EE z+dzF#Lbfe=tu4&y1f-tp_U%~!|3nBdEwP6PaS&Yv`}lh}7Zr*2t)=+pK)Rq(nPQMF zfh}R$$A`20`E8Gn_Rtqv++pk*}kO$R9(6X^HYF zzsD$V%nH?W3DmOdbV%i%_IFQAKWImKhqR&YlRfNB7N;s+MB%w%yhR(&=_de9Q186W zWBws+GPONA(4U}I6B_mmt$_uvz@0z}43C1Jk2)u0upyZwM6aJ~sd(QTR<#J)gf4cX zp4@U3so1_OCO(~LxnMK<+X58l@1D5Fjww>TEdp0O42kkC*+ws;9!}$d6oaoHU`sjg zQ=gqkua@4M#Se!iGGH1O zFiqKtfS=z<{rBU>l}E4z!n6I1ft$4U6ET#yV!kj^vJL%gErZx1mNKTF!Q7d3;qIy8GG}E&lz_Wou%*gSyl0Xow5I>%bn^?{F&Eud}_*?258A{6Fyr0+nGFx)P zK1M?H+4A0#!1m~_j%)mO*yA7ZKEerFr4ZiY6_Poee;2VQcn^jk4}ZwU&exncw(#QWwAeYU4uJd^h8;d)9CwQt zs*YYQ;tN9jR5nyzRgpP@NOs^b5vqYw_LPUcRUzrUBWHll#R}N3i%88&+|pxlDY^)` z3!GIk5&kc!ab3*h_}M`3oV>^KMOCa@YytB^W#w_T@iM@2^(ErY3}z~&Qdqwfj49pk zW&Cc(YlHf(XKNy!e-xQMqBgA`%5tQ7AB`F*d`{&ld_;)aRD9g_N801DVzuar)4lFI zdGdCl=?NlIBj!;tySCY-HQ}JCrM-ee~?IP5ck|h5#LS&-W{R_@S4G#XF zk~6rLLD@zv0e>Z_pqe43kzu)z8&vp9auEj(d!R5bkvDkOF5-qV(^P{u*g7-MUY^Ph zh4d4x9ST)_J;QZ*2b=D4(!l^P4Wk{(9Iw<$5@-=e{r5{X|Ug%JvuTMxGw6;iC;7D(v0YA5zNKHB$7*Ma+sP0uBMj(E><#@Xi>D zzD?EqNO<9`QRZ;W%IO{Z-TbkUx*cZ<&?9K8%fbZHUHT?6@j}^$Cda(9%<^F_5+Igv zm+f{co!yhm3h4E2o|MS2>h@7{i_9ppgOi(xXhIPSJ7qx+x3g!&&R#b){UoPUVumMI z(C4UsXqm0==8!1YZEZJq(!fv2<3Z+0`?c8+Ix%niBDbb7#F!JD$dtJv=Kd$7Wb&KT z^AF0-<8-vI{m#IIIW}NpPR&ze$OmMmPPKK3iR!y(KO6|U_e)HUnO*oJHrsd!z8g{* zf5*S=Yoc6kgxr3bl-Okc4w?xFz}KH3S35pXZcUQtR zF-?83zgF1<+t!3(@pt?CO!JoO6!5==#R9oS>Xer2ngj*MaQ#QK#r_e%VdUyPz6my6 zAMM9RZr-WI0<6XUaHJ?R4+lY#KgQVmIK0j{c2|MI-T_LbY3={au81q*)xSP8Buyqgy3YQI9*zjG+mAB#7f%kJI(Rw1w`IopHav>}PY8}Qcb z1lK>nm;8aZMZNmtSao==|7+Yw0fx@_dL}x^s{3+{MRvF=lgIjW3-o{Q6kH5s_rV*9 zz6ClzOmr7AAbFZsU#!FC?7J-Xdt0q-29K9!t<>4kfGb*+TiOOuTCO=tHtJmhN zH~sA2DT=5BC-TzNRzHopPFTggqXyK0*?O`Rp4-p!z1;+&gR z>YSUzb2d{80zQtPlJ`PM`Rv*3wgp{BZ$Fnw@=s|?nI#t*NmNn(Y&*KV z<3=cRA{=(vBb6CWPu2dQ>+Jfz?APbA{x>%@5gM-Gx0RyzFk+=*g=>(|ScwMYek5j> zPVCeEKqPWfXxm2qo)hy$xV%>HSaj;r+g>ZfL@R;QFqi)FamRHn?>EczsqUTCBJK+Y zp&I$be}XpYg*J0N&iz%i>F2QmhRa46o*d- z=6nH=T>*5$LSuOzmL@{{DI($7D^{7TZohq^gB^B~)^V}&-tsT5rL!w*2Z&jzhq=Fo zbIg>XIb=U>{th!r70hbj&QF7`+b&?yUz!+92nS^0-4-o6#PLb}$u z^;jNkzTMUtCo#F_cyj0T^M!)le`?tH}-OSE}U9rjc z9e~!o4utoXsbd<z~ z6P<>4IR~wGy2?aUbUOBOQp$OCJJdgRes@YLmpaa1Kihk=&_%~5Y7fbk4~4s>WNAla zWs#QQyZjh943C+y6|f1(a#BdhW>Nn0xkyY#`LmRAR_c)4jgog>m)!q6Qp#6jki1>3 z+v!)`**RH#^gi{;vxU4Nqq5BRJ8=Zw9wHxAcly1glCeNQL%KOts3wsChz+pOnDm8<+Kiu!}I@er_`&s<@)P6xoG|YQ0+JmZ=~n zq40}SuuRO&Ok8#XZq}~!MSvh@l^S$TMF0EDnBZ(V{4b+35gc<~x?;&i|0bqi49i=XnAKOHL)|JW@>$S$k2mzA&!-D%zm{FiR~C&VKDLu*$-IEs+Z=6W+sNO+qfl)syQx zs`~?y5f!8cfQ~fEgdofTPWxU*5vH>|@iQK5KI zI9cz*d1XZ6ZB>$tcvBBYM3LMGkzeDhFp%(6tHZ{$tUgUk zXum%(j=xuA{*15v-kLe@zjY(0Mwj2VeMnwDC&ZJ>J3z(@IC@At3?zN#6<-3wmB(Ra z*Hu~+U~#@f)J&;!fTyt%NyH)`?K>`KrSduII#0#Y9tw-8vL&>Mh%&!)W1xyj!uq|< z>~2lkf83De_N&OJMpo!_apA^&_imxeELw^i&*nWIJUbyAD_wY^S^NQ^0`XL%59kP#_33&F2?rk^r)RY^tLtc`UCzf83dP%|Fg{roSSyqT|&4f*yKN08$P zev=BmVz{#pt$RLVAcixc0b=@{AC^>hBxOA*1OI10k+kBdrVvj$?#?L5K&REPkK1TpAKwErJ#ja`|jBYR4{hO+qa}#cY$NE?8c5dbd zd|y0Ab@xzuOcE|{HH0qqfXpD7a2+sAyj=lRwDOC;D7nl4MXe(TrYq`x#hj7MJzlM; zk|LT1dxT?WQws#I@b>-E`NI+FnvmSTtcHaHyI1D+Oy@3tJeMwVwzn4B#+5`SW%eDV z@i}Y5M_5do`j5|G%2eju5Ew6Yz-c4 zx^IP)k3RSuJ+Ig zj)}kc=Zss7bYVN_5Cb~=chl9lIrqy(WUA@w7rO&ZC30cNEoT8<0~GVC+=fj{)7X zkCRfwe~~0SGJsZS1gR>DdwtRWmv`uRIuALn%Ce&0S4e}>j6HC|Mt8d{HYJbxF6OhD z|4iMaGkM|48lJZP&5gGBUIED{hWx>`cw`B5dqxCLI)0sV+$rz_C?D`uPV{?3ldY0B z{pEnyPpuJ8#j4yl{<|Nt7%!YyMW;^z{nk)b4)*^cMtx!+XEf|z4)Xs{*wK<(5a8JK zy1}nJ@tEWzvY$r$=ha20In1{K9Uv5ItR+ZY@4h` zy+lT(KK~C}cL5Vu)GZ9VNTGO(7B3WccXy|_yBBwd;#Si z>3i?@f0CQ5Oip%YjwB~*a?W1+S-7fY&bdrp&3~+RHair~PpzD~FN~b+IgrlgrExZq zh$1Xcn*0|9g)oMbm;cT~kT_*6drF$&;A{I*JMXmi@5OQdeqtkLeP@4!pEG9z80jv=Kx~6nnfAPp%)BN$ z{kF{d#>`X!ttZ4bJImpJ*H&q7=j!zH<&xs;i(9h3mBx+6{cJOPp2WFyg_Z&YRM2BM z#MNlOI-7xN_%?-*#o?%1`l(e*bW9XqUcS7=uPA38QyCps1HL$B&ygWgr&Y-+EYNj$8hD4 z$_YisnMBVn46iNx{!ds2N}u};-QqL)aj8O<$^Tl#v`jC^Tl~9mn!)5=JKoS`^yGAk>&MW9Ko~ar6ubYh-VJED+W}j4s>>8{1%>bsGcNET}PEG zTC`5@&3W2-ZA#@cn|p2IqFSEqe?7+zdI$0t>nxkv1eVkW0nZ#~sG555g@ZtM+z0qR zYcD%U^bPOxL}+eIbXSZMmbdH#D(#)b?O7tj&~Oh97>5u-il9{9*>;;02b3;LFQt2c zC|9>l_;4(SYvT8Scgv0qp5*QXv=F7nD^%%=Tn^`p!RSG6H(a#x)Qep6m(+4m7q1Hn z+kxA^RE!X%Br{)Xn>cahv)p%Z1F&Y_uJq3H&G{HVL8)yz0!?j%Yl8xa@Fn6dK{=6j z56-)&!f`19`fhooc=;>BLD*VvT@bFf3&$d2S}+#XNvDF;2Q53=xZeGa0G~qlPJD@& zIy{ERg~nARz0Vc@xWPIi1Y`l-Dl+cR8at z$n>ha;QmIh;ffdjhS|S@N&_3Sq0GWdP5?&w5|HPR1WbSbC>JOO{{GdQ^OKjjpHqze zRb^j?-odoo^P#^q9%X5}42Dl;-Zou*E0k5T140{0jqG_7VU*?>^&wGNW?? zwb~S+8P&sW3BcruY2y|RbT7O^I6U%m`WDTM{U!ej4Ma2QH$Z`q(BpiLSRxdJGPNqy70?%cu>~SOr~lqTdPSBi zPbro3w^`^%YEW>h=z5-K(6>;O@=I!(DgB;5O6fPur_E#eft|UvZr8N@2B6jO)uRu5 zaJ8S`r!BY6-3aja#N?K}tJ_q*>~fpnY+h__@;|}S?wn6tAR|V?CYEh;r&wP|R6iLR zJ|1cRnK;{Zc`oa>Z|Ky%zgsuE&Okc$nxj;Hz z!B~vQo}^O>p3P9q%{%7koR7|$T=8&X-VUwfV+~y_1GAnEyjHO~1kpN&U#3{(8IA>q zE{E~4A1%v(~{==YF{9swTUxnqm9-Klk?1 zR(V^?gc;BpAgPS}4Y3DVVUns5-mHnd$l^zW%Wzb^_6q_<^7*|uvAGbSrl)6!*P=Q`T(2E$!n4DQ}F%rFBZSrgoB^cC8qFCG}BiS zbfd^|urUl^!r53f1XG5L?Sz*3ozEzr;ZcE9Slx<0JnkedR~}BC`5k^Xi?9U`nSmNb znKVR-$wr=VqZP0t#iZmCDGv*n3}v|uB{2Uc(NsoU%E{otq#%FAtlYcAIaD%zCTqwV zus~Do)os%dtarcfsTq>edyZ&jBHdXDbq`TSjzMdDL0G0DokMJN3fcU4h@jIhs_B?O z?2sThi0RO$>e#2s&ycsdXY<3?#ep45wl6f!!Nt|_qxO3y#dsv);QHFqTZ_+v)9!{w zLUq@){sDJSc6=qzN9rd{aw>aW-KfU()RbJ*VErJZ-z?P^r#L)qhAXJqsse3X>t1kh z!!Zos!z8$H%RV8?SbL>UEA8J6f6ilbkVtD*7PPiVX%G;z92UDOR}`S#(gP^i19)_h z9aSN|2=9IPY}An0ArlNN<`l>elRRaYZlxvE>4(84)6F4 z3|&t51U@s}dQRVT9b9%D5N-x%;IiV;`zu(jJYp@l75oG0406Rxh4G?<#bh}bD{e~c58+&+a zCB}tx#os~8E`OkZkHE)(E8GD3wi_uCB094#kL@t^{mYjTFPnlkhi>cQvz8|%!=wqC z{;yyA(lx1gQgX~TszOQzbjT09`+VgMfa2r)zpt^|0AbdSZVZ+{qry1iY(eZx+di*W+Bmb{yiQBC=uf(^|!oFDr=e%FL1=qMSQY+&;sqJ z-HZIE=j7hNYl!m8#^C0DyHM#BWsR8}$j2F9IOfRoEQfF|YX!WjS7Rnq2M`EaK7o+l z%~c(b+w#1&za9lJmLS^%g*0Jon5RfHuzwO4(lo{N?v0-DnN&Q>xKTWgrIL2+=E%hk z{5gd=Px2&pl>fT$`nX5Q==OAtr#i@-gtzsbzs1Oog>%GD>#_=X(8{~ae5i?rBF=3(&`Ve!rZkOUCo$S`UW2Q%V)*i#(g|}h8 zzrWl5F4N6@gFi$6qO2%RddxF{YHxj6(T#Fx?R_Oft;Rl&UZ(de7~8oq75g5^+C-`(%pN+dh=o##{O0qc!a76F7qYb#!K( zzfAA$GPI)aF&@>#8~Ez`QD#-kqP6AtyfKf>31C1>T>aDqtrO`pw3W9oG5EDbWlRUA z%-Pew4d5R?x7%APoM>V-3Ge8N2+VlR$B45=JLnC3Y7Rt)Ttw*;3pRSk4rOkniPJ+j z+<5Q}CeFt{GF#3scivGUI^NYJ&b!zlU7QNYc^;T}0-T(Kx*_R$R^yA0#}_vS&oA## zx_(Y%SfBY9w0E_E0aQl0Xm~NG2Af(m)*)kiC#XzZ`#*g>-z`E3Z*UD$iyy&?Vj6eZ z>YXS3?PN>q7;;0%mluy@`Q@+BoZ}~qEOPGF+2xi$z5e4(UMe#~ZxE2PHMrWveeEG^ z$x;iUEd1t6^fetaYTlAyEE_!42T%5&r}&aSFqzelB5zg8Gl!+qG3ow-_&&A==t7Sk zR981njmO(kEW%VlXfpc3$CPuJgvTi_5}gN zt7zDo9F?Z~mtrEF{$@%|hH&^~79nljPDr2S-YNtvmXR8m&{G;+o0C(BZl#hHch~&V(qTs{no<+*#&Er~n&cxxJfv zV+M4&2WA#nAqyz-f;+s@fYbLasdayY#p2I5OO&)O)_HxK1NQF*i)pmO!97WT5)};~ zwdStDz8uWmqtO?9R9s$T0uOH}{Ql=SoAyXh#xcuJ8@p*ZgP(vtjmO7P)TzyP8jzP zamGzds0Ry9tkXs(h`iaqeJyw0^@2O_YQs4{n5*L-INyuF&*+=Ri^oJ1wdTMdkW+l> z58b}Z`MMhW2YXZ;23D_gLnan(#Z97tLSV%BQ0ME|>bsakRGQI+=RYEr2TdQl)}&~% z$iEB~5X$KFGJA{IP-VPxFjkiHSTXz{<;QI)W{OHdy6uPBxB5o^h9$iFc1j*!_P~RB ziY#R;xv&E=fAo1|6`hQ)n`zEeGKwJOAGJL&JNQb#l^rF>J9<#RieSgII2zp>{Z~Wh}Uq8O}H_ixSqbR9Jui{*`63zT%dr}^mzRDvq z$x1Y41~Uxv;KW9L_-oZXNYmhBh|6A!tCe5@x4Q@f0vFKld$A>cEGkLAVaRI`nONU8 z7wVTW<-sybq!`aTpF6nlf5vj=&Wh62M3k18?)gI(?fJv#F#}2_lMb zB_V;zh_1gZ>ZNc4Mb|diT)Fss<~ec4e|x6|)mi%~2m;irGP~kSi&E^P zv~>cwUG+Zix8C6H`x|_=!~PtboT=@jv=J_)@bS;bt_;cYrPAiM`p~*3AA9ENHavo} zFiYP8Z$*AveQ#LJmD{x3vCcRXA&)X^v$Bn0r8jAo)$)7O&8(kc!xswJ;syZIa`wV< zHtw0?$(drTnKHP+&x(rfS=pq8IcN(RvC5-XM5R8bYmO~|+bc8cDrqCEK_gqlEDFMpCzYQbwXdB(w5mp_}Q`-b87TpeGnA%AYof_Ni=E)3vd}${7<&5ciNd znd5xjWyAlmkrv!8xvrop`ju=gMP9VYnznq{ZmEQH={=9|CqMO<}n-t4<7cqHb%}<;j?P?SHpuA`Hp(UP*amA-M za&w8DUG#$g;xEjV`eg`j8jeRY0~o@Mc?&>pzh=(_E{mH93sfJq-9tU!Dgt%j-uKg^nioEV9L19x zJKgyvo1Q$yldGf!69z}u3cJS6Jb^95k5tc=vqupA`ekJ$!`qlUzaIj7&o`zAZ!7Wx zfL%y-{s5nG$iqy!T_irQJwg(P>74QW7q#UWTY=VI8prBH?Em{{tFeOP$eJe(>JkqG1Dh(FoCJM&rkutlq2I&}wFB$W?Yb|kz zl6KU`oSS??Uqkf#Nvb>-2+SyZK>c2pv&+3`F?=s&5#2RnHe~pdZWDHRi*)g?Hk2=A zd@mT8zrH`il5hg{UQ`ukV=i8Ft}9AB3@@rAh7Lq#iGT|j7t)`oYu}MM9XvJp`_K0* zH7riM>9q*5@}RQraK%!1EZ$k8Sz9N;^C5*mZkB$qK?-{aHj8{EtCeNSJ!DM#;4CA= zG2g%GyY5E#3RheL4LE%H)&^QG9Zoj03`{Jq6kj zw{2Wt_>F5lVuIOQG@ZSfck)jqU;HqWej5(@^uQH7ugH$Dv;4i!yK4Ak_NWtMbWXU! zSY2^Yw#fZX{lmO3t@mmVijk*tK?GMfHe8qpgR~zpT)D4_ge%eIWwvCC@NU^Av#wP> zW(yHkg%`V6+qAe4S;A!w;@@s=Ukvi?DRDe~S15RDMzZZ^1B(#+ahGVu*obSJH`_=U6$F0$Qa?pC}YhCqWRzaxUFe?2|E9(#Vkh5WTIx zkjkMNjes|UzXQRI&L;S|soze2N0wN;+_$Mvv+mg{R&PiYj<{%7e=pyrw(?lbuT4nN zw6;$M`LTJ@lO&(+m6k-0y@lF&O1xj96F&6&gyhTVtnC@0_w~y41KOw34UWm%WErj9 zj&Ha-KURkvugdff`(HV5+x&(K10Sk7CsuHJ>**1hV%f;PaN4@?)-HH4?06CrT2BU` z3XHX%G7A!uxW5!^O%q;e>&F9krN$_K+{eFxu-rnh|8(D}lzH?xpdRaiZax}o+BwMO z&r0CM17JAVF}LD5k{)QyV}=%-oKzics~w-A6P^?bt7qjH$NmVtd< z^TG!8FtGc1-6M83@a8PEki;K-O?yhhyZCy{Lkanmo$CvYj2o49Llr7ahDK%+bpSko zAp+7{?HaL$2Pq^!B!Qtr$lL;CxM%?5Y$Eca@VW+{i}q#j{r2UDo_3vSM=+HZ+^Nvvoz8$(ngarEq1_!Aq2eHZ zLpcStqV?3L_~8(2*0gu=H*Mmvyo|adHoW0ExEefPvU4!JrFHPFXl6!=APqH z52HCpiuYB-7RMB^2?e3<&yei<*d4R|F^sR9p02*)R1q()lguPV-~tW2twQ1+=wtFj z43_L4(a=vM4^SH*oDvT&R#$~#tE{I@HtM5Nc!+qB9P6EW%Jnn|Kof3DYJ)x<(?EZ- znhXqM=JA!4^>{o?h_zvlGyECu#Rl3?k{b3~7lhyZAS$-$-Klwgqz7-8Iwq&}PNr9# zl=|_UY(DNsE90o$bp&3yM@(-Rv~{v<=WiPNFAMK542a7Rl$FVsNh`1F9gw)ZHt;Xa zpUdCk*9?JF<7j%Nt>DCaM!gvXgshahF{e|mtfQk|Yy$y9&t8YjNW6^-pS-VECM;F^_BhZp5lWDUG+7tg>yAt5FHKz`C1r>FPpN^LI5-VE$##B&a^`DIo2!#YFU zdz-A4;|~fK+2D@K(TDC7_T5+ADd3M8>T1##CaJ(Iuy>?~tv*^@7f$sNQSqhK6t1+= z36IMo4bekee$)NH6~r~}sixCIH`acZ|74}2pf-15vE|i|I4~N#OJ(mh2DV)eLVg8KRqe^-;}V$|3e8E5Syvo2bULH;?O0U zvfDd#uD%Ay@VYz|+D&g@t;Liw>9(gaOgY^~~|#XnTDqUE;7Xzj=^k3iUNN6H8~l zjPYJZmLxbW?Imx8hqDB~GyS-cppT}&K4r7};|KqistVpTjQt24{P-hpbTb(&QPQtw zF=c#&;&FEM@Lhy*!p^E|A!-;g${}@jIQPcdx-sUSfg0Uzhg!#8#pO3*FwFfQpM65a zSttfk($U`sg!~$QDi$sw4$em+hJDhu58ZNVz@m zfACfKh{N@Bzt2Q2P%*vo>?Oxrn|5?Q2n_K0)AZP=SZvaX;k0{mpy{4ZUM&gz{F69q zQu5VYuZ6)(FKvclTsuA0VN5RDyrilz$zDgcsoLBit%r8pA<3d{jIPxJXR$IFplk;-Yo7^O1eb#@J!Wc#pjL4WWmJr)MIKlM z%5N~?o|^Xm_eZxj!xr`KAe*XI8|oq_>bhcdD@p{J*wk+Xicqbe9fQ5l$8hsER@g^V zjwt~8w09X?{i1}lO>^=#Q@i38ioMxOVh&(C-tIRIIO!`OklvAx8XmK*e>gSH(fDsx zm`FT}mV=mhgB0ya8Gsifik;$LQD-DD(ltTjtBtH3^? z5i77Z$+Y1m*aFZJ^pygA`=X4)N>HBIF;5+7TztlOy_`WL0*`X>$k?4_TQ;LVT3U~;O#Qf>yhCSvemE4BuT2r z0xDY8d1GM~`~JWdH-ZDS1|q}%wm&yW?}AxFE~jl@&(lasej8$)JJtIH!ivjak3*@T zYVjKCQXJTkWF4i30u$%++&!EMgT6PYp#-9pU%wDB-Ue|XTQ`?oeTheZm-x>W?rizz z3V&Q?W{ss1gO~hPPKrQBb?^xlvXPH?j9f|+7hFKQ59b;wjUAAbr(Nstp_!$v-n}gr zvuz*2wY1A$s`hQY5Ww;!J6`bGcrtEw6Mggm<;G%^Y#;d~K4-&tbTw4Da|!{#_BmFI z2fnJlsh@1AylxF64qezAzzm$xstucttICr8Ooj{zjtmW?VWnWbSsn~;;_w4ib;qxKxexutxp;Q9alifsj$RI4AhVHQVsZNFJCQdXoh6yTK6+fh#2|H zqu~*7S2wPwIy($j#Kkbt`XXL?Uyaq=Gw^Zo=q&ND;}p+x;apil9z(&IBE;l zS!&qu$(l4%O}19Wy13I*;v6HtKX;mB#Avw12jDg3l4BMNR{;9<_&I85vLhJ4uJva@ z-}{DCS7K6tqXn^WYD0hR*8EvzBgW~L0S&~ih=W8VBH%MYn%<65o(4zq$?K!|M8bad zy4(wlq^;0LBt6(M@#^>Rl?U72&3IlH>GnwGGw-&@JQYOVWZ|hRi3y_UO@5KPj(xST zOXbuHxzkp?Rawt{CX;6?kij$mKqkaD`0HQZc+(H44~s7}YQvoQN#4KuHa}a0ObUGC zC0HkY452HFt&1{>efFr1?8TzrY0++o%9r>W)6O?VV3yrYz2o@x+)vrtIQ|c2U==G% z7m*9Wulhl5Q=)Wm35nG<1iq0&DO}`Qx0zS#kLNz}N*=v@zNxBWXm8HMd_>H~diLZ! zuB{cBQ)Dzb`h?=zo^GEkJbJMmnhChJE8(IbM5C9+j<$L_ND5XIX4(Y%G`F{IHR&EV zn1vKJ`9~#Hyvyv+b|?z#2-#LozhIa)HFd>}R_%E4MdP|hV{>x#+iXFUlm6-Xq?WMn zy^K$VI|uZMke33_Nb}?!`Q2@0x5|DMtT>KVdQSJS5#1#0Gr^rG&XhVtz7G6(rn zOCGZ@WnJa2Cs=k+{5X;~2@oh+n=0U3v#V2^%HdpN4s0>}x+rHDZM%G;Kkl%vd&jld z=&66=?!pMQXxD5QZHbnu)!=ZgF@5_Y=^~wBob6GSzP#g(?xU-|{6BAaxaG#GJuSK2 ziH>}AK1=BpR*N%kNsS@JR?@D8q_f&pR^jheqv4`An)Bt1^2H^^a99s&UbVY`j-FQ| z!R3wacWr(F!R=8Wd;$CuFSa)xm}6^n>7N)p>V+>*a^fY|cA3JpMZ5lQ=%_>Y@8;nD z@`mC5+Z#@LQ;B=xsC`kCJ>c>TU|7V~nZ{i*3r zDp#e>pkz?OwSSyQg>wgb#>;_kEqr(>Cf4)O&GPMD85lQQzpP>!@pIJ)hdcwp-<9i? z4p{HA|AK`liR)hf!NQ;~o_FF(^5`G`D4ZuYn=psWw5P*##{GkZ=iXpp9wS^UMe|&_ zTFyl)jopAspBnEL03`%io$oAbG{EP|={axnTDDG@oR65nzYXZKvLQz+ehO3pJx=rJ zHcrhXF~+5FI5lf&fL5HFFPxiqC3&)*2WL(#<1D$IIDFr%VDh-T3B#IR;7qheoF<1$ zb74>s&YL$3c52?~-M4L&e&mLm@q>3L zSpZo=IxcF3?>up#L0Pv(jSb9iKPx0;?{1kJcZoI*2FY%BrdRB>)(j4xw;F0KU|ID% z%b;I8Eo)t~RxwQ zZ+#TKJndNS#;^EYcRU!{ZeyAUQddn;vOiyu_DXJ3!Xphwm(}( z+!gsNS)FM{H2Zri*8GEow>#5R-uHMkzQMwm-r3c8_+?}Q#mn{<@q0oR+v$If-eBRY z=VakaX~1l<(BVL|VtJ8kXecRNg%xdCsLmTK{8x9&7QPCK!D%c_~uUypJerCT|uZvr!(&8 z=KqF;eW>4HVaiAI=Kq3)&6DG7J>u5W2B8`eoRGw3zpIPpzj^LYYOJNX3ko}YY3%?7 z1J-~v_*N6jGx+wn-KmvS+MIIRzrYvSZ+SLBBe37~Cd94H{l(s>IR`T~qi(G--gDm> zk8X^}PP>!3jeoFkwx#~T8!Q|gnRhmnanMKZ7#1H*PfAI>Uvgd=W!r2(?@SYE{tp&z z#G?FaW%(=dFYjEw-r$rqj@r^$_v;%h9OYL{i=k(K!W*ZbRGVTO{M^3Jwso36lQ**L z65OxneAY{hq8TfBEgmHP;5 z7JGw*;a%TnN21~xo(T?xE0d1C!NTSLfrWnx`IjHF|Lv}aA8lcJgN3WkTc;Vg=ZQop z1BVVejGum;b0_B*IaT^5-JbVUm(fr=rUb(MkFfAtdmEmGyMsq9c#j|zmN!@!X{E)) z*wpt879M9cC|Q61U$AhfY-Q^kEc^-;S0$GmZLD!4ov3xRMqqcL07Ma&Xb+6HgcJ6sR#pEm&4DB;=`;cdVlV{I-wP+Zh6G)mYz4lza zdbFj*?1)z^o}@&basN!V-`Oj9K&hh;g4Z|=h*))6M%*y^9nf5y-1`N2pe-uXJI==O|NcZO!M=ZClWPCtz|z>=0tK>XK!DBiEtNLk`e?QmNPy|{te=I zIoHfdykRs7yZb%uhI%`l%&+Dcv1w=z4KnI9(+PCx#1+R}^59O^BLzHN>$Wtc&ehc( z@EkS!t-rXic3nk;R$YU$_v~PrJkAe_NyCL~oZE>0>^<%ZrC`Bn=*bJ@KX9YWnsyQ) zT|k9C%yC(QODMwXHq*BrdYJVlHgq6iWBw{_%-eTi$o}5mMukgS>ZjvP{zH3!!fk(5 zzt`f+7ulB=*|+?$1Es!uPQHdxpZ_PqAj)qABGDK5*qg!)7x^ih!p{E*+U~%l-rlT% z<(}GfRMF~#@3ed3x1T8cCeleTzC>B=Yqq4{yRb>D46ph=+{9v6?KLOgV-2t?t(O1c zTDQ+WYeu_kMsp>JlG&LR8od`27T>c%cWk(3|3<>x?DrK2>p8qX0zbWy1kUOi7vSRf zws%nJH)dP<{P3~ZjTKC`-`5PY(M{Q8Ay)dLX!RRQ)q(J=S#jLHNo>_vd6k9sa&j#d zF@7Ru`rFITwETuA{E<9f5aY;*6FQ0+XnDy_ucF#MGXIdbdkE_Rx|g)(z&8+8cdYcZ zIytV_xTY}5reeY6bq-waQmAt%JzfrVds4SDR4j?@GH@7aPSsw=zrmw;+KF&JX(=r_ zj?ZqL=)MOln%)>RUd0BeSya%*AX`WpE;L!R2*h0h8#z}+`ciIssNH&(JSlFfw7-UI~VMIZoy%%k0|_nRJx7|D; z9u9NU5Y_N@-9etL%a&}P%ssSEI;fu{WQfjM<>x#EF|n>4s`eb?LMF6kJ1=Pi$P3rX zoS+i?{yyIMZf(;vXUQ6O_}M~1M{`$XUK7_QiF70GG=@XY&JVt8sys%)Kt+Z7 zz&Vue*r$}KraT+WWBTvR+6F=8Bevyzp!q%L&H+%fc6zj_fqJ>#&XtQn{nvDauEW+} z_TxLvCa{XD8a{F$s=rza8E51Dvb=Ro)@6=akjV{i4gWGX^S_;RDnfO~gc^`sus{*N zzqG?+p=i3$g&Ktwq&rd^3)Dj%g<9lv-y z;yP@WS2|9={pJ;{ucdxReBck4t{gO=S80EKZKGhEsBE&k5Qgq3AR2+Ex{`h}Yigib zu9r0KvL38I?4VnKPKDlBVIZOzz6XgZfOKo zXzH>9l+yq=o3LV?ITsrtj~l4WlQ@=I2?jbIEw&n!=T7*aU;g;JQ^LD=4X=eP_fTd! z&oNEh^mZdo2&Qcou?#`R6-ClK(9@VXHPhkH_w*8up)5Vq>FlwI)F^&XRnx7>YfV5W zalQd{0?+tDkcPXl2C?rxIDLQlG5&|X7*ZUyAqSq2E_Ae_CW)!CZ98snnj zrA)vV!nnWuO1<5OG}WI0$WB&V>lDvhhN&11xa>wiN7(KwE7{KqP}v`=DBjE;+$f?L z#AYGhGB-w;o1a>go*v}|P<6@j0LOOf0^(eecxNJzy7Os6`=koeSJylEaCJQt#0hqa&F~*CzI7o=A_Z44apfVe#0Zq<}28`Z>7n% zf>|48%YwIgNSVsIC}+OR4op_V(;Cl7n!ntklTLgsSLrO7H%5W7i-}AjVZS$)S5(-L zaJ{>xp4I~mw(P6Q>@PavAQrYW2)4EICEjA+On^Pm% z=5lG=$#LCA*S<3jt8QiXnhu1gHeDaZqx4rWu%`XPqo>QEKXLMdetVg484?16_8Oeq zY8rcyb)9)VFmawtnB#LlZyIE9eei;Y%LKcZatmcrblDfVtTzAQTDAYTFKqGAJ(Ilc zoF{yj{Fxp0eIYo0kh?kj`LMHB17jYLWT&uq$CJvUR}pBqucQxLI-UwwP$ycs6%U^q zJXXSFNKx>|AFcy0A-CC!Vnx7&@t}^6tLouqHWq$c7$2AOeroRnEoj$mc6lreYPLt! z^obE6?7H^b>3kn66w^sezqMN~pIUig;R8sK1O~Y;^akCD#x=k1{o!N(HMSuYA5^fqj{TTK?Z zzU<;$p;#|Swl~!pAMc+uId>D{nH&*FspI1nP_=HSnz4?=4n^h)fm@b8pWPjm_|J|B zeVwDGhv0Yl2d}pP`~+z>bfiNa3=CBkYXhbD-E|DPeeg8qTTZ;X+!OV*)aP4l^Sj&y z+uqWz?c$}!$*{w^U#P#yIBL!-wO{!Ryt}fd)j%SVLxE^nXZN7?NEnh$TVXK zUqv_Isg&zQ#{9|ctk%ZEK2F(0$vA{Q+iJjn4p@UALzh z);ZiN+C|`bX_$7G=n|^?U2HNZi#$47qOJ5CRIg8;{&)7DT&Qg9OcPc&q8I^Dhxt03 zQrO~kI-|SBmq4rol!2HzyiTSFIa-^ZW=O`|RBF)|m!@{_&KH9C-911^dwj-a=rju^ zUG7Ut#N4IEUdA$MU96d^g2(e99tz=M&qe&+(6FVb9QM!Hkb1c+OzI8I$jx@Y-(C%Q z{B3VXL;Z=fpl>WG0FV3lZtqS+lC@Jt?gj|=-OjjfK0=P@-H*%o zv-?w@7*gNOcS69bi+JPJuWN`kGmkTQIvv(E(mMKZF9t7~kei2O7Mgr~WQWTt^h^rm z)dXXI|-v&B;Yfq9AwCjzWLQsci005JVg3&sXO_B`St%0yGK@*aFFtW_1|9 zEAM!hu;&UBMM|0-vlQXM)W{S61pS=@OzeHlV|e6ax;bSf<1CelLqhvOknFRmOa!*> zqq(~uSdPE)aF1=<6gs}D9=ZD(m;$~SPFkqT_1>N)4Y3;DLMtbLYv-p<#JJkRYE!uD zo9o~OdTtQ~>aF_&4}`ur5x0=E71aq2k@nQ-3F5tYQ=hPZ8Qr63&!2LVs>?2BpRpwl zX#YS}z=w#S*GqZNEt#&}=*IxOrpLa7BUnpx-7-7$FN|I;u<`c)?&bOzM#*PuWNTVIr@{}JMO~$0}59x>;gHr5!e{w$b#b3oZR>rRS)DednQ=i>QDUB z^|^(au~?P7DhD5^2LW}k=@!Vb zM|vze61Wv{b-S!N9lMi@vDr{+k1~7vp@Te-pgb&H8| zJfLyer(v2>xp8&ft>C>*V3%HskGt|HexNbP-@$uuw4cs(O_<&1q z0i%IWV33GJ3>^b0J>t*w<+sW@mDB5g1bW{#+4g0EmAA|j5k{1@3nzTxi1=msbG^VW zuK+fV_Xw1h1d{<*RSVBM(nwm&j3kb1dPQW zn5ECY8BmBzFd#4?pubI8u?_JNl-2xB4-DKGS;oQ|cfQ+q+C2@4U-+dxJZF)iCsplz zp_IDJ3#u9>m03|@7Jn+842uM{W_hL(lIed8+&7|pv0uuB4=nGo6FoFi8v3A_+AzIZ zgaP%cU`JwxCVANKw-dLS6^t_(mOxrDthAfw?#k{p?(LmPH>gac&nUZ5pPYC&eJ_7s z?w#EtDD&CB+KZ&6WAzHk-^~sXGhZc7Qe|%cignLEs~8Z@+r{L%{6ab?w_isZ@Qv1# zz*FMem#^T>>5Jm&n{AcR=K;^B5Ph{T_HR!uz;!{znvKU#bflA~CP^>Z3~+Y%X=x^5 zY}X5iaatF)$Z!>e!SX~(tHHeu;4&A5dy1Rns%3j=0LP2j?9?IO_kndbo|`l9c7#U> zQxX{Gj+uJ!QhE*d>RYizlP|`--742vL|tjj<%`}dk|QH?Mo+p)#+pN|kubr_jzYE zuAnWgCbqaHrRrpKT=9U>LH?H#Ra1#y{#`)s#m~ikO4e?&6B|NGn@r z7tQrfg312ZZ#1Aami&5=wOPFtebhqz*!hpbb(0~s@`U&YOFIgcX($r z4m@GMySS1xM-pi7U4Zv9X#fN-+f&g%>k)i77zQF-G}?-vuk?-v8j>A6mr zH&KZOwulxw{ug$S^ zU4X403a~A~P0k-hwjtONCfhW(*hF-Cgv%#F#~EO7h~4jo7- z03uX3CJD-0;O1y;?m;o zE`heVySuwP0ZMUqEAH;@g#y7{g1bv_4RCp$_x;`b$NkM@GLv)GW|P^IvwQaQr6J(; z)yd>U{G9G;8+(DCIMMWjKXuyFo$*((^>?ajMhhs{f_;LEEH0k_28oo4a*#-v-Dz)BU&ceh zk3lM4@2Ea{#TW*elb;Yzdspmu^Vgn_-f=z6Ca%}uQ_?}2ia@6&iN(vgNc;8{gqK25 zR1IUBv9Iz|?+Ypj`4Te~X!RTW`JG0{ zTW~zFOk7L0W{y_;&zD))HmE>yq~2En?H{~5uhLBjn%OX|O=8uAA}qIPO9WjD)S>kr z9!(2O^KPQMzKY#Rr`-D~vv==@Jwiq#AF(dbf-+uXHi?=0`LiA)$E!<(2CvEudgp%A zusjia-!F4tkodmL&$!U;s2(=XmotdX5?0m;0y>kDbLZMXi7}NU3d#tFY-G&ai)?YU zSh!B_8@Cp$!P<_>cJB@6oIgcg3V1l)@49Lwt0onCYL^_f4rY7PLT=O)eVMr+X)#D( zcf_gBin`Rtz2Xj#z*uyopc?X$I=^)|f5A&5M#z3G#%8VP=6F8Uef`); zSCdJ5o%o$6^UUf#l^v4z{)1rbn(O?TW(-7;AXVthV;5Zw69q43mE) zvG1XDkq(~EEkl#>0HB`}nN5g1q8yleRsLKwpLztoSr_ZBR&fT;o=^t>@$NbXe)Ih5 zlxNw~I7l~2ea2gOy&V8Ky2Go6jK^Oo>ift`_2b&z9}G6bl9|?T7`g1EWBpz~69aXj zk{wPFuGZ%B7GHx8;%Z?#U;LvZQ5(S4r9XDS(~y7?J`(&w&terJNFE04d4vQAr~B#q z7Yk3RCP)h%uIX+8lVrAKYxldOv|*tnfbkK&^|$B9Tk&?@5)~c7Rmt4NA=)61rQnj` zABFpV+fl=<Hin_6OR7Y-p+Eha$klP0fQD%zjq0CA_PG^Y)V ztg?m`!$py%6+^8L+GxZK`-QxfT<9Lq)*D|uH?I3#r*B2fX405;z7UD*W+9|_)87!+ zd|=Y96Q8$Xmod+?DZB1@4*RXXpo`FYt-b`yN=ZxiHG9fkT~st=J6+EE=K6jTaQrz7 zUVYQ$d%VL`+NR}`?Y-NB5f{+-Ns-s8`mET{JX94eX6zoiSzlG{AS(QwOe)aR2WLqQP#GT;3wXtT&#vY(E-b0hrvokWg}vyI&Fx z=ybfR;O^r8yVF@XaYST4B-QBK8L*A5)_O;+v{KXMhIzsqzp)0&6roN#8uZjzafcJq zbUAa+9$Ip}9eN+$d~w+?^}l}QT-Xy# zL(kLH#Ea0Vf{B^3JBN9$3AWZn7hiO0pD@$pA(8!zWM=c5VOjI!jolsGx#sC_=+)CN zAwA6DXi~S3Atz5x)OW5~-2vtiZuf3&8J!+a0}X{H(ryhBOw>ou9&>;kh%NB;JQL_m zknq`;=Sgn7tGcS0{_?zmkN@xfD&*t9?KnyEYIoGcpr^W$ywcewhWmsIuPCK?<@eJG zW$_epX5I2h-ltiupkb|_+b)$`hXi+cP`8WIfC2rsQGzC~E5%qt{Vo#M?n8mO;~dU4 zAk+Qude?13%+ok8^Xr)P+hhVItAzt5(%32t6Iae{`?a}YuN>u4xc7j$#NQa=RtE_U;X#& zK~6Bd|GboQfQlO~=@qq9FaL$EP@V4ZG-z|t*lPo7?Jh3I-%@E>J+6g}^iI&85jvqD z_js+Z4CwN{UqQvwq)<-?lzF`M#58D3K%*lpJlGoil`(c+wAv$&9z&mB&nW9lO-Ngk z;5Lm;b!z%se-+$3j_lbgNks@9;YhvgFORl=eC5Rlj-DK;l@;(F7330yc zbB_Qa`gZO4fOK*%hx&3vZbaABqN=K8q8!Lx3kkze;IQb8T|o2at{{bpE<1;2*Dmqo z0eOMf5GB`fX!$j1fsmtHt*oiX#G1Uj;E8p+cUL{mUUOqqStHusLCr=e8nT;Sw_Nh0M#VFEz5He2O>W>I*oAaY_^EnwBQJfhO<@vBTkfe+^9GiBmrB42OGURfMXjDUj1gRb<3ge4wXi zYAObq2DQ~~3CgQ=sHj=|_l(1^lBOY3lR2nX(AkvIE2~1Jw4z2#jX;z4t7fj6nvPBN z#2|=<&p`brJ^jU%38kDVJjZ{UDrI8Y-+!yH`+YYf?70q3TQET#Dsi$l9L`Ic*Ckk^ z+f8@~ng3Qd_oUkGHm3*PETVicf@)rD+GTh+Q^?q#6RTig1ppo$ltZBHn2a(&Wp=`BZ4?{QFGJh$iyJPPoBRuvV6O^y(l{DJhxAO z$3n72X# zwqF+luLRAVXR}!97lO*JtcAZrVc|8i+;3#XiQCN+BcK)Ec-=^w#g4OvGSS*AZ@BB3 zp;ul4@qE8KH01cJyCuwJUow4Twlc?5DNPxdkEg-O15Fvxwit;;O+kG3fbf{bWQqPW z=Vc{kH+vi8L0jp9uFm;?6NTC;?mNH|Nc@OjOg;z`0oh24kS#RTm@nfHcE=Dbzm=3w z%b1uq+w=u-TYSxNd8@UlP!GBW#yMKTsjg*=vgQ4{jA^-y$=f7KRL_`ap*>k|8xgh1 z-Bei1SZu5f^SRU(Lk>mgJIEH<$yT}(ud9}^w~?{r-<+U%z!3Yag&Ke~)PD z_inPSb%YKyaWw6^*dQ0{S!oMUN0ZiWHwFDuEzvqSd9abO;=h^mx>gYc!fuI|;ie&3 zAct&Q*fd*K&+)Fx_Q!SzozR#C)bmGCJYq4k3sdY=OYzm@==x&DT`e!YB-weiy<~a& zi&vG?a|!TM_Qn0HOBMW0v^KO#iDZ^tG+WTkd^DTLFmAezy0}*k0Jv+%)pu;?7g&GZ z6LpUEyCZsCXlh#C(>IHiQd3&^Z{+b_Vx0;hbInqBAu8u+oXyMDs|C> z@+}o7RT0dYa-Gk=%Iy6=W|ostWj$uW#PSUIE)xMHoqN3=wSUOphc$F~2tuN=TyOPu zRo{p8)9PWh+dB*+Z6<2;pBYoTK}>7C(G|Lc+#s46y+_;FNdXC(kz1muVwNn!hX#qM zbdi|SI`%B##a$8JAMzzMFNq?*X9p>sqC54Cvr|1BqHQzd=%S!m$*0cW5ozt1v&oMT~qM9z6J}fHfLc^Swq$l8?D1=EHeW>|**;^F=exNz5@JTwRq1^@HqUu?m4-aj8j@AfQ zUm^0^vhW4wUT#zOL+^+3^gGouuEq8%qr2tSqAo8n>m|}62u7z3l9hWHY<`yXGN=qk z_AroO5Y&5AL~3TVgr75*<$_p7T0%85u5R*p_16uOv3eO~GOJVAj3*W%PJlirsmOttU4QeIgn0DV?4lPf`)m)xqm9q|?aowq?6>H_GNbX?mAGSzj|lY{pUl3+ z^)d|dYBRs31mvJZ90?kd@oW2K$NJ(OU0pV^AmdZ+3OwY6y^SKffi@8etia8_bJ0qH zhovS8yDTVQljyK|uy#%l;~4J~LURU+U7S;VR=s#HuXzl%UGA^?XLAjOj%09V;GGX? z;EiL%Sg!f@eTgQP^?aY4nQY|Se=00z=Y!k>4K%@mt^46-Dd&T^=N@O2 z-T0IMd7}2|zAM6ZCo(tDk`+UpT{NtfT6(C)8Os^?^F2y?o-^5^{Teq{VJ&U3v2yCh zaM6cDhh46q0g%l{)%6bd@r8vZTDfuH($1*8&9LMmc4mwc7?{|gHV(A1{pejKTf5#? z93^XMGdu)N1TQ6mYiZXU)315H1*qdPN zYn^nXZpXJ%14S9pvfto}xZue^MLFAC@Naqd@PVevf!4~uJ07BBc`4H|Ez>dI4vVcp zSBgB|0*2f!-~LX^nZq-bSFM8_!1sLybniU z?ARr2-;EQ&=Te@|CR#4B|Ec$)Le|mf8vE=djSu6<3a4?|_(vEaQD zj$u9GEA`z5w>QP>iD3NqUG`+7-VDL`Ypm)e^2J7P3d$JgPI0HRjLh{{LFW1xo}ul_ zDB=f6{^@&dzpn279H~&DPowwRCt-a_=51}Q-Jh|Fx_$ODQr4erC5){xvtim7viisL zp0dH#>lxdR_B&5FmS`X2_Mf6Zl=Fe+7&Eqw;vS>R1j+pl2=xZ$S>o|l#@9qq?Ou6T z)(ql=gwQ6G725|@x87Mfp!iE^!&D>8EXvP>r z+j*g)3W5wq#*m60GE^Mi&kWzc62O$z`)D%!dMiO?fGiIO2ZI;q8!C=v&7hTP4T`cTQL+G0jQ~*s z1}8R+_liNHu?ct4K5*i-A83r?T1aqeFK!SbI5c)lYCinRdPE33Ct`q$F~mqUiW7K! zSDh4K!8Brt?;jP(!RExrMmD?XzM0`;{^YdizFH5V#P{bk?HgDi#J4or2{Z|`#IL<@ zRiN)e3ujZp(63I!NN*P)Wv6Qx-eXyb}{6z~}vnAJ!Pz z7ai#VGU=lq`A|tq&XI&s9Tz7iCMPZ?;5xACJl+!E^KjUHhJP0yne&^?$oS;n#(Zb{ z)e!kbT+FHuEd5rS@jtaibp4xALhRaI?$Y`63;%+zgqVehR7Lb6gYiUrneo!JAF?$bTiwLSyB8xhGkdy2}0Ub4It+?IS{UTTKmmO(Gi@Nf9M zw_znO>rZNUN7gb(d84k#YXwJ0_{|q{`Gnx`4J;rJ7#chySt|WY<(GmxwQgX8c!Y$E zk5pl*6@qR?rz{bTpigx^seR-%fsz)oGVxjFA!DAmZ%NRoE)a->(NS8Qvxv*CP8?w1 zqsv&47&6VpIa!g0S&@L$1TxbG@iTuY24~i(VDt*iJtYJ~j+^GdU6vh6M0ymZLC0&gh z-w+cHJotlHmO>=KXjEZVM)89N@q0Sn0g`fv3BqM8NG{`zKU}MHjWDAZ^<CutMa~w1c-_-GLShj{32kOHi%2;A!AU|2<#a& z!ti1U29q^}idtn^zlB8wvN!zC$nsAp1`b-T;=`#<8p|_}2-dtM4GK1mK+ba?Jy%a6R;r~6TEOR$JG#poQ8!|G?=RJYK0%kBUY&zg+b6#P`jw#NISU3` zB<)96ugXs6*)(F>bWZ)QQ;?9_zHSb$MYc_LB8E`-E$ohcKMLwsI)bl5!r=x( z8k)D0_F@?Io^Kv)P+0v>Z*S!$mi5(_*?GFCY@?h1^2^rG-MCREeSaFu{}dDMrv|%r zImhWcv$v%v(6s6rlg1o({qOp$L`R2KRMl4le zdL-Q^feEVF2VJ7t0%)YlM3qOG7a@#&ws9BD*fS$9$rWn%1WjWtyFSlM%OUKVq)j8o zTJ$UPw&k~KpX@W;UGqU#{iJvRq%N1ccHtWYpP%tF4NSCRn7 z@RDv-!2JE=87P$5JRa1ZZ))&#fZ)KPu0i-%FsRS6UtNEy585HPWVBnyfB8lE65l~* zIrO#`jByGA5d)3_eSf~DTIl_9pip^;D_B!#&~5E*%cL}1mVbbW0hG|&#{f>QIEesT zrhqLbQpp$erxdKb#}tSesI#|vwq0PO-gf!CyIropM5HP6vM@>9ZtuNX#aB&$clySL zlGCWoAvJ#WW}9_Qynqt@C{A6baipDRcx){fa4j>aumRlI!$g+ruMng&*DizkKsu zuL=3yEcID)_v4G0-5ZN01f`SR?YWynOoM|oNnkXNJ4`wTO znnJ97=huwN`BC+I>AC{pyIg8D%g7tof}^A5_X`+T6WQ#Lm+T8uoLXg|_-^-d)oJc$ zj<&CjCs&`k+1nF;qRH(X)7g$9Y4Y_oau}M5v$fG!O!Ho7XltTqdi%IrZ z&f{W%ee8fOd{WZ|@e+sdPVQ%K67uD;HK9 z*UVu3Uq3CO7B1y0Qs#609xepmee^KZMv^#zqLCi}OjV$zhttj1IlsT?bG3he+3tug z54zjr?@G6fq}2RLVcMJGiz@aFm@+?t$WXbT$Mzx5yCLxG^P37?Y<0P1n0>RO(4`pA zc=XXUn`ym3N@HZ&_s{5Sy56*1BMo3wStFe=LY6t8{)33Z+8$zpG9WZScgy`6?TY{T zl~C}q^?~W^t4`d741+D>sLk7}vTL|oeWY^MoZ)8CV$nRpDVxy_*pzU+n5Xewm1E`^M1v1OoZ7=cL{6;FOoM$j`eNQY_1oIBm#Epk_Jzd33;|@f?4=i)jI4$3ghZs%N{@plV3ZqS^ z$}H#*L9foF*lX8BT#yUhVGCd#L^-%g=&Q<}ba|#YMdv)Grf&7cL`_8`FCEEAsmv~T z!RBxAjZczXkjK38DeXL_4$~F7KBxhvzRt+k1g{Gw(}qg9O59vpwWa7iF^hW*Tg zJvAGXUvdDNBJd@0eQr4@A;l%t|6w>RXAU4@d~i^l3W*>jJ$vuN!x5T#xv3F|&<%$` zZQ=0bw4E?^nH*~xJ7B4qMLs|0Y}Gw}N!hAvCoxHud%3UV%m2qc;w7*mU_NNp(}zv- z{Syn*l9s+)bG6O!sYTt_ml4X=RffMmKanX`ZS|}^#gbk!M#@i}A0J+n*QEZC@ZE*? zWrQ?4y6!MG3G^bnr8P5+wy{$WeTBj@XS8V1`zLW}MdgQjs}e;W3pzB5II(TI*$xb% zukQ#v*^shEj{uCIc(3ljz82zzJB)hA*X(l)(F&jlECrV$ATO7GC6&Fq<70|OR!MK~ zVw*FW<1wsX9Ic;Y)~>(FlLM=R1M8qeE&BkSAf0HZ^lVr2{$uP#y2nDusO59y{5nMLYG+ZRat*d39Lv_5_b|8S8Dg0 zyWlR3dJ=T*Tt1?!UpqaT7V_zAKVT-&f-oI`mGvOesw?<>WHEegrl71+r{9q+VM$a`f5_2U9({A(lBY zJgO>1<1*6QpK@x4b=i&5rKxqwB6V(l|gh3aUpvEgWaco@>0=D~Ev3ug86#`>LKs z(NCX;=Y24#UoCIiVz%ap799328Qp=PtxmJmeUk@_Fa0qvd2B+xe9#Zb&<{?&??WEq zK0m~%UXrW77&TF26m_?&15KW|@SZ;I-4PHu_wrDwwdQ#U#NrSRbmygiD>MGH$thtC zqI~6jsxA%Rq>v-&ecqRjjot+VZM?TaCo?*gpXzSfOjDM-+W&0f-09V?Ip_IO&Sl>u z(@+*Yt`u*p*ZoLcI*=bDU3{^Ls|;DEe&69KZ8j1p^PD~&c>FBj?OLEd8@KlIj6J$2 zuQ(f5@m-wDT9CSed^@#>FMa@?Sn~Kt;^=5_a4t?UDVoDq&-@3Kb+_y0`P8OsRwQ+j zz^7^bHeZU$b8^dV@vJ6N+MG-BAgvumUkbFlrXGQD&k53DmO~nhu zhzc;a-90ceh$FbeWN<9%$5I#rB8hP zgxLBYEZtB!Zi?-vB=5F{27}iZI@&1dVmGTo)TZ`l2)Bw6DB7oX33L^a`_-I>2(8;b z_{(NTl1eP5e)+YG(~wJYm`NTM+)_dY21Z*SY?7O((wN8aeUwV%pRVkpM;W>ywyL1< zcoVk(KP7%ze)u=_|Go4itiw?@IRb~K;jnqe|ZYQ;;w8Wk|T==bvR#~3P;qmr@s2a<> zpP;Hw_v?~$alY~V;hn5T!*NIASyoqELIa<26{6muhqO00pR;)a-H;FC7vSmKReiXj z){_&*T5 zz){fbkuPx^rPsrzn|?s2w^0bab4@8FQ+;{~C)RX7tm<4%@ApN(n$^j`qmr@=Lox1n z=zAf_o4#1jiK9nhCGU`Pz^vD;Z=6Y;Mu>%w>>id<)e#P18|b)ghI2J~Zj92Q4;5hF zy0^&fb9*ZIq*r0<_$AX?aUzB?@`vpSAFIzweKaWRM!GjJkNPl8?sG!?Hl;}74A!@X zjP?ROKeBI_W!yCi@}d2|Jtd9>Wf}_HNJ|BN7#Ma$^PefUf8Xlr^wQ;v^CDz2gsxt) zs__Hq2p(Kk`ic+bviZh<1e}+LUd{42GXxdl>3u8KR^=dhU`} zHPL^~(9wvAzm+naYP4K}?va%IOGXZigl0;H|AGH4QSut{P` z<4(hKdW>E!5k1dpTW?wNpu@vY;Fk$@DwVUZm9GEsN2Rd_Ie3d7W=WG|bLbicBHZqt zzv{ev$#y6xPPO!Qk$MHHx3Pws5+bNi8hkG^j@5=&4fK9zN0u5Wd>z4DcR*#TizP>N6H2je z>n}UI2tISsy@Ty`8uL85oEPAj=sK*ohb-Q0FIl%n5!q$&WB>-FjES4l{baD@3ix@a ztOvqO$>kV+-@A0o6kD=q^F_UVLl=i$#qz1zQAfojtHjO?yPWl^T(xs0!ADc8j^f%g zW=(vuHk@VoUM}t@okg{G1iRk#VDDYbd^?VjeUs|FGx3ZvU=fb{JrhwjPx0prgoc7| zym_X=;vqeWW-|tj=tXWD#^@;T_ipFzJfIKnh*k#lyZ(l39XAI=a55DBKJw*u&fCNl zGAymeZ_)^Vf@Bz8qc}Ut0eAZ@&W|X4%Ly1H!HT=JNllsx-ykEXLJ(9chPCgjgg4gCRwYav2 zQFH%XjW9E!xAC6rDp6~Swv;=JSqi%0k`UV*d}cv~Wa5o(SJOoH05nu4DUlYEfWT$V zlc9O4CcVXT{gZQjfjfN-Au~Q%-S4vnr@haoDG}vF#OOTDy*U*aNF z`_Ox!N-yhvKNI3fbb-(B&^ES~m)c>rX!dTxe9*y3Kaigm{$@F+MP-}(rg>sgSmq;G zBkr40jqHf`gG*OOhtR?mFSbBe;k?INH=)_`7pLYvDj%uphe2K@rUKjH%iKMrw=$O? z4KSaIDNwEDJhnPzyOP%!#8SZ*Wj?xqI;_brcu6FTXvjGCjoqY@KK4h=_Sfv<*HxZ|fgo!E zR1r40K;+Viqu;?if7_}~V?95mtsUtRa{;{)A_BVynCI^tv0o?j;4+RH1Vmq}_^+4V z6EmNqz0(4>YZqm`PI~_ZZLA2xsan&fAfyUgjC}}YlNPuJT~?5XFyGA}DJ{sFFpQk2`!uj||N^n{3pIUU+sY7}J8h@R+rdJRMmKJ)w!7c=p}OFnONz zr^>RL%_7Tu^5D3Ed#Sw%3{WTC5YlJ1LIG}E2<3ynh1NX?7niWqITq#1DUf7M3AcI- zaOs=+ZCQ`o5Lw%)#X5H6yR!gFtugnnldkmtH^gv9$5wuskMLy$`VpI4k%Li6wOp1^ z^?U6Quz-)YNM(kcL{qv>kkS-&mZhK*dI$Q4dq+e#{&|{Hk8ZoQpwm_L)CRd`8Gf<6 z{}t4Pg$&vR@L<=DrO9G6AvydYH^@81N(|!pa}7ji<#+oY!VeevW1Z`EB}dQ*4?~JE zdo1d8Hya6N1>GF36@`ESud%;RXdf1hwHF(Hf0XrfGK|=9(BJ;!GVze3aC+ni%+v>b z6dhv`4Z<$~OhC_K8R^#BqA0hs7&%kUBZM@TR@H3>7d6Vk}$OXmhP-W6V3^X@Fzs z+7179Q+Bl9m=PktuT$l?sg)$S+)~YR3w1krv(e+!9`#$CpI;{I@6POE_Ll^+tZ!4v z&23~KtgTTy~*ze!~-t2ICj6Q>9_DgV7S$?rLSa<_tJ6p)8{9+=c0-CjXf_H)gEKs z==ZZflxWGPHfMn^MrI(>jOq)_H?4dvq}DW@-hGMF#;>)isPmw{p_!oijeci}BMM#q zqSV1e)LSA6bT->xe>#;g;CH~oDAGxg)Ct)9P+lwS7gwMNiM}G4Ns%lWK`}D_u*HZS4@XoSjs%(Fz zOs)sB%K%Uc)gdhS)}=db)A27wzg?|v ziUz0LuPUt+h*L&txA~tNIlOQd4mEXV>s$0Dw!AtDT=7Phb%uEHb=8S#-hD{$Wk0-r zA_kvOQ` zwXBUYh`j^auPV;)tH;fqR@et#Toib-#ise!x~)(eMP!Ru^)&c=j;8dw> ztX%*o`vYNsa5V2kwQg(Wvs8QP*ec;)<5FnEt`N7{OGra)jptdT#ZRDF)q*J*^#WS4 zPbmDIWbBkPR_&G^Ewh*#e$Fp(2^fxFp}V$;+++f=1D`_H31p(M3i14eu9yHoLUU=m2rhhC~514-uU%0|%64;g*K*vyS`S6`gKAp5~BOQZQ z?{*r3TUkGWv};1Pqg9x%r%x>db7S+FB#QKH@}o9AikvIS8>dw8sx_RO3U=g=j&6In z#t68&r`$b(>2>R#>kMOMU>cAh;K#xaY3Xy>_>mge`bz!zRX*_*eP;`sO9OnL43fr> zWA5@cAKJ&s9^8!mBzM90iDJTfkn@#h<7)$NY)wY3^wnO8cdhb(?t8R%VQ>k7aEs*+ zCHqSX6i6zV2&bjBu(`LQ-n?DXx3jzo6I9!VJU#vb-{4^Pl-cpNChbwyD<73wlHMt@ ze&f^FdkSO>m}rJn zU;b$&hfOyKMczNVT?~j_uK$C;J=(Ft+jfx5iX##toP~_|cJqGg1!x_(CmN0YfWH>O zB8zl>;s$sjp(gB*-ti@8g8K*z9y4S?A?$jxTUEyiUJ-YpAR=V-v{Qcsl1))7dMHip z%f}X0Wb2&(Z;H4{HMspNM~?4ovWb0$fAIFzfUZsKTr)B>hgg{NrxZ;5E~X^ zLQp_mNbI_-d4N?$r9(TaPnL+xFO2RMz({@S)%aIyepe0G&2EAS!dfHNF6a)F2?+i%ETs~g3 z^h9a@F;)%%l_qN8lP7Nt76PmV)SR_hjel(tQ{)G~-XGeg=#@^|tC)~dFX=eKN^QG0?|RPa7-_|#lgSQ9RoSGMN?5s`I~Oy0 ztirOWt?|1fTJ>^TjkVf%ZqN0Fjp3!MBl@P-llVC0l5d1>$N@(|JXAMYSd79xe22Q@ zCc(qGYICf$e%`@1gJ7GCyA0@ypC1J5n&RtPxw{hgi}PrzF`+=78`aWLc!UWh>|6I89Q zHgXb+GnJfbc^s)}KUZ~hNKRW;W#t5R*iK*vvC+PnS=bwB3=lkcvtlg&eP7&wdNOzK z-OuwiRx#)g(F1JG53?YbIVltYz z*Sr-7Y}^r#mpX@EMa%&PQ=_xp+Y>2$x)Nb7{X5G7)P{?(Ny(exuH zK*ijd>$=q8mu~4@nk7) zBP#b^OIe5ZlxCOqS6H=CSvM=^giO#rmA>|=*mkjX>v<_)PktbK>*cHU(|9C;&WY6A z@J|JzG@H_KRC-rY5B*F+t2h0r^gtAy~C~b;|p+ zTckXja{r3jc{kZ=#j;f`!ODu$vUDKR%4+4%hx6=us>9=X$>V}|ZEQEYT0a@Ly16eR zDC0i=nDekGMw0X9H}=s*%VShbul5kA!q@NO0NApU;HT@O-M+VfHM7v&X{M|!Z-NFz zT9xB=N@z_9^9B`YPw#si+E)~I)4mRrFzsUraqT{xrcLwR{G(REpbeW3Qyyf?4G_c5~?yUuAC#G~jc zC6+^Ovf$=|S?={~V$WckKbg4#Y^i(_THnrx#(k#V4_eADs;WQpJ46xxczGuMU*>I3 zbPV5Iz3CUC=Wwl$pUizeV{6BmB8g$eDYk|vI9Y%+uzkO&C^>&jlBiANYWXL~C9Qb0 z4gKr`)}iDU5J5cUZaNemg^)hk|BC_`SF;nSA}X4v8)xiEiNj@Z3mDPfNZ z@thBaFc)L6Uwjks(`*$CLI62XC3Uow9B#5tUm}gO`-V*)h%E_j{zkq_N&ScX6DhOI~C!*Lf={(`VNQqDiq8@tTsXd5D{#7qNek_Ad6Ndo|ZL@!cT9cm_WOoeMbD)MIBGskYNRxN^gwn!! z#6(!rMVx;6xiY@~%dhXG@@9T~!uFWd{+-(*+Qik{RMlUQuZ0WgHcLD244fP$`$GAx z9ZMz-!ERi(;?$nDD6`*$4@(eO3_g$ir*C1C^raH>&J|qbWHmPr47n4`7x6A_BAS9f zrJ`7SN))dU+EVQ=GUtG~n#sB-nuR|2vMe{YV&$Y`|_> zQzX53YtW-pfo)>;w_jM`;P<;ls%e&0M4kpjt?c_BE zY5kNWn_;QnCX}w47flr{nrayP}}iT zcydL}Di(9>QlwH^zNL6bqlg+HI6EnBcYyMhS0)b-)ykP*T1p zRC^@JWOB?dRskYV99WX0(4-PzTYWRs5}7FMN-Rh|_tCfqY)Zit{Yk}PnRH3ekUGPm zrBVqCLhloK*Ap5J{t-aS5NdW*m6TGa^ZSE-s5dzy%ul0t)0PG}1VcBbem9U~gO@b4 zyVL?HeUDc0Wxfb5c7%~y3qoX&X|EaVkto46GLvs`%Mp1-Yp|9c?)Xa0yHFJjN}US2 zCi!6x_AQl1U0kG91Nn#o=6x~WFZY7PGT zrpJJDj^$)@6gI=<3YxlU!rCWBjD`z5DMXcksm5~-b-%kol@tOH-HZk5KyM#LHsMQO z<&ZXbPSI(l8TiD)_jS>g9C*8z{}lZrz57!Qd$c^9IK(IaS9(ts{!OPsO8O?f zcgklGh5_2w-lTVxJr)jO!w=7I(mRO=hQFWi-s(TnyGR4?=YOR4xo1m}H|c$kTisFj zKhk^L=G8P+)tmH=AuA$))DU_ip8BY4C*h6B%?w#>|3`Z7r*J35j(L;b9Y_C_-thtd zO7AyaWv~p}n{IZ&O;15xGt3Q(%oI2D7I;>{7$#+6BxifL_A6altMu7|`HEj+i^K6y zXD2ldw?kNFZ<8NvM9{wcLb>C}kN5lX)FjVAG);zbfbA&ZPik?WQR2Y-VM6uwxs355 z!C}W3rsb=XKv9N+(^hKO*$&?b{4`(mXTB>CM@r*AF@eOegnI)OeK0!+Nl?o)#PT|QD^qtl@;{s`Y_PPa9qThJdEa>L zx*-@3z`ifg?WOkiLh-Pgg~Vl|S%|zLOqfyIx`|&|?Z=2%1UOcTnc0Yths?*K?%*(s zm@I!`a*0Oxz`sd=*kAza9mkpZChQlbrqm9t>Ud^rDgv@6_@Ygf(3}q+Z{F$m?+66; ztUWpFR~m+IO_Jgp0a(&oL^i31!VVi;{c-ko)Rqr(z@;rczZx@P$<@b+$@P^XV<3Ph z%f9%KeaOxg{A1nLC*&a10XM&vE!$pd-Qpke_|epyXgyLVHVz-SNNDc<=Kqzi+8=Vf zPPE>v&#&9V2n_8N6r$*XNWGVQFL(=Dow~6lgDxaS00M7ko`1^ZB1wjk?k;o5i7?Pm zVMqosl35~WOH~P=O62ZduK9>WC;l}*-xaLri0KXV4Rx?e1h!QOA))C#>VF0c6|ToU zr<)lag<`w|`*xp2EKTD!zDe)n;UP_kXyno7Qu;%gcNel!qaiO-_CpyuKmb%}yS(U+ zI4N4nKhk@W{`Z7Utd~*$NL%`Ur1y{iNbfQKNbg>Do1*`b-r@h1-W?!!5_`%RZ_>NR z!q9)D_vVE&dC~tXz1MEQDN0e8uaze(?kq#GE`sQ*as0~ad)Nbk#U()*Tj>$!X(B)l?Od9l=%nWz_GVxaxV zy{!}P8eY82i9{3^@3N}Xu}p>zKzSwX-;E>{lJ1$~#L*>m9c(H`sEbui^mM9$;X|z^ zVqI&5B~&Yx?C2WLHNfR5-?uKd;#qb1ha{KsCE3{EnrCNL{F}dhA5YbuH0O9P1j)oQ zBl71?qlI%-4rKImgP^(^pg-sL2S5C@a&+A1cJA~G#_4f51FX+MM0n{fBOKWYpNJ$D z33>-~?P=FV5ncaBdI$a^y&pi{r1z!xf2DWWfS+|#F>KR+dlKKIcdCufaowO)YU;3S z_2|EE(tCznN8LZtJ8I~Eq<3bYdx^&|Pmb6BNbg6kFc?pdrfW1;s{Xn0<O(i6qy$zbu4jx2QoG7Q)k8)H=4c zs^hHtnfn_nT&qkuof)mutu^_pZunZ0Z`gF`*LSo$$rpyxTh+SW62@5XGJ_hIT&w2n zwzN+7ThzSY_;$z1wY_6pgIXPzllqY}gD!Q%jF+z5h zbb5AqaF*1CnX`20@zs8#boF~N3|p-VTMb-+qHZ_CwXT?eI>*C?RT4E7H~2uGD<;^* z=J08@<>N*naPfPVILSw9q+j=r(n(vzSmFmP0I=I7<%U7SlWgvrUMIh1>+%XFZJnfs zvhZx|LtxAJe02)u?Dh&mcOC#zoM_@9|JXT!`<9n|{&Aw8-$e57No7-0&P=hk&Rdr? zsnkQ>S;V7`PSv`eA4ZjIRoN_Y^S+mSq+FHTD~{+A$F1i=Fdm@9dj0yN$K&hlili{^ zy=Wjwp4qFz;UOWQTWr*wx#yhBTcX1`_Si6%elPJX<*VTJG;pIXW!uUPGyTEZf)=zv&B zV91xvPi>`J8-8psa2GCE&;{-&o=Z!*yV43X&|)ZW2V~UR4M77EGsl_5YII z9a>jW(!29WRvG)gTWZ>OlKvUiOWA)(?}>9Y^8ZNh@K%axA(ZsKyIOgMRdxY!JP}L{ z-**{X=mDXm_nrTe-rEr<>7BhLDE*7j{Aag=j+SN=GBA;$qbSi&fe#8 z;?|{uKC$HPl*f~v^%MK;GY1JVOjV_Cn(+1}DF*+H=FNxC58S;Jw@c~4^u@@YgLOup=C+#IC8@sh=euRn(cgZQG}I7c7`t7T7@xz#(SU*WNeyea zLMMmz2nr_S3@(~om(tq|uZD{oFBV)9Mi;n5(zk6pSo}ZMfr#vPL)Q#%uOJYkdyDev z%;qEQyQAg(0bP1~v)gTtNDubw-=XK(n6+v}dx>iaX76fP2NP7HHA1Z9#a69&0r{gWOlDM0$FC>WAXooobh|#4$GWj|dA!uKf z*w(zr%fWt;e5%_VJ!Fb7%HC-{4Oxb+F&+G>kN_HgPinI#R!^S4?Le3EY9#uS^Ek2n zjrhBFK1o?=so$8wDLNo&H7b&CFR+GNK4-rr7UJ=a{7>1ut|U+Deu|Lld-=f4Mf_y7MC^zIw9 z?AW({&cPL=O@n;(Bde~fFRY+zvdI+B>#nK(F6GeO5Amz6nI>}C0Rem>l7<#`bjRYf ztT=QRwPG94b;T;m{w0? zb3>aeM&AmTctv2RUZ)Q8Vp#MdjrFd5xfshTnyDHISwz>cF}P7^WNax=yKX%~d1qK^ z)p&hzv9O>NpW_|2E zCm&SPM7aO23Wl7C+stRyT!t}!8zimC>JXn2dgf1+&TiLI*(^@Wky6{8CCjM}NU7k? z_I3_+6h;f%UhLd-GM+jUXYTa-bKp{lP^=8SqjfI8J3lx7oF}wN2SM^SmPoHN-ppUb z%oz}1`EA&9e9fGajI`w3SxbDIZ|2_n#i!OZ#A|1hrAPK_35(n`8V^N08yL(@(QZpc z+l{*U->Qqhr4d|PoQwp@@AO-~^^+T&(7DG1Ok_a`0RX|!;2Nl{ZDWPz9DkqMCHdNB z`0bsOqMbnYMxVAT%E#QX#kugzoa zhsKN*0pBY`pU8X9XBWVqkD~n{t6A6Tk7oi+gU%czt*8MgbmY!6r>gO5h zvwl0Ii0>-BAQS2ezF2nll?R;)K8!bCh)^6_%rG@6DhM(a4h~cJYhJh-i(@D{DP7{P zNxOeMEFOOXPsGCTggu3w$jB{Y?c3wwt^GQ`jk%=0jF|~XGIz0_VIAT7Aw+aT5`!;e z0L*-3{%VBA!s6vTmgy7J+bVj(x?iEdw-mXhus2EIDGb86>UE)~PL`Dk!IAahtIZt+XSZq6A#jbr^XyUOyFg7Q#XMM{?t zHn*|jVNdaOc$iae&oTb-<^HzM^s0D4z1rtROWT{LMQVeg>z-{0auPo#vcUg7<(*%^ zY;2S<1=jd~nDTDATsf^lDp1;K+GA^stvceFEi2+P({2v~l^uxuq$``#3P1PM0++O& zX6=%!?u$4fEwp?Fi%#El=I*w3A1|BMdV@&78~B0o0Pyepj((Y5&kiSLdDdT@eYK4o8G8{X2u#E z1w}2$`PHS#Qb7V{QZl}=e@tVD?S3lhV;_<#+LqBJ>1Mt-Td7sr+G}odEe)Sdem%57 z;*4VfPXP?5w1LD-PHJwAB697ZPWW*@vjex4qGz|i_p)yl-iRxoUTiCyZ4EyGcP0^g z)U_v9*$rCGW6*#Q4UYjiC8EouEmDk zL7J6=@N`l9w<=ZM51e&a_e-DZ2=TO;(AN3fBIkp4mI@EQuRAIrnszz})!EXR{m83k zK9MlBMIz4Mw^vi#((E;M#O+HiMRiE}JqWe+L_q)er2Qds*kT9XYdxuYR?fEia^)re z*Qo6MSG5~D9gxe>$e5mpjj~7X7Bec-I44?&bqlTw*IUNlWPT|@-SxRon>*s*0q^A# zhG^-1azkYv7@!pDhkaFDeZ6^aHuuXwa{WAjK#wVGmxqJY8Ww z+}{pUl=+QsQ}a%mEt)I9hJ0!*UDYy@q(=%FD&G^#<)NSch}?4`M| zF1TP{EM-;WG(8Sc*f7}%-`sJsxHXvNuzsf31ja1ZAoIgWRD8HfC3rA?{wlb`v(+t0 zIY4%;lE)8jOyseAV7&~ig!nA#)pxIvxHWi*8y-%W3FeU>ez!9SZgG6`F|2G-w6Z6{ z@r~wDnSiM^y+TDzaf5#kxZzPlxU#WuT^x!79 zMz2xZp6;@B7iFouY}NFwb%vj%36*qW7?v-?ejFOUD=yt{`NwAY#?5|!28xn1RS_4Wm zt0o4Zb_PK|ZHU#)4T3TjLbPN0sRan>+-}C^EzD4!dMZqj1sSEBTfSm>1jBHfzd3Jc z_pqeEZFTjOHEg>lIsRkrxw>bliSphd$8)lFsECdEN}rRts})rCN2Ou!as^qN>qW~a zN3y+2Llh`F5E)sMTJjpmT%H=9z3}SY+|S_FU_PFYB#|3MtgM5wYB&z6p7&ONkpLF)9qEypvM4~hd`DQCn6t$xBA-Iy1vF9@S9kNl>c+s8G z*{scRd*Qe(;FKrp$4y8w6jSMNL{PPo>bG4~LQ753%QY%cX}G&bvJYJ^OL9$;f!g;~ z!JoS*75;%lPSdAuq|>a|CU2u~L;jxecJDTAPsKj!_dc^{kT zQ~O)(ZZ(%mH+h)c=tm|ZYGzQs?4D*>F8cO~QYH>ITza{d*_(>A|1QIWu+1*zZ2}*B z)1OZJ@z_kBh*=){7P&Nb{_F0~r(ZU5pm+b#C!RVsm*AwOCb4`~Dyw(JY+oz`JX7=3 z5<4sHap)|3Rp-e<^l;LqNINmv_cqsc)$COdsTS;oQnU!y1v`pHjlpPUVoKtKZ9C;6 z%~;_pLG0mJ=&I`g#}^tm+Fi`&{bJ<_MSbB-Z#D(kb2*L5cR}Aaa>&rkg87JaaB=*D z#oxDxeVmeKzSlYm)Vl08f##&oh{B{w(n(La20m;e64E$%D&-R|*6AB!ys z`_NK19opq^KjgR9Xo8QRk9s_)<7|uJ&CkAH*Ul9`wu}>_zBLm;6)rXh*95*#Ko5{~ z3$Pb(Nt=4#ddtu3dWY(S^WXhayJp3F?&&c{EJFgwZhuKLhWEhogBreob4xB1hV8GL zh%vXmKaX#H|H4;xx%+^Q@eCglsL;tqDRC>7#eXpe( zq$yxxyhKpLff@M8(s5mE&M_BMmZ=yQC%XV8%BQ;am=3jICw}ym{Sg3R@P2b}aEBI_ zpB>2xqI>A%+;!YK?P7}TjCmynR91*)PB4=~%Nr$F2hPL3m zFp#epJl?ZWgUX*Cex3;STN}Q?RB#f)I4S1InmT0MSH9E>rD6|IECKm<&)H+#t4uMZ zuu_fI+`fEv`~A857Wp-?S8j=^+aAfZl8lVB~?~DvqlR^nUGp@xgPU59`eXh{v|r$^sJfRrQZh4~FB! zv*%Te0@*VAltQwdR6+O)gVHM>e97L%TPTdb!9%-7<$kVGsUSkVUY}E4fARKdoOLen z*zI*Mw_Xl#5%VLrHg1w#@bdlQJBsw9TD)FSJHw0Y@ZYleyvg8}m73P8^an+{pX1$; z7)59pMMSngjXB42@W2pir+?WVlry39`Xk@FmtXu-*SU-WusJY7Q`>1d!gDtnMofj? z?VRIP^((DxFidRx96C>cJGaZ2@y2;&d@zzqNfqxWS$)s9YPz{B6pQ{l)=pt9{$alOTJ~Ol*?E_Is}Av&-eHGUTd}0DXNeMEU9Ervp39EgBacnEHscVr4PM zrF{nKg#f1}catXQk7zzE&Xk#`3 z{xd5}xk-ZK?<3krK^Z|#8SzS#KrA;jC@b?Zz{x;rGuwD7w!4=vFUb0Va_7DyEAN!5 z(D>|FedgHzzL}Bj_uOrbfD^2*&nc@zh+GJ{UcmP@1?obwlY(or)}~?Z2D<(QMNep) z8GYSl?M$=TT(M)gE%$<`FBhR5?nmav*iH47L;v+nss>kpmif^IY_C_`=s>w=w6oA~ z3EOV)SZA*`QhUGSxR-?Rxc-jW_l>XqN@$bff;td`15JWlb)2%D)7ul+(VeKe>_-;2 zz1?R&kwLq~$Sv>SyHO0TTihmD zQ3C75qct?~M*E(U+UeYKRjFVkx*6DJ-5 z7>Z}MGe+z6D#;JDGZK`AXhkV>o0@A4D<+R56mPitg5%-N9&kfZ-|u=m3|PsSQVdMS z2&=Xe=8WG}72m2@m7tZZvU({;ogAh3g$dl=eGmZzxw(+2OK0Nm)7z;W6O}e~!C)=( zrB0uFn#?8&L;TJIg9JtJ`FmE=FC)KzI2)Jc9sQojnKN+&VaRo(*e5o<+L;t#o}njdsZ9(kc+fFTWW4g%t%R2q&%8uPQzHvMswS^7Oa?h@N*P*{KAS(Zx;CBYW|zXH zc<(b0yZSjvITedb*1IGNZw0~xmk+xnKYSeabB6D*Ecw3_3X}^OX~~`wy=qZeW8m|% zK;`a$1>09?IEXfqPbapLuKipB!fUV`gnzM`<@lw=EFn3M&6%>E`j`Udmn3yRgGDmM zZE5T>Va4!`&CDO+g`qpeZi3@h&5D)1%c4{E z1I#<02FiP56!~DZRWap|v1XpCf4IY1&(R&W+D^jNt4tWVkceilZ;dPUXznX_`0b%i z6rf2Iu@}d#2~9KVkw=KL>`PcZh)T#8+=V`EHrM&ul;!;XLy@M)o0d~ja1WG?KKm0` z>Qni;{%?rR%M&=;$oasB^CEL*q{vrW%_%uq%p(4ma+T2^;K}b9v6tUgeoI>7s4m#u zr2Y2e-IB+%B@e7`Bll_tUi|IUpZJ9PFw7h)nSV=XgsVs$h1jbNlTaHWiTNsi7Zqc^ujwi8;Tow%@*Y`8x zhHYMvc8y;x(;H4-Kh;21(?Xi^g#|w^y$%j{$tu~>?|n#9jrKFl!=G(?nSV)EqExJR zh*b(2sbMMasT6Hc1kRtkU3^KsGzv6U@`{zBNnZON9={!6}{*f z7w6j+u$2oRX{*?G6nVG3?`GA5AX^H#RV%>w<}A4NpusCCjLn`M@RdMw$68B23 z%r;id{-?QB!wJ{6*&+9zB+1sOp;3=UWxz;ZFu7#K^%W`X^GXt#q|O!j(*jW(BXVEQ z>=bh?bL%z2Uta9zyGA3x4y`0`|U%?cI9TR}aQen;6{37gW z*N=Mgg|0G(Q+2MQT1=l@X?1sPeYyt=Vj+=pH%D~j(eseG{yj`@+vq_XH%ER_Kk`v- z2z=P8@_es>at<<)38%|!vc7BO+gXLT8fd4C&bbf1UmJCSw}k8Wtam^KJo88(P^O^&0EGsSJa0c{G16i(a=SncyY9wbR!lM zm~Oo|Rc`bj_iR0S9Y0EmEH!zAyUaj^tGi3iLFa{|He~jaauQxS(RL#?aM)J2<^4w+ zocIYEOeQXT{_VTMB5N}-1!5;?r>SkK#y(KN>r&4B$O^ptmySk8jaO(&Hrm);N*9A4UGuD7b}OBFux1HHit4(kh@VKdR&CN zaUq6HI3xER8xhsUT{*dkGP=oVH=WSDvXBF>nwH*4wJojw2`5_+TPSwQ#dOx^Omxxv z6)y=)5wcsS7U~(IItC1ZF89KT<=m&k+~e?8_0AC|q3jM$Fjv-nZ92QhBnh&LvNiW~ zfrFmdPIJZhCVdpRC^v{&(o)>v<>hUad-ZZ6pv*y-MzMKs?5zHd-@DD5i>$Neu7tcn z8$MIb)AufP(8BxvOm|+pnU+Yq(lhXi3njEgR(t^vaxU{hR;5f4kz z?-2Yz*?2_!=VJWTIg&mp#-J@%LAk)YVO(iNSD`~Z@mELUm|aSja`jhZ=n2b={9&p~ ze?u+bIm|tr)cJZ$0spB%TLkS9jU&T`jB}y===rG%9^;SQ5F`kwbQl+xQg_3pX)#F zYG|^~t^MP^$k=IPKe23SeARKd27yGhpT-~hWxX03fv;r(wLIo3UdfezRJ%89fp68U zw)s9Ne13>aq*d|AR|Wo=@$q@^mHS+Fd=(+8NZH$(&Ep9t^CY%}6HL@G>~-m>3IH9y zM>eeZQaXxoi$~1*P4NIWZ>*C=WElJt}#u3pL$(u-HtEI zR*?A2b~?r)7%(D5hf|2^k3?nHEm8Ip5&v9PVR+jF;8++5c+$V@f!NFymbkDOp}Ob0 zA3JH?dZ(kzs5tGO>z-ipW2gA)bfZg)EW$E%%XdF9#`a!rde?duC}@*unZ9Bx+!dPG z*~dK!_~EQNnp)?zUBshw=5!u;pue9Ns%`zyyG|sF&VYmiTG}&0{DmjL-F31e-Xew| zqjn#&rBAgCB6{?x_*cH|U#TYH{NliC)lRYK;g=FwK1`Ni?fK<5o*sJH*&7!p?$6AC zma)qx-~r36c9v2mX82iHn`LX(kA%9<`LNy6g306BVlyR7@Ml%nZNwrHX3ua_iC_zkpkx2sTr8 zEWgu*s8mKUYWJ6J{R*Qm(r$V8R15s%jj*a|8Dc6ih=QuYEbQllLuDX%Bt_b}H)tPZLkt&N((Df7Jjj@Ie~gJ%bs-=QYp`<@GbG5#nk6kPrk;kI z5%+6Yo@Db}PW*nWU`D`f^W!fC|0b#j{q1;hXmkJD5<)piY`IdRGHqhnX5ydWGXlih zGMq0Xt^{&^BHs6Ozr7@u%g2_3=7g%ZlNU_>n`r-pxOhDYUIKBw6p2tz3snDM`Go)o z>ij!8MU+%L=vBx|p-a&`&X@9QYtFD7VawC3Ouy%H;aGBy|BCgcCIo`-<9pu5ClLjz zn}n#FzAm7ZYjNOwX@K6LZVDQ+0ka@M(=n%46{**|6y_QU(xY zfJU0>FUzR;Ucj1wGux?2bNuaJMEw2Ss zhonx>@y&+rm{jbS6i3`T!QDey=g!V7^MRZyqD90FF{eG11+GkU+A}fy zI_gN>AS+I#KwVYzx{rCBkt07-%?Jy*l%hIN0{a`zNDoGf8liKtF%&F6)6M#1ilFZA z5t1XMwujUrgwAvQbwvYptpasP$DH1!J;Qpfofb?7;CeO6snoadc&vxjA{>Ru(-PJ3 zS{{;(ISHpdE3LcwWKj~Rd%1Y?VgShX>aA(Yb$S|ugg(c=BzT&!0NP;PIOj&AlDaGJ z_aua~z#bX5#(Qy^JI+75+csYaxj&3}p3CC*+S`s|EE49MUiXA=MCy5-H+)lE5k< zdL83jd3g3%2C=+RE91`2r1Vq`xtBseG}%6RXR?f9P{6bMoCjVao?*8o=*g z1H_B@Q3>s$nplVcHIdgON2U-2mYa1o3ezX@|3T0uqbf=@1z8AgMG5hus6B33#lM0! z1s1l0s+GzoHU~kv-i4q|s&4l3?}k5izoZWJv#ThhCN2&%)HD)%EyCra$ztpqVfYep zo(qZWFXebnYFrNOR~;g{_?UHLTC;m?dZrU2MqlGOal%qbG6Rmn%Vml&wBAHS8w%mJ z(Q2M>Ryu`Zpm=v*R(E3eBUFd5;gnGPk-#Zg=Ja2QUD*MJtGhHiWlBNJ_=A7huZip) z+AI?=S&Dyi+7aO2F0_pR$urxEf6!yG6mQ@U7Mm|xuwR`SDB|Vc2H1YE{r2H#f#9@R z1xlXziO09f_ND8$52y$V+YuDUUIL@&^?wwjf;(s%;b8mH>mMM#+1~bpnTG0M5%pt@ z%qQ_?8k3Hh0jPa1Fgt6Rdm5Nk)^1S&;6P4^NT#L^F#L^Qo)tONDPQB^+Qm_nKKo%LHTv z|DM-lu1Ju}>!mwP$!(PX*{{0j8ZZG zoJ5K13y4zjCS3bC{%A=oAz`p(jZVlN1Uh}lNnMoB+Hyn;#M~BASl?DifWf988TzPR zSlqI~WHv{53|Cjc5g0SzPG`{Q=^cMz4PQ8_)@d`bX;F2jcGO@Ga=a5b_le|14<5Sk zkq^?!h8z%r9BUMO`t`Ah)xx9?GQ(wPYszqDr3QIavKd z!_mWx%IX`d6dz%{+lWoI0!nLs9{Dk^IxKTJ(+4lKCTz=5y^pp8rLEVv&;3Q6D!{A0Bw9X?Z5nZ64ro{9@?Q{;GnpFfzDHc8U+KK$c1aK ze-rSMYCdRE9@vEbsA-jJ6mlN?=SL)YQ@87*e*dM;DM)Y+j@leRopnAfM{OsID0clf z%1?(J{ujI6Qy;Z(EnM=(7+sd6G^|Q{By3zChx8u--UT3IMS>d>B{K-1e>eJ~jF}Er z4y2=tj>?LQ>eG`mm6vNbx8F%jQl=O6(qc2Vt7ey@y{`)XJ z^yEb4yM_X^-koiP|A3;@tv#YJG$>r&WdD4XFBh68n7uYQ_;AFT-DH z`Fg^mys|r>-{}#$C{Nwo9u%83fQVnnF^|ozJNlSS<&Vi(55IlEnq{u`%k)?aL3yqt zV#}$B($b$L_Pv{<6sd7b>t8Z^u_&&*iL28?U(bk=$?JM|ME?b{n!uj* zbQApkM1D5yX$q*WAS3PRcG}ZUd@M%mzk>VL{%N9uuA|eibRj2(%;h6S$!E&6D4YFO zS;Q7pFOasy%ZWkdv7he7%z{XV5hTjQQU0c{4^w=%d7PZqH?aJdM@MP#IX81pG{Jgj zd4Y;9?b%Yq$G!Bn=!r6XT#5irMd!*66a^osNUfFjRCsqOUwEFK3uDlhgONGQCf3F@ zVWFQsubUo=Q3y+U)04BGesY)$C%=atHv+aJ?{B?!ErV2d&OMU`Q#+3M-`WBp_I&qq z!`J%n`?0!zLt?u6HT+ltkhg3(H~Ma;pKXlNMb>=%`UX~ZW7w=sPomj`aP@mcqzpq>JuY$tUdoUfmq8m;2j?Ris@@cg&7afLPXRxfw7cI4j8oV@=WP}Yk;XGh2;Xm6(C`z_T*gA4NQ!4;#CIo2lTu5BE{s?&VbD@ zm2#A@UK}7BH;A&=KgP($86kfnt6wa2{|^BW!zQ?d%&a{ofSMO#gwnRSdVREf6Aew@ zEjvk;{(Wb82U2y-Ajq7#+%rnzb#Lz{R{zF|N5b0kFDCvs?I(WJ9pX;`HsNDt!VOz0 z!pH1{;fH4N3#Rdm1E>fK{BGKuB&=xJl2kKXofe$!p2g4~)kA$bYG}}U2p#_M9aY%wc{k4K%x0;#fr@<*U=`do54X7FHB^f>?kDT| z1uawUsgj!hszCJNo=UOnU5GO;_5B?;#t^qAadxk!zT!)31hFv$dW}9w9JG$`p>6o3 z`IfEI_Yd$5;)b>@CRr?QKBrR(A=+UCn0Itj$*r1$9Dn6aX$-3Hi#n~GUGtoEvmq&$ zH>`w7+>8c2U5#@vx0f^ATMLv1bG5!VdAmk~>svesV!yesn(Zjj z`~0oX;&D`cF0gr_EtN{ukpFhQ3svfjlr~OTGV=RQS6<~^pE}4PvH_T7YPFvtjO`sH zkT3JHy#4aZQ6F&2)_+;s#ZdO9GvphOou_fvC~QM{F7)`kb?#-8>+-LTH+{=c(N(9uQP)n4p6w!f z&l_Xy9?3fgH{`2D+&*)@7hb-1Rj#A~Z^E)SICM5ShRYIC+S#tjrhL6uHVRbt(63{| zcNkvCOC?h&9$?8XCnL+2b@3YSl5o!U0$b1jDRCS3ZqOO+(4CyeZ#`7|3DNxWL)f{k zu-ty=82zU_jP=lVDDy!Mu*__%=ecE}YSK@duwB=Lfz8e^IF{m@041$#d(JXU*U)22 zvz-3ar}j)hAp2Q*{IEGE6$JLRx#5tD5-@E@>@lV^Z&qLFA8wTR703%^P=>K4dgu1zhArSjSLsShr7s%aCE43O0X_My{J9ln**au@*Me zt|V%%B*{g@!d{iZpK{bMFt)wd8k!i8BWw@mH~x_VDV=($&9|1`a29Z`Vh#LZ?LaD3dqFq&c^7`&~H5`ClTb353@A2~|<5s~_xu%{!LIY>llmXAI?=N;>OG zM43N@KOKJC+q-sAU7A*5hBW5gefDDhry}|#^z<^rbC+@+W;`m60~M)L!q__lRQgZ_ z`kQhj5G(v@e4C;SXQ2)JGjY?$X^Hk*d8~G1BGK!>5rjpBF)S|%q051)yZHoVSc;DG zluGDqpDOwkol~wx`x+=w3?}7Tx}?W>VUvmp(C66ji;CP9Uj^Fm@I64EJiM_r zTX(;Y)6qJ_9X4wf-J(n~X3&~&OKw`$H0mcf)to<@EH`d((}{9O(N>9S zZRd__L2COB%G&rl$oGl&@7Hxeg#nXWvvO0vi&LFcb!gWVT`nr^fU@Te$wc4uT+i4) z+d%>zRL;_$9x(;%;q>^b z0a#Anv3a~OTJf}H?HG))^snr$C$~8=*!LHFXC#4%S^>307s{&u3$*&$@%(~QH%TmH zSvq8xWMtj}{KN`6`L>)<-y8qo-5sj1RLikKMxNXFJ{h!i7~wfe!}=^dvHnU(BAr5Y z49=KLF?UxpfSvn`;xqD~Wvgw$`G`}n-OY5Q(1wYbW2)DNDI8%p*WG|m+cIW?$&Kc9 zM_+Tu#A_&_h?E|`8CI;!l|kF-Ryg3^Ge2Z1mFP#2?f~;?6b0{X{Ppxk(R5y|J@Amp zL}&(_@>wwOXV)xg#GG|cWq#pZL;FCih^z#*EbkTM?YkSt`VcC4LkV`_gTem6`HyL} zGwC?;O5z5Zmm8Y{p(2u0*jThh-hzbr-BsVaF-TWBSFQnd?F;~tLPx!n-7wdytfi_t zZ$-OQGQ4_)lG~OfF!tH%4+)yXJXac5qg-XeZtd9N^-jd-}w=KQ`uPAlhHJLgQ{nUft@g*+UM7^ld$Zh>p1J4bxmLRTHGI(ToHg z8$Lf_`BqOVj|=}LNIDN(w+r6_^c*im#Zz?-d%_mQP03Sz`mVX|Pp`uqMJi9}EFkw1 z8*~vmh_ELLwm-aOq_vy5EPXxSu-AyH2M5==?#gV=q21GJ+;57Gq7B0~OxM><<2Fn! zqqMvw^eTK5;{C?q(K->)GLsvFd@nJL_LrOjh6KHV{5q9V)mDH>5 zt_wMV)Rt?n-=Tq79VSm6Aar(m;d*T_xkO@>V~Q0H6ud|a>L<> z)&#A?4|97XGqcI85gLXhb+wg+t}YC02O}jVECufjt&cm&JN(ppI4Z0^?Q0)gQN~r? zm2@IGFmyS7#%#sJ6uLe9g4ll|g9CTGnr5{uI+kaD`rUZBPZ^8WuNh9(6t}NYlr{5c zI_~NiU3$5Dynr~6&n>ZJSHh2s;ltN8U|OYUv+K9?2N@L)TmLcM|6{!WFBtDxIuB}) zX1s?M1PhEofdI!71+~3&he_QAKq&x@X*r63g*@3C>#n+5O<|U;0j{a zDjO>>=z4z&KfqbYoA2FIDRJDI6bzo zU&>VCFA%n6E7pgX4Hb(l`m3pp10uHR&wLnI+=nbg0IL+WQ0&EH>~!7hDu7Gq7?`Ha zZAjI9Xg~zeBm%HdKMwnO&}Nb$EVk#Vg9UHcwI+Q1IL5lOs~Cs=^u=(1-uvy8BRAzh z+p|uuD%DYqIUfmP%z(%DeCGUla>?pD{I1L$Xg(apx<2`$RJSA0dDw~T$#}7=-c!Bz zmuvQG6E-2{6hj;2fo7=z&)2ICJi{8^E&i<7@AVq$%PJ1N7>dUXi25m6aTzC1>tMp( zbimMhtiPy|L_eNEvZo;I9F`F7Q%Q31V!oU99BE_drmJM5|31gKsC7WY^H}+ZC;Jye z_ly!7Vcn0#RO8`6)Z>?b;$*=G&)#zbea~2VJC7D=_g%IF_o$VKG(LShNU3sBYjU;J zZ#68_S6B}t@t%T?MOxl$F8V>+&%bd|>sw8gGvP7D^UtYCF^!7u12&hN>6Mw~5)Aj0 zxtN6*pWv#hJ)3gch#z>+44~KS>X8&w6z>(*j#UFJ1V9I%T2V4`bJSa6_O7yL4V=Qhl8K`65CL#399 zQG0>cllCMc*Y9ZubJRuW;fK!%o+4lOnaFr)|6pxsWu1kiKbvZ?K8uYK|nF^)UB4mY@ zmn}-wDVM1_^N6V3xzil7mRXTAB4VDVvp>gIoM-Oiaa$7f>~>{>7&VuSx$kIlmc)Ni zG--a0L-Lk7!%t1zkcQ4dW|L0NuL}DPU3iCTkJ{K*O?AirX~>^}5Wdf>L|AKf@PMXh z))vK-_9UFBiU$nVT!D+`>53}`=dFw;j`(9&7ctL8y1o7@KyV_9FJI=0vaw@b*ZBBs zid{=7@aBViV?|qErId4yXM0`Pzc20W7O<=`zH6MvZ>Ct(`lt)$9BbVh>cT;Fb9`O> zwLjE6Gffpfz-vRK(WIpe;pbXCiN-*k{nJ0iNaq;T1!(-m->7$`=F=*1YGpGA`rH&< z@mWkW_hh02%n$c1^RiC`cIiQ8IxPAF$a%fgh_%p_D?n#vyh6?(8$ldv+1{_pWpOdF zy(Ht78#}j3$34a3#4pBs+awZ)cVitcH1)3USd)um_H+Y4tuXuZ> zK0wzkEeX1Q>w7b`I3@sGoC%o<`Vg+KcS$XKa+&|i?ocyTzn6YDQ(F>2Tj=Pt0Hw5@ zr|$3KZ8Y{NAFeM__t4=LVmitpXNg=W??>a+|o`o)PLt3UI0 zeI+_!L6NaQP)L8mAqGsfJr5nJ{E1@V_wI$9PJ5Qdz@p? z?V2JrhbXHS)poczb9d7A5uXxL%`UGDthh381j0AHBRh4;(AS4G^|8m^jCJ5~6{Y=l z1%MlPs*f2oLAyLS84dUzqD%P#&LeNRjJp?d@%##=c{^TIg*Ud_oTfWDXd|7cLOe*i z7Vx_~D7va00bV({$IP+H8Udy!SmxRns!yV;`RmxO8PKCD?De(C9*29l;rW?vu4ce+J9ahB zqRwEJ0}$u>SbwYiSNb$s(s=&9zUG$;D`2rVC|SFwTvxt7k!OiF7d;j{OReoV1+UQOQk|&E{4~$5(}P$WRO~*fE)i^i z%7dE5Pmghb6jh=dQ*|12M1odk^$LLbubxpl*GSeAC97~)`z)_`P}~Ys=spfLaG(QH z>LMgo%5{U^7&(uB+8%z~++I-YpLt)~7+eMD{gd+;Po`Q_4WUUJ0k~!hFfKpB$hD}) zR2y|5q(q7{m=l{wFm%)D=+gX2wH|~yNRs>^T9VeJWsoj`H&cJM6Ecy>y1K&zy@382 zlhjRPmGUy$fIKMDiBxaGJ6N#mwB8!NL)%|>Mw2y9ni`d zb31RG)T-_%!!yPgaHl6fMl`4(HROjwQ_FSrr9GWd@UFTWi&h8;B@ww}wFXV_F39SF zax&~1fw}tY%8Q3-aLIQ3NX;f?*D)t%J`3zHkFUM$H2%eY$2LT$z}Kp0vN)aUTrGQ- za(##H7T&}n7*GaICBL`n1qN533rh#rjPp>q_a0magp8mHe1}@tMgBWuJ2l;!&x8hf zZeAqT6;U~Yz(Nmb|5Lca#~#vH3kO4sUz9&O%o8Zb#IL38eJ_yEuq2*Bz|#P9uzT5) z@TtvdQ{b3?qAt@H9xB}-Q~P##*m3DwERKVH9kOA{DRbV8+~Uh2B1T zDmp|^TCKdia7&ExsE%NE2I|{TXB_Ktz7b&PPYqzP;;`?d+>Nbc)nt5?flJ60sbi&n z&Yr_3hsOJ7hw8nVQ1TSndfg4PAL?d?(OG{CXar+v5xgK zn(F2_c1(S0<+^5VPwbdI^Vs`NE3;m0 zd3QWF6WVo%s(xCsg)6R$C(!>YtCjuwh1F)XXgU1R$al0S({%6->Ql7k z@WWsX=^x9E>aW;0SXcMkdV2z(R5ge?WX^^2Q?SvKdhVd2=dor^8&xbjfb%r*g_!C? z%j)`e;QZ+;?dR@;J~P(5+=ji$YI`Km%VDZ) z(qc;wxn}Ry8#WKC>3H))FM?7};eghQ@z%?Yx}VDh3ehevw>xv!Zh(97l7^X{*oL`e5>6FE7wQM6kJSB~63`2Hs~@fi_-QQ6&;W4n#1 zD9Ofb?|D;Eu+eAj&X~cH8-gkPd1}zS4k%v5)od%{k68Q_PwbzaY>7{ll54L*9?Kzd zCY2N%bOyH|;UoBQVo~!#|H#U44`12372}6PCt(=DFHeqhOIKZMyYG6 zmg_(VqcK@tDZur*X|mvB$gqCQf&%?TRXL0*$fMChN6xB=K7Dj2_WPf@`yZ)r zca37dtk*w`J>tKn%OE~@*eep>ZzQ}b=}MDjJUpJ4)C(OJxR--c5w=v*={AL%Rj+|` z?Yovjc1YZ;6t$gf5Qrx9X++?%BspiT1;vpyOJi}xg3-R(fr2F(&W)3!lx_AR)#)J* zq3u_$60Yh}E(v8hO32LZNFmv~aEDeXGA8nOp%=mLs>njs;qFC9tEqVHL z@h%jK7@0_zQrn<#DN$1wO`yb ze}eImOWg7U^8Z(B?;X_C6UKY12&gm_>0J;M>AfS;rAhC-cj+}mK#El99i&U|y(%U2 z&|4&-2C0Dr2oMOD-#hc(J9FQ6=KgbMc6WBqKD*~6=S(tZ_wzj8tWU&AK5n4+#gSY< z$;HHVQpKv4_8rNNs#E5C$~BuR-?I9u#ZFJ+yd^Y(NS562bChU%M8d)@j8lQTD4#1J zA$25cj)r$bTN2r=WS^k4*#L@eCUgo(eW2Z>ltJ#oQH6$w{qx15lUzg^YatQXJslrO zl+?oMKW1+<^fbB_esJ*`o*a}EG<=ixYSgZjKSW~n6t}uY;iYw1KmUwAci98Qz00gk$qRj*=CfWPQ^Q>bC{cD`MQr6 z<3>Ub&!oz1s4Y;FG+o*e@)EPZcX~4L)JvA?GOsL~n-5C2tXh1XRy@;aIRA^Lb8Ad; z?c5+bYr!k`{eZW$V$$E%66ZY7o9U(Z7vuH=f{?fw{(;e6AeH!RkJL%#n+5G_b?2KM zlUX$Yt9`c?tf!9(LM{f^|4}g`;`mx%2NW~fB~va3OaC0dKdPiO(;I&6+yF#YSn_4JcNgdxsW;q#JTSC{Nlbky5gPj`iDXOj9T# z_zCL26ejqAjXF>A@3l$LE|;9cK>vr<+pE*(L6J_fd3*4b!}wn}0$uIGEGscwCFL`T zN!VAfkKg5=5u6*fnQV>j1Hm>}$=EK5rTS{bPE*v$qm3`i*}=UIRtG`F(wO`qkIvhk z@~#-ZE^~>NTJG8`>~i;?>)tz?dmKC2Z`h7G{rx?<3=Gv2$!-2a@b~5h0IToyi_gOL zOsf9rDQ!KQX*u(@jMDI+X>0SrjNf&M)j79yUH^U!A-NZCg>fGn9@>_B6&p{2K79=< z1XexvwL(}PHccC$UFMSMoM3%(Pur^UX2cT&SwE1!{&jI4W~6iHP`cF%<9oB1*bTf~ z@0^cwv7^mov5(W6x0iXBJ=h8lSFtvRqkypSiJwYH$sCQzsJ9hA%fpTt`Vr@*%gY?nHLzp@VMdmY{2s*Sj-!|1|+Q5O7J+&c~L zr^7C3h7)~WVzLI!R;TZ92iQ|^EvAZ`L=ul`h(fe*b3aO+4?cV9x{h0A{T%#&A+q%R z&9p^`XHvSC#;?)WeCiMu&P?&fXd^i9DspYX9YLSnE&W_YHf}1IFqST??&JulR`x(2 z4&36oFz=UL)rd|sXsRgK3QTqJEL#;wF?XnVg<;uR(WT&;Z~9BB`}Ezsp}!FCvZ6KM zb>ZrpfiN`|zZV(SXKRGaLOGm@wnL_V z3;;Y`o*(@qwMQe;Z3=7Ua$l(*=Ie(Xiw4`-^O15j8713}XE;yTI&z;$38}leFKz4` zwhk%q%>R^xSPHFK_}bVsevpsM1g^6A=C9OH=~Wyyo*w@bYRag# z|2$w7;>kJsTP5Jsd?*&_X$I$pm!4{wMb>TFBCX80JT7CzxR>tUDAfHT?Ji2VyKjN| z-{kidsc(__MArR6J)`}pzy6@-5&l0ikqp`iE~ z{gchUOp2Y-?g{guan^kFy6vTv87ub=?)bq8nU7gDP|to2cC2kbS9hch0?Ox6Sbtr} z>MNQmbBB~q{bvz}bM`+^_3OSdYe3Y)t|!Z#xG)`S-ICYsGVFvoZQLurpP63|GI@Uv zKV&0S)e&gCED<`XBC2;k&-l4{!oo#G)85j3ao?xCyF>XFxCdJip>db69Tc_3y+)2vkEyeHy zxys`bp?9-B%0j<7k1eo>y&qOm!oEhcf;8#ZN@bDT9Q7ZkX&toqhU&o&oXI-9CYM-p zlNuOb;&kxs3Ve+5o%t}@sqluVnIzsqoCwH3J?2Y|0yqe?&QTuAT9>Pan+k-j@vVgq zt7jd{+_%v`8%)di;;$3Rk&<-1_?;%u4KFclbJ5Z1T1@Tg_`}lh3To<8gXrkL_R!%O zNzq3PO{vCy-rw=7_STY#SFHoFjz85aUerZ!J-KA-u-CNF+~@g#LlkwUGd4^>Qv>k9 zE4O}oXn*0Ym_|ztczl<(s2`NTrJ{4x4WJNwzLaQFDNy!W%ImbvVcx zSNv-HWG&U08Nf2?TzR-1^iGpfo3`ouom2colAMpB@)lgbwMSd1sFhRH=nIVenATop zV&VfI*A-fGoc1?${kOeDhGTo;QoSca7N7JG&X)EKjib#ddYm<~?B3n(9&@#DPTwL8 zduGz62HK2`K&sIMIsDzZ(KVI?0;cC_{&~h{0C8tbtySW`cwhiH&Ii$kC&qV3c)W`C<(2*5sM6fWS`rL%^50v^wI4o zy7MsCya#EU>-_Sn-d`fhr<#fGB23>1L-{>5*8A8u>?Iv0*E$i&M>ISPsmDYoUZfr{ z=6<1n5eF((GpX#_!l%ONT|eJlY|Gp1+?6d)-Xup*fPpBnxB6^Y@$`s&kpKpqK)+w? zO?UW09I;nADSV9LSumwdDLvzaTXn{wy$lC-t86c($;fDUy`0zUvhSoTulB7YX)Fyx zRl_P9LprLpbbZaZAivnfIWqF1$6xchE1Bqx7|Rvz~Nd~fb74j7{zq1{*22L zhxERg!msf97`WVrrW>L|wnRmGSIl?;TQ-`8W( z&LeCAmWJ{MdOx}Ke7QKpDbih^j6d@p9wUyhjr!9_djCy9e;Bwcl?bye(o|BKzwTj5 z`dLo?x=+qEj5_za@A~;;wb;k?|^Q9GoD5c)BOr%LMNrp;&7N+ zFm3EdA_ZAtaemPpv|K7E{YunezJYuNvDf`Ri@UQUKvk@~vz1nM?Q*Jb?`%~KttHpD zvFVQ23-|C7D&UWE?!Lmb*ow2~7`miedwrb@$$UvbW0FM<4`3eKbuV%^Jj|=>n*rHp zEB$xJc+4vqbY{+Q1;$~&UjMAnnaL&i@190}wJVN+f4;Yfr(Q}(vm&jx{geuZJXE1m znH)1dE51#_P2@QMA1q)UD&}u~`5o>y*86IPDoQ1iufOOmUxsmj`}|mXJ`|`~JllG9 z4b3pvdy(U?s#jOMi-D#TN;^A|Ey`HLKZpNZW*@0n3D;vTAErj!A*&E zpjQnm8sIfy*Idtpoq~KIbB*qEPuPgl`|N^qQWBVC`0xGtyQ0dyz-C6wnfL{}!%xqZ zp9XsJx40mKf6w|Tu4l^k|Hyd{gSfeXuzD{lR~>npG{?te0ypf`A@X;rNWapsi|&|< z?l9ltn;uP>AOraz1DPN#tW?F%yeVz1poY(wCx=Rz)nre`tTh8nOzFRmF?(FOm{Scm zvCl}E{=5+zWz~E2;z-b^LFqWh`6>eW2;fq?OEE@Z)7Mc}kY1oOf~Px1ubWo)17Lgg zY(+nvL~bX1AKCk>+uYRb7k6oA_h)m|KJp_#uyUN>T<}$fxp~p|Cpn=by||u+`mEK8 zipkUJVzpE?Z+gB(H51p?YOf@W*s=P2YF9dVyx{X`S?M79&`GQOTViv9mTCF7q~?T? z;rnh8(m$0jBroZJnw%QA6it7*{4qH7&Q+3TgVVKe zzjZpjHLS8VjMMdM!S%{`RjYDUtF>9M&ds^Ev_?VKIG)p0cb{*K;`wxr&ce!B28VA^ zeh^8J^hy?oCX9J5$)tzUoz-I%0JFyCs#&qH&9+&-Ee`dYSuSR9pon)0wiO676&MuZ zm_G5F`88~&AiE+j8#nVP{)&rwp?$(Zz<1{PR@(>b_Si_uCS2+iQvp_EM+<n(V}1jc8yfb+LL^s-Ir0v^EV=P%^@PsBh;5JA)Ob z<-_98iZwP|7vV!*^FKciP%BXL37{WeSm&uv#we)>5mB!!J~|Ft&@jO{?lq=&%u;8e zNpgD8<+f0x9>2~IlId*pHT?6OK((Al?KgjOJvo9!=>D)W=;hxlYF59$M&u>r(X`{A znPcZS@^@b&`Lgp>jP{qL{yLu3zl{8{J99va0@|+a07+kNo+X$bB_^EXTs_2i{WJe3 zOxd>w{lZS#i*QMb9>e>4w1s|o9(ZF6is&ZQdyiB#^dYRGe^J&R$Sxf*t}zp)l)~9; z;LOs!9W=x=%O!(<5)Tnq7>KqRL+uS-1r&+Rl?-{IKVTUY-{|So8T&@fPcXoxc{;t~ zm3WgEeDt{y1$xcStViq~UC#msjVvdn2Ul%F61ge)6>B3_jHIjkwtN@|511?LoA=F! zjd}SsY!cx{TRO22On^LC13y^fV|Ux#9WN4JAl1m0>;;09X@$NvB-%WsN4WP=f)E zR%rqK8QcE~&5*DWlvX)E_YsvMnK|;7X8vrs=F(1|Z z2u=BX#!8eM`uiH`(mXY+aNtWHBgO&AN5<#m;D%_2!xD^PS8z@wHRIjzj~Q@5 zx$0u`_w^hlz0%vp&QiA)HQ6bR=;_ZnBH3Sngu(s_!iGV8b`3++hxSAH+0%9xN|NH% zgc!c1YP&Tu3}oJ2Eg8F^yePdKzJ=sr30&j-Vk=(H);7t8%aOmH`SjzwvqLFB;&;Az z=>(Hh3r|ZZ_iuw(>k|JPywgjf%qb7cyBMkoo&4Ye=gbs9p(^gwY)=i{1+&E|Cjsc^ zt%74+b@{Nr`qc2S=kg3xN`&C2BrV=V|J(2M(v|71`wSI%t%l3aRnv|}Wp3{78p;su zX3JSKOLz5VbNwN+7im%pwpvV__wN^P(C98l&Xh+{pav0sS`1GiNn^Kxl6S7Z55 z&+pC>_nnp`$2lc&`*hJUpIW{l^2)uUJWr*x-|P6+;$$OXtmTrTBSeCW4a|_!X`QXzxnT4=#~-@2 zRK*9kNBM*WcXjo;CILISJE|Bwf;aFDrSs9B!Y1y7db?3Aq#n1u&YGAvX5Y?J#>qliwiA`%!y;()WKhXu1ka+w$ zkHxy1RU&$iE8R^t^H%=V7va}l6Ja8(Z66?w#A!=Q&OlgI-`?u-)alf&p=zzn=ayF8 z4%Sv&>(WNuTgF%^bNkA?dKkuIsx&0mOL;>y9>>X`iBN)|W?qV503 z^mUjQf9ZcqaI`gX?f;fy#Qwk6bvHq4qA7~6uN1P7&UD4sBSv@k@fdG+8?}Dy=jr36 zi$Uw6kJ-nNe5W^WsH^_H+}d8^nIBm|j=#%FK#U+aP>5ZeS*$>fk2`h}9h}ly9~t?B z4IfvwrVtPnVgCRLxcn$pAj=?ir`}6Awb#5z3(Ey!XL~xk#ytH4TB-Krtqpd(dWe?i|`h^HyItvedxLu#O9Hec`qQ-EwAAl44jchYmAjUmB< z!Wk{P^YQ3K=ggKnMEk8^3nQL?3o!yuyH>Wp2lO%1D@}bj97aF0b?vF!wfAQ^)FABM zumm9GOI!%{CKBE`_ZI7KL1We27bb^Y<2!|WfPMs9m!Dl_-N>CRpcmd^mpvD;$t{zp z#_iQe;4TEO`?Ajoq@Q9Me^1ib;l!=8tJhA(SBJ+T*v{EpT1ufU3ps}f_8jwRB6Hez^h1QYjHfo2 z{lpc@ca3LfP=W2c@U9w;)$fD>+dm?tws{YaGyYj5A zf&=9q5%)BjJ&BBXn!i}S zuR(@^zHSll$p!>})+*irU@T-R@wyv}`Hf?^z>skcceI;h%zDOH|H1*r$+i>h!;3wM zJ#7m({yIAUZ1UVTX9Z_j+RA^s{TqO#A0BV)3?gD8M}Fg)}=qx7px1xiF4VXBi)~S|8Gv^>}dz>`e6gn9!A)f2k;7mVp~Mbs*(O123~uA(kcdjiZIVzXK0jH zc?6LR2jY%WVDWO zG%6CKEHCiW0I>mg{aDv*zzXYe^wxPOAyhi~df$7cTG0?%!qoJ8V#C3!+S#M~TU?96 ziS6%;O%Qw+i0gXnKHJVNkcp#GpO!DVB~*2FRqN~HgL5t1>5=g5YeYhTYU$~NoTfw9 zDn{5J-OI-v_+bKm57yak^D2zPFxb(aU`6Cemc6#utI;pLIXsZ&%k3n)qwX7H`{SjN z1?$TjY4g+p=6HSfqtp$m4dmW_+j^n0BBAg7PUIEL&oW}=yG+oPSPri1z@ zEuZ<=$|4zUWo+MO!MDLvWqq&_b(sUX{(wn;*HtF@X`f_d0CSD>SUAjGOv!Zq_48?L zUD{LBs26=oX+R{BSHtTh8d4Arl&N08nEKOa=;eY+M+5#&(8D*Mv>A3?5mMUR_3U#2 zQ5Nj4sn`yTzGPjkLp9d)^X>rOP5(v~NDm0h=9`euRnRd{mE!oO^Nl|edWy8Hm$CbQ zH%7?@MRk7F+Vv@tTk2_pz*kayH@tO+6Z6VBPE z7%<1IByy@g?zvS#^R3?%?>5hOdAx-coyFsnPLIv@+s-Sd;-Q%KCDsugJ#m&-o0JUX zpesp<5qBL&ZF&1vN6$8#o4{{dP3SMfSpe|A?8u?h1!rkc=U)D1Z>v9lB1N@Nqv!xC z_{)ZjOaJZhy-s}=*+!u9O)CZUFzL2>;UwcEAo=cg^0w2I8~z+q4%umo#`(zknbEP5 zoSld5<<9)1HJWMom@yAXek>$8)|{%pL~G1*H#&vKOVi=#6~OT?f7&SL79}e6)hDdr z+ir!_f?KxVuBnjYK1Viv$36!Tr#sCh{qTkM#Xlv$X2W~|+56P%T(}2UB9l<18f*8A zwgdtKP6#nnla47DHSKH^}DjU3OJBJ;u~l z2w14$zOS#X>(BlqFz-#Cv)_4CxhE=RRq=?SRS;`+ZQnTUx~9`~(@iU_j=rk4LiRML zCy%Rv?p4U8Pf||04|*w)-E^nu0*m5xf#S(BX!Y75txd9cW3ySK^^{xMNx`5*vdT^t zv&vs7!t^>Lab9RZB%RT0+TYEizGA(HeTyT!jOL-7S%bgOdA&hazEU>L%PyhWodCKD zPjZ!WSFf^s(HExmn!ndy`aIc`N)7qKxpJ7p4B2s3#EF%dhoyj63BDS@wgj<}ixyru z257q!oSiP{=O#N(;GnmES8oI@e_O_tWP~Den($=zVi$PYL%2czI5+JZCTc>|N=V_E zSE#F>|3u;^OZ zBBYoNKG4~K_yXkl|BPXSk*906bEm&J6lHiYKK5e#?tZYlGvfN?#%)6!N!ZSo z*{C$$IBXGn{$@1@MnY$GpV6PNG6vY;i`!`^Cgk7q``oU7uNRBNVnX7XBo-5Byv#9E zxy}+4j>ulX4qY|{^lo!EK`j6s06uar`gU`OafZqjzEWvoKu8-9mkJkN#=ZQ@MpN+$ z`LsZzEL_>uGh?k#^?JRRMgO<(m%EH{NzwOb=6=F2Z+HEeX)@ypYc{|w2)HBE+N5(U zr)%zXR=oG?dzB2ecKzOgMg886@U%+~Gb?Ze!qqilRF999mxc;Go5+9tyTM7|6|~E{ zv$V~xu_^e9b_Q4_{!sPU$F#Pys(GO8sMng$--OdV!2Rhe+?U(6@8WocAXVPH0f3X@1|0d07gBv=u=Q;s9%>^UN<~wCX*{$;NfNVc{;yFR z&kU%Bx>q3ERUB4`cj4F6PDorS5}iB)ML&$YEKh+>evrQM>;TeuXnl!G!47+9olFiZgLm;a=tE;SO_F}#U});k zfmOF<#WfVmfpuQ`{E+F$^~#jw0zySK)*P%NZ@jNb8i;! zWQ+jfwDx*5p98IpVV8EUxAkL-@9#(686U;cx%TuglAv49<2!_ASPgRcjiqxP!HE5y z*9;mPM?KlLddGnHYkmXF;1^)Xb%#pSNV)Lhao1T60()DtxNe<)6%HoXP5pc5kyE zJbBi5=?=!!gR{amOb7(XKTI&SQ7!V(nmDyT7hebYqRf9+{wSxRilAMS*u8LnUI0I2 zYyw7@_^lO`?e*cG2LV)G)uV>uThY9WpxzVYefuyrv!K>Sk|EncZzR z=r$W)vhQ!*+2rfr-AI5`EBSmV_P4R(G)M%Emi0TxQQGSwuI64QY3Tq*9;ExFf8v!! zsjblJ>wxAe!gWK;10DqAFeGONj*F`UW8&7$l-)nSqY<-|ax^w)yG8{Gc!jvIpW$36 zBI#9S(0f7AIhakvs4SE_W52$mx6M~4(~D3pGti9WtLWUoqHsHwP*QmQe8(boV!ejD z-M)h;<%HERxnK$8#kt)`bn^)+w>wuk{KW`Vm``2zE*<1y#A>)iny~X1k^m&uOFJ^q z^|jEwLe=jhhAaDUs;~uN3lGy$a6}fkLf+Hr(EyV;z?ijch`wS z7v1SJ{}_KFC?^*DeeK&RUmZ0!Du#E`KfjMmJ(cr<=Aux3Srht7JVemRGc@|51mcFTc{UmJy1d;7Op%WqZy- zG-QOXB-7Ps+8gfpCbsOhj!tznLaNyq&f%+Y%+A4=cDjKMN%ekJ=EST`tUdFbW^dw& z*(qei#_UZ>K!hsXorSd2i1ky1YN~MZck?%-eIHq|G@~rP(v?3mrL4!>gjL#vvD<_} zl~~)2Sld6cUdG$J)Ei}~{-G?@N@$h!_^oLlPFBAZg&Dp$=3z&vWES|m-s1MDf0%g6 z!)}d&tDX-8ILGL)M|mIWVLclt5lOKWQP$sXKh{ZfVu)EA%efbs2EHrhD@ ztbuSwUOmcAg%ea%vpRcU-MHCpc0J-$0_d-Db1omZX$AgVVk#D0{_&-M-YBaBb=rgd7wY?Aj9@6>;s-<1mPccs&Dui55Z)*j$WtRCqfhy);njM z;g=ZM4e|7)0a=WoP~y9xk&f=QM^pmP4|u3&R1@-inSG&zshquZeyPI!S$#zISeg-$ zUuQ=$ZgeMKE(rCP`8lY^FNqGRYU}L{T)@QK;q@Q!EYk>y-NCFy4LuFqS*_BdXYJJF zOGG)(Z`_TpuXgQr`$PppW3!l9gM2U z`rJAyC63Oh)poy}jZ?Rjq;_N)8>L?SU|Az@(psljvLlfwrc~dSicRPiUgz8$nB@;2 zy`AT)yR7eyH1;R*>fTJ%uYUKm4gw9~ZqDdkBDOygLetiA<`hH~RcabUjW4|0r*LLM z5NLhc@g0#ksI!+iFgOtk4w10;S&!Su8F{2X`Y6^ml!QCB-iW+V={}4Jxg~q-XW0r) zKh9Am&GP`!*h;N!G4|z?T(t(;(Fnf){@yuHM`O|uIRV0H7RYYYU)x-JS2~w-8c*=1 z{eeV_e_1hTRSnig2KmQ3t>pwavTjdP{U5Ol+FyQ&rL+A0B?D&tnh4ErbcNx$mD z(Ier+F=4_nd4qFv|6IJcd7f_j9B#v-YRkhh@)fqTqKLOHEO|hMkIAu&P|EqQCVD=)-tc7!0piYwyK zEB@gKF|fzIC;}tOnn8D5=sa;At6MXiaXX_`ag}tdnF=`W%CS0PwiwWpURBiuduY#c zjh*EK@2NY)-fic$y0RwX^tR^`s$+)eK!CC0jttHsFsYmZxAQf}W4?sbjU78kgs8ig zZyp5v#0p5XML;ojxZJb_2&a?)x(WF$@$^N4#)Y?Y=hKwKdy~+R}Z2s&qkC z(q`+M4_2AO7o=(HLNk{vQkK@IyI;Sk`!(@ijJD2T;yrYmj3ImJ^PsZf5BPbCm)wkxS z7rw%fDysHr;^|$)EAdE2K5;N@ii|3WG>C56EZX4jeKZgvbV&egnQ&<6QC152ZpuZV z8y$Shdm(+?l3zV1QJ~pF<5%Za%V+97+xw07Asv#jJyAF~ogh)$Kw6W7V#NH%g;7g^1iur~WVve~ zvJuFm2+si1GK2#`a8TitSMUq;!}nSAJMzsN#`p+S0NZOP&Sz2!$;I;fpcL3zYHtDZ zpL1dDPy^9m%xkDO@+N33<#!RsT9Uu&lkR_OyL{kNZBcPdAfi5GBtE z67bf}U=qYDahT7me!XtiN&xb%eda(QeDu$mlSFr@()2bZ zV7@@Pc4A8ldmEtsJ(Qf7)o4rImjJGS%fc*vD_sL8W? zRHvfHD1Hy=CYU+zV42g_;>sA?Iy+4bp)Q!)x!T*?t5gP&n73DJbnS?Nt;P3bWph3-{Ok)~ z*gDIQL7f$<_1%bZjsH9KyT>C+t3ant)49YUh2=;1*R~V3D3O0LAzOT**!Zl$vc&M; zj;IXZUItV%gI7(`#nvvFq%>VzC<#-7cHr*W?nAnQ^y~h!ThwK6{}rx;v{Y)JG$f-0 zaG|)09f%2eI=tY#>WHZzJ`roD-M;*Wc#iJRHmE&{I?wRH9+D-1X|1DW{sTWiueLfo z5sYcl(~t7!y!1tTJ0@fo3!>t&{cW;H3FRqimy@`4)q6SWU;LtP!B5~EITGc&^~hT) z_!NLPY*&E{O!N>OkAsrnMoCbdNJ#U5KaqiBzS{5fOJHpC0T030&;a5}f8xgy`1o+D zv;c)i`7@yb!@3d~u9RZ+M6y;idT>z*9&pO`!~h=Hz+&Je)RmGP!oyK-dD$;i9k$y@ zG=Se~Y2Y$2CIKdyXwn+;T8Z4ixi@IFw9UW8LDA}*nza6BOBm~FkY(>}k?%nUwxx+A zaT%yzj!e53v6w*ZWEX^k(cc1Yr3Qn?p@n?UZs3T@AaV4#4p2zCvWrcR=eS*&=|ZUeb)0M4@xx2T(*X<*Cs!3gOsQoMiilnl>Gr zEZDHi_ik9ACX}WSuVPT43|C{T!j}vn5+d&-Zp>f8%-^UhSxnUD=PiCD4vq?iQ-}3d zvHJWvbdi*O;##uPh%sxAW6rG>e*h%bwY|8zT94o zAG6pYPY(J!JVya-mZN4Y2y#!l-LuTTAm1mZpaUA3PB#`*Q+LRZZZ}%3r3oQ$M5h8O zxfXRmA2og6>XX=5n}&0+O0l;}vA-%^UmM<7i_=gWj&nf$-6#H2rvm=sd27qP(P^j; zU5q!~Gaov7ouyMTP-HFJXzrUj297$msChxXjy3iJv0g>JX^oKEt>>N4R;=c%&oOpc z#+wdC2Z_6aKQi6=OO-nC&*19IwAv=RtIdpnUkVP5fZSMBe7H!#@r-{(3W^oDsu6V63BAKrE@V0v| zATOCN)P1FgJlS1e)W2)TV1lCgfT4Ts=e!%EgRqEymu*+X^*w4Zk2E3jyf$C0C3i@Qpu_E-YWD73(-l2@u4P)Uc5 z>qJS!H-+m7);xml7Vd#&Zd6|{cYHJVm^myXV3p#o4iTGt@#gXXvsn(10Rqg!nz=9Q z5CoqvFR|x<-yY_lU6D)ZH>w!En*+=rtDvy5=7;u`OWO~TrMf-uH)5bEJO>ixw7@n; z86(M+RGZt0EqDL=#z2H3nxzODw|tF@frlm%rqtG(o%ZIiOsObFX3UAo-_%r|SON@B zu|sJXrEl&PAEw$mOHgRWz?z76DoCnRZ!9!i-AFpWT~a73=8z!IBJqkJj?Z7n@$nIW zO&Quge3m>-taT~sHj-#~>z4jLkU3$u?cm=j4GklL-|%96lH@JMTE)*1G1yd`l`x8% zLle}840=3z7ieSo5{?ZWHZcboT;aKJ<*+@_3v++;9=r1jKx6RKs(QVT_Wj$TF<}dL z!@sI0sp`E?tG{K;F%1Eq>E(mXgqw#=a`36KQv=k%CD!{;k^ljX^>{{cmd+u$jnQv+ zW+~e_XOgem`wmQ{`T#x^5rSL8l6zVipsl?w5rWFjo7g=g9ijm_{WJvh$^OrMF&SOD zzRm(fMq1_xAtWtpPKV+w!t99EUAij(GUl&*jHlh}+vIw)HnYR` zr-7Cu3&=fxwBRP>#W5h(vPi@o(E!+jnk;QoT9d9>xwlmeJ5E}1jq>!5<_v1k0;2PYhgsO9-v=s^y z1&*73UTw-pkZJ83*&UUgEuOXVHX^!up7vekK5E{LK|S6+-sv=TvPHX?s%}UwyeB91 zJBomUhDVQ%#JW@6jVDfL@{g9UqnVOl1Rsw_%ij}zA+~L0`Ykz*8JqIvZSfG&?p{K7 z_l5L{qNiorIhH>X{3joKeN|IuhNa*0w?lrUiYMv?KzZ%X4d4d~_gP)7&OkrQf-@po zXsx?(M%(A5mY@VRA7-;VwPDU?{8kI5Ht&Jsg6dPw&U;$EIJsN2$d8>bcPnestDZ4di><_DDhHAI&VW zwesS3mxIWOx4XR_6P(V%rKrUHR19sF0sy21nP;?(D`~+Wd0RSt>__c-~GkN=61krkxPP05u`WRnQY;;ATPq=+7}=<5#p9hnye8XKilx^e4 zS?eaZCGFJ_x_r|pgP%-vGHO+8FFh`iyOwPk?JD2v%Q^a^+yeVD?@v}?#>rDut%~dA z>y`V!CXLVUm$58~JxY91@~X_5-d))q=L+8WQ3uVDz7y!oe~9`1P#YD!!YCqJvrl~Q zcg{aAmYb-$$7)}@b`~sn)05bveXrR_)^Un`vs`}@@TK0c+SROJ$SqhBtq=>X~YU{dC~CJbE>G$@qoQ7_711BT}gj*j_AH(nN)kHiq`eQ zo4K~p1t$Bg8Rri!>FQd^`^+`kpGZ!o4AjSe{uy!7+j3#rQWJi@kjTWV?ERXc`YC9{dldViLIk diff --git a/impl1/s1_impl1.srf b/impl1/s1_impl1.srf deleted file mode 100644 index 140bf93..0000000 --- a/impl1/s1_impl1.srf +++ /dev/null @@ -1,1747 +0,0 @@ -#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018 -#install: /opt/synplicity/O-2018.09-SP1 -#OS: Linux -#Hostname: lxhadeb07 - -# Wed Jun 16 09:19:13 2021 - -#Implementation: impl1 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! -File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -Running optimization stage 1 on fifo_colector ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -Running optimization stage 1 on tdc_channel_fifo_out ....... -Running optimization stage 1 on top_tf ....... - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] - -Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Divided design in to 1 groups -@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog " -Compiling work_top_tf_verilog as a separate process -Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s - -Distributed Compiler Report -*************************** - -DP Name Status Start time End Time Total Real Time Log File ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -work.top_tf.verilog Success 0h:00m:00s 0h:00m:01s 0h:00m:01s /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log -============================================================================================================================================================================== -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB) - -Process took 0h:00m:02s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:17 2021 - -###########################################################] -Premap Report - -# Wed Jun 16 09:19:17 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@A: MF827 |No constraint file specified. -@N: MF284 |Setting synthesis effort to medium for the design -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt -Printing clock summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - -syn_allowed_resources : blockrams=108 set on top level netlist top_tf - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------- -0 - System 200.0 MHz 5.000 system system_clkgroup 0 - -0 - pll0|CLKOS3_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_0 787 - -0 - top_tf|rd_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_4 64 - -0 - pll0|CLKOP_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_1 36 - -0 - pll0|CLKOS2_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_3 36 - -0 - pll0|CLKOS_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_2 36 -=============================================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System 0 - - - - - -pll0|CLKOS3_inferred_clock 787 pll0inst.PLLInst_0.CLKOS3(EHXPLLL) reset_dl[2:1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv) - -top_tf|rd_clk 64 rd_clk(port) fifo_colector_inst.fifo40_inst.FF_1.CK - - - -pll0|CLKOP_inferred_clock 36 pll0inst.PLLInst_0.CLKOP(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv) - -pll0|CLKOS2_inferred_clock 36 pll0inst.PLLInst_0.CLKOS2(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv) - -pll0|CLKOS_inferred_clock 36 pll0inst.PLLInst_0.CLKOS(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv) -============================================================================================================================================================================================================================================================= - -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s) -4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s) -0 instances converted, 895 sequential instances remain driven by gated/generated clocks - -===================================== Non-Gated/Non-Generated Clocks ====================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------ -@KP:ckid0_8 rd_clk Unconstrained_port 64 trb_adapter_inst.FEE_DATA_WRITE_OUT -=========================================================================================================== -======================================================================================== Gated/Generated Clocks ======================================================================================== -Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -@KP:ckid0_1 pll0inst.PLLInst_0.CLKOS3 EHXPLLL 787 reset_dl[2:1] Black box on clock path -@KP:ckid0_3 pll0inst.PLLInst_0.CLKOS2 EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2] Black box on clock path -@KP:ckid0_5 pll0inst.PLLInst_0.CLKOS EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1] Black box on clock path -@KP:ckid0_7 pll0inst.PLLInst_0.CLKOP EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0] Black box on clock path -======================================================================================================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jun 16 09:19:18 2021 - -###########################################################] -Map & Optimize Report - -# Wed Jun 16 09:19:18 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog)) -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:02s -0.86ns 187 / 525 - 2 0h:00m:02s -0.86ns 184 / 525 -@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing. -Timing driven replication report -Added 1 Registers via timing driven replication -Added 0 LUTs via timing driven replication - - 3 0h:00m:04s -0.74ns 186 / 526 - - - 4 0h:00m:04s -0.74ns 186 / 526 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB) - -Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - -@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. -@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. -@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. -@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. -@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Wed Jun 16 09:19:25 2021 -# - - -Top view: top_tf -Requested Frequency: 200.0 MHz -Wire load mode: top -Paths requested: 3 -Constraint File(s): -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: -0.652 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------ -pll0|CLKOP_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_1 -pll0|CLKOS2_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_3 -pll0|CLKOS3_inferred_clock 200.0 MHz 158.6 MHz 5.000 6.305 -0.652 inferred Inferred_clkgroup_0 -pll0|CLKOS_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_2 -top_tf|rd_clk 200.0 MHz 256.6 MHz 5.000 3.897 1.103 inferred Inferred_clkgroup_4 -System 200.0 MHz 527.3 MHz 5.000 1.897 3.103 system system_clkgroup -=================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------ -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------ -System pll0|CLKOS3_inferred_clock | 5.000 3.104 | No paths - | No paths - | No paths - -System top_tf|rd_clk | 5.000 3.104 | No paths - | No paths - | No paths - -pll0|CLKOS3_inferred_clock System | 5.000 3.782 | No paths - | No paths - | 5.000 4.247 -pll0|CLKOS3_inferred_clock pll0|CLKOS3_inferred_clock | 5.000 0.197 | 5.000 2.602 | 2.500 1.172 | 2.500 -0.653 -pll0|CLKOS3_inferred_clock top_tf|rd_clk | Diff grp - | No paths - | No paths - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOP_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS2_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -top_tf|rd_clk System | 5.000 3.807 | No paths - | No paths - | No paths - -top_tf|rd_clk pll0|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -top_tf|rd_clk top_tf|rd_clk | 5.000 1.104 | No paths - | No paths - | No paths - -=============================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: pll0|CLKOP_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS2_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -============================================================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -=============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS3_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast pll0|CLKOS3_inferred_clock FD1S3AX Q valid_fast 0.863 -0.652 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX Q window[2] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX Q window[5] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX Q window[6] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX Q window[7] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX Q window[3] 0.838 0.720 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX Q window[4] 0.838 0.720 -=============================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[7] 2.289 -0.652 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[5] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[6] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX PD window_6[2] 2.183 -0.581 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[3] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[4] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[1] 2.289 -0.475 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -============================================================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.942 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -0.652 - - Number of logic level(s): 7 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.992 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.992 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.599 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.599 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.942 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.942 - -============================================================================================================================================= - - -Path information for path number 2: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - -Path information for path number 3: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B0 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: top_tf|rd_clk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------ -fifo_colector_inst.fifo40_inst.FF_12 top_tf|rd_clk FD1S3DX Q w_gcount_r29 0.883 1.103 -fifo_colector_inst.fifo40_inst.FF_13 top_tf|rd_clk FD1S3DX Q w_gcount_r28 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_14 top_tf|rd_clk FD1S3DX Q w_gcount_r27 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_15 top_tf|rd_clk FD1S3DX Q w_gcount_r26 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_16 top_tf|rd_clk FD1S3DX Q w_gcount_r25 0.863 1.169 -fifo_colector_inst.fifo40_inst.FF_17 top_tf|rd_clk FD1S3DX Q w_gcount_r24 0.838 1.194 -fifo_colector_inst.fifo40_inst.FF_18 top_tf|rd_clk FD1S3DX Q w_gcount_r23 0.798 1.234 -fifo_colector_inst.fifo40_inst.FF_19 top_tf|rd_clk FD1S3DX Q w_gcount_r22 0.753 1.278 -fifo_colector_inst.fifo40_inst.FF_20 top_tf|rd_clk FD1S3DX Q w_gcount_r21 0.798 1.841 -fifo_colector_inst.fifo40_inst.FF_21 top_tf|rd_clk FD1S3DX Q w_gcount_r20 0.753 1.887 -================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_1 top_tf|rd_clk FD1S3BX D empty_d 4.789 1.103 -fifo_colector_inst.fifo40_inst.FF_62 top_tf|rd_clk FD1P3DX D ircount_9 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_63 top_tf|rd_clk FD1P3DX D ircount_8 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_64 top_tf|rd_clk FD1P3DX D ircount_7 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_65 top_tf|rd_clk FD1P3DX D ircount_6 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_66 top_tf|rd_clk FD1P3DX D ircount_5 4.789 2.457 -fifo_colector_inst.fifo40_inst.FF_67 top_tf|rd_clk FD1P3DX D ircount_4 4.789 2.457 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR5 rptr_0 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR6 rptr_1 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR7 rptr_2 3.223 2.470 -========================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r1 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B1 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.640 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.148 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_13 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_13 FD1S3DX Q Out 0.838 0.838 - -w_gcount_r28 Net - - - - 3 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD1 In 0.000 0.838 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.491 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.491 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.014 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.014 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.798 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.798 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.857 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.857 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.916 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.916 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 2.975 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 2.975 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.034 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.034 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.640 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.640 - -============================================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 -Block Rams : 4 of 108 (3%) - - -Details: -AND2: 8 -CCU2C: 121 -EHXPLLL: 1 -FD1P3AX: 69 -FD1P3BX: 8 -FD1P3DX: 232 -FD1P3IX: 50 -FD1S3AX: 321 -FD1S3BX: 4 -FD1S3DX: 164 -FD1S3IX: 41 -FD1S3JX: 10 -GSR: 1 -IB: 11 -IFS1P3DX: 5 -INV: 20 -OB: 173 -OBZ: 2 -OFS1P3DX: 17 -OFS1P3IX: 13 -OR2: 4 -ORCALUT4: 180 -PDPW16KD: 4 -PUR: 1 -ROM16X1A: 96 -VHI: 25 -VLO: 6 -XOR2: 72 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB) - -Process took 0h:00m:07s realtime, 0h:00m:07s cputime -# Wed Jun 16 09:19:25 2021 - -###########################################################] diff --git a/impl1/s1_impl1.srm b/impl1/s1_impl1.srm deleted file mode 100644 index febdd833428d27f31f07f5f15d38bd68f94e48ce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22210 zcmV)LK)JskiwFP!0000015#C0RVXORFG)=VU zcSrMvv5(K|@0?@1^&bz7@7LP%b4x4?VVXa*TIagH(&U|Y;TnpQ2ded%`fo5j#j|F*j#6={&BVv?E@VX#PM zns!Z?DKay11<8aovtNviNUc-*QP)=2UA_CVForkk-|l9eNGIt8<%u%MG;*z(nP8D{ z%}gQ%;}?@?GON{pbXMJKt-E;9hus^a+kMfCbwZdiH&YRrhSXSgZE8eBEOWDhd-)5& z@mi++Sas^xU9I~v)E75hqx&NCZaYEF)o=VOl}5y_vy=6Oo-_h##nQ5bM|#qyr~BH> z@FM`a~pV)bgCb8aYxREL4(N$UcuO zj-D+~mN&dGmV}n$KgSlbEgL>g$m#^8;BPS2ssQJ~zjt|TSGcr) zFc>)O4y+W+E&qkzxRINd%`;2qt^IL-o_;XT>T!n>Vf6zsbA8Jxqn#YAImlav#A&(f zy^*hG#)XgF!KK27p2IC-2^!2q-*+r`i!BFh+WTwv^V@(q(!KQZH@^2Uf7Ri`g>gR^ z8jdTOXXmf>H!axNOvNp7-$&HoPDEvyentnfsyOvT;8G{>2C|g?WS{<{@wG9~kLT$Y zr2F$2QVu-f1sME>x6a>}gzn3yKbUWPq%4<}=|$hhn_BmLq5OSyGx%D{Q?k#KWze7} z0`B;}iyIUfWLr1e^v$~Xuh!|W`QxpP^#dEDRDO^9!f{o7q3UGeC#8GN_xCL8YfAl4 zzw#FVYn%hbIam#A-)+tYK<-2&ZL~M=0anID0?SNp*9HWP53Vnm<6q#IrETK)!MGo) zIM%jvd|%9ZS-?S(Q7yJT8-A<(JAxFhQ|ibW{FZ|aH6PS^!1b_rRO{_Qje}q$f;(C4 z$G{+}w%+pMlMezld4aaI7N8ZpFN}xBHMVKHIhj8TWRH^=M!1jnTV&VZ`rm2FA#{N_ zx#9=>HSVp(@Um(^!ybNL%Zus2nfVxVHa7;qB#D@rLBZPxgZNCizPxalW^LCSxZY@J zh;`dJXsHbIue>6lGu*qedfAuv8?+ibc|F6Ad^vN<^ew^gJ&`N;5z1~q(?iSn*7&&| z*f+b?*vUN{!*uoVD!1U2bLpHc_i$|B`f|A^1m;Ta+VYL<8Tf-7;J2lZ-@QPQpJ12s zHvWfu^N@HkLRcqK$3je-lDfl_Y97sR+QPjq_7OsuZTdx5;8Gu{-QQ!T`?sm4i%wTpK zW_^IpX8^mk+KyW?3<1IrM>EA6$iPMZa;SA}j*;~t@`V>l1QCv7v7I*}IO0D+za3r8 zZKlQz#yDlJBL;{G>CS&1$57NDu&zN0JyL@U+`BY((Z6KiwtC19@j^9&<_HL2zN_b}i~cYf<~7RG+Ma%Mf!u z7jeI5OYGZ0=IB3=%WwXx{j(Hi{w+Aa-cq>r9s2oKfK~@qTg>u-4J-(J^=D0cP0!+f zF&}=FK6P$?^<_chUw&Zi=7d%#0X~0rz`vFB*TRq0{x#puyCrs4ep~oT<5;$MoR`S+PeQSpF6Fu$?_+d(LBNoQ%~dV_|GsSP10A)=$2!}9~iUcKIMJ( z)Vj}8wNB}lL>Ej1p5$g5cKLcgcPgJ!7}A1ojV(TeV1*dv=qR5%xL5JL+Si6I(v1{9 z5%%z5?s8&7to*!zx{Q?ndsyeWG~|$zWUgP0R9v8rF}f)qxWY*#yumN{JpKH6`lfcn zUhs|2M8GZm)Y|RFc-*(k8{OKId2PrFJv}PEl;5DoS!;SsVF||`;}z@rGkC=6qBgX5 zb?prdLDAp(-Rt_3>e`}*{b_wOTw_8+MZpVO=QX7RQ`xrmxWfj}g42Lrxk25`CUeT(l%53>Wyd^2C`nHe*IK}!OcU!-8Bn_oMBlY$T$@g9NFbI{$qP-LVp z`dbWjoLkH-J}+{p3z6%J;36SU*LM1G?U%&$a>=kwm70e+#->^^uJF_1F4H7<+KeiU z41{|TDBnhXx%fR}xk7)<$NZ!EQ4B`IZv3)tO9`Tdy%u2brRNxJhZ zF(aPDtW)?^SkTQdm!fuDKhqpIJj>Cx{r$Jpq1zI4U#zB7jL{qW}b<++aT zQNPC~c-ehKN2wQUreZjr)*DNEQTWXGTVq(PH}BW{?$5PhQp^#Z?&fo%KHuLA$1nBg z=SE$0R=8QLc--e@crT_6RWvRaldZpVAIk=c6-~y8!~O#eZ9M$)t>E_)Bzm{;xNLo? z?>_JL)ITMM@*K_=Aue3Q|HZIP+7H=gTa z)v1p=_n%62*I9hp?h_EtM_Bb$Edx@sydV-;KN7P^`1J92NPW+eQ6_>2?HQ&|=FynB z8N(bW)cD6IEHu;K`(hSak@TKG|CsiF_h(ip7!|aooXlJn>A0{fo>^$)8ls2Y+Au+G)I^-lXft%M!cVzW%!mNz7>7MdOQ;$$!F4w zEP;utxyG?jItbSmRy=}<_4)TMPFOy0_?@3!I0e&tiX%-oPohy3>i+` zpm_oFc3b~jaf?H7&L#!FQ};>fsTefVJc@cbTyMT}z5d?)i`>G1cy1(BYC();GryRt z##If;(I(OZt-#}+x5m%S8Kbbxq#|~E1&(nc@6`QNEX<+~aSbedFh_0hx|qv~oUdvJ zUeHx?srpKt(Muw@cPC~h743KHVE$emT)j&Nqxb7z@?JlxrSH^%ZoW$gy3pUH1D%Sb zq7ImZ1AUz%o{fSv8_`970`TiBo-htJ_U%^sq4+Fz#BYo2064lzjzX3xU1aSw2Qg@#}3i<5lE1z!{H(p)|zXG3K52h8cWE+d!+O*m}1B?}=M-p;66^-F! zGI^*f-wgVp!d+n^aR2ALSoQCiCA>TQk9Be{cHkFQz*GvTzFxpo7xCz1U)Zjb@LC@a z!nHq=bnV|~%Ahb0Bi-eKIOpm?(FhsyiPdwe$43cvaxriPtFBicW+oFoim|S%_pPQb z{!=}6mN!*nXQ^W6rgAO0Os6-MbJoqWG9Kh*IUoBmyI-7_^r_-a%}2TaWUhHUSO2rQ zdWE@3*XLn-T@>)LaDDLUiFrFcoPY2Q05!|H<&=1{A++c-FL4nT9lWMVcG{c5iBW*Wyq z*c`RPxEVV*WbtIAwfkjfscqYQJzpaka+%8+c8!(}&0@Y|$k6i85Pq)Sny9n7;!MK> zLk`gAedmrt=3H*yVW{tVU~ooghTm@c%b7albp_Ui!9|j$@viSCSTAxCQLP81@8|Z< z3;S3rY;{hZTZf~$)#n9+2eB}R%jv^H3_D}d_%^hr)ob1j9ksr*T#m)!VL2Rj#Ppo{ z$^q#ThdV0&*dnMJ^TivNZ{vm-BPUDouow=-l%W%#PAg-li?xLyRN=2fv*<$wehR(x zJ(y9fQLFB2dB8XcWMGNP_*J}>6w(R&YHL+Zs&Z}Bvs1OFkJ$-JVyn8nd??;`!Rz}j z@Jg{LPSeq;SX8`?as$utf*oEUe{ZozF!BbUR9sG3u3}Q#f5%paM@)O=SM%iNtjYCx zzLJDzaIbZj_33ocX~9yAm&F-i2bP^yquv^dFCA@szd19#pDw2L*5-V)h#hqfn%qNi zU$(yn#`n8BfWtGMYCaN16jH-kwWTY7Uo(XU3$ww}yK zfi+KcJ3fAwG>3_LA6Drs(6k_ZC$^f2nYRB2ij+$5Ye-tm{zaHuL;^|tieCEJZZK&=a4&OF1D*Pux&*D?@l?f+$ zq962+*QcL@Y0Ou;i_p3OaW5+8AcaTL6V4O2^mBUqb1-<#vxgsvP-ps)lhNSAe+R?& zb#2lQC+Dk;zFzCeV?Tw>yH-2coYgz|8mBK+&3HWja&vFReBbdV&`!5^--tC{Fq6A? zCo)8Kxr-2t9*mf4X~({|j;nz&VC2o+n#v&u_irj5r+-1`O%C|ketzH)pYq}@QwW-R zf6Odj@F&Vsbq~XQrETGJEO|}7zVA^Z7=Ho*fMboX?s5v92U(HfQTRmSVlo;Wry8M`VOE8AmoIHs5Ei(_WVm|ilLl#I1Y#*TQ=OL$32 zcuCg0oZMsRpvB1~(VNyNO@g2q#3Qrcob)G?=GA0krg1+tHO|X=jM%=KSM4#(&3gdl zt7@!>4d-%Q`)uA*^$=s2pRw0kXvTcvB5Lpe?5kH92$4|_+rzS-wXrkp4R6rz7j={a z#;v4|58O4kxPo!O(+aih1`B_h`;sU9oP1jRyd(=m)ttc2e3MZ00Z7DAXQkMaS3c`K z2bXtej!d07>Xmq1uQ~a?W^YZko>8qi=ZyxvfbyT+gZ0m+;MzddfdR`M-*t;Ru&mbE z#DeQ!rfGXHvD5iU?}{jBNBb+^I^)daPwDKxJNnr?&j@@@s4uB-v>e`Ie0qfOWf)qL zFOuVY5g*Yy!qj;wt*c{Nqhr3xcrDq}gn7x>aV|4U_m~`w=_UK>V3v&OC1c0=Sci7W z*fB492`@#=IRm&A88<)=S8v`oNReYqMXYJ9`%npnLSIXrp%gzWq?I;Y>--btQ=<^LmjCiy4N{F7(?$MZ})N*uF4 zv6?(c+L&jq`fbcJeXAe$`$3xad0@u>B^um1-C0RR6=D@o1C zvF37c1poj5|NrcLZExGSvhe5lR|HmoD(DGUh6!1gVPI=1s&KqZjL-J>f{H)?RR#g!r6%&J8gwhc) zB#*ipxeN_cU)Y_RqmZVy5KPOaUZ_jdHYLfaYebh_ZML|RsXLa>I>UO6*q2R9H#K4z zs52J%-_#U@(3m+`Bc02dO^l`+>UTEP9ZkQpY)v9{4zE`4*uo__@hobvE`3SY4D3aH zgr<3EYN1Yy1!nkMnxrXcG{Ub#Fo$Cr;o@$ZAJ4cXAvG7KWC@fQZrzg%T9;ftrrp#n zd+`_w_8s}X-di3|rw^?LS<=z+x6z>Wdy6bvjnm`Cfd1C1kACNUmc8Gn57XmDhxh=q zwOo#9>$kxO{Z7V!SGErs{XT?m0%@Mu7L^Ri4W&C<(9Hiy;rWd&T9Vf2wYA3Og`uKT#~{wpr-UXN4PC?09qEXk z5Ko)`)v0lM>7E`uJoo;f_YG6C+)xQM3hh1}kw_n+c{z@59Gy_fn=?J=)c%6syg=8V z|L8s3(*~;ASE7a|h3+%pc~m2x5*Y~{&4oErPdd>$WL~TN70nUoeb=XpPa%PCHohbQ z32;5UFpi9-d?2|``J4pNRZ`h;IhVe-XndKn!PptP}gm{*!n|fe1 z1*v!c@W*4F{Ke%Wz=40kY*8~j;=HRqx<&?{NZMzi^KbMoM2L09$f$)jBL?}4QP=uJ zRFGF@%B6>9?+xOcnQ6ba}XBKL8f%F0QyU-SbE*@sq49^QSn+gJ-+l&f#;hlW~ z_M*Y;za~g`9Wp7{B0pz~=0_1+SUaED8U{Q|zO8NFV`-n{cXZz<>fpR!vp0TE?Q7FD zgbONZw#4nYOPV@0E@r=2=FBu*4aanWcKQW11jD07KRhCu#eIdiy$6D2O4PFjDu6FT zG$s4H$^4Gc);u8)*5lb1%=}6k)x6LXY=P7;r>lFR8w`--u{B|42__TZJH=XPx!-M9 zmn=!k;ip_s?and0gvW-fU)c1{Q@ng%?c59<2?J8|Rv-D^?Ku6IQdS zGdg*WZflODorm5<+OIdV?MK})S|P*9ykv6-IIebc)N^e8Q8L1ot?4J3?;i((cE`}a z3}SzB)NI>b&T{k+iL4L|t!toOW77`);0 z*|U9i_ug{tXSNmvCL4#X5%d>9Yq;m8G3U3&(HYG{4JCe_T6^$ zbPX~DYCY>G7;w?;zUI({1AUlY+&$agS$L-{OfA1|1#JGt8R&?9$-J(+nW5;C_RM|r zyXUi+sY}9hD4c0-_)GAN0fnKk5D1Pt2Fote;HpjZ%XnxU&0I$OUM zmluqn%!lTBZ;)o+6POHU)(86DaU{bE1w&^`5}j#x{cu7MAIE9FH(0DDjAL77HYMgl z3k;rz{W%&=kSN!NTn8P;qvuDOBaqphjAc;_*pC2nMw+HcrMm?S5^TZIS^Ng;WULeC z%qKTZVny*7wACrJ)19*;GM8nP#u6c0d?e347f2o7v6)jH--S)#j;&GV&*W!}=BldV z0I~Q}J#uuy{?{>CU$&w%0W?f|VcoG<)2Zu6{JYVF7}QpX8P@Bj)gd+W=lRcA#l9M- zs*giCT8|YL`fVADuVI}d;E4%qBy*Y^zHTW;W;XzYF;v? z$Hr8eP9N4$7NdeM@(I5E*XT1$CH`+5M810Le|yaT=KhgUU;833rxgD&;6KKpsA>|k zL_~2|G$cq4RZ8a&|5h)<)$G&={`qG{S;o=;=<7?1&|C#bZHGiM(PE{Npq+k$F+yhl z4V|(@ashH#H>GgF{Rk75{?KMNJv2$(V&4ql+dSgi9H~fkU6aY1!h%ye^Q9GTs{uLi zTiM)P!(@N!cHR*5F}EZs-FZ(bEq+&+u@w zWXl1amd)wm;RdtbAC|N=x>?d?>tR6agXvCvVFHJ7ppJ)(f6#wQ2RDP|Lkq@X|0X5h z%6P?bzZpz9Oqj!VxJC?D2Dmb2aF3sk`J6w}`w?FGAd^q@_?XXkbpLV1XcIiO$#LtL zLSE*6^>O3}xLjVdW9^X{jOS`F2ihYsg*W)^baa1AKR%68c)yKK2gfkpE_kQ(w*eg; z-`78mHs;NIlDZM=q6qMCfRU(9j@74Q;MHLHH2r(^ie#d0<+qO9aj~`BtkB^rP;L(Qt zVNj*SMld>00uFoPKZxpvJTsYMF$`ZvHgsSxpi`5E0$YE!%H5XsJ8@#`O~7$N0q&30 znG^~n?9YUnw5iXtdOxfS(oWif9K-sBu{t+ZMPQCQgBbm{jD~_@I*J|c!x2R|BBc8& zi{GR^ow?lZut-Aa!+P&>J5xp*hNeK>{)~FsozywmZRb?vV+PCz`LtYu*XZ5;otqwE`Z4C9UiMjxH6RxH?{jBX_J?=9;Z3qAymk5xwZWNniZy36XsR?ij6 z)PFAO@9E=^lk_ShzbhiU*eSw)j`%~k}PhAc+BWKN@U$wG@2w|^uZmyfB@O9xAQ zP2b+9L>7Top+N1+3u-IO?Q|}+?dz=>pI@O zCNb;o2WlX)@smExUo>s&QfIz!3eUtW!re`C9kc0QnikBf)JIzDuMcwMBevwna%2c> z86Rfo=~BaGKG}*fCZT=WrW3Tc%9(4pLS5T!KTrZ6sbUuXrNnu{<(b7_uI367@U&wp zJK<67AUX3R|AWCsGM}SKFRTlNIZ&F#VO|JqcuTpkSU|Upr`a}p;mK+sb9h4zZ$|qr z_;)a;gtysmJLk!4TcUS+?T|kQnPTp0BvXBX&O+uM+B&mz8cD~C?NXUdN^#R@s0*5{ z?VYO#G7NJS)4t4cMzD;^A0o_;B^tbrrxpsAG?!;x1;4;bK!sW7v3-Hia^0)y1SEjNT z7id>EchiL}L4eDctwkutMR80P3x`TP&i1t$c%U#DXYp^iSI(F_%@#W>$8yFZOKzhS z7Hekb9NQ$iQgoOfDQjD6Z?$XO7Bai8bo71rAixLt8M#+n8mova?CMJ$gBY7<&xzfaZJ- zeX1-RL=C|XHFY)2!8ND@i(}U2a~y5Q2v>qO+(n!0xO;Kpc5$5A3ZSXu(YwA!XV{J6 z=9q2_jOWlhufLkPI7>T^1-_nh2R3D;vgm4u{AAni^g+jSb zJm7soAApz8?Q?%W5MNIFI&(dD$61lSGl$ks^gTO9)_=?5vv18Qw%ulT7M)r@$rJUn zd7^%lC+cVNME%V?QU8Pp7VLpg=P21ziS`Ei(f(9Y-=I8m7{J4RoLiy`P0>QaoEt_X ztG0ms7ic52R{{ImCX1%9ppFyebg5%OO$K}qn}%sY_A<^%!ah*v@eQMe)$BV8?7LV2 z!}Jq^eQC?k`u}x4N&MeIyzlTA?AKWF{uJcW%%dnD9PeFNFs}tw7;wH%$jojqk8+t- zNe)ireUhA+UN7Ivtvg2?rrzZA(llkk;*(J5XmyS|TRHh$V>s~lLbIi0j|nqgS+EBM z`9dtLz(=+O(p)6CI7ieVmd0^0NE2#Fn5!dk`FwcO`{T`hgTqgGYypq`PgaJ<)+Udw zZ9En%a-vu?2bJKfJ^FczLgbOu;o9SMl*szn565#hq-;An=G-~#$f8HFh5PLI6dd&IRj z5uQZpb9w|!KY?DXTi^LFi#gc81B<{IT#llBR4y0MK5jf8*h?#;1&V1=N14fX(m z4vxjgPv^K@*Me>OiIcfP+xijNx^)!Qq?`2g#xMlI&!t@GVFRaSM>=I!y64r3ZKbF2Z~+=Xrn2ot$B?<}Sk zp&dNocwGv%24m^ewednAb0qUI(3A#y$3S@B7-;_({=PBB`^S*?jWORphPZEx{WL|p zY3d(BQ-3#2{X=N#@207L2u=OnH1!XmslS`1)^we$`WD!i2*2pmD<{3eMp(T&|O=v zVlNJ*E6fS%owVk{I_m2fU$3s4?Q8hG@6KEeaB9l5SDSv`TKYw4j`B30@1Xf1>ziG7 z^(c-!Y<=sIn;y&`;$-H)B>rN(chdvE*NXjKT61>#2`iY*tK1P zjxiAM+0}`A_YtoA?+j zYQpdL+23J*zeAQavhe;Brny->gnf}AM(SH%#OFa22ZPR9{TY)q4Qvci87DuIhu-LT zN^S;IGI%`w6ZYA?1+`BVIvo!NPr=iwy<|AR-ouJI!BxBVpRg;L&VtgwT(w^srabt6 zPdE<~XJO)3fH@!h@r3d)Q5Gh8A((OA1NM8U;@Kbr$7B4C>CH0Ep>TMhN7=t=&5U#r z&sErG5hEOY&_~`*p_0RFtEDlk0c%D;Zq7xMPZ*Gd|jx`5Xr5q`oVZ24pTZb22Z&4 z=>Hq=k^Us1-KUCVdzu+iiwaU{Jpn^hUzrBTUF)X%@G!#kwDp1SbMrlZ*o(b#YK@!6 zZttpBYcM~*3pFatnmWDORcqS)(E63lsV{}pwiOTRB7sIX&GNCB4hEoOz91RJ z8X@=FI%Ev`{VTw4kPoLYPGqAXhvV90A>u+I@4QK0h>x zNdyhA<6B;P1ZyE%>+M-xARm{^qSlXFe9R<|;vG>Yn*xhP6-ILIf0&v40Y6*wCar0D z!}C|Oz5x}ECmIbGlF5LEBpS0hbDhwp3Y%8&KKkY~-_yQnNRDB-5zWj2xqnxGcv?0( z$5C!Kj{ov=s;BFkh17}KWk5`Q@^GRyGtHwk4M>oQkI#=CZ>qBkYx{`kF=HN89zzOtK z`<~p2f$Xcpu{fy(uiKUZ|Nun&a@weHPG% zoc}9$(U~YWlyt#f5GJ3CUp>O%GhFyMAS;l6w_SZP7x-DE(i)*cJx?mXcJm@sEDhG_ zq^8d-&dDsDlbM@SBDauVfErpd6Y3v6GMbK#i*oA;kke-VoD)WS&VsqlSJe-p`){xN@Q2415=YRFRyDt!%4hg%>c`;EwV`{?Loxdq3Rp|? zl3ebJah6x`vx~9@^`#((wO>1n4<2dMPB-PXGaql{)Dz!&hyC1|YdTc!22aa}&$Okv zGbaEa@|Pf=3yV4~1HrT+6g1nYL;g~?kKXrq>3wK*r&q1o zuXcA6UULh)W(@D|_#gjd-C;2@i< zTpEzGkd#E`U&)u*nahsWfT4_-hN$vH6yGAXxNkqX6^AdVBk8_=;@h0Jx@nxjWH74f z0UxIE$a4$ed+6QuenZwrFV+-5ya~E66es_ubOCDik~zlquZX|72Y<7Oe`4nahe|VB z5}rtXc|3S%6@3)jI~VF2QJ4eiz-!Ora+=Is7+q-AuApnXV0I zqijnsh+gm8edoyNyidns+CUA>x(pdDqcc-qalP>8YJg;>4t~J>{IWV?Ojxk)$>xQdJO7^ ze>>hx<&_!M1>X}i1&&LSBepfRtms<(#!`EoUNqJTTWdmxg1<@Bx^+|U^-_9ezUTHA zNiF2HOCak$QUg(DJ`$d9oE5kokzp_#R+jhdxdHRz$Y?P+P0pn-`$C4d12*XA$$EBd z`f=oZs9iN~PI(@B(Td~7uNAjevF*t@hwM3wZ8pBBpXR21rap*71r{RA$h7|P!|`(T zS$17{!}ljr-=?r{K8)r1|FRA|4F=Oj>-S@@r(}LREXE7>kuNkza>RXw+P21~0=fMs ziEf->N%SD8i3OWKAFRhM#LZkjog-Rnu|G4l11!GywG78^-R2kPQ~#E7G=C=_ljy=m zT}iA57G+LCU(d<4(6r(51TN1OsjIL*nb0fyJtH^C{vH!^$owD>e9?c4)#OeZ#^dx1 zhe&QGiG5D#!|k~cd4wYzaHh0!tR>vu>C z#j6k=gnQ z7U6sbR>g_Te0<+j&n34%bFa1V8tNw6*Vjb6W%?loV{wQp$-Z=M@_Gv#Qkv{T?aJ%G z87AO!dlfL4gLK~j{Gr)n*E+}4WF9UJ5T(RMx8h)p7qkIiX(e(242qBq~VpN2tJllY|2wwatChkXnzt$58{cE1hw_VCQ&=RA=~ zsU1)>Ah%c){UEOEJ7nK4IU7i^vzoKtH{$q5(%75V+D6yp_pcP&pZ85^rnznieCxEo z&pkaAw(cNj75vbh??!jzZ(eui2kXxK3+N91p*!D=?##b=-4PGg9q|k34*H=x-;M5w z-@NV&57wRG7tkI5hwgkgx-uv&Ud3blW$yiQ1-0JF5N-WD)<7r zBmdBy??ZRcd-AQ<;vlGhIZ$`-7toy_d!yfv?tJt0IEU61pf6BYfPU9cO>$3xIOGoii1RVO*Cy7p z=p6-gyVjHJ`a9UO{(_Bp5GdR=mb~Q@o#!)L!PF$9y~63eHdSeWLS+WMeYRDF(iZwyx=y%!eq_5&C6pZd$({zkvj`Q0=la<(cl^0^ zKEJK!YIpf6hnzQOYvZ8x@Ofu!vv0No{Eqo1Yp-10W|R&!ff!cZ?(2?m)PJ9h1@-Ol z)EtW})TUaPRPYMN96ede8ngjJ{+M$K`S7 zJsG^?_o6&BvS-it-BoRt-Q}D33UDWJ-?DXP*RA9|x6fTm>ollz4!F3c)+aY#(>K|B zR%NGeg1#}|D$vhPyGcY+Oqi7#h!1LZcWxy5ERxy_;! z3$tJD-kXeCw*eW5h`+by!@b&D?knJT957iEP9-{>Fe=^NkinQ)RCxGQ9{MD?$1HjK zkm36+)Fkx4epR{Gz#w%#zwh_{GF02Vzbv}b?1k~r_;&JWRl!NG6bJP#OnC1 zI!A`6av8xZ4DTe~X7!}(zMYD94{|$XNaiYg<|6Y39{2fKTrdgHFue!)pB$r%f5a%? zPmD7D5u<#C7)8#+DCxVHRL~qaKR>x0U{#jW^YiDA+xIFCw5!ZN8U%qjRx$ELus>z@ zpW59GdkX!)8&QV{`!$)QcO=Cy7`}4p{YbS(9*6Wg4}b8rf5V6O_W1B#(TDdo-qcBa zjqKkAJ1_>ETBKL`On&z5=^tnD`C0rIJ)4rX3Hi4I)40Ua?Y;)O`*(fnPEhF{zYX8I zbCcd_EHXm@_F@iq8iS0in4ZDg42Z3%iJm;jrFU7DulIDzdLOOD=G<7dTd^-6zy0fk zEVyI=(~9`*TYoSK#`5}(vww81V*Vpn@jc`!=09>3Uny51Zp&5hGv4w9e=E6)Z=s&( zN3P;Uauwo_T*cSORSe5>6>^fR2)>P6#qdY2;`_-}48QMO1=LBZlR2KN6BWj^kSd>-QQK#2vIdMRYtgp%!vHA6BV_ z%)_V7KR!mNlt+kY#_y8uDBpLC@Urgbgw=_> zamV;R9~<~(D4}Okyt6JTY$}H1(YwA!XO}LG)~z5~?_kZE6nyP%Z*(PZ+ZEp2ooD^x zzCe??Ie^nY^*-{?S?6Z;z8g}-=y*SL;|s^iFLB@h+*g^Oh~W|7ISvCgmF2dINpOoX z^IUUrE`Dk?{_QXMdX&5&4)3qDGVe>5+`Zf@=*_R$w_EPnngefLCqClz>eqCvDgCvy zMuy4iKOu(XZ|P3SuchlrRb67z%xUtSyln^Y6^Km%j&fuMgkrqapY*rZ=l!j?a!dTj zb3o%c^N&>KvyDX``)`BTk5s&naniZtYYq4Xx61lW`1=ugmtCJ=ExMzQ$JQPf{5%#z zGEq^k&IjFXzdQHqd@)}$=$!{X7Wc0by`A&)R5140Kaw}(3+;KH8Ea9_D*KK&vrFmT zS6LrVqc&Ff-Ae;_Q*R4C>G-vFO0RiDuep!M<@ADmvK5n2$hl|V7k@|Yvp()dA1Y|x z%2qJc@_!g`|MNcCe=8fm6SR}JY{$&u4uD>7{c-xvdY0~S?40Zw9>mKe-c~$&#qVDz z;b+oj!eZQAG@NMbci~@~uR~?k9_+vc_9b|3;eP9UR-NG&q^-D{w&EVzieHen^FwGm z-$UE^7o@Gco3`>E+R9&$w&O!+JKjUv@fW16znixH9@_d}khbU$+M+$QMPHD%csFhF z9@^qBNZa5L+6H@Qn_bIfHIRX}NGzpol6MXQHO(PCzFY5KL#&p>y`H;&onOsd+`+F3 zKiCWZ73V*R`4hcWalg@K;;v;yj%5YGetn6o0IpU18ZOJja#>zc2hJ6j`8fIY_l4;p z?vU4Le{z#X;%n1rzLiGvtu&gy9*yLkG?GhcB)>L|##?DL-b$nK>(R*HNh80MM*eHl z2yLYi+DaqzsdM44r^QqbhpK=(N#RT@82oAK87?Vl0yVtq_BxHD1}+W1R46 z%wps5`ml=PH%=oV=GiaO4pe-_kUQ1^1 zE}6kwWCp*Q%mmwICfFh~K}KeLkQv`E$PB!9=1Y6y2ADhSp8_5}%)OZ3itn0PwSD|L zFiUc3YnZPxPXsx$tuWE#bzlzjx(IvkAp6;TSMq(hLhbb)Nvwyy>KF9TSj{AV-x{0T z6$JL6jl`S|CU4?J-|utZk;EMCwf^~${`n}Ii%w{!`nzN4WL{tg=4@^S-2)mq@V#J@ zV16j)OZ#fzbG`F(dIw|UmA}^>!Mr?)=N#ms&SmbvERhNMb!1|^MJC3ZGBJKNneeyB zgkL5T{%gnt+9DHZn@pfrkqNv-CUCh-yoxHn%c4gzqJCh&$rT%OUek=4EmizrVOChj{)Pa>(B?+PX&K zSFwlu-LdU3$FBp^-v!fu9hj(8$8k2#oqR{Hrf+zQzTq-`!>^%l!4`cBw&`2&^7=N} zj0HFj?bT$14ijnhD!ka@8xG6#J(qudAsUEVX|U-Rimye3c_|G_ZQg76ge7@|m_=p5-0RG_+!k)+1o)g^!S5@{1;l(WwS%uigL0oQD5XKx z1|l^;1sWtZsOrk!X@`?`QEtZH@b{A6*>9OO5WyOVvTGpZXCX)Id%N>NNjuM5@A+os zEcqRIYZ{}3#%N9Bq@HzUc>b<6H&ge@*W8Rx1vze>L(cBiX2#8~btqcvPcwR0alQ1f?<} zD5j&>;VvK4v;`;h6lz~7>-fSk1)GMsxY z1FryXc3K`G-&d5MI zkAf_w-`gv+)(L-tne#gtXLKSNdu1v+bu&BPVjW2`4@b$%Ve%c;s6-!t1`M{3ChMA! zEY0@lWje3OJ_M=H5iu20F33E`(*&uRZ7iN2BzKRyDOCAImbWG^C9qjSmb%MMw@$i9?v7?`I4;x zwRbqjV;hY>$8$bU(x+o8YdPn> zt)KG&tP4}2#)U?#?Kqh9!n#nHzoA(<8f3p;IjOu~D5hm-7u3qw`pDn$QC0@{nZ($> zY?XoJ{C(;Cqw~+{8NHMTneXfMK9&K@{(me3$=Lh$KjZO=d-v-*L^69V@%<~qjQmII zyU*5loS*wp+HG5s^Tfq{`t?0W>o_`YyUOGa{mAD7e&e+tALF;nzN~4U-;+=9nP=A3 zq%CWgk#`L8&cLtbJ;86!9ww(tF>cP>!I0fYiSNhF`gAYC<8djE#~VBzzc`QmG9LSz zJoaCj$7qAcsFcU(MR|l`R0IgDpT;g zgK2!m+}7DzU{FhQJ>7t_NPO-n@yihN%O>gE;Vue}H;XhJTq5V>-G5RV!230q7m=Up zTxzl0;WR&RGwSxPdMV$FW4EJorS~Og)`p2LpvaFyOcy4pF2EfSus&Y0QCE(%kx&26 z{kyDe=HP;i2DzNV=%&`|r7}_&8)Rj1?`@vZ9szt7gXs!ntv5)-Y%vtGzCd!P%|2fs z+pZ`_$z2ykUm)8j;|rju?vK$5uW4mU;UcfM`TIN;p_yC%Ln@h9il_nMQ+OjKKg zSco0G4Ky|KmH7T*iEYrx`gf2Gpn2kV!Mwn~(7Nk3>wHdV#m(t;$6!5t`?M}Kq*|ak{vorDC1)6l{oh0)RbXx+S?2c+4 zl}>m}oc-33PS$+k_8j;!$4a2`n7QmMp7JNj#ocC?@x!sXAEexObFnr`Y!?bJ#8or3 z9}+<-le4}s3sd@s{h7e*BG86^U)v!JG{^oVqB-2lbV^4bmb5jxS<)qa7!1NGWz;km zWqi0H4-X?uPg@^Y+tKo7uza9&Fbz%S>3fT4J~!R%ZJY(iiQn<^VZY_1gWu_KYZo4DcB7}k zVA^Q?eoROA9}^uc{SEZwxchVrycjH>roRsuA}#u{Hi~2cC+8VK*4R3BtVV5rThi0x z!3f4E^%;(zjyauA>2Cu%%F_ep!g%!C=yY)Wk=~C$2A}RXzprb2Bl$scw1y{RLz^8r z_GG>Z4WM=`O9%elkLxND8r(1GM}M^5XJqr2qxs9+S4-xfwAA`Q4w81;a{I?*jiWc>dCv*>FWEUV8H5_ML=F>r&;$_=TWU$?tA>!V~*!&w5~II zDV`@aW(A%j*kdg4JX>G(QaqQ-c`ldmTz+|;k2iTfF5&t3Re0`~@!T)rx&P8UN85Og zN_dW5oaeZl=eUID_~m&XZ1OxP;d$^HJdbL{a^JDT?Ou-Oc(j_lG|z`|{YZi5nA^QP z&vB-1;zfAQVq&qB=UCk2ITl}<=a}2F0?+4h-AtAq^GyBF%kf+;{7QZQ=Q*4~JjchfC_i3a~fq z+hnwQahjL;Z}Hi)oD99RZ4=Aqyy3fvuQBHmyB6iP3v+&9zfCTm^M*~6Ut`WCK3jZV zEI;QLwr76%oHzV6|25`ZV#}iZc45vh?5pAOIhWb7m!ETqpBC@6=jWWYVf?Ha%z20( z0u}BS9xSIf4|LFi9LC^wx?Vd5@!Ik5C)sG{P1pIF0jAT3o8@5CqNjrobPDSSYt)ZEMCkLWC4 zZtmi%%za)q_j&2u=Py3@T{)KA+~rr9`?zfGdJ zt;6NE4!^Xm!`o~fF0*y7G51Ydhs$jpera2`C*M-Ab+0k^OZWz~CW$_$lYMow+ z=1@Dh86R%iIQA{gEy8_=3_il>ZD6W-e|uX@46#bmEF@tq(K*O;PeW+lIbjH_Ff{MYsYeQRu1q{S12csNq$KBlK@U>eI<+)EFxM! zKRA1sIrqfRUx`r;gx}}yP^FXx@xA#@T2B@KeV_SvhdOCZEXUW6&UL{VB%&Xc(IAAk zB)p?2Z=*1B9yz=&l7DxOX!hNmg=tF`Uaaf*;EbfIA`CjCtIknb-JDLGqXg%8Y=`Pc zj>qHx=6OyQ24T~V?_!-y+k|#}5$@o>hr5^#ea{8%bxPg|I&UrvNsvy6r}2B|HPZa$ z$T??<5?W^(!CPPtBiQq=0b7h<%U=WbJc2#`8nEREw*NI?k0aRVYrys+*!XL}MiK1b zYrw`FHky15*g*t)_{CwvI{=hSQBCBv(R>f$z&C7p|MdOk#kp`INglkH1#N$6Y7RX= z@~m*CVRFXovd3*av~whq+?z?zl+K}cd`0eI?K$X8Oo!BY|M-oKg>Y_2o^+zcZ{Rc? z?U!@5ZiL#*BAqi_yY={5$lDntx~q?f?Ws%=f7>OvU$qZ?FU6?y{`?(}1!>2th_6&H9Ym=|R>ww@X9lkcNV}DZQv4S|~ezmSfZ_?gMTn;XdjF7+0q!CLJbW?&i z|KRs4sg}Mu4CiX~uBYqFk@SU?3j4LpAEb`c<$fl}&H63#h=*>I%fZ6)Nb<%M#4hmW znHRXE&U=heP1!p{hES;t9SYO0g;$cPEU4b4L8UjL z!)DYkqiealTflCY-RT0~z1mf3W7}%bO>8mTQNiXCpG{_MQ94GYw|bMl=e4Vid$xzp zO6>;ivOBNg%x^N6+&%c&KH0nX9hdU+x(S>uZ+&g+o4}m_To3r0=H0~9u4L~- z;WR6`uZ6FTNnd!QJ9$&l)T3PD=3TB>?T**9NbVa{F-mO&oKtibl%AX2^qeE5j%n1c z__<+9u`v7P?!9TVHam3Wz&F^F`DX7opyy8coducmzD}2#*)zHH%B=O6PusN?S|962 z*Vn6{EnPPihj~brZD}r(NH*Xa7niMi^g`=d&1tW8HSJQo=xdgKeS}x-;QCr=O3bTc zJhhk%QkVCPWe#MMkCBCCTsLQZiOw|Fg?9(XJ(`Rg{EcyOaa=hWSL-gUqrQ%V>(zC$ zeGPpb>)f`erbl_#SZ@Iy*n)-B)O4$Vw8Gcu`nuhO-Z*eZX+Q;4n+LsP4|2s~FFuEOU6gb2 zFB{wNNPI7dyb=Gd`;^OR)@RDf42tPi_D%=vd!=*3-v)1v_pdgH@*ipCB0mmO9lsIQ*do*N>5oNG`T6@nvIJ}aZK(Hq?Y28 z@x!Fiy);mtk(FE6CxV!#0B<9%2v`JkC;T$&ytm8vl#gxFvBoLySu& z77p8*CxywLMfMxSx>r(-=gMvdQ+_@Q?%1J&DbMTlCFb7Sj7`k9gIN5gxq0pj?iGeS z&X%)QTgNFm`vrF;Lq09xG0*vA?}38Ya@YMsERNlEPY|4;%H8YaoY0N?n)jGZ#2 zdPbMI{FmIJ#OYNMKjmmw(6^nmN%n~nf4fMR0vvuvR7TG^o+jDQ|M+`)t}QbTuZ2nL zud2i{iOwZ-&Dxu7I<>wR7mnnC{tVT(zMs@zI+~$7p=5CRguT~`fEXk^;<+f@F*L(j z>k!PxF(ACrBx;0w-{<%$UkeF!oKNk1Z6?$jg04U=1adpJa}FCy6yyiw8}t!FJ`?%D zqTNmMT><2~cJ+Zbwb-26+P|Wl8jf;mV8^!R)u7HlX^#$QKVD(=U&D4T7icwS81nCB z`M{MRiHr8Xk~!dgbC^r3y|f87X|s3SB5e+tYnC>_=gJJXL0wgBVp}|+ka;B6B}1Euh!>< zVJ!gI(4U@Q2kd0_oH^K#Ok5b0{*L$jj`sZS@A-Ya=XZI}@AEysi+g?_?)iPP`}bT- z!2H-Jj}+`NZWq?bjdME1JXEpnd>;+r&9PlL$op}a@5Nyc9ou-g6Nkwj9N>K79vsj< zS!^S;69+hFx(A2xUL5wwV;jwP;vnwFVYnBEeKP6qlS#jb!%lm-qIe@Wx6i*Q#=#cZ zZo?_F;kleEi=}2B*=3Wdk2m7=eRJ5zl=RvX7ai9LNiC4ra z*vQ@OizTYhVO(hra`icE>_P0ELp7NVa{E08%wbY}4!F3Vu@5I)S&sso@of)+;eQT{ zaWxq7=fId(gCTwnjA1nxlj<-~b)HwXIRUE9^J*|E+Ner?6pMu`*(Z1_vl{M|Y*Quw ziQ!(!E{T{FwuV9CG`)a(cWP^D73TqB;U%~$H z_SN`X$@cK}74^0ve>Z$1$QQ?XpADOl`)v)!&(`V$Lbd$(B(6b;^X?j)(JtyQ=&MFU zexAOdt7%TG827mzNpoP?b0xd?3xdzi^UIleBzd#!-on0If1o1%X2=``>f5mhdu7{f z3P1B?kc&_{A{%YUOtN%MGKnA^R0~@Zq^pF!ffDTxMgLy4XSJ(+IoZm&f2hZXx_GF2 z4ouojYM!CiUB6nNMd}9a+&QJNc9qsNB(>M@ZfZ84>fi`};479+Aop3RP8sk98?QBU zIbis`@6KFJ2{qcB)85sz2K(BdJuWUASB}OF{>HdL*|_6q+{HA{r)@lPr6$0*utKfb z=}mJwR^02`V_P=zaJzF1t4g_~Vr|{tb-0lG+=Kf@{%#lUa%J4-)o>Rp;l7dg+lBk2 zBJROv{&i>jlDzfK_NZcezhe7w#r7pR@15=E72Asy+Yc+YFUgnh;qOLXc@KZ9wMP}( zm*m=cJ+|pk%5;az`EcXhX;5kH_BZ-ht5@FakN#$VzjD1a)a;bi{l#@cx&6BWJ=40a zs`%30G_3(YurAw=>%9`*9bAtMXZN9YtSY?t%zEy8yHYQ=opnLldQLYvlMDVC^LvmQ z%*SvhS5eEy%GNe1WU~#DD3L5pmzY>d8OtAj+AI2L znV2NCnTPlWL1n)NSMzI7CBJ6l&VXIGk1OLYSHpc?33ssy?!(HsPb%SFtTou*z8YWK zxSDScZ^u+?Kd#um8gJXUntu-O9aU>Ttk}LHe^EvLqKf=Q75R(u{FOYCt{sIM^3OhV z7T0L5`{TdaAN|e#e&sWBBG?g)q-WK0XF8&~dGt9rr8W4U;ok+H>EBg_hs*8)+GZa+ zQgla;CvcxmA!b-NOlt<;llN+we}<5+2IG137VNgMviIebwIS5s%%`F1`81^Db5&g$ zq&^!ushn%uTZg$j*M>eT*A|_zM}OmtJu05DpRdpE|D8Jlwx8Yqdv^kCziZ&oI|0n5 z>s}Z%Y-(1oHeKhX70ph4v230@&Pf-~<{Z8kc!=+UEBP)Pb%lrT1s;NXwY9uhH+Se> z;32q+m2t1Oju-3gD(nRw*1j5FaYg@oqkgo)Uf^NvtML|B^uaf3Pb=&N9@f4Ze^EvL zZq%(-*b6+YeSyCrN!O0tx$Dfi`Xt9+DUVZfciiXpM}M<_<$D1{9y_hiu4ZCwl;*b3 z=jFDNyFjY?cfn`+cRX)U0UjoP*}aKd?PGkOpt diff --git a/impl1/s1_impl1.srr b/impl1/s1_impl1.srr deleted file mode 100644 index 140bf93..0000000 --- a/impl1/s1_impl1.srr +++ /dev/null @@ -1,1747 +0,0 @@ -#Build: Synplify (R) Premier O-2018.09-SP1, Build 3588R, Nov 27 2018 -#install: /opt/synplicity/O-2018.09-SP1 -#OS: Linux -#Hostname: lxhadeb07 - -# Wed Jun 16 09:19:13 2021 - -#Implementation: impl1 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys HDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys VHDL Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@N:"/home/hadaq/mmichalek/lattice/simplified/trb5_tb.vhd":8:7:8:13|Top entity is set to trb5_tb. -VHDL syntax check successful! - -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/lucent/pmi_def.v" (library work) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/hypermods.v" (library __hyper__lib__) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/umr_capim.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/synip/hcei/zceistubs.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_objects.v" (library snps_haps) -@I::"/opt/synplicity/O-2018.09-SP1/lib/vlog/scemi_pipes.svh" (library snps_haps) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll1/pll1.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/multipll/uart/source/UART_VerilogWrapper_TOP.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll8/pll8.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/pll_random/pll_random.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/modules2.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/top2.v" (library work) -@W: CG921 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":181:21:181:33|fifo_data_out is already declared in this scope. -@W: CG1337 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":270:9:270:24|Net buf_rden_falling is not declared. -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v" (library work) -@I::"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v" (library work) -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":170:12:170:22|Redeclaration of implicit signal decoder_out -@W: CG1249 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":171:12:171:26|Redeclaration of implicit signal decoder_out_neg -Verilog syntax check successful! -File /home/hadaq/mmichalek/lattice/simplified/hades_modules2.v changed - recompiling -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":757:7:757:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":761:7:761:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":1696:7:1696:13|Synthesizing module EHXPLLL in library work. -Running optimization stage 1 on EHXPLLL ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":8:7:8:10|Synthesizing module pll0 in library work. -Running optimization stage 1 on pll0 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":160:7:160:19|Synthesizing module tdc4ddr_short in library work. -Running optimization stage 1 on tdc4ddr_short ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":236:7:236:21|Synthesizing module output_decoder8 in library work. -Running optimization stage 1 on output_decoder8 ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":2:7:2:24|Synthesizing module hades_LVL1_raw_out in library work. -Running optimization stage 1 on hades_LVL1_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":341:7:341:14|Synthesizing module trig_inv in library work. -Running optimization stage 1 on trig_inv ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":110:7:110:31|Synthesizing module hades_tdc_channel_raw_out in library work. -Running optimization stage 1 on hades_tdc_channel_raw_out ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":2:7:2:22|Synthesizing module hades_tdc_bundle in library work. -Running optimization stage 1 on hades_tdc_bundle ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":230:7:230:17|Synthesizing module trb_adapter in library work. -Running optimization stage 1 on trb_adapter ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":25:7:25:10|Synthesizing module AND2 in library work. -Running optimization stage 1 on AND2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":367:7:367:9|Synthesizing module INV in library work. -Running optimization stage 1 on INV ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":656:7:656:9|Synthesizing module OR2 in library work. -Running optimization stage 1 on OR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":810:7:810:10|Synthesizing module XOR2 in library work. -Running optimization stage 1 on XOR2 ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":710:7:710:14|Synthesizing module ROM16X1A in library work. -Running optimization stage 1 on ROM16X1A ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":959:7:959:14|Synthesizing module PDPW16KD in library work. -Running optimization stage 1 on PDPW16KD ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":110:7:110:13|Synthesizing module FD1P3BX in library work. -Running optimization stage 1 on FD1P3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":119:7:119:13|Synthesizing module FD1P3DX in library work. -Running optimization stage 1 on FD1P3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":168:7:168:13|Synthesizing module FD1S3DX in library work. -Running optimization stage 1 on FD1S3DX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":160:7:160:13|Synthesizing module FD1S3BX in library work. -Running optimization stage 1 on FD1S3BX ....... -@N: CG364 :"/opt/synplicity/O-2018.09-SP1/lib/lucent/ecp5um5g.v":76:7:76:11|Synthesizing module CCU2C in library work. -Running optimization stage 1 on CCU2C ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":8:7:8:15|Synthesizing module fifo40_dc in library work. -Running optimization stage 1 on fifo40_dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo_colector.v":3:7:3:19|Synthesizing module fifo_colector in library work. -Running optimization stage 1 on fifo_colector ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":1:7:1:12|Synthesizing module top_tf in library work. -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/fifo32dc/fifo32dc.v":8:7:8:14|Synthesizing module fifo32dc in library work. -Running optimization stage 1 on fifo32dc ....... -@N: CG364 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":3:7:3:26|Synthesizing module tdc_channel_fifo_out in library work. -Running optimization stage 1 on tdc_channel_fifo_out ....... -Running optimization stage 1 on top_tf ....... - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) - - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:13 2021 - -###########################################################] - -Finished Containment srs generation. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) - -Divided design in to 1 groups -@L:"/home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log" "Log file for distribution node work.top_tf.verilog " -Compiling work_top_tf_verilog as a separate process -Compilation of node work.top_tf finished successfully.Real start time 0h:00m:00s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:01s - -Distributed Compiler Report -*************************** - -DP Name Status Start time End Time Total Real Time Log File ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -work.top_tf.verilog Success 0h:00m:00s 0h:00m:01s 0h:00m:01s /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.log -============================================================================================================================================================================== -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork//distcomp/distcomp0/distcomp0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 6MB) - -Process took 0h:00m:02s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:16 2021 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 004R, Built Nov 27 2018 21:19:49 - -@N|Running in 64-bit mode -File /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Wed Jun 16 09:19:17 2021 - -###########################################################] -Premap Report - -# Wed Jun 16 09:19:17 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@A: MF827 |No constraint file specified. -@N: MF284 |Setting synthesis effort to medium for the design -@L: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt -Printing clock summary report in "/home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_scck.rpt" file -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":90:17:90:28|Removing instance dec_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.output_decoder8(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":69:15:69:26|Removing instance tdc_neg_inst (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.tdc4ddr_short(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":43:10:43:23|Removing instance trig_inv_inst3 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":37:10:37:23|Removing instance trig_inv_inst2 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@N: BN115 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":31:10:31:23|Removing instance trig_inv_inst1 (in view: work.tdc_channel_fifo_out(verilog)) of type view:work.trig_inv(verilog) because it does not drive other instances. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[24] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing sequential instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[9] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MH105 |UMR3 is only supported for HAPS-80. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Removing sequential instance out[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":153:2:153:7|Removing sequential instance referenced_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":96:1:96:6|Removing sequential instance buf_out[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_0(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_1(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":272:1:272:6|Removing sequential instance out_internal[2:0] (in view: work.output_decoder8_3_2(verilog)) of type view:PrimLib.sdffs(prim) because it does not drive other instances. -@W: BN114 :"/home/hadaq/mmichalek/lattice/simplified/fifo40_dc/fifo40_dc.v":407:13:407:25|Removing instance pdp_ram_0_1_0 (in view: work.fifo40_dc(verilog)) of black box view:LUCENT.PDPW16KD(PRIM) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":122:1:122:6|Removing sequential instance hitbuffer[23:0] (in view: work.hades_tdc_bundle(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":220:0:220:5|Removing sequential instance coarse[19:0] (in view: work.top_tf(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) - -syn_allowed_resources : blockrams=108 set on top level netlist top_tf - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------- -0 - System 200.0 MHz 5.000 system system_clkgroup 0 - -0 - pll0|CLKOS3_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_0 787 - -0 - top_tf|rd_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_4 64 - -0 - pll0|CLKOP_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_1 36 - -0 - pll0|CLKOS2_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_3 36 - -0 - pll0|CLKOS_inferred_clock 200.0 MHz 5.000 inferred Inferred_clkgroup_2 36 -=============================================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -System 0 - - - - - -pll0|CLKOS3_inferred_clock 787 pll0inst.PLLInst_0.CLKOS3(EHXPLLL) reset_dl[2:1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.un1_pll_clks.I[0](inv) - -top_tf|rd_clk 64 rd_clk(port) fifo_colector_inst.fifo40_inst.FF_1.CK - - - -pll0|CLKOP_inferred_clock 36 pll0inst.PLLInst_0.CLKOP(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks.I[0](inv) - -pll0|CLKOS2_inferred_clock 36 pll0inst.PLLInst_0.CLKOS2(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_2.I[0](inv) - -pll0|CLKOS_inferred_clock 36 pll0inst.PLLInst_0.CLKOS(EHXPLLL) genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1].C - genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.un1_clks_1.I[0](inv) -============================================================================================================================================================================================================================================================= - -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS3_inferred_clock which controls 787 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[3\]\.out_buffered[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOP_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[4]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":181:3:181:8|Found inferred clock pll0|CLKOS2_inferred_clock which controls 36 sequential elements including hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. -@W: MT529 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":305:2:305:7|Found inferred clock top_tf|rd_clk which controls 64 sequential elements including trb_adapter_inst.FEE_DATA_WRITE_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 64 clock pin(s) of sequential element(s) -4 gated/generated clock tree(s) driving 895 clock pin(s) of sequential element(s) -0 instances converted, 895 sequential instances remain driven by gated/generated clocks - -===================================== Non-Gated/Non-Generated Clocks ====================================== -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------ -@KP:ckid0_8 rd_clk Unconstrained_port 64 trb_adapter_inst.FEE_DATA_WRITE_OUT -=========================================================================================================== -======================================================================================== Gated/Generated Clocks ======================================================================================== -Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -@KP:ckid0_1 pll0inst.PLLInst_0.CLKOS3 EHXPLLL 787 reset_dl[2:1] Black box on clock path -@KP:ckid0_3 pll0inst.PLLInst_0.CLKOS2 EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered[2] Black box on clock path -@KP:ckid0_5 pll0inst.PLLInst_0.CLKOS EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered[1] Black box on clock path -@KP:ckid0_7 pll0inst.PLLInst_0.CLKOP EHXPLLL 36 genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered[0] Black box on clock path -======================================================================================================================================================================================================== - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -None -None - -Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 145MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jun 16 09:19:18 2021 - -###########################################################] -Map & Optimize Report - -# Wed Jun 16 09:19:18 2021 - - -Copyright (C) 1994-2018 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify (R) Premier -Build: O-2018.09-SP1 -Install: /opt/synplicity/O-2018.09-SP1 -OS: Debian GNU/Linux 9 (stretch) -Hostname: lxhadeb07 -max virtual memory: unlimited (bytes) -max user processes: 1031428 -max stack size: 8388608 (bytes) - - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version maprc, Build 4745R, Built Nov 27 2018 21:14:52 - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -@N: MF284 |Setting synthesis effort to medium for the design -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) - -@N: MF284 |Setting synthesis effort to medium for the design - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB) - -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_1 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_2 (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. - -Available hyper_sources - for debug and ip models - None Found - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB) - -@N: MF179 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules.v":140:8:140:43|Found 10 by 10 bit equality operator ('==') hades_tdc_bundle_inst.hit_valid25 (in view: work.top_tf(verilog)) -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[11] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[11] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[10] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[10] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: BN362 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Removing sequential instance offset[9] (in view: work.hades_LVL1_raw_out(verilog)) because it does not drive other instances. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register offset[9] (in view: work.hades_LVL1_raw_out(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_buf_positive (in view: work.hades_tdc_channel_raw_out(verilog)) -@N: MF179 :|Found 10 by 10 bit equality operator ('==') un1_coarse_1 (in view: work.hades_tdc_channel_raw_out(verilog)) -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[27] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[26] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[13] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[12] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB) - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[1].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[2].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. -@W: BN132 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":138:1:138:6|Removing instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[15] because it is equivalent to instance genblk1[0].tdc_channel_fifo_out_inst.fifo_in_data[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. - -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 147MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:02s -0.86ns 187 / 525 - 2 0h:00m:02s -0.86ns 184 / 525 -@N: FX271 :"/home/hadaq/mmichalek/lattice/simplified/modules2.v":262:0:262:5|Replicating instance hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid (in view: work.top_tf(verilog)) with 10 loads 1 time to improve timing. -Timing driven replication report -Added 1 Registers via timing driven replication -Added 0 LUTs via timing driven replication - - 3 0h:00m:04s -0.74ns 186 / 526 - - - 4 0h:00m:04s -0.74ns 186 / 526 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_0_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[0] (in view: work.top_tf(verilog)) has its enable tied to GND. -@N: MO111 :"/home/hadaq/mmichalek/lattice/simplified/top2.v":28:10:28:29|Tristate driver hades_raw_valid_vect_obuft_1_.un1[0] (in view: work.top_tf(verilog)) on net hades_raw_valid_vect[1] (in view: work.top_tf(verilog)) has its enable tied to GND. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_8_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_7_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_6_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_4_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_3_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_2_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_0_.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_valid.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"/home/hadaq/mmichalek/lattice/simplified/hades_modules2.v":74:1:74:6|Boundary register hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.discard.fb (in view: work.top_tf(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 147MB peak: 148MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 112MB peak: 149MB) - -Writing Analyst data base /home/hadaq/mmichalek/lattice/simplified/impl1/synwork/s1_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 145MB peak: 149MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 153MB) - -@W: MT246 :"/home/hadaq/mmichalek/lattice/simplified/pll0/pll0.v":60:12:60:20|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@W: MT420 |Found inferred clock pll0|CLKOS3_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[3]. -@W: MT420 |Found inferred clock pll0|CLKOP_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[0]. -@W: MT420 |Found inferred clock pll0|CLKOS_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[1]. -@W: MT420 |Found inferred clock pll0|CLKOS2_inferred_clock with period 5.00ns. Please declare a user-defined clock on net pll0inst.pll_clks[2]. -@W: MT420 |Found inferred clock top_tf|rd_clk with period 5.00ns. Please declare a user-defined clock on port rd_clk. - - -##### START OF TIMING REPORT #####[ -# Timing Report written on Wed Jun 16 09:19:25 2021 -# - - -Top view: top_tf -Requested Frequency: 200.0 MHz -Wire load mode: top -Paths requested: 3 -Constraint File(s): -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: -0.652 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------ -pll0|CLKOP_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_1 -pll0|CLKOS2_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_3 -pll0|CLKOS3_inferred_clock 200.0 MHz 158.6 MHz 5.000 6.305 -0.652 inferred Inferred_clkgroup_0 -pll0|CLKOS_inferred_clock 200.0 MHz 1037.3 MHz 5.000 0.964 4.036 inferred Inferred_clkgroup_2 -top_tf|rd_clk 200.0 MHz 256.6 MHz 5.000 3.897 1.103 inferred Inferred_clkgroup_4 -System 200.0 MHz 527.3 MHz 5.000 1.897 3.103 system system_clkgroup -=================================================================================================================================== - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------ -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------ -System pll0|CLKOS3_inferred_clock | 5.000 3.104 | No paths - | No paths - | No paths - -System top_tf|rd_clk | 5.000 3.104 | No paths - | No paths - | No paths - -pll0|CLKOS3_inferred_clock System | 5.000 3.782 | No paths - | No paths - | 5.000 4.247 -pll0|CLKOS3_inferred_clock pll0|CLKOS3_inferred_clock | 5.000 0.197 | 5.000 2.602 | 2.500 1.172 | 2.500 -0.653 -pll0|CLKOS3_inferred_clock top_tf|rd_clk | Diff grp - | No paths - | No paths - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOP_inferred_clock pll0|CLKOP_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS_inferred_clock pll0|CLKOS_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS3_inferred_clock | No paths - | Diff grp - | Diff grp - | No paths - -pll0|CLKOS2_inferred_clock pll0|CLKOS2_inferred_clock | 5.000 4.036 | 5.000 4.036 | No paths - | No paths - -top_tf|rd_clk System | 5.000 3.807 | No paths - | No paths - | No paths - -top_tf|rd_clk pll0|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - -top_tf|rd_clk top_tf|rd_clk | 5.000 1.104 | No paths - | No paths - | No paths - -=============================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: pll0|CLKOP_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[0] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.in_clk_synced[4] pll0|CLKOP_inferred_clock FD1S3AX Q in_clk_synced[4] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[0] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[4] pll0|CLKOP_inferred_clock FD1S3AX D in_clk_synced[4] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] / D - The start point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOP_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.in_clk_synced[0] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[0] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[0\]\.out_buffered1[0] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS2_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[2] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.in_clk_synced[6] pll0|CLKOS2_inferred_clock FD1S3AX Q in_clk_synced[6] 0.753 4.036 -============================================================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[2] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[6] pll0|CLKOS2_inferred_clock FD1S3AX D in_clk_synced[6] 4.789 4.036 -=============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] / D - The start point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS2_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.in_clk_synced[2] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[2] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[2\]\.out_buffered1[2] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS3_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast pll0|CLKOS3_inferred_clock FD1S3AX Q valid_fast 0.863 -0.652 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo_in_data[11] pll0|CLKOS3_inferred_clock FD1S3IX Q fifo_in_data[9] 0.913 0.007 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX Q window[2] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX Q window[5] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX Q window[6] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX Q window[7] 0.838 0.197 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX Q window[3] 0.838 0.720 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX Q window[4] 0.838 0.720 -=============================================================================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[7] 2.289 -0.652 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[5] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[5] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[6] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[6] 2.289 -0.594 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[2] pll0|CLKOS3_inferred_clock FD1S3JX PD window_6[2] 2.183 -0.581 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[3] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[3] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[4] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[4] 2.289 -0.534 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[1] pll0|CLKOS3_inferred_clock FD1S3IX D window_6[1] 2.289 -0.475 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2] pll0|CLKOS3_inferred_clock OFS1P3IX CD valid_fast_RNI999V 2.183 -0.059 -============================================================================================================================================================ - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.942 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : -0.652 - - Number of logic level(s): 7 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_0_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.992 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.992 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.599 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.599 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.942 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.942 - -============================================================================================================================================= - - -Path information for path number 2: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B1 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - -Path information for path number 3: - Requested Period: 2.500 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 2.289 - - - Propagation time: 2.882 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : -0.593 - - Number of logic level(s): 6 - Starting point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast / Q - Ending point: hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] / D - The start point is clocked by pll0|CLKOS3_inferred_clock [falling] on pin CK - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------- -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast FD1S3AX Q Out 0.863 0.863 - -valid_fast Net - - - - 4 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 C In 0.000 0.863 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.dec_inst.valid_fast_RNI5DQ71 ORCALUT4 Z Out 0.168 1.031 - -un1_reset_0_a2_2_0 Net - - - - 8 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C B0 In 0.000 1.031 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_1_0 CCU2C COUT Out 0.784 1.815 - -un1_window_8_cry_2 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C CIN In 0.000 1.815 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_3_0 CCU2C COUT Out 0.059 1.874 - -un1_window_8_cry_4 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C CIN In 0.000 1.874 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_cry_5_0 CCU2C COUT Out 0.059 1.933 - -un1_window_8_cry_6 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C CIN In 0.000 1.933 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.un1_window_8_s_7_0 CCU2C S0 Out 0.607 2.539 - -un1_window_8_s_7_0_S0 Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 C In 0.000 2.539 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window_6[7] ORCALUT4 Z Out 0.343 2.882 - -window_6[7] Net - - - - 1 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.window[7] FD1S3IX D In 0.000 2.882 - -============================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: pll0|CLKOS_inferred_clock -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[1] 0.753 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.in_clk_synced[5] pll0|CLKOS_inferred_clock FD1S3AX Q in_clk_synced[5] 0.753 4.036 -============================================================================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[1] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[1] 4.789 4.036 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -hades_tdc_bundle_inst.hades_tdc_channel_raw_out_inst.tdc_neg_inst.genblk1\[1\]\.out_buffered1[5] pll0|CLKOS_inferred_clock FD1S3AX D in_clk_synced[5] 4.789 4.036 -============================================================================================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 0.753 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 4.036 - - Number of logic level(s): 0 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] / Q - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] / D - The start point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - The end point is clocked by pll0|CLKOS_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.in_clk_synced[1] FD1S3AX Q Out 0.753 0.753 - -in_clk_synced[1] Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.tdc_inst.genblk1\[1\]\.out_buffered1[1] FD1S3AX D In 0.000 0.753 - -================================================================================================================================================= - - - - -==================================== -Detailed Report for Clock: top_tf|rd_clk -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------ -fifo_colector_inst.fifo40_inst.FF_12 top_tf|rd_clk FD1S3DX Q w_gcount_r29 0.883 1.103 -fifo_colector_inst.fifo40_inst.FF_13 top_tf|rd_clk FD1S3DX Q w_gcount_r28 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_14 top_tf|rd_clk FD1S3DX Q w_gcount_r27 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_15 top_tf|rd_clk FD1S3DX Q w_gcount_r26 0.838 1.149 -fifo_colector_inst.fifo40_inst.FF_16 top_tf|rd_clk FD1S3DX Q w_gcount_r25 0.863 1.169 -fifo_colector_inst.fifo40_inst.FF_17 top_tf|rd_clk FD1S3DX Q w_gcount_r24 0.838 1.194 -fifo_colector_inst.fifo40_inst.FF_18 top_tf|rd_clk FD1S3DX Q w_gcount_r23 0.798 1.234 -fifo_colector_inst.fifo40_inst.FF_19 top_tf|rd_clk FD1S3DX Q w_gcount_r22 0.753 1.278 -fifo_colector_inst.fifo40_inst.FF_20 top_tf|rd_clk FD1S3DX Q w_gcount_r21 0.798 1.841 -fifo_colector_inst.fifo40_inst.FF_21 top_tf|rd_clk FD1S3DX Q w_gcount_r20 0.753 1.887 -================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock -------------------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_1 top_tf|rd_clk FD1S3BX D empty_d 4.789 1.103 -fifo_colector_inst.fifo40_inst.FF_62 top_tf|rd_clk FD1P3DX D ircount_9 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_63 top_tf|rd_clk FD1P3DX D ircount_8 4.789 2.338 -fifo_colector_inst.fifo40_inst.FF_64 top_tf|rd_clk FD1P3DX D ircount_7 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_65 top_tf|rd_clk FD1P3DX D ircount_6 4.789 2.397 -fifo_colector_inst.fifo40_inst.FF_66 top_tf|rd_clk FD1P3DX D ircount_5 4.789 2.457 -fifo_colector_inst.fifo40_inst.FF_67 top_tf|rd_clk FD1P3DX D ircount_4 4.789 2.457 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR5 rptr_0 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR6 rptr_1 3.223 2.470 -fifo_colector_inst.fifo40_inst.pdp_ram_0_0_1 top_tf|rd_clk PDPW16KD ADR7 rptr_2 3.223 2.470 -========================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.686 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.103 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_12 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_12 FD1S3DX Q Out 0.883 0.883 - -w_gcount_r29 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD0 In 0.000 0.883 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.536 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A AD3 In 0.000 1.536 - -fifo_colector_inst.fifo40_inst.LUT4_15 ROM16X1A DO0 Out 0.523 2.059 - -wcount_r1 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B1 In 0.000 2.059 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.843 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.843 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.902 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.902 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.961 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.961 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 3.020 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 3.020 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.079 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.079 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.686 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.686 - -============================================================================================================= - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 3.640 - - Clock delay at starting point: 0.000 (ideal) - = Slack (non-critical) : 1.148 - - Number of logic level(s): 8 - Starting point: fifo_colector_inst.fifo40_inst.FF_13 / Q - Ending point: fifo_colector_inst.fifo40_inst.FF_1 / D - The start point is clocked by top_tf|rd_clk [rising] on pin CK - The end point is clocked by top_tf|rd_clk [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- -fifo_colector_inst.fifo40_inst.FF_13 FD1S3DX Q Out 0.838 0.838 - -w_gcount_r28 Net - - - - 3 -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A AD1 In 0.000 0.838 - -fifo_colector_inst.fifo40_inst.LUT4_23 ROM16X1A DO0 Out 0.653 1.491 - -w_g2b_xor_cluster_0 Net - - - - 5 -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A AD3 In 0.000 1.491 - -fifo_colector_inst.fifo40_inst.LUT4_14 ROM16X1A DO0 Out 0.523 2.014 - -wcount_r0 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C B0 In 0.000 2.014 - -fifo_colector_inst.fifo40_inst.empty_cmp_0 CCU2C COUT Out 0.784 2.798 - -co0_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C CIN In 0.000 2.798 - -fifo_colector_inst.fifo40_inst.empty_cmp_1 CCU2C COUT Out 0.059 2.857 - -co1_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C CIN In 0.000 2.857 - -fifo_colector_inst.fifo40_inst.empty_cmp_2 CCU2C COUT Out 0.059 2.916 - -co2_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C CIN In 0.000 2.916 - -fifo_colector_inst.fifo40_inst.empty_cmp_3 CCU2C COUT Out 0.059 2.975 - -co3_2 Net - - - - 1 -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C CIN In 0.000 2.975 - -fifo_colector_inst.fifo40_inst.empty_cmp_4 CCU2C COUT Out 0.059 3.034 - -empty_d_c Net - - - - 1 -fifo_colector_inst.fifo40_inst.a0 CCU2C CIN In 0.000 3.034 - -fifo_colector_inst.fifo40_inst.a0 CCU2C S0 Out 0.607 3.640 - -empty_d Net - - - - 1 -fifo_colector_inst.fifo40_inst.FF_1 FD1S3BX D In 0.000 3.640 - -============================================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t19 System AND2 Z rden_i 0.000 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.AND2_t20 System AND2 Z wren_i 0.000 3.103 -fifo_colector_inst.fifo40_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.XOR2_t0 System XOR2 Z r_gdata_8 0.000 4.789 -================================================================================================================================= - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ------------------------------------------------------------------------------------------------------------------------------------------ -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_0 System FD1S3DX D full_d 4.789 3.103 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -fifo_colector_inst.fifo40_inst.FF_1 System FD1S3BX D empty_d 4.789 3.103 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.pdp_ram_0_0_0 System PDPW16KD CER rden_i 3.228 3.228 -========================================================================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[1\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 2: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[2\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - -Path information for path number 3: - Requested Period: 5.000 - - Setup time: 0.211 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 4.789 - - - Propagation time: 1.685 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 3.103 - - Number of logic level(s): 7 - Starting point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 / Z - Ending point: genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 / D - The start point is clocked by System [rising] - The end point is clocked by pll0|CLKOS3_inferred_clock [rising] on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.AND2_t19 AND2 Z Out 0.000 0.000 - -rden_i Net - - - - 34 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C A1 In 0.000 0.000 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_ci_a CCU2C COUT Out 0.784 0.784 - -cmp_ci Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C CIN In 0.000 0.784 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_0 CCU2C COUT Out 0.059 0.843 - -co0_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C CIN In 0.000 0.843 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_1 CCU2C COUT Out 0.059 0.902 - -co1_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C CIN In 0.000 0.902 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_2 CCU2C COUT Out 0.059 0.961 - -co2_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C CIN In 0.000 0.961 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_3 CCU2C COUT Out 0.059 1.020 - -co3_2 Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C CIN In 0.000 1.020 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.empty_cmp_4 CCU2C COUT Out 0.059 1.079 - -empty_d_c Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C CIN In 0.000 1.079 - -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.a0 CCU2C S0 Out 0.607 1.685 - -empty_d Net - - - - 1 -genblk1\[0\]\.tdc_channel_fifo_out_inst.fifo32dc_inst.FF_1 FD1S3BX D In 0.000 1.685 - -====================================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied -None - -Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - - -Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 151MB peak: 153MB) - ---------------------------------------- -Resource Usage Report -Part: lfe5um5g_45f-8 - -Register bits: 934 of 43848 (2%) -PIC Latch: 0 -I/O cells: 186 -Block Rams : 4 of 108 (3%) - - -Details: -AND2: 8 -CCU2C: 121 -EHXPLLL: 1 -FD1P3AX: 69 -FD1P3BX: 8 -FD1P3DX: 232 -FD1P3IX: 50 -FD1S3AX: 321 -FD1S3BX: 4 -FD1S3DX: 164 -FD1S3IX: 41 -FD1S3JX: 10 -GSR: 1 -IB: 11 -IFS1P3DX: 5 -INV: 20 -OB: 173 -OBZ: 2 -OFS1P3DX: 17 -OFS1P3IX: 13 -OR2: 4 -ORCALUT4: 180 -PDPW16KD: 4 -PUR: 1 -ROM16X1A: 96 -VHI: 25 -VLO: 6 -XOR2: 72 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 37MB peak: 153MB) - -Process took 0h:00m:07s realtime, 0h:00m:07s cputime -# Wed Jun 16 09:19:25 2021 - -###########################################################] diff --git a/impl1/s1_impl1.srr.db b/impl1/s1_impl1.srr.db deleted file mode 100644 index de140168a9646e8d9b3a327ec898a95a0c1b99ef..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 36864 zcmeHQ$#WaodFKx9)L5f%G>S$oX~rUB2}E~eAvq)4TqRi)NpX>6Q*uuOcp!TSbVJ<@ zO4M+o0u&#dKf*qwa`V9lxhji&$i)X9a!G0qKDg|uq>@UxQg)>(m2#HK@9V}!0wB=@ zNP(V4Nsl1d-S2z9?=9c*dk@R^=My0Q!x>L3F@MlztRjKiXMfDG@}Lk3G1 z{6V@{JU|yM=Shb3n)<_7fN-Fa_m}Mti_?n_`QY8@N*$u*o!W&60RoH)0;0SSOAGh- z;3Iybf)IZ?NHRz@0WoUHKqc=h3&f*^C80w7JAZ`w-+EG0{lNgu3{;Mlt^R=8&(&VL z7zF;~RF<#(&isQ)ZGRiJ57dUe5J2T9Dj+{GKV1p=bn{tM-;>Bgzo8}A$c7x1pN=FF z3f7D`+Z>6@rl~~Oh@m7fS;rI>9Wk|}K=ZL6QrDxB50%B;)WZ@Umo%AP0fBVSS0KZ= zXO3lnn9PvuncuL4AyLK!p{yYG)n+szg;Q!2Yej`s;@!782h*3*UA2j0fx}y4f=aRc za#fHCNUJJ~OS=3_(o$w6;abiBs-h{YT6JYXvZNCIJoQzS6=n-lSJov(-Kr!+{{Vy- z{Im`L3AVz@Pg*uOa}VbD!%*q!Csb071u8~G5NZCPQYf!0XeF64r6`MNQKpYp0>{%w zvOKLxmLemg{B(j|?2kru$=J~JN`2+iUI@}xm{_XqD#>`7q(7 zwDwRRsnymRBc1R;{HS1M%-nvoI5#&}L5iJj2vOs@5(?62p|ZRx9?UINs=ccYwFhWj z38Ab|`|UdwYEPf(^qfy$PF#Ss%?tjqDLU_X91_V#^Su+1^5VSc zfHXZ1EonqCR6RiXwGWk#jSD1#e`lVVTsRez^e9uMm>h?rwazI92j7DL0bVTX&DWi7 zZ>P~|X=hB}o!8BeLKn~qeu&~uOo?eyR5oRM?Jzhwt}{8hov)cXiMauBjEI(GMRJ^J zYp`Czr+Zr)sF(0BTHaVM;nVGK_fMpkz&r2MQFy{AI#yA%PoiiGplE%Ma`W%Og&%m{ z|3CeSzF+h$^?u%atLL@r|CdG}T>syW!~h4^|A&|1`v2L`oa_IWjY{sg{=e)0MxwyEQ+ZZ?ky9ZRTrgGhfn0oVVF8bPV<_L&>*!Utsm#l1R~OO^t7J zMk<*^o(Ujf2M~9AVsZJ#s4t6@pFhf7nY%t3Mz2yAFpPNdh{K2%(Xo&j8XXTFIE>br z8jf%BYr+#RrGIm-mK8Lo90m1wul1XvT2b`1u_wjD1UO)DD(ImYpwv-vLxgkwWIpi3 z%dKeKCSyrN?RLg?71Ny#DATc8?n%Q z)}Uw#{!;~K`l*-T%-o_mp63Hco8v|FOv?KsrJV1aIbCzP47=6!N{4=#PFg(q70>S$ zzb*H;{6)pRx5`QWMm^e$WG&iEY4k(dTspye?J4U77$FzR1spmC9@nI+C*S&Lysx0bX7iz=yvwZPM=1Y#9(`4(^X z_4bfwurIwv4+#c?Q*kY_NvjmhH-iWOwh1nYlnRFRa_aNE64cYf?apMof566CR^XW8J5ZN%~^gB+OB8vgW6&8y^m+y zIu8j(h0wfKypU6qI3vj-7I)4oN4LPHGhe5>uOhwM^RgzckO+PVCZAwg&RaQihwv-M zj`m!EFc%AK*lOt_WH^aJG%}KVQ^Xr8PwdKFSV5BKmmx?ibeW}zS1U-4mO*?S;;WQL z#BwDn)ST|*Q1v+ghm*z1?$lB~iLBL6pmiV-)D&exH=phxM*V zA%U`><(xHN$d5(%YGuySuQA71{oaJ@<0Y zHo)(tY0A{KxWS3R;ur*@-6bk~WJQg{Q&F0CZEu^V6q`V6`%U(z#Vk$xbGnXf0&mtw zdc4Lze)8B${uXFb5QIh7EMJINNw%oumaAG}qJ(3fpo)uJB3tH!yv@Ne+9G$XXeC16 z!&+%Lc&Yh?#(p*!QGkZ-!{m#Fi^0w zH?1RIiH`i_uQs-hu71JQh6dDa3^GFg)v=nN1Ev4Bvpe0WxJEYu}quy&)a!#qC%)xmlOO^8^3)MjUUd0tVk4(J$}_1Z+R2MG9&Y5 zi{A%ZP8_EnLP6_!Uo#m^VsAh~@=3hp+wW}VAGx=|;kXP3CagWT1LSk7Q#11`-W*M9 zXmRPzJtsl({8Ewr^dp*vGH{d}D!zC*7eb_SDi7AV9k;}$8W66l%n=BCaVX6ZP`5XZ zs`*bpZ0y$a$J_ex#%}$g`JtM0zcq%|pUd2J-1AGOJlg3oj^g0XPds}Jfci{#==AKU zo&M!08h$?W?b;j82jIjbss_g~A6qIn*XxW-XBer`#y}t$vO0dFuSh{CW8&x z#?!1o+Z*x>4xQUb_QsU+|hYdT3Uc#pxx_0yCwP7x$@{(=i zN+qeIf~}X!a%MM_7FIti;<=k{UZMIoDPnqr`e_DEYKCGGZ(tugp=ud2SC=u8247t| z4~t0{bHFUvvu;>h)IxqN94La56a=A@A9S`3t^qg(8mt;-Qckz5pv9q!0!kDlMtEQo zaTKItHBLsL0h^!Mb1uT-aVv!zRSb(hkgtfYN4(-Xygxg6OG(~B;+7Z-VP-yK%no?x z@1xKJ1>N`7kc|@WrdO8;rHrSxMP@Hb2d*(k1I!_>WHb)n^JQYl?WUjJJ>fQ& z*gE@_K?JFatiaOFTypzitiavLZ`GV7-rc_QrjqHqL$@J*HOchdk8a`0qbAdLCueJi zDcw5bIp3GYxiqtnc-}8AZz{#}F4sO{-6W3Wp?bjy(%1l;m!L4WGNQ^Z!?y`hVK@yw~6T+pZsVZg}4B@VEc0 z?QdKEx=hkZ%rb{PG5@Rf4B-b@9H#X1P9*psoR1KW|4LXtNYKFpM99EUe^ zTW(k=M^6`&>6ahV0+yjL&&llF&=46ik&W{rN>$BPjN`W1(l4bqf`G3s2$TjboLjA_ z?~=udjUBM0g8miQL|JMkqFNNO$_L7b>tn^C?kr4#>|^f?3RASIKwab(T+)XE*0QiB-H>hGE|b9!QohT@aSW~@KFO|C>|e%fV<8c`!F9qY&;Bw z;PGK79tVaG8W6+Kv0(`H)V&{)|9_@wvZ?i);B?{|K^<3HN}vh8u}?^}P+ z^5d4bo41>Oi3=*e(&u$pp_y|OI^&3$ZQ`9{9J?mZ2lP$XsZz#}a&{p6aac?*M&Qp@@Y<03>P20<&ueWHJi;F}{ zRxes9dA#1D!8$C6c3yL!(NfNIy=BAHQIKs@#h8C9Ba%u5f3W)067`h);m7nP58z?K z|L{!`X_Ppl`2&XxE}`@@r z1oqz1b~kj<>^27(RL*S!R}&wAe6)n}!a8Hu;D+w!xF9iZi5aQ5X$T*Q`6S3Gy4VWC8z@^nGD-mp*# zrwz(j!$K*ZHYi!cLg_zkP(~XT%D`!ZGSaY622U51Z<|06h41`|ku6KDWWZpD1Wv829@2vy#i@Ek>tzWe zFS~SisEgzu-&wcuAyp+LV0rV+n>Q>L3mBXwCF$+1nz}`;qIoojog$5%;Ovk{8L$Sv zs|LP~2C@QHWtH)D5BVz3Sbdnxpiv@CVEz_rG$-Yja2!!nDBszikcW!wA>op(9VUmb z9l?j~N65-@6NgU$Wd}d`B|I9Lz)Oezb_U+IbQVs5FbxQ;L3nQ^3bqc7m1D0A2}14` zL_F5uP?2yGkbO@Mh+a%=O;2!CFnWdzqw}LM6!g?7Amw_0l}c+G3}_Fw1#t_8$5zI( zqgSU?=nrS4?tQb*?A0>Rg*HoYioG?X47?@uw!s#q`158RG#sGA<9MBfy9FozX28Pm z;lB}ZZ~-HU=i_!A9+5>!SZ_4nKfOHecZX_riNmHYG1=h~_oF8C&d;Lx_SsO&XrE06SZEN_|#e4{B-qAqlpstjL*sU)~kbr!T(&00960)L7qd z;ykmyCVxd_SK4wx)`+OMM3wffjb9_h4p<_4v&aHcl?}A~@OJxk|N1jd3#Cg~eS0pB zbZ)BRjAzEB2fYHlSH|z;CaQ#L{W6CVpw>s-9u9zJ-Z9(T> z=^>4dvvMsvYB-e4aU|Bg7-2h;E53^D(sF`7I~+Uk{`juI`xGo|HY4sYW1b6{Tb>Cf zvj5fIIW2AWm-~pNS*H40S;i~-e;cQ~(UCjsN(`_qU|12=1Qc!!sj&!5CPG3I4BkjxlK z%SCXvH9x~o-cQ}>Q_HZAQ%aYL57}!jC+kmU_+q4C0~u2jZ0{C7KZT~s-xR#mn$8?y z`}2Kz0Sjy>2Nbs4Melz2_}N@!Oz_MRQ7>P-%R^qmjoH4^isjt;y`r-ub?2BLpX0Z9 zf6%Y40(1H0OYd^r>&4?YDn7-%Cpx#KGhIm-A-L5ds15ihH6xFahc zj9AAy35L>iFte|@n3y;)df1V|tyhbW`}~@+5({GU}|Jc+dsG8_j(n+ux^FH9wz?&ynSps7aSBb)o`$e#$~39s4UCYWjc>r<5vDS&fyPL(-1U$wYfS#Y6j? zt#(qN;EOU}dhun{>s>}sFM_1;_-hXMtI{PkoK<;|h;?;WE*C4SdBz#9&Zg1F`brq8 z!Bx#LfQ?;rZwJ*K-J^8&004H@Dr|*xjJ6dBd7aX-pKP zCqrukU@Gh^TiHBa?#%slNxvyb$ysJsvvjx2V^h|w#n)x}O)Y6|-A>HP^4fe`sx)_& zifFdG{$@%A`mCUCcD*Z%D!(1u0sbJ|4zm;8c9~~RXdJU$3_8&s2Uf~r>oAs#(8QF7 z`%zprpa$sJpvRKwc`GX)X*6zK&Bt`!(s|BW^s->{vM5TF(?gt>R;_@;xGQWPllbwV z53eAj*KP^jl18R=koR~)X1b3}ecw(n`k=$4X@%9ybpC~2rHtmW1bo1bv4EW75Cb4X zj3g%Tx_O3qV^5#e5I z`8PWb5t*z}uz}WRH!*?rIvm=>cN;5-TYDRKX0rk8g$Aukvq4)0zMS&BBxtuYk zG71?$ie1!8%IgzMbOwEp^VrCYUvY|N%=0CC&L+g`M9$kD2xxnX4uEvgy4b0K1mZk^ ze;|zlQJpgvIo>f6mvMc(H=DZ{vLYv#RTzKt`>cOHCL*>u%Q4Y*$dRn<`TQ2UC5g`6 zt*;F@Pi5!r|FbrhD9wG`e$x*b#&v?(NxV~omM*tUbA~-er@}1r90-Dv{e;n4`Tcjq zD*b&(3h2>9_I5=XT%Yo3q3>h3Z_yy1HbU<2S$O+Nd+l#oMTnA+x#?shx1 zo4f63)U}IqxY)GQA6wg<-fiu+yBS$DT6jAZuHKCn)!L6~(1q5Tz1PwOE>&!PAA>(&A}0>1a~ ztE#CGINB6;FP=xEus!MivJca`^VZ4vdJ4^R=;ILD=B6EP!$0l!vDh@jFx<8e_J5C~ z-Hb+VVWq;b@xO@svAp+ZX;R1+Qj6yVXok0msm!Q$wRP_?7&(u}()SZaR&)!yCN~|S-HO9B#WjDmeJuNi3zFfFb2h-thgn>hj$7>GkxK!X z%n8fH8}@vdlO#xF!U`DB2okT@r8_X8uAdx+{G1@*_>0A++crM8zfMQpN!M(F`WU*O<7=E6Yhq)6l za;27;>uVgDVt%9#ni*a%otRN8P11_qF%`R6UlVigeeJkUfQ~dyUw!|#!w8&5$K3dO z8D!4#pi$S02cEMdkI~lAEa8nhJ`8*%Yk1BL=?xt1w1z!r_B^!GBNf$}?0WZC=Qxlh zAmQ~XBdc1CE_StCTp9!iV>3i9e2q#61R9tDOO@skJHH2dDv&ea{yJr^*yH&qC57JI zpW!r~KYG8b8u$Fx`xRW&aWX;PeUg5kqfA@PRGRQpek(lAkaxd*K2T{Y-dM+{;#o8Qp z*ro5mfBQ!B2R$F~=TG*IIZ_T>8~m44S-m5=n(d|X=w_9_+gQKN_pk!ItIDzKUF2u{ z3PbmKX^QJI|E7+0&41T*RjcdqRM+K+u5pcDb-te1gtf<-wac2dIve-DuSGR>VJ)s% zi)z-2nzgH%wG&^W8efVUUkd&4Ev2vQg_|)2Ft{{|#sBRa%ROLE9u-$D_88ym%T_tR z9G9*8VqUfYgVV?RC@#_C)yW%6giVwb(f`{w7Gd7ztmv{9X9cRhSD5VIOzQN#y`>0g z@|+5*Ezy6RFa7QLyMsSfjpl%3ko!*2dfwz~1+GZ#Z7^Y17c+8JcF)_0@WY^8UXpr@ zhk2^{?tKWpgu(v+00960N-Igt$+6~ga0LJW0RR8gI$dw#I-A$cuRx?1RMQi=ss$k^ zQZ+VNcSRg9B6Bm9MaUd_k`94*UUf99{qOtOAt5a=ZD+O8yH^C~@$>y@=Pnd?9^PQj z>tV;kA`tfqU5EfBGA3fG0!9lyvZk@P4Y+!uL`Ia;@Tp4#l0kw-an}-jYRk(ou>+ft z2}L4Eu-?POt*xen6*LeQ9`W0$U;s&|VgWA1XlikxZUe@P$Jh9RLNRHx5XCYOK^G;l zL|u)Oid+7#u;5RM+n+`E;c@ra5!;)=Znu=noEG5$u9%3d~mGQi0`H^_6TcXc-1oT7$Ge;`U#@d^!)8jI&j2JE_Yv+v%!Po zr(&=J1f3hhL;B!5BVpvY4ed*bIEtSF#k)v+etg(H-gLJ9U~t$k{K4*OFzCpeoBF@u z+ZMN%<4|6zgoG+cauE_-uRn#-mdXaMkUJ8Yp%ujR9!Z-EME*<5NpIsIxtBat1kA~7 zTXH*O1;K8mhy8nH2Z>C0LS05`JH_`jkSq`XGtLtjO&n!-y~d;Hpdb4QtX!y^C9;vl z&}o=1>Pq;Mleh>ao;hk?$3HL9fca}zi9yB6&}?i<=E0>3Xa#~Uhvm{XLV$cD|@ zDP9;-h1DGecj69jHX28^0kOR}W&xKjIIql8RN|qRiBoHx=Z@6z@JoJQ;xhF{*%0*4 zZmB|&1*&)oIf+G=$vAL1M-l~jH)#0o;hy1p5eF=mM7bdYDk=cMNq7#A3SH8|vBqnS z!^sSegghZ}iJRxqB|e9Tpr_<=gd3YQ4xi?Y5MiV<%=#;M1B)3PX zv4MlJmtnJi<380Qj_>g&Q z;_?(PHsvUnllV!Jq>C;Oe(t0g5_YP6Ba9g%_Sl6y5{{WoEce(ptXsW%!58GoMW34aC{F5Zrc&)cN+5Z0?vt z?w6{|ik4hGEmu$H2>o6`0S@kEK1Gtdl!+5-r+mWjz@@s+Wq`PxLeX+tG!~l1V%?%K zy*IdIG$qI@aW)=Syx%J>>6EjnD@hq4lmE}{v4+Qb=iM>v1a!Uqu8}hiV!KPw z!9G9*WN~U)0tgur+s2NyEPGn=4OtBRy`MC)q_r%m*Wb%>@3Jr;_c9#2mF~lP=E~rn zjKbp>ulcTFx?#(=(!S=sU;FRGmU$4r^xs!&XZ=^l{Yn2#H<|{tE(aP4S_vJOV^Z<2 za}0$@Cfxolej*jM2`6=)PB&i9#tIjcdyXu?;E1?b6_$_{DI$r0U6fZn* z5wL-?GH^_ek(RTREUn{fY=gRy%o&m;G$^${jUkx?GDplS)8EBg1J{zPsz2%48Luk2 z(3lzjN!^1FYhJXzOXj}dWpAsBmoqWhf@{^CmG-q2T)dzg$VeB2cHT2Q@+eTHO%`v_uJN|?+^_W9Z(>mE z?ny?8jwxK?Mn)ywAWG!ZB#}9e%ceeo-vFs3l26H`%wv46uYC>M&ErF!S#9tN^2`ci z^)(#WDN+HqF*!~1gYVDkr!8L;AL*&eRjXcF`(s;A?RwG1GmU?rcTd1}i;)$EBF9`B z`y%N^6E_bjgECOsXl;Bt6p%`%5`{$am=?mu&Zxh!L=i#)#Rj)4Q3Slf&`-@-O$OqF zT|!&j0=p!X1jPk~`5lYCwHXz8D8ez8Mz#pKGMwZPk%XbpE{7P8LXd&q+EXA&VkD`} z3)~mZrsfxdY~o7JNrDu_zHOm5`80DRjRF!x)gFi+=N;K`t%^&XT z{o%gFAMSgHpE)M3GE%=>v{JIC)s- zy?5BY;&t^QUixA3L4^0irXPS^eE|0THXGv2 z2Vi?2fL(k5_PpJaeP6QJpC>pAZ|!~RH}j^hInZ-W5sBpASY*P>kWlR8`+ClMJ!8hu zTj&8U#?`NdN5%I<{K}Tb_mWFthk;BKMKKqJz0h@CpKr(D&SLTte~3rt4IZ77JZAq} z9@U;lDB)gj<3XQ?KP7#SGMYgYqQA4u6Y4&=pdz8uOqlzRq!8x4Wuy5&pSLsWM;D*1 z`SxG`eD`TW7mIyOB*VN(&D){CEGxIjlMLTH36Q(xG*y_IEqZ zLZ7`k=>izs>+Yy_i@&}5Oaww*ynZk0JDmL)hdYU6PD7XIJU&O3InO4(vLS!C4lRd? zHK!4kw7jtO+|kIR`{nu2GUwTT)AJ!VFD!HJWzJUoW^T8>&9~cn#vi+WbB<8={mPmX z6~kN@My~Fc)6(&3y!CmBUbC{{JO(a91x`R*JxiJWds_NDqglJR<}3)^dq{@$`(~b= zyA_{$#xDsneQ4;P?W6Eo_o>$}&ki&%`fRv8^VhOzyr4tF$HbbOx!QrgL+h|TYwy>r ze14dz{e5rPp0h3H&Resy|9ZZj6RSP@Ht*vY3>&hsMclcbD`7s7DJvV@zM63@Hh(c^ z`lseh7xb!Uzgkw?Ws%F370zGHaQ^YUXYBW44)c%ZFz~Bavy^`{OKChuGmd|9#J@6EJrgk8kMk3EAO49ot23|e6u$4|uYBo;2usCbh(tUgOi7a)>$CnV`DG@To$vmy<=NFpM+uR{3LU#h*}gt|hx};HNc{adyQQj_ ztj^5+7iZ>rAH=5Xld!o@iy>}wEc(Q)YPjaHRRpqSv9p1LmATkvG6{nX`gv< z90f9nC_yq%dfpNqR3&}aA72Q4mllzLMhXRukLbHXh!YBRGpKC=g){Q$#i8z`!@0f- zg*9_$I=?us1V$85mf)N{(s&4$6CJx!iK;&P5Fd)r33wpZ|+%L!p;5w{0d^3 zmx!m?x~f?K@Y*LJZ?4m8=lEU`_|g1T_c}hcCrIWbHuRwefe*ImYhLyJuSLT7KF9lY zuIF>5>nao(>eE=~Kxxh`E^qBHlz9{eAt9hl&|PBZNbqh0-&KdZFX*ovPv7u+tDdg8 zQ8?xRMorA+Lza=$Ny8f{cIbTBUogc3+bW{dUh|1@o%Lcur5- zL-&=}TIQHszxf=IYcq4LOKfVE?u(R z2FSU(-_+}S-}3c7eOHIkr3IZpq;Ys`f2#Vi;cOAT|j~I>i!w(G5&jK`f*o(8dcX1 zUB{s#ul>yvc-XwV-akju6^FBcbd*?yus)Btoruc>^bsqh&vJzRhVk_s6zNvDN3_zl zi7jV^A+{W6<-y?4Z_WW>7Fp|i4c!yEg1hbWBM+~$e0VqqTvzusFZO9W)#o&hzE(4z zh-Cf1JK)&sz>ZyTM{!t>hN6x4h^N+Bh-l3uAJRq8HT1gH$g=(i00960;&M>n0ssI2 P|NjF3J1?><3`+n2fLALI diff --git a/impl1/s1_impl1.t2b b/impl1/s1_impl1.t2b deleted file mode 100644 index f783761..0000000 --- a/impl1/s1_impl1.t2b +++ /dev/null @@ -1,8 +0,0 @@ - - - - --g CfgMode:Disable --g RamCfg:Reset --g DisableUES:FALSE --g ES:No diff --git a/impl1/s1_impl1.tw1 b/impl1/s1_impl1.tw1 deleted file mode 100644 index 324cec7..0000000 --- a/impl1/s1_impl1.tw1 +++ /dev/null @@ -1,639 +0,0 @@ - -Loading design for application trce from file s1_impl1_map.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:19:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf -Design file: s1_impl1_map.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,8 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "clk_c" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - 3875 items scored, 78 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 1.095ns (weighted slack = -2.190ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] (to pll_clks[3] +) - - Delay: 2.537ns (44.3% logic, 55.7% route), 5 logic levels. - - Constraint Details: - - 2.537ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds - 1.667ns delay constraint less - 0.225ns LSR_SET requirement (totaling 1.442ns) by 1.095ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.CLK to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 e 0.156 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.Q0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOF_DEL --- 0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 -ROUTE 10 e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 -C1TOFCO_DE --- 0.278 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.B1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 -ROUTE 1 e 0.001 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113.FCO to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 -FCITOF1_DE --- 0.273 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.FCI to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 -ROUTE 1 e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114.F1 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -CTOF_DEL --- 0.141 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.C0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 -ROUTE 1 e 0.419 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738.F0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3]) - -------- - 2.537 (44.3% logic, 55.7% route), 5 logic levels. - -Warning: 181.028MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.722ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.728ns (42.4% logic, 57.6% route), 1 logic levels. - - Constraint Details: - - 0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets - 3.333ns delay constraint less - -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2]) -ROUTE 1 e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.728 (42.4% logic, 57.6% route), 1 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.722ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.728ns (42.4% logic, 57.6% route), 1 logic levels. - - Constraint Details: - - 0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets - 3.333ns delay constraint less - -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1]) -ROUTE 1 e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.728 (42.4% logic, 57.6% route), 1 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.722ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.728ns (42.4% logic, 57.6% route), 1 logic levels. - - Constraint Details: - - 0.728ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets - 3.333ns delay constraint less - -0.117ns M_SET requirement (totaling 3.450ns) by 2.722ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0]) -ROUTE 1 e 0.419 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.728 (42.4% logic, 57.6% route), 1 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY PORT "clk" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 7.298ns - The internal maximum frequency of the following component is 370.096 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SIOLOGIC CLK reset_dc_MGIOL - - Delay: 2.702ns -- based on Minimum Pulse Width - -Report: 370.096MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 - - Delay: 1.778ns -- based on Minimum Pulse Width - -Report: 562.430MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "clk_c" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks[3]" 300.000000 | | | -MHz ; | 300.000 MHz| 181.028 MHz| 5 * - | | | -FREQUENCY NET "pll_clks[2]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY NET "pll_clks[1]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY NET "pll_clks[0]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY PORT "clk" 100.000000 MHz ; | 100.000 MHz| 370.096 MHz| 0 - | | | -FREQUENCY NET "pll_clks*" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | ----------------------------------------------------------------------------- - - -1 preference(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/valid_fast | 5| 48| 61.54% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_reset_0_a2_2_0 | 10| 46| 58.97% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_1_0_S1 | 1| 33| 42.31% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/window_6[2] | 1| 33| 42.31% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_0 | 1| 21| 26.92% - | | | -valid_fast_RNI999V | 9| 18| 23.08% - | | | -hades_tdc_bundle_inst.hades_LVL1_raw_out| | | -_inst.offset_1_sqmuxa_i_0 | 11| 18| 23.08% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_4 | 1| 15| 19.23% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_2 | 1| 15| 19.23% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_reset_0_a2_c | 7| 14| 17.95% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/N_97 | 3| 14| 17.95% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/discard4_0_a2_0_3 | 3| 12| 15.38% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_s_7_0_S0 | 1| 8| 10.26% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/window_6[7] | 1| 8| 10.26% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/G_25_0_a3_5_0 | 1| 8| 10.26% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/G_25_0_a3_4_0 | 1| 8| 10.26% - | | | ----------------------------------------------------------------------------- - - -Clock Domains Analysis ------------------------- - -Found 6 clocks: - -Clock Domain: rd_clk_c Source: rd_clk.PAD Loads: 38 - No transfer within this clock domain is found - -Clock Domain: pll_clks[3] Source: pll0inst/PLLInst_0.CLKOS3 Loads: 446 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - - Data transfers from: - Clock Domain: rd_clk_c Source: rd_clk.PAD - Not reported because source and destination domains are unrelated. - - Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - -Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 Loads: 24 - Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - -Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS Loads: 24 - Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - -Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP Loads: 25 - Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - -Clock Domain: clk_c Source: clk.PAD Loads: 1 - No transfer within this clock domain is found - - -Timing summary (Setup): ---------------- - -Timing errors: 78 Score: 41485 -Cumulative negative slack: 24538 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:19:34 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -fullname -mapchkpnt 0 -sethld -o s1_impl1.tw1 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1_map.ncd s1_impl1.prf -Design file: s1_impl1_map.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "clk_c" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - 3875 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.096ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3] (from pll_clks[3] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3] (to pll_clks[3] +) - - Delay: 0.199ns (70.9% logic, 29.1% route), 1 logic levels. - - Constraint Details: - - 0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 meets - 0.103ns M_HLD and - 0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (from pll_clks[3]) -ROUTE 1 e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] (to pll_clks[3]) - -------- - 0.199 (70.9% logic, 29.1% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.096ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.199ns (70.9% logic, 29.1% route), 1 logic levels. - - Constraint Details: - - 0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets - 0.103ns M_HLD and - 0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2]) -ROUTE 1 e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.199 (70.9% logic, 29.1% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.096ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.199ns (70.9% logic, 29.1% route), 1 logic levels. - - Constraint Details: - - 0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets - 0.103ns M_HLD and - 0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1]) -ROUTE 1 e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.199 (70.9% logic, 29.1% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.096ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.199ns (70.9% logic, 29.1% route), 1 logic levels. - - Constraint Details: - - 0.199ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets - 0.103ns M_HLD and - 0.000ns delay constraint requirement (totaling 0.103ns) by 0.096ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.CLK to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0]) -ROUTE 1 e 0.058 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.Q1 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.199 (70.9% logic, 29.1% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY PORT "clk" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "clk_c" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks[3]" 300.000000 | | | -MHz ; | 0.000 ns| 0.096 ns| 1 - | | | -FREQUENCY NET "pll_clks[2]" 300.000000 | | | -MHz ; | 0.000 ns| 0.096 ns| 1 - | | | -FREQUENCY NET "pll_clks[1]" 300.000000 | | | -MHz ; | 0.000 ns| 0.096 ns| 1 - | | | -FREQUENCY NET "pll_clks[0]" 300.000000 | | | -MHz ; | 0.000 ns| 0.096 ns| 1 - | | | -FREQUENCY PORT "clk" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks*" 300.000000 | | | -MHz ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 6 clocks: - -Clock Domain: rd_clk_c Source: rd_clk.PAD Loads: 38 - No transfer within this clock domain is found - -Clock Domain: pll_clks[3] Source: pll0inst/PLLInst_0.CLKOS3 Loads: 446 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - - Data transfers from: - Clock Domain: rd_clk_c Source: rd_clk.PAD - Not reported because source and destination domains are unrelated. - - Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - -Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 Loads: 24 - Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - -Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS Loads: 24 - Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - -Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP Loads: 25 - Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - -Clock Domain: clk_c Source: clk.PAD Loads: 1 - No transfer within this clock domain is found - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 78 (setup), 0 (hold) -Score: 41485 (setup), 0 (hold) -Cumulative negative slack: 24538 (24538+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/impl1/s1_impl1.twr b/impl1/s1_impl1.twr deleted file mode 100644 index b3d8a86..0000000 --- a/impl1/s1_impl1.twr +++ /dev/null @@ -1,4135 +0,0 @@ - -Loading design for application trce from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application trce from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:20:29 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf -Design file: s1_impl1.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,8 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "clk_c" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - 3875 items scored, 280 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 1.497ns (weighted slack = -2.994ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] (to pll_clks[3] +) - - Delay: 2.939ns (38.2% logic, 61.8% route), 5 logic levels. - - Constraint Details: - - 2.939ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds - 1.667ns delay constraint less - 0.000ns skew and - 0.225ns LSR_SET requirement (totaling 1.442ns) by 1.497ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.281 R29C37C.Q0 to R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOF_DEL --- 0.141 R29C37C.C0 to R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 -ROUTE 10 0.731 R29C37C.F0 to R31C37A.A1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 -C1TOFCO_DE --- 0.278 R31C37A.A1 to R31C37A.FCO hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 -ROUTE 1 0.000 R31C37A.FCO to R31C37B.FCI hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 -FCITOF1_DE --- 0.273 R31C37B.FCI to R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 -ROUTE 1 0.404 R31C37B.F1 to R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -CTOF_DEL --- 0.141 R29C37A.D0 to R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 -ROUTE 1 0.400 R29C37A.F0 to R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3]) - -------- - 2.939 (38.2% logic, 61.8% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C36C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.396ns (weighted slack = -2.792ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5] (to pll_clks[3] +) - - Delay: 3.050ns (22.0% logic, 78.0% route), 3 logic levels. - - Constraint Details: - - 3.050ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.396ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.639 R29C37C.Q0 to R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.C0 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.435 R25C31B.F0 to IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.050 (22.0% logic, 78.0% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26C.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.387ns (weighted slack = -2.774ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5] (to pll_clks[3] +) - - Delay: 3.041ns (22.0% logic, 78.0% route), 3 logic levels. - - Constraint Details: - - 3.041ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.387ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[5]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.630 R29C37C.Q0 to R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.D1 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.435 R25C31B.F0 to IOL_L26C.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.041 (22.0% logic, 78.0% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[5]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26C.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3] (to pll_clks[3] +) - - Delay: 3.011ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.639 R29C37C.Q0 to R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.C0 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.396 R25C31B.F0 to IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.011 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26B.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.357ns (weighted slack = -2.714ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4] (to pll_clks[3] +) - - Delay: 3.011ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 3.011ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.357ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.639 R29C37C.Q0 to R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.C0 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.396 R25C31B.F0 to IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.011 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26A.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.354ns (weighted slack = -2.708ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6] (to pll_clks[3] +) - - Delay: 3.008ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 3.008ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.354ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.639 R29C37C.Q0 to R27C31A.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.C0 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.393 R25C31B.F0 to IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.008 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L23A.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3] (to pll_clks[3] +) - - Delay: 3.002ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[3]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.630 R29C37C.Q0 to R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.D1 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.396 R25C31B.F0 to IOL_L26B.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.002 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[3]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26B.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.348ns (weighted slack = -2.696ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4] (to pll_clks[3] +) - - Delay: 3.002ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 3.002ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.348ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[4]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.630 R29C37C.Q0 to R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.D1 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.396 R25C31B.F0 to IOL_L26A.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 3.002 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[4]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L26A.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.345ns (weighted slack = -2.690ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6] (to pll_clks[3] +) - - Delay: 2.999ns (22.3% logic, 77.7% route), 3 logic levels. - - Constraint Details: - - 2.999ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL exceeds - 1.667ns delay constraint less - -0.063ns skew and - 0.076ns RST_SET requirement (totaling 1.654ns) by 1.345ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_offset[6]_MGIOL: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.630 R29C37C.Q0 to R27C31A.D1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOOFX_DEL --- 0.239 R27C31A.D1 to R27C31A.OFX0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 -ROUTE 11 0.306 R27C31A.OFX0 to R25C31B.D0 hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 -CTOF_DEL --- 0.141 R25C31B.D0 to R25C31B.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 -ROUTE 9 1.393 R25C31B.F0 to IOL_L23A.LSR valid_fast_RNI999V (to pll_clks[3]) - -------- - 2.999 (22.3% logic, 77.7% route), 3 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_offset[6]_MGIOL: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.717 PLL_BL0.CLKOS3 to IOL_L23A.CLK pll_clks[3] - -------- - 1.717 (0.0% logic, 100.0% route), 0 logic levels. - - -Error: The following path exceeds requirements by 1.337ns (weighted slack = -2.674ns) - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast (from pll_clks[3] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] (to pll_clks[3] +) - - Delay: 2.779ns (34.7% logic, 65.3% route), 4 logic levels. - - Constraint Details: - - 2.779ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 exceeds - 1.667ns delay constraint less - 0.000ns skew and - 0.225ns LSR_SET requirement (totaling 1.442ns) by 1.337ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C37C.CLK to R29C37C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (from pll_clks[3]) -ROUTE 5 0.281 R29C37C.Q0 to R29C37C.C0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast -CTOF_DEL --- 0.141 R29C37C.C0 to R29C37C.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 -ROUTE 10 0.730 R29C37C.F0 to R31C37B.B0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 -CTOF1_DEL --- 0.392 R31C37B.B0 to R31C37B.F1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 -ROUTE 1 0.404 R31C37B.F1 to R29C37A.D0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 -CTOF_DEL --- 0.141 R29C37A.D0 to R29C37A.F0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 -ROUTE 1 0.400 R29C37A.F0 to R29C36C.LSR hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] (to pll_clks[3]) - -------- - 2.779 (34.7% logic, 65.3% route), 4 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C37C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520: - - Name Fanout Delay (ns) Site Resource -ROUTE 446 1.654 PLL_BL0.CLKOS3 to R29C36C.CLK pll_clks[3] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - -Warning: 158.003MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R28C3B.CLK to R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2]) -ROUTE 1 0.251 R28C3B.Q0 to R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R28C3B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R28C3A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R68C15B.CLK to R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2]) -ROUTE 1 0.251 R68C15B.Q0 to R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R68C15B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R68C15D.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R28C6B.CLK to R28C6B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (from pll_clks[2]) -ROUTE 1 0.251 R28C6B.Q0 to R28C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R28C6B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R28C6A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C52B.CLK to R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2]) -ROUTE 1 0.251 R66C52B.Q0 to R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C52B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C52C.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R66C51D.CLK to R66C51D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (from pll_clks[2]) -ROUTE 1 0.251 R66C51D.Q0 to R66C51A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C51D.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C51A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R68C14B.CLK to R68C14B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (from pll_clks[2]) -ROUTE 1 0.251 R68C14B.Q0 to R68C14A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R68C14B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R68C14A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R25C5D.CLK to R25C5D.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (from pll_clks[2]) -ROUTE 1 0.251 R25C5D.Q0 to R25C5A.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R25C5D.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R25C5A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C42D.CLK to R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2]) -ROUTE 1 0.251 R66C42D.Q0 to R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C42D.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C42B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R66C41B.CLK to R66C41B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (from pll_clks[2]) -ROUTE 1 0.251 R66C41B.Q0 to R66C41A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C41B.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R66C41A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[6] (from pll_clks[2] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6] (to pll_clks[2] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C3D.CLK to R29C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 (from pll_clks[2]) -ROUTE 1 0.251 R29C3D.Q0 to R29C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] (to pll_clks[2]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R29C3D.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS2 to R29C3A.CLK pll_clks[2] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.685ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.765ns (40.4% logic, 59.6% route), 1 logic levels. - - Constraint Details: - - 0.765ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.685ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R68C16C.CLK to R68C16C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1]) -ROUTE 1 0.456 R68C16C.Q0 to R68C16A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.765 (40.4% logic, 59.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C16C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C16A.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.840ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.610ns (50.5% logic, 49.5% route), 1 logic levels. - - Constraint Details: - - 0.610ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.840ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.308 R68C16C.CLK to R68C16C.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (from pll_clks[1]) -ROUTE 1 0.302 R68C16C.Q1 to R68C16C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.610 (50.5% logic, 49.5% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C16C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C16C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R25C3C.CLK to R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1]) -ROUTE 1 0.251 R25C3C.Q0 to R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R25C3C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R25C3B.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C44B.CLK to R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1]) -ROUTE 1 0.251 R66C44B.Q0 to R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C44B.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C44D.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[5] (from pll_clks[1] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5] (to pll_clks[1] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C6D.CLK to R29C6D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 (from pll_clks[1]) -ROUTE 1 0.251 R29C6D.Q0 to R29C6A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] (to pll_clks[1]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R29C6D.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R29C6A.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5] (from pll_clks[1] -) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] (to pll_clks[1] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R68C14D.CLK to R68C14D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (from pll_clks[1]) -ROUTE 1 0.251 R68C14D.Q0 to R68C14C.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C14D.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R68C14C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5] (from pll_clks[1] -) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] (to pll_clks[1] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R66C50C.CLK to R66C50C.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (from pll_clks[1]) -ROUTE 1 0.251 R66C50C.Q0 to R66C50B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C50C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C50B.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R28C3D.CLK to R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1]) -ROUTE 1 0.251 R28C3D.Q0 to R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R28C3D.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R28C3C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[5] (from pll_clks[1] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5] (to pll_clks[1] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R28C5C.CLK to R28C5C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (from pll_clks[1]) -ROUTE 1 0.251 R28C5C.Q0 to R28C5A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] (to pll_clks[1]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R28C5C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R28C5A.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C51B.CLK to R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1]) -ROUTE 1 0.251 R66C51B.Q0 to R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C51B.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 1.654 PLL_BL0.CLKOS to R66C51C.CLK pll_clks[1] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 - - Delay: 1.778ns -- based on Minimum Pulse Width - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R28C5B.CLK to R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0]) -ROUTE 1 0.251 R28C5B.Q0 to R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R28C5B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R28C5D.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R68C16D.CLK to R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0]) -ROUTE 1 0.251 R68C16D.Q0 to R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R68C16D.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R68C16B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R28C4D.CLK to R28C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (from pll_clks[0]) -ROUTE 1 0.251 R28C4D.Q0 to R28C4C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R28C4D.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R28C4C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C49B.CLK to R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0]) -ROUTE 1 0.251 R66C49B.Q0 to R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C49B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C49C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R66C52D.CLK to R66C52D.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (from pll_clks[0]) -ROUTE 1 0.251 R66C52D.Q0 to R66C52A.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C52D.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C52A.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R68C15C.CLK to R68C15C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (from pll_clks[0]) -ROUTE 1 0.251 R68C15C.Q0 to R68C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R68C15C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R68C15A.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R25C5B.CLK to R25C5B.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (from pll_clks[0]) -ROUTE 1 0.251 R25C5B.Q0 to R25C5C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R25C5B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R25C5C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.560ns (55.2% logic, 44.8% route), 1 logic levels. - - Constraint Details: - - 0.560ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.117ns M_SET requirement (totaling 3.450ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.309 R66C43B.CLK to R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0]) -ROUTE 1 0.251 R66C43B.Q0 to R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.560 (55.2% logic, 44.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C43B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C43C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R66C43D.CLK to R66C43D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (from pll_clks[0]) -ROUTE 1 0.251 R66C43D.Q0 to R66C43A.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C43D.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R66C43A.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 2.890ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4] (to pll_clks[0] -) - - Delay: 0.541ns (53.6% logic, 46.4% route), 1 logic levels. - - Constraint Details: - - 0.541ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 meets - 3.333ns delay constraint less - 0.000ns skew and - -0.098ns M_SET requirement (totaling 3.431ns) by 2.890ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.290 R29C3B.CLK to R29C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 (from pll_clks[0]) -ROUTE 1 0.251 R29C3B.Q0 to R29C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] (to pll_clks[0]) - -------- - 0.541 (53.6% logic, 46.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R29C3B.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 1.654 PLL_BL0.CLKOP to R29C3C.CLK pll_clks[0] - -------- - 1.654 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 562.430MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY PORT "clk" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 7.298ns - The internal maximum frequency of the following component is 370.096 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SIOLOGIC CLK reset_dc_MGIOL - - Delay: 2.702ns -- based on Minimum Pulse Width - -Report: 370.096MHz is the maximum frequency for this preference. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 1.555ns - The internal maximum frequency of the following component is 562.430 MHz - - Logical Details: Cell type Pin name Component name - - Destination: SLICE CLK hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 - - Delay: 1.778ns -- based on Minimum Pulse Width - -Report: 562.430MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "clk_c" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks[3]" 300.000000 | | | -MHz ; | 300.000 MHz| 158.003 MHz| 5 * - | | | -FREQUENCY NET "pll_clks[2]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY NET "pll_clks[1]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY NET "pll_clks[0]" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | -FREQUENCY PORT "clk" 100.000000 MHz ; | 100.000 MHz| 370.096 MHz| 0 - | | | -FREQUENCY NET "pll_clks*" 300.000000 | | | -MHz ; | 300.000 MHz| 562.430 MHz| 0 - | | | ----------------------------------------------------------------------------- - - -1 preference(marked by "*" above) not met. - ----------------------------------------------------------------------------- -Critical Nets | Loads| Errors| % of total ----------------------------------------------------------------------------- -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/N_97 | 3| 141| 50.36% - | | | -hades_tdc_bundle_inst.hades_LVL1_raw_out| | | -_inst.offset_1_sqmuxa_i_0 | 11| 130| 46.43% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/discard4_0_a2_0_3 | 3| 122| 43.57% - | | | -valid_fast_RNI999V | 9| 82| 29.29% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/valid_fast | 5| 82| 29.29% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_reset_0_a2_2_0 | 10| 66| 23.57% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_reset_0_a2_c | 7| 52| 18.57% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/window[7] | 3| 45| 16.07% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/window[5] | 3| 45| 16.07% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_4 | 1| 44| 15.71% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/window_6[2] | 1| 44| 15.71% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_1_0_S1 | 1| 43| 15.36% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_2 | 1| 38| 13.57% - | | | -hades_tdc_bundle_inst/hades_LVL1_raw_out| | | -_inst/un1_window_8_cry_0 | 1| 33| 11.79% - | | | ----------------------------------------------------------------------------- - - -Clock Domains Analysis ------------------------- - -Found 6 clocks: - -Clock Domain: rd_clk_c Source: rd_clk.PAD Loads: 38 - No transfer within this clock domain is found - -Clock Domain: pll_clks[3] Source: pll0inst/PLLInst_0.CLKOS3 Loads: 446 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - - Data transfers from: - Clock Domain: rd_clk_c Source: rd_clk.PAD - Not reported because source and destination domains are unrelated. - - Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - -Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 Loads: 24 - Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - -Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS Loads: 24 - Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - -Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP Loads: 25 - Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - -Clock Domain: clk_c Source: clk.PAD Loads: 1 - No transfer within this clock domain is found - - -Timing summary (Setup): ---------------- - -Timing errors: 280 Score: 209210 -Cumulative negative slack: 139580 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446 -Wed Jun 16 09:20:29 2021 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -fullname -gt -sethld -sp 8 -sphld m -o s1_impl1.twr -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml s1_impl1.ncd s1_impl1.prf -Design file: s1_impl1.ncd -Preference file: s1_impl1.prf -Device,speed: LFE5UM5G-45F,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY NET "clk_c" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - 3875 items scored, 18 timing errors detected. --------------------------------------------------------------------------------- - - -Error: The following path exceeds requirements by 1.015ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.328ns (40.5% logic, 59.5% route), 1 logic levels. - - Constraint Details: - - 0.328ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R29C3C.CLK to R29C3C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 (from pll_clks[0]) -ROUTE 1 0.195 R29C3C.Q0 to R30C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] (to pll_clks[3]) - -------- - 0.328 (40.5% logic, 59.5% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R29C3C.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R30C3B.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 1.015ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.328ns (40.5% logic, 59.5% route), 1 logic levels. - - Constraint Details: - - 0.328ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 1.015ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R68C15A.CLK to R68C15A.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (from pll_clks[0]) -ROUTE 1 0.195 R68C15A.Q0 to R66C15A.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3]) - -------- - 0.328 (40.5% logic, 59.5% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R68C15A.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C15A.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 1.000ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.343ns (38.8% logic, 61.2% route), 1 logic levels. - - Constraint Details: - - 0.343ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 1.000ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R25C5C.CLK to R25C5C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (from pll_clks[0]) -ROUTE 1 0.210 R25C5C.Q0 to R25C8C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] (to pll_clks[3]) - -------- - 0.343 (38.8% logic, 61.2% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R25C5C.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R25C8C.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.939ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.404ns (32.9% logic, 67.1% route), 1 logic levels. - - Constraint Details: - - 0.404ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 0.939ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R28C4C.CLK to R28C4C.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (from pll_clks[0]) -ROUTE 1 0.271 R28C4C.Q0 to R27C6B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] (to pll_clks[3]) - -------- - 0.404 (32.9% logic, 67.1% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R28C4C.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R27C6B.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.928ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.415ns (32.0% logic, 68.0% route), 1 logic levels. - - Constraint Details: - - 0.415ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 0.928ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R66C52A.CLK to R66C52A.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (from pll_clks[0]) -ROUTE 1 0.282 R66C52A.Q0 to R66C47D.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3]) - -------- - 0.415 (32.0% logic, 68.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C52A.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C47D.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.914ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] (from pll_clks[0] -) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] (to pll_clks[3] -) - - Delay: 0.429ns (31.0% logic, 69.0% route), 1 logic levels. - - Constraint Details: - - 0.429ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds - 0.093ns M_HLD and - 0.000ns delay constraint less - -1.250ns skew less - 0.000ns feedback compensation requirement (totaling 1.343ns) by 0.914ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R66C43A.CLK to R66C43A.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (from pll_clks[0]) -ROUTE 1 0.296 R66C43A.Q0 to R66C39B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] (to pll_clks[3]) - -------- - 0.429 (31.0% logic, 69.0% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OP_DE --- 0.000 PLL_BL0.CLKI to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C43A.CLK pll_clks[0] - -------- - 0.715 (11.5% logic, 88.5% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C39B.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.588ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] (from pll_clks[1] -) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] (to pll_clks[3] -) - - Delay: 0.340ns (39.1% logic, 60.9% route), 1 logic levels. - - Constraint Details: - - 0.340ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 exceeds - 0.094ns M_HLD and - 0.000ns delay constraint less - -0.834ns skew less - 0.000ns feedback compensation requirement (totaling 0.928ns) by 0.588ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R66C41C.CLK to R66C41C.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (from pll_clks[1]) -ROUTE 1 0.207 R66C41C.Q0 to R66C39B.M1 genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3]) - -------- - 0.340 (39.1% logic, 60.9% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS_DE --- 0.416 PLL_BL0.CLKI to PLL_BL0.CLKOS pll0inst/PLLInst_0 -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C41C.CLK pll_clks[1] - -------- - 1.131 (44.0% logic, 56.0% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C39B.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.585ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] (from pll_clks[1] -) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] (to pll_clks[3] -) - - Delay: 0.343ns (38.8% logic, 61.2% route), 1 logic levels. - - Constraint Details: - - 0.343ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 exceeds - 0.094ns M_HLD and - 0.000ns delay constraint less - -0.834ns skew less - 0.000ns feedback compensation requirement (totaling 0.928ns) by 0.585ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R66C50B.CLK to R66C50B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (from pll_clks[1]) -ROUTE 1 0.210 R66C50B.Q0 to R66C47D.M1 genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3]) - -------- - 0.343 (38.8% logic, 61.2% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS_DE --- 0.416 PLL_BL0.CLKI to PLL_BL0.CLKOS pll0inst/PLLInst_0 -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C50B.CLK pll_clks[1] - -------- - 1.131 (44.0% logic, 56.0% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C47D.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.575ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5] (from pll_clks[1] -) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] (to pll_clks[3] -) - - Delay: 0.353ns (37.7% logic, 62.3% route), 1 logic levels. - - Constraint Details: - - 0.353ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 exceeds - 0.094ns M_HLD and - 0.000ns delay constraint less - -0.834ns skew less - 0.000ns feedback compensation requirement (totaling 0.928ns) by 0.575ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R25C4A.CLK to R25C4A.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (from pll_clks[1]) -ROUTE 1 0.220 R25C4A.Q0 to R25C8C.M1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] (to pll_clks[3]) - -------- - 0.353 (37.7% logic, 62.3% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS_DE --- 0.416 PLL_BL0.CLKI to PLL_BL0.CLKOS pll0inst/PLLInst_0 -ROUTE 24 0.616 PLL_BL0.CLKOS to R25C4A.CLK pll_clks[1] - -------- - 1.131 (44.0% logic, 56.0% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R25C8C.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -Error: The following path exceeds requirements by 0.524ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] (from pll_clks[1] -) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] (to pll_clks[3] -) - - Delay: 0.404ns (32.9% logic, 67.1% route), 1 logic levels. - - Constraint Details: - - 0.404ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 exceeds - 0.094ns M_HLD and - 0.000ns delay constraint less - -0.834ns skew less - 0.000ns feedback compensation requirement (totaling 0.928ns) by 0.524ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R68C14C.CLK to R68C14C.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (from pll_clks[1]) -ROUTE 1 0.271 R68C14C.Q0 to R66C15A.M1 genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] (to pll_clks[3]) - -------- - 0.404 (32.9% logic, 67.1% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS_DE --- 0.416 PLL_BL0.CLKI to PLL_BL0.CLKOS pll0inst/PLLInst_0 -ROUTE 24 0.616 PLL_BL0.CLKOS to R68C14C.CLK pll_clks[1] - -------- - 1.131 (44.0% logic, 56.0% route), 2 logic levels. - - Source Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - Destination Clock Path clk to genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194: - - Name Fanout Delay (ns) Site Resource -PADI_DEL --- 0.082 P3.PAD to P3.PADDI clk -ROUTE 1 0.017 P3.PADDI to PLL_BL0.CLKI clk_c -CLKI2OS3_D --- 1.250 PLL_BL0.CLKI to PLL_BL0.CLKOS3 pll0inst/PLLInst_0 -ROUTE 446 0.616 PLL_BL0.CLKOS3 to R66C15A.CLK pll_clks[3] - -------- - 1.965 (67.8% logic, 32.2% route), 2 logic levels. - - Destination Clock f/b: - - Name Fanout Delay (ns) Site Resource -CLKFB2OP_D --- 0.000 PLL_BL0.CLKFB to PLL_BL0.CLKOP pll0inst/PLLInst_0 -ROUTE 25 0.654 PLL_BL0.CLKOP to PLL_BL0.CLKFB pll_clks[0] - -------- - 0.654 (0.0% logic, 100.0% route), 1 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C52B.CLK to R66C52B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2]) -ROUTE 1 0.119 R66C52B.Q1 to R66C52B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C52B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C52B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R68C15B.CLK to R68C15B.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2]) -ROUTE 1 0.119 R68C15B.Q1 to R68C15B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R68C15B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R68C15B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R28C3B.CLK to R28C3B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2]) -ROUTE 1 0.119 R28C3B.Q1 to R28C3B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R28C3B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R28C3B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C42D.CLK to R66C42D.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2]) -ROUTE 1 0.119 R66C42D.Q1 to R66C42D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C42D.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C42D.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R25C4B.CLK to R25C4B.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (from pll_clks[2]) -ROUTE 1 0.119 R25C4B.Q1 to R25C4B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R25C4B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R25C4B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2] (from pll_clks[2] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered1[2] (to pll_clks[2] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R29C5B.CLK to R29C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 (from pll_clks[2]) -ROUTE 1 0.119 R29C5B.Q1 to R29C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] (to pll_clks[2]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R29C5B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R29C5B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C52B.CLK to R66C52B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (from pll_clks[2]) -ROUTE 1 0.119 R66C52B.Q0 to R66C52C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C52B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C52C.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R28C3B.CLK to R28C3B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (from pll_clks[2]) -ROUTE 1 0.119 R28C3B.Q0 to R28C3A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R28C3B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R28C3A.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R68C15B.CLK to R68C15B.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (from pll_clks[2]) -ROUTE 1 0.119 R68C15B.Q0 to R68C15D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R68C15B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R68C15D.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2] (from pll_clks[2] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] (to pll_clks[2] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C42D.CLK to R66C42D.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (from pll_clks[2]) -ROUTE 1 0.119 R66C42D.Q0 to R66C42B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] (to pll_clks[2]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C42D.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS2 to R66C42B.CLK pll_clks[2] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R25C3C.CLK to R25C3C.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1]) -ROUTE 1 0.119 R25C3C.Q1 to R25C3C.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R25C3C.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R25C3C.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C44B.CLK to R66C44B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1]) -ROUTE 1 0.119 R66C44B.Q1 to R66C44B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C44B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C44B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R29C4D.CLK to R29C4D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1]) -ROUTE 1 0.119 R29C4D.Q1 to R29C4D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R29C4D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R29C4D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C51B.CLK to R66C51B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1]) -ROUTE 1 0.119 R66C51B.Q1 to R66C51B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C51B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C51B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (to pll_clks[1] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R28C3D.CLK to R28C3D.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1]) -ROUTE 1 0.119 R28C3D.Q1 to R28C3D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] (to pll_clks[1]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R28C3D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R28C3D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C51B.CLK to R66C51B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (from pll_clks[1]) -ROUTE 1 0.119 R66C51B.Q0 to R66C51C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C51B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C51C.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R28C3D.CLK to R28C3D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (from pll_clks[1]) -ROUTE 1 0.119 R28C3D.Q0 to R28C3C.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R28C3D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R28C3C.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R25C3C.CLK to R25C3C.Q0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (from pll_clks[1]) -ROUTE 1 0.119 R25C3C.Q0 to R25C3B.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R25C3C.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R25C3B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R29C4D.CLK to R29C4D.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 (from pll_clks[1]) -ROUTE 1 0.119 R29C4D.Q0 to R29C4A.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R29C4D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R29C4A.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1] (from pll_clks[1] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] (to pll_clks[1] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C44B.CLK to R66C44B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (from pll_clks[1]) -ROUTE 1 0.119 R66C44B.Q0 to R66C44D.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] (to pll_clks[1]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C44B.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345: - - Name Fanout Delay (ns) Site Resource -ROUTE 24 0.616 PLL_BL0.CLKOS to R66C44D.CLK pll_clks[1] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - 24 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C49B.CLK to R66C49B.Q1 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0]) -ROUTE 1 0.119 R66C49B.Q1 to R66C49B.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C49B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C49B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R68C16D.CLK to R68C16D.Q1 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0]) -ROUTE 1 0.119 R68C16D.Q1 to R68C16D.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R68C16D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R68C16D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R28C5B.CLK to R28C5B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0]) -ROUTE 1 0.119 R28C5B.Q1 to R28C5B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R28C5B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R28C5B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R66C43B.CLK to R66C43B.Q1 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0]) -ROUTE 1 0.119 R66C43B.Q1 to R66C43B.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C43B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C43B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R25C6D.CLK to R25C6D.Q1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (from pll_clks[0]) -ROUTE 1 0.119 R25C6D.Q1 to R25C6D.M0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R25C6D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R25C6D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.157ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0] (from pll_clks[0] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0] (to pll_clks[0] +) - - Delay: 0.260ns (54.2% logic, 45.8% route), 1 logic levels. - - Constraint Details: - - 0.260ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.157ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.141 R29C4B.CLK to R29C4B.Q1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 (from pll_clks[0]) -ROUTE 1 0.119 R29C4B.Q1 to R29C4B.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] (to pll_clks[0]) - -------- - 0.260 (54.2% logic, 45.8% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R29C4B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R29C4B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C49B.CLK to R66C49B.Q0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (from pll_clks[0]) -ROUTE 1 0.119 R66C49B.Q0 to R66C49C.M0 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C49B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C49C.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R28C5B.CLK to R28C5B.Q0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (from pll_clks[0]) -ROUTE 1 0.119 R28C5B.Q0 to R28C5D.M0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R28C5B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R28C5D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R68C16D.CLK to R68C16D.Q0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (from pll_clks[0]) -ROUTE 1 0.119 R68C16D.Q0 to R68C16B.M0 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R68C16D.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R68C16B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.158ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0] (from pll_clks[0] +) - Destination: FF Data in genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] (to pll_clks[0] +) - - Delay: 0.261ns (54.4% logic, 45.6% route), 1 logic levels. - - Constraint Details: - - 0.261ns physical path delay genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 meets - 0.103ns M_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling 0.103ns) by 0.158ns - - Physical Path Details: - - Data path genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.142 R66C43B.CLK to R66C43B.Q0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (from pll_clks[0]) -ROUTE 1 0.119 R66C43B.Q0 to R66C43C.M0 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] (to pll_clks[0]) - -------- - 0.261 (54.4% logic, 45.6% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C43B.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path pll0inst/PLLInst_0 to genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344: - - Name Fanout Delay (ns) Site Resource -ROUTE 25 0.616 PLL_BL0.CLKOP to R66C43C.CLK pll_clks[0] - -------- - 0.616 (0.0% logic, 100.0% route), 0 logic levels. - - -================================================================================ -Preference: FREQUENCY PORT "clk" 100.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -================================================================================ -Preference: FREQUENCY NET "pll_clks*" 300.000000 MHz ; - 0 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY NET "clk_c" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks[3]" 300.000000 | | | -MHz ; | 0.000 ns| -1.015 ns| 1 * - | | | -FREQUENCY NET "pll_clks[2]" 300.000000 | | | -MHz ; | 0.000 ns| 0.157 ns| 1 - | | | -FREQUENCY NET "pll_clks[1]" 300.000000 | | | -MHz ; | 0.000 ns| 0.157 ns| 1 - | | | -FREQUENCY NET "pll_clks[0]" 300.000000 | | | -MHz ; | 0.000 ns| 0.157 ns| 1 - | | | -FREQUENCY PORT "clk" 100.000000 MHz ; | -| -| 0 - | | | -FREQUENCY NET "pll_clks*" 300.000000 | | | -MHz ; | -| -| 0 - | | | ----------------------------------------------------------------------------- - - -1 preference(marked by "*" above) not met. - -No net is responsible for more than 10% of the timing errors. - - -Clock Domains Analysis ------------------------- - -Found 6 clocks: - -Clock Domain: rd_clk_c Source: rd_clk.PAD Loads: 38 - No transfer within this clock domain is found - -Clock Domain: pll_clks[3] Source: pll0inst/PLLInst_0.CLKOS3 Loads: 446 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; - - Data transfers from: - Clock Domain: rd_clk_c Source: rd_clk.PAD - Not reported because source and destination domains are unrelated. - - Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - - Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP - Covered under: FREQUENCY NET "pll_clks[3]" 300.000000 MHz ; Transfers: 12 - -Clock Domain: pll_clks[2] Source: pll0inst/PLLInst_0.CLKOS2 Loads: 24 - Covered under: FREQUENCY NET "pll_clks[2]" 300.000000 MHz ; - -Clock Domain: pll_clks[1] Source: pll0inst/PLLInst_0.CLKOS Loads: 24 - Covered under: FREQUENCY NET "pll_clks[1]" 300.000000 MHz ; - -Clock Domain: pll_clks[0] Source: pll0inst/PLLInst_0.CLKOP Loads: 25 - Covered under: FREQUENCY NET "pll_clks[0]" 300.000000 MHz ; - -Clock Domain: clk_c Source: clk.PAD Loads: 1 - No transfer within this clock domain is found - - -Timing summary (Hold): ---------------- - -Timing errors: 18 Score: 9647 -Cumulative negative slack: 9647 - -Constraints cover 3947 paths, 5 nets, and 3290 connections (88.32% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 280 (setup), 18 (hold) -Score: 209210 (setup), 9647 (hold) -Cumulative negative slack: 149227 (139580+9647) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/impl1/s1_impl1_bgn.html b/impl1/s1_impl1_bgn.html deleted file mode 100644 index f66e157..0000000 --- a/impl1/s1_impl1_bgn.html +++ /dev/null @@ -1,146 +0,0 @@ - -Bitgen Report - - -

    +pH{uD7Y^M)_dJK0@4ZO6t_z^u^_IfABB*0s71pt?GWl1~kddY<9``9(pk#9U zaKo=}X(q<&iXdS~#kwjiZ4&D|1X*R0EhE-gwpbUp>55e!Hjw$^p>(Y8C+XQAg>`v~ zuB*X=tLtW9y+bPE==!w9O5RV()LpFKOlXDgInoi{a*iPt>uN=g#5x~AHgmtsShMZJ zqo3OFHLwn1z7PCqSbex13{UnbtZPzqU2EuAu~RC%!xFF@tk3uvLI|VQhxb+d{fEH1 zCa5aiKD^eDHi(SRZD-wQ8@V#;b2ljGo(3SUw_BBl3f=6`XDmWus&xY%`l~zg0^qrA=a8h(5f_B3nkR3$q=sAJ6SO3CRp$zE7j+Sl34AnH#0+x)iK91=Ggs z9uNPvA~Mpjjr)T8OnU0 zn`u}}zC%Cl5L8%K*;*g=ZM1c)drkUsBxR&w9gm^*o$8WqAAWE2gaUzel`UH6`<#u+ zCb7PQAbU;n%c$$3Y_WFi_F4cLKEizEfpo090(4ziVcn3_v2OMQE6&sTac#-3ar!PM zWu#%H3%$D#oQymO{)eY_e>^qvxxl(1sVYSuely5?oBh%zvEnEN(aDw(>w;|i@UUaY z??W<=G9NC>i1)*)xvAvW5MA|kuo^nnEfF2-??B!yNEvBZU$c>BNEkJ&8xNd!vBYYq zN*C*vh_p$pIGQW@-A}fRSQlrjYmdw3JdF$=W4>0G^Lbi-p7iFvKBX{1|3s{FS z-#1n|);|rpVym!jis@LlK}i?u5u3i)N*QUo(k0kG4Pn%-W#+@vZKZ;_2F$Y ziaO6(fgne03X&1)JK5^mXv#k&$nbII+a6BGnvBu)ScUbQfR1&isbf7Br0>yEMjF-< ziGLQ*Yk{L<=43PE*>Xt}7AbSdeTPu};kv>*uxpSd0vZGvBUYI@W&@ z{M*7bg?gCp>yVDsj%!#;b1eGWF8wsDWqwxjPeK?qUDqCdMV`NY9a5EUAGYJtCb7Qf zXNXR=j98at+lPxg{!xYuM=;;FMmp9bVgBW0iFIc}$4Yxtrw^CbM5#C|vUJ8PT^v0k zjT+XZw<~%G9S`qxh;XrreJN&aiS>PxA$s*#v(qzF?W2a#)tr6wlg_c-% zBz3Gmm^#*zP%5_5u+Fp?LI|UV^{4jV$!CssBvqx0^#@bhB-T|3auT;?)OC5bSUbcM zU4Zoo=KC?0jx{I1zj`gP?g{Hyf3kF}`EmLVw8+xYb(W3p7m%q_5V3#lZLeJ=blnqH zl`htwENPQi;|P);CtF6WOSA36TduiaGq6UO@8?K5*8C7%HlT zm21jK8?UqdNK+D^>3Z;Bp}dCS9#pwlf2APAip07GK~D9PEhE+y+3LEZ_?DiCJ&O5$ z3#DT{F-faP3hU2?j&*+!Sk-z{Y265YZ;LY0u+Fhq>50;)VKv&{E}t;{*$^$%JUj<8 z;QpYr39R0O5r*hw%ZPP(wz^J!_vgdNa5VEJ{pnci8nlX}u>KU#vHou9SkED>GIOU7 zW2vaLt^>#E!#5jCyNN#hQ$XU<)?j|Oq)lS|JQjw*D6-z}3A&i=?w@p}5BCsBCh!B04bUkRx1`_L! z&^5qq8L=+SwhuQ+)_opWpJKj0h%0Rp>kq(xh}$w^eK%WOPYztx2Uy22-{ELF)boBNmk#IYixs&ugW{xYOZV%>v2+$K)8 z%viJ4^{0dHz74EnneT5i9qXSVT18U29`@^4|3RIL^>ROb&yq6I<|Zr^`Th(Eqo(Va zzb;%VbUo}>l`htQR0E0iJM`hpxnD-C?`4bi`5HfMMTSo^-?2bC)}uD9A}L+lgfy%L z9-wovUKPQ&4NZ}`qbn^H9kqo~!}{0IyE_P7+bCS_+=RHYfyBDo!%DA;kS!zDmD%>; zhV%FL2iE_w0_@XL&tFTgLO<;iQM&Gr=~#1s&c%8ySZSCPSvpv;RD=-1s9}9+{ol2O zuKQ!E($TdbCn9YU>n`YetxdL!Sl`c9*DKb|@B-^Itl+prI@Zf#w2CCL7I>mM*4(&` zwL=hCBb1TWhZotb^fCvIGhT05^VL|66%j=XZU0)38<#eTb!U*3b_kL!Bi8q_)%ArM z)9ASASyoWPO2>+IHLM~jUH?tdwU%GU+R37C6^SezUElGu(i;=PsOdU>=Ob8srDOkp z9U@#^Yx!jZiFJpEm3FeomJ#dw*<$_F*gXhXpJN3lgwwHJ8>UqxrE86Vt}7kwyXQGL zlEnA6M3xTLB^J70SQs^|t=s>`gswFLs#0KmGsp_WalU(u=#8+_&g7OEYdqUNeB{`$ z$-p{}6`UMQ$9h|oR*@9e+>nknFRo*S`uL8T$lSq-rJ_=G3#EqjzAI{+C$Q#*L<`l2 z32RrJ~YKj&#m=om1C3Ah4b!+0n832$pv2kF%1}?s2kZ#5y@!tVepBcM4*UX9Yex z9c%Xxts*I`I1_M>B??Y~k}g)$Pv17AjI_B4OGTyXL{HOo%j~gt3#{&mf!l{qF+~)0 zo`Z;`rk`vXvA&)y*1EqY8YA8dtl-pGI#$fVSVdA;ePJDIZA-`6CqiF!6j?gDVyURK zOHvp$tb6BPEZ)FX;FB$MU29vift;I;#aU^e2-z}XoslipRnHE86j-CIpiU$mYafGF zkrY-Vs$;F^(XsZkft3={b)}`EK87%ASPN$yyF=(|L{+7$Ydtc#eV9H&TH4PhTSlyJ zW{cH7c2r-)evuW_52a)66{A%og|&{MV{H)Bu?|3~g`YCg`YSwXX8I@TdkT18S=PfzGrTYv{w*Jn{`CKYjX zrKO@FQJK1{>vcVzK3-rwUAEA%wg}4x66+xkD}9#RGU~co!)jLdWsKn$?;i}Tudsra z@pP;M1FWz|Kw)hb;aJ7nKnl)|=~%~uhZkcaO9$%*7P?=c64n+KLna8U%_6eWeZvUi zN}I&`Mu3%$PmnDm)>YZ|;YMTsc^z0MvVvC8bgbh|V6_z1rZ|fI1IYQlgatNz66;k9&~l4RlM}_52S{%IEVoyuZf+1Cv-mYg00CGOM-0 zhOP8jj7^}dwZcTHpp{>gFhQVhVjNFT_*tzC3sO;K9HJ*Na^ zJ6<={&r8=|0gSA4nuiq*GuZX@BfMm@!kz}JS(|&l7Dp+9TO@gDx`k5GgCFy#bm>DF zNLd(V(qu#8%EnX2XU8agW#a(2ZIY#I90s>djwl-k!)>pc%Elpa+mxWPO|p>`w@vjc zTa0W*flUyV?KPA9KJvqcS}w4Fn*XuMN?(gB8wZ@f&SIt0En)L`DvARCN%RMe=R08Q zlUc!q!F17I3-MQ83eiiaMs?9&O-S)fv@V@&h!SV3;OroOIb7vgJ z=%UX;6v!+^$F1gtccPmL(cehO&l1_Rz1cDPEDv#@iT+juWQBxL6CH^wn=AUO31xFd zpKK@_hvA)v4s&);**F;9vC6{A=88Teq->LHB*jIa8BjJZIv04Bp=?6*^?p_=?smth zmZA@_Sm_%H@*|rNeW*>Kg$<&2`ER1%RrmG9$nsTI&`#~I)zB$@!{qO>l%mhX=%R5i zMtYg8i#{o!iC#JdlAMI&HzE3T)KNPj`n;qr`uv10`rBv+nWgBlC`!1)Lx{d0EWbBo zBiqu2A^P49aiEF*b_8UZ!l;Wr(^589^fFu7T+t^5lud}f5F47piN+)?z;My0JASU{ z^OCCVBt#aX&rc|u5S;{mJEm+x^iNGz8jF(675!28EeI={5dAUuEer`8MDO=jg^uQcR`gm}A^N&1iuaiEF5I1aMN2BR+e+d*Y>MV}W@ zHdpk?G9arZL|+WfP*4z{^9*CPe?tVx=nr zWOGFy2HQ$Q*@WoB{jep4jYj%^+ow0Ff7j#4aw;ph)=n3Fg~i`KDMepq>!L69>!MGH z>!Qy$`Fk3r=nG^!A$oaG7k!go7k#sb%Pd9TjCMHZlOz3$xcowpjciM|SoDP);y@F9 z1u9lp!l;YB%vLs6^re1fb48yJS2iK~yAf78-&8hN^aZxExuTZ`m2DDgh3K37$|gi7 zfj5(hcS<4p1{*e;Y_8}dOji0uT-k)^Bhhw?C2SDA>wg>Rh38z^8CgtY1vkahMgIaL z53iM!qHl`oq9+o%=+nZw=*u9U5tB1w>B@*cy>GR3(YM8Q(YIS%W-0m(v@`um^qr>s z^pA~fOLqn7(>KI{Ci*H=d=U~xUGz;+Wm{~c0Uw2lgtED!PYWxX5PfwVQxTcO%wgmI ze0pCQQ8rift*8}#lkk_=#5d55T+yF^-%eB6gy^H-w<{=Y z_yGG9|9?7=`{=@M#mMqCR&cA8F8Yq7kc%I^mu?T}qHmQlbIwX z8<9)5pdHnTk-kTIa&Ah$hm@$3)B6vQ@-a(I??3t>dQ^$N*TV|$QpYu=du^1YM(PlR z3$i0g#H3E|+XKqxioR7gmZu-QBg~2@KQ21AmB*BggWqn~W9=;bym-Ag8J6QXbS!)6N`ME~r+iQaPB$#)~O>8zk@ zBwh3$qx@lbInuvR=%Vj2gp@*bTwm2h-xlJJjmznMr)(!g-zPmeH>LX_r7QY=NC}zc zNKeKgtgS@<-I6aX1#(t;AVM$fBo4HZ{$UUVMukxy>E9=m%@uu*p=|C*kNK5NjP$h; zR=O>uY+Q8SvE2L4T+#PAZ711Cii^IVn!2Lrlfe5?D{MmaFHBaNjFZh3{RQ~_ZYi4( zJ!%tZVT0(OTmNaK&s%@&M`ZCjE9hyai~f6nKjkh(-yhaR|1GAAz8nHUJUP<$B>D5; zQuMvDoe=$y^yJ)>9)^^z=tm$WWR{};WwOG%LrV0&gYr$JHnJ@}>Zdnx(oYk8T@Yji zgi#lLe^}XE(SM66n=AVAxUvb+*T-4uo}{w5qVIL$xuPF(+D@{O6c_!lrP_+=odiA- zQ8pnu4o*t{GRfwOKEcmQ{|+jf5d9^zJ?a-W8tMN{^p4|4Y(kb6E9f0e7yYjUe|%kv ze#Fp4KNQkM-wa`0(f399gWgi~1F{`wsEk2M^5oo<bD^s?h1C1e(&mz|1scgLmZ zWv3?PD@JW(TXtH4Ua?6WXrgb3fWU+>>Y^Vpl+6|WP)ONa(Km;cO^BZGu+n`|WphP8 z;KXx82Q1|`$wpEnI>0HL5FG*oqOu9mzw$ExC7Uby%kVojscb^@iSRouA#60#|J(F_ zMR>w5$g+eL+~-ddz3kKoe=c2!UX~NnL@)C|1TLP5)}=cPUG&2N{sgxa{cqV$h<>{C z)(Ho*&?|>4$QB=M=)W-J88i(oKnZ$u6`lblTiU^}7IuchlM|7mG zY_8}#3}q9dZwa!}!vSS;MgQB0=Zb#1({_@Lq`2s(CskV^Itkn$p=?6*uT56gFh(|4 z^hvNaiYl8BeX>QMg$<%__-~>g|K*BVBpWMu$dfL5BaFP$Lz2I;2Bt20eM=Yp2M9!6 zfU{M`68zC@A$r+qvYimUsq~y=lX%Udy6DZrTxKbHix5hd61`uYdFfMwtsPYq{ zlfccx$|gkr#$shHLS%DAf7NDXEd$CXM8|q{*;$6Ld06h!|0eqAJI~ob^s|D&cDm>- z;zDMA^j_B7ql?}&sEeM2K(6SgN5q>uI8SAb(XM7v9=(^fmY$Pr+Uj|b679s%dszTd zJ{C~ZdmzaQ`xr{}!UReYxhh$9ehj4~aiEDl2LW5eg;5v1Iho)n7ZbT4O@qqjik=K9 zn-G0wl9invQ8pnu*&36H$8$w*?X=~<_%_Z9C_gT`VL-Tmp=?6*tu|~)vbmyfhhJer z*@WmjEC$fR2GO@vA^IM=yz->YYVkkrF{`=Y5@=)5f!qvMFf5)fdZDQuy_cP5;c}rV znJYWj)`L(0>vX*GqG@?YmM0!rLvDLCRkkS>sElFu8(c48?A*IfjVaqNJ zqm)phUlwA8eS^e-Ci;g#kYx&^68+COdX}YZ?npn^RyJ4kBgy|q+O>d7HTCaVN9S}w zjWg%W5M}G*e5o*p+!98TkW5raWfP@DBS|GSx(UhXo^GQ#mu{GpN|7l=QW@k{s$F~u z$+#W2@PB{nviF)fXU>1V=bPuDv)=VvYp?fx*IIk+wfD?cm@s{F7*mm!u+lO8N>~Y-<@Da(4`buX^sC&gw4b3&@9sj1Yo(cv)qCs`(uI#gK0P%|g&}l6 zVUFn+h81R;4iX9zrepOUJ3FB;Vfyzt#<>B7Ii_DB8zYHv)7ynqoG_gXzA~sVVfuk6 zi?#O?=9vDa!D3gr6(&sokI7=)2|^r9-}1kW^iO;KMy6M=!U^F_)7!&JUs9dZ+gYr% zSwfk9g`u0?B%qsqk*TfTW0z1ltPHq9vD;+iObbVi^)z(Td%3vH()3;^caKY%-aCO* zNSS_n6e-kzI-FapSiQ&EM+K-x`VkzYoux3x^eYU7Ii@!WC`_1+)qCtBQ(?mN!#Ktz zmcks zo&H~pboaIn1JQ~~RyfJbG`%-Q-boQCl~AVl53te!e$qfQ{ev*X3JOq}ejtFJ z6;YUDdXJ>S9MelIg$dKKdXKduNX#4-{%!azux@sJj_G$HSH#VvIBxpg355yM4@Oz6 zZ&YEz^lyOm3lrv;{;kDg_m~P3rhjL!SpR^)VEU&2ZKRJM`oMqC%0;YjN+8qpekpzR z-q#QFLdx{JLb~aG8046KTO2PjazS?sHOFp8xpPoXjP(0uB-bW32v(w;T*!rBC2W?a zKVZPvs4{)9iq7Dgo%*C9MkW&%g(fv>4QuaCrl@ULji>e(~p=e_JBc{WBT`q8%z+#gy}yR zz$}5eSiui9nEqcpIdjlB!HZTdW`(niOw%8T=&ScZNqzNxzgsuG4GeNjzdI<)p_S;g zvYaq|n2hAw#D>F4$MoT_5;jZIv9K(?H>FH}B+8%J63-OGMuu7GK$A4kOsCcR0}%l# z(+L}tRG4G>{ceRhrnfN^CPq4yy*sEdZaQtlf{?--(}&q*XIjei;S|Pa31K=JJRG?K z6Q=(NY(#=E$MiR&EcQrLVZ!vEfQ<|b%*E>LtzmlqFHHYwT-{61iY2UYK4!1y;;2{M z!H7NL*G(TD(oKIjuA6=(4024rKP6slCPw;Tlq-m;k^Y#Bz)HvTv9NMjLYY3! zgt19w`uG4Vy)U3f`UC?hYHOzHkN5?sn?5|GFvs+VWnt}xOYF*oiW8Pbaz9G#m0seCQSbs*f^6g$Mh;3V|+ki!t`IGEH=Rq z7^e4t`9Gc02S-lFg9mIWD~ws0rjJW%k4weIy78-ahML|V3+kr#g0YV2!y?+_Qn8UJ zcUC}|K1W7!ZDMnSy6N-$+-5n_=cC;HhBAGA3aN-PeL<3y4k8J3)0c)JU{Zk6^hS*m z5ZbLU$Mna73Ufw!uaLro=`XlgY*<8LVtPLw*hsrR$MiXN*_oCyeQr>d6(gMtp66GX zF#R`R^WB6wrvG68ODRm4{-?=e3z7nZ=~zovdoc39Sjcsle9>EIdIFV`ke2lyX z_CjuM0$-akmFaU_y6OF3kYoB7zxKFPYk*D<}HTVcZVm(jp6 zeuW9s>jy9j;|g<3FSpCiv`{Y}>E$UECrl@UE0PKmrXP*6SY@0r$MnAq7F!fim@xex zlf@Q?1P0U3{NGG}w85a3Xyps6@TF*`>5DLl9v77Q#VSmg7gna1MRn6dFvu}|j-@>= z6@JdRbIqj_IMe!i4E~Tq-ulQkXEkAdC@bD$FtcMY}8~#!Y`IqT+<< zWNVVWngGT3892 zrRi%^tn?wA#l?=?x+GF@W%_GzRyx!m4K&l&qQd0~0ZP*w9t}Wfg7~O*On)(;Fvs)} zL4^s^UkhU@3M)*Qo{#z#6U6ItOkZP{<;1w@uliLSH=P^2)~zsMdYveXtxXZ;n4WL3 z*t(>`gz0q+7JDr&FqnSM|7QCAh0o%VAoda~TxVvQ4#as}D)wp==J}QBt1aF1u`tLn z{Uw8y`e}x+P;=~Ml=CN)=^JF^OrEz9RywA?2`gc2C#* z3Xuky>2Kg*>r4TvkzNPbt5JnHrmwaX=9oSBkx@_Eu0}xMcgrsD4iWFIMl1 z7A+f#R>oQ3hCrt2n_c?q{mp>BdfyP%O`iv29n;q&WI2mWe@&L-3dMHI$eBFv^RRCE z9+TTFP2Y=h592H@Oy6hlub#+DHp_)|KG#4q9aBndGwH%dq1c8c?9G6}9Md<173P>e zFRCyx(y8p4gu=M#{F3dpfWjQpcSjY*iE-0E4=YTVP6qEW6*dolG52x6_67*EO>eZx zVzGUO!i4F^N11qP8*woGY}0kjF|6KdEV16l7hCeYCSxfBH(cEKYg~|y_aC6kC?2W z8IOG5#fm<{q3f6~b_^@{G0F-Wnf;nq=CQ&L0tig9ybdbMRaFw-)oJFPtdJhF92sB* zCs}r>Li6fFb=I=Nj}2tu&{wHaEblVw&B?}9tniZ*D}B^p1t&VCPB4!i+<6--{0xnH zG=frgR^Fvn-UV!3kD}K&KB`;hre6LZIoCy3Cw9_~Om1a9;>n z7ArtEvw2xv8x|bH3ipH8=pf5$Z)fGTwR#VI4$l^T;YL;hEp(3Mwl3Scdkic5(qg4y zKg+w)&dR>iNUKPpt4Dc!i^^z-MO_xXprF9^TCg4}sTXZj^G4b+J{v3!T;b9Y5DYVe8Ft4rIGyD{OrQ(R6m5wo4L1U*>p|wAF!FE=d0!&u=@;59amET_U^>zYv)-Ny=liL=si z1}iw(DdjQO?u?hR!e7J4im-xHoKi*B+AXY@75)xh<6S7_WO=N=>U3_)3jYMJ@gbCQ zDl9VF?CRoSg@1w9c#E;84CNOa8|`}8>@KYEA9PW4TK0sKHO}}pKD9pcxRR_0y_-E5 zwM#u59rD31!RxP8s!;%`gbN?$YQWf7!^4MUrUh&ky4RkYKp8=I&lABR#G=Y%BaZ4YdZQd z_xcZCfJo4)gK35+F*c#5I`a-pxaWLUQV=4KROI6|MY1-7o7}-l@+~r2MPjp~x=OBB zJ5FAXNH_Hs87U^X5*B5J?{h5AC8x)dV?s1Via0!vj(M?;m}Kj9i1IHDy4cm-9-6LHfT(+e2LK-l0c2g--nl7Czzb2G9?o%YGOZgEGrW% zYE6(>yt9(z1=(pm~C2 zUaW>6?EQJuD~}5%=USqKoYraa7dvVamYs>?$;GvLGI*mmjMluyJm*#Ozc)ald@wlPR5wj28{`p!!hS!Se$7wT<`+}MMqcS%ltHVU1*6C z$`dS-Q4?X=n9%i(WPvtE1{ty#}J7gh7*PmB|+xFwS|X`a-@IC&%~+GU?l zutbmjS$&*@zlj@yNgGp?P)u+FDythMEGv_f?A}#SSSypeTTPz;CT}p$CDlCn2jgUH zKrv~X=E<=bCnMvcT{aV3QN;d{pw_!K8$Ig_CT%TILNUP!sO(siu&hjQU8p=cp;jg* zM?W;cB*8qFW_nVFwH;m0NKYWu_b_ zI02P4G6>7cE`sH~7;>9=_9Te@dnc(uWtU*dP)?rfC?v~Yp2__5)B`hlwT+=Hi?pm3A z+j(|f)cq#&Tvg4Jh8QQ~#mU;mJRQo znUV=kKxK_h!m={KK7-Aq)^YOE#P6@gfj2SF)zv&H#5frrQl4Cs=1EhGlgHemT{e?H zO>~x!05vA}w*NaJm|SDZOvwZ%pt7b0VcD5Dy{k^Go;+L-z5+}(GtafvJn>?jjJFh% z>(V?q4ddjolxUaD1bYo-UcUe}CM&wX7Zpsdvt*`Zf)h~LX&lSS1p6_{lfqh=oV})X zJ1}{Rc{)||5${3bDAe-V4RFeigwvd{&BIglO#Qj$>_w?gMvwCGo1-eKxJn{ z3Cqd^+eeCtx7ObE&X)H3!Q^e`xuKdTP2zlGMluPed2%Mk$=Cq3!I_0=C#S4QT!0#r z?~nYazhDxyWTx~4C!n%3O~SG=Y2q*`u9eA&uKu(Z-oiXxs(FHE*k~U~GPxz%3PiW(*?6i<Rp~%J-O$_2Ja07E_c^Oy~sEK2BIxCfNE^Op0ptq@vEkwP5lt^W0j^leP)IsVF_^k>*Lq5S?p8 zyKE-dg)D2E5TG_rUT)Y;_O2e5%#`DVPCy+)gk@!dom$1jQ!A4xb((YqlWoj%TQyGt z*g35*)i~*u=1C`vlkvO_+K9)dX;~mF8|#dduAS;1Cp_t8%1p_GPC%Xfgk@!NiqpG_ zYVBR~X4EYMlkLpYyP7BM1ANO?dUAW3CpTc6jJHI)Y)`PqTh=}xK+Tg+mu&rg611ZtclOFUy7+c!2yJ-cK!oKXgto;qY1aG8p=q|xe+gml zG0$Btxdmp^yfsX_=ZfYnaen7U(!AN?cVxr{W?47Td@RgF3(AiT5NXjWRT*u?m)#l` zprVOAin3ec3KKMOwO@9#r7%vDZsgz)5)%g@>NpT#pb0nq)oK3X(45yfcsgh%nWvxO z?DPpYKS_wIW#MLzAYC6TDs_<>k)oq$j?rS}lY{^j6}lkq5mXpa(LXdN5*7UeOggqB z%*yNXvfQzj)g7yUa@6ja-=6piV%hu5Gaw+TV4MglyG_ygIF<4S5!w<{9rIJ9=*}DO zisgBToRFaQXvC#&6=4eQIM_iIL|x5S8V`9yVOK3m|U3V#M)3 zKEfaTE^NdQgONRLygK8oOK_MEnP-q&-i1AlWpndd=2|Bc1;n^T`$w%@}%Lri{_&bz{?@CK{fjC-+B_YgFC9Gk86ELCCN z@z(k7Kj$*f!w_tuTi)OB3`h02{hNM2s^O5Y4CWc(=961q7p;1;OYUogw8zndebAYq~PT^19nuc{iGi$1OaTd0=7b#1v!yF;t_NWxUXMOeyn(aMgqd;UZrA)BlbL5MPVQK6<=y0zy4F1M;=@OnXFQckvU>C3 z8uLuR&6cy`Ebjy-@OZQ7%b#IE`Z$z&GLUhv?ySo`y@q+7i1PDPUXiKVo7c#!n|J&v z%=2Utr6AjvQI*B^MIYQax*zjQin2yn-K5`x?6&GUsP%M`FLm>}I~8`Z%n?hkXP#$V ztn?`ZRGh4!xoYk7NzC)C8(Fv{o@cp0WeQF*XXA$N2~J=`v*OTZKl4ltv(ibJDbwyq zj$HOzA@fWR^2I~m%}%Kst-BXJ){J>(P^l1O2MwEw6`eP+(b>#1E5aI8;aHB%d2aJx zt*%|jJhKxhWo6uieYW?r6PRaCgkPHEb#;yvw9Z?2@88Tb7p0yKvU+nlmHDXN57P@R zb>zH;mRZ#7M&?-%LSQ1}zUvop}Y$N{)B9|LXVz!LQ8QgbcCBiaq`S^ zEA-}u$DAT=h2r+Fij3B9<1oKzhpiuoTcOi~DsoIsk#)w5d+;xDEA;t*ihSItq0VE9 zKRAHft8^=Lh^Znc)Kq8Qsn>3sEN+F4O{vJoYl>vUo_y;(aVzxcq>7wS)6reeuK(pC zek&B7smT3Ko&SldTg%6+Z~tpQR&sot<|B&4oX_?tOCaNVX6HHaglXOItJvo@~MS{pZ_`9xd$~uv-C4#uMl5*OHa1L6Prm{I7N$Z zYJ=tp8dlaTBtWfqx!O0zEq!9LJ;M_$;ZYM6$jamghsly!nf$Z!&%J2PUgp{1&t!r# zFkSUXChw(!d-3dzPgz3aZVyH66HeBe)KLfvt4sx~J1$659) zyv3;PeA4f?NBV<_#XKKY^CTSR*J#p{o$v&6fSkLgW5n+Wi+0(b;G(W9EJ3YztxSB1 zae~V_&rU^CdV=e@vgyfMnKW{kJZII$E2Plh5D@u4Sbsu?SthigwwaJd1HMIV>CN^seBf%IEpDu;(+$UCqL{2ri37s6bXG zjT|QLL~HY8Q-cZAyS`waUDZ694o`5gEj_^+Ut_W)L|5CQ(KZum*mP5XnkUN#zjvQt zVlVlnC)0zhY)Oa;WMfk27sK{sTdhnI7j?KBOul5EJ=Hv!8_-Am-n4PDJV-rHG}>lD zbJyH}05v9`wBG-<=w0?>s*(wH$K^pPkc~+`wlmbaYkRG|>p$&283rc*VV-@}Jc$`P zll^I)tnpLN6OB$|5;Fv-F*#cHAD{4Kzh7obCe$6*a4ahmpJg-IU8^S_c0c=NFgeIP z2da6p#KkvdWbgU{o>bZ6@{N+#IA zDSN|BSXL%Y98W&2)sw>wAN>gj#tQGtYM#U`YAtUPRx1bLiNjujdzRpUiW!yw*JRD<-SSepgjXG=_P83nCR|b@^tS z=l2LJea6l5J6LM}H~&mCaQ}XpVr z#$8oGo>zd#DTb@+I-XY-ky9eBsvCG-y%Z~*iraM8@>Bzqn;Jqn9(gPxr&_M6Yk2B7 zL{1B$79QCUk<$_=$MYJ6Sm|`XtEw~4bEDk!D9Z6vAtGnET~*ifln0SB!e}Q?Vd5yA zkwQ5?wYoUPN@tp`s*XI*hjKHM;K%b$MC7c1tLkc=ho^-~XT?z`&pR2Bvkk_UlAJ}S zgpi6bHixI0pxkpV#@^zZor=ikaBpBS&odDDoWs4=y~$Ip5IH}| zSd6F6Lgaz~${AGdY(y@IGgiU#&PlP-sDb10R4K~E5{#Ae)VYW(^P^6K%AJSEGAQ4Z z>vBFK@zV@dy?E+^5K>US2UqYylq-kwy?N?lMB?JKsvnPRgUAXf-FnIOM8o&-1PfA!Q-O^V*}_ zlAx=qIZt&!cGo&L?kvgs_x)<*Q8kKGB@&g>N=EL7IsycJhBra zm!;5`c;5Ahd;!XTz%{!8kuN~`cX=upVx=!a`JG(BE-3dRl>d9`1 zz7#d8!8@mnRsD@>EYmzU)UY z;N@ro;pHe}3wd5|lw09OPv$8Tkt@RRok!k*$Q3EZ;5J%zCn8sxI0Db>lR_$qJf6B6 z4DB3DIN{u-Vd5MrgP@g4kiQ98oCD7QM~s%pX2 zy$_MAEtcQRq`dnPxhBZ+&#)*p2$5?NEWeX!PiI$JQ%8ONIV%cbeH4wms?Oo2495Bc z`{h+<^3;$3Qn2}yuY>wNLp76G(R(+QozIF!C&Vr4>74mv;QD%m zv1vRt23*&>7@N*384IrKLySGk^Twr+vJlDhCZOCKLB=riLY2o6`9^}VsXTHbA`^b( z@zj%uOhl2#BcBSf(hY9Lij{t@s#j7i&c690Rx}Cgfmc(E8BW%4f3xN{&SpiE(dIRA z#+q7^j;m^PeCg*Wk7q@Z2y3)D#Mr4$sYm?hZ2EKwE1H7y%PXkxRHxLaxW9E|8Y`NH zGxo~3tLlJZSNLfB_~5TkvZ5I-)@TKmigqbh*JrK`?0lIO&2pphVSJNQ9Sc!rqk&I7 z!-{5G$ilhobSJB+X*PY~RaP`7&Pq4pai7ywGg#fGR>RI~f5({@Hf>C@x;AB2w~2Y& zWuH96iWUS}>6-yo_g_w_Cf0WaonBx?&zs1Kv%1ZkET1+0^Qxy=QOwUuHyJ49G~*QO ziNr~_v7&MpvLcLq$9htJ_ z_xv(}6)khKM(?ATp&H_?N9?Z3XqzBR1qCHTAp+V79r zS)=?x|L+&EqUG>;d&pH~Ii((n|Jio*FRW+R<8YxdT|yI`Dc6 z6=Er(vWEG)_b95vie3Y+&2h#s8>p-`A*9Qu3*&iv9G)jw9>xGtJ5sFlZREA!siYq%JjQV*Pr?4uEm%Lc;N?C*xh-Lq_ivuJ z6Omi6EIgCveT2w&OqSQ2r#?m`nv>U@M}CrGrCS3mPt38Oq1@KEtEw-b*mfZjvwKxv zKI!d79 z`ZmN$ce;?rBM+n8&JfExhvywZ zi2N*oJRW%zk)OpG`-G?dLgX%kvCnwq-zlUb$fH!T3*~l0`8!F^Vur}wP~POJJVfq> z@^_Ge#dQ$*Ih60oQ~4pJp!{t-vH<1wK>6EvUOhzaf%4sWsy-t3y0N0;kqr>JH;k7F z^1NeHNTu)+QJy*;<@SN!XVmKAhKSq;exLGGBSc!@_bG4n35c}7?|q&s46)Mv;P(NK z^q|~+@OzJ^iV=Chg-D+AA`*Ruy~oS>5P862EXnguOtI20f=Kba#whm%)(7i&-pPpk z($DfSiKAtwAo5G_yP3DTDI)&^emC*dsUf7m??#?7Q0_k|R4^L)fIOZ$BZX8PKk&{||3^r`o8_;MQn}VBcR0-QMLW+&;zr*vcK)Dq7t>>wB zi2NbQ^55pED-roag5?ViS0VC8Kg(as^E!l(in9DSqjZF;QSK)<%TMssHHiEv%nDLG zbuA))0>AHg>N-UJY(f{F>Xbq%$@2L;Slk)qehIMrf16b24T$_D4j&9k1rb?gu>7_b zrEWxIRfOeV%2PLmSn01Wc*G;SqTH_`{9vF-k=+sbtHts!;;EYv`CAaWL@DnUME;gw z`4{lKTT`s`cR$NN&!W8BQ116Abm5Ub5&4Iknk@fpUdtUQ_h*vj^Es=y4Zjg<_K($Z2zdTTm*(Spu*U4ck9 ztxxU9n(Fkt^!LV2tYlb#7P%_&q?+n1JmBXoS`VDzdnyqc{4du){$_x@du+B2THQ&W0P>l$5fPhoI+Mww@=~ zROj(|-~4ecD;WYkH<@;wHANnGsMRYY5eYpv236$AH68uf*Bie%j+HzZrbU;EY*JI5 z4K5k_P>7WbPSMIuL}Hy7t)Yk1?>XR&dWbY>`KRhUp{AqPd!*S%$Fh&iisPmX5C2ks?HN@sxz7Te7pr@-MSH9C2w{h*Zu~J0H$}cQU1=|# zZ}Q~%H=x>lR{TD;x_`7#7~ebCj!Ia`ZBg2tV)Zsts=QTzcBfdqcM-!%dbw$L3MtAf zUSQGg6stFer;;d#-6?#SU0KojeyUJ_vdW?h@PK@)fWmmiMHj}YavL*INzuiAI)uXb zL5kXhSaC8+SRO*^b~pcju8oEnLlIuUig!ZLG_J)vz@RdqxE6(J4^46{Z)eaRn&eu3 zWq|h3B-irxNxp}MW@ub5i8EA4ZG$&LzM{4%?1hIFCb(YaXQpeoHwJK z)(6-j#7E=Ghy!n%!xb2+RU8CY_>anM%p|Vlf5)K01lM+myT(tL;F^Q4AN_cE1;XpG z;$4wUu2)+c*YehIl6th@dL4A&J(?O*-YJe0dbHqreT46Sq8S-nueN|`z7nt2hQb6_ z;&q*^373-kH4dTT1lKDOcYTB~&h?fYd|lV#gaHVz&x-fNGr4v`&s-dmz7{9p79XJ& zu?r$aBUJd>#VvZf;Myg{cX!bYjVt-kDF9643J$1NVS+2hCMvfv6Y)jp|K(lW3KLx0 z6P6;3bM27>*E^f}W+J=+E4GrET!ZMfi!C)?uS`mI7IEzw5$pulZXq$21=sFDzITmg zXk5vMU=*0fm3Up5RG8pOyt+ng%p|TfuDgX4Cb)J$+3rEYIM>^9=)=judpaQeSXTT+ zDwAtB7tN=NYsZ9SXA#$1Qi7e}dTUb5RDx@dINzB^Gc>N4H_N+G(=@Kct7Af8f-CX5 zC1qnKai#g{)}+D&S4UWuBU?tpg=*E=IR*FGVB9|g_G z;MyxeZF9I@172Oi3Uj#9riO@fxZW92nBaPypOyCs5hl3i(1)*iZDC7vx*S>J_1uzg?dj$C1D|yZt z0PkLmt3G^hkl($MTnGB;?v-eo&GiO9ID`eLxCTQQa{+}3U%SLv`GAm(nZ*All)X2o zFu}De$`14s#<|{>Lm!@(x8*8?yIJv1kxZ^w!j{G{Xav{ZQGSn2a=jnk#W6>V@j58Z z@3Bd)p$Oe$6HT+Zb|Vg!02SBnDU8FY!UWe_!0Y~`jhV#tR+JqSSD4`117$-I!Z_F7 zIr!SJ^PlSxegZ45if3{i1Sg&G+Q+5OO=FQqo(rzy4B@%x!{ZV8GM7AKybcPe_Hy}( zXuj%0kk*IE|FHoZGl?ttKh98?;Mx;$;|Y>|I0s+*g^wSH@IqGndoq*jSh(eI?Pp4M z77kzjcvSXilTs7IqDKp^PayK;C|Z#@H;uKu5nPE^KU6@0aw6co9*^3XiM%4}*Av4E z6I^?N{}afST)XDL^@BTiPeZte6(3Dya-HbrcX(wVzBeI9s7351xx@$+zT&Ym-rEJ& zrxCfrP0i4JB_AeAQ1xNraBo5cDy}p(ClMt0o5Yp+|0GLcf@^PJPbUcDeYk55eYk4d z_unJDh?|Ck1Ks_{x( z=Y?&|R9xrdFP-b%epbF9Kp5xRJqKUUI{VcV5q=``9v8{vIuA~+wAT{P#`&`$lI!#E z&f&T+p>vHz>A4YVhQ^h6&9gleT>Hi`4&x$F=lZ;5W2WM|FrhHvYd_Q%ixS4U-cp0F zyR7v6re8Ncb0fk}V%|paOs)&zq~q%hw|=c&0q@HEst;Eh{5cpoUKhFOIT-qAT&ce< zv^^AD&j&WcEdmwSbHTqNU}Gk6?T@%hLt%m|7H;K>2ohX-)WG$Kna(x&;+FFf-k5m{ zlbKvA;H1O#xsc9v3A}T-E)DBkmzn%2A2cI_YlZEh!}Ylkwbwbn64xbB8#5KxrD25$ zuJLm+8F*4TvrAZCb(h=UjB+f7;$BXqplmUEqoVFd?^!u^fl!lcd0-6sVpo2Ma(_w zkG?AF9`#2b^~b#`1{VjS)V=DD0V->t`lG+f!dAKnzE5S{ul^XQvhG)Z^jBFSg@hFH zfcj&Q%6dTkF-T=SsQwtNvK~}_;0}ps#t`*K2bJ}(LWbIi`eUfd8m9huNM#MT|4>;Y z)E~oC)(G{-Ln>>eLPjd&QT4|oD(g}8$0I6hwEAO|${MZy7^Skp>W?8RYm7o3vk~>j zV=8N``Xj8e#wo;YvbwFP|6Ggvr!x%v3c(D-tN>DPs{EtwiHNy|Vot&z{1+}KB5NSU z%t1ZhTlixx{`i6ZSf^s{wpiUl3txhr1^CK~kZNVR(r#b;xa*;F(3_hu?gw;s%flADXri*FTLzjHN;Kjaq0COE)HfK`tx_|f1MuLz$J ze!opdC3Vl@M@5rPt~#YtW|PD+Xp+r84;(`L2$K^o`5|niNiB&)bZjWcXr2@wihIza zIPu60p@a?Q*bGYY505h`ZkAg@6j%2ui!kbe;zMzROv2`*weLQQFmdTgkrWr^aSMW! zrVnAGO^SOS{}&&QS%it@BB6vmY7$mXN&X>hltoxYQbHn*V~g}Q*BfP0+~SBHH=JWj z(#nqHWyRwT6idf=gkvw@|KdZ~aHQ0u7KHLRld$CpO4En15hh_P(vCaABJ369h!4d* zfRuW~giykUS%kexN&X@1VT&;Fcng6%&Lr$L_EDNP^3hFXMe z401qX4{(e|rugvskW!Bn5lYw)j%}eN|8UHrxOdVt9c&WzZj=Y%e|bpO#k7epG4o%E z8erlNv8v*0r1YPQ+R(h!XDHK@dAmfNYnItmXZZ?Tk-e3`%MB^zy(z-KF(> z2>;2Cx3otoaxL<3btAs0SiUaAztM)aFjs;6*-m=w8WjSgF)FIWEKSu)%=t2BvnlW6 zTL+^P3`dcf;y8RGe61=Vjz-^~!x1SC3f1%?AyyYBDy2q0tQfPaabH(s6zVyZdAlYu z)mZ1^Pl_uwa9uVzD!)wZ?TY8pp@w*clDB(YS0m}>-{?d8G&Odl&}eFNrW%IC95q%S zd~O_914mJruUIHZYT#HBlWOGqS$Wb;SXMQj=3f%!eWP|YKAZ8<64YZb@6A@G8u1{1 zQeLQ0UK!EVz`a^cjUHiLjgO$l6zQPdHSL5+q`^Lk2XAFWGr!ntst_(H2J-}*hut?mh%>MK+?O+N zpjt&3rw*~6IB`@059pB^x7(SH8m7Xe8powr`M%oKcqZ4rac{$BXG4vDG4CCLOf_)x zqI3(sJ;jYI|13?7I}^GZebUtU5^AW;c3X{|81klHGS}4jOp$Z?#+wtb#3O^G#+?aS zK+I2k-sqzWNHrRTSoxQ=s}adnjW#Vd-VQZRXI^X=+0WDQbBebQ)OZJH3Zcf{G&SzF zbT#@W^uF;m)KFWrwi+K{r1YsljlGJTqsF)!Z(l0ZxZA3(M&E?Qq#A`7DPPyF1};2v z8!1zti*|$>XE1NSaHbl4gZ!I9QjIUt)adWh)fiytY8)XoQliba8Xse%^bIN^_PkO4 zMO0#r8jnpYmw@XnkXVAu*{&QJj?@sa=g{bL|`3jrmVNjS}V^5Y14dd@VR` z4X9c4W>cRx1{%5=_qlX6eu5e^lcLSG8lPZzueFKTYItupB{@fpk{jC$6>1Dr1vEA8 zqj-LrF0t@$kq>?2r~gNdT>Hiw_4c-b8vkbA`w|&ycn3!4n__CDd>7T#7!=Ue2thYz z7X1xs%!-RP+iHACtFd#9h#x9JMziL-wa;_s~`ejQ-K#en*cZe%fjloI!?FXgC zuW4#L6xP+i2DH;RD)LAT*$r$p>ZO=>FoYMK-02&?MkVH`vAFPid}Eo;DG!BJrlSU3 z3F{+ecZ%VNgk@cePR+G%)H%FiD(Y#$ybl|hYCM#pU%OCh98FVWSX5VIcvx4XF4WjY z&C^$3$6^+JC?!ByC0~mkjY`Z>BVKP1zLQF746`#GHHL>}0ogb9_*q5W+SQnnYv1@H z@!%Aw(UN&b1Txha4p!3=vgs8pO^rtqx*8*qXU`iI$B`N#(Pq1EG{n3yoHsh{stwgj za*i4+zG?EUP~(w=%5>BisR~Fn_J$aaNO4*F#+M=FT%!_*=8S}KljB)EH&yYJ^?78mAfj8@6blwla64Z;bR)qtnzVKNOXiqsF5%-g!!>G0IYzjv8Tt zv~$Y7IIB3#AS|mIlXF$$({aB~Mm=XSZ#bNxMnwVm&j_o&acr6zV_do#V=P^b5~#5~ zNbS?q@W8@?r~tK*QgN)p95tGDE-x2qjG=g9uAO1WSQ3+cV?Rbpi9uLaHD=_h#w>69 z=TXnu%sV!kp@w%%h<>$3sbR$RGwgUnS7U-pSED7Vk)ZZzY7}D@6&tc?eWSvNi$Lv% zk*vlypDNTCZ>UVCZ%iOa>l+6kb4!D;tZGcpb>3*U>y={Ea}M)PNMx!pK7w^aK&f#? zni>-Wx*AV_zcX+6k=h{#g*|Vah>ahEQW-Ko-#Y#uJ9bWZ(D# zBgN0LtZK~2RSoKig1hv`ACqDN|QtQb1SZd{QGS+H9+FG7d3O zF?ZG*6)hCzjFeSlt~o=f@sufQ(MQUpfW)L4U#3{a`37NG)tH{^NZE7B?K4nMDf2$< z%2ea2B!5CdG~L@jq>q%zVO@=9qPiMwpvHS{(Pmo>EE&B|B?YL>8>m)djv5!OKTuDo zF*&RuoYwr%7SwYt^G1veH7d?QZ+O-oDXr7`#`YE-mVn4`vxd3C-KYCId21+l{ z6$(&SS@iqGt5ji zru%7sQ>k%Tni?}LU5!}@U5!pb{T2Bfv3HqJW2Qwc)6cN8 z5)zXm1=k1_oq~jARRh)Jw!bm^j}axP=X~a!9nMr^7FbOUDK)N4Q)7-xS7VN)tI>tj z2#Yq`BL&-+-dViS>F1Oy<04Qy!@d?g_XMHF9Lmd3V~!;;sm4%@lrFWaF*{c^*1t8E z`o;y!J2#rC#+(rCZ%Q@1qruU+gD~IF)mY%y)#y%Yq(qx-HL!i@ofA?-?5j3ZD=}x@ zc*4IwCe)a3s7z-TUEo)hh>$PfVTPyS`u^A z7_jP{GNDFgSYsxcBH5hlYv0&d_Cp`ka|!b<3uLOXG^(vdD|)1<@j^mV!}}s4oq1z4)L3naHrr~@ zT6AetfO_BPAp^B@O7AtU?Lv(g60(4{-gq%8F{#FVSc{IXU5)vU8nxe}e|E>(XP`z~ z=6%V`RO3ZI|J5$htt)Pa8qcKEUFo>R)e!g2y~`6&1HFjP@)hHt#_Wh_v#rKg7%4CM z6%o-l{x%q@m6+2vd?Q-EBh-kiOnHw!FT`*xSwO0BN{Hczgk|j;b8{Ujtyg~dF6z0I zd0!4^shz7C;pEDs7$^$k+vE=yvL8ohS? zG*YOslJd0m2C4CiTVhg;CRp-6QM(!ooW4=}J^Ii^UmXWEF2hlxnQE*=|Nk(e=8X}i z-Zxeox*BU-x*C&74NJ7y?i=6unRjJW5pnv)2vcH?8Xq;?fS-n>bINK%Wr}%&)W9@{ z4^72lym#ecO=s)1*=wRz)pQ&(esKv!cH)R-F;ZMM}o9B1COmH_pUGR~BkqsFw0 zZaE;-c-_u))L0*o1*96-g{qiUyBc$IRby_|-?SFJf_dL?WvcNySnagbNO>YnjYL>i zV*~P>S#%!C%?pb*+iD!aNO_$%+F5VVyzzu7$vJ8?n{a%6p@w*F3brpB95U5!m~U5$lM11B|nv}@S! zK_rn9px!sIpUnfcGwf$WM_n(}cr&UpoxZUtE-|S_3-pbJwX5-buJgu$p%Ryjv8-s=FTj7R)|$p)~?3FT-EsTwHec(MtkPnVrHuGHu!(+S8B{kQ{x>=S7U2J zS7RB}h#G>2t;P>2=6&0gSt*fydYLxj! zn{74lSd@2bP!Vy?DOfe*lcq-FBfDk^HMUb8&vew-;g*X>W zqfjGhs7yzV_X(l`QjMRX#;X5Eja>W2&5=HXp~ltB`+g!*jbwzsl|ZUdnWn~v0bPxq zL0ye^E&8=v(PmqX(=cx&BZ`QlMx`k+XQTv2)%{hd@nJw^I%@0;N=&Np3r5Pj7GYUe z=GYj>ZMSE5(=X{7wj=Z6T$*to_Cv6mYtI|Y($x6a)YbSTpsSH2HBzF@wi>6SZ+yrb zO}08}EHg!*HgA}pdW(e`AKRIZ8lMDY0jb8XepZpR2+OKQG}n>xMa5Wp3ho-_{nVAI z#>eRK^W16{U7n`KXJK89UFb#5Iprg$@u^Ae)6TFZDdzo{cj$CAmdij*jej*=aD!0e zv#_W|UvKQPJD6CR{}y5uA6XQaRgH>V`^J#LN2jBnYngYqk*UTmgTHG-j+9ktYJ48m z)z}l))!0R9NaA+iI5Wh&y9{b{x*DrYi8&*s$=vSpe#+-jmFe`2J#mT2zVSQeja?RD zS=A`dwQscEICnMbxsG}F1~S#y6X0(bk!rjf(pTpD61o~zR99mk)c7nw?bG^3D~yyq z64Xb^yCD&%^^JG^{|<}3u`i)A9W|_|#H1R3Vx;V|2+OKQMXqX`ckR9HP){f3-EU^9 zVfp#{RHPcoG&K%bx*A`kbTz&tHKc=f-#9zYyp~@PapsL=bu~KwI8Qz=dVsS;XVO;Y zU!+teVx%0!Ncob-WmTg**OAh{Re#i!cRlld8O~JWi!gtKj8x;JG&K&obTtlwzcX)q zjg%S`wi>1A8()MK5l4-Ws;e=qU1xb$`XI&A(9+a6Xh}@=jlVEbzUEj~H7axM8@C=Q zqIsh;^L`c0RO2A{mqpbqx+_hMuMJ%dY+h(;93eF#qRqA%=cSnUpkgir=4;Vi3UlU- zsov$I#7Ozt5Vh!PeB+mxRO9ayt2km2mR*fp`^K<>FJ_>g8<_W-M5Y>FC-|>J$iA^J zO^w3=U5)PyU5%fh#%^k!K5t;j=>0k&Kz-iWS6z))hx{P>#^Hc0p!JRK3{?pqDfHX= z6+c;oWmRKQu4-)Q+_*F92{P|@R;C)?C;7Xiq#A#uv{|&`PrNDui*3=$ilcE|jlUxF z&KS{VyKi9o())cj0rIuk+7_4EXlQRlpMKdKkB)Wd4D!C z)u;l;=Pad0VL(^Iqt6?aMJ`>9B8-&vvdwni!1krL$|hpZqLqaKNzPHDe}mibHWKuW zN{^v39W}5WgAZm_Id6=Ov&tfiu&in<&b4pk&uZNk_1wg~zXmeZ_&vhkmnKF^Wm9P5 z^o>)4dfzbox*Dgs>77Z`K5e~$?Mv_P5drFbqp4EJQDf}67kw$zI5j8>IP*rO;a8Q2 zzA-MvDo=A0mQ{_Vx%Q0(qdqtt^>k(4Kg>)uXf~Lu&MB2Gz}QivrCV2{WlC40Rg&Hr zCE9HF4QyX}ogwe^jTVZWqsGUR>xt(#DqC`vX=m8VmZ@|#Ciq!pt7NTeEY4Mpwsksx z2sOGf?_c3eHU0ssd0{nDE=W_OLtIzm>WHpJ#}K_UD?<%zUwZ%HjiyfSsBwW`l5^DP zo}B)Z=o=m4D$^M$S4Si!N6OHER>T28+*VX76p?8LfHrssz+n1I)eFbg->V2bkP-2c6+onz5Ce*myuQHv!VcL}lHJ-#sF;f(mRgGo2s&R7b z58p#Qx1gz3rW*DA{7sKijR9$D+?%Gxz%(@mLX8cw&9)lnq?oV1BBza%0YOFB-WR=M z ziRc^s(Km+0YgOY#M~!=G{pR>Dhgvs;8a&HfepHWXw zG)w({oz2w;2HQk4;p_B-?(2-G&UI#(zbA~h(&oCy&wM`K%rvgG}zLO)FeYgo2Y_k;CC8qA{(tz&kGK0V44K32R;>$d~CcK$xzRsH8R6J={iHjIs zLg%_PATi0cAkHe68H8o$nrk0Uh3-BN_1w;UP0dWMMv%VQqqwe2$$Y1&AAYm@ z@V~%ddqQztAJKh%Bc%J9fGT_CG-Qw01L(v5;>}F+b<@NPTM4e~Bg7$nyuJ~VnB-a? zeK^4d%gXhIT)B>I_Y9`KygQihbae){xt@`tZ{;Yi@1(6jwz_q$TM@Z8ELv%E{Q`aX zjFfD;GY|J{KfI;j`i@^^I=*goOH6WYfIhsHSCW@4o&OKlTz%c& zVDSmy+K2hhjAn9e8R75jBujA4*^|`!@ZPxY>pn#8GX*W1>p_gymXT^)&wFvT?8AGK zD%0_GZ(L&1*W)o>_wh=y`nn=lt}6@Lp8>9SF<+}tCfBn~x-YDJ{VI*?A>x`;>!z=X zt8BT=6*qc)XPb(S?dv&3Jmpsr2DSkg|CaeDV?hid3GOObYh&|*h($Z&ab!y>$@N+K+V@)_1OD@ zt2d=G9j-oAKyobv{}baBmzC=)x%#^K@6)EBo_m<@!gwavi=+JQyOQf^hR(GaJa@P@ zv*>-aqUE-)zhk^!92KC(^`fKKTp_rgW~fYuYcqnVBS@~EI9t@rA}lM{Ik|FO-gNpE zsHZ>kwFzf(Z5!h67M5IFCUmZ?po7EptT4T8mp+=WxP9tt8xo+#b>qMx;>p=XEfXr! z;o2%HG0C+UefX>}VOhDZ$+Zs;4qkW?>KVX%mj*MrULN3YPL^EHPvd$)8rKVntE6T7 zdK7*5@&GlHmPYn?jn2QRr||XsgvxZdUJ#X-B_1ZM9*QIgo1g>8MMJsJz|4uPqdrN>C z*XRF!bD!XPt*J5{uGa-5Cb^!NVv9N%gk|NrI@dmYRl9+IqMrMh@2W&5*Q+tR?iSt8 z#TIpq=)QKtSay8v9;CNiQ;Qs5>9(cs>bL+ku89#9tp!)H<4PUe;o2=E3rMbwF!$x;))$TZ7ne% zjq3p7>dxSbts>v`+>*4pY0d=?j1gS>`;`#FSK>NA)}nS*uSo$*QCxOkbLBep+?{l- z9%8=E{!FexjKa@@itB?(o$HXe?(0JldKYO1S8Nsef`$OKKD>70zq<&o4<=Qn!*xhp zVxkYzYe*M8#B0vVb#<+^)-`e+*0QE6O96IV$~%}vGF zD)QZ!QgrNd&fEsOHw&(h*1&aC2G`5r_2}BUzLu-6D?7Gb08H0k3R*T-Y!&&sC8}{f$C&n@;5sp+G96!^2ue))+7^BINk3s(eSIxg zU){f5ycqR7$b8+SnOtvyTYI94>y$LEQ`5NOjEOhzidNcOu~p=|B_cqr4>wcx#G(yxn1WRKW6Lm;5vl)ZVhE}z0IUuB*k@}TlaNdO80es67M!N zGq_@_$ak9rHLl-vx^a`>I?t_yaD1JYl9=@MV)WtpNy4)Fx-Qo~eBs;|-a zCfD9@Yj0R_tqkj27eNQ-oU=GU@1GT|w0&)WKHS?co9?U;fBUW8d4g+YSYtvE|SePrE}d7(YbC+fNPjqq^%{e zRph&aFlxHP_4!%nA1Ap=b<|pd&N&;<8lCF}A+~5^g0QSyU(eOotNd+upq_`(EGv_1 zAN0(9rsDc;Qs=rYu5-oCYH7KfTBLEs<-D&?Qh*xQiplHbwfehursM0jxGW%jJsD087fEsbIBjnFBnYl*ziH8@etO@QXrj z8x^3&^}xyz4+&pC4yjDRmG&h*2}(?I?HgyPov^H26S?-`z2Q-Kcq?x>^Ysg7a_t|Y zT_nZTit4`Z59?eHnDnMG(Mp>uwu*fHZ94Y(wR@W>;y&FXD=JE;K1^Kqhb1Pt_DQit z2Ta1Ua-Ev1uj}p^e;euwh4mkF9DV5aIG>VCb{0?XN!I%C_C2$xpHkB z{^DfRGZM{8WpaJMqFp4#^&fq_E_UhTbunhp(zxudwyz$H*9Rh;`zXsOM4U8=T1GIwVfJNRsQ~25zknFK&?1`tago zli*4X(&u4p75VI?ymQX!5o|nwb487!gf?DLuf!zRZgGa%3CqfLNv>S$eembksAm-O zJrv30`f!+bkrdY=eJ!!L*wndt19-QgAzEqs>O~)ZI4nS|58p7f^D%;Jk)7%IT5QS! zlIu-=w%8jWEGyTSa^-r_s;Yd{Gn)B^nVDQi1ZfvZac!E?eLWRU+UK0bMx5S1D_UuD z#a5ATL{NYl*ZO_0StGbMO{q+W>#0eJNv>VstHEo|%5`O~TyO4vxG}hfneP#QCf7#| z+C@@ao2PL-GmUEt;u;XGw7Fud$oHrro9^`CO|8!VL~w0h1J^S%xCTRPaf{lyt}}C7 z`w#fE@jc-B81s#CWpW*zqFp4#^*lrOmF|ByzP7gLU4R)}8)LkVw&~dC*DcW!u@}Dh zJX;9I*Va@CO=i;98_zD*9{nD?vUYg)s z#jk-ZzAUP9y&PkCilk-xdNTU(m;^O5Z65w{Vec)%*GpBV^9v)WR~8UlJ^z?&@#SH{ zvT}VR*FJptYlj{{J!6?~Y&4VW_z1X071yf;SFz`}xFc~@duxlY3FE0Zw`ir!^%V5s z@eu*?NeO4+b+ zTl#Q2<{JKC0vbAm9%&oQKLj#FdjKJhEyC6jPlgQ22!$jspis;9iYhp{6T8bXpWs{D2z9~ z{hT;8Utyepz+8oK8XP-6sW484V;9&8c&c)IOheTpZ0d{h9#( z%1deb=%8-;1*SC5Lfco3b3{s*eqoA#Ib;iA`ZY08PMAJ9t(!hI!}MESZnHG~_9!d) z65UjoJ})VMmdK^!p@WvZVUh+c;F;b8!dydGmg%E|3iD0BKo*w0mYX!rQE|fbd>C?J zN@2ou>R8vr6y}>gIjyjzE{@OZn`$Xcm`(=Yid@k?VR~m^w?_%{Os5}BS~V}JFm8JL zchf{#U@#rc|2rdn{O)E|IN}1<@ji9FRw}N#A12&~^|cu34?y+=rV*~(st0Y|^d)iK z^raU6)<*TsE_mqk_z)pf6!K#Khl@P6(&qS7=}=;>_je^Nv1E0D9ktgAwywHU5caGWH~{+ z0}9j0;N{2_m@xgQ7+dvlk}%)&6yhH7Fk$-ph+82sn112kGkyBbYpQX?g{{&kMh^s1O{dUaGc-7$63R|mPx()1dnzKST* z*F@wG3Axa0)w41BAstAio8B@FLmUC>rkBY;*Y`En7>=nhVLBPSI;b#VdKZVSs^OS#`Zi!|A{0lMFnzm8qyFO=PCP}w~ES3COejr0vQr;_P+u#W#sWt;wQ2)#5V^;@+wrJMetqnrLwLN|R^ zjDG>6G<|neH+_$(o4z-wo4z;AZI-5goMI*W3}w2D)E10;Vfv>5`so|eKr_9g$yWW_ z6P2Hn_;kE8B?5KRKa_>_bNWXK6(>v&!;oDuh54rMjw;MIeUGWIrLHo4Z%|>vbTW8v zT4BQUW6uxzFfyI7<;LGSr@uJz)i7$hlXYC>WShRx6n2So z`VScQ{`8)X=%)XOk>^kE`(X*C#7N)eiWFC9)lN&6bJ6%RT>Dd`IH#9kC05F8c}_3O zH(+`~nqJl{!AibXvt3z>2vRZ9Kr@{|n2n|Y^^yLAr7-`To{lKYAL&0D3KOQ&d3irU zIEW;}r|n&?!hF+rS_)f=Tt2;noWg|ZS2+w66(&qS7FfPPm}h#2u4x9k3gf1CINoF+ zEijn=_TMvoezSIEIO1KbV|60S^s){R`XRNDE5rVnZ+cnBs5H+a^FpRbaka|ALH^pf zFue=|hL__Cl@+9P(+eHl^r8f}S&a0u!;$*hRi<}J$}cQ+>3Bz^=?gna1I_fJ7(>-bzO%k)*>yZkM8aZWEg zA*!3+-PBF*5!6lZ0ZXvHO_pJuudV`#Dfb<EGZOCwZ7K{acjnWm8!`y}$kUOdlFAXo;Hc zW*uLMW|>~r-{h~aOVbAgb<+o=b<+o?bkhep{6%kR`rw3a`jD7z`p~Fu`Y@B*EKMIC zL@KFFAA!{Nm@@q=Oz+!W(m*r)Xb9Nf6rgVUfS|&B(+8v#=9@k+r7&Uou@HZdqcDG@ z4^Ak|H+@JE9u4gog>!zen6z5fMit{qIfh zmoGoGGmdx<>xeUW=IXs{NPxeWE=?a3(@h^6)lDB~>ZV@|gH}e=NWVC(n|?`3H~msa zH{D8bo2BWOA@!}POdp?=-yP~g(=y!Q#dl|t2Ab)|L98K!0n|+&6H}OP`q-$#eACC7 z3KOQE5MyN*bMZ4r`o(D#=bL^>N?}V~W%{L#!i4E$u$54lFx|v4F5{SQ`VYXyCn?UK z-qQ||78p!_=kJ*wIlIZFsQn+TBQBq^Oz#FuY(wf-c3o6A{d!Y3eOgdAeOj8onk`5A z4JqC98y(&B=?UHRn_}E%Y5F1yDO;I-2gdfl&;`Wwey2fSib)!1ruRs*vTmNx-s&9< z7lGR9z3h5ZVZQ0pf(jF+mqO@iX@&VC{f3mneA91q6t>h=rcX~OOqfmv-xO1rFdb*R zvPBkQzUe=L#~l%ciIM)3$;$3D1QuZV>;9hUd4bX&al{1c_;xzm^ko5I7uTVchf%CpoO_F^R$S9rc+0Io)2l-DNHK zhX!xBj4wXpB^>cy)^S@Z+w`iazIv}Val6ox!==m#>ZUts-SpKdef3`B;PK};YavWu zlh93nHl~~YT$I}^NBUZmmHfw2rmv$^N}0aiVkO^4NEgj?TD@0A1*oR?vmk12JgpCQPT*`#Oy5cnAJxKiGI%R;1tv`IgZ916G2islOjbs>IYmbhruW5h-wO&1roZ|3M*745 z{qhIYen0EDH<4}nE{v{6V6&LscSGp1q%wVXS~q=9N;iG4qp#jSPM};=neN7P(?5yo zrhjU3o2BWW1zAZtpiKWff>cbI{sn4Db6qskY4yH~j}U($HwXgm=3)`%o4z|u0utt% zz9*$HvVpay)%#vYVZ!tQIL5~bh54qtF@-JVWoe{;5>=QmoecieRG2WmAF$7Yg!!hQ zo@QmAM-(PZKf`2YU&I6k)7RQ{uhahzBYkJMC*&tzj)BD6&+5VKmeA9n&6y}?LAfYf}I<4M+jwwu--XBQaXx(|-*rOqfmv|C&~qF#Swmzj4ery?>g4F2xZhOdn_hlW{QpwZAvg`;Y7M z4QhXob^IopWqNrisjc42!#2!|Nz=;<;+pB@g_dS|c~JyEVuV4&bt*sHKnmr!Lgk$T zn(5`8T+Q_IBa+-^VS2e?!&qCHek4*q1(oTYQ%J>yexB)Ay`#wjROj?FAy(K{m}feg zuQ1PakWiQ~{puJ46@>}YuW=X%Dam@s{)$;vyYL|lM1`>`I={|`^joYU<2lW@c(tYg~DGQDiSsjc42&6u`&FE5Ge zrk5fTd+6fUYI)C~Ea!q(dC#;+3DZwZ>84{*>hHam_eyY^rRgUl^;24zehN~bo67Xw z=pF|w(mC9 zNshvV>11%Pgu;aB!+@R4G2e9TO_!hIVZ!v`zzp3H%^HCtE@K`4NN1Zq+|VAEDz`AY)?zes<;pL!b<@Ykb<;1mw8y2& zuZZ9+lZcw$Cm6cv69c;G6J2hz9O+jgRck2IuL>fSP^MoUVI{wi1o}wFO}g^oh5*$_ zzY?NaNrm~QUuG-JH+_6uVPd4`L;TAvg^7_q0oWB0h54pWFch}bRi;lQh_5e%>16Ok z^civ8^qH1!`Yc#-KhEM}q~C0?k~L{%`s{#i`fOJ>{gx!RS(-ivsb6Bs z^tqIBmFe*`EBQ4_8fepdbBC4pNC{AxJ|5Ujw!(bVXT%len?BQ0m@xfdh(9Z$Fk$*- z5dUUFVZQ0J3E~F(rq6a2CQK)TZ%Halm_7>ao5L~R^b2s@xgI7=AC2S2(^QtG_x!GZ z&-A0NXuBUZEoUKUmbndEes^4ZT&jGQ1M}jZ=@@x*7U!Ck#}VnD)2)d1xK#P0F_a4` z(^tYgUd~11%O5j!(;v6F&C>KIaD-oz%Je63gx|b#`qL=)n@t*MrniKscgF>&Ot&E5 zEJtCQ=|P40rpLXq!t^!}+KQ++VfrNw10jX^rmsvYY^jSz(dr%K6edh3gCDmQCQQE& z*b}@hzUddGS^1N3it|VMSd*1M&FkZ)ANTjB_h@|EGSvPs3$;pQoBk|JSOUBF>9PDd z$X=aLrqj=t_@=Lm=%%kXw8y2&Hw0Kojjc@I;OeG7pVUo%!R9tg(_f6UlHY^M^p_|V zS0nvp2dT8s&pW3d3SpkL1*l9P6=P_)!hF-oF6uGbb$a=_h{A;F?HyLW-cXn@{bJO& zfgoPiH+_Svu%-AUOn*M9Fkw0w{DQ48Vfr{=FUAS;O}{wJ%3ty@G14zJS^3M3h{H(l z@%Kz0Tf7{7C+`s!Y8T5k{icBSxK#Pu7y#!K8 zWqK;6oBn=OH+`GQZI-5gfYcwBGJQLxQp)rl7AyI0gf!4bdPfLz6JgvC-c#F;1NL@M zVZP~a%O0bf{!U883Dc*>SoynLXnx)Al9|^!L`cQ?rl(>GTgu~Tq`x0km@u6T-exLH zm~P=1A8^b!{W8RD_b_4lCL_|>Ymg853Bd@o_Kj9YFfcU;b^w$pI~&+ z15#YS@=qbO_qbH~XA#}>&kf!5F9Nchiw2f|;ffSjsQk;MZu(cYZu-7Bw^^G0wFP4x zW%@S>{_2TX*OY&YTK+Uh1I=_=se5nPibnI*`=^!&l>L=Yy`M!C=1=dR8wwMqQ+;0$ zBs!6ce|ddh;FG|7)4xnAY^h6eWcpXO!i4E$@V>ahgy~lR``RMRH@zs$%D+h{Oqf2w zVIVCqnBLtAG-<+Gtb;l4n8qD!}*P@~O4ofEA15*y`?Va@xx zXj!NWy-^ZpE$-y0qwyYEiNo^Fv?%Ww19|B{?Ied%$6BnkiN%_A=8;`(*8cG%Yu3~X zuqLe8ew#IGV{J03j%K0bTm+_A-XN6~s4aFb{k+Ry7V4H}rA;HOS=jYT9cumX>CJ;! zsCyDwIP^eOiskilSHF1I$1G$fSZTh&nuYvQZLRSq-m#U1O3|qN1WI{Xd41jOr#yKd z3*kmpX|n*1VGZs1nybcPYlz*(=Zu2Lq`ms=d@H!}tQeIZGrtS$(tl7ds z0|UrPqlI3Dd8b*s%pW$h(4Z76J=kK+3j9)sx|e-_Y6lh?0$vBFShG%Esb+^+?OUF^ zjfIAR*C7$s>~KG;gSB?dW*ln-cpc&(%dfD5yT=LL%R*;IS!qjyH7oQ>wX@E7VD;B5 z6g7~QV9kpBQtjQBJGY0tBf+ax0Hyq_cJ7X25C4{hMuAtW7)tpSwzuXkAJ&3}&Ihkn zE@O8Ysz~wCkxefAh0D_8<~Xu+l2>w)!HQ{v*<1I4hnQBV|Mb%- zOmM|koQ1k_EH5CZ$Kvrg_R*3#o=3;L*i=liEe65CGcd!m!52790zZH6;=km9N&B}3 z0(pAIQp!V+MyxrYbQWL30mHC{Dk~Ej2UWti!Cuv4U?Sz5i*?V{{rNmzz{;9pj^eA3s z)kAUQxK=w+{Bah#*_0GR=rFfow5BE)PrgH7C6t%@|etx z@iUrWQqdx)Gid>qO(WC>jmdE?3(buQP-9ZG?^Dd}um^R>Olbv9j1?_7^_)y_ViZj1 z#Mls%i(YK;2ADj-LUFi|$>dgQts_0D2qttUZNW0%5baX^lupZ`TkCpqN56ugU=mDZ zGQr8ZqHT<@+)Vh($Fyd^$+{sXEoyGP8udKMLbuiNWFEB^SDL(cRfID<34>)bYJ%{O%;d#Ct4SdV&Q+g?KDFClf3nJWs5Kn2a7`pf!0g0sSVmV!ICO;M_o@&{cGnM!K6=Alu#oc z3$2P%d4Zfv`upRgZ-bt!o%QLjVDbzL-C4(zyWj~{ZIVgcu*dv4|!xN%}@&pUgiV+Qaf(5D9yBhRl`*%&~fxj{q z`bQm467U48TghZp#)uz0A1KgUnB=vD|Aho=O&4Qpb~J&>hz^lF5{m z&Sa`X=Ni#2Z^YvQD71`AoN+!G`270bg2|MWD51s)PCyk?od%hN{od8qZK!ws_xG;X zf=Lw%Jyge&3+OmMvxTAr4T^?TRSAy;1_m`smmGQkO`;wG~} zCb)i9p0sI@Nw4)E3;~mB7J9gjCoA9yt`;SeIT@bJg(uBryF5>Dc^O&}tHY#!@INOC zCUa7mOmG6KnCmpi1lRP6Nw7gCYa{cAf(bhKqjfx42~TiwE14|J@MIA@X<>?Xc}#FM z99o&K!(>@#aTCF0VKkEoPCyllcr7`{3HBL0CJm005tm%I986ZTkX^@<$KeUC#U+zO z#+mV6oEZ-aW--CVd+7049VX9qJ`xxGv=&Z8GMSu#adNLgSZ*eM?`qnhCpRws^H9`N z!$SY8v-}swlf~~X5q(zI+Mr1^59e!6Ksuyp5_h9n7iU# z-oHyQc`TU81Sg=1$I=Zl!S<12a#(}CYfJp?OTpw>7J8nGulc4kcM&Zc|RDiC(?JBs+BN9O*{7Yi3H7XFq3SxGtcEAprISovjp|HZGwEDIZP3=j*wzcJjtP(# zLz{8UxU075Y{BH!sLYg1a004$%_J-*6Ks7dChZ&a)=E%gGU(Z{@*KZCn#lwwpo$%4 zgG{ioteCWKuy>vD?5+u5@;nQztK-Rfc!Dik$z*qiCws^fH;c&?IG?Of%f?bM(Ysc4 zf5H}?>`uu{=?P9i6?+`Qa(EJ`y~?3mL3HD%`3dC7xh^}XiREoczJ5v9Q7HWa3vEzN zU{CRF3%$N#UyydPSPL47tm4ZQ?FQkd5~V`xBwlD0Af z_~RRtyfV7eg9-&GtEBrls8(U3Vr;UYa)pVFL+p0r5E2syp$$(Qh%oF+@@?^Knl1kH zX-+>b@i8J_WT6)!CEo&5G%K%x6|G?tr&(E&=67xc&B_wcY+);!Uq|WkSkZhQg0zl` zR;kKpD;^aJP|?I51*%n;poyz}RIV^VldhY;mKDl_gh0LW`4q+R?boZ!I&QZ3*{At) z%_|2X@+B5}CF$?-5K_S&dt`6Nbsw}k> zMpX1abXUIBn}tcojxiVxM0wn?>tKikFWeMiomEXuDlC-B+EO)Qg@*8 z&T$7?`PeUbJIPAhn2ddFs4TX}E=XT+C=0!ZlkZQsnRuvQs-=5i@>ShfC}pCQops-8 z)%MhQ7TOlzC-A%$uBtGvl{@8`+guj<0HuOKb^CXRIJalsj~WpB>sS`r;qu8X?_B@L z=UC4SISx0t{vAXeamFV2?LF5zbIbRCvCvMJby|b=2K^(qap#YiH-G1tE#*U{0c`}qf;w~vC!T$D{X7BytaN;E9*%6 zta&WtLeaJ<*5Xks0G~fiur?<+SvTY^8M)_27WypCPeys?`E?AlzDtzXve4(K<4_#A zz2%A6#=7PE5|sKffh<(`xvjF;$M$M_*oLJ-hyS zIQs+iZI78U=|8+I)-5-E# zwK!HgS7qe|t&_SOh7ML6L@77xChW3JmkeZ~UmSjEk~hjfR@8mEOZov8`V}lYL|KbR zIF;WW*2aV!hx*mGcK^KR&DU7y4+>0X-FNL58jGFPKVjG%$pHRXplz;Op--(nZk4zd zx&w!zVVmn#X!D(2o)EV}KZ|>jc73-($1UG5OWX?mF{&bOt1q(YOSgUgsJIpSr&s4f zqnN>k--7UEB)&+V$$J@92TV z&J{(B-wOT3QIVhcb$(&1Tgy$3?SA9?toUklviB&Erd9TdU#B0Lch;sGdLR-r`tG=j z{ItGE=7w(D$BM6t(~wb-Tk1P{;LgO1-EcEaJyJztRtm7j2#zjHn` z`SVdzJQ;D{CsiDu6pAN<&8Mn9@iYv--MfRrzz{D+d}63YV$+M|wBF(>D^T~o?HnMPA9BGS-3e>H{%HuJ9F}aIHV&w@@KA(%_U1j$eP2q^f@x0|O&ITwXKyA5u zRctR-H#i@l4w)$zi8v9UCc<(o5?Rx6w#Vclx1nvu-)B9&2=#1Y;danFgGsmpMkP)- za=H5p=IozLc|lk4t4(Jd(Jqe(8iqmw)R^>n^f8k&srV%>GbNL4Scd*;6PA<7Uf+`? zRzpm-nP<*GJ+HFxVcDL9LzXxRVg(L8qiOA8s`A_vo%g5>nkOHCNyrkQ#$@yM?ptxD z=W%Oq5uP zc6pxsJIKNXt^hSA?Iw+#C74{qdlJTuWCH4_i3;Ro;`&S;X|Q*l`FU4brEg~8!aAND zZt<0aWO5li@p@O~_!NyH(P)nemKtGf+~AJ}x_2>E61)CrF-|T^%S_3H2G;l#VL6## zs#2b;XwZ|NTW%VPdR|8p>UeU5SOZBWIF{x~9`{SMD}%`qt^hSAZ6b&F6`o+(i9g>H zm{^(T5|)$6_r50&H^}6af{UA?o;O(7sN+dz8YgMhyAC$^Dov*oDVbnR zTv=ZQo}Mv z{MX}dI7Kiy%9fdu38+_gi4&I7lOKIg${J)+^j&oc>e6W^1H2APyDSUUyvyp1N*@uYjk z+%+4k72lIvO!AA`kj13CD?p9O4P$P+MtCwiDl?@gFtPF$ldxP&@>{yzEc~X?&^g{6 z@#I$2^9~F5sN+cq#>t_M>Rt0v{IX1rllizt5w~eHCb*~zmsql~{`usq#11^2iOagm zc`2DGnc#Y^a=t@YP9|-9Cd=K1m`rM4yAAccizd|Zq$kEnJ3}$K8=l|-Q!=@SJmGE7 znBZzM+|!kf^_lEnVw-}=-BFn-nSgrbJtko}nFKA*lPwK;a^An@H9WhIj(4qd*Ac6qZfE`GzkECFi0YyJ41oA|YG<%21iDVg9RxN-^CBPWwK zK9jfXhCHzYL#KgB3Qefv$tmyz7u#~~s&aKE)k(VA7VYwwpkd)tT-jLPlLH_92e-v= zRbN@9G9?pSvsYFpsX#6!O@B5#Pu^~jN&o#1K$E=pS-5u{PfpF4yVl`+;`grg0qS|w z2Ca9|+;yrYK+Thr+%Irbl*Y+ALuN`Q=#G`^3ChVN9}}cncfHeK@4B|j5&cllHZ-A* zCw(*Ku8l$6lZ|QWd7@pOC&Z+$D?p9On9{}VgeMz=GE*`^cdXo)CM=gH`5j%4$*u-H zd3Wlcy-?2wEZnb-ClQR3_A%AF-b(O&7}18xEiu}95$*DrU>7GGu>`0wd18M68(G-L zseDUvSLYLK;GiZdkdq14*2(r2=}K_;(+F5ZuNcCc{&I-U%K zCmo`S$w%-6n^%&_E_l)*Dca>R`4zoupd~imv(IEtgG@gDa_&Yj`8Nv>spHA8jJfOEjB)ZEjT5eB*4#DBs>5XWxVc}6 z-t}#kCm2|j-!<&XQGV~*V>fg@dF#aYPX?2nEIh1^CnGZEt^*mK9KhVwAu1Z}c|vp7 z2)7QCDa%_G3r`LNWu_b_=#G^K(uCz4Cu?l)#>Oren}0)HMB`;Iy0MYJLArzw6ZZXc zHmdoEh0ifq@j5h(wPpFITlhD8E;fSZMp@p8Jat}_l^$jWYL7Q5Z&U&)n>D`^^|J8! zDOTDs$npofYI`}qtM!wyqZJE}2LA-MhEL*w7oxv*j5GF#LB+;k9Cl2z{E<9wtj$_~ zlVZ*9vM6sHBC)r__S%%X#6T()s2$-@>Qa;oM*_72c~dMzhMhodl;@2{WPuT=9nSME zM`S@FPiS%GfhJHOEFOiE=!0F3NQ=8GD+iZbf7lo3TwibsHj& z4x$`S-Hynk}WX z_7u;%%Vwp=8aN(LEk?Ox6O28{Q}-aUYXEf`RPG;$>>3Nyj^nx{5Qz)Q+KYMWK7*AW z7Y)>o;R@c5a>peDwU_YJ1BgT?uDy~+EYta%9Ta~wa4<*V~8wG z!fBrRCn9^Af!aa5+!KiGX$NXA<9Scotn|bn@_6bglshpVsI_?HGl)DfjlRV5Rw42v zD8G$sR))xvp!`;zsxVk-FDSpAD_Dtgy`cODJg*9oCqsE`%R*fTktaj>4|r-dB2R(x zJ9uP`jZ_RNp0@_&PH|Bu&wCD$y`zl%i>KBivUid(o2S+xvX6;gz{_ngkg^$joaa4{ za;FB-lX>a|M4lRl?>zD)L}HD|p5S>eBl0v0N8ov{*hr<2$5Tm^>l*=Ep4x=Sz7Bd8 zPrZuBeg z2YBCPrDww06L{V>M4kz2yYjpb9Hd}vH=f##a{Vo&c;vqj**}G5^3=Z(IRM8yo=5IP z{K#ab13~>`Lp77R_GQMsU0E3G9on5`584#C2UQMCF!lgX?M0P?0?6Z) ze2gjw#TdJn=Y4`I2f2vkd7q-(;3#AF@f21brGt}<-OnSxK;#e{;Xa=F5|Kk}^O!GeDuM=4K+W>3x?=)kbTuCQTJJ&hF zYH=G2f0trypbNv)Dqd|4)ZT2~*JWBKlMUy7TzCWZMHeAxmSuc?`Vx4@lI0~J`hFY<9K;f9Sc#`<=al~$-=ehB}1_~ z?&4>4vPQfXFP5##Rs4=Z31 zWF;8;54lp%B*;q7g45rUD+NuXNI}GJcq%`I6rA42Bby`g>?mU%vq0@``||rLZ(#*3 zqO1*+WQJ-;p!V5V(P33Ztl(f=i~e8+YCkbNf#;fQ5>+R&ftQfZK zM^?}pK7Z!~YF)q7&Cc5O{U))3Ht_k|7_$6Qx0tK1KKuk$&=x*_jS9D?y$WZWy|=Av z%L>}T=Y6Qq8wY{f+0M?1_a4CtI>6_zP$6bN)jKAc^V*-*hZS@LuP;qx`Nx`JzBw}W z5i1CT*XL=*FdL{+>tnO8o;#Hl6oA)fP{Z>%P`f_;<+i)uX9Yz`*5*?ar7W-1v*{@aqepS3n^l%6|>6?6u#y*Sp9elym^ei?B4 zW>(Mzymq6)&VH%qVt@VKZX7Ep4zf18P@&gx0<~*nC7;$TW(CK%tj$MQwVhxE&>y;{ z;dzqfVGJO3yva(>F3Rl+E&R?nNGU7)zr;|^AdsD zQ9Q3VB1Z*qPUd-i9Hijr6+92;kJ3?Yp!RZ}*B6oJN0G-<{SbM65_vrGbVOcY;;he8 zXP8LYf!gsrbtcMTMVogbZ)bl*jt0NuIfsFW91VV@JP$Kv>4o4|!c&7Cq`i3&l`rwiyTDqJdEVhF$T*sd1?eA$0U&Ak!PE%bZh{}297HiO5UiNZFKk9wIMAANYvpjdED2Wihsk=bevoRtkAMH5!qZMUclMFGS>J=pg^* zsf!Rf-eBxQ9y!)TDuFzn8i#V1L;3Ms&x;XxIh40}>QY2r4&^W73R;M~0?Lo$Db!wi z1(YAlBgdm0ysI6{^R7VT1So$#PfbAN#2{95JaQr;C&uynfjn=LiBuZD8_H8xq1=_= z_aSff)rh3jDV5$ZJvVD)4)cr>;Zf)d58E z)b)tGI)*%6ZWL%Vv_KHpA;)uL9f;^tO z%|yzYxX)%{ljFXHw0O}h)kf|4RMw)INXcK z8`9usQ=RuC@R-oJr@Ozo(J&MSgQI`J(&$AIZGs*Hd^VDOA zoMp27=XvDg4pKJDf0d{HiE=jwS^g%TdJ>U0$62#9Pd$amo5Ak~o_ZRQvn}Xi6WdiL zQYn@%X1+3%yCuT%i(SeqN8~LIeBk9O5jn@e*FEyQDn!mnu>8IjMOHhkbZ!71@kj^d z=EhilA0AnQ$hj`d@6A(d5E+j`7n{mGi^zDA<@e%wYfV;qtI6_DvM6sI%H3*17aqAD zk+%g|zL?#fN91jBmM`X|7Z7<{n&o%lFpNF@6J;%q1^2$mVW|Iy@JSj5!UQG zUS|@K^T1E6IyNG5KJJY;E*WMsT{+t;j5NXk>P(_C7i|kPJ zKrcM@v@JzTOBH!oeMfKq;EW5dL?l*Z-=)0B`s!@=pI@io0n_(mw8&MF;ri-4^s5Ee zw`RpDmsZMNWPNqEEi0)05Rp+jt*gj_`XYm8?kk?hir-7p+CW8isPE`)dJO9N0wPUX zV5rEV`s!@`?5GbWv*LFxTBWGS!uslL)w62DbXNRMik3PmvZ%humZxtz4=TMAq4koA zEUfS7ha7z1ZHE?JD)R99>OA=0PaTABD0$nUm79pfI?=ADha5EQih~xh;;ji< z{;4|K)_3$4FU~#$kNRy5&>B+J`Dvt{I-7s>>>0na;w>>+h^jgdt*_2z^UiEKgcZN# z(rQ*kwsq^NGk?aX;g=8@r6sY7JhZ;Zremrm;<3CpleDfDk=Pz_>Z!BI!bi^Rg-DYY z=c>+7eRbyT{HA0bD}KYK6~2l*ygo*3f9t{z5E-P)1Qpq-zR19ZeU2Q>ieHb@wT6mx zZ4CV4*Mf8@OBf5V{QfRs8*I7?R~TP*7H^N!mZZW)^0*yQ79PvvFe`|?&tgns*#8u9 z0oHu9tG-HQ(EUMd49~-Tkk73^#&69Jyr*R%5Xjrl3cIFhI~9fT82dXGno?C9q}?gj zVzWqL{yGl#AGW%bcP#RbOCrVdx?(mv-efIq<0(YZ?iBu*S6MjWQiTGPRfe(QRaKl; z7_T^dzeSaMn1xEh*!-&MYATE$B)kM=kBbtPhmhtMSpR>n2R6;@i}0UV;Rz5vlWPgu z+%2fMmV!^WxZ>I~NPB3CYtJ<8p((B>A+Lm5p>tgd4kf&8@Kwkc#hlH2J<-1^})G43i91uv`rhYGxIES-R3KLvuY+mB= z;?;+#|I_v}RVWVDF>CPskq_6n}V>qZPU2Yc%9{O5WW(2v&TVj zrTKMsRPhqNl1{gn3KLv$bE9fbkTA}5TqC%CIDSxfg#XS8&rD}?#dU+m6;}$lSE9Hs zK(F<=E<~@T9w4|bviW@!G$V`ae1qENpL3oBuLT5g%;&nm^)L&0{9L*)sW8FyDVJ3( zvI!Gh8_|cC4;eWS;eW8gLBVXU_oW3pZbH@lDZ2NgxIWL(k@*T;f%_ewO)o14nu!wRpxq7PRXtm;wTUh-OS ztpxv-QN>I2;VP81O@#@r4$3|jB#d(%+lW5Aq4QUZ5dJ4C91+dt`V1JHf<_2mSAoGP zF~xONn%`rST+34Y9-HjLW$Vxvl}PRcTQe2eZi6 z=TNpRr7*#DEy|WVgmJEyG{V=DyWQ6c;eWBhb7I+CYtUwYZd#Mj=cZ?4!gJo3s^_A@ zbKZ=qwIa;7YqAeQdNsAFssgCEhll zEAe_cC<0Xt^Alr~oTG-^u3s2DRB# zefZ6U9HB0;dn+bJsPJ`5RP=Vib*o8te?`+gU&)6zc-wrg#No|^2vl5YY`zuqFpIcS z|KAc-nBa1?jM(dLsAitC<)Wakpsy)nT~aQ!%nl&j`p*Q7i5qG_J5G;i+a zZS%PjuRRG7sJIfZy)h57$XA-LK8`9(aK+;RRjx@G=Q_9%eRy)kfJ4Ex2`jubn9cPo zwAml8`-1x1^lO4Y&miaF-(o@);p^{FdM<&Qq4`SV^()>spDSVef+A3HrTO*Ogojzg zm2~+$s?H*>#f@8TbR1J`D(a8fLrYez8f z`fzm!47y@W@+MV>4Ww{jK3=N}0{l4`v6iSVaOpW1`qQ|Quh=W+pyHYU7K$iLaJ>io z#f~WP;?;*=LtFucXZK_Y_6Tbz~|Z-41BIf zC3UV{Y@O@TasHGKZ(2ql?o3VN?G@`L;@a6&n9ud7q=#9E=Ultk3KMB4)TwAchsZKW6ZeZYZJpl}8bu4`CZqajs%GVwd{?wB6)ifBMS`tmm z;M&a=pz^g0Tu+EAOmMx?X4P~vM`$8^#Y0imJt7JdT(=mk+B68`TraK1*Ke#$uAO&U z*n??u5G%YcmCf~Ju=BZ|0(L&v-eBi*?E`kFqkr>eRG%6E*CaI~s}G+X7og7d6iZ<~ z*WM8iLoN#w*FJ{A1lO$=!-43JxU%o;z&Y3!z5U(aFxo!EhJIT6qPkqeVDAWrm7EDsjQenVhXuVeYjR- zU8g==tFor44|s%C9CVucaJ|a9L46pcvTjnybPrJcfpHYo_->WzA9_W~i)L z>cfpHYqmmWE94gS;bxU}i~4Z0%9^V_%u!i$)rUDME3Q7=pt5dL$gLitKHRFZZdV`T zDr=rXf);Dujrz|p+&^7n;EM;AAZ87a7Wc~!%|nP8N-<%4;9qLF2w9UU=3&(HgNqN3 z;KPsf;RO{l!DY>H?}wea3~+xe&~ThU#_fw0Gw5b~lY?2|4QV+PdH-gCYtalVfPpa1 z*ylkc}3+stnR9{>@*rIyM#_NfDm1FP50`iag#zu=ge=n_L zn_R-)H+5_y$F^mZ-DFYR2aX>13Xj{KQD2f{|H>$v~8>*a&n=9&1q#G26Lf7Q{+0Qb{Zsyn*8D-z%WxvcQ`zFV}asu*?+IOuh-T3^wuLshrF?yzL zQ6}8@>lAwaS={KR04n*gOD)M%Z@EJkFaSj#ic!+2)mwR`y&Y9 ze>~2jxC2oMQQ77LUBYS&4Qp|&Mc6NC9h>43_FGcN;uc|lBy?;p$Nsc4Fqh)~7t^s@ zEMRz&TF2(Ngf$83*ex7u8r88m7RBYKbZjQanrD=q?NXe0+<{_AgPS>aut911BW$Ki zapF-6h23ls)|!(1kK$%ogo(#I2;`VcSX-OY^helr7GdpT9FW)ym#_{I9lMER9iuun z!=gBGDM&cgccV*KL7LL^N7zjkVMR$w(;s2eUBbj;Jqo*yV}?y>`s4Lk6xTVUeK&Bd zO9UbOkK%4{DXusuAzt=+i?CymBmVM`Y>sIY@5s`ZZ??GF!UwUc;%lVLUj|ya=sz`B zC>_EI%PjwzGI*b#d>6N%M*lrIFPaS-Kiy@Ra^fCX;H6 z#r3S;H^$+5wjd#RczvT=j1|_T1*rFpi!6!xeWTZw`5lECV!Nkk zxc8Fxe-&z6uL@{tObf~avTsbXS@pCuVL8>nMM&e+xGBnY?fKKjLXEbp@FgQ#jaOp)O&O`i zKO(vs2}4)oUd$B!NO>&H-$mwa_WDK%M#?KOYINpE`A0-zz8Yi3oZe5UkuX%Iug1Lu zX=-54sroUlT23`^;n}#pvG0a0O`yi1tS}kLR%26wzbPcuD7SPqDl%r#N<&wp3fgqy z?bG^3DMresgd*afQ_3xg`D#2eYT8nv`NKB5Dn8m8A2+G|z?rm(}SoiEH zo1jKJR`{xwt;S~b_>mDcQr1OvHP&a$8ykYU8XMC5eRH%=Q{zOF6>fH@(V2Z?T~uPe z8V{IX&k|~^H&v#u#)hD(M2r+{4OVYR6PB}Y+}qf`F|_4JJ)lN=R`_~6Ta7nU^ro0n zW0R|^@oG{ZDX-bO8k^(%4STdtQ{yDe8*io*5x;NHmH=1CSHm1}3ck^i)*G)TRi>}T zYqrE>-=OXE&2hqVs&QXq)%ffAD?37s4y^DkJ6nyd@VLNGYP_4F#(NoRq%zcaA8MRu zQ2Tr}!s88AxRqO&**D&GMWD78eQCF22sPeIs!U&vlr1r#2EET${eGOVoNCs+sSM--b4Q{3@9~rA?2S_c4eGXcB2>hv*;d&zhQ{>X=+?yv%>ehPVV=O zT?+I2#=LO@N`)G`lziGbWp|30lcap4(EE(ldmO@Ys&Ri~`$qeM4lh8Bj%cczt;RN! zzU@M(@g@BC)%Yr|kCc6uuEy69{)Q!QvpT1QaYv(Yn@Nq%>>FR&67$tK?6|we3N^lp zt4zOd?6V{$)#!~8^>u`>oNCTp}B@fZB})%c%&hIImlriKH$^oA||G&OK@ zs&FT7bfy}ASt3xIH#Q$Pvy)Kce-V}GsexljO!kda(+o$Xznp4d1G{nSjYIZbHWz9X zu)+@`*=p>9dhOdRs?El;0?G( zxf(c%%JkJ}X-G_}(Kp7NRs`i%V@YGxSRQ$B7}O|ag}be6HTF96tu;!G!=R1VH=K?! zZKOD%sNOfiCV#^k?bG_kbv7#$8?qUF!#PYT*w}gF+8KMUfEq=t@Z)&48lR-FZipx~I>UcojiUm(8b`Uh8eNk74RhXR zuW#TcY2ha+YILR=oehckY7`whRqXaSM^PRX(9}4}m6%lHbc~cPNy2ifv81tT44C!d z4^ZQ9R`{u%t;XkR{>?;UW$tu`|GpYM^tGsC26Z(|l)J#D_Gx`%y2}bbPYX~AOuId( zR${&yokm^tvgjK^c$hX1}AeUf_LIMvqGI4w@!Fd*9O^$jc;3%w`CM3r2P-fkT=D$|RG2sQd7Ri;00 zoN7x<_Kh=R%sDMiSWY#THdc-GlV2-@8b_e1ZnhfVnzX;E)EKC%QTSEHEP6poS7Wrp z=xcNEr}d3XF;c#jpx!s=Hh>rm-cDe<$J?&tYTzg;(^unyl*EJ@;di0NXos+zYCO=` zkrKN4j}xGV!3w_%WUKLgl=e538siPUZ(N=+Z{R@?e=X``vnDN{2>%C)wxMl8<1HVN(1`o`tx8$ZUV(V4U86jx%t8l6jr{2|nsnpBy7 z-?-M6m{j9^%p0*dVL8=U+StDFa<8LCK#k6<5G%;6)z>fZxG<*Fm=)C3n5AE*I5($s zHD){fYopLUO^pfY8^0u}(V1$@3QEjZqvf&-X9zWBrB$Y{#?2{J37gBAWoSe6?1+7k2CSTX>sVA|hs?u)BT zUyb`MiAgoKr(H=K$9|JpcC+&iblELPMs zLXFNGDXT1r`D%3U*Jiy?qb#B_{k~CdNKE#Pe`BOn5R_Yu6^)%Y){Qyi6R2?vE6NXM ztI-_%k4Pyso`e6s8f!DIQ)tiBS7W_NUz;b|?5Tn6%cAC%0A-bY_4S;x+E?Sq3*Hku zfzDd)d1l}6Hd3V;J26tk{%Ov>v7)hkqi^f=pFxddSy2l!TaAO``dV}&{P)$^6wvzy z?V0*&V9ylK)n=)IwP?}7@w#ekG$iJ$F=OYf&Z2K@qCDzM+I7k%S7K6)H(lnunj|cz z8jt#FG<=V~!}5m@h8kU2(IL@nHCoyHTf5}S{2hyb2Q4)^z?^r*ND=qWo%al=fnLN% zvXctXcdb(U{CT6Gf0`AwvIVI6#u$q^?^qJ^)p)h&1AJ>c&7$u{WTw1Fe~H0xEQv`q zW&leOlv|BQ8aq;6zTiDteI3V&TF0{02qyWrmPs`}#7OCwmiOA6k1|HeE*dGG8oM!4 zI`j5vY78`4Q7}oUKW~s4AJ!cy-G)pTdtW$;EFk*^sj(}nDiO2jOjNSlBrIp&Sn2nT zD;s=b;f_g@+CYutSy9_Wwi@kR{;h3NjW6K8uf~@dBjrm(`f7Xy6+644&1&8#7!+eg z?Ifu8jV}xlsO|PV`d?#?=o?>Bo;FfQjW1n^$-Xfg*jGuya;ouYWBbM{`%XFoYII{o z?VW5jItKW+)=4#fg#W%8`%Qh`_$jEX@l%?GfhK~;(98*^-6X~J@R_WH&U%o_!U05vsGt;BpamOgdH(OeB2MP-UJEY!fUR3$=< zTPtMN!<)j08y&0j!`?r3T{TaCjb{96k}-&h@vYkgyNfu;40)rE-kM#}0UsCaZ- zwAoW*7)HwB5k;hfg^ojC4vuOi=Bp9i`>j}g;V3H8SEDc@F*#ChcNvaISkAujcw^OQ z{`&PNL5&`)s8cXo4a4H!+9=gHIzx@(3^k6)P~%vrQEXBBw2?9#BgK%Q-ZzwN+Pv|? z^8@}R`i81SonfhO91{^W%QIMb0VF-vAS|aEk2QAQI6idZ{ZPYXMMs+1Y8(arV-m9I zt4lB%ym@1FNm}n4r768{^mOQZ!Kr zR+pw!C1Rx90fl-xgymG@@y4q0-lMm5fEp#Ns7o|kjbfXBYp3iRec`{aMn6MW8 z#_2A76S`=#H&V`q;KjB8bv61%B<8Epe%{>&gc|(}mFbU^(+Q&Uj2tO<*=)5~>*ZAA zvBr*+bKj1<12sxn(J`@XHM%DGx0XsZhJvxL#!y#RV;Ca+d1JUuZ}N#Ydup5$V?|w) z0@T$QDg(8V($w8`l2Bu)D+~DRjn%`F5|e7&gOM`aCM>5K|7>jEcxLxM_d<=HtmwEz zwi?}B{vG{Njq@|qI6p&;3o_Ig4K>EP)INWtglFM8rJDqGHO{9vvfA$(f7DFE?;T<- zy83)oKvUy_q%0uRpzoGlJ=!KLw;GM@8y_0KY=jyovZ525Y&A^qKPoDlzWTBZH7?6g zV|<1hmqU$9?ZxqnW%OkutnW2SHVU8r%HD+_39j895Tsxi`Jt1q_+ z%c;f_ja8#}r~OAjjg!#SRJIyD4gNa}vTsaI=p$u{zA|4uHL8!4YfbvLU(seYQo?i5 zH+mWZ)ceNdgv5L`ni^A{7ivt2sZ4*~m>N};@L80;TX^-gCSf_%up2v4);Ar69jPY0 z(A0Fc8oeU?mnWneGvL2JZ_Kpyd1F>wSL0@jzU^4F*;C^-T*LN?2vApJMp9zF8W%aQ z;CBLPq|CHcrmx1VxWr`N80E0lH(P||RO6|}_Ki16J4}WeC$plHgV}2I2CJjfYNX5q zV_%K=mafKvh_1#$gTC!qwAoW*zQKxm^G4I@z#l2|;v!I+H=5e}M+i0Ms{-0cSrCy0 zq#Ea^+3JM`VL8=!vax+*=wGkWPT(o5sE?Vg2Hi6&#+4~=`szf68uwVOtjJK~(F`?Kk{XU^v)4E7v{=#UwgC0M@km@^{z!TH zzNI${HC9+E(^uosh{U8C7hX5DT_u{OoJMISWzUFt;U&2{tGfvjc0=T zNO>k>ExIA5kCf*zr;g|C)B46@^o=u<)acB<@k~%+z8cp%B|U^1&!knRuf~R$szl79 z7h$A4A0;fO8c#R2Z$w8vgC& zJ|Wud^^JentZ1MsK)r9gW=PCeRMQ5|e#ntjSito+K={8jbB6 z6T2LsS@bkkG|0(TgI1qi)s(k7717mr-_X_AhDcwHZ7%<|d$dpM8(1BmTi#eBVu8*>fj9 z`fBVY$XA1Yp=R}7m#~~_JlxokGVsoc)lj1!nwrj5;~ensteU=hUxpfAXQ=T_h8o{M zjX~5rwAmXe*uE?}Cn7*yjeQF9)wpC#OYtaPu1KpQFF5TvQG*I}!_aS6+*MpS9YHYYqWp@0?Q8 z($>{z71z~hZP9N=i8gy`+=`KMA#ZfXyn$*(pf-y(NwQCb8ZA`;f27p3ipv60jZdLk zYm2a)YOHFk8a-c}ejU^}lNDVQ%T{A7_#YitYIMv{Bb1>=I75vBQX@(2(?-heE-M-< zL2abebX1t%H+lx=wGnEBY*a#Xgr-I~E-|UbXK7X=_D^%FQPEg6KHvUMKGf*XipC|f z)wsmvzXB*n%263=pwIYk`PD!({|sAG3^j(BqRn34Sb)B9iK~cs=aibGk`nXPsEiL2 zSM)VqY?bMcl%wMklWKf{ky30CmQ#)L#?BiXV-I}~H3qPvOPy>r#s~QC9!fQOV1?_c?k@C%HPyZ?UhAB1G`-ZoXD%JQB zBSq|==2WAiv1;5o>z7lZ#y~VRm954Ega6W_RO3|m@2hc|rK{05qN~vl<%R|Yaj$P+ z`?6?)QCE#q;}Y}x#-PQie4)l^mdf<|M&F3Uq#9p2tfrqqSWY#bX{;I-fAhpXs4)ml zO=qhy2^_t(Xw6`xd^Ls`x*9_Rx*FIs#qSu3HhXH^gOM^RB0#-w3|5%0#_mlYNi~KT zvVb;k3?+znuwobg(pQ|-i2c)?YE=1ZOlt5xZ1c}|y#qA{v!bhlQVsQ!xJB21<9P<} z!U0w@GOqJK&jNo-p7U!)Mfh(`@m8uANa>{_R6&0<4OY7J57ynb(S5dXeq>x_3g^dx z*Ljx2g!2U#V~!jZAuKmn%X^NgVXm!q&fN*FL(nWYo9mPmyq6? zq=gpoZ#LsE%hD@DMN?AL%nYu}lMAmDT*pOKrq6YODiWzWj;TyKh~ zOrPrvLt>Jvh52nJLAkl2$EfGi8uqpQffp|X*I}&ax_Gv)(_-{?km7o42G`p%xZX}& zlhh*3*FFv_nidnF)`wsI{lk5Dr+d>yc9*t>%3U9QUXxh_sh zOmZEM@p`vSSk6A|G`0^nyQBx|X)=Np-DG5Qof)Jzdlc6PGq^6v;JTE!+Nen9+82Fz zW>A2dulu(oJ``LZbXBI$bxBfUlIs=d!%J<#a&leWSgysV^`<_27Mi8bO5S+A*`@b( z6jwW_`)a3kUmr{H-{(V%G++Cn58v!kGc$a(_RcF7Ty0MXpR1jg1tixA=);et2+PT} zvawwEM*2Pmu4l8N*~x5Q=Q#9Mj^bLTU)9!>Cv>hAG5+g=oR&8?osK>{$B|9<&pDTL z`%-c(^D=#|Bk#rJjIzzn0Z1Vm)wOr{5wK?DrrfJWkzu zRrT(>ud1u7JIO%g@UkGo(sEs0+xeO^^q(H!dIRM?6HewjD#Si>Be@nQa4kvTTFSV_ zg_kzhD}0nYDkMN9hnv1y*j4CSoPujf64yaKS}op^OwYBpx{f?+<=x;Kpxn`VGS{&I z_K6zFbwk4SHR@A!eap>$IWmcB=OE>d4OHX0V%a#0>jt~h(KYI`8d$pChxz)Jn_+3W zuBk28>%QsmE4bcBx#N7vT-o!T{`NY&J%Q^E#uZOV_)c#1PR2DRytH)rIq9(Ur_~Qk?(BDVu88 zBYqfC*QVXN%5{&Q{pu(4NLick7&muPT!2ar-}>s)O9a;sL$XrndYeY8ck32raUF~t z-s5LjTCT;l)%E+auM7m&n<;m4ESW32hTa~RIeb7To0P;H%*0?wyrlLhwaOy zvo>ve{K%Jr>j6!)Q11&5GKekQ7FRrTUVYGHSX!=YYO8B(U{x1z?Mb=V4~S2|*w>tC zVgCEHmag9=a6Od3^$@t;r!kKdU3*3-cUoA0ims#A9)C@6{myEkay`WC6|O@gwEB?A zu(VuDYOCw9d0);2*Itwx4kmM*uJd2twYVNln6JMi%-3U>ulHHBY+dnyHFvts+)S9S zBes2TKyW=8kd;mj|KhVSOV?qTugBaBOUw18+Hx(pWFK3bdQz~>IX%;CS{ zY7YM$Q*-#A2>Z2N;ib(Lk56-7kghv9Tv7KDYrg&!7cEp>|BhLh#q~kt@IMiTrR7>) z+Z_JL|IQ+C?L)b<+{s+$AWyOP7P_vutZ(&i1)gO z>xv#_rL8OawJ?k8@Cc!IhNb6PTV0<%*}VW<`@$_Vnd@Bexl@x|@lLgKs<);|P|n+IPxzcq<*H4!0I3l<<4vQ9wuISgoEUpj53B5BcE!T?La_v5S?)%_+ z3+28PN#;7=;J3T*2*EVjIYnwRx9cbaD&9%Rea_1WYRMw`pyE=-K>@{bk;M&G* zHL$oo;-fWf;tWg6wXC)|ob%P>Vc^=2auxw6km-Q|+HUgTDFy$I~=y~LUhG4?Ch z!b_Vg9$V&$4?ZQVO_h@~?-#mWBzZY|i8U8-Ud}b=(IBDs8o5^1R@Za)j;RZ-{VDgA zKr+|Y{OlA-a`i`4u2+P?Rh~Dk!FI6d0?SLAD~^hCU-OFqD7v1w{x9)eb8Gw&S!wSP z*IW^{FrjPCVx7=C!_w+nQCnR*bsupuxZX;+uWQL%7rNOglH__#0@rI3xb|RN-NH+o z>+Q(lg%+rAJ!%$xBXqqcV)3$c#o5}LYr__1aec#}H9dk1OUt#gwp<6iKIBbs9RRoD z$y^tk>=a3I?G;dU?d?-_?SrWJEH7=YI4a7;=`Q{y(U52MUq@^PvEL2aJ>Uu#R{VAn{c_x zT^gyzwPJFf#r5`ptaNf%PvZI__}}4Xc4@h;t*x%l4n5;ZaJ`*!mxYtLt_ZPHB+2!@ zxT@>@F;&+G5S2C|;km6Vj*4e{CHbw|Jz$M!4rWUi|M>=a3I#d(x+eSO@ea(x`xF0U3gR~!}Pt_oPLJJ;9UgCAZd zxIU)IN=Mhn8RYDT+0T%!dE8`JTCVGA%k{gB85e`=9hAG;m&~!_&8b+n;! z9TUQD8~T_>N)F?wD7RP>prY%lXEPQHuA`!|(&0MVurN#4naJTWA%>;pT2<>DUN|@h zT<@gZ5?3$6sL)Es`! zZ8fmC&Va7Z@lMimU0+*Wf6o0^2iLnOw=9;-wIa$+ktEky30!9#P)9XD4x;uF;y=HFI58TV0>He-XQE!S$5eu_)4I_tN<(;J0wYFSO>oU*{ zuJ=&xx?nQb4LUnTl3bT0aAnscXOD%oBNMZS@^3OW39jA3cHE~zcow)>{w#nL(tQ0}{d zWUetkJ4KRQe+#Kxe@E6j>+m0lN(W7NY3n*1IUMr~P~n>S%_8xh@|xd5veM!DyKZ5Y zt}BqkfAE;3<+`%AT#L+sMc_J^a^KgIxqj$or$`pp;yPi4YjIt$v$+;$2H5Y<3NLN0 zI4a8h&@JiMYtzV^x}VK;MUS%5=8Aq3xh~fUy)!H=*W%i8-PL(FI}0BIx8liM_n7Py zNpfwFz_nol*G7!1UwCPA#Zgi29#epduCHew$rW51q~O{xiR&_riW}9;wMwt$`x0NS z&)W&ELn(J}G@0wZ2s=fRT=C|lbImEno0E#J?9IswV@X_bRFu0fQjP1YcQ-5%Tu+b6 zN=H}wT}dm4mzY#6-jz(ND=ta)yCHf_zl?G6?g541I*f8Z4kvT{6buIYB-a)?=PJGp zr1(s~%JnRb8XivO`WSNf(~zWN=kPt7uZjt-Ep)5W`GyhnYhf1G{stAFr7j7luU_)|kBe;q^PH|htRi3RCx6|;}n_GBk=kOEA;R68yDmi@L zvrmibYjGQ0RtjBl27`Vr%;MTBM(CYkX}G$M7e-w5tlxhrVY-gjDf@f&#~7?N{EvI! zXm=AxH~xn!;pg*KY@7BABJd#P9`soes88ANn7F1CUu1HY**L01sY6thut1=6v4Kxd zXp}vh*ZnUfO1pU7CAui#C=8aD`bDXfTXxi}cD(K~7cX_|xS%4&*=2(ZQ#JKDD*)it6#5e(t{Vyaj zPJ?5Y=n~^(ICiODVw@7kI%*P|ZNe#zUB)23lZ-IT^ESr441Wo1zRs`_K}M8e5Li(4 zJQ<;4zguFQu;-~b6<-k*n9Fti7T4r3}k5h3^muM$M?;TV{?}Lej)UibG>*F$8qTd3Uhaydd=(ohJ zpCvNcc>OWL4M-FgKU?(Mbt=BW5TGi0AS5wI^c!`FIila>mzWS;M-ttvNlb{&600YJ zxR{RUy@L{)ZK95g-X|b2AvzPduTNq^^pU`BaWl*j{Tv8(k2}x+p^x;UP0FRX-`dtwHULGvmv?w!uP>cnOVUFncMI`2k zet%eELiBqe@B=}KIie2^NX!v^h)-g(O)2_Nx5R|#OyHq$i3!o4iBR#d7{eUV+rTbp zV?y+{up7?IUQ4=(xPN{Ie2<;HP|J$%-@-L~hM1RJoiXL*SqKD$D z=%XMIzRuASeP~D(eR@C@eTGjJeWshsY>EDYpNfY0rRcLF)(;7ph-vX0o&Aswi-98g zAcNqt09DbS@kz`PJ>-^{BYMc{kg|p74`@_8Dkkk5(T9d4=7>H$AhFq|6n%zIVnTE# z@JzSFgy;xd@e6*2Iij}%HY*}AA-XTfNDGY3^#68E|9iosVTk?+lqHjhis7cYcpoE=+wY+adLfph-rHDQpqTj&c!o}p*B)*Ybr%TM4>FfOxb7uMm zO=3dyM+_>CGD!4i;{UwADE<AbIp&Cd z0qnNem=OI!*lo3v13$n%SNl)P`~HoMKY{3vQC>zcS@aM6LN0Ml->s>l?{TT3v%7V+ zm*>$c#vLv%@ySvAks(SvLdE++Ryz~1DgIdJC2J%1i66W7pxnKGszLOy6n#HR54xo2 zp9N3~y6{gCoo%u{^b1g(>AN+FIil}jP|{4_V@gbj&V<_=m6(|64ExBCm?QeWki;C( zKh`BCMBfsp;!pe%6QYj=_Nm4&NA&R+W510F(I*6{__KhpgXp{do9K_f{$?gbf1L8N z1IePVjq(q}TQeOSJ!PhUAG5^MnRq{7<~gGO80H@vx0d&xg6d5FIiQLj_o<>EadVli znSK48H*Qj`HRDi1Jhb=>OBlmqw+Bq}*hls?4=uhZW z{9{;R&hq|KP-2egKL;c>+k{hmrpJ8}6QVPLkGLf!M4uR;;-egMM86Vtzu1@%{VE?7 zAM>-e*vJvRYy78~{*5-^7?)XyUeX*XH#}g8UXo*2-$ZJHbcrX#zKN5?KoR{Z zjo`8X7180i#O#?4_a$bF4iXX*qK`BPR3v7L4nh*MMF%a3%{DF3K~7>qbO;QJ5)-0N ziW7)3%n`k7kU&>rLiBEE>j?>r&Gi2!`dn@MXApe^| zDtc>E75&^O|Dd-edK*I(y=_Ppy`8R#ex9GpY>DpEP>M>?+q^)^5_3dvV@S*qy=_Qhj_B=li3!n} zz~}iTCPbeCfqfdo9MQYOu04Y|CPcpmc13Q1v6=qgmiJ2@?>HW!KS_Bx@nq3E`S|D3 zt(kr~0&Q>PN-mG9qWfd2=vPGeC%7%qJBL-#uMDc9cL}JXV+~_6TcUS$Q_({{DS9^~ zL_f`1-b=cpmwsUu14VS4MV7FmJt3yOkt?~J2P*Psi3!msX;gAWL}HHU zox>7yM87g9vDqfZXUls@mw?2C=uF_Nd=e9)KO3Qvu5N}oqF)QFn_pr=^d4~nX@NoX zcmA8``=(!Y9YlYM^73QJq8A$c1Lv0Ly<)29y(6mVeZs2feIdy?xEtbeD!C<~ir&ws zir(L?irzoYWwu1Wm6Z%BI^Gy9>hF@G-;PzFKaYVT`V@mo3Jn$*Ca@!Vub9M~nT{J> z%gzzKPgr6?^r=XqzSbZX8Mb=|A!+A`-p?no*`^e|zguELbS7~BxWt6$&q2&vIp&Cd zy^l%;*q9Lgh9H&PuCcc4nx0wq-$Z|LS*P9*{b|ZOJCZE=0}&w?k6+2)uqyhHpep*% zfGYYhpZEm65IyJ?B_5%YU|bdb!I&yK9;FtI#}CGPLLgT1P?(Ayc1zJ8W~Go6{gEh2 zR{Z2y5*Orw2n$T2=!3%&b3`8!l$ay>(165*==~u2FrUQ4OlMfoEip&*U|eFeO)2_= zF^LJ$H$%AL5s3-Wr$OL{!VGgn55w+Z8xx{GAE%N>qQVZM?@1y0SM2c$E=k$^j~XAi zOvxS3UgsW3dFO_cMepTPcJC!)bUZH9tu1iLSidUzILthI_g(_w*q1(8Gkv^?*Pla_ zEkvIXRYjj@sG?5_ahWaAC!_R;E=8ZhN--%qCQZ?!eij2|repVB(#t16In&=X2#!n4 z5q+#*VvgwJG>Hk(v3myj+p67+*EYF zAw^#jS4CeMQ$=4EQFrgl!)S*?St0t0pep*xfGT>#$7QxeUxm`65h?m=or)gQr08qH zDDlalh|YHJZzhTUI)q!|X2D{!-w}ODTw;#sOJfofqK`DFWLZRFLiE=##`3Vl9MM+< zB{tiXqOS}{Oo+||j`$=dM4uI>l2sgYM4toESL@7S`c=_4Y3lBMvkUD4QuNKHD*BeFD*9G~ z%WR4MHcEH}TRd9hUsl$Oo%=g*xMY-kW@YMd<448 zj$uOd`9Uh#!5}fyOO5LH>HmkBK6c*A&q4H2ly{jgS@hASx_kdf$D82xOyB2MMgLe+ zMgPR5?%qE!si?gvMgKIaioV}aMgJ_sWwt~=fYK8IDf&THib~PV2o;Us6GRc6?cPV5 zEHG?Vi;dhYjY>Y!CFacZeSV2KqJOMOOo+~Q@1HP8^k*_LUuGEo5||_Ur%{PHqVG2( zCPZffe-@IM5Pbo#0~~WiHz4{!8xx|x0@2L~Ys;7S&Hrttmu|Z<8={Yp?=)dR^6QVPLkNG7gM1M6xCBJG6b3}g)cE@c@i2epdKM@diF3LKR zLiGQ`n=_5SDtri{kD)xA2_!yREn#Qq&2?+il-9-UVkI8A(#)_TdTCZr5xuk?B;oB$ z#I-crCrUg*r6;)+(MwN?E25X49OE(z(MwN3>B+bydTD)>2Ky}0OB=eV=qa7WKoR{` z2)s8cKsnQa!EuS%qQiZO*`kAl#DwUqZM}fRgy;;*_DReZ9ke7i+k{i>J{{yFCPat8 zpeQjR`a)o*aLf_?u{eP)vvZdBMZg*|h|l!82U0BW{|C{}>(OW|L?26e*T<4XFU1QK zis)wqRnc<;s_6A~RrD-K(#)`Cdg&>sVzCMUQ;Oa$BrzfSCLfia7nhh29eZUEWtb!Sk|329#Uv(XI-Wt7UJw!(HgbOb zKV8!oWNiEpqK~7zo{?nHuYd?SemT=SBkY|tIn%Fto6)7{{SbD0_g>o1R7LL}RbH1Wz15(iOXE`X0U=fN+jLd*+x=W-OLQHjXM$4n zJ6Oq-qTd;$qELXvKoR{eh+fw%KsnRb1G`0&m^0J+F^JD#XQuZvB_>3_2LktxN=%5p zP9qSKm?Qdtki=%2QuNz&i3!n}z_EHeus?-(bquqJA7YrdL6@VWz|!(SuQm zIif#kNKAxOoln4m-?vm zF&h)2mj$Wx3AeDr^4|KtE$?UUsN4n7CsN*hp=8nfhLqQ(O2=b%b-=vmkt>}LP(`2U zQ$?QyNxYcbJWi#P;#72rAw{1YQ$?Q=QAK|?%w@Jje-5S5ZYlayRtm|PJ}rt;oW(#9 zeFy~Z8xo+L=@AGwJ}5Cq^a%lpIigSWNlb_ygus*B5)-0Vpub6Ri8-QAj!A5`38(l* zZc0RALUbnZvtfw|(aV87$1z9rN{Bwy#)Rlq5Pe#dwdFJYy#FTpo}TM|fasGbZV_WAH?%X(HFQ?(Q!B89K)8r9HSzCz!n{;V`B01J$BpI!!RzE5I~=nLEub3|VdmzWTJ z2LygOCNUxUP936$B<6_zkZm{Hl%huh(oTrZ1YV^}Oo+ZVLZz#DTSxSDuq*a6JBA6- zH$e1~xWI7Bc37)^P5(da-p4L(#AfUBBzEYNMM%YDy6J;t?v{W~icX52>Q>(7DW(=sW!oHX=peh0c zLf}oh0Od?)*k-@P9MQLE5_3e~${?OFLUh)4t0^%dI>X+MO3V>`n<25;Ci>treS1h^ zLUbnZ4qakG^eC{Meug=sKjEX&T{b2}e=AOeQj^GRW~hKG>4cOeczK zc;Mp3A3qy^3?I-DqCQ7?BSX}(EP!@}RPSOFp5=vnRD@+ZdonMLGO1Df2xWBES>0&J zfu{(^2Sr$EOq7bSglDzjmg8L1bZm&S>gq14Ls>@+%4($dYCcn=yz$UxqCpv5WtHoA z%g9U9&5I~+Vt|UU@Mq}3=d4o(QQl+?RUyi_O17emPUdbi?`z7Nf;o)~L{@XB zRb#z%)-8BK^cv-uU2_6?TladG?WeqXQOXO)(aIU? ze`dzUSGQB%f-tygXk}Mr)iu{H{`*48!vS&LbIe1#!;Fr)t8U|sl=rF+aSTzG$7$8X ze7@&PvnlU&Kjlq|P?pzjmDNl?^4n6pNwpBXCV*F-Q+1lY$hGwo%3B0pW5cL&Iy}wX ze%t%?DDTY(vL!%SXE?1+)wRCkKcKv&A<7#C%DGOfrsk@>YY$T1@-TU}q3R5$>Qu9L z>q-yht<=f0HHubFhfVc~t1rY@t9<0y;wPG-$&8{ghOVCumDeCeN4kk7IaOn|o4*~#2yvG1Dg znUq%{8%It*!BFS+zZ%3H5d(?ST{>4@-2sUb8KY6qcE{Pu?|%TEaDul9r=WS=PPb;%B~~ zmKzKf8EH8o)#!C@zJwaV(#^svEyt(oGo$0iH}9dA>ybgFrnH=p%95&DZF!hl;%W(@ zrRDfkqq`0aK4TIrHI^-wrC8uvR)FO=j$tVl%VWzb#AuW$?C?H1*2TJFk_roc-ne!yeLg`~ja$@jg8T#Q_`dx(F1fQQqFLMG+UG7j-t|z5u^qSQJfhX%R!0 zeja6)4~&2mmN8-eppgI-Qt>VqH4vms)2g%x;39;c7?y?rzX;(&y|_NHi;yK&N+xYC zIrn2Q0gHWRGLui31cnsr5I*P%u`DKsaaE8v05%g`0`orMktHM#G{*n%^(Q+sjy@`w z9MYNBKrJS?FqR(nGb}9=To?rtc44fE$-ToLtN@eeDeqG~naO9+1Xo#0lOqY59L2R% z-nQ6Ga9Pe1FJ>n&xhAXAYl6uUlX>khnS!m!(I~^xGvOaTW_t!)tZQO&@}TP)fys2Z zP)(DA&;(b0i^(4en*0e(=C#8F8;H_B{R~UX1RDrj z6TK!TIgi(`4<<7x&#b1&7tjQ|5y7OaPC&`7vbsLD9brBw^90+Myf3QHlS8`)ujWk9 zhiDESl=rosJWsw2@Lik5 zq^YJdInBkkZS0?-3ESpv^cUCfZG7=LjabhG-#~EC^Fs zUWj37HRNOzWmKS3rw&pJ*+1)`2m_>cWW^@J3*6{F1Ed8J}6AscKCq2*PS%+ZiYAND#V;`dDoh?& zyQYI+(#fhBx*X zO!`WiR(9b6gq~_-f^!C&NsaU5>)tos0VWIJLN!hPj`4eOi^+o#b)F1|)8RPtL76AG zdC&V>I?I}g8NcV)_Ui?c2f5ddCb$5V4G-7M#L2F@HEMFl@$g(Qd71M5N!G;cf+jdR zu$Vj%SDB1J<~&A@TSNVjA%I;b+iN`Pxk5)&Mapiwm@ox3*>yZW-x!9*sw0F{ji)W`(K zN0Ldi8ndg_{S<>@PP-(N(`sb0xz&@c!Q@rAP)(D1&;;j5R(8!uSi5FM z*|jE#2@amT^|)gROdk1Q81AkalNn|rlSRO0Mj4i#iIZKY)tFtewJ)p#lh??bT}_jd zp~(n4yXN`S?3(Xp*BarMy>^vH$a}H{Dw?!%_xMIIndcKNq$aokmCbk8$OLDJQj=3_ z)MV%S#UFvm>u{l(CiS7o<92qv9#NUR5r%Kf1vR^HtmhT4OC@Mhl6%~`KY2YOT1Y0i z0F}KFW>{KHaP%peG_6sS2KRq+E||PQ-Uih)X#`DhsAy%^@&rv*xY@Nv_+@LdHbCA+ z0RbwSbX#!rEuqPBpH*qCUAO?1t#C6eEfbv7N+ze)$fU!w?1rh%Lby;(lg7~G(ST%9 zlAuXxm|bg_56XT*vQ=ut!1c!B4%mOp_Z;I;oCsA4xvAe#8ave=!D@O5jX!myQURZ4a`O zEXuAjS!o+9#qm&ymAt2#{9%eX*(+P`e!b7a#31az69X{}=aT$bJeg+p-ww?Wn#_F(G~Xm| zbM!Ydgl3Xv`KeKMdT#ktekv}HvkZ%7c@qR>2CgIAkFp&R@uWr2?8?vJnFk8ZO@2a$ z0+cjyMuBc6CTQYrADv4~&}8?`J0ccl(FFDKt_)%{p{B2zn%TcPG+)m6{29<(Lf$hp z=gy1^P~H^l8M|BNYL=glFtEozoJv_t=MVNUfZGY?}Zy^@?Uwlaqr$+R+U;=qt>HI34afQ?24d!dFo_8O4&%rVp^;5=; zN|oMv$Et?pJy$2s`l$7M!`oI|M>4WaIdVn=^R$`6A0RIdDLm`oRKlaG*WSIZfV}6K z;!#ykyL-A(pZ3q~2g%#sP2N>_jM>}i@FxA6*E_W#Z;?r!wSJ^{S-_gMVbO!8h6BF`!~^^GR0$TXsR&%chmJ;K!JIL4adRE;q% ziI#RJ?{!gr|B=zh8S5tV#{HM|C-3!f@`^FE zm6_t=ndVXGrwt>0VTs6I8n!KsRF6W>t$W6`#2$qr(9&{rD$Bap`er=IABDnMX*oel z(Py1KyFJtRqfks{X*oVspBXRD-0(Jk6pE~umJ?E0Qq%HVtN5c(B$c!rpK5g1hU-V& zz#oM|PHFkM)92TQe6(C=UF4MG)N(WCcA<}1VhN?sojx7QjHkaCIe}VY!Ni=FmS3c@ zq{};(zeX)LM%a{*mOE07?z-UJ=QUVrEF+~QRyG$rGT4e^VIr+sZh=BKNjouXT5f?| zS5w;YMWN+Zu(>2IvB{_<_P7^IqQG2K_f|u066?OmwpMPPvhUMf?8{;kpZos$&rRL2 z(qm1!52K&SJd(%pUc4mA7I(2pEN|%J>$%w8l{dl$as;zRMCB%tT@BDkfXXKE$!K;q zzaF3ut5WpBE(GX_VaW4TPj#v8=bFuAfOUaN&E&zU3tGYXm2e@F%w&kcuPPRkmRN~! zWwMyGaxs?72ZaePL*5~V02L;&PCsLz#FeeQrD;`KOhCOH!{c9iCXOa^^_n#4A6j}H zn1IDlUow**G+`IPTG?&arU{aP1dJ}69Z)$|560V+%k-}vz?V^|+nrNsnS zPxQpFv`h{-n#`(^$<{gF>tM19E>zQGI5fdk+G5fHORD{#y8PlGyG#qe?CgSL-r`M7nLky$04A%+`%pDa9?|&D!D4cGLU#G1 zEc1k4HWRkhctjJR!sON>4{ml?c3o~-l@=4EW4S-du(V9DR9Ux$b?4WpNwdHiqrhYh zT&SkWV_0pl2NF!mz78sylzkImna6xkvWqc!%n+c$HQ88#CdTtqJyc-VvGr6(%=L z99YSBd1XJwtV)Z?MH-upDm>S$ z>3Z_EeoA*R!P+vRnkJJlPs-$sFCS#^+cM!p`F$aFC&qkGR$<)Kc_(QCRG56*?lW9@ zaa)HztV)Xs?&r`G!_sMzS>Iu@O{}h^4T>gY`{B8_Y2h&G0|$AUoW4M`OXH#I!0c zCcXSrUK(XsS|%+VCZE;FP7CQN1a=v=Y~~WkNZyqg;kA(K_*H!LRT_C-^}CJ- zc-?B9Jg>N1$FJpeYhd{@+TFnGicRt?faNv3REl<3Gmi(jWf?4Ag5}k`R1V9zA@ss6 zD`EK}Ysc%Vbn?uG<@LO7E!xe3<<-2j9+oe_@;YAH0Lz&!_{mFASWai{e2l|eCV8HR zWp`e;3GKqL?7{0c!*VJtyYad$uzW6rK6%~N5P6eM z<>P3#kk@@;kmoU2Zses;{p5KRmT&OV{wR4Kh9%EP?`LTD5aMzxkIMlUd4~I4#|QAz zL9`1Zg8d?F1T#dQVX(Z7m%f1IP*~o}Ex&~25Etrr=_^=1fOZ48<=0X2+z-p!dEK{Y zcONW!@zQs&ycd@DaLYrm92jyP@67AIhvhwJ*M-;p;3v;ruyE?nmJrbg zJZ8VavM=JfQ*+u5_Q;^U>nOhvV_gxY zEUbgl!zo61-gvmt3S(W44wpL}jxrv0J@p9XpM$YFhS18XnymSY|5{1;txalr32Wta zIMJxLEq*QKx4~E){FJrKshXr+`%lX|DZeeox*&=wr^89cqEA{)p!{|is|Xz~aav8( zzG>L(QOZ9LW1SbGEG*5^`3c5tyBeNH`PkAlZHrcKIvtMJx((d(59JqOtk!jnfe2i5XMU~RZXzc%D7Uf@nvCc+^uQ*kswbkD&pF#N-VXPJ*%39=9jnlg9 zh({sZM?l?+5yV{AI9=TDeDcTm6kcM zZ+FVS6k|0tX&Cn9UcVbdD&Q66FH=R7Ku?8K~Bm+E<&-m`=R+Qh}Cte15!C;10W5ZL=B$_Eo26?g!q8E54*Z9ek zsS#mSfaNtNdFn7rUUzMXJQ=V=98lLoBabUa#BOy_ic-$MF4XbTbq3}9g%<#3aLeoQ z{Sbem&sRhVw+&~Tlzp-$-K_Voad^RZCn*1h5H&2ui%4F>uKH8UTyXVZ$`3@S;i@oY z=Q>q?8z)*`mqqzE;nz`Dy3xw%@J}QE{)gsM{>=euxC|ZUIaPmaE1vQpw|Zi%H)E)B zI{ZuPU3AA?l-~U(a=?}xGer&D&0)9QC)c-Dgbl;0m?ov%^0$7%JO z*8TCWn<;;Qn;M>nu{=(zU$tKktbd;JZ^KyUpsJqJ>V$FTHJ7!a{M#{B3mltirXAih z%+TVN=Tp9JQqJ!Is)s9&mHqW{^)@{pzyf_IzJ>Edi0TzMRXJv(*6oi{{#_9E*9fYV z4)x;ISvOMt-S~31??RM)mS%VOhcWWE-FcLM4|shEz4Gm<>^j;LKeff8c`taG&@0EV zTm7Te-5M*P{6T(d_!;!7<5c}-Ox^coUCO^NNDV(lt1PGLxbc8yeoy)LW2}8)%FcAE zPH3N&Ua+0=2V<rxonb`7Zk3&(o&43_4U|6|V{La+wx(1W7qyx4 zEag9hv9_YaGwrH+{}_KAy)#7l4`ZxNG0JXXS7noNe0P0>_mLPie2cZxB(H3jF?0A* zTqhpGSnI=-UEoxa)@10Z4^aN&7;CK?Rd$E<{?(p&{n=Y7{|Ss$feu?Ztz4Sl9E(|r z&ptFPjZsEh-369UxhUsbyeyP&veMHb%J~Mjajki2WR!Bgic-coycB}vm#}Qj+l}&5 z&KIyORty{J>p7FZT>%ee;SYz|V!dA#l=wA+Ms?RnjNSiS{IA1^I{WfYb^Zuv4SH^A~- zUV25NoOM`>KhszwUPZgL5u*LP^cpOyd?*>L?hRO0!15Dbw-A=)u>6$QEix#lEQmT@ zT8wt3X!j|%Tms8tSboGyOJTVNmLGG=Ww2Zg%a3?zg+@7%IHJVkxf1PGMsRDvOA%PE zKm_mL5nK(+Ww5-Jm)5{?DJ=VQ%VL9amIP7abtP!`CffDlr7~D9f@ME$Sq{sEu$Yi>Gb@gp0$#Tr?Oupb z=9wl_Wrv?~X2R<}-0K}^H$Cn;ezT9&?LxcfBd+5&^3pqK7Y1c&V!YquAccwk0v z^U_DK92cjoEe5Om7?xu(!bV>DM5mlF7~w6A)qRR~c=(yMftNmmWeApn?EzRm1Iw+v z?jS5j!k6{DWSW%o6yma$m%c!|C(&-R!TS6XmLp*KAuoLe%g15)0WW<6%g12(7B79P zQ_iD7$`m?$hjx#k-MhT*Ff1Q}WmIE*eh`7N;!X+0SS< zG(wqMc`tET4uPfc>mO3muam#;Tc^fP{ za?5|?lrsR98=0j>F3RZ-%S%|Dmf@$ITOySCKVGU6rJUXd;$pD6Oj!2PDf2>;m9k*j zQ=?42x@q-7)ckKZ;=(PnqtyHl+`{tpOgq_6%}=1jS1|1qSpH&C=2<%Hr9LdKA?WTjJKiM+^Ot+P_o5H)A} zhgH0E8rtp0HEos2>Q0BHIL0JbH_EPW$oDF-u$(x z`0kj(pRgV3ZA#0=sro$q)uNB9V5zZ9wX}4nvTXKc-Ivd%!XFXOo*`-3IMwK}XOmQYHeK2|wi1?z=S`aI^VC#*o;prnw~7kCH`tAaZJDaiCSQ3nvta3F zcPrAeNvb{@U(@icKdJCA;yEHFEt{sYbWa+-@L4K6gm^w-*p{hAZ*;6U{v|9C&&Pw( z^0ZWz4TrXVqaPK17iPOYX?b$0(HmTF^8M3c>0(<)X?c38KI;b-fBF~|ev5cMY)H#y zsro$S{@sHXQQxi%~SPx^7y)C_rVhJ9PXEW)=Oo1(gmJ#W>VqTA-0{Cmf5LB z&u;j|-X2u=Rh;d~ZOc@B)~gdZ@*OM@&!M)TC#AB?dSv+J(CACVbBN#Sv))`Y#eC1) z8P!T)iFgjS{cMn`&${kQZfrq?Uj*5GiuAL7D$6a-K;)ww17pmutk&|E-(xi zldM^G>#SFCP9WCQg4oE*&ZWXfOmHNrkw?;{-`szL2WV-0goD+o^B} z`uv|ME$61{^NeY8_Z^_Z`_bpc5!*6VpPt8>O+QS9gV1LOzqEWYm1WM3tv^hp!ht?^ zswOR8N;P`(4<4O0feP#`51@K*HM-u82Ts?nP^Z65DKg}21mai#2YK`P5r^9Fy}oC^D(&vv$- z3sQ~V z`fOCP^@B&K@VX#72bO&rsrqdA$@CVmyas)?vi&qt_1WO!5wGJ)-W`1w+J3&0%Ci2Z zPTQJN;Z^9fr6xz8nQHV?o*sM&)|D&K=UKL&ucfj)x!*tCi>UAlH#=aLeLkOR^pjfd zZ;KVE6Z&jn`#B?(W%hx}3p`ZV5q%bDvd`(MMz7~SYwO)qc(I>7FOZfqQdwr@ul=?S z6<&zd#v78Bqf(8YS@)vz_fX;a=rhmub9O4rx*v@$c%2G;=rdQ7ea=Z`S*O`gdp@Va zb|Ll*MOw~FYHUu1x{FvA4bTIjkb`_Cx29wcp}mdrH>pB=6b1}%0bhOZbNurgX_C45|kXSCq@ zu$w=ihZ{*;gWNZVE93QG5Oy%M5{B~{9wuxY zdf;l3w#A>!^-1u#$JX^Ji;vLtY4Bk)ROtG2Tx7f8Ix@yzKY$wwSEj?0HV2+6oWoN# z2cavQn@@8NoWIVveiZ^1M}Isfg6ogKM#dP%x%R6C*DH^Xy%tGF~Rj`w4D@S80Xr*7CAiNsTRw@^$XH=hLX94;qwqAmzb~5`z&@Q<2v1KtyDTM z#l=b`xXy_2S4ZH6qU)D_st9x69Iju1*YiHuDO}llHQjAvI_kV^y~2^EWhc1C(cg?1 z!#LMowa~Tv?jf&$>zAaxYb0}>3!k0&`cgz)o92btS}SuHXSqBog6o0+e=&x;X6wq< zp}E{QhbzNgiZFj2UD^6NFKlBv+76cf^x!zg}u7}+FT7c_Uq`ekaOk!}Tb5E%ZqaV!kr2i`+J* zORkIJ5))jHxu{}sjA4RnEpoW$t{=OB>(`|1Hj}xogwKqf$l*wYy__VuzU5Q7Zgi_$ zH^$kEOTsl}6cv^4XX!xo&hzOmIC8yNz*%ajpYu!S$5i z+S~}P-;lNs$+FNyTj^fK4(ycr+FW;Hr_|f#x(hp{ULl#o@96yXDr?{LuAjYL#r`R} z{^lZdC_pQG-ro$W*l9>i==!@!6}v(QupYU#vrG!{Yr5ZQu1XjC1W@iyUrv zxWzZ%`YmanYRO#pfB|-fmacojAmEp}ex&i2z^rQy;>2D8v$*av*-K!|4TbC9;IKy* zpyc|mMiqPg660Li+hr9WX*Q;#6ZVc-#Xbf(T=VOo?LL!Xoa=41&^4pT`y{x2N7?~@ zGS`Ff*_p3+^2tlwrHaoDp}Dx`d=V0w^Yp6tQfIHYF*g*hY`z{e1t_^P%#2D*=*sl} z+^{hnopAlX2uX|&l3y1w`4Y7GNRCfeHb^;a;s7VNg@jL&f};4>69D4Al03SCb`MYapBn1*;g z5j`nfxemW-0+d|Y+&s=8o|}T}pE~Q@#&pzqS^l4hN=$Ig0`{B1FrLFbYmvimUvTUX zaQ&XN!?9$p|H9|1F$+1@N>|8YXJYtD(gi!twKBsm<}!Dq5>p8;UotlwUGp;ys`%Fs zpyUc(=vHEaD|n%E8^d4Z#k|H45))jr(YB7pFwV7CEx4ZFu&@!h{y^G~@g%O5C&TBP zU6Si5E{mOs;VVxut(8h=B|PC`ud9l+sj`8=UM*$+9IkBLM27;DTp6!Z7^LXRc%5R} zn2tKOUSSA{39cuhzXk@wIM;5q$YJ_v)m`BFBWXw6$y}SlXM4U@o)%KprpjhIf8kcF z!3tg9=wP+T&{!H45Kr+{J;PaJo zZK`Y?;x8{-T+h{2u5J7(*R~pav6;EyaOJ$tF$5^NHiR~PDQ}Y7FCC`=-$K6EpF=DeIpjr-N&pv_FE$TrU6vN7oC%fSo>ZmntuE@z?yV9KOip zFKS!!wL_G>sLkAPxO!Q>Uf>s?%;5trs=QE>81LA-KT7D_#&mR&-&hA`N=$HVg0>x^ z4C7q;rQrILp2+oF^KQ16I6~Ur;bg9tgPp_G4|Wb$KiEASwf2aWSAbn7#6is0&IW%C z9d0CXyg79*amHOaQg}?alGu#F%ArLGy z;`3XTw`lw`OfJ;8vaByGWbf*sLtxBl(IxwE6}q)B)-kH^X}z_BS{~-F5MvapQjEiA zLtnpzS)UeLX%I$aSVo%f6si|>qH(WTQ#20eZqpHsV{kQ|9F3Fk63REy^~yWJ*onqn z8jptfjhxE6U1~J$Hu-0`;GYtWr$bb5k{?)7H13p`6OEfM`8``i<1P*MtbrJZN8@e= z@lINr_`i3RMwNHtuNtE9oNnhv&C&S2YcHIC*ZGwSPIf0pqrT2xue5SwC>T4@7>XCJ zksDSthDFtA1P%VFHTb7QV`P*H>g&wu#M~IlAWqoMjnhY8b(@IBP*YZx;4ge~4lCub zsD)X%u?D#jG#HjPHzw3JHx72XxGth`oC+HFlB3Zm#9uG9qVYsnjmC(e8Vz>1>C6;% zxH+G>r$!^>qJl;t0je|QiLiw^xv^mJ!iPjOMg(Q06Ak;^(~3qZazmVZrj16pwz<*f zpZCiUjT2Ph4kSmTiNRm5wW2W&`a8KX-cX}4A*4oQqRu~=2qH>ujPg@K6T>2>tQ+H^ z7Uo3bozd-n6ww$j8z?hnLda@hMWfuL%85F|(ne!iZF6Ic=kz6r#&1+`YA`t(r$zbe z#a1+)Pl(3!glNo2h{jArV|JAJr$l3Phzd@#Ks7g>mzWcc%&&Zxi)c(Y&I_R8jc{$FvB6*eYeeIBDrgo?jz)8nzg}%cW4Wp3#)_z#8(7zsnG!*4 zUhp&jlxU1~Q9*N4fNC_@B}x#s*NuYS-{YPB?pPyML}jHDjg^LlSM5j7fBSW}#JV{MRs-WL8T(HQ5af?Vb^ zlUkW66*wJ9ipF~buY6iWqcS2ZooH0ag~p0T)S$|>e0@n9jpu8d8|{CZ@*bk`CtQss zM*}xR?Dcvp8e5S6&bqPHuSVl-O^wDj7ypDYCu#3D#)qiDz9CYg!A=a4qH+JA+*3p} zw)$nI6OFeu3$voJ3AwS2LFsej`P$}2Pv5%N5RJd!YCJg_E&S}`1u`1%Lw_e4A0%8; zJ`AYQ*zMz=sfK?_ZcK<$K?^^yq}+I4O6{y0r!~18ALC;)7gd@yM`LPjXUg4k&wL8e_=gHw`jVs3 zD#SkRFLUEiLNpF1MC1E}X#9X^eB>9z?PwI6RM09UKy}?XR6QDVHa`ENh{oX*(fB?o z8k0j*`9saom{Hr@`1OK;T@a0bso+|(-0Dm@ftSCSoM)hd?D#sgFmWeavgj;sPXG;E*C{><_Gc5f~scmjN{nOUL zE>~R_6|@N^N26VoeWQaFjVhO^M5Bt-D{NH;;$~k{s_KOJ$CBWmvu=1RH7aNqWlkr| z6m)B0PBa!zy{sM24U8fy?NtIh`1d22yG#8m+GH zvRXu=0oObsH!zm$MC8U)KUFn~Ff45}rq(tZ|NL{J6w%0_f}%)rG%j?pZ|#uL$VrGs zPC_(13DGzM(fEM5r$%FgP6ZcQpw%V2qp!-T9*v3Zd}3!_m6IYGo}_3@3sKb>HAiDs zZKE+}>``1(@Fn;K7sisKak0j}r$k2M?1X5Xoe+(d3DGD-G-A=DXuM@o!Nr;Y)o7eu zJsLfJ`=~_Z#@Q*N(K0C-&m*LTHAmxx+O8XsOYW?XXw-$P@#JV+>Sy1~BBS90V`rwc zkEk=HD6Gzu^Mm|jiD0hGl+6YeT7b(=k)d z4>Bz6Oqo^NXiR-|9{Q=9Nd+C<$_w}t=9(ww#x()iiO7waQL4Ju$FQ`yF}t?WC^oLT4biAa1)T%Q(dc5Z z^G!KZdL~4pS3)#;Cq$!5O$_Xq;i`XG(2zW7@{0{~#JCQ^B>7b^;@?&R|CE_hirl!K`J6OU9y2Y>iN<@ko{BG$V9|IyDl476=o5y8S*z%kI#rDb zF)VE~UaW027R=1;g=m}tS7XW1xKU&0n=%?>p}!N2v2isw#>LcVjF0edYk_}CG|EjX zxKU$HC$1Y~rPNL|4*vyTcr?ax%@cEDTugQ%a-)ljs>VkcmOdJ_ohc*rjB^l;`fxR# z9F3lScD^a25l)CkI3XI(Cq!d9qH$hS_-xM<9A6gn^b64HlJ7;s)uYiQw*kJwgXKmz zMKqpIj)p;1(`$~#+}cKCL94gR5RC>@(94}14Lnc7`KFAr0MCKg|E>c5alr)R}_Bcb+a)RYcWjR2ux-iV~xN(fAsfW_GGZ1Ae89EeMB^3F{^H*KBy9{YqB8%0*~aoG2nVl3GSAI-Z>CydCjw9$CE zwz)B`O^dS-jV4rZcO*F)_u}qrE52~*G@bGPE+HC+5~6V^AsUAfjS0*>H5zj?D!A7I z)o6TIJsOLfow-p&<4}rd97>ADPK~M#*Bp%nwatxABW5&3G){%9vE*pnukkPUv7+${ z=FOsz_5McHF{~SBo7OY>s$a2gIJt2g>&94rQZ!!Fso?(qN7|KuH&OKO{7NZ^2ob14 zRoFBsO1**y2m*#f1VxND9-pqa;uQtKgHNL%DxyY2@x&GHJ6?!T+C@c0+7b{Im16}& zMAV>wh=~7puAND2`tSGH=kbw!=h%7Q_cyb%vzu8kvRd|N0drDPVitPl<+GnWogiWDQ5;WD=Qw;-JjRT{dFyFu^inEAX zWRGN{D9$A@smAAs4NL^^S5S?onmTT*uByBaYV1j&(eZpW#yEU)FR4ZtjI|n(l&MBV z!c?Pcob7!q+N@^gU8Xw}8siAiR3og&X*GV?_WM&pjRIjvVfsRcLpKq)VBq`cBrbm$FPEGJk`{ma`VKUF4X8m zp&L{AYK-&v=5A7rBXiW~lcPr895wnvjnSx;wb@tWDT_kmJOP?&_$$XcHoBjLFPQP3 z(#Mho3^n>P$WUXsOI3Y6h80xf>88epwf3u#P@{}O|4rwskp#y(W3uU0$Kh;eWl!nyv`1B^1zE)f)p(|L;uqE&X*RO7r1+Z0g{_hX~pqtL{d08KT{Rphi9hnHWD zO*z>$#pWz?)v#sFN{weNsyZ*jDlVvo)6|}l?(@;XP-7no-4V=J<1U-;t}kO_q-&~i zdCq*}ilnK=l{VWHQV{pmSnN>fE?a=68Y5kaX*KE|{`&@@#^sJm)IH^jq{PG(w##!i zRb6Q_te_gtH8nOao3ecY)aXp1Nzr^YCWGUDT{Ujp0RMGt+?X@pxG8O_F)qb6#T0G! z)mUm#XmV13rW!XWtF;=P4jP6x7FcZD$UV=Ejhm#-DmI>XsA^n_Ra{VwXPX)u75#SE z7ix5&&^_^dHSTlx7ZhY{+@7Px#2hv5$Wh}?s4+7ti2G`Mfu3@oBS2G)+p`kWY7ER) zy)D$3m{Ey3HttBPO89)E%L`EL&J@E6s_|S?)p+gZUp7Du7>DgM^JeB)_hR3SkZMe^ z%-DD!V2+{>cxG(i=@&Ld6>av__{yfx6jy+z8dEHZX*JF`;y~}<@CQXJKAqqW^%2(q-a2(^0qEFyR_mt_bsm7CzsfLqe zo5G4V`)Yg>qtJt%08KTpN{2s2_*IYn55GZ(&TflmZA^{nu1eIg@uVX$sm99=RXIt9 z6;$K-rpCqvTSu@_w46c@rSsKzB*4B4qGIF8sHw(#IoFi;(2Jfy6!F-tniF7~;e21^MPMs1Y@q8XLd% zxVszF2&1W)d^H}o_z#R^Pnn-HZhVw8ZhV|GZhV4qBQ4wP$HsD(LXTUl(Yb2OSLAeT zEQtnx7HWKykp&DjK2EDjgc`3|RP{-UVFhF3g{G=;&43msL5&ESn$1_^$r%4$j#OiD zjv7mH)c7n%jio8JIX`Qk5gQ*vjVEIQG-G4&Kh+r5I+PS@ENMWE&+^n58l|eGjjQok zQ+rBXa_BQqqk=+CFkg)sHve9bRAVI~MUNY+az@crp4n48mwlW-5cgvP%a@@U_CM8F zX-Q1ShPAzCsZe7TOJl)g#KtO5VshLVigCkp8CEbhUTSJ=47#HCeo&(;g`SS)tMP1- zt#7Jv;|DO-YHY|EMSpZmH8!GLbBndlhz%@XhMr9d(2R{AJc(&F#$R~Z%R-F}u1eIS z=#P%Xq#DP@sA^-9VFlHAv8k~!aQMfkLXCYX^jth&jTgXiLQJW#C1I+uHEv#0evg`J zYzwlFQ?T|KYScLtdchH(sm7Ls#Izb+?M-6MylQJ)C2BQ(kE%+}YV1d$7ZdqvyzKI?V2PeGmrOP07MW_yZDy)57f)yKaSqXDzo%qu3cc(K z&`<-_N=&QKdFiwGl^?DtIEza3)xfz_B|?qkl7urdte_e%HdT#QkrVEN8r>-LN-AHC z*F65+FR8|EIcl`YQKM~+8bPQL$cQ%kYGC;?^qMC?Q;ppc64PqDbNy9&2{qcpRiaj- zZB$hv)EH*b++dJl1=V<^scJl59k~>0R8r{mbiNvI2KblGq#B*jZ~Sp%ZduakDRcL- zjh-@h?-=_yi)gd229_^FZ%WWqqmv^t8uN{QsYkX7HOi7IQLC|+EipN6408!*WLQBp zUT*5R@p>xgLXG{=)J(n_?^yiXZc>d3FxF~xjhSlfi=5A>+1K3tF#Fn(W$iP@jb#>v z-mwH|s!?G}OvlDcYptb1jjl13sMXlll9*KEc!zLC_E%7iSDLCu$97#eL5%~@)NH;Q zvts;fc2bRK)>NarIp3IjNZM56P|Uvmv{?HLHL!dcniUhEsYX=FX2iyTQ@)!j)aag( z1@sjb=Teo3o-#Z}a}P~1te_g`q3S*JOB;R9JTdix6QIU{6vA9v+_k9>kA~O`ds&h< zGeC2X%$m{ACu2N^p4&IgKSF^P@t=b~V&fm|ha;$h{jmvye;2a%3-2@&T#xjH;LfvO zyUy*S_)F(sw+XegN(yt;qeA0cpBUq`0oQ}jEH9ty+zk5_iQ+ogHn|>ysCW+7R<8cs zAr}9{2B(F6Y6RCwNeazXP1jsIzvg``xDK`%2Y=?ox%!Ksl55%{)Xwr1&4*ulBDIw@Vzk#eH3HO%;DN+-TK*r>qRUrkLyLA#3a|Z z9h!Tw%do;+n;OH@uexarxE?~GkF9*J3xe#|8;a}IQPbB1<}JFvCbIm~HfWLI>wQTI zEeNt^=5W0&eLTKTHXQx%>ZnT8F`Q5ZB-eM4FOg;W3UYm;saz-bIPgJmJrvDSS0%r{ zF7()MGZfbwa;`%+;yR?c-jw1W?%}k2U+)i4XrafNnZxy}rOzBIxZaRaiJI$;X^Ba$ z?;?h8N-?Y;*H@d$^^}QkbOYDJC{*j_`&yr7zr0Xf$LDaJki+$MaD6TzTIqA05~EPP zYPueW?^-z@?^QEj$7dujaed|E@B~#ra-HSS+}l%)a(%O@{k6mO&)o^Ghf`=#Dxd4( zB>P>3;(BkwjN$v@rmv|e|L78$WW?|TNeV4aDmwo4^~TO`{35vCn^1|`*ZblUlU(0} zCaEaH3i|qHQ+*x$(8G1$+Jiz%?0l|EOmJTxQ3WK|ITp=*G|KW7sy?lU&S3UYm;sWE)otovDiJ%U2Z0{L9O%JPq&Nv^M;zxunR%zYL8^%?(; z;k6X|9GGaO@9WbZg}%xP(BOK_@M(B5j`x}8zLHUin(M1lG4)JmE@Jq#6w6nT>)TEB zb=T-?hl6V`3Vof)=epeGpLUa6UyYeuKMtB)KZ&uAor#wFT%WZlwA>Y-!8Lisi_-RnxgE7{o5f z(${$o&0XO!te~%tHI?h0kFMPnT>DUHO)Q`5cNkq~`q!LwDU<8>36tykIQtAAYmsry zdBLO5cM>#W_}EhpXfL>~^G(;jelHbMT;E53T_10h>#U~6@T4gpjt1Ah6j~R|=ej{nIgh-H~LUP|V}{vO^*9`fg5ty`}uf&VuW9R|%ng z{nL?{jN$o+;T=ha6^!Bcn#%Qy;^S(-^(YGcn9k?=lfyrUDY#Y_XAQ2^%`*nq>XJ13 zK%{7;-(T@4FZ7cmKqH1%I0ww-Tv4M+^tqy5iAk;>d4$>-R*>tvO^xB@>xcgWt}zPz zoXqE%O|a*B(%0&?W(-#c%^0rU9WnfnY`M?%HH$*ogreim5kE|NNX8T>Ig6jYZ zZMO2cZVj?kB*it7Fu7L5O|D&|YI&{5 zI=JNet4q~gqpXsGTxU0x>n|VmSOu;F(X4Df*KHnKMN(W3%Heu&4%aBSUg8Q`zOPs+ z3T^WQXmI^&U5oPt*Ml11dT<`s_3$;?IM;WZ8pCB9hV%v3K@|GK&FA_jMx2-Z815A` zeeIPseeIoLAB4!`ilw5^pXq;aJ#_T5*xQQ5aIc_B)G^#ED>3Qo_W`Qzoncr(U#ptx zYwPsxW5M-k3hhYcbKQw6$x8|4>%bhY19P|z0@sl-(MsRfw;c-YObXEObpNFG-# z6`_iMaD6s7qKDvmd`u;3Ux!-~lfJG+44=TD!oJRJD%buKZ+jD5kD>CSXg=3si>)Fl zUr$e)Tt}o#u4g3J$6Z*9jIjwzMdiho01aO!{Mwm+KZ~kQPpd@Dbwo;HlIv>3@EHk) z6^!9IO^xBjGlpIWu0yE2c_5!_NtUf5DX!;Z?qA`_d3yB)aPm2|?q7X@$38+NTIt8| zEQiWVvH~=?mfTtYk?{3=OC@Tq7chujha^`IzFy!ltRUCwruuqs?BS!pbtsj$$mDa~ z#bv8Vit81aBWkW!IwsevlI-(KtVM>eSSl*tMS=#`Ef0OsM{vEuPt;tmbWn-GbybY2 zuSznkAlJD~^))ng$xv`TmdaZ>`CMD4_=m~m9C1tz*ReTVuLsv_W2{96*EtrIw^kv^ zDuG*AgBiYI_p=1oF|H_KtT$DUbtEQzU5OaJKFP3xT&tVPb(j5yEdkf#sC>6XKG(K3 z|LnTtn#`K>;af5CKI6(rtG+GGHYsNNYioA8a%15O5tv<-u4!*LG3bUcRsUWY{W_ z^7W;h7=Ae?hF?Yu$9ankU*|bgzE6fVGso8lH#aX6Twk(OqW1M=2I&}P-}tD0*<)Bi zuFo`;YssaL{}){2RNgtA&((6+Dw5**cFOeiorLM@%sBf92y2nS^?i@ZEk}Tcub+8S zUld&5PN_uA^__&o#~o#h*tVBjHROTuxh&QuOru;cB0@~!wPWIHP;$XVv_5hh+)@dSV69@Hkab1wZbwLi-Pr>!nBx{l3>wJgGyT$})_Dt#dFo4FsLblS6;ZH0o-`|r>*D>7p+Dfr^QT0zrm8iM?Y)edW z4N&zjjd2ZZ-8UU*A-@Ijj*Wjzw5jEf>>uMXd*}bS$fg!U*sD*+@P7nyKCQc?dT3WD za4MA_;7SErsGSGkMOx(y|;++nM4=$MlP`oPQ^%1D9_zNj*NucZ7$iO0^jcba{ogZ)uJ zo9+;rEI`9_G+bf6>1e*feA7WfVVp+iH!K1bg>f=0h(JhTzUiQ)uxTDM6M+SC3gf18 zgFCqj6QUWw7o@98!B$4t`?uuRhr4DcP`r0EBGrs)T{rs)Sers+`_3!A0s-EHc05Bj#~ z>4)HGE#?QJryrVP-`-#v7^c4k0lOsyXqsMWD@>cde@tQ8^aCt~3Daj(|XIZA{X9rBv&-P5y|KoC-rRnG3=x%>_KNm-- z7IU(vU*(vlU!62fPuQmE*Tlqk&$v!C*IK6OqXMSsqde2}(ZXhF`gIO<&I}&yDomLE8P0K?!!T|7#3a>>@iAfg9WH^i$QK}b)cRKwxi{Y|IR~bn zMdk58zUimKAU2@$PE&Jx)HHo!&@_Ew)-?T&j5rde-q{s z*W4Yaj?07Unm##BolsU@)3GZ+r#sN^xdt`&CaKfyJn#+E*(B?9rVAHe_w?JN3VYi_ z8lPlM3@S{UK2cUkExGAD-yIp1kCWlpooR(>)9*?tY?`OeF)5)iZn{+p_CM-?Ia+7gQ ze0?=NBmaLW942)Sm8*To=$L^Wlw*@qfQfi z)8B&W3veV%e<#4UGGrPUrhn{G&0}1w+~HllZDscKCxW7|yyp~V#uO%c`X@Glio%SZ zo>G`L{Z${E=Alu%zSmhc9)O~!GlSC!g$dKY0)`hx@uy9HC_puD#T6z@f5@YncNip0 zuXp}cPhYgOIcBKE|Dp1;+-^CHN1c2nWlg3nx=n)zRmit z=;_Oo{3o!|^cA*g`pTGT`YOvb-9!I{&C>L5adcZ$nZ6oFA0h-qPhS&dn-4M#4AV0Z zW`ZxYHvKD4WHe3x+Ethy-oJ4aCQM)AQO)wC!nEltY=vpl)vOXhNz>gHQNwh%WzaC)ZHb(IPj`38h%YpAo!nMw!*qAolwrEtI$@aZ?iS}Z z3)9^;IJyOWn=j6|ZE;i+m8QGFB-<{KX<(TCHH4WbLD^__%Z7%FjE3oGzQX*T?zZ&H z3e%UnsGp6ZX(x&NFO8in= zm>x=qBd(BJ9yd)7M@`csLF(wmhkX7BD1F)BM7Y6#PNS*Gc| z1E%S{J#Mq?=||$|M&I;4IJ(|9yh->6-%tLJHHS_p%f=%~PiLW)Keq(bJj1y^$&~Vfq?iM{-P?zSbkR zkBNF;ydiu#Yx(*@0HE=J?P^VF8 zrh#EPX7BE?jsTVEo05cvD@>a{%vP8-{rH%|gz1>QyTdJo3DdJN0wINI(@*dercIB# z3KOO?gHLo6CQSd{CikQy!?fw^k?&+56Q*yl2&6?mnEuJX>*;$}^{a;I7gG5IFW>ZQ z(9`|dyL)Yd%Fc@^(?`Wk(?>^5)2|B}vv>EpER~&~R6Tu6#x#9w+BE(86t`KLenWyf z;hb`KzY#~*_@>{4@VGk5G%!rZ?A^U4B|v5RF9AZs6{bxe6<3%xeRNb|!gS2u-Rpu1 z6Q<({I|wOEn?5F^uxTC|#qQHxH55@xVLCJT`jpBiO#czs4GD&6(>FTg-soe(^q)L( zZ*oLFm_F0_=Y9JB(9^%)&~+tDzlh2)kms(wyN992j)Ps|ntmsG<(25MqNm^Gn5Iuk znx@}v8?$$Ja*WC@aFyxzSf=Us229iM^|;N_^!sphRa%*z!qJt!=~IH#>GCYoz%U)N zcQjdm%Jelca_@8%rcJ-gQJ6M;Qc_{Ubj;q}yKRLD(>J2N$uWg#)9CfZnvV02CfUr3950V>(lfa(9kn=_XMKb{TKFQM{>lKH0J3G<$V&7!Bz#GuWNL{FcILA%nG zx4G`Sa?s{#xw9~6^Ku?caoTj(OasGoHhaI*5}-1jVKajY)27eNDopqEcQXnTJ)M=El~$PO=?r@>r7&&!?1aLm zd1w?5qB(Je3DcRuRZ)cr(|-pxmt)%W1va_WJ|;}x2CT+rWm!)zUfIC#{y&)B_J~XI z+_(5rDu3M0H+^B&G`%)snqHSSO|MUhBVqcYg!ssj=;@ibI1;8Wj+&+~37V!a$x_GF zmg?!BWvJ7IQ8m0T#nJg$W%?HZ>U3UO=%=0p^Lz4zSpk}+*Jc!^O|O%Mjl~(aKBe*r z(_apdyC|VBVLHPyafNBq7e^H~%~Pf?2`Y@6Zn05fNmgOP^gkSOKg%#oo4(y6cd3sF z(|1_pe!;Sd;XP*mt84m-pZm{*>6cOYj99+u84SKpCsj{h1G|pGk?84bgb>(o{AepoaJFQ>N+b6Q=1u#JSC~r*FWK?VJ81hWB%P(>JE6(|^)T1GA?? zz>F(E+2}4oh_xoFFm3wUpu%)dUz=5!F#Qdb{Vt<0F}&|)69_3xoBn-DVbeTi`uc>z zL{Dc1{}5N0F#RuJ8#ty--|3P2W0K`#m@xhCEV&!g0>eZOcX|JKG4g+y$X&TMH3O!P zr1BT6eAC(M+D~E#7sLDZAe9ZmkuZIGR+?vnqx)yZG<`?fcwNfY_-M7hnv^m&A%vy|!cig0vBT52$_8HV@M9HxO``dbjte-m6Zx=SkvxIHK`%BJ(7 zcY9W0+Vnp&3KOQ!w8-7Tg=W`zVfrpO$6qOxPn*6op|EM5GX3wk!i4EC7!(!8O}9`p zh%(GK-71O^=qikxZZ&fWqy+}kyZt-UhjeIp08GD}%3llQnLe*=)_7fNUNA#t$Hb&^ z^L9@grq64aGEAS>K4H8rHLpXQ%7!FmPoGzmHBDcgHchXHahs*-T@%#lRIDrU6}fr) zderF@OPSs+MIHYNG7SvVXL*Ds3sCj+mNuc`3iEq9ny)b5bdXS(FntcnwofQbm|lW& zbcid=HyyMTHqBF}uTCpW4DZa~ikQNL>CJ(4O)yNGUJ|2u`+9(MPq$hmX4KZ@1?UF#QTDf6L1^y=TC9U20xWkIGI)$aCf99f6_WpUBPY<(Q`TP8zRE%{$Vj zvZ1ary-&{ zr0Jb^IKX5^qoClL`~2HwSj4tuSqRpP0g?dD3){Qy^p`S_H>wj6_wXGd8W_1z%yp=^DcCa+55bU9MklRlcwpH z*s`352F|-QCXTp5^DeVY(?bTBg z8W^VIb_z`vpz7%iyU4C;7{0m4V8c5QMbhz)N~h>tZ@R=j7olWsAQ#c z|F&EAqVi9n`qC5?pJS<{;&YuVul)_bqpnR+t4N%RadKIz_Z@z1yxyi(`(}}3 z`$^|HQ`)5PYtBrRTJ4`9!Zaj665|w|M;lH?|CmeNZYHy!aYxSk_Wk}kTrK07$ zj<0MAwnY(#_MH=&oSjqK zw4`#}9d$f0NkzYSDye9V-Fo(}KU4X4_}ScqG?gsXr83qB%Tv9md|ie*o{*-ZpLMCV z-m*bmx={IghuTlKa4t(#SW@dm4jTzMHYBLy@gB})tE8eEZKwDB&r|uvB(Y*9B!aD2nvR@vg@+^Acupkxvq)V;xo+%rTSb^;ArzGIBqs~=Q z?_4(dENm(98zSu37!_@_RZ`Kn_Ug^^@y6zs47E?$RPvc|F6X8Rt?;h??+$ew5=AL} zF3*nI#k){Bu1)PH!<5gAb6IU)S<#uw|3pj;w$Va;F3;PZcyUwl zoc#j<@Hco3N>Q_By3_{yt(R85OyK}{O-xeBSC(pg$zrQ`^VmBmTm)VNTxwSAsidOy z-c@T?^rCQairSAyskOS)7tTY^JId(bF+DsAx5RG=$3sI5bgGwn zPQ-m?Cxu&qS3eKuvQ<*i5B9OI-1iNITL-D_t>CrRQAs5$oT*cP{+PnMdDO8l{Q5(m zYqi%tvNJ^CwrOgcOjF5s`dq85W7}*kqwwzFb!3d173p)Ww?7y+{{afOPf=UE2vPE_ zF16AMT>INf3ge2|u~&kc1$3$Jy#W!N zu##+*RP?>={hA#|VJk^(@ocwbwJx>XdNMZlVG5VWspFw875%Nx^_@3<>bhAJj@Z-| z&wxu-JF3Ex<<4u@zi=9byGE&F_be6d)TP#VchCHzg2MZO*Vr_y)TLHAM?|gTDBLYW z9itY`WvdE{zO%pIc--j}-ru3NW5DY>UCOgMU(tO#g%1R;gW^<_)uqvfWCU30*~V<>zCt}A8WlZuYA=e+;)Llo{4pjPcrYOJ4Be3r9d=22%*xNnA9wZ^&5cT@|D&vYgYzdlOg zqa140GDaoea5?&?sr0e{j;sL08IYyYOF%5_*H}_!fB)JZ%_%%6N~M_ov>4>Ej7Q_> zB2>~{7c-il`5-@fe#* z&x3)7@S`E91m#Q0`O#31O3!hLj;-)CuFJgblh2d?XVM^7^QY~sIog+Af^oz zweRlz%8L{}3B^uDC5Q4#PKi+|{-Z;ACBREhMkQbJN>E)pFGJ0jS*%K&s@*E2{l?3o z8SR#5iF)uOw72v`m#8N{0+-S_&d}3i<-oJ_gaC5#BWO^1JaQh+kI=f(VaVBAH?z0b zLvr@hUF}Qt7d%L|AuWib}BzL49Qv>%YXI zQY=zYKVHeD9+eJqiDEo$q(!9zQAvM(bUAVkK+XX?=M~5qLr&3+u0l?%i&BiIU2Rio zzZezW#>*uz6@Mp9G>jizgJ$+cEq7bK?Bkt*n`8G<_?je@9*Iis(n%Anx1tLUpzyUQ z)jLKs$?;2#b%w-uct~=nv==J8ODEmx?0WrsH&b|2luCQLD5WdB#rb5vwslBysk8^q zb(>DQ)!KFX_#Y`eIz^?2qry9Ng-PqJ^FKe8!q-_;dMGNKU?e#o4C?zPlG0Rq2r68s zEA*V>C%m+o!ee68b}Is5tuD37IeBLF*GS4x+bz&WU#ZBmK3zHqgZ)^Hmz%Nez$7jk z`gGeUj;3>guSeQJ`04r+Jne=cwZ#zH@^Nv55wkn0yjeHoI;UeS&9qNO+hL>2+Xe6N!M9jt;GY71nmz*h5ywRjiB4IM*0m;V5hI`hK&K z`I_=j`AAF zSrXWMdMo4vqdqJnyN@d#-B8Zv`<&gWEmii#C8T#$y z9vJrMNw`Z~>an{wnG>@Hw71(9wCE6Zo}$hEd5Zo*3iG^$J>7WQ{k&dm+wEUkXXeVQt-_SjTP<=oQH**lEBc(=~T8D~>9 zm2+!Db+%vSO}T(7uX5Q`(9hXWo$cDTTzVaH!neIWm2*o&b?!dunc>e-<&{vW6U)fC z|K3oY!9DK%`zz!OviY#ec~nDnw*7Ydp5v+ViX@wFtDJu}l(WrgtN%WoDlgBn`MjUA zp|kH6ow8;-a@y>ELFL@hP@S#+ynf>!R5>!k?nnHb4b{2p$sg_3oVxvrI*a{w{?$;< zR*RBTzoc&20K1=3b^hE?&Rt@c?!6av`^jPVYbxiahH|$2e&&!bsN0VLc0Z_cX1xZY zuEk^9rp~5r>rv;HjLNyGp`0b*1J1mcx~)TPP_v*P_4pv#cUmJ;aypUJz}F0wg87yNKBlBEyLkN4C6F0?lea8xmPY_ zG)GZ*VJwek?a%;UwG%XJholUewL>hE=H#?V^D&pL?}=6^&DatkDiokW6V)p0U5`-$ zO;oNhO>?rWkR;8|<5c^Y%kpuWFFAo?;bzOhPJr$C6QE;GOZ#>%J84D*c#ftpP9W@5 zpV_HBF3MLR#nytg$7hXgp28W6uQQ4bifSKEuysb!IJNar`4=fd6#_K2v^q6@Kp9`c zM2#x(9gk7O+9m3hn5Y?nNvNG+xTFqW!Ar0s@y997wAeOJY(o zuGdj`G0vt!mrEJ`3~L6b+E{D1(URISIE=Mdu~l?!na8pCP=K;Zu0|Py_z3bU+Q&E0bhE!q6>99|szhH6oLOR0jTK3%-P>VUVKp3IjdvPV zBewB{7oo-&3NN+t)Tk{6f3}{&)d+tPG}VX+=cO9`1Ew1NJ+|sA+N?ea$ySL`p#Tjv zP_4xDwpd4uT>hOYGN35nP^Kd2IYHEPd` zs!D_!nCjq+3@fO{yIPG`8&#up>Ebt`#tjrk|H~aWYA?3=0|u!EmUXlm;Z^7jo3e82 zxY}JarW&o&?CFDOv)@xTBnTA>&{Sg;gL21>*;U_k7i#R9QHj19IJ3m$xUmuAM(Z@g z3aas*?kTTYjg6w4Hjg+2YTQU+&&g9GyxQVdMybXcQ;pg#Iciw0sYVD-aHh&O`)c6I zhzePwF;t2w*(e%b!=PL>ZkyO`j!?sLRidv3&MYyh#?Kg#LJq?Us`0K?_z@=BvUW#NeLFM=9)(y-3USL25$ ze+DMi=#e$m=!w3ed&&`MQ;lADkd)%>Ge*(hTnhgXWsS~NqeoU^dfbR_yK#b0;|L|6 zaZTx&QI!Zaw%|I`E5)#aYRuAVyxgc7t$XbL1Jw90g*OE9)%Y>VpY6$>ve7oxxGE<$ zuFi>#1Y%=yRJ7TTjo%##|Ckh@*;6*!64Ppo?09@csByI_V5o7GBMZpbz+=YRgw3$R zYUrNwN~1kx_LLd7K@BXp{$%B=@k@d~vy`!MLrzb*F-MJ?a?}_HHSWxcHv4M)iE-nX zga8dSYHx5Qrq!ry`TG{3#!X3;sC&wdj>M!Ie+8*_oXxO;YRuDWyxnMQ?Cf~nIH++8 zg|o4IHGWO;XR%U^iIy1~cLdCya))R3lsjGapq91I=qZ0=-1wCTbZ$?XXo-x*xH0MN zO@o9QcX%pMt8oW|cz5GHg*_Ioz0+k_K{Z^h#ygG1M&R+2-i8`U3jb#3tAT}Y_KaDo zaevOZF(qf*cpzuon93hOv-W8<*aPeEmb3uP*tlN?k)cML3-`cV9$#WSct8~}ddifH zszj(!oTA#PDTWnPW1b#2-fA>9A{Q?xhZ?t1cxy6W4L1A4vvZ-w!Uq#ZY%F{zZp6mI zX;C9K7Cszg57tGSRZn3L;=}&DQ&h>Wu&7pKG}PEMV-M^!1T|2vO7vp`XO@`gDeN&m z&d9KWYSif1c)QWq2%R#z5^CH=;Xj;wHU302^z)P&Goq#%PlNF$HTzolbk5a?GxcQ zf;=`}OG$ECjVV=^zAMy7$5o<^jn@+rlWO3#i-m7Q8CFn@xmu048dc-H)EYK!Oh8k; zJT)Rkh=wC$DmG^4s4*u;jj9|q>X3GeY_qS%?k=H1MMSGHJ0&r##+u&qKM`tF#Z{tK zV~(s@&c4{|Bn#^}R#1%^t;U;;sSU8^6%OfE`$HN zr+gJOW8M^pvW$9v7Cdyf@)M5YBV}-%$)sv7;4-_k+#WvHFnSN*TSS4 z^Mj@u^D#E~<3{aA8B>jq)9jrw(Plq3%HtH-JtIItXycC? zwVy$ovAlgoY;=uMq=QeyzoyhKj{ZZ9qko?DvQR_+6jH~=lAtUgV`IMn;f#%{G22k1 z(Vnto>av%i#@!Stb@SEeh-ipf(#YBsIpfC4fT_kx&s1ZT%ii%5ZT4dW?*v9V`b4xE zD=bM)$42P<$z6pSD?OE{)mX_OW8A<>OYJI`VFhCYPodNkgmj~^QDqlThZ>X7R4-qR zy$}rt#g!UAjTXZSslncjRF8~CdVzmFGCDDP;nxu19*XQ8kRqr@Mv;A7{_3Ud zAe-?+sx%&>u;HC*x4?GYCAK>3-AmRG{bdmL<|e8TprnmgFQ|62CoxU?{Db;`ENE}> z3y52>!)&VE>aYR@DK7KFA8)|RNkoHOpQ>+l3b@`&kuS9786|mc4VTklRard?F=i(wMuhc zth#!GT>D1bYyj8$C=yEKa}C@4Emz@dUCWHYwQd&-^}erlt)PkuXZ0vB+#^Vlu+5t3 zPm#jlii#wreO)#D{Tj{{^{N8gSN0qUwKJ?B*U$Zqj9(ix=If5zrq+XNiXssx%O3^$ zF^qAUy|yd4wvU@!J48*cr9t*!NVHOObtuv`DnP^6y7qC2X|7ki{nk-}YX`r8;JPMC zb)`X8pdilA6o48(tgUKcl$rgFflUaNR)|n6$442iRjD zK|yh4&)Fm07?$VjK90mR*Sm+G-cN8n$dZXNhSz1N?qCKL=K8sg;o3%hJutDjAGl6I zv%Gw+;K_clBYiyrd^Fc1Jdk$lM{599M>jU^n1r|%{ zj__onE|`CJdei`{tlLUJ9D6T<^@Vt5c@ zxZYwdGPvSBi^xHa08Op~;u6zbCm(PzzOBi)4veY-B8Kt&rfyJ>VFkG^)m-Zu<$Cyr zm1W>Ml_I!+<;8IK1b>%aavhcv!^bC0Ux(Z5fsAOSiebELNRjRd)pS0X^Ra1|BQedj zk{2x>l=;X0h@0e1FjEJ6RJ8 zBLXJZ5gvQo!dj$#Wxp+m940~2*V8SL(TL#%GuD0}xQ<|HEWl+9xR-J%jw$4wCD636tyjag*x>QT8x}waDPw8@~3GW}95kQ(kLd zD~jfA7hKPei&_*{JXxu`fY)4@tKn;-G2C)c@k!u14b95tbM58vpKnO6m*@1?D{}hl zmFTa7?L4l10u<@xsix}~zFg7KTqn#f7Ryt0S8!h1*FVu;uMDzE3UXbhxn>&m^$}~+ z)!_OtMS8pWT>IdqDEuBpa=i|HQjf#zC3t>+~yq zxO+g5;$y?d{apQDL2*(>6%Z5$WU20M9uoyAuGMya(P-#iIdK`g)I3I!fq{IkgR zPrQfKJ&@r)d}8qypt`APlk0;i_MAqv(&st|L((7#Dy~OI2^C2?I&>o+J)IC-r*d9? zH)RiP>K;t70tLCQ(_Fnqxz0SSZyRuZoFYeO^0^-4^51SrU!TBlCoYQdcmvnzuF3UD zhdqT66nw5nI}|y_6`;xW37OFd-TjaKV?V)lx?e!}ibpbaPdcoUf?U_?A!$XUT;H9r z`Dbu_f+9nle6Gi)_>a*f*XQA~=K4ZT48NFW&sbQCjBYv@z8=dhVK(vLV84p1dp;{N z8eCUw=z~w-vgy(b8JQ?9tL&GmbuXqFR*>s=+SgT$4oN=`DPmlwQ{*^A(I*}%^>1&E zx6LX4n+cQaTRB70+Zd9LjG?T-l~4JPw*_c&eKR339m6|^Y`sTteJidC2w(9yrS9!0 z!wPc!R&!n1DAyLT@y$T*Ns0`Q<#UZk%_)BsB3k=emvgD9$EBv1q@ZG$Px<4#nYq4J zxvc5HG}k{*aj=0m^R+G}6Q!@EHr0sQLmwU_RHA1Ll8OC@SG5m!mG0pY5Yo}}wT)%W>qMRDyQAi!;2>2_= z^;^yL%SL_O`sPy~fa_CemY2`<)Qmah_j3B{w>kZFHTr8$-Xf#FvMK+m8P?2Pu3lDR zn(N9XyABpyzx4}<7{-H+y47h`pdi;ZI)+y?%5}vK_8M3542qnV&gVM9F{k`L2Fw`# z(KE;4jV^m~At)$c`ILWzBS6#F9~qPz!wcR&ZoJ_7qbCz(4C66I-A0#T1-Y))T$eY> zwdm`gCxPqJ6geZA&-JW?IpyDyG`ViIO|HMk*mDWiBEwfUFK@KJ?*DMvQQ-OvMb3`rb3G?!PWk`N7+mWE=3Jtl zFqi0_6|MArWmEohcr$Zj`0tF!XpBv7_E@tI_Z9WZMCohSD4}+S738{3b6wRa*R}_w zLg4x=Mb5SIxtZX` z1lLxa7ZXSLiU$m+ofRm^^*hbgYcz%*XtU2uaD5KV%I0&uz%!=&_3h1TPJIW*khWNlMY1Y4Lv;7L# zA0L`D%~cXKXrfw?(V&US6~<|@hsgCIS7MST=CC*s!x+tyh0Z@|20Y)*8E>Z}p!p(2 zE{ANNcqrz(`9_fM^B~-;PY3yy7((>=RSw^5LAr_MZob*V90#YYe+k|m5JOESP27mp zzY!FmqKW4*s8(U`dMFSc>Jchen4o!V96_t{Nt$>dgcGrRoaUGRq}g((ruo7ik6a9z zFHz(wE1%|Obi_+s*{1rff_i z8t;D{8rYw2gNH{m=%*!H*dTk6EkBbo-lLX3*@2wz(m(Uc!QX-ED-;=ROR8$;;`*8B zb*D$=u4nZ(*y8AI4-D#WjESRZHaofr#97W-o;EJPUxgC;^VN^@_-kU~Gb#1|b@|Ov z%V|94%?`hP5Fa_LzXfqok(67t)hE$4Fo6+Uwbg%?`!mi#&+LA zlLaUn&9NJ7h4H3y?8cbFI025`WGRf(V7m>~k7E!{g8DrCpY2-&LJFH{17kOAprtTQ zjNRDO-|Q$X?Xj{qdjyIKd%|WI7SlnLVYrS6s^Q__@mW@3r5?+7LY6>UU>J0}d;i>@ zZ)3jc!hL4?MlaX&H(t2vYMA~iMPQ>Ct$fpO$@0zA#P+rI>`tbqBR6HN{|Z~FWKwc- z>iVy3F?~+wz6|8Ky5m!Yy1ZZjy~ewyP5wE;7odv#T4LuP|;pzcPMpD@>Tq zhW(#X3KOPd!U{qP!+G-oUa^g$dJ{!JC2#6Q-Y(0G4H#HXStUfAuk8 zI)ngekq@RH)`00h6gK@QFW2;&E`9qpnEo0?l2*Ryi_k0EVTv)^29Np-dL`D6#rCW9 zi($HlG||(S*nDpt+0$>0@u`^X>9^sUy*#T-A0LqAJXR;dknPDMO`qU$o2BWu31LmPGAxkrn9}6>KC~Jl#OPaFrncJ<2@Ze*d{bzVZ!tgF{)o;D@>Sv zltcBm#uO$@$Iw%Mo24*eI;(FygZPLr&BOoMWvA`$Iu2R%ndXkmp*Ytr6 z^z{GXnto;K&Ie$6nj&|5`KIrTO7m=H9($pkg#cHs{^6K3kEcC|p`WFR;eD#he}*Z0 z`b>-eL{(hV7X{haepCZJ{eQToPk6M;M=<>j zirnw!nZBq3R$iKx`Yr036IAJ{cHN7{bBl^_!>?>XhDk(5H?HG55&`qVcc|fO-J(;CWiN(Q345taT@%NwVS0dVfyb5fsn$)@Q!QxqDoI;+;nzL z2RVfa)0x2sI0_S{UzDLm2XaiCehJQTP=@7Wm@xfPj}}2Aj=}U^4VeBvT+=U4Kkx}m zf0H7QX7Wt0Uj!@tYx<%?JmZ?a2vakCO<#1FV_wsvj(JV*o;0uNhuG#d{m__sO+O65 z0-NRVj<*fio^^8e-UCMilm_)ZG1$jkrhztHT+?F$l%}(5IvTDpVfyI-Lh}{oU(-QC zVZwBFO^^DRzNU9is(dqTG=R?$4#B@zW8@5#U(*kbDNL9SgX<5o6edg`X;J;*9Mh&> zj`Q~LF=6@@9)UC~%ZGP7%KOI`GyaEb`s?fN-Up_?MG+^RZ~8!S#g!AeL2+|<#{)Ay zpmWXY2g{+Kt5rWZE7G`5^~Yqy5m%^wNLrTjpi%wM6hD&J^kWm;W@-9yI6BHVeHe}~ zn~~S_;~lmcA=5yc&aa~b69QB{on7Y#aj}>odU!vYcN=b!jY@dg!9i7)(-2rzVWOwA z`i{vcj8o$IhNKlX%~SOaO({&6&I~>_p)g@ORzB*FbVq|g-t?#$0ozK>ZDujq3e&bDKZ;_&~|K)yW9(aSXI#2k2_M8 zrqaDI?6mibmF#prsGol#MdoIy-8PR}R&%XtTxyHA_F7i)O6J9=?a_$6YJT*7lG+Z= zP|F&g^8@4@;!um8ew8hH*uSl|7Eokd}>i?$7En@Z|zKv^owV|J%l27_E)-REUuF(mmj3Z=KXLIwaUVM3H)jN;{y!fx5yzQD?uePN2vlG_gG@JVGZOmLA=4$PU6b zK2+Kc6&|H4?3+F(bt1f2f>J>@u(g*?>JgoC=Vz4^S&DPD#kuqVWte$PBMn3EOp-@H#d))Ov=E{$i<&%?`F} zmmm5zMShG?>t+@;8*C(bc5!SoMScp>t~;>Pau+Xv;QIyQ6rsWU@uRFwr5HD9Uw*X7 zp$>n$)S?eR`ZY)$b|$g0vpDjo!(Y%K%#SwP)L{qK9n1OA7L?l#>8|FTbt}sK0r{`t z!M+vcwn6c0c-l6LI&5_VTd(D5f1unJlpD>{wj<|e;Q+}Jgvx~_Q4=L;Azb~YWJB#E$-rJ%~9?r z@VkqrHBV88jWLwtMsebWN^rg((Xz4psD(!zen88{@S|N&%lagaSUW3P zA?NqVIf|$4ik#me=e0a-H{@K4oC%)R#-H#paA`dqhKd!B#&LsZehrVd}D!aH?^N$cj*T5P0>(kOLUh6*Pb zNzQJY2i}S#mpXij3fJihJ*R5$rO#2t9vJGjX7l#k-Er^zmm_nG*vw)M8syVyI>qQ|>s9T@++j2ZGJya%wYFe^Hx z6gJ&v?Y=k*%u?7Sk71YC=vQfpiGEgjNrv?`hJl|LA}jkNUkQWQIm7^4ITZCZ^AyI1 z;L2j0x5!Z#AEYZw;%uOnn7FuAUK*pw29*!jM%EUrOyKG$^NC4OWgPhy#3hCq7R%S% zV{~$j;FM z*xW3`z*o#E+4h~7SIT^10$qta9ZaG{K3oa9r`hYh*dZ~n^`Nwvxa++=o9PFO_dT?B zL?BQ+lPcKM^@SKJP|pdMbjI8v5|a-*m+bAb*}Hsby<{&Og_7c_AT25L*z8?C5Bv;6 zASUdrDf($RyA?o%0+dy<8v<0Tuy;KaV7CRRTw#yc48zRc}Xh?(9#uHyTt$L|@$ z^Wr64Ty~qF__hhK+XU7WgD-APmMnAysQBWZ1l1}`@O>*zOFs1!Civnm1gDUg(W}Amon#6GDgDM25h~bt86)8**!;KHBQy3#={-JY7Vz}?YiC7vZ z*7KjlT5i|zYLAFa1F`q0VyKnx-vm$GGYS7D;EH-Q+!Vwn;3CTInYh58VFttQnM4bg zJe1(KNoaxLA8x>wOz>EtTF=tBF}zN8FN=C5Cb_bK>5e4B3UbB$t>W6RQLg=$p0pEO ztEl2cJD=;x7*F<$@n(YEy@)`~^*)Rsn(GHR!o4&846eA>t~fa^K!fY8!+L}T*Ly9M zsJY(9AjV&E#a;Q54>(qkEAFoq*S?K%Juq?mWN@8J6{ke=xt<2^+65HX%c3UNkwKH| z$Sl8i=dHwrNBFupKozH1tevdyA{MK|eCf@)hKY zRRP7dPorE12cL%Y#nn`S#a@3n<&CWv0S0Z8itDJH7#`)BTt~Zn#eviExh{1GRVX?> z*NfIp`%7>g#nQMCn(HV}V$xTvWh@!(GOQriSk&j*H`-W#r9RVe%HkTTI3ttK^(-)G z?JBPSbxdDxPMTad{2yuG0xwh5{y*z*E^g-x4k5A0nK{Fxsk{=>gj7O9Dyg)SS1M`3 ztCGvOCYPF|LbshLsinDd7gE7)?RB5qP*++aTwtB3$wCY3q=-Q?uwn;h-*@mv zbyzLG7FO%mNB8`54zQwY-KM2t9TKJO9EtT;WLj2#{Vib#@7?XX3KZ!upqH&u2&7OVK2K{B;7Nfg`AotP$8a*WO$74 z^cl0~3t=0QeJ>&=&x?}|HY8B2V0cUrZAhLOKkb0<(+er_M+?>$tBXIrD=&T0S2xBL z#}&;te>dI*B&Dq2?z4P?8G^61#foOBh(BS?eajGkElFoP5-3(+O#2rV%ZjPcoY7=8edEbccn^3j=>03IJtjIc~T@_JD%>biU0hF462;qw<|q zV$nK^$RoYr5wX8S6v^gGR5GaUvSf!#6=_rF(gJyNHI}?ZhEda;3 zn`piiUF=&_SQ|7d7=ihn#`e9*g`_pYrMe8vj7zF@=QHbez71>aU_v4Sz0 zAli^@-rf(7&}ag?P)3~Llea(%aL=YglGRGDzKdP9=3R94n(wiKvCtR0FjHBVE=+RX|cQjBnvsr$Z8alX%D z>`+{Wk&#s0pu=(dI%DhopSawU=o047TA>_Ye^DYX_E9>;L8JIHa@wQ{)S9GmQEh(F zNSvfCQt6xZL0u!KU8S<}E@3J`PRpM$r2?y!WdYl)P0RwY_gTUCpaBfd<(loo{x&`I zF@Rl<2Ml=VV*u+H6WdUv2P^mwM%u(ImN0rLY^5Q(J1yggxud0RpRE!Sq>Ep~5~qvP7V zIa#B}dqOK28g0mPw> zkfd=@+<$jS5Ij7nTz;(Hh+UrYhq*lNzd{H9wNT6*!Y5nTxD3EPWCb(hslX<Ln_v*_z#feXMx$eM@3dDXjXY-mSimqul}`&%8TVL+fVH)4 zWU|&)@86c|R(DOF0Kx<-cwA43(DESGUD&V|9kKih#OogsL#^^FRCi#qEe#8pq*(OguzLq}_wc{O!@zuh6CGehtEx1DaZor6Y;T@&$ zGYwEB1@8k3to%w<(oDQ)!k`&=kt&yuQi#U!c8XbetMl*1VXKyt_1h@&l@*;O(oEe%7=}c>9JWP2fER z9DRwz`Aod!S0xOZffw5#<-0VZ3IAGnJ64DHQ~jKMz+27=o=&9V-BShc9=9Fu`$0PH zVB!tf@s33Q#rYU~QtE903 z#dAdmwiI|PSiy5jD&AX-Ifc)9<+sA4Ry+?5(18w#cYtQcTbAIbh@eUe-dhuf&bD~I zl}Ox|0`DI>D<3Se8C#Xqe+Os=pMe+Km*r(#9>o1eAfFw7a1#;bp;hR!y;!=jQV@Sagv`CV~Iv;2EA z$7YSsdo@=6hnx5WUdz87tMhM0VD(Jk-OmbMjHlxLNU`_dM9hvifq4EUBJmEd;$OVG zoKB?Slj7fx6hXAdb0Q{b8+24?^OwrX6G2I{@DA4un&Dq;#h1%hmSY9c&0z)ck8V!1 z&xX1j0?bcX!7J`mn4e+IK+hOO7#~D%((^~IP5DO&e%eUHS@~~O+#q{7up%Oof%7h*Mp-m1QZ_uO~(>O&$l#1FT?a zz<_Bklyrq3l`>#{2AFPu=Gv719HvciIlrDl-~B5{ZCd`LlUC)rB8bv|*xfJxOe!oy z(TP5YlY9is{;}c}E6Vay0V*S48O_wQSAeIiWyCSp>ni~4Q&#YL$N+}DL@})%3)#a| z7u`~rul&aVZ3$5;78H7tU4ASih!P4-C3;lSHt6)t`atb!)_mA1LPNyOebnk~D79)@ zq4?bk+7duH$O=}54Ja~t%4b5|hCvyMGcXUrWS;|BodXRKg#l!=9b>9MzsZ4lApzKipx`UaHDB=tDava}1%@v!o@H9?e6u+vfg zU0l*O==9C{RPQnLzKYBwaTAp6hG#>m)k-r5kL31(CjjMhRuGG&LRlrA)f>I)9XEfD zZ$POTq2q|uip?u{B455r6+{VTGXm%xx1{|~Q0UBKMa>A+B`8_{C}(-a4&}G3n_mT# zFId4_i4-UmO?3V|-hi?SV;!E=8&ED&=qx3*VuMl=XQ(8I5=wCd@Dh^tzd^x)&5Fwu zs>{7nUq2g4OU3kxK4NMipd4Za$fHvNY+I6__ZCnpnuhFNX{FIYP-?{ng}kyYDTopZ zyn?Ed_P;@?p|grs8r3Bz87&* z3mBMWcdjUK+lIM{HW5MlHxxSVhM$@o~Ht$4tDJREIaQpxqAO{fZUDBdK`Xg+%hs$GeKQ zy4YjlYE^h(3z~?zLKPicwu!i6C>B{i1cl1dc(lb*(Jmy25-+w`AXd`2U^u|}IVM{W!-h#*C*`HK2rPEgVWF!WW3lQaTm|Ddh`EQ>cpW!#ZtV`pEl z`ktPyT&)@}!od1o+?}4Lvz+6qtI8WOdMq6KCV(Gd1v`=kaQSkCin>95p+sD-s;H-k zzt-yn70aqd=emr0@)fzd_=_?-R*@GMaj}{I<<|J#vA9TC(ZIz|+2=gR%Nh!q;(Ap@ zKH_4(yi-@vNTn0%#+|x~#t}N9Zd|V_e;#GuL|ph-*Q@CM3se?F<9ZdR)l(#mtIlb; zMB)y4PQ|~1rb`-!!6Py+E@>PL?Os>7HA#C%rMlSk11w47z_`4IiloJK@X?`ZK$Nr> zRib4<9z7u-XBtoovULWylGaEkzFJr*Jg*8GMyrPcXFL5kJ-+$xoW80FZ8_IG$_n<# zXqQeee?2I=@n&$a^5u$f9=BZi3YXzLUbdo&(>uGw;3u5kS+_gAOWf}Ct{M*(!|9ht zxSPeDx{7WpT{e(Tzaq-BF>$A^A_ytJ#$EW>oKCy2uLlKDIvq}e;*utuPCK($YU4w_ z&~$qF3SH8K(`nf4OeD@{IlZ$kX_nKw#3jvgdRI--gwx5vmq#Q`IK4J#-BhBPPH%(! zu;PlSq;aRWIioOu7Bo2h-v67^w_d#F8aVxHRKSo55bif3B;A@ivAIs)618`d1uJhI&4|dA2S}t3&ZI*parcJuo*FoMnLGzaum$S~wgt~BqN{fNYArqiLmq?t|!2uTx8r}-nKNt)&K{t-zt zoeo%%W;wloQqqLe$-y@eiR&VqUPosY0|P{}oc;%BH>#2*oQ{pJiksbn2B(ktzd8NL zu>n)z^kb~xKs43q<8`q>5l(+JZg=_w&F=Jx5xdhTsbVR^?Nl*2Xmff+M6o-4ip%cw zDLQwv;qu5we9a9tSn;K4^j=xTk3G7a%#m{(M5baKXG%jhD(W;uOgMAC%Q zksnq}QYDRp;XyPxC~2nC0ZY;>r%xdgcd&3eIe3aLX~OB4Gb^TYn&tFUpiMJr!s(T$ zJKdmBPj{HpzfC{9f3H`a)4%hC=D_L4S;3+3Sx$%ZvVw;FD&_~pxqEK8il-IfW^S{J z1;Tma

    • 8#h+Y!qKN!=&E# zR`2`r{`xA$SaSRRj3sx!A@vwb?s|i<1mDCEOHi({B*PGM?mme1@Lg8Vuw?Z^Np22o z{pe^UB3(X#9xsW?5)r=Tq(h>p2S1b3xDUy zj+pTG0PN*uf<8Ku^_T!l>v@@=cQ0l=CdJZvUIsM(1Y*Xd{X9`>J&of>ypWXvOw-FD z$HL!v@|1cyE^`l7c^NTT@^$$?PpDbFq}^>8TUsVql3dmfzY>0T$ghH3`a_cZYk9~) zfbtukrS&|w07}ziss;0$AuR<%+ZPxs)?ZwX^?;q5x0SpupZK~Gqnh`(m5rJB8awE? zEaeaWsvqyq{Y$_Y6Pw~wA{+FLPl+7RZ5akV3YO%$+?p1bBmTG^i6yzlY2jK?J--&9 zH0|3}+PWSADTcNe`Sk_EMOLKgVQILQV$kD_c#&Qg{A`0itYG>6aLn z7g%*%k>nmboS4(?X962(n9;dkz~}BDmeJVQTzDw4#A*57H^PJ#%=&XW2b=xtIP1@8 z<-HU$xfS#_Im%svCDTPlKvnu!PrE_8?z+n!Lx%5~1JrKxo`d$@x_;}ewW!OU1NOqo zW5mFrdk+~re83)3BUjH>#~my0?mzNS!8-KWzP|tVeHylJs7GgGcNwtHfUzS+?K5`# zn0h^B+`-PR!ZG|lR>$A&G9r7tsA}&dH+6SRZ|{&r+z9k2pDM)Ybf4yEvXPWwq@Iqc zFEYK{+3onEVCZ9CsqK9!mZakpvz}OQeH=JifD!9u()PUd74tp-dEdBSb_y2imN7`< z2F1D1*6z|@pf|q{nQA-1lEmrJeK8BToS4(6w@Z=((Oy1I-_<5b&OlxH7@aE|46K7f zPUjB9H5@ZKHw{bHIh(Ma(Tc5kC}5xk%k73`Fg{M}_slN>20AyjG08o$fSA#_Gmc7f z_wP*1XxEv5UYT z9jdt%5WChHaIJd18k}gav}u07H2vLaC9d^bqGz8Gqse;G$Xx3TGyh7(*vAa-D`01z z?>!M)Iy+4#UT4_(0Xz3dYdb?Ry6ws|oihM|MH9BuY5LpC;97RKf^?d8|2r_ajqpc0 zEiRj!VMeFL6kdZy{jdx?29$^t5SV z9*0wYPmFZhv;cdNr~i@IzS4@(a*U@mbR5^ojjiy>9mP@6s(!q`TSf5JA)mY z{dX|CY7LF5MyAEKo2SLiN5uxNIw>vo#=B)p(d4IkX+{*x6*Qvg$Uz^~Qrr8|dd1%O zMIOP}6S3W9rNus50n;*K-S8r4!Pp0{!M?G!tjkPdbeit|9!xTZ^+=~_ug`#KKy(^Q z9q?=JVRTx&W=X(Ez2YR@G9boV3~v37|Yok(=ZIx(8qvPu)vdFDp< zX*cWxQz!Nnupw={Ct^=vY1c5yFeC(gFx5?x;a^%?g}m=Hz3UTCI8LYO8%KM>3G}u| z4qF|gjT5IYK0aVhf3QoyjLz+Zq0>9C;!)9x8p#8v@f;(KM1nbiVMZg7{E0iQRr)z-~Ve7=Bh}4BSEc zQyRaG_9;et4Y8vTP3oU(8KZtm+wS@W+O8r-IxW`X9rVBGN{n<`q`n1f?jHKkPlq1m z?lBYY(I74GsT$4^I;>M16RIW?9g3NBnAny?ikapfowXZ{5X17`SHOm@vhIGHtbTjxrUh2osNKsCu`fp>ApuJqU=n}=|izmvz3}NNt}M< zGGK@d@-aHs70Jq@g3-C78Uto@Zqdwu8J*wgqYQI8f1F&GQOoK4y|ozG@91Tn&OiQd zM31G!jMmW(UC1Y^_uwgL`z$e|^Yfnw(ZgtM3*F+=+!gdW<_??mihZb^)^yom<4QL$E(dQNv5og_V;5e(7GXfc0}TZuU>=I?O^F{9NL zdhDZ^)9MP2i7S9sS8z;R0koRmFsIf0j)_}HJ#mHZFdsfn=f$ku?Vi(=WZ2V~7g=&4EqC&hWRm9CK#S`fca-!;HxgQ0=QzwY zxx8RnA5qVeibmIbBitxn9=!-z>BqYI)5Bo!!e`PbtXNetT>%t z(l<%2?Lf@v{9kWLk_BAYI-URPUx4}CgS6{W8hbza$KS#hscs-(enVR8!3Ov=cNu-! zzC&HP%iIc=*+yF6Q#Dk~hd1NC6gx-NaYUP*kI|AnlUvQKFKRdJ<7w|JU`bn9=!tuFNo}^EY3LglNOY==>As0yDiBonMY<*M5!2kvPro_ap3mnEFJl ztRS=0GdjNvyZkR*P0Z;0(jtx--bBpk{F0Y2RcEAiS|bW{D<5x@U-VPlf%u-7(ORFc zO2>844`^)*TjA5(wfY|fumiSe^7xLU(OqyYPPT#XE@n=WYi7qzRCO%Tt8R$e3H5X-l0QA0j=CqAP899sE1~&j-+z}CK zD{1RA&OsufjL`Xm)BNVh4s<8fx%>#dZsPQzaHGr7r+l1#1a9P*(VE;0b6OLfW0L4V zYoc>Z5*=twZiYFniOw-ebW%?e-OT%x6{j`P&AgtNBs$QV=w_ZzOcEVvjWW=qe7syS z=o_Er?!nz!>|Zx`kNe;r+0&v`Lui-DV`5LJnnd*2u`ybbt#Cp^{o^6Iw)J5v?8##S zb}W*+_|CCoiHUz4c#~oK1nflI?2&qt_Y}f)oA@#&RCLJz3XSDjqBxG&D#6Li*{V7{Ut1m#0T2Fii<@v|IOOhkhKQdbD!3Ov= z_Ze=({<7R>9ul9)_F;F!PY`X~e4$)*OxpBO`{roL`sg9EtNK6sSeHv>_9gtJO&{Wy z%CI44JrPUa(514KDOT(}k;`ZHp&0!Ue)*?+kRo~$Bb}x@ydE&pY4N@DGR)|-coAkK zwl`~ZTI~OufRV;VAkNXg^BH*|P0Tmn1e=K^uYCLF8)?O|%{O4W`6l1K`9_-ceDh5( z*?h|{2%BYvE4f+L5=Q-G{7KuU@6X0kS$)Cjw28Wvdd+-+Zz<`pb-6D*CcdERMXRd8 z9Jg1@i6ceTM52GbGe%2%;W6Hfuen|)D;#s|h)4FSR+P=hOHx0Dz zpq)0-F!(ZPjRDgvPRp)ZhOL%*&3%Czti8*9;jiKgeY9)%!XVmU$yc$}tBxl6-jEnA z@dcc#)pOdN$)n_fB_DZT0ecVmQ_9{OLQL$w@dLsdqfuqUwli8;Nz4%h|6 zjL!8qEyJA7oeW!AJ*RUkejYHR^L279_UCl|tla}I&_@E^!5UNkB*3smq?*s5(^dkQJ}ICAN9hc|MHF6|l?ac~8V}hpBk=pA4H9u&c1n!5zcmmG>&f+d)s_W#X?Q0*oL=I!%u}7o**> z2I(|i7qbe#Q%5>2K7^6(8G>|L9KT+`NTu~)pF8ND_fz~^E z#Y+&)q#o|_6)*d~WlVH?Ra#n)`WCF2cj)$edwaRBtx43dxS^N*)I!yGj?a&Fjs2j? zb~`^A7^5ZL;WzXilPg;v+j(CB`(ztpp9~}>apIFL4cjKd9?$v!Xr70>bk`!piM~?L zX}*{8h_1xs9hFCPW!bfBg?iVnMeLL71NO=FSPmYKnDsI-r?=h2G2|Pg<<1T3C5h8= z=f*LkHJ=#fwB{DaB)5Rp+~U}0J1eI7#4x8dw>T!b1+?aocQF^m$7#(Y?`~=sat3IP z6QB4_N{nqO^_qEy?!LGGt~_?&K3(=Z7FCCcRnqj%?PEWvI+y4_X2hsx5p^-YPj?qN z)IPTMz5@1-GrT8avhndk!LTy|cK3X1yR~5E9at61JvrYDaat_cuDiBXYYHtEbj)e7 zpkqd>1r2jrt?8Ip6SP{>F|j6SwV+{6=dalfWmhRLPUn|g<2QRSYapFp)DPbJ9P1gK zUxxGfbC5~!aT*rJQO5bivbH!v{`aqlEh4S;S6)s``T?zNp<8^Kd4g`fx3^bK$8iF; z=?3V~Lz}8`Vu2*r_tp=O&j*&PU$EeBY~D((|!AEf4ccDwCt4btMiFK%dV-cVzO%rTIZN6 z;r;kHt+C;Y0mNj!30mXC7uy?#m;hSi#F|}Oz+MronRnHBWLwt>WgZSy8Ect>t~9O+fe zG$YuiJ+nSg(Y&J_t>5MxX&Y$q1RI;`2|~BS_@);HT6XWY`cT>;JK#^~ixHW(LS~YW z)3Vy|J9kFsx~!WWNOL;3(;u?~X-;d5@xx~lV?b++aqP3571Ow4nA4gu9FvRzT0O!J zt~ssWc5uyU@tE937pWLdi^t^n20`^6p~YiFxAO6FxjUHq#TCSi)_SlDKFz#{TklDE zw!sa)0sXWSc+uD-_dYhsnjKd>C&_)#w>j$jU+P7EgAX%0d~)w^%j1gdi`WMPh_NSP zMf8m0ia9IOwx54P%=!Rk`y@Xg#@rm%ETrL0SK~e>XM!0m_k7(uoIVuZ;@;u(`7<-` zNSu~f0h@S~_e4zQ+GDyJ zc2vNoF1NOto6TcB!tNJxupbH`joq)m28=Xzzhr)*QQv9oe#tz>Fw)rl+9P13)24rQ z0CpgGA)PioiY(F=@eT4CjWx^Q>_nu|hS_>T%dtjV_>1f)o6%gm*lwDxW3Zdnv=EPX z4E_hNL0Ylm8lBZU&F|YWN`x2GE8c!JuKOOI4tj{#W2@5QDQ~olEqpL7p0T#IRa#Fl z7N;&R?N9nu71%Wn#J5~y&!fXN_P(TLOs+9{LAb`~1-!->U12oyN^a!aj|{}w5VsHq za5;lGrkM#Zmzf^>U)40pO=*m&cNlP| zhP2j$Zt-d63H+6@4)&`Tu`A&2UU(O5mF8pEZdnfxcu%Y+cE?+S)E72=AYiq#tnFU}^S;v*6AM|#D(3XyI~>Eo0;8`x zBVbN{y)s}%=Z0^QVNT~}!4AAe;&kqZrvqkmexK_z%xNAhxLWv2oX$UiIenYo5i?rt zwb4n$#CD+7c92^>-bPnT{1HR$s({wj65msl(b|@8TWW51?!;r_l}Ep^-EoI*K)6G9 zKw3QShUWL;s?JJ_6VGXmme~Cvv&~(?Hu{*!J9O-e*u+zau_t2F#_(<&%ZOc%1Nw4g zo_#1rpF*6O+XFhBK#VjFxMCdpUMuM|-3<}b?y?z8%;p7(VP1fzDAM$Ze(aC5JW-Kh zMyJIqR))KAq!r8V#sSm2aq@jTd`@&gn%{mmPB6I}cNvZg`%(Bm-^{ylEn(C}=ug^S zctLhI&S<>QM)fH5n%kY{nmd-;9e3lxdx@*|=bUii*YU`%I+N&vZ(}sE-Aoo=T`hQU`FTbFl)4HIGsOh$AB4~pN;uI!_LZ!)A@&R-BB+RGdlm5dSHu) z8J(Bkg_`y%F{5?&Y$f!7kJEb2@Cn`RLY%)PNkHqF!zZ3+Jvn~}T4O(S%eL$rhtHDa zdi6`}%aX=HvLv}_G3yzPJ=i3DxBaN7XT^Orpw8jO`O}ajP=QChf zpU#BeX#7wb7~;%e^%fc(i%l^8B(=d?DL&9W7%%O}}|1wtCfRj0BrK9-}2Y^2odD z3mA|1u#acGFURmktNXntViJ4s3RI0fD3cHT8FPZ4Wqknhz7c!=53%POsTOFtGw*T6 zX}L4+Cp(;8jyZ{AM(28*m|;%mP8OfpU9OQhom(NkWth?Vx>XtGbpEVe0%o+vnKmD2 ze@<(hX|s};#2L`}C42Y^I-?OsAm>EZGa4}kn9i*vz9{WFlZwtm{(*JT?)zWKSN4jMYD0CqMA9;^G6? zYVlzKTX3-VL=3)AyzOqo4i4DjVb=Bl!Mtzi0{yocN6hJNdDx`8U`gWi38Mq%w4B`V zdPeKX4PRTxi4M?ua>Fq>(IJ?e+;GfjJ-K0+(|U@-F*(Hnnm%!vvgb7Y;|yZzAISdl zm;>j^8Lb%S%EUk`#uI57Ett)56cZXJ2Yrr{(c(vl&AhIaYdy|!SP!(;gI(}x?nm5W z#ilH@Ub239UHquOc8vl&PIB$x&G+A{PDygt9n%~wi8HU8t)JA6a@U@~9eDOd?7CBl zu_t2l7IFvP$^^{Kt|w-F0P?=^t8VZk-@_nH-|EE}tbQi6_>(>Ll+of(jyWy<oQcHpnYJsaPF zH#&FK^sobOwChau=h)mm!w$UBIny`lReCe+*a_n&O*v-r*pqt8eXs&v0V9sn0e?4O zsd_5jAoOMSPT~BXdt-+Ff@(yjBorcO!XRV$)WZnBji4s7PV{s`232`#gcnTDYo9_1#BaLqU zAlEO)YQdMZjqCN?p%lC032aR0wjz$RD9!%5ZOnQl7#DL{f3s1gZeeMEipf9Gb>+YQ z>QLuJG2@T4n~81N#xR|{f<{r@Y&TS>SGUkG<3;pQJBR9Z9Z*NaTvvj1D-i2uvMIK) zVWtDYdhS4s`m5leC(%9CIdQv6oU<+d_C^=jM{DSmIj2Iv zLyLzY?eimhGN@H|Q3ho`w$4Crm_a=UW(}hSenTfP^cEg7-BJ2Phuv`5#ddkqxnOm8 z{|+z4dTfKX&`ZOZQcV11i;szsPSg9~$NpOpq}jHc`D_WcPHEeP2#nnyBt{y?`uD=` zd3;HXG=Irp$Bl@|FB$B(k;~Hp_I_!9Qh&2|L%q%3W!t)oh*3`Ptd=6Cx_aMqW&Nq| z;QeS)ubauCSWm-L-b%hBzk>nGCIuum@f@tdvLA0cF7uqsv}>2goy~$XiQ9=~5fkf< z!}l7DjE4=&4y2UOj#|d#@%aEOFGpfP%5y%LJ>y+aM?uwF>rhd(7F$>{kZ#XSLvSHJ4_gBZ(D>On5&g z+|C$jyftZ&ybfEKa2g(lcu{jHG19=aYr!fod)UNdC!ai4HED|q;rC#?x$O%0?_t64 z0__XvPt7&yRg>f=a6!5{uYyU%xFDaXqeM_2*@!x1O!?S z0Xg>B&Wh>5AH$s1LqLwnAt2EC#}G+=UZboyouBtXnx?-bX0&4W{4rpl^GmUbf9o(} zM(3B|^+U4;5i>eJ{{hs~2!oqzr1OvLCbrRfiR-2B0k|$E*79+>7Mq~Y97oLQ^}fK5 zgTU+L~x!Erv zoSaQE66{gxYf-<+p!{isde&zRGib;z^}@D%*5el$0Ylx=>?hInmFy?mx8K3*;ZTdw&bzesdTlTV+TtZakS2_l`kZ&Lt{E7x1LfDN?%L}MsdsjQy1LAhdDuY#mU+R%}_T=;~-%J9Kf zSeGl{DQU<(0__WBZ`D%nk*X*^7vH-%ds5fi7-r@AI}j*q?Z8&1Zb6JRp03*uhPB~D8hv8e`BKcW_p9L)8}S;Xv4`?24CA@PNaI%$ zWVl1q!V779zl?|Hml~!t`CP4S1OJ^jKni$4>fv01(Q1k91@V65htKgVI}3=BcDV&Z zf7?L@v{7%cwv@>gF14Ho>WaKnaK@8-f8%)WZ;YVDW&F&8+BYv*LgtU;ON(pghQW6f z8E6<7)&@tjR^4WqUu2{9XXQ};Y?~tKLLqonTpb4T^&)9LI_XDG<2qN+16=1ez(lyr_&Jfuc&9v!g6ADo3THZyUK`( z(HaK2&O*I9tX$;%(rhaRN2CF-8dZ#E#lWj#%5&?DD}k<``C!~>s)=~ zvc!~k^@T0GWNnJU{?IS}-}gYnl!jNsgL^$kj5KEoTU%I?Sp%Me(JzLR~Ls} z64LmUfprlg?`40a%^Y*eF%O%n<~gQjtEXzloB3rn;MY|(V;4fbxu^8kdNpIhloa+V zSM!W=FP#-4iK{tmY-MU5oN2y9%`>3pc2M&n6qhu-v@^WagOHX(^*x~aZ&;5sRbP)R zB_1xSmmg|XRg59Vek@RYOiTmB$5eBjd3cQRq?VasmZ^Cb+p=#{vt2{gJlNE%{Z&?T z??cA^cGB_K@0fDJ2I~TNusC7ukzoSzYet*eNZan`&t&uM{BOuc z&oBkgBcG`Q+?$1o3|bm&0)1(!<0rZ5@eq#$9n3d(%Z0Jow+po!Rfvm z5kwcVEorN_w6s65tG}?!X`K+O?QFsfS^}`0sLN;x#wE6UhLSta!hg>p#GGff-Mz$| zXT_EpruLfU{wP+ukJzCW8c)MUqeR{-teOV%lczKrg`g6u?G#){#tL1zPNm0R0v{jjdMZ}b8AG? zAx{hgvQ=_6V3ubitt8c+1Jz#>sa|QQ{&lGSOjDK85Mw@OFBXVM0~6Kj%)-lw)eUIY z7WL|uM=Jdp>S3mmwUzP##JsJlZ@FRGw)N_hNn2qw)mH@?CkW&RZsXf*uD;E~oYUPj z+(46%Cc%Y`@qGb0`MF_ABM;)gzT;1tI_L@4mbNkGcb`;mo0|@-p31w>XxWkv8G#iK!szn&ZF-bTOkAfea; z5|UzSwMbz7;F22skGEE;5<(shuIP~q$#>N>ueUm(Zo z7G1Fpz^+E$TZxf|E8zdWs3naZ7RlVhKy2*-7pX$Z%}TFJ5I4IGP+ z*o!|2p~`V|>&iI}2Tfuf*Byoyl35=%j+N$|>*u|Q$^7f*y^Q18#FXRN#<60RI1YPE z;=~0!@hnVBa-U14`?U`-97f;7Eo}dURw|lGmcX3VU#{kY~rQf=~H=X_#=ASm-NA_BUAQ zGfF`kqu`(LsT+uqHVfJ8RV}o=SxB);90v>Oq7XlGV{VmMs47fH+(OI3LM}E(6_|!g zW#&*Ci{WCDY=`hF1BNu034NvzlWBdQDNytLu+v7`%(jg6)I`h7M2b}s&di~b9g<0w zEq6~XH%HjHjLlJt8|167WUa*}u?~BsZNNwXfn+*h`j|P8DFst=V1G}CxMCGJKHkl7 zQg59(97?8{51oY#zw9_! zSnnt6QdB)ohWY4{iBOZxM@i#o*!}QYog6#Ovjx77$8ut|Z~{?XjQQ%>u^SLTd{IN1 z$F_XjmSD3=`%J20 z={pn#cy?wnOwcnZ(yF7D#45w>AM!mP5mOq z5V#bxw#vhu#JHkh-!dam|FOLc^%eA|zGD5UuWV($qIzk)Utr>w6mY&-qI~QZlR}ht zCx}9UL($fs$B<~B&!Mnwk@-awqTDaSeuv-wQNKX3Jj+zO8}&{a@!%NP_61_3aqQxf z5C=%pSA2}dm~T*cTeXwzE|y>(fAo506D+zkCdJrtV%iVJvf9?#vTwue8iLhfLr86F z{V9gc62+`PwKrmo+S_86+8Y}!8XE@4bt~Ju*?L`5-~^hzfH~tt^!6#V9PRjGQYaUw zK0o9MsRgJuGW#*cMr7mZgnC93`i@i%FM;Bx(8+Malm_+(D8z-1FyB698yFe01KzE7 znr(fjCaZ^~e6PKDjk}e`3BxPHW+Z90tv=s)0T0#Z15>#JR{IRGj2GpVSjIE3o|_YE z)q*3+?Yh=GBC|$vU79}E9_olrUiw&?k=-fJyXvDv?qey;BC`}7b{KuzmY2Y#ro$ST zn~6)S3(hbXoI#A`IBoYWG(U|PX-F%Yu(TLsz9$%C_~j72hGRF%wv_cpn&H_Oq7sT_ zBZoY(Ew5*qx9ci~Nv;kDyM|yru|Fvod8s@^I6FM4x2{=_q%~w+=hg^k@G{j$Nzhdv zZZu`84_ocNm!+!5uFi8)gX&2`&DfIcE;7R$q)p9tmSet~T~co_>#16hQB*C~Rx#Ww zQY@<1b4ydzmeRKMs?xTo(5x?&9G+nwO z^zyOr;qNpSjq}ihVDyVvk2DxOGo&-pCXhLY8WYQJHKt;f1!yNGPM^n%G6#+sab9kE-lA= zlI8Vod?09yG$V!gC)%mSBulj8ZB=7SO=EhEN*c46po_1Gnca0{i(JtH{&03%(>_a= zzG74jU;%$W?CT47(#%L3X$p6m8mK||7oQQ1YubC)g0+(4{-|2OGg&q=^AeuGac#7x z>Iwd~aHGkCSoxkR8>15hZQoNRO(uO$)v>!Di_)*s5b&08Ly9yW)A&s|8cCY{Ro?~y zOaaxm0fQN1tZo=FUbmG>(L6gTm{F1{+_G-$h(Y`5KCxW$Q2J%J=z#{?-D6!8uYe97 zCV!;U^oCvFj^ZZZnKa$8+h$e|U)`|um$@CWR`RUb=-9xs8#3BKb&d9`kk@QeY?5&-0O{6gAgT10qEYvbsn?td&w| z_&+{KA1rbAPmnG_3pc@Msfhv*f0fLM^$eUrw+} zQUputQf^8nNaB{97Um>w$#Cn{?}@9~ra=%SgUoD7!$jA^Y}=AS(!{oy7_cqSwS;Zo zLL*I6)-Gl}HQQn{n_`uOGZU#~CuWjmi_~bJ)=kuU~(T9G`ki_TFtdR40m!l*U_xUxeg0XT?gPg zD&JS&6e}{$dIGIn0hf={%AsNvILw~bGqvI&dLP4LZe*33SHecVPs^e)j7X|83#|#) z$F!{aAH+!0eQRuN>J$uPQ=$&B3Je};PvWZkzL;^BjDYh%U-7+ufe^eK>YE?y_p10t zqVPNW;)4xXy08sdW;rk|6RZMzF?T)5o#a{PE}R2aNVp3px)UF7(JU7$5P8F^ zUvfX8noqMegKz1n0@{Mxk&p^gCNYFQv4`BFPwc@cg0Y+_u->Ktk`Cp7rAj)mwB9{8 zW4ieUG1Ba};i*#W;X~n#Hlj)M)e9gyb=R&*!RH1<-tlSRh_+{yayGDK?Y$Hst~ z1Lp*0FAe7eRK5L;Wm!guIkX(#_+Nu!71%Q;Q||tc+{qH(oh*77-MI^Ab~7i7p0IT% zdpyK>hhEB-FPYzcnLQ^~;&+`Oz&;RkM+&8W_oeyWm&90Zf{rQ0?)f`>%%(P^&BtD1 zy%Oy4QtaXVFrCrZji>aK=F{UFEN4A=8hnH0<~z-JktwVn*dR^*YHE!?d^L;#CS%ok z23Au`%0olYh1DaCO~q3%LA{f0NrM;gr$#eB; z)|-v5hKF%oHEFYuGcG`nFsNiHi2KwMSg;&bQz$Ib&;bUOle~7)8 zfW5cj8ZQQx8|Il9^9<8+VEAu?Vinl4F`(T2vV07Lv*6hncrGk(d<@JAQPmwj-1ko$ ziuQ?o41{NNlb@IXG6v3v0IxM01K-#f_{QpKxe01vbU=5|%i)X<xfDOQ0!^KIp>ce!telZ=^fj|_3veS6~oxg)8wW@G4Qv*784_Feqz_~w&H8< zPo#NWf76$@ePS)lad%~Zr14XOzy?@V=t?s{3(^y8_JU|Wt2D1sGs*Z9BQK>5`ntTzKQWg>`AVt3M&pIN8m2r~a1{6B{bY3%sIRe64YEaVAVGfbDq@~4>Di0>nditB7YSe!2NR@@L2d)@Xx(* zEyR>~LscNK)Y673tD+n#^9@z;LD^7c8>)ciz_d)T3hbGGDtFri|8(x64OQnZ+EDfV z>F5TAJLA+4XXkLm+89j@9wJm14utv9YZbID1b732?n0qt-CKv)D|@VUGfYq|r{DP= ztN5Mlv8wO`OY7b78T@o#Vx$=>{efwTf!*N~51)wZj%7X4xGt{mdDh#ikFQ`o(!6d> z7h>L@i3~Y^SYV5V$gxOhB%1J2CN2?L&5yI>Yr21XYCr~pZcR5 z6`aC-7Wz&KZHgzTndn{+PAy%0^YFYVv zr<}j=v`%s-uhp|{ncpgVpQ0EGHGg(S*z1X)E{l_%ZH+xG=jNyfK3TN)Tu7E#uQJQ3 z(LU(2fESJD@hyL@(de9!YjorC$)B>k21daA)ejn}MzQYFJ%EkLGRw(conn>Qqehj# zcgy(;FWt^G+9~+0MFM5-OI#LHaewq*HQI^n_3T9USkCE>znoX5Kk{;3)|YyfSyqke zrdOZ9F~*4S(Rf8z76Q`M=CYQ3wDAfwK{y_OZ8r&M!b0ORZ$pgbUM5&&_NYHeLtzkRY8si3E+<9Fj=TxRbG`<$NdocFTy#?;UIhF<8HK zEUQKvP`A)f&hebEKyi&e)3T2?VkY(6g<$y$vZ5M&#x(j2F_xP~6>F_VmB07P`J0s; zs>(FFYw%Hvt?C=Iz#g_*N;JBwX>?a(Ps`KvHP~&t1;j|BUQc-mH8IkrWo=to4ApW! zv@i4zQeZx+ywwE1^(pGm|KPVZ&>mvzfJ4cOYI&$>d8lDpZdz8XGJEt}`}|g-$&*A zMKSmuUTfg?!Iz`?t;ArN-^T0>+}@iQds?2RvMAb7{0)9fnk)~5rd!W4bd?l7E@wFk za?bLA5aeQ(5#(e7S;F!FV|jqE;^p}66r6xGFlc$8)~ldpf4{0uc|Q#tBR%QsMb`;K zO`v^o{I#L^Q1hzzPH{x?7GV#xyoD3do^1@Xaxbf>QG5HVa<>DyYlE(wyXeKq&Rz84 zWSsZVr^ut@f|ttBPt(7Ki%>{>s%$f^F6{0WjMrt_`9706~8xn8Xb{>5lb? zzH;>vt7qjZ=>DZxyH7BS7N^FCG+t7GiH1L_Nt&;L^yAL*8p!G$5CndT!x}e9OQ&%U zpaXb8j1!DBd0LJ2dKqRx#p^wZ8TKb1vL0!dN3e*$>%rf>f`C`0p@)4Shx(Wq8*-|# zRbDT58?deDYBiz>jSyi7dWy9saJkR+M*G5N!DmO~`eL8cLlPE9eD==fN!Y96z~$P0 ztQVO0?4905*bC)e)>@xc?sf`3>)eGi$BA>dFzmAWTS&qKi`hGY=ZEdt%a|f+qVw~% zUXRb$tWN<{C(|IvIxZ-agq*LD8350Rgz_$1;^iw<*4AhhejzdTlcukqh!;AZA(+!? z`tnTpM0aAO@tUBE;X5;kk%p4RcWxlYez4zrCEinEzC#*&w(sHn7nsb+HAtIp&o6EJ z;*R0?JZZ|vBmY6RHhcJaZHyzOA!|qM?M`8Tq%pQu1&p-oOzN4VKp*N{su!0D-^T^n z)ZgcuZyV2&uu1(usl|74Mx z6~kJ^(BU1*y{xtVuG|eM_xJF$MCR`+f+xGbM^8(*b4N$a9EzTMaet4_(sVVUL{RwK zPq0(r=k-PB)!&%Ef5UoSu7a*8#i|~MUx-Bbkj6`)4hTL*nwUSLA(%Xlp}uWC;q^Yg z5&m?f^oH@EwE3s`b_sSJ>v?}t*6W(kw%0X0U(@R)Vsh4|*GssE_5~L1U5Jr}A7g6X z)$#yo^JCM2%dQTfI&l8+Eq-irsLxI}pEaHp!_-P*NUI(Zaz93{OA4!kAMXnX6q|h? z;rdi`kMEM zIjzF)K+OATcMR-WO^h_!;l8dvkV6{RM2z-l)E#^E$xx3pmUrmOpGPMxe2SE%*VS>f zEiuv<3;ojcYx6PEE~C`*@-%(%5RAR4#7OfRHFMdY%c)MI@;d)+7q(TOoh$l-&uUxe zl^A($<(#@>B~p}0tzhD-sHkFC126Zo z*7~t>w`;i{w+)L^=MKN+$m@sqT*bbBK3 z+VxcQGnChLx&!90^jW+gQfc_<0l@BMf245@1gJGl#7Mi`?9b&?W2?N*KfaH{*fTkF zEMYyUk;8aaY=L3Qb1QweAFf@%Z$#$tEr0v*Cuo|chS&>8e#E3{Zh7pLABkzgFx;dq zz7MAu^1~-hbG;2QFZZ(6`mAy{IQXn{H$B8&=WcO`z1X7C*GYz#$!8849=}g!Qd@Q5 zeH00l`uW>X_6;HSu4@8_pvZHZ$lB^)!Q{PaQq`MSJuB~qFz!EH;j{|BxU}Aer@)W5 zA?CFF5)Ic@{8bvE<%uu;LSo=S{m#&3UB_*p~g6e_DTn)nUCUe%z`T!uotc#zEoBa-Y34 z#98->`Q>p|efCnQ@h4y%DNQ~q#(Wb4-}3QtFKeyODtAN5efGi-XPvuO!qFM`+30ao zchK+_kj!Vpn}af+on01ZRnQ9|NGAw-fQV#vpKU%nTd+{Bg1%CUsb5)+cDl`J$h~Sq zteK3K?=3X85!<2(J_oG3<#N)Pe;yn#()2NZk$VZYoV^G}QA>a)uYQ~p{RXW{Ef;ore$v94A7M88)A zNPjGC=i~r7u`sY&fPvy^fa4Se}t@PP#QMK?@na>uZ zJz)2W7WRO}XN&8=RM^_^Jzy0B6HygICZzayxtCRB4=(}J`xKb&C50UWd)T;ru06IB z$A_tl@8w?FeCpy=@r@bXst1J;+eymW5M#NQ306US**nUVzpu;rJ2FgOE|(pAusl6X zII_F%fR6-wQv-WTx=B@UV(e)-Hp4E!#+Xe8Nz10c)NdWjs?mDXE!Zz<%4Ey~%16h$#FF!!5tJqVCv7C{LKT2DfJ>Fka{=O~eFZ>K` z0*lJMyf}cH-zs|}!CsfZp4@zr&1E(*_Ou+Qoel{btE5GvQeWy-W?3~Vlice0309dsYFYXFuAIN{TGr%B zUaN)kV=4)v!<(morQM8`|EKL*z^yE*_O~~30Pm)zf)@}KFp--`ilhg;L@H>Cmw=93 zPI6E|P@wYnPg65W(=sdXmYJFwninudBPD+`HNPZGJ$RTR0;RfcIg#Us|<7FGE^td%c4fE-)2_WYQ(D5is# zPltFK%29-V@S)nG*y~aw&~%<%@bhDGc0taMi4pLe*_uUG8`TYi&n1Z^9)*o&kMqSf z)W!8}RNmba-|3H)i3okI7v!g@MP#N^JYs7Wk2b3E{kvAa^iF1Rnaq}`KRq7k4-cs( zC!l)xP8UxOu*kE3%wpncy8SLke`5N39sRKYI~&2QEoMmbVvXCfT(S{cX1S7g&8lh3 z4+CrGLuxh4-iGqU!DaPrS$+gUe5^kXr7e%v5M$|k8P#CAwY*|$7LP5j^0n5=m)?tw zEq_r>?4T__3*v3rrsXvp0(Oy!r|H)6;`L!H+VVrt@>`?jpC(4yT3Pe1Sq*Jv7-P|S zOwvLYSLn^|V^hp4&@4b-tF>>kA{|wB7k3HqbcOOY&tsUTdzxTt7LTp0@>Oc(8<%3< z%dM{L;fM9CTG3=2l7E1|yBl^SXv7YxlEws{j#UNb7{4e<8fnV^pNNb&rsy1MMIN6f zXBRn}oO6-KqguqV-TP)DV{%rJR~x43{Dp(9O2qzwNqVc2iL88UXytgqf3{4n4Mmb! zPM`k}r`oe4{9gVx+;hFdd>NZF*?lcIzSG zaYH%jakDHf;Gxocw)!h%;{a_?)Ar;<4$RH|ETj6l4b0DNK$)2ir||-u#>K=)o9|P; zcFR0OWbRZeb9!?)%Dh=k+pElfhs+2dt7P8HWZukV)^r}S_46Ha$hPNv@b!}koqVKC z56#? zSifaQHgBh(dt8^sjLD}xjF?vZk)MAQ-S)W7vrrGFL$|~5h6Mbr^e<`Xb|Q3JK#Vl? z*yB3E+O5YhFgJ9m)gwE{>3ZCp#!=o!_{1bWtV$1f5V5~KZl-)pXW;Oe5p>K9akL+CExdyLFSPyP<2+O%9}4rK$T43OaP>)JLWp zIr&ca$Q>x3+TYHeh1gPz_mMkb%;10b`6e;ac-QE!=r{d#>9l;WlJR7GN>jI?I}6rs z-Sz@=L$_MpdZ#(wb^BCJzo~A$`KWr8Zl5yUK1KPKZbjYR{ugxnB{9;_=bzB+Wn!d} zccJtZG18`+mbV7o;x6MnjRn?Ey2%b0R)wpwZN@9)<|6`)?7L>{H*PaN@NU`^y8~xc z<+~=cP(G&P-KU4L{P*4f{s_o@BZyjl77K{X0Hs)2%(eB=wud z5gR7mWCsZ2t^4vc-sGu#m~OsZVfI2!B%g#Fn^Hd6Hk0iNW-(0DdB51-3X%K8eGcGp zc0Z>hN89ChBUpyyZFe7OY_U>L5G?IL) z#PlF1>U|42K1-R!wq>hC#z&v?i7}mM;j;{2emeCYtJTk?C=f>7nT+JM1m$(I0wz1A3fAj5P9M9C#m* zHr=$mcI&1w!zYq%vQWOQ+J|8xkp|D#LR}~eIg#VqY9H1YYawPaK1~ndu~&*>OZYC) zjWpi48-sSyb*R&rqt1Z7%g9F>zOEwMTEs|G-@Y3N)^2?@j@Z0b-^|y!zS%k|*B8F7 zf;cAkb$zjpQhgB{iEd1Xj(>o@R}&)*9lrp54k)@pn4+aeCxnbW2HLzH`cKC4;(d`2(~4Ja9&RbRMHb> zn;dy`)953bMvWbF#F0%$j6SGTT7x)KW)4K=hHa7{R_V~`nIMO;qM>u^3o;awy9hs2 z4QP!uYT(g5)##=FC9CmpEAby6QR81c9n!DK#HP&DaG*!3(MsR*OIeNblF%>E0bk8( zw8=(v+Y=9?$o#RVbR0TBUcJ}@o2tx1?8g1DphK|7G-Awy$4fO$ur;=ixXOlYle8{b zZW>2e&2>yeC3?%#+fk#0P0=K`PxT&&V<9+d+4|S4mBtzN&#aZyB%RmOQSaKDWRsdm zuOy09TbY)LaulnooLXO$$}~@JM-xn$If!-cnCkTMU(4z|+RA+ABkFw3)7w?&VAk0? z)oJC2sac)J;7A9|z4gmkoobk@D@?`Ty|E%VUh3p&mex6*huG#{MO3{ir3vbJJgq&3 zNqKil^15ufi5zQn*D(>*11nMe`%jT#O@jfyRzO#|OR5w$SveK1`thuhWSdy97qUh& zS4mz^Z%?H&2R5n4u-E9z$YbUAJuItp0?X_>p?;lx;n$?@zL-MRtSAgn>$FFrrA{yZ z(X38cn>5CNec1m(^*WQR?b<2n*dLEGj$MAoRY4TYyI;QDVYFua@iW)x0+uq6aCvn>Az9{P+`3Z!chFuc&rmxeF-T##)w(@)InbkRkW%d|Zzs??edV0I+9K<^JOL}_ww`X-u zwK9MG5p`m7Q1tBa>vq*Sn04CSBhk~!-*#|TXEUeK?gwUdWRD%I7~2 z!q4|4W_0GXbaXxTq-I^DgU z)1U4O3{#x^b9&Ifu?u}VF{k@(jGa;4F+r$cv>ex6X|lw6%?>5E%X}l`yYms2=d{?@ zuXH6^6i&O%<$3=P=Sl8d&b&sKI)9-kE&8cqPM0R!4(zMMj4s`dPZ^FGUEW|q#GEcq z!E^t{=XCkpd(ifawLGWGXX72MJNF}IblL1*K(}{u1m&nD0L(wCZN zH_e;f)I4L-DdO#NWH|-y4Q09m101 z@EHuTjqs7i*6Hrp-adyIX<$2IJ5?Qv)7(1X)pVy_1j$=Rsg_flXHPnH=Irr98VvX{iqBv$?x z?|g550h|A4GB0V=@muh1R|m6tb3Xqq%PQ>L+PwY{Z_ejGckY-R+GxwC*te_86RfR# zikW<_+xu6h4;!TMn80xuou{xo($X&IziVr;mDki_t9n(-A|F^coJowdv>(bmq7G*L z>-s)}6{6=Q4ZHkw%3Fn5Ua#ZzU0`4sfnqPDS?{VL)!5%KO~3VfVx-CEHsp0YgH`9> ze@s5olx3A{&!Ubh%-X=~{nOSsRC71^NXw)7kk7(i((;<2Uo3JOwyQSGysG;WkE;y3D&>`5v6Z|oAIF|yQ9ki6B8&V@ZMAAI!>o@uzF|M=qR6MV zjlA?x30n!7>7)|2>RRKou^?@_YKX`pe}(VkW~G5TD?Q3tNp_cgR(dSXvW3q|{bIl# zr=UY)q#vQ?^r*wvC`BdXawy|EgZ;JbR;et92Bfll3c4b3Idn(j@+s(tNmPdxq*tuY zVo&wBB$ee*_9TT*L7Szr9O{?KI>&mmPn;tPhxSdETE9VmpHCYO9h{_x^@+8#K9=Ni z==H?)O^G z=^dJsq_@wG-LrmlDC@`X(55Q~rM7n{s}Y}KWz^*1pF>$cUdXaS_9lr#<5CZOm$n*4 zr5YW|xIDVZ-X!tpA~O?%dSt&O=mAInRJ=n6L}Q8p$3v;TPPLJK8}xikS~o=(>VE`-!GDnH1f*K`cO3{PmuVnI?`w_c$#nRdDRncR)_CaVwB(V>LM)Fp&lIzjJ#gOen`x9 zYaNI-e3}?(>KklUuEIuCm-naRpoe)`(ipEY3*AA!D(nhkUaz+40d=tc#JsKKDBFh5 z5hE?fD$$0o5hKmEcbT0}`Xkuv?Xt*`g>7vOlk-)YtLxC2_)ub=_n9-2ETlzW@lWK- zF)yzQYg3*)z2v%)#%2WEpzB5&_AJrG4y?oZ1oJv_K94wZOrBv7JMg>@y@RM`Bgceh z9jgwmgXxUvHjD9bd6Jnl?Zsuu`?qos%kwsP=2Y~PtvyMz{Z{R3e41`pA7VaM<%tP@ zdX2R7Ir`GZTNP$w#`{hC92;300iGf9TfeydCi+6D18w?4*8}td!xkj0$0fvi zSRYB=9=951wxPDT8L@56{%D_unVm`-tm-4O$Y0i>*uIACOHAxZqE?ABd^M!l!G_sb zmAtK(2N@@&@>*Xv%xqHnzZEkqBPH@F20q1%k7GsZNbO9YX_&RM+WY;K#r+G%fMKyb z^#5>T?wf?Kg8tPQ%KBIBb2Md3Iy(bYN(qRa<_9G%Yil_%ZV2ljeMxg5j%yZ0_Sf4f7z_ zs`Q#bjQp-jL47ByPdU-L!ywl^#7LVAR~etkbCt=e*hjPy#d#u%Q^?MjwA1maoqRLw zhab^S$0N%{$Z|-kd*u&V_e%3FOa}(Jh<%higHTA9r;!U#b?>(xwHGE;^wnse zZBWm7NuE_bD9@@M#F$Qbh}Ds2&Wxc==)2j?lcuIk=q^tu*(9`=Q2e3PRszie^g+G0 z5>}23-xJgk_<`p!*)VdtFB93M9Kq_yR%KIQ>0&?J4m*h!mA&|3O}6sY^i55B8s@+9 z_zdep5h_Q)e5ON$iAaCdFr`J*49oeB&-lb7v~0t~Y^Ol=ossu0Vx-}i5rq5p7HQU!hTJ`W5T&pnGjrcRMPa#&yM2V)OBM)olDpMc`5Y90}CX8c9)$w!1hV`8Zc z@H|q2r+b=UYm|+<{C`TaeGTfP394lSsFQsi*~pAcTO`>uK!9w_L)n-P3=UWxKWc|; zgC~Nk%L_@iGoTtqYmfW$b`uazyPi3d8E2yVh`CY@2{wAboSBCh)1}=$#+l!FRoVWWWIKzp^*A7JH-I8rk2~}!U5qm>XFXrtgAbd!@aDmK7hY#^^K?7Ta3(RBors=>W z5dNrep<1?2t8CftI-m%7vnLN^0BNXPCy*g4(%(;#X($cJn1_-v9hijP?UQUTl`Q)) z1eYwEs$H@=Q?*Klse1WLNM=*D){d!KC9|oT=_Z+CYa9oII4S%+8QZyNbD0#f_d5kb zch8$uW59wdBu9LOKt)9m)O$VlFf~{FJ&I#FbxGq}uOrwid^Gu_OhG6SucxFD+ zXw@&oUr}eFiKgkE);`fVC1fv1%1$yye%@-nxm@$=sk7qmcx16w(^VE)O;=gBQZ%Lm zlU12wYi>2p2-%}+E?U-VE?S*dQ!UVH4@^as2&;U7)rwYA(X7>&ZlWo+X3;nyWY2HS z=Z%~^Dg-2J%6e{1uCho}xcrjj)@02o({ zm{!rAgJ{^U?fwMC(CUMU7EClvH_;SZvuKMfw{^H(L|u zAtRJ|Ok7PD(IicJgJHKvuk`qQ|eIp5(U4OzohRUr)pl(cUD|< z-T+x_9j?1GpQ7{NtNETz=kbv*=~qwggLO9Onmun|qUDdHyJ$6!qf@ki4eX`cL9_<8 zkcu|QL>okm=_Z0P(9@P0H5JYL8q-a*_W89ToDH^0qJ09P# zUw1iX~Hswa1Jpbk9@$6?j7JqBp6z(*`0*A^D0(?#n^O@NiNDDE4F z0sw92l0A1SAV8~FJX|HKk+r)1xL{B}ysmI;om zUx#ZTui`J3;lKEu%EM#qTLNpw^^GkJW4fmSY%9?2ha7dtpr#`~e^8TLT4_3}@sQE` zH;o?CH1$MoTX(xG%GjwTgbU%ymz*#>^B;q!^%Xo}Li&UU_{ zaQe(=iqcqou9tsKKYI(XCx{tc8iZ$g#$p+Ze@>Ua`Nf18U3&4C2{XDp4EH-MuhZr4 zNWCo2>GB=lFG>SGp>;Sde~Xu7oS|in*1zB7=x|#9j`~dE0}TwH_q#f#bosUuaTQ=M zVn&zm-W4zAz%S#U)7~$D+8W4!k2Vml3@)XCVECvlz%mzP4;Z--r?Z98V$wt3<;!Rh zxBNJ{4eU9HfMV$jTJZN0So+Tl`z)~Y&4|u7jOpdOcgmC_P37p~y`1u$2jhaAehw;} zCZCmO|^^1F^MkP6rn?0I}AZ ziNBYlwXQa)NmEPxN^crZ0-v;`nTNKBVYl3zX}lM;b3Vy~bZV@8Z8fG(89j#1M0`u` zP%cjn<@lof2=XrKy&qY2_=$jY>mL{O*Dc|ugRCqi2 zj4uCn(-5xLbxq-P`Jo9RT&teBa9SJXdXq&O3p7pQ0G4NRm47`ygtN_bjMh$oO!Ck3 zaO%;#ljqDnXQ za!SjLq=BAW;u;-#!qUQHuu9l{v zTAuQ6{|7y~8TpJZFZo*tSHDcmXjSvOLsEI56+^lBH@o@7=1HeCH_e=5{keba&$ud> zleF5qC|({YQF*Rar^ceVbGbwg)puhH+8&n{a}ZNqg$UpaDoOG32r0!&Bli0j8OO6M zVsBuBR$_bS7u3u73*L3O@j3E2{ldZ&pF90$#O!{n(P=MNay#Es6Ogx+TV+=2MzZojRpy@|+n{Pi$sTJ+0-`rn!?&Y?(TEXw$%^(M^MgHBFiQ6_nd8 zTaJD?gcGM1#qyrnjqz!Q?UvmbFNr+P>*<26v2O5mvuz-(@d_#Y22?mS_Gam(P+5)7 z2D>ka^K$7Iq4EYUEBCxA9t@Ar!gMekn>1q&E=s*_i%@}s!YZd$0SAt0=kXE5NQcmj zL!=-4iWun-jy<&~ZF4#?(kL1?KYQu=%+o{Y`F};J$FAff9V)M`7xNko;jtR+sp|?) zH|(nFynlPYDD8HMVinS83!LHDod*w%_Vyv4mVK2sP=+lujP;uQ-bBJzzprFb;|nlx z=UuOlb7u*`-hKhiuq^eKK#Pmgj-}dzJ!B1`5%<1(J}WhX_iEwwJj9spX@XI*ToO9B z>Cp{DQJ#)7Vd>&fSum(5?b9z#;+?wV!{44oX|EZ%XDBvdy(-_+kPpjCldrO13n{=0 zQa+Y&nwLau>2*bE?*|P#jpebN5c>ZvT7c1^^4|8*Qj89jyS@hT4HET3FR1SbeIYv6P{_Up`Gdi^1^F*{fqeClolsecS zQzsukm@awzAdMo|zcTd)Eby#{iem2k)F0P|&~Q#sEPFBbNBR9w`4%*+_SA*0M?63N zA_SWATh%Qz;289>7rh|r`>i2Tf|o?>>UrXkfoU2smV-7MSroJOCq_Di^{{C$tGi-G zhe|-5yr=JUsI-0$^=la5bO`wEnBobYK+DBStz@zJCp7hxLh(4i#w&&JIrVugqB9mu+Wm#^EIdDPA)tYiFY@BAC)c7464wm|%})@%=Sf+2bxF{T zEbHv6B2?@G6)^OuC;n~&eXVQYh@q$}Og_OLU+fwuY}pc5Ibo0Q>pCk&lUZV>y@c3_ zpA&6eYhsvqqz+R%@h#fG_0BK^&7$R^`3bwLi))_BJNqhET`|)$RNmPMF3H+}bf~QQ zYEirmQTo=$8Tb+bGu``hftgl%QM=Bqt$CNhhD!dir4MTGU*Tw{5k?Hn}kW@^4K7hH;i?VMq6ng z5Ocl*zgQIa2g8&`V9>oNZqZ@pG}<0I+}@3Rq=BKI@1k3=bYhD(sO9s%^m;%0Xi?mR zdSp5!4VmFqPWu}%($H&_Oh&s#SH^%vQM`AJqZLx`A0~E77 zA*_#>?$NIiBOSuVyQWxGIR_ zkZ;k7TE0ab<5qU4EPVyj`n}{Mt!0#Y>Jry!Ee}mr&G#fiv<-Fqg$il3HWmz9xE|js zP!7`0gKxHaNt3Ua`AFvR&SM>d^}?Jbt0(7!?vMepX!ns%+G7#ICt&!SVJi%?HekCE z^Y&BhZNs$vKEfEW0Bzw0f7fNv0@Xxdfs3-h(JgRJ{G?ZM3mgzHBS#CoF}`aO&F#LJ zF+y)d+luD)P&Duey&Q`#wzO7I*=ThOxrk9~T=;CLJdELd+gs!#jaCrLLLe+wS%tk^ zi!FMi4t5_gv3RLt>353a#q)@fhBaYH^9i~FqqW{r&l}0d^iX-~o3N~j#7LWE*#aZy z+h$(k+h!j4uobfHa$=;Jx7Pr}#6suLvbM1D)Y=9Rb3U{O(BVqB)Uwe|cULGJHPi%>MJ zr;`D?b9*egK!;wBF0jh9E`VumBwd{~>qKi->pE%Ho*xkF`2qRR45gl@X*1w2F_r_Y z7Xpq>#-}teG0Vs5V6V5yD_!$+HMVprOz<1TNW%ojzyzC#k%qZ{0&Dx5iILWNqkPWy z)P68aGa1sM@)zu`Z1NN4B@KPW#HxOB&%$YH$N%qZJng(N0G-)vE=ynB-3GP9?24q=yZdwpsrrlJvV!519 zzC5{t(9)gb!lQI0)@auh#f8~|=qfCQ&y^*0siGVnBl4A+-9; z1pPxGyr4QILY+Dh+POJFoeA}7Nl+J-_4uF&6`1eEEF_*;crO0V#NQK%!IWfOCG#Nu zCJbvR#Vqa?lPi|)?7c(2t6};V?(5w{>?{O}bLV^iD2DBl5LO&Pu|8m6DqASUM#Cw6 z@8c8S#Y4$={i_LE&_e7c&J<^4fSf17K#DJ7{#WM1(KGQMu(M;CSXG(@?#}~!UbOk66`rbvpUTACd2kX@y z#PL+Dt+bD{Z?I)`6P`1)Z4T1dvif7fNMp+iePDb>BhY@QC~o*W>mVIk?>il_>;uF| z6YJMEVg337!$rEMUouQ-lvfGi$Fqo$rtIHesF=wL`QCyozaT~$@?8n+Z0046I(93H z@4iHgG_g_pCv4RIsP{K`eV`99(v-zsV^F#98iTguie<*9vJ$&^sA5sROAkf8?-L^( zD(9h%=c8|=?Ma8qSASO&XKh4`bf}zu50;Rii6G8NQ=y3uT~z~NZa70qS)mQV)rObKKoGu&4V8$(7%1&CZCiOG1!yH z;_WAC-Qrjfnt3;3teo+|nYMa)LJOaa9V-v*9NYc~VzeEp3vYcPI@3159@Jx()yJf~ zr)Wd1zcxO__G(iePM_a>5wUxerY!e#u7jP`CNE^Uc0XcL$MuI&mbRGGi<1rb$M%Tr zf_?&KK2z5k#VsEa!&(D$sH_+p_c4rypF9NN!Up7HIx+XLp7*7n6~zM>n^Fg9mbavL z%DbdD^Df<)nA_xezb%THUm-?1RDSpp)_x`*=}@_Jeo>rvH~C1zXTxt?xUXOz5hcb? zWmBe2nlYpK#3o-X>p`@s%~P6YG#}3oXc7#_2g#NhIH)#b(uqTcHVtahwk#MDAjT|j z9V!LJ->A*98*&PwkwzU<^Nqxqk?DE)H82&vRetVl)Iq>B4;5lMj!SFWx={#srBC_F zj491ihxr#|)uv2s)`K=zhSn#p!OzcK5d)m^Cn?v+OVaJ=@>YiR$S`RLk$#Hb=(+r zFDII!l$q{vL?cYU#aBkexm_Qqy(BJQc=ix2DdxHz{;r4?SlMoUVf8Fhx~GTA`a43~ zhlr5|pYjW~wwleHio>5&3Ih%WHQ*zav|lHfp$HGtY`i9IQoR!@e?*hF?3H$rT*Wsd zRCE)OJTv~nTQ&ZVVM?3mZ&qUm!Wc%NV#!N7RIbEvmwo<3j5OBfiy*=E#7M()K7se; z4wi%PR$~_e~U2vw_Pk!nsM!%0tzo=QpppyDW zF0N}KBe57MmZJF>aA}W^T2Gc{O8v?k!8N?dRW*(`N{@SXh79v`~KB!PbIwq>p z!$dNLN^eoR{HNA9ld3U^Lfb*eTp|3_nzjLdLe0}dWsAMz&oLSuDm`9{KM`d#_%RHa zcWsqS{ddwJOfLFs2}QbV6#MOxT8I2l{mEtICFnTpv6!AZfsA|z7@YG+8^%oMkiPZo?E^Ywa)n5^A)+``iA?oO-B{*FxlnqZ+io``KM1?>GC?ba0l2PclS#>FlQlo3N1KF_+r3_`WM6D>$hho#f%yte zhfVGdn=~a!Q%U=oHdVOyt5lMC*H+2gCh_nKZF2qEzPvGBGK)dNV>Oq|*qPW5EU=Pk z#0pL(NC|32K4v!g81-bjrwP_^`KxSFPcUE(J$G+4dv%O+L|F2sx1h z!KM8=G;I#LpqV*o>-?rVAPME-`T@quynAjnuqrt8SG|s*(+MOhar^ zG!j3Vlq_NEUL+nhJSoYb$2gHZzFNsq!#xXyXL_jgIv9g&5;4-DvNcx5dt0B9hT?C< z;K*o{2j4krxa3`1#gmWy_DFuygVuvT!f#5DxexT7s`}7I4+bWF z6MAY$r0Hg(igjFe+<_Q0(I)JTlL8xu)>ZK0+0QGNKLO};2vaj*8)s;JXB?7up!})*-tUPEx49N^vj7FBjp{cis($uu^O=}U&gODE4p@lF;vzJFTk&o%t^QRG0FLs() zNQRASBIbFeWgD@VLGdMT$6J_I!)bQYTB}JvTpg_@n`Y4u;)T_|dZXPi+N-SQe#&ao ztfhz6H-CyYI+1xvvn@L|rKVAwtcH4RM!n#Gqt&FDHCoM__ysRo&9Uh_-~X~J8ds%H zHf~5SMlN5cs$pJ>1{skVlG0FAjEC`r(NwrQxBRxrsG>xWlRW(+@lEa4} zX*0NEtN8-T_j*a25zZl>8X-Q*shi5MQOBAQT6x0PxXN3DdDSrSIYA9m^;lPi$+;Gv zhuj};5-J-%SMAO=2XqN6uXe5_XQ*s4D;j2H&!X~MdZ>J2G1};OVx$oV?ty-= zIFU5+Y8k@UaXpik)oa;}HMuy4Ms`XWaRg7= zt?}9T&D-qPYDMxRNX8z8Oj)EurR&$wMmrEAjWo1Jukj5d4Y^0*3f zC(1l#zs*`+72invsGzobrrBzSjcPVqwY+MpSRRW_dmWm$ljXIgI_3A~ka|1buXL>X zutI?&w{7h=bF6N^2c-229V;yzo12@=Yh%9$P}Y$Lu+5ondrV`A>3-8#_6_+uu2ZsA z>SgEub6f2bKaWRSZK*ZPtO2N5}){7i^W?>o1G(A&dYn@ zThWiSl7^P>D;`vk2KIOxTWv90wer-aUo@LGSrl7sn90m?yd_l@j#Dh{bl7VfblfIr z=lV(q&R#`3-!!zY7*y@2x1ca}!cKA`$Ai(%wH+kv6ieX#kEe&$mw$nFlM#jfBF%Q| z*gjFc0D^jLm3%Uk5NYd$ol~N1Mx##V8llz{oVuMS2VC};B4sQ#qn@l4wch~yu;7$5 zUJBnl&Ra&aJt6QoFNW5)VCSBfw8bqP zOC}fiux051Flif0t*oO8v%EPratis>Pfs!1&#*?=uljS#tG3^2nAM@S|153C+dyL! zoLtZtWu4l-J_A#1U2FT9k9XUz4W8BZ5j?NJTIzFD0kEdQZ$1WqS3*r&C{VaI)k2-Isu-KQ!N5`-t+J0u}Zu{9x;I^M}x!X^H zjJbUdLWI~W7G%RgX*36#!b4rsY$6Y_nJ2Wqy(^j$A)hoaX)|etG7(b~tAmX^x;n3# z?AujXrQ7#V#|MfTZBvk~8=1$<-0~`Rv|&~UWiT^0S=7uCcI#wmQ-PW}Okd5Me02K= zgVgP7y&X3bx_y0SsOX+de=~mf%R|;J0by$=-zBnjqkL8y*$c@RqYus9Jh8v9dKR`N z(?jd>o@uHj4L;=;zK-jZOrLu7pkAF|`l1A+&394U&Sxgmccad{H^z;a7c+;}C-+LD zoHRV~mti6gk&m>Qt9dxbKEy{OH&@aYY0P9^HJh1cHioH*!0V}rtW&QyY@*bjR6jy813C6?BQPX_S)&AFRQG zJ4+`P^J+TFBj38T8aByxX*9UiWD|jW7#ICBkG7uaCH94h;K_Y66HywLj|tiX9@3_( zc@fncJ3}m5%ImmZ7~unbKM{8jeF3vRe9L_@ZsRA_vTQM)4&iI|fsGT%w?btb;o_lW zgfk0uXL@LT@5j&+%_BpGG(0o*824UCj5PKg5y*IZkVbjONx8zeu5{<_(GIn`XD05t zClj~NF?SnI=jfeKC=*GdZ=uKacuo$H2APtux|T_i_u=SI%R>1>r~TE z)ahF2bZi@)8ciqmlcfVYDfW}mrqep@CoVj8Oge3dSVtBf*|@_ROZ<91?mBDx8z*w~ zPUB9d0vUJAVtkq&TAw)wI*lVn8q?B1jJubKk><3tZu^cwX75@(voYp+*7P0q#28xv z|L9{(^~4xcJ=u4b9$NqOWb8YmO{aC*cZ?ozA<}&&&R}Y+lZ`Q%EhnKnvrWrv9>5uc z)+c*Jd(?Rio0gV^eZq7`MeYli_muGlKFo6+`xuxO!<+{=x9wc3Q#Qt2r<#o{YL96B z$zE-AI>2-~z;x1dU_(@Zx+*__b1Y%c-&`IT?aJ87!#@>}CHJRryspTDH zgNvN}OfBp=T31(zSrFyXJ|1ePnP zGgrgoskio|f@2ofDwy?Frl6b)U-c85xBUSHR|U~qs-X22)1e?vGBu7e1(mkhYzJaG zo9$oyhtnC=kb#OY3HP7NK{m&$up=eY*l5_P}wX%vsSJ2zWbI@@Sq zuNo)k?kc5m7)F)8p9;#{4YRFuzA2im(cqK0&y*%@3ToaCk4v5O8lFrF;=+PVdbxs_ z2gS438JFZl4(yQmxRl92#wD|;f|edy|A=PvaY>rHi9Rl6XHmu_%aFVsR#0cV274Jn z%yw_~U_LHg!E9Wb*-BqyTvj%|H;qdb4&zc4l_8WzEF zCGT1(z2+0~1Dj@I+AoR$Y>ZAA9`Yd*UcKHi@|V+YyMF;aBJMcKb|rMQ%=p_Mg?!yG zrSX$dtD-M6n%gO(;Qur)`FL0xwkeo6|IbXaZI_o7jyEKYL&pH# zZ*tqXn$d1O+ju>GjL!FIWDKmjD%yt8q4i()Bzq@q&GCAsIxha|*jH?=RFbEYPM z%c(7MoAuWbzk=c$zC(pDR7<$S{oHodk8NN-U*24pH#RC%@~aI)qHC0la@%3vh&UwT zg^p|o7NcLh8>_(Ii_@DKq(kKi9D_NGJ9tKi%1xgyiXFeiyrl7@{WpMNK_lgn#z{^X zSf;_EOv{oK8N{ycIET1TmLy89dIk(ZopG?Fsc8 zu2ZP|VHV2cZlcj>N7&E2vCK=_+m@K#!Wd#VFRVPl=8f>yC7<5Lz~@Oh6x)H_zZ05wPU2b_DxbOo zEx0N{IO8SDg1)KvqKD}T;l!J6hxYbaRc|nyK;8SEklI5o2#a+A#X}i+E=#JMLc3|F7 z)<@ocyI}D&c{s}>9V$CtRup>83bK$!A8B6+-&%RUs>tx9L3&d_e?_+#mR!0=f(vTr z!4QwMJrL9BKA1~aY^{~jo1hz^~9-h}k$Vf7~^!KdRTOXe}9HJu7hhga`F52-To3u*PmPkTBT zGgbK~3_qv6na;~MP^OmG(}m75Zhgy6QcFvQbtN{vIm5gSGR&T4)k~2re}itTQI5{N zPJ4Z9msOLI4!%|JS}o#M5z~=&8EW~aHz&U7%`O+Qu#)9Tz0OD4+TQZY!gU(H$w_QI z4caEG$KEv4@#aml!IgfJ(VU)`c;~$}fht%tRsM(d5`D6W2`I#I_K_ zF}c*zjK#O`kq(t{aP?E3B1Rf7j*dwf=}=h)N~9#36}3emJzCtt_h~wQf0bzKhw== zDb_LBt1fR1oG2CJJ=C^3yd5o}j8mf8Zkr^l?xNySTU>jRjbT%PR=SC2F+NS_9?N8O zvy6S&Z<+i*q4oaX;_scrNMjA%H+H+xjG8CIcZkVI)I51JGp$VoTiYh_OJ3u(AsX<& zvNwcijUh2@Rcwe77I4xKB=98-`vyT{I8vU`)w~R+siUt+UIFaL4 z2<1Z^Vzz8aRa>?+K268LV0ggE2N5HU{@WjzMN*_0!FePl5nS`}RG;Oot@^Ql`3dN| zNonuj)$xRO?B5TQ(s}=`hCuKq(;iS|*f$?i>G2;Lrs?QYEDgsaG}Qi8nhG8R_aK-k zc+8fwB%k(|KO^wPS8M3exh>sDvJvV z8f1CuL4$mvYQf@r>sz3V%^IY+80lEhKntsh+kJ~pjqZS?p?6nR?C!B_ZS2k-L%jD6 zhK|SXVpxdX)#wMES;C9d=8V#Q!q zzP7k6Mt9{i*aaw%7+6p>fNk7#SS)1>+M*_ z(9k&P;!%2Y&e70j#ra43NvtNDbhG(q`m9jd9{-=aHJNnP&^YN@It*=7wD)$}7Dj^) z?dlUOX<%Y}nzv&*CgY=?qic;X&9l+cZjKwX<*%{5rw>SwTU!5Qq7EGp_w|bnsifLB zCg_cqqzRfduO>|%O2d%rOp|fEMXn~rRin~okT+NJsWBW-2kT#r$*D^(k2DlI4u)oP ziyGg}W_(r$(_L|vr}gzWXL(Pq=H(0Oy7he22|ryUgA5*`>(Kcm)-^P%cm4O6Sd zi~O=hUDn0O;Q3j+nd`3F zN5-7ws(oZ+uG%6{9Yb@_rwG)h{fup28-K#zuJ+J4JrIAi5Npm`u1i&7R2$m8amEL`#fN6 zp)}6e!kgQ=&}j7Saj*-sDW)6Nk9n&wtP{j;9s3Yp6f7WaB~4py8PbLi`wd?2he~r} z-1|k&Mo7P?{hB?JHe1eYboza?$LS`E%HPj0lbJdhmW`nnd{tw!iF_UFdwO}En;sKw zxs1i9%$0e3yPj2AyK6~KEI?+VD^FsZiQcjRQ8~|7%+fK_!rm>uHQL%+`8uXgvSsQt zHrcW$fF8(aF1O`_VwhTXTfQq@P;y)Do#I=Eh9@q!UlWz>;k{+ww%p1Zp)cT z`Xc41!9IEuF!FzlYm&>)RZMX#jtNOQQfU;b-<6qe6* z63;FbvlANb;fXk0xD_RPt&h3vc%8gbRRCarq!hnm-%rEvFv_6h3>Yxv?@^5 z4QP}RR9riEzI86*7coAj!w9hj;=78Z!FL>FGQJ#Zxs`bxQ@>;L25B2u7V|oveCu=r zCv5}EVrVtop){&Iu5P*2jL+&-Zky)&+Om_1cwl-OVSXM(KQ+INs9`ZZXZ6MH|#{8?8#B~4?msD$HCXz=yQSTbAjoj={#`cJ8|-c zs(t<^h)jZyC`Y_xHvde7pO z^D4bBGQAl#>XmfS`=Qn7JBxuxn?CCxM5JAEse_-lEu(?(U+LdmzU6bctmrPO9%q;t z;WPQAX(s+Yg4VU=iGB>jIAa#$({#S~)_eysIWX6J2i{wK3w_3AtI^0SAJlXzTNi!C z5O{p8j@eYq>j+GammwjQ@_KFJzE>sTv`^+w?5_6JfU z3}7RS&wkuoX2MC(C<{w$+7nY9|1@%Jfxl2t!cLi<5SCaLVob+1x}Az*oGsx)R0{jq&g!t}_N4oCJ`h-)TIny;|i$0>c09S3&xB~<%%Z?q}ganH>wv;UVA#y+{2d9E;K zS(#62$F*@H2Ug`iu65~%am_5+o0iUd!bk7O9+rE;NAHMhv~Xn8#uForsrPmn%fv`? zs_H;!AGrB(+{DE%%itde zbIS+#y9_RCKf{!^Jsx~BP`(`Fw9Ri+y^&Y;z;X;XL>1G#9n-nyFqr&;*TANMBGt6i zf3l&5_$u!|*EySgGo8_YdNtd}v&hT3hq3#kQSfq4ACfApK>XNu{ zE=PVZv?a^{$2{Q{w_NQclJ zi@`aED`qs>U{1W*XEZQrGX{j!7#3nup4Ynz%KPl*#7KwAj(>!F&BRFCfm7ADV?HMP z-KH6}#^Xt+i7{I$@D3G!22ys_QW}5Y337q)nj(#8jaLrbItts!%^uNU^n2NFtQ@OODv! zo^s*|_Tz`+x%qZ-(ycF}w6Tq8lUpFf;bV`DpIv-YSmL>{5+nZsZ+FaAnKdjOd#q5-w1rzm>PSmU>(;@4yEHF`j?t#H%}d8y3MZDZFpQ>m*x2((e3H_ zy5S?DY{ZTEvgskR!lyBdVVcghL(~m^FzTkhZ(Zxg4W3hzZo9!s4#oZUVM#Z6h6Mq| znCEJABPWtqKpzc+Xm?}m34}4|SMeiE=ld83Z>yO8pyR>YI=^5Y*R9$nsoT6--9{vv z6m_B7VdLuShJ*FR8`ZiUHqNuC9+u8irBOH7sq1#wxc`Q3+~ogC(oIfbpx^TGW(PCs zj5l&3$H+L|)al81ljh(!@^tEEHmRp)VUxzcZgi_2Z`AFyTHUhoHp~RA9dD|ee6-&; zjyKAR@us?248e5TWYq0>^3PI#A1`=UpKl{k2mUeMy+nyc!Rp4TkUwGZX=)@{9vvd#+zj^ z-87vm@TePNFxPEejkju>|tvZhV#w^s0 z=?wl|HwpelH}d~C`i;7sU8`HxZ=x=AtJ80)8~ROt@haC%`i)skH%*6b@HtU8rK#J0 zr{DO2>71k+B6W#2@_yT!6LD?787DVMO*f4*WPX#m+vhjgBpr)$6dPf_Hr|J@k$$TaK#w^s0>73tOH<{l=H}bC=-Kys|>SkLfWo(_e zZdtzpQbB9hIBW&ejJ-^S4WC)^6GL=$;ta@R1Xq zO>we7@FNpe)x^oc!)w39;>GX|X#NM0iH;8ZiVju7+zhGa_4-k*UgMJ;imK3S!YOV0i+YVmGRDgI^F%hvIpGw~Vwk4WFGjuK7hSIjrwE_v zHM`~bCVZp-uzsLi-7xNN!{^IuP|LEoWm?A5Ub48D@Rf9)aeI#IiE|RP1EHMD2iEGu z)r$h>8F#eeGcIiN>xj&1^u|dLevbzKTwMG;3u4=Y8?q@h;VUjT`NSbjoa2Hg41DUO zCVWLP4%pQu!D{k}QAl3tpNZIPlzO!e@M+tSk9koqrB8XK4((gkVY2d9xsHOnmGb0Q zxsEFHSGkVDbxy&ay%rc^xb+5L&|RjO(fBCvNqpTh<0Wk}Ssj+Q^{t!0*MsGe<`*w} zvq8Uj;mrn}TwFIfMe3NfOO!=^oqF5>l!Y|(6(?tH<+8BNSg&JpVdNM%7152fw_|mA za)QbD^qcE3M_3)Eo0lhbP`-{0)@tXujElM}r=A+bGi zLd-(_WuhPdJx=sKSY@J@!AgGN>zH2ElRWjhqE@fW3HdOtbwa8aoRCcN?u0~6aYCXO zor|Y)l8<`9F}Yq(98Hc-e1*rNWHF3{pEUP zlcAg#fRMFzNWEmigG~jqLzPqB?qL?SLrdo*AN9f{?|O}Yuj6`E+aVX__Dq)qo0v|- zx+Wf-CPSZLYJwNzL=NcXr+d`5&!inPDDiaKp#?8`v;n~jecd__UZ~ekQ-8T$=^$Pi z$JcbQ)C8N<>u|`84X|7<1e=yc`^(blH=q|N|5?&YrtCu@WfpA8Q5^&c zb?lIwNM4E@@OeIWiXAeGVwTQLOV>*-fQVi)*RFdzq+U1F>Xj`HJUXfAFSfw5(Ba`~ zy<~BqF#+Z}=xXWQXpVZp*SKEmqQ9!g*T9KV^UsrB62VD-W&Y5Ex>|ooPUJw~=zd;f z9r#1lOM^&Hr(W*o<@pKm^W+yPl1E<~KVR(+sn<=ldS(7l&c4D9>nwUyFZe^*9QS!y ze{M+#h=2TXrFJInyYMo|^H+7JxsLjpJM|@rTT!{blJ~z(u{V zm~*{4Fuvr$ZhRD;BoB6vS8vf^_YOPZC<&fio--WJ9B&q9toQF^*!R`(G4qyCvYE1%I2AIi=?lNf1WpAeM{Q`*%OjDvpaIo>#sZ2@34<#a!eN;6=ANqF!jex9s@z})d2UdQwO!=35?gv5 z#sM|~S!cqQBK}tCE@FACFN87cquZtvBMq5$mv*b>+Xu1UOp}?kb?*xDIW`c!(#s=l zeDGAFuk)#CG!v_;_gP{tpUQ$*C(paXagb#PVx;YGkC~qy^udT?n^p6bVcwpXbf`Qu z1O3DGwb7w+{u7bU=ukO%QNl>0j}Tv)*&EHFH5a22kndq)q(kd{TNK5Wun*{AG|T(diNvIi#Y^gAQpZxp0JNtEZ9H0EYQH{fnDsgB z&M>n-+KCTIt(R`)KEuqely8M$YLoTci^ksTFX3FXG2F`!P#fG!=ADZc7SfVESaebd z`z;373Gv*mW;_^BQ}Q_CssPPlINpbWqdl2k$=$DRelNk^x`At9MHxuVfv7<##X^!^r1~V+U_lfd-ITQzpJHP zynPg-|H5G_b+-M;r(^LN^Iz8}MyYOg>4=Hl%x!ep5;k<4@!ibwC|3xh;iP@qAq|-^ z4(1(S%{Tm~7`uj%4q@OwisH-T$wwNx$uxBWG3Qf^V>eV`OUYMN@2hn%_y}!NZA;2G zw~3gSw>@N;If@u*^IvSMU|8j~ZzW$vI#e#$rzlQ-M)MjCzw>pJrxTdd=9kzXk#87$ zzvm^*n=XdwO_!6O39a|`M|uCNbr_9t58t4!0RCagr;(12;Po)}DRuLHI|A|M?8k_a z4&if0p$zK}(y*(mQ-657Y>2%j`+1K*I)v?C!J$(6T%*yKoe=h%#5zc`fBg}$m#{Y~ zy8UT;d>_XACVq}IZ}tqik=U~<@zV@9@@7wehE{sZr~e(HRdgF_zDn$FZWH=f9RurC zTYQArJhua}&sPmId!fx5W_C(jJjjzO}`#jMd zCI=kd;j$=Kgx-kWwu}xJcX;sSRqhbSa>N~;a!?z0xQBJ)`A}{HD0wp6;h%{~v$q_~ zX16CgX|B!Y4x5!v&u@>y*-kmXZNELPzmm~%k)7XWNJgn{aOpI!n%7)$;3`|f#?CiB zhJq%Sxx;fQpSq=UA+wm94J*nY!tgUN)NFbt4L!v5y}`Uy*s^L&!n)`-mA1U*(yHoR zUPqR@Yq7a(tEh(#r6a2A-5aiOw&_ON+=JzHnYTx% zLNc09qmQ{(>(FP?$KZFV<>_qy%}vrg6Yq9qb+oo3bhCPmhKojsJ9Dg-XEegPyW;d| zG+o+UJ0HS4_%TF;rPJt2jRy8;Q5;H_W^`zM;Cu3&o^_CBd1L2O59)5e7Q^!R%Q3hH zt9KeW7Sv|v9$`+!>_BY-V~dVP%cE`IO>CaomD>Aq!_59T1`M;Yp!N=TtqX6nUB#9e zW_HhUVVI7Owc4(dYeTlqmFq(IVW+*ILqmE-M4iu_r82B~YvvGk`Wl*q!@eR{SLR*grI3&5q4M6=FnL?Wkq(uowuQ-$ zRz9P7C1oC5iPT|vL!YH78X?UFvtdBj_%s`g*jhE1m_XiWnHi+lN}?HD94|!_Gi*jl zGn-u;2xTJ~N5Q*YrMbdt(t37utyN zA=knhY2&&YlOIo$)!4LEiBEovP5AtWzO+2lAz%ISI{HFO!TPG}$a~0@z;BD}U#YM4G59TF}P~+cd7xfBG!~S5KZX2Fgp7Qq}bR-RX!PM?Q zNJknN?A2{3$Gp5M?ComZet2HejWld%Ueb*;Ftsn{^?utLJ7u5itxk8kpKT%VRpRI2JUI@#&aZD^Hux9piO9*YHKI=P>W- zrB#f-{Fc0X+%(}94U|$|A(M9ywu9t$OI~|-D7=Sy9`hbd=S9dd6PZ^oMUI(BY>$2k z+XH((^4mQF|3ZwkwXBv`SL@x0+8GY&)h(UV&}jqG4o#l`I(3m1Q3%WCwOOq(bkJM0 z>Ox<}ZzVpd!eAv8!acZH!h94^o?zSKNp7YNID>q$u{z)kM8>-n#m0XkMq02C7Q@xZ zMgeKr{0!mN-w|7KMhJK8P#>2@jq9|+4VPA*WX~6rlXtTSjU`6j5M)5FsY#>G<}alxi;}ZC2Ny7sIwk*w=0eVB zbS*~H#!o4q(cIVSgqcUWUiP{gPO6W|e$d7$OI?Nkqi)uZVGWa0bI2X^)d=I$j}(+V zfXeRMYwga7zi+_gZZfUKf1l58?sGmdrejG4tww#07-`Id7|nfp5hIP?+1VJa_%Jcj z81-)zMZf!qkwzU_mtb{UqD|MUuHCLqx{6}x%RWihPIz`+x_+k{+jM`HWA~(e>XbiXDGNKGJ;DZYKt3`oP^zL%4qJJ6!ncD)Jw7DW5EwN;Nyd zX?vHZ=iUn6aXU6HiAo-!rY{8k(;sRNbI{A^0e=BbXCwGxjnMj0X{LwDfM+plBI=WY zOFC4hAn(+}iIEPKyZ?|b{gV!1^IhXbd!s`b26uSstD4tnTVou{@+@!VrAx6)T}+I0 zsQhJj%%szak+vCC4lH-hPo)YvFMT0#bBZehkwpU0ro_2TLu+o-kG_3SVyuh%9kd_%sXdhc?FimDKTF1vVtQ(9rUDsdM8ccR%!wu%vcut@&H>(D-8RYmb4CaN@P77~k zJ1xA`Fij7Y75`flr~Qo>X&TXu`w$Z&x)B%7U;1WIJkXmMY2?L>d^?+%kvW@1=4_Y_z0SbkSdV#0L$8yI z;?5<+NYfGA^*k|g1a~1i5nE$heSDtB+!O36OtUqtK4;7|jOrdUcN*`|Y|Hu62A|Bf4>DGj&~* zj6>Q4-em6lIIc=pP{F06Vl!2F&iP2b0-p1?s+W%XrK3EHVVVx(cml?;DKXM8`U`Oc z1%pdHqS7!JOx+I*B}ST4?h-RfnSPhxMKT$%OGgRc$LZQWgZZ=?%t^^$R-=5hL>8*Y zP26;3tmHOybDCB*py15R#_{M~r{9~|ICF0{J~Ym>n-H7r6yr6c5u0I}v6#!~5cI>@ znVQ#V^F(lm(umR-D6g{O2SqW7!LiY3Sj2GCt|1?3^Exb#Ugu1dfrd5tI3?p;j_xsQ z9Us@&Zdlr!U4K<;SQn)6=Y};pwOu|XUjR9-hW@{%yxQ5L*>+1u8>Z=@@-|jNb{4_t zP+5i5kez)p8iNRiv-oc2C5`e%z?inP@|33jtmET!ZJ%N7H4$Yuq$iU~Zdhr-Pdl8M;d(d&~=_yX{xy9AHDRhqY_>3O-gv*rJqiVeK#eI z#Juldu~#GB@L!JBHl9KyE}UYDX*&Ap9`v29oJbS9fH91wUvNXHTsj|pcL(#5reZ8_ z9rPV{*iK1md*7vJzf1P1r_Qj`zMF-eCtcmAE`~7U9Lgg=K66GSfqm(eUdvb z|AX6HyWG%bo6E)&*^v#4!9F8ZLfz)-bFJqysWlzjTt6y`9T6I#4~)jqjf1cq){7Wv z!-iy-ZGH8*Ry^}fj+dpk4I%7Kj5JPYt{=kt*E26^oY3qO!s?$8BP~1B zA*>ukj5Kz)?+W2Xcmc5o(z3-F!k>2#tZpl`XNxnANj33?^e~&A=Yxrl+Ab{$yq~kT z_%rL4FVpg);v-ce>mzKj=vU~?RB}rX75Q5E8Cbe_7}9u<{14dsKa?10zR%qoF^BNU zz46|!dbxtt)w*rp>poGpYtq>DzE3}sQ(nnFTt25w-*;op+V}6GW=Plv5xew(wEffi zRU?GuHuo`|k8%4JwLHeXdsw{G@#~c#Ja$%n zOl;us1(sK7mr1a?E%P7Q1Gl{GF}qIKnZ%g|8O@`5$5=j|J54{#SMoC-OHx4SLtHcS z=fK@W^x(r1Y=a{xXk4Po=+A+V+yU>`{-r4P`6V&ZxO%ZSW?>E%qeJCNEO({~8%%^W zZa-~N6jS&q$Y^Zld>^xQZ{;(ZYjgV%zF2RsgJGJ-vpmv}56;-+_q8Q!zZ^HJ(gX*xawy@UbP zj~HoU+q{>sZQhelNN^+nB1Ss2w(b(b!d(nVf$y6Q*u7;RDQsRhGIP)z*Y{ zQ?c8%$&<=p7n{5xx`gtZG{t`}X=B1Ri;^ALo<}xnte&)WvFD>EOy}3l9{(mLUpIUF zTTHVkwzRyYVVY>E&2Lpcqxqe8L(E4qOco>F+c0qE{GgSXc+d}8X|Ao9k3Pa&+qQ!4 zo^?wX=H*_f-1f}E^YR;_4UXBauHOn|rw!WL7_ETM_3wHe|A8G-$bTe+CUj z2JPS3MA_$xctke+yk)##o2{xhR3Wu}@kV-O4!nwg)zaIvSXJw7+AWPw(=lj&jW1Ix ziIK)Z(|@LcOd99LU&5fpmogckq%lx2$n2cA(MUu2ekFyp4P=^}$%R|IkayZ>)=SzB zbI~#IVAn}J%*EBbmt%ub%d6V~ZOu^k+PYnr2BVu{TH%*p=b(D>l#ek(Ec4|Kvj3{N zgf&m$a=C=GPo6?em<}_F^k@l)uitm^UKcfGIYjGBR%GeH#t- zbTUIdOE{c!$0(#rLol7;h+o2%&;*yTH5_r%lrZIF#CQ^#*hf>NX%_QFusqLu2|S^n zmn4mOqI(g~OOnPs@dL~g7|$XLY0M43!94L8G18&3>#68an>$Ezo-jRho|renn?v%} z?Uc5rsT+sgu1}^Zjf{CBTS}B)rHTE#UmMfxMhVFtD!ZK@*AqHVeBVN(pIcbNbj%5Z z;SEpLyhig-h^;a7P{?P-!rL7sa|roJ3l_rfe(RXfFwIH`-#?ldY4MaHe0PZPDNS?z z{@a4pZJGbbT=_A=p0gFNxsuJ6O)SxCE>4F`+=A1+D>qkZL^-xA@t|+Ps=4A;lO7>% zRAnq3Ch|T`mfc5;G_l5SC#(_XuOY<_#7LvOAEAHSls68`7(bvwI#g~R89#U!9m0B- z#|YkN9)h=Dgx3S{_(k~8|7UT(&1epj7M;AErnwTU+bM0#b+GP6bxSYBl-yj?N~gSn z=6X|~Hs*@3LI#$DAJbv3yTM#9Rm^A{PeWL<_jANZ%fb(X_GMzE zVTL%(82S<;P3)HQ5_ZdZnCx-F@u#;~dH>Jam%v+DRqem$@-aH#m>HsgnVBQP1#w1H zAccF)DMGs;pk4t{M$Iun{cs3}L`gx-w3PhB)b1rkBs4`FK~qyhMN<d+qT(KZIXnvRVxjkAGK_q^sIm>t({+_P8kZd^h1V zD3$zhf8pp`Avio4PWOF}ojjf51hH^0r=*R%pXs=7sRh4-C6v(CHOHzBd z0t-vW3#pBr+Q<0IH!@U#r}KT@q5^kn?^#qFeV)zXRRG4Og#aiM_Rn`6kn)A=D#$F3zLnaweH&I(_zI2j^BX);8E{B_^(E z&P=Z}Vbk!0jdC}b<*`0IBLqIii#1`sO`1`gKU?IOJnP{nP)S=lE6>yE`KSKnb?CDc zONo)j{o&ov>LaRPD~Wk|2i}BsVFVoc+YV!<^Gq6@^Tfm-X|&aJ(Jaezc@KrWKMBN0 zhcN7-EIa!EVx(bC-_5e=&l7WAc7k?Kw(>}`4H|DP&pWa{%VyHG2huEW4s;{!T!x{G z31)KSf5p(@&xnx5vn1PMqKavfbY0STisWl(gQJO&=Idnko`AkicE)h7YuF{-n78lY zsXWpgwoczg%hMt3^j$b?o%StaGHjiOPj@WZKb{>k8XoSsEW3IZ(>?SAdca-PF&W-w zvrTn)n~ferdtEDUj`pJ+VA>}%@57%5eWDHYZv1)EnRnWUig5w;R_J4Q>_?bB4!lWh z$Bs;y4XNF&wEOFwcL{R5rdZSGcbK9UDTX|;B>;vRwiuDD-rVb`H z)%uKLM;oTPtma;Iy}grtrguZQS8<8AgS%mIxQj0F=J;SogzicHZywp49^xAwvJ9wR zCY{WUE^+6$P#<05kV^ko7i)|zF+Ipsb0KS-c44fs=DE; zF-y;MtPef*s%Vi$hw%M3;WZ{R9cc&)uQu(%a_rD4*w&awj5J;ic?`XGI5E<&0m8(-cM9iS)TB&2CL;meo z5=J_-{Ch+2hp1b;B4RjeyefNc3xG#u{r@FuwZvUS)m_@5svJ z^15r+@@qR<+lwD>KszG}n6rywe7&W!vq4M_-Qx4UdL^QfYc3ki{rnKGRnzHcIt`D; zv(ALgl_<1Nmi_z?#jHL=K3M0OHHR4K5Dq;BzV3cvq|L9LS&r?q8vYOMBDPB!J2gY$ z>);avBTe7bxP%zx3}Fmpz0vvtY4c5p5F~H0-s$fX^E&#zlIkFh5&kBO^sh3VV|&BS zY>O_C4q>xx;uf9JIE;N;+>SGvn0>5Xv6HbCEvMc693g2QP&R$UbkEPly4Nt}B_|#7 z<_i)=8hsj(o*xk=9rA;b?Sxw9C5>kl5KW%2DKXNpjqAij%P_rkJMuxrjAj%zc~@c* zrA^+|q9%?#8o3E3zs;oIHJa(>?x1-YT`gh%bzQQ}ExNL{SHFRUc=aWwOZ6M?o8K^9 zYTrN8`o7v#wZ5;LmYtTd?{`GsmuViXX8MgW^2x@KsZ$D{?Hx~^rl!zDGr}CEza9ga z2(3x+k@x+y+Zp?QTFr`m|D;$}&2sjxMgLpu`W5{cKTkrRJcJl&>$?zM`junyc&w)*jsA+U zb8;7^BaMe0|DI)I`V%9~{(Q>r#Jt|q9?!D#RuLo3{ycq673_6lUT@##R4-}v=czV! zIMxsTX2AZ;OB(%o@3_fiH2UrjvCU8aWi+vqKG3|1orJhoE*$uoZqlxU@^pVf{O0|S zbjasGUh8W{^GOuPLqRc+3djcehqoA_#1g4jeXi*X4$11 zDrPkM?hR)VlYV@|S?s%apr?q=W$Zm=ckd>|r0-6}7%i7cyq%@*PJf+!ce?3Fu{DO7 zF17ETWPMlds#@RGo!(AQvhQM)iGBChG;Vv}t&MYt%=>OyX^9=RFl&)j%h_1)n~?_T zPjN^b4R}g|Vn-dG7INfRR-X_yxuUG2Vla}1(vFHL;idos{h;Zs>A3={I3(z zAVxamcl-$HY!D-j_ju+5vq6k>$ghC0`hZG0SlenHR(8mn8sk82G?zjAtc@&*;9N~E zOBs%l##Ri1h2E#LJks1$il>+12)BQVOVHn*QI@Xdv!}2;{eogfbIYdtO~ho&ru$8y zWf|n^{vt8bc>NSZRXC6sXS((EavKPba4#i@2A=MHQ|WyVDpL$L;7e(!xW0 zw7%d+JlHP``0ht$#-)yu`;i3IJi{*h*@Q^p9m8i6y>v~d`-=IIhD~H0ESnC(*Nz+;d}6!>A4oHukG!7lV0iQiO)QVJb#ha< z=RFi7>ZE@&9cefmIKdMjpEx1Xc&igp^T>CIk;c27=uAEWl19g$i@aNDI-}9a-%TSR zY3umbR-X6l-^CF>CyjSNFN!0+(Kr$D0QTfDl7T;?u@jAYyU`&U4SkH0rL6CwV=|FDNuj7(HUtnGG0OvUaoCXKOIff5iQzlixdZ4`Cbs1d^?}2`wCl8 zC%=c^TQL8BMpARTsj-XaF-(8=-vs-L_(w_Y?AvqyQ{eu?IK|Kh7>7tp#(+Nxv||h{ zWCu>S+XfuuV*AT7vfCzye$WE(&=2X5Ke`FJ2gg*SL%!q^jL{6hjJCJ>=wGdzkUzIL zbtBT&JUdGBcsU_|{xU48ok@%|^ZFYHl2_h1&|SU(Os8)H4z_m#tzP-PaYu^TXmv1; zi!OPqt7X)L@uxM69Cw<&+G&rs;%g+QwZN=I19*SV) z0{Xc?8mp=QLJ&Hh<&n0aQLGcPIX3cqtPb2xj5O2Dxw8s(4Kb0u5ks!-#~3f-tEN0c zU*&S>iUFQo)fEHFtJs}}SsfZwyi9Dm@h5dmF@G4_PuhF{>z(TDta>nPxbRoqNE2H1 znV{;A&Z_&nDZ0OC!fm7bi;I!z?ewxoXWN3aBVaw8>luwTHH?0?7H+gzz`JZ=ZOwPB zH5E(zuZKskd`(#;N;fOj_|Yi~XA9zr>(Ug2!FhUrm|B8Ft71H4G;H-CwESSEBaL)o zCrd4_($o{NR!dZT<&Q7wrt496zRTRB<^6_@)#ZrdQADzcG=#A#`gKgI8 z@&mqskjoN*KM+FNJSzpKmxX85!9uZC3mG55ZbbXFOSeF>v1mhR?3B?-Kp%p4jegDr zWXceFm7s}n)C6fndB2GfozWqG1|^T4qv?#MfQ`En(_vy)3P|kB3%Ezas1cJ!G)x+I zn!VPUE_>)*qdmd;QHKtw6At8`3>t#{=+FV$#DYOQHBe3KzYA8Ky>*OOGVkfwp546- zMl2aDq;qUuIbuB>HyWY`sC=B8nNi3mFfaIYWl?Fw+K4Uv5ISk|056oM+iBbQNu)rU zpJa(EcZe&;^hX`izn-?dN(0+HVd_!vIJZ7AqIFbnnuM;?Pe#)$XpZ+;(@D&zrR4?9 z$@ES%^p|yLZn^(1VkAb24zIfAMvUB}p~dO9MD1`Y7kp%x(%d8Qy%yOo znS3#4es)Dc_fQ0reG`Ahh%~LpBa<@BMoceHezT<5;bncyZKRB%9sUz7O_dC779E9~)%I}~5w|n;i93?f ztP0lQtEB1hSv0G{R;HhTOC}mOJQv1=Q;%bH9bV{DrIkj@zw+MIErw1EE}!ca_H z{5%+Gvp#EimIEt29F{wfc}X+xg_DU%-U}x)@AS3mkhKQ?#2jg}+@qPd3{wqxeOO@K zAJ%s)(~&mKzh9oWFGe`~oLnG{TMd6t>m8)c!uMg`GHiQdYLPg_qE=eO_A$)zszt)8 z)FO>%#f~=2WK)a8u9+^P8P95wuyCE%Ydf!xMT!IL*^3^qg?8Dt-~qRbu|hP$A!z_} ziz}R_bn_}~v&}PGNxm)X%;r%?wjF*R2Zv^%B563N^Pwtq4KXj$A?$_!H`zKOX;b}( z@^o@F(9?N&LpzB{F&$|$FDs9EP}iw2FV2gNW;)*x@pQ8BHM*YVkv4M}LQGXZ#MEq< zs&s^@)Oc3)Vbev`SI4~C#o%~!Sw{J*uF{15{|vc<8}{tmFmi&()-HVyR`rUp^_2R; zcq^fzV8>M-Z%>gWDE(ddO%}O!o!* zaV3k2$KR3vt7nl>OM045V>w}Gb%90c9)f+k4i;DY?_VX0MJ?Z-n$UQedP;#mnel+X zsZ*-+Hx=urY{hgDL%O=( zGhJP6Dz6T)k;vrO!-&djF9KgX;BO1lk#=4U)5ZbzKJs=nY#Wi8>FQP)roRKz-^#K3 z5p5g@UPU&RgEt_K!iP(5B1Srdr*^^Dv8)c#;91*;=~zw(fA|z1RDFpUX_Tw-5c4{o zLJU3db7G|NErE-0l^r|^FQi#V-R~`(@({w(r?5}|Au-ZOe;L|a-JsLVd(cgiE;*V? z_p?sJ?88qXxBDdakeWO2J`5URXj2^W)JVn7?kU(0j91$ea*Mu2cXi&zN(0k8OvfU@ z@4G1a24bY4i~nTVAmowqNVARY3t!saM{LA4W;?Y;R+IE!lvGx;z3(lEtJxVg9>q#) zQ|wqX$pmQ|XDJctnnHjL$iDXF1;_z4MRQd;g!ezg7g?TQI?^HhbvaCPCNa_>yo%|~ zu5*Zy22*zkQ&xwS_uz>zFPM`yo6@LP%)f0FtSd2=<3bW+9+$F!Vb@btsClb4xm`Z0 zFt6RlpLpWL(UTf_n%`?^)X1u%y?(tRBCCUN4)i`)?OR31cMoeUeAcK2M-I-Kh_L9r z*!*qm*x>9V;wO^YY>(5YIJLPreMqT|T`ie2B&D*CWKU?5pq;Rpcs!z{kRba;T=8%OOlfk3OUf%G9O1r1*OcBz`6}F*ZK5iS0uL7$X(8&Mki=#@PmEF$JN`~$ z6q6Wb0)O+-jIR?T9l~UIKzniAXku$@FF<}@^P*y!nlq@hS>-jg)u3MwPhInPr6mH1D(5NZBh`OAc@{3ZF@?ZAkYb~}*# zo&7j5;qUCnLpW(dR=VMCVx&VjD$h#uZB!v00^5=4oR`BfBH4+@KpJm=Ac>!XB#qNm zzeyNrKCa^FXfSXI|&d%+d1Z}%x9#x{;>IB~>8 zvFCQL#!#>3*Bn^u(s1K}-f`PS=caxUH8=K(`>7F1p9+s&@vW2!#cP1|d4#gfDUpo5 zbr_UZ{3H!Zq!DL42QAp(KpMqdpJm@al6gsU06Gq>DLuvW{&Ii$#27Ksu#)5AC$x+X z;m3QWbCRUl;`V{$5c8g&c$uKIrR&8yyj~f^>MXAEyttQ;O?iOnNP`y)jx(<%M%py} z7BMO3I83{x*<3c!eq%3cztQSd>C@#`li~QL-_yv9O!&^Mg;~LRFj|42$cs5js7srTXOH z^th%L=L<99np(-G3w;hqWjS zQNmEs%g{9mx|5Bw`I#|en@vM_@rM|4%kE2MdsDw`+z`&*HQBxBeE26Ud$_n%*z=2c zfgg9EtR!Nu?*z}b%zq=sa$r~RG(UKr7-=X{?B=kwuz~PC3(RoA#=SS?#S}oPF>#nVc(vY zGeYm8RmLZYzEW0ex;5+2e6Jl zrVquAHO%y;{Smx~e|BEjM-8*SDs|MOUkZP2yOM6&OHAkegSO*tit;O)JI-*9O%raN;=CoZivs3zoFfaE zPjWgIFq`E}X25rV>E;}nu;b+l31(>%7)EP(XS5?WrEN-g#)iZuwO33- zeyM{p5tHeHV3diNgyVuyCSv3tP8Tz4zf4J*-+(?Bh6s7}d(h`@!%Gk6uoLN}hjVbI zKrSm7X6>QVhIkPZ(+1GM5WK8;i1m`z0U$a~3;>`x4Y_s`rju#XwVQ-+;kM|UD~XZj zlxWcv<>^kEg>)|wBh4w1r*n*Lq3Mi&UaT-V^kM~M(-&IK{D!8}FBP7BY;{bg5*K!3 zz22si;Mk8pml$cb^D$^Iu_0;aV{q13zOQ`@oUFI=F*u7ZmrIV}^vr0svt!cc$NZ8! z8>T!9CNIex@r0JAJRjY$Iwm|Hzg*Lq{=o|(HnRhx!OMdQBMn|wCyX?wVwP8@Kj$9G zdM7_kUWBj7Pvh$Tb#dF!XikaF*pTV?yJ77VOFFs;^`6Fbe^(lHz*g*g6h`xTfZ5Gf z-c`5+-OTcCJW4T{2CH3R3SU}i&Y5%wr)>!v`X|$oMsUApR$5>fY4m;V+mdemrcR?q zkL0qs9J?Anc@qB5q|p;j9Wl07EtZlRrNFe5UwRVf#oEgz zjNg~ydwA>#dhopY9?v5c`0qS)-F%N=t(2ni)P{*?o;q^$sJ;yo8YecMdJ;vjFOg@O-KYP;k|yW&9LE^R(ouOHVLe)5QhMg)gMbHlG{cm39xBUgx|o=h-GrmE!oOo>^;&t#!!)bc>(FKh`Sg9V zY|gDLk2F5{@UtwteE~7j{LF)Y%S}G{Am4H$@8#)!{J&YY1Z9h2N#oT0kF)IYkBN~E z`3$)8B`*^rjVm~RmU4-ahEZrc3f4-aU^w80Ed?#)j1X2DO}g-5tEU)W6s}y$LV|=V zbuYx}pTD4}{Xs5Y!LgW$YgCRef@l`I6{}bs&N8tWVZ!r-{Q5VuZ2mH0q;cyW1KV$J zAVwNzs164RNXn0vTDZFMGr{ew6?A*8I z8se%;oOe%+$3NpFdup7_MrdZ7QO9|Azc{~*&=GNV9w){h$5g(TM|RN~7=lj5Fexog zn)@n#Jx%slPC!hq@p`}VbW5RWTa^o>@x1??@%d$=+2VYD*?%`J*k%Uv7&eu4czN=- z|A2(`AHZ}23h5%&P@Znl!Pp$JForZ&`Fhf)=_+5(wv?^U5zH&AfDto!DLdy3jot>Z zzyS^51)Xbv)hm`YV5(uppIVz?bwz9@)74oU=)9z#%}WaP_Bp~Z<4?-NQ`%bZe}B@t za>X$Yo5dlMM?teiG-#Y2(2?a>c=hxWed*qi-_OZp5u^2PN3z0@0T9;r| zd-Q+Xc&fGUyW?dLh@Oe~A}hYMbkrkpwXKazV|J8j%v$eHbdY*IIsP7lY;zUk%01SF zn9tJb?;-#7AF&JY3Ng~~oPW+ra~BgM4bOQXu%EL$(kQPJR@bpkC4H832**Nszu$lu zY1=ta?_9NA*10MjZDd?ei=^`C#i^ zNqjf!W%1^C8=0}=O_(n9Aa|1i3YP~KJv`pAsf1^ZFCt8vtAud*l3vb zp};r;F*-;&3ra3)jnxk9g*&|5~3H8xEn|@N9=y?3! zRK0^X;RBgh^+hJc^Ww{{#I(2xUjftDyonfp_usyR9AzC;kA!7#h3;LP{mY}{E#0RJ zWZ8;gY1}cNtAbt*KKBN{Cn}%%ZrBRMD{>5Q#W3Stf5!*pF$Mqa`@~4|Bc;FnBlF4! zOMm;v5Wd?DQSArBNMr5%Y<$6$w@)Fh7_6MWeX1Mk#TdqVs~YEj@3h(^9WkNy zCK35BN1^+~CTSx}Z@aIv(^_(zFy21PmhVUYbVnPVmidVBcU^1G*8H9r*4;q^do7E* z?4*JHF72|D#?7|nnC8F7yrlKLw9@Z6mz4L?K--S`GD%mpUH*Hg9W{1%&*Lpnc`UWg zAMoVIzcCFgJmL38zGSx`y+rCBohgyy&&aW-GOdr_E!e@c5aaJ5mxtZ2TR@C-$j3jB zWwUIMCLQvzeejSBf*a{Pr169#)=lm~a4i^VKESqM2f8aS7>FnqW(y90erISs51D92xs%PQqI#N2)AwLgYV7{(_IBjlE z)t)f9sP13NCQY}p;AoathS7YjY`%2ittu~F+_TzZhDFS)Zr0tl)hq6-c@d>-wse9m z*v}=mdIdY$Fy*C{TB4~k_;|e1RMUHFqBMDQaY1?^vdmN)V5(SCn6nERl&``p*x9oX zl zRMAumUoLmMd^XOOYq01e18LLKakd=oG98qUPxq9wk>ruiB0bich%W0OY`e&J|xLCW44p6%Eqk z`R_0>#JSC~u_flFG(Ii*j$ov*YF!u$mzO@(|#9+W~qNud!@sDw*VWx<2` z0_*6sJmbzKc~D)6+Y&M*KO2pAX`2sxEE>^Oj+QE3syCmBn<;qnXa@II}DIM?Yeusg9=Ct6<<&)aL2V z#XvaUTrX+nExP08(bgBNUUlVg+Zs(5+;%fGpi@WVS^LaVrfaf#6?@$<<4@ZI*M%kT z0&4@dkzv|aU#cJJ`|a6NmHp_DIN^%@sNnM96Q!}VA02|f-O-O+>C%tj^0gnSJNDnv zcSgYwu*4;KNu%$akA_}Fj5P9U8G^M^xa7(ypgk*u?jQS1!IgWT85Wlzd~MJHtyD&zJK7>%UV%8hD@8e8f`xF2sW1b&m+uw`&VLaMa6VYOPG#j z!zJtm>;0S#jJ;@_2SE1 z>dRG*Rw|R$t4|qcn0fjf*{!#K^0RKecc*o|qV#U0rO+!Vbo+w!UY&$?>urcJMw|o|p7@bP77T(- zg-FB=`t2C##7HDv!jJAaJ@I3=QrV60!j7tGH zX{Kv>yF8s5(<9}W4&=itF%M3>UNvk4P%>tcHX}ETWt*W|9g?mI!35ikdDY0@W;*AO zJTTn?<3-CGXyvKAt+WFgzP{s|J(mpsk&vIbJ7$P4q(I$5p*d5N+ipvynG!jmm^pCC z(g?!foT+4R&QwdMzr*l9g5lpqj5PPs?Y-$-_R?>>-OG@4trRX9IR(VAE9u!_yCl*e zs4K4TxRIxCC`2Pq)5qww)94k=H)VA5WfiFEH>he)N~~(ffTn7nM~uJYbil)D!H0Cn z)nu*vlV-~_4`E(UC#~j#9BE5ub3jjb*&mbNCe7s!pAyOPhn!>}pRB{vT?&8iu86dm zyYV7Xg;`KbD6<3%x~Q%uvfQo}S~eabfb6Sa#ebji*4)#Sq5e9wt~TTi}R zjFT@{#>teglBh+a4Nm+f^aj@)EgCEH!tAXB?m$_H64(4rTyClnJ+q{svwp)H$E{Y9tZCnzu=dajDuv|0^-PM%!-Q2}GhzM?fzj<}*o1;K1jdyAhF&JH(#Sg_ znJ{S+Sj+oT0(0dAo7EnEf&IaogZ;vC5rRTl*}UTTGzyu(Od0Y)IN0gSMH1v+alB`t zApAY#-@~%u#>n&(u$zgI=H%h3nZ#uBa24K&Wx0ZVDSzcoW-#8o482IwNxXU4eI~G$ z_oW2pOzD**@Ix@3f8*WL?kUbd%q<$evam1Lp3E>Mz8E_mC)LqUg+UScO3a6ug&2Rw z+VvD1N9|3FbjXJe!hNi*iIEQZh@V67VZ=yN>zBdgr4G^hWplkQ!M;=@FyOXJc`)^o zH^PpoUwb1oB&`=4VMjE=l#!b@)?Mmprje+TJzCq_EtqY$Ur!DORRo|Y@=zLdZmhjBmLotq0>=<6=< z=Sl14+*Dxn^}R7^_P(x+eQp9HFcVYd?+`eLz-JI64S~0Xz#9-F9rA`1$(xflfwjE# z6IdQ9#x6X!5ZmKSlS}#n2kK%cm$7>`dT!zPs7)qhpq}0x^A3f4MFbr^1s zdseQ$mqN>ji^`oeM&?1!!W1ipVM`fWKI)tFH|SnT>RFUq`#t1c_D@clbjT0*OVTOn zkPo~<^hilbqdYCQ^^)rN+x|OA(m$I{cSt&QNekmIJu!8P+fS>ufKGFArW|4X)yCoY zYrjLM2sh6)OC=rh0T4JXc}JX$IGZhEbjZJjP|Y#Yj3uWZ z(0ZNf=-M8)1>JgIq4iEH=+vb;B=u8DrPezQI{ok$NvA3me6KddAu5&q4(t6^(kbbX z*TQF?eL1BkZBl98*7ZppF5B;#q=MfN4HTu40cAjWpR|~PDUoB3B-P&FT>2!ln6C8q zkne|K(zSluXdeR~9d47_fbjW+}l=>uTle86mG9HZ` z+OTIoXd%nqiPGwd>9JUpDWw}azSNr5Rf{)_7L>3A^LE<6BF&|m;;Ld3RvL8~3Tf9@ zH)R}S9L%zJ$#EM*w6c^2j+@gf@$oQk+H#Bg+i3~e<2zU z%b>FP#}FfJ=@3LnI$f7KlEO9@F+^O_04#6)j59Vs#R*EeD7FVrQ2s4x@mGOogbN3p zpS0S4RpDJ_;jph8BcCDax?*I{t2(JL)x^#`^eUXq08lOWGPj^R`mhaXoRy zwV{`kisQG|A9a%o95-E@EOZ%|zZgOkWcwfTBC^R9t!cO8?^wf5k))o*F#SE`7h{q1 z-ouEIMmkL|SgYlbQ?6>af3K8dc6@9&+HGNPqA15~@bX*8@dM*oX>9FcvDeR?khZoT z$aHFu15KBTeK|R3Z672_rlV}}8R^yQC`n=45PemXTe@F z%w+@C2Y1$J4yj(bv!>V)2|I3UV&2Z$=D1TO>5enms4sgrL-n?Pokb>0`jV>LF~CE) zCyt&ldQ{KhT)kZrdw&TpM97Lj;p3+zOeo*@0DNIUZq$cYx6u9a{c!31%8LBO#5vT85-+rI6S<8aZ~1-5NI`|5GVs`bwn8EkaH& zyjf0brjWNn$S2E%oW9VrP$2#uT3);mLelz-hLCWwHc2#^Lh>#0uS7_$&9x*U|77!v z+tZ4yK(ism;-pFXan3}r?X&SSm|vhv%ZMtgP17(TV-~~ocdSnRFus0mw5OMJtrV!- zG$~N16sWLRC37eds9>5!fo{Ri(AovB8S^600MBBW{?6q#d(JzTU*)OU+%O<+)o>a(dgmgk#FW*YqWEa$dss{nWtHe7%J4gnoz}r)iI- zRBncaj4Lqb#b{Pc^&B%6i^nlJNmYbg+o||$YZcnq1>4h5t~VGOXZjN7o9UzP^UdHR~X4UDJG$WABYbx4xO_NJEYviHzlW zUwJ;IBW>kTUgxjn^V^c&BOO}8%9NKhFm1=mdR>lUI>XB3C4a5#k>!3=7gaG|@+p%V z@FFxp!Ns^uSGX81OWlq}!@`WY7&hQyGbWCv_Iqgg2j;`pBaOBO*L1BEsNBU+pf;5P z6@92t;!(69RNYZAm0|aZOhRRKj0=2Ic zs4#T9>njZ1=F?Q5TfsbHj-o&qy6JDQG$SJ&e}_OA-J(EBQ=qSKnARi;Nh8Qgr=SAi9qLuLmkWfr!?Kt_`a1;rzk)zYQ=n;Iom0@o_mWK`u{czc(H35= z*oS02UPkVUK4d9F%ST5ilha`WAu+R1ApTCL;2IJKao%(~g=t@1AEH1TB@MYig+AmF zMMWQ?KnQ<7!UV|skO(B9B?gD*6sU8hKsTm6Jli_19ET{- zjXV}sCJ=V9R3JKqyfYkz3WV@B3Z%3N^wl{9-IgnDngo&{7UNKHqgi(9Bx0@ba+VT5 zgCUFEH4Kt%IcAZT_un}Vd88oY5Mp;r|0Oh3J`Pc!%_{{eggzdqS9m!JgxOVw{@|gH z4y>46>A=d+$A0HH6a~UKqx`X>FBsP_G(lMZP0)YwRpaz=$QmrT=$8?u#Wk+@(D9jZ zajXU_l2T*;^yz}Es}$)H;OEtlWIi#{Sk3wf>#E`@kd8Fc-2qw7EXU;aqd^-HBMqju z!OGgS@^nl8idCbwhAGYRdcR7{>;2`ovh3I%#7N_D&dcB_Yz2ul9{0nf#lB`~{PRt& z_;T$<>E+tvc4m3m!sKD;#VOLPx8CF}woCu_nAb6B zi@iT4MmmK1G3_6E7%|dptNJU6N&EJGmFn_#5jpGewwSyi>-Fji*XB&;awxX5VJ5HW zq5euYCDy@qV|m_w)R!Am;-&sfmghQ`I{LpyjPkCZ|6Y5^88x*_Cjo0@$@W@s+%qjW zPv(+c@526|*$`8P@Wzg?wSMH8G+xWD#|rB`#7J`$*T0q{tGIoz;wYnEFiVyTb0ioz)`cNNQu@20pLC{?_hLcg*Mt&FgHI4n`DRJB`T%O6)VOn>*^1Y19j zCrxNPsR0M8brG}OYjnyQrmY@aXK%X57Lg)MPEpIg0J zwsTL6zdQSawXWfG{@d<#HXNoHrIoz&*El(?8G6Hg5U=xT^P)2keK{^8#_#hmEK5Wy?`x8%ENyJDr~t^xF`&JUWD*HC0%4 zVRJ5OBN=;}jqsv#pAatkaee=T53UpT<=iWB_FTjs`BexPuQ2Rl z%d2@p*ciKQ4?IPTbO`%D5W-)~jgiK~=`g6jU^tX|Nz1Sj!UtyWr16;gFSG31-(ot_ zAw2k_)b~i6-gFDp^Mr5>-27l{gh?HwLzpr)^+(d|x4s)m*+c$U><3;^qj`-E`OIw- zMmpqu4^J5B(DGWR5N5upd5sP&590CkpDrgxTHY*1JB}bmITST zkq&|FsOhXdV3O!YP3$s8!zA&v`S1Rt>5PU+;;Hoeo*+gVUmf}bbYQzyq-lP4btf<0 zE(?F0WgD#~MjG9>2cng8h>?a#!bKj|ix_EkRqt-<67h`}F=uZpF=sJxafz)t5U|!q zB2js}H&ajmza!&%;WR*;-E1BwDGn7s1?iu#XKs83Wk;0ak%ElQ7_n81RTP)Mn;BHW z>epvtP)cn2ED4*QCQH0u2GQ;NZbN>+&OYOd9eh zQBl(?%4q%shUDf2o`)EJ2d2LX)_>?hz3`_a9yk-X*a`pr7$5S)#@xP}Mh}u9(3VeF zbl)jHW1*?=CiA}Ov5U+<%d>k5CVqypkg7*vI_XehI(alx&0mrxipLP@HZRs#gA*B2 zR)L8&Ukmx3N8vfR@(RzJdoBnI=P~HkOg>^`zbR&ULgZTnW9RbnB=5eMw#nF4EU$-Ijbq=%Gk9A=|B{Y0G=Sr!UN2<| zp&xcCPvDqtG}3>Xl`b&nMmmH;_s&W`4lIu}%NxHtF_wdGCPVSRgmFl{q*2FyS*iJ5 zOQ$p(9*zy(elRi8Y?t{<%CXJB^V|!Fkq-IqUjz1i#f-*n5WM&~cQ<0BLw;}{d?xN{ zVx)2I9$my<#WdRW$2!2 zY9cfwF4UB~vuzZ+WQ}*WrkJtDJKO9^=X z(eR>_yQ^TciFqAr4DhUC^krBrF|W7pgK!3xmo)3xx1l`m-nfI~-((~W{{9ZRtq#&5 z)ZzmWzk7yxNwd89P384|7tbDSJ&hP?w6iz^Lkq&vy63B5NG16FaRy`|byt1=7&!U@s z@rt-~EN?&6LoL&dH`%Bg!>s)zZx5_FX{R)K1)JYQ%-c`(Kbu%L)0<*<8>Y5_PAS7_ z$9vf+Hw5h?V0r^QcFKL?>o~Df7S7#DMiD5zp%XjhK5@k}LIdO27W--8(4cqSzOlyG zb?;8S*}HC2bQW=(O#Y+I*F$*e#EP!#{!9k@4KPk#6UWK$65arpkG(M$)%Zb^c3u08 z81ulq@u1Q!PZJ}JmVipSnJE{s9(~L69&mP6>hlj`q?vc$F;y@d*StJQ-{a1duE(9s z+hc2Dp6*6n3{z5u3t z==ZXce85ifl4g11*TzuqnDI;}^^O^D>8xI_qu=LgEG7-t*AHFtBjzOyH!=j>?+s$4 zF?QqF!$NZzq=9AVA|siOG|IarEB)r*R-V#qzxn1iy^d30J@Z~>I@0*~^ml<_3tHqQ z9m1Q#!OMfhNQdw)-fHy++DT*brMAR$t|PG*cMsG9+C`#HYZv)_-+|yydYHATVq*+5 zdr_CM5A%+Oj`xMUJ+@|Ew-+g|M_>fwo=xqv5xVX1TZ!|{NvQ?VbyB{fhJ=H^i zh0!NPr;+?y%}=fQZ;pJm**fId2w6Mc-Vt)a1}GQ)o(K89ZW#L0_^nvb_^lMnm*YUH z#NaH6*t`2NEZ}dJSIgm$+_f_?8J@d#MtRatZ!S-VSyAlIq%EDrcjU`34_mB`eIA2< zFh4>XdW1fEY*$`y-#4<-u5F2tX1aYxSHWz!@_OarXnAB>+KMzj@;D(&A9++7zC*&H zi|7v zdNDson!f(770fGr_pTLegZT^#tn3gZ+?aO*(~%DOtI(hM2ctv2sxJBmqeD)6VBVrW z+!v_+w?`X@e{fxjO;}9d-E=NG+;<53~X zw`d=(ri;SrVl zMRI4R9#g1C;Qo9kOxJ=&*jmsCO2OZ49Z50rmN?<3fk%;*Hdz)~=^LGC4aR@5iOnyJ zuC2|sS@yEz3#8-JS^=^*D0 zBIfkKp8~r@(qT2z=o{f|r$77`?Cc<7PRrjJx&WVLPJb{L^MdhA z=d`z(4i4y?n_uY4k#w!H$3A!pA9>q-9PLp)Bqc{325c3#W#hM{23A@llOhY|0|%LN zm)*+&2oB^J!T<{n_&awmiM57bx>CYO7L+>gD{=U|Sn5+jYg+n^f`E5|N|i4V5;n{)_A zVK2%*E=@XwlQ4(y&!v&(Dy{QJnQ(Irv2wh*rZo6NcRg^X@uxIZU%Ov9FMs$niaN}q)3@wmM=YfBj`&s_t?bQnx-3rrqt^3+?F#qm-bBM;463V5V-O(WyKZ##F{lm`#pQ4&LlF~5 zy9;l12uhj9F#X+s6Rb7-8n>S%qjql7i`Vf2?25P~6^;7B1i4Y46U{Xm^`&v98V~fX zjH}7nCKO292!ZPI&ms63CZy6KJl+Y)xwIU63}gLa8dQWp+KlELrYmCg796o09=6-# z9j23mb$h(ShOD)j3wgk3fG8=B21+wsz41~kZ+~$MP?nUpe+|?1Ur9`j6*D0p5nuCWjj9rOfN~sE@95O0UIBw-%^m0bM;lLvNV9aG%{ z*C9As0X+5{A;#Z^u4~Pam4bWH_R zw`sIY-QBbxr>;L(%^}hR6G>?VB`3q5m57n1$@!P-i&!1z4BB@subd(64?iauY5L`8 zhVaX7hJ6mOylAdI2e2s}6B8M_#wB7pHJeS%Y_#6iG%w6S@7%O&N#+2DD3hStmgKtx zg0JqgYo+gEQqJaT+a})n?CN=l$!xB+EilN^XIH^m!>@6RO-?ahF$d$ePn#4!L-*3@ z`Wzb-9nB#mM`adLw^dvy&)~5|RU%TKHk{76NHVn(_Qk{W9LRK}Y2kg2CFbewKNPXp zyTnLS^r4{=tJ{j0^prlwI`hO-^?^<4c~$jW5o6xgG$mB8cW&E-3f1@NoIHW6zE`Cu z&~`%1|43J~4dyc1cB0;1Xi=RsY&>TuFjgBwiCIFOiW96KaM3H_y{r56n*H&l~^5mg*2O< z=3V5>6I0cH%%=3bs`?FxF>lqTT<5p-{0yz$59oMz)O?#-oV|i+pVoEo&_iLm`mcoZ zq4GXwBa>(s$e{0tLDk3+2RV<%%>C`x~|Nq;pl{>~?9M~@>W&(n?`XA)?-^^;&|L$7|iWY``% zIzEEm1B-yuI{CfivIT<6ZtPOsWuN>Wejko3&nR2!mK(cx9>er^VCd70T?8Ym<4-(M zo?+p^RautmbOKpvgU;!!d>9+D&30Mo{tMP#Z)<}UxCgN6S@F5mEv#~p=R;KfL;QVQ zFqAS=*Ws)*V#{CFbvP@F*u&TW!`hsu2k7PC^xBjxoBX<@a~kV)m_Nwe?_=Gj%Pe9}54;VSPQ(#58hzurzz&jhSW7edU&|9_bZO|fBIb1I)*mO# z=+YD0W~D)xsNxk8=pRV8nCXlz zSvvxx;>!*zYZvN-?N%{D(YzltEgV(`H2Qs<0DU=jp*Ed)$n*U3%Z`w4EENYHA#K9n z&5-E|Vxymt0=yu_^qA=RmwQRXP-faK5?*FGt>t#c|GFERVFj87t)yV|{pI zx(AM9ZbyuC$iJ~iI{8aFv^+Zs={T1#IZybMm3B+6~(nL+|<1Zt33B17JnoS?gC8& zv|zv?Qn~!I_}@&llxJ-wt`KMB^lcGD9Dw8wUr z*_qxVgLA0cy|CX9@1zwDN67UYtisigi|aC(2Pv8zKH(I^)#p+W(pbNEC>jzXQy1spkc;aGlzqp$l=kA3!s7&=N59Q87!<(lh&E?ahZW7L&#w|5S zbqrQ31S5@GagcuKPl%DGiPR&eD@%7B+Tc7(r!>8dgAYFXx3U-TBP?XXOgWhSnXiv zvVdXNPB|Y@z#erz3)o7-=;m};pwA)1`l$B-jXL@qZy2Ic)wc45zV!!0)%Or1&1ILk z#(5F)zQi(WA7wgOmT^p{xv-uhR%^U?d6cod4#iBiV!Ga|s??!!tiScxj^F9l8A`G$HYNGOM{3Dw&qTJD-+~j4RCUxtS6hbh_XeUd32ptgfe z#&w8v+C(_4AkJYXj$&VhII5k^l6Fj-;(CcMpIx7{)0QlWIJGV8Za%@3t|w~?OP@oEy6ywWfI3?fZFt! zYRw(igl$tFD;nkI5C==Ty?;$MNkbfr;{6duiLsHU#(d*aG$tFDYKT@IX|GQ5eib6B z#=cf5V&RQx*VyPJVo_ryumo{>f0yErM$qy~VJ}r_iZfuer9&SZFq+~JTR(9uBF6)= z@^I-M`V?{duTv0-*Wf^8_CB;JnqJ&%DeR*7Ud!n*oQ?5XdUe59v{@d?9gcEupctfW zjdT3n&T%QWPL_H@unuWcvgRBJf+G!0g{PwbFXZnwW~FXdN29V8K1+!lXCTK9 ztcjEk`6JC)wi0{4umYn)z69$Wn|(rzbjY8dk3*D;h>_;uzHL?zlY@TS;2o8B56{2? zG1AVKVAbU#T6s=QqVX6{NeH5D14~e5Df;Zm<8T724;@e^#mhg5z6JaA&;f&qU_C_`<((mGJOz! z{<#i*WGhvF{|fl&Bm8_b@nd!OIkCWx1jOHmzJ6Tb#~i)z(dR_)a|ix53O`7@7t&7k zJjDL=H|)KA?7tCX9-MX1-vq0!>roTNpVlyP+-dT%Zo|m&BPL87-LNOmigdscJh8Mk zFraI3x(#v9)I!uG5CYMu_odyG64tE*TmE`nB=g+}<_@8Lcbq4@ggoM)E3$hr30wZU z7ekDBfNA=2Y%u!qsR%ZuZAjyg@!6PXEF?x+4<%>wzC#QLltJqO7SK@i`ScF*>B(1bVi4; z;VxPBFzYosgwnlPw#-5u(s;Atfh>E@_#+KolqZ(w=|0#b%l>kRVmaxMzjdX7$d3Rj5tR z2z0ulQf-AVEW6s$2j6f4LL2+9e=1X3XNsX}#}3K6S3+$+BBo8$U}|enj3un{l8A}g zp8dCBtC*MNU_`+R-on#}kq-H5FpX!`y*nN9kNyF*ZN+q?O+~EN@?g}$KGiZ)CFzjQ zc`(c5n4pY!q(gqlN5Gnikq#|?pBpiwL(4++z(=tXfxIn?&qt4WxjIG}C0&I&bn&9o zRY@H;uopF_3u&cauoai5XIg4rzMa1}J9^)GdY!V2j>R586 zmqbihefU-XO))DcDG&kW{-KQ8`DXTd8(V&PfU8p!<({qEPRic z^pu6~v3D#&^GhAlI~IM!-r<<^4q)0N3^SU&!^+d%f%3FREbgl18O`4D@T-DVs6+S7 zJN>Lu9qERAR7djaH7(j;r47HePIW-scW;6^4pLUsfxxd*9qM1LgkD~frqf;4HLxl; zy3&Tdn3v_CcT6wz4yDl}zL#asT+ei*L;mqE#WIPJM!n0RmcGPDn~KPbl@szm{XENF z_<-q1qnA9KWiKr!MjAclQ(&B58jT)zMUVxw4k$Fnwe zjO{EXcu7o$?@sFb0sPI%Loa(6S7=|m4SBC6MjDO@O|oovVx-YKFx38mA+C9m7-?X*IbrvYj0T2x0cJr>(gvilDgOqx6(ig8fQ=OM2{bS;cn2vPFFTDd{2*wm?X3`-)0kNNMqAe<(9k^D(b0cLOS6(H^K*vU+0GWCdg9!zUeR7w9AiA-RQHB z--n6#THVOTPv%ECXaoPkvFK>|@m>(+xbIc!h$RtwqC0iO--xlCkpFxyOze*#Mmpq= zA0ERuqoKFn(CIl$N19zL4m{{uao`afMccC+%xp22$# zVmi>ot~FPJyrpY5VcvzOr@RYK5BWnMKyUvfMmpqw>;=79`;o>hT-!p@RqBl!@i$cJ z?U2;BTyN=9b2V#1-tLYHy=_KbRBwksZ?JLyc&qAdr0H!W)3w93U2%UbiP$zcS}M<{ z@HZ<@%YoiDhTaY)MjGw?L+I^~#7IML--h0X5hES)4_{5A5oz|f<;IKW#p*-MOB(uU zmJ=K-kF>^dr7lP-`bA6!T4TCWm!pUwrUM=Fubm7xY5s*YF?W-K&H6OtTWpftB;y+Fo}q1lnZlQkot2-& zO-E%}xVtf~pT~zqZj7ngY{|G~<8PKlMVlMPBEv;}@rhK0?)<2T?iJyaUkT_4BGBDZKdqq!Q_ZLRWt z{~Ge{&GJa|RgI0!FUYGJ8^bSb@R0mvI?|!#X&iXA8-GS4Dtam_wdFL?Xhub!T&j7s z4L-TlBBeuE9%V9(n{0~RXc&3s(+oFqrIB*1+ctY~rSp+wo3e@sMRhx(Xq&#YcyV>x z>~;h)U5ZTmCQiHI6MMQGd9h*oJ1|)vRE%5|ZIj+_0-0$C+jM4*j|b37a8QWZO1s@3 zw*@qnEPS4o1~R|ietopf8q3(NV6I!x$Z98)nd{e#VQB>nZCIHob?al8Fn^W_c9vpl zrnTpJNyIRx!Xl_)=P738=*mQ?%R?sP zXw0eL+Ux-tqpgw2U&P?@OK#T86Y{^W#>*ZS4U$$jjMgpVIY+2d>Vn8t+$(8@HI7M$ z)8*GN|6inZq+$M7fWMnHuhBY3!(uTptY*lG&!Dc1N+k7Tbj~ zG2MSNb$mDy1$B5dnfhI5C{gm$MN=0L#?-y-I!qm})4z+js@t~8m6~(+ww}i@{T&#r zr8``#4-Q3B=hKdpk{fnr(%TUwXC=KI5ux-}TYSmkns_^+&E~YczNeMhb-@jH!@2<0 z3j8Gpwc)osPt+6L=(!@X&nOOtKR*ZrNf+^~Q{ zGPuu5+r(xN665#r_-k$$4*?>r=gIKTf5%__O|VKgtdBBxnv!hOnJKtoXXV!9h8?Q% zTG6I)ORCLgw5VQ_%52j@Rh0rh_X&&v=5y6Hd;P?73CGk2+S`6p%9e;O2&nfuGwF7AJnX>!P zh$}AYGdm!1lF(KD!-loIOLOY`1qU8q$=SZ5lUQP88i!0Tq5!B=7#P1j{$f}e&+cr$ z`)`u2dXtsy9q|Y~dh!%D;&YKtiCI4FhY@XDJQNVam^l?(T2f@e*tF{sNO6p^24o)qOEyig8tXIWR)$<-j=pEJ!m0Sm3?z ztZOYJY-wyuOH71#xUu5m-TOSJp3KE`3$NzXlfPMB&0`|pSB`zq38B1Uq!AlEfWE7~ z*J(~6wt0YgWeTy)0~~9*-CYHnT~`o zZ8}OipYVw6$|L>~8~a_!?!{O-&4YBBz8o9$8XjorL5y?= z-~SgD)ITIf8fW~W-=>blNQW?Hmn^$yH8IktSL+w7O1JYCvg!6;Q~QYEx1)x%XPQl+ z5X-y71HCm%@J#l1D|%38a=`q^bQ#Jy(J*kcyo(n^?15voS6NBKa0XEpbOL{~yjl(< z#{!uxuo;b84nyL?sL`lH>tbH!!BaQ?iEGkE<8khv!s0oa8m$M7d{mP|N1$% zc2l(EyW>)KnI&%pYn%d0PQy($WgoNTeXRY(lJ2JNn!HzP9AmCub0UKP0U5?s-47Y({D0xGY_P^E-n!oO^KFo zDS7>OSSVV^FM*MkuNc5WXE7aVoU6Ve&10P2=wwfaC)AA|g#|soEavp3v)q!i%xU>c zOC~1tjQ!n`6Ma#gTXL2;?Q*NU((AT_Y;c>DZGEhpu@j;Q_tSo$rEo^p547BsVv=~E zCGAA}#Tz})avlz}bcJu$1sz)J)VpZiQ_UL17h@k<#uwj*wmhDm?ay*x-6y1nv`Ax& zJsg{ytC)^-2t#2*wyS0|%i~`67g@5lMW?@|wvbahmxH_X(V1+jHS}3=R$a3gcgJ8a zYgsZD!8MH3{AdltvdcFjcEz3azsyDKwh!rl`5Q6j3E{}`@U>hmG8*q5VJ^39d!{38 z*3H!&`yJm;K`TG;8Pkyt;imsh7Ec-&q7{ocj3(y3R(=;>JGY%%sM8@_zm;34(;-kE z)~n+JVsf=mo) zKVdFOhZmo>hYvn+8?3_3<%!KCA0)6In&B9iCXR$OpG*Qyl)j^Jf)epc_&Ht zMV8ESaeq&8i$J$yb1a?ciI#kI8W|VigK(IitmRKS8>gBd$((5Yz&-^icSqtF-q z(M+d*^fg$m^**N?Fl6}ynNA=7GmMrPz2%?NF1K66a%{<|)v6rpW3_r>u*2&~d$Umz z{KNFw$*&58E-`&+!LQy`o%8;s})XP>cv<(SY|V#BPqK1SHzeH z7=D|+v>cO%Pv>n*j5Kt3YL+c|nHXu#rx%!Y%Y1slt1ORoe32#d^yEjWEksDPMe~ff zl$D)9hL;x}2*NCM%YS{LC8NKN!zj%gBw6;gHne2s67I8Xmw~io|4mwwc_8H^Ncp~` za+)KGN2oHoJSV*ct+qUrryKoiL<0{IBMnQw&1V-*+uXSe)9Kt9^ZozG99w%|qIb9i zQNuBkF3X&jzxKq0VnT0^?I(L;BGTQkEA+bqHEZUy%N;E_cmqqi^|53#z3@NQ&lctn*cvK~RsxPHnVXOJ9 z50;90emg;Ga60G%$}2A-CJ!jDyaY3CISeEd(_UD{0PA%M46bL3bwP(Tq;*zFR zxL}9me>)0?o*RGR38oxt7^0r3J-rxW;w={J;Kf)v&4YBBz8o8bv2$)GVx;ll^f$0F zbS*K`^ia3!TCdaeR?#QJTe(kOu!H3NB1`6(UAR|o9}yfrc|rRMpS&VH*jICZmR)yB zg(VlFiv{gr$p^r~L z)AHB-w9_~I5kC1*sUyprcDbW<%h)2;t#Yi7b?b574sTO?&|nGPROZpsuP*GWDG2*6 z#uu{O@5VeGA-OEz*hlQuI3<{nKH)(Ef2ZLR`y!*_DdSI*Q8`;TRvJ}$_OAx2`0+Cp zM%B5%DZ;S&?VVGk#(Y)WBXdbQ{ALTt{+me2JY1gg5J#4$=HaW4!|>OQg|r!!Eg3i_ z?$Hg1w7R-zK;jCJi<14>f(vI!H4TeX1KVi9~UL zm@yjb_44wii0_{GDeE8|@(IZ27-_sPH8f$Q<%KEK`!CIFbZC)FNz35DA+OOmp@RAE z#}Q9Ruanr|af$3@hVqlLy!p~okr(-;SxJX{ z_M1s1q|qb3kyJujdqm04VxdQX4lRGfe3_2RY5t|-avE}+>oXLmL(5w@C&(F!)4}9c z{)~T9lgd$5ODgSeMLr=g_o3# zO^gLCKg!t#<@{XPVd`r=7csd(Iqv|&u2szP;C?YmxBFm5%eU2&BP4C=q{F0YFErJu z?{^-creo55Fw&};ct;Fs0xd5crgWq^4lTpHAL`U`Xc=x*E;=X6euHsOFw!^``PVGF z={jN${Ugh6Sy&yDd&sxFYk8ICcr_34x0s-MlFLnX>mI|nIQep=>K;uKVOQPkbVTBD zZSc}&-PWnPN6~ECL3KYPi*lb}vt2zGF*$U+`I(08s+i@0>V5##AyO1kNJDi`p(lPu zjI@nm6N%|~HW3>}=r!(GNn3Nw)^uJ+{^1Gei5S~ZhtW_mCgA^s`UE4bjy3ydJ7RFG zpc!g>{0cD%H9mfYYW?V7#Z<)~9SqfB>d|&bVx)PHu=65f(gvLu5!?Js#i%-4iCL~Z zSM7CNjVtW<;BJzRb?GumT#YNd-o7;C<2qG1(T%if%a3w)hU(5HHV!+F;zXH?*tFqv zqWsPBY95SrzfEc)jS~|8m()qxRI;WluQvG;ZxEB_f8q^Zb#gVyRVO?kE8|~udZdZD z(-Tab-sR6>yuxf))JZzz%yBl-3*IOU3eb*F}kI9o-6Am zn~)t<6>f%ox*M8$iel>E-g(_~5fcZuda+@zTVBnBroJgTGtxX(<=dcgtZLZ?47B57 zC>%~)47GsV^LB;9w9Bo5bjUwJmH$L>Wmvas(VSo!RQenvQDv*wmyvQ%&-0$b`{jM~}d}AtRBr6QTo& z{5oOYc1_6dnuycnX&*4&qe?s45lUNw@t9@dbhTf>Sr{i)@iIWybY#=745ZJ)mi$8Wi zh3$ubUX)=T)@YWu#no%2L#uCLZQ$*4 z@4Z>+P;(iiL;kxzWu>z*sg*V$9rBs`rVp!=4tZZJsrkp&Nkbn8rw^->4mowj@_=@738pP=H{LMY+IH()XWo^;#+G&K zx>tb=VqzsSP#TOsI;cOgg*2sP5Qs>O8jU7u6`EKk{{YirWGl#6COTsK9>34|p68zP zwznGl&wcuRpXYqeIrrRi?>+b2bL|v%yU%%?Eu0vRwQ}VgxxCE74Tqfl%&Cbo`PY(% z3CWjFuSllx=%`hb^~4%oc-uP9(~Ps-RQ@Y$-EjIm#zyQ%A+5Gley)@JV5rg_{>YF0 z?lUMguloFKWkTT^U0KJmp8WP>o@aIY9mxDk%#T}Bi*NT~v`z9uEj>TM#Cc4fm$m9R zev`{28MNP1#QgaWd?tC0s8jp%?|jx?fk@siV+JuM2u}>(4Pd*iY(&KA!4Ztk_S?Qo!rO)p4$@mib`qTF(yZ>dGueR~&ItnV>((NTIL z;w&O~gX3&t8o!csHqLgH&Bo2je$-XA)zb6m-|QM3_~M=N3cz~1R#^@mrko6k#qILEHd>Wa)0V&`blr}S1DRwtw`EU z_SWuB{`1xg_B(@6?Y3MfjfCk?Cm#e?r zuYExuH07foT~yE!sEug_b%T;29l|j`rVj=)xIXGkOtZci^+F$L7`!iNasD3F?DTzZI%% zpz4q9ci~|R=xs(x8UnWmMsHW4Ctx>tc3Tu3``RKligavfDK`D#am2ILW>m=DSZFVF z-_+LXOO7EC*N0_WqUc9>?zN!gH$s(R>C}?bA08u~t~R5D&Zarke}{dMFZj|7uKpE{ zJ@C^XEP{Uu>itW=oj*Ke9Gumzwu|!cU=c&EjDu=c^t;i7Z^Amr>%x7TeHYYrs4GL& zbxF=29tC*tOzdopN=5SxilZKVnV_R6zbAxbmq{W}yF%5Y#b40a_6bI9jY>uHp~M3o zorOElwYx${HfAEV?V%c?Yj+V>+w0M_y&9E@-oQa398|8xW1NVDUDqE{;)_hBZgZ%H z?7Duk>$Z4y-4=~XXLHo#QP0MZr|j*2emSJX7bF#^`$E;T#b4Oi9#*#48kNrGvrdeD1E063;S~xm!auWY5XCEZB3dL#M4#>1?+1 zlb(G}*!U#%6Cou&E2%)O=;b|I{DqC}2`#tS8kNrG6Qw6T`!!)3bLtZn?7vAWP(Ku^ zo-O{u#ug_(9^PVWR63iFKc4bzc~lPe#9u;6{8y$j@rO_i*%LDI2lm7%&z?A?QR!@s z-($!^+nTKR3HIdakP@F^Dw9*88nP!(lRY`(*^^ipL~3htDxJ-~W}T~dgfMJqf)@^Rk}PFlj#p1TLfMU^{Y#P=?@Rw_wtfK zZH-C+vrFmm;A@Q8g4^H)7fNfO&MpO}KRhmaFl~)W0kc2Z>cP@4pnVOQaBpVuI9=M; z&}^vseQXy*x9w}_qCjMSLvv@_q1hBLJCki5EGumQT$&FN*{caIoek9xT$(4Wbisp5 z_Ed|s&ZdCblWh0ks|Y@n2@%;kf(PFS)ew9rL-63+9z6KAMx}t+jqLDXImMyGV>gG0 zY%P-*yEarq@Yu}+k2QMmSffUzfZ2!OojcceW-*pCgt3zajcXOuyO(NQ^oPg2zH!mk zs1z_ekewbZ7ZfP*Xh&GKY@T@^y*^aK5|4JU#G|-<(8e{|qEQ}fKi0Vm|5t4!vkJFW zpN1dq;tJodxHCoFU$_UKk_gtK#vT``voD$d9baY2(R(Vrt~TY%k5x)&xo6H-N*||J zm=+E!@d~9iOg@yJ=Dp;O70GOn=p(Mswh$-`Zix#|QoFEIuv!$ab@pjlsF^pdpDT>j z%JLctVqIzIcjk{wkHztRNYDCpx|;#<69x<98R91urhd#TpK&#;q@UcXH>|{0T_293 zbqA=?w$pF)OSm#E2R6#_x#X*D&W5&A^2u2KPEENQ`|m-_X+)(*}AoU73pc78ACtS!u+YGjNji9 zMcdyYmo|qccJL9m9j4f^LYtHL@$ldZH@PW)R6bxwp~|J-RU9EtVUz=t8@7)mV>gja zS)J`LRk`$INjb6ODTI{XOU>Ewv$c4rK0?je@gvK<=Ir>EdQ(0)L_cT8RlA{~%fO%7 znWx{MXliHre(p7AXO`{rn%a-!VfjHj7XnjKoPDIql=t9#C4XuUKPE+|rZ%es+EU|V zu7d4VMDDk~g1?RxZ(B@x^<5PejOR|(y_FS=LkCUOIb+*^prcN+wyem4kyJD#@uO|Z zzu9QYYdWaWHfGs(OnGg+)tqfi->lbYW4<|7rcpoIm~Z|IWUI_r+Q!VjWXj#&qo#IM zr)ubOon3vsuQ;_?OvL_=inBMAIZQ;?6V*2`D2df&7E~M_Hh=Sj7_9E|EtA92&KW`X m`--D&$`76M6-OI>T^PRRvFmL3p;a`opL4e2{!0O-rv3x%l&h=& diff --git a/impl1/s1_impl1.dir/5_1.pad b/impl1/s1_impl1.dir/5_1.pad deleted file mode 100644 index 9c4860c..0000000 --- a/impl1/s1_impl1.dir/5_1.pad +++ /dev/null @@ -1,702 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LFE5UM5G-45F -Performance Grade: 8 -PACKAGE: CABGA381 -Package Status: Final Version 1.38 - -Wed Jun 16 09:20:00 2021 - -Pinout by Port Name: -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | BC Enable | Properties | -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ -| FEE_DATAFINISHED_OUT | D13/1 | LVCMOS25_OUT | PT53A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[0] | R17/3 | LVCMOS25_OUT | PR44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[10] | J19/2 | LVCMOS25_OUT | PR32A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[11] | R3/8 | LVCMOS25_OUT | PB15B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[12] | N5/6 | LVCMOS25_OUT | PL59B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[13] | G16/2 | LVCMOS25_OUT | PR17C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[14] | P5/6 | LVCMOS25_OUT | PL59D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[15] | M19/3 | LVCMOS25_OUT | PR35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[16] | N19/3 | LVCMOS25_OUT | PR59A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[17] | B15/1 | LVCMOS25_OUT | PT69A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[18] | A15/1 | LVCMOS25_OUT | PT67A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[19] | K5/6 | LVCMOS25_OUT | PL44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[1] | N3/6 | LVCMOS25_OUT | PL62A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[20] | V1/8 | LVCMOS25_OUT | PB6B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[21] | G19/2 | LVCMOS25_OUT | PR29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[22] | T2/8 | LVCMOS25_OUT | PB13A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[23] | H20/2 | LVCMOS25_OUT | PR29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[24] | K19/2 | LVCMOS25_OUT | PR32B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[25] | H17/2 | LVCMOS25_OUT | PR20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[26] | L19/3 | LVCMOS25_OUT | PR35C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[27] | C20/2 | LVCMOS25_OUT | PR23A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[28] | F19/2 | LVCMOS25_OUT | PR26B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[29] | U1/8 | LVCMOS25_OUT | PB6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[2] | G18/2 | LVCMOS25_OUT | PR17B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[30] | D20/2 | LVCMOS25_OUT | PR23C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[31] | H18/2 | LVCMOS25_OUT | PR20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[3] | M17/3 | LVCMOS25_OUT | PR41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[4] | E18/2 | LVCMOS25_OUT | PR14C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[5] | F16/2 | LVCMOS25_OUT | PR11D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[6] | A16/1 | LVCMOS25_OUT | PT74A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[7] | L3/6 | LVCMOS25_OUT | PL62C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[8] | L16/3 | LVCMOS25_OUT | PR38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_OUT[9] | F20/2 | LVCMOS25_OUT | PR26C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_DATA_WRITE_OUT | C13/1 | LVCMOS25_OUT | PT51B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| FEE_TRG_RELEASE_OUT | E13/1 | LVCMOS25_OUT | PT53B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| LVL1_INVALID_TRG_IN | R16/3 | LVCMOS25_IN | PR44C | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| LVL1_TRG_DATA_VALID_IN | A9/0 | LVCMOS25_IN | PT33A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| LVL1_TRG_DATA_VALI_IN_rising | N18/3 | LVCMOS25_OUT | PR41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| burst | N16/3 | LVCMOS25_OUT | PR41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| clk | P3/6 | LVDS_IN | PL68C | | CLAMP:ON | -| discard | P16/3 | LVCMOS25_OUT | PR44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[0] | P17/3 | LVCMOS25_OUT | PR41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[10] | K20/2 | LVCMOS25_OUT | PR32D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[11] | U2/8 | LVCMOS25_OUT | PB13B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[12] | N4/6 | LVCMOS25_OUT | PL59C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[13] | J16/2 | LVCMOS25_OUT | PR20D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[14] | M4/6 | LVCMOS25_OUT | PL59A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[15] | J20/2 | LVCMOS25_OUT | PR32C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[16] | P18/3 | LVCMOS25_OUT | PR59D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[17] | C15/1 | LVCMOS25_OUT | PT69B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[18] | E14/1 | LVCMOS25_OUT | PT58B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[19] | L4/6 | LVCMOS25_OUT | PL44C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[1] | M3/6 | LVCMOS25_OUT | PL62B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[20] | Y2/8 | LVCMOS25_OUT | PB9B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[21] | K18/2 | LVCMOS25_OUT | PR29D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[22] | W1/8 | LVCMOS25_OUT | PB9A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[23] | J18/2 | LVCMOS25_OUT | PR29C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[24] | M20/3 | LVCMOS25_OUT | PR35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[25] | J17/2 | LVCMOS25_OUT | PR20C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[26] | L20/3 | LVCMOS25_OUT | PR35A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[27] | D19/2 | LVCMOS25_OUT | PR23B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[28] | G20/2 | LVCMOS25_OUT | PR26D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[29] | T1/8 | LVCMOS25_OUT | PB4B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[2] | F17/2 | LVCMOS25_OUT | PR17A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[30] | E19/2 | LVCMOS25_OUT | PR23D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[31] | H16/2 | LVCMOS25_OUT | PR17D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[3] | L17/3 | LVCMOS25_OUT | PR38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[4] | F18/2 | LVCMOS25_OUT | PR14D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[5] | D17/2 | LVCMOS25_OUT | PR11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[6] | B16/1 | LVCMOS25_OUT | PT74B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[7] | N1/6 | LVCMOS25_OUT | PL65D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[8] | M18/3 | LVCMOS25_OUT | PR38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_data_out[9] | E20/2 | LVCMOS25_OUT | PR26A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_empty1 | N17/3 | LVCMOS25_OUT | PR44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| fifo_rden | A19/1 | LVCMOS25_OUT | PT85A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| finished | D14/1 | LVCMOS25_OUT | PT58A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[0] | N20/3 | LVCMOS25_OUT | PR59B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[1] | A10/0 | LVCMOS25_OUT | PT36A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[2] | R20/3 | LVCMOS25_OUT | PR62B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_drop[3] | U16/3 | LVCMOS25_OUT | PR68C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_finished | A4/7 | LVCMOS25_OUT | PL11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_out_valid | C9/0 | LVCMOS25_OUT | PT27A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_buf_release | E7/0 | LVCMOS25_OUT | PT9A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[0] | G5/7 | LVCMOS25_OUT | PL29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[1] | H3/7 | LVCMOS25_OUT | PL29D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[2] | E3/7 | LVCMOS25_OUT | PL20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[3] | C2/7 | LVCMOS25_OUT | PL23D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[4] | B6/0 | LVCMOS25_OUT | PT4B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[5] | B1/7 | LVCMOS25_OUT | PL23B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[6] | E5/7 | LVCMOS25_OUT | PL20C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[7] | M5/6 | LVCMOS25_OUT | PL53A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_coarse[8] | F1/6 | LVCMOS25_OUT | PL35B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[0] | J3/6 | LVCMOS25_OUT | PL38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[10] | A8/0 | LVCMOS25_OUT | PT18B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[11] | D6/0 | LVCMOS25_OUT | PT6B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[12] | B8/0 | LVCMOS25_OUT | PT15B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[13] | P19/3 | LVCMOS25_OUT | PR59C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[14] | P1/6 | LVCMOS25_OUT | PL68A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[15] | C17/1 | LVCMOS25_OUT | PT78B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[16] | G3/7 | LVCMOS25_OUT | PL32A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[17] | G1/6 | LVCMOS25_OUT | PL35D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[18] | J5/6 | LVCMOS25_OUT | PL38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[19] | R1/8 | LVCMOS25_OUT | PB4A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[1] | E2/7 | LVCMOS25_OUT | PL32D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[20] | K3/6 | LVCMOS25_OUT | PL38D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[21] | G2/6 | LVCMOS25_OUT | PL35A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[22] | H4/7 | LVCMOS25_OUT | PL29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[23] | J4/6 | LVCMOS25_OUT | PL38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[24] | H1/6 | LVCMOS25_OUT | PL41C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[25] | J1/6 | LVCMOS25_OUT | PL41B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[26] | K1/6 | LVCMOS25_OUT | PL41D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[27] | F2/7 | LVCMOS25_OUT | PL32C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[28] | H2/6 | LVCMOS25_OUT | PL35C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[29] | A17/1 | LVCMOS25_OUT | PT80A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[2] | F3/7 | LVCMOS25_OUT | PL32B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[30] | E16/2 | LVCMOS25_OUT | PR11C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[31] | R18/3 | LVCMOS25_OUT | PR65B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[3] | C16/1 | LVCMOS25_OUT | PT76A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[4] | E4/7 | LVCMOS25_OUT | PL17A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[5] | C3/7 | LVCMOS25_OUT | PL17C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[6] | F4/7 | LVCMOS25_OUT | PL20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[7] | B3/7 | LVCMOS25_OUT | PL14D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[8] | E8/0 | LVCMOS25_OUT | PT13A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_dbg2_out[9] | C7/0 | LVCMOS25_OUT | PT11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_discard | B11/0 | LVCMOS25_OUT | PT38A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[0] | D3/7 | LVCMOS25_OUT | PL17D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[10] | B17/1 | LVCMOS25_OUT | PT78A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[11] | U17/3 | LVCMOS25_OUT | PR68B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[1] | D9/0 | LVCMOS25_OUT | PT20A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[2] | A6/0 | LVCMOS25_OUT | PT4A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[3] | C6/0 | LVCMOS25_OUT | PT11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[4] | F5/7 | LVCMOS25_OUT | PL20D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[5] | C4/7 | LVCMOS25_OUT | PL14A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[6] | D8/0 | LVCMOS25_OUT | PT13B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[7] | D5/7 | LVCMOS25_OUT | PL17B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[8] | B4/7 | LVCMOS25_OUT | PL14B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf[9] | B20/1 | LVCMOS25_OUT | PT85B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[0] | A11/0 | LVCMOS25_OUT | PT36B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[10] | T17/3 | LVCMOS25_OUT | PR68D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[11] | D18/2 | LVCMOS25_OUT | PR14A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[1] | A13/1 | LVCMOS25_OUT | PT49B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[2] | B10/0 | LVCMOS25_OUT | PT33B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[3] | C12/1 | LVCMOS25_OUT | PT44B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[4] | E12/1 | LVCMOS25_OUT | PT47B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[5] | D12/1 | LVCMOS25_OUT | PT47A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[6] | E11/1 | LVCMOS25_OUT | PT42B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[7] | D11/1 | LVCMOS25_OUT | PT42A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[8] | B13/1 | LVCMOS25_OUT | PT51A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_coarse[9] | A12/1 | LVCMOS25_OUT | PT49A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_drop_cmp_buf_valid | A7/0 | LVCMOS25_OUT | PT18A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[0] | E9/0 | LVCMOS25_OUT | PT20B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[1] | C11/0 | LVCMOS25_OUT | PT38B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[2] | E6/0 | LVCMOS25_OUT | PT6A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_out_i[3] | D7/0 | LVCMOS25_OUT | PT9B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[0] | A3/7 | LVCMOS25_OUT | PL14C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[1] | B5/7 | LVCMOS25_OUT | PL11C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[2] | A5/7 | LVCMOS25_OUT | PL11B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_hit_valid[3] | C5/7 | LVCMOS25_OUT | PL11D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[0] | V2/8 | LVCMOS25_OUT | PB11A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[1] | L5/6 | LVCMOS25_OUT | PL44D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[2] | K2/6 | LVCMOS25_OUT | PL41A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_invalid_dl[3] | K4/6 | LVCMOS25_OUT | PL44A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_lvl1 | E1/7 | LVCMOS25_IN | PL26D | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_lvl1_invalid | W2/8 | LVCMOS25_IN | PB11B | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_offset[0] | D10/0 | LVCMOS25_OUT | PT29A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[1] | C10/0 | LVCMOS25_OUT | PT31B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[2] | E10/0 | LVCMOS25_OUT | PT29B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[3] | D1/7 | LVCMOS25_OUT | PL26B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[4] | C1/7 | LVCMOS25_OUT | PL26A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[5] | D2/7 | LVCMOS25_OUT | PL26C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[6] | A2/7 | LVCMOS25_OUT | PL23A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[7] | B9/0 | LVCMOS25_OUT | PT31A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset[8] | B2/7 | LVCMOS25_OUT | PL23C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_offset_valid | D15/1 | LVCMOS25_OUT | PT71A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_out_valid | E15/1 | LVCMOS25_OUT | PT71B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_valid_vect[0] | U20/3 | LVCMOS25_OUT | PR62D | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_raw_valid_vect[1] | E17/2 | LVCMOS25_OUT | PR14B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| hades_trig | H5/7 | LVCMOS25_IN | PL29C | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| hades_window_end | C14/1 | LVCMOS25_OUT | PT56B | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| last_buf_empty | L18/3 | LVCMOS25_OUT | PR38C | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| rd_clk | B12/1 | LVCMOS25_IN | PT44A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| release_out | A14/1 | LVCMOS25_OUT | PT56A | | DRIVE:8mA CLAMP:ON SLEW:SLOW | -| reset_dc | C8/0 | LVCMOS25_IN | PT15A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[0] | R2/8 | LVCMOS25_IN | PB15A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[1] | T3/8 | LVCMOS25_IN | PB18A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -| trig[2] | T19/3 | LVCMOS25_IN | PR65A | | PULL:DOWN CLAMP:ON HYSTERESIS:ON | -+-------------------------------+----------+--------------+-------+-----------+-----------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 2.5V | -| 1 | 2.5V | -| 2 | 2.5V | -| 3 | 2.5V | -| 6 | 2.5V | -| 7 | 2.5V | -| 8 | 2.5V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | BC Enable | -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ -| A2/7 | hades_offset[6] | | LVCMOS25_OUT | PL23A | LDQ29 | | -| A3/7 | hades_hit_valid[0] | | LVCMOS25_OUT | PL14C | LDQ17 | | -| A4/7 | hades_buf_finished | | LVCMOS25_OUT | PL11A | ULC_GPLL0T_IN/LDQ17 | | -| A5/7 | hades_hit_valid[2] | | LVCMOS25_OUT | PL11B | ULC_GPLL0C_IN/LDQ17 | | -| A6/0 | hades_drop_cmp_buf[2] | | LVCMOS25_OUT | PT4A | ULC_GPLL1T_IN | | -| A7/0 | hades_drop_cmp_buf_valid | | LVCMOS25_OUT | PT18A | | | -| A8/0 | hades_dbg2_out[10] | | LVCMOS25_OUT | PT18B | | | -| A9/0 | LVL1_TRG_DATA_VALID_IN | LOCATED | LVCMOS25_IN | PT33A | GR_PCLK0_1 | | -| A10/0 | hades_buf_drop[1] | | LVCMOS25_OUT | PT36A | PCLKT0_1 | | -| A11/0 | hades_drop_cmp_buf_coarse[0] | | LVCMOS25_OUT | PT36B | | | -| A12/1 | hades_drop_cmp_buf_coarse[9] | | LVCMOS25_OUT | PT49A | | | -| A13/1 | hades_drop_cmp_buf_coarse[1] | | LVCMOS25_OUT | PT49B | | | -| A14/1 | release_out | | LVCMOS25_OUT | PT56A | | | -| A15/1 | FEE_DATA_OUT[18] | | LVCMOS25_OUT | PT67A | | | -| A16/1 | FEE_DATA_OUT[6] | | LVCMOS25_OUT | PT74A | | | -| A17/1 | hades_dbg2_out[29] | | LVCMOS25_OUT | PT80A | | | -| A18/1 | unused, PULL:DOWN | | | PT83A | | | -| A19/1 | fifo_rden | | LVCMOS25_OUT | PT85A | URC_GPLL1T_IN | | -| B1/7 | hades_dbg2_coarse[5] | | LVCMOS25_OUT | PL23B | LDQ29 | | -| B2/7 | hades_offset[8] | | LVCMOS25_OUT | PL23C | VREF1_7/LDQ29 | | -| B3/7 | hades_dbg2_out[7] | | LVCMOS25_OUT | PL14D | LDQ17 | | -| B4/7 | hades_drop_cmp_buf[8] | | LVCMOS25_OUT | PL14B | LDQ17 | | -| B5/7 | hades_hit_valid[1] | | LVCMOS25_OUT | PL11C | LDQ17 | | -| B6/0 | hades_dbg2_coarse[4] | | LVCMOS25_OUT | PT4B | ULC_GPLL1C_IN | | -| B8/0 | hades_dbg2_out[12] | | LVCMOS25_OUT | PT15B | | | -| B9/0 | hades_offset[7] | | LVCMOS25_OUT | PT31A | | | -| B10/0 | hades_drop_cmp_buf_coarse[2] | | LVCMOS25_OUT | PT33B | GR_PCLK0_0 | | -| B11/0 | hades_discard | | LVCMOS25_OUT | PT38A | PCLKT0_0 | | -| B12/1 | rd_clk | | LVCMOS25_IN | PT44A | PCLKT1_0 | | -| B13/1 | hades_drop_cmp_buf_coarse[8] | | LVCMOS25_OUT | PT51A | | | -| B15/1 | FEE_DATA_OUT[17] | | LVCMOS25_OUT | PT69A | | | -| B16/1 | fifo_data_out[6] | | LVCMOS25_OUT | PT74B | | | -| B17/1 | hades_drop_cmp_buf[10] | | LVCMOS25_OUT | PT78A | | | -| B18/1 | unused, PULL:DOWN | | | PT80B | | | -| B19/1 | unused, PULL:DOWN | | | PT83B | | | -| B20/1 | hades_drop_cmp_buf[9] | | LVCMOS25_OUT | PT85B | URC_GPLL1C_IN | | -| C1/7 | hades_offset[4] | | LVCMOS25_OUT | PL26A | LDQ29 | | -| C2/7 | hades_dbg2_coarse[3] | | LVCMOS25_OUT | PL23D | LDQ29 | | -| C3/7 | hades_dbg2_out[5] | | LVCMOS25_OUT | PL17C | LDQ17 | | -| C4/7 | hades_drop_cmp_buf[5] | | LVCMOS25_OUT | PL14A | LDQ17 | | -| C5/7 | hades_hit_valid[3] | | LVCMOS25_OUT | PL11D | LDQ17 | | -| C6/0 | hades_drop_cmp_buf[3] | | LVCMOS25_OUT | PT11A | | | -| C7/0 | hades_dbg2_out[9] | | LVCMOS25_OUT | PT11B | | | -| C8/0 | reset_dc | | LVCMOS25_IN | PT15A | | | -| C9/0 | hades_buf_out_valid | | LVCMOS25_OUT | PT27A | | | -| C10/0 | hades_offset[1] | | LVCMOS25_OUT | PT31B | | | -| C11/0 | hades_hit_out_i[1] | | LVCMOS25_OUT | PT38B | | | -| C12/1 | hades_drop_cmp_buf_coarse[3] | | LVCMOS25_OUT | PT44B | | | -| C13/1 | FEE_DATA_WRITE_OUT | | LVCMOS25_OUT | PT51B | | | -| C14/1 | hades_window_end | | LVCMOS25_OUT | PT56B | | | -| C15/1 | fifo_data_out[17] | | LVCMOS25_OUT | PT69B | | | -| C16/1 | hades_dbg2_out[3] | | LVCMOS25_OUT | PT76A | | | -| C17/1 | hades_dbg2_out[15] | | LVCMOS25_OUT | PT78B | | | -| C18/2 | unused, PULL:DOWN | | | PR11A | URC_GPLL0T_IN/RDQ17 | | -| C20/2 | FEE_DATA_OUT[27] | | LVCMOS25_OUT | PR23A | RDQ29 | | -| CCLK/8 | | | | CCLK | MCLK/SCK | | -| D1/7 | hades_offset[3] | | LVCMOS25_OUT | PL26B | LDQ29 | | -| D2/7 | hades_offset[5] | | LVCMOS25_OUT | PL26C | LDQ29 | | -| D3/7 | hades_drop_cmp_buf[0] | | LVCMOS25_OUT | PL17D | LDQ17 | | -| D5/7 | hades_drop_cmp_buf[7] | | LVCMOS25_OUT | PL17B | LDQSN17 | | -| D6/0 | hades_dbg2_out[11] | | LVCMOS25_OUT | PT6B | | | -| D7/0 | hades_hit_out_i[3] | | LVCMOS25_OUT | PT9B | | | -| D8/0 | hades_drop_cmp_buf[6] | | LVCMOS25_OUT | PT13B | | | -| D9/0 | hades_drop_cmp_buf[1] | | LVCMOS25_OUT | PT20A | | | -| D10/0 | hades_offset[0] | | LVCMOS25_OUT | PT29A | | | -| D11/1 | hades_drop_cmp_buf_coarse[7] | | LVCMOS25_OUT | PT42A | PCLKT1_1 | | -| D12/1 | hades_drop_cmp_buf_coarse[5] | | LVCMOS25_OUT | PT47A | GR_PCLK1_0 | | -| D13/1 | FEE_DATAFINISHED_OUT | | LVCMOS25_OUT | PT53A | | | -| D14/1 | finished | | LVCMOS25_OUT | PT58A | | | -| D15/1 | hades_offset_valid | | LVCMOS25_OUT | PT71A | | | -| D16/1 | unused, PULL:DOWN | | | PT76B | | | -| D17/2 | fifo_data_out[5] | | LVCMOS25_OUT | PR11B | URC_GPLL0C_IN/RDQ17 | | -| D18/2 | hades_drop_cmp_buf_coarse[11] | | LVCMOS25_OUT | PR14A | RDQ17 | | -| D19/2 | fifo_data_out[27] | | LVCMOS25_OUT | PR23B | RDQ29 | | -| D20/2 | FEE_DATA_OUT[30] | | LVCMOS25_OUT | PR23C | VREF1_2/RDQ29 | | -| E1/7 | hades_lvl1 | LOCATED | LVCMOS25_IN | PL26D | LDQ29 | | -| E2/7 | hades_dbg2_out[1] | | LVCMOS25_OUT | PL32D | PCLKC7_0/LDQ29 | | -| E3/7 | hades_dbg2_coarse[2] | | LVCMOS25_OUT | PL20B | LDQ17 | | -| E4/7 | hades_dbg2_out[4] | | LVCMOS25_OUT | PL17A | LDQS17 | | -| E5/7 | hades_dbg2_coarse[6] | | LVCMOS25_OUT | PL20C | LDQ17 | | -| E6/0 | hades_hit_out_i[2] | | LVCMOS25_OUT | PT6A | | | -| E7/0 | hades_buf_release | | LVCMOS25_OUT | PT9A | | | -| E8/0 | hades_dbg2_out[8] | | LVCMOS25_OUT | PT13A | | | -| E9/0 | hades_hit_out_i[0] | | LVCMOS25_OUT | PT20B | | | -| E10/0 | hades_offset[2] | | LVCMOS25_OUT | PT29B | | | -| E11/1 | hades_drop_cmp_buf_coarse[6] | | LVCMOS25_OUT | PT42B | | | -| E12/1 | hades_drop_cmp_buf_coarse[4] | | LVCMOS25_OUT | PT47B | GR_PCLK1_1 | | -| E13/1 | FEE_TRG_RELEASE_OUT | | LVCMOS25_OUT | PT53B | | | -| E14/1 | fifo_data_out[18] | | LVCMOS25_OUT | PT58B | | | -| E15/1 | hades_raw_out_valid | | LVCMOS25_OUT | PT71B | | | -| E16/2 | hades_dbg2_out[30] | | LVCMOS25_OUT | PR11C | RDQ17 | | -| E17/2 | hades_raw_valid_vect[1] | | LVCMOS25_OUT | PR14B | RDQ17 | | -| E18/2 | FEE_DATA_OUT[4] | | LVCMOS25_OUT | PR14C | RDQ17 | | -| E19/2 | fifo_data_out[30] | | LVCMOS25_OUT | PR23D | RDQ29 | | -| E20/2 | fifo_data_out[9] | | LVCMOS25_OUT | PR26A | RDQ29 | | -| F1/6 | hades_dbg2_coarse[8] | | LVCMOS25_OUT | PL35B | PCLKC6_1/LDQ41 | | -| F2/7 | hades_dbg2_out[27] | | LVCMOS25_OUT | PL32C | PCLKT7_0/LDQ29 | | -| F3/7 | hades_dbg2_out[2] | | LVCMOS25_OUT | PL32B | PCLKC7_1/LDQ29 | | -| F4/7 | hades_dbg2_out[6] | | LVCMOS25_OUT | PL20A | LDQ17 | | -| F5/7 | hades_drop_cmp_buf[4] | | LVCMOS25_OUT | PL20D | LDQ17 | | -| F16/2 | FEE_DATA_OUT[5] | | LVCMOS25_OUT | PR11D | RDQ17 | | -| F17/2 | fifo_data_out[2] | | LVCMOS25_OUT | PR17A | RDQS17 | | -| F18/2 | fifo_data_out[4] | | LVCMOS25_OUT | PR14D | RDQ17 | | -| F19/2 | FEE_DATA_OUT[28] | | LVCMOS25_OUT | PR26B | RDQ29 | | -| F20/2 | FEE_DATA_OUT[9] | | LVCMOS25_OUT | PR26C | RDQ29 | | -| G1/6 | hades_dbg2_out[17] | | LVCMOS25_OUT | PL35D | PCLKC6_0/LDQ41 | | -| G2/6 | hades_dbg2_out[21] | | LVCMOS25_OUT | PL35A | PCLKT6_1/LDQ41 | | -| G3/7 | hades_dbg2_out[16] | | LVCMOS25_OUT | PL32A | PCLKT7_1/LDQ29 | | -| G5/7 | hades_dbg2_coarse[0] | | LVCMOS25_OUT | PL29B | LDQSN29 | | -| G16/2 | FEE_DATA_OUT[13] | | LVCMOS25_OUT | PR17C | RDQ17 | | -| G18/2 | FEE_DATA_OUT[2] | | LVCMOS25_OUT | PR17B | RDQSN17 | | -| G19/2 | FEE_DATA_OUT[21] | | LVCMOS25_OUT | PR29A | GR_PCLK2_1/RDQS29 | | -| G20/2 | fifo_data_out[28] | | LVCMOS25_OUT | PR26D | RDQ29 | | -| H1/6 | hades_dbg2_out[24] | | LVCMOS25_OUT | PL41C | LDQ41 | | -| H2/6 | hades_dbg2_out[28] | | LVCMOS25_OUT | PL35C | PCLKT6_0/LDQ41 | | -| H3/7 | hades_dbg2_coarse[1] | | LVCMOS25_OUT | PL29D | LDQ29 | | -| H4/7 | hades_dbg2_out[22] | | LVCMOS25_OUT | PL29A | GR_PCLK7_1/LDQS29 | | -| H5/7 | hades_trig | LOCATED | LVCMOS25_IN | PL29C | GR_PCLK7_0/LDQ29 | | -| H16/2 | fifo_data_out[31] | | LVCMOS25_OUT | PR17D | RDQ17 | | -| H17/2 | FEE_DATA_OUT[25] | | LVCMOS25_OUT | PR20B | RDQ17 | | -| H18/2 | FEE_DATA_OUT[31] | | LVCMOS25_OUT | PR20A | RDQ17 | | -| H20/2 | FEE_DATA_OUT[23] | | LVCMOS25_OUT | PR29B | RDQSN29 | | -| J1/6 | hades_dbg2_out[25] | | LVCMOS25_OUT | PL41B | LDQSN41 | | -| J3/6 | hades_dbg2_out[0] | | LVCMOS25_OUT | PL38C | GR_PCLK6_1/LDQ41 | | -| J4/6 | hades_dbg2_out[23] | | LVCMOS25_OUT | PL38A | GR_PCLK6_0/LDQ41 | | -| J5/6 | hades_dbg2_out[18] | | LVCMOS25_OUT | PL38B | LDQ41 | | -| J16/2 | fifo_data_out[13] | | LVCMOS25_OUT | PR20D | RDQ17 | | -| J17/2 | fifo_data_out[25] | | LVCMOS25_OUT | PR20C | RDQ17 | | -| J18/2 | fifo_data_out[23] | | LVCMOS25_OUT | PR29C | GR_PCLK2_0/RDQ29 | | -| J19/2 | FEE_DATA_OUT[10] | | LVCMOS25_OUT | PR32A | PCLKT2_1/RDQ29 | | -| J20/2 | fifo_data_out[15] | | LVCMOS25_OUT | PR32C | PCLKT2_0/RDQ29 | | -| K1/6 | hades_dbg2_out[26] | | LVCMOS25_OUT | PL41D | LDQ41 | | -| K2/6 | hades_invalid_dl[2] | | LVCMOS25_OUT | PL41A | LDQS41 | | -| K3/6 | hades_dbg2_out[20] | | LVCMOS25_OUT | PL38D | LDQ41 | | -| K4/6 | hades_invalid_dl[3] | | LVCMOS25_OUT | PL44A | LDQ41 | | -| K5/6 | FEE_DATA_OUT[19] | | LVCMOS25_OUT | PL44B | VREF1_6/LDQ41 | | -| K18/2 | fifo_data_out[21] | | LVCMOS25_OUT | PR29D | RDQ29 | | -| K19/2 | FEE_DATA_OUT[24] | | LVCMOS25_OUT | PR32B | PCLKC2_1/RDQ29 | | -| K20/2 | fifo_data_out[10] | | LVCMOS25_OUT | PR32D | PCLKC2_0/RDQ29 | | -| L1/6 | unused, PULL:DOWN | | | PL65C | LDQ65 | | -| L2/6 | unused, PULL:DOWN | | | PL62D | LDQ65 | | -| L3/6 | FEE_DATA_OUT[7] | | LVCMOS25_OUT | PL62C | LDQ65 | | -| L4/6 | fifo_data_out[19] | | LVCMOS25_OUT | PL44C | LDQ41 | | -| L5/6 | hades_invalid_dl[1] | | LVCMOS25_OUT | PL44D | LDQ41 | | -| L16/3 | FEE_DATA_OUT[8] | | LVCMOS25_OUT | PR38A | GR_PCLK3_0/RDQ41 | | -| L17/3 | fifo_data_out[3] | | LVCMOS25_OUT | PR38B | RDQ41 | | -| L18/3 | last_buf_empty | | LVCMOS25_OUT | PR38C | GR_PCLK3_1/RDQ41 | | -| L19/3 | FEE_DATA_OUT[26] | | LVCMOS25_OUT | PR35C | PCLKT3_0/RDQ41 | | -| L20/3 | fifo_data_out[26] | | LVCMOS25_OUT | PR35A | PCLKT3_1/RDQ41 | | -| M1/6 | unused, PULL:DOWN | | | PL65B | LDQSN65 | | -| M3/6 | fifo_data_out[1] | | LVCMOS25_OUT | PL62B | LDQ65 | | -| M4/6 | fifo_data_out[14] | | LVCMOS25_OUT | PL59A | LDQ65 | | -| M5/6 | hades_dbg2_coarse[7] | | LVCMOS25_OUT | PL53A | LDQS53 | | -| M17/3 | FEE_DATA_OUT[3] | | LVCMOS25_OUT | PR41B | RDQSN41 | | -| M18/3 | fifo_data_out[8] | | LVCMOS25_OUT | PR38D | RDQ41 | | -| M19/3 | FEE_DATA_OUT[15] | | LVCMOS25_OUT | PR35D | PCLKC3_0/RDQ41 | | -| M20/3 | fifo_data_out[24] | | LVCMOS25_OUT | PR35B | PCLKC3_1/RDQ41 | | -| N1/6 | fifo_data_out[7] | | LVCMOS25_OUT | PL65D | LDQ65 | | -| N2/6 | unused, PULL:DOWN | | | PL65A | LDQS65 | | -| N3/6 | FEE_DATA_OUT[1] | | LVCMOS25_OUT | PL62A | LDQ65 | | -| N4/6 | fifo_data_out[12] | | LVCMOS25_OUT | PL59C | LDQ65 | | -| N5/6 | FEE_DATA_OUT[12] | | LVCMOS25_OUT | PL59B | LDQ65 | | -| N16/3 | burst | | LVCMOS25_OUT | PR41A | RDQS41 | | -| N17/3 | fifo_empty1 | | LVCMOS25_OUT | PR44A | RDQ41 | | -| N18/3 | LVL1_TRG_DATA_VALI_IN_rising | | LVCMOS25_OUT | PR41C | RDQ41 | | -| N19/3 | FEE_DATA_OUT[16] | | LVCMOS25_OUT | PR59A | RDQ65 | | -| N20/3 | hades_buf_drop[0] | | LVCMOS25_OUT | PR59B | RDQ65 | | -| P1/6 | hades_dbg2_out[14] | | LVCMOS25_OUT | PL68A | LDQ65 | | -| P2/6 | unused, PULL:DOWN | | | PL68B | LDQ65 | | -| P3/6 | clk+ | LOCATED | LVDS_IN | PL68C | LLC_GPLL0T_IN/LDQ65 | | -| P4/6 | clk- | | LVDS_IN | PL68D | LLC_GPLL0C_IN/LDQ65 | | -| P5/6 | FEE_DATA_OUT[14] | | LVCMOS25_OUT | PL59D | LDQ65 | | -| P16/3 | discard | | LVCMOS25_OUT | PR44B | VREF1_3/RDQ41 | | -| P17/3 | fifo_data_out[0] | | LVCMOS25_OUT | PR41D | RDQ41 | | -| P18/3 | fifo_data_out[16] | | LVCMOS25_OUT | PR59D | RDQ65 | | -| P19/3 | hades_dbg2_out[13] | | LVCMOS25_OUT | PR59C | RDQ65 | | -| P20/3 | unused, PULL:DOWN | | | PR62A | RDQ65 | | -| PL47A/6 | unused, PULL:DOWN | | | PL47A | LDQ53 | | -| PL47B/6 | unused, PULL:DOWN | | | PL47B | LDQ53 | | -| PL47C/6 | unused, PULL:DOWN | | | PL47C | LDQ53 | | -| PL47D/6 | unused, PULL:DOWN | | | PL47D | LDQ53 | | -| PL50A/6 | unused, PULL:DOWN | | | PL50A | LDQ53 | | -| PL50B/6 | unused, PULL:DOWN | | | PL50B | LDQ53 | | -| PL50C/6 | unused, PULL:DOWN | | | PL50C | LDQ53 | | -| PL50D/6 | unused, PULL:DOWN | | | PL50D | LDQ53 | | -| PL53B/6 | unused, PULL:DOWN | | | PL53B | LDQSN53 | | -| PL53C/6 | unused, PULL:DOWN | | | PL53C | LDQ53 | | -| PL53D/6 | unused, PULL:DOWN | | | PL53D | LDQ53 | | -| PL56A/6 | unused, PULL:DOWN | | | PL56A | LDQ53 | | -| PL56B/6 | unused, PULL:DOWN | | | PL56B | LDQ53 | | -| PL56C/6 | unused, PULL:DOWN | | | PL56C | LDQ53 | | -| PL56D/6 | unused, PULL:DOWN | | | PL56D | LDQ53 | | -| PR47A/3 | unused, PULL:DOWN | | | PR47A | RDQ53 | | -| PR47B/3 | unused, PULL:DOWN | | | PR47B | RDQ53 | | -| PR47C/3 | unused, PULL:DOWN | | | PR47C | RDQ53 | | -| PR47D/3 | unused, PULL:DOWN | | | PR47D | RDQ53 | | -| PR50A/3 | unused, PULL:DOWN | | | PR50A | RDQ53 | | -| PR50B/3 | unused, PULL:DOWN | | | PR50B | RDQ53 | | -| PR50C/3 | unused, PULL:DOWN | | | PR50C | RDQ53 | | -| PR50D/3 | unused, PULL:DOWN | | | PR50D | RDQ53 | | -| PR53B/3 | unused, PULL:DOWN | | | PR53B | RDQSN53 | | -| PR53C/3 | unused, PULL:DOWN | | | PR53C | RDQ53 | | -| PR53D/3 | unused, PULL:DOWN | | | PR53D | RDQ53 | | -| PR56A/3 | unused, PULL:DOWN | | | PR56A | RDQ53 | | -| PR56B/3 | unused, PULL:DOWN | | | PR56B | RDQ53 | | -| PR56C/3 | unused, PULL:DOWN | | | PR56C | RDQ53 | | -| PR56D/3 | unused, PULL:DOWN | | | PR56D | RDQ53 | | -| PT22A/0 | unused, PULL:DOWN | | | PT22A | | | -| PT22B/0 | unused, PULL:DOWN | | | PT22B | | | -| PT24A/0 | unused, PULL:DOWN | | | PT24A | | | -| PT24B/0 | unused, PULL:DOWN | | | PT24B | | | -| PT27B/0 | unused, PULL:DOWN | | | PT27B | | | -| PT60A/1 | unused, PULL:DOWN | | | PT60A | | | -| PT60B/1 | unused, PULL:DOWN | | | PT60B | | | -| PT62A/1 | unused, PULL:DOWN | | | PT62A | | | -| PT62B/1 | unused, PULL:DOWN | | | PT62B | | | -| PT65A/1 | unused, PULL:DOWN | | | PT65A | | | -| PT65B/1 | unused, PULL:DOWN | | | PT65B | | | -| PT67B/1 | unused, PULL:DOWN | | | PT67B | | | -| R1/8 | hades_dbg2_out[19] | | LVCMOS25_OUT | PB4A | D7/IO7 | | -| R2/8 | trig[0] | LOCATED | LVCMOS25_IN | PB15A | HOLDN/DI/BUSY/CSSPIN/CEN | | -| R3/8 | FEE_DATA_OUT[11] | | LVCMOS25_OUT | PB15B | DOUT/CSON | | -| R16/3 | LVL1_INVALID_TRG_IN | | LVCMOS25_IN | PR44C | RDQ41 | | -| R17/3 | FEE_DATA_OUT[0] | | LVCMOS25_OUT | PR44D | RDQ41 | | -| R18/3 | hades_dbg2_out[31] | | LVCMOS25_OUT | PR65B | RDQSN65 | | -| R20/3 | hades_buf_drop[2] | | LVCMOS25_OUT | PR62B | RDQ65 | | -| T1/8 | fifo_data_out[29] | | LVCMOS25_OUT | PB4B | D6/IO6 | | -| T2/8 | FEE_DATA_OUT[22] | | LVCMOS25_OUT | PB13A | SN/CSN | | -| T3/8 | trig[1] | LOCATED | LVCMOS25_IN | PB18A | WRITEN | | -| T16/3 | unused, PULL:DOWN | | | PR53A | RDQS53 | | -| T17/3 | hades_drop_cmp_buf_coarse[10] | | LVCMOS25_OUT | PR68D | LRC_GPLL0C_IN/RDQ65 | | -| T18/3 | unused, PULL:DOWN | | | PR65D | RDQ65 | | -| T19/3 | trig[2] | LOCATED | LVCMOS25_IN | PR65A | RDQS65 | | -| T20/3 | unused, PULL:DOWN | | | PR62C | RDQ65 | | -| TCK/40 | | | | TCK | | | -| TDI/40 | | | | TDI | | | -| TDO/40 | | | | TDO | | | -| TMS/40 | | | | TMS | | | -| U1/8 | FEE_DATA_OUT[29] | | LVCMOS25_OUT | PB6A | D5/MISO2/IO5 | | -| U2/8 | fifo_data_out[11] | | LVCMOS25_OUT | PB13B | CS1N | | -| U16/3 | hades_buf_drop[3] | | LVCMOS25_OUT | PR68C | LRC_GPLL0T_IN/RDQ65 | | -| U17/3 | hades_drop_cmp_buf[11] | | LVCMOS25_OUT | PR68B | RDQ65 | | -| U18/3 | unused, PULL:DOWN | | | PR68A | RDQ65 | | -| U19/3 | unused, PULL:DOWN | | | PR65C | RDQ65 | | -| U20/3 | hades_raw_valid_vect[0] | | LVCMOS25_OUT | PR62D | RDQ65 | | -| V1/8 | FEE_DATA_OUT[20] | | LVCMOS25_OUT | PB6B | D4/MOSI2/IO4 | | -| V2/8 | hades_invalid_dl[0] | | LVCMOS25_OUT | PB11A | D1/MISO/IO1 | | -| W1/8 | fifo_data_out[22] | | LVCMOS25_OUT | PB9A | D3/IO3 | | -| W2/8 | hades_lvl1_invalid | | LVCMOS25_IN | PB11B | D0/MOSI/IO0 | | -| W4/50 | | | | HDTXP0_D0CH0 | | | -| W5/50 | | | | HDTXN0_D0CH0 | | | -| W8/50 | | | | HDTXP0_D0CH1 | | | -| W9/50 | | | | HDTXN0_D0CH1 | | | -| W13/51 | | | | HDTXP0_D1CH0 | | | -| W14/51 | | | | HDTXN0_D1CH0 | | | -| W17/51 | | | | HDTXP0_D1CH1 | | | -| W18/51 | | | | HDTXN0_D1CH1 | | | -| W20/51 | | | | REFCLKN_D1 | | | -| Y2/8 | fifo_data_out[20] | | LVCMOS25_OUT | PB9B | D2/IO2 | | -| Y5/50 | | | | HDRXP0_D0CH0 | | | -| Y6/50 | | | | HDRXN0_D0CH0 | | | -| Y7/50 | | | | HDRXP0_D0CH1 | | | -| Y8/50 | | | | HDRXN0_D0CH1 | | | -| Y11/50 | | | | REFCLKP_D0 | | | -| Y12/50 | | | | REFCLKN_D0 | | | -| Y14/51 | | | | HDRXP0_D1CH0 | | | -| Y15/51 | | | | HDRXN0_D1CH0 | | | -| Y16/51 | | | | HDRXP0_D1CH1 | | | -| Y17/51 | | | | HDRXN0_D1CH1 | | | -| Y19/51 | | | | REFCLKP_D1 | | | -+----------+-------------------------------+------------+--------------+--------------+--------------------------+-----------+ - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "FEE_DATAFINISHED_OUT" SITE "D13"; -LOCATE COMP "FEE_DATA_OUT[0]" SITE "R17"; -LOCATE COMP "FEE_DATA_OUT[10]" SITE "J19"; -LOCATE COMP "FEE_DATA_OUT[11]" SITE "R3"; -LOCATE COMP "FEE_DATA_OUT[12]" SITE "N5"; -LOCATE COMP "FEE_DATA_OUT[13]" SITE "G16"; -LOCATE COMP "FEE_DATA_OUT[14]" SITE "P5"; -LOCATE COMP "FEE_DATA_OUT[15]" SITE "M19"; -LOCATE COMP "FEE_DATA_OUT[16]" SITE "N19"; -LOCATE COMP "FEE_DATA_OUT[17]" SITE "B15"; -LOCATE COMP "FEE_DATA_OUT[18]" SITE "A15"; -LOCATE COMP "FEE_DATA_OUT[19]" SITE "K5"; -LOCATE COMP "FEE_DATA_OUT[1]" SITE "N3"; -LOCATE COMP "FEE_DATA_OUT[20]" SITE "V1"; -LOCATE COMP "FEE_DATA_OUT[21]" SITE "G19"; -LOCATE COMP "FEE_DATA_OUT[22]" SITE "T2"; -LOCATE COMP "FEE_DATA_OUT[23]" SITE "H20"; -LOCATE COMP "FEE_DATA_OUT[24]" SITE "K19"; -LOCATE COMP "FEE_DATA_OUT[25]" SITE "H17"; -LOCATE COMP "FEE_DATA_OUT[26]" SITE "L19"; -LOCATE COMP "FEE_DATA_OUT[27]" SITE "C20"; -LOCATE COMP "FEE_DATA_OUT[28]" SITE "F19"; -LOCATE COMP "FEE_DATA_OUT[29]" SITE "U1"; -LOCATE COMP "FEE_DATA_OUT[2]" SITE "G18"; -LOCATE COMP "FEE_DATA_OUT[30]" SITE "D20"; -LOCATE COMP "FEE_DATA_OUT[31]" SITE "H18"; -LOCATE COMP "FEE_DATA_OUT[3]" SITE "M17"; -LOCATE COMP "FEE_DATA_OUT[4]" SITE "E18"; -LOCATE COMP "FEE_DATA_OUT[5]" SITE "F16"; -LOCATE COMP "FEE_DATA_OUT[6]" SITE "A16"; -LOCATE COMP "FEE_DATA_OUT[7]" SITE "L3"; -LOCATE COMP "FEE_DATA_OUT[8]" SITE "L16"; -LOCATE COMP "FEE_DATA_OUT[9]" SITE "F20"; -LOCATE COMP "FEE_DATA_WRITE_OUT" SITE "C13"; -LOCATE COMP "FEE_TRG_RELEASE_OUT" SITE "E13"; -LOCATE COMP "LVL1_INVALID_TRG_IN" SITE "R16"; -LOCATE COMP "LVL1_TRG_DATA_VALID_IN" SITE "A9"; -LOCATE COMP "LVL1_TRG_DATA_VALI_IN_rising" SITE "N18"; -LOCATE COMP "burst" SITE "N16"; -LOCATE COMP "clk" SITE "P3"; -LOCATE COMP "discard" SITE "P16"; -LOCATE COMP "fifo_data_out[0]" SITE "P17"; -LOCATE COMP "fifo_data_out[10]" SITE "K20"; -LOCATE COMP "fifo_data_out[11]" SITE "U2"; -LOCATE COMP "fifo_data_out[12]" SITE "N4"; -LOCATE COMP "fifo_data_out[13]" SITE "J16"; -LOCATE COMP "fifo_data_out[14]" SITE "M4"; -LOCATE COMP "fifo_data_out[15]" SITE "J20"; -LOCATE COMP "fifo_data_out[16]" SITE "P18"; -LOCATE COMP "fifo_data_out[17]" SITE "C15"; -LOCATE COMP "fifo_data_out[18]" SITE "E14"; -LOCATE COMP "fifo_data_out[19]" SITE "L4"; -LOCATE COMP "fifo_data_out[1]" SITE "M3"; -LOCATE COMP "fifo_data_out[20]" SITE "Y2"; -LOCATE COMP "fifo_data_out[21]" SITE "K18"; -LOCATE COMP "fifo_data_out[22]" SITE "W1"; -LOCATE COMP "fifo_data_out[23]" SITE "J18"; -LOCATE COMP "fifo_data_out[24]" SITE "M20"; -LOCATE COMP "fifo_data_out[25]" SITE "J17"; -LOCATE COMP "fifo_data_out[26]" SITE "L20"; -LOCATE COMP "fifo_data_out[27]" SITE "D19"; -LOCATE COMP "fifo_data_out[28]" SITE "G20"; -LOCATE COMP "fifo_data_out[29]" SITE "T1"; -LOCATE COMP "fifo_data_out[2]" SITE "F17"; -LOCATE COMP "fifo_data_out[30]" SITE "E19"; -LOCATE COMP "fifo_data_out[31]" SITE "H16"; -LOCATE COMP "fifo_data_out[3]" SITE "L17"; -LOCATE COMP "fifo_data_out[4]" SITE "F18"; -LOCATE COMP "fifo_data_out[5]" SITE "D17"; -LOCATE COMP "fifo_data_out[6]" SITE "B16"; -LOCATE COMP "fifo_data_out[7]" SITE "N1"; -LOCATE COMP "fifo_data_out[8]" SITE "M18"; -LOCATE COMP "fifo_data_out[9]" SITE "E20"; -LOCATE COMP "fifo_empty1" SITE "N17"; -LOCATE COMP "fifo_rden" SITE "A19"; -LOCATE COMP "finished" SITE "D14"; -LOCATE COMP "hades_buf_drop[0]" SITE "N20"; -LOCATE COMP "hades_buf_drop[1]" SITE "A10"; -LOCATE COMP "hades_buf_drop[2]" SITE "R20"; -LOCATE COMP "hades_buf_drop[3]" SITE "U16"; -LOCATE COMP "hades_buf_finished" SITE "A4"; -LOCATE COMP "hades_buf_out_valid" SITE "C9"; -LOCATE COMP "hades_buf_release" SITE "E7"; -LOCATE COMP "hades_dbg2_coarse[0]" SITE "G5"; -LOCATE COMP "hades_dbg2_coarse[1]" SITE "H3"; -LOCATE COMP "hades_dbg2_coarse[2]" SITE "E3"; -LOCATE COMP "hades_dbg2_coarse[3]" SITE "C2"; -LOCATE COMP "hades_dbg2_coarse[4]" SITE "B6"; -LOCATE COMP "hades_dbg2_coarse[5]" SITE "B1"; -LOCATE COMP "hades_dbg2_coarse[6]" SITE "E5"; -LOCATE COMP "hades_dbg2_coarse[7]" SITE "M5"; -LOCATE COMP "hades_dbg2_coarse[8]" SITE "F1"; -LOCATE COMP "hades_dbg2_out[0]" SITE "J3"; -LOCATE COMP "hades_dbg2_out[10]" SITE "A8"; -LOCATE COMP "hades_dbg2_out[11]" SITE "D6"; -LOCATE COMP "hades_dbg2_out[12]" SITE "B8"; -LOCATE COMP "hades_dbg2_out[13]" SITE "P19"; -LOCATE COMP "hades_dbg2_out[14]" SITE "P1"; -LOCATE COMP "hades_dbg2_out[15]" SITE "C17"; -LOCATE COMP "hades_dbg2_out[16]" SITE "G3"; -LOCATE COMP "hades_dbg2_out[17]" SITE "G1"; -LOCATE COMP "hades_dbg2_out[18]" SITE "J5"; -LOCATE COMP "hades_dbg2_out[19]" SITE "R1"; -LOCATE COMP "hades_dbg2_out[1]" SITE "E2"; -LOCATE COMP "hades_dbg2_out[20]" SITE "K3"; -LOCATE COMP "hades_dbg2_out[21]" SITE "G2"; -LOCATE COMP "hades_dbg2_out[22]" SITE "H4"; -LOCATE COMP "hades_dbg2_out[23]" SITE "J4"; -LOCATE COMP "hades_dbg2_out[24]" SITE "H1"; -LOCATE COMP "hades_dbg2_out[25]" SITE "J1"; -LOCATE COMP "hades_dbg2_out[26]" SITE "K1"; -LOCATE COMP "hades_dbg2_out[27]" SITE "F2"; -LOCATE COMP "hades_dbg2_out[28]" SITE "H2"; -LOCATE COMP "hades_dbg2_out[29]" SITE "A17"; -LOCATE COMP "hades_dbg2_out[2]" SITE "F3"; -LOCATE COMP "hades_dbg2_out[30]" SITE "E16"; -LOCATE COMP "hades_dbg2_out[31]" SITE "R18"; -LOCATE COMP "hades_dbg2_out[3]" SITE "C16"; -LOCATE COMP "hades_dbg2_out[4]" SITE "E4"; -LOCATE COMP "hades_dbg2_out[5]" SITE "C3"; -LOCATE COMP "hades_dbg2_out[6]" SITE "F4"; -LOCATE COMP "hades_dbg2_out[7]" SITE "B3"; -LOCATE COMP "hades_dbg2_out[8]" SITE "E8"; -LOCATE COMP "hades_dbg2_out[9]" SITE "C7"; -LOCATE COMP "hades_discard" SITE "B11"; -LOCATE COMP "hades_drop_cmp_buf[0]" SITE "D3"; -LOCATE COMP "hades_drop_cmp_buf[10]" SITE "B17"; -LOCATE COMP "hades_drop_cmp_buf[11]" SITE "U17"; -LOCATE COMP "hades_drop_cmp_buf[1]" SITE "D9"; -LOCATE COMP "hades_drop_cmp_buf[2]" SITE "A6"; -LOCATE COMP "hades_drop_cmp_buf[3]" SITE "C6"; -LOCATE COMP "hades_drop_cmp_buf[4]" SITE "F5"; -LOCATE COMP "hades_drop_cmp_buf[5]" SITE "C4"; -LOCATE COMP "hades_drop_cmp_buf[6]" SITE "D8"; -LOCATE COMP "hades_drop_cmp_buf[7]" SITE "D5"; -LOCATE COMP "hades_drop_cmp_buf[8]" SITE "B4"; -LOCATE COMP "hades_drop_cmp_buf[9]" SITE "B20"; -LOCATE COMP "hades_drop_cmp_buf_coarse[0]" SITE "A11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[10]" SITE "T17"; -LOCATE COMP "hades_drop_cmp_buf_coarse[11]" SITE "D18"; -LOCATE COMP "hades_drop_cmp_buf_coarse[1]" SITE "A13"; -LOCATE COMP "hades_drop_cmp_buf_coarse[2]" SITE "B10"; -LOCATE COMP "hades_drop_cmp_buf_coarse[3]" SITE "C12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[4]" SITE "E12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[5]" SITE "D12"; -LOCATE COMP "hades_drop_cmp_buf_coarse[6]" SITE "E11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[7]" SITE "D11"; -LOCATE COMP "hades_drop_cmp_buf_coarse[8]" SITE "B13"; -LOCATE COMP "hades_drop_cmp_buf_coarse[9]" SITE "A12"; -LOCATE COMP "hades_drop_cmp_buf_valid" SITE "A7"; -LOCATE COMP "hades_hit_out_i[0]" SITE "E9"; -LOCATE COMP "hades_hit_out_i[1]" SITE "C11"; -LOCATE COMP "hades_hit_out_i[2]" SITE "E6"; -LOCATE COMP "hades_hit_out_i[3]" SITE "D7"; -LOCATE COMP "hades_hit_valid[0]" SITE "A3"; -LOCATE COMP "hades_hit_valid[1]" SITE "B5"; -LOCATE COMP "hades_hit_valid[2]" SITE "A5"; -LOCATE COMP "hades_hit_valid[3]" SITE "C5"; -LOCATE COMP "hades_invalid_dl[0]" SITE "V2"; -LOCATE COMP "hades_invalid_dl[1]" SITE "L5"; -LOCATE COMP "hades_invalid_dl[2]" SITE "K2"; -LOCATE COMP "hades_invalid_dl[3]" SITE "K4"; -LOCATE COMP "hades_lvl1" SITE "E1"; -LOCATE COMP "hades_lvl1_invalid" SITE "W2"; -LOCATE COMP "hades_offset[0]" SITE "D10"; -LOCATE COMP "hades_offset[1]" SITE "C10"; -LOCATE COMP "hades_offset[2]" SITE "E10"; -LOCATE COMP "hades_offset[3]" SITE "D1"; -LOCATE COMP "hades_offset[4]" SITE "C1"; -LOCATE COMP "hades_offset[5]" SITE "D2"; -LOCATE COMP "hades_offset[6]" SITE "A2"; -LOCATE COMP "hades_offset[7]" SITE "B9"; -LOCATE COMP "hades_offset[8]" SITE "B2"; -LOCATE COMP "hades_offset_valid" SITE "D15"; -LOCATE COMP "hades_raw_out_valid" SITE "E15"; -LOCATE COMP "hades_raw_valid_vect[0]" SITE "U20"; -LOCATE COMP "hades_raw_valid_vect[1]" SITE "E17"; -LOCATE COMP "hades_trig" SITE "H5"; -LOCATE COMP "hades_window_end" SITE "C14"; -LOCATE COMP "last_buf_empty" SITE "L18"; -LOCATE COMP "rd_clk" SITE "B12"; -LOCATE COMP "release_out" SITE "A14"; -LOCATE COMP "reset_dc" SITE "C8"; -LOCATE COMP "trig[0]" SITE "R2"; -LOCATE COMP "trig[1]" SITE "T3"; -LOCATE COMP "trig[2]" SITE "T19"; - -#PLL -LOCATE COMP "pll0inst/PLLInst_0" SITE "PLL_BL0" ; - - - - -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:20:03 2021 - diff --git a/impl1/s1_impl1.dir/5_1.par b/impl1/s1_impl1.dir/5_1.par deleted file mode 100644 index da19d19..0000000 --- a/impl1/s1_impl1.dir/5_1.par +++ /dev/null @@ -1,296 +0,0 @@ - -Lattice Place and Route Report for Design "s1_impl1_map.ncd" -Wed Jun 16 09:19:35 2021 - -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Command Line: par -w -l 5 -i 6 -y -t 1 -c 0 -e 0 -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF s1_impl1_map.ncd s1_impl1.dir/5_1.ncd s1_impl1.prf -Preference file: s1_impl1.prf. -Placement level-cost: 5-1. -Routing Iterations: 6 - -Loading design for application par from file s1_impl1_map.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 8 -Loading device for application par from file 'sa5p45m.nph' in environment: /home/soft/lattice/diamond/3.11_x64/ispfpga. -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -License checked out. - - -Ignore Preference Error(s): True -Device utilization summary: - - PIO (prelim) 187/245 76% used - 187/203 92% bonded - IOLOGIC 35/245 14% used - - SLICE 692/21924 3% used - - EBR 4/108 3% used - PLL 1/4 25% used - - -Number of Signals: 1594 -Number of Connections: 3725 - -Pin Constraint Summary: - 7 out of 186 pins locked (3% locked). - -The following 5 signals are selected to use the primary clock routing resources: - pll_clks[0] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 25/0/0) - pll_clks[1] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - pll_clks[3] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 446/0/0) - rd_clk_c (driver: rd_clk, clk/ce/sr load #: 38/0/0) - pll_clks[2] (driver: pll0inst/PLLInst_0, clk/ce/sr load #: 24/0/0) - - -No signal is selected as Global Set/Reset. -. -Starting Placer Phase 0. -............. -Finished Placer Phase 0. REAL time: 8 secs - -Starting Placer Phase 1. -................. -Placer score = 788909. -Finished Placer Phase 1. REAL time: 24 secs - -Starting Placer Phase 2. -. -Placer score = 774601 -Finished Placer Phase 2. REAL time: 25 secs - - ------------------- Clock Report ------------------ - -Global Clock Resources: - CLK_PIN : 1 out of 12 (8%) - GR_PCLK : 0 out of 12 (0%) - PLL : 1 out of 4 (25%) - DCS : 0 out of 2 (0%) - DCC : 0 out of 60 (0%) - CLKDIV : 0 out of 4 (0%) - -Quadrant TL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 196 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 17 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 12 - - PRIMARY : 5 out of 16 (31%) - -Quadrant TR Clocks: - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 3 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 8 - - PRIMARY : 2 out of 16 (12%) - -Quadrant BL Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 5 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 132 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 4 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 4 - - PRIMARY : 5 out of 16 (31%) - -Quadrant BR Clocks: - PRIMARY "pll_clks[0]" from CLKOP on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[1]" from CLKOS on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - PRIMARY "pll_clks[3]" from CLKOS3 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 115 - PRIMARY "rd_clk_c" from comp "rd_clk" on CLK_PIN site "B12 (PT44A)", CLK/CE/SR load = 9 - PRIMARY "pll_clks[2]" from CLKOS2 on comp "pll0inst/PLLInst_0" on PLL site "PLL_BL0", CLK/CE/SR load = 8 - - PRIMARY : 5 out of 16 (31%) - -Edge Clocks: - - No edge clock selected. - - ---------------- End of Clock Report --------------- - - -+ -I/O Usage Summary (final): - 187 out of 245 (76.3%) PIO sites used. - 187 out of 203 (92.1%) bonded PIO sites used. - Number of PIO comps: 186; differential: 1. - Number of Vref pins used: 0. - -I/O Bank Usage Summary: -+----------+----------------+------------+------------+------------+ -| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | -+----------+----------------+------------+------------+------------+ -| 0 | 27 / 27 (100%) | 2.5V | - | - | -| 1 | 29 / 33 ( 87%) | 2.5V | - | - | -| 2 | 31 / 32 ( 96%) | 2.5V | - | - | -| 3 | 27 / 33 ( 81%) | 2.5V | - | - | -| 6 | 28 / 33 ( 84%) | 2.5V | - | - | -| 7 | 32 / 32 (100%) | 2.5V | - | - | -| 8 | 13 / 13 (100%) | 2.5V | - | - | -+----------+----------------+------------+------------+------------+ - -Total placer CPU time: 24 secs - -Dumping design to file s1_impl1.dir/5_1.ncd. - -0 connections routed; 3725 unrouted. -Starting router resource preassignment - -Completed router resource preassignment. Real time: 39 secs - -Start NBR router at Wed Jun 16 09:20:14 CEST 2021 - -***************************************************************** -Info: NBR allows conflicts(one node used by more than one signal) - in the earlier iterations. In each iteration, it tries to - solve the conflicts while keeping the critical connections - routed as short as possible. The routing process is said to - be completed when no conflicts exist and all connections - are routed. -Note: NBR uses a different method to calculate timing slacks. The - worst slack and total negative slack may not be the same as - that in TRCE report. You should always run TRCE to verify - your design. -***************************************************************** - -Start NBR special constraint process at Wed Jun 16 09:20:14 CEST 2021 - -Start NBR section for initial routing at Wed Jun 16 09:20:15 CEST 2021 -Level 1, iteration 1 -21(0.00%) conflicts; 2630(70.60%) untouched conns; 158654 (nbr) score; -Estimated worst slack/total negative slack: -2.876ns/-158.654ns; real time: 41 secs -Level 2, iteration 1 -46(0.00%) conflicts; 2243(60.21%) untouched conns; 159216 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-159.217ns; real time: 41 secs -Level 3, iteration 1 -167(0.01%) conflicts; 385(10.34%) untouched conns; 163305 (nbr) score; -Estimated worst slack/total negative slack: -2.962ns/-163.305ns; real time: 42 secs -Level 4, iteration 1 -81(0.00%) conflicts; 0(0.00%) untouched conn; 177384 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-177.384ns; real time: 42 secs - -Info: Initial congestion level at 75% usage is 0 -Info: Initial congestion area at 75% usage is 0 (0.00%) - -Start NBR section for normal routing at Wed Jun 16 09:20:17 CEST 2021 -Level 1, iteration 1 -53(0.00%) conflicts; 49(1.32%) untouched conns; 171398 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-171.398ns; real time: 43 secs -Level 4, iteration 1 -54(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 2 -35(0.00%) conflicts; 0(0.00%) untouched conn; 180675 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-180.675ns; real time: 43 secs -Level 4, iteration 3 -24(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 4 -12(0.00%) conflicts; 0(0.00%) untouched conn; 172068 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.068ns; real time: 43 secs -Level 4, iteration 5 -8(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 43 secs -Level 4, iteration 6 -5(0.00%) conflicts; 0(0.00%) untouched conn; 172304 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.304ns; real time: 44 secs -Level 4, iteration 7 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 8 -1(0.00%) conflict; 0(0.00%) untouched conn; 172750 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.750ns; real time: 44 secs -Level 4, iteration 9 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for performance tuning (iteration 1) at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 173131 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-173.131ns; real time: 44 secs - -Start NBR section for re-routing at Wed Jun 16 09:20:19 CEST 2021 -Level 4, iteration 1 -0(0.00%) conflict; 0(0.00%) untouched conn; 172896 (nbr) score; -Estimated worst slack/total negative slack: -2.994ns/-172.896ns; real time: 44 secs - -Start NBR section for post-routing at Wed Jun 16 09:20:19 CEST 2021 - -End NBR router with 0 unrouted connection - -NBR Summary ------------ - Number of unrouted connections : 0 (0.00%) - Number of connections with timing violations : 156 (4.19%) - Estimated worst slack : -2.994ns - Timing score : 209210 ------------ -Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. - - - -Total CPU time 46 secs -Total REAL time: 47 secs -Completely routed. -End of route. 3725 routed (100.00%); 0 unrouted. - -Generating "par" statistics. - - - The Delay Summary Report - - The SCORE FOR THIS DESIGN is: 284326 - - - The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 - - The AVERAGE CONNECTION DELAY for this design is: 0.79 ( 0.79) - The AVERAGE CONNECTION DELAY on CRITICAL NETS is: 0.00 ( 0.00) - The CLOCK SKEW AVERAGE for this design is: 0.03 - The MAXIMUM PIN DELAY IS: 4.32 ( 4.32) - The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.37 ( 3.37) - - Listing Pin Delays by value: (nsec) - - d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 - --------- --------- --------- --------- --------- --------- - 3725 0 0 0 0 0 - -Hold time timing score: 9, hold timing errors: 18 - - -Timing score: 209210 - -Dumping design to file s1_impl1.dir/5_1.ncd. - - -All signals are completely routed. - - -PAR_SUMMARY::Run status = Completed -PAR_SUMMARY::Number of unrouted conns = 0 -PAR_SUMMARY::Worst slack> = -2.994 -PAR_SUMMARY::Timing score> = 209.210 -PAR_SUMMARY::Worst slack> = -1.015 -PAR_SUMMARY::Timing score> = 9.647 -PAR_SUMMARY::Number of errors = 0 - -Total CPU time to completion: 48 secs -Total REAL time to completion: 48 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. diff --git a/impl1/s1_impl1.dir/5_1_par.asd b/impl1/s1_impl1.dir/5_1_par.asd deleted file mode 100644 index a3e7dbd..0000000 --- a/impl1/s1_impl1.dir/5_1_par.asd +++ /dev/null @@ -1,67 +0,0 @@ -[ActiveSupport PAR] -; Global primary clocks -GLOBAL_PRIMARY_USED = 5; -; Global primary clock #0 -GLOBAL_PRIMARY_0_SIGNALNAME = pll_clks[0]; -GLOBAL_PRIMARY_0_DRIVERTYPE = PLL; -GLOBAL_PRIMARY_0_LOADNUM = 25; -; Global primary clock #1 -GLOBAL_PRIMARY_1_SIGNALNAME = pll_clks[1]; -GLOBAL_PRIMARY_1_DRIVERTYPE = PLL; -GLOBAL_PRIMARY_1_LOADNUM = 24; -; Global primary clock #2 -GLOBAL_PRIMARY_2_SIGNALNAME = pll_clks[3]; -GLOBAL_PRIMARY_2_DRIVERTYPE = PLL; -GLOBAL_PRIMARY_2_LOADNUM = 446; -; Global primary clock #3 -GLOBAL_PRIMARY_3_SIGNALNAME = rd_clk_c; -GLOBAL_PRIMARY_3_DRIVERTYPE = CLK_PIN; -GLOBAL_PRIMARY_3_LOADNUM = 38; -; Global primary clock #4 -GLOBAL_PRIMARY_4_SIGNALNAME = pll_clks[2]; -GLOBAL_PRIMARY_4_DRIVERTYPE = PLL; -GLOBAL_PRIMARY_4_LOADNUM = 24; -; # of global secondary clocks -GLOBAL_SECONDARY_USED = 0; -; I/O Bank 0 Usage -BANK_0_USED = 27; -BANK_0_AVAIL = 27; -BANK_0_VCCIO = 2.5V; -BANK_0_VREF1 = NA; -BANK_0_VREF2 = NA; -; I/O Bank 1 Usage -BANK_1_USED = 29; -BANK_1_AVAIL = 33; -BANK_1_VCCIO = 2.5V; -BANK_1_VREF1 = NA; -BANK_1_VREF2 = NA; -; I/O Bank 2 Usage -BANK_2_USED = 31; -BANK_2_AVAIL = 32; -BANK_2_VCCIO = 2.5V; -BANK_2_VREF1 = NA; -BANK_2_VREF2 = NA; -; I/O Bank 3 Usage -BANK_3_USED = 27; -BANK_3_AVAIL = 33; -BANK_3_VCCIO = 2.5V; -BANK_3_VREF1 = NA; -BANK_3_VREF2 = NA; -; I/O Bank 6 Usage -BANK_6_USED = 28; -BANK_6_AVAIL = 33; -BANK_6_VCCIO = 2.5V; -BANK_6_VREF1 = NA; -BANK_6_VREF2 = NA; -; I/O Bank 7 Usage -BANK_7_USED = 32; -BANK_7_AVAIL = 32; -BANK_7_VCCIO = 2.5V; -BANK_7_VREF1 = NA; -BANK_7_VREF2 = NA; -; I/O Bank 8 Usage -BANK_8_USED = 13; -BANK_8_AVAIL = 13; -BANK_8_VCCIO = 2.5V; -BANK_8_VREF1 = NA; -BANK_8_VREF2 = NA; diff --git a/impl1/s1_impl1.dir/s1_impl1.par b/impl1/s1_impl1.dir/s1_impl1.par deleted file mode 100644 index 2e34b09..0000000 --- a/impl1/s1_impl1.dir/s1_impl1.par +++ /dev/null @@ -1,27 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:19:35 2021 - -/home/soft/lattice/diamond/3.11_x64/ispfpga/bin/lin64/par -f s1_impl1.p2t -s1_impl1_map.ncd s1_impl1.dir s1_impl1.prf -gui -msgset -/home/hadaq/mmichalek/lattice/simplified/promote.xml - - -Preference file: s1_impl1.prf. - -Level/ Number Worst Timing Worst Timing Run NCD -Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ----------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 -2.994 209210 -1.015 9647 48 Completed - -* : Design saved. - -Total (real) run time for 1-seed: 48 secs - -par done! - -Note: user must run 'Trace' for timing closure signoff. diff --git a/impl1/s1_impl1.dly b/impl1/s1_impl1.dly deleted file mode 100644 index cd0d94a..0000000 --- a/impl1/s1_impl1.dly +++ /dev/null @@ -1,8546 +0,0 @@ -PAR: Place And Route Diamond (64-bit) 3.11.2.446. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights reserved. -Wed Jun 16 09:19:35 2021 - -File: s1_impl1.dir/5_1.dly - - The 20 worst nets by delay are: ---------------------------------- -| Max Delay | Netname | ---------------------------------- - 4.3 fifo_rden_c - 3.7 trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - 3.4 reset_dl[2] - 3.3 FEE_DATA_OUT_c[16] - 3.3 hades_dbg2_coarse_c[7] - 3.2 FEE_DATA_OUT_c[18] - 3.2 FEE_DATA_OUT_c[5] - 3.1 FEE_DATA_OUT_c[7] - 3.1 FEE_DATA_OUT_c[6] - 3.0 FEE_DATA_OUT_c[20] - 3.0 hades_dbg2_coarse_c[4] - 2.9 FEE_DATA_OUT_c[17] - 2.9 FEE_DATA_OUT_c[28] - 2.9 FEE_DATA_OUT_c[1] - 2.9 hades_dbg2_coarse_c[5] - 2.9 FEE_DATA_OUT_c[4] - 2.9 FEE_DATA_OUT_c[2] - 2.8 FEE_DATA_OUT_c[13] - 2.8 FEE_DATA_OUT_c[22] - 2.8 FEE_DATA_OUT_c[25] ---------------------------------- - -------------------------------------------------------------------------------- - Net Delays -------------------------------------------------------------------------------- - -ANB0 - hades_tdc_bundle_inst/hit_out_i_RNO[0].Q0 - 0.2 hades_tdc_bundle_inst/hit_out_i_RNO[0].D0 - 0.5 hades_tdc_bundle_inst/hit_out_i_RNO[0].B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.C1 - 0.9 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].M0 - 0.3 hades_tdc_bundle_inst/buf_finished5_0_a2_0.D0 - 1.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.C0 - 0.3 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D0 - 1.5 hades_hit_out_i_pad[0].PADDO - -ANB1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q0 - 0.6 hades_tdc_bundle_inst/hit_out_i_RNO[0].D1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.D1 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].C0 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A1 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.C0 - 0.3 hades_tdc_bundle_inst/buf_finished5_0_a2_0.D1 - 1.3 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.A0 - 0.5 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C1 - 0.5 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.C1 - 1.3 hades_hit_out_i_pad[1].PADDO - -ANB2 - hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].Q0 - 0.9 hades_tdc_bundle_inst/hit_out_i_RNO[0].C1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.B1 - 0.6 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B0 - 0.6 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].B1 - 1.2 hades_tdc_bundle_inst/buf_finished5_0_a2_0.A0 - 0.9 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.B0 - 1.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B0 - 1.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.B1 - 1.5 hades_hit_out_i_pad[2].PADDO - -ANB3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.Q1 - 0.7 hades_tdc_bundle_inst/hit_out_i_RNO[0].A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.A1 - 1.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].A0 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.B0 - 0.6 hades_tdc_bundle_inst/buf_finished5_0_a2_0.B1 - 0.8 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.D0 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A1 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A1 - 1.7 hades_hit_out_i_pad[3].PADDO - -FEE_DATAFINISHED_OUT_c - trb_adapter_inst_FEE_DATAFINISHED_OUTio.IOLDO - 0.0 FEE_DATAFINISHED_OUT_pad.IOLDO - -FEE_DATA_OUT_c[0] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA0 - 2.5 fifo_data_out_pad[0].PADDO - 2.8 FEE_DATA_OUT_pad[0].PADDO - -FEE_DATA_OUT_c[10] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA10 - 2.1 FEE_DATA_OUT_pad[10].PADDO - 2.1 fifo_data_out_pad[10].PADDO - -FEE_DATA_OUT_c[11] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA11 - 2.5 FEE_DATA_OUT_pad[11].PADDO - 2.5 fifo_data_out_pad[11].PADDO - -FEE_DATA_OUT_c[12] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA12 - 2.4 FEE_DATA_OUT_pad[12].PADDO - 2.6 fifo_data_out_pad[12].PADDO - -FEE_DATA_OUT_c[13] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA13 - 2.8 FEE_DATA_OUT_pad[13].PADDO - 2.8 fifo_data_out_pad[13].PADDO - -FEE_DATA_OUT_c[14] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA14 - 2.6 FEE_DATA_OUT_pad[14].PADDO - 2.8 fifo_data_out_pad[14].PADDO - -FEE_DATA_OUT_c[15] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA15 - 2.5 FEE_DATA_OUT_pad[15].PADDO - 2.1 fifo_data_out_pad[15].PADDO - -FEE_DATA_OUT_c[16] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA16 - 3.2 FEE_DATA_OUT_pad[16].PADDO - 3.3 fifo_data_out_pad[16].PADDO - -FEE_DATA_OUT_c[17] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA17 - 2.8 FEE_DATA_OUT_pad[17].PADDO - 2.9 fifo_data_out_pad[17].PADDO - -FEE_DATA_OUT_c[18] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB0 - 2.8 FEE_DATA_OUT_pad[18].PADDO - 3.2 fifo_data_out_pad[18].PADDO - -FEE_DATA_OUT_c[19] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB1 - 2.2 FEE_DATA_OUT_pad[19].PADDO - 2.2 fifo_data_out_pad[19].PADDO - -FEE_DATA_OUT_c[1] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA1 - 2.9 FEE_DATA_OUT_pad[1].PADDO - 2.9 fifo_data_out_pad[1].PADDO - -FEE_DATA_OUT_c[20] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB2 - 2.8 FEE_DATA_OUT_pad[20].PADDO - 3.0 fifo_data_out_pad[20].PADDO - -FEE_DATA_OUT_c[21] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB3 - 2.4 FEE_DATA_OUT_pad[21].PADDO - 2.3 fifo_data_out_pad[21].PADDO - -FEE_DATA_OUT_c[22] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB4 - 2.7 FEE_DATA_OUT_pad[22].PADDO - 2.8 fifo_data_out_pad[22].PADDO - -FEE_DATA_OUT_c[23] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB5 - 2.4 FEE_DATA_OUT_pad[23].PADDO - 2.4 fifo_data_out_pad[23].PADDO - -FEE_DATA_OUT_c[24] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB6 - 2.4 FEE_DATA_OUT_pad[24].PADDO - 2.7 fifo_data_out_pad[24].PADDO - -FEE_DATA_OUT_c[25] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB7 - 2.8 FEE_DATA_OUT_pad[25].PADDO - 2.8 fifo_data_out_pad[25].PADDO - -FEE_DATA_OUT_c[26] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB8 - 2.7 FEE_DATA_OUT_pad[26].PADDO - 2.8 fifo_data_out_pad[26].PADDO - -FEE_DATA_OUT_c[27] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB9 - 2.8 FEE_DATA_OUT_pad[27].PADDO - 2.8 fifo_data_out_pad[27].PADDO - -FEE_DATA_OUT_c[28] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB10 - 2.8 FEE_DATA_OUT_pad[28].PADDO - 2.9 fifo_data_out_pad[28].PADDO - -FEE_DATA_OUT_c[29] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB11 - 2.7 FEE_DATA_OUT_pad[29].PADDO - 2.7 fifo_data_out_pad[29].PADDO - -FEE_DATA_OUT_c[2] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA2 - 2.9 FEE_DATA_OUT_pad[2].PADDO - 2.9 fifo_data_out_pad[2].PADDO - -FEE_DATA_OUT_c[30] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB12 - 2.6 FEE_DATA_OUT_pad[30].PADDO - 2.6 fifo_data_out_pad[30].PADDO - -FEE_DATA_OUT_c[31] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOB13 - 2.6 FEE_DATA_OUT_pad[31].PADDO - 2.8 fifo_data_out_pad[31].PADDO - -FEE_DATA_OUT_c[3] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA3 - 2.5 FEE_DATA_OUT_pad[3].PADDO - 2.5 fifo_data_out_pad[3].PADDO - -FEE_DATA_OUT_c[4] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA4 - 2.9 FEE_DATA_OUT_pad[4].PADDO - 2.9 fifo_data_out_pad[4].PADDO - -FEE_DATA_OUT_c[5] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA5 - 3.0 FEE_DATA_OUT_pad[5].PADDO - 3.2 fifo_data_out_pad[5].PADDO - -FEE_DATA_OUT_c[6] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA6 - 2.9 FEE_DATA_OUT_pad[6].PADDO - 3.1 fifo_data_out_pad[6].PADDO - -FEE_DATA_OUT_c[7] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA7 - 2.9 FEE_DATA_OUT_pad[7].PADDO - 3.1 fifo_data_out_pad[7].PADDO - -FEE_DATA_OUT_c[8] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA8 - 2.5 FEE_DATA_OUT_pad[8].PADDO - 2.5 fifo_data_out_pad[8].PADDO - -FEE_DATA_OUT_c[9] - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DOA9 - 2.4 FEE_DATA_OUT_pad[9].PADDO - 2.6 fifo_data_out_pad[9].PADDO - -FEE_DATA_WRITE_OUT_c - trb_adapter_inst_FEE_DATA_WRITE_OUTio.IOLDO - 0.0 FEE_DATA_WRITE_OUT_pad.IOLDO - -FEE_TRG_RELEASE_OUT_c - trb_adapter_inst_FEE_TRG_RELEASE_OUTio.IOLDO - 0.0 FEE_TRG_RELEASE_OUT_pad.IOLDO - -LVL1_INVALID_TRG_IN_c - LVL1_INVALID_TRG_IN_pad.PADDI - 0.0 trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].DI - -LVL1_TRG_DATA_VALID_IN_c - LVL1_TRG_DATA_VALID_IN_pad.PADDI - 0.0 trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].DI - -LVL1_TRG_DATA_VALI_IN_rising_c - trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.F0 - 0.6 LVL1_TRG_DATA_VALI_IN_rising_pad.PADDO - -N_248_i - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.OFX0 - 0.4 hades_tdc_bundle_inst_buf_out_validio.CE - -burst_c - trb_adapter_inst/burst.F1 - 0.4 trb_adapter_inst/burst.B0 - 0.4 burst_pad.PADDO - -clk_c - clk_pad.PADDI - 0.1 pll0inst/PLLInst_0.CLKI - -discard_c - trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].Q0 - 0.8 trb_adapter_inst/burst.C1 - 0.4 discard_pad.PADDO - -fifo_colector_inst/buffer_wr_enable - fifo_colector_inst/in_empty_pmux_0_RNIDRET.Q0 - 0.9 fifo_colector_inst/fifo40_inst/AND2_t20.B0 - -fifo_colector_inst/data_buffer[0] - fifo_colector_inst/data_buffer_3[0].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA0 - -fifo_colector_inst/data_buffer[10] - fifo_colector_inst/data_buffer_3_0[11].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA10 - -fifo_colector_inst/data_buffer[11] - fifo_colector_inst/data_buffer_3_0[11].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA11 - -fifo_colector_inst/data_buffer[12] - fifo_colector_inst/data_buffer_3_0[13].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA12 - -fifo_colector_inst/data_buffer[13] - fifo_colector_inst/data_buffer_3_0[13].Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA13 - -fifo_colector_inst/data_buffer[14] - fifo_colector_inst/data_buffer_3_0[15].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA14 - -fifo_colector_inst/data_buffer[15] - fifo_colector_inst/data_buffer_3_0[15].Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA15 - -fifo_colector_inst/data_buffer[16] - fifo_colector_inst/data_buffer_3_0[17].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA16 - -fifo_colector_inst/data_buffer[17] - fifo_colector_inst/data_buffer_3_0[17].Q1 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA17 - -fifo_colector_inst/data_buffer[18] - fifo_colector_inst/data_buffer_3_0[19].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB0 - -fifo_colector_inst/data_buffer[19] - fifo_colector_inst/data_buffer_3_0[19].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB1 - -fifo_colector_inst/data_buffer[1] - fifo_colector_inst/data_buffer_3[1].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA1 - -fifo_colector_inst/data_buffer[20] - fifo_colector_inst/data_buffer_3_0[21].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB2 - -fifo_colector_inst/data_buffer[21] - fifo_colector_inst/data_buffer_3_0[21].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB3 - -fifo_colector_inst/data_buffer[22] - fifo_colector_inst/data_buffer_3_0[23].Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB4 - -fifo_colector_inst/data_buffer[23] - fifo_colector_inst/data_buffer_3_0[23].Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB5 - -fifo_colector_inst/data_buffer[24] - fifo_colector_inst/data_buffer_3_0[25].Q0 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB6 - -fifo_colector_inst/data_buffer[25] - fifo_colector_inst/data_buffer_3_0[25].Q1 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB7 - -fifo_colector_inst/data_buffer[26] - fifo_colector_inst/data_buffer_3_0[27].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB8 - -fifo_colector_inst/data_buffer[27] - fifo_colector_inst/data_buffer_3_0[27].Q1 - 1.0 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB9 - -fifo_colector_inst/data_buffer[28] - fifo_colector_inst/data_buffer_3_0[29].Q0 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB10 - -fifo_colector_inst/data_buffer[29] - fifo_colector_inst/data_buffer_3_0[29].Q1 - 0.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB11 - -fifo_colector_inst/data_buffer[2] - fifo_colector_inst/data_buffer_3[2].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA2 - -fifo_colector_inst/data_buffer[30] - fifo_colector_inst/data_buffer_3_0[31].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB12 - -fifo_colector_inst/data_buffer[31] - fifo_colector_inst/data_buffer_3_0[31].Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB13 - -fifo_colector_inst/data_buffer[32] - fifo_colector_inst/data_buffer[33].Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB14 - -fifo_colector_inst/data_buffer[33] - fifo_colector_inst/data_buffer[33].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIB15 - -fifo_colector_inst/data_buffer[3] - fifo_colector_inst/data_buffer_3[3].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA3 - -fifo_colector_inst/data_buffer[4] - fifo_colector_inst/data_buffer_3[4].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA4 - -fifo_colector_inst/data_buffer[5] - fifo_colector_inst/data_buffer_3[5].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA5 - -fifo_colector_inst/data_buffer[6] - fifo_colector_inst/data_buffer_3[6].Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA6 - -fifo_colector_inst/data_buffer[7] - fifo_colector_inst/data_buffer_3[7].Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA7 - -fifo_colector_inst/data_buffer[8] - fifo_colector_inst/data_buffer_3_0[9].Q0 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA8 - -fifo_colector_inst/data_buffer[9] - fifo_colector_inst/data_buffer_3_0[9].Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.DIA9 - -fifo_colector_inst/data_buffer_3[0] - fifo_colector_inst/data_buffer_3[0].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[0].DI0 - -fifo_colector_inst/data_buffer_3[10] - fifo_colector_inst/data_buffer_3_0[11].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[11].DI0 - -fifo_colector_inst/data_buffer_3[11] - fifo_colector_inst/data_buffer_3_0[11].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[11].DI1 - -fifo_colector_inst/data_buffer_3[12] - fifo_colector_inst/data_buffer_3_0[13].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[13].DI0 - -fifo_colector_inst/data_buffer_3[13] - fifo_colector_inst/data_buffer_3_0[13].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[13].DI1 - -fifo_colector_inst/data_buffer_3[14] - fifo_colector_inst/data_buffer_3_0[15].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[15].DI0 - -fifo_colector_inst/data_buffer_3[15] - fifo_colector_inst/data_buffer_3_0[15].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[15].DI1 - -fifo_colector_inst/data_buffer_3[16] - fifo_colector_inst/data_buffer_3_0[17].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[17].DI0 - -fifo_colector_inst/data_buffer_3[17] - fifo_colector_inst/data_buffer_3_0[17].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[17].DI1 - -fifo_colector_inst/data_buffer_3[18] - fifo_colector_inst/data_buffer_3_0[19].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[19].DI0 - -fifo_colector_inst/data_buffer_3[19] - fifo_colector_inst/data_buffer_3_0[19].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[19].DI1 - -fifo_colector_inst/data_buffer_3[1] - fifo_colector_inst/data_buffer_3[1].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[1].DI0 - -fifo_colector_inst/data_buffer_3[20] - fifo_colector_inst/data_buffer_3_0[21].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[21].DI0 - -fifo_colector_inst/data_buffer_3[21] - fifo_colector_inst/data_buffer_3_0[21].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[21].DI1 - -fifo_colector_inst/data_buffer_3[22] - fifo_colector_inst/data_buffer_3_0[23].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[23].DI0 - -fifo_colector_inst/data_buffer_3[23] - fifo_colector_inst/data_buffer_3_0[23].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[23].DI1 - -fifo_colector_inst/data_buffer_3[24] - fifo_colector_inst/data_buffer_3_0[25].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[25].DI0 - -fifo_colector_inst/data_buffer_3[25] - fifo_colector_inst/data_buffer_3_0[25].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[25].DI1 - -fifo_colector_inst/data_buffer_3[26] - fifo_colector_inst/data_buffer_3_0[27].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[27].DI0 - -fifo_colector_inst/data_buffer_3[27] - fifo_colector_inst/data_buffer_3_0[27].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[27].DI1 - -fifo_colector_inst/data_buffer_3[28] - fifo_colector_inst/data_buffer_3_0[29].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[29].DI0 - -fifo_colector_inst/data_buffer_3[29] - fifo_colector_inst/data_buffer_3_0[29].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[29].DI1 - -fifo_colector_inst/data_buffer_3[2] - fifo_colector_inst/data_buffer_3[2].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[2].DI0 - -fifo_colector_inst/data_buffer_3[30] - fifo_colector_inst/data_buffer_3_0[31].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[31].DI0 - -fifo_colector_inst/data_buffer_3[31] - fifo_colector_inst/data_buffer_3_0[31].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[31].DI1 - -fifo_colector_inst/data_buffer_3[3] - fifo_colector_inst/data_buffer_3[3].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[3].DI0 - -fifo_colector_inst/data_buffer_3[4] - fifo_colector_inst/data_buffer_3[4].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[4].DI0 - -fifo_colector_inst/data_buffer_3[5] - fifo_colector_inst/data_buffer_3[5].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[5].DI0 - -fifo_colector_inst/data_buffer_3[6] - fifo_colector_inst/data_buffer_3[6].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[6].DI0 - -fifo_colector_inst/data_buffer_3[7] - fifo_colector_inst/data_buffer_3[7].OFX0 - 0.0 fifo_colector_inst/data_buffer_3[7].DI0 - -fifo_colector_inst/data_buffer_3[8] - fifo_colector_inst/data_buffer_3_0[9].F0 - 0.0 fifo_colector_inst/data_buffer_3_0[9].DI0 - -fifo_colector_inst/data_buffer_3[9] - fifo_colector_inst/data_buffer_3_0[9].F1 - 0.0 fifo_colector_inst/data_buffer_3_0[9].DI1 - -fifo_colector_inst/fb_0 - fifo_colector_inst/in_read_enable_1_.fb.F0 - 0.0 fifo_colector_inst/in_read_enable_1_.fb.DI0 - -fifo_colector_inst/fb_0_0 - fifo_colector_inst/in_read_enable_2_.fb.F0 - 0.0 fifo_colector_inst/in_read_enable_2_.fb.DI0 - -fifo_colector_inst/fb_0_1 - fifo_colector_inst/in_read_enable_1_.fb.F1 - 0.0 fifo_colector_inst/in_read_enable_1_.fb.DI1 - -fifo_colector_inst/fifo40_inst/Full - fifo_colector_inst/fifo40_inst/FF_0.Q0 - 0.4 fifo_colector_inst/fifo40_inst/AND2_t20.C0 - -fifo_colector_inst/fifo40_inst/cmp_ci - fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_0.FCI - -fifo_colector_inst/fifo40_inst/cmp_ci_1 - fifo_colector_inst/fifo40_inst/full_cmp_ci_a.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_0.FCI - -fifo_colector_inst/fifo40_inst/co0 - fifo_colector_inst/fifo40_inst/FF_100.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_98.FCI - -fifo_colector_inst/fifo40_inst/co0_1 - fifo_colector_inst/fifo40_inst/FF_70.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_68.FCI - -fifo_colector_inst/fifo40_inst/co0_2 - fifo_colector_inst/fifo40_inst/empty_cmp_0.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_1.FCI - -fifo_colector_inst/fifo40_inst/co0_3 - fifo_colector_inst/fifo40_inst/full_cmp_0.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_1.FCI - -fifo_colector_inst/fifo40_inst/co1 - fifo_colector_inst/fifo40_inst/FF_98.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_96.FCI - -fifo_colector_inst/fifo40_inst/co1_1 - fifo_colector_inst/fifo40_inst/FF_68.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_66.FCI - -fifo_colector_inst/fifo40_inst/co1_2 - fifo_colector_inst/fifo40_inst/empty_cmp_1.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_2.FCI - -fifo_colector_inst/fifo40_inst/co1_3 - fifo_colector_inst/fifo40_inst/full_cmp_1.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_2.FCI - -fifo_colector_inst/fifo40_inst/co2 - fifo_colector_inst/fifo40_inst/FF_96.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_94.FCI - -fifo_colector_inst/fifo40_inst/co2_1 - fifo_colector_inst/fifo40_inst/FF_66.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_64.FCI - -fifo_colector_inst/fifo40_inst/co2_2 - fifo_colector_inst/fifo40_inst/empty_cmp_2.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_3.FCI - -fifo_colector_inst/fifo40_inst/co2_3 - fifo_colector_inst/fifo40_inst/full_cmp_2.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_3.FCI - -fifo_colector_inst/fifo40_inst/co3 - fifo_colector_inst/fifo40_inst/FF_94.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_92.FCI - -fifo_colector_inst/fifo40_inst/co3_1 - fifo_colector_inst/fifo40_inst/FF_64.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_62.FCI - -fifo_colector_inst/fifo40_inst/co3_2 - fifo_colector_inst/fifo40_inst/empty_cmp_3.FCO - 0.0 fifo_colector_inst/fifo40_inst/empty_cmp_4.FCI - -fifo_colector_inst/fifo40_inst/co3_3 - fifo_colector_inst/fifo40_inst/full_cmp_3.FCO - 0.0 fifo_colector_inst/fifo40_inst/full_cmp_4.FCI - -fifo_colector_inst/fifo40_inst/empty_cmp_clr - fifo_colector_inst/fifo40_inst/LUT4_2.F1 - 0.4 fifo_colector_inst/fifo40_inst/empty_cmp_4.A1 - -fifo_colector_inst/fifo40_inst/empty_cmp_set - fifo_colector_inst/fifo40_inst/LUT4_2.F0 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_4.B1 - -fifo_colector_inst/fifo40_inst/empty_d - fifo_colector_inst/fifo40_inst/FF_1.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_1.DI0 - -fifo_colector_inst/fifo40_inst/empty_d_c - fifo_colector_inst/fifo40_inst/empty_cmp_4.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_1.FCI - -fifo_colector_inst/fifo40_inst/full_cmp_clr - fifo_colector_inst/fifo40_inst/LUT4_1.F0 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_4.B1 - -fifo_colector_inst/fifo40_inst/full_cmp_set - fifo_colector_inst/fifo40_inst/LUT4_1.F1 - 0.4 fifo_colector_inst/fifo40_inst/full_cmp_4.A1 - -fifo_colector_inst/fifo40_inst/full_d - fifo_colector_inst/fifo40_inst/FF_0.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_0.DI0 - -fifo_colector_inst/fifo40_inst/full_d_c - fifo_colector_inst/fifo40_inst/full_cmp_4.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_0.FCI - -fifo_colector_inst/fifo40_inst/ircount_0 - fifo_colector_inst/fifo40_inst/FF_70.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_70.DI0 - -fifo_colector_inst/fifo40_inst/ircount_1 - fifo_colector_inst/fifo40_inst/FF_70.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_70.DI1 - -fifo_colector_inst/fifo40_inst/ircount_2 - fifo_colector_inst/fifo40_inst/FF_68.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_68.DI0 - -fifo_colector_inst/fifo40_inst/ircount_3 - fifo_colector_inst/fifo40_inst/FF_68.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_68.DI1 - -fifo_colector_inst/fifo40_inst/ircount_4 - fifo_colector_inst/fifo40_inst/FF_66.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_66.DI0 - -fifo_colector_inst/fifo40_inst/ircount_5 - fifo_colector_inst/fifo40_inst/FF_66.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_66.DI1 - -fifo_colector_inst/fifo40_inst/ircount_6 - fifo_colector_inst/fifo40_inst/FF_64.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_64.DI0 - -fifo_colector_inst/fifo40_inst/ircount_7 - fifo_colector_inst/fifo40_inst/FF_64.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_64.DI1 - -fifo_colector_inst/fifo40_inst/ircount_8 - fifo_colector_inst/fifo40_inst/FF_62.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_62.DI0 - -fifo_colector_inst/fifo40_inst/ircount_9 - fifo_colector_inst/fifo40_inst/FF_62.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_62.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_0 - fifo_colector_inst/fifo40_inst/FF_100.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_100.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_1 - fifo_colector_inst/fifo40_inst/FF_100.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_100.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_2 - fifo_colector_inst/fifo40_inst/FF_98.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_98.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_3 - fifo_colector_inst/fifo40_inst/FF_98.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_98.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_4 - fifo_colector_inst/fifo40_inst/FF_96.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_96.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_5 - fifo_colector_inst/fifo40_inst/FF_96.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_96.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_6 - fifo_colector_inst/fifo40_inst/FF_94.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_94.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_7 - fifo_colector_inst/fifo40_inst/FF_94.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_94.DI1 - -fifo_colector_inst/fifo40_inst/iwcount_8 - fifo_colector_inst/fifo40_inst/FF_92.F0 - 0.0 fifo_colector_inst/fifo40_inst/FF_92.DI0 - -fifo_colector_inst/fifo40_inst/iwcount_9 - fifo_colector_inst/fifo40_inst/FF_92.F1 - 0.0 fifo_colector_inst/fifo40_inst/FF_92.DI1 - -fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - fifo_colector_inst/fifo40_inst/LUT4_4.F0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_4.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_5.D1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.B0 - -fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - fifo_colector_inst/fifo40_inst/LUT4_5.F0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.M0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_4.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_5.C1 - -fifo_colector_inst/fifo40_inst/r_gcount_0 - fifo_colector_inst/fifo40_inst/XOR2_t7.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_30.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_1 - fifo_colector_inst/fifo40_inst/XOR2_t7.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_30.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_2 - fifo_colector_inst/fifo40_inst/XOR2_t5.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_28.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_3 - fifo_colector_inst/fifo40_inst/XOR2_t5.Q1 - 0.5 fifo_colector_inst/fifo40_inst/FF_28.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_4 - fifo_colector_inst/fifo40_inst/XOR2_t3.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_26.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_5 - fifo_colector_inst/fifo40_inst/XOR2_t3.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_26.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_6 - fifo_colector_inst/fifo40_inst/XOR2_t1.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_24.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_7 - fifo_colector_inst/fifo40_inst/XOR2_t1.Q1 - 0.5 fifo_colector_inst/fifo40_inst/FF_24.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_8 - fifo_colector_inst/fifo40_inst/XOR2_t0.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_22.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_9 - fifo_colector_inst/fifo40_inst/XOR2_t0.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_22.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w0 - fifo_colector_inst/fifo40_inst/FF_30.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_10.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w1 - fifo_colector_inst/fifo40_inst/FF_30.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_10.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w2 - fifo_colector_inst/fifo40_inst/FF_28.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_8.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w20 - fifo_colector_inst/fifo40_inst/FF_10.Q0 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_4.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w21 - fifo_colector_inst/fifo40_inst/FF_10.Q1 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_4.A1 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_5.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w22 - fifo_colector_inst/fifo40_inst/FF_8.Q0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_5.B0 - -fifo_colector_inst/fifo40_inst/r_gcount_w23 - fifo_colector_inst/fifo40_inst/FF_8.Q1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_5.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_11.D0 - -fifo_colector_inst/fifo40_inst/r_gcount_w24 - fifo_colector_inst/fifo40_inst/FF_6.Q0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_5.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_8.C1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_11.C0 - -fifo_colector_inst/fifo40_inst/r_gcount_w25 - fifo_colector_inst/fifo40_inst/FF_6.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.M0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_5.A0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_8.A1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.A0 - -fifo_colector_inst/fifo40_inst/r_gcount_w26 - fifo_colector_inst/fifo40_inst/FF_4.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_6.D1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_9.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_9.D1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_4.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_8.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w27 - fifo_colector_inst/fifo40_inst/FF_4.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.C1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.C0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_9.A1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_4.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_8.C0 - -fifo_colector_inst/fifo40_inst/r_gcount_w28 - fifo_colector_inst/fifo40_inst/FF_2.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_6.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_6.A1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_9.A0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_4.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_8.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_11.D1 - -fifo_colector_inst/fifo40_inst/r_gcount_w29 - fifo_colector_inst/fifo40_inst/FF_2.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_6.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_9.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_4.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_8.B0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_1.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_1.A1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_11.B1 - -fifo_colector_inst/fifo40_inst/r_gcount_w3 - fifo_colector_inst/fifo40_inst/FF_28.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_8.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w4 - fifo_colector_inst/fifo40_inst/FF_26.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_6.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w5 - fifo_colector_inst/fifo40_inst/FF_26.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_6.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w6 - fifo_colector_inst/fifo40_inst/FF_24.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_4.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w7 - fifo_colector_inst/fifo40_inst/FF_24.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_4.M1 - -fifo_colector_inst/fifo40_inst/r_gcount_w8 - fifo_colector_inst/fifo40_inst/FF_22.Q0 - 0.8 fifo_colector_inst/fifo40_inst/FF_2.M0 - -fifo_colector_inst/fifo40_inst/r_gcount_w9 - fifo_colector_inst/fifo40_inst/FF_22.Q1 - 0.8 fifo_colector_inst/fifo40_inst/FF_2.M1 - -fifo_colector_inst/fifo40_inst/r_gctr_ci - fifo_colector_inst/fifo40_inst/r_gctr_cia.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_70.FCI - -fifo_colector_inst/fifo40_inst/r_gdata_0 - fifo_colector_inst/fifo40_inst/XOR2_t7.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t7.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_1 - fifo_colector_inst/fifo40_inst/XOR2_t7.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t7.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_2 - fifo_colector_inst/fifo40_inst/XOR2_t5.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t5.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_3 - fifo_colector_inst/fifo40_inst/XOR2_t5.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t5.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_4 - fifo_colector_inst/fifo40_inst/XOR2_t3.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t3.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_5 - fifo_colector_inst/fifo40_inst/XOR2_t3.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t3.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_6 - fifo_colector_inst/fifo40_inst/XOR2_t1.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t1.DI0 - -fifo_colector_inst/fifo40_inst/r_gdata_7 - fifo_colector_inst/fifo40_inst/XOR2_t1.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t1.DI1 - -fifo_colector_inst/fifo40_inst/r_gdata_8 - fifo_colector_inst/fifo40_inst/XOR2_t0.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t0.DI0 - -fifo_colector_inst/fifo40_inst/rcount_0 - fifo_colector_inst/fifo40_inst/FF_70.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_70.A0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_0.B0 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.D0 - 1.5 fifo_colector_inst/fifo40_inst/FF_50.M0 - -fifo_colector_inst/fifo40_inst/rcount_1 - fifo_colector_inst/fifo40_inst/FF_70.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_70.B1 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_0.B1 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.C0 - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t7.C1 - 1.3 fifo_colector_inst/fifo40_inst/FF_50.M1 - -fifo_colector_inst/fifo40_inst/rcount_2 - fifo_colector_inst/fifo40_inst/FF_68.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_68.B0 - 1.1 fifo_colector_inst/fifo40_inst/empty_cmp_1.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t7.A1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t5.B0 - 0.8 fifo_colector_inst/fifo40_inst/FF_48.M0 - -fifo_colector_inst/fifo40_inst/rcount_3 - fifo_colector_inst/fifo40_inst/FF_68.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_68.A1 - 1.0 fifo_colector_inst/fifo40_inst/empty_cmp_1.B1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t5.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t5.A1 - 1.4 fifo_colector_inst/fifo40_inst/FF_48.M1 - -fifo_colector_inst/fifo40_inst/rcount_4 - fifo_colector_inst/fifo40_inst/FF_66.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_66.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_2.A0 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t5.D1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t3.D0 - 0.5 fifo_colector_inst/fifo40_inst/FF_46.M0 - -fifo_colector_inst/fifo40_inst/rcount_5 - fifo_colector_inst/fifo40_inst/FF_66.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_66.A1 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_2.A1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t3.A0 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t3.A1 - 0.8 fifo_colector_inst/fifo40_inst/FF_46.M1 - -fifo_colector_inst/fifo40_inst/rcount_6 - fifo_colector_inst/fifo40_inst/FF_64.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_64.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_3.B0 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t3.C1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t1.C0 - 0.6 fifo_colector_inst/fifo40_inst/FF_44.M0 - -fifo_colector_inst/fifo40_inst/rcount_7 - fifo_colector_inst/fifo40_inst/FF_64.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_64.B1 - 1.1 fifo_colector_inst/fifo40_inst/empty_cmp_3.B1 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t1.D0 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t1.D1 - 0.5 fifo_colector_inst/fifo40_inst/FF_44.M1 - -fifo_colector_inst/fifo40_inst/rcount_8 - fifo_colector_inst/fifo40_inst/FF_62.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_62.B0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_4.B0 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t1.C1 - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t0.B0 - 0.9 fifo_colector_inst/fifo40_inst/FF_42.M0 - -fifo_colector_inst/fifo40_inst/rcount_9 - fifo_colector_inst/fifo40_inst/FF_62.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_62.B1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t0.D0 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t0.M1 - 0.7 fifo_colector_inst/fifo40_inst/FF_42.M1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_2.D0 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_2.D1 - -fifo_colector_inst/fifo40_inst/rcount_w0 - fifo_colector_inst/fifo40_inst/LUT4_4.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_0.B0 - -fifo_colector_inst/fifo40_inst/rcount_w1 - fifo_colector_inst/fifo40_inst/LUT4_5.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_0.A1 - -fifo_colector_inst/fifo40_inst/rcount_w2 - fifo_colector_inst/fifo40_inst/LUT4_6.OFX0 - 0.6 fifo_colector_inst/fifo40_inst/full_cmp_1.B0 - -fifo_colector_inst/fifo40_inst/rcount_w3 - fifo_colector_inst/fifo40_inst/LUT4_11.F0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_1.A1 - -fifo_colector_inst/fifo40_inst/rcount_w4 - fifo_colector_inst/fifo40_inst/LUT4_8.F1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_2.A0 - -fifo_colector_inst/fifo40_inst/rcount_w5 - fifo_colector_inst/fifo40_inst/LUT4_9.OFX0 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_2.B1 - -fifo_colector_inst/fifo40_inst/rcount_w7 - fifo_colector_inst/fifo40_inst/LUT4_8.F0 - 0.8 fifo_colector_inst/fifo40_inst/full_cmp_3.B1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_8.D1 - -fifo_colector_inst/fifo40_inst/rcount_w8 - fifo_colector_inst/fifo40_inst/LUT4_11.F1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_4.A0 - -fifo_colector_inst/fifo40_inst/rden_i - fifo_colector_inst/fifo40_inst/AND2_t19.F0 - 0.5 fifo_colector_inst/fifo40_inst/FF_70.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_68.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_66.CE - 0.4 fifo_colector_inst/fifo40_inst/FF_64.CE - 0.4 fifo_colector_inst/fifo40_inst/FF_62.CE - 1.4 fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.A1 - 1.4 fifo_colector_inst/fifo40_inst/empty_cmp_ci_a.B1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t7.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t5.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t3.CE - 1.3 fifo_colector_inst/fifo40_inst/XOR2_t1.CE - 1.0 fifo_colector_inst/fifo40_inst/XOR2_t0.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_50.CE - 1.3 fifo_colector_inst/fifo40_inst/FF_48.CE - 1.1 fifo_colector_inst/fifo40_inst/FF_46.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_44.CE - 1.0 fifo_colector_inst/fifo40_inst/FF_42.CE - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CEB - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.OCEB - -fifo_colector_inst/fifo40_inst/rptr_0 - fifo_colector_inst/fifo40_inst/FF_50.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB5 - -fifo_colector_inst/fifo40_inst/rptr_1 - fifo_colector_inst/fifo40_inst/FF_50.Q1 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB6 - -fifo_colector_inst/fifo40_inst/rptr_2 - fifo_colector_inst/fifo40_inst/FF_48.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB7 - -fifo_colector_inst/fifo40_inst/rptr_3 - fifo_colector_inst/fifo40_inst/FF_48.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB8 - -fifo_colector_inst/fifo40_inst/rptr_4 - fifo_colector_inst/fifo40_inst/FF_46.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB9 - -fifo_colector_inst/fifo40_inst/rptr_5 - fifo_colector_inst/fifo40_inst/FF_46.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB10 - -fifo_colector_inst/fifo40_inst/rptr_6 - fifo_colector_inst/fifo40_inst/FF_44.Q0 - 0.9 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB11 - -fifo_colector_inst/fifo40_inst/rptr_7 - fifo_colector_inst/fifo40_inst/FF_44.Q1 - 0.6 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB12 - -fifo_colector_inst/fifo40_inst/rptr_8 - fifo_colector_inst/fifo40_inst/FF_42.Q0 - 1.1 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADB13 - -fifo_colector_inst/fifo40_inst/rptr_9 - fifo_colector_inst/fifo40_inst/FF_42.Q1 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_2.C0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_2.C1 - -fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - fifo_colector_inst/fifo40_inst/LUT4_14.F0 - 0.7 fifo_colector_inst/fifo40_inst/empty_cmp_3.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_14.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_15.D1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_17.D0 - 0.4 fifo_colector_inst/fifo40_inst/LUT4_17.C1 - -fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - fifo_colector_inst/fifo40_inst/LUT4_15.F0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_14.B1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_15.C1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_17.C0 - -fifo_colector_inst/fifo40_inst/w_gcount_0 - fifo_colector_inst/fifo40_inst/XOR2_t16.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_40.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_1 - fifo_colector_inst/fifo40_inst/XOR2_t16.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_40.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_2 - fifo_colector_inst/fifo40_inst/XOR2_t14.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_38.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_3 - fifo_colector_inst/fifo40_inst/XOR2_t14.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_38.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_4 - fifo_colector_inst/fifo40_inst/XOR2_t12.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_36.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_5 - fifo_colector_inst/fifo40_inst/XOR2_t12.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_36.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_6 - fifo_colector_inst/fifo40_inst/XOR2_t10.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_34.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_7 - fifo_colector_inst/fifo40_inst/XOR2_t10.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_34.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_8 - fifo_colector_inst/fifo40_inst/XOR2_t9.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_32.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_9 - fifo_colector_inst/fifo40_inst/XOR2_t9.Q1 - 0.3 fifo_colector_inst/fifo40_inst/FF_32.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r0 - fifo_colector_inst/fifo40_inst/FF_40.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_20.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r1 - fifo_colector_inst/fifo40_inst/FF_40.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_20.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r2 - fifo_colector_inst/fifo40_inst/FF_38.Q0 - 0.3 fifo_colector_inst/fifo40_inst/FF_18.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r20 - fifo_colector_inst/fifo40_inst/FF_20.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_14.C1 - -fifo_colector_inst/fifo40_inst/w_gcount_r21 - fifo_colector_inst/fifo40_inst/FF_20.Q1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_14.A1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_15.B1 - -fifo_colector_inst/fifo40_inst/w_gcount_r22 - fifo_colector_inst/fifo40_inst/FF_18.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_15.D0 - -fifo_colector_inst/fifo40_inst/w_gcount_r23 - fifo_colector_inst/fifo40_inst/FF_18.Q1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_15.B0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_17.B1 - -fifo_colector_inst/fifo40_inst/w_gcount_r24 - fifo_colector_inst/fifo40_inst/FF_16.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_15.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_18.B1 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_17.D1 - -fifo_colector_inst/fifo40_inst/w_gcount_r25 - fifo_colector_inst/fifo40_inst/FF_16.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_15.C0 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_19.A1 - 0.5 fifo_colector_inst/fifo40_inst/LUT4_18.A1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_17.A1 - -fifo_colector_inst/fifo40_inst/w_gcount_r26 - fifo_colector_inst/fifo40_inst/FF_14.Q0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_14.A0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_19.B1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_18.C1 - -fifo_colector_inst/fifo40_inst/w_gcount_r27 - fifo_colector_inst/fifo40_inst/FF_14.Q1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_14.B0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_19.C1 - 0.9 fifo_colector_inst/fifo40_inst/LUT4_18.B0 - -fifo_colector_inst/fifo40_inst/w_gcount_r28 - fifo_colector_inst/fifo40_inst/FF_12.Q0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_14.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_19.D0 - 0.3 fifo_colector_inst/fifo40_inst/LUT4_18.D0 - -fifo_colector_inst/fifo40_inst/w_gcount_r29 - fifo_colector_inst/fifo40_inst/FF_12.Q1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_14.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_19.B0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_18.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_2.A0 - 0.8 fifo_colector_inst/fifo40_inst/LUT4_2.A1 - -fifo_colector_inst/fifo40_inst/w_gcount_r3 - fifo_colector_inst/fifo40_inst/FF_38.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_18.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r4 - fifo_colector_inst/fifo40_inst/FF_36.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_16.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r5 - fifo_colector_inst/fifo40_inst/FF_36.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_16.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r6 - fifo_colector_inst/fifo40_inst/FF_34.Q0 - 0.4 fifo_colector_inst/fifo40_inst/FF_14.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r7 - fifo_colector_inst/fifo40_inst/FF_34.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_14.M1 - -fifo_colector_inst/fifo40_inst/w_gcount_r8 - fifo_colector_inst/fifo40_inst/FF_32.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_12.M0 - -fifo_colector_inst/fifo40_inst/w_gcount_r9 - fifo_colector_inst/fifo40_inst/FF_32.Q1 - 0.6 fifo_colector_inst/fifo40_inst/FF_12.M1 - -fifo_colector_inst/fifo40_inst/w_gctr_ci - fifo_colector_inst/fifo40_inst/w_gctr_cia.FCO - 0.0 fifo_colector_inst/fifo40_inst/FF_100.FCI - -fifo_colector_inst/fifo40_inst/w_gdata_0 - fifo_colector_inst/fifo40_inst/XOR2_t16.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t16.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_1 - fifo_colector_inst/fifo40_inst/XOR2_t16.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t16.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_2 - fifo_colector_inst/fifo40_inst/XOR2_t14.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t14.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_3 - fifo_colector_inst/fifo40_inst/XOR2_t14.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t14.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_4 - fifo_colector_inst/fifo40_inst/XOR2_t12.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t12.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_5 - fifo_colector_inst/fifo40_inst/XOR2_t12.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t12.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_6 - fifo_colector_inst/fifo40_inst/XOR2_t10.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t10.DI0 - -fifo_colector_inst/fifo40_inst/w_gdata_7 - fifo_colector_inst/fifo40_inst/XOR2_t10.F1 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t10.DI1 - -fifo_colector_inst/fifo40_inst/w_gdata_8 - fifo_colector_inst/fifo40_inst/XOR2_t9.F0 - 0.0 fifo_colector_inst/fifo40_inst/XOR2_t9.DI0 - -fifo_colector_inst/fifo40_inst/wcount_0 - fifo_colector_inst/fifo40_inst/FF_100.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_100.B0 - 1.0 fifo_colector_inst/fifo40_inst/full_cmp_0.A0 - 0.3 fifo_colector_inst/fifo40_inst/XOR2_t16.D0 - 0.6 fifo_colector_inst/fifo40_inst/FF_80.M0 - -fifo_colector_inst/fifo40_inst/wcount_1 - fifo_colector_inst/fifo40_inst/FF_100.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_100.B1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_0.B1 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t16.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t16.B1 - 0.6 fifo_colector_inst/fifo40_inst/FF_80.M1 - -fifo_colector_inst/fifo40_inst/wcount_2 - fifo_colector_inst/fifo40_inst/FF_98.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_98.A0 - 0.9 fifo_colector_inst/fifo40_inst/full_cmp_1.A0 - 0.4 fifo_colector_inst/fifo40_inst/XOR2_t16.C1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t14.C0 - 1.2 fifo_colector_inst/fifo40_inst/FF_78.M0 - -fifo_colector_inst/fifo40_inst/wcount_3 - fifo_colector_inst/fifo40_inst/FF_98.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_98.A1 - 0.5 fifo_colector_inst/fifo40_inst/full_cmp_1.B1 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.D0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.D1 - 0.9 fifo_colector_inst/fifo40_inst/FF_78.M1 - -fifo_colector_inst/fifo40_inst/wcount_4 - fifo_colector_inst/fifo40_inst/FF_96.Q0 - 0.6 fifo_colector_inst/fifo40_inst/FF_96.B0 - 1.2 fifo_colector_inst/fifo40_inst/full_cmp_2.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.C1 - 0.9 fifo_colector_inst/fifo40_inst/XOR2_t12.A0 - 0.6 fifo_colector_inst/fifo40_inst/FF_76.M0 - -fifo_colector_inst/fifo40_inst/wcount_5 - fifo_colector_inst/fifo40_inst/FF_96.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_96.A1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_2.A1 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t12.C0 - 1.1 fifo_colector_inst/fifo40_inst/XOR2_t12.C1 - 0.6 fifo_colector_inst/fifo40_inst/FF_76.M1 - -fifo_colector_inst/fifo40_inst/wcount_6 - fifo_colector_inst/fifo40_inst/FF_94.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_94.B0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.B0 - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t12.D1 - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t10.D0 - 0.9 fifo_colector_inst/fifo40_inst/FF_74.M0 - -fifo_colector_inst/fifo40_inst/wcount_7 - fifo_colector_inst/fifo40_inst/FF_94.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_94.B1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_3.A1 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t10.B0 - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t10.B1 - 0.6 fifo_colector_inst/fifo40_inst/FF_74.M1 - -fifo_colector_inst/fifo40_inst/wcount_8 - fifo_colector_inst/fifo40_inst/FF_92.Q0 - 0.5 fifo_colector_inst/fifo40_inst/FF_92.B0 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_4.B0 - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t10.D1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.C0 - 0.6 fifo_colector_inst/fifo40_inst/FF_72.M0 - -fifo_colector_inst/fifo40_inst/wcount_9 - fifo_colector_inst/fifo40_inst/FF_92.Q1 - 0.4 fifo_colector_inst/fifo40_inst/FF_92.B1 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.D0 - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t9.M1 - 0.6 fifo_colector_inst/fifo40_inst/FF_72.M1 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_1.C0 - 0.6 fifo_colector_inst/fifo40_inst/LUT4_1.C1 - -fifo_colector_inst/fifo40_inst/wcount_r0 - fifo_colector_inst/fifo40_inst/LUT4_14.F1 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_0.A0 - -fifo_colector_inst/fifo40_inst/wcount_r1 - fifo_colector_inst/fifo40_inst/LUT4_15.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_0.A1 - -fifo_colector_inst/fifo40_inst/wcount_r2 - fifo_colector_inst/fifo40_inst/LUT4_17.F0 - 0.5 fifo_colector_inst/fifo40_inst/empty_cmp_1.B0 - -fifo_colector_inst/fifo40_inst/wcount_r3 - fifo_colector_inst/fifo40_inst/LUT4_17.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_1.A1 - -fifo_colector_inst/fifo40_inst/wcount_r4 - fifo_colector_inst/fifo40_inst/LUT4_18.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_2.B0 - -fifo_colector_inst/fifo40_inst/wcount_r5 - fifo_colector_inst/fifo40_inst/LUT4_19.F1 - 0.6 fifo_colector_inst/fifo40_inst/empty_cmp_2.B1 - -fifo_colector_inst/fifo40_inst/wcount_r7 - fifo_colector_inst/fifo40_inst/LUT4_18.F0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_3.A1 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_18.D1 - -fifo_colector_inst/fifo40_inst/wcount_r8 - fifo_colector_inst/fifo40_inst/LUT4_19.F0 - 0.9 fifo_colector_inst/fifo40_inst/empty_cmp_4.A0 - 0.1 fifo_colector_inst/fifo40_inst/LUT4_19.D1 - -fifo_colector_inst/fifo40_inst/wptr_0 - fifo_colector_inst/fifo40_inst/FF_80.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA5 - -fifo_colector_inst/fifo40_inst/wptr_1 - fifo_colector_inst/fifo40_inst/FF_80.Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA6 - -fifo_colector_inst/fifo40_inst/wptr_2 - fifo_colector_inst/fifo40_inst/FF_78.Q0 - 0.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA7 - -fifo_colector_inst/fifo40_inst/wptr_3 - fifo_colector_inst/fifo40_inst/FF_78.Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA8 - -fifo_colector_inst/fifo40_inst/wptr_4 - fifo_colector_inst/fifo40_inst/FF_76.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA9 - -fifo_colector_inst/fifo40_inst/wptr_5 - fifo_colector_inst/fifo40_inst/FF_76.Q1 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA10 - -fifo_colector_inst/fifo40_inst/wptr_6 - fifo_colector_inst/fifo40_inst/FF_74.Q0 - 0.4 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA11 - -fifo_colector_inst/fifo40_inst/wptr_7 - fifo_colector_inst/fifo40_inst/FF_74.Q1 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA12 - -fifo_colector_inst/fifo40_inst/wptr_8 - fifo_colector_inst/fifo40_inst/FF_72.Q0 - 0.5 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.ADA13 - -fifo_colector_inst/fifo40_inst/wptr_9 - fifo_colector_inst/fifo40_inst/FF_72.Q1 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_1.B0 - 0.7 fifo_colector_inst/fifo40_inst/LUT4_1.B1 - -fifo_colector_inst/fifo40_inst/wren_i - fifo_colector_inst/fifo40_inst/AND2_t20.F0 - 0.6 fifo_colector_inst/fifo40_inst/FF_100.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_98.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_96.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_94.CE - 0.6 fifo_colector_inst/fifo40_inst/FF_92.CE - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_ci_a.A1 - 0.7 fifo_colector_inst/fifo40_inst/full_cmp_ci_a.B1 - 0.3 fifo_colector_inst/fifo40_inst/XOR2_t16.CE - 0.6 fifo_colector_inst/fifo40_inst/XOR2_t14.CE - 0.7 fifo_colector_inst/fifo40_inst/XOR2_t12.CE - 0.8 fifo_colector_inst/fifo40_inst/XOR2_t10.CE - 0.5 fifo_colector_inst/fifo40_inst/XOR2_t9.CE - 0.3 fifo_colector_inst/fifo40_inst/FF_80.CE - 0.8 fifo_colector_inst/fifo40_inst/FF_78.CE - 0.8 fifo_colector_inst/fifo40_inst/FF_76.CE - 0.7 fifo_colector_inst/fifo40_inst/FF_74.CE - 0.3 fifo_colector_inst/fifo40_inst/FF_72.CE - 1.0 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CEA - -fifo_colector_inst/in_empty_pmux - fifo_colector_inst/in_empty_pmux_0.F0 - 0.2 fifo_colector_inst/in_read_enable_1_.fb.LSR - 0.2 fifo_colector_inst/in_read_enable_2_.fb.LSR - -fifo_colector_inst/in_empty_pmux_0 - fifo_colector_inst/in_empty_pmux_0.F1 - 0.4 fifo_colector_inst/in_empty_pmux_0.A0 - -fifo_colector_inst/in_empty_pmux_i - fifo_colector_inst/in_empty_pmux_0_RNIDRET.OFX0 - 0.0 fifo_colector_inst/in_empty_pmux_0_RNIDRET.DI0 - 1.2 fifo_colector_inst/data_buffer_3[0].CE - 1.2 fifo_colector_inst/data_buffer_3[1].CE - 0.7 fifo_colector_inst/data_buffer_3[2].CE - 0.7 fifo_colector_inst/data_buffer_3[3].CE - 1.4 fifo_colector_inst/data_buffer_3[4].CE - 1.3 fifo_colector_inst/data_buffer_3[5].CE - 1.3 fifo_colector_inst/data_buffer_3[6].CE - 0.4 fifo_colector_inst/data_buffer_3[7].CE - 0.4 fifo_colector_inst/data_buffer_3_0[9].CE - 1.2 fifo_colector_inst/data_buffer_3_0[11].CE - 1.1 fifo_colector_inst/data_buffer_3_0[13].CE - 0.7 fifo_colector_inst/data_buffer_3_0[15].CE - 1.4 fifo_colector_inst/data_buffer_3_0[17].CE - 1.4 fifo_colector_inst/data_buffer_3_0[19].CE - 1.1 fifo_colector_inst/data_buffer_3_0[21].CE - 0.9 fifo_colector_inst/data_buffer_3_0[23].CE - 1.0 fifo_colector_inst/data_buffer_3_0[25].CE - 0.8 fifo_colector_inst/data_buffer_3_0[27].CE - 0.9 fifo_colector_inst/data_buffer_3_0[29].CE - 1.2 fifo_colector_inst/data_buffer_3_0[31].CE - 1.4 fifo_colector_inst/data_buffer[33].CE - -fifo_colector_inst/iterator[0] - fifo_colector_inst/un5_in_read_enable.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.C0 - 0.9 fifo_colector_inst/data_buffer_3[0].D0 - 0.9 fifo_colector_inst/data_buffer_3[0].D1 - 0.6 fifo_colector_inst/data_buffer_3[1].D0 - 0.6 fifo_colector_inst/data_buffer_3[1].D1 - 0.6 fifo_colector_inst/data_buffer_3[2].D0 - 0.6 fifo_colector_inst/data_buffer_3[2].D1 - 0.6 fifo_colector_inst/data_buffer_3[3].D0 - 0.6 fifo_colector_inst/data_buffer_3[3].D1 - 0.5 fifo_colector_inst/data_buffer_3[4].C0 - 0.5 fifo_colector_inst/data_buffer_3[4].C1 - 0.5 fifo_colector_inst/data_buffer_3[5].D0 - 0.5 fifo_colector_inst/data_buffer_3[5].D1 - 0.5 fifo_colector_inst/data_buffer_3[6].C0 - 0.5 fifo_colector_inst/data_buffer_3[6].C1 - 1.3 fifo_colector_inst/data_buffer_3[7].B0 - 1.3 fifo_colector_inst/data_buffer_3[7].B1 - 1.0 fifo_colector_inst/data_buffer_3_0[9].D0 - 1.0 fifo_colector_inst/data_buffer_3_0[9].D1 - 0.9 fifo_colector_inst/data_buffer_3_0[11].D0 - 0.9 fifo_colector_inst/data_buffer_3_0[11].D1 - 1.4 fifo_colector_inst/data_buffer_3_0[13].A0 - 1.1 fifo_colector_inst/data_buffer_3_0[13].D1 - 0.6 fifo_colector_inst/data_buffer_3_0[15].D0 - 0.6 fifo_colector_inst/data_buffer_3_0[15].D1 - 1.3 fifo_colector_inst/data_buffer_3_0[17].B0 - 0.9 fifo_colector_inst/data_buffer_3_0[17].D1 - 1.3 fifo_colector_inst/data_buffer_3_0[19].A0 - 0.9 fifo_colector_inst/data_buffer_3_0[19].D1 - 1.1 fifo_colector_inst/data_buffer_3_0[21].D0 - 1.1 fifo_colector_inst/data_buffer_3_0[21].D1 - 0.9 fifo_colector_inst/data_buffer_3_0[23].D0 - 0.9 fifo_colector_inst/data_buffer_3_0[23].D1 - 0.7 fifo_colector_inst/data_buffer_3_0[25].C0 - 0.8 fifo_colector_inst/data_buffer_3_0[25].D1 - 0.6 fifo_colector_inst/data_buffer_3_0[27].B0 - 0.6 fifo_colector_inst/data_buffer_3_0[27].D1 - 1.0 fifo_colector_inst/data_buffer_3_0[29].B0 - 1.0 fifo_colector_inst/data_buffer_3_0[29].B1 - 0.8 fifo_colector_inst/data_buffer_3_0[31].C0 - 1.0 fifo_colector_inst/data_buffer_3_0[31].B1 - 1.0 fifo_colector_inst/data_buffer[33].M0 - 0.3 fifo_colector_inst/un5_in_read_enable.C0 - 0.6 fifo_colector_inst/un5_in_read_enable.M1 - 0.7 fifo_colector_inst/in_read_enable_1_.fb.C0 - 0.7 fifo_colector_inst/in_read_enable_1_.fb.C1 - 0.6 fifo_colector_inst/in_empty_pmux_0.D1 - -fifo_colector_inst/iterator[1] - fifo_colector_inst/un5_in_read_enable.Q1 - 1.0 fifo_colector_inst/in_empty_pmux_0_RNIDRET.M0 - 0.9 fifo_colector_inst/data_buffer_3[0].A0 - 0.9 fifo_colector_inst/data_buffer_3[0].A1 - 0.9 fifo_colector_inst/data_buffer_3[1].A0 - 0.9 fifo_colector_inst/data_buffer_3[1].A1 - 0.6 fifo_colector_inst/data_buffer_3[2].A0 - 0.6 fifo_colector_inst/data_buffer_3[2].A1 - 0.6 fifo_colector_inst/data_buffer_3[3].A0 - 0.6 fifo_colector_inst/data_buffer_3[3].A1 - 0.6 fifo_colector_inst/data_buffer_3[4].A0 - 0.6 fifo_colector_inst/data_buffer_3[4].A1 - 0.6 fifo_colector_inst/data_buffer_3[5].A0 - 0.6 fifo_colector_inst/data_buffer_3[5].A1 - 0.6 fifo_colector_inst/data_buffer_3[6].A0 - 0.6 fifo_colector_inst/data_buffer_3[6].A1 - 1.1 fifo_colector_inst/data_buffer_3[7].A0 - 1.1 fifo_colector_inst/data_buffer_3[7].A1 - 1.3 fifo_colector_inst/data_buffer[33].M1 - 0.5 fifo_colector_inst/un5_in_read_enable.B0 - 0.8 fifo_colector_inst/in_read_enable_1_.fb.A0 - 0.8 fifo_colector_inst/in_read_enable_2_.fb.A0 - 0.8 fifo_colector_inst/in_empty_pmux_0.B0 - 0.8 fifo_colector_inst/iterator_RNI7U5I[1].D0 - -fifo_colector_inst/iterator_RNI7U5I[1] - fifo_colector_inst/iterator_RNI7U5I[1].F0 - 1.2 fifo_colector_inst/data_buffer_3_0[9].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[11].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[13].LSR - 1.3 fifo_colector_inst/data_buffer_3_0[15].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[17].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[19].LSR - 0.9 fifo_colector_inst/data_buffer_3_0[21].LSR - 1.3 fifo_colector_inst/data_buffer_3_0[23].LSR - 0.7 fifo_colector_inst/data_buffer_3_0[25].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[27].LSR - 0.7 fifo_colector_inst/data_buffer_3_0[29].LSR - 0.8 fifo_colector_inst/data_buffer_3_0[31].LSR - -fifo_colector_inst/un5_in_read_enable - fifo_colector_inst/un5_in_read_enable.F0 - 0.0 fifo_colector_inst/un5_in_read_enable.DI0 - -fifo_empty1_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.A0 - 0.9 fifo_colector_inst/in_empty_pmux_0.C1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - 2.6 fifo_empty1_pad.PADDO - -fifo_empty[1] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 0.9 fifo_colector_inst/in_empty_pmux_0_RNIDRET.D0 - 0.9 fifo_colector_inst/in_empty_pmux_0.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - -fifo_empty[2] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.Q0 - 1.3 fifo_colector_inst/in_empty_pmux_0_RNIDRET.B1 - 1.4 fifo_colector_inst/in_empty_pmux_0.D0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.A0 - 1.3 fifo_colector_inst/iterator_RNI7U5I[1].A0 - -fifo_rden_c - trb_adapter_inst/burst.Q0 - 0.1 trb_adapter_inst/burst.D0 - 3.3 trb_adapter_inst/buf_rden_prev.M0 - 2.6 fifo_colector_inst/fifo40_inst/AND2_t19.C0 - 3.3 trb_adapter_inst/release_out.LSR - 3.4 trb_adapter_inst_FEE_DATA_WRITE_OUTio.TXDATA0 - 4.3 fifo_rden_pad.PADDO - -fifo_read[0] - fifo_colector_inst/in_read_enable_1_.fb.Q0 - 0.1 fifo_colector_inst/in_read_enable_1_.fb.D0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.B0 - -fifo_read[1] - fifo_colector_inst/in_read_enable_1_.fb.Q1 - 0.4 fifo_colector_inst/in_read_enable_1_.fb.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0 - -fifo_read[2] - fifo_colector_inst/in_read_enable_2_.fb.Q0 - 0.1 fifo_colector_inst/in_read_enable_2_.fb.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.D0 - -finished_c - trb_adapter_inst/release_out.Q0 - 0.5 trb_adapter_inst/finished_prev.M0 - 0.6 trb_adapter_inst/release_out.A0 - 1.0 finished_pad.PADDO - 0.5 trb_adapter_inst_FEE_DATAFINISHED_OUTio.TXDATA0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.A0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 1.6 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fb_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - 1.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 1.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 1.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 1.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0 - 1.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 1.0 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 1.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.A0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.D0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1 - -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.3 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 0.8 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.9 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.1 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.8 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[0] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 1.1 fifo_colector_inst/data_buffer_3[0].B0 - 1.1 fifo_colector_inst/data_buffer_3[0].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[10] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.9 fifo_colector_inst/data_buffer_3_0[11].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[11] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 1.2 fifo_colector_inst/data_buffer_3_0[11].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[12] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 0.7 fifo_colector_inst/data_buffer_3_0[13].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[13] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.8 fifo_colector_inst/data_buffer_3_0[13].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[14] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 0.9 fifo_colector_inst/data_buffer_3_0[15].A0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[15] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.7 fifo_colector_inst/data_buffer_3_0[15].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[16] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 0.6 fifo_colector_inst/data_buffer_3_0[17].D0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[17] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 0.8 fifo_colector_inst/data_buffer_3_0[17].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[18] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.7 fifo_colector_inst/data_buffer_3_0[19].D0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[19] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 1.1 fifo_colector_inst/data_buffer_3_0[19].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[1] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.0 fifo_colector_inst/data_buffer_3[1].B0 - 1.0 fifo_colector_inst/data_buffer_3[1].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[20] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.9 fifo_colector_inst/data_buffer_3_0[21].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[21] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 1.0 fifo_colector_inst/data_buffer_3_0[21].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[22] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.8 fifo_colector_inst/data_buffer_3_0[23].C0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[23] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.9 fifo_colector_inst/data_buffer_3_0[23].A1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[2] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 1.0 fifo_colector_inst/data_buffer_3[2].C0 - 1.0 fifo_colector_inst/data_buffer_3[2].C1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[3] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 0.8 fifo_colector_inst/data_buffer_3[3].C0 - 0.8 fifo_colector_inst/data_buffer_3[3].C1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[4] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.9 fifo_colector_inst/data_buffer_3[4].D0 - 0.9 fifo_colector_inst/data_buffer_3[4].D1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[5] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 1.1 fifo_colector_inst/data_buffer_3[5].B0 - 1.1 fifo_colector_inst/data_buffer_3[5].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[6] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 0.9 fifo_colector_inst/data_buffer_3[6].B0 - 0.9 fifo_colector_inst/data_buffer_3[6].B1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[7] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 0.8 fifo_colector_inst/data_buffer_3[7].D0 - 0.8 fifo_colector_inst/data_buffer_3[7].D1 - -genblk1[0].un1_tdc_channel_fifo_out_inst[8] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 1.0 fifo_colector_inst/data_buffer_3_0[9].B0 - -genblk1[0].un1_tdc_channel_fifo_out_inst[9] - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3_0[9].C1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.2 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.A0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fb_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.D0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.A0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.B1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.C0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.A0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.B1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.A0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 1.1 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.C1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.A0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 1.0 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.C1 - -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.3 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 1.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.1 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.D0 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.9 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.2 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.5 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[0] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 0.9 fifo_colector_inst/data_buffer_3_0[25].A0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[10] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.9 fifo_colector_inst/data_buffer_3[2].B0 - 0.9 fifo_colector_inst/data_buffer_3[2].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[11] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 0.7 fifo_colector_inst/data_buffer_3[3].B0 - 0.7 fifo_colector_inst/data_buffer_3[3].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[12] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 0.6 fifo_colector_inst/data_buffer_3[4].B0 - 0.6 fifo_colector_inst/data_buffer_3[4].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[13] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.5 fifo_colector_inst/data_buffer_3[5].C0 - 0.5 fifo_colector_inst/data_buffer_3[5].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[14] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 0.4 fifo_colector_inst/data_buffer_3[6].D0 - 0.4 fifo_colector_inst/data_buffer_3[6].D1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[15] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.9 fifo_colector_inst/data_buffer_3[7].C0 - 0.9 fifo_colector_inst/data_buffer_3[7].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[16] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 0.7 fifo_colector_inst/data_buffer_3_0[9].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[17] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 1.1 fifo_colector_inst/data_buffer_3_0[9].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[18] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.8 fifo_colector_inst/data_buffer_3_0[11].B0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[19] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 0.9 fifo_colector_inst/data_buffer_3_0[11].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[1] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.0 fifo_colector_inst/data_buffer_3_0[25].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[20] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.8 fifo_colector_inst/data_buffer_3_0[13].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[21] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 0.8 fifo_colector_inst/data_buffer_3_0[13].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[22] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.6 fifo_colector_inst/data_buffer_3_0[15].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[23] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.8 fifo_colector_inst/data_buffer_3_0[15].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[2] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 0.5 fifo_colector_inst/data_buffer_3_0[27].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[3] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 0.7 fifo_colector_inst/data_buffer_3_0[27].B1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[4] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.7 fifo_colector_inst/data_buffer_3_0[29].C0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[5] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 0.8 fifo_colector_inst/data_buffer_3_0[29].A1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[6] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 0.6 fifo_colector_inst/data_buffer_3_0[31].D0 - -genblk1[1].un1_tdc_channel_fifo_out_inst[7] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 0.7 fifo_colector_inst/data_buffer_3_0[31].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[8] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 0.9 fifo_colector_inst/data_buffer_3[0].C0 - 0.9 fifo_colector_inst/data_buffer_3[0].C1 - -genblk1[1].un1_tdc_channel_fifo_out_inst[9] - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3[1].C0 - 0.9 fifo_colector_inst/data_buffer_3[1].C1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].M1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.C0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.LSR - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.B0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.A0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.M0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.D1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.B1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.C1 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].Q1 - 0.2 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO_0.D0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0.OFX0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.D0 - -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.M0 - -genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.Q0 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fb_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A0 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.M0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.C0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.M0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.D0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.C1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.C1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.Q1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.A1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.B1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.D1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.C1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.C0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.A1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.C0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.M1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.M1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_4.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_5.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_6.OFX0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_9.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.F0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_8.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_11.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t19.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.A1 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CE - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CE - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEB - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.OCEB - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB5 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.Q1 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB6 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB7 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB8 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.Q1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB10 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB11 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.Q1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB12 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q0 - 1.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADB13 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.D0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.M0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.C0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.M0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.D1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.D0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.B0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.C1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.C1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.C1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.Q1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A0 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.A0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_2.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.Q1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia.FCO - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.FCI - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.F1 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.DI1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.F0 - 0.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.DI0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.C0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.B1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.B0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.D1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.A1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.B0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.C1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.A1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.A1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.B0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.D1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.B1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3.A1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.B1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.M1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4.A0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.D1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.B0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.Q1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.B1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.C0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_14.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.B0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_15.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_16.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_19.OFX0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2.B1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.F0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3.B1 - 0.1 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_18.D1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_21.F1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4.A0 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA5 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA6 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA7 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA8 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA10 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q0 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA11 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.Q1 - 0.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA12 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q0 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.ADA13 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/LUT4_0.A1 - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.A1 - 0.9 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a.B1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CE - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CE - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CE - 0.5 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CE - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CEA - -genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.C0 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA9 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA11 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA12 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA13 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIA15 - 1.0 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB6 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB8 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DIB9 - -genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.Q0 - 0.2 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.D0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.3 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].M1 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M0 - -genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].M1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[0] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA0 - 0.9 fifo_colector_inst/data_buffer_3_0[17].C0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[10] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA10 - 0.8 fifo_colector_inst/data_buffer_3_0[27].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[11] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA11 - 0.7 fifo_colector_inst/data_buffer_3_0[27].C1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[12] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA12 - 1.0 fifo_colector_inst/data_buffer_3_0[29].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[13] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA13 - 0.8 fifo_colector_inst/data_buffer_3_0[29].D1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[14] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA14 - 1.1 fifo_colector_inst/data_buffer_3_0[31].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[15] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA15 - 0.8 fifo_colector_inst/data_buffer_3_0[31].D1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[16] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA16 - 1.0 fifo_colector_inst/data_buffer_3[0].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[17] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA17 - 1.0 fifo_colector_inst/data_buffer_3[1].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[18] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB0 - 0.8 fifo_colector_inst/data_buffer_3[2].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[19] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB1 - 0.8 fifo_colector_inst/data_buffer_3[3].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[1] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA1 - 1.1 fifo_colector_inst/data_buffer_3_0[17].C1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[20] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB2 - 0.8 fifo_colector_inst/data_buffer_3[4].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[21] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB3 - 0.9 fifo_colector_inst/data_buffer_3[5].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[22] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB4 - 0.9 fifo_colector_inst/data_buffer_3[6].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[23] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOB5 - 0.9 fifo_colector_inst/data_buffer_3[7].M0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[2] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA2 - 1.0 fifo_colector_inst/data_buffer_3_0[19].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[3] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA3 - 1.0 fifo_colector_inst/data_buffer_3_0[19].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[4] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA4 - 0.9 fifo_colector_inst/data_buffer_3_0[21].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[5] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA5 - 1.1 fifo_colector_inst/data_buffer_3_0[21].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[6] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA6 - 1.0 fifo_colector_inst/data_buffer_3_0[23].A0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[7] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA7 - 1.0 fifo_colector_inst/data_buffer_3_0[23].B1 - -genblk1[2].un1_tdc_channel_fifo_out_inst[8] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA8 - 1.0 fifo_colector_inst/data_buffer_3_0[25].B0 - -genblk1[2].un1_tdc_channel_fifo_out_inst[9] - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.DOA9 - 0.9 fifo_colector_inst/data_buffer_3_0[25].C1 - -hades_buf_drop_c[1] - hades_tdc_bundle_inst_buf_drop_1io[1].IOLDO - 0.0 hades_buf_drop_pad[1].IOLDO - -hades_buf_finished_c - hades_tdc_bundle_inst/buf_finished5_0_a2_0.Q0 - 0.9 hades_tdc_bundle_inst/buf_release.M0 - 1.2 hades_buf_finished_pad.PADDO - -hades_buf_out_valid_c - hades_tdc_bundle_inst_buf_out_validio.IOLDO - 0.0 hades_buf_out_valid_pad.IOLDO - -hades_buf_release_c - hades_tdc_bundle_inst/buf_release.Q0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[0].D0 - 1.2 hades_tdc_bundle_inst/hit_valid_1_RNO[0].B1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].D0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].D1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].C1 - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[3].C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[3].B1 - 1.3 hades_buf_release_pad.PADDO - -hades_dbg2_coarse_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.C1 - 0.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.C1 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].A0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].A1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B1 - 1.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.D1 - 1.8 hades_dbg2_coarse_pad[0].PADDO - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].TXDATA0 - -hades_dbg2_coarse_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.Q1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.D1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.B1 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].D0 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.B1 - 1.8 hades_dbg2_coarse_pad[1].PADDO - 1.5 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].TXDATA0 - -hades_dbg2_coarse_c[2] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q0 - 0.3 hades_tdc_bundle_inst/coarse_RNI6RPP[2].C0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].B1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A1 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].M1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C1 - 2.7 hades_dbg2_coarse_pad[2].PADDO - 2.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].TXDATA0 - -hades_dbg2_coarse_c[3] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A0 - 0.5 hades_tdc_bundle_inst/coarse_RNI6RPP[2].C1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A0 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.A0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.C0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A1 - 2.0 hades_dbg2_coarse_pad[3].PADDO - 1.8 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].TXDATA0 - -hades_dbg2_coarse_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q0 - 0.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.C1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.D1 - 1.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].M1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].M1 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.C0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.D1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.D1 - 3.0 hades_dbg2_coarse_pad[4].PADDO - 1.9 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].TXDATA0 - -hades_dbg2_coarse_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.Q1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.D1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.A1 - 2.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M0 - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.B1 - 2.9 hades_dbg2_coarse_pad[5].PADDO - 2.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].TXDATA0 - -hades_dbg2_coarse_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.C1 - 2.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].M1 - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].M1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.C0 - 2.5 hades_dbg2_coarse_pad[6].PADDO - -hades_dbg2_coarse_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D1 - 1.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M0 - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.A0 - 3.3 hades_dbg2_coarse_pad[7].PADDO - -hades_dbg2_coarse_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.Q0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.C1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.D1 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.C0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.C1 - 1.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].M1 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].M1 - 2.4 hades_dbg2_coarse_pad[8].PADDO - -hades_dbg2_out_c[0] - hades_tdc_bundle_inst_hitbuffer_1_io[0].IOLDO - 0.0 hades_dbg2_out_pad[0].IOLDO - -hades_dbg2_out_c[10] - hades_tdc_bundle_inst/hitbuffer_1_[10].Q0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[7].M0 - 1.7 hades_dbg2_out_pad[10].PADDO - -hades_dbg2_out_c[11] - hades_tdc_bundle_inst/hitbuffer_1_[10].Q1 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[7].M1 - 1.9 hades_dbg2_out_pad[11].PADDO - -hades_dbg2_out_c[12] - hades_tdc_bundle_inst/hitbuffer_1_[11].Q0 - 1.0 hades_tdc_bundle_inst/drop_cmp_buf_1[8].M0 - 1.7 hades_dbg2_out_pad[12].PADDO - -hades_dbg2_out_c[16] - hades_tdc_bundle_inst_hitbuffer_1_io[12].IOLDO - 0.0 hades_dbg2_out_pad[16].IOLDO - -hades_dbg2_out_c[17] - hades_tdc_bundle_inst_hitbuffer_1_io[13].IOLDO - 0.0 hades_dbg2_out_pad[17].IOLDO - -hades_dbg2_out_c[18] - hades_tdc_bundle_inst_hitbuffer_1_io[14].IOLDO - 0.0 hades_dbg2_out_pad[18].IOLDO - -hades_dbg2_out_c[1] - hades_tdc_bundle_inst_hitbuffer_1_io[1].IOLDO - 0.0 hades_dbg2_out_pad[1].IOLDO - -hades_dbg2_out_c[20] - hades_tdc_bundle_inst_hitbuffer_1_io[15].IOLDO - 0.0 hades_dbg2_out_pad[20].IOLDO - -hades_dbg2_out_c[21] - hades_tdc_bundle_inst_hitbuffer_1_io[16].IOLDO - 0.0 hades_dbg2_out_pad[21].IOLDO - -hades_dbg2_out_c[22] - hades_tdc_bundle_inst_hitbuffer_1_io[17].IOLDO - 0.0 hades_dbg2_out_pad[22].IOLDO - -hades_dbg2_out_c[23] - hades_tdc_bundle_inst_hitbuffer_1_io[18].IOLDO - 0.0 hades_dbg2_out_pad[23].IOLDO - -hades_dbg2_out_c[24] - hades_tdc_bundle_inst_hitbuffer_1_io[19].IOLDO - 0.0 hades_dbg2_out_pad[24].IOLDO - -hades_dbg2_out_c[25] - hades_tdc_bundle_inst_hitbuffer_1_io[20].IOLDO - 0.0 hades_dbg2_out_pad[25].IOLDO - -hades_dbg2_out_c[26] - hades_tdc_bundle_inst_hitbuffer_1_io[21].IOLDO - 0.0 hades_dbg2_out_pad[26].IOLDO - -hades_dbg2_out_c[27] - hades_tdc_bundle_inst_hitbuffer_1_io[22].IOLDO - 0.0 hades_dbg2_out_pad[27].IOLDO - -hades_dbg2_out_c[28] - hades_tdc_bundle_inst_hitbuffer_1_io[23].IOLDO - 0.0 hades_dbg2_out_pad[28].IOLDO - -hades_dbg2_out_c[2] - hades_tdc_bundle_inst_hitbuffer_1_io[2].IOLDO - 0.0 hades_dbg2_out_pad[2].IOLDO - -hades_dbg2_out_c[4] - hades_tdc_bundle_inst/hitbuffer_1_[4].Q0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[1].M0 - 1.8 hades_dbg2_out_pad[4].PADDO - -hades_dbg2_out_c[5] - hades_tdc_bundle_inst/hitbuffer_1_[4].Q1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[1].M1 - 1.4 hades_dbg2_out_pad[5].PADDO - -hades_dbg2_out_c[6] - hades_tdc_bundle_inst/hitbuffer_1_[6].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[3].M0 - 1.5 hades_dbg2_out_pad[6].PADDO - -hades_dbg2_out_c[7] - hades_tdc_bundle_inst/hitbuffer_1_[6].Q1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[3].M1 - 1.4 hades_dbg2_out_pad[7].PADDO - -hades_dbg2_out_c[8] - hades_tdc_bundle_inst/hitbuffer_1_[8].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[5].M0 - 1.5 hades_dbg2_out_pad[8].PADDO - -hades_dbg2_out_c[9] - hades_tdc_bundle_inst/hitbuffer_1_[8].Q1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_1[5].M1 - 1.5 hades_dbg2_out_pad[9].PADDO - -hades_discard_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.Q0 - 1.5 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].D0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].M0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].B1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].A1 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B0 - 1.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.B0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].B0 - 1.3 hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].A0 - 2.1 hades_discard_pad.PADDO - -hades_drop_cmp_buf_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.D1 - 1.1 hades_drop_cmp_buf_pad[0].PADDO - -hades_drop_cmp_buf_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_1[1].Q1 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.A1 - 1.3 hades_drop_cmp_buf_pad[1].PADDO - -hades_drop_cmp_buf_c[2] - hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C0 - 1.5 hades_drop_cmp_buf_pad[2].PADDO - -hades_drop_cmp_buf_c[3] - hades_tdc_bundle_inst/drop_cmp_buf_1[3].Q1 - 1.0 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A0 - 1.5 hades_drop_cmp_buf_pad[3].PADDO - -hades_drop_cmp_buf_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q0 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.A1 - 1.4 hades_drop_cmp_buf_pad[4].PADDO - -hades_drop_cmp_buf_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_1[5].Q1 - 0.9 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.C1 - 1.4 hades_drop_cmp_buf_pad[5].PADDO - -hades_drop_cmp_buf_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B0 - 1.2 hades_drop_cmp_buf_pad[6].PADDO - -hades_drop_cmp_buf_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_1[7].Q1 - 0.8 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.A0 - 1.6 hades_drop_cmp_buf_pad[7].PADDO - -hades_drop_cmp_buf_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_1[8].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D1 - 1.4 hades_drop_cmp_buf_pad[8].PADDO - -hades_drop_cmp_buf_coarse_c[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.C1 - 1.5 hades_drop_cmp_buf_coarse_pad[0].PADDO - -hades_drop_cmp_buf_coarse_c[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_1_0.B1 - 1.9 hades_drop_cmp_buf_coarse_pad[1].PADDO - -hades_drop_cmp_buf_coarse_c[2] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B0 - 1.5 hades_drop_cmp_buf_coarse_pad[2].PADDO - -hades_drop_cmp_buf_coarse_c[3] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D0 - 2.0 hades_drop_cmp_buf_coarse_pad[3].PADDO - -hades_drop_cmp_buf_coarse_c[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.B1 - 1.8 hades_drop_cmp_buf_coarse_pad[4].PADDO - -hades_drop_cmp_buf_coarse_c[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].Q1 - 0.5 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.D1 - 1.9 hades_drop_cmp_buf_coarse_pad[5].PADDO - -hades_drop_cmp_buf_coarse_c[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q0 - 0.6 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C0 - 1.7 hades_drop_cmp_buf_coarse_pad[6].PADDO - -hades_drop_cmp_buf_coarse_c[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].Q1 - 0.4 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.D0 - 1.6 hades_drop_cmp_buf_coarse_pad[7].PADDO - -hades_drop_cmp_buf_coarse_c[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.B1 - 1.9 hades_drop_cmp_buf_coarse_pad[8].PADDO - -hades_drop_cmp_buf_coarse_c[9] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.Q0 - 0.7 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.C1 - 2.0 hades_drop_cmp_buf_coarse_pad[9].PADDO - -hades_drop_cmp_buf_valid_c - hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.Q0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.C0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].B0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[1].B1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.D1 - 1.3 hades_drop_cmp_buf_valid_pad.PADDO - -hades_hit_valid_c[0] - hades_tdc_bundle_inst/hit_valid_1_RNO[0].Q0 - 0.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].C0 - 0.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].D1 - 0.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.C0 - 1.2 hades_hit_valid_pad[0].PADDO - -hades_hit_valid_c[1] - hades_tdc_bundle_inst/hit_valid_1_RNO[1].Q0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.D0 - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[1].M0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C0 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.C0 - 1.1 hades_hit_valid_pad[1].PADDO - -hades_hit_valid_c[2] - hades_tdc_bundle_inst/hit_valid_1_RNO[2].Q0 - 0.2 hades_tdc_bundle_inst/hit_valid_1_RNO[2].D0 - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[2].A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.B0 - 1.2 hades_hit_valid_pad[2].PADDO - -hades_hit_valid_c[3] - hades_tdc_bundle_inst/hit_valid_1_RNO[3].Q0 - 0.2 hades_tdc_bundle_inst/hit_valid_1_RNO[3].D0 - 0.4 hades_tdc_bundle_inst/hit_valid_1_RNO[3].C1 - 0.9 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.A0 - 0.9 hades_hit_valid_pad[3].PADDO - -hades_invalid_dl_c[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].INFF - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M0 - 0.6 hades_invalid_dl_pad[0].PADDO - -hades_invalid_dl_c[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].M1 - 1.2 hades_invalid_dl_pad[1].PADDO - -hades_invalid_dl_c[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].Q1 - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].M0 - 1.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.D0 - 0.9 hades_invalid_dl_pad[2].PADDO - -hades_invalid_dl_c[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].Q0 - 1.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.B0 - 1.2 hades_invalid_dl_pad[3].PADDO - -hades_lvl1_c - hades_lvl1_pad.PADDI - 0.9 hades_lvl1_pad_RNINMH5.D0 - 0.0 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].DI - -hades_lvl1_c_i - hades_lvl1_pad_RNINMH5.F0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -hades_lvl1_invalid_c - hades_lvl1_invalid_pad.PADDI - 0.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].DI - -hades_offset_c[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].IOLDO - 0.0 hades_offset_pad[0].IOLDO - -hades_offset_c[1] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].IOLDO - 0.0 hades_offset_pad[1].IOLDO - -hades_offset_c[2] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].IOLDO - 0.0 hades_offset_pad[2].IOLDO - -hades_offset_c[3] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].IOLDO - 0.0 hades_offset_pad[3].IOLDO - -hades_offset_c[4] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].IOLDO - 0.0 hades_offset_pad[4].IOLDO - -hades_offset_c[5] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].IOLDO - 0.0 hades_offset_pad[5].IOLDO - -hades_offset_c[6] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].IOLDO - 0.0 hades_offset_pad[6].IOLDO - -hades_offset_c[7] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].IOLDO - 0.0 hades_offset_pad[7].IOLDO - -hades_offset_c[8] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].IOLDO - 0.0 hades_offset_pad[8].IOLDO - -hades_offset_valid_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.Q0 - 2.7 hades_offset_valid_pad.PADDO - 2.5 hades_tdc_bundle_inst_referenced_out_validio.TXDATA0 - -hades_raw_out_valid_c - hades_tdc_bundle_inst_referenced_out_validio.IOLDO - 0.0 hades_raw_out_valid_pad.IOLDO - -hades_tdc_bundle_inst.buf_out12 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F0 - 0.8 hades_tdc_bundle_inst_buf_out_validio.TXDATA0 - -hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F1 - 1.0 hades_tdc_bundle_inst_buf_drop_1io[1].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.OFX0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CE - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.D0 - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CE - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CE - 1.5 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CE - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CE - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CE - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q0 - 1.0 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].Q1 - 1.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].Q0 - 1.1 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].TXDATA0 - -hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].INFF - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].M0 - -hades_tdc_bundle_inst.hades_raw_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q0 - 1.0 hades_tdc_bundle_inst_hitbuffer_1_io[0].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[12] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q1 - 0.5 hades_tdc_bundle_inst_hitbuffer_1_io[12].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[13] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q0 - 0.9 hades_tdc_bundle_inst_hitbuffer_1_io[13].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[14] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].Q1 - 0.9 hades_tdc_bundle_inst_hitbuffer_1_io[14].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[15] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q0 - 1.2 hades_tdc_bundle_inst_hitbuffer_1_io[15].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[16] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].Q1 - 1.1 hades_tdc_bundle_inst_hitbuffer_1_io[16].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[17] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q0 - 1.0 hades_tdc_bundle_inst_hitbuffer_1_io[17].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[18] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].Q1 - 1.1 hades_tdc_bundle_inst_hitbuffer_1_io[18].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[19] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q0 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[19].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].Q1 - 0.8 hades_tdc_bundle_inst_hitbuffer_1_io[1].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[20] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].Q1 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[20].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[21] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q0 - 1.3 hades_tdc_bundle_inst_hitbuffer_1_io[21].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[22] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].Q1 - 0.7 hades_tdc_bundle_inst_hitbuffer_1_io[22].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[23] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].Q0 - 0.8 hades_tdc_bundle_inst_hitbuffer_1_io[23].TXDATA0 - -hades_tdc_bundle_inst.hades_raw_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].Q0 - 0.5 hades_tdc_bundle_inst_hitbuffer_1_io[2].TXDATA0 - -hades_tdc_bundle_inst/N_243_i - hades_tdc_bundle_inst/hit_valid_1_RNO[1].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].DI0 - -hades_tdc_bundle_inst/N_244_i - hades_tdc_bundle_inst/hit_valid_1_RNO[3].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[3].DI0 - -hades_tdc_bundle_inst/N_245_i - hades_tdc_bundle_inst/hit_valid_1_RNO[2].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[2].DI0 - -hades_tdc_bundle_inst/N_246_i - hades_tdc_bundle_inst/hit_valid_1_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hit_valid_1_RNO[0].DI0 - -hades_tdc_bundle_inst/N_247_i - hades_tdc_bundle_inst/hit_out_i_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hit_out_i_RNO[0].DI0 - -hades_tdc_bundle_inst/N_44 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F1 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].A0 - -hades_tdc_bundle_inst/N_45 - hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.F0 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.D1 - -hades_tdc_bundle_inst/N_46_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.DI0 - -hades_tdc_bundle_inst/N_50_i_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.DI1 - -hades_tdc_bundle_inst/N_59_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.DI0 - -hades_tdc_bundle_inst/N_66 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F1 - 0.2 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.D0 - -hades_tdc_bundle_inst/N_80 - hades_tdc_bundle_inst/buf_finished5_0_a2_0.F1 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.A0 - -hades_tdc_bundle_inst/N_90 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.F1 - 0.4 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.B0 - -hades_tdc_bundle_inst/SUM1_0_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.DI1 - -hades_tdc_bundle_inst/buf_finished5 - hades_tdc_bundle_inst/buf_finished5_0_a2_0.F0 - 0.0 hades_tdc_bundle_inst/buf_finished5_0_a2_0.DI0 - -hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.F0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[1].CE - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_1[3].CE - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[5].CE - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_1[7].CE - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_1[8].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CE - 1.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CE - 1.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CE - 1.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CE - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.DI1 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].F0 - 0.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].DI0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - hades_tdc_bundle_inst/coarse_RNI6RPP[2].F1 - 0.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].DI1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.DI0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.DI1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.DI0 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.F1 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.DI1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].M1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.DI0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.OFX0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.DI0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.F0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.C1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.D0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.B1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0.F1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.B0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.B1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.B0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.B1 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.D0 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.B1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.A0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.B0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.B0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.B1 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.B1 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.F1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.A1 - 0.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.A1 - 0.5 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.B0 - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.M0 - -hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.A1 - -hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].F1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.F1 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].Q1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].Q1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].M1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].F0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.A1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.D1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].Q1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.M0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].Q1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_RNI3HPF[7].C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.F0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.Q0 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.M0 - 1.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].B1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].A1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].F0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.B1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.A0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.F1 - 0.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CE - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].M1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].Q1 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.A0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].M0 - 1.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.OFX0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].D1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.F0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.F0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.A1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.A0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].C1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2.D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.C1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.C1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.F1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.F1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.FCO - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.FCI - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.Q0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].D0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.D1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.C0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0.B1 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.B1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].B1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.D0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.C0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].D0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.A0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.D1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.M0 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_1_sqmuxa_i_0.M0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.M0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.B0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].A0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.Q0 - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0.A1 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].D0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].D1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].Q1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.A0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.D1 - 1.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.B0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.D1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].C0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].Q0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0.A1 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1.C0 - 0.6 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0.B1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNICU4C[3].B0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].Q1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].B1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].Q0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0.B1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].C1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].Q1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0.A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].A0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNIOA5C[2].A1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.F0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.C1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.OFX0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].LSR - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].LSR - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.DI0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].LSR - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].F0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.LSR - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].F0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].DI0 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].F1 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].DI1 - -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.OFX0 - 0.0 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.DI0 - -hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.F0 - 0.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.DI0 - 0.8 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].M0 - -hades_tdc_bundle_inst/hades_raw_out[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q1 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[10].M1 - -hades_tdc_bundle_inst/hades_raw_out[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].Q0 - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[11].M0 - -hades_tdc_bundle_inst/hades_raw_out[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[4].M0 - -hades_tdc_bundle_inst/hades_raw_out[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].Q1 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[4].M1 - -hades_tdc_bundle_inst/hades_raw_out[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[6].M0 - -hades_tdc_bundle_inst/hades_raw_out[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].Q1 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[6].M1 - -hades_tdc_bundle_inst/hades_raw_out[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q0 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[8].M0 - -hades_tdc_bundle_inst/hades_raw_out[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].Q1 - 0.8 hades_tdc_bundle_inst/hitbuffer_1_[8].M1 - -hades_tdc_bundle_inst/hades_raw_out[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].Q0 - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[10].M0 - -hades_tdc_bundle_inst/hades_raw_out_valid - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.Q0 - 1.3 hades_tdc_bundle_inst/hit_valid_1_RNO[0].B0 - 1.2 hades_tdc_bundle_inst/hit_valid_1_RNO[2].D1 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[3].D1 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C0 - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.C1 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D0 - 0.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CE - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CE - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.F0 - 1.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CE - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CE - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CE - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CE - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CE - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CE - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CE - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CE - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CE - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CE - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].Q1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.A1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].Q0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.B1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].M0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].Q0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].Q1 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].M0 - 0.9 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].Q0 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].Q1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.A0 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].Q1 - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.A1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].M0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.A1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.C0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].Q1 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].M0 - 0.3 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.A0 - 1.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].M1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.LSR - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.B0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.D0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.C1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.B1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.D0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.B0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.D1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.A1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.A1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.C1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.C1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.C0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.M0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].Q1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced_RNIB4EQ[7].B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1_0.F1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m11_i_1.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_0.F0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].Q0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].M1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced7_rising_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.LSR - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.LSR - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.LSR - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.C1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.C0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].Q1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.B1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.B0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.A1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.D1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.D0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.D1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.D0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.B1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.D0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.C0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.C1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.A0 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].Q1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.A1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.A0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.B0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.A0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.A1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].Q1 - 0.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced_RNIT1GT[7].D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_0.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.F0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m11_i_m3.F0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.F1 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.DI1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.F1 - 0.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.F1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.B0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.B1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.B0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_0.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_0_o5 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i_1.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.C0 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.A0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal35_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.OFX0 - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.DI0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].Q1 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.D0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.D0 - 0.1 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_synced[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buffered1[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].Q0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].Q0 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].Q0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].Q0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].Q0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].M1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_cry - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_14 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_3.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N_19 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F1 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_data_tmp[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_21_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_27_0.F0 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.C0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_cry - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14 - hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_7.F0 - 0.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.C1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19 - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I_9_0_RNO.F0 - 0.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.D0 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[0] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_tmp[2] - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_0.FCI - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_0.F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.B0 - -hades_tdc_bundle_inst/hit_i[0] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q0 - 0.9 hades_tdc_bundle_inst/hit_valid_1_RNO[0].A0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[2].B1 - 0.7 hades_tdc_bundle_inst/hit_valid_1_RNO[3].A1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A0 - 0.3 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.D1 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B0 - 0.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.B1 - -hades_tdc_bundle_inst/hit_i[1] - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.Q1 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[0].M0 - 0.8 hades_tdc_bundle_inst/hit_valid_1_RNO[2].M0 - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[3].M0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.A1 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C0 - 0.4 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.C1 - -hades_tdc_bundle_inst/hit_out_i_6[2] - hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].OFX0 - 0.0 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].DI0 - -hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].F0 - 0.4 hades_tdc_bundle_inst/hit_out_i_RNO[0].M0 - -hades_tdc_bundle_inst/hit_valid25 - hades_tdc_bundle_inst/hit_valid25_0_I_27_0.F0 - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.B0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].C0 - 1.0 hades_tdc_bundle_inst/hit_valid_1_RNO[1].C1 - 0.6 hades_tdc_bundle_inst/drop_cmp_buf_valid_0_sqmuxa_0_a2.C1 - -hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_27_0.FCI - -hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - hades_tdc_bundle_inst/hit_valid25_0_I_1_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCI - -hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - hades_tdc_bundle_inst/hit_valid25_0_I_9_0.FCO - 0.0 hades_tdc_bundle_inst/hit_valid25_0_I_21_0.FCI - -hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2.F0 - 0.1 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2.D0 - -hades_trig_c - hades_trig_pad.PADDI - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].M1 - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].M1 - 1.1 hades_trig_pad_RNIE1B4.A0 - -hades_trig_c_i - hades_trig_pad_RNIE1B4.F0 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.5 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.8 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -hades_window_end_c - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.Q0 - 1.2 hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0].C0 - 2.5 hades_window_end_pad.PADDO - -last_buf_empty_c - fifo_colector_inst/fifo40_inst/FF_1.Q0 - 2.6 trb_adapter_inst/burst.C0 - 1.0 fifo_colector_inst/fifo40_inst/AND2_t19.D0 - 2.7 last_buf_empty_pad.PADDO - -pll0inst/GND - pll0inst/GND.F0 - 0.5 pll0inst/PLLInst_0.STDBY - -pll_clks[0] - pll0inst/PLLInst_0.CLKOP - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[0].out_buffered[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[0].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[0].out_buffered[4].CLK - 1.7 pll0inst/PLLInst_0.CLKFB - -pll_clks[1] - pll0inst/PLLInst_0.CLKOS - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[1].out_buffered[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[1].out_buffered[5].CLK - -pll_clks[2] - pll0inst/PLLInst_0.CLKOS2 - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[2].out_buffered[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[2].out_buffered[6].CLK - -pll_clks[3] - pll0inst/PLLInst_0.CLKOS3 - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_100.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_98.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_96.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_94.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_92.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_0.CLK - 1.7 hades_tdc_bundle_inst/hit_out_i_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.CLK - 1.7 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].CLK - 1.7 fifo_colector_inst/in_empty_pmux_0_RNIDRET.CLK - 1.7 fifo_colector_inst/data_buffer_3[0].CLK - 1.7 fifo_colector_inst/data_buffer_3[1].CLK - 1.7 fifo_colector_inst/data_buffer_3[2].CLK - 1.7 fifo_colector_inst/data_buffer_3[3].CLK - 1.7 fifo_colector_inst/data_buffer_3[4].CLK - 1.7 fifo_colector_inst/data_buffer_3[5].CLK - 1.7 fifo_colector_inst/data_buffer_3[6].CLK - 1.7 fifo_colector_inst/data_buffer_3[7].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[9].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[11].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[13].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[15].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[17].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[19].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[21].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[23].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[25].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[27].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[29].CLK - 1.7 fifo_colector_inst/data_buffer_3_0[31].CLK - 1.7 fifo_colector_inst/data_buffer[33].CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_30.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_28.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_26.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_24.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_22.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_10.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_8.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_6.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_4.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_2.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t16.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t14.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t12.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t10.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t9.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_80.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_78.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_76.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_74.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_72.CLK - 1.7 fifo_colector_inst/un5_in_read_enable.CLK - 1.7 fifo_colector_inst/in_read_enable_1_.fb.CLK - 1.7 fifo_colector_inst/in_read_enable_2_.fb.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t7.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t5.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t3.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t1.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t0.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t16.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t14.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t12.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t10.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/XOR2_t9.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/buf_finished5_0_a2_0.CLK - 1.7 hades_tdc_bundle_inst/buf_release.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.CLK - 1.7 hades_tdc_bundle_inst/coarse_RNI6RPP[2].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[4].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[6].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[8].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[10].CLK - 1.7 hades_tdc_bundle_inst/hitbuffer_1_[11].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[1].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[3].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[5].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[7].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_1[8].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8].CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_15.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[1].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[2].CLK - 1.7 hades_tdc_bundle_inst/hit_valid_1_RNO[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_RNO[0].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal35_1_0_o7.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_internal31_1_i_0.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[5].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_internal_2_1_0_.m15_i.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out_internal31_1_i_0_o5.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal_RNO.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3].CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/genblk1[3].out_buffered[7].CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5_0_a2.CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.CLK - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.CLK - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.CLK - 1.7 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[23].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[22].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[21].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[20].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[19].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[18].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[17].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[16].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[15].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[14].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[13].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[12].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[2].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[1].CLK - 1.7 hades_tdc_bundle_inst_hitbuffer_1_io[0].CLK - 1.7 hades_tdc_bundle_inst_buf_drop_1io[1].CLK - 1.7 hades_tdc_bundle_inst_buf_out_validio.CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0].CLK - 1.7 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0].CLK - 1.7 hades_tdc_bundle_inst_referenced_out_validio.CLK - 1.7 reset_dl_0io[1].CLK - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKA - 1.7 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0.CLKB - 1.7 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKA - -rd_clk_c - rd_clk_pad.PADDI - 1.7 fifo_colector_inst/fifo40_inst/FF_70.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_68.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_66.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_64.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_62.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_1.CLK - 1.7 trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t7.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t5.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t3.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t1.CLK - 1.7 fifo_colector_inst/fifo40_inst/XOR2_t0.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_50.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_48.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_46.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_44.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_42.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_40.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_38.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_36.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_34.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_32.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_20.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_18.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_16.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_14.CLK - 1.7 fifo_colector_inst/fifo40_inst/FF_12.CLK - 1.7 trb_adapter_inst/burst.CLK - 1.7 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].CLK - 1.7 trb_adapter_inst/buf_rden_prev.CLK - 1.7 trb_adapter_inst/finished_prev.CLK - 1.7 trb_adapter_inst/release_out.CLK - 1.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.CLK - 1.8 trb_adapter_inst_FEE_DATAFINISHED_OUTio.CLK - 1.8 trb_adapter_inst_FEE_DATA_WRITE_OUTio.CLK - 1.8 trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].CLK - 1.8 trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].CLK - 1.8 fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1.CLKB - -release_out_c - trb_adapter_inst/release_out.F0 - 0.7 release_out_pad.PADDO - 0.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.TXDATA0 - -reset_dc_c - reset_dc_pad.PADDI - 0.0 reset_dl_0io[1].DI - -reset_dl[1] - reset_dl_0io[1].INFF - 1.1 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.M0 - -reset_dl[2] - hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.Q0 - 0.8 hades_tdc_bundle_inst/hit_out_i_RNO[0].LSR - 0.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_50_i_i.LSR - 1.4 hades_tdc_bundle_inst/hit_out_i_6_f1_0[2].LSR - 2.1 genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 2.4 genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 3.4 genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data_11_.fb.LSR - 0.5 hades_tdc_bundle_inst/buf_finished5_0_a2_0.LSR - 0.9 hades_tdc_bundle_inst/buf_release.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc1.LSR - 2.0 hades_tdc_bundle_inst/coarse_RNI6RPP[2].LSR - 2.1 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc5.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_axbxc7.LSR - 2.0 hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_5.LSR - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en.LSR - 0.4 hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i.CE - 0.6 hades_tdc_bundle_inst/hit_valid_1_RNO[0].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[1].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[2].CE - 0.5 hades_tdc_bundle_inst/hit_valid_1_RNO[3].CE - 1.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid_RNO.LSR - 1.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1].LSR - 2.3 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14].LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16].LSR - 1.4 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18].LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22].LSR - 2.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23].LSR - 2.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A0 - 2.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3].A1 - 1.8 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup.M0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5].C1 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C0 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7].C1 - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4].LSR - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6].LSR - 1.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8].LSR - 1.7 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10].LSR - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11].LSR - 1.2 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_RNIG7JA.LSR - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4_f0_0_0.CE - 0.9 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready_4_iv_i_0.CE - 0.9 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0.LSR - 1.6 hades_tdc_bundle_inst/hit_valid_pmux_iv_0_a2_2_RNITDG11.M0 - 1.2 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.A0 - 3.2 genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.8 genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.2 genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/AND2_t20.LSR - 2.0 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_RNI97O31.A0 - 1.6 hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_RNI8UMR.C0 - 2.1 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.B0 - 2.5 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI5DQ71.A0 - 1.7 hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2].C0 - 0.2 hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa_0_a2.D0 - 1.4 hades_tdc_bundle_inst_buf_drop_1io[1].LSR - 1.8 trb_adapter_inst_FEE_TRG_RELEASE_OUTio.LSR - 1.8 trb_adapter_inst_FEE_DATAFINISHED_OUTio.LSR - 1.9 trb_adapter_inst_FEE_DATA_WRITE_OUTio.LSR - -trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0].INFF - 0.6 trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1].M0 - -trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0].INFF - 3.7 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M0 - -trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q0 - 0.5 trb_adapter_inst/burst.B1 - 0.3 trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].M1 - 0.5 trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.B0 - -trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2].Q1 - 0.5 trb_adapter_inst/burst.A1 - 0.3 trb_adapter_inst/LVL1_TRG_DATA_VALI_IN_rising.D0 - -trb_adapter_inst/buf_rden4 - trb_adapter_inst/burst.F0 - 0.0 trb_adapter_inst/burst.DI0 - -trb_adapter_inst/buf_rden_prev - trb_adapter_inst/buf_rden_prev.Q0 - 0.3 trb_adapter_inst/release_out.M0 - -trb_adapter_inst/finished_prev - trb_adapter_inst/finished_prev.Q0 - 0.5 trb_adapter_inst/release_out.B0 - -trig_c[0] - trig_pad[0].PADDI - 0.4 trig_pad_RNII4FF[0].D0 - -trig_c[1] - trig_pad[1].PADDI - 1.5 trig_pad_RNIJ5FF[1].D0 - -trig_c[2] - trig_pad[2].PADDI - 1.7 trig_pad_RNIK6FF[2].D0 - -trig_c_i[0] - trig_pad_RNII4FF[0].F0 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.4 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.5 genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -trig_c_i[1] - trig_pad_RNIJ5FF[1].F0 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.7 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.4 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -trig_c_i[2] - trig_pad_RNIK6FF[2].F0 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1].M1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2].M1 - 0.4 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3].M1 - 0.8 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4].M1 - 0.5 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6].M1 - 0.6 genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7].M1 - -un1_hit_i_2_0_a2 - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SUM1_0_0_o2_0.F0 - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[4].CE - 0.4 hades_tdc_bundle_inst/hitbuffer_1_[6].CE - 0.6 hades_tdc_bundle_inst/hitbuffer_1_[8].CE - 1.3 hades_tdc_bundle_inst/hitbuffer_1_[10].CE - 1.0 hades_tdc_bundle_inst/hitbuffer_1_[11].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[23].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[22].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[21].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[20].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[19].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[18].CE - 1.4 hades_tdc_bundle_inst_hitbuffer_1_io[17].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[16].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[15].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[14].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[13].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[12].CE - 1.5 hades_tdc_bundle_inst_hitbuffer_1_io[2].CE - 1.6 hades_tdc_bundle_inst_hitbuffer_1_io[1].CE - 1.8 hades_tdc_bundle_inst_hitbuffer_1_io[0].CE - -valid_fast_RNI999V - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast_RNI999V.F0 - 1.3 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4].LSR - 1.4 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1].LSR - 1.2 hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0].LSR diff --git a/impl1/s1_impl1.drc b/impl1/s1_impl1.drc deleted file mode 100644 index ec074a2..0000000 --- a/impl1/s1_impl1.drc +++ /dev/null @@ -1 +0,0 @@ -DRC detected 0 errors and 0 warnings. diff --git a/impl1/s1_impl1.edi b/impl1/s1_impl1.edi deleted file mode 100644 index eff80c7..0000000 --- a/impl1/s1_impl1.edi +++ /dev/null @@ -1,20420 +0,0 @@ -(edif top_tf - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timeStamp 2021 6 16 9 19 25) - (author "Synopsys, Inc.") - (program "Synplify Premier" (version "O-2018.09-SP1, mapper maprc, Build 4745R")) - ) - ) - (library LUCENT - (edifLevel 0) - (technology (numberDefinition )) - (cell PDPW16KD (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port DI0 (direction INPUT)) - (port DI1 (direction INPUT)) - (port DI2 (direction INPUT)) - (port DI3 (direction INPUT)) - (port DI4 (direction INPUT)) - (port DI5 (direction INPUT)) - (port DI6 (direction INPUT)) - (port DI7 (direction INPUT)) - (port DI8 (direction INPUT)) - (port DI9 (direction INPUT)) - (port DI10 (direction INPUT)) - (port DI11 (direction INPUT)) - (port DI12 (direction INPUT)) - (port DI13 (direction INPUT)) - (port DI14 (direction INPUT)) - (port DI15 (direction INPUT)) - (port DI16 (direction INPUT)) - (port DI17 (direction INPUT)) - (port DI18 (direction INPUT)) - (port DI19 (direction INPUT)) - (port DI20 (direction INPUT)) - (port DI21 (direction INPUT)) - (port DI22 (direction INPUT)) - (port DI23 (direction INPUT)) - (port DI24 (direction INPUT)) - (port DI25 (direction INPUT)) - (port DI26 (direction INPUT)) - (port DI27 (direction INPUT)) - (port DI28 (direction INPUT)) - (port DI29 (direction INPUT)) - (port DI30 (direction INPUT)) - (port DI31 (direction INPUT)) - (port DI32 (direction INPUT)) - (port DI33 (direction INPUT)) - (port DI34 (direction INPUT)) - (port DI35 (direction INPUT)) - (port ADW0 (direction INPUT)) - (port ADW1 (direction INPUT)) - (port ADW2 (direction INPUT)) - (port ADW3 (direction INPUT)) - (port ADW4 (direction INPUT)) - (port ADW5 (direction INPUT)) - (port ADW6 (direction INPUT)) - (port ADW7 (direction INPUT)) - (port ADW8 (direction INPUT)) - (port BE0 (direction INPUT)) - (port BE1 (direction INPUT)) - (port BE2 (direction INPUT)) - (port BE3 (direction INPUT)) - (port CEW (direction INPUT)) - (port CLKW (direction INPUT)) - (port CSW0 (direction INPUT)) - (port CSW1 (direction INPUT)) - (port CSW2 (direction INPUT)) - (port ADR0 (direction INPUT)) - (port ADR1 (direction INPUT)) - (port ADR2 (direction INPUT)) - (port ADR3 (direction INPUT)) - (port ADR4 (direction INPUT)) - (port ADR5 (direction INPUT)) - (port ADR6 (direction INPUT)) - (port ADR7 (direction INPUT)) - (port ADR8 (direction INPUT)) - (port ADR9 (direction INPUT)) - (port ADR10 (direction INPUT)) - (port ADR11 (direction INPUT)) - (port ADR12 (direction INPUT)) - (port ADR13 (direction INPUT)) - (port CER (direction INPUT)) - (port CLKR (direction INPUT)) - (port CSR0 (direction INPUT)) - (port CSR1 (direction INPUT)) - (port CSR2 (direction INPUT)) - (port RST (direction INPUT)) - (port OCER (direction INPUT)) - (port DO0 (direction OUTPUT)) - (port DO1 (direction OUTPUT)) - (port DO2 (direction OUTPUT)) - (port DO3 (direction OUTPUT)) - (port DO4 (direction OUTPUT)) - (port DO5 (direction OUTPUT)) - (port DO6 (direction OUTPUT)) - (port DO7 (direction OUTPUT)) - (port DO8 (direction OUTPUT)) - (port DO9 (direction OUTPUT)) - (port DO10 (direction OUTPUT)) - (port DO11 (direction OUTPUT)) - (port DO12 (direction OUTPUT)) - (port DO13 (direction OUTPUT)) - (port DO14 (direction OUTPUT)) - (port DO15 (direction OUTPUT)) - (port DO16 (direction OUTPUT)) - (port DO17 (direction OUTPUT)) - (port DO18 (direction OUTPUT)) - (port DO19 (direction OUTPUT)) - (port DO20 (direction OUTPUT)) - (port DO21 (direction OUTPUT)) - (port DO22 (direction OUTPUT)) - (port DO23 (direction OUTPUT)) - (port DO24 (direction OUTPUT)) - (port DO25 (direction OUTPUT)) - (port DO26 (direction OUTPUT)) - (port DO27 (direction OUTPUT)) - (port DO28 (direction OUTPUT)) - (port DO29 (direction OUTPUT)) - (port DO30 (direction OUTPUT)) - (port DO31 (direction OUTPUT)) - (port DO32 (direction OUTPUT)) - (port DO33 (direction OUTPUT)) - (port DO34 (direction OUTPUT)) - (port DO35 (direction OUTPUT)) - ) - (property INITVAL_3F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_3E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_3D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_3C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_3B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_3A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_39 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_38 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_37 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_36 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_35 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_34 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_33 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_32 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_31 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_30 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_2A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_29 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_28 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_27 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_26 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_25 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_24 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_23 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_22 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_21 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_20 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_1A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_19 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_18 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_17 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_16 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_15 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_14 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_13 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_12 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_11 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_10 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0F (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0E (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0D (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0C (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0B (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_0A (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_09 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_08 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_07 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_06 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_05 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_04 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_03 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_02 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_01 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property INITVAL_00 (string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000")) - (property GSR (string "DISABLED")) - (property REGMODE (string "NOREG")) - (property DATA_WIDTH_R (integer 36)) - (property DATA_WIDTH_W (integer 36)) - ) - ) - (cell ROM16X1A (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port AD0 (direction INPUT)) - (port AD1 (direction INPUT)) - (port AD2 (direction INPUT)) - (port AD3 (direction INPUT)) - (port DO0 (direction OUTPUT)) - ) - ) - ) - (cell CCU2C (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A0 (direction INPUT)) - (port B0 (direction INPUT)) - (port C0 (direction INPUT)) - (port D0 (direction INPUT)) - (port A1 (direction INPUT)) - (port B1 (direction INPUT)) - (port C1 (direction INPUT)) - (port D1 (direction INPUT)) - (port CIN (direction INPUT)) - (port COUT (direction OUTPUT)) - (port S0 (direction OUTPUT)) - (port S1 (direction OUTPUT)) - ) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0000")) - (property INIT0 (string "0000")) - ) - ) - (cell OBZ (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port T (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell OB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell IB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell FD1S3JX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3BX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell IFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3BX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell XOR2 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell OR2 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell AND2 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell ORCALUT4 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port C (direction INPUT)) - (port D (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell GSR (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port GSR (direction INPUT)) - ) - ) - ) - (cell INV (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VHI (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VLO (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - ) - (library work - (edifLevel 0) - (technology (numberDefinition )) - (cell output_decoder8_0_1 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port reset_dl_0 (direction INPUT)) - (port (array (rename tdc_out_neg "tdc_out_neg[7:0]") 8) (direction INPUT)) - (port (array (rename decoder_out_neg "decoder_out_neg[2:0]") 3) (direction OUTPUT)) - (port N_11_i (direction OUTPUT)) - (port buf_positive_ready (direction INPUT)) - (port decoder_valid_neg (direction OUTPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+A)))")) - ) - (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D+(!C+(!B+A)))")) - ) - (instance valid_RNI97O31 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) - ) - (instance (rename in_synced_RNIT1GT_7 "in_synced_RNIT1GT[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance un1_out_internal35_1_0_o5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance (rename out_internal_2_1_0__m11_i_0 "out_internal_2_1_0_.m11_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B !A)+D (!C+(B !A)))")) - ) - (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance (rename out_internal_2_1_0__m11_i_m3 "out_internal_2_1_0_.m11_i_m3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (!B+A))")) - ) - (instance (rename out_internal_2_1_0__m15_i_1 "out_internal_2_1_0_.m15_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C !A))")) - ) - (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(!B+A))")) - ) - (instance un1_out_internal31_1_i_0_o5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !A+C (!B+!A))+D (!C+(!B+!A)))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net un1_out_internal35_1_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef out_internal_2)) - (portRef CK (instanceRef out_2)) - (portRef CK (instanceRef out_internal_1)) - (portRef CK (instanceRef out_1)) - (portRef CK (instanceRef out_internal_0)) - (portRef CK (instanceRef out_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef in_synced_RNIT1GT_7)) - (portRef PD (instanceRef out_internal_2)) - (portRef PD (instanceRef out_internal_1)) - (portRef PD (instanceRef out_internal_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - )) - (net decoder_valid_neg (joined - (portRef Q (instanceRef valid)) - (portRef B (instanceRef valid_RNI97O31)) - (portRef decoder_valid_neg) - )) - (net (rename out_internal_0 "out_internal[0]") (joined - (portRef Q (instanceRef out_internal_0)) - (portRef D (instanceRef out_0)) - )) - (net (rename decoder_out_neg_0 "decoder_out_neg[0]") (joined - (portRef Q (instanceRef out_0)) - (portRef (member decoder_out_neg 2)) - )) - (net m11_i_1 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i)) - (portRef D (instanceRef out_internal_0)) - )) - (net (rename out_internal_1 "out_internal[1]") (joined - (portRef Q (instanceRef out_internal_1)) - (portRef D (instanceRef out_1)) - )) - (net (rename decoder_out_neg_1 "decoder_out_neg[1]") (joined - (portRef Q (instanceRef out_1)) - (portRef (member decoder_out_neg 1)) - )) - (net m15_i_1 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i)) - (portRef D (instanceRef out_internal_1)) - )) - (net (rename out_internal_2 "out_internal[2]") (joined - (portRef Q (instanceRef out_internal_2)) - (portRef D (instanceRef out_2)) - )) - (net (rename decoder_out_neg_2 "decoder_out_neg[2]") (joined - (portRef Q (instanceRef out_2)) - (portRef (member decoder_out_neg 0)) - )) - (net N_5 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0)) - (portRef D (instanceRef out_internal_2)) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef D (instanceRef un1_out_internal31_1_i_0_o5)) - (portRef A (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_0)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef C (instanceRef un1_out_internal31_1_i_0_o5)) - (portRef A (instanceRef out_internal_2_1_0__m15_i_1)) - (portRef B (instanceRef un1_out_internal35_1_0_m3)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_0)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef B (instanceRef un1_out_internal31_1_i_0_o5)) - (portRef B (instanceRef out_internal_2_1_0__m15_i_1)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_m3)) - (portRef C (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef un1_out_internal35_1_0_o5)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef C (instanceRef out_internal_2_1_0__m15_i_1)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_m3)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - (portRef B (instanceRef un1_out_internal35_1_0_o5)) - (portRef B (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef D (instanceRef out_internal_2_1_0__m15_i_1)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_0)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef un1_out_internal35_1_0_o5)) - (portRef C (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef B (instanceRef out_internal_2_1_0__m15_i)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_m3)) - (portRef D (instanceRef out_internal_2_1_0__m11_i_0)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef un1_out_internal35_1_0_o5)) - (portRef D (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef A (instanceRef un1_out_internal31_1_i_0_o5)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef in_synced_RNIT1GT_7)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef in_synced_RNIT1GT_7)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined - (portRef (member tdc_out_neg 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined - (portRef (member tdc_out_neg 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined - (portRef (member tdc_out_neg 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined - (portRef (member tdc_out_neg 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined - (portRef (member tdc_out_neg 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined - (portRef (member tdc_out_neg 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined - (portRef (member tdc_out_neg 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined - (portRef (member tdc_out_neg 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net un1_out_internal35_1_0_m3 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net un1_out_internal35_1_0_o5 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_o5)) - (portRef A (instanceRef out_internal_2_1_0__m11_i)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net m11_i_m3 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_m3)) - (portRef B (instanceRef out_internal_2_1_0__m11_i)) - )) - (net un1_out_internal31_1_i_0_o5 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0_o5)) - (portRef A (instanceRef out_internal_2_1_0__m15_i)) - (portRef A (instanceRef un1_out_internal31_1_i_0)) - (portRef C (instanceRef out_internal_2_1_0__m11_i)) - )) - (net m11_i_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_0)) - (portRef D (instanceRef out_internal_2_1_0__m11_i)) - )) - (net buf_positive_ready (joined - (portRef buf_positive_ready) - (portRef A (instanceRef valid_RNI97O31)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef C (instanceRef valid_RNI97O31)) - )) - (net N_11_i (joined - (portRef Z (instanceRef valid_RNI97O31)) - (portRef N_11_i) - )) - (net m15_i_1_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i_1)) - (portRef C (instanceRef out_internal_2_1_0__m15_i)) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell output_decoder8_0_0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port reset_dl_0 (direction INPUT)) - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT)) - (port (array (rename decoder_out "decoder_out[2:0]") 3) (direction OUTPUT)) - (port N_251_i (direction OUTPUT)) - (port decoder_valid (direction OUTPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B A)))")) - ) - (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(!B+!A)))")) - ) - (instance (rename out_internal_2_1_0__m15_i_3 "out_internal_2_1_0_.m15_i_3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B+!A)))")) - ) - (instance (rename in_synced_RNIB4EQ_7 "in_synced_RNIB4EQ[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance valid_RNI8UMR (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance un1_out_internal35_1_0_o7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance (rename out_internal_2_1_0__m11_i_1 "out_internal_2_1_0_.m11_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B !A)+D (!C+(B !A)))")) - ) - (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance un1_out_internal31_1_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename out_internal_2_1_0__m15_i_0 "out_internal_2_1_0_.m15_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename out_internal_2_1_0__m11_i_1_0 "out_internal_2_1_0_.m11_i_1_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B A+B !A)))")) - ) - (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+A)))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net un1_out_internal35_1_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef out_internal_2)) - (portRef CK (instanceRef out_2)) - (portRef CK (instanceRef out_internal_1)) - (portRef CK (instanceRef out_1)) - (portRef CK (instanceRef out_0)) - (portRef CK (instanceRef out_internal_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef in_synced_RNIB4EQ_7)) - (portRef PD (instanceRef out_internal_2)) - (portRef PD (instanceRef out_internal_1)) - (portRef PD (instanceRef out_internal_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - )) - (net decoder_valid (joined - (portRef Q (instanceRef valid)) - (portRef A (instanceRef valid_RNI8UMR)) - (portRef decoder_valid) - )) - (net m11_i_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i)) - (portRef D (instanceRef out_internal_0)) - )) - (net (rename out_internal_0 "out_internal[0]") (joined - (portRef Q (instanceRef out_internal_0)) - (portRef D (instanceRef out_0)) - )) - (net (rename decoder_out_0 "decoder_out[0]") (joined - (portRef Q (instanceRef out_0)) - (portRef (member decoder_out 2)) - )) - (net (rename out_internal_1 "out_internal[1]") (joined - (portRef Q (instanceRef out_internal_1)) - (portRef D (instanceRef out_1)) - )) - (net (rename decoder_out_1 "decoder_out[1]") (joined - (portRef Q (instanceRef out_1)) - (portRef (member decoder_out 1)) - )) - (net m15_i_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i)) - (portRef D (instanceRef out_internal_1)) - )) - (net (rename out_internal_2 "out_internal[2]") (joined - (portRef Q (instanceRef out_internal_2)) - (portRef D (instanceRef out_2)) - )) - (net (rename decoder_out_2 "decoder_out[2]") (joined - (portRef Q (instanceRef out_2)) - (portRef (member decoder_out 0)) - )) - (net un1_out_internal31_1_i_0_0 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0)) - (portRef D (instanceRef out_internal_2)) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef A (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m15_i)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef B (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m15_i_3)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef C (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef A (instanceRef un1_out_internal35_1_0_o7)) - (portRef B (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef B (instanceRef out_internal_2_1_0__m15_i)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef A (instanceRef un1_out_internal31_1_i_0_1)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - (portRef B (instanceRef un1_out_internal35_1_0_o7)) - (portRef C (instanceRef out_internal_2_1_0__m15_i_3)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef un1_out_internal35_1_0_o7)) - (portRef D (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef B (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef D (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef A (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef B (instanceRef un1_out_internal31_1_i_0_1)) - (portRef D (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef un1_out_internal35_1_0_o7)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef B (instanceRef out_internal_2_1_0__m11_i)) - (portRef B (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef in_synced_RNIB4EQ_7)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef in_synced_RNIB4EQ_7)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net N_268 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef un1_out_internal31_1_i_0)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net N_269 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_o7)) - (portRef A (instanceRef out_internal_2_1_0__m11_i)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net m15_i_0_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef C (instanceRef out_internal_2_1_0__m15_i)) - )) - (net m15_i_3 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef D (instanceRef out_internal_2_1_0__m15_i)) - )) - (net un1_out_internal31_1_i_0_1 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0_1)) - (portRef D (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef B (instanceRef valid_RNI8UMR)) - )) - (net N_251_i (joined - (portRef Z (instanceRef valid_RNI8UMR)) - (portRef N_251_i) - )) - (net m11_i_1 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef C (instanceRef out_internal_2_1_0__m11_i)) - )) - (net m11_i_1_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef D (instanceRef out_internal_2_1_0__m11_i)) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell tdc4ddr_short_1 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out_neg "tdc_out_neg[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port trig_gate_neg (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out_neg 4)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out_neg 0)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net trig_gate_neg (joined - (portRef trig_gate_neg) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out_neg 5)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out_neg 1)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out_neg 6)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out_neg 2)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out_neg 7)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out_neg 3)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell tdc4ddr_short_0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port hades_trig_c_i (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out 4)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out 0)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net hades_trig_c_i (joined - (portRef hades_trig_c_i) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out 5)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out 1)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out 6)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out 2)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out 7)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out 3)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell trig_inv (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port hades_trig_c_i (direction INPUT)) - (port trig_gate_neg (direction OUTPUT)) - ) - (contents - (instance out_RNO (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (net in_1 (joined - (portRef A (instanceRef out_RNO)) - (portRef hades_trig_c_i) - )) - (net (rename out "trig_gate_neg") (joined - (portRef trig_gate_neg) - (portRef Z (instanceRef out_RNO)) - )) - ) - (property orig_inst_of (string "trig_inv")) - ) - ) - (cell output_decoder8_0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT)) - (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT)) - (port pll_clks_0 (direction INPUT)) - (port reset_dl_0 (direction INPUT)) - (port un1_reset_0_a2_2_0 (direction OUTPUT)) - (port G_25_0_a3_5_0 (direction INPUT)) - (port G_25_0_a3_4_0 (direction INPUT)) - (port decoder_valid (direction OUTPUT)) - (port CN (direction OUTPUT)) - (port valid_fast_RNI999V_1z (direction OUTPUT)) - (port hades_discard_c (direction INPUT)) - (port valid_fast_1z (direction OUTPUT)) - (port offset_1_sqmuxa_i_0 (direction INPUT)) - ) - (contents - (instance valid_fast_RNI999V (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B+A)+C A)+D (B+A))")) - ) - (instance (rename in_synced_7__CN "in_synced_7_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid_fast (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_0 "out[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_0 "out_internal[0]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_1 "out[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename out_internal_1 "out_internal[1]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_internal_2 "out_internal[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename out_2 "out[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename out_internal_2_1_0__m15_i "out_internal_2_1_0_.m15_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B A)))")) - ) - (instance un1_out_internal31_1_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(!B+!A)))")) - ) - (instance (rename out_internal_2_1_0__m15_i_3 "out_internal_2_1_0_.m15_i_3") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B+!A)))")) - ) - (instance (rename in_synced_RNI3HPF_7 "in_synced_RNI3HPF[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance un1_out_internal35_1_0_o7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(!B A))+D (!B A))")) - ) - (instance (rename out_internal_2_1_0__m11_i_1 "out_internal_2_1_0_.m11_i_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B !A)+D (!C+(B !A)))")) - ) - (instance un1_out_internal35_1_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance un1_out_internal31_1_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename out_internal_2_1_0__m15_i_0 "out_internal_2_1_0_.m15_i_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance (rename out_internal_2_1_0__m11_i_1_0 "out_internal_2_1_0_.m11_i_1_0") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+A))+D (!C (B+A)+C (!B A+B !A)))")) - ) - (instance (rename out_internal_2_1_0__m11_i "out_internal_2_1_0_.m11_i") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+A)))")) - ) - (instance valid_fast_RNI5DQ71 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (B A)))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef D (instanceRef valid_fast_RNI5DQ71)) - (portRef A (instanceRef valid_fast_RNI999V)) - )) - (net offset_1_sqmuxa_i_0 (joined - (portRef offset_1_sqmuxa_i_0) - (portRef B (instanceRef valid_fast_RNI999V)) - )) - (net (rename valid_fast_1z "valid_fast") (joined - (portRef Q (instanceRef valid_fast)) - (portRef C (instanceRef valid_fast_RNI5DQ71)) - (portRef C (instanceRef valid_fast_RNI999V)) - (portRef valid_fast_1z) - )) - (net hades_discard_c (joined - (portRef hades_discard_c) - (portRef D (instanceRef valid_fast_RNI999V)) - )) - (net (rename valid_fast_RNI999V_1z "valid_fast_RNI999V") (joined - (portRef Z (instanceRef valid_fast_RNI999V)) - (portRef valid_fast_RNI999V_1z) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef A (instanceRef in_synced_7__CN)) - )) - (net CN (joined - (portRef Z (instanceRef in_synced_7__CN)) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef out_2)) - (portRef CK (instanceRef out_internal_2)) - (portRef CK (instanceRef out_internal_1)) - (portRef CK (instanceRef out_1)) - (portRef CK (instanceRef out_internal_0)) - (portRef CK (instanceRef out_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_fast)) - (portRef CK (instanceRef valid_internal)) - (portRef CN) - )) - (net un1_out_internal35_1_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef in_synced_RNI3HPF_7)) - (portRef PD (instanceRef out_internal_2)) - (portRef PD (instanceRef out_internal_1)) - (portRef PD (instanceRef out_internal_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - (portRef D (instanceRef valid_fast)) - )) - (net decoder_valid (joined - (portRef Q (instanceRef valid)) - (portRef decoder_valid) - )) - (net (rename out_internal_0 "out_internal[0]") (joined - (portRef Q (instanceRef out_internal_0)) - (portRef D (instanceRef out_0)) - )) - (net (rename offset_5_0 "offset_5[0]") (joined - (portRef Q (instanceRef out_0)) - (portRef (member offset_5 2)) - )) - (net m11_i (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i)) - (portRef D (instanceRef out_internal_0)) - )) - (net (rename out_internal_1 "out_internal[1]") (joined - (portRef Q (instanceRef out_internal_1)) - (portRef D (instanceRef out_1)) - )) - (net (rename offset_5_1 "offset_5[1]") (joined - (portRef Q (instanceRef out_1)) - (portRef (member offset_5 1)) - )) - (net m15_i (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i)) - (portRef D (instanceRef out_internal_1)) - )) - (net un1_out_internal31_1_i_0 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0)) - (portRef D (instanceRef out_internal_2)) - )) - (net (rename out_internal_2 "out_internal[2]") (joined - (portRef Q (instanceRef out_internal_2)) - (portRef D (instanceRef out_2)) - )) - (net (rename offset_5_2 "offset_5[2]") (joined - (portRef Q (instanceRef out_2)) - (portRef (member offset_5 0)) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef A (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m15_i)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef B (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m15_i_3)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef C (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef A (instanceRef un1_out_internal35_1_0_o7)) - (portRef B (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef B (instanceRef out_internal_2_1_0__m15_i)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef A (instanceRef un1_out_internal31_1_i_0_1)) - (portRef B (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - (portRef B (instanceRef un1_out_internal35_1_0_o7)) - (portRef C (instanceRef out_internal_2_1_0__m15_i_3)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef C (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef un1_out_internal35_1_0_o7)) - (portRef D (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef B (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef D (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef A (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef B (instanceRef un1_out_internal31_1_i_0_1)) - (portRef D (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef un1_out_internal35_1_0_o7)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef B (instanceRef out_internal_2_1_0__m11_i)) - (portRef B (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef un1_out_internal31_1_i_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef in_synced_RNI3HPF_7)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef in_synced_RNI3HPF_7)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net N_290 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m3)) - (portRef A (instanceRef un1_out_internal31_1_i_0)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net N_291 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_o7)) - (portRef A (instanceRef out_internal_2_1_0__m11_i)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net m15_i_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i_0)) - (portRef C (instanceRef out_internal_2_1_0__m15_i)) - )) - (net m15_i_3 (joined - (portRef Z (instanceRef out_internal_2_1_0__m15_i_3)) - (portRef D (instanceRef out_internal_2_1_0__m15_i)) - )) - (net un1_out_internal31_1_i_0_1 (joined - (portRef Z (instanceRef un1_out_internal31_1_i_0_1)) - (portRef D (instanceRef un1_out_internal31_1_i_0)) - )) - (net m11_i_1 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_1)) - (portRef C (instanceRef out_internal_2_1_0__m11_i)) - )) - (net m11_i_1_0 (joined - (portRef Z (instanceRef out_internal_2_1_0__m11_i_1_0)) - (portRef D (instanceRef out_internal_2_1_0__m11_i)) - )) - (net G_25_0_a3_4_0 (joined - (portRef G_25_0_a3_4_0) - (portRef A (instanceRef valid_fast_RNI5DQ71)) - )) - (net G_25_0_a3_5_0 (joined - (portRef G_25_0_a3_5_0) - (portRef B (instanceRef valid_fast_RNI5DQ71)) - )) - (net un1_reset_0_a2_2_0 (joined - (portRef Z (instanceRef valid_fast_RNI5DQ71)) - (portRef un1_reset_0_a2_2_0) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell tdc4ddr_short (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port hades_lvl1_c_i (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction OUTPUT)) - (port CN_0 (direction OUTPUT)) - (port CN (direction OUTPUT)) - ) - (contents - (instance (rename genblk1_2__out_buffered1_6__CN "genblk1[2].out_buffered1_6_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename genblk1_1__out_buffered1_5__CN "genblk1[1].out_buffered1_5_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename genblk1_0__out_buffered1_4__CN "genblk1[0].out_buffered1_4_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - (portRef A (instanceRef genblk1_2__out_buffered1_6__CN)) - )) - (net CN (joined - (portRef Z (instanceRef genblk1_2__out_buffered1_6__CN)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - (portRef CN) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - (portRef A (instanceRef genblk1_1__out_buffered1_5__CN)) - )) - (net CN_0 (joined - (portRef Z (instanceRef genblk1_1__out_buffered1_5__CN)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - (portRef CN_0) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - (portRef A (instanceRef genblk1_0__out_buffered1_4__CN)) - )) - (net CN_1 (joined - (portRef Z (instanceRef genblk1_0__out_buffered1_4__CN)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - (portRef CN_1) - )) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out 4)) - )) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out 0)) - )) - (net hades_lvl1_c_i (joined - (portRef hades_lvl1_c_i) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out 5)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out 1)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out 6)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out 2)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out 7)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out 3)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell fifo32dc_1 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port pll_clks_0 (direction INPUT)) - (port fifo_in_data_0 (direction INPUT)) - (port fifo_empty_0 (direction OUTPUT)) - (port fifo_read_0 (direction INPUT)) - (port fifo_wren (direction INPUT)) - ) - (contents - (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT))) - ) - (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0410")) - ) - (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x1004")) - ) - (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0140")) - ) - (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x4001")) - ) - (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT))) - (property MEM_LPC_FILE (string "fifo32dc.lpc")) - (property MEM_INIT_FILE (string "")) - (property DATA_WIDTH_W (integer 36)) - (property DATA_WIDTH_R (integer 36)) - (property REGMODE (string "NOREG")) - (property RESETMODE (string "SYNC")) - (property GSR (string "ENABLED")) - (property CSDECODE_W (string "0b001")) - (property CSDECODE_R (string "0b000")) - (property ASYNC_RESET_RELEASE (string "SYNC")) - (property INIT_DATA (string "STATIC")) - ) - (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net fifo_wren (joined - (portRef fifo_wren) - (portRef A (instanceRef AND2_t20)) - )) - (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)) - )) - (net wren_i (joined - (portRef Z (instanceRef AND2_t20)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_101)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - )) - (net Full (joined - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)) - )) - (net (rename fifo_read_0 "fifo_read[2]") (joined - (portRef fifo_read_0) - (portRef A (instanceRef AND2_t19)) - )) - (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)) - )) - (net rden_i (joined - (portRef Z (instanceRef AND2_t19)) - (portRef B1 (instanceRef empty_cmp_ci_a)) - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef SP (instanceRef FF_42)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_71)) - (portRef OCER (instanceRef pdp_ram_0_0_0)) - (portRef CER (instanceRef pdp_ram_0_0_0)) - )) - (net (rename fifo_empty_0 "fifo_empty[2]") (joined - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)) - (portRef fifo_empty_0) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef B1 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A0 (instanceRef a1)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef CD (instanceRef FF_0)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_100)) - (portRef PD (instanceRef FF_101)) - (portRef RST (instanceRef pdp_ram_0_0_0)) - (portRef CSR2 (instanceRef pdp_ram_0_0_0)) - (portRef CSR1 (instanceRef pdp_ram_0_0_0)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef ADR4 (instanceRef pdp_ram_0_0_0)) - (portRef ADR3 (instanceRef pdp_ram_0_0_0)) - (portRef ADR2 (instanceRef pdp_ram_0_0_0)) - (portRef ADR1 (instanceRef pdp_ram_0_0_0)) - (portRef ADR0 (instanceRef pdp_ram_0_0_0)) - (portRef CSW2 (instanceRef pdp_ram_0_0_0)) - (portRef CSW1 (instanceRef pdp_ram_0_0_0)) - (portRef DI35 (instanceRef pdp_ram_0_0_0)) - (portRef DI34 (instanceRef pdp_ram_0_0_0)) - (portRef DI33 (instanceRef pdp_ram_0_0_0)) - (portRef DI32 (instanceRef pdp_ram_0_0_0)) - (portRef DI31 (instanceRef pdp_ram_0_0_0)) - (portRef DI30 (instanceRef pdp_ram_0_0_0)) - (portRef DI29 (instanceRef pdp_ram_0_0_0)) - (portRef DI28 (instanceRef pdp_ram_0_0_0)) - (portRef DI25 (instanceRef pdp_ram_0_0_0)) - (portRef DI23 (instanceRef pdp_ram_0_0_0)) - (portRef DI22 (instanceRef pdp_ram_0_0_0)) - (portRef DI21 (instanceRef pdp_ram_0_0_0)) - (portRef DI20 (instanceRef pdp_ram_0_0_0)) - (portRef DI19 (instanceRef pdp_ram_0_0_0)) - (portRef DI18 (instanceRef pdp_ram_0_0_0)) - (portRef DI17 (instanceRef pdp_ram_0_0_0)) - (portRef DI16 (instanceRef pdp_ram_0_0_0)) - (portRef DI14 (instanceRef pdp_ram_0_0_0)) - (portRef DI10 (instanceRef pdp_ram_0_0_0)) - (portRef DI8 (instanceRef pdp_ram_0_0_0)) - (portRef DI7 (instanceRef pdp_ram_0_0_0)) - (portRef DI6 (instanceRef pdp_ram_0_0_0)) - (portRef DI5 (instanceRef pdp_ram_0_0_0)) - (portRef DI4 (instanceRef pdp_ram_0_0_0)) - (portRef DI3 (instanceRef pdp_ram_0_0_0)) - (portRef DI2 (instanceRef pdp_ram_0_0_0)) - (portRef DI1 (instanceRef pdp_ram_0_0_0)) - (portRef DI0 (instanceRef pdp_ram_0_0_0)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef B (instanceRef OR2_t18)) - (portRef A (instanceRef OR2_t18)) - )) - (net rRst (joined - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_1)) - (portRef CD (instanceRef FF_2)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_70)) - (portRef PD (instanceRef FF_71)) - )) - (net wcount_0 (joined - (portRef Q (instanceRef FF_101)) - (portRef A0 (instanceRef full_cmp_0)) - (portRef A0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_81)) - (portRef A (instanceRef XOR2_t17)) - )) - (net wcount_1 (joined - (portRef Q (instanceRef FF_100)) - (portRef A1 (instanceRef full_cmp_0)) - (portRef A1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_80)) - (portRef A (instanceRef XOR2_t16)) - (portRef B (instanceRef XOR2_t17)) - )) - (net w_gdata_0 (joined - (portRef Z (instanceRef XOR2_t17)) - (portRef D (instanceRef FF_91)) - )) - (net wcount_2 (joined - (portRef Q (instanceRef FF_99)) - (portRef A0 (instanceRef full_cmp_1)) - (portRef A0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_79)) - (portRef A (instanceRef XOR2_t15)) - (portRef B (instanceRef XOR2_t16)) - )) - (net w_gdata_1 (joined - (portRef Z (instanceRef XOR2_t16)) - (portRef D (instanceRef FF_90)) - )) - (net wcount_3 (joined - (portRef Q (instanceRef FF_98)) - (portRef A1 (instanceRef full_cmp_1)) - (portRef A1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_78)) - (portRef A (instanceRef XOR2_t14)) - (portRef B (instanceRef XOR2_t15)) - )) - (net w_gdata_2 (joined - (portRef Z (instanceRef XOR2_t15)) - (portRef D (instanceRef FF_89)) - )) - (net wcount_4 (joined - (portRef Q (instanceRef FF_97)) - (portRef A0 (instanceRef full_cmp_2)) - (portRef A0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_77)) - (portRef A (instanceRef XOR2_t13)) - (portRef B (instanceRef XOR2_t14)) - )) - (net w_gdata_3 (joined - (portRef Z (instanceRef XOR2_t14)) - (portRef D (instanceRef FF_88)) - )) - (net wcount_5 (joined - (portRef Q (instanceRef FF_96)) - (portRef A1 (instanceRef full_cmp_2)) - (portRef A1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_76)) - (portRef A (instanceRef XOR2_t12)) - (portRef B (instanceRef XOR2_t13)) - )) - (net w_gdata_4 (joined - (portRef Z (instanceRef XOR2_t13)) - (portRef D (instanceRef FF_87)) - )) - (net wcount_6 (joined - (portRef Q (instanceRef FF_95)) - (portRef A0 (instanceRef full_cmp_3)) - (portRef A0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_75)) - (portRef A (instanceRef XOR2_t11)) - (portRef B (instanceRef XOR2_t12)) - )) - (net w_gdata_5 (joined - (portRef Z (instanceRef XOR2_t12)) - (portRef D (instanceRef FF_86)) - )) - (net wcount_7 (joined - (portRef Q (instanceRef FF_94)) - (portRef A1 (instanceRef full_cmp_3)) - (portRef A1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_74)) - (portRef A (instanceRef XOR2_t10)) - (portRef B (instanceRef XOR2_t11)) - )) - (net w_gdata_6 (joined - (portRef Z (instanceRef XOR2_t11)) - (portRef D (instanceRef FF_85)) - )) - (net wcount_8 (joined - (portRef Q (instanceRef FF_93)) - (portRef A0 (instanceRef full_cmp_4)) - (portRef A0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_73)) - (portRef A (instanceRef XOR2_t9)) - (portRef B (instanceRef XOR2_t10)) - )) - (net w_gdata_7 (joined - (portRef Z (instanceRef XOR2_t10)) - (portRef D (instanceRef FF_84)) - )) - (net wcount_9 (joined - (portRef Q (instanceRef FF_92)) - (portRef A1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_72)) - (portRef D (instanceRef FF_82)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef B (instanceRef XOR2_t9)) - )) - (net w_gdata_8 (joined - (portRef Z (instanceRef XOR2_t9)) - (portRef D (instanceRef FF_83)) - )) - (net rcount_0 (joined - (portRef Q (instanceRef FF_71)) - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_51)) - (portRef A (instanceRef XOR2_t8)) - )) - (net rcount_1 (joined - (portRef Q (instanceRef FF_70)) - (portRef A1 (instanceRef empty_cmp_0)) - (portRef A1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_50)) - (portRef A (instanceRef XOR2_t7)) - (portRef B (instanceRef XOR2_t8)) - )) - (net r_gdata_0 (joined - (portRef Z (instanceRef XOR2_t8)) - (portRef D (instanceRef FF_61)) - )) - (net rcount_2 (joined - (portRef Q (instanceRef FF_69)) - (portRef A0 (instanceRef empty_cmp_1)) - (portRef A0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_49)) - (portRef A (instanceRef XOR2_t6)) - (portRef B (instanceRef XOR2_t7)) - )) - (net r_gdata_1 (joined - (portRef Z (instanceRef XOR2_t7)) - (portRef D (instanceRef FF_60)) - )) - (net rcount_3 (joined - (portRef Q (instanceRef FF_68)) - (portRef A1 (instanceRef empty_cmp_1)) - (portRef A1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_48)) - (portRef A (instanceRef XOR2_t5)) - (portRef B (instanceRef XOR2_t6)) - )) - (net r_gdata_2 (joined - (portRef Z (instanceRef XOR2_t6)) - (portRef D (instanceRef FF_59)) - )) - (net rcount_4 (joined - (portRef Q (instanceRef FF_67)) - (portRef A0 (instanceRef empty_cmp_2)) - (portRef A0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_47)) - (portRef A (instanceRef XOR2_t4)) - (portRef B (instanceRef XOR2_t5)) - )) - (net r_gdata_3 (joined - (portRef Z (instanceRef XOR2_t5)) - (portRef D (instanceRef FF_58)) - )) - (net rcount_5 (joined - (portRef Q (instanceRef FF_66)) - (portRef A1 (instanceRef empty_cmp_2)) - (portRef A1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_46)) - (portRef A (instanceRef XOR2_t3)) - (portRef B (instanceRef XOR2_t4)) - )) - (net r_gdata_4 (joined - (portRef Z (instanceRef XOR2_t4)) - (portRef D (instanceRef FF_57)) - )) - (net rcount_6 (joined - (portRef Q (instanceRef FF_65)) - (portRef A0 (instanceRef empty_cmp_3)) - (portRef A0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_45)) - (portRef A (instanceRef XOR2_t2)) - (portRef B (instanceRef XOR2_t3)) - )) - (net r_gdata_5 (joined - (portRef Z (instanceRef XOR2_t3)) - (portRef D (instanceRef FF_56)) - )) - (net rcount_7 (joined - (portRef Q (instanceRef FF_64)) - (portRef A1 (instanceRef empty_cmp_3)) - (portRef A1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_44)) - (portRef A (instanceRef XOR2_t1)) - (portRef B (instanceRef XOR2_t2)) - )) - (net r_gdata_6 (joined - (portRef Z (instanceRef XOR2_t2)) - (portRef D (instanceRef FF_55)) - )) - (net rcount_8 (joined - (portRef Q (instanceRef FF_63)) - (portRef A0 (instanceRef empty_cmp_4)) - (portRef A0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_43)) - (portRef A (instanceRef XOR2_t0)) - (portRef B (instanceRef XOR2_t1)) - )) - (net r_gdata_7 (joined - (portRef Z (instanceRef XOR2_t1)) - (portRef D (instanceRef FF_54)) - )) - (net rcount_9 (joined - (portRef Q (instanceRef FF_62)) - (portRef A1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_42)) - (portRef D (instanceRef FF_52)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef B (instanceRef XOR2_t0)) - )) - (net r_gdata_8 (joined - (portRef Z (instanceRef XOR2_t0)) - (portRef D (instanceRef FF_53)) - )) - (net w_gcount_r29 (joined - (portRef Q (instanceRef FF_12)) - (portRef AD1 (instanceRef LUT4_2)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_23)) - )) - (net w_gcount_r28 (joined - (portRef Q (instanceRef FF_13)) - (portRef AD2 (instanceRef LUT4_20)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_23)) - )) - (net w_gcount_r27 (joined - (portRef Q (instanceRef FF_14)) - (portRef AD1 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_23)) - )) - (net w_gcount_r26 (joined - (portRef Q (instanceRef FF_15)) - (portRef AD1 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_23)) - )) - (net w_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_23)) - (portRef B0 (instanceRef empty_cmp_3)) - (portRef AD3 (instanceRef LUT4_14)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_17)) - )) - (net w_gcount_r25 (joined - (portRef Q (instanceRef FF_16)) - (portRef AD1 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD0 (instanceRef LUT4_22)) - )) - (net w_gcount_r24 (joined - (portRef Q (instanceRef FF_17)) - (portRef AD2 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_22)) - )) - (net w_gcount_r23 (joined - (portRef Q (instanceRef FF_18)) - (portRef AD3 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_22)) - )) - (net w_gcount_r22 (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)) - )) - (net w_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_14)) - (portRef AD2 (instanceRef LUT4_15)) - (portRef AD2 (instanceRef LUT4_16)) - )) - (net wcount_r8 (joined - (portRef DO0 (instanceRef LUT4_21)) - (portRef B0 (instanceRef empty_cmp_4)) - (portRef AD0 (instanceRef LUT4_19)) - )) - (net wcount_r7 (joined - (portRef DO0 (instanceRef LUT4_20)) - (portRef B1 (instanceRef empty_cmp_3)) - (portRef AD0 (instanceRef LUT4_18)) - )) - (net wcount_r5 (joined - (portRef DO0 (instanceRef LUT4_19)) - (portRef B1 (instanceRef empty_cmp_2)) - )) - (net wcount_r4 (joined - (portRef DO0 (instanceRef LUT4_18)) - (portRef B0 (instanceRef empty_cmp_2)) - )) - (net wcount_r3 (joined - (portRef DO0 (instanceRef LUT4_17)) - (portRef B1 (instanceRef empty_cmp_1)) - )) - (net wcount_r2 (joined - (portRef DO0 (instanceRef LUT4_16)) - (portRef B0 (instanceRef empty_cmp_1)) - )) - (net w_gcount_r21 (joined - (portRef Q (instanceRef FF_20)) - (portRef AD0 (instanceRef LUT4_14)) - (portRef AD1 (instanceRef LUT4_15)) - )) - (net wcount_r1 (joined - (portRef DO0 (instanceRef LUT4_15)) - (portRef B1 (instanceRef empty_cmp_0)) - )) - (net w_gcount_r20 (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)) - )) - (net wcount_r0 (joined - (portRef DO0 (instanceRef LUT4_14)) - (portRef B0 (instanceRef empty_cmp_0)) - )) - (net r_gcount_w29 (joined - (portRef Q (instanceRef FF_2)) - (portRef AD1 (instanceRef LUT4_0)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_13)) - )) - (net r_gcount_w28 (joined - (portRef Q (instanceRef FF_3)) - (portRef AD2 (instanceRef LUT4_10)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_13)) - )) - (net r_gcount_w27 (joined - (portRef Q (instanceRef FF_4)) - (portRef AD1 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_13)) - )) - (net r_gcount_w26 (joined - (portRef Q (instanceRef FF_5)) - (portRef AD1 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_13)) - )) - (net r_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_13)) - (portRef B0 (instanceRef full_cmp_3)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_7)) - )) - (net r_gcount_w25 (joined - (portRef Q (instanceRef FF_6)) - (portRef AD1 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_12)) - )) - (net r_gcount_w24 (joined - (portRef Q (instanceRef FF_7)) - (portRef AD2 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_12)) - )) - (net r_gcount_w23 (joined - (portRef Q (instanceRef FF_8)) - (portRef AD3 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_12)) - )) - (net r_gcount_w22 (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)) - )) - (net r_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_4)) - (portRef AD2 (instanceRef LUT4_5)) - (portRef AD2 (instanceRef LUT4_6)) - )) - (net rcount_w8 (joined - (portRef DO0 (instanceRef LUT4_11)) - (portRef B0 (instanceRef full_cmp_4)) - (portRef AD0 (instanceRef LUT4_9)) - )) - (net rcount_w7 (joined - (portRef DO0 (instanceRef LUT4_10)) - (portRef B1 (instanceRef full_cmp_3)) - (portRef AD0 (instanceRef LUT4_8)) - )) - (net rcount_w5 (joined - (portRef DO0 (instanceRef LUT4_9)) - (portRef B1 (instanceRef full_cmp_2)) - )) - (net rcount_w4 (joined - (portRef DO0 (instanceRef LUT4_8)) - (portRef B0 (instanceRef full_cmp_2)) - )) - (net rcount_w3 (joined - (portRef DO0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef full_cmp_1)) - )) - (net rcount_w2 (joined - (portRef DO0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef full_cmp_1)) - )) - (net r_gcount_w21 (joined - (portRef Q (instanceRef FF_10)) - (portRef AD0 (instanceRef LUT4_4)) - (portRef AD1 (instanceRef LUT4_5)) - )) - (net rcount_w1 (joined - (portRef DO0 (instanceRef LUT4_5)) - (portRef B1 (instanceRef full_cmp_0)) - )) - (net r_gcount_w20 (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)) - )) - (net rcount_w0 (joined - (portRef DO0 (instanceRef LUT4_4)) - (portRef B0 (instanceRef full_cmp_0)) - )) - (net rptr_9 (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_2)) - (portRef AD3 (instanceRef LUT4_3)) - )) - (net empty_cmp_set (joined - (portRef DO0 (instanceRef LUT4_3)) - (portRef A1 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_2)) - (portRef B1 (instanceRef empty_cmp_4)) - )) - (net wptr_9 (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_0)) - (portRef AD3 (instanceRef LUT4_1)) - )) - (net full_cmp_set (joined - (portRef DO0 (instanceRef LUT4_1)) - (portRef A1 (instanceRef full_cmp_4)) - )) - (net full_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_0)) - (portRef B1 (instanceRef full_cmp_4)) - )) - (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined - (portRef fifo_in_data_0) - (portRef DI27 (instanceRef pdp_ram_0_0_0)) - (portRef DI26 (instanceRef pdp_ram_0_0_0)) - (portRef DI24 (instanceRef pdp_ram_0_0_0)) - (portRef DI15 (instanceRef pdp_ram_0_0_0)) - (portRef DI13 (instanceRef pdp_ram_0_0_0)) - (portRef DI12 (instanceRef pdp_ram_0_0_0)) - (portRef DI11 (instanceRef pdp_ram_0_0_0)) - (portRef DI9 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_0 (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_1 (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_2 (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_3 (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_4 (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_5 (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_6 (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_7 (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_8 (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef a1)) - (portRef C1 (instanceRef a1)) - (portRef D0 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef a0)) - (portRef C1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef CSW0 (instanceRef pdp_ram_0_0_0)) - (portRef BE3 (instanceRef pdp_ram_0_0_0)) - (portRef BE2 (instanceRef pdp_ram_0_0_0)) - (portRef BE1 (instanceRef pdp_ram_0_0_0)) - (portRef BE0 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef CK (instanceRef FF_0)) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_71)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_101)) - (portRef CLKR (instanceRef pdp_ram_0_0_0)) - (portRef CLKW (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_0 (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_1 (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_2 (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_3 (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_4 (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_5 (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_6 (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_7 (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_8 (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef DO0 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef DO1 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef DO2 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef DO3 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef DO4 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef DO5 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename Q_1_24 "Q_1[24]") (joined - (portRef DO6 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_25 "Q_1[25]") (joined - (portRef DO7 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_26 "Q_1[26]") (joined - (portRef DO8 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_27 "Q_1[27]") (joined - (portRef DO9 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_28 "Q_1[28]") (joined - (portRef DO10 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_29 "Q_1[29]") (joined - (portRef DO11 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_30 "Q_1[30]") (joined - (portRef DO12 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_31 "Q_1[31]") (joined - (portRef DO13 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO14_1 (joined - (portRef DO14 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO15_1 (joined - (portRef DO15 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO16_1 (joined - (portRef DO16 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO17_1 (joined - (portRef DO17 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef DO18 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef DO19 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef DO20 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef DO21 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef DO22 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef DO23 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef DO24 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef DO25 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef DO26 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef DO27 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef DO28 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef DO29 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef DO30 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef DO31 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef DO32 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef DO33 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef DO34 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef DO35 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net iwcount_0 (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)) - )) - (net iwcount_1 (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)) - )) - (net iwcount_2 (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)) - )) - (net iwcount_3 (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)) - )) - (net iwcount_4 (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)) - )) - (net iwcount_5 (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)) - )) - (net iwcount_6 (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)) - )) - (net iwcount_7 (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)) - )) - (net iwcount_8 (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)) - )) - (net iwcount_9 (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)) - )) - (net w_gcount_0 (joined - (portRef Q (instanceRef FF_91)) - (portRef D (instanceRef FF_41)) - )) - (net w_gcount_1 (joined - (portRef Q (instanceRef FF_90)) - (portRef D (instanceRef FF_40)) - )) - (net w_gcount_2 (joined - (portRef Q (instanceRef FF_89)) - (portRef D (instanceRef FF_39)) - )) - (net w_gcount_3 (joined - (portRef Q (instanceRef FF_88)) - (portRef D (instanceRef FF_38)) - )) - (net w_gcount_4 (joined - (portRef Q (instanceRef FF_87)) - (portRef D (instanceRef FF_37)) - )) - (net w_gcount_5 (joined - (portRef Q (instanceRef FF_86)) - (portRef D (instanceRef FF_36)) - )) - (net w_gcount_6 (joined - (portRef Q (instanceRef FF_85)) - (portRef D (instanceRef FF_35)) - )) - (net w_gcount_7 (joined - (portRef Q (instanceRef FF_84)) - (portRef D (instanceRef FF_34)) - )) - (net w_gcount_8 (joined - (portRef Q (instanceRef FF_83)) - (portRef D (instanceRef FF_33)) - )) - (net w_gcount_9 (joined - (portRef Q (instanceRef FF_82)) - (portRef D (instanceRef FF_32)) - )) - (net ircount_0 (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)) - )) - (net ircount_1 (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)) - )) - (net ircount_2 (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)) - )) - (net ircount_3 (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)) - )) - (net ircount_4 (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)) - )) - (net ircount_5 (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)) - )) - (net ircount_6 (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)) - )) - (net ircount_7 (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)) - )) - (net ircount_8 (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)) - )) - (net ircount_9 (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)) - )) - (net r_gcount_0 (joined - (portRef Q (instanceRef FF_61)) - (portRef D (instanceRef FF_31)) - )) - (net r_gcount_1 (joined - (portRef Q (instanceRef FF_60)) - (portRef D (instanceRef FF_30)) - )) - (net r_gcount_2 (joined - (portRef Q (instanceRef FF_59)) - (portRef D (instanceRef FF_29)) - )) - (net r_gcount_3 (joined - (portRef Q (instanceRef FF_58)) - (portRef D (instanceRef FF_28)) - )) - (net r_gcount_4 (joined - (portRef Q (instanceRef FF_57)) - (portRef D (instanceRef FF_27)) - )) - (net r_gcount_5 (joined - (portRef Q (instanceRef FF_56)) - (portRef D (instanceRef FF_26)) - )) - (net r_gcount_6 (joined - (portRef Q (instanceRef FF_55)) - (portRef D (instanceRef FF_25)) - )) - (net r_gcount_7 (joined - (portRef Q (instanceRef FF_54)) - (portRef D (instanceRef FF_24)) - )) - (net r_gcount_8 (joined - (portRef Q (instanceRef FF_53)) - (portRef D (instanceRef FF_23)) - )) - (net r_gcount_9 (joined - (portRef Q (instanceRef FF_52)) - (portRef D (instanceRef FF_22)) - )) - (net w_gcount_r0 (joined - (portRef Q (instanceRef FF_41)) - (portRef D (instanceRef FF_21)) - )) - (net w_gcount_r1 (joined - (portRef Q (instanceRef FF_40)) - (portRef D (instanceRef FF_20)) - )) - (net w_gcount_r2 (joined - (portRef Q (instanceRef FF_39)) - (portRef D (instanceRef FF_19)) - )) - (net w_gcount_r3 (joined - (portRef Q (instanceRef FF_38)) - (portRef D (instanceRef FF_18)) - )) - (net w_gcount_r4 (joined - (portRef Q (instanceRef FF_37)) - (portRef D (instanceRef FF_17)) - )) - (net w_gcount_r5 (joined - (portRef Q (instanceRef FF_36)) - (portRef D (instanceRef FF_16)) - )) - (net w_gcount_r6 (joined - (portRef Q (instanceRef FF_35)) - (portRef D (instanceRef FF_15)) - )) - (net w_gcount_r7 (joined - (portRef Q (instanceRef FF_34)) - (portRef D (instanceRef FF_14)) - )) - (net w_gcount_r8 (joined - (portRef Q (instanceRef FF_33)) - (portRef D (instanceRef FF_13)) - )) - (net w_gcount_r9 (joined - (portRef Q (instanceRef FF_32)) - (portRef D (instanceRef FF_12)) - )) - (net r_gcount_w0 (joined - (portRef Q (instanceRef FF_31)) - (portRef D (instanceRef FF_11)) - )) - (net r_gcount_w1 (joined - (portRef Q (instanceRef FF_30)) - (portRef D (instanceRef FF_10)) - )) - (net r_gcount_w2 (joined - (portRef Q (instanceRef FF_29)) - (portRef D (instanceRef FF_9)) - )) - (net r_gcount_w3 (joined - (portRef Q (instanceRef FF_28)) - (portRef D (instanceRef FF_8)) - )) - (net r_gcount_w4 (joined - (portRef Q (instanceRef FF_27)) - (portRef D (instanceRef FF_7)) - )) - (net r_gcount_w5 (joined - (portRef Q (instanceRef FF_26)) - (portRef D (instanceRef FF_6)) - )) - (net r_gcount_w6 (joined - (portRef Q (instanceRef FF_25)) - (portRef D (instanceRef FF_5)) - )) - (net r_gcount_w7 (joined - (portRef Q (instanceRef FF_24)) - (portRef D (instanceRef FF_4)) - )) - (net r_gcount_w8 (joined - (portRef Q (instanceRef FF_23)) - (portRef D (instanceRef FF_3)) - )) - (net r_gcount_w9 (joined - (portRef Q (instanceRef FF_22)) - (portRef D (instanceRef FF_2)) - )) - (net empty_d (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)) - )) - (net full_d (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)) - )) - (net w_gctr_ci (joined - (portRef COUT (instanceRef w_gctr_cia)) - (portRef CIN (instanceRef w_gctr_0)) - )) - (net w_gctr_cia_S0_1 (joined - (portRef S0 (instanceRef w_gctr_cia)) - )) - (net w_gctr_cia_S1_1 (joined - (portRef S1 (instanceRef w_gctr_cia)) - )) - (net co0 (joined - (portRef COUT (instanceRef w_gctr_0)) - (portRef CIN (instanceRef w_gctr_1)) - )) - (net co1 (joined - (portRef COUT (instanceRef w_gctr_1)) - (portRef CIN (instanceRef w_gctr_2)) - )) - (net co2 (joined - (portRef COUT (instanceRef w_gctr_2)) - (portRef CIN (instanceRef w_gctr_3)) - )) - (net co3 (joined - (portRef COUT (instanceRef w_gctr_3)) - (portRef CIN (instanceRef w_gctr_4)) - )) - (net co4 (joined - (portRef COUT (instanceRef w_gctr_4)) - )) - (net r_gctr_ci (joined - (portRef COUT (instanceRef r_gctr_cia)) - (portRef CIN (instanceRef r_gctr_0)) - )) - (net r_gctr_cia_S0_1 (joined - (portRef S0 (instanceRef r_gctr_cia)) - )) - (net r_gctr_cia_S1_1 (joined - (portRef S1 (instanceRef r_gctr_cia)) - )) - (net co0_1 (joined - (portRef COUT (instanceRef r_gctr_0)) - (portRef CIN (instanceRef r_gctr_1)) - )) - (net co1_1 (joined - (portRef COUT (instanceRef r_gctr_1)) - (portRef CIN (instanceRef r_gctr_2)) - )) - (net co2_1 (joined - (portRef COUT (instanceRef r_gctr_2)) - (portRef CIN (instanceRef r_gctr_3)) - )) - (net co3_1 (joined - (portRef COUT (instanceRef r_gctr_3)) - (portRef CIN (instanceRef r_gctr_4)) - )) - (net co4_1 (joined - (portRef COUT (instanceRef r_gctr_4)) - )) - (net cmp_ci (joined - (portRef COUT (instanceRef empty_cmp_ci_a)) - (portRef CIN (instanceRef empty_cmp_0)) - )) - (net empty_cmp_ci_a_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_ci_a)) - )) - (net empty_cmp_ci_a_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_ci_a)) - )) - (net co0_2 (joined - (portRef COUT (instanceRef empty_cmp_0)) - (portRef CIN (instanceRef empty_cmp_1)) - )) - (net empty_cmp_0_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_0)) - )) - (net empty_cmp_0_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_0)) - )) - (net co1_2 (joined - (portRef COUT (instanceRef empty_cmp_1)) - (portRef CIN (instanceRef empty_cmp_2)) - )) - (net empty_cmp_1_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_1)) - )) - (net empty_cmp_1_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_1)) - )) - (net co2_2 (joined - (portRef COUT (instanceRef empty_cmp_2)) - (portRef CIN (instanceRef empty_cmp_3)) - )) - (net empty_cmp_2_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_2)) - )) - (net empty_cmp_2_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_2)) - )) - (net co3_2 (joined - (portRef COUT (instanceRef empty_cmp_3)) - (portRef CIN (instanceRef empty_cmp_4)) - )) - (net empty_cmp_3_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_3)) - )) - (net empty_cmp_3_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_3)) - )) - (net empty_d_c (joined - (portRef COUT (instanceRef empty_cmp_4)) - (portRef CIN (instanceRef a0)) - )) - (net empty_cmp_4_S0_1 (joined - (portRef S0 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_4_S1_1 (joined - (portRef S1 (instanceRef empty_cmp_4)) - )) - (net a0_COUT_1 (joined - (portRef COUT (instanceRef a0)) - )) - (net a0_S1_1 (joined - (portRef S1 (instanceRef a0)) - )) - (net cmp_ci_1 (joined - (portRef COUT (instanceRef full_cmp_ci_a)) - (portRef CIN (instanceRef full_cmp_0)) - )) - (net full_cmp_ci_a_S0_1 (joined - (portRef S0 (instanceRef full_cmp_ci_a)) - )) - (net full_cmp_ci_a_S1_1 (joined - (portRef S1 (instanceRef full_cmp_ci_a)) - )) - (net co0_3 (joined - (portRef COUT (instanceRef full_cmp_0)) - (portRef CIN (instanceRef full_cmp_1)) - )) - (net full_cmp_0_S0_1 (joined - (portRef S0 (instanceRef full_cmp_0)) - )) - (net full_cmp_0_S1_1 (joined - (portRef S1 (instanceRef full_cmp_0)) - )) - (net co1_3 (joined - (portRef COUT (instanceRef full_cmp_1)) - (portRef CIN (instanceRef full_cmp_2)) - )) - (net full_cmp_1_S0_1 (joined - (portRef S0 (instanceRef full_cmp_1)) - )) - (net full_cmp_1_S1_1 (joined - (portRef S1 (instanceRef full_cmp_1)) - )) - (net co2_3 (joined - (portRef COUT (instanceRef full_cmp_2)) - (portRef CIN (instanceRef full_cmp_3)) - )) - (net full_cmp_2_S0_1 (joined - (portRef S0 (instanceRef full_cmp_2)) - )) - (net full_cmp_2_S1_1 (joined - (portRef S1 (instanceRef full_cmp_2)) - )) - (net co3_3 (joined - (portRef COUT (instanceRef full_cmp_3)) - (portRef CIN (instanceRef full_cmp_4)) - )) - (net full_cmp_3_S0_1 (joined - (portRef S0 (instanceRef full_cmp_3)) - )) - (net full_cmp_3_S1_1 (joined - (portRef S1 (instanceRef full_cmp_3)) - )) - (net full_d_c (joined - (portRef COUT (instanceRef full_cmp_4)) - (portRef CIN (instanceRef a1)) - )) - (net full_cmp_4_S0_1 (joined - (portRef S0 (instanceRef full_cmp_4)) - )) - (net full_cmp_4_S1_1 (joined - (portRef S1 (instanceRef full_cmp_4)) - )) - (net a1_COUT_1 (joined - (portRef COUT (instanceRef a1)) - )) - (net a1_S1_1 (joined - (portRef S1 (instanceRef a1)) - )) - (net CIN (joined - (portRef CIN (instanceRef full_cmp_ci_a)) - )) - (net CIN_0 (joined - (portRef CIN (instanceRef empty_cmp_ci_a)) - )) - (net CIN_1 (joined - (portRef CIN (instanceRef r_gctr_cia)) - )) - (net CIN_2 (joined - (portRef CIN (instanceRef w_gctr_cia)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "fifo32dc")) - ) - ) - (cell output_decoder8_2_1 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT)) - (port decoder_valid (direction OUTPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))")) - ) - (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net N_350_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef valid_internal_RNO_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - )) - (net decoder_valid (joined - (portRef Q (instanceRef valid)) - (portRef decoder_valid) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef A (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef B (instanceRef un1_out_internal35_1_0_m4_0)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef C (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef valid_internal_RNO_0)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef valid_internal_RNO_0)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef valid_internal_RNO)) - )) - (net N_42 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell tdc4ddr_short_4 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port trig_c_i_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out 4)) - )) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out 0)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net (rename trig_c_i_0 "trig_c_i[2]") (joined - (portRef trig_c_i_0) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out 5)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out 1)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out 6)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out 2)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out 7)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out 3)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell fifo32dc_0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port pll_clks_0 (direction INPUT)) - (port fifo_in_data_0 (direction INPUT)) - (port fifo_empty_0 (direction OUTPUT)) - (port fifo_read_0 (direction INPUT)) - (port fifo_wren (direction INPUT)) - ) - (contents - (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT))) - ) - (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0410")) - ) - (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x1004")) - ) - (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0140")) - ) - (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x4001")) - ) - (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT))) - (property MEM_LPC_FILE (string "fifo32dc.lpc")) - (property MEM_INIT_FILE (string "")) - (property DATA_WIDTH_W (integer 36)) - (property DATA_WIDTH_R (integer 36)) - (property REGMODE (string "NOREG")) - (property RESETMODE (string "SYNC")) - (property GSR (string "ENABLED")) - (property CSDECODE_W (string "0b001")) - (property CSDECODE_R (string "0b000")) - (property ASYNC_RESET_RELEASE (string "SYNC")) - (property INIT_DATA (string "STATIC")) - ) - (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net fifo_wren (joined - (portRef fifo_wren) - (portRef A (instanceRef AND2_t20)) - )) - (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)) - )) - (net wren_i (joined - (portRef Z (instanceRef AND2_t20)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_101)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - )) - (net Full (joined - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)) - )) - (net (rename fifo_read_0 "fifo_read[1]") (joined - (portRef fifo_read_0) - (portRef A (instanceRef AND2_t19)) - )) - (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)) - )) - (net rden_i (joined - (portRef Z (instanceRef AND2_t19)) - (portRef B1 (instanceRef empty_cmp_ci_a)) - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef SP (instanceRef FF_42)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_71)) - (portRef OCER (instanceRef pdp_ram_0_0_0)) - (portRef CER (instanceRef pdp_ram_0_0_0)) - )) - (net (rename fifo_empty_0 "fifo_empty[1]") (joined - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)) - (portRef fifo_empty_0) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef B1 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A0 (instanceRef a1)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef CD (instanceRef FF_0)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_100)) - (portRef PD (instanceRef FF_101)) - (portRef RST (instanceRef pdp_ram_0_0_0)) - (portRef CSR2 (instanceRef pdp_ram_0_0_0)) - (portRef CSR1 (instanceRef pdp_ram_0_0_0)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef ADR4 (instanceRef pdp_ram_0_0_0)) - (portRef ADR3 (instanceRef pdp_ram_0_0_0)) - (portRef ADR2 (instanceRef pdp_ram_0_0_0)) - (portRef ADR1 (instanceRef pdp_ram_0_0_0)) - (portRef ADR0 (instanceRef pdp_ram_0_0_0)) - (portRef CSW2 (instanceRef pdp_ram_0_0_0)) - (portRef CSW1 (instanceRef pdp_ram_0_0_0)) - (portRef DI35 (instanceRef pdp_ram_0_0_0)) - (portRef DI34 (instanceRef pdp_ram_0_0_0)) - (portRef DI33 (instanceRef pdp_ram_0_0_0)) - (portRef DI32 (instanceRef pdp_ram_0_0_0)) - (portRef DI31 (instanceRef pdp_ram_0_0_0)) - (portRef DI30 (instanceRef pdp_ram_0_0_0)) - (portRef DI29 (instanceRef pdp_ram_0_0_0)) - (portRef DI28 (instanceRef pdp_ram_0_0_0)) - (portRef DI25 (instanceRef pdp_ram_0_0_0)) - (portRef DI23 (instanceRef pdp_ram_0_0_0)) - (portRef DI22 (instanceRef pdp_ram_0_0_0)) - (portRef DI21 (instanceRef pdp_ram_0_0_0)) - (portRef DI20 (instanceRef pdp_ram_0_0_0)) - (portRef DI19 (instanceRef pdp_ram_0_0_0)) - (portRef DI18 (instanceRef pdp_ram_0_0_0)) - (portRef DI17 (instanceRef pdp_ram_0_0_0)) - (portRef DI16 (instanceRef pdp_ram_0_0_0)) - (portRef DI14 (instanceRef pdp_ram_0_0_0)) - (portRef DI10 (instanceRef pdp_ram_0_0_0)) - (portRef DI8 (instanceRef pdp_ram_0_0_0)) - (portRef DI7 (instanceRef pdp_ram_0_0_0)) - (portRef DI6 (instanceRef pdp_ram_0_0_0)) - (portRef DI5 (instanceRef pdp_ram_0_0_0)) - (portRef DI4 (instanceRef pdp_ram_0_0_0)) - (portRef DI3 (instanceRef pdp_ram_0_0_0)) - (portRef DI2 (instanceRef pdp_ram_0_0_0)) - (portRef DI1 (instanceRef pdp_ram_0_0_0)) - (portRef DI0 (instanceRef pdp_ram_0_0_0)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef B (instanceRef OR2_t18)) - (portRef A (instanceRef OR2_t18)) - )) - (net rRst (joined - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_1)) - (portRef CD (instanceRef FF_2)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_70)) - (portRef PD (instanceRef FF_71)) - )) - (net wcount_0 (joined - (portRef Q (instanceRef FF_101)) - (portRef A0 (instanceRef full_cmp_0)) - (portRef A0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_81)) - (portRef A (instanceRef XOR2_t17)) - )) - (net wcount_1 (joined - (portRef Q (instanceRef FF_100)) - (portRef A1 (instanceRef full_cmp_0)) - (portRef A1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_80)) - (portRef A (instanceRef XOR2_t16)) - (portRef B (instanceRef XOR2_t17)) - )) - (net w_gdata_0 (joined - (portRef Z (instanceRef XOR2_t17)) - (portRef D (instanceRef FF_91)) - )) - (net wcount_2 (joined - (portRef Q (instanceRef FF_99)) - (portRef A0 (instanceRef full_cmp_1)) - (portRef A0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_79)) - (portRef A (instanceRef XOR2_t15)) - (portRef B (instanceRef XOR2_t16)) - )) - (net w_gdata_1 (joined - (portRef Z (instanceRef XOR2_t16)) - (portRef D (instanceRef FF_90)) - )) - (net wcount_3 (joined - (portRef Q (instanceRef FF_98)) - (portRef A1 (instanceRef full_cmp_1)) - (portRef A1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_78)) - (portRef A (instanceRef XOR2_t14)) - (portRef B (instanceRef XOR2_t15)) - )) - (net w_gdata_2 (joined - (portRef Z (instanceRef XOR2_t15)) - (portRef D (instanceRef FF_89)) - )) - (net wcount_4 (joined - (portRef Q (instanceRef FF_97)) - (portRef A0 (instanceRef full_cmp_2)) - (portRef A0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_77)) - (portRef A (instanceRef XOR2_t13)) - (portRef B (instanceRef XOR2_t14)) - )) - (net w_gdata_3 (joined - (portRef Z (instanceRef XOR2_t14)) - (portRef D (instanceRef FF_88)) - )) - (net wcount_5 (joined - (portRef Q (instanceRef FF_96)) - (portRef A1 (instanceRef full_cmp_2)) - (portRef A1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_76)) - (portRef A (instanceRef XOR2_t12)) - (portRef B (instanceRef XOR2_t13)) - )) - (net w_gdata_4 (joined - (portRef Z (instanceRef XOR2_t13)) - (portRef D (instanceRef FF_87)) - )) - (net wcount_6 (joined - (portRef Q (instanceRef FF_95)) - (portRef A0 (instanceRef full_cmp_3)) - (portRef A0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_75)) - (portRef A (instanceRef XOR2_t11)) - (portRef B (instanceRef XOR2_t12)) - )) - (net w_gdata_5 (joined - (portRef Z (instanceRef XOR2_t12)) - (portRef D (instanceRef FF_86)) - )) - (net wcount_7 (joined - (portRef Q (instanceRef FF_94)) - (portRef A1 (instanceRef full_cmp_3)) - (portRef A1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_74)) - (portRef A (instanceRef XOR2_t10)) - (portRef B (instanceRef XOR2_t11)) - )) - (net w_gdata_6 (joined - (portRef Z (instanceRef XOR2_t11)) - (portRef D (instanceRef FF_85)) - )) - (net wcount_8 (joined - (portRef Q (instanceRef FF_93)) - (portRef A0 (instanceRef full_cmp_4)) - (portRef A0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_73)) - (portRef A (instanceRef XOR2_t9)) - (portRef B (instanceRef XOR2_t10)) - )) - (net w_gdata_7 (joined - (portRef Z (instanceRef XOR2_t10)) - (portRef D (instanceRef FF_84)) - )) - (net wcount_9 (joined - (portRef Q (instanceRef FF_92)) - (portRef A1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_72)) - (portRef D (instanceRef FF_82)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef B (instanceRef XOR2_t9)) - )) - (net w_gdata_8 (joined - (portRef Z (instanceRef XOR2_t9)) - (portRef D (instanceRef FF_83)) - )) - (net rcount_0 (joined - (portRef Q (instanceRef FF_71)) - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_51)) - (portRef A (instanceRef XOR2_t8)) - )) - (net rcount_1 (joined - (portRef Q (instanceRef FF_70)) - (portRef A1 (instanceRef empty_cmp_0)) - (portRef A1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_50)) - (portRef A (instanceRef XOR2_t7)) - (portRef B (instanceRef XOR2_t8)) - )) - (net r_gdata_0 (joined - (portRef Z (instanceRef XOR2_t8)) - (portRef D (instanceRef FF_61)) - )) - (net rcount_2 (joined - (portRef Q (instanceRef FF_69)) - (portRef A0 (instanceRef empty_cmp_1)) - (portRef A0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_49)) - (portRef A (instanceRef XOR2_t6)) - (portRef B (instanceRef XOR2_t7)) - )) - (net r_gdata_1 (joined - (portRef Z (instanceRef XOR2_t7)) - (portRef D (instanceRef FF_60)) - )) - (net rcount_3 (joined - (portRef Q (instanceRef FF_68)) - (portRef A1 (instanceRef empty_cmp_1)) - (portRef A1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_48)) - (portRef A (instanceRef XOR2_t5)) - (portRef B (instanceRef XOR2_t6)) - )) - (net r_gdata_2 (joined - (portRef Z (instanceRef XOR2_t6)) - (portRef D (instanceRef FF_59)) - )) - (net rcount_4 (joined - (portRef Q (instanceRef FF_67)) - (portRef A0 (instanceRef empty_cmp_2)) - (portRef A0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_47)) - (portRef A (instanceRef XOR2_t4)) - (portRef B (instanceRef XOR2_t5)) - )) - (net r_gdata_3 (joined - (portRef Z (instanceRef XOR2_t5)) - (portRef D (instanceRef FF_58)) - )) - (net rcount_5 (joined - (portRef Q (instanceRef FF_66)) - (portRef A1 (instanceRef empty_cmp_2)) - (portRef A1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_46)) - (portRef A (instanceRef XOR2_t3)) - (portRef B (instanceRef XOR2_t4)) - )) - (net r_gdata_4 (joined - (portRef Z (instanceRef XOR2_t4)) - (portRef D (instanceRef FF_57)) - )) - (net rcount_6 (joined - (portRef Q (instanceRef FF_65)) - (portRef A0 (instanceRef empty_cmp_3)) - (portRef A0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_45)) - (portRef A (instanceRef XOR2_t2)) - (portRef B (instanceRef XOR2_t3)) - )) - (net r_gdata_5 (joined - (portRef Z (instanceRef XOR2_t3)) - (portRef D (instanceRef FF_56)) - )) - (net rcount_7 (joined - (portRef Q (instanceRef FF_64)) - (portRef A1 (instanceRef empty_cmp_3)) - (portRef A1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_44)) - (portRef A (instanceRef XOR2_t1)) - (portRef B (instanceRef XOR2_t2)) - )) - (net r_gdata_6 (joined - (portRef Z (instanceRef XOR2_t2)) - (portRef D (instanceRef FF_55)) - )) - (net rcount_8 (joined - (portRef Q (instanceRef FF_63)) - (portRef A0 (instanceRef empty_cmp_4)) - (portRef A0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_43)) - (portRef A (instanceRef XOR2_t0)) - (portRef B (instanceRef XOR2_t1)) - )) - (net r_gdata_7 (joined - (portRef Z (instanceRef XOR2_t1)) - (portRef D (instanceRef FF_54)) - )) - (net rcount_9 (joined - (portRef Q (instanceRef FF_62)) - (portRef A1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_42)) - (portRef D (instanceRef FF_52)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef B (instanceRef XOR2_t0)) - )) - (net r_gdata_8 (joined - (portRef Z (instanceRef XOR2_t0)) - (portRef D (instanceRef FF_53)) - )) - (net w_gcount_r29 (joined - (portRef Q (instanceRef FF_12)) - (portRef AD1 (instanceRef LUT4_2)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_23)) - )) - (net w_gcount_r28 (joined - (portRef Q (instanceRef FF_13)) - (portRef AD2 (instanceRef LUT4_20)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_23)) - )) - (net w_gcount_r27 (joined - (portRef Q (instanceRef FF_14)) - (portRef AD1 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_23)) - )) - (net w_gcount_r26 (joined - (portRef Q (instanceRef FF_15)) - (portRef AD1 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_23)) - )) - (net w_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_23)) - (portRef B0 (instanceRef empty_cmp_3)) - (portRef AD3 (instanceRef LUT4_14)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_17)) - )) - (net w_gcount_r25 (joined - (portRef Q (instanceRef FF_16)) - (portRef AD1 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD0 (instanceRef LUT4_22)) - )) - (net w_gcount_r24 (joined - (portRef Q (instanceRef FF_17)) - (portRef AD2 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_22)) - )) - (net w_gcount_r23 (joined - (portRef Q (instanceRef FF_18)) - (portRef AD3 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_22)) - )) - (net w_gcount_r22 (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)) - )) - (net w_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_14)) - (portRef AD2 (instanceRef LUT4_15)) - (portRef AD2 (instanceRef LUT4_16)) - )) - (net wcount_r8 (joined - (portRef DO0 (instanceRef LUT4_21)) - (portRef B0 (instanceRef empty_cmp_4)) - (portRef AD0 (instanceRef LUT4_19)) - )) - (net wcount_r7 (joined - (portRef DO0 (instanceRef LUT4_20)) - (portRef B1 (instanceRef empty_cmp_3)) - (portRef AD0 (instanceRef LUT4_18)) - )) - (net wcount_r5 (joined - (portRef DO0 (instanceRef LUT4_19)) - (portRef B1 (instanceRef empty_cmp_2)) - )) - (net wcount_r4 (joined - (portRef DO0 (instanceRef LUT4_18)) - (portRef B0 (instanceRef empty_cmp_2)) - )) - (net wcount_r3 (joined - (portRef DO0 (instanceRef LUT4_17)) - (portRef B1 (instanceRef empty_cmp_1)) - )) - (net wcount_r2 (joined - (portRef DO0 (instanceRef LUT4_16)) - (portRef B0 (instanceRef empty_cmp_1)) - )) - (net w_gcount_r21 (joined - (portRef Q (instanceRef FF_20)) - (portRef AD0 (instanceRef LUT4_14)) - (portRef AD1 (instanceRef LUT4_15)) - )) - (net wcount_r1 (joined - (portRef DO0 (instanceRef LUT4_15)) - (portRef B1 (instanceRef empty_cmp_0)) - )) - (net w_gcount_r20 (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)) - )) - (net wcount_r0 (joined - (portRef DO0 (instanceRef LUT4_14)) - (portRef B0 (instanceRef empty_cmp_0)) - )) - (net r_gcount_w29 (joined - (portRef Q (instanceRef FF_2)) - (portRef AD1 (instanceRef LUT4_0)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_13)) - )) - (net r_gcount_w28 (joined - (portRef Q (instanceRef FF_3)) - (portRef AD2 (instanceRef LUT4_10)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_13)) - )) - (net r_gcount_w27 (joined - (portRef Q (instanceRef FF_4)) - (portRef AD1 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_13)) - )) - (net r_gcount_w26 (joined - (portRef Q (instanceRef FF_5)) - (portRef AD1 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_13)) - )) - (net r_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_13)) - (portRef B0 (instanceRef full_cmp_3)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_7)) - )) - (net r_gcount_w25 (joined - (portRef Q (instanceRef FF_6)) - (portRef AD1 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_12)) - )) - (net r_gcount_w24 (joined - (portRef Q (instanceRef FF_7)) - (portRef AD2 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_12)) - )) - (net r_gcount_w23 (joined - (portRef Q (instanceRef FF_8)) - (portRef AD3 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_12)) - )) - (net r_gcount_w22 (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)) - )) - (net r_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_4)) - (portRef AD2 (instanceRef LUT4_5)) - (portRef AD2 (instanceRef LUT4_6)) - )) - (net rcount_w8 (joined - (portRef DO0 (instanceRef LUT4_11)) - (portRef B0 (instanceRef full_cmp_4)) - (portRef AD0 (instanceRef LUT4_9)) - )) - (net rcount_w7 (joined - (portRef DO0 (instanceRef LUT4_10)) - (portRef B1 (instanceRef full_cmp_3)) - (portRef AD0 (instanceRef LUT4_8)) - )) - (net rcount_w5 (joined - (portRef DO0 (instanceRef LUT4_9)) - (portRef B1 (instanceRef full_cmp_2)) - )) - (net rcount_w4 (joined - (portRef DO0 (instanceRef LUT4_8)) - (portRef B0 (instanceRef full_cmp_2)) - )) - (net rcount_w3 (joined - (portRef DO0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef full_cmp_1)) - )) - (net rcount_w2 (joined - (portRef DO0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef full_cmp_1)) - )) - (net r_gcount_w21 (joined - (portRef Q (instanceRef FF_10)) - (portRef AD0 (instanceRef LUT4_4)) - (portRef AD1 (instanceRef LUT4_5)) - )) - (net rcount_w1 (joined - (portRef DO0 (instanceRef LUT4_5)) - (portRef B1 (instanceRef full_cmp_0)) - )) - (net r_gcount_w20 (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)) - )) - (net rcount_w0 (joined - (portRef DO0 (instanceRef LUT4_4)) - (portRef B0 (instanceRef full_cmp_0)) - )) - (net rptr_9 (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_2)) - (portRef AD3 (instanceRef LUT4_3)) - )) - (net empty_cmp_set (joined - (portRef DO0 (instanceRef LUT4_3)) - (portRef A1 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_2)) - (portRef B1 (instanceRef empty_cmp_4)) - )) - (net wptr_9 (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_0)) - (portRef AD3 (instanceRef LUT4_1)) - )) - (net full_cmp_set (joined - (portRef DO0 (instanceRef LUT4_1)) - (portRef A1 (instanceRef full_cmp_4)) - )) - (net full_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_0)) - (portRef B1 (instanceRef full_cmp_4)) - )) - (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined - (portRef fifo_in_data_0) - (portRef DI27 (instanceRef pdp_ram_0_0_0)) - (portRef DI26 (instanceRef pdp_ram_0_0_0)) - (portRef DI24 (instanceRef pdp_ram_0_0_0)) - (portRef DI15 (instanceRef pdp_ram_0_0_0)) - (portRef DI13 (instanceRef pdp_ram_0_0_0)) - (portRef DI12 (instanceRef pdp_ram_0_0_0)) - (portRef DI11 (instanceRef pdp_ram_0_0_0)) - (portRef DI9 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_0 (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_1 (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_2 (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_3 (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_4 (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_5 (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_6 (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_7 (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_8 (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef a1)) - (portRef C1 (instanceRef a1)) - (portRef D0 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef a0)) - (portRef C1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef CSW0 (instanceRef pdp_ram_0_0_0)) - (portRef BE3 (instanceRef pdp_ram_0_0_0)) - (portRef BE2 (instanceRef pdp_ram_0_0_0)) - (portRef BE1 (instanceRef pdp_ram_0_0_0)) - (portRef BE0 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef CK (instanceRef FF_0)) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_71)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_101)) - (portRef CLKR (instanceRef pdp_ram_0_0_0)) - (portRef CLKW (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_0 (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_1 (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_2 (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_3 (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_4 (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_5 (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_6 (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_7 (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_8 (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef DO0 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef DO1 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef DO2 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef DO3 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef DO4 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef DO5 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename Q_1_24 "Q_1[24]") (joined - (portRef DO6 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_25 "Q_1[25]") (joined - (portRef DO7 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_26 "Q_1[26]") (joined - (portRef DO8 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_27 "Q_1[27]") (joined - (portRef DO9 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_28 "Q_1[28]") (joined - (portRef DO10 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_29 "Q_1[29]") (joined - (portRef DO11 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_30 "Q_1[30]") (joined - (portRef DO12 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_31 "Q_1[31]") (joined - (portRef DO13 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO14_0 (joined - (portRef DO14 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO15_0 (joined - (portRef DO15 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO16_0 (joined - (portRef DO16 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO17_0 (joined - (portRef DO17 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef DO18 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef DO19 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef DO20 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef DO21 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef DO22 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef DO23 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef DO24 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef DO25 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef DO26 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef DO27 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef DO28 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef DO29 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef DO30 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef DO31 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef DO32 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef DO33 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef DO34 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef DO35 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net iwcount_0 (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)) - )) - (net iwcount_1 (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)) - )) - (net iwcount_2 (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)) - )) - (net iwcount_3 (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)) - )) - (net iwcount_4 (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)) - )) - (net iwcount_5 (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)) - )) - (net iwcount_6 (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)) - )) - (net iwcount_7 (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)) - )) - (net iwcount_8 (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)) - )) - (net iwcount_9 (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)) - )) - (net w_gcount_0 (joined - (portRef Q (instanceRef FF_91)) - (portRef D (instanceRef FF_41)) - )) - (net w_gcount_1 (joined - (portRef Q (instanceRef FF_90)) - (portRef D (instanceRef FF_40)) - )) - (net w_gcount_2 (joined - (portRef Q (instanceRef FF_89)) - (portRef D (instanceRef FF_39)) - )) - (net w_gcount_3 (joined - (portRef Q (instanceRef FF_88)) - (portRef D (instanceRef FF_38)) - )) - (net w_gcount_4 (joined - (portRef Q (instanceRef FF_87)) - (portRef D (instanceRef FF_37)) - )) - (net w_gcount_5 (joined - (portRef Q (instanceRef FF_86)) - (portRef D (instanceRef FF_36)) - )) - (net w_gcount_6 (joined - (portRef Q (instanceRef FF_85)) - (portRef D (instanceRef FF_35)) - )) - (net w_gcount_7 (joined - (portRef Q (instanceRef FF_84)) - (portRef D (instanceRef FF_34)) - )) - (net w_gcount_8 (joined - (portRef Q (instanceRef FF_83)) - (portRef D (instanceRef FF_33)) - )) - (net w_gcount_9 (joined - (portRef Q (instanceRef FF_82)) - (portRef D (instanceRef FF_32)) - )) - (net ircount_0 (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)) - )) - (net ircount_1 (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)) - )) - (net ircount_2 (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)) - )) - (net ircount_3 (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)) - )) - (net ircount_4 (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)) - )) - (net ircount_5 (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)) - )) - (net ircount_6 (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)) - )) - (net ircount_7 (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)) - )) - (net ircount_8 (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)) - )) - (net ircount_9 (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)) - )) - (net r_gcount_0 (joined - (portRef Q (instanceRef FF_61)) - (portRef D (instanceRef FF_31)) - )) - (net r_gcount_1 (joined - (portRef Q (instanceRef FF_60)) - (portRef D (instanceRef FF_30)) - )) - (net r_gcount_2 (joined - (portRef Q (instanceRef FF_59)) - (portRef D (instanceRef FF_29)) - )) - (net r_gcount_3 (joined - (portRef Q (instanceRef FF_58)) - (portRef D (instanceRef FF_28)) - )) - (net r_gcount_4 (joined - (portRef Q (instanceRef FF_57)) - (portRef D (instanceRef FF_27)) - )) - (net r_gcount_5 (joined - (portRef Q (instanceRef FF_56)) - (portRef D (instanceRef FF_26)) - )) - (net r_gcount_6 (joined - (portRef Q (instanceRef FF_55)) - (portRef D (instanceRef FF_25)) - )) - (net r_gcount_7 (joined - (portRef Q (instanceRef FF_54)) - (portRef D (instanceRef FF_24)) - )) - (net r_gcount_8 (joined - (portRef Q (instanceRef FF_53)) - (portRef D (instanceRef FF_23)) - )) - (net r_gcount_9 (joined - (portRef Q (instanceRef FF_52)) - (portRef D (instanceRef FF_22)) - )) - (net w_gcount_r0 (joined - (portRef Q (instanceRef FF_41)) - (portRef D (instanceRef FF_21)) - )) - (net w_gcount_r1 (joined - (portRef Q (instanceRef FF_40)) - (portRef D (instanceRef FF_20)) - )) - (net w_gcount_r2 (joined - (portRef Q (instanceRef FF_39)) - (portRef D (instanceRef FF_19)) - )) - (net w_gcount_r3 (joined - (portRef Q (instanceRef FF_38)) - (portRef D (instanceRef FF_18)) - )) - (net w_gcount_r4 (joined - (portRef Q (instanceRef FF_37)) - (portRef D (instanceRef FF_17)) - )) - (net w_gcount_r5 (joined - (portRef Q (instanceRef FF_36)) - (portRef D (instanceRef FF_16)) - )) - (net w_gcount_r6 (joined - (portRef Q (instanceRef FF_35)) - (portRef D (instanceRef FF_15)) - )) - (net w_gcount_r7 (joined - (portRef Q (instanceRef FF_34)) - (portRef D (instanceRef FF_14)) - )) - (net w_gcount_r8 (joined - (portRef Q (instanceRef FF_33)) - (portRef D (instanceRef FF_13)) - )) - (net w_gcount_r9 (joined - (portRef Q (instanceRef FF_32)) - (portRef D (instanceRef FF_12)) - )) - (net r_gcount_w0 (joined - (portRef Q (instanceRef FF_31)) - (portRef D (instanceRef FF_11)) - )) - (net r_gcount_w1 (joined - (portRef Q (instanceRef FF_30)) - (portRef D (instanceRef FF_10)) - )) - (net r_gcount_w2 (joined - (portRef Q (instanceRef FF_29)) - (portRef D (instanceRef FF_9)) - )) - (net r_gcount_w3 (joined - (portRef Q (instanceRef FF_28)) - (portRef D (instanceRef FF_8)) - )) - (net r_gcount_w4 (joined - (portRef Q (instanceRef FF_27)) - (portRef D (instanceRef FF_7)) - )) - (net r_gcount_w5 (joined - (portRef Q (instanceRef FF_26)) - (portRef D (instanceRef FF_6)) - )) - (net r_gcount_w6 (joined - (portRef Q (instanceRef FF_25)) - (portRef D (instanceRef FF_5)) - )) - (net r_gcount_w7 (joined - (portRef Q (instanceRef FF_24)) - (portRef D (instanceRef FF_4)) - )) - (net r_gcount_w8 (joined - (portRef Q (instanceRef FF_23)) - (portRef D (instanceRef FF_3)) - )) - (net r_gcount_w9 (joined - (portRef Q (instanceRef FF_22)) - (portRef D (instanceRef FF_2)) - )) - (net empty_d (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)) - )) - (net full_d (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)) - )) - (net w_gctr_ci (joined - (portRef COUT (instanceRef w_gctr_cia)) - (portRef CIN (instanceRef w_gctr_0)) - )) - (net w_gctr_cia_S0_0 (joined - (portRef S0 (instanceRef w_gctr_cia)) - )) - (net w_gctr_cia_S1_0 (joined - (portRef S1 (instanceRef w_gctr_cia)) - )) - (net co0 (joined - (portRef COUT (instanceRef w_gctr_0)) - (portRef CIN (instanceRef w_gctr_1)) - )) - (net co1 (joined - (portRef COUT (instanceRef w_gctr_1)) - (portRef CIN (instanceRef w_gctr_2)) - )) - (net co2 (joined - (portRef COUT (instanceRef w_gctr_2)) - (portRef CIN (instanceRef w_gctr_3)) - )) - (net co3 (joined - (portRef COUT (instanceRef w_gctr_3)) - (portRef CIN (instanceRef w_gctr_4)) - )) - (net co4 (joined - (portRef COUT (instanceRef w_gctr_4)) - )) - (net r_gctr_ci (joined - (portRef COUT (instanceRef r_gctr_cia)) - (portRef CIN (instanceRef r_gctr_0)) - )) - (net r_gctr_cia_S0_0 (joined - (portRef S0 (instanceRef r_gctr_cia)) - )) - (net r_gctr_cia_S1_0 (joined - (portRef S1 (instanceRef r_gctr_cia)) - )) - (net co0_1 (joined - (portRef COUT (instanceRef r_gctr_0)) - (portRef CIN (instanceRef r_gctr_1)) - )) - (net co1_1 (joined - (portRef COUT (instanceRef r_gctr_1)) - (portRef CIN (instanceRef r_gctr_2)) - )) - (net co2_1 (joined - (portRef COUT (instanceRef r_gctr_2)) - (portRef CIN (instanceRef r_gctr_3)) - )) - (net co3_1 (joined - (portRef COUT (instanceRef r_gctr_3)) - (portRef CIN (instanceRef r_gctr_4)) - )) - (net co4_1 (joined - (portRef COUT (instanceRef r_gctr_4)) - )) - (net cmp_ci (joined - (portRef COUT (instanceRef empty_cmp_ci_a)) - (portRef CIN (instanceRef empty_cmp_0)) - )) - (net empty_cmp_ci_a_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_ci_a)) - )) - (net empty_cmp_ci_a_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_ci_a)) - )) - (net co0_2 (joined - (portRef COUT (instanceRef empty_cmp_0)) - (portRef CIN (instanceRef empty_cmp_1)) - )) - (net empty_cmp_0_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_0)) - )) - (net empty_cmp_0_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_0)) - )) - (net co1_2 (joined - (portRef COUT (instanceRef empty_cmp_1)) - (portRef CIN (instanceRef empty_cmp_2)) - )) - (net empty_cmp_1_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_1)) - )) - (net empty_cmp_1_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_1)) - )) - (net co2_2 (joined - (portRef COUT (instanceRef empty_cmp_2)) - (portRef CIN (instanceRef empty_cmp_3)) - )) - (net empty_cmp_2_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_2)) - )) - (net empty_cmp_2_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_2)) - )) - (net co3_2 (joined - (portRef COUT (instanceRef empty_cmp_3)) - (portRef CIN (instanceRef empty_cmp_4)) - )) - (net empty_cmp_3_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_3)) - )) - (net empty_cmp_3_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_3)) - )) - (net empty_d_c (joined - (portRef COUT (instanceRef empty_cmp_4)) - (portRef CIN (instanceRef a0)) - )) - (net empty_cmp_4_S0_0 (joined - (portRef S0 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_4_S1_0 (joined - (portRef S1 (instanceRef empty_cmp_4)) - )) - (net a0_COUT_0 (joined - (portRef COUT (instanceRef a0)) - )) - (net a0_S1_0 (joined - (portRef S1 (instanceRef a0)) - )) - (net cmp_ci_1 (joined - (portRef COUT (instanceRef full_cmp_ci_a)) - (portRef CIN (instanceRef full_cmp_0)) - )) - (net full_cmp_ci_a_S0_0 (joined - (portRef S0 (instanceRef full_cmp_ci_a)) - )) - (net full_cmp_ci_a_S1_0 (joined - (portRef S1 (instanceRef full_cmp_ci_a)) - )) - (net co0_3 (joined - (portRef COUT (instanceRef full_cmp_0)) - (portRef CIN (instanceRef full_cmp_1)) - )) - (net full_cmp_0_S0_0 (joined - (portRef S0 (instanceRef full_cmp_0)) - )) - (net full_cmp_0_S1_0 (joined - (portRef S1 (instanceRef full_cmp_0)) - )) - (net co1_3 (joined - (portRef COUT (instanceRef full_cmp_1)) - (portRef CIN (instanceRef full_cmp_2)) - )) - (net full_cmp_1_S0_0 (joined - (portRef S0 (instanceRef full_cmp_1)) - )) - (net full_cmp_1_S1_0 (joined - (portRef S1 (instanceRef full_cmp_1)) - )) - (net co2_3 (joined - (portRef COUT (instanceRef full_cmp_2)) - (portRef CIN (instanceRef full_cmp_3)) - )) - (net full_cmp_2_S0_0 (joined - (portRef S0 (instanceRef full_cmp_2)) - )) - (net full_cmp_2_S1_0 (joined - (portRef S1 (instanceRef full_cmp_2)) - )) - (net co3_3 (joined - (portRef COUT (instanceRef full_cmp_3)) - (portRef CIN (instanceRef full_cmp_4)) - )) - (net full_cmp_3_S0_0 (joined - (portRef S0 (instanceRef full_cmp_3)) - )) - (net full_cmp_3_S1_0 (joined - (portRef S1 (instanceRef full_cmp_3)) - )) - (net full_d_c (joined - (portRef COUT (instanceRef full_cmp_4)) - (portRef CIN (instanceRef a1)) - )) - (net full_cmp_4_S0_0 (joined - (portRef S0 (instanceRef full_cmp_4)) - )) - (net full_cmp_4_S1_0 (joined - (portRef S1 (instanceRef full_cmp_4)) - )) - (net a1_COUT_0 (joined - (portRef COUT (instanceRef a1)) - )) - (net a1_S1_0 (joined - (portRef S1 (instanceRef a1)) - )) - (net CIN (joined - (portRef CIN (instanceRef full_cmp_ci_a)) - )) - (net CIN_0 (joined - (portRef CIN (instanceRef empty_cmp_ci_a)) - )) - (net CIN_1 (joined - (portRef CIN (instanceRef r_gctr_cia)) - )) - (net CIN_2 (joined - (portRef CIN (instanceRef w_gctr_cia)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "fifo32dc")) - ) - ) - (cell output_decoder8_2_0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT)) - (port decoder_valid (direction OUTPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))")) - ) - (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net N_351_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef valid_internal_RNO_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - )) - (net decoder_valid (joined - (portRef Q (instanceRef valid)) - (portRef decoder_valid) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef A (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef B (instanceRef un1_out_internal35_1_0_m4_0)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef C (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef valid_internal_RNO_0)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef valid_internal_RNO_0)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef valid_internal_RNO)) - )) - (net N_42 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell tdc4ddr_short_3 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port trig_c_i_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out 4)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out 0)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net (rename trig_c_i_0 "trig_c_i[1]") (joined - (portRef trig_c_i_0) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out 5)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out 1)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out 6)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out 2)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out 7)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out 3)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell fifo32dc (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port pll_clks_0 (direction INPUT)) - (port fifo_in_data_0 (direction INPUT)) - (port fifo_read_0 (direction INPUT)) - (port fifo_empty1_c (direction OUTPUT)) - (port fifo_wren (direction INPUT)) - ) - (contents - (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT))) - ) - (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0410")) - ) - (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x1004")) - ) - (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0140")) - ) - (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x4001")) - ) - (instance pdp_ram_0_0_0 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT))) - (property MEM_LPC_FILE (string "fifo32dc.lpc")) - (property MEM_INIT_FILE (string "")) - (property DATA_WIDTH_W (integer 36)) - (property DATA_WIDTH_R (integer 36)) - (property REGMODE (string "NOREG")) - (property RESETMODE (string "SYNC")) - (property GSR (string "ENABLED")) - (property CSDECODE_W (string "0b001")) - (property CSDECODE_R (string "0b000")) - (property ASYNC_RESET_RELEASE (string "SYNC")) - (property INIT_DATA (string "STATIC")) - ) - (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net fifo_wren (joined - (portRef fifo_wren) - (portRef A (instanceRef AND2_t20)) - )) - (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)) - )) - (net wren_i (joined - (portRef Z (instanceRef AND2_t20)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_101)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - )) - (net Full (joined - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)) - )) - (net (rename fifo_read_0 "fifo_read[0]") (joined - (portRef fifo_read_0) - (portRef A (instanceRef AND2_t19)) - )) - (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)) - )) - (net rden_i (joined - (portRef Z (instanceRef AND2_t19)) - (portRef B1 (instanceRef empty_cmp_ci_a)) - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef SP (instanceRef FF_42)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_71)) - (portRef OCER (instanceRef pdp_ram_0_0_0)) - (portRef CER (instanceRef pdp_ram_0_0_0)) - )) - (net fifo_empty1_c (joined - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)) - (portRef fifo_empty1_c) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef B1 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A0 (instanceRef a1)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef CD (instanceRef FF_0)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_100)) - (portRef PD (instanceRef FF_101)) - (portRef RST (instanceRef pdp_ram_0_0_0)) - (portRef CSR2 (instanceRef pdp_ram_0_0_0)) - (portRef CSR1 (instanceRef pdp_ram_0_0_0)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef ADR4 (instanceRef pdp_ram_0_0_0)) - (portRef ADR3 (instanceRef pdp_ram_0_0_0)) - (portRef ADR2 (instanceRef pdp_ram_0_0_0)) - (portRef ADR1 (instanceRef pdp_ram_0_0_0)) - (portRef ADR0 (instanceRef pdp_ram_0_0_0)) - (portRef CSW2 (instanceRef pdp_ram_0_0_0)) - (portRef CSW1 (instanceRef pdp_ram_0_0_0)) - (portRef DI35 (instanceRef pdp_ram_0_0_0)) - (portRef DI34 (instanceRef pdp_ram_0_0_0)) - (portRef DI33 (instanceRef pdp_ram_0_0_0)) - (portRef DI32 (instanceRef pdp_ram_0_0_0)) - (portRef DI31 (instanceRef pdp_ram_0_0_0)) - (portRef DI30 (instanceRef pdp_ram_0_0_0)) - (portRef DI29 (instanceRef pdp_ram_0_0_0)) - (portRef DI28 (instanceRef pdp_ram_0_0_0)) - (portRef DI25 (instanceRef pdp_ram_0_0_0)) - (portRef DI23 (instanceRef pdp_ram_0_0_0)) - (portRef DI22 (instanceRef pdp_ram_0_0_0)) - (portRef DI21 (instanceRef pdp_ram_0_0_0)) - (portRef DI20 (instanceRef pdp_ram_0_0_0)) - (portRef DI19 (instanceRef pdp_ram_0_0_0)) - (portRef DI18 (instanceRef pdp_ram_0_0_0)) - (portRef DI17 (instanceRef pdp_ram_0_0_0)) - (portRef DI16 (instanceRef pdp_ram_0_0_0)) - (portRef DI14 (instanceRef pdp_ram_0_0_0)) - (portRef DI10 (instanceRef pdp_ram_0_0_0)) - (portRef DI8 (instanceRef pdp_ram_0_0_0)) - (portRef DI7 (instanceRef pdp_ram_0_0_0)) - (portRef DI6 (instanceRef pdp_ram_0_0_0)) - (portRef DI5 (instanceRef pdp_ram_0_0_0)) - (portRef DI4 (instanceRef pdp_ram_0_0_0)) - (portRef DI3 (instanceRef pdp_ram_0_0_0)) - (portRef DI2 (instanceRef pdp_ram_0_0_0)) - (portRef DI1 (instanceRef pdp_ram_0_0_0)) - (portRef DI0 (instanceRef pdp_ram_0_0_0)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef B (instanceRef OR2_t18)) - (portRef A (instanceRef OR2_t18)) - )) - (net rRst (joined - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_1)) - (portRef CD (instanceRef FF_2)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_70)) - (portRef PD (instanceRef FF_71)) - )) - (net wcount_0 (joined - (portRef Q (instanceRef FF_101)) - (portRef A0 (instanceRef full_cmp_0)) - (portRef A0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_81)) - (portRef A (instanceRef XOR2_t17)) - )) - (net wcount_1 (joined - (portRef Q (instanceRef FF_100)) - (portRef A1 (instanceRef full_cmp_0)) - (portRef A1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_80)) - (portRef A (instanceRef XOR2_t16)) - (portRef B (instanceRef XOR2_t17)) - )) - (net w_gdata_0 (joined - (portRef Z (instanceRef XOR2_t17)) - (portRef D (instanceRef FF_91)) - )) - (net wcount_2 (joined - (portRef Q (instanceRef FF_99)) - (portRef A0 (instanceRef full_cmp_1)) - (portRef A0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_79)) - (portRef A (instanceRef XOR2_t15)) - (portRef B (instanceRef XOR2_t16)) - )) - (net w_gdata_1 (joined - (portRef Z (instanceRef XOR2_t16)) - (portRef D (instanceRef FF_90)) - )) - (net wcount_3 (joined - (portRef Q (instanceRef FF_98)) - (portRef A1 (instanceRef full_cmp_1)) - (portRef A1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_78)) - (portRef A (instanceRef XOR2_t14)) - (portRef B (instanceRef XOR2_t15)) - )) - (net w_gdata_2 (joined - (portRef Z (instanceRef XOR2_t15)) - (portRef D (instanceRef FF_89)) - )) - (net wcount_4 (joined - (portRef Q (instanceRef FF_97)) - (portRef A0 (instanceRef full_cmp_2)) - (portRef A0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_77)) - (portRef A (instanceRef XOR2_t13)) - (portRef B (instanceRef XOR2_t14)) - )) - (net w_gdata_3 (joined - (portRef Z (instanceRef XOR2_t14)) - (portRef D (instanceRef FF_88)) - )) - (net wcount_5 (joined - (portRef Q (instanceRef FF_96)) - (portRef A1 (instanceRef full_cmp_2)) - (portRef A1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_76)) - (portRef A (instanceRef XOR2_t12)) - (portRef B (instanceRef XOR2_t13)) - )) - (net w_gdata_4 (joined - (portRef Z (instanceRef XOR2_t13)) - (portRef D (instanceRef FF_87)) - )) - (net wcount_6 (joined - (portRef Q (instanceRef FF_95)) - (portRef A0 (instanceRef full_cmp_3)) - (portRef A0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_75)) - (portRef A (instanceRef XOR2_t11)) - (portRef B (instanceRef XOR2_t12)) - )) - (net w_gdata_5 (joined - (portRef Z (instanceRef XOR2_t12)) - (portRef D (instanceRef FF_86)) - )) - (net wcount_7 (joined - (portRef Q (instanceRef FF_94)) - (portRef A1 (instanceRef full_cmp_3)) - (portRef A1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_74)) - (portRef A (instanceRef XOR2_t10)) - (portRef B (instanceRef XOR2_t11)) - )) - (net w_gdata_6 (joined - (portRef Z (instanceRef XOR2_t11)) - (portRef D (instanceRef FF_85)) - )) - (net wcount_8 (joined - (portRef Q (instanceRef FF_93)) - (portRef A0 (instanceRef full_cmp_4)) - (portRef A0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_73)) - (portRef A (instanceRef XOR2_t9)) - (portRef B (instanceRef XOR2_t10)) - )) - (net w_gdata_7 (joined - (portRef Z (instanceRef XOR2_t10)) - (portRef D (instanceRef FF_84)) - )) - (net wcount_9 (joined - (portRef Q (instanceRef FF_92)) - (portRef A1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_72)) - (portRef D (instanceRef FF_82)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef B (instanceRef XOR2_t9)) - )) - (net w_gdata_8 (joined - (portRef Z (instanceRef XOR2_t9)) - (portRef D (instanceRef FF_83)) - )) - (net rcount_0 (joined - (portRef Q (instanceRef FF_71)) - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_51)) - (portRef A (instanceRef XOR2_t8)) - )) - (net rcount_1 (joined - (portRef Q (instanceRef FF_70)) - (portRef A1 (instanceRef empty_cmp_0)) - (portRef A1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_50)) - (portRef A (instanceRef XOR2_t7)) - (portRef B (instanceRef XOR2_t8)) - )) - (net r_gdata_0 (joined - (portRef Z (instanceRef XOR2_t8)) - (portRef D (instanceRef FF_61)) - )) - (net rcount_2 (joined - (portRef Q (instanceRef FF_69)) - (portRef A0 (instanceRef empty_cmp_1)) - (portRef A0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_49)) - (portRef A (instanceRef XOR2_t6)) - (portRef B (instanceRef XOR2_t7)) - )) - (net r_gdata_1 (joined - (portRef Z (instanceRef XOR2_t7)) - (portRef D (instanceRef FF_60)) - )) - (net rcount_3 (joined - (portRef Q (instanceRef FF_68)) - (portRef A1 (instanceRef empty_cmp_1)) - (portRef A1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_48)) - (portRef A (instanceRef XOR2_t5)) - (portRef B (instanceRef XOR2_t6)) - )) - (net r_gdata_2 (joined - (portRef Z (instanceRef XOR2_t6)) - (portRef D (instanceRef FF_59)) - )) - (net rcount_4 (joined - (portRef Q (instanceRef FF_67)) - (portRef A0 (instanceRef empty_cmp_2)) - (portRef A0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_47)) - (portRef A (instanceRef XOR2_t4)) - (portRef B (instanceRef XOR2_t5)) - )) - (net r_gdata_3 (joined - (portRef Z (instanceRef XOR2_t5)) - (portRef D (instanceRef FF_58)) - )) - (net rcount_5 (joined - (portRef Q (instanceRef FF_66)) - (portRef A1 (instanceRef empty_cmp_2)) - (portRef A1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_46)) - (portRef A (instanceRef XOR2_t3)) - (portRef B (instanceRef XOR2_t4)) - )) - (net r_gdata_4 (joined - (portRef Z (instanceRef XOR2_t4)) - (portRef D (instanceRef FF_57)) - )) - (net rcount_6 (joined - (portRef Q (instanceRef FF_65)) - (portRef A0 (instanceRef empty_cmp_3)) - (portRef A0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_45)) - (portRef A (instanceRef XOR2_t2)) - (portRef B (instanceRef XOR2_t3)) - )) - (net r_gdata_5 (joined - (portRef Z (instanceRef XOR2_t3)) - (portRef D (instanceRef FF_56)) - )) - (net rcount_7 (joined - (portRef Q (instanceRef FF_64)) - (portRef A1 (instanceRef empty_cmp_3)) - (portRef A1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_44)) - (portRef A (instanceRef XOR2_t1)) - (portRef B (instanceRef XOR2_t2)) - )) - (net r_gdata_6 (joined - (portRef Z (instanceRef XOR2_t2)) - (portRef D (instanceRef FF_55)) - )) - (net rcount_8 (joined - (portRef Q (instanceRef FF_63)) - (portRef A0 (instanceRef empty_cmp_4)) - (portRef A0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_43)) - (portRef A (instanceRef XOR2_t0)) - (portRef B (instanceRef XOR2_t1)) - )) - (net r_gdata_7 (joined - (portRef Z (instanceRef XOR2_t1)) - (portRef D (instanceRef FF_54)) - )) - (net rcount_9 (joined - (portRef Q (instanceRef FF_62)) - (portRef A1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_42)) - (portRef D (instanceRef FF_52)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef B (instanceRef XOR2_t0)) - )) - (net r_gdata_8 (joined - (portRef Z (instanceRef XOR2_t0)) - (portRef D (instanceRef FF_53)) - )) - (net w_gcount_r29 (joined - (portRef Q (instanceRef FF_12)) - (portRef AD1 (instanceRef LUT4_2)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_23)) - )) - (net w_gcount_r28 (joined - (portRef Q (instanceRef FF_13)) - (portRef AD2 (instanceRef LUT4_20)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_23)) - )) - (net w_gcount_r27 (joined - (portRef Q (instanceRef FF_14)) - (portRef AD1 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_23)) - )) - (net w_gcount_r26 (joined - (portRef Q (instanceRef FF_15)) - (portRef AD1 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_23)) - )) - (net w_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_23)) - (portRef B0 (instanceRef empty_cmp_3)) - (portRef AD3 (instanceRef LUT4_14)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_17)) - )) - (net w_gcount_r25 (joined - (portRef Q (instanceRef FF_16)) - (portRef AD1 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD0 (instanceRef LUT4_22)) - )) - (net w_gcount_r24 (joined - (portRef Q (instanceRef FF_17)) - (portRef AD2 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_22)) - )) - (net w_gcount_r23 (joined - (portRef Q (instanceRef FF_18)) - (portRef AD3 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_22)) - )) - (net w_gcount_r22 (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)) - )) - (net w_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_14)) - (portRef AD2 (instanceRef LUT4_15)) - (portRef AD2 (instanceRef LUT4_16)) - )) - (net wcount_r8 (joined - (portRef DO0 (instanceRef LUT4_21)) - (portRef B0 (instanceRef empty_cmp_4)) - (portRef AD0 (instanceRef LUT4_19)) - )) - (net wcount_r7 (joined - (portRef DO0 (instanceRef LUT4_20)) - (portRef B1 (instanceRef empty_cmp_3)) - (portRef AD0 (instanceRef LUT4_18)) - )) - (net wcount_r5 (joined - (portRef DO0 (instanceRef LUT4_19)) - (portRef B1 (instanceRef empty_cmp_2)) - )) - (net wcount_r4 (joined - (portRef DO0 (instanceRef LUT4_18)) - (portRef B0 (instanceRef empty_cmp_2)) - )) - (net wcount_r3 (joined - (portRef DO0 (instanceRef LUT4_17)) - (portRef B1 (instanceRef empty_cmp_1)) - )) - (net wcount_r2 (joined - (portRef DO0 (instanceRef LUT4_16)) - (portRef B0 (instanceRef empty_cmp_1)) - )) - (net w_gcount_r21 (joined - (portRef Q (instanceRef FF_20)) - (portRef AD0 (instanceRef LUT4_14)) - (portRef AD1 (instanceRef LUT4_15)) - )) - (net wcount_r1 (joined - (portRef DO0 (instanceRef LUT4_15)) - (portRef B1 (instanceRef empty_cmp_0)) - )) - (net w_gcount_r20 (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)) - )) - (net wcount_r0 (joined - (portRef DO0 (instanceRef LUT4_14)) - (portRef B0 (instanceRef empty_cmp_0)) - )) - (net r_gcount_w29 (joined - (portRef Q (instanceRef FF_2)) - (portRef AD1 (instanceRef LUT4_0)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_13)) - )) - (net r_gcount_w28 (joined - (portRef Q (instanceRef FF_3)) - (portRef AD2 (instanceRef LUT4_10)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_13)) - )) - (net r_gcount_w27 (joined - (portRef Q (instanceRef FF_4)) - (portRef AD1 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_13)) - )) - (net r_gcount_w26 (joined - (portRef Q (instanceRef FF_5)) - (portRef AD1 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_13)) - )) - (net r_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_13)) - (portRef B0 (instanceRef full_cmp_3)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_7)) - )) - (net r_gcount_w25 (joined - (portRef Q (instanceRef FF_6)) - (portRef AD1 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_12)) - )) - (net r_gcount_w24 (joined - (portRef Q (instanceRef FF_7)) - (portRef AD2 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_12)) - )) - (net r_gcount_w23 (joined - (portRef Q (instanceRef FF_8)) - (portRef AD3 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_12)) - )) - (net r_gcount_w22 (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)) - )) - (net r_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_4)) - (portRef AD2 (instanceRef LUT4_5)) - (portRef AD2 (instanceRef LUT4_6)) - )) - (net rcount_w8 (joined - (portRef DO0 (instanceRef LUT4_11)) - (portRef B0 (instanceRef full_cmp_4)) - (portRef AD0 (instanceRef LUT4_9)) - )) - (net rcount_w7 (joined - (portRef DO0 (instanceRef LUT4_10)) - (portRef B1 (instanceRef full_cmp_3)) - (portRef AD0 (instanceRef LUT4_8)) - )) - (net rcount_w5 (joined - (portRef DO0 (instanceRef LUT4_9)) - (portRef B1 (instanceRef full_cmp_2)) - )) - (net rcount_w4 (joined - (portRef DO0 (instanceRef LUT4_8)) - (portRef B0 (instanceRef full_cmp_2)) - )) - (net rcount_w3 (joined - (portRef DO0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef full_cmp_1)) - )) - (net rcount_w2 (joined - (portRef DO0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef full_cmp_1)) - )) - (net r_gcount_w21 (joined - (portRef Q (instanceRef FF_10)) - (portRef AD0 (instanceRef LUT4_4)) - (portRef AD1 (instanceRef LUT4_5)) - )) - (net rcount_w1 (joined - (portRef DO0 (instanceRef LUT4_5)) - (portRef B1 (instanceRef full_cmp_0)) - )) - (net r_gcount_w20 (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)) - )) - (net rcount_w0 (joined - (portRef DO0 (instanceRef LUT4_4)) - (portRef B0 (instanceRef full_cmp_0)) - )) - (net rptr_9 (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_2)) - (portRef AD3 (instanceRef LUT4_3)) - )) - (net empty_cmp_set (joined - (portRef DO0 (instanceRef LUT4_3)) - (portRef A1 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_2)) - (portRef B1 (instanceRef empty_cmp_4)) - )) - (net wptr_9 (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_0)) - (portRef AD3 (instanceRef LUT4_1)) - )) - (net full_cmp_set (joined - (portRef DO0 (instanceRef LUT4_1)) - (portRef A1 (instanceRef full_cmp_4)) - )) - (net full_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_0)) - (portRef B1 (instanceRef full_cmp_4)) - )) - (net (rename fifo_in_data_0 "fifo_in_data[9]") (joined - (portRef fifo_in_data_0) - (portRef DI27 (instanceRef pdp_ram_0_0_0)) - (portRef DI26 (instanceRef pdp_ram_0_0_0)) - (portRef DI24 (instanceRef pdp_ram_0_0_0)) - (portRef DI15 (instanceRef pdp_ram_0_0_0)) - (portRef DI13 (instanceRef pdp_ram_0_0_0)) - (portRef DI12 (instanceRef pdp_ram_0_0_0)) - (portRef DI11 (instanceRef pdp_ram_0_0_0)) - (portRef DI9 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_0 (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_1 (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_2 (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_3 (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_4 (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_5 (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_6 (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_7 (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_0)) - )) - (net wptr_8 (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef a1)) - (portRef C1 (instanceRef a1)) - (portRef D0 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef a0)) - (portRef C1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef CSW0 (instanceRef pdp_ram_0_0_0)) - (portRef BE3 (instanceRef pdp_ram_0_0_0)) - (portRef BE2 (instanceRef pdp_ram_0_0_0)) - (portRef BE1 (instanceRef pdp_ram_0_0_0)) - (portRef BE0 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef CK (instanceRef FF_0)) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_71)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_101)) - (portRef CLKR (instanceRef pdp_ram_0_0_0)) - (portRef CLKW (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_0 (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_1 (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_2 (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_3 (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_4 (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_5 (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_6 (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_7 (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_0)) - )) - (net rptr_8 (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef DO0 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef DO1 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef DO2 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef DO3 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef DO4 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef DO5 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename Q_1_24 "Q_1[24]") (joined - (portRef DO6 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_25 "Q_1[25]") (joined - (portRef DO7 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_26 "Q_1[26]") (joined - (portRef DO8 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_27 "Q_1[27]") (joined - (portRef DO9 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_28 "Q_1[28]") (joined - (portRef DO10 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_29 "Q_1[29]") (joined - (portRef DO11 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_30 "Q_1[30]") (joined - (portRef DO12 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename Q_1_31 "Q_1[31]") (joined - (portRef DO13 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO14 (joined - (portRef DO14 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO15 (joined - (portRef DO15 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO16 (joined - (portRef DO16 (instanceRef pdp_ram_0_0_0)) - )) - (net pdp_ram_0_0_0_DO17 (joined - (portRef DO17 (instanceRef pdp_ram_0_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef DO18 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef DO19 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef DO20 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef DO21 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef DO22 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef DO23 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef DO24 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef DO25 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef DO26 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef DO27 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef DO28 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef DO29 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef DO30 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef DO31 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef DO32 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef DO33 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef DO34 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef DO35 (instanceRef pdp_ram_0_0_0)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net iwcount_0 (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)) - )) - (net iwcount_1 (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)) - )) - (net iwcount_2 (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)) - )) - (net iwcount_3 (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)) - )) - (net iwcount_4 (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)) - )) - (net iwcount_5 (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)) - )) - (net iwcount_6 (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)) - )) - (net iwcount_7 (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)) - )) - (net iwcount_8 (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)) - )) - (net iwcount_9 (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)) - )) - (net w_gcount_0 (joined - (portRef Q (instanceRef FF_91)) - (portRef D (instanceRef FF_41)) - )) - (net w_gcount_1 (joined - (portRef Q (instanceRef FF_90)) - (portRef D (instanceRef FF_40)) - )) - (net w_gcount_2 (joined - (portRef Q (instanceRef FF_89)) - (portRef D (instanceRef FF_39)) - )) - (net w_gcount_3 (joined - (portRef Q (instanceRef FF_88)) - (portRef D (instanceRef FF_38)) - )) - (net w_gcount_4 (joined - (portRef Q (instanceRef FF_87)) - (portRef D (instanceRef FF_37)) - )) - (net w_gcount_5 (joined - (portRef Q (instanceRef FF_86)) - (portRef D (instanceRef FF_36)) - )) - (net w_gcount_6 (joined - (portRef Q (instanceRef FF_85)) - (portRef D (instanceRef FF_35)) - )) - (net w_gcount_7 (joined - (portRef Q (instanceRef FF_84)) - (portRef D (instanceRef FF_34)) - )) - (net w_gcount_8 (joined - (portRef Q (instanceRef FF_83)) - (portRef D (instanceRef FF_33)) - )) - (net w_gcount_9 (joined - (portRef Q (instanceRef FF_82)) - (portRef D (instanceRef FF_32)) - )) - (net ircount_0 (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)) - )) - (net ircount_1 (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)) - )) - (net ircount_2 (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)) - )) - (net ircount_3 (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)) - )) - (net ircount_4 (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)) - )) - (net ircount_5 (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)) - )) - (net ircount_6 (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)) - )) - (net ircount_7 (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)) - )) - (net ircount_8 (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)) - )) - (net ircount_9 (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)) - )) - (net r_gcount_0 (joined - (portRef Q (instanceRef FF_61)) - (portRef D (instanceRef FF_31)) - )) - (net r_gcount_1 (joined - (portRef Q (instanceRef FF_60)) - (portRef D (instanceRef FF_30)) - )) - (net r_gcount_2 (joined - (portRef Q (instanceRef FF_59)) - (portRef D (instanceRef FF_29)) - )) - (net r_gcount_3 (joined - (portRef Q (instanceRef FF_58)) - (portRef D (instanceRef FF_28)) - )) - (net r_gcount_4 (joined - (portRef Q (instanceRef FF_57)) - (portRef D (instanceRef FF_27)) - )) - (net r_gcount_5 (joined - (portRef Q (instanceRef FF_56)) - (portRef D (instanceRef FF_26)) - )) - (net r_gcount_6 (joined - (portRef Q (instanceRef FF_55)) - (portRef D (instanceRef FF_25)) - )) - (net r_gcount_7 (joined - (portRef Q (instanceRef FF_54)) - (portRef D (instanceRef FF_24)) - )) - (net r_gcount_8 (joined - (portRef Q (instanceRef FF_53)) - (portRef D (instanceRef FF_23)) - )) - (net r_gcount_9 (joined - (portRef Q (instanceRef FF_52)) - (portRef D (instanceRef FF_22)) - )) - (net w_gcount_r0 (joined - (portRef Q (instanceRef FF_41)) - (portRef D (instanceRef FF_21)) - )) - (net w_gcount_r1 (joined - (portRef Q (instanceRef FF_40)) - (portRef D (instanceRef FF_20)) - )) - (net w_gcount_r2 (joined - (portRef Q (instanceRef FF_39)) - (portRef D (instanceRef FF_19)) - )) - (net w_gcount_r3 (joined - (portRef Q (instanceRef FF_38)) - (portRef D (instanceRef FF_18)) - )) - (net w_gcount_r4 (joined - (portRef Q (instanceRef FF_37)) - (portRef D (instanceRef FF_17)) - )) - (net w_gcount_r5 (joined - (portRef Q (instanceRef FF_36)) - (portRef D (instanceRef FF_16)) - )) - (net w_gcount_r6 (joined - (portRef Q (instanceRef FF_35)) - (portRef D (instanceRef FF_15)) - )) - (net w_gcount_r7 (joined - (portRef Q (instanceRef FF_34)) - (portRef D (instanceRef FF_14)) - )) - (net w_gcount_r8 (joined - (portRef Q (instanceRef FF_33)) - (portRef D (instanceRef FF_13)) - )) - (net w_gcount_r9 (joined - (portRef Q (instanceRef FF_32)) - (portRef D (instanceRef FF_12)) - )) - (net r_gcount_w0 (joined - (portRef Q (instanceRef FF_31)) - (portRef D (instanceRef FF_11)) - )) - (net r_gcount_w1 (joined - (portRef Q (instanceRef FF_30)) - (portRef D (instanceRef FF_10)) - )) - (net r_gcount_w2 (joined - (portRef Q (instanceRef FF_29)) - (portRef D (instanceRef FF_9)) - )) - (net r_gcount_w3 (joined - (portRef Q (instanceRef FF_28)) - (portRef D (instanceRef FF_8)) - )) - (net r_gcount_w4 (joined - (portRef Q (instanceRef FF_27)) - (portRef D (instanceRef FF_7)) - )) - (net r_gcount_w5 (joined - (portRef Q (instanceRef FF_26)) - (portRef D (instanceRef FF_6)) - )) - (net r_gcount_w6 (joined - (portRef Q (instanceRef FF_25)) - (portRef D (instanceRef FF_5)) - )) - (net r_gcount_w7 (joined - (portRef Q (instanceRef FF_24)) - (portRef D (instanceRef FF_4)) - )) - (net r_gcount_w8 (joined - (portRef Q (instanceRef FF_23)) - (portRef D (instanceRef FF_3)) - )) - (net r_gcount_w9 (joined - (portRef Q (instanceRef FF_22)) - (portRef D (instanceRef FF_2)) - )) - (net empty_d (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)) - )) - (net full_d (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)) - )) - (net w_gctr_ci (joined - (portRef COUT (instanceRef w_gctr_cia)) - (portRef CIN (instanceRef w_gctr_0)) - )) - (net w_gctr_cia_S0 (joined - (portRef S0 (instanceRef w_gctr_cia)) - )) - (net w_gctr_cia_S1 (joined - (portRef S1 (instanceRef w_gctr_cia)) - )) - (net co0 (joined - (portRef COUT (instanceRef w_gctr_0)) - (portRef CIN (instanceRef w_gctr_1)) - )) - (net co1 (joined - (portRef COUT (instanceRef w_gctr_1)) - (portRef CIN (instanceRef w_gctr_2)) - )) - (net co2 (joined - (portRef COUT (instanceRef w_gctr_2)) - (portRef CIN (instanceRef w_gctr_3)) - )) - (net co3 (joined - (portRef COUT (instanceRef w_gctr_3)) - (portRef CIN (instanceRef w_gctr_4)) - )) - (net co4 (joined - (portRef COUT (instanceRef w_gctr_4)) - )) - (net r_gctr_ci (joined - (portRef COUT (instanceRef r_gctr_cia)) - (portRef CIN (instanceRef r_gctr_0)) - )) - (net r_gctr_cia_S0 (joined - (portRef S0 (instanceRef r_gctr_cia)) - )) - (net r_gctr_cia_S1 (joined - (portRef S1 (instanceRef r_gctr_cia)) - )) - (net co0_1 (joined - (portRef COUT (instanceRef r_gctr_0)) - (portRef CIN (instanceRef r_gctr_1)) - )) - (net co1_1 (joined - (portRef COUT (instanceRef r_gctr_1)) - (portRef CIN (instanceRef r_gctr_2)) - )) - (net co2_1 (joined - (portRef COUT (instanceRef r_gctr_2)) - (portRef CIN (instanceRef r_gctr_3)) - )) - (net co3_1 (joined - (portRef COUT (instanceRef r_gctr_3)) - (portRef CIN (instanceRef r_gctr_4)) - )) - (net co4_1 (joined - (portRef COUT (instanceRef r_gctr_4)) - )) - (net cmp_ci (joined - (portRef COUT (instanceRef empty_cmp_ci_a)) - (portRef CIN (instanceRef empty_cmp_0)) - )) - (net empty_cmp_ci_a_S0 (joined - (portRef S0 (instanceRef empty_cmp_ci_a)) - )) - (net empty_cmp_ci_a_S1 (joined - (portRef S1 (instanceRef empty_cmp_ci_a)) - )) - (net co0_2 (joined - (portRef COUT (instanceRef empty_cmp_0)) - (portRef CIN (instanceRef empty_cmp_1)) - )) - (net empty_cmp_0_S0 (joined - (portRef S0 (instanceRef empty_cmp_0)) - )) - (net empty_cmp_0_S1 (joined - (portRef S1 (instanceRef empty_cmp_0)) - )) - (net co1_2 (joined - (portRef COUT (instanceRef empty_cmp_1)) - (portRef CIN (instanceRef empty_cmp_2)) - )) - (net empty_cmp_1_S0 (joined - (portRef S0 (instanceRef empty_cmp_1)) - )) - (net empty_cmp_1_S1 (joined - (portRef S1 (instanceRef empty_cmp_1)) - )) - (net co2_2 (joined - (portRef COUT (instanceRef empty_cmp_2)) - (portRef CIN (instanceRef empty_cmp_3)) - )) - (net empty_cmp_2_S0 (joined - (portRef S0 (instanceRef empty_cmp_2)) - )) - (net empty_cmp_2_S1 (joined - (portRef S1 (instanceRef empty_cmp_2)) - )) - (net co3_2 (joined - (portRef COUT (instanceRef empty_cmp_3)) - (portRef CIN (instanceRef empty_cmp_4)) - )) - (net empty_cmp_3_S0 (joined - (portRef S0 (instanceRef empty_cmp_3)) - )) - (net empty_cmp_3_S1 (joined - (portRef S1 (instanceRef empty_cmp_3)) - )) - (net empty_d_c (joined - (portRef COUT (instanceRef empty_cmp_4)) - (portRef CIN (instanceRef a0)) - )) - (net empty_cmp_4_S0 (joined - (portRef S0 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_4_S1 (joined - (portRef S1 (instanceRef empty_cmp_4)) - )) - (net a0_COUT (joined - (portRef COUT (instanceRef a0)) - )) - (net a0_S1 (joined - (portRef S1 (instanceRef a0)) - )) - (net cmp_ci_1 (joined - (portRef COUT (instanceRef full_cmp_ci_a)) - (portRef CIN (instanceRef full_cmp_0)) - )) - (net full_cmp_ci_a_S0 (joined - (portRef S0 (instanceRef full_cmp_ci_a)) - )) - (net full_cmp_ci_a_S1 (joined - (portRef S1 (instanceRef full_cmp_ci_a)) - )) - (net co0_3 (joined - (portRef COUT (instanceRef full_cmp_0)) - (portRef CIN (instanceRef full_cmp_1)) - )) - (net full_cmp_0_S0 (joined - (portRef S0 (instanceRef full_cmp_0)) - )) - (net full_cmp_0_S1 (joined - (portRef S1 (instanceRef full_cmp_0)) - )) - (net co1_3 (joined - (portRef COUT (instanceRef full_cmp_1)) - (portRef CIN (instanceRef full_cmp_2)) - )) - (net full_cmp_1_S0 (joined - (portRef S0 (instanceRef full_cmp_1)) - )) - (net full_cmp_1_S1 (joined - (portRef S1 (instanceRef full_cmp_1)) - )) - (net co2_3 (joined - (portRef COUT (instanceRef full_cmp_2)) - (portRef CIN (instanceRef full_cmp_3)) - )) - (net full_cmp_2_S0 (joined - (portRef S0 (instanceRef full_cmp_2)) - )) - (net full_cmp_2_S1 (joined - (portRef S1 (instanceRef full_cmp_2)) - )) - (net co3_3 (joined - (portRef COUT (instanceRef full_cmp_3)) - (portRef CIN (instanceRef full_cmp_4)) - )) - (net full_cmp_3_S0 (joined - (portRef S0 (instanceRef full_cmp_3)) - )) - (net full_cmp_3_S1 (joined - (portRef S1 (instanceRef full_cmp_3)) - )) - (net full_d_c (joined - (portRef COUT (instanceRef full_cmp_4)) - (portRef CIN (instanceRef a1)) - )) - (net full_cmp_4_S0 (joined - (portRef S0 (instanceRef full_cmp_4)) - )) - (net full_cmp_4_S1 (joined - (portRef S1 (instanceRef full_cmp_4)) - )) - (net a1_COUT (joined - (portRef COUT (instanceRef a1)) - )) - (net a1_S1 (joined - (portRef S1 (instanceRef a1)) - )) - (net CIN (joined - (portRef CIN (instanceRef full_cmp_ci_a)) - )) - (net CIN_0 (joined - (portRef CIN (instanceRef empty_cmp_ci_a)) - )) - (net CIN_1 (joined - (portRef CIN (instanceRef r_gctr_cia)) - )) - (net CIN_2 (joined - (portRef CIN (instanceRef w_gctr_cia)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "fifo32dc")) - ) - ) - (cell output_decoder8_2 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction INPUT)) - (port decoder_valid (direction OUTPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance valid_internal (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance valid (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_0 "in_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_1 "in_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_2 "in_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_3 "in_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_4 "in_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_5 "in_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_6 "in_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_synced_7 "in_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__0 "dl[1][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__1 "dl[1][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__2 "dl[1][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__3 "dl[1][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__4 "dl[1][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__5 "dl[1][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__6 "dl[1][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_1__7 "dl[1][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__0 "dl[0][0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__1 "dl[0][1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__2 "dl[0][2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__3 "dl[0][3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__4 "dl[0][4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__5 "dl[0][5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__6 "dl[0][6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename dl_0__7 "dl[0][7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance valid_internal_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C (B+!A)))")) - ) - (instance un1_out_internal35_1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B+!A))+D (!C (B+!A)+C !A))")) - ) - (instance valid_internal_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance un1_out_internal35_1_0_m4_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A)+C (B+!A))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net N_352_i (joined - (portRef Z (instanceRef valid_internal_RNO)) - (portRef D (instanceRef valid_internal)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef dl_0__7)) - (portRef CK (instanceRef dl_0__6)) - (portRef CK (instanceRef dl_0__5)) - (portRef CK (instanceRef dl_0__4)) - (portRef CK (instanceRef dl_0__3)) - (portRef CK (instanceRef dl_0__2)) - (portRef CK (instanceRef dl_0__1)) - (portRef CK (instanceRef dl_0__0)) - (portRef CK (instanceRef dl_1__7)) - (portRef CK (instanceRef dl_1__6)) - (portRef CK (instanceRef dl_1__5)) - (portRef CK (instanceRef dl_1__4)) - (portRef CK (instanceRef dl_1__3)) - (portRef CK (instanceRef dl_1__2)) - (portRef CK (instanceRef dl_1__1)) - (portRef CK (instanceRef dl_1__0)) - (portRef CK (instanceRef in_synced_7)) - (portRef CK (instanceRef in_synced_6)) - (portRef CK (instanceRef in_synced_5)) - (portRef CK (instanceRef in_synced_4)) - (portRef CK (instanceRef in_synced_3)) - (portRef CK (instanceRef in_synced_2)) - (portRef CK (instanceRef in_synced_1)) - (portRef CK (instanceRef in_synced_0)) - (portRef CK (instanceRef valid)) - (portRef CK (instanceRef valid_internal)) - )) - (net in_synced7_rising_i (joined - (portRef Z (instanceRef valid_internal_RNO_0)) - (portRef CD (instanceRef valid_internal)) - )) - (net valid_internal (joined - (portRef Q (instanceRef valid_internal)) - (portRef D (instanceRef valid)) - )) - (net decoder_valid (joined - (portRef Q (instanceRef valid)) - (portRef decoder_valid) - )) - (net (rename dl_1__0 "dl[1][0]") (joined - (portRef Q (instanceRef dl_1__0)) - (portRef D (instanceRef in_synced_0)) - )) - (net (rename in_synced_0 "in_synced[0]") (joined - (portRef Q (instanceRef in_synced_0)) - (portRef A (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__1 "dl[1][1]") (joined - (portRef Q (instanceRef dl_1__1)) - (portRef D (instanceRef in_synced_1)) - )) - (net (rename in_synced_1 "in_synced[1]") (joined - (portRef Q (instanceRef in_synced_1)) - (portRef B (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__2 "dl[1][2]") (joined - (portRef Q (instanceRef dl_1__2)) - (portRef D (instanceRef in_synced_2)) - )) - (net (rename in_synced_2 "in_synced[2]") (joined - (portRef Q (instanceRef in_synced_2)) - (portRef A (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef C (instanceRef valid_internal_RNO)) - )) - (net (rename dl_1__3 "dl[1][3]") (joined - (portRef Q (instanceRef dl_1__3)) - (portRef D (instanceRef in_synced_3)) - )) - (net (rename in_synced_3 "in_synced[3]") (joined - (portRef Q (instanceRef in_synced_3)) - (portRef B (instanceRef un1_out_internal35_1_0_m4_0)) - )) - (net (rename dl_1__4 "dl[1][4]") (joined - (portRef Q (instanceRef dl_1__4)) - (portRef D (instanceRef in_synced_4)) - )) - (net (rename in_synced_4 "in_synced[4]") (joined - (portRef Q (instanceRef in_synced_4)) - (portRef C (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef B (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__5 "dl[1][5]") (joined - (portRef Q (instanceRef dl_1__5)) - (portRef D (instanceRef in_synced_5)) - )) - (net (rename in_synced_5 "in_synced[5]") (joined - (portRef Q (instanceRef in_synced_5)) - (portRef C (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__6 "dl[1][6]") (joined - (portRef Q (instanceRef dl_1__6)) - (portRef D (instanceRef in_synced_6)) - )) - (net (rename in_synced_6 "in_synced[6]") (joined - (portRef Q (instanceRef in_synced_6)) - (portRef D (instanceRef un1_out_internal35_1_0_0)) - )) - (net (rename dl_1__7 "dl[1][7]") (joined - (portRef Q (instanceRef dl_1__7)) - (portRef A (instanceRef valid_internal_RNO_0)) - (portRef D (instanceRef in_synced_7)) - )) - (net (rename in_synced_7 "in_synced[7]") (joined - (portRef Q (instanceRef in_synced_7)) - (portRef B (instanceRef valid_internal_RNO_0)) - )) - (net (rename dl_0__0 "dl[0][0]") (joined - (portRef Q (instanceRef dl_0__0)) - (portRef D (instanceRef dl_1__0)) - )) - (net (rename dl_0__1 "dl[0][1]") (joined - (portRef Q (instanceRef dl_0__1)) - (portRef D (instanceRef dl_1__1)) - )) - (net (rename dl_0__2 "dl[0][2]") (joined - (portRef Q (instanceRef dl_0__2)) - (portRef D (instanceRef dl_1__2)) - )) - (net (rename dl_0__3 "dl[0][3]") (joined - (portRef Q (instanceRef dl_0__3)) - (portRef D (instanceRef dl_1__3)) - )) - (net (rename dl_0__4 "dl[0][4]") (joined - (portRef Q (instanceRef dl_0__4)) - (portRef D (instanceRef dl_1__4)) - )) - (net (rename dl_0__5 "dl[0][5]") (joined - (portRef Q (instanceRef dl_0__5)) - (portRef D (instanceRef dl_1__5)) - )) - (net (rename dl_0__6 "dl[0][6]") (joined - (portRef Q (instanceRef dl_0__6)) - (portRef D (instanceRef dl_1__6)) - )) - (net (rename dl_0__7 "dl[0][7]") (joined - (portRef Q (instanceRef dl_0__7)) - (portRef D (instanceRef dl_1__7)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7)) - (portRef D (instanceRef dl_0__0)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6)) - (portRef D (instanceRef dl_0__1)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5)) - (portRef D (instanceRef dl_0__2)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4)) - (portRef D (instanceRef dl_0__3)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3)) - (portRef D (instanceRef dl_0__4)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2)) - (portRef D (instanceRef dl_0__5)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1)) - (portRef D (instanceRef dl_0__6)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0)) - (portRef D (instanceRef dl_0__7)) - )) - (net un1_out_internal35_1_0_0 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_0)) - (portRef D (instanceRef valid_internal_RNO)) - )) - (net N_42 (joined - (portRef Z (instanceRef un1_out_internal35_1_0_m4_0)) - (portRef A (instanceRef un1_out_internal35_1_0_0)) - )) - ) - (property orig_inst_of (string "output_decoder8")) - ) - ) - (cell tdc4ddr_short_2 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename tdc_out "tdc_out[7:0]") 8) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port trig_c_i_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename genblk1_3__out_buffered_3 "genblk1[3].out_buffered[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_3 "genblk1[3].out_buffered1[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered1_7 "genblk1[3].out_buffered1[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__out_buffered_7 "genblk1[3].out_buffered[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_3 "genblk1[3].in_clk_synced[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_3__in_clk_synced_7 "genblk1[3].in_clk_synced[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_2 "genblk1[2].out_buffered1[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_2 "genblk1[2].out_buffered[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered_6 "genblk1[2].out_buffered[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__out_buffered1_6 "genblk1[2].out_buffered1[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_2 "genblk1[2].in_clk_synced[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_2__in_clk_synced_6 "genblk1[2].in_clk_synced[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_1 "genblk1[1].out_buffered1[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_1 "genblk1[1].out_buffered[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered_5 "genblk1[1].out_buffered[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__out_buffered1_5 "genblk1[1].out_buffered1[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_1 "genblk1[1].in_clk_synced[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_1__in_clk_synced_5 "genblk1[1].in_clk_synced[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_0 "genblk1[0].out_buffered[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_0 "genblk1[0].out_buffered1[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered1_4 "genblk1[0].out_buffered1[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__out_buffered_4 "genblk1[0].out_buffered[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_0 "genblk1[0].in_clk_synced[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename genblk1_0__in_clk_synced_4 "genblk1[0].in_clk_synced[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename out_buffered1_3 "out_buffered1[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_3)) - (portRef D (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CK (instanceRef genblk1_3__in_clk_synced_3)) - (portRef CK (instanceRef genblk1_3__out_buffered1_3)) - (portRef CK (instanceRef genblk1_3__out_buffered_3)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_3)) - (portRef (member tdc_out 4)) - )) - (net (rename in_clk_synced_3 "in_clk_synced[3]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_3)) - (portRef D (instanceRef genblk1_3__out_buffered1_3)) - )) - (net (rename in_clk_synced_7 "in_clk_synced[7]") (joined - (portRef Q (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__out_buffered1_7)) - )) - (net CN (joined - (portRef CN) - (portRef CK (instanceRef genblk1_3__in_clk_synced_7)) - (portRef CK (instanceRef genblk1_3__out_buffered_7)) - (portRef CK (instanceRef genblk1_3__out_buffered1_7)) - )) - (net (rename out_buffered1_7 "out_buffered1[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered1_7)) - (portRef D (instanceRef genblk1_3__out_buffered_7)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef Q (instanceRef genblk1_3__out_buffered_7)) - (portRef (member tdc_out 0)) - )) - (net (rename trig_c_i_0 "trig_c_i[0]") (joined - (portRef trig_c_i_0) - (portRef D (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_3__in_clk_synced_7)) - (portRef D (instanceRef genblk1_3__in_clk_synced_3)) - )) - (net (rename in_clk_synced_2 "in_clk_synced[2]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_2)) - (portRef D (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CK (instanceRef genblk1_2__in_clk_synced_2)) - (portRef CK (instanceRef genblk1_2__out_buffered_2)) - (portRef CK (instanceRef genblk1_2__out_buffered1_2)) - )) - (net (rename out_buffered1_2 "out_buffered1[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_2)) - (portRef D (instanceRef genblk1_2__out_buffered_2)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_2)) - (portRef (member tdc_out 5)) - )) - (net (rename out_buffered1_6 "out_buffered1[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered1_6)) - (portRef D (instanceRef genblk1_2__out_buffered_6)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CK (instanceRef genblk1_2__in_clk_synced_6)) - (portRef CK (instanceRef genblk1_2__out_buffered1_6)) - (portRef CK (instanceRef genblk1_2__out_buffered_6)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef Q (instanceRef genblk1_2__out_buffered_6)) - (portRef (member tdc_out 1)) - )) - (net (rename in_clk_synced_6 "in_clk_synced[6]") (joined - (portRef Q (instanceRef genblk1_2__in_clk_synced_6)) - (portRef D (instanceRef genblk1_2__out_buffered1_6)) - )) - (net (rename in_clk_synced_1 "in_clk_synced[1]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_1)) - (portRef D (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CK (instanceRef genblk1_1__in_clk_synced_1)) - (portRef CK (instanceRef genblk1_1__out_buffered_1)) - (portRef CK (instanceRef genblk1_1__out_buffered1_1)) - )) - (net (rename out_buffered1_1 "out_buffered1[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_1)) - (portRef D (instanceRef genblk1_1__out_buffered_1)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_1)) - (portRef (member tdc_out 6)) - )) - (net (rename out_buffered1_5 "out_buffered1[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered1_5)) - (portRef D (instanceRef genblk1_1__out_buffered_5)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CK (instanceRef genblk1_1__in_clk_synced_5)) - (portRef CK (instanceRef genblk1_1__out_buffered1_5)) - (portRef CK (instanceRef genblk1_1__out_buffered_5)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef Q (instanceRef genblk1_1__out_buffered_5)) - (portRef (member tdc_out 2)) - )) - (net (rename in_clk_synced_5 "in_clk_synced[5]") (joined - (portRef Q (instanceRef genblk1_1__in_clk_synced_5)) - (portRef D (instanceRef genblk1_1__out_buffered1_5)) - )) - (net (rename out_buffered1_0 "out_buffered1[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_0)) - (portRef D (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef CK (instanceRef genblk1_0__in_clk_synced_0)) - (portRef CK (instanceRef genblk1_0__out_buffered1_0)) - (portRef CK (instanceRef genblk1_0__out_buffered_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_0)) - (portRef (member tdc_out 7)) - )) - (net (rename in_clk_synced_0 "in_clk_synced[0]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_0)) - (portRef D (instanceRef genblk1_0__out_buffered1_0)) - )) - (net (rename in_clk_synced_4 "in_clk_synced[4]") (joined - (portRef Q (instanceRef genblk1_0__in_clk_synced_4)) - (portRef D (instanceRef genblk1_0__out_buffered1_4)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CK (instanceRef genblk1_0__in_clk_synced_4)) - (portRef CK (instanceRef genblk1_0__out_buffered_4)) - (portRef CK (instanceRef genblk1_0__out_buffered1_4)) - )) - (net (rename out_buffered1_4 "out_buffered1[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered1_4)) - (portRef D (instanceRef genblk1_0__out_buffered_4)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef Q (instanceRef genblk1_0__out_buffered_4)) - (portRef (member tdc_out 3)) - )) - ) - (property orig_inst_of (string "tdc4ddr_short")) - ) - ) - (cell fifo40_dc (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename fee_data_out_c "FEE_DATA_OUT_c[31:0]") 32) (direction OUTPUT)) - (port pll_clks_0 (direction INPUT)) - (port (array (rename data_buffer "data_buffer[33:0]") 34) (direction INPUT)) - (port rd_clk_c (direction INPUT)) - (port last_buf_empty_c (direction OUTPUT)) - (port fifo_rden_c (direction INPUT)) - (port buffer_wr_enable (direction INPUT)) - ) - (contents - (instance AND2_t20 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_1 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance AND2_t19 (viewRef PRIM (cellRef AND2 (libraryRef LUCENT))) - ) - (instance INV_0 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) - ) - (instance OR2_t18 (viewRef PRIM (cellRef OR2 (libraryRef LUCENT))) - ) - (instance XOR2_t17 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t16 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t15 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t14 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t13 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t12 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t11 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t10 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t9 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t8 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t7 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t6 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t5 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t4 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t3 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t2 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t1 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance XOR2_t0 (viewRef PRIM (cellRef XOR2 (libraryRef LUCENT))) - ) - (instance LUT4_23 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_22 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_21 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_20 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_19 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_18 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_17 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_16 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_15 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_14 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_13 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_12 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_11 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_10 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_9 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_8 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_7 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_6 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_5 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_4 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x6996")) - ) - (instance LUT4_3 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0410")) - ) - (instance LUT4_2 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x1004")) - ) - (instance LUT4_1 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x0140")) - ) - (instance LUT4_0 (viewRef PRIM (cellRef ROM16X1A (libraryRef LUCENT))) - (property initval (string "0x4001")) - ) - (instance pdp_ram_0_0_1 (viewRef PRIM (cellRef PDPW16KD (libraryRef LUCENT))) - (property MEM_LPC_FILE (string "fifo40_dc.lpc")) - (property MEM_INIT_FILE (string "")) - (property DATA_WIDTH_W (integer 36)) - (property DATA_WIDTH_R (integer 36)) - (property REGMODE (string "NOREG")) - (property RESETMODE (string "ASYNC")) - (property GSR (string "ENABLED")) - (property CSDECODE_W (string "0b001")) - (property CSDECODE_R (string "0b000")) - (property ASYNC_RESET_RELEASE (string "SYNC")) - (property INIT_DATA (string "STATIC")) - ) - (instance FF_101 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_100 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_99 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_98 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_97 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_96 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_95 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_94 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_93 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_92 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_91 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_90 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_89 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_88 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_87 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_86 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_85 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_84 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_83 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_82 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_81 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_80 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_79 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_78 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_77 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_76 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_75 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_74 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_73 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_72 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_71 (viewRef PRIM (cellRef FD1P3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_70 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_69 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_68 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_67 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_66 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_65 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_64 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_63 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_62 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_61 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_60 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_59 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_58 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_57 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_56 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_55 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_54 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_53 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_52 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_51 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_50 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_49 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_48 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_47 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_46 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_45 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_44 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_43 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_42 (viewRef PRIM (cellRef FD1P3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_41 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_40 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_39 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_38 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_37 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_36 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_35 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_34 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_33 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_32 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_31 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_30 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_29 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_28 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_27 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_26 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_25 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_24 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_23 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_22 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_21 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_20 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_19 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_18 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_17 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_16 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_15 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_14 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_13 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_12 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_11 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_10 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_9 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_8 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_7 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_6 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_5 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_4 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_3 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_2 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_1 (viewRef PRIM (cellRef FD1S3BX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance FF_0 (viewRef PRIM (cellRef FD1S3DX (libraryRef LUCENT))) - (property GSR (string "ENABLED")) - ) - (instance w_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance w_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_cia (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance r_gctr_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance empty_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_ci_a (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_2 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_3 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance full_cmp_4 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x99AA")) - (property INIT1 (string "0x99AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance a1 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x66AA")) - (property INIT1 (string "0x66AA")) - (property INJECT1_0 (string "NO")) - (property INJECT1_1 (string "NO")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net buffer_wr_enable (joined - (portRef buffer_wr_enable) - (portRef A (instanceRef AND2_t20)) - )) - (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t20)) - )) - (net wren_i (joined - (portRef Z (instanceRef AND2_t20)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_91)) - (portRef SP (instanceRef FF_92)) - (portRef SP (instanceRef FF_93)) - (portRef SP (instanceRef FF_94)) - (portRef SP (instanceRef FF_95)) - (portRef SP (instanceRef FF_96)) - (portRef SP (instanceRef FF_97)) - (portRef SP (instanceRef FF_98)) - (portRef SP (instanceRef FF_99)) - (portRef SP (instanceRef FF_100)) - (portRef SP (instanceRef FF_101)) - (portRef CEW (instanceRef pdp_ram_0_0_1)) - )) - (net Full (joined - (portRef Q (instanceRef FF_0)) - (portRef A (instanceRef INV_1)) - )) - (net fifo_rden_c (joined - (portRef fifo_rden_c) - (portRef A (instanceRef AND2_t19)) - )) - (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t19)) - )) - (net rden_i (joined - (portRef Z (instanceRef AND2_t19)) - (portRef B1 (instanceRef empty_cmp_ci_a)) - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef SP (instanceRef FF_42)) - (portRef SP (instanceRef FF_43)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_67)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_71)) - (portRef OCER (instanceRef pdp_ram_0_0_1)) - (portRef CER (instanceRef pdp_ram_0_0_1)) - )) - (net last_buf_empty_c (joined - (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_0)) - (portRef last_buf_empty_c) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef B1 (instanceRef a1)) - (portRef A1 (instanceRef a1)) - (portRef B0 (instanceRef a1)) - (portRef A0 (instanceRef a1)) - (portRef B0 (instanceRef full_cmp_ci_a)) - (portRef A0 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef a0)) - (portRef A1 (instanceRef a0)) - (portRef B0 (instanceRef a0)) - (portRef A0 (instanceRef a0)) - (portRef B0 (instanceRef empty_cmp_ci_a)) - (portRef A0 (instanceRef empty_cmp_ci_a)) - (portRef B1 (instanceRef r_gctr_4)) - (portRef B0 (instanceRef r_gctr_4)) - (portRef B1 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef r_gctr_3)) - (portRef B1 (instanceRef r_gctr_2)) - (portRef B0 (instanceRef r_gctr_2)) - (portRef B1 (instanceRef r_gctr_1)) - (portRef B0 (instanceRef r_gctr_1)) - (portRef B1 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_0)) - (portRef B0 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef w_gctr_4)) - (portRef B0 (instanceRef w_gctr_4)) - (portRef B1 (instanceRef w_gctr_3)) - (portRef B0 (instanceRef w_gctr_3)) - (portRef B1 (instanceRef w_gctr_2)) - (portRef B0 (instanceRef w_gctr_2)) - (portRef B1 (instanceRef w_gctr_1)) - (portRef B0 (instanceRef w_gctr_1)) - (portRef B1 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_0)) - (portRef B0 (instanceRef w_gctr_cia)) - (portRef A0 (instanceRef w_gctr_cia)) - (portRef CD (instanceRef FF_0)) - (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_13)) - (portRef CD (instanceRef FF_14)) - (portRef CD (instanceRef FF_15)) - (portRef CD (instanceRef FF_16)) - (portRef CD (instanceRef FF_17)) - (portRef CD (instanceRef FF_18)) - (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_20)) - (portRef CD (instanceRef FF_21)) - (portRef CD (instanceRef FF_32)) - (portRef CD (instanceRef FF_33)) - (portRef CD (instanceRef FF_34)) - (portRef CD (instanceRef FF_35)) - (portRef CD (instanceRef FF_36)) - (portRef CD (instanceRef FF_37)) - (portRef CD (instanceRef FF_38)) - (portRef CD (instanceRef FF_39)) - (portRef CD (instanceRef FF_40)) - (portRef CD (instanceRef FF_41)) - (portRef CD (instanceRef FF_72)) - (portRef CD (instanceRef FF_73)) - (portRef CD (instanceRef FF_74)) - (portRef CD (instanceRef FF_75)) - (portRef CD (instanceRef FF_76)) - (portRef CD (instanceRef FF_77)) - (portRef CD (instanceRef FF_78)) - (portRef CD (instanceRef FF_79)) - (portRef CD (instanceRef FF_80)) - (portRef CD (instanceRef FF_81)) - (portRef CD (instanceRef FF_82)) - (portRef CD (instanceRef FF_83)) - (portRef CD (instanceRef FF_84)) - (portRef CD (instanceRef FF_85)) - (portRef CD (instanceRef FF_86)) - (portRef CD (instanceRef FF_87)) - (portRef CD (instanceRef FF_88)) - (portRef CD (instanceRef FF_89)) - (portRef CD (instanceRef FF_90)) - (portRef CD (instanceRef FF_91)) - (portRef CD (instanceRef FF_92)) - (portRef CD (instanceRef FF_93)) - (portRef CD (instanceRef FF_94)) - (portRef CD (instanceRef FF_95)) - (portRef CD (instanceRef FF_96)) - (portRef CD (instanceRef FF_97)) - (portRef CD (instanceRef FF_98)) - (portRef CD (instanceRef FF_99)) - (portRef CD (instanceRef FF_100)) - (portRef PD (instanceRef FF_101)) - (portRef RST (instanceRef pdp_ram_0_0_1)) - (portRef CSR2 (instanceRef pdp_ram_0_0_1)) - (portRef CSR1 (instanceRef pdp_ram_0_0_1)) - (portRef CSR0 (instanceRef pdp_ram_0_0_1)) - (portRef ADR4 (instanceRef pdp_ram_0_0_1)) - (portRef ADR3 (instanceRef pdp_ram_0_0_1)) - (portRef ADR2 (instanceRef pdp_ram_0_0_1)) - (portRef ADR1 (instanceRef pdp_ram_0_0_1)) - (portRef ADR0 (instanceRef pdp_ram_0_0_1)) - (portRef CSW2 (instanceRef pdp_ram_0_0_1)) - (portRef CSW1 (instanceRef pdp_ram_0_0_1)) - (portRef DI35 (instanceRef pdp_ram_0_0_1)) - (portRef DI34 (instanceRef pdp_ram_0_0_1)) - (portRef AD0 (instanceRef LUT4_0)) - (portRef AD0 (instanceRef LUT4_1)) - (portRef AD0 (instanceRef LUT4_2)) - (portRef AD0 (instanceRef LUT4_3)) - (portRef AD0 (instanceRef LUT4_5)) - (portRef AD1 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_10)) - (portRef AD1 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_15)) - (portRef AD1 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_20)) - (portRef AD1 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_21)) - (portRef B (instanceRef OR2_t18)) - (portRef A (instanceRef OR2_t18)) - )) - (net rRst (joined - (portRef Z (instanceRef OR2_t18)) - (portRef PD (instanceRef FF_1)) - (portRef CD (instanceRef FF_2)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_11)) - (portRef CD (instanceRef FF_22)) - (portRef CD (instanceRef FF_23)) - (portRef CD (instanceRef FF_24)) - (portRef CD (instanceRef FF_25)) - (portRef CD (instanceRef FF_26)) - (portRef CD (instanceRef FF_27)) - (portRef CD (instanceRef FF_28)) - (portRef CD (instanceRef FF_29)) - (portRef CD (instanceRef FF_30)) - (portRef CD (instanceRef FF_31)) - (portRef CD (instanceRef FF_42)) - (portRef CD (instanceRef FF_43)) - (portRef CD (instanceRef FF_44)) - (portRef CD (instanceRef FF_45)) - (portRef CD (instanceRef FF_46)) - (portRef CD (instanceRef FF_47)) - (portRef CD (instanceRef FF_48)) - (portRef CD (instanceRef FF_49)) - (portRef CD (instanceRef FF_50)) - (portRef CD (instanceRef FF_51)) - (portRef CD (instanceRef FF_52)) - (portRef CD (instanceRef FF_53)) - (portRef CD (instanceRef FF_54)) - (portRef CD (instanceRef FF_55)) - (portRef CD (instanceRef FF_56)) - (portRef CD (instanceRef FF_57)) - (portRef CD (instanceRef FF_58)) - (portRef CD (instanceRef FF_59)) - (portRef CD (instanceRef FF_60)) - (portRef CD (instanceRef FF_61)) - (portRef CD (instanceRef FF_62)) - (portRef CD (instanceRef FF_63)) - (portRef CD (instanceRef FF_64)) - (portRef CD (instanceRef FF_65)) - (portRef CD (instanceRef FF_66)) - (portRef CD (instanceRef FF_67)) - (portRef CD (instanceRef FF_68)) - (portRef CD (instanceRef FF_69)) - (portRef CD (instanceRef FF_70)) - (portRef PD (instanceRef FF_71)) - )) - (net wcount_0 (joined - (portRef Q (instanceRef FF_101)) - (portRef A0 (instanceRef full_cmp_0)) - (portRef A0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_81)) - (portRef A (instanceRef XOR2_t17)) - )) - (net wcount_1 (joined - (portRef Q (instanceRef FF_100)) - (portRef A1 (instanceRef full_cmp_0)) - (portRef A1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_80)) - (portRef A (instanceRef XOR2_t16)) - (portRef B (instanceRef XOR2_t17)) - )) - (net w_gdata_0 (joined - (portRef Z (instanceRef XOR2_t17)) - (portRef D (instanceRef FF_91)) - )) - (net wcount_2 (joined - (portRef Q (instanceRef FF_99)) - (portRef A0 (instanceRef full_cmp_1)) - (portRef A0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_79)) - (portRef A (instanceRef XOR2_t15)) - (portRef B (instanceRef XOR2_t16)) - )) - (net w_gdata_1 (joined - (portRef Z (instanceRef XOR2_t16)) - (portRef D (instanceRef FF_90)) - )) - (net wcount_3 (joined - (portRef Q (instanceRef FF_98)) - (portRef A1 (instanceRef full_cmp_1)) - (portRef A1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_78)) - (portRef A (instanceRef XOR2_t14)) - (portRef B (instanceRef XOR2_t15)) - )) - (net w_gdata_2 (joined - (portRef Z (instanceRef XOR2_t15)) - (portRef D (instanceRef FF_89)) - )) - (net wcount_4 (joined - (portRef Q (instanceRef FF_97)) - (portRef A0 (instanceRef full_cmp_2)) - (portRef A0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_77)) - (portRef A (instanceRef XOR2_t13)) - (portRef B (instanceRef XOR2_t14)) - )) - (net w_gdata_3 (joined - (portRef Z (instanceRef XOR2_t14)) - (portRef D (instanceRef FF_88)) - )) - (net wcount_5 (joined - (portRef Q (instanceRef FF_96)) - (portRef A1 (instanceRef full_cmp_2)) - (portRef A1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_76)) - (portRef A (instanceRef XOR2_t12)) - (portRef B (instanceRef XOR2_t13)) - )) - (net w_gdata_4 (joined - (portRef Z (instanceRef XOR2_t13)) - (portRef D (instanceRef FF_87)) - )) - (net wcount_6 (joined - (portRef Q (instanceRef FF_95)) - (portRef A0 (instanceRef full_cmp_3)) - (portRef A0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_75)) - (portRef A (instanceRef XOR2_t11)) - (portRef B (instanceRef XOR2_t12)) - )) - (net w_gdata_5 (joined - (portRef Z (instanceRef XOR2_t12)) - (portRef D (instanceRef FF_86)) - )) - (net wcount_7 (joined - (portRef Q (instanceRef FF_94)) - (portRef A1 (instanceRef full_cmp_3)) - (portRef A1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_74)) - (portRef A (instanceRef XOR2_t10)) - (portRef B (instanceRef XOR2_t11)) - )) - (net w_gdata_6 (joined - (portRef Z (instanceRef XOR2_t11)) - (portRef D (instanceRef FF_85)) - )) - (net wcount_8 (joined - (portRef Q (instanceRef FF_93)) - (portRef A0 (instanceRef full_cmp_4)) - (portRef A0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_73)) - (portRef A (instanceRef XOR2_t9)) - (portRef B (instanceRef XOR2_t10)) - )) - (net w_gdata_7 (joined - (portRef Z (instanceRef XOR2_t10)) - (portRef D (instanceRef FF_84)) - )) - (net wcount_9 (joined - (portRef Q (instanceRef FF_92)) - (portRef A1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_72)) - (portRef D (instanceRef FF_82)) - (portRef AD2 (instanceRef LUT4_0)) - (portRef AD2 (instanceRef LUT4_1)) - (portRef B (instanceRef XOR2_t9)) - )) - (net w_gdata_8 (joined - (portRef Z (instanceRef XOR2_t9)) - (portRef D (instanceRef FF_83)) - )) - (net rcount_0 (joined - (portRef Q (instanceRef FF_71)) - (portRef A0 (instanceRef empty_cmp_0)) - (portRef A0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_51)) - (portRef A (instanceRef XOR2_t8)) - )) - (net rcount_1 (joined - (portRef Q (instanceRef FF_70)) - (portRef A1 (instanceRef empty_cmp_0)) - (portRef A1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_50)) - (portRef A (instanceRef XOR2_t7)) - (portRef B (instanceRef XOR2_t8)) - )) - (net r_gdata_0 (joined - (portRef Z (instanceRef XOR2_t8)) - (portRef D (instanceRef FF_61)) - )) - (net rcount_2 (joined - (portRef Q (instanceRef FF_69)) - (portRef A0 (instanceRef empty_cmp_1)) - (portRef A0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_49)) - (portRef A (instanceRef XOR2_t6)) - (portRef B (instanceRef XOR2_t7)) - )) - (net r_gdata_1 (joined - (portRef Z (instanceRef XOR2_t7)) - (portRef D (instanceRef FF_60)) - )) - (net rcount_3 (joined - (portRef Q (instanceRef FF_68)) - (portRef A1 (instanceRef empty_cmp_1)) - (portRef A1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_48)) - (portRef A (instanceRef XOR2_t5)) - (portRef B (instanceRef XOR2_t6)) - )) - (net r_gdata_2 (joined - (portRef Z (instanceRef XOR2_t6)) - (portRef D (instanceRef FF_59)) - )) - (net rcount_4 (joined - (portRef Q (instanceRef FF_67)) - (portRef A0 (instanceRef empty_cmp_2)) - (portRef A0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_47)) - (portRef A (instanceRef XOR2_t4)) - (portRef B (instanceRef XOR2_t5)) - )) - (net r_gdata_3 (joined - (portRef Z (instanceRef XOR2_t5)) - (portRef D (instanceRef FF_58)) - )) - (net rcount_5 (joined - (portRef Q (instanceRef FF_66)) - (portRef A1 (instanceRef empty_cmp_2)) - (portRef A1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_46)) - (portRef A (instanceRef XOR2_t3)) - (portRef B (instanceRef XOR2_t4)) - )) - (net r_gdata_4 (joined - (portRef Z (instanceRef XOR2_t4)) - (portRef D (instanceRef FF_57)) - )) - (net rcount_6 (joined - (portRef Q (instanceRef FF_65)) - (portRef A0 (instanceRef empty_cmp_3)) - (portRef A0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_45)) - (portRef A (instanceRef XOR2_t2)) - (portRef B (instanceRef XOR2_t3)) - )) - (net r_gdata_5 (joined - (portRef Z (instanceRef XOR2_t3)) - (portRef D (instanceRef FF_56)) - )) - (net rcount_7 (joined - (portRef Q (instanceRef FF_64)) - (portRef A1 (instanceRef empty_cmp_3)) - (portRef A1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_44)) - (portRef A (instanceRef XOR2_t1)) - (portRef B (instanceRef XOR2_t2)) - )) - (net r_gdata_6 (joined - (portRef Z (instanceRef XOR2_t2)) - (portRef D (instanceRef FF_55)) - )) - (net rcount_8 (joined - (portRef Q (instanceRef FF_63)) - (portRef A0 (instanceRef empty_cmp_4)) - (portRef A0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_43)) - (portRef A (instanceRef XOR2_t0)) - (portRef B (instanceRef XOR2_t1)) - )) - (net r_gdata_7 (joined - (portRef Z (instanceRef XOR2_t1)) - (portRef D (instanceRef FF_54)) - )) - (net rcount_9 (joined - (portRef Q (instanceRef FF_62)) - (portRef A1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_42)) - (portRef D (instanceRef FF_52)) - (portRef AD2 (instanceRef LUT4_2)) - (portRef AD2 (instanceRef LUT4_3)) - (portRef B (instanceRef XOR2_t0)) - )) - (net r_gdata_8 (joined - (portRef Z (instanceRef XOR2_t0)) - (portRef D (instanceRef FF_53)) - )) - (net w_gcount_r29 (joined - (portRef Q (instanceRef FF_12)) - (portRef AD1 (instanceRef LUT4_2)) - (portRef AD1 (instanceRef LUT4_3)) - (portRef AD1 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_21)) - (portRef AD0 (instanceRef LUT4_23)) - )) - (net w_gcount_r28 (joined - (portRef Q (instanceRef FF_13)) - (portRef AD2 (instanceRef LUT4_20)) - (portRef AD3 (instanceRef LUT4_21)) - (portRef AD1 (instanceRef LUT4_23)) - )) - (net w_gcount_r27 (joined - (portRef Q (instanceRef FF_14)) - (portRef AD1 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_20)) - (portRef AD2 (instanceRef LUT4_23)) - )) - (net w_gcount_r26 (joined - (portRef Q (instanceRef FF_15)) - (portRef AD1 (instanceRef LUT4_18)) - (portRef AD2 (instanceRef LUT4_19)) - (portRef AD3 (instanceRef LUT4_23)) - )) - (net w_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_23)) - (portRef B0 (instanceRef empty_cmp_3)) - (portRef AD3 (instanceRef LUT4_14)) - (portRef AD3 (instanceRef LUT4_15)) - (portRef AD3 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_17)) - )) - (net w_gcount_r25 (joined - (portRef Q (instanceRef FF_16)) - (portRef AD1 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_18)) - (portRef AD3 (instanceRef LUT4_19)) - (portRef AD0 (instanceRef LUT4_22)) - )) - (net w_gcount_r24 (joined - (portRef Q (instanceRef FF_17)) - (portRef AD2 (instanceRef LUT4_17)) - (portRef AD3 (instanceRef LUT4_18)) - (portRef AD1 (instanceRef LUT4_22)) - )) - (net w_gcount_r23 (joined - (portRef Q (instanceRef FF_18)) - (portRef AD3 (instanceRef LUT4_17)) - (portRef AD2 (instanceRef LUT4_22)) - )) - (net w_gcount_r22 (joined - (portRef Q (instanceRef FF_19)) - (portRef AD3 (instanceRef LUT4_22)) - )) - (net w_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_22)) - (portRef AD2 (instanceRef LUT4_14)) - (portRef AD2 (instanceRef LUT4_15)) - (portRef AD2 (instanceRef LUT4_16)) - )) - (net wcount_r8 (joined - (portRef DO0 (instanceRef LUT4_21)) - (portRef B0 (instanceRef empty_cmp_4)) - (portRef AD0 (instanceRef LUT4_19)) - )) - (net wcount_r7 (joined - (portRef DO0 (instanceRef LUT4_20)) - (portRef B1 (instanceRef empty_cmp_3)) - (portRef AD0 (instanceRef LUT4_18)) - )) - (net wcount_r5 (joined - (portRef DO0 (instanceRef LUT4_19)) - (portRef B1 (instanceRef empty_cmp_2)) - )) - (net wcount_r4 (joined - (portRef DO0 (instanceRef LUT4_18)) - (portRef B0 (instanceRef empty_cmp_2)) - )) - (net wcount_r3 (joined - (portRef DO0 (instanceRef LUT4_17)) - (portRef B1 (instanceRef empty_cmp_1)) - )) - (net wcount_r2 (joined - (portRef DO0 (instanceRef LUT4_16)) - (portRef B0 (instanceRef empty_cmp_1)) - )) - (net w_gcount_r21 (joined - (portRef Q (instanceRef FF_20)) - (portRef AD0 (instanceRef LUT4_14)) - (portRef AD1 (instanceRef LUT4_15)) - )) - (net wcount_r1 (joined - (portRef DO0 (instanceRef LUT4_15)) - (portRef B1 (instanceRef empty_cmp_0)) - )) - (net w_gcount_r20 (joined - (portRef Q (instanceRef FF_21)) - (portRef AD1 (instanceRef LUT4_14)) - )) - (net wcount_r0 (joined - (portRef DO0 (instanceRef LUT4_14)) - (portRef B0 (instanceRef empty_cmp_0)) - )) - (net r_gcount_w29 (joined - (portRef Q (instanceRef FF_2)) - (portRef AD1 (instanceRef LUT4_0)) - (portRef AD1 (instanceRef LUT4_1)) - (portRef AD1 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_11)) - (portRef AD0 (instanceRef LUT4_13)) - )) - (net r_gcount_w28 (joined - (portRef Q (instanceRef FF_3)) - (portRef AD2 (instanceRef LUT4_10)) - (portRef AD3 (instanceRef LUT4_11)) - (portRef AD1 (instanceRef LUT4_13)) - )) - (net r_gcount_w27 (joined - (portRef Q (instanceRef FF_4)) - (portRef AD1 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_10)) - (portRef AD2 (instanceRef LUT4_13)) - )) - (net r_gcount_w26 (joined - (portRef Q (instanceRef FF_5)) - (portRef AD1 (instanceRef LUT4_8)) - (portRef AD2 (instanceRef LUT4_9)) - (portRef AD3 (instanceRef LUT4_13)) - )) - (net r_g2b_xor_cluster_0 (joined - (portRef DO0 (instanceRef LUT4_13)) - (portRef B0 (instanceRef full_cmp_3)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef AD3 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_6)) - (portRef AD0 (instanceRef LUT4_7)) - )) - (net r_gcount_w25 (joined - (portRef Q (instanceRef FF_6)) - (portRef AD1 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_8)) - (portRef AD3 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_12)) - )) - (net r_gcount_w24 (joined - (portRef Q (instanceRef FF_7)) - (portRef AD2 (instanceRef LUT4_7)) - (portRef AD3 (instanceRef LUT4_8)) - (portRef AD1 (instanceRef LUT4_12)) - )) - (net r_gcount_w23 (joined - (portRef Q (instanceRef FF_8)) - (portRef AD3 (instanceRef LUT4_7)) - (portRef AD2 (instanceRef LUT4_12)) - )) - (net r_gcount_w22 (joined - (portRef Q (instanceRef FF_9)) - (portRef AD3 (instanceRef LUT4_12)) - )) - (net r_g2b_xor_cluster_1 (joined - (portRef DO0 (instanceRef LUT4_12)) - (portRef AD2 (instanceRef LUT4_4)) - (portRef AD2 (instanceRef LUT4_5)) - (portRef AD2 (instanceRef LUT4_6)) - )) - (net rcount_w8 (joined - (portRef DO0 (instanceRef LUT4_11)) - (portRef B0 (instanceRef full_cmp_4)) - (portRef AD0 (instanceRef LUT4_9)) - )) - (net rcount_w7 (joined - (portRef DO0 (instanceRef LUT4_10)) - (portRef B1 (instanceRef full_cmp_3)) - (portRef AD0 (instanceRef LUT4_8)) - )) - (net rcount_w5 (joined - (portRef DO0 (instanceRef LUT4_9)) - (portRef B1 (instanceRef full_cmp_2)) - )) - (net rcount_w4 (joined - (portRef DO0 (instanceRef LUT4_8)) - (portRef B0 (instanceRef full_cmp_2)) - )) - (net rcount_w3 (joined - (portRef DO0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef full_cmp_1)) - )) - (net rcount_w2 (joined - (portRef DO0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef full_cmp_1)) - )) - (net r_gcount_w21 (joined - (portRef Q (instanceRef FF_10)) - (portRef AD0 (instanceRef LUT4_4)) - (portRef AD1 (instanceRef LUT4_5)) - )) - (net rcount_w1 (joined - (portRef DO0 (instanceRef LUT4_5)) - (portRef B1 (instanceRef full_cmp_0)) - )) - (net r_gcount_w20 (joined - (portRef Q (instanceRef FF_11)) - (portRef AD1 (instanceRef LUT4_4)) - )) - (net rcount_w0 (joined - (portRef DO0 (instanceRef LUT4_4)) - (portRef B0 (instanceRef full_cmp_0)) - )) - (net rptr_9 (joined - (portRef Q (instanceRef FF_42)) - (portRef AD3 (instanceRef LUT4_2)) - (portRef AD3 (instanceRef LUT4_3)) - )) - (net empty_cmp_set (joined - (portRef DO0 (instanceRef LUT4_3)) - (portRef A1 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_2)) - (portRef B1 (instanceRef empty_cmp_4)) - )) - (net wptr_9 (joined - (portRef Q (instanceRef FF_72)) - (portRef AD3 (instanceRef LUT4_0)) - (portRef AD3 (instanceRef LUT4_1)) - )) - (net full_cmp_set (joined - (portRef DO0 (instanceRef LUT4_1)) - (portRef A1 (instanceRef full_cmp_4)) - )) - (net full_cmp_clr (joined - (portRef DO0 (instanceRef LUT4_0)) - (portRef B1 (instanceRef full_cmp_4)) - )) - (net (rename data_buffer_0 "data_buffer[0]") (joined - (portRef (member data_buffer 33)) - (portRef DI0 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_1 "data_buffer[1]") (joined - (portRef (member data_buffer 32)) - (portRef DI1 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_2 "data_buffer[2]") (joined - (portRef (member data_buffer 31)) - (portRef DI2 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_3 "data_buffer[3]") (joined - (portRef (member data_buffer 30)) - (portRef DI3 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_4 "data_buffer[4]") (joined - (portRef (member data_buffer 29)) - (portRef DI4 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_5 "data_buffer[5]") (joined - (portRef (member data_buffer 28)) - (portRef DI5 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_6 "data_buffer[6]") (joined - (portRef (member data_buffer 27)) - (portRef DI6 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_7 "data_buffer[7]") (joined - (portRef (member data_buffer 26)) - (portRef DI7 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_8 "data_buffer[8]") (joined - (portRef (member data_buffer 25)) - (portRef DI8 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_9 "data_buffer[9]") (joined - (portRef (member data_buffer 24)) - (portRef DI9 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_10 "data_buffer[10]") (joined - (portRef (member data_buffer 23)) - (portRef DI10 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_11 "data_buffer[11]") (joined - (portRef (member data_buffer 22)) - (portRef DI11 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_12 "data_buffer[12]") (joined - (portRef (member data_buffer 21)) - (portRef DI12 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_13 "data_buffer[13]") (joined - (portRef (member data_buffer 20)) - (portRef DI13 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_14 "data_buffer[14]") (joined - (portRef (member data_buffer 19)) - (portRef DI14 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_15 "data_buffer[15]") (joined - (portRef (member data_buffer 18)) - (portRef DI15 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_16 "data_buffer[16]") (joined - (portRef (member data_buffer 17)) - (portRef DI16 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_17 "data_buffer[17]") (joined - (portRef (member data_buffer 16)) - (portRef DI17 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_18 "data_buffer[18]") (joined - (portRef (member data_buffer 15)) - (portRef DI18 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_19 "data_buffer[19]") (joined - (portRef (member data_buffer 14)) - (portRef DI19 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_20 "data_buffer[20]") (joined - (portRef (member data_buffer 13)) - (portRef DI20 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_21 "data_buffer[21]") (joined - (portRef (member data_buffer 12)) - (portRef DI21 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_22 "data_buffer[22]") (joined - (portRef (member data_buffer 11)) - (portRef DI22 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_23 "data_buffer[23]") (joined - (portRef (member data_buffer 10)) - (portRef DI23 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_24 "data_buffer[24]") (joined - (portRef (member data_buffer 9)) - (portRef DI24 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_25 "data_buffer[25]") (joined - (portRef (member data_buffer 8)) - (portRef DI25 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_26 "data_buffer[26]") (joined - (portRef (member data_buffer 7)) - (portRef DI26 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_27 "data_buffer[27]") (joined - (portRef (member data_buffer 6)) - (portRef DI27 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_28 "data_buffer[28]") (joined - (portRef (member data_buffer 5)) - (portRef DI28 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_29 "data_buffer[29]") (joined - (portRef (member data_buffer 4)) - (portRef DI29 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_30 "data_buffer[30]") (joined - (portRef (member data_buffer 3)) - (portRef DI30 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_31 "data_buffer[31]") (joined - (portRef (member data_buffer 2)) - (portRef DI31 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_32 "data_buffer[32]") (joined - (portRef (member data_buffer 1)) - (portRef DI32 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename data_buffer_33 "data_buffer[33]") (joined - (portRef (member data_buffer 0)) - (portRef DI33 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_0 (joined - (portRef Q (instanceRef FF_81)) - (portRef ADW0 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_1 (joined - (portRef Q (instanceRef FF_80)) - (portRef ADW1 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_2 (joined - (portRef Q (instanceRef FF_79)) - (portRef ADW2 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_3 (joined - (portRef Q (instanceRef FF_78)) - (portRef ADW3 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_4 (joined - (portRef Q (instanceRef FF_77)) - (portRef ADW4 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_5 (joined - (portRef Q (instanceRef FF_76)) - (portRef ADW5 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_6 (joined - (portRef Q (instanceRef FF_75)) - (portRef ADW6 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_7 (joined - (portRef Q (instanceRef FF_74)) - (portRef ADW7 (instanceRef pdp_ram_0_0_1)) - )) - (net wptr_8 (joined - (portRef Q (instanceRef FF_73)) - (portRef ADW8 (instanceRef pdp_ram_0_0_1)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef a1)) - (portRef C1 (instanceRef a1)) - (portRef D0 (instanceRef a1)) - (portRef C0 (instanceRef a1)) - (portRef D1 (instanceRef full_cmp_4)) - (portRef C1 (instanceRef full_cmp_4)) - (portRef D0 (instanceRef full_cmp_4)) - (portRef C0 (instanceRef full_cmp_4)) - (portRef D1 (instanceRef full_cmp_3)) - (portRef C1 (instanceRef full_cmp_3)) - (portRef D0 (instanceRef full_cmp_3)) - (portRef C0 (instanceRef full_cmp_3)) - (portRef D1 (instanceRef full_cmp_2)) - (portRef C1 (instanceRef full_cmp_2)) - (portRef D0 (instanceRef full_cmp_2)) - (portRef C0 (instanceRef full_cmp_2)) - (portRef D1 (instanceRef full_cmp_1)) - (portRef C1 (instanceRef full_cmp_1)) - (portRef D0 (instanceRef full_cmp_1)) - (portRef C0 (instanceRef full_cmp_1)) - (portRef D1 (instanceRef full_cmp_0)) - (portRef C1 (instanceRef full_cmp_0)) - (portRef D0 (instanceRef full_cmp_0)) - (portRef C0 (instanceRef full_cmp_0)) - (portRef D1 (instanceRef full_cmp_ci_a)) - (portRef C1 (instanceRef full_cmp_ci_a)) - (portRef D0 (instanceRef full_cmp_ci_a)) - (portRef C0 (instanceRef full_cmp_ci_a)) - (portRef D1 (instanceRef a0)) - (portRef C1 (instanceRef a0)) - (portRef D0 (instanceRef a0)) - (portRef C0 (instanceRef a0)) - (portRef D1 (instanceRef empty_cmp_4)) - (portRef C1 (instanceRef empty_cmp_4)) - (portRef D0 (instanceRef empty_cmp_4)) - (portRef C0 (instanceRef empty_cmp_4)) - (portRef D1 (instanceRef empty_cmp_3)) - (portRef C1 (instanceRef empty_cmp_3)) - (portRef D0 (instanceRef empty_cmp_3)) - (portRef C0 (instanceRef empty_cmp_3)) - (portRef D1 (instanceRef empty_cmp_2)) - (portRef C1 (instanceRef empty_cmp_2)) - (portRef D0 (instanceRef empty_cmp_2)) - (portRef C0 (instanceRef empty_cmp_2)) - (portRef D1 (instanceRef empty_cmp_1)) - (portRef C1 (instanceRef empty_cmp_1)) - (portRef D0 (instanceRef empty_cmp_1)) - (portRef C0 (instanceRef empty_cmp_1)) - (portRef D1 (instanceRef empty_cmp_0)) - (portRef C1 (instanceRef empty_cmp_0)) - (portRef D0 (instanceRef empty_cmp_0)) - (portRef C0 (instanceRef empty_cmp_0)) - (portRef D1 (instanceRef empty_cmp_ci_a)) - (portRef C1 (instanceRef empty_cmp_ci_a)) - (portRef D0 (instanceRef empty_cmp_ci_a)) - (portRef C0 (instanceRef empty_cmp_ci_a)) - (portRef D1 (instanceRef r_gctr_4)) - (portRef C1 (instanceRef r_gctr_4)) - (portRef D0 (instanceRef r_gctr_4)) - (portRef C0 (instanceRef r_gctr_4)) - (portRef D1 (instanceRef r_gctr_3)) - (portRef C1 (instanceRef r_gctr_3)) - (portRef D0 (instanceRef r_gctr_3)) - (portRef C0 (instanceRef r_gctr_3)) - (portRef D1 (instanceRef r_gctr_2)) - (portRef C1 (instanceRef r_gctr_2)) - (portRef D0 (instanceRef r_gctr_2)) - (portRef C0 (instanceRef r_gctr_2)) - (portRef D1 (instanceRef r_gctr_1)) - (portRef C1 (instanceRef r_gctr_1)) - (portRef D0 (instanceRef r_gctr_1)) - (portRef C0 (instanceRef r_gctr_1)) - (portRef D1 (instanceRef r_gctr_0)) - (portRef C1 (instanceRef r_gctr_0)) - (portRef D0 (instanceRef r_gctr_0)) - (portRef C0 (instanceRef r_gctr_0)) - (portRef D1 (instanceRef r_gctr_cia)) - (portRef C1 (instanceRef r_gctr_cia)) - (portRef B1 (instanceRef r_gctr_cia)) - (portRef A1 (instanceRef r_gctr_cia)) - (portRef D0 (instanceRef r_gctr_cia)) - (portRef C0 (instanceRef r_gctr_cia)) - (portRef D1 (instanceRef w_gctr_4)) - (portRef C1 (instanceRef w_gctr_4)) - (portRef D0 (instanceRef w_gctr_4)) - (portRef C0 (instanceRef w_gctr_4)) - (portRef D1 (instanceRef w_gctr_3)) - (portRef C1 (instanceRef w_gctr_3)) - (portRef D0 (instanceRef w_gctr_3)) - (portRef C0 (instanceRef w_gctr_3)) - (portRef D1 (instanceRef w_gctr_2)) - (portRef C1 (instanceRef w_gctr_2)) - (portRef D0 (instanceRef w_gctr_2)) - (portRef C0 (instanceRef w_gctr_2)) - (portRef D1 (instanceRef w_gctr_1)) - (portRef C1 (instanceRef w_gctr_1)) - (portRef D0 (instanceRef w_gctr_1)) - (portRef C0 (instanceRef w_gctr_1)) - (portRef D1 (instanceRef w_gctr_0)) - (portRef C1 (instanceRef w_gctr_0)) - (portRef D0 (instanceRef w_gctr_0)) - (portRef C0 (instanceRef w_gctr_0)) - (portRef D1 (instanceRef w_gctr_cia)) - (portRef C1 (instanceRef w_gctr_cia)) - (portRef B1 (instanceRef w_gctr_cia)) - (portRef A1 (instanceRef w_gctr_cia)) - (portRef D0 (instanceRef w_gctr_cia)) - (portRef C0 (instanceRef w_gctr_cia)) - (portRef CSW0 (instanceRef pdp_ram_0_0_1)) - (portRef BE3 (instanceRef pdp_ram_0_0_1)) - (portRef BE2 (instanceRef pdp_ram_0_0_1)) - (portRef BE1 (instanceRef pdp_ram_0_0_1)) - (portRef BE0 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef CK (instanceRef FF_0)) - (portRef CK (instanceRef FF_2)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_22)) - (portRef CK (instanceRef FF_23)) - (portRef CK (instanceRef FF_24)) - (portRef CK (instanceRef FF_25)) - (portRef CK (instanceRef FF_26)) - (portRef CK (instanceRef FF_27)) - (portRef CK (instanceRef FF_28)) - (portRef CK (instanceRef FF_29)) - (portRef CK (instanceRef FF_30)) - (portRef CK (instanceRef FF_31)) - (portRef CK (instanceRef FF_72)) - (portRef CK (instanceRef FF_73)) - (portRef CK (instanceRef FF_74)) - (portRef CK (instanceRef FF_75)) - (portRef CK (instanceRef FF_76)) - (portRef CK (instanceRef FF_77)) - (portRef CK (instanceRef FF_78)) - (portRef CK (instanceRef FF_79)) - (portRef CK (instanceRef FF_80)) - (portRef CK (instanceRef FF_81)) - (portRef CK (instanceRef FF_82)) - (portRef CK (instanceRef FF_83)) - (portRef CK (instanceRef FF_84)) - (portRef CK (instanceRef FF_85)) - (portRef CK (instanceRef FF_86)) - (portRef CK (instanceRef FF_87)) - (portRef CK (instanceRef FF_88)) - (portRef CK (instanceRef FF_89)) - (portRef CK (instanceRef FF_90)) - (portRef CK (instanceRef FF_91)) - (portRef CK (instanceRef FF_92)) - (portRef CK (instanceRef FF_93)) - (portRef CK (instanceRef FF_94)) - (portRef CK (instanceRef FF_95)) - (portRef CK (instanceRef FF_96)) - (portRef CK (instanceRef FF_97)) - (portRef CK (instanceRef FF_98)) - (portRef CK (instanceRef FF_99)) - (portRef CK (instanceRef FF_100)) - (portRef CK (instanceRef FF_101)) - (portRef CLKW (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_0 (joined - (portRef Q (instanceRef FF_51)) - (portRef ADR5 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_1 (joined - (portRef Q (instanceRef FF_50)) - (portRef ADR6 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_2 (joined - (portRef Q (instanceRef FF_49)) - (portRef ADR7 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_3 (joined - (portRef Q (instanceRef FF_48)) - (portRef ADR8 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_4 (joined - (portRef Q (instanceRef FF_47)) - (portRef ADR9 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_5 (joined - (portRef Q (instanceRef FF_46)) - (portRef ADR10 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_6 (joined - (portRef Q (instanceRef FF_45)) - (portRef ADR11 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_7 (joined - (portRef Q (instanceRef FF_44)) - (portRef ADR12 (instanceRef pdp_ram_0_0_1)) - )) - (net rptr_8 (joined - (portRef Q (instanceRef FF_43)) - (portRef ADR13 (instanceRef pdp_ram_0_0_1)) - )) - (net rd_clk_c (joined - (portRef rd_clk_c) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_12)) - (portRef CK (instanceRef FF_13)) - (portRef CK (instanceRef FF_14)) - (portRef CK (instanceRef FF_15)) - (portRef CK (instanceRef FF_16)) - (portRef CK (instanceRef FF_17)) - (portRef CK (instanceRef FF_18)) - (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_20)) - (portRef CK (instanceRef FF_21)) - (portRef CK (instanceRef FF_32)) - (portRef CK (instanceRef FF_33)) - (portRef CK (instanceRef FF_34)) - (portRef CK (instanceRef FF_35)) - (portRef CK (instanceRef FF_36)) - (portRef CK (instanceRef FF_37)) - (portRef CK (instanceRef FF_38)) - (portRef CK (instanceRef FF_39)) - (portRef CK (instanceRef FF_40)) - (portRef CK (instanceRef FF_41)) - (portRef CK (instanceRef FF_42)) - (portRef CK (instanceRef FF_43)) - (portRef CK (instanceRef FF_44)) - (portRef CK (instanceRef FF_45)) - (portRef CK (instanceRef FF_46)) - (portRef CK (instanceRef FF_47)) - (portRef CK (instanceRef FF_48)) - (portRef CK (instanceRef FF_49)) - (portRef CK (instanceRef FF_50)) - (portRef CK (instanceRef FF_51)) - (portRef CK (instanceRef FF_52)) - (portRef CK (instanceRef FF_53)) - (portRef CK (instanceRef FF_54)) - (portRef CK (instanceRef FF_55)) - (portRef CK (instanceRef FF_56)) - (portRef CK (instanceRef FF_57)) - (portRef CK (instanceRef FF_58)) - (portRef CK (instanceRef FF_59)) - (portRef CK (instanceRef FF_60)) - (portRef CK (instanceRef FF_61)) - (portRef CK (instanceRef FF_62)) - (portRef CK (instanceRef FF_63)) - (portRef CK (instanceRef FF_64)) - (portRef CK (instanceRef FF_65)) - (portRef CK (instanceRef FF_66)) - (portRef CK (instanceRef FF_67)) - (portRef CK (instanceRef FF_68)) - (portRef CK (instanceRef FF_69)) - (portRef CK (instanceRef FF_70)) - (portRef CK (instanceRef FF_71)) - (portRef CLKR (instanceRef pdp_ram_0_0_1)) - )) - (net (rename FEE_DATA_OUT_c_18 "FEE_DATA_OUT_c[18]") (joined - (portRef DO0 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 13)) - )) - (net (rename FEE_DATA_OUT_c_19 "FEE_DATA_OUT_c[19]") (joined - (portRef DO1 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 12)) - )) - (net (rename FEE_DATA_OUT_c_20 "FEE_DATA_OUT_c[20]") (joined - (portRef DO2 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 11)) - )) - (net (rename FEE_DATA_OUT_c_21 "FEE_DATA_OUT_c[21]") (joined - (portRef DO3 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 10)) - )) - (net (rename FEE_DATA_OUT_c_22 "FEE_DATA_OUT_c[22]") (joined - (portRef DO4 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 9)) - )) - (net (rename FEE_DATA_OUT_c_23 "FEE_DATA_OUT_c[23]") (joined - (portRef DO5 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 8)) - )) - (net (rename FEE_DATA_OUT_c_24 "FEE_DATA_OUT_c[24]") (joined - (portRef DO6 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 7)) - )) - (net (rename FEE_DATA_OUT_c_25 "FEE_DATA_OUT_c[25]") (joined - (portRef DO7 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 6)) - )) - (net (rename FEE_DATA_OUT_c_26 "FEE_DATA_OUT_c[26]") (joined - (portRef DO8 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 5)) - )) - (net (rename FEE_DATA_OUT_c_27 "FEE_DATA_OUT_c[27]") (joined - (portRef DO9 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 4)) - )) - (net (rename FEE_DATA_OUT_c_28 "FEE_DATA_OUT_c[28]") (joined - (portRef DO10 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 3)) - )) - (net (rename FEE_DATA_OUT_c_29 "FEE_DATA_OUT_c[29]") (joined - (portRef DO11 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 2)) - )) - (net (rename FEE_DATA_OUT_c_30 "FEE_DATA_OUT_c[30]") (joined - (portRef DO12 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 1)) - )) - (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined - (portRef DO13 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 0)) - )) - (net (rename Q_1_32 "Q_1[32]") (joined - (portRef DO14 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename Q_1_33 "Q_1[33]") (joined - (portRef DO15 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename Q_1_34 "Q_1[34]") (joined - (portRef DO16 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename Q_1_35 "Q_1[35]") (joined - (portRef DO17 (instanceRef pdp_ram_0_0_1)) - )) - (net (rename FEE_DATA_OUT_c_0 "FEE_DATA_OUT_c[0]") (joined - (portRef DO18 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 31)) - )) - (net (rename FEE_DATA_OUT_c_1 "FEE_DATA_OUT_c[1]") (joined - (portRef DO19 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 30)) - )) - (net (rename FEE_DATA_OUT_c_2 "FEE_DATA_OUT_c[2]") (joined - (portRef DO20 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 29)) - )) - (net (rename FEE_DATA_OUT_c_3 "FEE_DATA_OUT_c[3]") (joined - (portRef DO21 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 28)) - )) - (net (rename FEE_DATA_OUT_c_4 "FEE_DATA_OUT_c[4]") (joined - (portRef DO22 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 27)) - )) - (net (rename FEE_DATA_OUT_c_5 "FEE_DATA_OUT_c[5]") (joined - (portRef DO23 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 26)) - )) - (net (rename FEE_DATA_OUT_c_6 "FEE_DATA_OUT_c[6]") (joined - (portRef DO24 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 25)) - )) - (net (rename FEE_DATA_OUT_c_7 "FEE_DATA_OUT_c[7]") (joined - (portRef DO25 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 24)) - )) - (net (rename FEE_DATA_OUT_c_8 "FEE_DATA_OUT_c[8]") (joined - (portRef DO26 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 23)) - )) - (net (rename FEE_DATA_OUT_c_9 "FEE_DATA_OUT_c[9]") (joined - (portRef DO27 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 22)) - )) - (net (rename FEE_DATA_OUT_c_10 "FEE_DATA_OUT_c[10]") (joined - (portRef DO28 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 21)) - )) - (net (rename FEE_DATA_OUT_c_11 "FEE_DATA_OUT_c[11]") (joined - (portRef DO29 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 20)) - )) - (net (rename FEE_DATA_OUT_c_12 "FEE_DATA_OUT_c[12]") (joined - (portRef DO30 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 19)) - )) - (net (rename FEE_DATA_OUT_c_13 "FEE_DATA_OUT_c[13]") (joined - (portRef DO31 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 18)) - )) - (net (rename FEE_DATA_OUT_c_14 "FEE_DATA_OUT_c[14]") (joined - (portRef DO32 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 17)) - )) - (net (rename FEE_DATA_OUT_c_15 "FEE_DATA_OUT_c[15]") (joined - (portRef DO33 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 16)) - )) - (net (rename FEE_DATA_OUT_c_16 "FEE_DATA_OUT_c[16]") (joined - (portRef DO34 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 15)) - )) - (net (rename FEE_DATA_OUT_c_17 "FEE_DATA_OUT_c[17]") (joined - (portRef DO35 (instanceRef pdp_ram_0_0_1)) - (portRef (member fee_data_out_c 14)) - )) - (net iwcount_0 (joined - (portRef S0 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_101)) - )) - (net iwcount_1 (joined - (portRef S1 (instanceRef w_gctr_0)) - (portRef D (instanceRef FF_100)) - )) - (net iwcount_2 (joined - (portRef S0 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_99)) - )) - (net iwcount_3 (joined - (portRef S1 (instanceRef w_gctr_1)) - (portRef D (instanceRef FF_98)) - )) - (net iwcount_4 (joined - (portRef S0 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_97)) - )) - (net iwcount_5 (joined - (portRef S1 (instanceRef w_gctr_2)) - (portRef D (instanceRef FF_96)) - )) - (net iwcount_6 (joined - (portRef S0 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_95)) - )) - (net iwcount_7 (joined - (portRef S1 (instanceRef w_gctr_3)) - (portRef D (instanceRef FF_94)) - )) - (net iwcount_8 (joined - (portRef S0 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_93)) - )) - (net iwcount_9 (joined - (portRef S1 (instanceRef w_gctr_4)) - (portRef D (instanceRef FF_92)) - )) - (net w_gcount_0 (joined - (portRef Q (instanceRef FF_91)) - (portRef D (instanceRef FF_41)) - )) - (net w_gcount_1 (joined - (portRef Q (instanceRef FF_90)) - (portRef D (instanceRef FF_40)) - )) - (net w_gcount_2 (joined - (portRef Q (instanceRef FF_89)) - (portRef D (instanceRef FF_39)) - )) - (net w_gcount_3 (joined - (portRef Q (instanceRef FF_88)) - (portRef D (instanceRef FF_38)) - )) - (net w_gcount_4 (joined - (portRef Q (instanceRef FF_87)) - (portRef D (instanceRef FF_37)) - )) - (net w_gcount_5 (joined - (portRef Q (instanceRef FF_86)) - (portRef D (instanceRef FF_36)) - )) - (net w_gcount_6 (joined - (portRef Q (instanceRef FF_85)) - (portRef D (instanceRef FF_35)) - )) - (net w_gcount_7 (joined - (portRef Q (instanceRef FF_84)) - (portRef D (instanceRef FF_34)) - )) - (net w_gcount_8 (joined - (portRef Q (instanceRef FF_83)) - (portRef D (instanceRef FF_33)) - )) - (net w_gcount_9 (joined - (portRef Q (instanceRef FF_82)) - (portRef D (instanceRef FF_32)) - )) - (net ircount_0 (joined - (portRef S0 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_71)) - )) - (net ircount_1 (joined - (portRef S1 (instanceRef r_gctr_0)) - (portRef D (instanceRef FF_70)) - )) - (net ircount_2 (joined - (portRef S0 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_69)) - )) - (net ircount_3 (joined - (portRef S1 (instanceRef r_gctr_1)) - (portRef D (instanceRef FF_68)) - )) - (net ircount_4 (joined - (portRef S0 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_67)) - )) - (net ircount_5 (joined - (portRef S1 (instanceRef r_gctr_2)) - (portRef D (instanceRef FF_66)) - )) - (net ircount_6 (joined - (portRef S0 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_65)) - )) - (net ircount_7 (joined - (portRef S1 (instanceRef r_gctr_3)) - (portRef D (instanceRef FF_64)) - )) - (net ircount_8 (joined - (portRef S0 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_63)) - )) - (net ircount_9 (joined - (portRef S1 (instanceRef r_gctr_4)) - (portRef D (instanceRef FF_62)) - )) - (net r_gcount_0 (joined - (portRef Q (instanceRef FF_61)) - (portRef D (instanceRef FF_31)) - )) - (net r_gcount_1 (joined - (portRef Q (instanceRef FF_60)) - (portRef D (instanceRef FF_30)) - )) - (net r_gcount_2 (joined - (portRef Q (instanceRef FF_59)) - (portRef D (instanceRef FF_29)) - )) - (net r_gcount_3 (joined - (portRef Q (instanceRef FF_58)) - (portRef D (instanceRef FF_28)) - )) - (net r_gcount_4 (joined - (portRef Q (instanceRef FF_57)) - (portRef D (instanceRef FF_27)) - )) - (net r_gcount_5 (joined - (portRef Q (instanceRef FF_56)) - (portRef D (instanceRef FF_26)) - )) - (net r_gcount_6 (joined - (portRef Q (instanceRef FF_55)) - (portRef D (instanceRef FF_25)) - )) - (net r_gcount_7 (joined - (portRef Q (instanceRef FF_54)) - (portRef D (instanceRef FF_24)) - )) - (net r_gcount_8 (joined - (portRef Q (instanceRef FF_53)) - (portRef D (instanceRef FF_23)) - )) - (net r_gcount_9 (joined - (portRef Q (instanceRef FF_52)) - (portRef D (instanceRef FF_22)) - )) - (net w_gcount_r0 (joined - (portRef Q (instanceRef FF_41)) - (portRef D (instanceRef FF_21)) - )) - (net w_gcount_r1 (joined - (portRef Q (instanceRef FF_40)) - (portRef D (instanceRef FF_20)) - )) - (net w_gcount_r2 (joined - (portRef Q (instanceRef FF_39)) - (portRef D (instanceRef FF_19)) - )) - (net w_gcount_r3 (joined - (portRef Q (instanceRef FF_38)) - (portRef D (instanceRef FF_18)) - )) - (net w_gcount_r4 (joined - (portRef Q (instanceRef FF_37)) - (portRef D (instanceRef FF_17)) - )) - (net w_gcount_r5 (joined - (portRef Q (instanceRef FF_36)) - (portRef D (instanceRef FF_16)) - )) - (net w_gcount_r6 (joined - (portRef Q (instanceRef FF_35)) - (portRef D (instanceRef FF_15)) - )) - (net w_gcount_r7 (joined - (portRef Q (instanceRef FF_34)) - (portRef D (instanceRef FF_14)) - )) - (net w_gcount_r8 (joined - (portRef Q (instanceRef FF_33)) - (portRef D (instanceRef FF_13)) - )) - (net w_gcount_r9 (joined - (portRef Q (instanceRef FF_32)) - (portRef D (instanceRef FF_12)) - )) - (net r_gcount_w0 (joined - (portRef Q (instanceRef FF_31)) - (portRef D (instanceRef FF_11)) - )) - (net r_gcount_w1 (joined - (portRef Q (instanceRef FF_30)) - (portRef D (instanceRef FF_10)) - )) - (net r_gcount_w2 (joined - (portRef Q (instanceRef FF_29)) - (portRef D (instanceRef FF_9)) - )) - (net r_gcount_w3 (joined - (portRef Q (instanceRef FF_28)) - (portRef D (instanceRef FF_8)) - )) - (net r_gcount_w4 (joined - (portRef Q (instanceRef FF_27)) - (portRef D (instanceRef FF_7)) - )) - (net r_gcount_w5 (joined - (portRef Q (instanceRef FF_26)) - (portRef D (instanceRef FF_6)) - )) - (net r_gcount_w6 (joined - (portRef Q (instanceRef FF_25)) - (portRef D (instanceRef FF_5)) - )) - (net r_gcount_w7 (joined - (portRef Q (instanceRef FF_24)) - (portRef D (instanceRef FF_4)) - )) - (net r_gcount_w8 (joined - (portRef Q (instanceRef FF_23)) - (portRef D (instanceRef FF_3)) - )) - (net r_gcount_w9 (joined - (portRef Q (instanceRef FF_22)) - (portRef D (instanceRef FF_2)) - )) - (net empty_d (joined - (portRef S0 (instanceRef a0)) - (portRef D (instanceRef FF_1)) - )) - (net full_d (joined - (portRef S0 (instanceRef a1)) - (portRef D (instanceRef FF_0)) - )) - (net w_gctr_ci (joined - (portRef COUT (instanceRef w_gctr_cia)) - (portRef CIN (instanceRef w_gctr_0)) - )) - (net w_gctr_cia_S0_2 (joined - (portRef S0 (instanceRef w_gctr_cia)) - )) - (net w_gctr_cia_S1_2 (joined - (portRef S1 (instanceRef w_gctr_cia)) - )) - (net co0 (joined - (portRef COUT (instanceRef w_gctr_0)) - (portRef CIN (instanceRef w_gctr_1)) - )) - (net co1 (joined - (portRef COUT (instanceRef w_gctr_1)) - (portRef CIN (instanceRef w_gctr_2)) - )) - (net co2 (joined - (portRef COUT (instanceRef w_gctr_2)) - (portRef CIN (instanceRef w_gctr_3)) - )) - (net co3 (joined - (portRef COUT (instanceRef w_gctr_3)) - (portRef CIN (instanceRef w_gctr_4)) - )) - (net co4 (joined - (portRef COUT (instanceRef w_gctr_4)) - )) - (net r_gctr_ci (joined - (portRef COUT (instanceRef r_gctr_cia)) - (portRef CIN (instanceRef r_gctr_0)) - )) - (net r_gctr_cia_S0_2 (joined - (portRef S0 (instanceRef r_gctr_cia)) - )) - (net r_gctr_cia_S1_2 (joined - (portRef S1 (instanceRef r_gctr_cia)) - )) - (net co0_1 (joined - (portRef COUT (instanceRef r_gctr_0)) - (portRef CIN (instanceRef r_gctr_1)) - )) - (net co1_1 (joined - (portRef COUT (instanceRef r_gctr_1)) - (portRef CIN (instanceRef r_gctr_2)) - )) - (net co2_1 (joined - (portRef COUT (instanceRef r_gctr_2)) - (portRef CIN (instanceRef r_gctr_3)) - )) - (net co3_1 (joined - (portRef COUT (instanceRef r_gctr_3)) - (portRef CIN (instanceRef r_gctr_4)) - )) - (net co4_1 (joined - (portRef COUT (instanceRef r_gctr_4)) - )) - (net cmp_ci (joined - (portRef COUT (instanceRef empty_cmp_ci_a)) - (portRef CIN (instanceRef empty_cmp_0)) - )) - (net empty_cmp_ci_a_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_ci_a)) - )) - (net empty_cmp_ci_a_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_ci_a)) - )) - (net co0_2 (joined - (portRef COUT (instanceRef empty_cmp_0)) - (portRef CIN (instanceRef empty_cmp_1)) - )) - (net empty_cmp_0_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_0)) - )) - (net empty_cmp_0_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_0)) - )) - (net co1_2 (joined - (portRef COUT (instanceRef empty_cmp_1)) - (portRef CIN (instanceRef empty_cmp_2)) - )) - (net empty_cmp_1_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_1)) - )) - (net empty_cmp_1_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_1)) - )) - (net co2_2 (joined - (portRef COUT (instanceRef empty_cmp_2)) - (portRef CIN (instanceRef empty_cmp_3)) - )) - (net empty_cmp_2_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_2)) - )) - (net empty_cmp_2_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_2)) - )) - (net co3_2 (joined - (portRef COUT (instanceRef empty_cmp_3)) - (portRef CIN (instanceRef empty_cmp_4)) - )) - (net empty_cmp_3_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_3)) - )) - (net empty_cmp_3_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_3)) - )) - (net empty_d_c (joined - (portRef COUT (instanceRef empty_cmp_4)) - (portRef CIN (instanceRef a0)) - )) - (net empty_cmp_4_S0_2 (joined - (portRef S0 (instanceRef empty_cmp_4)) - )) - (net empty_cmp_4_S1_2 (joined - (portRef S1 (instanceRef empty_cmp_4)) - )) - (net a0_COUT_2 (joined - (portRef COUT (instanceRef a0)) - )) - (net a0_S1_2 (joined - (portRef S1 (instanceRef a0)) - )) - (net cmp_ci_1 (joined - (portRef COUT (instanceRef full_cmp_ci_a)) - (portRef CIN (instanceRef full_cmp_0)) - )) - (net full_cmp_ci_a_S0_2 (joined - (portRef S0 (instanceRef full_cmp_ci_a)) - )) - (net full_cmp_ci_a_S1_2 (joined - (portRef S1 (instanceRef full_cmp_ci_a)) - )) - (net co0_3 (joined - (portRef COUT (instanceRef full_cmp_0)) - (portRef CIN (instanceRef full_cmp_1)) - )) - (net full_cmp_0_S0_2 (joined - (portRef S0 (instanceRef full_cmp_0)) - )) - (net full_cmp_0_S1_2 (joined - (portRef S1 (instanceRef full_cmp_0)) - )) - (net co1_3 (joined - (portRef COUT (instanceRef full_cmp_1)) - (portRef CIN (instanceRef full_cmp_2)) - )) - (net full_cmp_1_S0_2 (joined - (portRef S0 (instanceRef full_cmp_1)) - )) - (net full_cmp_1_S1_2 (joined - (portRef S1 (instanceRef full_cmp_1)) - )) - (net co2_3 (joined - (portRef COUT (instanceRef full_cmp_2)) - (portRef CIN (instanceRef full_cmp_3)) - )) - (net full_cmp_2_S0_2 (joined - (portRef S0 (instanceRef full_cmp_2)) - )) - (net full_cmp_2_S1_2 (joined - (portRef S1 (instanceRef full_cmp_2)) - )) - (net co3_3 (joined - (portRef COUT (instanceRef full_cmp_3)) - (portRef CIN (instanceRef full_cmp_4)) - )) - (net full_cmp_3_S0_2 (joined - (portRef S0 (instanceRef full_cmp_3)) - )) - (net full_cmp_3_S1_2 (joined - (portRef S1 (instanceRef full_cmp_3)) - )) - (net full_d_c (joined - (portRef COUT (instanceRef full_cmp_4)) - (portRef CIN (instanceRef a1)) - )) - (net full_cmp_4_S0_2 (joined - (portRef S0 (instanceRef full_cmp_4)) - )) - (net full_cmp_4_S1_2 (joined - (portRef S1 (instanceRef full_cmp_4)) - )) - (net a1_COUT_2 (joined - (portRef COUT (instanceRef a1)) - )) - (net a1_S1_2 (joined - (portRef S1 (instanceRef a1)) - )) - (net CIN (joined - (portRef CIN (instanceRef full_cmp_ci_a)) - )) - (net CIN_0 (joined - (portRef CIN (instanceRef empty_cmp_ci_a)) - )) - (net CIN_1 (joined - (portRef CIN (instanceRef r_gctr_cia)) - )) - (net CIN_2 (joined - (portRef CIN (instanceRef w_gctr_cia)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "fifo40_dc")) - ) - ) - (cell hades_tdc_channel_raw_out (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port (array (rename hades_dbg2_coarse_c "hades_dbg2_coarse_c[8:0]") 9) (direction INPUT)) - (port reset_dl_i_0 (direction INPUT)) - (port (array (rename hades_raw_out "hades_raw_out[23:0]") 24) (direction OUTPUT)) - (port reset_dl_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - (port hades_trig_c_i (direction INPUT)) - (port drop_cmp_buf_coarse_2_ac0_13_0 (direction INPUT)) - (port drop_cmp_buf_coarse_2_c4 (direction INPUT)) - (port drop_cmp_buf_coarse_2_ac0_9_0 (direction INPUT)) - (port drop_cmp_buf_coarse_2_c5 (direction INPUT)) - (port drop_cmp_buf_coarse_2_c3 (direction INPUT)) - (port hades_raw_out_valid (direction OUTPUT)) - ) - (contents - (instance un1_coarse_1_0_I_9_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A+B !A)+D (!C (!B A+B !A)+C (!B !A+B A)))")) - ) - (instance un1_buf_positive_0_I_9_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A+B !A)+D (!C (!B A+B !A)+C (!B !A+B A)))")) - ) - (instance raw_out_valid (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_0 "raw_out[0]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_1 "raw_out[1]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_2 "raw_out[2]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_3 "raw_out[3]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_4 "raw_out[4]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_5 "raw_out[5]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_6 "raw_out[6]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_7 "raw_out[7]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_8 "raw_out[8]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_9 "raw_out[9]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_10 "raw_out[10]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_11 "raw_out[11]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_12 "raw_out[12]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_13 "raw_out[13]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_14 "raw_out[14]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_15 "raw_out[15]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_16 "raw_out[16]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_17 "raw_out[17]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_18 "raw_out[18]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_19 "raw_out[19]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_20 "raw_out[20]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_21 "raw_out[21]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_22 "raw_out[22]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename raw_out_23 "raw_out[23]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance buf_positive_ready (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_0 "buf_positive[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_1 "buf_positive[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_2 "buf_positive[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_3 "buf_positive[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_4 "buf_positive[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_5 "buf_positive[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_6 "buf_positive[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_7 "buf_positive[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_8 "buf_positive[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_9 "buf_positive[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_10 "buf_positive[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_positive_11 "buf_positive[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance buf_negative_ready (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_0 "buf_negative[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_1 "buf_negative[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_2 "buf_negative[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_3 "buf_negative[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_4 "buf_negative[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_5 "buf_negative[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_6 "buf_negative[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_7 "buf_negative[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_8 "buf_negative[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_9 "buf_negative[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_10 "buf_negative[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename buf_negative_11 "buf_negative[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance un1_buf_positive_0_I_9_0_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (!B A+B !A))+D (!C !B+C (!B !A+B A)))")) - ) - (instance un1_coarse_1_0_I_9_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (!B A+B !A))+D (!C !B+C (!B !A+B A)))")) - ) - (instance buf_positive_ready_4_iv_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (B !A)+C (!B+!A)))")) - ) - (instance buf_negative_ready_4_f0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A))+D (!C (!B A)+C (!B A+B !A)))")) - ) - (instance buf_negative_ready_RNIG7JA (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance un1_coarse_1_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x500c")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x1824")) - ) - (instance un1_coarse_1_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x1441")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x1441")) - ) - (instance un1_coarse_1_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x8111")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x1555")) - ) - (instance un1_coarse_1_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0xa003")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x0000")) - ) - (instance un1_buf_positive_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x500c")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x1824")) - ) - (instance un1_buf_positive_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x1441")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x1441")) - ) - (instance un1_buf_positive_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x8111")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x1555")) - ) - (instance un1_buf_positive_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0xa003")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x0000")) - ) - (instance trig_inv_inst1 (viewRef netlist (cellRef trig_inv)) - ) - (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_0)) - ) - (instance tdc_neg_inst (viewRef netlist (cellRef tdc4ddr_short_1)) - ) - (instance dec_inst (viewRef netlist (cellRef output_decoder8_0_0)) - ) - (instance dec_neg_inst (viewRef netlist (cellRef output_decoder8_0_1)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename buf_negative_5 "buf_negative[5]") (joined - (portRef Q (instanceRef buf_negative_5)) - (portRef D (instanceRef raw_out_17)) - (portRef A (instanceRef un1_coarse_1_0_I_9_0_RNO)) - )) - (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined - (portRef (member hades_dbg2_coarse_c 6)) - (portRef D (instanceRef buf_negative_5)) - (portRef D (instanceRef buf_positive_5)) - (portRef B (instanceRef un1_buf_positive_0_I_9_0_RNO)) - (portRef B (instanceRef un1_coarse_1_0_I_9_0_RNO)) - )) - (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined - (portRef (member hades_dbg2_coarse_c 7)) - (portRef D1 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef D1 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef D (instanceRef buf_negative_4)) - (portRef D (instanceRef buf_positive_4)) - (portRef C (instanceRef un1_buf_positive_0_I_9_0_RNO)) - (portRef C (instanceRef un1_coarse_1_0_I_9_0_RNO)) - )) - (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined - (portRef (member hades_dbg2_coarse_c 8)) - (portRef C1 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef C1 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef D (instanceRef buf_negative_3)) - (portRef D (instanceRef buf_positive_3)) - (portRef D (instanceRef un1_buf_positive_0_I_9_0_RNO)) - (portRef D (instanceRef un1_coarse_1_0_I_9_0_RNO)) - )) - (net un1_coarse_1_0_N_19 (joined - (portRef Z (instanceRef un1_coarse_1_0_I_9_0_RNO)) - (portRef A0 (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net (rename buf_positive_5 "buf_positive[5]") (joined - (portRef Q (instanceRef buf_positive_5)) - (portRef D (instanceRef raw_out_5)) - (portRef A (instanceRef un1_buf_positive_0_I_9_0_RNO)) - )) - (net un1_buf_positive_0_N_19 (joined - (portRef Z (instanceRef un1_buf_positive_0_I_9_0_RNO)) - (portRef A0 (instanceRef un1_buf_positive_0_I_9_0)) - )) - (net N_249_i (joined - (portRef Z (instanceRef buf_negative_ready_RNIG7JA)) - (portRef SP (instanceRef raw_out_23)) - (portRef SP (instanceRef raw_out_22)) - (portRef SP (instanceRef raw_out_21)) - (portRef SP (instanceRef raw_out_20)) - (portRef SP (instanceRef raw_out_19)) - (portRef SP (instanceRef raw_out_18)) - (portRef SP (instanceRef raw_out_17)) - (portRef SP (instanceRef raw_out_16)) - (portRef SP (instanceRef raw_out_15)) - (portRef SP (instanceRef raw_out_14)) - (portRef SP (instanceRef raw_out_13)) - (portRef SP (instanceRef raw_out_12)) - (portRef SP (instanceRef raw_out_11)) - (portRef SP (instanceRef raw_out_10)) - (portRef SP (instanceRef raw_out_9)) - (portRef SP (instanceRef raw_out_8)) - (portRef SP (instanceRef raw_out_7)) - (portRef SP (instanceRef raw_out_6)) - (portRef SP (instanceRef raw_out_5)) - (portRef SP (instanceRef raw_out_4)) - (portRef SP (instanceRef raw_out_3)) - (portRef SP (instanceRef raw_out_2)) - (portRef SP (instanceRef raw_out_1)) - (portRef SP (instanceRef raw_out_0)) - (portRef D (instanceRef raw_out_valid)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef (member pll_clks 0) (instanceRef tdc_neg_inst)) - (portRef (member pll_clks 0) (instanceRef tdc_inst)) - (portRef CK (instanceRef buf_negative_11)) - (portRef CK (instanceRef buf_negative_10)) - (portRef CK (instanceRef buf_negative_9)) - (portRef CK (instanceRef buf_negative_8)) - (portRef CK (instanceRef buf_negative_7)) - (portRef CK (instanceRef buf_negative_6)) - (portRef CK (instanceRef buf_negative_5)) - (portRef CK (instanceRef buf_negative_4)) - (portRef CK (instanceRef buf_negative_3)) - (portRef CK (instanceRef buf_negative_2)) - (portRef CK (instanceRef buf_negative_1)) - (portRef CK (instanceRef buf_negative_0)) - (portRef CK (instanceRef buf_negative_ready)) - (portRef CK (instanceRef buf_positive_11)) - (portRef CK (instanceRef buf_positive_10)) - (portRef CK (instanceRef buf_positive_9)) - (portRef CK (instanceRef buf_positive_8)) - (portRef CK (instanceRef buf_positive_7)) - (portRef CK (instanceRef buf_positive_6)) - (portRef CK (instanceRef buf_positive_5)) - (portRef CK (instanceRef buf_positive_4)) - (portRef CK (instanceRef buf_positive_3)) - (portRef CK (instanceRef buf_positive_2)) - (portRef CK (instanceRef buf_positive_1)) - (portRef CK (instanceRef buf_positive_0)) - (portRef CK (instanceRef buf_positive_ready)) - (portRef CK (instanceRef raw_out_23)) - (portRef CK (instanceRef raw_out_22)) - (portRef CK (instanceRef raw_out_21)) - (portRef CK (instanceRef raw_out_20)) - (portRef CK (instanceRef raw_out_19)) - (portRef CK (instanceRef raw_out_18)) - (portRef CK (instanceRef raw_out_17)) - (portRef CK (instanceRef raw_out_16)) - (portRef CK (instanceRef raw_out_15)) - (portRef CK (instanceRef raw_out_14)) - (portRef CK (instanceRef raw_out_13)) - (portRef CK (instanceRef raw_out_12)) - (portRef CK (instanceRef raw_out_11)) - (portRef CK (instanceRef raw_out_10)) - (portRef CK (instanceRef raw_out_9)) - (portRef CK (instanceRef raw_out_8)) - (portRef CK (instanceRef raw_out_7)) - (portRef CK (instanceRef raw_out_6)) - (portRef CK (instanceRef raw_out_5)) - (portRef CK (instanceRef raw_out_4)) - (portRef CK (instanceRef raw_out_3)) - (portRef CK (instanceRef raw_out_2)) - (portRef CK (instanceRef raw_out_1)) - (portRef CK (instanceRef raw_out_0)) - (portRef CK (instanceRef raw_out_valid)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef reset_dl_0 (instanceRef dec_neg_inst)) - (portRef reset_dl_0 (instanceRef dec_inst)) - (portRef CD (instanceRef raw_out_23)) - (portRef CD (instanceRef raw_out_22)) - (portRef CD (instanceRef raw_out_21)) - (portRef CD (instanceRef raw_out_20)) - (portRef CD (instanceRef raw_out_19)) - (portRef CD (instanceRef raw_out_18)) - (portRef CD (instanceRef raw_out_17)) - (portRef CD (instanceRef raw_out_16)) - (portRef CD (instanceRef raw_out_15)) - (portRef CD (instanceRef raw_out_14)) - (portRef CD (instanceRef raw_out_13)) - (portRef CD (instanceRef raw_out_12)) - (portRef CD (instanceRef raw_out_11)) - (portRef CD (instanceRef raw_out_10)) - (portRef CD (instanceRef raw_out_9)) - (portRef CD (instanceRef raw_out_8)) - (portRef CD (instanceRef raw_out_7)) - (portRef CD (instanceRef raw_out_6)) - (portRef CD (instanceRef raw_out_5)) - (portRef CD (instanceRef raw_out_4)) - (portRef CD (instanceRef raw_out_3)) - (portRef CD (instanceRef raw_out_2)) - (portRef CD (instanceRef raw_out_1)) - (portRef CD (instanceRef raw_out_0)) - (portRef CD (instanceRef raw_out_valid)) - )) - (net hades_raw_out_valid (joined - (portRef Q (instanceRef raw_out_valid)) - (portRef hades_raw_out_valid) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef C1 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef B1 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef A1 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef D0 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef C0 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef B0 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef A0 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef D0 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef C0 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef B0 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef A0 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef D1 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef C1 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef B1 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef A1 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef D0 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef C0 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef B0 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef A0 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef D0 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef C0 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef B0 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef A0 (instanceRef un1_coarse_1_0_I_1_0)) - )) - (net (rename buf_positive_0 "buf_positive[0]") (joined - (portRef Q (instanceRef buf_positive_0)) - (portRef D (instanceRef raw_out_0)) - )) - (net (rename hades_raw_out_0 "hades_raw_out[0]") (joined - (portRef Q (instanceRef raw_out_0)) - (portRef (member hades_raw_out 23)) - )) - (net (rename buf_positive_1 "buf_positive[1]") (joined - (portRef Q (instanceRef buf_positive_1)) - (portRef D (instanceRef raw_out_1)) - )) - (net (rename hades_raw_out_1 "hades_raw_out[1]") (joined - (portRef Q (instanceRef raw_out_1)) - (portRef (member hades_raw_out 22)) - )) - (net (rename buf_positive_2 "buf_positive[2]") (joined - (portRef Q (instanceRef buf_positive_2)) - (portRef D (instanceRef raw_out_2)) - )) - (net (rename hades_raw_out_2 "hades_raw_out[2]") (joined - (portRef Q (instanceRef raw_out_2)) - (portRef (member hades_raw_out 21)) - )) - (net (rename buf_positive_3 "buf_positive[3]") (joined - (portRef Q (instanceRef buf_positive_3)) - (portRef B1 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef D (instanceRef raw_out_3)) - )) - (net (rename hades_raw_out_3 "hades_raw_out[3]") (joined - (portRef Q (instanceRef raw_out_3)) - (portRef (member hades_raw_out 20)) - )) - (net (rename buf_positive_4 "buf_positive[4]") (joined - (portRef Q (instanceRef buf_positive_4)) - (portRef A1 (instanceRef un1_buf_positive_0_I_1_0)) - (portRef D (instanceRef raw_out_4)) - )) - (net (rename hades_raw_out_4 "hades_raw_out[4]") (joined - (portRef Q (instanceRef raw_out_4)) - (portRef (member hades_raw_out 19)) - )) - (net (rename hades_raw_out_5 "hades_raw_out[5]") (joined - (portRef Q (instanceRef raw_out_5)) - (portRef (member hades_raw_out 18)) - )) - (net (rename buf_positive_6 "buf_positive[6]") (joined - (portRef Q (instanceRef buf_positive_6)) - (portRef B0 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef D (instanceRef raw_out_6)) - )) - (net (rename hades_raw_out_6 "hades_raw_out[6]") (joined - (portRef Q (instanceRef raw_out_6)) - (portRef (member hades_raw_out 17)) - )) - (net (rename buf_positive_7 "buf_positive[7]") (joined - (portRef Q (instanceRef buf_positive_7)) - (portRef D (instanceRef un1_buf_positive_0_I_9_0_RNO_0)) - (portRef D (instanceRef raw_out_7)) - )) - (net (rename hades_raw_out_7 "hades_raw_out[7]") (joined - (portRef Q (instanceRef raw_out_7)) - (portRef (member hades_raw_out 16)) - )) - (net (rename buf_positive_8 "buf_positive[8]") (joined - (portRef Q (instanceRef buf_positive_8)) - (portRef B1 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef D (instanceRef raw_out_8)) - )) - (net (rename hades_raw_out_8 "hades_raw_out[8]") (joined - (portRef Q (instanceRef raw_out_8)) - (portRef (member hades_raw_out 15)) - )) - (net (rename buf_positive_9 "buf_positive[9]") (joined - (portRef Q (instanceRef buf_positive_9)) - (portRef D (instanceRef raw_out_9)) - )) - (net (rename hades_raw_out_9 "hades_raw_out[9]") (joined - (portRef Q (instanceRef raw_out_9)) - (portRef (member hades_raw_out 14)) - )) - (net (rename buf_positive_10 "buf_positive[10]") (joined - (portRef Q (instanceRef buf_positive_10)) - (portRef D (instanceRef raw_out_10)) - )) - (net (rename hades_raw_out_10 "hades_raw_out[10]") (joined - (portRef Q (instanceRef raw_out_10)) - (portRef (member hades_raw_out 13)) - )) - (net (rename buf_positive_11 "buf_positive[11]") (joined - (portRef Q (instanceRef buf_positive_11)) - (portRef D (instanceRef raw_out_11)) - )) - (net (rename hades_raw_out_11 "hades_raw_out[11]") (joined - (portRef Q (instanceRef raw_out_11)) - (portRef (member hades_raw_out 12)) - )) - (net (rename buf_negative_0 "buf_negative[0]") (joined - (portRef Q (instanceRef buf_negative_0)) - (portRef D (instanceRef raw_out_12)) - )) - (net (rename hades_raw_out_12 "hades_raw_out[12]") (joined - (portRef Q (instanceRef raw_out_12)) - (portRef (member hades_raw_out 11)) - )) - (net (rename buf_negative_1 "buf_negative[1]") (joined - (portRef Q (instanceRef buf_negative_1)) - (portRef D (instanceRef raw_out_13)) - )) - (net (rename hades_raw_out_13 "hades_raw_out[13]") (joined - (portRef Q (instanceRef raw_out_13)) - (portRef (member hades_raw_out 10)) - )) - (net (rename buf_negative_2 "buf_negative[2]") (joined - (portRef Q (instanceRef buf_negative_2)) - (portRef D (instanceRef raw_out_14)) - )) - (net (rename hades_raw_out_14 "hades_raw_out[14]") (joined - (portRef Q (instanceRef raw_out_14)) - (portRef (member hades_raw_out 9)) - )) - (net (rename buf_negative_3 "buf_negative[3]") (joined - (portRef Q (instanceRef buf_negative_3)) - (portRef B1 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef D (instanceRef raw_out_15)) - )) - (net (rename hades_raw_out_15 "hades_raw_out[15]") (joined - (portRef Q (instanceRef raw_out_15)) - (portRef (member hades_raw_out 8)) - )) - (net (rename buf_negative_4 "buf_negative[4]") (joined - (portRef Q (instanceRef buf_negative_4)) - (portRef A1 (instanceRef un1_coarse_1_0_I_1_0)) - (portRef D (instanceRef raw_out_16)) - )) - (net (rename hades_raw_out_16 "hades_raw_out[16]") (joined - (portRef Q (instanceRef raw_out_16)) - (portRef (member hades_raw_out 7)) - )) - (net (rename hades_raw_out_17 "hades_raw_out[17]") (joined - (portRef Q (instanceRef raw_out_17)) - (portRef (member hades_raw_out 6)) - )) - (net (rename buf_negative_6 "buf_negative[6]") (joined - (portRef Q (instanceRef buf_negative_6)) - (portRef B0 (instanceRef un1_coarse_1_0_I_9_0)) - (portRef D (instanceRef raw_out_18)) - )) - (net (rename hades_raw_out_18 "hades_raw_out[18]") (joined - (portRef Q (instanceRef raw_out_18)) - (portRef (member hades_raw_out 5)) - )) - (net (rename buf_negative_7 "buf_negative[7]") (joined - (portRef Q (instanceRef buf_negative_7)) - (portRef D (instanceRef un1_coarse_1_0_I_9_RNO_0)) - (portRef D (instanceRef raw_out_19)) - )) - (net (rename hades_raw_out_19 "hades_raw_out[19]") (joined - (portRef Q (instanceRef raw_out_19)) - (portRef (member hades_raw_out 4)) - )) - (net (rename buf_negative_8 "buf_negative[8]") (joined - (portRef Q (instanceRef buf_negative_8)) - (portRef B1 (instanceRef un1_coarse_1_0_I_9_0)) - (portRef D (instanceRef raw_out_20)) - )) - (net (rename hades_raw_out_20 "hades_raw_out[20]") (joined - (portRef Q (instanceRef raw_out_20)) - (portRef (member hades_raw_out 3)) - )) - (net (rename buf_negative_9 "buf_negative[9]") (joined - (portRef Q (instanceRef buf_negative_9)) - (portRef D (instanceRef raw_out_21)) - )) - (net (rename hades_raw_out_21 "hades_raw_out[21]") (joined - (portRef Q (instanceRef raw_out_21)) - (portRef (member hades_raw_out 2)) - )) - (net (rename buf_negative_10 "buf_negative[10]") (joined - (portRef Q (instanceRef buf_negative_10)) - (portRef D (instanceRef raw_out_22)) - )) - (net (rename hades_raw_out_22 "hades_raw_out[22]") (joined - (portRef Q (instanceRef raw_out_22)) - (portRef (member hades_raw_out 1)) - )) - (net (rename buf_negative_11 "buf_negative[11]") (joined - (portRef Q (instanceRef buf_negative_11)) - (portRef D (instanceRef raw_out_23)) - )) - (net (rename hades_raw_out_23 "hades_raw_out[23]") (joined - (portRef Q (instanceRef raw_out_23)) - (portRef (member hades_raw_out 0)) - )) - (net N_7 (joined - (portRef Z (instanceRef buf_positive_ready_4_iv_i_0)) - (portRef D (instanceRef buf_positive_ready)) - )) - (net (rename reset_dl_i_0 "reset_dl_i[2]") (joined - (portRef reset_dl_i_0) - (portRef SP (instanceRef buf_negative_ready)) - (portRef SP (instanceRef buf_positive_ready)) - )) - (net buf_positive_ready (joined - (portRef Q (instanceRef buf_positive_ready)) - (portRef buf_positive_ready (instanceRef dec_neg_inst)) - (portRef B (instanceRef buf_negative_ready_RNIG7JA)) - (portRef B (instanceRef buf_negative_ready_4_f0_0_0)) - (portRef B (instanceRef buf_positive_ready_4_iv_i_0)) - )) - (net (rename decoder_out_0 "decoder_out[0]") (joined - (portRef (member decoder_out 2) (instanceRef dec_inst)) - (portRef D (instanceRef buf_positive_0)) - )) - (net N_251_i (joined - (portRef N_251_i (instanceRef dec_inst)) - (portRef SP (instanceRef buf_positive_11)) - (portRef SP (instanceRef buf_positive_10)) - (portRef SP (instanceRef buf_positive_9)) - (portRef SP (instanceRef buf_positive_8)) - (portRef SP (instanceRef buf_positive_7)) - (portRef SP (instanceRef buf_positive_6)) - (portRef SP (instanceRef buf_positive_5)) - (portRef SP (instanceRef buf_positive_4)) - (portRef SP (instanceRef buf_positive_3)) - (portRef SP (instanceRef buf_positive_2)) - (portRef SP (instanceRef buf_positive_1)) - (portRef SP (instanceRef buf_positive_0)) - )) - (net (rename decoder_out_1 "decoder_out[1]") (joined - (portRef (member decoder_out 1) (instanceRef dec_inst)) - (portRef D (instanceRef buf_positive_1)) - )) - (net (rename decoder_out_2 "decoder_out[2]") (joined - (portRef (member decoder_out 0) (instanceRef dec_inst)) - (portRef D (instanceRef buf_positive_2)) - )) - (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined - (portRef (member hades_dbg2_coarse_c 5)) - (portRef D0 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef D0 (instanceRef un1_coarse_1_0_I_9_0)) - (portRef A (instanceRef un1_coarse_1_0_I_9_RNO_0)) - (portRef A (instanceRef un1_buf_positive_0_I_9_0_RNO_0)) - (portRef D (instanceRef buf_negative_6)) - (portRef D (instanceRef buf_positive_6)) - )) - (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined - (portRef (member hades_dbg2_coarse_c 4)) - (portRef B (instanceRef un1_coarse_1_0_I_9_RNO_0)) - (portRef B (instanceRef un1_buf_positive_0_I_9_0_RNO_0)) - (portRef D (instanceRef buf_negative_7)) - (portRef D (instanceRef buf_positive_7)) - )) - (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined - (portRef (member hades_dbg2_coarse_c 3)) - (portRef D1 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef D1 (instanceRef un1_coarse_1_0_I_9_0)) - (portRef D (instanceRef buf_negative_8)) - (portRef D (instanceRef buf_positive_8)) - )) - (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined - (portRef (member hades_dbg2_coarse_c 2)) - (portRef A0 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef A0 (instanceRef un1_coarse_1_0_I_21_0)) - (portRef D (instanceRef buf_negative_9)) - (portRef D (instanceRef buf_positive_9)) - )) - (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined - (portRef (member hades_dbg2_coarse_c 1)) - (portRef B0 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef B0 (instanceRef un1_coarse_1_0_I_21_0)) - (portRef D (instanceRef buf_negative_10)) - (portRef D (instanceRef buf_positive_10)) - )) - (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined - (portRef (member hades_dbg2_coarse_c 0)) - (portRef A1 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef A1 (instanceRef un1_coarse_1_0_I_21_0)) - (portRef D (instanceRef buf_negative_11)) - (portRef D (instanceRef buf_positive_11)) - )) - (net buf_negative_ready_4 (joined - (portRef Z (instanceRef buf_negative_ready_4_f0_0_0)) - (portRef D (instanceRef buf_negative_ready)) - )) - (net buf_negative_ready (joined - (portRef Q (instanceRef buf_negative_ready)) - (portRef A (instanceRef buf_negative_ready_RNIG7JA)) - (portRef A (instanceRef buf_negative_ready_4_f0_0_0)) - (portRef A (instanceRef buf_positive_ready_4_iv_i_0)) - )) - (net (rename decoder_out_neg_0 "decoder_out_neg[0]") (joined - (portRef (member decoder_out_neg 2) (instanceRef dec_neg_inst)) - (portRef D (instanceRef buf_negative_0)) - )) - (net N_11_i (joined - (portRef N_11_i (instanceRef dec_neg_inst)) - (portRef SP (instanceRef buf_negative_11)) - (portRef SP (instanceRef buf_negative_10)) - (portRef SP (instanceRef buf_negative_9)) - (portRef SP (instanceRef buf_negative_8)) - (portRef SP (instanceRef buf_negative_7)) - (portRef SP (instanceRef buf_negative_6)) - (portRef SP (instanceRef buf_negative_5)) - (portRef SP (instanceRef buf_negative_4)) - (portRef SP (instanceRef buf_negative_3)) - (portRef SP (instanceRef buf_negative_2)) - (portRef SP (instanceRef buf_negative_1)) - (portRef SP (instanceRef buf_negative_0)) - )) - (net (rename decoder_out_neg_1 "decoder_out_neg[1]") (joined - (portRef (member decoder_out_neg 1) (instanceRef dec_neg_inst)) - (portRef D (instanceRef buf_negative_1)) - )) - (net (rename decoder_out_neg_2 "decoder_out_neg[2]") (joined - (portRef (member decoder_out_neg 0) (instanceRef dec_neg_inst)) - (portRef D (instanceRef buf_negative_2)) - )) - (net drop_cmp_buf_coarse_2_c3 (joined - (portRef drop_cmp_buf_coarse_2_c3) - (portRef C0 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef C0 (instanceRef un1_coarse_1_0_I_9_0)) - (portRef C (instanceRef un1_coarse_1_0_I_9_RNO_0)) - (portRef C (instanceRef un1_buf_positive_0_I_9_0_RNO_0)) - )) - (net un1_buf_positive_0_N_14 (joined - (portRef Z (instanceRef un1_buf_positive_0_I_9_0_RNO_0)) - (portRef A1 (instanceRef un1_buf_positive_0_I_9_0)) - )) - (net un1_coarse_1_0_N_14 (joined - (portRef Z (instanceRef un1_coarse_1_0_I_9_RNO_0)) - (portRef A1 (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net decoder_valid (joined - (portRef decoder_valid (instanceRef dec_inst)) - (portRef C (instanceRef buf_positive_ready_4_iv_i_0)) - )) - (net un1_buf_positive_i (joined - (portRef S0 (instanceRef un1_buf_positive_0_I_27_0)) - (portRef D (instanceRef buf_positive_ready_4_iv_i_0)) - )) - (net decoder_valid_neg (joined - (portRef decoder_valid_neg (instanceRef dec_neg_inst)) - (portRef C (instanceRef buf_negative_ready_4_f0_0_0)) - )) - (net un1_coarse_1_i (joined - (portRef S0 (instanceRef un1_coarse_1_0_I_27_0)) - (portRef D (instanceRef buf_negative_ready_4_f0_0_0)) - )) - (net (rename un1_coarse_1_0_data_tmp_0 "un1_coarse_1_0_data_tmp[0]") (joined - (portRef COUT (instanceRef un1_coarse_1_0_I_1_0)) - (portRef CIN (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net un1_coarse_1_0_I_1_0_S0 (joined - (portRef S0 (instanceRef un1_coarse_1_0_I_1_0)) - )) - (net un1_coarse_1_0_I_1_0_S1 (joined - (portRef S1 (instanceRef un1_coarse_1_0_I_1_0)) - )) - (net drop_cmp_buf_coarse_2_c5 (joined - (portRef drop_cmp_buf_coarse_2_c5) - (portRef C1 (instanceRef un1_buf_positive_0_I_9_0)) - (portRef C1 (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net (rename un1_coarse_1_0_data_tmp_2 "un1_coarse_1_0_data_tmp[2]") (joined - (portRef COUT (instanceRef un1_coarse_1_0_I_9_0)) - (portRef CIN (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net un1_coarse_1_0_I_9_0_S0 (joined - (portRef S0 (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net un1_coarse_1_0_I_9_0_S1 (joined - (portRef S1 (instanceRef un1_coarse_1_0_I_9_0)) - )) - (net drop_cmp_buf_coarse_2_ac0_9_0 (joined - (portRef drop_cmp_buf_coarse_2_ac0_9_0) - (portRef C1 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef C0 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef C1 (instanceRef un1_coarse_1_0_I_21_0)) - (portRef C0 (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net drop_cmp_buf_coarse_2_c4 (joined - (portRef drop_cmp_buf_coarse_2_c4) - (portRef D1 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef D0 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef D1 (instanceRef un1_coarse_1_0_I_21_0)) - (portRef D0 (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net drop_cmp_buf_coarse_2_ac0_13_0 (joined - (portRef drop_cmp_buf_coarse_2_ac0_13_0) - (portRef B1 (instanceRef un1_buf_positive_0_I_21_0)) - (portRef B1 (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net un1_coarse_1_0_I_27_cry (joined - (portRef COUT (instanceRef un1_coarse_1_0_I_21_0)) - (portRef CIN (instanceRef un1_coarse_1_0_I_27_0)) - )) - (net un1_coarse_1_0_I_21_0_S0 (joined - (portRef S0 (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net un1_coarse_1_0_I_21_0_S1 (joined - (portRef S1 (instanceRef un1_coarse_1_0_I_21_0)) - )) - (net un1_coarse_1_0_I_27_0_COUT (joined - (portRef COUT (instanceRef un1_coarse_1_0_I_27_0)) - )) - (net un1_coarse_1_0_I_27_0_S1 (joined - (portRef S1 (instanceRef un1_coarse_1_0_I_27_0)) - )) - (net (rename un1_buf_positive_0_data_tmp_0 "un1_buf_positive_0_data_tmp[0]") (joined - (portRef COUT (instanceRef un1_buf_positive_0_I_1_0)) - (portRef CIN (instanceRef un1_buf_positive_0_I_9_0)) - )) - (net un1_buf_positive_0_I_1_0_S0 (joined - (portRef S0 (instanceRef un1_buf_positive_0_I_1_0)) - )) - (net un1_buf_positive_0_I_1_0_S1 (joined - (portRef S1 (instanceRef un1_buf_positive_0_I_1_0)) - )) - (net (rename un1_buf_positive_0_data_tmp_2 "un1_buf_positive_0_data_tmp[2]") (joined - (portRef COUT (instanceRef un1_buf_positive_0_I_9_0)) - (portRef CIN (instanceRef un1_buf_positive_0_I_21_0)) - )) - (net un1_buf_positive_0_I_9_0_S0 (joined - (portRef S0 (instanceRef un1_buf_positive_0_I_9_0)) - )) - (net un1_buf_positive_0_I_9_0_S1 (joined - (portRef S1 (instanceRef un1_buf_positive_0_I_9_0)) - )) - (net un1_buf_positive_0_I_27_cry (joined - (portRef COUT (instanceRef un1_buf_positive_0_I_21_0)) - (portRef CIN (instanceRef un1_buf_positive_0_I_27_0)) - )) - (net un1_buf_positive_0_I_21_0_S0 (joined - (portRef S0 (instanceRef un1_buf_positive_0_I_21_0)) - )) - (net un1_buf_positive_0_I_21_0_S1 (joined - (portRef S1 (instanceRef un1_buf_positive_0_I_21_0)) - )) - (net un1_buf_positive_0_I_27_0_COUT (joined - (portRef COUT (instanceRef un1_buf_positive_0_I_27_0)) - )) - (net un1_buf_positive_0_I_27_0_S1 (joined - (portRef S1 (instanceRef un1_buf_positive_0_I_27_0)) - )) - (net hades_trig_c_i (joined - (portRef hades_trig_c_i) - (portRef hades_trig_c_i (instanceRef tdc_inst)) - (portRef hades_trig_c_i (instanceRef trig_inv_inst1)) - )) - (net trig_gate_neg (joined - (portRef trig_gate_neg (instanceRef trig_inv_inst1)) - (portRef trig_gate_neg (instanceRef tdc_neg_inst)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7) (instanceRef tdc_inst)) - (portRef (member tdc_out 7) (instanceRef dec_inst)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6) (instanceRef tdc_inst)) - (portRef (member tdc_out 6) (instanceRef dec_inst)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5) (instanceRef tdc_inst)) - (portRef (member tdc_out 5) (instanceRef dec_inst)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4) (instanceRef tdc_inst)) - (portRef (member tdc_out 4) (instanceRef dec_inst)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3) (instanceRef tdc_inst)) - (portRef (member tdc_out 3) (instanceRef dec_inst)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2) (instanceRef tdc_inst)) - (portRef (member tdc_out 2) (instanceRef dec_inst)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1) (instanceRef tdc_inst)) - (portRef (member tdc_out 1) (instanceRef dec_inst)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0) (instanceRef tdc_inst)) - (portRef (member tdc_out 0) (instanceRef dec_inst)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef tdc_neg_inst)) - (portRef (member pll_clks 3) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef tdc_neg_inst)) - (portRef (member pll_clks 2) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef tdc_neg_inst)) - (portRef (member pll_clks 1) (instanceRef tdc_inst)) - )) - (net CN (joined - (portRef CN) - (portRef CN_2 (instanceRef tdc_neg_inst)) - (portRef CN_2 (instanceRef tdc_inst)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CN_1 (instanceRef tdc_neg_inst)) - (portRef CN_1 (instanceRef tdc_inst)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CN_0 (instanceRef tdc_neg_inst)) - (portRef CN_0 (instanceRef tdc_inst)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CN (instanceRef dec_neg_inst)) - (portRef CN (instanceRef dec_inst)) - (portRef CN (instanceRef tdc_neg_inst)) - (portRef CN (instanceRef tdc_inst)) - )) - (net (rename tdc_out_neg_0 "tdc_out_neg[0]") (joined - (portRef (member tdc_out_neg 7) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 7) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_1 "tdc_out_neg[1]") (joined - (portRef (member tdc_out_neg 6) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 6) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_2 "tdc_out_neg[2]") (joined - (portRef (member tdc_out_neg 5) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 5) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_3 "tdc_out_neg[3]") (joined - (portRef (member tdc_out_neg 4) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 4) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_4 "tdc_out_neg[4]") (joined - (portRef (member tdc_out_neg 3) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 3) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_5 "tdc_out_neg[5]") (joined - (portRef (member tdc_out_neg 2) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 2) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_6 "tdc_out_neg[6]") (joined - (portRef (member tdc_out_neg 1) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 1) (instanceRef dec_neg_inst)) - )) - (net (rename tdc_out_neg_7 "tdc_out_neg[7]") (joined - (portRef (member tdc_out_neg 0) (instanceRef tdc_neg_inst)) - (portRef (member tdc_out_neg 0) (instanceRef dec_neg_inst)) - )) - (net N_1 (joined - (portRef CIN (instanceRef un1_buf_positive_0_I_1_0)) - )) - (net N_2 (joined - (portRef CIN (instanceRef un1_coarse_1_0_I_1_0)) - )) - ) - (property TDC_WIDTH (integer 3)) - (property COARSE_WIDTH (integer 9)) - (property orig_inst_of (string "hades_tdc_channel_raw_out")) - ) - ) - (cell hades_LVL1_raw_out (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port (array (rename hades_invalid_dl_c "hades_invalid_dl_c[3:0]") 4) (direction INOUT)) - (port reset_dl_0 (direction INPUT)) - (port trig_dl_0 (direction INPUT)) - (port (array (rename hit_i "hit_i[1:0]") 2) (direction INPUT)) - (port valid_fast_RNI999V (direction OUTPUT)) - (port CN_2 (direction OUTPUT)) - (port CN_1 (direction OUTPUT)) - (port CN_0 (direction OUTPUT)) - (port CN (direction OUTPUT)) - (port hades_lvl1_c_i (direction INPUT)) - (port N_44 (direction OUTPUT)) - (port N_40 (direction OUTPUT)) - (port N_46_i (direction OUTPUT)) - (port N_59_i (direction OUTPUT)) - (port hades_offset_valid_c (direction OUTPUT)) - (port offset_1_sqmuxa_i_0_1z (direction OUTPUT)) - (port hades_window_end_c (direction OUTPUT)) - (port N_50_i_i_1z (direction OUTPUT)) - (port ANB0 (direction INPUT)) - (port ANB1 (direction INPUT)) - (port ANB2 (direction INPUT)) - (port ANB3 (direction INPUT)) - (port SUM1_0_0_1z (direction OUTPUT)) - (port hades_raw_out_valid (direction INPUT)) - (port hades_discard_c (direction OUTPUT)) - ) - (contents - (instance (rename window_RNO_0 "window_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A+B A)+C (!B+A))+D (!B !A+B A))")) - ) - (instance (rename trig_dl_RNI41GL1_3 "trig_dl_RNI41GL1[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B+A))+D (B+A))")) - ) - (instance SUM1_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (!B A+B !A))")) - ) - (instance N_50_i_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) - ) - (instance window_end (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename window_0 "window[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_1 "window[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_2 "window[2]") (viewRef PRIM (cellRef FD1S3JX (libraryRef LUCENT))) - ) - (instance (rename window_3 "window[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_4 "window[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_5 "window[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_6 "window[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename window_7 "window[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename trig_dl_1 "trig_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename trig_dl_2 "trig_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename trig_dl_3 "trig_dl[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance offset_valid (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename invalid_dl_1 "invalid_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename invalid_dl_2 "invalid_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename invalid_dl_3 "invalid_dl[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance discard (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance un1_reset_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance offset_1_sqmuxa_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !A+C (B+!A))+D !A)")) - ) - (instance discard_en (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (B A)))")) - ) - (instance un1_reset_0_a2_c (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance window_end5_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance un1_reset_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename window_6_7 "window_6[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_6 "window_6[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_5 "window_6[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_4 "window_6[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_3 "window_6[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_2 "window_6[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance (rename window_6_1 "window_6[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D C)")) - ) - (instance window_0_sqmuxadup (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B+A)))")) - ) - (instance discard4_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance offset_valid_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) - ) - (instance discard4_0_a2_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance un1_invalid_dl (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance SUM0_1_0_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A+B !A)")) - ) - (instance SUM1_1_x2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A+B !A)")) - ) - (instance SUM1_0_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance offset_1_sqmuxa_i_0_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+A)")) - ) - (instance (rename window_RNIOA5C_2 "window_RNIOA5C[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename window_RNICU4C_3 "window_RNICU4C[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance SUM1_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C+(!B+A))")) - ) - (instance un1_window_8_cry_0_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x5003")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0xa90a")) - ) - (instance un1_window_8_cry_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0xa90a")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0xa90a")) - ) - (instance un1_window_8_cry_3_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0xa90a")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0xa90a")) - ) - (instance un1_window_8_cry_5_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0xa90a")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0xa90a")) - ) - (instance un1_window_8_s_7_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x900a")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x5003")) - ) - (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short)) - ) - (instance dec_inst (viewRef netlist (cellRef output_decoder8_0)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename window_0 "window[0]") (joined - (portRef Q (instanceRef window_0)) - (portRef A1 (instanceRef un1_window_8_cry_0_0)) - (portRef A (instanceRef window_RNICU4C_3)) - (portRef B (instanceRef un1_reset_0_a2_1)) - (portRef B (instanceRef window_end5_0_a2)) - (portRef C (instanceRef un1_reset_0_a2_c)) - (portRef B (instanceRef discard_en)) - (portRef C (instanceRef offset_1_sqmuxa_i_0)) - (portRef A (instanceRef window_RNO_0)) - )) - (net un1_reset_0_a2_2 (joined - (portRef Z (instanceRef un1_reset_0_a2_2)) - (portRef B0 (instanceRef un1_window_8_s_7_0)) - (portRef B (instanceRef window_RNO_0)) - )) - (net valid_fast (joined - (portRef valid_fast_1z (instanceRef dec_inst)) - (portRef B (instanceRef offset_1_sqmuxa_i_0_o2)) - (portRef C (instanceRef window_RNO_0)) - )) - (net hades_discard_c (joined - (portRef Q (instanceRef discard)) - (portRef hades_discard_c (instanceRef dec_inst)) - (portRef A (instanceRef offset_1_sqmuxa_i_0_o2)) - (portRef A (instanceRef offset_valid_RNO)) - (portRef A (instanceRef window_6_1)) - (portRef A (instanceRef window_6_2)) - (portRef A (instanceRef window_6_3)) - (portRef A (instanceRef window_6_4)) - (portRef A (instanceRef window_6_5)) - (portRef A (instanceRef window_6_6)) - (portRef A (instanceRef window_6_7)) - (portRef B (instanceRef un1_reset_0_a2_c)) - (portRef A (instanceRef un1_reset_0_a2_2)) - (portRef D (instanceRef window_RNO_0)) - (portRef hades_discard_c) - )) - (net (rename window_6_0 "window_6[0]") (joined - (portRef Z (instanceRef window_RNO_0)) - (portRef D (instanceRef window_0)) - )) - (net (rename trig_dl_3 "trig_dl[3]") (joined - (portRef Q (instanceRef trig_dl_3)) - (portRef B (instanceRef window_0_sqmuxadup)) - (portRef A (instanceRef trig_dl_RNI41GL1_3)) - )) - (net (rename trig_dl_2 "trig_dl[2]") (joined - (portRef Q (instanceRef trig_dl_2)) - (portRef A (instanceRef window_0_sqmuxadup)) - (portRef D (instanceRef trig_dl_3)) - (portRef B (instanceRef trig_dl_RNI41GL1_3)) - )) - (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined - (portRef Q (instanceRef invalid_dl_3)) - (portRef (member hades_invalid_dl_c 0)) - (portRef B (instanceRef un1_invalid_dl)) - (portRef C (instanceRef trig_dl_RNI41GL1_3)) - )) - (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined - (portRef Q (instanceRef invalid_dl_2)) - (portRef (member hades_invalid_dl_c 1)) - (portRef A (instanceRef un1_invalid_dl)) - (portRef D (instanceRef invalid_dl_3)) - (portRef D (instanceRef trig_dl_RNI41GL1_3)) - )) - (net window_0_sqmuxa (joined - (portRef Z (instanceRef trig_dl_RNI41GL1_3)) - (portRef D (instanceRef discard_en)) - (portRef D (instanceRef discard)) - )) - (net (rename hit_i_1 "hit_i[1]") (joined - (portRef (member hit_i 0)) - (portRef A (instanceRef SUM1_0_0_o2_0)) - (portRef A (instanceRef SUM1_0_0)) - )) - (net (rename hit_i_0 "hit_i[0]") (joined - (portRef (member hit_i 1)) - (portRef B (instanceRef SUM1_0_0_o2_0)) - (portRef B (instanceRef SUM1_0_0_o2)) - (portRef B (instanceRef SUM0_1_0_x2)) - (portRef B (instanceRef SUM1_0_0)) - )) - (net hades_raw_out_valid (joined - (portRef hades_raw_out_valid) - (portRef C (instanceRef SUM1_0_0_o2_0)) - (portRef A (instanceRef SUM1_0_0_o2)) - (portRef A (instanceRef SUM0_1_0_x2)) - (portRef C (instanceRef SUM1_0_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef un1_window_8_s_7_0)) - (portRef C1 (instanceRef un1_window_8_s_7_0)) - (portRef B1 (instanceRef un1_window_8_s_7_0)) - (portRef A1 (instanceRef un1_window_8_s_7_0)) - (portRef D0 (instanceRef un1_window_8_s_7_0)) - (portRef C0 (instanceRef un1_window_8_s_7_0)) - (portRef D1 (instanceRef un1_window_8_cry_5_0)) - (portRef D0 (instanceRef un1_window_8_cry_5_0)) - (portRef D1 (instanceRef un1_window_8_cry_3_0)) - (portRef D0 (instanceRef un1_window_8_cry_3_0)) - (portRef D1 (instanceRef un1_window_8_cry_1_0)) - (portRef D0 (instanceRef un1_window_8_cry_1_0)) - (portRef D1 (instanceRef un1_window_8_cry_0_0)) - (portRef D0 (instanceRef un1_window_8_cry_0_0)) - (portRef C0 (instanceRef un1_window_8_cry_0_0)) - (portRef B0 (instanceRef un1_window_8_cry_0_0)) - (portRef A0 (instanceRef un1_window_8_cry_0_0)) - )) - (net (rename SUM1_0_0_1z "SUM1_0_0") (joined - (portRef Z (instanceRef SUM1_0_0)) - (portRef SUM1_0_0_1z) - )) - (net ANB3 (joined - (portRef ANB3) - (portRef A (instanceRef N_50_i_i)) - )) - (net ANB2 (joined - (portRef ANB2) - (portRef B (instanceRef N_50_i_i)) - )) - (net ANB1 (joined - (portRef ANB1) - (portRef B (instanceRef SUM1_1_x2)) - (portRef C (instanceRef N_50_i_i)) - )) - (net ANB0 (joined - (portRef ANB0) - (portRef A (instanceRef SUM1_1_x2)) - (portRef D (instanceRef N_50_i_i)) - )) - (net (rename N_50_i_i_1z "N_50_i_i") (joined - (portRef Z (instanceRef N_50_i_i)) - (portRef N_50_i_i_1z) - )) - (net window_end5 (joined - (portRef Z (instanceRef window_end5_0_a2)) - (portRef D (instanceRef window_end)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef pll_clks_0 (instanceRef dec_inst)) - (portRef (member pll_clks 0) (instanceRef tdc_inst)) - (portRef CK (instanceRef discard)) - (portRef CK (instanceRef invalid_dl_3)) - (portRef CK (instanceRef invalid_dl_2)) - (portRef CK (instanceRef invalid_dl_1)) - (portRef CK (instanceRef offset_valid)) - (portRef CK (instanceRef trig_dl_3)) - (portRef CK (instanceRef trig_dl_2)) - (portRef CK (instanceRef trig_dl_1)) - (portRef CK (instanceRef window_7)) - (portRef CK (instanceRef window_6)) - (portRef CK (instanceRef window_5)) - (portRef CK (instanceRef window_4)) - (portRef CK (instanceRef window_3)) - (portRef CK (instanceRef window_2)) - (portRef CK (instanceRef window_1)) - (portRef CK (instanceRef window_0)) - (portRef CK (instanceRef window_end)) - )) - (net hades_window_end_c (joined - (portRef Q (instanceRef window_end)) - (portRef hades_window_end_c) - )) - (net window_0_sqmuxadup (joined - (portRef Z (instanceRef window_0_sqmuxadup)) - (portRef CD (instanceRef window_7)) - (portRef CD (instanceRef window_6)) - (portRef CD (instanceRef window_5)) - (portRef CD (instanceRef window_4)) - (portRef CD (instanceRef window_3)) - (portRef D (instanceRef window_2)) - (portRef CD (instanceRef window_1)) - (portRef CD (instanceRef window_0)) - )) - (net (rename window_6_1 "window_6[1]") (joined - (portRef Z (instanceRef window_6_1)) - (portRef D (instanceRef window_1)) - )) - (net (rename window_1 "window[1]") (joined - (portRef Q (instanceRef window_1)) - (portRef A0 (instanceRef un1_window_8_cry_1_0)) - (portRef B (instanceRef window_RNICU4C_3)) - (portRef C (instanceRef un1_reset_0_a2_1)) - (portRef C (instanceRef window_end5_0_a2)) - (portRef D (instanceRef un1_reset_0_a2_c)) - (portRef C (instanceRef discard_en)) - (portRef D (instanceRef offset_1_sqmuxa_i_0)) - )) - (net (rename window_6_2 "window_6[2]") (joined - (portRef Z (instanceRef window_6_2)) - (portRef PD (instanceRef window_2)) - )) - (net (rename window_2 "window[2]") (joined - (portRef Q (instanceRef window_2)) - (portRef A1 (instanceRef un1_window_8_cry_1_0)) - (portRef A (instanceRef window_RNIOA5C_2)) - (portRef A (instanceRef discard4_0_a2_0_3)) - )) - (net (rename window_6_3 "window_6[3]") (joined - (portRef Z (instanceRef window_6_3)) - (portRef D (instanceRef window_3)) - )) - (net (rename window_3 "window[3]") (joined - (portRef Q (instanceRef window_3)) - (portRef A0 (instanceRef un1_window_8_cry_3_0)) - (portRef C (instanceRef window_RNICU4C_3)) - (portRef B (instanceRef discard4_0_a2_0)) - )) - (net (rename window_6_4 "window_6[4]") (joined - (portRef Z (instanceRef window_6_4)) - (portRef D (instanceRef window_4)) - )) - (net (rename window_4 "window[4]") (joined - (portRef Q (instanceRef window_4)) - (portRef A1 (instanceRef un1_window_8_cry_3_0)) - (portRef D (instanceRef window_RNICU4C_3)) - (portRef C (instanceRef discard4_0_a2_0)) - )) - (net (rename window_6_5 "window_6[5]") (joined - (portRef Z (instanceRef window_6_5)) - (portRef D (instanceRef window_5)) - )) - (net (rename window_5 "window[5]") (joined - (portRef Q (instanceRef window_5)) - (portRef A0 (instanceRef un1_window_8_cry_5_0)) - (portRef B (instanceRef window_RNIOA5C_2)) - (portRef B (instanceRef discard4_0_a2_0_3)) - )) - (net (rename window_6_6 "window_6[6]") (joined - (portRef Z (instanceRef window_6_6)) - (portRef D (instanceRef window_6)) - )) - (net (rename window_6 "window[6]") (joined - (portRef Q (instanceRef window_6)) - (portRef A1 (instanceRef un1_window_8_cry_5_0)) - (portRef C (instanceRef window_RNIOA5C_2)) - (portRef C (instanceRef discard4_0_a2_0_3)) - )) - (net (rename window_6_7 "window_6[7]") (joined - (portRef Z (instanceRef window_6_7)) - (portRef D (instanceRef window_7)) - )) - (net (rename window_7 "window[7]") (joined - (portRef Q (instanceRef window_7)) - (portRef A0 (instanceRef un1_window_8_s_7_0)) - (portRef D (instanceRef window_RNIOA5C_2)) - (portRef D (instanceRef discard4_0_a2_0_3)) - )) - (net (rename trig_dl_0 "trig_dl[0]") (joined - (portRef trig_dl_0) - (portRef D (instanceRef trig_dl_1)) - )) - (net (rename trig_dl_1 "trig_dl[1]") (joined - (portRef Q (instanceRef trig_dl_1)) - (portRef D (instanceRef trig_dl_2)) - )) - (net N_39_i (joined - (portRef Z (instanceRef offset_valid_RNO)) - (portRef D (instanceRef offset_valid)) - )) - (net (rename offset_1_sqmuxa_i_0_1z "offset_1_sqmuxa_i_0") (joined - (portRef Z (instanceRef offset_1_sqmuxa_i_0)) - (portRef offset_1_sqmuxa_i_0 (instanceRef dec_inst)) - (portRef SP (instanceRef offset_valid)) - (portRef offset_1_sqmuxa_i_0_1z) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef reset_dl_0 (instanceRef dec_inst)) - (portRef D (instanceRef window_0_sqmuxadup)) - (portRef D (instanceRef window_6_1)) - (portRef D (instanceRef window_6_2)) - (portRef D (instanceRef window_6_3)) - (portRef D (instanceRef window_6_4)) - (portRef D (instanceRef window_6_5)) - (portRef D (instanceRef window_6_6)) - (portRef D (instanceRef window_6_7)) - (portRef CD (instanceRef discard)) - (portRef CD (instanceRef offset_valid)) - )) - (net hades_offset_valid_c (joined - (portRef Q (instanceRef offset_valid)) - (portRef hades_offset_valid_c) - )) - (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined - (portRef (member hades_invalid_dl_c 3)) - (portRef D (instanceRef invalid_dl_1)) - )) - (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined - (portRef Q (instanceRef invalid_dl_1)) - (portRef (member hades_invalid_dl_c 2)) - (portRef D (instanceRef invalid_dl_2)) - )) - (net discard_en (joined - (portRef Z (instanceRef discard_en)) - (portRef SP (instanceRef discard)) - )) - (net un1_reset_0_a2_1 (joined - (portRef Z (instanceRef un1_reset_0_a2_1)) - (portRef B (instanceRef un1_reset_0_a2_2)) - )) - (net un1_reset_0_a2_2_0 (joined - (portRef un1_reset_0_a2_2_0 (instanceRef dec_inst)) - (portRef B1 (instanceRef un1_window_8_cry_5_0)) - (portRef B0 (instanceRef un1_window_8_cry_5_0)) - (portRef B1 (instanceRef un1_window_8_cry_3_0)) - (portRef B0 (instanceRef un1_window_8_cry_3_0)) - (portRef B1 (instanceRef un1_window_8_cry_1_0)) - (portRef B0 (instanceRef un1_window_8_cry_1_0)) - (portRef B1 (instanceRef un1_window_8_cry_0_0)) - (portRef C (instanceRef un1_reset_0_a2_2)) - )) - (net N_39 (joined - (portRef Z (instanceRef offset_1_sqmuxa_i_0_o2)) - (portRef A (instanceRef offset_1_sqmuxa_i_0)) - )) - (net N_97 (joined - (portRef Z (instanceRef discard4_0_a2_0)) - (portRef A (instanceRef un1_reset_0_a2_1)) - (portRef A (instanceRef window_end5_0_a2)) - (portRef A (instanceRef un1_reset_0_a2_c)) - (portRef A (instanceRef discard_en)) - (portRef B (instanceRef offset_1_sqmuxa_i_0)) - )) - (net un1_reset_0_a2_c (joined - (portRef Z (instanceRef un1_reset_0_a2_c)) - (portRef C1 (instanceRef un1_window_8_cry_5_0)) - (portRef C0 (instanceRef un1_window_8_cry_5_0)) - (portRef C1 (instanceRef un1_window_8_cry_3_0)) - (portRef C0 (instanceRef un1_window_8_cry_3_0)) - (portRef C1 (instanceRef un1_window_8_cry_1_0)) - (portRef C0 (instanceRef un1_window_8_cry_1_0)) - (portRef C1 (instanceRef un1_window_8_cry_0_0)) - )) - (net decoder_valid (joined - (portRef decoder_valid (instanceRef dec_inst)) - (portRef B (instanceRef offset_valid_RNO)) - (portRef B (instanceRef window_6_1)) - (portRef B (instanceRef window_6_2)) - (portRef B (instanceRef window_6_3)) - (portRef B (instanceRef window_6_4)) - (portRef B (instanceRef window_6_5)) - (portRef B (instanceRef window_6_6)) - (portRef B (instanceRef window_6_7)) - )) - (net un1_window_8_s_7_0_S0 (joined - (portRef S0 (instanceRef un1_window_8_s_7_0)) - (portRef C (instanceRef window_6_7)) - )) - (net un1_window_8_cry_5_0_S1 (joined - (portRef S1 (instanceRef un1_window_8_cry_5_0)) - (portRef C (instanceRef window_6_6)) - )) - (net un1_window_8_cry_5_0_S0 (joined - (portRef S0 (instanceRef un1_window_8_cry_5_0)) - (portRef C (instanceRef window_6_5)) - )) - (net un1_window_8_cry_3_0_S1 (joined - (portRef S1 (instanceRef un1_window_8_cry_3_0)) - (portRef C (instanceRef window_6_4)) - )) - (net un1_window_8_cry_3_0_S0 (joined - (portRef S0 (instanceRef un1_window_8_cry_3_0)) - (portRef C (instanceRef window_6_3)) - )) - (net un1_window_8_cry_1_0_S1 (joined - (portRef S1 (instanceRef un1_window_8_cry_1_0)) - (portRef C (instanceRef window_6_2)) - )) - (net un1_window_8_cry_1_0_S0 (joined - (portRef S0 (instanceRef un1_window_8_cry_1_0)) - (portRef C (instanceRef window_6_1)) - )) - (net un1_invalid_dl (joined - (portRef Z (instanceRef un1_invalid_dl)) - (portRef C (instanceRef window_0_sqmuxadup)) - )) - (net discard4_0_a2_0_3 (joined - (portRef Z (instanceRef discard4_0_a2_0_3)) - (portRef A (instanceRef discard4_0_a2_0)) - )) - (net N_59_i (joined - (portRef Z (instanceRef SUM0_1_0_x2)) - (portRef N_59_i) - )) - (net N_46_i (joined - (portRef Z (instanceRef SUM1_1_x2)) - (portRef N_46_i) - )) - (net N_40 (joined - (portRef Z (instanceRef SUM1_0_0_o2)) - (portRef N_40) - )) - (net G_25_0_a3_4_0 (joined - (portRef Z (instanceRef window_RNIOA5C_2)) - (portRef G_25_0_a3_4_0 (instanceRef dec_inst)) - )) - (net G_25_0_a3_5_0 (joined - (portRef Z (instanceRef window_RNICU4C_3)) - (portRef G_25_0_a3_5_0 (instanceRef dec_inst)) - )) - (net N_44 (joined - (portRef Z (instanceRef SUM1_0_0_o2_0)) - (portRef N_44) - )) - (net un1_window_8_cry_0 (joined - (portRef COUT (instanceRef un1_window_8_cry_0_0)) - (portRef CIN (instanceRef un1_window_8_cry_1_0)) - )) - (net un1_window_8_cry_0_0_S0 (joined - (portRef S0 (instanceRef un1_window_8_cry_0_0)) - )) - (net un1_window_8_cry_0_0_S1 (joined - (portRef S1 (instanceRef un1_window_8_cry_0_0)) - )) - (net un1_window_8_cry_2 (joined - (portRef COUT (instanceRef un1_window_8_cry_1_0)) - (portRef CIN (instanceRef un1_window_8_cry_3_0)) - )) - (net un1_window_8_cry_4 (joined - (portRef COUT (instanceRef un1_window_8_cry_3_0)) - (portRef CIN (instanceRef un1_window_8_cry_5_0)) - )) - (net un1_window_8_cry_6 (joined - (portRef COUT (instanceRef un1_window_8_cry_5_0)) - (portRef CIN (instanceRef un1_window_8_s_7_0)) - )) - (net un1_window_8_s_7_0_COUT (joined - (portRef COUT (instanceRef un1_window_8_s_7_0)) - )) - (net un1_window_8_s_7_0_S1 (joined - (portRef S1 (instanceRef un1_window_8_s_7_0)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7) (instanceRef tdc_inst)) - (portRef (member tdc_out 7) (instanceRef dec_inst)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6) (instanceRef tdc_inst)) - (portRef (member tdc_out 6) (instanceRef dec_inst)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5) (instanceRef tdc_inst)) - (portRef (member tdc_out 5) (instanceRef dec_inst)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4) (instanceRef tdc_inst)) - (portRef (member tdc_out 4) (instanceRef dec_inst)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3) (instanceRef tdc_inst)) - (portRef (member tdc_out 3) (instanceRef dec_inst)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2) (instanceRef tdc_inst)) - (portRef (member tdc_out 2) (instanceRef dec_inst)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1) (instanceRef tdc_inst)) - (portRef (member tdc_out 1) (instanceRef dec_inst)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0) (instanceRef tdc_inst)) - (portRef (member tdc_out 0) (instanceRef dec_inst)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef tdc_inst)) - )) - (net hades_lvl1_c_i (joined - (portRef hades_lvl1_c_i) - (portRef hades_lvl1_c_i (instanceRef tdc_inst)) - )) - (net CN (joined - (portRef CN (instanceRef dec_inst)) - (portRef CN_2 (instanceRef tdc_inst)) - (portRef CN) - )) - (net CN_0 (joined - (portRef CN_1 (instanceRef tdc_inst)) - (portRef CN_0) - )) - (net CN_1 (joined - (portRef CN_0 (instanceRef tdc_inst)) - (portRef CN_1) - )) - (net CN_2 (joined - (portRef CN (instanceRef tdc_inst)) - (portRef CN_2) - )) - (net (rename offset_5_0 "offset_5[0]") (joined - (portRef (member offset_5 2) (instanceRef dec_inst)) - (portRef (member offset_5 2)) - )) - (net (rename offset_5_1 "offset_5[1]") (joined - (portRef (member offset_5 1) (instanceRef dec_inst)) - (portRef (member offset_5 1)) - )) - (net (rename offset_5_2 "offset_5[2]") (joined - (portRef (member offset_5 0) (instanceRef dec_inst)) - (portRef (member offset_5 0)) - )) - (net valid_fast_RNI999V (joined - (portRef valid_fast_RNI999V_1z (instanceRef dec_inst)) - (portRef valid_fast_RNI999V) - )) - (net N_1 (joined - (portRef CIN (instanceRef un1_window_8_cry_0_0)) - )) - ) - (property WINDOW_LENGTH (string "32'h000000ff")) - (property TDC_WIDTH (integer 3)) - (property COARSE_WIDTH (integer 9)) - (property orig_inst_of (string "hades_LVL1_raw_out")) - ) - ) - (cell EHXPLLL (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port CLKI (direction INPUT)) - (port CLKFB (direction INPUT)) - (port PHASESEL1 (direction INPUT)) - (port PHASESEL0 (direction INPUT)) - (port PHASEDIR (direction INPUT)) - (port PHASESTEP (direction INPUT)) - (port PHASELOADREG (direction INPUT)) - (port STDBY (direction INPUT)) - (port PLLWAKESYNC (direction INPUT)) - (port RST (direction INPUT)) - (port ENCLKOP (direction INPUT)) - (port ENCLKOS (direction INPUT)) - (port ENCLKOS2 (direction INPUT)) - (port ENCLKOS3 (direction INPUT)) - (port CLKOP (direction OUTPUT)) - (port CLKOS (direction OUTPUT)) - (port CLKOS2 (direction OUTPUT)) - (port CLKOS3 (direction OUTPUT)) - (port LOCK (direction OUTPUT)) - (port INTLOCK (direction OUTPUT)) - (port REFCLK (direction OUTPUT)) - (port CLKINTFB (direction OUTPUT)) - ) - (property INTFB_WAKE (string "DISABLED")) - (property PLLRST_ENA (string "DISABLED")) - (property DPHASE_SOURCE (string "DISABLED")) - (property INT_LOCK_STICKY (string "ENABLED")) - (property SYNC_ENABLE (string "DISABLED")) - (property REFIN_RESET (string "DISABLED")) - (property STDBY_ENABLE (string "DISABLED")) - (property PLL_LOCK_DELAY (integer 200)) - (property PLL_LOCK_MODE (integer 0)) - (property OUTDIVIDER_MUXD (string "DIVD")) - (property OUTDIVIDER_MUXC (string "DIVC")) - (property OUTDIVIDER_MUXB (string "DIVB")) - (property OUTDIVIDER_MUXA (string "DIVA")) - (property CLKOS_TRIM_DELAY (integer 0)) - (property CLKOS_TRIM_POL (string "FALLING")) - (property CLKOP_TRIM_DELAY (integer 0)) - (property CLKOP_TRIM_POL (string "FALLING")) - (property FEEDBK_PATH (string "CLKOP")) - (property CLKOS3_FPHASE (integer 6)) - (property CLKOS2_FPHASE (integer 4)) - (property CLKOS_FPHASE (integer 2)) - (property CLKOP_FPHASE (integer 0)) - (property CLKOS3_CPHASE (integer 1)) - (property CLKOS2_CPHASE (integer 1)) - (property CLKOS_CPHASE (integer 1)) - (property CLKOP_CPHASE (integer 1)) - (property CLKOS3_ENABLE (string "ENABLED")) - (property CLKOS2_ENABLE (string "ENABLED")) - (property CLKOS_ENABLE (string "ENABLED")) - (property CLKOP_ENABLE (string "ENABLED")) - (property CLKOS3_DIV (integer 2)) - (property CLKOS2_DIV (integer 2)) - (property CLKOS_DIV (integer 2)) - (property CLKOP_DIV (integer 2)) - (property CLKFB_DIV (integer 3)) - (property CLKI_DIV (integer 1)) - (property orig_inst_of (string "EHXPLLL")) - ) - ) - (cell tdc_channel_fifo_out_3 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port fifo_read_0 (direction INPUT)) - (port fifo_empty_0 (direction OUTPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port trig_c_i_0 (direction INPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port reset_dl_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_4)) - ) - (instance dec_inst (viewRef netlist (cellRef output_decoder8_2_1)) - ) - (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc_1)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net decoder_valid (joined - (portRef decoder_valid (instanceRef dec_inst)) - (portRef D (instanceRef fifo_wren)) - (portRef A (instanceRef fifo_in_data_11__fb)) - )) - (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined - (portRef Q (instanceRef fifo_in_data_11)) - (portRef fifo_in_data_0 (instanceRef fifo32dc_inst)) - (portRef B (instanceRef fifo_in_data_11__fb)) - )) - (net fb_0 (joined - (portRef Z (instanceRef fifo_in_data_11__fb)) - (portRef D (instanceRef fifo_in_data_11)) - )) - (net CN (joined - (portRef CN) - (portRef CN (instanceRef dec_inst)) - (portRef CN (instanceRef tdc_inst)) - (portRef CK (instanceRef fifo_in_data_11)) - (portRef CK (instanceRef fifo_wren)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef CD (instanceRef fifo_in_data_11)) - (portRef CD (instanceRef fifo_wren)) - )) - (net fifo_wren (joined - (portRef Q (instanceRef fifo_wren)) - (portRef fifo_wren (instanceRef fifo32dc_inst)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7) (instanceRef tdc_inst)) - (portRef (member tdc_out 7) (instanceRef dec_inst)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6) (instanceRef tdc_inst)) - (portRef (member tdc_out 6) (instanceRef dec_inst)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5) (instanceRef tdc_inst)) - (portRef (member tdc_out 5) (instanceRef dec_inst)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4) (instanceRef tdc_inst)) - (portRef (member tdc_out 4) (instanceRef dec_inst)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3) (instanceRef tdc_inst)) - (portRef (member tdc_out 3) (instanceRef dec_inst)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2) (instanceRef tdc_inst)) - (portRef (member tdc_out 2) (instanceRef dec_inst)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1) (instanceRef tdc_inst)) - (portRef (member tdc_out 1) (instanceRef dec_inst)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0) (instanceRef tdc_inst)) - (portRef (member tdc_out 0) (instanceRef dec_inst)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef pll_clks_0 (instanceRef fifo32dc_inst)) - (portRef (member pll_clks 0) (instanceRef tdc_inst)) - )) - (net (rename trig_c_i_0 "trig_c_i[2]") (joined - (portRef trig_c_i_0) - (portRef trig_c_i_0 (instanceRef tdc_inst)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CN_2 (instanceRef tdc_inst)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CN_1 (instanceRef tdc_inst)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CN_0 (instanceRef tdc_inst)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename fifo_empty_0 "fifo_empty[2]") (joined - (portRef fifo_empty_0 (instanceRef fifo32dc_inst)) - (portRef fifo_empty_0) - )) - (net (rename fifo_read_0 "fifo_read[2]") (joined - (portRef fifo_read_0) - (portRef fifo_read_0 (instanceRef fifo32dc_inst)) - )) - ) - (property orig_inst_of (string "tdc_channel_fifo_out")) - ) - ) - (cell tdc_channel_fifo_out_2 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port fifo_read_0 (direction INPUT)) - (port fifo_empty_0 (direction OUTPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port trig_c_i_0 (direction INPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port reset_dl_0 (direction INPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_3)) - ) - (instance dec_inst (viewRef netlist (cellRef output_decoder8_2_0)) - ) - (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc_0)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net decoder_valid (joined - (portRef decoder_valid (instanceRef dec_inst)) - (portRef D (instanceRef fifo_wren)) - (portRef A (instanceRef fifo_in_data_11__fb)) - )) - (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined - (portRef Q (instanceRef fifo_in_data_11)) - (portRef fifo_in_data_0 (instanceRef fifo32dc_inst)) - (portRef B (instanceRef fifo_in_data_11__fb)) - )) - (net fb_0 (joined - (portRef Z (instanceRef fifo_in_data_11__fb)) - (portRef D (instanceRef fifo_in_data_11)) - )) - (net CN (joined - (portRef CN) - (portRef CN (instanceRef dec_inst)) - (portRef CN (instanceRef tdc_inst)) - (portRef CK (instanceRef fifo_in_data_11)) - (portRef CK (instanceRef fifo_wren)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef CD (instanceRef fifo_in_data_11)) - (portRef CD (instanceRef fifo_wren)) - )) - (net fifo_wren (joined - (portRef Q (instanceRef fifo_wren)) - (portRef fifo_wren (instanceRef fifo32dc_inst)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7) (instanceRef tdc_inst)) - (portRef (member tdc_out 7) (instanceRef dec_inst)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6) (instanceRef tdc_inst)) - (portRef (member tdc_out 6) (instanceRef dec_inst)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5) (instanceRef tdc_inst)) - (portRef (member tdc_out 5) (instanceRef dec_inst)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4) (instanceRef tdc_inst)) - (portRef (member tdc_out 4) (instanceRef dec_inst)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3) (instanceRef tdc_inst)) - (portRef (member tdc_out 3) (instanceRef dec_inst)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2) (instanceRef tdc_inst)) - (portRef (member tdc_out 2) (instanceRef dec_inst)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1) (instanceRef tdc_inst)) - (portRef (member tdc_out 1) (instanceRef dec_inst)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0) (instanceRef tdc_inst)) - (portRef (member tdc_out 0) (instanceRef dec_inst)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef pll_clks_0 (instanceRef fifo32dc_inst)) - (portRef (member pll_clks 0) (instanceRef tdc_inst)) - )) - (net (rename trig_c_i_0 "trig_c_i[1]") (joined - (portRef trig_c_i_0) - (portRef trig_c_i_0 (instanceRef tdc_inst)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CN_2 (instanceRef tdc_inst)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CN_1 (instanceRef tdc_inst)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CN_0 (instanceRef tdc_inst)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename fifo_empty_0 "fifo_empty[1]") (joined - (portRef fifo_empty_0 (instanceRef fifo32dc_inst)) - (portRef fifo_empty_0) - )) - (net (rename fifo_read_0 "fifo_read[1]") (joined - (portRef fifo_read_0) - (portRef fifo_read_0 (instanceRef fifo32dc_inst)) - )) - ) - (property orig_inst_of (string "tdc_channel_fifo_out")) - ) - ) - (cell tdc_channel_fifo_out (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port fifo_read_0 (direction INPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction OUTPUT)) - (port trig_c_i_0 (direction INPUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port reset_dl_0 (direction INPUT)) - (port fifo_empty1_c (direction OUTPUT)) - (port CN_2 (direction INPUT)) - (port CN_1 (direction INPUT)) - (port CN_0 (direction INPUT)) - (port CN (direction INPUT)) - ) - (contents - (instance (rename fifo_in_data_11__fb "fifo_in_data_11_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance fifo_wren (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename fifo_in_data_11 "fifo_in_data[11]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance tdc_inst (viewRef netlist (cellRef tdc4ddr_short_2)) - ) - (instance dec_inst (viewRef netlist (cellRef output_decoder8_2)) - ) - (instance fifo32dc_inst (viewRef netlist (cellRef fifo32dc)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net decoder_valid (joined - (portRef decoder_valid (instanceRef dec_inst)) - (portRef D (instanceRef fifo_wren)) - (portRef A (instanceRef fifo_in_data_11__fb)) - )) - (net (rename fifo_in_data_9 "fifo_in_data[9]") (joined - (portRef Q (instanceRef fifo_in_data_11)) - (portRef fifo_in_data_0 (instanceRef fifo32dc_inst)) - (portRef B (instanceRef fifo_in_data_11__fb)) - )) - (net fb_0 (joined - (portRef Z (instanceRef fifo_in_data_11__fb)) - (portRef D (instanceRef fifo_in_data_11)) - )) - (net CN (joined - (portRef CN) - (portRef CN (instanceRef dec_inst)) - (portRef CN (instanceRef tdc_inst)) - (portRef CK (instanceRef fifo_in_data_11)) - (portRef CK (instanceRef fifo_wren)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef CD (instanceRef fifo_in_data_11)) - (portRef CD (instanceRef fifo_wren)) - )) - (net fifo_wren (joined - (portRef Q (instanceRef fifo_wren)) - (portRef fifo_wren (instanceRef fifo32dc_inst)) - )) - (net (rename tdc_out_0 "tdc_out[0]") (joined - (portRef (member tdc_out 7) (instanceRef tdc_inst)) - (portRef (member tdc_out 7) (instanceRef dec_inst)) - )) - (net (rename tdc_out_1 "tdc_out[1]") (joined - (portRef (member tdc_out 6) (instanceRef tdc_inst)) - (portRef (member tdc_out 6) (instanceRef dec_inst)) - )) - (net (rename tdc_out_2 "tdc_out[2]") (joined - (portRef (member tdc_out 5) (instanceRef tdc_inst)) - (portRef (member tdc_out 5) (instanceRef dec_inst)) - )) - (net (rename tdc_out_3 "tdc_out[3]") (joined - (portRef (member tdc_out 4) (instanceRef tdc_inst)) - (portRef (member tdc_out 4) (instanceRef dec_inst)) - )) - (net (rename tdc_out_4 "tdc_out[4]") (joined - (portRef (member tdc_out 3) (instanceRef tdc_inst)) - (portRef (member tdc_out 3) (instanceRef dec_inst)) - )) - (net (rename tdc_out_5 "tdc_out[5]") (joined - (portRef (member tdc_out 2) (instanceRef tdc_inst)) - (portRef (member tdc_out 2) (instanceRef dec_inst)) - )) - (net (rename tdc_out_6 "tdc_out[6]") (joined - (portRef (member tdc_out 1) (instanceRef tdc_inst)) - (portRef (member tdc_out 1) (instanceRef dec_inst)) - )) - (net (rename tdc_out_7 "tdc_out[7]") (joined - (portRef (member tdc_out 0) (instanceRef tdc_inst)) - (portRef (member tdc_out 0) (instanceRef dec_inst)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef tdc_inst)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef pll_clks_0 (instanceRef fifo32dc_inst)) - (portRef (member pll_clks 0) (instanceRef tdc_inst)) - )) - (net (rename trig_c_i_0 "trig_c_i[0]") (joined - (portRef trig_c_i_0) - (portRef trig_c_i_0 (instanceRef tdc_inst)) - )) - (net CN_0 (joined - (portRef CN_0) - (portRef CN_2 (instanceRef tdc_inst)) - )) - (net CN_1 (joined - (portRef CN_1) - (portRef CN_1 (instanceRef tdc_inst)) - )) - (net CN_2 (joined - (portRef CN_2) - (portRef CN_0 (instanceRef tdc_inst)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo32dc_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - )) - (net (rename fifo_read_0 "fifo_read[0]") (joined - (portRef fifo_read_0) - (portRef fifo_read_0 (instanceRef fifo32dc_inst)) - )) - (net fifo_empty1_c (joined - (portRef fifo_empty1_c (instanceRef fifo32dc_inst)) - (portRef fifo_empty1_c) - )) - ) - (property orig_inst_of (string "tdc_channel_fifo_out")) - ) - ) - (cell fifo_colector (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename fee_data_out_c "FEE_DATA_OUT_c[31:0]") 32) (direction OUTPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst_1 "un1_tdc_channel_fifo_out_inst_1[23:0]") 24) (direction INPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst_0 "un1_tdc_channel_fifo_out_inst_0[23:0]") 24) (direction INPUT)) - (port (array (rename un1_tdc_channel_fifo_out_inst "un1_tdc_channel_fifo_out_inst[23:0]") 24) (direction INPUT)) - (port (array (rename fifo_empty "fifo_empty[2:1]") 2) (direction INPUT)) - (port pll_clks_0 (direction INPUT)) - (port (array (rename fifo_read "fifo_read[2:0]") 3) (direction OUTPUT)) - (port fifo_rden_c (direction INPUT)) - (port last_buf_empty_c (direction OUTPUT)) - (port rd_clk_c (direction INPUT)) - (port fifo_empty1_c (direction INPUT)) - ) - (contents - (instance (rename in_read_enable_0__fb "in_read_enable_0_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A)+C A)")) - ) - (instance in_empty_pmux_0_RNIDRET (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+!A)+C (B !A))")) - ) - (instance (rename in_read_enable_2__fb "in_read_enable_2_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance (rename in_read_enable_1__fb "in_read_enable_1_.fb") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+A)")) - ) - (instance (rename iterator_0 "iterator[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename iterator_1 "iterator[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename in_read_enable_0 "in_read_enable[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename in_read_enable_1 "in_read_enable[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename in_read_enable_2 "in_read_enable[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_0 "data_buffer[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_1 "data_buffer[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_2 "data_buffer[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_3 "data_buffer[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_4 "data_buffer[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_5 "data_buffer[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_6 "data_buffer[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_7 "data_buffer[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_8 "data_buffer[8]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_9 "data_buffer[9]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_10 "data_buffer[10]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_11 "data_buffer[11]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_12 "data_buffer[12]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_13 "data_buffer[13]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_14 "data_buffer[14]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_15 "data_buffer[15]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_16 "data_buffer[16]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_17 "data_buffer[17]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_18 "data_buffer[18]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_19 "data_buffer[19]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_20 "data_buffer[20]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_21 "data_buffer[21]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_22 "data_buffer[22]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_23 "data_buffer[23]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_24 "data_buffer[24]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_25 "data_buffer[25]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_26 "data_buffer[26]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_27 "data_buffer[27]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_28 "data_buffer[28]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_29 "data_buffer[29]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_30 "data_buffer[30]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_31 "data_buffer[31]") (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_32 "data_buffer[32]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename data_buffer_33 "data_buffer[33]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance buffer_wr_enable (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance in_empty_pmux_u (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0 "data_buffer_3[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_1 "data_buffer_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_2 "data_buffer_3[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_3 "data_buffer_3[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_4 "data_buffer_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_5 "data_buffer_3[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_6 "data_buffer_3[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance (rename data_buffer_3_7 "data_buffer_3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A)+C (B+A))")) - ) - (instance in_empty_pmux_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_0 "data_buffer_3_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_1 "data_buffer_3_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_2 "data_buffer_3_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_3 "data_buffer_3_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_4 "data_buffer_3_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_5 "data_buffer_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_6 "data_buffer_3_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_8 "data_buffer_3_0[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_9 "data_buffer_3_0[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_10 "data_buffer_3_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_11 "data_buffer_3_0[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_12 "data_buffer_3_0[12]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_13 "data_buffer_3_0[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_14 "data_buffer_3_0[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_15 "data_buffer_3_0[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_16 "data_buffer_3_0[16]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_17 "data_buffer_3_0[17]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_18 "data_buffer_3_0[18]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_19 "data_buffer_3_0[19]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_20 "data_buffer_3_0[20]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_21 "data_buffer_3_0[21]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_22 "data_buffer_3_0[22]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_23 "data_buffer_3_0[23]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_24 "data_buffer_3_0[24]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_25 "data_buffer_3_0[25]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_26 "data_buffer_3_0[26]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_27 "data_buffer_3_0[27]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_28 "data_buffer_3_0[28]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_29 "data_buffer_3_0[29]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_30 "data_buffer_3_0[30]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_31 "data_buffer_3_0[31]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance (rename data_buffer_3_0_7 "data_buffer_3_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance un5_in_read_enable (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance (rename iterator_RNI7U5I_1 "iterator_RNI7U5I[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance fifo40_inst (viewRef netlist (cellRef fifo40_dc)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename fifo_read_0 "fifo_read[0]") (joined - (portRef Q (instanceRef in_read_enable_0)) - (portRef A (instanceRef in_read_enable_0__fb)) - (portRef (member fifo_read 2)) - )) - (net (rename iterator_1 "iterator[1]") (joined - (portRef Q (instanceRef iterator_1)) - (portRef A (instanceRef iterator_RNI7U5I_1)) - (portRef B (instanceRef un5_in_read_enable)) - (portRef B (instanceRef data_buffer_3_7)) - (portRef B (instanceRef data_buffer_3_6)) - (portRef B (instanceRef data_buffer_3_5)) - (portRef B (instanceRef data_buffer_3_4)) - (portRef B (instanceRef data_buffer_3_3)) - (portRef B (instanceRef data_buffer_3_2)) - (portRef B (instanceRef data_buffer_3_1)) - (portRef B (instanceRef data_buffer_3_0)) - (portRef B (instanceRef in_empty_pmux_u)) - (portRef D (instanceRef data_buffer_33)) - (portRef A (instanceRef in_read_enable_2__fb)) - (portRef B (instanceRef in_empty_pmux_0_RNIDRET)) - (portRef B (instanceRef in_read_enable_0__fb)) - )) - (net (rename iterator_0 "iterator[0]") (joined - (portRef Q (instanceRef iterator_0)) - (portRef A (instanceRef un5_in_read_enable)) - (portRef A (instanceRef data_buffer_3_0_7)) - (portRef A (instanceRef data_buffer_3_0_31)) - (portRef A (instanceRef data_buffer_3_0_30)) - (portRef A (instanceRef data_buffer_3_0_29)) - (portRef A (instanceRef data_buffer_3_0_28)) - (portRef A (instanceRef data_buffer_3_0_27)) - (portRef A (instanceRef data_buffer_3_0_26)) - (portRef A (instanceRef data_buffer_3_0_25)) - (portRef A (instanceRef data_buffer_3_0_24)) - (portRef A (instanceRef data_buffer_3_0_23)) - (portRef A (instanceRef data_buffer_3_0_22)) - (portRef A (instanceRef data_buffer_3_0_21)) - (portRef A (instanceRef data_buffer_3_0_20)) - (portRef A (instanceRef data_buffer_3_0_19)) - (portRef A (instanceRef data_buffer_3_0_18)) - (portRef A (instanceRef data_buffer_3_0_17)) - (portRef A (instanceRef data_buffer_3_0_16)) - (portRef A (instanceRef data_buffer_3_0_15)) - (portRef A (instanceRef data_buffer_3_0_14)) - (portRef A (instanceRef data_buffer_3_0_13)) - (portRef A (instanceRef data_buffer_3_0_12)) - (portRef A (instanceRef data_buffer_3_0_11)) - (portRef A (instanceRef data_buffer_3_0_10)) - (portRef A (instanceRef data_buffer_3_0_9)) - (portRef A (instanceRef data_buffer_3_0_8)) - (portRef A (instanceRef data_buffer_3_0_6)) - (portRef A (instanceRef data_buffer_3_0_5)) - (portRef A (instanceRef data_buffer_3_0_4)) - (portRef A (instanceRef data_buffer_3_0_3)) - (portRef A (instanceRef data_buffer_3_0_2)) - (portRef A (instanceRef data_buffer_3_0_1)) - (portRef A (instanceRef data_buffer_3_0_0)) - (portRef A (instanceRef in_empty_pmux_0)) - (portRef D (instanceRef data_buffer_32)) - (portRef D (instanceRef iterator_1)) - (portRef A (instanceRef in_read_enable_1__fb)) - (portRef C (instanceRef in_read_enable_0__fb)) - )) - (net fb_0 (joined - (portRef Z (instanceRef in_read_enable_0__fb)) - (portRef D (instanceRef in_read_enable_0)) - )) - (net (rename fifo_empty_2 "fifo_empty[2]") (joined - (portRef (member fifo_empty 0)) - (portRef B (instanceRef iterator_RNI7U5I_1)) - (portRef C (instanceRef in_empty_pmux_u)) - (portRef A (instanceRef in_empty_pmux_0_RNIDRET)) - )) - (net in_empty_pmux_0 (joined - (portRef Z (instanceRef in_empty_pmux_0)) - (portRef A (instanceRef in_empty_pmux_u)) - (portRef C (instanceRef in_empty_pmux_0_RNIDRET)) - )) - (net in_empty_pmux_i (joined - (portRef Z (instanceRef in_empty_pmux_0_RNIDRET)) - (portRef D (instanceRef buffer_wr_enable)) - (portRef SP (instanceRef data_buffer_33)) - (portRef SP (instanceRef data_buffer_32)) - (portRef SP (instanceRef data_buffer_31)) - (portRef SP (instanceRef data_buffer_30)) - (portRef SP (instanceRef data_buffer_29)) - (portRef SP (instanceRef data_buffer_28)) - (portRef SP (instanceRef data_buffer_27)) - (portRef SP (instanceRef data_buffer_26)) - (portRef SP (instanceRef data_buffer_25)) - (portRef SP (instanceRef data_buffer_24)) - (portRef SP (instanceRef data_buffer_23)) - (portRef SP (instanceRef data_buffer_22)) - (portRef SP (instanceRef data_buffer_21)) - (portRef SP (instanceRef data_buffer_20)) - (portRef SP (instanceRef data_buffer_19)) - (portRef SP (instanceRef data_buffer_18)) - (portRef SP (instanceRef data_buffer_17)) - (portRef SP (instanceRef data_buffer_16)) - (portRef SP (instanceRef data_buffer_15)) - (portRef SP (instanceRef data_buffer_14)) - (portRef SP (instanceRef data_buffer_13)) - (portRef SP (instanceRef data_buffer_12)) - (portRef SP (instanceRef data_buffer_11)) - (portRef SP (instanceRef data_buffer_10)) - (portRef SP (instanceRef data_buffer_9)) - (portRef SP (instanceRef data_buffer_8)) - (portRef SP (instanceRef data_buffer_7)) - (portRef SP (instanceRef data_buffer_6)) - (portRef SP (instanceRef data_buffer_5)) - (portRef SP (instanceRef data_buffer_4)) - (portRef SP (instanceRef data_buffer_3)) - (portRef SP (instanceRef data_buffer_2)) - (portRef SP (instanceRef data_buffer_1)) - (portRef SP (instanceRef data_buffer_0)) - )) - (net (rename fifo_read_2 "fifo_read[2]") (joined - (portRef Q (instanceRef in_read_enable_2)) - (portRef B (instanceRef in_read_enable_2__fb)) - (portRef (member fifo_read 0)) - )) - (net fb_0_0 (joined - (portRef Z (instanceRef in_read_enable_2__fb)) - (portRef D (instanceRef in_read_enable_2)) - )) - (net (rename fifo_read_1 "fifo_read[1]") (joined - (portRef Q (instanceRef in_read_enable_1)) - (portRef B (instanceRef in_read_enable_1__fb)) - (portRef (member fifo_read 1)) - )) - (net fb_0_1 (joined - (portRef Z (instanceRef in_read_enable_1__fb)) - (portRef D (instanceRef in_read_enable_1)) - )) - (net un5_in_read_enable (joined - (portRef Z (instanceRef un5_in_read_enable)) - (portRef D (instanceRef iterator_0)) - )) - (net (rename pll_clks_0 "pll_clks[3]") (joined - (portRef pll_clks_0) - (portRef pll_clks_0 (instanceRef fifo40_inst)) - (portRef CK (instanceRef buffer_wr_enable)) - (portRef CK (instanceRef data_buffer_33)) - (portRef CK (instanceRef data_buffer_32)) - (portRef CK (instanceRef data_buffer_31)) - (portRef CK (instanceRef data_buffer_30)) - (portRef CK (instanceRef data_buffer_29)) - (portRef CK (instanceRef data_buffer_28)) - (portRef CK (instanceRef data_buffer_27)) - (portRef CK (instanceRef data_buffer_26)) - (portRef CK (instanceRef data_buffer_25)) - (portRef CK (instanceRef data_buffer_24)) - (portRef CK (instanceRef data_buffer_23)) - (portRef CK (instanceRef data_buffer_22)) - (portRef CK (instanceRef data_buffer_21)) - (portRef CK (instanceRef data_buffer_20)) - (portRef CK (instanceRef data_buffer_19)) - (portRef CK (instanceRef data_buffer_18)) - (portRef CK (instanceRef data_buffer_17)) - (portRef CK (instanceRef data_buffer_16)) - (portRef CK (instanceRef data_buffer_15)) - (portRef CK (instanceRef data_buffer_14)) - (portRef CK (instanceRef data_buffer_13)) - (portRef CK (instanceRef data_buffer_12)) - (portRef CK (instanceRef data_buffer_11)) - (portRef CK (instanceRef data_buffer_10)) - (portRef CK (instanceRef data_buffer_9)) - (portRef CK (instanceRef data_buffer_8)) - (portRef CK (instanceRef data_buffer_7)) - (portRef CK (instanceRef data_buffer_6)) - (portRef CK (instanceRef data_buffer_5)) - (portRef CK (instanceRef data_buffer_4)) - (portRef CK (instanceRef data_buffer_3)) - (portRef CK (instanceRef data_buffer_2)) - (portRef CK (instanceRef data_buffer_1)) - (portRef CK (instanceRef data_buffer_0)) - (portRef CK (instanceRef in_read_enable_2)) - (portRef CK (instanceRef in_read_enable_1)) - (portRef CK (instanceRef in_read_enable_0)) - (portRef CK (instanceRef iterator_1)) - (portRef CK (instanceRef iterator_0)) - )) - (net in_empty_pmux (joined - (portRef Z (instanceRef in_empty_pmux_u)) - (portRef CD (instanceRef in_read_enable_2)) - (portRef CD (instanceRef in_read_enable_1)) - (portRef CD (instanceRef in_read_enable_0)) - )) - (net (rename data_buffer_3_0 "data_buffer_3[0]") (joined - (portRef Z (instanceRef data_buffer_3_0)) - (portRef D (instanceRef data_buffer_0)) - )) - (net (rename data_buffer_0 "data_buffer[0]") (joined - (portRef Q (instanceRef data_buffer_0)) - (portRef (member data_buffer 33) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_1 "data_buffer_3[1]") (joined - (portRef Z (instanceRef data_buffer_3_1)) - (portRef D (instanceRef data_buffer_1)) - )) - (net (rename data_buffer_1 "data_buffer[1]") (joined - (portRef Q (instanceRef data_buffer_1)) - (portRef (member data_buffer 32) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_2 "data_buffer_3[2]") (joined - (portRef Z (instanceRef data_buffer_3_2)) - (portRef D (instanceRef data_buffer_2)) - )) - (net (rename data_buffer_2 "data_buffer[2]") (joined - (portRef Q (instanceRef data_buffer_2)) - (portRef (member data_buffer 31) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_3 "data_buffer_3[3]") (joined - (portRef Z (instanceRef data_buffer_3_3)) - (portRef D (instanceRef data_buffer_3)) - )) - (net (rename data_buffer_3 "data_buffer[3]") (joined - (portRef Q (instanceRef data_buffer_3)) - (portRef (member data_buffer 30) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_4 "data_buffer_3[4]") (joined - (portRef Z (instanceRef data_buffer_3_4)) - (portRef D (instanceRef data_buffer_4)) - )) - (net (rename data_buffer_4 "data_buffer[4]") (joined - (portRef Q (instanceRef data_buffer_4)) - (portRef (member data_buffer 29) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_5 "data_buffer_3[5]") (joined - (portRef Z (instanceRef data_buffer_3_5)) - (portRef D (instanceRef data_buffer_5)) - )) - (net (rename data_buffer_5 "data_buffer[5]") (joined - (portRef Q (instanceRef data_buffer_5)) - (portRef (member data_buffer 28) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_6 "data_buffer_3[6]") (joined - (portRef Z (instanceRef data_buffer_3_6)) - (portRef D (instanceRef data_buffer_6)) - )) - (net (rename data_buffer_6 "data_buffer[6]") (joined - (portRef Q (instanceRef data_buffer_6)) - (portRef (member data_buffer 27) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_7 "data_buffer_3[7]") (joined - (portRef Z (instanceRef data_buffer_3_7)) - (portRef D (instanceRef data_buffer_7)) - )) - (net (rename data_buffer_7 "data_buffer[7]") (joined - (portRef Q (instanceRef data_buffer_7)) - (portRef (member data_buffer 26) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_8 "data_buffer_3[8]") (joined - (portRef Z (instanceRef data_buffer_3_0_8)) - (portRef D (instanceRef data_buffer_8)) - )) - (net (rename iterator_RNI7U5I_1 "iterator_RNI7U5I[1]") (joined - (portRef Z (instanceRef iterator_RNI7U5I_1)) - (portRef CD (instanceRef data_buffer_31)) - (portRef CD (instanceRef data_buffer_30)) - (portRef CD (instanceRef data_buffer_29)) - (portRef CD (instanceRef data_buffer_28)) - (portRef CD (instanceRef data_buffer_27)) - (portRef CD (instanceRef data_buffer_26)) - (portRef CD (instanceRef data_buffer_25)) - (portRef CD (instanceRef data_buffer_24)) - (portRef CD (instanceRef data_buffer_23)) - (portRef CD (instanceRef data_buffer_22)) - (portRef CD (instanceRef data_buffer_21)) - (portRef CD (instanceRef data_buffer_20)) - (portRef CD (instanceRef data_buffer_19)) - (portRef CD (instanceRef data_buffer_18)) - (portRef CD (instanceRef data_buffer_17)) - (portRef CD (instanceRef data_buffer_16)) - (portRef CD (instanceRef data_buffer_15)) - (portRef CD (instanceRef data_buffer_14)) - (portRef CD (instanceRef data_buffer_13)) - (portRef CD (instanceRef data_buffer_12)) - (portRef CD (instanceRef data_buffer_11)) - (portRef CD (instanceRef data_buffer_10)) - (portRef CD (instanceRef data_buffer_9)) - (portRef CD (instanceRef data_buffer_8)) - )) - (net (rename data_buffer_8 "data_buffer[8]") (joined - (portRef Q (instanceRef data_buffer_8)) - (portRef (member data_buffer 25) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_9 "data_buffer_3[9]") (joined - (portRef Z (instanceRef data_buffer_3_0_9)) - (portRef D (instanceRef data_buffer_9)) - )) - (net (rename data_buffer_9 "data_buffer[9]") (joined - (portRef Q (instanceRef data_buffer_9)) - (portRef (member data_buffer 24) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_10 "data_buffer_3[10]") (joined - (portRef Z (instanceRef data_buffer_3_0_10)) - (portRef D (instanceRef data_buffer_10)) - )) - (net (rename data_buffer_10 "data_buffer[10]") (joined - (portRef Q (instanceRef data_buffer_10)) - (portRef (member data_buffer 23) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_11 "data_buffer_3[11]") (joined - (portRef Z (instanceRef data_buffer_3_0_11)) - (portRef D (instanceRef data_buffer_11)) - )) - (net (rename data_buffer_11 "data_buffer[11]") (joined - (portRef Q (instanceRef data_buffer_11)) - (portRef (member data_buffer 22) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_12 "data_buffer_3[12]") (joined - (portRef Z (instanceRef data_buffer_3_0_12)) - (portRef D (instanceRef data_buffer_12)) - )) - (net (rename data_buffer_12 "data_buffer[12]") (joined - (portRef Q (instanceRef data_buffer_12)) - (portRef (member data_buffer 21) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_13 "data_buffer_3[13]") (joined - (portRef Z (instanceRef data_buffer_3_0_13)) - (portRef D (instanceRef data_buffer_13)) - )) - (net (rename data_buffer_13 "data_buffer[13]") (joined - (portRef Q (instanceRef data_buffer_13)) - (portRef (member data_buffer 20) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_14 "data_buffer_3[14]") (joined - (portRef Z (instanceRef data_buffer_3_0_14)) - (portRef D (instanceRef data_buffer_14)) - )) - (net (rename data_buffer_14 "data_buffer[14]") (joined - (portRef Q (instanceRef data_buffer_14)) - (portRef (member data_buffer 19) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_15 "data_buffer_3[15]") (joined - (portRef Z (instanceRef data_buffer_3_0_15)) - (portRef D (instanceRef data_buffer_15)) - )) - (net (rename data_buffer_15 "data_buffer[15]") (joined - (portRef Q (instanceRef data_buffer_15)) - (portRef (member data_buffer 18) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_16 "data_buffer_3[16]") (joined - (portRef Z (instanceRef data_buffer_3_0_16)) - (portRef D (instanceRef data_buffer_16)) - )) - (net (rename data_buffer_16 "data_buffer[16]") (joined - (portRef Q (instanceRef data_buffer_16)) - (portRef (member data_buffer 17) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_17 "data_buffer_3[17]") (joined - (portRef Z (instanceRef data_buffer_3_0_17)) - (portRef D (instanceRef data_buffer_17)) - )) - (net (rename data_buffer_17 "data_buffer[17]") (joined - (portRef Q (instanceRef data_buffer_17)) - (portRef (member data_buffer 16) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_18 "data_buffer_3[18]") (joined - (portRef Z (instanceRef data_buffer_3_0_18)) - (portRef D (instanceRef data_buffer_18)) - )) - (net (rename data_buffer_18 "data_buffer[18]") (joined - (portRef Q (instanceRef data_buffer_18)) - (portRef (member data_buffer 15) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_19 "data_buffer_3[19]") (joined - (portRef Z (instanceRef data_buffer_3_0_19)) - (portRef D (instanceRef data_buffer_19)) - )) - (net (rename data_buffer_19 "data_buffer[19]") (joined - (portRef Q (instanceRef data_buffer_19)) - (portRef (member data_buffer 14) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_20 "data_buffer_3[20]") (joined - (portRef Z (instanceRef data_buffer_3_0_20)) - (portRef D (instanceRef data_buffer_20)) - )) - (net (rename data_buffer_20 "data_buffer[20]") (joined - (portRef Q (instanceRef data_buffer_20)) - (portRef (member data_buffer 13) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_21 "data_buffer_3[21]") (joined - (portRef Z (instanceRef data_buffer_3_0_21)) - (portRef D (instanceRef data_buffer_21)) - )) - (net (rename data_buffer_21 "data_buffer[21]") (joined - (portRef Q (instanceRef data_buffer_21)) - (portRef (member data_buffer 12) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_22 "data_buffer_3[22]") (joined - (portRef Z (instanceRef data_buffer_3_0_22)) - (portRef D (instanceRef data_buffer_22)) - )) - (net (rename data_buffer_22 "data_buffer[22]") (joined - (portRef Q (instanceRef data_buffer_22)) - (portRef (member data_buffer 11) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_23 "data_buffer_3[23]") (joined - (portRef Z (instanceRef data_buffer_3_0_23)) - (portRef D (instanceRef data_buffer_23)) - )) - (net (rename data_buffer_23 "data_buffer[23]") (joined - (portRef Q (instanceRef data_buffer_23)) - (portRef (member data_buffer 10) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_24 "data_buffer_3[24]") (joined - (portRef Z (instanceRef data_buffer_3_0_24)) - (portRef D (instanceRef data_buffer_24)) - )) - (net (rename data_buffer_24 "data_buffer[24]") (joined - (portRef Q (instanceRef data_buffer_24)) - (portRef (member data_buffer 9) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_25 "data_buffer_3[25]") (joined - (portRef Z (instanceRef data_buffer_3_0_25)) - (portRef D (instanceRef data_buffer_25)) - )) - (net (rename data_buffer_25 "data_buffer[25]") (joined - (portRef Q (instanceRef data_buffer_25)) - (portRef (member data_buffer 8) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_26 "data_buffer_3[26]") (joined - (portRef Z (instanceRef data_buffer_3_0_26)) - (portRef D (instanceRef data_buffer_26)) - )) - (net (rename data_buffer_26 "data_buffer[26]") (joined - (portRef Q (instanceRef data_buffer_26)) - (portRef (member data_buffer 7) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_27 "data_buffer_3[27]") (joined - (portRef Z (instanceRef data_buffer_3_0_27)) - (portRef D (instanceRef data_buffer_27)) - )) - (net (rename data_buffer_27 "data_buffer[27]") (joined - (portRef Q (instanceRef data_buffer_27)) - (portRef (member data_buffer 6) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_28 "data_buffer_3[28]") (joined - (portRef Z (instanceRef data_buffer_3_0_28)) - (portRef D (instanceRef data_buffer_28)) - )) - (net (rename data_buffer_28 "data_buffer[28]") (joined - (portRef Q (instanceRef data_buffer_28)) - (portRef (member data_buffer 5) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_29 "data_buffer_3[29]") (joined - (portRef Z (instanceRef data_buffer_3_0_29)) - (portRef D (instanceRef data_buffer_29)) - )) - (net (rename data_buffer_29 "data_buffer[29]") (joined - (portRef Q (instanceRef data_buffer_29)) - (portRef (member data_buffer 4) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_30 "data_buffer_3[30]") (joined - (portRef Z (instanceRef data_buffer_3_0_30)) - (portRef D (instanceRef data_buffer_30)) - )) - (net (rename data_buffer_30 "data_buffer[30]") (joined - (portRef Q (instanceRef data_buffer_30)) - (portRef (member data_buffer 3) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_31 "data_buffer_3[31]") (joined - (portRef Z (instanceRef data_buffer_3_0_31)) - (portRef D (instanceRef data_buffer_31)) - )) - (net (rename data_buffer_31 "data_buffer[31]") (joined - (portRef Q (instanceRef data_buffer_31)) - (portRef (member data_buffer 2) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_32 "data_buffer[32]") (joined - (portRef Q (instanceRef data_buffer_32)) - (portRef (member data_buffer 1) (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_33 "data_buffer[33]") (joined - (portRef Q (instanceRef data_buffer_33)) - (portRef (member data_buffer 0) (instanceRef fifo40_inst)) - )) - (net buffer_wr_enable (joined - (portRef Q (instanceRef buffer_wr_enable)) - (portRef buffer_wr_enable (instanceRef fifo40_inst)) - )) - (net (rename data_buffer_3_0_0 "data_buffer_3_0[0]") (joined - (portRef Z (instanceRef data_buffer_3_0_0)) - (portRef A (instanceRef data_buffer_3_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_16 "un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7)) - (portRef C (instanceRef data_buffer_3_0)) - )) - (net (rename data_buffer_3_0_1 "data_buffer_3_0[1]") (joined - (portRef Z (instanceRef data_buffer_3_0_1)) - (portRef A (instanceRef data_buffer_3_1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_17 "un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6)) - (portRef C (instanceRef data_buffer_3_1)) - )) - (net (rename data_buffer_3_0_2 "data_buffer_3_0[2]") (joined - (portRef Z (instanceRef data_buffer_3_0_2)) - (portRef A (instanceRef data_buffer_3_2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_18 "un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5)) - (portRef C (instanceRef data_buffer_3_2)) - )) - (net (rename data_buffer_3_0_3 "data_buffer_3_0[3]") (joined - (portRef Z (instanceRef data_buffer_3_0_3)) - (portRef A (instanceRef data_buffer_3_3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_19 "un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4)) - (portRef C (instanceRef data_buffer_3_3)) - )) - (net (rename data_buffer_3_0_4 "data_buffer_3_0[4]") (joined - (portRef Z (instanceRef data_buffer_3_0_4)) - (portRef A (instanceRef data_buffer_3_4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_20 "un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3)) - (portRef C (instanceRef data_buffer_3_4)) - )) - (net (rename data_buffer_3_0_5 "data_buffer_3_0[5]") (joined - (portRef Z (instanceRef data_buffer_3_0_5)) - (portRef A (instanceRef data_buffer_3_5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_21 "un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2)) - (portRef C (instanceRef data_buffer_3_5)) - )) - (net (rename data_buffer_3_0_6 "data_buffer_3_0[6]") (joined - (portRef Z (instanceRef data_buffer_3_0_6)) - (portRef A (instanceRef data_buffer_3_6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_22 "un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1)) - (portRef C (instanceRef data_buffer_3_6)) - )) - (net N_210 (joined - (portRef Z (instanceRef data_buffer_3_0_7)) - (portRef A (instanceRef data_buffer_3_7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_23 "un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0)) - (portRef C (instanceRef data_buffer_3_7)) - )) - (net fifo_empty1_c (joined - (portRef fifo_empty1_c) - (portRef B (instanceRef in_empty_pmux_0)) - )) - (net (rename fifo_empty_1 "fifo_empty[1]") (joined - (portRef (member fifo_empty 1)) - (portRef C (instanceRef in_empty_pmux_0)) - )) - (net (rename un1_tdc_channel_fifo_out_instZ0Z_0 "un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23)) - (portRef B (instanceRef data_buffer_3_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_8 "un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15)) - (portRef C (instanceRef data_buffer_3_0_0)) - )) - (net (rename un1_tdc_channel_fifo_out_instZ0Z_1 "un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22)) - (portRef B (instanceRef data_buffer_3_0_1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_9 "un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14)) - (portRef C (instanceRef data_buffer_3_0_1)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_2 "un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21)) - (portRef B (instanceRef data_buffer_3_0_2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_10 "un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13)) - (portRef C (instanceRef data_buffer_3_0_2)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_3 "un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20)) - (portRef B (instanceRef data_buffer_3_0_3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_11 "un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12)) - (portRef C (instanceRef data_buffer_3_0_3)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_4 "un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19)) - (portRef B (instanceRef data_buffer_3_0_4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_12 "un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11)) - (portRef C (instanceRef data_buffer_3_0_4)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_5 "un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18)) - (portRef B (instanceRef data_buffer_3_0_5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_13 "un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10)) - (portRef C (instanceRef data_buffer_3_0_5)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_6 "un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17)) - (portRef B (instanceRef data_buffer_3_0_6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_14 "un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9)) - (portRef C (instanceRef data_buffer_3_0_6)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_8 "un1_tdc_channel_fifo_out_inst_0[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 15)) - (portRef B (instanceRef data_buffer_3_0_8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_16 "un1_tdc_channel_fifo_out_inst_0[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 7)) - (portRef C (instanceRef data_buffer_3_0_8)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_9 "un1_tdc_channel_fifo_out_inst_0[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 14)) - (portRef B (instanceRef data_buffer_3_0_9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_17 "un1_tdc_channel_fifo_out_inst_0[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 6)) - (portRef C (instanceRef data_buffer_3_0_9)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_10 "un1_tdc_channel_fifo_out_inst_0[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 13)) - (portRef B (instanceRef data_buffer_3_0_10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_18 "un1_tdc_channel_fifo_out_inst_0[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 5)) - (portRef C (instanceRef data_buffer_3_0_10)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_11 "un1_tdc_channel_fifo_out_inst_0[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 12)) - (portRef B (instanceRef data_buffer_3_0_11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_19 "un1_tdc_channel_fifo_out_inst_0[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 4)) - (portRef C (instanceRef data_buffer_3_0_11)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_12 "un1_tdc_channel_fifo_out_inst_0[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 11)) - (portRef B (instanceRef data_buffer_3_0_12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_20 "un1_tdc_channel_fifo_out_inst_0[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 3)) - (portRef C (instanceRef data_buffer_3_0_12)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_13 "un1_tdc_channel_fifo_out_inst_0[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 10)) - (portRef B (instanceRef data_buffer_3_0_13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_21 "un1_tdc_channel_fifo_out_inst_0[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 2)) - (portRef C (instanceRef data_buffer_3_0_13)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_14 "un1_tdc_channel_fifo_out_inst_0[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 9)) - (portRef B (instanceRef data_buffer_3_0_14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_22 "un1_tdc_channel_fifo_out_inst_0[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 1)) - (portRef C (instanceRef data_buffer_3_0_14)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_15 "un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8)) - (portRef B (instanceRef data_buffer_3_0_15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_23 "un1_tdc_channel_fifo_out_inst_0[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 0)) - (portRef C (instanceRef data_buffer_3_0_15)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_16 "un1_tdc_channel_fifo_out_inst_1[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 7)) - (portRef B (instanceRef data_buffer_3_0_16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_0 "un1_tdc_channel_fifo_out_inst_0[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 23)) - (portRef C (instanceRef data_buffer_3_0_16)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_17 "un1_tdc_channel_fifo_out_inst_1[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 6)) - (portRef B (instanceRef data_buffer_3_0_17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_1 "un1_tdc_channel_fifo_out_inst_0[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 22)) - (portRef C (instanceRef data_buffer_3_0_17)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_18 "un1_tdc_channel_fifo_out_inst_1[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 5)) - (portRef B (instanceRef data_buffer_3_0_18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_2 "un1_tdc_channel_fifo_out_inst_0[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 21)) - (portRef C (instanceRef data_buffer_3_0_18)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_19 "un1_tdc_channel_fifo_out_inst_1[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 4)) - (portRef B (instanceRef data_buffer_3_0_19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_3 "un1_tdc_channel_fifo_out_inst_0[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 20)) - (portRef C (instanceRef data_buffer_3_0_19)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_20 "un1_tdc_channel_fifo_out_inst_1[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 3)) - (portRef B (instanceRef data_buffer_3_0_20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_4 "un1_tdc_channel_fifo_out_inst_0[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 19)) - (portRef C (instanceRef data_buffer_3_0_20)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_21 "un1_tdc_channel_fifo_out_inst_1[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 2)) - (portRef B (instanceRef data_buffer_3_0_21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_5 "un1_tdc_channel_fifo_out_inst_0[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 18)) - (portRef C (instanceRef data_buffer_3_0_21)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_22 "un1_tdc_channel_fifo_out_inst_1[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 1)) - (portRef B (instanceRef data_buffer_3_0_22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_6 "un1_tdc_channel_fifo_out_inst_0[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 17)) - (portRef C (instanceRef data_buffer_3_0_22)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_23 "un1_tdc_channel_fifo_out_inst_1[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 0)) - (portRef B (instanceRef data_buffer_3_0_23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_7 "un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16)) - (portRef C (instanceRef data_buffer_3_0_23)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_0 "un1_tdc_channel_fifo_out_inst_1[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 23)) - (portRef B (instanceRef data_buffer_3_0_24)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_8 "un1_tdc_channel_fifo_out_inst_1[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 15)) - (portRef C (instanceRef data_buffer_3_0_24)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_1 "un1_tdc_channel_fifo_out_inst_1[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 22)) - (portRef B (instanceRef data_buffer_3_0_25)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_9 "un1_tdc_channel_fifo_out_inst_1[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 14)) - (portRef C (instanceRef data_buffer_3_0_25)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_2 "un1_tdc_channel_fifo_out_inst_1[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 21)) - (portRef B (instanceRef data_buffer_3_0_26)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_10 "un1_tdc_channel_fifo_out_inst_1[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 13)) - (portRef C (instanceRef data_buffer_3_0_26)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_3 "un1_tdc_channel_fifo_out_inst_1[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 20)) - (portRef B (instanceRef data_buffer_3_0_27)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_11 "un1_tdc_channel_fifo_out_inst_1[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 12)) - (portRef C (instanceRef data_buffer_3_0_27)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_4 "un1_tdc_channel_fifo_out_inst_1[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 19)) - (portRef B (instanceRef data_buffer_3_0_28)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_12 "un1_tdc_channel_fifo_out_inst_1[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 11)) - (portRef C (instanceRef data_buffer_3_0_28)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_5 "un1_tdc_channel_fifo_out_inst_1[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 18)) - (portRef B (instanceRef data_buffer_3_0_29)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_13 "un1_tdc_channel_fifo_out_inst_1[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 10)) - (portRef C (instanceRef data_buffer_3_0_29)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_6 "un1_tdc_channel_fifo_out_inst_1[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 17)) - (portRef B (instanceRef data_buffer_3_0_30)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_14 "un1_tdc_channel_fifo_out_inst_1[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 9)) - (portRef C (instanceRef data_buffer_3_0_30)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_7 "un1_tdc_channel_fifo_out_inst_0[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 16)) - (portRef B (instanceRef data_buffer_3_0_31)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_0_15 "un1_tdc_channel_fifo_out_inst_0[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_0 8)) - (portRef C (instanceRef data_buffer_3_0_31)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_7 "un1_tdc_channel_fifo_out_inst_1[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 16)) - (portRef B (instanceRef data_buffer_3_0_7)) - )) - (net (rename un1_tdc_channel_fifo_out_inst_1_15 "un1_tdc_channel_fifo_out_inst_1[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst_1 8)) - (portRef C (instanceRef data_buffer_3_0_7)) - )) - (net (rename FEE_DATA_OUT_c_0 "FEE_DATA_OUT_c[0]") (joined - (portRef (member fee_data_out_c 31) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 31)) - )) - (net (rename FEE_DATA_OUT_c_1 "FEE_DATA_OUT_c[1]") (joined - (portRef (member fee_data_out_c 30) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 30)) - )) - (net (rename FEE_DATA_OUT_c_2 "FEE_DATA_OUT_c[2]") (joined - (portRef (member fee_data_out_c 29) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 29)) - )) - (net (rename FEE_DATA_OUT_c_3 "FEE_DATA_OUT_c[3]") (joined - (portRef (member fee_data_out_c 28) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 28)) - )) - (net (rename FEE_DATA_OUT_c_4 "FEE_DATA_OUT_c[4]") (joined - (portRef (member fee_data_out_c 27) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 27)) - )) - (net (rename FEE_DATA_OUT_c_5 "FEE_DATA_OUT_c[5]") (joined - (portRef (member fee_data_out_c 26) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 26)) - )) - (net (rename FEE_DATA_OUT_c_6 "FEE_DATA_OUT_c[6]") (joined - (portRef (member fee_data_out_c 25) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 25)) - )) - (net (rename FEE_DATA_OUT_c_7 "FEE_DATA_OUT_c[7]") (joined - (portRef (member fee_data_out_c 24) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 24)) - )) - (net (rename FEE_DATA_OUT_c_8 "FEE_DATA_OUT_c[8]") (joined - (portRef (member fee_data_out_c 23) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 23)) - )) - (net (rename FEE_DATA_OUT_c_9 "FEE_DATA_OUT_c[9]") (joined - (portRef (member fee_data_out_c 22) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 22)) - )) - (net (rename FEE_DATA_OUT_c_10 "FEE_DATA_OUT_c[10]") (joined - (portRef (member fee_data_out_c 21) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 21)) - )) - (net (rename FEE_DATA_OUT_c_11 "FEE_DATA_OUT_c[11]") (joined - (portRef (member fee_data_out_c 20) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 20)) - )) - (net (rename FEE_DATA_OUT_c_12 "FEE_DATA_OUT_c[12]") (joined - (portRef (member fee_data_out_c 19) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 19)) - )) - (net (rename FEE_DATA_OUT_c_13 "FEE_DATA_OUT_c[13]") (joined - (portRef (member fee_data_out_c 18) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 18)) - )) - (net (rename FEE_DATA_OUT_c_14 "FEE_DATA_OUT_c[14]") (joined - (portRef (member fee_data_out_c 17) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 17)) - )) - (net (rename FEE_DATA_OUT_c_15 "FEE_DATA_OUT_c[15]") (joined - (portRef (member fee_data_out_c 16) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 16)) - )) - (net (rename FEE_DATA_OUT_c_16 "FEE_DATA_OUT_c[16]") (joined - (portRef (member fee_data_out_c 15) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 15)) - )) - (net (rename FEE_DATA_OUT_c_17 "FEE_DATA_OUT_c[17]") (joined - (portRef (member fee_data_out_c 14) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 14)) - )) - (net (rename FEE_DATA_OUT_c_18 "FEE_DATA_OUT_c[18]") (joined - (portRef (member fee_data_out_c 13) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 13)) - )) - (net (rename FEE_DATA_OUT_c_19 "FEE_DATA_OUT_c[19]") (joined - (portRef (member fee_data_out_c 12) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 12)) - )) - (net (rename FEE_DATA_OUT_c_20 "FEE_DATA_OUT_c[20]") (joined - (portRef (member fee_data_out_c 11) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 11)) - )) - (net (rename FEE_DATA_OUT_c_21 "FEE_DATA_OUT_c[21]") (joined - (portRef (member fee_data_out_c 10) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 10)) - )) - (net (rename FEE_DATA_OUT_c_22 "FEE_DATA_OUT_c[22]") (joined - (portRef (member fee_data_out_c 9) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 9)) - )) - (net (rename FEE_DATA_OUT_c_23 "FEE_DATA_OUT_c[23]") (joined - (portRef (member fee_data_out_c 8) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 8)) - )) - (net (rename FEE_DATA_OUT_c_24 "FEE_DATA_OUT_c[24]") (joined - (portRef (member fee_data_out_c 7) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 7)) - )) - (net (rename FEE_DATA_OUT_c_25 "FEE_DATA_OUT_c[25]") (joined - (portRef (member fee_data_out_c 6) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 6)) - )) - (net (rename FEE_DATA_OUT_c_26 "FEE_DATA_OUT_c[26]") (joined - (portRef (member fee_data_out_c 5) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 5)) - )) - (net (rename FEE_DATA_OUT_c_27 "FEE_DATA_OUT_c[27]") (joined - (portRef (member fee_data_out_c 4) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 4)) - )) - (net (rename FEE_DATA_OUT_c_28 "FEE_DATA_OUT_c[28]") (joined - (portRef (member fee_data_out_c 3) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 3)) - )) - (net (rename FEE_DATA_OUT_c_29 "FEE_DATA_OUT_c[29]") (joined - (portRef (member fee_data_out_c 2) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 2)) - )) - (net (rename FEE_DATA_OUT_c_30 "FEE_DATA_OUT_c[30]") (joined - (portRef (member fee_data_out_c 1) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 1)) - )) - (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined - (portRef (member fee_data_out_c 0) (instanceRef fifo40_inst)) - (portRef (member fee_data_out_c 0)) - )) - (net rd_clk_c (joined - (portRef rd_clk_c) - (portRef rd_clk_c (instanceRef fifo40_inst)) - )) - (net last_buf_empty_c (joined - (portRef last_buf_empty_c (instanceRef fifo40_inst)) - (portRef last_buf_empty_c) - )) - (net fifo_rden_c (joined - (portRef fifo_rden_c) - (portRef fifo_rden_c (instanceRef fifo40_inst)) - )) - ) - (property ADDRESS_WIDTH (integer 8)) - (property DATA_WIDTH (integer 32)) - (property CHANNELS (integer 3)) - (property orig_inst_of (string "fifo_colector")) - ) - ) - (cell trb_adapter (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port LVL1_INVALID_TRG_IN_dl_0 (direction INPUT)) - (port LVL1_TRG_DATA_VALID_IN_dl_0 (direction INPUT)) - (port release_out_c (direction OUTPUT)) - (port LVL1_TRG_DATA_VALI_IN_rising_c (direction OUTPUT)) - (port last_buf_empty_c (direction INPUT)) - (port burst_c (direction OUTPUT)) - (port discard_c (direction OUTPUT)) - (port fifo_rden_c (direction OUTPUT)) - (port rd_clk_c (direction INPUT)) - (port finished_c (direction OUTPUT)) - ) - (contents - (instance finished_prev (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance finished (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance buf_rden_prev (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance buf_rden (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename LVL1_TRG_DATA_VALID_IN_dl_1 "LVL1_TRG_DATA_VALID_IN_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename LVL1_TRG_DATA_VALID_IN_dl_2 "LVL1_TRG_DATA_VALID_IN_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename LVL1_INVALID_TRG_IN_dl_1 "LVL1_INVALID_TRG_IN_dl[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance buf_rden4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A)+C A)")) - ) - (instance LVL1_TRG_DATA_VALI_IN_rising (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance release_out (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B !A)")) - ) - (instance burst (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B !A))")) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net finished_c (joined - (portRef Q (instanceRef finished)) - (portRef A (instanceRef release_out)) - (portRef D (instanceRef finished_prev)) - (portRef finished_c) - )) - (net rd_clk_c (joined - (portRef rd_clk_c) - (portRef CK (instanceRef LVL1_INVALID_TRG_IN_dl_1)) - (portRef CK (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2)) - (portRef CK (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1)) - (portRef CK (instanceRef buf_rden)) - (portRef CK (instanceRef buf_rden_prev)) - (portRef CK (instanceRef finished)) - (portRef CK (instanceRef finished_prev)) - )) - (net finished_prev (joined - (portRef Q (instanceRef finished_prev)) - (portRef B (instanceRef release_out)) - )) - (net buf_rden_prev (joined - (portRef Q (instanceRef buf_rden_prev)) - (portRef D (instanceRef finished)) - )) - (net fifo_rden_c (joined - (portRef Q (instanceRef buf_rden)) - (portRef B (instanceRef buf_rden4)) - (portRef D (instanceRef buf_rden_prev)) - (portRef CD (instanceRef finished)) - (portRef fifo_rden_c) - )) - (net buf_rden4 (joined - (portRef Z (instanceRef buf_rden4)) - (portRef D (instanceRef buf_rden)) - )) - (net (rename LVL1_TRG_DATA_VALID_IN_dl_0 "LVL1_TRG_DATA_VALID_IN_dl[0]") (joined - (portRef LVL1_TRG_DATA_VALID_IN_dl_0) - (portRef D (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1)) - )) - (net (rename LVL1_TRG_DATA_VALID_IN_dl_1 "LVL1_TRG_DATA_VALID_IN_dl[1]") (joined - (portRef Q (instanceRef LVL1_TRG_DATA_VALID_IN_dl_1)) - (portRef C (instanceRef burst)) - (portRef A (instanceRef LVL1_TRG_DATA_VALI_IN_rising)) - (portRef D (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2)) - )) - (net (rename LVL1_TRG_DATA_VALID_IN_dl_2 "LVL1_TRG_DATA_VALID_IN_dl[2]") (joined - (portRef Q (instanceRef LVL1_TRG_DATA_VALID_IN_dl_2)) - (portRef B (instanceRef burst)) - (portRef B (instanceRef LVL1_TRG_DATA_VALI_IN_rising)) - )) - (net (rename LVL1_INVALID_TRG_IN_dl_0 "LVL1_INVALID_TRG_IN_dl[0]") (joined - (portRef LVL1_INVALID_TRG_IN_dl_0) - (portRef D (instanceRef LVL1_INVALID_TRG_IN_dl_1)) - )) - (net discard_c (joined - (portRef Q (instanceRef LVL1_INVALID_TRG_IN_dl_1)) - (portRef A (instanceRef burst)) - (portRef discard_c) - )) - (net burst_c (joined - (portRef Z (instanceRef burst)) - (portRef A (instanceRef buf_rden4)) - (portRef burst_c) - )) - (net last_buf_empty_c (joined - (portRef last_buf_empty_c) - (portRef C (instanceRef buf_rden4)) - )) - (net LVL1_TRG_DATA_VALI_IN_rising_c (joined - (portRef Z (instanceRef LVL1_TRG_DATA_VALI_IN_rising)) - (portRef LVL1_TRG_DATA_VALI_IN_rising_c) - )) - (net release_out_c (joined - (portRef Z (instanceRef release_out)) - (portRef release_out_c) - )) - ) - (property orig_inst_of (string "trb_adapter")) - ) - ) - (cell hades_tdc_bundle (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port hades_raw_out_0 (direction OUTPUT)) - (port hades_raw_out_1 (direction OUTPUT)) - (port hades_raw_out_2 (direction OUTPUT)) - (port hades_raw_out_12 (direction OUTPUT)) - (port hades_raw_out_13 (direction OUTPUT)) - (port hades_raw_out_14 (direction OUTPUT)) - (port hades_raw_out_15 (direction OUTPUT)) - (port hades_raw_out_16 (direction OUTPUT)) - (port hades_raw_out_17 (direction OUTPUT)) - (port hades_raw_out_18 (direction OUTPUT)) - (port hades_raw_out_19 (direction OUTPUT)) - (port hades_raw_out_20 (direction OUTPUT)) - (port hades_raw_out_21 (direction OUTPUT)) - (port hades_raw_out_22 (direction OUTPUT)) - (port hades_raw_out_23 (direction OUTPUT)) - (port trig_dl_0 (direction INPUT)) - (port (array (rename hades_invalid_dl_c "hades_invalid_dl_c[3:0]") 4) (direction INOUT)) - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction INPUT)) - (port (array (rename offset_5 "offset_5[2:0]") 3) (direction OUTPUT)) - (port (array (rename hades_dbg2_coarse_c "hades_dbg2_coarse_c[8:0]") 9) (direction OUTPUT)) - (port (array (rename hades_drop_cmp_buf_c "hades_drop_cmp_buf_c[8:0]") 9) (direction OUTPUT)) - (port (array (rename hades_drop_cmp_buf_coarse_c "hades_drop_cmp_buf_coarse_c[9:0]") 10) (direction OUTPUT)) - (port reset_dl_0 (direction INPUT)) - (port (array (rename hades_hit_valid_c "hades_hit_valid_c[3:0]") 4) (direction OUTPUT)) - (port reset_dl_i_0 (direction INPUT)) - (port (array (rename hades_dbg2_out_c "hades_dbg2_out_c[12:4]") 9) (direction OUTPUT)) - (port hades_trig_c_i (direction INPUT)) - (port offset_1_sqmuxa_i_0 (direction OUTPUT)) - (port hades_offset_valid_c (direction OUTPUT)) - (port hades_lvl1_c_i (direction INPUT)) - (port CN_2 (direction OUTPUT)) - (port CN_1 (direction OUTPUT)) - (port CN_0 (direction OUTPUT)) - (port CN (direction OUTPUT)) - (port valid_fast_RNI999V (direction OUTPUT)) - (port buf_out12_1z (direction OUTPUT)) - (port hades_window_end_c (direction OUTPUT)) - (port hades_discard_c (direction OUTPUT)) - (port N_248_i (direction OUTPUT)) - (port drop_cmp_buf_valid_0_sqmuxa (direction OUTPUT)) - (port hades_buf_release_c (direction OUTPUT)) - (port hades_buf_finished_c (direction OUTPUT)) - (port hades_drop_cmp_buf_valid_c (direction OUTPUT)) - (port un1_hit_i_2_0_a2_1z (direction OUTPUT)) - (port ANB1 (direction OUTPUT)) - (port ANB3 (direction OUTPUT)) - (port ANB0 (direction OUTPUT)) - (port ANB2 (direction OUTPUT)) - ) - (contents - (instance (rename coarse_RNI8DE6_0 "coarse_RNI8DE6[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance buf_finished_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename coarse_RNI6RPP_2 "coarse_RNI6RPP[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) - ) - (instance (rename hitbuffer_1__3 "hitbuffer_1_[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__4 "hitbuffer_1_[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__5 "hitbuffer_1_[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__6 "hitbuffer_1_[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__7 "hitbuffer_1_[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__8 "hitbuffer_1_[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__9 "hitbuffer_1_[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__10 "hitbuffer_1_[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hitbuffer_1__11 "hitbuffer_1_[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hit_valid_1_0 "hit_valid_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hit_valid_1_1 "hit_valid_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hit_valid_1_2 "hit_valid_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hit_valid_1_3 "hit_valid_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename hit_out_i_0 "hit_out_i[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_out_i_1 "hit_out_i[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_out_i_2 "hit_out_i[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_out_i_3 "hit_out_i[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_i_0 "hit_i[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_i_1 "hit_i[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance drop_cmp_buf_valid (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_0 "drop_cmp_buf_coarse_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_1 "drop_cmp_buf_coarse_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_2 "drop_cmp_buf_coarse_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_3 "drop_cmp_buf_coarse_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_4 "drop_cmp_buf_coarse_1[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_5 "drop_cmp_buf_coarse_1[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_6 "drop_cmp_buf_coarse_1[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_7 "drop_cmp_buf_coarse_1[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_8 "drop_cmp_buf_coarse_1[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_coarse_1_9 "drop_cmp_buf_coarse_1[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_0 "drop_cmp_buf_1[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_1 "drop_cmp_buf_1[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_2 "drop_cmp_buf_1[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_3 "drop_cmp_buf_1[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_4 "drop_cmp_buf_1[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_5 "drop_cmp_buf_1[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_6 "drop_cmp_buf_1[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_7 "drop_cmp_buf_1[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename drop_cmp_buf_1_8 "drop_cmp_buf_1[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename coarse_0 "coarse[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_1 "coarse[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_2 "coarse[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_3 "coarse[3]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_4 "coarse[4]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_5 "coarse[5]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_6 "coarse[6]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_7 "coarse[7]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename coarse_8 "coarse[8]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance buf_release (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance buf_finished (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename hit_valid_1_RNO_1 "hit_valid_1_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C !B))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D B+D (!C B+C (!B A+B !A)))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D A+D (!C A+C (!B A+B !A)))")) - ) - (instance drop_cmp_buf_coarse_2_ac0_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance hit_valid_pmux_iv_0_a2_2_RNITDG11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B+A))")) - ) - (instance (rename hit_out_i_RNO_0 "hit_out_i_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D !A+D (!C !A+C (B !A)))")) - ) - (instance (rename hit_valid_1_RNO_2 "hit_valid_1_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))")) - ) - (instance (rename hit_valid_1_RNO_3 "hit_valid_1_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))")) - ) - (instance (rename hit_valid_1_RNO_0 "hit_valid_1_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)+C !B)+D (C !B))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (!C (B A)+C (!B+!A)))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D B+D (!C B+C (!B A+B !A)))")) - ) - (instance (rename hit_out_i_6_f1_0_2 "hit_out_i_6_f1_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B !A+B A)+D (C+(!B !A+B A)))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C B+C (!B A+B !A))")) - ) - (instance drop_cmp_buf_coarse_2_ac0_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) - ) - (instance hit_valid_pmux_iv_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D B+D (!C B+C (B+!A)))")) - ) - (instance drop_cmp_buf_coarse_2_ac0_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance hit_valid_pmux_iv_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B A)))")) - ) - (instance drop_cmp_buf_valid_4_iv_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A)+C (B !A))")) - ) - (instance drop_cmp_buf_coarse_2_axbxc2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A)+C (!B+!A))")) - ) - (instance drop_cmp_buf_coarse_2_ac0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B A))")) - ) - (instance hit_valid_pmux_iv_0_m2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C (B+A))")) - ) - (instance drop_cmp_buf_valid_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance drop_cmp_buf_0_sqmuxa_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance (rename hit_valid_4_i_o2_0_2 "hit_valid_4_i_o2_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B+!A)")) - ) - (instance (rename hit_out_i_6_f1_0_o2_2 "hit_out_i_6_f1_0_o2[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+!A)")) - ) - (instance buf_finished5_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance drop_cmp_buf_coarse_2_axbxc1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A+B !A)")) - ) - (instance (rename hit_out_i_6_i_a2_0_0 "hit_out_i_6_i_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B !A)")) - ) - (instance drop_cmp_buf_coarse_2_ac0_9_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance drop_cmp_buf_coarse_2_ac0_13_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(B A)")) - ) - (instance buf_out12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance hit_valid_pmux_iv_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) - ) - (instance un1_hit_i_2_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A)))")) - ) - (instance hit_valid25_0_I_1_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x500c")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x9009")) - ) - (instance hit_valid25_0_I_9_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x9009")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x9009")) - ) - (instance hit_valid25_0_I_21_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x9009")) - (property INJECT1_1 (string "YES")) - (property INJECT1_0 (string "YES")) - (property INIT1 (string "0x410a")) - ) - (instance hit_valid25_0_I_27_0 (viewRef PRIM (cellRef CCU2C (libraryRef LUCENT))) - (property INIT0 (string "0x5003")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x0000")) - ) - (instance hades_LVL1_raw_out_inst (viewRef netlist (cellRef hades_LVL1_raw_out)) - ) - (instance hades_tdc_channel_raw_out_inst (viewRef netlist (cellRef hades_tdc_channel_raw_out)) - ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined - (portRef Q (instanceRef coarse_0)) - (portRef (member hades_dbg2_coarse_c 8) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc1)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_3)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc2)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_5)) - (portRef D (instanceRef coarse_RNI6RPP_2)) - (portRef A (instanceRef coarse_RNI8DE6_0)) - (portRef (member hades_dbg2_coarse_c 8)) - )) - (net (rename hades_dbg2_coarse_c_i_0 "hades_dbg2_coarse_c_i[0]") (joined - (portRef Z (instanceRef coarse_RNI8DE6_0)) - (portRef D (instanceRef coarse_0)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_0)) - )) - (net ANB2 (joined - (portRef Q (instanceRef hit_out_i_2)) - (portRef ANB2 (instanceRef hades_LVL1_raw_out_inst)) - (portRef B (instanceRef hit_valid_pmux_iv_0_a2)) - (portRef A (instanceRef hit_valid_pmux_iv_0_0)) - (portRef A (instanceRef hit_out_i_6_f1_0_2)) - (portRef B (instanceRef hit_out_i_RNO_0)) - (portRef A (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11)) - (portRef A (instanceRef buf_finished_RNO)) - (portRef ANB2) - )) - (net ANB0 (joined - (portRef Q (instanceRef hit_out_i_0)) - (portRef ANB0 (instanceRef hades_LVL1_raw_out_inst)) - (portRef A (instanceRef hit_valid_pmux_iv_0_a2_2)) - (portRef A (instanceRef hit_out_i_6_f1_0_o2_2)) - (portRef A (instanceRef hit_valid_pmux_iv_0_m2)) - (portRef A (instanceRef hit_out_i_RNO_0)) - (portRef B (instanceRef buf_finished_RNO)) - (portRef ANB0) - )) - (net ANB3 (joined - (portRef Q (instanceRef hit_out_i_3)) - (portRef ANB3 (instanceRef hades_LVL1_raw_out_inst)) - (portRef B (instanceRef hit_valid_pmux_iv_0_a2_2)) - (portRef B (instanceRef buf_finished5_0_a2_0)) - (portRef C (instanceRef hit_valid_pmux_iv_0_a2)) - (portRef C (instanceRef buf_finished_RNO)) - (portRef ANB3) - )) - (net ANB1 (joined - (portRef Q (instanceRef hit_out_i_1)) - (portRef ANB1 (instanceRef hades_LVL1_raw_out_inst)) - (portRef C (instanceRef hit_valid_pmux_iv_0_a2_2)) - (portRef A (instanceRef buf_finished5_0_a2_0)) - (portRef B (instanceRef hit_out_i_6_f1_0_o2_2)) - (portRef A (instanceRef hit_valid_pmux_iv_0_a2)) - (portRef D (instanceRef buf_finished_RNO)) - (portRef ANB1) - )) - (net buf_finished5 (joined - (portRef Z (instanceRef buf_finished_RNO)) - (portRef D (instanceRef buf_finished)) - )) - (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined - (portRef Q (instanceRef coarse_3)) - (portRef (member hades_dbg2_coarse_c 5) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_ac0_5)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_7)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc4)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc6)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc5)) - (portRef A (instanceRef coarse_RNI6RPP_2)) - (portRef (member hades_dbg2_coarse_c 5)) - )) - (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined - (portRef Q (instanceRef coarse_2)) - (portRef (member hades_dbg2_coarse_c 6) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_3)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc2)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_5)) - (portRef B (instanceRef coarse_RNI6RPP_2)) - (portRef (member hades_dbg2_coarse_c 6)) - )) - (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined - (portRef Q (instanceRef coarse_1)) - (portRef (member hades_dbg2_coarse_c 7) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc1)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_3)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc2)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_5)) - (portRef C (instanceRef coarse_RNI6RPP_2)) - (portRef (member hades_dbg2_coarse_c 7)) - )) - (net (rename drop_cmp_buf_coarse_2_3 "drop_cmp_buf_coarse_2[3]") (joined - (portRef Z (instanceRef coarse_RNI6RPP_2)) - (portRef D (instanceRef coarse_3)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_3)) - )) - (net (rename hades_raw_out_3 "hades_raw_out[3]") (joined - (portRef (member hades_raw_out 20) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__3)) - )) - (net (rename un1_hit_i_2_0_a2_1z "un1_hit_i_2_0_a2") (joined - (portRef Z (instanceRef un1_hit_i_2_0_a2)) - (portRef SP (instanceRef hitbuffer_1__11)) - (portRef SP (instanceRef hitbuffer_1__10)) - (portRef SP (instanceRef hitbuffer_1__9)) - (portRef SP (instanceRef hitbuffer_1__8)) - (portRef SP (instanceRef hitbuffer_1__7)) - (portRef SP (instanceRef hitbuffer_1__6)) - (portRef SP (instanceRef hitbuffer_1__5)) - (portRef SP (instanceRef hitbuffer_1__4)) - (portRef SP (instanceRef hitbuffer_1__3)) - (portRef un1_hit_i_2_0_a2_1z) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef (member pll_clks 0) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef (member pll_clks 0) (instanceRef hades_LVL1_raw_out_inst)) - (portRef CK (instanceRef buf_finished)) - (portRef CK (instanceRef buf_release)) - (portRef CK (instanceRef coarse_8)) - (portRef CK (instanceRef coarse_7)) - (portRef CK (instanceRef coarse_6)) - (portRef CK (instanceRef coarse_5)) - (portRef CK (instanceRef coarse_4)) - (portRef CK (instanceRef coarse_3)) - (portRef CK (instanceRef coarse_2)) - (portRef CK (instanceRef coarse_1)) - (portRef CK (instanceRef coarse_0)) - (portRef CK (instanceRef drop_cmp_buf_1_8)) - (portRef CK (instanceRef drop_cmp_buf_1_7)) - (portRef CK (instanceRef drop_cmp_buf_1_6)) - (portRef CK (instanceRef drop_cmp_buf_1_5)) - (portRef CK (instanceRef drop_cmp_buf_1_4)) - (portRef CK (instanceRef drop_cmp_buf_1_3)) - (portRef CK (instanceRef drop_cmp_buf_1_2)) - (portRef CK (instanceRef drop_cmp_buf_1_1)) - (portRef CK (instanceRef drop_cmp_buf_1_0)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_9)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_8)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_7)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_6)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_5)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_4)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_3)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_2)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_1)) - (portRef CK (instanceRef drop_cmp_buf_coarse_1_0)) - (portRef CK (instanceRef drop_cmp_buf_valid)) - (portRef CK (instanceRef hit_i_1)) - (portRef CK (instanceRef hit_i_0)) - (portRef CK (instanceRef hit_out_i_3)) - (portRef CK (instanceRef hit_out_i_2)) - (portRef CK (instanceRef hit_out_i_1)) - (portRef CK (instanceRef hit_out_i_0)) - (portRef CK (instanceRef hit_valid_1_3)) - (portRef CK (instanceRef hit_valid_1_2)) - (portRef CK (instanceRef hit_valid_1_1)) - (portRef CK (instanceRef hit_valid_1_0)) - (portRef CK (instanceRef hitbuffer_1__11)) - (portRef CK (instanceRef hitbuffer_1__10)) - (portRef CK (instanceRef hitbuffer_1__9)) - (portRef CK (instanceRef hitbuffer_1__8)) - (portRef CK (instanceRef hitbuffer_1__7)) - (portRef CK (instanceRef hitbuffer_1__6)) - (portRef CK (instanceRef hitbuffer_1__5)) - (portRef CK (instanceRef hitbuffer_1__4)) - (portRef CK (instanceRef hitbuffer_1__3)) - )) - (net (rename hades_dbg2_out_c_4 "hades_dbg2_out_c[4]") (joined - (portRef Q (instanceRef hitbuffer_1__3)) - (portRef D (instanceRef drop_cmp_buf_1_0)) - (portRef (member hades_dbg2_out_c 8)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef D1 (instanceRef hit_valid25_0_I_27_0)) - (portRef C1 (instanceRef hit_valid25_0_I_27_0)) - (portRef B1 (instanceRef hit_valid25_0_I_27_0)) - (portRef A1 (instanceRef hit_valid25_0_I_27_0)) - (portRef D0 (instanceRef hit_valid25_0_I_27_0)) - (portRef C0 (instanceRef hit_valid25_0_I_27_0)) - (portRef B0 (instanceRef hit_valid25_0_I_27_0)) - (portRef A0 (instanceRef hit_valid25_0_I_27_0)) - (portRef D1 (instanceRef hit_valid25_0_I_21_0)) - (portRef D0 (instanceRef hit_valid25_0_I_1_0)) - (portRef C0 (instanceRef hit_valid25_0_I_1_0)) - (portRef B0 (instanceRef hit_valid25_0_I_1_0)) - (portRef A0 (instanceRef hit_valid25_0_I_1_0)) - )) - (net (rename hades_raw_out_4 "hades_raw_out[4]") (joined - (portRef (member hades_raw_out 19) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__4)) - )) - (net (rename hades_dbg2_out_c_5 "hades_dbg2_out_c[5]") (joined - (portRef Q (instanceRef hitbuffer_1__4)) - (portRef D (instanceRef drop_cmp_buf_1_1)) - (portRef (member hades_dbg2_out_c 7)) - )) - (net (rename hades_raw_out_5 "hades_raw_out[5]") (joined - (portRef (member hades_raw_out 18) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__5)) - )) - (net (rename hades_dbg2_out_c_6 "hades_dbg2_out_c[6]") (joined - (portRef Q (instanceRef hitbuffer_1__5)) - (portRef D (instanceRef drop_cmp_buf_1_2)) - (portRef (member hades_dbg2_out_c 6)) - )) - (net (rename hades_raw_out_6 "hades_raw_out[6]") (joined - (portRef (member hades_raw_out 17) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__6)) - )) - (net (rename hades_dbg2_out_c_7 "hades_dbg2_out_c[7]") (joined - (portRef Q (instanceRef hitbuffer_1__6)) - (portRef D (instanceRef drop_cmp_buf_1_3)) - (portRef (member hades_dbg2_out_c 5)) - )) - (net (rename hades_raw_out_7 "hades_raw_out[7]") (joined - (portRef (member hades_raw_out 16) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__7)) - )) - (net (rename hades_dbg2_out_c_8 "hades_dbg2_out_c[8]") (joined - (portRef Q (instanceRef hitbuffer_1__7)) - (portRef D (instanceRef drop_cmp_buf_1_4)) - (portRef (member hades_dbg2_out_c 4)) - )) - (net (rename hades_raw_out_8 "hades_raw_out[8]") (joined - (portRef (member hades_raw_out 15) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__8)) - )) - (net (rename hades_dbg2_out_c_9 "hades_dbg2_out_c[9]") (joined - (portRef Q (instanceRef hitbuffer_1__8)) - (portRef D (instanceRef drop_cmp_buf_1_5)) - (portRef (member hades_dbg2_out_c 3)) - )) - (net (rename hades_raw_out_9 "hades_raw_out[9]") (joined - (portRef (member hades_raw_out 14) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__9)) - )) - (net (rename hades_dbg2_out_c_10 "hades_dbg2_out_c[10]") (joined - (portRef Q (instanceRef hitbuffer_1__9)) - (portRef D (instanceRef drop_cmp_buf_1_6)) - (portRef (member hades_dbg2_out_c 2)) - )) - (net (rename hades_raw_out_10 "hades_raw_out[10]") (joined - (portRef (member hades_raw_out 13) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__10)) - )) - (net (rename hades_dbg2_out_c_11 "hades_dbg2_out_c[11]") (joined - (portRef Q (instanceRef hitbuffer_1__10)) - (portRef D (instanceRef drop_cmp_buf_1_7)) - (portRef (member hades_dbg2_out_c 1)) - )) - (net (rename hades_raw_out_11 "hades_raw_out[11]") (joined - (portRef (member hades_raw_out 12) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef hitbuffer_1__11)) - )) - (net (rename hades_dbg2_out_c_12 "hades_dbg2_out_c[12]") (joined - (portRef Q (instanceRef hitbuffer_1__11)) - (portRef D (instanceRef drop_cmp_buf_1_8)) - (portRef (member hades_dbg2_out_c 0)) - )) - (net N_246_i (joined - (portRef Z (instanceRef hit_valid_1_RNO_0)) - (portRef D (instanceRef hit_valid_1_0)) - )) - (net (rename reset_dl_i_0 "reset_dl_i[2]") (joined - (portRef reset_dl_i_0) - (portRef reset_dl_i_0 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef SP (instanceRef drop_cmp_buf_valid)) - (portRef SP (instanceRef hit_valid_1_3)) - (portRef SP (instanceRef hit_valid_1_2)) - (portRef SP (instanceRef hit_valid_1_1)) - (portRef SP (instanceRef hit_valid_1_0)) - )) - (net (rename hades_hit_valid_c_0 "hades_hit_valid_c[0]") (joined - (portRef Q (instanceRef hit_valid_1_0)) - (portRef D (instanceRef hit_valid_pmux_iv_0_0)) - (portRef C (instanceRef hit_valid_1_RNO_0)) - (portRef (member hades_hit_valid_c 3)) - )) - (net N_243_i (joined - (portRef Z (instanceRef hit_valid_1_RNO_1)) - (portRef D (instanceRef hit_valid_1_1)) - )) - (net (rename hades_hit_valid_c_1 "hades_hit_valid_c[1]") (joined - (portRef Q (instanceRef hit_valid_1_1)) - (portRef A (instanceRef drop_cmp_buf_0_sqmuxa_0_a2)) - (portRef B (instanceRef hit_valid_pmux_iv_0_m2)) - (portRef B (instanceRef drop_cmp_buf_valid_4_iv_i)) - (portRef C (instanceRef hit_valid_1_RNO_1)) - (portRef (member hades_hit_valid_c 2)) - )) - (net N_245_i (joined - (portRef Z (instanceRef hit_valid_1_RNO_2)) - (portRef D (instanceRef hit_valid_1_2)) - )) - (net (rename hades_hit_valid_c_2 "hades_hit_valid_c[2]") (joined - (portRef Q (instanceRef hit_valid_1_2)) - (portRef C (instanceRef hit_valid_pmux_iv_0_m2)) - (portRef C (instanceRef hit_valid_1_RNO_2)) - (portRef (member hades_hit_valid_c 1)) - )) - (net N_244_i (joined - (portRef Z (instanceRef hit_valid_1_RNO_3)) - (portRef D (instanceRef hit_valid_1_3)) - )) - (net (rename hades_hit_valid_c_3 "hades_hit_valid_c[3]") (joined - (portRef Q (instanceRef hit_valid_1_3)) - (portRef B (instanceRef buf_out12)) - (portRef C (instanceRef hit_valid_1_RNO_3)) - (portRef (member hades_hit_valid_c 0)) - )) - (net N_247_i (joined - (portRef Z (instanceRef hit_out_i_RNO_0)) - (portRef D (instanceRef hit_out_i_0)) - )) - (net (rename reset_dl_0 "reset_dl[2]") (joined - (portRef reset_dl_0) - (portRef reset_dl_0 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef reset_dl_0 (instanceRef hades_LVL1_raw_out_inst)) - (portRef A (instanceRef un1_hit_i_2_0_a2)) - (portRef B (instanceRef drop_cmp_buf_0_sqmuxa_0_a2)) - (portRef C (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11)) - (portRef CD (instanceRef buf_finished)) - (portRef CD (instanceRef buf_release)) - (portRef CD (instanceRef coarse_8)) - (portRef CD (instanceRef coarse_7)) - (portRef CD (instanceRef coarse_6)) - (portRef CD (instanceRef coarse_5)) - (portRef CD (instanceRef coarse_4)) - (portRef CD (instanceRef coarse_3)) - (portRef CD (instanceRef coarse_2)) - (portRef CD (instanceRef coarse_1)) - (portRef CD (instanceRef coarse_0)) - (portRef CD (instanceRef hit_i_1)) - (portRef CD (instanceRef hit_i_0)) - (portRef CD (instanceRef hit_out_i_3)) - (portRef CD (instanceRef hit_out_i_2)) - (portRef CD (instanceRef hit_out_i_1)) - (portRef CD (instanceRef hit_out_i_0)) - )) - (net N_46_i (joined - (portRef N_46_i (instanceRef hades_LVL1_raw_out_inst)) - (portRef D (instanceRef hit_out_i_1)) - )) - (net (rename hit_out_i_6_2 "hit_out_i_6[2]") (joined - (portRef Z (instanceRef hit_out_i_6_f1_0_2)) - (portRef D (instanceRef hit_out_i_2)) - )) - (net N_50_i_i (joined - (portRef N_50_i_i_1z (instanceRef hades_LVL1_raw_out_inst)) - (portRef D (instanceRef hit_out_i_3)) - )) - (net N_59_i (joined - (portRef N_59_i (instanceRef hades_LVL1_raw_out_inst)) - (portRef D (instanceRef hit_i_0)) - )) - (net (rename hit_i_0 "hit_i[0]") (joined - (portRef Q (instanceRef hit_i_0)) - (portRef (member hit_i 1) (instanceRef hades_LVL1_raw_out_inst)) - (portRef C (instanceRef un1_hit_i_2_0_a2)) - (portRef B (instanceRef hit_valid_4_i_o2_0_2)) - )) - (net SUM1_0_0 (joined - (portRef SUM1_0_0_1z (instanceRef hades_LVL1_raw_out_inst)) - (portRef D (instanceRef hit_i_1)) - )) - (net (rename hit_i_1 "hit_i[1]") (joined - (portRef Q (instanceRef hit_i_1)) - (portRef (member hit_i 0) (instanceRef hades_LVL1_raw_out_inst)) - (portRef D (instanceRef un1_hit_i_2_0_a2)) - (portRef D (instanceRef hit_valid_1_RNO_0)) - (portRef D (instanceRef hit_valid_1_RNO_3)) - (portRef D (instanceRef hit_valid_1_RNO_2)) - )) - (net drop_cmp_buf_valid_4_iv_i (joined - (portRef Z (instanceRef drop_cmp_buf_valid_4_iv_i)) - (portRef D (instanceRef drop_cmp_buf_valid)) - )) - (net hades_drop_cmp_buf_valid_c (joined - (portRef Q (instanceRef drop_cmp_buf_valid)) - (portRef A (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2)) - (portRef A (instanceRef drop_cmp_buf_valid_4_iv_i)) - (portRef hades_drop_cmp_buf_valid_c) - )) - (net drop_cmp_buf_0_sqmuxa (joined - (portRef Z (instanceRef drop_cmp_buf_0_sqmuxa_0_a2)) - (portRef SP (instanceRef drop_cmp_buf_1_8)) - (portRef SP (instanceRef drop_cmp_buf_1_7)) - (portRef SP (instanceRef drop_cmp_buf_1_6)) - (portRef SP (instanceRef drop_cmp_buf_1_5)) - (portRef SP (instanceRef drop_cmp_buf_1_4)) - (portRef SP (instanceRef drop_cmp_buf_1_3)) - (portRef SP (instanceRef drop_cmp_buf_1_2)) - (portRef SP (instanceRef drop_cmp_buf_1_1)) - (portRef SP (instanceRef drop_cmp_buf_1_0)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_9)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_8)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_7)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_6)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_5)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_4)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_3)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_2)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_1)) - (portRef SP (instanceRef drop_cmp_buf_coarse_1_0)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_0 "hades_drop_cmp_buf_coarse_c[0]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_0)) - (portRef C1 (instanceRef hit_valid25_0_I_1_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 9)) - )) - (net (rename drop_cmp_buf_coarse_2_1 "drop_cmp_buf_coarse_2[1]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc1)) - (portRef D (instanceRef coarse_1)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_1)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_1 "hades_drop_cmp_buf_coarse_c[1]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_1)) - (portRef A1 (instanceRef hit_valid25_0_I_1_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 8)) - )) - (net (rename drop_cmp_buf_coarse_2_2 "drop_cmp_buf_coarse_2[2]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc2)) - (portRef D (instanceRef coarse_2)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_2)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_2 "hades_drop_cmp_buf_coarse_c[2]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_2)) - (portRef C0 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 7)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_3 "hades_drop_cmp_buf_coarse_c[3]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_3)) - (portRef A0 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 6)) - )) - (net (rename drop_cmp_buf_coarse_2_4 "drop_cmp_buf_coarse_2[4]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc4)) - (portRef D (instanceRef coarse_4)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_4)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_4 "hades_drop_cmp_buf_coarse_c[4]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_4)) - (portRef C1 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 5)) - )) - (net (rename drop_cmp_buf_coarse_2_5 "drop_cmp_buf_coarse_2[5]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc5)) - (portRef D (instanceRef coarse_5)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_5)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_5 "hades_drop_cmp_buf_coarse_c[5]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_5)) - (portRef A1 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 4)) - )) - (net (rename drop_cmp_buf_coarse_2_6 "drop_cmp_buf_coarse_2[6]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc6)) - (portRef D (instanceRef coarse_6)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_6)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_6 "hades_drop_cmp_buf_coarse_c[6]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_6)) - (portRef C0 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 3)) - )) - (net (rename drop_cmp_buf_coarse_2_7 "drop_cmp_buf_coarse_2[7]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc7)) - (portRef D (instanceRef coarse_7)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_7)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_7 "hades_drop_cmp_buf_coarse_c[7]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_7)) - (portRef A0 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 2)) - )) - (net (rename drop_cmp_buf_coarse_2_8 "drop_cmp_buf_coarse_2[8]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_axbxc8)) - (portRef D (instanceRef coarse_8)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_8)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_8 "hades_drop_cmp_buf_coarse_c[8]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_8)) - (portRef B1 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 1)) - )) - (net (rename drop_cmp_buf_coarse_2_9 "drop_cmp_buf_coarse_2[9]") (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_15)) - (portRef D (instanceRef drop_cmp_buf_coarse_1_9)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_9 "hades_drop_cmp_buf_coarse_c[9]") (joined - (portRef Q (instanceRef drop_cmp_buf_coarse_1_9)) - (portRef A1 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_coarse_c 0)) - )) - (net (rename hades_drop_cmp_buf_c_0 "hades_drop_cmp_buf_c[0]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_0)) - (portRef D1 (instanceRef hit_valid25_0_I_1_0)) - (portRef (member hades_drop_cmp_buf_c 8)) - )) - (net (rename hades_drop_cmp_buf_c_1 "hades_drop_cmp_buf_c[1]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_1)) - (portRef B1 (instanceRef hit_valid25_0_I_1_0)) - (portRef (member hades_drop_cmp_buf_c 7)) - )) - (net (rename hades_drop_cmp_buf_c_2 "hades_drop_cmp_buf_c[2]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_2)) - (portRef D0 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_c 6)) - )) - (net (rename hades_drop_cmp_buf_c_3 "hades_drop_cmp_buf_c[3]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_3)) - (portRef B0 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_c 5)) - )) - (net (rename hades_drop_cmp_buf_c_4 "hades_drop_cmp_buf_c[4]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_4)) - (portRef D1 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_c 4)) - )) - (net (rename hades_drop_cmp_buf_c_5 "hades_drop_cmp_buf_c[5]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_5)) - (portRef B1 (instanceRef hit_valid25_0_I_9_0)) - (portRef (member hades_drop_cmp_buf_c 3)) - )) - (net (rename hades_drop_cmp_buf_c_6 "hades_drop_cmp_buf_c[6]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_6)) - (portRef D0 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_c 2)) - )) - (net (rename hades_drop_cmp_buf_c_7 "hades_drop_cmp_buf_c[7]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_7)) - (portRef B0 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_c 1)) - )) - (net (rename hades_drop_cmp_buf_c_8 "hades_drop_cmp_buf_c[8]") (joined - (portRef Q (instanceRef drop_cmp_buf_1_8)) - (portRef C1 (instanceRef hit_valid25_0_I_21_0)) - (portRef (member hades_drop_cmp_buf_c 0)) - )) - (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined - (portRef Q (instanceRef coarse_4)) - (portRef (member hades_dbg2_coarse_c 4) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_9_0)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_7)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc4)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc5)) - (portRef (member hades_dbg2_coarse_c 4)) - )) - (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined - (portRef Q (instanceRef coarse_5)) - (portRef (member hades_dbg2_coarse_c 3) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_9_0)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc5)) - (portRef (member hades_dbg2_coarse_c 3)) - )) - (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined - (portRef Q (instanceRef coarse_6)) - (portRef (member hades_dbg2_coarse_c 2) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_13_0)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc6)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc7)) - (portRef (member hades_dbg2_coarse_c 2)) - )) - (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined - (portRef Q (instanceRef coarse_7)) - (portRef (member hades_dbg2_coarse_c 1) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_13_0)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc7)) - (portRef (member hades_dbg2_coarse_c 1)) - )) - (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined - (portRef Q (instanceRef coarse_8)) - (portRef (member hades_dbg2_coarse_c 0) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_ac0_15)) - (portRef A (instanceRef drop_cmp_buf_coarse_2_axbxc8)) - (portRef (member hades_dbg2_coarse_c 0)) - )) - (net hades_buf_finished_c (joined - (portRef Q (instanceRef buf_finished)) - (portRef D (instanceRef buf_release)) - (portRef hades_buf_finished_c) - )) - (net hades_buf_release_c (joined - (portRef Q (instanceRef buf_release)) - (portRef B (instanceRef hit_valid_1_RNO_0)) - (portRef B (instanceRef hit_valid_1_RNO_3)) - (portRef B (instanceRef hit_valid_1_RNO_2)) - (portRef B (instanceRef hit_valid_1_RNO_1)) - (portRef hades_buf_release_c) - )) - (net N_44 (joined - (portRef N_44 (instanceRef hades_LVL1_raw_out_inst)) - (portRef A (instanceRef hit_valid_1_RNO_1)) - )) - (net drop_cmp_buf_valid_0_sqmuxa (joined - (portRef Z (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2)) - (portRef D (instanceRef hit_valid_1_RNO_1)) - (portRef drop_cmp_buf_valid_0_sqmuxa) - )) - (net drop_cmp_buf_coarse_2_ac0_9_0 (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_9_0)) - (portRef drop_cmp_buf_coarse_2_ac0_9_0 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc6)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_ac0_15)) - (portRef B (instanceRef drop_cmp_buf_coarse_2_axbxc8)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc7)) - )) - (net drop_cmp_buf_coarse_2_c4 (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_5)) - (portRef drop_cmp_buf_coarse_2_c4 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_ac0_15)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc8)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc7)) - )) - (net drop_cmp_buf_coarse_2_ac0_13_0 (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_13_0)) - (portRef drop_cmp_buf_coarse_2_ac0_13_0 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_15)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc8)) - )) - (net N_90 (joined - (portRef Z (instanceRef hit_valid_pmux_iv_0_a2_2)) - (portRef A (instanceRef buf_out12)) - (portRef C (instanceRef hit_out_i_6_f1_0_2)) - (portRef B (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11)) - )) - (net N_248_i (joined - (portRef Z (instanceRef hit_valid_pmux_iv_0_a2_2_RNITDG11)) - (portRef N_248_i) - )) - (net N_80 (joined - (portRef Z (instanceRef buf_finished5_0_a2_0)) - (portRef C (instanceRef hit_valid_pmux_iv_0_0)) - (portRef C (instanceRef hit_out_i_RNO_0)) - )) - (net (rename hit_out_i_6_i_a2_0_0 "hit_out_i_6_i_a2_0[0]") (joined - (portRef Z (instanceRef hit_out_i_6_i_a2_0_0)) - (portRef D (instanceRef hit_out_i_RNO_0)) - )) - (net N_42 (joined - (portRef Z (instanceRef hit_valid_4_i_o2_0_2)) - (portRef A (instanceRef hit_valid_1_RNO_0)) - (portRef A (instanceRef hit_valid_1_RNO_2)) - )) - (net N_40 (joined - (portRef N_40 (instanceRef hades_LVL1_raw_out_inst)) - (portRef A (instanceRef hit_valid_1_RNO_3)) - )) - (net drop_cmp_buf_coarse_2_c3 (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_3)) - (portRef drop_cmp_buf_coarse_2_c3 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_ac0_7)) - (portRef C (instanceRef drop_cmp_buf_coarse_2_axbxc4)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc6)) - (portRef D (instanceRef drop_cmp_buf_coarse_2_axbxc5)) - )) - (net N_41 (joined - (portRef Z (instanceRef hit_out_i_6_f1_0_o2_2)) - (portRef B (instanceRef hit_out_i_6_f1_0_2)) - )) - (net hades_discard_c (joined - (portRef hades_discard_c (instanceRef hades_LVL1_raw_out_inst)) - (portRef A (instanceRef hit_out_i_6_i_a2_0_0)) - (portRef D (instanceRef hit_out_i_6_f1_0_2)) - (portRef hades_discard_c) - )) - (net drop_cmp_buf_coarse_2_c5 (joined - (portRef Z (instanceRef drop_cmp_buf_coarse_2_ac0_7)) - (portRef drop_cmp_buf_coarse_2_c5 (instanceRef hades_tdc_channel_raw_out_inst)) - )) - (net N_66 (joined - (portRef Z (instanceRef hit_valid_pmux_iv_0_a2)) - (portRef B (instanceRef hit_valid_pmux_iv_0_0)) - )) - (net hit_valid_pmux_iv_0_0 (joined - (portRef Z (instanceRef hit_valid_pmux_iv_0_0)) - (portRef C (instanceRef buf_out12)) - )) - (net N_45 (joined - (portRef Z (instanceRef hit_valid_pmux_iv_0_m2)) - (portRef D (instanceRef hit_valid_pmux_iv_0_a2)) - )) - (net hit_valid25 (joined - (portRef S0 (instanceRef hit_valid25_0_I_27_0)) - (portRef B (instanceRef drop_cmp_buf_valid_0_sqmuxa_0_a2)) - (portRef C (instanceRef drop_cmp_buf_valid_4_iv_i)) - )) - (net hades_raw_out_valid (joined - (portRef hades_raw_out_valid (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_valid (instanceRef hades_LVL1_raw_out_inst)) - (portRef B (instanceRef un1_hit_i_2_0_a2)) - (portRef A (instanceRef hit_valid_4_i_o2_0_2)) - )) - (net hades_window_end_c (joined - (portRef hades_window_end_c (instanceRef hades_LVL1_raw_out_inst)) - (portRef B (instanceRef hit_out_i_6_i_a2_0_0)) - (portRef hades_window_end_c) - )) - (net (rename buf_out12_1z "buf_out12") (joined - (portRef Z (instanceRef buf_out12)) - (portRef buf_out12_1z) - )) - (net (rename hit_valid25_0_data_tmp_0 "hit_valid25_0_data_tmp[0]") (joined - (portRef COUT (instanceRef hit_valid25_0_I_1_0)) - (portRef CIN (instanceRef hit_valid25_0_I_9_0)) - )) - (net hit_valid25_0_I_1_0_S0 (joined - (portRef S0 (instanceRef hit_valid25_0_I_1_0)) - )) - (net hit_valid25_0_I_1_0_S1 (joined - (portRef S1 (instanceRef hit_valid25_0_I_1_0)) - )) - (net (rename hit_valid25_0_data_tmp_2 "hit_valid25_0_data_tmp[2]") (joined - (portRef COUT (instanceRef hit_valid25_0_I_9_0)) - (portRef CIN (instanceRef hit_valid25_0_I_21_0)) - )) - (net hit_valid25_0_I_9_0_S0 (joined - (portRef S0 (instanceRef hit_valid25_0_I_9_0)) - )) - (net hit_valid25_0_I_9_0_S1 (joined - (portRef S1 (instanceRef hit_valid25_0_I_9_0)) - )) - (net hit_valid25_0_I_27_cry (joined - (portRef COUT (instanceRef hit_valid25_0_I_21_0)) - (portRef CIN (instanceRef hit_valid25_0_I_27_0)) - )) - (net hit_valid25_0_I_21_0_S0 (joined - (portRef S0 (instanceRef hit_valid25_0_I_21_0)) - )) - (net hit_valid25_0_I_21_0_S1 (joined - (portRef S1 (instanceRef hit_valid25_0_I_21_0)) - )) - (net hit_valid25_0_I_27_0_COUT (joined - (portRef COUT (instanceRef hit_valid25_0_I_27_0)) - )) - (net hit_valid25_0_I_27_0_S1 (joined - (portRef S1 (instanceRef hit_valid25_0_I_27_0)) - )) - (net (rename offset_5_0 "offset_5[0]") (joined - (portRef (member offset_5 2) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member offset_5 2)) - )) - (net (rename offset_5_1 "offset_5[1]") (joined - (portRef (member offset_5 1) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member offset_5 1)) - )) - (net (rename offset_5_2 "offset_5[2]") (joined - (portRef (member offset_5 0) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member offset_5 0)) - )) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3)) - (portRef (member pll_clks 3) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef (member pll_clks 3) (instanceRef hades_LVL1_raw_out_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef (member pll_clks 2) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef (member pll_clks 2) (instanceRef hades_LVL1_raw_out_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef (member pll_clks 1) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef (member pll_clks 1) (instanceRef hades_LVL1_raw_out_inst)) - )) - (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined - (portRef (member hades_invalid_dl_c 3)) - (portRef (member hades_invalid_dl_c 3) (instanceRef hades_LVL1_raw_out_inst)) - )) - (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined - (portRef (member hades_invalid_dl_c 2) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member hades_invalid_dl_c 2)) - )) - (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined - (portRef (member hades_invalid_dl_c 1) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member hades_invalid_dl_c 1)) - )) - (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined - (portRef (member hades_invalid_dl_c 0) (instanceRef hades_LVL1_raw_out_inst)) - (portRef (member hades_invalid_dl_c 0)) - )) - (net (rename trig_dl_0 "trig_dl[0]") (joined - (portRef trig_dl_0) - (portRef trig_dl_0 (instanceRef hades_LVL1_raw_out_inst)) - )) - (net valid_fast_RNI999V (joined - (portRef valid_fast_RNI999V (instanceRef hades_LVL1_raw_out_inst)) - (portRef valid_fast_RNI999V) - )) - (net CN (joined - (portRef CN_2 (instanceRef hades_LVL1_raw_out_inst)) - (portRef CN_1 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef CN) - )) - (net CN_0 (joined - (portRef CN_1 (instanceRef hades_LVL1_raw_out_inst)) - (portRef CN_0 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef CN_0) - )) - (net CN_1 (joined - (portRef CN_0 (instanceRef hades_LVL1_raw_out_inst)) - (portRef CN (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef CN_1) - )) - (net CN_2 (joined - (portRef CN (instanceRef hades_LVL1_raw_out_inst)) - (portRef CN_2 (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef CN_2) - )) - (net hades_lvl1_c_i (joined - (portRef hades_lvl1_c_i) - (portRef hades_lvl1_c_i (instanceRef hades_LVL1_raw_out_inst)) - )) - (net hades_offset_valid_c (joined - (portRef hades_offset_valid_c (instanceRef hades_LVL1_raw_out_inst)) - (portRef hades_offset_valid_c) - )) - (net offset_1_sqmuxa_i_0 (joined - (portRef offset_1_sqmuxa_i_0_1z (instanceRef hades_LVL1_raw_out_inst)) - (portRef offset_1_sqmuxa_i_0) - )) - (net (rename hades_raw_out_0 "hades_raw_out[0]") (joined - (portRef (member hades_raw_out 23) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_0) - )) - (net (rename hades_raw_out_1 "hades_raw_out[1]") (joined - (portRef (member hades_raw_out 22) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_1) - )) - (net (rename hades_raw_out_2 "hades_raw_out[2]") (joined - (portRef (member hades_raw_out 21) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_2) - )) - (net (rename hades_raw_out_12 "hades_raw_out[12]") (joined - (portRef (member hades_raw_out 11) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_12) - )) - (net (rename hades_raw_out_13 "hades_raw_out[13]") (joined - (portRef (member hades_raw_out 10) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_13) - )) - (net (rename hades_raw_out_14 "hades_raw_out[14]") (joined - (portRef (member hades_raw_out 9) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_14) - )) - (net (rename hades_raw_out_15 "hades_raw_out[15]") (joined - (portRef (member hades_raw_out 8) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_15) - )) - (net (rename hades_raw_out_16 "hades_raw_out[16]") (joined - (portRef (member hades_raw_out 7) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_16) - )) - (net (rename hades_raw_out_17 "hades_raw_out[17]") (joined - (portRef (member hades_raw_out 6) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_17) - )) - (net (rename hades_raw_out_18 "hades_raw_out[18]") (joined - (portRef (member hades_raw_out 5) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_18) - )) - (net (rename hades_raw_out_19 "hades_raw_out[19]") (joined - (portRef (member hades_raw_out 4) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_19) - )) - (net (rename hades_raw_out_20 "hades_raw_out[20]") (joined - (portRef (member hades_raw_out 3) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_20) - )) - (net (rename hades_raw_out_21 "hades_raw_out[21]") (joined - (portRef (member hades_raw_out 2) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_21) - )) - (net (rename hades_raw_out_22 "hades_raw_out[22]") (joined - (portRef (member hades_raw_out 1) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_22) - )) - (net (rename hades_raw_out_23 "hades_raw_out[23]") (joined - (portRef (member hades_raw_out 0) (instanceRef hades_tdc_channel_raw_out_inst)) - (portRef hades_raw_out_23) - )) - (net hades_trig_c_i (joined - (portRef hades_trig_c_i) - (portRef hades_trig_c_i (instanceRef hades_tdc_channel_raw_out_inst)) - )) - (net N_73 (joined - (portRef CIN (instanceRef hit_valid25_0_I_1_0)) - )) - ) - (property COARSE_WIDTH_INTERNAL (integer 9)) - (property HITBUFFER_DEPTH (integer 4)) - (property TDC_WIDTH (integer 3)) - (property COARSE_WIDTH (integer 9)) - (property TRIG_WIDTH (integer 1)) - (property orig_inst_of (string "hades_tdc_bundle")) - ) - ) - (cell pll0 (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename pll_clks "pll_clks[3:0]") 4) (direction OUTPUT)) - (port clk_c (direction INPUT)) - ) - (contents - (instance PLLInst_0 (viewRef verilog (cellRef EHXPLLL)) - (property FREQUENCY_PIN_CLKOS3 (string "300.000000")) - (property FREQUENCY_PIN_CLKOS2 (string "300.000000")) - (property FREQUENCY_PIN_CLKOS (string "300.000000")) - (property FREQUENCY_PIN_CLKOP (string "300.000000")) - (property FREQUENCY_PIN_CLKI (string "100.000000")) - (property ICP_CURRENT (string "9")) - (property LPF_RESISTOR (string "72")) - (property FEEDBK_PATH (string "CLKOP")) - (property CLKI_DIV (integer 1)) - (property CLKFB_DIV (integer 3)) - (property CLKOP_DIV (integer 2)) - (property CLKOS_DIV (integer 2)) - (property CLKOS2_DIV (integer 2)) - (property CLKOS3_DIV (integer 2)) - (property CLKOP_ENABLE (string "ENABLED")) - (property OUTDIVIDER_MUXA (string "DIVA")) - (property CLKOS_ENABLE (string "ENABLED")) - (property OUTDIVIDER_MUXB (string "DIVB")) - (property CLKOS2_ENABLE (string "ENABLED")) - (property OUTDIVIDER_MUXC (string "DIVC")) - (property CLKOS3_ENABLE (string "ENABLED")) - (property OUTDIVIDER_MUXD (string "DIVD")) - (property CLKOP_TRIM_POL (string "FALLING")) - (property CLKOP_TRIM_DELAY (integer 0)) - (property CLKOS_TRIM_POL (string "FALLING")) - (property CLKOS_TRIM_DELAY (integer 0)) - (property PLL_LOCK_MODE (integer 0)) - (property CLKOP_CPHASE (integer 1)) - (property CLKOP_FPHASE (integer 0)) - (property CLKOS_CPHASE (integer 1)) - (property CLKOS_FPHASE (integer 2)) - (property CLKOS2_CPHASE (integer 1)) - (property CLKOS2_FPHASE (integer 4)) - (property CLKOS3_CPHASE (integer 1)) - (property CLKOS3_FPHASE (integer 6)) - (property DPHASE_SOURCE (string "DISABLED")) - (property STDBY_ENABLE (string "DISABLED")) - (property INTFB_WAKE (string "DISABLED")) - (property PLLRST_ENA (string "DISABLED")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (net (rename CLKOS2_inferred_clock "pll_clks[2]") (joined - (portRef (member pll_clks 1)) - (portRef CLKOS2 (instanceRef PLLInst_0)) - )) - (net (rename CLKOS_inferred_clock "pll_clks[1]") (joined - (portRef (member pll_clks 2)) - (portRef CLKOS (instanceRef PLLInst_0)) - )) - (net (rename CLKOP_inferred_clock "pll_clks[0]") (joined - (portRef CLKFB (instanceRef PLLInst_0)) - (portRef (member pll_clks 3)) - (portRef CLKOP (instanceRef PLLInst_0)) - )) - (net (rename CLKOS3_inferred_clock "pll_clks[3]") (joined - (portRef (member pll_clks 0)) - (portRef CLKOS3 (instanceRef PLLInst_0)) - )) - (net clk_c (joined - (portRef clk_c) - (portRef CLKI (instanceRef PLLInst_0)) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef ENCLKOS3 (instanceRef PLLInst_0)) - (portRef ENCLKOS2 (instanceRef PLLInst_0)) - (portRef ENCLKOS (instanceRef PLLInst_0)) - (portRef ENCLKOP (instanceRef PLLInst_0)) - (portRef RST (instanceRef PLLInst_0)) - (portRef PLLWAKESYNC (instanceRef PLLInst_0)) - (portRef STDBY (instanceRef PLLInst_0)) - (portRef PHASELOADREG (instanceRef PLLInst_0)) - (portRef PHASESTEP (instanceRef PLLInst_0)) - (portRef PHASEDIR (instanceRef PLLInst_0)) - (portRef PHASESEL0 (instanceRef PLLInst_0)) - (portRef PHASESEL1 (instanceRef PLLInst_0)) - )) - (net LOCK (joined - (portRef LOCK (instanceRef PLLInst_0)) - )) - (net INTLOCK (joined - (portRef INTLOCK (instanceRef PLLInst_0)) - )) - (net REFCLK (joined - (portRef REFCLK (instanceRef PLLInst_0)) - )) - (net CLKINTFB (joined - (portRef CLKINTFB (instanceRef PLLInst_0)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "pll0")) - ) - ) - (cell top_tf (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port clk (direction INPUT)) - (port rd_clk (direction INPUT)) - (port reset_dc (direction INPUT)) - (port (array (rename trig "trig[2:0]") 3) (direction INPUT)) - (port (array (rename fifo_data_out "fifo_data_out[31:0]") 32) (direction OUTPUT)) - (port fifo_rden (direction OUTPUT)) - (port fifo_empty1 (direction OUTPUT)) - (port LVL1_TRG_DATA_VALID_IN (direction INPUT)) - (port LVL1_INVALID_TRG_IN (direction INPUT)) - (port (array (rename fee_data_out "FEE_DATA_OUT[31:0]") 32) (direction OUTPUT)) - (port FEE_DATA_WRITE_OUT (direction OUTPUT)) - (port FEE_DATAFINISHED_OUT (direction OUTPUT)) - (port FEE_TRG_RELEASE_OUT (direction OUTPUT)) - (port LVL1_TRG_DATA_VALI_IN_rising (direction OUTPUT)) - (port burst (direction OUTPUT)) - (port discard (direction OUTPUT)) - (port last_buf_empty (direction OUTPUT)) - (port finished (direction OUTPUT)) - (port release_out (direction OUTPUT)) - (port hades_trig (direction INPUT)) - (port hades_raw_out_valid (direction OUTPUT)) - (port (array (rename hades_raw_valid_vect "hades_raw_valid_vect[1:0]") 2) (direction OUTPUT)) - (port hades_lvl1 (direction INPUT)) - (port hades_lvl1_invalid (direction INPUT)) - (port (array (rename hades_offset "hades_offset[8:0]") 9) (direction OUTPUT)) - (port hades_offset_valid (direction OUTPUT)) - (port hades_window_end (direction OUTPUT)) - (port hades_buf_out_valid (direction OUTPUT)) - (port hades_buf_release (direction OUTPUT)) - (port hades_buf_finished (direction OUTPUT)) - (port (array (rename hades_hit_out_i "hades_hit_out_i[3:0]") 4) (direction OUTPUT)) - (port (array (rename hades_hit_valid "hades_hit_valid[3:0]") 4) (direction OUTPUT)) - (port hades_discard (direction OUTPUT)) - (port (array (rename hades_invalid_dl "hades_invalid_dl[3:0]") 4) (direction OUTPUT)) - (port (array (rename hades_buf_drop "hades_buf_drop[3:0]") 4) (direction OUTPUT)) - (port (array (rename hades_dbg2_out "hades_dbg2_out[31:0]") 32) (direction OUTPUT)) - (port (array (rename hades_dbg2_coarse "hades_dbg2_coarse[8:0]") 9) (direction OUTPUT)) - (port (array (rename hades_drop_cmp_buf "hades_drop_cmp_buf[11:0]") 12) (direction OUTPUT)) - (port (array (rename hades_drop_cmp_buf_coarse "hades_drop_cmp_buf_coarse[11:0]") 12) (direction OUTPUT)) - (port hades_drop_cmp_buf_valid (direction OUTPUT)) - ) - (contents - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) - ) - (instance (rename reset_dl_RNISCAF_2 "reset_dl_RNISCAF[2]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename trig_pad_RNII4FF_0 "trig_pad_RNII4FF[0]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename trig_pad_RNIJ5FF_1 "trig_pad_RNIJ5FF[1]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename trig_pad_RNIK6FF_2 "trig_pad_RNIK6FF[2]") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance hades_trig_pad_RNIE1B4 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance hades_lvl1_pad_RNINMH5 (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) - (instance (rename trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0 "trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0 "trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename reset_dl_0io_1 "reset_dl_0io[1]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0]") (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance trb_adapter_inst_FEE_TRG_RELEASE_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance trb_adapter_inst_FEE_DATA_WRITE_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance trb_adapter_inst_FEE_DATAFINISHED_OUTio (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance hades_tdc_bundle_inst_referenced_out_validio (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_0 "hades_tdc_bundle_inst_hitbuffer_1_io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_1 "hades_tdc_bundle_inst_hitbuffer_1_io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_2 "hades_tdc_bundle_inst_hitbuffer_1_io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_12 "hades_tdc_bundle_inst_hitbuffer_1_io[12]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_13 "hades_tdc_bundle_inst_hitbuffer_1_io[13]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_14 "hades_tdc_bundle_inst_hitbuffer_1_io[14]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_15 "hades_tdc_bundle_inst_hitbuffer_1_io[15]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_16 "hades_tdc_bundle_inst_hitbuffer_1_io[16]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_17 "hades_tdc_bundle_inst_hitbuffer_1_io[17]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_18 "hades_tdc_bundle_inst_hitbuffer_1_io[18]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_19 "hades_tdc_bundle_inst_hitbuffer_1_io[19]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_20 "hades_tdc_bundle_inst_hitbuffer_1_io[20]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_21 "hades_tdc_bundle_inst_hitbuffer_1_io[21]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_22 "hades_tdc_bundle_inst_hitbuffer_1_io[22]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hitbuffer_1_io_23 "hades_tdc_bundle_inst_hitbuffer_1_io[23]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8 "hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance hades_tdc_bundle_inst_buf_out_validio (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename hades_tdc_bundle_inst_buf_drop_1io_1 "hades_tdc_bundle_inst_buf_drop_1io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) - (property IOB (string "FALSE")) - ) - (instance (rename reset_dl_2 "reset_dl[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance hades_drop_cmp_buf_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_11 "hades_drop_cmp_buf_coarse_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_10 "hades_drop_cmp_buf_coarse_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_9 "hades_drop_cmp_buf_coarse_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_8 "hades_drop_cmp_buf_coarse_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_7 "hades_drop_cmp_buf_coarse_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_6 "hades_drop_cmp_buf_coarse_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_5 "hades_drop_cmp_buf_coarse_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_4 "hades_drop_cmp_buf_coarse_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_3 "hades_drop_cmp_buf_coarse_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_2 "hades_drop_cmp_buf_coarse_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_1 "hades_drop_cmp_buf_coarse_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_coarse_pad_0 "hades_drop_cmp_buf_coarse_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_11 "hades_drop_cmp_buf_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_10 "hades_drop_cmp_buf_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_9 "hades_drop_cmp_buf_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_8 "hades_drop_cmp_buf_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_7 "hades_drop_cmp_buf_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_6 "hades_drop_cmp_buf_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_5 "hades_drop_cmp_buf_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_4 "hades_drop_cmp_buf_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_3 "hades_drop_cmp_buf_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_2 "hades_drop_cmp_buf_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_1 "hades_drop_cmp_buf_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_drop_cmp_buf_pad_0 "hades_drop_cmp_buf_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_8 "hades_dbg2_coarse_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_7 "hades_dbg2_coarse_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_6 "hades_dbg2_coarse_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_5 "hades_dbg2_coarse_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_4 "hades_dbg2_coarse_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_3 "hades_dbg2_coarse_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_2 "hades_dbg2_coarse_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_1 "hades_dbg2_coarse_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_coarse_pad_0 "hades_dbg2_coarse_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_31 "hades_dbg2_out_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_30 "hades_dbg2_out_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_29 "hades_dbg2_out_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_28 "hades_dbg2_out_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_27 "hades_dbg2_out_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_26 "hades_dbg2_out_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_25 "hades_dbg2_out_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_24 "hades_dbg2_out_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_23 "hades_dbg2_out_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_22 "hades_dbg2_out_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_21 "hades_dbg2_out_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_20 "hades_dbg2_out_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_19 "hades_dbg2_out_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_18 "hades_dbg2_out_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_17 "hades_dbg2_out_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_16 "hades_dbg2_out_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_15 "hades_dbg2_out_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_14 "hades_dbg2_out_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_13 "hades_dbg2_out_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_12 "hades_dbg2_out_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_11 "hades_dbg2_out_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_10 "hades_dbg2_out_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_9 "hades_dbg2_out_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_8 "hades_dbg2_out_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_7 "hades_dbg2_out_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_6 "hades_dbg2_out_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_5 "hades_dbg2_out_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_4 "hades_dbg2_out_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_3 "hades_dbg2_out_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_2 "hades_dbg2_out_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_1 "hades_dbg2_out_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_dbg2_out_pad_0 "hades_dbg2_out_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_buf_drop_pad_3 "hades_buf_drop_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_buf_drop_pad_2 "hades_buf_drop_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_buf_drop_pad_1 "hades_buf_drop_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_buf_drop_pad_0 "hades_buf_drop_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_invalid_dl_pad_3 "hades_invalid_dl_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_invalid_dl_pad_2 "hades_invalid_dl_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_invalid_dl_pad_1 "hades_invalid_dl_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_invalid_dl_pad_0 "hades_invalid_dl_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_discard_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_valid_pad_3 "hades_hit_valid_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_valid_pad_2 "hades_hit_valid_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_valid_pad_1 "hades_hit_valid_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_valid_pad_0 "hades_hit_valid_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_out_i_pad_3 "hades_hit_out_i_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_out_i_pad_2 "hades_hit_out_i_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_out_i_pad_1 "hades_hit_out_i_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_hit_out_i_pad_0 "hades_hit_out_i_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_buf_finished_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_buf_release_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_buf_out_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_window_end_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_offset_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_8 "hades_offset_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_7 "hades_offset_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_6 "hades_offset_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_5 "hades_offset_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_4 "hades_offset_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_3 "hades_offset_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_2 "hades_offset_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_1 "hades_offset_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename hades_offset_pad_0 "hades_offset_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_lvl1_invalid_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance hades_lvl1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance (rename hades_raw_valid_vect_pad_1 "hades_raw_valid_vect_pad[1]") (viewRef PRIM (cellRef OBZ (libraryRef LUCENT))) ) - (instance (rename hades_raw_valid_vect_pad_0 "hades_raw_valid_vect_pad[0]") (viewRef PRIM (cellRef OBZ (libraryRef LUCENT))) ) - (instance hades_raw_out_valid_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance hades_trig_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance release_out_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance finished_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance last_buf_empty_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance discard_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance burst_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance LVL1_TRG_DATA_VALI_IN_rising_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance FEE_TRG_RELEASE_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance FEE_DATAFINISHED_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance FEE_DATA_WRITE_OUT_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_31 "FEE_DATA_OUT_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_30 "FEE_DATA_OUT_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_29 "FEE_DATA_OUT_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_28 "FEE_DATA_OUT_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_27 "FEE_DATA_OUT_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_26 "FEE_DATA_OUT_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_25 "FEE_DATA_OUT_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_24 "FEE_DATA_OUT_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_23 "FEE_DATA_OUT_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_22 "FEE_DATA_OUT_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_21 "FEE_DATA_OUT_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_20 "FEE_DATA_OUT_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_19 "FEE_DATA_OUT_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_18 "FEE_DATA_OUT_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_17 "FEE_DATA_OUT_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_16 "FEE_DATA_OUT_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_15 "FEE_DATA_OUT_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_14 "FEE_DATA_OUT_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_13 "FEE_DATA_OUT_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_12 "FEE_DATA_OUT_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_11 "FEE_DATA_OUT_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_10 "FEE_DATA_OUT_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_9 "FEE_DATA_OUT_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_8 "FEE_DATA_OUT_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_7 "FEE_DATA_OUT_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_6 "FEE_DATA_OUT_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_5 "FEE_DATA_OUT_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_4 "FEE_DATA_OUT_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_3 "FEE_DATA_OUT_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_2 "FEE_DATA_OUT_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_1 "FEE_DATA_OUT_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename FEE_DATA_OUT_pad_0 "FEE_DATA_OUT_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance LVL1_INVALID_TRG_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance LVL1_TRG_DATA_VALID_IN_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance fifo_empty1_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance fifo_rden_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_31 "fifo_data_out_pad[31]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_30 "fifo_data_out_pad[30]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_29 "fifo_data_out_pad[29]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_28 "fifo_data_out_pad[28]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_27 "fifo_data_out_pad[27]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_26 "fifo_data_out_pad[26]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_25 "fifo_data_out_pad[25]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_24 "fifo_data_out_pad[24]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_23 "fifo_data_out_pad[23]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_22 "fifo_data_out_pad[22]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_21 "fifo_data_out_pad[21]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_20 "fifo_data_out_pad[20]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_19 "fifo_data_out_pad[19]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_18 "fifo_data_out_pad[18]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_17 "fifo_data_out_pad[17]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_16 "fifo_data_out_pad[16]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_15 "fifo_data_out_pad[15]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_14 "fifo_data_out_pad[14]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_13 "fifo_data_out_pad[13]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_12 "fifo_data_out_pad[12]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_11 "fifo_data_out_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_10 "fifo_data_out_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_9 "fifo_data_out_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_8 "fifo_data_out_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_7 "fifo_data_out_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_6 "fifo_data_out_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_5 "fifo_data_out_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_4 "fifo_data_out_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_3 "fifo_data_out_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_2 "fifo_data_out_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_1 "fifo_data_out_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename fifo_data_out_pad_0 "fifo_data_out_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename trig_pad_2 "trig_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename trig_pad_1 "trig_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename trig_pad_0 "trig_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance reset_dc_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance rd_clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance clk_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance pll0inst (viewRef netlist (cellRef pll0)) - ) - (instance hades_tdc_bundle_inst (viewRef netlist (cellRef hades_tdc_bundle)) - ) - (instance trb_adapter_inst (viewRef netlist (cellRef trb_adapter)) - ) - (instance fifo_colector_inst (viewRef netlist (cellRef fifo_colector)) - ) - (instance (rename genblk1_0__tdc_channel_fifo_out_inst "genblk1[0].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out)) - ) - (instance (rename genblk1_1__tdc_channel_fifo_out_inst "genblk1[1].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out_2)) - ) - (instance (rename genblk1_2__tdc_channel_fifo_out_inst "genblk1[2].tdc_channel_fifo_out_inst") (viewRef netlist (cellRef tdc_channel_fifo_out_3)) - ) - (net (rename pll_clks_0 "pll_clks[0]") (joined - (portRef (member pll_clks 3) (instanceRef pll0inst)) - (portRef (member pll_clks 3) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 3) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 3) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 3) (instanceRef hades_tdc_bundle_inst)) - )) - (net (rename pll_clks_1 "pll_clks[1]") (joined - (portRef (member pll_clks 2) (instanceRef pll0inst)) - (portRef (member pll_clks 2) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 2) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 2) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 2) (instanceRef hades_tdc_bundle_inst)) - )) - (net (rename pll_clks_2 "pll_clks[2]") (joined - (portRef (member pll_clks 1) (instanceRef pll0inst)) - (portRef (member pll_clks 1) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 1) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 1) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 1) (instanceRef hades_tdc_bundle_inst)) - )) - (net (rename pll_clks_3 "pll_clks[3]") (joined - (portRef (member pll_clks 0) (instanceRef pll0inst)) - (portRef (member pll_clks 0) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 0) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member pll_clks 0) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef pll_clks_0 (instanceRef fifo_colector_inst)) - (portRef (member pll_clks 0) (instanceRef hades_tdc_bundle_inst)) - (portRef CK (instanceRef reset_dl_2)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_buf_out_validio)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_referenced_out_validio)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0)) - (portRef SCLK (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0)) - (portRef SCLK (instanceRef reset_dl_0io_1)) - )) - (net (rename reset_dl_2 "reset_dl[2]") (joined - (portRef Q (instanceRef reset_dl_2)) - (portRef reset_dl_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef reset_dl_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef reset_dl_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef reset_dl_0 (instanceRef hades_tdc_bundle_inst)) - (portRef CD (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1)) - (portRef CD (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio)) - (portRef CD (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio)) - (portRef CD (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio)) - (portRef A (instanceRef reset_dl_RNISCAF_2)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_0 "genblk1[0].un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_1 "genblk1[0].un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_2 "genblk1[0].un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_3 "genblk1[0].un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_4 "genblk1[0].un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_5 "genblk1[0].un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_6 "genblk1[0].un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_7 "genblk1[0].un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 16) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_8 "genblk1[0].un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 15) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_9 "genblk1[0].un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 14) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_10 "genblk1[0].un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 13) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_11 "genblk1[0].un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 12) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_12 "genblk1[0].un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 11) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_13 "genblk1[0].un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 10) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_14 "genblk1[0].un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 9) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_15 "genblk1[0].un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_16 "genblk1[0].un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 7) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_17 "genblk1[0].un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 6) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_18 "genblk1[0].un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 5) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_19 "genblk1[0].un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 4) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_20 "genblk1[0].un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 3) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_21 "genblk1[0].un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 2) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_22 "genblk1[0].un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 1) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_0__un1_tdc_channel_fifo_out_inst_23 "genblk1[0].un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 0) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_0 "genblk1[1].un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 23) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_1 "genblk1[1].un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 22) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_2 "genblk1[1].un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 21) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_3 "genblk1[1].un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 20) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_4 "genblk1[1].un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 19) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_5 "genblk1[1].un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 18) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_6 "genblk1[1].un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 17) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_7 "genblk1[1].un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 16) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_8 "genblk1[1].un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_9 "genblk1[1].un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_10 "genblk1[1].un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_11 "genblk1[1].un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_12 "genblk1[1].un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_13 "genblk1[1].un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_14 "genblk1[1].un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_15 "genblk1[1].un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 8) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_16 "genblk1[1].un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 7) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_17 "genblk1[1].un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 6) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_18 "genblk1[1].un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 5) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_19 "genblk1[1].un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 4) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_20 "genblk1[1].un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 3) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_21 "genblk1[1].un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 2) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_22 "genblk1[1].un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 1) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_1__un1_tdc_channel_fifo_out_inst_23 "genblk1[1].un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 0) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_0 "genblk1[2].un1_tdc_channel_fifo_out_inst[0]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 23) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 23) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_1 "genblk1[2].un1_tdc_channel_fifo_out_inst[1]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 22) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 22) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_2 "genblk1[2].un1_tdc_channel_fifo_out_inst[2]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 21) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 21) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_3 "genblk1[2].un1_tdc_channel_fifo_out_inst[3]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 20) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 20) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_4 "genblk1[2].un1_tdc_channel_fifo_out_inst[4]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 19) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 19) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_5 "genblk1[2].un1_tdc_channel_fifo_out_inst[5]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 18) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 18) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_6 "genblk1[2].un1_tdc_channel_fifo_out_inst[6]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 17) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 17) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_7 "genblk1[2].un1_tdc_channel_fifo_out_inst[7]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 16) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_8 "genblk1[2].un1_tdc_channel_fifo_out_inst[8]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 15) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 15) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_9 "genblk1[2].un1_tdc_channel_fifo_out_inst[9]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 14) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 14) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_10 "genblk1[2].un1_tdc_channel_fifo_out_inst[10]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 13) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 13) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_11 "genblk1[2].un1_tdc_channel_fifo_out_inst[11]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 12) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 12) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_12 "genblk1[2].un1_tdc_channel_fifo_out_inst[12]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 11) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 11) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_13 "genblk1[2].un1_tdc_channel_fifo_out_inst[13]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 10) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 10) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_14 "genblk1[2].un1_tdc_channel_fifo_out_inst[14]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 9) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_1 9) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_15 "genblk1[2].un1_tdc_channel_fifo_out_inst[15]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 8) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst_0 8) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_16 "genblk1[2].un1_tdc_channel_fifo_out_inst[16]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 7) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_17 "genblk1[2].un1_tdc_channel_fifo_out_inst[17]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 6) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_18 "genblk1[2].un1_tdc_channel_fifo_out_inst[18]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 5) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_19 "genblk1[2].un1_tdc_channel_fifo_out_inst[19]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 4) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_20 "genblk1[2].un1_tdc_channel_fifo_out_inst[20]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 3) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_21 "genblk1[2].un1_tdc_channel_fifo_out_inst[21]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 2) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_22 "genblk1[2].un1_tdc_channel_fifo_out_inst[22]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 1) (instanceRef fifo_colector_inst)) - )) - (net (rename genblk1_2__un1_tdc_channel_fifo_out_inst_23 "genblk1[2].un1_tdc_channel_fifo_out_inst[23]") (joined - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member un1_tdc_channel_fifo_out_inst 0) (instanceRef fifo_colector_inst)) - )) - (net (rename fifo_empty_1 "fifo_empty[1]") (joined - (portRef fifo_empty_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef (member fifo_empty 1) (instanceRef fifo_colector_inst)) - )) - (net (rename fifo_empty_2 "fifo_empty[2]") (joined - (portRef fifo_empty_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef (member fifo_empty 0) (instanceRef fifo_colector_inst)) - )) - (net (rename fifo_read_0 "fifo_read[0]") (joined - (portRef (member fifo_read 2) (instanceRef fifo_colector_inst)) - (portRef fifo_read_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net (rename fifo_read_1 "fifo_read[1]") (joined - (portRef (member fifo_read 1) (instanceRef fifo_colector_inst)) - (portRef fifo_read_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - )) - (net (rename fifo_read_2 "fifo_read[2]") (joined - (portRef (member fifo_read 0) (instanceRef fifo_colector_inst)) - (portRef fifo_read_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - )) - (net (rename reset_dl_1 "reset_dl[1]") (joined - (portRef Q (instanceRef reset_dl_0io_1)) - (portRef D (instanceRef reset_dl_2)) - )) - (net (rename trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dl_0 "trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0]") (joined - (portRef Q (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0)) - (portRef LVL1_TRG_DATA_VALID_IN_dl_0 (instanceRef trb_adapter_inst)) - )) - (net (rename trb_adapter_inst_LVL1_INVALID_TRG_IN_dl_0 "trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0]") (joined - (portRef Q (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0)) - (portRef LVL1_INVALID_TRG_IN_dl_0 (instanceRef trb_adapter_inst)) - )) - (net un1_hit_i_2_0_a2 (joined - (portRef un1_hit_i_2_0_a2_1z (instanceRef hades_tdc_bundle_inst)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_0 "hades_tdc_bundle_inst.hades_raw_out[0]") (joined - (portRef hades_raw_out_0 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_1 "hades_tdc_bundle_inst.hades_raw_out[1]") (joined - (portRef hades_raw_out_1 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_2 "hades_tdc_bundle_inst.hades_raw_out[2]") (joined - (portRef hades_raw_out_2 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_12 "hades_tdc_bundle_inst.hades_raw_out[12]") (joined - (portRef hades_raw_out_12 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_13 "hades_tdc_bundle_inst.hades_raw_out[13]") (joined - (portRef hades_raw_out_13 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_14 "hades_tdc_bundle_inst.hades_raw_out[14]") (joined - (portRef hades_raw_out_14 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_15 "hades_tdc_bundle_inst.hades_raw_out[15]") (joined - (portRef hades_raw_out_15 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_16 "hades_tdc_bundle_inst.hades_raw_out[16]") (joined - (portRef hades_raw_out_16 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_17 "hades_tdc_bundle_inst.hades_raw_out[17]") (joined - (portRef hades_raw_out_17 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_18 "hades_tdc_bundle_inst.hades_raw_out[18]") (joined - (portRef hades_raw_out_18 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_19 "hades_tdc_bundle_inst.hades_raw_out[19]") (joined - (portRef hades_raw_out_19 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_20 "hades_tdc_bundle_inst.hades_raw_out[20]") (joined - (portRef hades_raw_out_20 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_21 "hades_tdc_bundle_inst.hades_raw_out[21]") (joined - (portRef hades_raw_out_21 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_22 "hades_tdc_bundle_inst.hades_raw_out[22]") (joined - (portRef hades_raw_out_22 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22)) - )) - (net (rename hades_tdc_bundle_inst_hades_raw_out_23 "hades_tdc_bundle_inst.hades_raw_out[23]") (joined - (portRef hades_raw_out_23 (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23)) - )) - (net (rename hades_tdc_bundle_inst_drop_cmp_buf_valid_0_sqmuxa "hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa") (joined - (portRef drop_cmp_buf_valid_0_sqmuxa (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1)) - )) - (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0]") (joined - (portRef (member offset_5 2) (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0)) - )) - (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_1 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1]") (joined - (portRef (member offset_5 1) (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1)) - )) - (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_5_2 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2]") (joined - (portRef (member offset_5 0) (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2)) - )) - (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dl_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0)) - (portRef trig_dl_0 (instanceRef hades_tdc_bundle_inst)) - )) - (net (rename hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offset_1_sqmuxa_i_0 "hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0") (joined - (portRef offset_1_sqmuxa_i_0 (instanceRef hades_tdc_bundle_inst)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0)) - )) - (net ANB0 (joined - (portRef ANB0 (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_out_i_pad_0)) - )) - (net ANB1 (joined - (portRef ANB1 (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_out_i_pad_1)) - )) - (net ANB2 (joined - (portRef ANB2 (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_out_i_pad_2)) - )) - (net ANB3 (joined - (portRef ANB3 (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_out_i_pad_3)) - )) - (net (rename hades_tdc_bundle_inst_buf_out12 "hades_tdc_bundle_inst.buf_out12") (joined - (portRef buf_out12_1z (instanceRef hades_tdc_bundle_inst)) - (portRef D (instanceRef hades_tdc_bundle_inst_buf_out_validio)) - )) - (net valid_fast_RNI999V (joined - (portRef valid_fast_RNI999V (instanceRef hades_tdc_bundle_inst)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0)) - )) - (net N_248_i (joined - (portRef N_248_i (instanceRef hades_tdc_bundle_inst)) - (portRef SP (instanceRef hades_tdc_bundle_inst_buf_out_validio)) - )) - (net (rename genblk1_0__tdc_channel_fifo_out_inst_fifo_wren_CN "genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN") (joined - (portRef CN_2 (instanceRef hades_tdc_bundle_inst)) - (portRef CN (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef CN (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef CN (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_0__out_buffered_4__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_.CN") (joined - (portRef CN_1 (instanceRef hades_tdc_bundle_inst)) - (portRef CN_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef CN_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef CN_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_1__out_buffered_5__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_.CN") (joined - (portRef CN_0 (instanceRef hades_tdc_bundle_inst)) - (portRef CN_1 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef CN_1 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef CN_1 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net (rename genblk1_0__tdc_channel_fifo_out_inst_tdc_inst_genblk1_2__out_buffered_6__CN "genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_.CN") (joined - (portRef CN (instanceRef hades_tdc_bundle_inst)) - (portRef CN_2 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - (portRef CN_2 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - (portRef CN_2 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef T (instanceRef hades_raw_valid_vect_pad_0)) - (portRef T (instanceRef hades_raw_valid_vect_pad_1)) - (portRef SP (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1)) - (portRef SP (instanceRef hades_tdc_bundle_inst_referenced_out_validio)) - (portRef SP (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio)) - (portRef SP (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio)) - (portRef SP (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0)) - (portRef SP (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0)) - (portRef SP (instanceRef reset_dl_0io_1)) - (portRef SP (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0)) - (portRef SP (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0)) - (portRef GSR (instanceRef GSR_INST)) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef I (instanceRef hades_raw_valid_vect_pad_0)) - (portRef I (instanceRef hades_raw_valid_vect_pad_1)) - (portRef I (instanceRef hades_buf_drop_pad_0)) - (portRef I (instanceRef hades_buf_drop_pad_2)) - (portRef I (instanceRef hades_buf_drop_pad_3)) - (portRef I (instanceRef hades_dbg2_out_pad_3)) - (portRef I (instanceRef hades_dbg2_out_pad_13)) - (portRef I (instanceRef hades_dbg2_out_pad_14)) - (portRef I (instanceRef hades_dbg2_out_pad_15)) - (portRef I (instanceRef hades_dbg2_out_pad_19)) - (portRef I (instanceRef hades_dbg2_out_pad_29)) - (portRef I (instanceRef hades_dbg2_out_pad_30)) - (portRef I (instanceRef hades_dbg2_out_pad_31)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_9)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_10)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_11)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_10)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_11)) - (portRef CD (instanceRef hades_tdc_bundle_inst_buf_out_validio)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0)) - (portRef CD (instanceRef hades_tdc_bundle_inst_referenced_out_validio)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0)) - (portRef CD (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0)) - (portRef CD (instanceRef reset_dl_0io_1)) - (portRef CD (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0)) - (portRef CD (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0)) - )) - (net clk_c (joined - (portRef O (instanceRef clk_pad)) - (portRef clk_c (instanceRef pll0inst)) - )) - (net clk (joined - (portRef clk) - (portRef I (instanceRef clk_pad)) - )) - (net rd_clk_c (joined - (portRef O (instanceRef rd_clk_pad)) - (portRef rd_clk_c (instanceRef fifo_colector_inst)) - (portRef rd_clk_c (instanceRef trb_adapter_inst)) - (portRef SCLK (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio)) - (portRef SCLK (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio)) - (portRef SCLK (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio)) - (portRef SCLK (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0)) - (portRef SCLK (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0)) - )) - (net rd_clk (joined - (portRef rd_clk) - (portRef I (instanceRef rd_clk_pad)) - )) - (net reset_dc_c (joined - (portRef O (instanceRef reset_dc_pad)) - (portRef D (instanceRef reset_dl_0io_1)) - )) - (net reset_dc (joined - (portRef reset_dc) - (portRef I (instanceRef reset_dc_pad)) - )) - (net (rename trig_c_0 "trig_c[0]") (joined - (portRef O (instanceRef trig_pad_0)) - (portRef A (instanceRef trig_pad_RNII4FF_0)) - )) - (net (rename trig_0 "trig[0]") (joined - (portRef (member trig 2)) - (portRef I (instanceRef trig_pad_0)) - )) - (net (rename trig_c_1 "trig_c[1]") (joined - (portRef O (instanceRef trig_pad_1)) - (portRef A (instanceRef trig_pad_RNIJ5FF_1)) - )) - (net (rename trig_1 "trig[1]") (joined - (portRef (member trig 1)) - (portRef I (instanceRef trig_pad_1)) - )) - (net (rename trig_c_2 "trig_c[2]") (joined - (portRef O (instanceRef trig_pad_2)) - (portRef A (instanceRef trig_pad_RNIK6FF_2)) - )) - (net (rename trig_2 "trig[2]") (joined - (portRef (member trig 0)) - (portRef I (instanceRef trig_pad_2)) - )) - (net (rename fifo_data_out_0 "fifo_data_out[0]") (joined - (portRef O (instanceRef fifo_data_out_pad_0)) - (portRef (member fifo_data_out 31)) - )) - (net (rename fifo_data_out_1 "fifo_data_out[1]") (joined - (portRef O (instanceRef fifo_data_out_pad_1)) - (portRef (member fifo_data_out 30)) - )) - (net (rename fifo_data_out_2 "fifo_data_out[2]") (joined - (portRef O (instanceRef fifo_data_out_pad_2)) - (portRef (member fifo_data_out 29)) - )) - (net (rename fifo_data_out_3 "fifo_data_out[3]") (joined - (portRef O (instanceRef fifo_data_out_pad_3)) - (portRef (member fifo_data_out 28)) - )) - (net (rename fifo_data_out_4 "fifo_data_out[4]") (joined - (portRef O (instanceRef fifo_data_out_pad_4)) - (portRef (member fifo_data_out 27)) - )) - (net (rename fifo_data_out_5 "fifo_data_out[5]") (joined - (portRef O (instanceRef fifo_data_out_pad_5)) - (portRef (member fifo_data_out 26)) - )) - (net (rename fifo_data_out_6 "fifo_data_out[6]") (joined - (portRef O (instanceRef fifo_data_out_pad_6)) - (portRef (member fifo_data_out 25)) - )) - (net (rename fifo_data_out_7 "fifo_data_out[7]") (joined - (portRef O (instanceRef fifo_data_out_pad_7)) - (portRef (member fifo_data_out 24)) - )) - (net (rename fifo_data_out_8 "fifo_data_out[8]") (joined - (portRef O (instanceRef fifo_data_out_pad_8)) - (portRef (member fifo_data_out 23)) - )) - (net (rename fifo_data_out_9 "fifo_data_out[9]") (joined - (portRef O (instanceRef fifo_data_out_pad_9)) - (portRef (member fifo_data_out 22)) - )) - (net (rename fifo_data_out_10 "fifo_data_out[10]") (joined - (portRef O (instanceRef fifo_data_out_pad_10)) - (portRef (member fifo_data_out 21)) - )) - (net (rename fifo_data_out_11 "fifo_data_out[11]") (joined - (portRef O (instanceRef fifo_data_out_pad_11)) - (portRef (member fifo_data_out 20)) - )) - (net (rename fifo_data_out_12 "fifo_data_out[12]") (joined - (portRef O (instanceRef fifo_data_out_pad_12)) - (portRef (member fifo_data_out 19)) - )) - (net (rename fifo_data_out_13 "fifo_data_out[13]") (joined - (portRef O (instanceRef fifo_data_out_pad_13)) - (portRef (member fifo_data_out 18)) - )) - (net (rename fifo_data_out_14 "fifo_data_out[14]") (joined - (portRef O (instanceRef fifo_data_out_pad_14)) - (portRef (member fifo_data_out 17)) - )) - (net (rename fifo_data_out_15 "fifo_data_out[15]") (joined - (portRef O (instanceRef fifo_data_out_pad_15)) - (portRef (member fifo_data_out 16)) - )) - (net (rename fifo_data_out_16 "fifo_data_out[16]") (joined - (portRef O (instanceRef fifo_data_out_pad_16)) - (portRef (member fifo_data_out 15)) - )) - (net (rename fifo_data_out_17 "fifo_data_out[17]") (joined - (portRef O (instanceRef fifo_data_out_pad_17)) - (portRef (member fifo_data_out 14)) - )) - (net (rename fifo_data_out_18 "fifo_data_out[18]") (joined - (portRef O (instanceRef fifo_data_out_pad_18)) - (portRef (member fifo_data_out 13)) - )) - (net (rename fifo_data_out_19 "fifo_data_out[19]") (joined - (portRef O (instanceRef fifo_data_out_pad_19)) - (portRef (member fifo_data_out 12)) - )) - (net (rename fifo_data_out_20 "fifo_data_out[20]") (joined - (portRef O (instanceRef fifo_data_out_pad_20)) - (portRef (member fifo_data_out 11)) - )) - (net (rename fifo_data_out_21 "fifo_data_out[21]") (joined - (portRef O (instanceRef fifo_data_out_pad_21)) - (portRef (member fifo_data_out 10)) - )) - (net (rename fifo_data_out_22 "fifo_data_out[22]") (joined - (portRef O (instanceRef fifo_data_out_pad_22)) - (portRef (member fifo_data_out 9)) - )) - (net (rename fifo_data_out_23 "fifo_data_out[23]") (joined - (portRef O (instanceRef fifo_data_out_pad_23)) - (portRef (member fifo_data_out 8)) - )) - (net (rename fifo_data_out_24 "fifo_data_out[24]") (joined - (portRef O (instanceRef fifo_data_out_pad_24)) - (portRef (member fifo_data_out 7)) - )) - (net (rename fifo_data_out_25 "fifo_data_out[25]") (joined - (portRef O (instanceRef fifo_data_out_pad_25)) - (portRef (member fifo_data_out 6)) - )) - (net (rename fifo_data_out_26 "fifo_data_out[26]") (joined - (portRef O (instanceRef fifo_data_out_pad_26)) - (portRef (member fifo_data_out 5)) - )) - (net (rename fifo_data_out_27 "fifo_data_out[27]") (joined - (portRef O (instanceRef fifo_data_out_pad_27)) - (portRef (member fifo_data_out 4)) - )) - (net (rename fifo_data_out_28 "fifo_data_out[28]") (joined - (portRef O (instanceRef fifo_data_out_pad_28)) - (portRef (member fifo_data_out 3)) - )) - (net (rename fifo_data_out_29 "fifo_data_out[29]") (joined - (portRef O (instanceRef fifo_data_out_pad_29)) - (portRef (member fifo_data_out 2)) - )) - (net (rename fifo_data_out_30 "fifo_data_out[30]") (joined - (portRef O (instanceRef fifo_data_out_pad_30)) - (portRef (member fifo_data_out 1)) - )) - (net (rename fifo_data_out_31 "fifo_data_out[31]") (joined - (portRef O (instanceRef fifo_data_out_pad_31)) - (portRef (member fifo_data_out 0)) - )) - (net fifo_rden_c (joined - (portRef fifo_rden_c (instanceRef trb_adapter_inst)) - (portRef fifo_rden_c (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_rden_pad)) - (portRef D (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio)) - )) - (net fifo_rden (joined - (portRef O (instanceRef fifo_rden_pad)) - (portRef fifo_rden) - )) - (net fifo_empty1_c (joined - (portRef fifo_empty1_c (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - (portRef fifo_empty1_c (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_empty1_pad)) - )) - (net fifo_empty1 (joined - (portRef O (instanceRef fifo_empty1_pad)) - (portRef fifo_empty1) - )) - (net LVL1_TRG_DATA_VALID_IN_c (joined - (portRef O (instanceRef LVL1_TRG_DATA_VALID_IN_pad)) - (portRef D (instanceRef trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio_0)) - )) - (net LVL1_TRG_DATA_VALID_IN (joined - (portRef LVL1_TRG_DATA_VALID_IN) - (portRef I (instanceRef LVL1_TRG_DATA_VALID_IN_pad)) - )) - (net LVL1_INVALID_TRG_IN_c (joined - (portRef O (instanceRef LVL1_INVALID_TRG_IN_pad)) - (portRef D (instanceRef trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio_0)) - )) - (net LVL1_INVALID_TRG_IN (joined - (portRef LVL1_INVALID_TRG_IN) - (portRef I (instanceRef LVL1_INVALID_TRG_IN_pad)) - )) - (net (rename FEE_DATA_OUT_c_0 "FEE_DATA_OUT_c[0]") (joined - (portRef (member fee_data_out_c 31) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_0)) - (portRef I (instanceRef FEE_DATA_OUT_pad_0)) - )) - (net (rename FEE_DATA_OUT_0 "FEE_DATA_OUT[0]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_0)) - (portRef (member fee_data_out 31)) - )) - (net (rename FEE_DATA_OUT_c_1 "FEE_DATA_OUT_c[1]") (joined - (portRef (member fee_data_out_c 30) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_1)) - (portRef I (instanceRef FEE_DATA_OUT_pad_1)) - )) - (net (rename FEE_DATA_OUT_1 "FEE_DATA_OUT[1]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_1)) - (portRef (member fee_data_out 30)) - )) - (net (rename FEE_DATA_OUT_c_2 "FEE_DATA_OUT_c[2]") (joined - (portRef (member fee_data_out_c 29) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_2)) - (portRef I (instanceRef FEE_DATA_OUT_pad_2)) - )) - (net (rename FEE_DATA_OUT_2 "FEE_DATA_OUT[2]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_2)) - (portRef (member fee_data_out 29)) - )) - (net (rename FEE_DATA_OUT_c_3 "FEE_DATA_OUT_c[3]") (joined - (portRef (member fee_data_out_c 28) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_3)) - (portRef I (instanceRef FEE_DATA_OUT_pad_3)) - )) - (net (rename FEE_DATA_OUT_3 "FEE_DATA_OUT[3]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_3)) - (portRef (member fee_data_out 28)) - )) - (net (rename FEE_DATA_OUT_c_4 "FEE_DATA_OUT_c[4]") (joined - (portRef (member fee_data_out_c 27) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_4)) - (portRef I (instanceRef FEE_DATA_OUT_pad_4)) - )) - (net (rename FEE_DATA_OUT_4 "FEE_DATA_OUT[4]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_4)) - (portRef (member fee_data_out 27)) - )) - (net (rename FEE_DATA_OUT_c_5 "FEE_DATA_OUT_c[5]") (joined - (portRef (member fee_data_out_c 26) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_5)) - (portRef I (instanceRef FEE_DATA_OUT_pad_5)) - )) - (net (rename FEE_DATA_OUT_5 "FEE_DATA_OUT[5]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_5)) - (portRef (member fee_data_out 26)) - )) - (net (rename FEE_DATA_OUT_c_6 "FEE_DATA_OUT_c[6]") (joined - (portRef (member fee_data_out_c 25) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_6)) - (portRef I (instanceRef FEE_DATA_OUT_pad_6)) - )) - (net (rename FEE_DATA_OUT_6 "FEE_DATA_OUT[6]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_6)) - (portRef (member fee_data_out 25)) - )) - (net (rename FEE_DATA_OUT_c_7 "FEE_DATA_OUT_c[7]") (joined - (portRef (member fee_data_out_c 24) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_7)) - (portRef I (instanceRef FEE_DATA_OUT_pad_7)) - )) - (net (rename FEE_DATA_OUT_7 "FEE_DATA_OUT[7]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_7)) - (portRef (member fee_data_out 24)) - )) - (net (rename FEE_DATA_OUT_c_8 "FEE_DATA_OUT_c[8]") (joined - (portRef (member fee_data_out_c 23) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_8)) - (portRef I (instanceRef FEE_DATA_OUT_pad_8)) - )) - (net (rename FEE_DATA_OUT_8 "FEE_DATA_OUT[8]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_8)) - (portRef (member fee_data_out 23)) - )) - (net (rename FEE_DATA_OUT_c_9 "FEE_DATA_OUT_c[9]") (joined - (portRef (member fee_data_out_c 22) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_9)) - (portRef I (instanceRef FEE_DATA_OUT_pad_9)) - )) - (net (rename FEE_DATA_OUT_9 "FEE_DATA_OUT[9]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_9)) - (portRef (member fee_data_out 22)) - )) - (net (rename FEE_DATA_OUT_c_10 "FEE_DATA_OUT_c[10]") (joined - (portRef (member fee_data_out_c 21) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_10)) - (portRef I (instanceRef FEE_DATA_OUT_pad_10)) - )) - (net (rename FEE_DATA_OUT_10 "FEE_DATA_OUT[10]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_10)) - (portRef (member fee_data_out 21)) - )) - (net (rename FEE_DATA_OUT_c_11 "FEE_DATA_OUT_c[11]") (joined - (portRef (member fee_data_out_c 20) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_11)) - (portRef I (instanceRef FEE_DATA_OUT_pad_11)) - )) - (net (rename FEE_DATA_OUT_11 "FEE_DATA_OUT[11]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_11)) - (portRef (member fee_data_out 20)) - )) - (net (rename FEE_DATA_OUT_c_12 "FEE_DATA_OUT_c[12]") (joined - (portRef (member fee_data_out_c 19) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_12)) - (portRef I (instanceRef FEE_DATA_OUT_pad_12)) - )) - (net (rename FEE_DATA_OUT_12 "FEE_DATA_OUT[12]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_12)) - (portRef (member fee_data_out 19)) - )) - (net (rename FEE_DATA_OUT_c_13 "FEE_DATA_OUT_c[13]") (joined - (portRef (member fee_data_out_c 18) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_13)) - (portRef I (instanceRef FEE_DATA_OUT_pad_13)) - )) - (net (rename FEE_DATA_OUT_13 "FEE_DATA_OUT[13]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_13)) - (portRef (member fee_data_out 18)) - )) - (net (rename FEE_DATA_OUT_c_14 "FEE_DATA_OUT_c[14]") (joined - (portRef (member fee_data_out_c 17) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_14)) - (portRef I (instanceRef FEE_DATA_OUT_pad_14)) - )) - (net (rename FEE_DATA_OUT_14 "FEE_DATA_OUT[14]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_14)) - (portRef (member fee_data_out 17)) - )) - (net (rename FEE_DATA_OUT_c_15 "FEE_DATA_OUT_c[15]") (joined - (portRef (member fee_data_out_c 16) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_15)) - (portRef I (instanceRef FEE_DATA_OUT_pad_15)) - )) - (net (rename FEE_DATA_OUT_15 "FEE_DATA_OUT[15]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_15)) - (portRef (member fee_data_out 16)) - )) - (net (rename FEE_DATA_OUT_c_16 "FEE_DATA_OUT_c[16]") (joined - (portRef (member fee_data_out_c 15) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_16)) - (portRef I (instanceRef FEE_DATA_OUT_pad_16)) - )) - (net (rename FEE_DATA_OUT_16 "FEE_DATA_OUT[16]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_16)) - (portRef (member fee_data_out 15)) - )) - (net (rename FEE_DATA_OUT_c_17 "FEE_DATA_OUT_c[17]") (joined - (portRef (member fee_data_out_c 14) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_17)) - (portRef I (instanceRef FEE_DATA_OUT_pad_17)) - )) - (net (rename FEE_DATA_OUT_17 "FEE_DATA_OUT[17]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_17)) - (portRef (member fee_data_out 14)) - )) - (net (rename FEE_DATA_OUT_c_18 "FEE_DATA_OUT_c[18]") (joined - (portRef (member fee_data_out_c 13) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_18)) - (portRef I (instanceRef FEE_DATA_OUT_pad_18)) - )) - (net (rename FEE_DATA_OUT_18 "FEE_DATA_OUT[18]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_18)) - (portRef (member fee_data_out 13)) - )) - (net (rename FEE_DATA_OUT_c_19 "FEE_DATA_OUT_c[19]") (joined - (portRef (member fee_data_out_c 12) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_19)) - (portRef I (instanceRef FEE_DATA_OUT_pad_19)) - )) - (net (rename FEE_DATA_OUT_19 "FEE_DATA_OUT[19]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_19)) - (portRef (member fee_data_out 12)) - )) - (net (rename FEE_DATA_OUT_c_20 "FEE_DATA_OUT_c[20]") (joined - (portRef (member fee_data_out_c 11) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_20)) - (portRef I (instanceRef FEE_DATA_OUT_pad_20)) - )) - (net (rename FEE_DATA_OUT_20 "FEE_DATA_OUT[20]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_20)) - (portRef (member fee_data_out 11)) - )) - (net (rename FEE_DATA_OUT_c_21 "FEE_DATA_OUT_c[21]") (joined - (portRef (member fee_data_out_c 10) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_21)) - (portRef I (instanceRef FEE_DATA_OUT_pad_21)) - )) - (net (rename FEE_DATA_OUT_21 "FEE_DATA_OUT[21]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_21)) - (portRef (member fee_data_out 10)) - )) - (net (rename FEE_DATA_OUT_c_22 "FEE_DATA_OUT_c[22]") (joined - (portRef (member fee_data_out_c 9) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_22)) - (portRef I (instanceRef FEE_DATA_OUT_pad_22)) - )) - (net (rename FEE_DATA_OUT_22 "FEE_DATA_OUT[22]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_22)) - (portRef (member fee_data_out 9)) - )) - (net (rename FEE_DATA_OUT_c_23 "FEE_DATA_OUT_c[23]") (joined - (portRef (member fee_data_out_c 8) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_23)) - (portRef I (instanceRef FEE_DATA_OUT_pad_23)) - )) - (net (rename FEE_DATA_OUT_23 "FEE_DATA_OUT[23]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_23)) - (portRef (member fee_data_out 8)) - )) - (net (rename FEE_DATA_OUT_c_24 "FEE_DATA_OUT_c[24]") (joined - (portRef (member fee_data_out_c 7) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_24)) - (portRef I (instanceRef FEE_DATA_OUT_pad_24)) - )) - (net (rename FEE_DATA_OUT_24 "FEE_DATA_OUT[24]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_24)) - (portRef (member fee_data_out 7)) - )) - (net (rename FEE_DATA_OUT_c_25 "FEE_DATA_OUT_c[25]") (joined - (portRef (member fee_data_out_c 6) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_25)) - (portRef I (instanceRef FEE_DATA_OUT_pad_25)) - )) - (net (rename FEE_DATA_OUT_25 "FEE_DATA_OUT[25]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_25)) - (portRef (member fee_data_out 6)) - )) - (net (rename FEE_DATA_OUT_c_26 "FEE_DATA_OUT_c[26]") (joined - (portRef (member fee_data_out_c 5) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_26)) - (portRef I (instanceRef FEE_DATA_OUT_pad_26)) - )) - (net (rename FEE_DATA_OUT_26 "FEE_DATA_OUT[26]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_26)) - (portRef (member fee_data_out 5)) - )) - (net (rename FEE_DATA_OUT_c_27 "FEE_DATA_OUT_c[27]") (joined - (portRef (member fee_data_out_c 4) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_27)) - (portRef I (instanceRef FEE_DATA_OUT_pad_27)) - )) - (net (rename FEE_DATA_OUT_27 "FEE_DATA_OUT[27]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_27)) - (portRef (member fee_data_out 4)) - )) - (net (rename FEE_DATA_OUT_c_28 "FEE_DATA_OUT_c[28]") (joined - (portRef (member fee_data_out_c 3) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_28)) - (portRef I (instanceRef FEE_DATA_OUT_pad_28)) - )) - (net (rename FEE_DATA_OUT_28 "FEE_DATA_OUT[28]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_28)) - (portRef (member fee_data_out 3)) - )) - (net (rename FEE_DATA_OUT_c_29 "FEE_DATA_OUT_c[29]") (joined - (portRef (member fee_data_out_c 2) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_29)) - (portRef I (instanceRef FEE_DATA_OUT_pad_29)) - )) - (net (rename FEE_DATA_OUT_29 "FEE_DATA_OUT[29]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_29)) - (portRef (member fee_data_out 2)) - )) - (net (rename FEE_DATA_OUT_c_30 "FEE_DATA_OUT_c[30]") (joined - (portRef (member fee_data_out_c 1) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_30)) - (portRef I (instanceRef FEE_DATA_OUT_pad_30)) - )) - (net (rename FEE_DATA_OUT_30 "FEE_DATA_OUT[30]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_30)) - (portRef (member fee_data_out 1)) - )) - (net (rename FEE_DATA_OUT_c_31 "FEE_DATA_OUT_c[31]") (joined - (portRef (member fee_data_out_c 0) (instanceRef fifo_colector_inst)) - (portRef I (instanceRef fifo_data_out_pad_31)) - (portRef I (instanceRef FEE_DATA_OUT_pad_31)) - )) - (net (rename FEE_DATA_OUT_31 "FEE_DATA_OUT[31]") (joined - (portRef O (instanceRef FEE_DATA_OUT_pad_31)) - (portRef (member fee_data_out 0)) - )) - (net FEE_DATA_WRITE_OUT_c (joined - (portRef Q (instanceRef trb_adapter_inst_FEE_DATA_WRITE_OUTio)) - (portRef I (instanceRef FEE_DATA_WRITE_OUT_pad)) - )) - (net FEE_DATA_WRITE_OUT (joined - (portRef O (instanceRef FEE_DATA_WRITE_OUT_pad)) - (portRef FEE_DATA_WRITE_OUT) - )) - (net FEE_DATAFINISHED_OUT_c (joined - (portRef Q (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio)) - (portRef I (instanceRef FEE_DATAFINISHED_OUT_pad)) - )) - (net FEE_DATAFINISHED_OUT (joined - (portRef O (instanceRef FEE_DATAFINISHED_OUT_pad)) - (portRef FEE_DATAFINISHED_OUT) - )) - (net FEE_TRG_RELEASE_OUT_c (joined - (portRef Q (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio)) - (portRef I (instanceRef FEE_TRG_RELEASE_OUT_pad)) - )) - (net FEE_TRG_RELEASE_OUT (joined - (portRef O (instanceRef FEE_TRG_RELEASE_OUT_pad)) - (portRef FEE_TRG_RELEASE_OUT) - )) - (net LVL1_TRG_DATA_VALI_IN_rising_c (joined - (portRef LVL1_TRG_DATA_VALI_IN_rising_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef LVL1_TRG_DATA_VALI_IN_rising_pad)) - )) - (net LVL1_TRG_DATA_VALI_IN_rising (joined - (portRef O (instanceRef LVL1_TRG_DATA_VALI_IN_rising_pad)) - (portRef LVL1_TRG_DATA_VALI_IN_rising) - )) - (net burst_c (joined - (portRef burst_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef burst_pad)) - )) - (net burst (joined - (portRef O (instanceRef burst_pad)) - (portRef burst) - )) - (net discard_c (joined - (portRef discard_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef discard_pad)) - )) - (net discard (joined - (portRef O (instanceRef discard_pad)) - (portRef discard) - )) - (net last_buf_empty_c (joined - (portRef last_buf_empty_c (instanceRef fifo_colector_inst)) - (portRef last_buf_empty_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef last_buf_empty_pad)) - )) - (net last_buf_empty (joined - (portRef O (instanceRef last_buf_empty_pad)) - (portRef last_buf_empty) - )) - (net finished_c (joined - (portRef finished_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef finished_pad)) - (portRef D (instanceRef trb_adapter_inst_FEE_DATAFINISHED_OUTio)) - )) - (net finished (joined - (portRef O (instanceRef finished_pad)) - (portRef finished) - )) - (net release_out_c (joined - (portRef release_out_c (instanceRef trb_adapter_inst)) - (portRef I (instanceRef release_out_pad)) - (portRef D (instanceRef trb_adapter_inst_FEE_TRG_RELEASE_OUTio)) - )) - (net release_out (joined - (portRef O (instanceRef release_out_pad)) - (portRef release_out) - )) - (net hades_trig_c (joined - (portRef O (instanceRef hades_trig_pad)) - (portRef A (instanceRef hades_trig_pad_RNIE1B4)) - )) - (net hades_trig (joined - (portRef hades_trig) - (portRef I (instanceRef hades_trig_pad)) - )) - (net hades_raw_out_valid_c (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_referenced_out_validio)) - (portRef I (instanceRef hades_raw_out_valid_pad)) - )) - (net hades_raw_out_valid (joined - (portRef O (instanceRef hades_raw_out_valid_pad)) - (portRef hades_raw_out_valid) - )) - (net (rename hades_raw_valid_vect_0 "hades_raw_valid_vect[0]") (joined - (portRef O (instanceRef hades_raw_valid_vect_pad_0)) - (portRef (member hades_raw_valid_vect 1)) - )) - (net (rename hades_raw_valid_vect_1 "hades_raw_valid_vect[1]") (joined - (portRef O (instanceRef hades_raw_valid_vect_pad_1)) - (portRef (member hades_raw_valid_vect 0)) - )) - (net hades_lvl1_c (joined - (portRef O (instanceRef hades_lvl1_pad)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio_0)) - (portRef A (instanceRef hades_lvl1_pad_RNINMH5)) - )) - (net hades_lvl1 (joined - (portRef hades_lvl1) - (portRef I (instanceRef hades_lvl1_pad)) - )) - (net hades_lvl1_invalid_c (joined - (portRef O (instanceRef hades_lvl1_invalid_pad)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0)) - )) - (net hades_lvl1_invalid (joined - (portRef hades_lvl1_invalid) - (portRef I (instanceRef hades_lvl1_invalid_pad)) - )) - (net (rename hades_offset_c_0 "hades_offset_c[0]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_0)) - (portRef I (instanceRef hades_offset_pad_0)) - )) - (net (rename hades_offset_0 "hades_offset[0]") (joined - (portRef O (instanceRef hades_offset_pad_0)) - (portRef (member hades_offset 8)) - )) - (net (rename hades_offset_c_1 "hades_offset_c[1]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_1)) - (portRef I (instanceRef hades_offset_pad_1)) - )) - (net (rename hades_offset_1 "hades_offset[1]") (joined - (portRef O (instanceRef hades_offset_pad_1)) - (portRef (member hades_offset 7)) - )) - (net (rename hades_offset_c_2 "hades_offset_c[2]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_2)) - (portRef I (instanceRef hades_offset_pad_2)) - )) - (net (rename hades_offset_2 "hades_offset[2]") (joined - (portRef O (instanceRef hades_offset_pad_2)) - (portRef (member hades_offset 6)) - )) - (net (rename hades_offset_c_3 "hades_offset_c[3]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3)) - (portRef I (instanceRef hades_offset_pad_3)) - )) - (net (rename hades_offset_3 "hades_offset[3]") (joined - (portRef O (instanceRef hades_offset_pad_3)) - (portRef (member hades_offset 5)) - )) - (net (rename hades_offset_c_4 "hades_offset_c[4]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4)) - (portRef I (instanceRef hades_offset_pad_4)) - )) - (net (rename hades_offset_4 "hades_offset[4]") (joined - (portRef O (instanceRef hades_offset_pad_4)) - (portRef (member hades_offset 4)) - )) - (net (rename hades_offset_c_5 "hades_offset_c[5]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5)) - (portRef I (instanceRef hades_offset_pad_5)) - )) - (net (rename hades_offset_5 "hades_offset[5]") (joined - (portRef O (instanceRef hades_offset_pad_5)) - (portRef (member hades_offset 3)) - )) - (net (rename hades_offset_c_6 "hades_offset_c[6]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6)) - (portRef I (instanceRef hades_offset_pad_6)) - )) - (net (rename hades_offset_6 "hades_offset[6]") (joined - (portRef O (instanceRef hades_offset_pad_6)) - (portRef (member hades_offset 2)) - )) - (net (rename hades_offset_c_7 "hades_offset_c[7]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7)) - (portRef I (instanceRef hades_offset_pad_7)) - )) - (net (rename hades_offset_7 "hades_offset[7]") (joined - (portRef O (instanceRef hades_offset_pad_7)) - (portRef (member hades_offset 1)) - )) - (net (rename hades_offset_c_8 "hades_offset_c[8]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8)) - (portRef I (instanceRef hades_offset_pad_8)) - )) - (net (rename hades_offset_8 "hades_offset[8]") (joined - (portRef O (instanceRef hades_offset_pad_8)) - (portRef (member hades_offset 0)) - )) - (net hades_offset_valid_c (joined - (portRef hades_offset_valid_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_offset_valid_pad)) - (portRef D (instanceRef hades_tdc_bundle_inst_referenced_out_validio)) - )) - (net hades_offset_valid (joined - (portRef O (instanceRef hades_offset_valid_pad)) - (portRef hades_offset_valid) - )) - (net hades_window_end_c (joined - (portRef hades_window_end_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_window_end_pad)) - )) - (net hades_window_end (joined - (portRef O (instanceRef hades_window_end_pad)) - (portRef hades_window_end) - )) - (net hades_buf_out_valid_c (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_buf_out_validio)) - (portRef I (instanceRef hades_buf_out_valid_pad)) - )) - (net hades_buf_out_valid (joined - (portRef O (instanceRef hades_buf_out_valid_pad)) - (portRef hades_buf_out_valid) - )) - (net hades_buf_release_c (joined - (portRef hades_buf_release_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_buf_release_pad)) - )) - (net hades_buf_release (joined - (portRef O (instanceRef hades_buf_release_pad)) - (portRef hades_buf_release) - )) - (net hades_buf_finished_c (joined - (portRef hades_buf_finished_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_buf_finished_pad)) - )) - (net hades_buf_finished (joined - (portRef O (instanceRef hades_buf_finished_pad)) - (portRef hades_buf_finished) - )) - (net (rename hades_hit_out_i_0 "hades_hit_out_i[0]") (joined - (portRef O (instanceRef hades_hit_out_i_pad_0)) - (portRef (member hades_hit_out_i 3)) - )) - (net (rename hades_hit_out_i_1 "hades_hit_out_i[1]") (joined - (portRef O (instanceRef hades_hit_out_i_pad_1)) - (portRef (member hades_hit_out_i 2)) - )) - (net (rename hades_hit_out_i_2 "hades_hit_out_i[2]") (joined - (portRef O (instanceRef hades_hit_out_i_pad_2)) - (portRef (member hades_hit_out_i 1)) - )) - (net (rename hades_hit_out_i_3 "hades_hit_out_i[3]") (joined - (portRef O (instanceRef hades_hit_out_i_pad_3)) - (portRef (member hades_hit_out_i 0)) - )) - (net (rename hades_hit_valid_c_0 "hades_hit_valid_c[0]") (joined - (portRef (member hades_hit_valid_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_valid_pad_0)) - )) - (net (rename hades_hit_valid_0 "hades_hit_valid[0]") (joined - (portRef O (instanceRef hades_hit_valid_pad_0)) - (portRef (member hades_hit_valid 3)) - )) - (net (rename hades_hit_valid_c_1 "hades_hit_valid_c[1]") (joined - (portRef (member hades_hit_valid_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_valid_pad_1)) - )) - (net (rename hades_hit_valid_1 "hades_hit_valid[1]") (joined - (portRef O (instanceRef hades_hit_valid_pad_1)) - (portRef (member hades_hit_valid 2)) - )) - (net (rename hades_hit_valid_c_2 "hades_hit_valid_c[2]") (joined - (portRef (member hades_hit_valid_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_valid_pad_2)) - )) - (net (rename hades_hit_valid_2 "hades_hit_valid[2]") (joined - (portRef O (instanceRef hades_hit_valid_pad_2)) - (portRef (member hades_hit_valid 1)) - )) - (net (rename hades_hit_valid_c_3 "hades_hit_valid_c[3]") (joined - (portRef (member hades_hit_valid_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_hit_valid_pad_3)) - )) - (net (rename hades_hit_valid_3 "hades_hit_valid[3]") (joined - (portRef O (instanceRef hades_hit_valid_pad_3)) - (portRef (member hades_hit_valid 0)) - )) - (net hades_discard_c (joined - (portRef hades_discard_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_discard_pad)) - )) - (net hades_discard (joined - (portRef O (instanceRef hades_discard_pad)) - (portRef hades_discard) - )) - (net (rename hades_invalid_dl_c_0 "hades_invalid_dl_c[0]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio_0)) - (portRef (member hades_invalid_dl_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_invalid_dl_pad_0)) - )) - (net (rename hades_invalid_dl_0 "hades_invalid_dl[0]") (joined - (portRef O (instanceRef hades_invalid_dl_pad_0)) - (portRef (member hades_invalid_dl 3)) - )) - (net (rename hades_invalid_dl_c_1 "hades_invalid_dl_c[1]") (joined - (portRef (member hades_invalid_dl_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_invalid_dl_pad_1)) - )) - (net (rename hades_invalid_dl_1 "hades_invalid_dl[1]") (joined - (portRef O (instanceRef hades_invalid_dl_pad_1)) - (portRef (member hades_invalid_dl 2)) - )) - (net (rename hades_invalid_dl_c_2 "hades_invalid_dl_c[2]") (joined - (portRef (member hades_invalid_dl_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_invalid_dl_pad_2)) - )) - (net (rename hades_invalid_dl_2 "hades_invalid_dl[2]") (joined - (portRef O (instanceRef hades_invalid_dl_pad_2)) - (portRef (member hades_invalid_dl 1)) - )) - (net (rename hades_invalid_dl_c_3 "hades_invalid_dl_c[3]") (joined - (portRef (member hades_invalid_dl_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_invalid_dl_pad_3)) - )) - (net (rename hades_invalid_dl_3 "hades_invalid_dl[3]") (joined - (portRef O (instanceRef hades_invalid_dl_pad_3)) - (portRef (member hades_invalid_dl 0)) - )) - (net (rename hades_buf_drop_0 "hades_buf_drop[0]") (joined - (portRef O (instanceRef hades_buf_drop_pad_0)) - (portRef (member hades_buf_drop 3)) - )) - (net (rename hades_buf_drop_c_1 "hades_buf_drop_c[1]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_buf_drop_1io_1)) - (portRef I (instanceRef hades_buf_drop_pad_1)) - )) - (net (rename hades_buf_drop_1 "hades_buf_drop[1]") (joined - (portRef O (instanceRef hades_buf_drop_pad_1)) - (portRef (member hades_buf_drop 2)) - )) - (net (rename hades_buf_drop_2 "hades_buf_drop[2]") (joined - (portRef O (instanceRef hades_buf_drop_pad_2)) - (portRef (member hades_buf_drop 1)) - )) - (net (rename hades_buf_drop_3 "hades_buf_drop[3]") (joined - (portRef O (instanceRef hades_buf_drop_pad_3)) - (portRef (member hades_buf_drop 0)) - )) - (net (rename hades_dbg2_out_c_0 "hades_dbg2_out_c[0]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_0)) - (portRef I (instanceRef hades_dbg2_out_pad_0)) - )) - (net (rename hades_dbg2_out_0 "hades_dbg2_out[0]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_0)) - (portRef (member hades_dbg2_out 31)) - )) - (net (rename hades_dbg2_out_c_1 "hades_dbg2_out_c[1]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_1)) - (portRef I (instanceRef hades_dbg2_out_pad_1)) - )) - (net (rename hades_dbg2_out_1 "hades_dbg2_out[1]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_1)) - (portRef (member hades_dbg2_out 30)) - )) - (net (rename hades_dbg2_out_c_2 "hades_dbg2_out_c[2]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_2)) - (portRef I (instanceRef hades_dbg2_out_pad_2)) - )) - (net (rename hades_dbg2_out_2 "hades_dbg2_out[2]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_2)) - (portRef (member hades_dbg2_out 29)) - )) - (net (rename hades_dbg2_out_3 "hades_dbg2_out[3]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_3)) - (portRef (member hades_dbg2_out 28)) - )) - (net (rename hades_dbg2_out_c_4 "hades_dbg2_out_c[4]") (joined - (portRef (member hades_dbg2_out_c 8) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_4)) - )) - (net (rename hades_dbg2_out_4 "hades_dbg2_out[4]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_4)) - (portRef (member hades_dbg2_out 27)) - )) - (net (rename hades_dbg2_out_c_5 "hades_dbg2_out_c[5]") (joined - (portRef (member hades_dbg2_out_c 7) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_5)) - )) - (net (rename hades_dbg2_out_5 "hades_dbg2_out[5]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_5)) - (portRef (member hades_dbg2_out 26)) - )) - (net (rename hades_dbg2_out_c_6 "hades_dbg2_out_c[6]") (joined - (portRef (member hades_dbg2_out_c 6) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_6)) - )) - (net (rename hades_dbg2_out_6 "hades_dbg2_out[6]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_6)) - (portRef (member hades_dbg2_out 25)) - )) - (net (rename hades_dbg2_out_c_7 "hades_dbg2_out_c[7]") (joined - (portRef (member hades_dbg2_out_c 5) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_7)) - )) - (net (rename hades_dbg2_out_7 "hades_dbg2_out[7]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_7)) - (portRef (member hades_dbg2_out 24)) - )) - (net (rename hades_dbg2_out_c_8 "hades_dbg2_out_c[8]") (joined - (portRef (member hades_dbg2_out_c 4) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_8)) - )) - (net (rename hades_dbg2_out_8 "hades_dbg2_out[8]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_8)) - (portRef (member hades_dbg2_out 23)) - )) - (net (rename hades_dbg2_out_c_9 "hades_dbg2_out_c[9]") (joined - (portRef (member hades_dbg2_out_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_9)) - )) - (net (rename hades_dbg2_out_9 "hades_dbg2_out[9]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_9)) - (portRef (member hades_dbg2_out 22)) - )) - (net (rename hades_dbg2_out_c_10 "hades_dbg2_out_c[10]") (joined - (portRef (member hades_dbg2_out_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_10)) - )) - (net (rename hades_dbg2_out_10 "hades_dbg2_out[10]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_10)) - (portRef (member hades_dbg2_out 21)) - )) - (net (rename hades_dbg2_out_c_11 "hades_dbg2_out_c[11]") (joined - (portRef (member hades_dbg2_out_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_11)) - )) - (net (rename hades_dbg2_out_11 "hades_dbg2_out[11]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_11)) - (portRef (member hades_dbg2_out 20)) - )) - (net (rename hades_dbg2_out_c_12 "hades_dbg2_out_c[12]") (joined - (portRef (member hades_dbg2_out_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_out_pad_12)) - )) - (net (rename hades_dbg2_out_12 "hades_dbg2_out[12]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_12)) - (portRef (member hades_dbg2_out 19)) - )) - (net (rename hades_dbg2_out_13 "hades_dbg2_out[13]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_13)) - (portRef (member hades_dbg2_out 18)) - )) - (net (rename hades_dbg2_out_14 "hades_dbg2_out[14]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_14)) - (portRef (member hades_dbg2_out 17)) - )) - (net (rename hades_dbg2_out_15 "hades_dbg2_out[15]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_15)) - (portRef (member hades_dbg2_out 16)) - )) - (net (rename hades_dbg2_out_c_16 "hades_dbg2_out_c[16]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_12)) - (portRef I (instanceRef hades_dbg2_out_pad_16)) - )) - (net (rename hades_dbg2_out_16 "hades_dbg2_out[16]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_16)) - (portRef (member hades_dbg2_out 15)) - )) - (net (rename hades_dbg2_out_c_17 "hades_dbg2_out_c[17]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_13)) - (portRef I (instanceRef hades_dbg2_out_pad_17)) - )) - (net (rename hades_dbg2_out_17 "hades_dbg2_out[17]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_17)) - (portRef (member hades_dbg2_out 14)) - )) - (net (rename hades_dbg2_out_c_18 "hades_dbg2_out_c[18]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_14)) - (portRef I (instanceRef hades_dbg2_out_pad_18)) - )) - (net (rename hades_dbg2_out_18 "hades_dbg2_out[18]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_18)) - (portRef (member hades_dbg2_out 13)) - )) - (net (rename hades_dbg2_out_19 "hades_dbg2_out[19]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_19)) - (portRef (member hades_dbg2_out 12)) - )) - (net (rename hades_dbg2_out_c_20 "hades_dbg2_out_c[20]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_15)) - (portRef I (instanceRef hades_dbg2_out_pad_20)) - )) - (net (rename hades_dbg2_out_20 "hades_dbg2_out[20]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_20)) - (portRef (member hades_dbg2_out 11)) - )) - (net (rename hades_dbg2_out_c_21 "hades_dbg2_out_c[21]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_16)) - (portRef I (instanceRef hades_dbg2_out_pad_21)) - )) - (net (rename hades_dbg2_out_21 "hades_dbg2_out[21]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_21)) - (portRef (member hades_dbg2_out 10)) - )) - (net (rename hades_dbg2_out_c_22 "hades_dbg2_out_c[22]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_17)) - (portRef I (instanceRef hades_dbg2_out_pad_22)) - )) - (net (rename hades_dbg2_out_22 "hades_dbg2_out[22]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_22)) - (portRef (member hades_dbg2_out 9)) - )) - (net (rename hades_dbg2_out_c_23 "hades_dbg2_out_c[23]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_18)) - (portRef I (instanceRef hades_dbg2_out_pad_23)) - )) - (net (rename hades_dbg2_out_23 "hades_dbg2_out[23]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_23)) - (portRef (member hades_dbg2_out 8)) - )) - (net (rename hades_dbg2_out_c_24 "hades_dbg2_out_c[24]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_19)) - (portRef I (instanceRef hades_dbg2_out_pad_24)) - )) - (net (rename hades_dbg2_out_24 "hades_dbg2_out[24]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_24)) - (portRef (member hades_dbg2_out 7)) - )) - (net (rename hades_dbg2_out_c_25 "hades_dbg2_out_c[25]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_20)) - (portRef I (instanceRef hades_dbg2_out_pad_25)) - )) - (net (rename hades_dbg2_out_25 "hades_dbg2_out[25]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_25)) - (portRef (member hades_dbg2_out 6)) - )) - (net (rename hades_dbg2_out_c_26 "hades_dbg2_out_c[26]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_21)) - (portRef I (instanceRef hades_dbg2_out_pad_26)) - )) - (net (rename hades_dbg2_out_26 "hades_dbg2_out[26]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_26)) - (portRef (member hades_dbg2_out 5)) - )) - (net (rename hades_dbg2_out_c_27 "hades_dbg2_out_c[27]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_22)) - (portRef I (instanceRef hades_dbg2_out_pad_27)) - )) - (net (rename hades_dbg2_out_27 "hades_dbg2_out[27]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_27)) - (portRef (member hades_dbg2_out 4)) - )) - (net (rename hades_dbg2_out_c_28 "hades_dbg2_out_c[28]") (joined - (portRef Q (instanceRef hades_tdc_bundle_inst_hitbuffer_1_io_23)) - (portRef I (instanceRef hades_dbg2_out_pad_28)) - )) - (net (rename hades_dbg2_out_28 "hades_dbg2_out[28]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_28)) - (portRef (member hades_dbg2_out 3)) - )) - (net (rename hades_dbg2_out_29 "hades_dbg2_out[29]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_29)) - (portRef (member hades_dbg2_out 2)) - )) - (net (rename hades_dbg2_out_30 "hades_dbg2_out[30]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_30)) - (portRef (member hades_dbg2_out 1)) - )) - (net (rename hades_dbg2_out_31 "hades_dbg2_out[31]") (joined - (portRef O (instanceRef hades_dbg2_out_pad_31)) - (portRef (member hades_dbg2_out 0)) - )) - (net (rename hades_dbg2_coarse_c_0 "hades_dbg2_coarse_c[0]") (joined - (portRef (member hades_dbg2_coarse_c 8) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_0)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_3)) - )) - (net (rename hades_dbg2_coarse_0 "hades_dbg2_coarse[0]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_0)) - (portRef (member hades_dbg2_coarse 8)) - )) - (net (rename hades_dbg2_coarse_c_1 "hades_dbg2_coarse_c[1]") (joined - (portRef (member hades_dbg2_coarse_c 7) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_1)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_4)) - )) - (net (rename hades_dbg2_coarse_1 "hades_dbg2_coarse[1]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_1)) - (portRef (member hades_dbg2_coarse 7)) - )) - (net (rename hades_dbg2_coarse_c_2 "hades_dbg2_coarse_c[2]") (joined - (portRef (member hades_dbg2_coarse_c 6) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_2)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_5)) - )) - (net (rename hades_dbg2_coarse_2 "hades_dbg2_coarse[2]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_2)) - (portRef (member hades_dbg2_coarse 6)) - )) - (net (rename hades_dbg2_coarse_c_3 "hades_dbg2_coarse_c[3]") (joined - (portRef (member hades_dbg2_coarse_c 5) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_3)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_6)) - )) - (net (rename hades_dbg2_coarse_3 "hades_dbg2_coarse[3]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_3)) - (portRef (member hades_dbg2_coarse 5)) - )) - (net (rename hades_dbg2_coarse_c_4 "hades_dbg2_coarse_c[4]") (joined - (portRef (member hades_dbg2_coarse_c 4) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_4)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_7)) - )) - (net (rename hades_dbg2_coarse_4 "hades_dbg2_coarse[4]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_4)) - (portRef (member hades_dbg2_coarse 4)) - )) - (net (rename hades_dbg2_coarse_c_5 "hades_dbg2_coarse_c[5]") (joined - (portRef (member hades_dbg2_coarse_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_5)) - (portRef D (instanceRef hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio_8)) - )) - (net (rename hades_dbg2_coarse_5 "hades_dbg2_coarse[5]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_5)) - (portRef (member hades_dbg2_coarse 3)) - )) - (net (rename hades_dbg2_coarse_c_6 "hades_dbg2_coarse_c[6]") (joined - (portRef (member hades_dbg2_coarse_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_6)) - )) - (net (rename hades_dbg2_coarse_6 "hades_dbg2_coarse[6]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_6)) - (portRef (member hades_dbg2_coarse 2)) - )) - (net (rename hades_dbg2_coarse_c_7 "hades_dbg2_coarse_c[7]") (joined - (portRef (member hades_dbg2_coarse_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_7)) - )) - (net (rename hades_dbg2_coarse_7 "hades_dbg2_coarse[7]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_7)) - (portRef (member hades_dbg2_coarse 1)) - )) - (net (rename hades_dbg2_coarse_c_8 "hades_dbg2_coarse_c[8]") (joined - (portRef (member hades_dbg2_coarse_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_dbg2_coarse_pad_8)) - )) - (net (rename hades_dbg2_coarse_8 "hades_dbg2_coarse[8]") (joined - (portRef O (instanceRef hades_dbg2_coarse_pad_8)) - (portRef (member hades_dbg2_coarse 0)) - )) - (net (rename hades_drop_cmp_buf_c_0 "hades_drop_cmp_buf_c[0]") (joined - (portRef (member hades_drop_cmp_buf_c 8) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_0)) - )) - (net (rename hades_drop_cmp_buf_0 "hades_drop_cmp_buf[0]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_0)) - (portRef (member hades_drop_cmp_buf 11)) - )) - (net (rename hades_drop_cmp_buf_c_1 "hades_drop_cmp_buf_c[1]") (joined - (portRef (member hades_drop_cmp_buf_c 7) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_1)) - )) - (net (rename hades_drop_cmp_buf_1 "hades_drop_cmp_buf[1]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_1)) - (portRef (member hades_drop_cmp_buf 10)) - )) - (net (rename hades_drop_cmp_buf_c_2 "hades_drop_cmp_buf_c[2]") (joined - (portRef (member hades_drop_cmp_buf_c 6) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_2)) - )) - (net (rename hades_drop_cmp_buf_2 "hades_drop_cmp_buf[2]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_2)) - (portRef (member hades_drop_cmp_buf 9)) - )) - (net (rename hades_drop_cmp_buf_c_3 "hades_drop_cmp_buf_c[3]") (joined - (portRef (member hades_drop_cmp_buf_c 5) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_3)) - )) - (net (rename hades_drop_cmp_buf_3 "hades_drop_cmp_buf[3]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_3)) - (portRef (member hades_drop_cmp_buf 8)) - )) - (net (rename hades_drop_cmp_buf_c_4 "hades_drop_cmp_buf_c[4]") (joined - (portRef (member hades_drop_cmp_buf_c 4) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_4)) - )) - (net (rename hades_drop_cmp_buf_4 "hades_drop_cmp_buf[4]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_4)) - (portRef (member hades_drop_cmp_buf 7)) - )) - (net (rename hades_drop_cmp_buf_c_5 "hades_drop_cmp_buf_c[5]") (joined - (portRef (member hades_drop_cmp_buf_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_5)) - )) - (net (rename hades_drop_cmp_buf_5 "hades_drop_cmp_buf[5]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_5)) - (portRef (member hades_drop_cmp_buf 6)) - )) - (net (rename hades_drop_cmp_buf_c_6 "hades_drop_cmp_buf_c[6]") (joined - (portRef (member hades_drop_cmp_buf_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_6)) - )) - (net (rename hades_drop_cmp_buf_6 "hades_drop_cmp_buf[6]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_6)) - (portRef (member hades_drop_cmp_buf 5)) - )) - (net (rename hades_drop_cmp_buf_c_7 "hades_drop_cmp_buf_c[7]") (joined - (portRef (member hades_drop_cmp_buf_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_7)) - )) - (net (rename hades_drop_cmp_buf_7 "hades_drop_cmp_buf[7]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_7)) - (portRef (member hades_drop_cmp_buf 4)) - )) - (net (rename hades_drop_cmp_buf_c_8 "hades_drop_cmp_buf_c[8]") (joined - (portRef (member hades_drop_cmp_buf_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_pad_8)) - )) - (net (rename hades_drop_cmp_buf_8 "hades_drop_cmp_buf[8]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_8)) - (portRef (member hades_drop_cmp_buf 3)) - )) - (net (rename hades_drop_cmp_buf_9 "hades_drop_cmp_buf[9]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_9)) - (portRef (member hades_drop_cmp_buf 2)) - )) - (net (rename hades_drop_cmp_buf_10 "hades_drop_cmp_buf[10]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_10)) - (portRef (member hades_drop_cmp_buf 1)) - )) - (net (rename hades_drop_cmp_buf_11 "hades_drop_cmp_buf[11]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_pad_11)) - (portRef (member hades_drop_cmp_buf 0)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_0 "hades_drop_cmp_buf_coarse_c[0]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 9) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_0)) - )) - (net (rename hades_drop_cmp_buf_coarse_0 "hades_drop_cmp_buf_coarse[0]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_0)) - (portRef (member hades_drop_cmp_buf_coarse 11)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_1 "hades_drop_cmp_buf_coarse_c[1]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 8) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_1)) - )) - (net (rename hades_drop_cmp_buf_coarse_1 "hades_drop_cmp_buf_coarse[1]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_1)) - (portRef (member hades_drop_cmp_buf_coarse 10)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_2 "hades_drop_cmp_buf_coarse_c[2]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 7) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_2)) - )) - (net (rename hades_drop_cmp_buf_coarse_2 "hades_drop_cmp_buf_coarse[2]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_2)) - (portRef (member hades_drop_cmp_buf_coarse 9)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_3 "hades_drop_cmp_buf_coarse_c[3]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 6) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_3)) - )) - (net (rename hades_drop_cmp_buf_coarse_3 "hades_drop_cmp_buf_coarse[3]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_3)) - (portRef (member hades_drop_cmp_buf_coarse 8)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_4 "hades_drop_cmp_buf_coarse_c[4]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 5) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_4)) - )) - (net (rename hades_drop_cmp_buf_coarse_4 "hades_drop_cmp_buf_coarse[4]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_4)) - (portRef (member hades_drop_cmp_buf_coarse 7)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_5 "hades_drop_cmp_buf_coarse_c[5]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 4) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_5)) - )) - (net (rename hades_drop_cmp_buf_coarse_5 "hades_drop_cmp_buf_coarse[5]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_5)) - (portRef (member hades_drop_cmp_buf_coarse 6)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_6 "hades_drop_cmp_buf_coarse_c[6]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 3) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_6)) - )) - (net (rename hades_drop_cmp_buf_coarse_6 "hades_drop_cmp_buf_coarse[6]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_6)) - (portRef (member hades_drop_cmp_buf_coarse 5)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_7 "hades_drop_cmp_buf_coarse_c[7]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 2) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_7)) - )) - (net (rename hades_drop_cmp_buf_coarse_7 "hades_drop_cmp_buf_coarse[7]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_7)) - (portRef (member hades_drop_cmp_buf_coarse 4)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_8 "hades_drop_cmp_buf_coarse_c[8]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 1) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_8)) - )) - (net (rename hades_drop_cmp_buf_coarse_8 "hades_drop_cmp_buf_coarse[8]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_8)) - (portRef (member hades_drop_cmp_buf_coarse 3)) - )) - (net (rename hades_drop_cmp_buf_coarse_c_9 "hades_drop_cmp_buf_coarse_c[9]") (joined - (portRef (member hades_drop_cmp_buf_coarse_c 0) (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_coarse_pad_9)) - )) - (net (rename hades_drop_cmp_buf_coarse_9 "hades_drop_cmp_buf_coarse[9]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_9)) - (portRef (member hades_drop_cmp_buf_coarse 2)) - )) - (net (rename hades_drop_cmp_buf_coarse_10 "hades_drop_cmp_buf_coarse[10]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_10)) - (portRef (member hades_drop_cmp_buf_coarse 1)) - )) - (net (rename hades_drop_cmp_buf_coarse_11 "hades_drop_cmp_buf_coarse[11]") (joined - (portRef O (instanceRef hades_drop_cmp_buf_coarse_pad_11)) - (portRef (member hades_drop_cmp_buf_coarse 0)) - )) - (net hades_drop_cmp_buf_valid_c (joined - (portRef hades_drop_cmp_buf_valid_c (instanceRef hades_tdc_bundle_inst)) - (portRef I (instanceRef hades_drop_cmp_buf_valid_pad)) - )) - (net hades_drop_cmp_buf_valid (joined - (portRef O (instanceRef hades_drop_cmp_buf_valid_pad)) - (portRef hades_drop_cmp_buf_valid) - )) - (net hades_lvl1_c_i (joined - (portRef Z (instanceRef hades_lvl1_pad_RNINMH5)) - (portRef hades_lvl1_c_i (instanceRef hades_tdc_bundle_inst)) - )) - (net hades_trig_c_i (joined - (portRef Z (instanceRef hades_trig_pad_RNIE1B4)) - (portRef hades_trig_c_i (instanceRef hades_tdc_bundle_inst)) - )) - (net (rename trig_c_i_2 "trig_c_i[2]") (joined - (portRef Z (instanceRef trig_pad_RNIK6FF_2)) - (portRef trig_c_i_0 (instanceRef genblk1_2__tdc_channel_fifo_out_inst)) - )) - (net (rename trig_c_i_1 "trig_c_i[1]") (joined - (portRef Z (instanceRef trig_pad_RNIJ5FF_1)) - (portRef trig_c_i_0 (instanceRef genblk1_1__tdc_channel_fifo_out_inst)) - )) - (net (rename trig_c_i_0 "trig_c_i[0]") (joined - (portRef Z (instanceRef trig_pad_RNII4FF_0)) - (portRef trig_c_i_0 (instanceRef genblk1_0__tdc_channel_fifo_out_inst)) - )) - (net (rename reset_dl_i_2 "reset_dl_i[2]") (joined - (portRef Z (instanceRef reset_dl_RNISCAF_2)) - (portRef reset_dl_i_0 (instanceRef hades_tdc_bundle_inst)) - )) - ) - (property ADDRESS_WIDTH (integer 8)) - (property DATA_WIDTH (integer 24)) - (property CHANNELS (integer 3)) - (property orig_inst_of (string "top_tf")) - ) - ) - ) - (design top_tf (cellRef top_tf (libraryRef work)) - (property PART (string "lfe5um5g_45f-8") )) -) diff --git a/impl1/s1_impl1.fse b/impl1/s1_impl1.fse deleted file mode 100644 index e69de29..0000000 diff --git a/impl1/s1_impl1.htm b/impl1/s1_impl1.htm deleted file mode 100644 index 7846630..0000000 --- a/impl1/s1_impl1.htm +++ /dev/null @@ -1,9 +0,0 @@ - - - syntmp/s1_impl1_srr.htm log file - - - - - - diff --git a/impl1/s1_impl1.ior b/impl1/s1_impl1.ior deleted file mode 100644 index a7ae11f..0000000 --- a/impl1/s1_impl1.ior +++ /dev/null @@ -1,204 +0,0 @@ -Loading design for application iotiming from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: 9 -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -Loading design for application iotiming from file s1_impl1.ncd. -Design name: top_tf -NCD version: 3.3 -Vendor: LATTICE -Device: LFE5UM5G-45F -Package: CABGA381 -Performance: M -Package Status: Final Version 1.38. -Performance Hardware Data Status: Final Version 55.1. -// Design: top_tf -// Package: CABGA381 -// ncd File: s1_impl1.ncd -// Version: Diamond (64-bit) 3.11.2.446 -// Written on Wed Jun 16 09:20:37 2021 -// M: Minimum Performance Grade -// iotiming s1_impl1.ncd s1_impl1.prf -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml - -I/O Timing Report (All units are in ns) - -Worst Case Results across Performance Grades (M, 9, 8): - -// Input Setup and Hold Times - -Port Clock Edge Setup Performance_Grade Hold Performance_Grade ----------------------------------------------------------------------- -LVL1_INVALID_TRG_IN rd_clk R -0.242 M 2.049 8 -LVL1_TRG_DATA_VALID_IN rd_clk R -0.242 M 2.049 8 -hades_lvl1 clk F 2.162 8 1.169 M -hades_lvl1_invalid clk R -0.529 8 1.138 M -hades_trig clk F 2.282 8 0.712 M - - -// Clock to Output Delay - -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------- -FEE_DATAFINISHED_OUT rd_clk R 5.311 8 2.067 M -FEE_DATA_OUT[0] rd_clk R 8.637 8 5.249 M -FEE_DATA_OUT[10] rd_clk R 7.965 8 4.919 M -FEE_DATA_OUT[11] rd_clk R 8.348 8 5.096 M -FEE_DATA_OUT[12] rd_clk R 8.295 8 5.082 M -FEE_DATA_OUT[13] rd_clk R 8.705 8 5.299 M -FEE_DATA_OUT[14] rd_clk R 8.495 8 5.173 M -FEE_DATA_OUT[15] rd_clk R 8.386 8 5.119 M -FEE_DATA_OUT[16] rd_clk R 9.036 8 5.453 M -FEE_DATA_OUT[17] rd_clk R 8.626 8 5.229 M -FEE_DATA_OUT[18] rd_clk R 8.622 8 5.246 M -FEE_DATA_OUT[19] rd_clk R 8.108 8 4.987 M -FEE_DATA_OUT[1] rd_clk R 8.763 8 5.277 M -FEE_DATA_OUT[20] rd_clk R 8.695 8 5.268 M -FEE_DATA_OUT[21] rd_clk R 8.276 8 5.092 M -FEE_DATA_OUT[22] rd_clk R 8.532 8 5.199 M -FEE_DATA_OUT[23] rd_clk R 8.304 8 5.100 M -FEE_DATA_OUT[24] rd_clk R 8.280 8 5.083 M -FEE_DATA_OUT[25] rd_clk R 8.697 8 5.287 M -FEE_DATA_OUT[26] rd_clk R 8.529 8 5.194 M -FEE_DATA_OUT[27] rd_clk R 8.687 8 5.296 M -FEE_DATA_OUT[28] rd_clk R 8.632 8 5.249 M -FEE_DATA_OUT[29] rd_clk R 8.555 8 5.214 M -FEE_DATA_OUT[2] rd_clk R 8.715 8 5.294 M -FEE_DATA_OUT[30] rd_clk R 8.514 8 5.199 M -FEE_DATA_OUT[31] rd_clk R 8.519 8 5.194 M -FEE_DATA_OUT[3] rd_clk R 8.357 8 5.108 M -FEE_DATA_OUT[4] rd_clk R 8.716 8 5.293 M -FEE_DATA_OUT[5] rd_clk R 8.884 8 5.392 M -FEE_DATA_OUT[6] rd_clk R 8.803 8 5.322 M -FEE_DATA_OUT[7] rd_clk R 8.785 8 5.315 M -FEE_DATA_OUT[8] rd_clk R 8.395 8 5.107 M -FEE_DATA_OUT[9] rd_clk R 8.309 8 5.083 M -FEE_DATA_WRITE_OUT rd_clk R 5.311 8 2.067 M -FEE_TRG_RELEASE_OUT rd_clk R 5.311 8 2.067 M -LVL1_TRG_DATA_VALI_IN_rising rd_clk R 5.988 8 2.652 M -burst rd_clk R 5.985 8 2.605 M -discard rd_clk R 5.080 8 2.333 M -fifo_data_out[0] rd_clk R 8.408 8 5.132 M -fifo_data_out[10] rd_clk R 7.965 8 4.919 M -fifo_data_out[11] rd_clk R 8.348 8 5.096 M -fifo_data_out[12] rd_clk R 8.448 8 5.158 M -fifo_data_out[13] rd_clk R 8.654 8 5.273 M -fifo_data_out[14] rd_clk R 8.648 8 5.249 M -fifo_data_out[15] rd_clk R 7.943 8 4.904 M -fifo_data_out[16] rd_clk R 9.189 8 5.529 M -fifo_data_out[17] rd_clk R 8.779 8 5.305 M -fifo_data_out[18] rd_clk R 9.117 8 5.486 M -fifo_data_out[19] rd_clk R 8.108 8 4.987 M -fifo_data_out[1] rd_clk R 8.763 8 5.277 M -fifo_data_out[20] rd_clk R 8.873 8 5.361 M -fifo_data_out[21] rd_clk R 8.150 8 5.026 M -fifo_data_out[22] rd_clk R 8.710 8 5.292 M -fifo_data_out[23] rd_clk R 8.304 8 5.100 M -fifo_data_out[24] rd_clk R 8.545 8 5.205 M -fifo_data_out[25] rd_clk R 8.697 8 5.287 M -fifo_data_out[26] rd_clk R 8.682 8 5.269 M -fifo_data_out[27] rd_clk R 8.687 8 5.296 M -fifo_data_out[28] rd_clk R 8.785 8 5.324 M -fifo_data_out[29] rd_clk R 8.555 8 5.214 M -fifo_data_out[2] rd_clk R 8.715 8 5.294 M -fifo_data_out[30] rd_clk R 8.514 8 5.199 M -fifo_data_out[31] rd_clk R 8.672 8 5.269 M -fifo_data_out[3] rd_clk R 8.357 8 5.108 M -fifo_data_out[4] rd_clk R 8.716 8 5.293 M -fifo_data_out[5] rd_clk R 9.037 8 5.468 M -fifo_data_out[6] rd_clk R 8.957 8 5.398 M -fifo_data_out[7] rd_clk R 8.963 8 5.408 M -fifo_data_out[8] rd_clk R 8.395 8 5.107 M -fifo_data_out[9] rd_clk R 8.462 8 5.159 M -fifo_empty1 clk R 6.338 8 3.901 M -fifo_rden rd_clk R 9.015 8 4.309 M -finished rd_clk R 5.699 8 2.640 M -hades_buf_drop[1] clk R 4.373 8 2.516 M -hades_buf_finished clk R 5.004 8 3.223 M -hades_buf_out_valid clk R 4.373 8 2.516 M -hades_buf_release clk R 5.056 8 3.233 M -hades_dbg2_coarse[0] clk R 5.517 8 3.457 M -hades_dbg2_coarse[1] clk R 5.565 8 3.485 M -hades_dbg2_coarse[2] clk R 6.422 8 3.891 M -hades_dbg2_coarse[3] clk R 5.749 8 3.576 M -hades_dbg2_coarse[4] clk R 6.730 8 4.066 M -hades_dbg2_coarse[5] clk R 6.629 8 3.989 M -hades_dbg2_coarse[6] clk R 6.270 8 3.843 M -hades_dbg2_coarse[7] clk R 7.034 8 4.220 M -hades_dbg2_coarse[8] clk R 6.138 8 3.750 M -hades_dbg2_out[0] clk R 4.373 8 2.516 M -hades_dbg2_out[10] clk R 5.455 8 3.421 M -hades_dbg2_out[11] clk R 5.684 8 3.543 M -hades_dbg2_out[12] clk R 5.446 8 3.434 M -hades_dbg2_out[16] clk R 4.373 8 2.516 M -hades_dbg2_out[17] clk R 4.373 8 2.516 M -hades_dbg2_out[18] clk R 4.373 8 2.516 M -hades_dbg2_out[1] clk R 4.373 8 2.516 M -hades_dbg2_out[20] clk R 4.373 8 2.516 M -hades_dbg2_out[21] clk R 4.373 8 2.516 M -hades_dbg2_out[22] clk R 4.373 8 2.516 M -hades_dbg2_out[23] clk R 4.373 8 2.516 M -hades_dbg2_out[24] clk R 4.373 8 2.516 M -hades_dbg2_out[25] clk R 4.373 8 2.516 M -hades_dbg2_out[26] clk R 4.373 8 2.516 M -hades_dbg2_out[27] clk R 4.373 8 2.516 M -hades_dbg2_out[28] clk R 4.373 8 2.516 M -hades_dbg2_out[2] clk R 4.373 8 2.516 M -hades_dbg2_out[4] clk R 5.601 8 3.511 M -hades_dbg2_out[5] clk R 5.147 8 3.282 M -hades_dbg2_out[6] clk R 5.274 8 3.349 M -hades_dbg2_out[7] clk R 5.147 8 3.282 M -hades_dbg2_out[8] clk R 5.245 8 3.329 M -hades_dbg2_out[9] clk R 5.236 8 3.332 M -hades_discard clk R 5.876 8 3.609 M -hades_drop_cmp_buf[0] clk R 4.849 8 3.145 M -hades_drop_cmp_buf[1] clk R 5.102 8 3.255 M -hades_drop_cmp_buf[2] clk R 5.292 8 3.360 M -hades_drop_cmp_buf[3] clk R 5.275 8 3.342 M -hades_drop_cmp_buf[4] clk R 5.205 8 3.328 M -hades_drop_cmp_buf[5] clk R 5.149 8 3.303 M -hades_drop_cmp_buf[6] clk R 4.937 8 3.174 M -hades_drop_cmp_buf[7] clk R 5.330 8 3.397 M -hades_drop_cmp_buf[8] clk R 5.190 8 3.317 M -hades_drop_cmp_buf_coarse[0] clk R 5.257 8 3.329 M -hades_drop_cmp_buf_coarse[1] clk R 5.665 8 3.523 M -hades_drop_cmp_buf_coarse[2] clk R 5.260 8 3.330 M -hades_drop_cmp_buf_coarse[3] clk R 5.770 8 3.582 M -hades_drop_cmp_buf_coarse[4] clk R 5.512 8 3.459 M -hades_drop_cmp_buf_coarse[5] clk R 5.675 8 3.526 M -hades_drop_cmp_buf_coarse[6] clk R 5.490 8 3.439 M -hades_drop_cmp_buf_coarse[7] clk R 5.333 8 3.360 M -hades_drop_cmp_buf_coarse[8] clk R 5.655 8 3.532 M -hades_drop_cmp_buf_coarse[9] clk R 5.740 8 3.562 M -hades_drop_cmp_buf_valid clk R 5.087 8 3.238 M -hades_hit_out_i[0] clk R 5.277 8 3.312 M -hades_hit_out_i[1] clk R 5.091 8 3.241 M -hades_hit_out_i[2] clk R 5.226 8 3.328 M -hades_hit_out_i[3] clk R 5.455 8 3.423 M -hades_hit_valid[0] clk R 4.969 8 3.196 M -hades_hit_valid[1] clk R 4.807 8 3.119 M -hades_hit_valid[2] clk R 4.969 8 3.196 M -hades_hit_valid[3] clk R 4.695 8 3.062 M -hades_invalid_dl[0] clk R 4.420 8 2.938 M -hades_invalid_dl[1] clk R 5.004 8 3.220 M -hades_invalid_dl[2] clk R 4.671 8 3.052 M -hades_invalid_dl[3] clk R 4.976 8 3.211 M -hades_offset[0] clk R 4.373 8 2.516 M -hades_offset[1] clk R 4.373 8 2.516 M -hades_offset[2] clk R 4.373 8 2.516 M -hades_offset[3] clk R 4.373 8 2.516 M -hades_offset[4] clk R 4.373 8 2.516 M -hades_offset[5] clk R 4.373 8 2.516 M -hades_offset[6] clk R 4.373 8 2.516 M -hades_offset[7] clk R 4.373 8 2.516 M -hades_offset[8] clk R 4.373 8 2.516 M -hades_offset_valid clk R 6.416 8 3.925 M -hades_raw_out_valid clk R 4.373 8 2.516 M -hades_window_end clk R 6.286 8 3.867 M -last_buf_empty rd_clk R 7.396 8 3.504 M -release_out rd_clk R 6.079 8 2.759 M -WARNING: you must also run trce with hold speed: 8 -WARNING: you must also run trce with setup speed: M diff --git a/impl1/s1_impl1.log b/impl1/s1_impl1.log deleted file mode 100644 index d0353b8..0000000 --- a/impl1/s1_impl1.log +++ /dev/null @@ -1,4 +0,0 @@ ----- MParTrce Tool Log File ---- - -==== Par Standard Out ==== -==== End of Par Standard Out ==== diff --git a/impl1/s1_impl1.lpf b/impl1/s1_impl1.lpf deleted file mode 100644 index 2743d95..0000000 --- a/impl1/s1_impl1.lpf +++ /dev/null @@ -1,4 +0,0 @@ -#BLOCK ASYNCPATHS; -#BLOCK RESETPATHS; - -#FREQUENCY 200.000000 MHz; diff --git a/impl1/s1_impl1.lsedata b/impl1/s1_impl1.lsedata deleted file mode 100644 index e16710f..0000000 --- a/impl1/s1_impl1.lsedata +++ /dev/null @@ -1,120 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/impl1/s1_impl1.mrp b/impl1/s1_impl1.mrp deleted file mode 100644 index 954bf0e..0000000 --- a/impl1/s1_impl1.mrp +++ /dev/null @@ -1,12546 +0,0 @@ - - Lattice Mapping Report File for Design Module 'top_tf' - - -Design Information ------------------- - -Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial - s1_impl1.ngd -o s1_impl1_map.ncd -pr s1_impl1.prf -mp s1_impl1.mrp -lpf - /home/hadaq/mmichalek/lattice/simplified/impl1/s1_impl1_synplify.lpf -lpf - /home/hadaq/mmichalek/lattice/simplified/s1.lpf -xref_sym -xref_sig -tdm - -gui -msgset /home/hadaq/mmichalek/lattice/simplified/promote.xml -Target Vendor: LATTICE -Target Device: LFE5UM5G-45FCABGA381 -Target Performance: 8 -Mapper: sa5p00g, version: Diamond (64-bit) 3.11.2.446 -Mapped on: 06/16/21 09:19:26 - -Design Summary --------------- - - Number of registers: 934 out of 44457 (2%) - PFU registers: 899 out of 43848 (2%) - PIO registers: 35 out of 609 (6%) - Number of SLICEs: 692 out of 21924 (3%) - SLICEs as Logic/ROM: 692 out of 21924 (3%) - SLICEs as RAM: 0 out of 16443 (0%) - SLICEs as Carry: 121 out of 21924 (1%) - Number of LUT4s: 630 out of 43848 (1%) - Number used as logic LUTs: 388 - Number used as distributed RAM: 0 - Number used as ripple logic: 242 - Number used as shift registers: 0 - Number of PIO sites used: 187 out of 203 (92%) - Number of PIO sites used for single ended IOs: 185 - Number of PIO sites used for differential IOs: 2 (represented by 1 PIO - comps in NCD) - Number of block RAMs: 4 out of 108 (4%) - Number of GSRs: 0 out of 1 (0%) - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - DTR used : No - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%) - Number of DCC: 0 out of 60 (0%) - Number of DCS: 0 out of 2 (0%) - Number of PLLs: 1 out of 4 (25%) - Number of DDRDLLs: 0 out of 4 (0%) - Number of CLKDIV: 0 out of 4 (0%) - Number of ECLKSYNC: 0 out of 10 (0%) - Number of ECLKBRIDGECS: 0 out of 2 (0%) - Number of DCUs: 0 out of 2 (0%) - Number of DCU Channels: 0 out of 4 (0%) - Number of EXTREFs: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - - - Page 1 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Design Summary (cont) ---------------------- - Number Of Mapped DSP Components: - -------------------------------- - MULT18X18D 0 - MULT9X9D 0 - ALU54B 0 - ALU24B 0 - PRADD18A 0 - PRADD9A 0 - -------------------------------- - Number of Used DSP MULT Sites: 0 out of 144 (0 %) - Number of Used DSP ALU Sites: 0 out of 72 (0 %) - Number of Used DSP PRADD Sites: 0 out of 144 (0 %) - Number of clocks: 6 - Net clk_c: 1 loads, 1 rising, 0 falling (Driver: PIO clk ) - Net pll_clks[3]: 446 loads, 329 rising, 117 falling (Driver: - pll0inst/PLLInst_0 ) - Net pll_clks[2]: 24 loads, 12 rising, 12 falling (Driver: - pll0inst/PLLInst_0 ) - Net pll_clks[1]: 24 loads, 12 rising, 12 falling (Driver: - pll0inst/PLLInst_0 ) - Net pll_clks[0]: 25 loads, 13 rising, 12 falling (Driver: - pll0inst/PLLInst_0 ) - Net rd_clk_c: 38 loads, 38 rising, 0 falling (Driver: PIO rd_clk ) - Number of Clock Enables: 18 - Net reset_dl[2]: 7 loads, 7 LSLICEs - Net N_248_i: 1 loads, 0 LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 - LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 - LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 - LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 - LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i: 16 loads, 15 - LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 17 loads, 15 - LSLICEs - Net fifo_colector_inst/in_empty_pmux_i: 21 loads, 21 LSLICEs - Net fifo_colector_inst/fifo40_inst/wren_i: 16 loads, 15 LSLICEs - Net fifo_colector_inst/fifo40_inst/rden_i: 17 loads, 15 LSLICEs - Net hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa: 11 loads, 11 LSLICEs - Net un1_hit_i_2_0_a2: 20 loads, 5 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i: 6 loads, 6 - LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i: 6 loads, - 6 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i: 13 loads, - 13 LSLICEs - Net hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0: 10 - loads, 1 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en: 1 loads, 1 - LSLICEs - Number of LSRs: 13 - Net reset_dl[2]: 37 loads, 33 LSLICEs - Net genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 - - Page 2 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Design Summary (cont) ---------------------- - loads, 1 LSLICEs - Net genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 - loads, 1 LSLICEs - Net genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i: 1 - loads, 1 LSLICEs - Net fifo_colector_inst/iterator_RNI7U5I[1]: 12 loads, 12 LSLICEs - Net fifo_rden_c: 1 loads, 1 LSLICEs - Net fifo_colector_inst/in_empty_pmux: 2 loads, 2 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sy - nced7_rising_i: 3 loads, 3 LSLICEs - Net hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced - 7_rising_i: 4 loads, 4 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup: 4 - loads, 4 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2]: 1 loads, 1 - LSLICEs - Net valid_fast_RNI999V: 9 loads, 0 LSLICEs - Net hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_risin - g_i: 4 loads, 4 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net reset_dl[2]: 59 loads - Net fifo_colector_inst/iterator[0]: 47 loads - Net fifo_colector_inst/iterator[1]: 23 loads - Net fifo_colector_inst/in_empty_pmux_i: 22 loads - Net un1_hit_i_2_0_a2: 20 loads - Net fifo_colector_inst/fifo40_inst/rden_i: 19 loads - Net genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i: 19 loads - Net fifo_colector_inst/fifo40_inst/wren_i: 18 loads - -Symbol Cross Reference ----------------------- - -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0 (PFU) covers blocks: - w_gctr_cia -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6 (PFU) covers blocks: - r_gctr_cia -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71, - - Page 3 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12 (PFU) covers blocks: - empty_cmp_ci_a -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13 (PFU) covers blocks: - empty_cmp_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14 (PFU) covers blocks: - empty_cmp_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15 (PFU) covers blocks: - empty_cmp_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16 (PFU) covers blocks: - empty_cmp_3 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17 (PFU) covers blocks: - empty_cmp_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19 (PFU) covers blocks: - full_cmp_ci_a -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20 (PFU) covers blocks: - full_cmp_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21 (PFU) covers blocks: - full_cmp_1 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22 (PFU) covers blocks: - full_cmp_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23 (PFU) covers blocks: - full_cmp_3 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24 (PFU) covers blocks: - full_cmp_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26 (PFU) covers blocks: - w_gctr_cia -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31 (PFU) covers blocks: - - Page 4 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32 (PFU) covers blocks: - r_gctr_cia -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38 (PFU) covers blocks: - empty_cmp_ci_a -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39 (PFU) covers blocks: - empty_cmp_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40 (PFU) covers blocks: - empty_cmp_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41 (PFU) covers blocks: - empty_cmp_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42 (PFU) covers blocks: - empty_cmp_3 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43 (PFU) covers blocks: - empty_cmp_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45 (PFU) covers blocks: - full_cmp_ci_a -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46 (PFU) covers blocks: - full_cmp_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47 (PFU) covers blocks: - full_cmp_1 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48 (PFU) covers blocks: - full_cmp_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49 (PFU) covers blocks: - full_cmp_3 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50 (PFU) covers blocks: - full_cmp_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52 (PFU) covers blocks: - w_gctr_cia -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_101, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_100, w_gctr_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_99, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_98, w_gctr_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55 (PFU) covers blocks: - - Page 5 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_97, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_96, w_gctr_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_95, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_94, w_gctr_3 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_93, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_92, w_gctr_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58 (PFU) covers blocks: - r_gctr_cia -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_71, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_70, r_gctr_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_69, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_68, r_gctr_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_67, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_66, r_gctr_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_65, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_64, r_gctr_3 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_63, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_62, r_gctr_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64 (PFU) covers blocks: - empty_cmp_ci_a -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65 (PFU) covers blocks: - empty_cmp_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66 (PFU) covers blocks: - empty_cmp_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67 (PFU) covers blocks: - empty_cmp_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68 (PFU) covers blocks: - empty_cmp_3 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69 (PFU) covers blocks: - empty_cmp_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_1, a0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71 (PFU) covers blocks: - full_cmp_ci_a -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72 (PFU) covers blocks: - full_cmp_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73 (PFU) covers blocks: - full_cmp_1 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74 (PFU) covers blocks: - full_cmp_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75 (PFU) covers blocks: - full_cmp_3 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76 (PFU) covers blocks: - full_cmp_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_0, a1 -fifo_colector_inst/fifo40_inst/SLICE_78 (PFU) covers blocks: w_gctr_cia -fifo_colector_inst/fifo40_inst/SLICE_79 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_101, - - Page 6 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/FF_100, w_gctr_0 -fifo_colector_inst/fifo40_inst/SLICE_80 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_99, fifo_colector_inst/fifo40_inst/FF_98, - w_gctr_1 -fifo_colector_inst/fifo40_inst/SLICE_81 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_97, fifo_colector_inst/fifo40_inst/FF_96, - w_gctr_2 -fifo_colector_inst/fifo40_inst/SLICE_82 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_95, fifo_colector_inst/fifo40_inst/FF_94, - w_gctr_3 -fifo_colector_inst/fifo40_inst/SLICE_83 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_93, fifo_colector_inst/fifo40_inst/FF_92, - w_gctr_4 -fifo_colector_inst/fifo40_inst/SLICE_84 (PFU) covers blocks: r_gctr_cia -fifo_colector_inst/fifo40_inst/SLICE_85 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_71, fifo_colector_inst/fifo40_inst/FF_70, - r_gctr_0 -fifo_colector_inst/fifo40_inst/SLICE_86 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_69, fifo_colector_inst/fifo40_inst/FF_68, - r_gctr_1 -fifo_colector_inst/fifo40_inst/SLICE_87 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_67, fifo_colector_inst/fifo40_inst/FF_66, - r_gctr_2 -fifo_colector_inst/fifo40_inst/SLICE_88 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_65, fifo_colector_inst/fifo40_inst/FF_64, - r_gctr_3 -fifo_colector_inst/fifo40_inst/SLICE_89 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_63, fifo_colector_inst/fifo40_inst/FF_62, - r_gctr_4 -fifo_colector_inst/fifo40_inst/SLICE_90 (PFU) covers blocks: empty_cmp_ci_a -fifo_colector_inst/fifo40_inst/SLICE_91 (PFU) covers blocks: empty_cmp_0 -fifo_colector_inst/fifo40_inst/SLICE_92 (PFU) covers blocks: empty_cmp_1 -fifo_colector_inst/fifo40_inst/SLICE_93 (PFU) covers blocks: empty_cmp_2 -fifo_colector_inst/fifo40_inst/SLICE_94 (PFU) covers blocks: empty_cmp_3 -fifo_colector_inst/fifo40_inst/SLICE_95 (PFU) covers blocks: empty_cmp_4 -fifo_colector_inst/fifo40_inst/SLICE_96 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_1, a0 -fifo_colector_inst/fifo40_inst/SLICE_97 (PFU) covers blocks: full_cmp_ci_a -fifo_colector_inst/fifo40_inst/SLICE_98 (PFU) covers blocks: full_cmp_0 -fifo_colector_inst/fifo40_inst/SLICE_99 (PFU) covers blocks: full_cmp_1 -fifo_colector_inst/fifo40_inst/SLICE_100 (PFU) covers blocks: full_cmp_2 -fifo_colector_inst/fifo40_inst/SLICE_101 (PFU) covers blocks: full_cmp_3 -fifo_colector_inst/fifo40_inst/SLICE_102 (PFU) covers blocks: full_cmp_4 -fifo_colector_inst/fifo40_inst/SLICE_103 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_0, a1 -hades_tdc_bundle_inst/SLICE_104 (PFU) covers blocks: hit_valid25_0_I_27_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105 (PFU) covers - blocks: un1_coarse_1_0_I_1_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106 (PFU) covers - blocks: un1_coarse_1_0_I_9_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107 (PFU) covers - blocks: un1_coarse_1_0_I_21_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108 (PFU) covers - blocks: un1_coarse_1_0_I_27_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109 (PFU) covers - blocks: un1_buf_positive_0_I_1_0 - - Page 7 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110 (PFU) covers - blocks: un1_buf_positive_0_I_9_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111 (PFU) covers - blocks: un1_buf_positive_0_I_21_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112 (PFU) covers - blocks: un1_buf_positive_0_I_27_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113 (PFU) covers blocks: - un1_window_8_cry_0_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114 (PFU) covers blocks: - un1_window_8_cry_1_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115 (PFU) covers blocks: - un1_window_8_cry_3_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116 (PFU) covers blocks: - un1_window_8_cry_5_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117 (PFU) covers blocks: - un1_window_8_s_7_0 -hades_tdc_bundle_inst/SLICE_118 (PFU) covers blocks: hit_valid25_0_I_1_0 -hades_tdc_bundle_inst/SLICE_119 (PFU) covers blocks: hit_valid25_0_I_9_0 -hades_tdc_bundle_inst/SLICE_120 (PFU) covers blocks: hit_valid25_0_I_21_0 -hades_tdc_bundle_inst/SLICE_121 (PFU) covers blocks: hit_out_i_RNO[0], - buf_finished5_0_a2_0, hades_tdc_bundle_inst/hit_out_i[0] -hades_tdc_bundle_inst/SLICE_122 (PFU) covers blocks: SUM1_1_x2, N_50_i_i, - hades_tdc_bundle_inst/hit_out_i[1], hades_tdc_bundle_inst/hit_out_i[3] -hades_tdc_bundle_inst/SLICE_123 (PFU) covers blocks: hit_out_i_6_f1_0[2], - hit_valid_pmux_iv_0_a2_2, hades_tdc_bundle_inst/hit_out_i[2] -trb_adapter_inst/SLICE_124 (PFU) covers blocks: - trb_adapter_inst/LVL1_INVALID_TRG_IN_dl[1] -fifo_colector_inst/SLICE_125 (PFU) covers blocks: in_empty_pmux_0_RNIDRET, - in_empty_pmux_0, fifo_colector_inst/buffer_wr_enable -fifo_colector_inst/SLICE_126 (PFU) covers blocks: data_buffer_3[0], - data_buffer_3_0[0], fifo_colector_inst/data_buffer[0] -fifo_colector_inst/SLICE_127 (PFU) covers blocks: data_buffer_3[1], - data_buffer_3_0[1], fifo_colector_inst/data_buffer[1] -fifo_colector_inst/SLICE_128 (PFU) covers blocks: data_buffer_3[2], - data_buffer_3_0[2], fifo_colector_inst/data_buffer[2] -fifo_colector_inst/SLICE_129 (PFU) covers blocks: data_buffer_3[3], - data_buffer_3_0[3], fifo_colector_inst/data_buffer[3] -fifo_colector_inst/SLICE_130 (PFU) covers blocks: data_buffer_3[4], - data_buffer_3_0[4], fifo_colector_inst/data_buffer[4] -fifo_colector_inst/SLICE_131 (PFU) covers blocks: data_buffer_3[5], - data_buffer_3_0[5], fifo_colector_inst/data_buffer[5] -fifo_colector_inst/SLICE_132 (PFU) covers blocks: data_buffer_3[6], - data_buffer_3_0[6], fifo_colector_inst/data_buffer[6] -fifo_colector_inst/SLICE_133 (PFU) covers blocks: data_buffer_3[7], - data_buffer_3_0[7], fifo_colector_inst/data_buffer[7] -fifo_colector_inst/SLICE_134 (PFU) covers blocks: data_buffer_3_0[8], - data_buffer_3_0[9], fifo_colector_inst/data_buffer[8], - fifo_colector_inst/data_buffer[9] -fifo_colector_inst/SLICE_135 (PFU) covers blocks: data_buffer_3_0[10], - data_buffer_3_0[11], fifo_colector_inst/data_buffer[10], - fifo_colector_inst/data_buffer[11] -fifo_colector_inst/SLICE_136 (PFU) covers blocks: data_buffer_3_0[12], - data_buffer_3_0[13], fifo_colector_inst/data_buffer[12], - fifo_colector_inst/data_buffer[13] -fifo_colector_inst/SLICE_137 (PFU) covers blocks: data_buffer_3_0[14], - data_buffer_3_0[15], fifo_colector_inst/data_buffer[14], - - Page 8 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - fifo_colector_inst/data_buffer[15] -fifo_colector_inst/SLICE_138 (PFU) covers blocks: data_buffer_3_0[16], - data_buffer_3_0[17], fifo_colector_inst/data_buffer[16], - fifo_colector_inst/data_buffer[17] -fifo_colector_inst/SLICE_139 (PFU) covers blocks: data_buffer_3_0[18], - data_buffer_3_0[19], fifo_colector_inst/data_buffer[18], - fifo_colector_inst/data_buffer[19] -fifo_colector_inst/SLICE_140 (PFU) covers blocks: data_buffer_3_0[20], - data_buffer_3_0[21], fifo_colector_inst/data_buffer[20], - fifo_colector_inst/data_buffer[21] -fifo_colector_inst/SLICE_141 (PFU) covers blocks: data_buffer_3_0[22], - data_buffer_3_0[23], fifo_colector_inst/data_buffer[22], - fifo_colector_inst/data_buffer[23] -fifo_colector_inst/SLICE_142 (PFU) covers blocks: data_buffer_3_0[24], - data_buffer_3_0[25], fifo_colector_inst/data_buffer[24], - fifo_colector_inst/data_buffer[25] -fifo_colector_inst/SLICE_143 (PFU) covers blocks: data_buffer_3_0[26], - data_buffer_3_0[27], fifo_colector_inst/data_buffer[26], - fifo_colector_inst/data_buffer[27] -fifo_colector_inst/SLICE_144 (PFU) covers blocks: data_buffer_3_0[28], - data_buffer_3_0[29], fifo_colector_inst/data_buffer[28], - fifo_colector_inst/data_buffer[29] -fifo_colector_inst/SLICE_145 (PFU) covers blocks: data_buffer_3_0[30], - data_buffer_3_0[31], fifo_colector_inst/data_buffer[30], - fifo_colector_inst/data_buffer[31] -fifo_colector_inst/SLICE_146 (PFU) covers blocks: - fifo_colector_inst/data_buffer[32], fifo_colector_inst/data_buffer[33] -fifo_colector_inst/fifo40_inst/SLICE_147 (PFU) covers blocks: XOR2_t8, XOR2_t7, - fifo_colector_inst/fifo40_inst/FF_61, fifo_colector_inst/fifo40_inst/FF_60 -fifo_colector_inst/fifo40_inst/SLICE_148 (PFU) covers blocks: XOR2_t6, XOR2_t5, - fifo_colector_inst/fifo40_inst/FF_59, fifo_colector_inst/fifo40_inst/FF_58 -fifo_colector_inst/fifo40_inst/SLICE_149 (PFU) covers blocks: XOR2_t4, XOR2_t3, - fifo_colector_inst/fifo40_inst/FF_57, fifo_colector_inst/fifo40_inst/FF_56 -fifo_colector_inst/fifo40_inst/SLICE_150 (PFU) covers blocks: XOR2_t2, XOR2_t1, - fifo_colector_inst/fifo40_inst/FF_55, fifo_colector_inst/fifo40_inst/FF_54 -fifo_colector_inst/fifo40_inst/SLICE_151 (PFU) covers blocks: XOR2_t0, - fifo_colector_inst/fifo40_inst/FF_53, fifo_colector_inst/fifo40_inst/FF_52 -fifo_colector_inst/fifo40_inst/SLICE_152 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_31, fifo_colector_inst/fifo40_inst/FF_30 -fifo_colector_inst/fifo40_inst/SLICE_153 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_29, fifo_colector_inst/fifo40_inst/FF_28 -fifo_colector_inst/fifo40_inst/SLICE_154 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_27, fifo_colector_inst/fifo40_inst/FF_26 -fifo_colector_inst/fifo40_inst/SLICE_155 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_25, fifo_colector_inst/fifo40_inst/FF_24 -fifo_colector_inst/fifo40_inst/SLICE_156 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_23, fifo_colector_inst/fifo40_inst/FF_22 -fifo_colector_inst/fifo40_inst/SLICE_157 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_11, fifo_colector_inst/fifo40_inst/FF_10 -fifo_colector_inst/fifo40_inst/SLICE_158 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_9, fifo_colector_inst/fifo40_inst/FF_8 -fifo_colector_inst/fifo40_inst/SLICE_159 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_7, fifo_colector_inst/fifo40_inst/FF_6 -fifo_colector_inst/fifo40_inst/SLICE_160 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_5, fifo_colector_inst/fifo40_inst/FF_4 -fifo_colector_inst/fifo40_inst/SLICE_161 (PFU) covers blocks: - - Page 9 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/FF_3, fifo_colector_inst/fifo40_inst/FF_2 -fifo_colector_inst/fifo40_inst/SLICE_162 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_51, fifo_colector_inst/fifo40_inst/FF_50 -fifo_colector_inst/fifo40_inst/SLICE_163 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_49, fifo_colector_inst/fifo40_inst/FF_48 -fifo_colector_inst/fifo40_inst/SLICE_164 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_47, fifo_colector_inst/fifo40_inst/FF_46 -fifo_colector_inst/fifo40_inst/SLICE_165 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_45, fifo_colector_inst/fifo40_inst/FF_44 -fifo_colector_inst/fifo40_inst/SLICE_166 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_43, fifo_colector_inst/fifo40_inst/FF_42 -fifo_colector_inst/fifo40_inst/SLICE_167 (PFU) covers blocks: XOR2_t17, - XOR2_t16, fifo_colector_inst/fifo40_inst/FF_91, - fifo_colector_inst/fifo40_inst/FF_90 -fifo_colector_inst/fifo40_inst/SLICE_168 (PFU) covers blocks: XOR2_t15, - XOR2_t14, fifo_colector_inst/fifo40_inst/FF_89, - fifo_colector_inst/fifo40_inst/FF_88 -fifo_colector_inst/fifo40_inst/SLICE_169 (PFU) covers blocks: XOR2_t13, - XOR2_t12, fifo_colector_inst/fifo40_inst/FF_87, - fifo_colector_inst/fifo40_inst/FF_86 -fifo_colector_inst/fifo40_inst/SLICE_170 (PFU) covers blocks: XOR2_t11, - XOR2_t10, fifo_colector_inst/fifo40_inst/FF_85, - fifo_colector_inst/fifo40_inst/FF_84 -fifo_colector_inst/fifo40_inst/SLICE_171 (PFU) covers blocks: XOR2_t9, - fifo_colector_inst/fifo40_inst/FF_83, fifo_colector_inst/fifo40_inst/FF_82 -fifo_colector_inst/fifo40_inst/SLICE_172 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_41, fifo_colector_inst/fifo40_inst/FF_40 -fifo_colector_inst/fifo40_inst/SLICE_173 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_39, fifo_colector_inst/fifo40_inst/FF_38 -fifo_colector_inst/fifo40_inst/SLICE_174 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_37, fifo_colector_inst/fifo40_inst/FF_36 -fifo_colector_inst/fifo40_inst/SLICE_175 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_35, fifo_colector_inst/fifo40_inst/FF_34 -fifo_colector_inst/fifo40_inst/SLICE_176 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_33, fifo_colector_inst/fifo40_inst/FF_32 -fifo_colector_inst/fifo40_inst/SLICE_177 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_21, fifo_colector_inst/fifo40_inst/FF_20 -fifo_colector_inst/fifo40_inst/SLICE_178 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_19, fifo_colector_inst/fifo40_inst/FF_18 -fifo_colector_inst/fifo40_inst/SLICE_179 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_17, fifo_colector_inst/fifo40_inst/FF_16 -fifo_colector_inst/fifo40_inst/SLICE_180 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_15, fifo_colector_inst/fifo40_inst/FF_14 -fifo_colector_inst/fifo40_inst/SLICE_181 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_13, fifo_colector_inst/fifo40_inst/FF_12 -fifo_colector_inst/fifo40_inst/SLICE_182 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_81, fifo_colector_inst/fifo40_inst/FF_80 -fifo_colector_inst/fifo40_inst/SLICE_183 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_79, fifo_colector_inst/fifo40_inst/FF_78 -fifo_colector_inst/fifo40_inst/SLICE_184 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_77, fifo_colector_inst/fifo40_inst/FF_76 -fifo_colector_inst/fifo40_inst/SLICE_185 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_75, fifo_colector_inst/fifo40_inst/FF_74 -fifo_colector_inst/fifo40_inst/SLICE_186 (PFU) covers blocks: - fifo_colector_inst/fifo40_inst/FF_73, fifo_colector_inst/fifo40_inst/FF_72 -fifo_colector_inst/SLICE_187 (PFU) covers blocks: un5_in_read_enable, - - Page 10 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - fifo_colector_inst/iterator[0], fifo_colector_inst/iterator[1] -trb_adapter_inst/SLICE_188 (PFU) covers blocks: buf_rden4, burst, - trb_adapter_inst/buf_rden -fifo_colector_inst/SLICE_189 (PFU) covers blocks: in_read_enable_0_.fb, - in_read_enable_1_.fb, fifo_colector_inst/in_read_enable[0], - fifo_colector_inst/in_read_enable[1] -fifo_colector_inst/SLICE_190 (PFU) covers blocks: in_read_enable_2_.fb, - fifo_colector_inst/in_read_enable[2] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6], - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204 (PFU) covers blocks: - valid_internal_RNO, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206 (PFU) covers - blocks: XOR2_t8, XOR2_t7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207 (PFU) covers - blocks: XOR2_t6, XOR2_t5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59, - - Page 11 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208 (PFU) covers - blocks: XOR2_t4, XOR2_t3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209 (PFU) covers - blocks: XOR2_t2, XOR2_t1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210 (PFU) covers - blocks: XOR2_t0, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43, - - Page 12 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226 (PFU) covers - blocks: XOR2_t17, XOR2_t16, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227 (PFU) covers - blocks: XOR2_t15, XOR2_t14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228 (PFU) covers - blocks: XOR2_t13, XOR2_t12, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229 (PFU) covers - blocks: XOR2_t11, XOR2_t10, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230 (PFU) covers - blocks: XOR2_t9, genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78 - - Page 13 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245 (PFU) covers - blocks: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72 -genblk1[0].tdc_channel_fifo_out_inst/SLICE_246 (PFU) covers blocks: - fifo_in_data_11_.fb, genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[11] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7], - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] -genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271 (PFU) covers blocks: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2], - - Page 14 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6], - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284 (PFU) covers blocks: - valid_internal_RNO, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286 (PFU) covers - blocks: XOR2_t8, XOR2_t7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287 (PFU) covers - blocks: XOR2_t6, XOR2_t5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288 (PFU) covers - blocks: XOR2_t4, XOR2_t3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289 (PFU) covers - blocks: XOR2_t2, XOR2_t1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290 (PFU) covers - blocks: XOR2_t0, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291 (PFU) covers - - Page 15 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306 (PFU) covers - blocks: XOR2_t17, XOR2_t16, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307 (PFU) covers - blocks: XOR2_t15, XOR2_t14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308 (PFU) covers - blocks: XOR2_t13, XOR2_t12, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86 - - Page 16 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309 (PFU) covers - blocks: XOR2_t11, XOR2_t10, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310 (PFU) covers - blocks: XOR2_t9, genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325 (PFU) covers - blocks: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72 -genblk1[1].tdc_channel_fifo_out_inst/SLICE_326 (PFU) covers blocks: - fifo_in_data_11_.fb, genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[11] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0], - - Page 17 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7], - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] -genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351 (PFU) covers blocks: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - - Page 18 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6], - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364 (PFU) covers blocks: - valid_internal_RNO, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366 (PFU) covers - blocks: XOR2_t8, XOR2_t7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_61, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_60 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367 (PFU) covers - blocks: XOR2_t6, XOR2_t5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_59, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_58 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368 (PFU) covers - blocks: XOR2_t4, XOR2_t3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_57, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_56 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369 (PFU) covers - blocks: XOR2_t2, XOR2_t1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_55, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_54 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370 (PFU) covers - blocks: XOR2_t0, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_53, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_52 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_31, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_30 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_29, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_28 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_27, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_26 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_25, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_24 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_23, - - Page 19 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_22 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_11, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_10 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_8 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_6 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_51, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_50 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_49, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_48 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_47, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_46 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_45, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_44 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_43, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_42 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386 (PFU) covers - blocks: XOR2_t17, XOR2_t16, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_91, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_90 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387 (PFU) covers - blocks: XOR2_t15, XOR2_t14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_89, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_88 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388 (PFU) covers - blocks: XOR2_t13, XOR2_t12, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_87, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_86 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389 (PFU) covers - blocks: XOR2_t11, XOR2_t10, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_85, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_84 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390 (PFU) covers - blocks: XOR2_t9, genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_83, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_82 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_41, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_40 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_39, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_38 - - Page 20 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_37, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_36 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_35, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_34 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_33, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_32 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_21, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_20 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_19, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_18 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_17, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_16 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_14 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_13, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_12 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_81, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_80 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_79, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_78 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_77, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_76 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_75, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_74 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405 (PFU) covers - blocks: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_73, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/FF_72 -genblk1[2].tdc_channel_fifo_out_inst/SLICE_406 (PFU) covers blocks: - fifo_in_data_11_.fb, genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[11] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[0], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[0] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[1], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[1] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[2], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[2] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[3], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[3] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered1[4], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].in_clk_synced[4] - - Page 21 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered1[5], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].in_clk_synced[5] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered1[6], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].in_clk_synced[6] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered1[7], - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].in_clk_synced[7] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[0] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[1] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[2] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[3] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[0].out_buffered[4] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[1].out_buffered[5] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[2].out_buffered[6] -genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431 (PFU) covers blocks: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/genblk1[3].out_buffered[7] -hades_tdc_bundle_inst/SLICE_432 (PFU) covers blocks: buf_finished_RNO, - buf_finished5_0_a2_0, hades_tdc_bundle_inst/buf_finished -hades_tdc_bundle_inst/SLICE_433 (PFU) covers blocks: - hades_tdc_bundle_inst/buf_release -hades_tdc_bundle_inst/SLICE_434 (PFU) covers blocks: coarse_RNI8DE6[0], - drop_cmp_buf_coarse_2_axbxc1, hades_tdc_bundle_inst/coarse[0], - hades_tdc_bundle_inst/coarse[1] -hades_tdc_bundle_inst/SLICE_435 (PFU) covers blocks: - drop_cmp_buf_coarse_2_axbxc2, coarse_RNI6RPP[2], - hades_tdc_bundle_inst/coarse[2], hades_tdc_bundle_inst/coarse[3] -hades_tdc_bundle_inst/SLICE_436 (PFU) covers blocks: - drop_cmp_buf_coarse_2_axbxc4, drop_cmp_buf_coarse_2_axbxc5, - hades_tdc_bundle_inst/coarse[4], hades_tdc_bundle_inst/coarse[5] -hades_tdc_bundle_inst/SLICE_437 (PFU) covers blocks: - drop_cmp_buf_coarse_2_axbxc6, drop_cmp_buf_coarse_2_axbxc7, - hades_tdc_bundle_inst/coarse[6], hades_tdc_bundle_inst/coarse[7] -hades_tdc_bundle_inst/SLICE_438 (PFU) covers blocks: - drop_cmp_buf_coarse_2_axbxc8, drop_cmp_buf_coarse_2_ac0_5, - hades_tdc_bundle_inst/coarse[8] -hades_tdc_bundle_inst/SLICE_439 (PFU) covers blocks: - hades_tdc_bundle_inst/hitbuffer_1_[3], - hades_tdc_bundle_inst/hitbuffer_1_[4] -hades_tdc_bundle_inst/SLICE_440 (PFU) covers blocks: - hades_tdc_bundle_inst/hitbuffer_1_[5], - hades_tdc_bundle_inst/hitbuffer_1_[6] -hades_tdc_bundle_inst/SLICE_441 (PFU) covers blocks: - hades_tdc_bundle_inst/hitbuffer_1_[7], - hades_tdc_bundle_inst/hitbuffer_1_[8] -hades_tdc_bundle_inst/SLICE_442 (PFU) covers blocks: - hades_tdc_bundle_inst/hitbuffer_1_[9], - hades_tdc_bundle_inst/hitbuffer_1_[10] - - Page 22 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/SLICE_443 (PFU) covers blocks: - hades_tdc_bundle_inst/hitbuffer_1_[11] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444 (PFU) covers blocks: - trig_dl_RNI41GL1[3], discard_en, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard -hades_tdc_bundle_inst/SLICE_445 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_1[0], - hades_tdc_bundle_inst/drop_cmp_buf_1[1] -hades_tdc_bundle_inst/SLICE_446 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_1[2], - hades_tdc_bundle_inst/drop_cmp_buf_1[3] -hades_tdc_bundle_inst/SLICE_447 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_1[4], - hades_tdc_bundle_inst/drop_cmp_buf_1[5] -hades_tdc_bundle_inst/SLICE_448 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_1[6], - hades_tdc_bundle_inst/drop_cmp_buf_1[7] -hades_tdc_bundle_inst/SLICE_449 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_1[8] -hades_tdc_bundle_inst/SLICE_450 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[0], - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[1] -hades_tdc_bundle_inst/SLICE_451 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[2], - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[3] -hades_tdc_bundle_inst/SLICE_452 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[4], - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[5] -hades_tdc_bundle_inst/SLICE_453 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[6], - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[7] -hades_tdc_bundle_inst/SLICE_454 (PFU) covers blocks: - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[8] -hades_tdc_bundle_inst/SLICE_455 (PFU) covers blocks: - drop_cmp_buf_coarse_2_ac0_15, drop_cmp_buf_coarse_2_ac0_9_0, - hades_tdc_bundle_inst/drop_cmp_buf_coarse_1[9] -hades_tdc_bundle_inst/SLICE_456 (PFU) covers blocks: drop_cmp_buf_valid_4_iv_i, - hades_tdc_bundle_inst/drop_cmp_buf_valid -hades_tdc_bundle_inst/SLICE_457 (PFU) covers blocks: hit_valid_1_RNO[0], - hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[0] -hades_tdc_bundle_inst/SLICE_458 (PFU) covers blocks: hit_valid_1_RNO[1], - drop_cmp_buf_valid_0_sqmuxa_0_a2, hades_tdc_bundle_inst/hit_valid_1[1] -hades_tdc_bundle_inst/SLICE_459 (PFU) covers blocks: hit_valid_1_RNO[2], - hit_valid_4_i_o2_0[2], hades_tdc_bundle_inst/hit_valid_1[2] -hades_tdc_bundle_inst/SLICE_460 (PFU) covers blocks: hit_valid_1_RNO[3], - SUM1_0_0_o2, hades_tdc_bundle_inst/hit_valid_1[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461 (PFU) covers blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[1], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462 (PFU) covers blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/invalid_dl[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463 (PFU) covers blocks: - offset_valid_RNO, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/offset_valid -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[0], - - Page 23 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[12] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[13], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[14] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[15], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[16] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[17], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[18] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[19], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[20] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[21], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[22] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[23] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483 (PFU) covers - blocks: - - Page 24 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486 (PFU) covers - blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487 (PFU) covers - blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488 (PFU) covers - blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489 (PFU) covers - blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o - ut_buffered1[0], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[0].in_clk_synced[0] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o - ut_buffered1[1], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[1].in_clk_synced[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o - ut_buffered1[2], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[2].in_clk_synced[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o - ut_buffered1[3], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[3].in_clk_synced[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o - ut_buffered1[4], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[0].in_clk_synced[4] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o - ut_buffered1[5], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[1].in_clk_synced[5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o - ut_buffered1[6], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[2].in_clk_synced[6] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o - ut_buffered1[7], hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/gen - blk1[3].in_clk_synced[7] - - Page 25 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o - ut_buffered[0] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o - ut_buffered[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o - ut_buffered[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o - ut_buffered[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].o - ut_buffered[4] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].o - ut_buffered[5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].o - ut_buffered[6] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[3].o - ut_buffered[7] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515 (PFU) covers blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516 (PFU) covers blocks: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518 (PFU) covers blocks: - window_RNO[0], un1_reset_0_a2_2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519 (PFU) covers blocks: - window_6[1], window_6[3], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520 (PFU) covers blocks: - window_0_sqmuxadup, un1_invalid_dl, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521 (PFU) covers blocks: - window_6[4], window_6[5], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522 (PFU) covers blocks: - window_6[6], window_6[7], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6], - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[3], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[4] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[5], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[6] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[7], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[8] - - Page 26 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[9], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[10] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527 (PFU) covers - blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out[11] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528 (PFU) covers - blocks: buf_negative_ready_RNIG7JA, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/raw_out_valid -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535 (PFU) covers - blocks: buf_negative_ready_4_f0_0_0, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540 (PFU) covers - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541 (PFU) covers - - Page 27 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542 (PFU) covers - blocks: buf_positive_ready_4_iv_i_0, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins - t/in_synced[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins - t/in_synced[2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins - t/in_synced[4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins - t/in_synced[6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555 (PFU) - covers blocks: out_internal_2_1_0_.m11_i, un1_out_internal35_1_0_o7, hades_ - - Page 28 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[0] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556 (PFU) - covers blocks: out_internal_2_1_0_.m15_i, out_internal_2_1_0_.m15_i_0, hade - s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557 (PFU) - covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_1, hades_ - tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_internal[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558 (PFU) - covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_tdc_bun - dle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_internal -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_559 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[0][0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_560 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[0][2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_561 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[0][4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_562 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[0][6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_563 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[1][0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[1][2], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[1][4], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/dl[1][6], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_567 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/in_synced[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/in_synced[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_568 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/in_synced[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/in_synced[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_569 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/in_synced[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/in_synced[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_570 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - - Page 29 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - ec_neg_inst/in_synced[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/in_synced[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_571 - (PFU) covers blocks: out_internal_2_1_0_.m11_i, out_internal_2_1_0_.m15_i, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inter - nal[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/o - ut_internal[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572 - (PFU) covers blocks: un1_out_internal31_1_i_0, un1_out_internal31_1_i_0_o5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_inte - rnal[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573 - (PFU) covers blocks: valid_internal_RNO, un1_out_internal35_1_0_m3, hades_t - dc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_internal -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575 (PFU) - covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_576 - (PFU) covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[0], - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_577 - (PFU) covers blocks: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[0].in_clk_synced[0] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[1].in_clk_synced[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[2].in_clk_synced[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[3].in_clk_synced[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[0].in_clk_synced[4] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[1].in_clk_synced[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[2].in_clk_synced[6] - - Page 30 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/genblk1[3].in_clk_synced[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_604 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[0].out_buffered1[0], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[0] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_605 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[1].out_buffered1[1], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_606 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[2].out_buffered1[2], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_607 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[3].out_buffered1[3], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_608 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[0].out_buffered1[4], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[0].in_clk_synced[4] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[1].out_buffered1[5], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[1].in_clk_synced[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[2].out_buffered1[6], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[2].in_clk_synced[6] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[3].out_buffered1[7], hades_tdc_bundle_inst/hades_tdc_ch - annel_raw_out_inst/tdc_neg_inst/genblk1[3].in_clk_synced[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[0].out_buffered[0] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[1].out_buffered[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[2].out_buffered[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[3].out_buffered[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[0].out_buffered[4] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[1].out_buffered[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - - Page 31 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - t/genblk1[2].out_buffered[6] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619 (PFU) - covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ins - t/genblk1[3].out_buffered[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_620 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[0].out_buffered[0] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_621 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[1].out_buffered[1] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_622 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[2].out_buffered[2] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[3].out_buffered[3] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[0].out_buffered[4] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[1].out_buffered[5] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[2].out_buffered[6] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_627 - (PFU) covers blocks: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/t - dc_neg_inst/genblk1[3].out_buffered[7] -hades_tdc_bundle_inst/SLICE_628 (PFU) covers blocks: SUM0_1_0_x2, SUM1_0_0, - hades_tdc_bundle_inst/hit_i[0], hades_tdc_bundle_inst/hit_i[1] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629 (PFU) covers blocks: - window_end5_0_a2, discard4_0_a2_0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end -trb_adapter_inst/SLICE_631 (PFU) covers blocks: - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1], - trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] -trb_adapter_inst/SLICE_632 (PFU) covers blocks: trb_adapter_inst/buf_rden_prev -trb_adapter_inst/SLICE_633 (PFU) covers blocks: trb_adapter_inst/finished_prev -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634 (PFU) covers blocks: - offset_1_sqmuxa_i_0, offset_1_sqmuxa_i_0_o2 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635 (PFU) covers blocks: - un1_reset_0_a2_1, discard4_0_a2_0 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636 (PFU) covers - blocks: LUT4_16, LUT4_23 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637 (PFU) covers - blocks: LUT4_19, LUT4_21 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638 (PFU) covers - blocks: LUT4_6, LUT4_13 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639 (PFU) covers - blocks: LUT4_9, LUT4_11 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640 (PFU) covers - blocks: LUT4_16, LUT4_23 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641 (PFU) covers - blocks: LUT4_19, LUT4_21 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642 (PFU) covers - blocks: LUT4_6, LUT4_13 - - Page 32 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643 (PFU) covers - blocks: LUT4_9, LUT4_11 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644 (PFU) covers - blocks: LUT4_16, LUT4_23 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645 (PFU) covers - blocks: LUT4_19, LUT4_21 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646 (PFU) covers - blocks: LUT4_6, LUT4_13 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647 (PFU) covers - blocks: LUT4_9, LUT4_11 -fifo_colector_inst/fifo40_inst/SLICE_648 (PFU) covers blocks: LUT4_6, LUT4_13 -fifo_colector_inst/fifo40_inst/SLICE_649 (PFU) covers blocks: LUT4_9, LUT4_11 -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650 (PFU) covers blocks: - un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0 -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651 (PFU) covers blocks: - un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0 -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652 (PFU) covers blocks: - un1_out_internal35_1_0_0, un1_out_internal35_1_0_m4_0 -hades_tdc_bundle_inst/SLICE_653 (PFU) covers blocks: - hit_valid_pmux_iv_0_a2_2_RNITDG11, hit_valid_pmux_iv_0_a2_2 -hades_tdc_bundle_inst/SLICE_654 (PFU) covers blocks: hit_valid_pmux_iv_0_0, - hit_valid_pmux_iv_0_a2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655 (PFU) covers - blocks: LUT4_23, LUT4_14 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656 (PFU) covers - blocks: LUT4_22, LUT4_15 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657 (PFU) covers - blocks: LUT4_20, LUT4_18 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658 (PFU) covers - blocks: LUT4_13, LUT4_4 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659 (PFU) covers - blocks: LUT4_12, LUT4_5 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660 (PFU) covers - blocks: LUT4_10, LUT4_8 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661 (PFU) covers - blocks: LUT4_23, LUT4_14 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662 (PFU) covers - blocks: LUT4_22, LUT4_15 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663 (PFU) covers - blocks: LUT4_20, LUT4_18 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664 (PFU) covers - blocks: LUT4_13, LUT4_4 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665 (PFU) covers - blocks: LUT4_12, LUT4_5 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666 (PFU) covers - blocks: LUT4_10, LUT4_8 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667 (PFU) covers - blocks: LUT4_23, LUT4_14 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668 (PFU) covers - blocks: LUT4_22, LUT4_15 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669 (PFU) covers - blocks: LUT4_20, LUT4_18 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670 (PFU) covers - blocks: LUT4_13, LUT4_4 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671 (PFU) covers - blocks: LUT4_12, LUT4_5 - - Page 33 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672 (PFU) covers - blocks: LUT4_10, LUT4_8 -fifo_colector_inst/fifo40_inst/SLICE_673 (PFU) covers blocks: LUT4_23, LUT4_14 -fifo_colector_inst/fifo40_inst/SLICE_674 (PFU) covers blocks: LUT4_22, LUT4_15 -fifo_colector_inst/fifo40_inst/SLICE_675 (PFU) covers blocks: LUT4_21, LUT4_19 -fifo_colector_inst/fifo40_inst/SLICE_676 (PFU) covers blocks: LUT4_20, LUT4_18 -fifo_colector_inst/fifo40_inst/SLICE_677 (PFU) covers blocks: LUT4_13, LUT4_4 -fifo_colector_inst/fifo40_inst/SLICE_678 (PFU) covers blocks: LUT4_12, LUT4_5 -fifo_colector_inst/fifo40_inst/SLICE_679 (PFU) covers blocks: LUT4_10, LUT4_8 -fifo_colector_inst/SLICE_680 (PFU) covers blocks: in_empty_pmux_u, - in_empty_pmux_0 -hades_tdc_bundle_inst/SLICE_681 (PFU) covers blocks: - un1_buf_positive_0_I_9_0_RNO_0, drop_cmp_buf_coarse_2_ac0_3 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682 (PFU) covers blocks: - un1_reset_0_a2_c, discard4_0_a2_0 -hades_tdc_bundle_inst/SLICE_683 (PFU) covers blocks: buf_out12, - hit_valid_pmux_iv_0_a2_2 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684 (PFU) covers blocks: - discard4_0_a2_0_3, window_RNIOA5C[2] -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685 (PFU) covers - blocks: LUT4_3, LUT4_2 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686 (PFU) covers - blocks: LUT4_1, LUT4_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687 (PFU) covers - blocks: LUT4_3, LUT4_2 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688 (PFU) covers - blocks: LUT4_1, LUT4_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689 (PFU) covers - blocks: LUT4_3, LUT4_2 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690 (PFU) covers - blocks: LUT4_1, LUT4_0 -fifo_colector_inst/fifo40_inst/SLICE_691 (PFU) covers blocks: LUT4_0, LUT4_1 -fifo_colector_inst/fifo40_inst/SLICE_692 (PFU) covers blocks: LUT4_3, LUT4_2 -hades_tdc_bundle_inst/SLICE_693 (PFU) covers blocks: un1_hit_i_2_0_a2, - SUM1_0_0_o2_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_694 - (PFU) covers blocks: un1_out_internal35_1_0_o5, out_internal_2_1_0_.m15_i_1 - -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695 (PFU) - covers blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696 (PFU) - covers blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697 (PFU) covers - blocks: un1_coarse_1_0_I_9_0_RNO, un1_buf_positive_0_I_9_0_RNO -hades_tdc_bundle_inst/SLICE_698 (PFU) covers blocks: un1_coarse_1_0_I_9_RNO_0, - drop_cmp_buf_coarse_2_ac0_7 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699 (PFU) covers - blocks: out_internal_2_1_0_.m15_i_3, out_internal_2_1_0_.m11_i_1 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700 (PFU) covers - blocks: un1_out_internal35_1_0_m3, out_internal_2_1_0_.m11_i_1_0 -hades_tdc_bundle_inst/SLICE_701 (PFU) covers blocks: - drop_cmp_buf_coarse_2_ac0_13_0, drop_cmp_buf_coarse_2_ac0_9_0 -fifo_colector_inst/fifo40_inst/SLICE_702 (PFU) covers blocks: LUT4_16, LUT4_17 -fifo_colector_inst/fifo40_inst/SLICE_703 (PFU) covers blocks: LUT4_7, LUT4_11 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704 (PFU) covers - blocks: LUT4_7, LUT4_11 - - Page 34 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705 (PFU) covers - blocks: LUT4_17, LUT4_21 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706 (PFU) covers - blocks: LUT4_7, LUT4_11 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707 (PFU) covers - blocks: LUT4_17, LUT4_21 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708 (PFU) covers - blocks: LUT4_7, LUT4_11 -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709 (PFU) covers - blocks: LUT4_17, LUT4_21 -hades_tdc_bundle_inst/SLICE_710 (PFU) covers blocks: hit_valid_pmux_iv_0_m2, - drop_cmp_buf_valid_0_sqmuxa_0_a2 -genblk1[2].tdc_channel_fifo_out_inst/SLICE_711 (PFU) covers blocks: AND2_t20, - genblk1[2].tdc_channel_fifo_out_inst/fifo_wren -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712 (PFU) covers - blocks: AND2_t19 -genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713 (PFU) covers blocks: - valid_internal_RNO_0 -genblk1[1].tdc_channel_fifo_out_inst/SLICE_714 (PFU) covers blocks: AND2_t20, - genblk1[1].tdc_channel_fifo_out_inst/fifo_wren -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715 (PFU) covers - blocks: AND2_t19 -genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716 (PFU) covers blocks: - valid_internal_RNO_0 -genblk1[0].tdc_channel_fifo_out_inst/SLICE_717 (PFU) covers blocks: AND2_t20, - genblk1[0].tdc_channel_fifo_out_inst/fifo_wren -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718 (PFU) covers - blocks: AND2_t19 -genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719 (PFU) covers blocks: - valid_internal_RNO_0 -fifo_colector_inst/fifo40_inst/SLICE_720 (PFU) covers blocks: AND2_t19 -fifo_colector_inst/fifo40_inst/SLICE_721 (PFU) covers blocks: AND2_t20 -fifo_colector_inst/SLICE_722 (PFU) covers blocks: iterator_RNI7U5I[1] -trb_adapter_inst/SLICE_723 (PFU) covers blocks: LVL1_TRG_DATA_VALI_IN_rising -trb_adapter_inst/SLICE_724 (PFU) covers blocks: release_out, - trb_adapter_inst/finished -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725 - (PFU) covers blocks: valid_RNI97O31, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_726 - (PFU) covers blocks: in_synced_RNIT1GT[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_727 - (PFU) covers blocks: un1_out_internal35_1_0_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_728 - (PFU) covers blocks: out_internal_2_1_0_.m11_i_0 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729 - (PFU) covers blocks: out_internal_2_1_0_.m11_i_m3 -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730 (PFU) - covers blocks: in_synced_RNIB4EQ[7] -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731 (PFU) - covers blocks: valid_RNI8UMR, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid -hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732 (PFU) - covers blocks: un1_out_internal35_1_0_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733 (PFU) covers - blocks: valid_fast_RNI999V - - Page 35 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734 (PFU) covers - blocks: in_synced_RNI3HPF[7] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735 (PFU) covers - blocks: un1_out_internal35_1_0_0 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736 (PFU) covers - blocks: valid_fast_RNI5DQ71, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_fast -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737 (PFU) covers blocks: - un1_reset_0_a2_2 -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738 (PFU) covers blocks: - window_6[2] -hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739 (PFU) covers blocks: - window_RNICU4C[3] -SLICE_740 (PFU) covers blocks: drop_cmp_buf_0_sqmuxa_0_a2, reset_dl[2] -hades_tdc_bundle_inst/SLICE_741 (PFU) covers blocks: hit_out_i_6_i_a2_0[0] -pll0inst/SLICE_742 (PFU) covers blocks: GND -SLICE_743 (PFU) covers blocks: hades_lvl1_pad_RNINMH5 -SLICE_744 (PFU) covers blocks: trig_pad_RNII4FF[0] -SLICE_745 (PFU) covers blocks: trig_pad_RNIJ5FF[1] -SLICE_746 (PFU) covers blocks: trig_pad_RNIK6FF[2] -SLICE_747 (PFU) covers blocks: hades_trig_pad_RNIE1B4 -hades_raw_valid_vect[0] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[0] -fifo_data_out[0] (PIC/PIO) covers blocks: fifo_data_out_pad[0] -clk (PIC/PIO) covers blocks: clk_pad -hades_drop_cmp_buf_valid (PIC/PIO) covers blocks: hades_drop_cmp_buf_valid_pad -hades_drop_cmp_buf_coarse[11] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[11] -hades_drop_cmp_buf_coarse[10] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[10] -hades_drop_cmp_buf_coarse[9] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[9] -hades_drop_cmp_buf_coarse[8] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[8] -hades_drop_cmp_buf_coarse[7] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[7] -hades_drop_cmp_buf_coarse[6] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[6] -hades_drop_cmp_buf_coarse[5] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[5] -hades_drop_cmp_buf_coarse[4] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[4] -hades_drop_cmp_buf_coarse[3] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[3] -hades_drop_cmp_buf_coarse[2] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[2] -hades_drop_cmp_buf_coarse[1] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[1] -hades_drop_cmp_buf_coarse[0] (PIC/PIO) covers blocks: - hades_drop_cmp_buf_coarse_pad[0] -hades_drop_cmp_buf[11] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[11] -hades_drop_cmp_buf[10] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[10] -hades_drop_cmp_buf[9] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[9] -hades_drop_cmp_buf[8] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[8] -hades_drop_cmp_buf[7] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[7] -hades_drop_cmp_buf[6] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[6] -hades_drop_cmp_buf[5] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[5] - - Page 36 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -hades_drop_cmp_buf[4] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[4] -hades_drop_cmp_buf[3] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[3] -hades_drop_cmp_buf[2] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[2] -hades_drop_cmp_buf[1] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[1] -hades_drop_cmp_buf[0] (PIC/PIO) covers blocks: hades_drop_cmp_buf_pad[0] -hades_dbg2_coarse[8] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[8] -hades_dbg2_coarse[7] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[7] -hades_dbg2_coarse[6] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[6] -hades_dbg2_coarse[5] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[5] -hades_dbg2_coarse[4] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[4] -hades_dbg2_coarse[3] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[3] -hades_dbg2_coarse[2] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[2] -hades_dbg2_coarse[1] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[1] -hades_dbg2_coarse[0] (PIC/PIO) covers blocks: hades_dbg2_coarse_pad[0] -hades_dbg2_out[31] (PIC/PIO) covers blocks: hades_dbg2_out_pad[31] -hades_dbg2_out[30] (PIC/PIO) covers blocks: hades_dbg2_out_pad[30] -hades_dbg2_out[29] (PIC/PIO) covers blocks: hades_dbg2_out_pad[29] -hades_dbg2_out[28] (PIC/PIO) covers blocks: hades_dbg2_out_pad[28], - hades_tdc_bundle_inst_hitbuffer_1_io[23] -hades_dbg2_out[27] (PIC/PIO) covers blocks: hades_dbg2_out_pad[27], - hades_tdc_bundle_inst_hitbuffer_1_io[22] -hades_dbg2_out[26] (PIC/PIO) covers blocks: hades_dbg2_out_pad[26], - hades_tdc_bundle_inst_hitbuffer_1_io[21] -hades_dbg2_out[25] (PIC/PIO) covers blocks: hades_dbg2_out_pad[25], - hades_tdc_bundle_inst_hitbuffer_1_io[20] -hades_dbg2_out[24] (PIC/PIO) covers blocks: hades_dbg2_out_pad[24], - hades_tdc_bundle_inst_hitbuffer_1_io[19] -hades_dbg2_out[23] (PIC/PIO) covers blocks: hades_dbg2_out_pad[23], - hades_tdc_bundle_inst_hitbuffer_1_io[18] -hades_dbg2_out[22] (PIC/PIO) covers blocks: hades_dbg2_out_pad[22], - hades_tdc_bundle_inst_hitbuffer_1_io[17] -hades_dbg2_out[21] (PIC/PIO) covers blocks: hades_dbg2_out_pad[21], - hades_tdc_bundle_inst_hitbuffer_1_io[16] -hades_dbg2_out[20] (PIC/PIO) covers blocks: hades_dbg2_out_pad[20], - hades_tdc_bundle_inst_hitbuffer_1_io[15] -hades_dbg2_out[19] (PIC/PIO) covers blocks: hades_dbg2_out_pad[19] -hades_dbg2_out[18] (PIC/PIO) covers blocks: hades_dbg2_out_pad[18], - hades_tdc_bundle_inst_hitbuffer_1_io[14] -hades_dbg2_out[17] (PIC/PIO) covers blocks: hades_dbg2_out_pad[17], - hades_tdc_bundle_inst_hitbuffer_1_io[13] -hades_dbg2_out[16] (PIC/PIO) covers blocks: hades_dbg2_out_pad[16], - hades_tdc_bundle_inst_hitbuffer_1_io[12] -hades_dbg2_out[15] (PIC/PIO) covers blocks: hades_dbg2_out_pad[15] -hades_dbg2_out[14] (PIC/PIO) covers blocks: hades_dbg2_out_pad[14] -hades_dbg2_out[13] (PIC/PIO) covers blocks: hades_dbg2_out_pad[13] -hades_dbg2_out[12] (PIC/PIO) covers blocks: hades_dbg2_out_pad[12] -hades_dbg2_out[11] (PIC/PIO) covers blocks: hades_dbg2_out_pad[11] -hades_dbg2_out[10] (PIC/PIO) covers blocks: hades_dbg2_out_pad[10] -hades_dbg2_out[9] (PIC/PIO) covers blocks: hades_dbg2_out_pad[9] -hades_dbg2_out[8] (PIC/PIO) covers blocks: hades_dbg2_out_pad[8] -hades_dbg2_out[7] (PIC/PIO) covers blocks: hades_dbg2_out_pad[7] -hades_dbg2_out[6] (PIC/PIO) covers blocks: hades_dbg2_out_pad[6] -hades_dbg2_out[5] (PIC/PIO) covers blocks: hades_dbg2_out_pad[5] -hades_dbg2_out[4] (PIC/PIO) covers blocks: hades_dbg2_out_pad[4] -hades_dbg2_out[3] (PIC/PIO) covers blocks: hades_dbg2_out_pad[3] -hades_dbg2_out[2] (PIC/PIO) covers blocks: hades_dbg2_out_pad[2], - - Page 37 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst_hitbuffer_1_io[2] -hades_dbg2_out[1] (PIC/PIO) covers blocks: hades_dbg2_out_pad[1], - hades_tdc_bundle_inst_hitbuffer_1_io[1] -hades_dbg2_out[0] (PIC/PIO) covers blocks: hades_dbg2_out_pad[0], - hades_tdc_bundle_inst_hitbuffer_1_io[0] -hades_buf_drop[3] (PIC/PIO) covers blocks: hades_buf_drop_pad[3] -hades_buf_drop[2] (PIC/PIO) covers blocks: hades_buf_drop_pad[2] -hades_buf_drop[1] (PIC/PIO) covers blocks: hades_buf_drop_pad[1], - hades_tdc_bundle_inst_buf_drop_1io[1] -hades_buf_drop[0] (PIC/PIO) covers blocks: hades_buf_drop_pad[0] -hades_invalid_dl[3] (PIC/PIO) covers blocks: hades_invalid_dl_pad[3] -hades_invalid_dl[2] (PIC/PIO) covers blocks: hades_invalid_dl_pad[2] -hades_invalid_dl[1] (PIC/PIO) covers blocks: hades_invalid_dl_pad[1] -hades_invalid_dl[0] (PIC/PIO) covers blocks: hades_invalid_dl_pad[0] -hades_discard (PIC/PIO) covers blocks: hades_discard_pad -hades_hit_valid[3] (PIC/PIO) covers blocks: hades_hit_valid_pad[3] -hades_hit_valid[2] (PIC/PIO) covers blocks: hades_hit_valid_pad[2] -hades_hit_valid[1] (PIC/PIO) covers blocks: hades_hit_valid_pad[1] -hades_hit_valid[0] (PIC/PIO) covers blocks: hades_hit_valid_pad[0] -hades_hit_out_i[3] (PIC/PIO) covers blocks: hades_hit_out_i_pad[3] -hades_hit_out_i[2] (PIC/PIO) covers blocks: hades_hit_out_i_pad[2] -hades_hit_out_i[1] (PIC/PIO) covers blocks: hades_hit_out_i_pad[1] -hades_hit_out_i[0] (PIC/PIO) covers blocks: hades_hit_out_i_pad[0] -hades_buf_finished (PIC/PIO) covers blocks: hades_buf_finished_pad -hades_buf_release (PIC/PIO) covers blocks: hades_buf_release_pad -hades_buf_out_valid (PIC/PIO) covers blocks: hades_buf_out_valid_pad, - hades_tdc_bundle_inst_buf_out_validio -hades_window_end (PIC/PIO) covers blocks: hades_window_end_pad -hades_offset_valid (PIC/PIO) covers blocks: hades_offset_valid_pad -hades_offset[8] (PIC/PIO) covers blocks: hades_offset_pad[8], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[8] -hades_offset[7] (PIC/PIO) covers blocks: hades_offset_pad[7], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[7] -hades_offset[6] (PIC/PIO) covers blocks: hades_offset_pad[6], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[6] -hades_offset[5] (PIC/PIO) covers blocks: hades_offset_pad[5], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[5] -hades_offset[4] (PIC/PIO) covers blocks: hades_offset_pad[4], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[4] -hades_offset[3] (PIC/PIO) covers blocks: hades_offset_pad[3], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[3] -hades_offset[2] (PIC/PIO) covers blocks: hades_offset_pad[2], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[2] -hades_offset[1] (PIC/PIO) covers blocks: hades_offset_pad[1], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[1] -hades_offset[0] (PIC/PIO) covers blocks: hades_offset_pad[0], - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_offsetio[0] -hades_lvl1_invalid (PIC/PIO) covers blocks: hades_lvl1_invalid_pad, - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_invalid_dlio[0] -hades_lvl1 (PIC/PIO) covers blocks: hades_lvl1_pad, - hades_tdc_bundle_inst_hades_LVL1_raw_out_inst_trig_dlio[0] -hades_raw_valid_vect[1] (PIC/PIO) covers blocks: hades_raw_valid_vect_pad[1] -hades_raw_out_valid (PIC/PIO) covers blocks: hades_raw_out_valid_pad, - hades_tdc_bundle_inst_referenced_out_validio -hades_trig (PIC/PIO) covers blocks: hades_trig_pad -release_out (PIC/PIO) covers blocks: release_out_pad - - Page 38 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -finished (PIC/PIO) covers blocks: finished_pad -last_buf_empty (PIC/PIO) covers blocks: last_buf_empty_pad -discard (PIC/PIO) covers blocks: discard_pad -burst (PIC/PIO) covers blocks: burst_pad -LVL1_TRG_DATA_VALI_IN_rising (PIC/PIO) covers blocks: - LVL1_TRG_DATA_VALI_IN_rising_pad -FEE_TRG_RELEASE_OUT (PIC/PIO) covers blocks: FEE_TRG_RELEASE_OUT_pad, - trb_adapter_inst_FEE_TRG_RELEASE_OUTio -FEE_DATAFINISHED_OUT (PIC/PIO) covers blocks: FEE_DATAFINISHED_OUT_pad, - trb_adapter_inst_FEE_DATAFINISHED_OUTio -FEE_DATA_WRITE_OUT (PIC/PIO) covers blocks: FEE_DATA_WRITE_OUT_pad, - trb_adapter_inst_FEE_DATA_WRITE_OUTio -FEE_DATA_OUT[31] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[31] -FEE_DATA_OUT[30] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[30] -FEE_DATA_OUT[29] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[29] -FEE_DATA_OUT[28] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[28] -FEE_DATA_OUT[27] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[27] -FEE_DATA_OUT[26] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[26] -FEE_DATA_OUT[25] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[25] -FEE_DATA_OUT[24] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[24] -FEE_DATA_OUT[23] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[23] -FEE_DATA_OUT[22] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[22] -FEE_DATA_OUT[21] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[21] -FEE_DATA_OUT[20] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[20] -FEE_DATA_OUT[19] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[19] -FEE_DATA_OUT[18] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[18] -FEE_DATA_OUT[17] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[17] -FEE_DATA_OUT[16] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[16] -FEE_DATA_OUT[15] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[15] -FEE_DATA_OUT[14] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[14] -FEE_DATA_OUT[13] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[13] -FEE_DATA_OUT[12] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[12] -FEE_DATA_OUT[11] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[11] -FEE_DATA_OUT[10] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[10] -FEE_DATA_OUT[9] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[9] -FEE_DATA_OUT[8] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[8] -FEE_DATA_OUT[7] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[7] -FEE_DATA_OUT[6] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[6] -FEE_DATA_OUT[5] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[5] -FEE_DATA_OUT[4] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[4] -FEE_DATA_OUT[3] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[3] -FEE_DATA_OUT[2] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[2] -FEE_DATA_OUT[1] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[1] -FEE_DATA_OUT[0] (PIC/PIO) covers blocks: FEE_DATA_OUT_pad[0] -LVL1_INVALID_TRG_IN (PIC/PIO) covers blocks: LVL1_INVALID_TRG_IN_pad, - trb_adapter_inst_LVL1_INVALID_TRG_IN_dlio[0] -LVL1_TRG_DATA_VALID_IN (PIC/PIO) covers blocks: LVL1_TRG_DATA_VALID_IN_pad, - trb_adapter_inst_LVL1_TRG_DATA_VALID_IN_dlio[0] -fifo_empty1 (PIC/PIO) covers blocks: fifo_empty1_pad -fifo_rden (PIC/PIO) covers blocks: fifo_rden_pad -fifo_data_out[31] (PIC/PIO) covers blocks: fifo_data_out_pad[31] -fifo_data_out[30] (PIC/PIO) covers blocks: fifo_data_out_pad[30] -fifo_data_out[29] (PIC/PIO) covers blocks: fifo_data_out_pad[29] -fifo_data_out[28] (PIC/PIO) covers blocks: fifo_data_out_pad[28] -fifo_data_out[27] (PIC/PIO) covers blocks: fifo_data_out_pad[27] -fifo_data_out[26] (PIC/PIO) covers blocks: fifo_data_out_pad[26] - - Page 39 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Symbol Cross Reference (cont) ------------------------------ -fifo_data_out[25] (PIC/PIO) covers blocks: fifo_data_out_pad[25] -fifo_data_out[24] (PIC/PIO) covers blocks: fifo_data_out_pad[24] -fifo_data_out[23] (PIC/PIO) covers blocks: fifo_data_out_pad[23] -fifo_data_out[22] (PIC/PIO) covers blocks: fifo_data_out_pad[22] -fifo_data_out[21] (PIC/PIO) covers blocks: fifo_data_out_pad[21] -fifo_data_out[20] (PIC/PIO) covers blocks: fifo_data_out_pad[20] -fifo_data_out[19] (PIC/PIO) covers blocks: fifo_data_out_pad[19] -fifo_data_out[18] (PIC/PIO) covers blocks: fifo_data_out_pad[18] -fifo_data_out[17] (PIC/PIO) covers blocks: fifo_data_out_pad[17] -fifo_data_out[16] (PIC/PIO) covers blocks: fifo_data_out_pad[16] -fifo_data_out[15] (PIC/PIO) covers blocks: fifo_data_out_pad[15] -fifo_data_out[14] (PIC/PIO) covers blocks: fifo_data_out_pad[14] -fifo_data_out[13] (PIC/PIO) covers blocks: fifo_data_out_pad[13] -fifo_data_out[12] (PIC/PIO) covers blocks: fifo_data_out_pad[12] -fifo_data_out[11] (PIC/PIO) covers blocks: fifo_data_out_pad[11] -fifo_data_out[10] (PIC/PIO) covers blocks: fifo_data_out_pad[10] -fifo_data_out[9] (PIC/PIO) covers blocks: fifo_data_out_pad[9] -fifo_data_out[8] (PIC/PIO) covers blocks: fifo_data_out_pad[8] -fifo_data_out[7] (PIC/PIO) covers blocks: fifo_data_out_pad[7] -fifo_data_out[6] (PIC/PIO) covers blocks: fifo_data_out_pad[6] -fifo_data_out[5] (PIC/PIO) covers blocks: fifo_data_out_pad[5] -fifo_data_out[4] (PIC/PIO) covers blocks: fifo_data_out_pad[4] -fifo_data_out[3] (PIC/PIO) covers blocks: fifo_data_out_pad[3] -fifo_data_out[2] (PIC/PIO) covers blocks: fifo_data_out_pad[2] -fifo_data_out[1] (PIC/PIO) covers blocks: fifo_data_out_pad[1] -trig[2] (PIC/PIO) covers blocks: trig_pad[2] -trig[1] (PIC/PIO) covers blocks: trig_pad[1] -trig[0] (PIC/PIO) covers blocks: trig_pad[0] -reset_dc (PIC/PIO) covers blocks: reset_dc_pad, reset_dl_0io[1] -rd_clk (PIC/PIO) covers blocks: rd_clk_pad -genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD) - covers block: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 -genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD) - covers block: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 -genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 (PDPW16KD) - covers block: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 -fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 (PDPW16KD) covers block: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 -pll0inst/PLLInst_0 (EHXPLLL) covers block: pll0inst/PLLInst_0 - - -Signal Cross Reference ----------------------- - -Signal FEE_DATA_OUT_c[0] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO18 - Load Comps: fifo_data_out[0]:I0, FEE_DATA_OUT[0]:I0 -Signal clk_c - Driver Comp: clk:O0 - Load Comps: pll0inst/PLLInst_0:CLKI -Signal reset_dl[1] - Driver Comp: reset_dc_MGIOL:O2 - Load Comps: SLICE_740:I4 -Signal pll_clks[3] - Driver Comp: pll0inst/PLLInst_0:CLKOS3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I15, - - Page 40 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I15, - fifo_colector_inst/fifo40_inst/SLICE_79:I15, - fifo_colector_inst/fifo40_inst/SLICE_80:I15, - fifo_colector_inst/fifo40_inst/SLICE_81:I15, - fifo_colector_inst/fifo40_inst/SLICE_82:I15, - fifo_colector_inst/fifo40_inst/SLICE_83:I15, - fifo_colector_inst/fifo40_inst/SLICE_103:I15, - hades_tdc_bundle_inst/SLICE_121:I15, - hades_tdc_bundle_inst/SLICE_122:I15, - hades_tdc_bundle_inst/SLICE_123:I15, fifo_colector_inst/SLICE_125:I15, - fifo_colector_inst/SLICE_126:I15, fifo_colector_inst/SLICE_127:I15, - fifo_colector_inst/SLICE_128:I15, fifo_colector_inst/SLICE_129:I15, - fifo_colector_inst/SLICE_130:I15, fifo_colector_inst/SLICE_131:I15, - fifo_colector_inst/SLICE_132:I15, fifo_colector_inst/SLICE_133:I15, - fifo_colector_inst/SLICE_134:I15, fifo_colector_inst/SLICE_135:I15, - fifo_colector_inst/SLICE_136:I15, fifo_colector_inst/SLICE_137:I15, - fifo_colector_inst/SLICE_138:I15, fifo_colector_inst/SLICE_139:I15, - fifo_colector_inst/SLICE_140:I15, fifo_colector_inst/SLICE_141:I15, - fifo_colector_inst/SLICE_142:I15, fifo_colector_inst/SLICE_143:I15, - fifo_colector_inst/SLICE_144:I15, fifo_colector_inst/SLICE_145:I15, - fifo_colector_inst/SLICE_146:I15, - fifo_colector_inst/fifo40_inst/SLICE_152:I15, - - Page 41 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_153:I15, - fifo_colector_inst/fifo40_inst/SLICE_154:I15, - fifo_colector_inst/fifo40_inst/SLICE_155:I15, - fifo_colector_inst/fifo40_inst/SLICE_156:I15, - fifo_colector_inst/fifo40_inst/SLICE_157:I15, - fifo_colector_inst/fifo40_inst/SLICE_158:I15, - fifo_colector_inst/fifo40_inst/SLICE_159:I15, - fifo_colector_inst/fifo40_inst/SLICE_160:I15, - fifo_colector_inst/fifo40_inst/SLICE_161:I15, - fifo_colector_inst/fifo40_inst/SLICE_167:I15, - fifo_colector_inst/fifo40_inst/SLICE_168:I15, - fifo_colector_inst/fifo40_inst/SLICE_169:I15, - fifo_colector_inst/fifo40_inst/SLICE_170:I15, - fifo_colector_inst/fifo40_inst/SLICE_171:I15, - fifo_colector_inst/fifo40_inst/SLICE_182:I15, - fifo_colector_inst/fifo40_inst/SLICE_183:I15, - fifo_colector_inst/fifo40_inst/SLICE_184:I15, - fifo_colector_inst/fifo40_inst/SLICE_185:I15, - fifo_colector_inst/fifo40_inst/SLICE_186:I15, - fifo_colector_inst/SLICE_187:I15, fifo_colector_inst/SLICE_189:I15, - fifo_colector_inst/SLICE_190:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I15, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I15, - - Page 42 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I15, - genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I15, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I15, - - Page 43 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I15, - genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I15, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I15, - - Page 44 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I15, - genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I15, - hades_tdc_bundle_inst/SLICE_432:I15, - hades_tdc_bundle_inst/SLICE_433:I15, - hades_tdc_bundle_inst/SLICE_434:I15, - hades_tdc_bundle_inst/SLICE_435:I15, - hades_tdc_bundle_inst/SLICE_436:I15, - hades_tdc_bundle_inst/SLICE_437:I15, - hades_tdc_bundle_inst/SLICE_438:I15, - hades_tdc_bundle_inst/SLICE_439:I15, - hades_tdc_bundle_inst/SLICE_440:I15, - hades_tdc_bundle_inst/SLICE_441:I15, - hades_tdc_bundle_inst/SLICE_442:I15, - hades_tdc_bundle_inst/SLICE_443:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I15, - hades_tdc_bundle_inst/SLICE_445:I15, - hades_tdc_bundle_inst/SLICE_446:I15, - hades_tdc_bundle_inst/SLICE_447:I15, - hades_tdc_bundle_inst/SLICE_448:I15, - hades_tdc_bundle_inst/SLICE_449:I15, - hades_tdc_bundle_inst/SLICE_450:I15, - hades_tdc_bundle_inst/SLICE_451:I15, - hades_tdc_bundle_inst/SLICE_452:I15, - hades_tdc_bundle_inst/SLICE_453:I15, - hades_tdc_bundle_inst/SLICE_454:I15, - hades_tdc_bundle_inst/SLICE_455:I15, - hades_tdc_bundle_inst/SLICE_456:I15, - hades_tdc_bundle_inst/SLICE_457:I15, - - Page 45 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/SLICE_458:I15, - hades_tdc_bundle_inst/SLICE_459:I15, - hades_tdc_bundle_inst/SLICE_460:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I15, - - Page 46 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I15, hade - s_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544 - :I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLIC - E_545:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_546:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec - _inst/SLICE_547:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins - t/dec_inst/SLICE_548:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou - t_inst/dec_inst/SLICE_549:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_inst/SLICE_550:I15, hades_tdc_bundle_inst/hades_tdc_chan - nel_raw_out_inst/dec_inst/SLICE_551:I15, hades_tdc_bundle_inst/hades_tdc - _channel_raw_out_inst/dec_inst/SLICE_552:I15, hades_tdc_bundle_inst/hade - s_tdc_channel_raw_out_inst/dec_inst/SLICE_553:I15, hades_tdc_bundle_inst - /hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:I15, hades_tdc_bundle - _inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:I15, hades_tdc_b - undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:I15, hades_ - tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:I15, h - ades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:I - 15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL - ICE_559:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne - g_inst/SLICE_560:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/dec_neg_inst/SLICE_561:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_562:I15, hades_tdc_bundle_inst/hades_tdc_ - channel_raw_out_inst/dec_neg_inst/SLICE_563:I15, hades_tdc_bundle_inst/h - ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_564:I15, hades_tdc_bund - le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_565:I15, hades - _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_566:I - 15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SL - ICE_567:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ne - g_inst/SLICE_568:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/dec_neg_inst/SLICE_569:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_570:I15, hades_tdc_bundle_inst/hades_tdc_ - channel_raw_out_inst/dec_neg_inst/SLICE_571:I15, hades_tdc_bundle_inst/h - ades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_572:I15, hades_tdc_bund - le_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_573:I15, hades - _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:I15, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575: - I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/S - LICE_576:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_n - eg_inst/SLICE_577:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/tdc_inst/SLICE_591:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/tdc_inst/SLICE_595:I15, hades_tdc_bundle_inst/hades_tdc_channel - _raw_out_inst/tdc_neg_inst/SLICE_607:I15, hades_tdc_bundle_inst/hades_td - c_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I15, hades_tdc_bundle_inst - /hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:I15, hades_tdc_bundle - _inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:I15, hades_tdc_b - undle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_623:I15, ha - des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_62 - 7:I15, hades_tdc_bundle_inst/SLICE_628:I15, - - Page 47 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I15, - genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I15, - genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I15, - genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I15, hades_tdc_bundle_ins - t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I15, hades_tdc_b - undle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I15, - SLICE_740:I15, hades_dbg2_out[28]_MGIOL:I6, hades_dbg2_out[27]_MGIOL:I6, - hades_dbg2_out[26]_MGIOL:I6, hades_dbg2_out[25]_MGIOL:I6, - hades_dbg2_out[24]_MGIOL:I6, hades_dbg2_out[23]_MGIOL:I6, - hades_dbg2_out[22]_MGIOL:I6, hades_dbg2_out[21]_MGIOL:I6, - hades_dbg2_out[20]_MGIOL:I6, hades_dbg2_out[18]_MGIOL:I6, - hades_dbg2_out[17]_MGIOL:I6, hades_dbg2_out[16]_MGIOL:I6, - hades_dbg2_out[2]_MGIOL:I6, hades_dbg2_out[1]_MGIOL:I6, - hades_dbg2_out[0]_MGIOL:I6, hades_buf_drop[1]_MGIOL:I6, - hades_buf_out_valid_MGIOL:I6, hades_offset[8]_MGIOL:I6, - hades_offset[7]_MGIOL:I6, hades_offset[6]_MGIOL:I6, - hades_offset[5]_MGIOL:I6, hades_offset[4]_MGIOL:I6, - hades_offset[3]_MGIOL:I6, hades_offset[2]_MGIOL:I6, - hades_offset[1]_MGIOL:I6, hades_offset[0]_MGIOL:I6, - hades_lvl1_invalid_MGIOL:I6, hades_lvl1_MGIOL:I6, - hades_raw_out_valid_MGIOL:I6, reset_dc_MGIOL:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKW, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CLKR, - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKW -Signal reset_dl[2] - Driver Comp: SLICE_740:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I16, - hades_tdc_bundle_inst/SLICE_122:I16, - hades_tdc_bundle_inst/SLICE_123:I16, - genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I16, - genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I16, - genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I16, - hades_tdc_bundle_inst/SLICE_432:I16, - hades_tdc_bundle_inst/SLICE_433:I16, - hades_tdc_bundle_inst/SLICE_434:I16, - hades_tdc_bundle_inst/SLICE_435:I16, - hades_tdc_bundle_inst/SLICE_436:I16, - hades_tdc_bundle_inst/SLICE_437:I16, - hades_tdc_bundle_inst/SLICE_438:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I16, - hades_tdc_bundle_inst/SLICE_456:I14, - hades_tdc_bundle_inst/SLICE_457:I14, - hades_tdc_bundle_inst/SLICE_458:I14, - hades_tdc_bundle_inst/SLICE_459:I14, - hades_tdc_bundle_inst/SLICE_460:I14, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I16, - - Page 48 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I9, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I16, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I14, - hades_tdc_bundle_inst/SLICE_628:I16, hades_tdc_bundle_inst/SLICE_653:I4, - hades_tdc_bundle_inst/SLICE_693:I0, - genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I16, - genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I16, - genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I16, hades_tdc_bundle_ins - t/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I2, hades_tdc_bu - ndle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I3, - SLICE_740:I1, hades_buf_drop[1]_MGIOL:I9, FEE_TRG_RELEASE_OUT_MGIOL:I9, - FEE_DATAFINISHED_OUT_MGIOL:I9, FEE_DATA_WRITE_OUT_MGIOL:I9 -Signal hades_tdc_bundle_inst.drop_cmp_buf_valid_0_sqmuxa - Driver Comp: - hades_tdc_bundle_inst/SLICE_710:O1 - Load Comps: hades_buf_drop[1]_MGIOL:I10 -Signal hades_buf_drop_c[1] - Driver Comp: hades_buf_drop[1]_MGIOL:O0 - Load Comps: hades_buf_drop[1]:I1 -Signal hades_tdc_bundle_inst.buf_out12 - Driver Comp: - hades_tdc_bundle_inst/SLICE_683:O0 - Load Comps: hades_buf_out_valid_MGIOL:I10 -Signal N_248_i - Driver Comp: hades_tdc_bundle_inst/SLICE_653:O2 - Load Comps: hades_buf_out_valid_MGIOL:I8 -Signal hades_buf_out_valid_c - Driver Comp: hades_buf_out_valid_MGIOL:O0 - Load Comps: hades_buf_out_valid:I1 -Signal hades_lvl1_invalid_c - Driver Comp: hades_lvl1_invalid:O0 - Load Comps: hades_lvl1_invalid_MGIOL:I5 -Signal hades_invalid_dl_c[0] - Driver Comp: hades_lvl1_invalid_MGIOL:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I4, - hades_invalid_dl[0]:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I6, - - Page 49 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I2 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:I4, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I2 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:I3 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I3 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:I4, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I8, - - Page 50 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_637:O2 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_657:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_709:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_636:O2 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_656:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_655:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I2, - - Page 51 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I2 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I3, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:I4, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I2 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:I3 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I3 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:I4, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I8, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_639:O2 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_660:O1 - - Page 52 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_708:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_638:O2 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_659:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_658:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:I8 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_685:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I5, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I2, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:I8 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_686:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I7 - - Page 53 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:I7, - - Page 54 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:O4 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:O3 - Load Comps: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:I7, - - Page 55 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I14, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[18] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0 - Load Comps: fifo_colector_inst/SLICE_128:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[19] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1 - Load Comps: fifo_colector_inst/SLICE_129:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[20] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2 - Load Comps: fifo_colector_inst/SLICE_130:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[21] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3 - Load Comps: fifo_colector_inst/SLICE_131:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[22] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4 - Load Comps: fifo_colector_inst/SLICE_132:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[23] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5 - Load Comps: fifo_colector_inst/SLICE_133:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[0] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18 - Load Comps: fifo_colector_inst/SLICE_138:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[1] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19 - Load Comps: fifo_colector_inst/SLICE_138:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20 - Load Comps: fifo_colector_inst/SLICE_139:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[3] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21 - Load Comps: fifo_colector_inst/SLICE_139:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[4] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22 - Load Comps: fifo_colector_inst/SLICE_140:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[5] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23 - Load Comps: fifo_colector_inst/SLICE_140:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[6] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24 - Load Comps: fifo_colector_inst/SLICE_141:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[7] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25 - Load Comps: fifo_colector_inst/SLICE_141:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[8] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26 - - Page 56 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/SLICE_142:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[9] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27 - Load Comps: fifo_colector_inst/SLICE_142:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[10] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28 - Load Comps: fifo_colector_inst/SLICE_143:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[11] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29 - Load Comps: fifo_colector_inst/SLICE_143:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[12] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30 - Load Comps: fifo_colector_inst/SLICE_144:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[13] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31 - Load Comps: fifo_colector_inst/SLICE_144:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[14] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32 - Load Comps: fifo_colector_inst/SLICE_145:I2 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[15] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33 - Load Comps: fifo_colector_inst/SLICE_145:I8 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[16] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34 - Load Comps: fifo_colector_inst/SLICE_126:I4 -Signal genblk1[2].un1_tdc_channel_fifo_out_inst[17] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35 - Load Comps: fifo_colector_inst/SLICE_127:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_401:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I0, - - Page 57 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_402:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_403:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_404:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O3 - - Page 58 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_405:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_386:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_387:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_388:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_389:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:I5 - - Page 59 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_390:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_381:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_382:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I7, - - Page 60 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_383:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I6, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_384:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I7, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I0, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_385:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_366:O4 - - Page 61 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_367:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_368:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O1 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:I13 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_369:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_370:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_391:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_396:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver - - Page 62 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_392:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_397:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_393:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_398:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_394:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_399:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_395:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_400:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_371:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_376:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_372:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_377:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_373:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_378:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_374:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_379:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_375:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_380:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I12 -Signal fifo_empty[2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:O3 - Load Comps: fifo_colector_inst/SLICE_125:I6, fifo_colector_inst/SLICE_680:I2, - - Page 63 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I1, - fifo_colector_inst/SLICE_722:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_0:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_1:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_2:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_3:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_4:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_5:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_6:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_7:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_8:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_9:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_10:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_11:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_12:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_13:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_14:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_15:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_16:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_17:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_18:I17 - - Page 64 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_19:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_20:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_21:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_22:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_23:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_24:O6 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_25:I17 -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I0 -Signal fifo_read[2] - Driver Comp: fifo_colector_inst/SLICE_190:O3 - Load Comps: fifo_colector_inst/SLICE_190:I1, - genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_712:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/N_350_i - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I12 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - - Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I16 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_365:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I0, - genblk1[2].tdc_channel_fifo_out_inst/SLICE_711:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_360:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I2, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I4 - - Page 65 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_361:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I1, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I7 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I2, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I8 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_362:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I3, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I9 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I0, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:I6 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:I5, - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I0 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_363:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_713:I1 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_356:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_357:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_358:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I4 - - Page 66 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_359:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_352:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_353:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_354:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_355:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - - Driver Comp: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_650:O2 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/dec_inst/SLICE_364:I3 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_427:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_431:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I4 -Signal trig_c_i[2] - Driver Comp: SLICE_746:O0 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_419:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I5, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_423:I5 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I4 -Signal pll_clks[2] - Driver Comp: pll0inst/PLLInst_0:CLKOS2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I15, - - Page 67 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I15, ha - des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:I1 - 5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5 - 94:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins - t/SLICE_606:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td - c_neg_inst/SLICE_610:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou - t_inst/tdc_inst/SLICE_614:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/tdc_inst/SLICE_618:I15, hades_tdc_bundle_inst/hades_tdc_chan - nel_raw_out_inst/tdc_neg_inst/SLICE_622:I15, hades_tdc_bundle_inst/hades - _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_626:I15 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_418:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_426:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_422:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_430:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I4 -Signal pll_clks[1] - Driver Comp: pll0inst/PLLInst_0:CLKOS - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_425:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I15, ha - des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:I1 - 5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5 - 93:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins - - Page 68 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - t/SLICE_605:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td - c_neg_inst/SLICE_609:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou - t_inst/tdc_inst/SLICE_613:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/tdc_inst/SLICE_617:I15, hades_tdc_bundle_inst/hades_tdc_chan - nel_raw_out_inst/tdc_neg_inst/SLICE_621:I15, hades_tdc_bundle_inst/hades - _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_625:I15 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_417:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_421:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_429:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I4 -Signal pll_clks[0] - Driver Comp: pll0inst/PLLInst_0:CLKOP - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I15, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I15, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I15, - genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I15, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I15, ha - des_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:I1 - 5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_5 - 92:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_ins - t/SLICE_604:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/td - c_neg_inst/SLICE_608:I15, hades_tdc_bundle_inst/hades_tdc_channel_raw_ou - t_inst/tdc_inst/SLICE_612:I15, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/tdc_inst/SLICE_616:I15, hades_tdc_bundle_inst/hades_tdc_chan - nel_raw_out_inst/tdc_neg_inst/SLICE_620:I15, hades_tdc_bundle_inst/hades - _tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_624:I15, - pll0inst/PLLInst_0:CLKFB -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_416:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_424:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O4 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver - Comp: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_420:O3 - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/SLICE_428:I4 -Signal genblk1[2].tdc_channel_fifo_out_inst/fb_0 - Driver Comp: - genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:O0 - - Page 69 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[2].tdc_channel_fifo_out_inst/SLICE_406:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I2 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I0 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:I4, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I2 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver - - Page 70 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:I3 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I3 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:I4, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_641:O2 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_663:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_707:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_640:O2 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_662:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_661:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver - - Page 71 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I2 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I3, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I0 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:I4, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I2 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:I3 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I3 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:I4, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver - - Page 72 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_643:O2 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_666:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_706:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_642:O2 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_665:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_664:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:I8 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_687:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I5, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I1, - - Page 73 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I2, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:I8 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_688:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:O3 - - Page 74 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O3 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:O4 - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:O3 - - Page 75 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I14, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[18] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0 - Load Comps: fifo_colector_inst/SLICE_135:I2 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[19] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1 - Load Comps: fifo_colector_inst/SLICE_135:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[20] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2 - Load Comps: fifo_colector_inst/SLICE_136:I2 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[21] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3 - Load Comps: fifo_colector_inst/SLICE_136:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[22] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4 - Load Comps: fifo_colector_inst/SLICE_137:I2 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[23] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5 - Load Comps: fifo_colector_inst/SLICE_137:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[0] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18 - Load Comps: fifo_colector_inst/SLICE_142:I1 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19 - Load Comps: fifo_colector_inst/SLICE_142:I7 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[2] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20 - Load Comps: fifo_colector_inst/SLICE_143:I1 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[3] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21 - Load Comps: fifo_colector_inst/SLICE_143:I7 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[4] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22 - Load Comps: fifo_colector_inst/SLICE_144:I1 - - Page 76 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[5] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23 - Load Comps: fifo_colector_inst/SLICE_144:I7 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[6] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24 - Load Comps: fifo_colector_inst/SLICE_145:I1 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[7] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25 - Load Comps: fifo_colector_inst/SLICE_145:I7 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[8] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26 - Load Comps: fifo_colector_inst/SLICE_126:I2, fifo_colector_inst/SLICE_126:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[9] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27 - Load Comps: fifo_colector_inst/SLICE_127:I2, fifo_colector_inst/SLICE_127:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[10] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28 - Load Comps: fifo_colector_inst/SLICE_128:I2, fifo_colector_inst/SLICE_128:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[11] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29 - Load Comps: fifo_colector_inst/SLICE_129:I2, fifo_colector_inst/SLICE_129:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[12] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30 - Load Comps: fifo_colector_inst/SLICE_130:I2, fifo_colector_inst/SLICE_130:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[13] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31 - Load Comps: fifo_colector_inst/SLICE_131:I2, fifo_colector_inst/SLICE_131:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[14] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32 - Load Comps: fifo_colector_inst/SLICE_132:I2, fifo_colector_inst/SLICE_132:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[15] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33 - Load Comps: fifo_colector_inst/SLICE_133:I2, fifo_colector_inst/SLICE_133:I8 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[16] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34 - Load Comps: fifo_colector_inst/SLICE_134:I2 -Signal genblk1[1].un1_tdc_channel_fifo_out_inst[17] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35 - Load Comps: fifo_colector_inst/SLICE_134:I8 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I1, - - Page 77 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_321:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_322:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_323:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver - - Page 78 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_324:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_325:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_306:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_307:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_308:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver - - Page 79 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_309:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_310:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_301:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I6, - - Page 80 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_302:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_303:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I1, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I6, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_304:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I0, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_305:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I13 - - Page 81 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_286:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_287:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_288:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O1 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:I13 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_289:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_290:O4 - - Page 82 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_311:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_316:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_312:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_317:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_313:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_318:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_314:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_319:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_315:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_320:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_291:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_296:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_292:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_297:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_293:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_298:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_294:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_299:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver - - Page 83 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_295:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_300:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I12 -Signal fifo_empty[1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:O3 - Load Comps: fifo_colector_inst/SLICE_125:I2, fifo_colector_inst/SLICE_680:I8, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_26:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_27:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_28:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_29:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_30:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_31:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_32:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_33:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_34:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_35:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_36:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_37:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_38:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_39:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_40:O6 - - Page 84 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_41:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_42:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_43:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_44:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_45:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_46:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_47:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_48:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_49:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_50:O6 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_51:I17 -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I0 -Signal fifo_read[1] - Driver Comp: fifo_colector_inst/SLICE_189:O4 - Load Comps: fifo_colector_inst/SLICE_189:I7, - genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_715:I0 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/N_351_i - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I12 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - - Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I16 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_285:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I0, - genblk1[1].tdc_channel_fifo_out_inst/SLICE_714:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I0 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:I5 - - Page 85 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_280:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I2, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_281:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I1, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I7 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I2, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I8 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_282:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I3, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I9 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I0, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:I6 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:I5, - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I0 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_283:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_716:I1 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_276:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:O4 - - Page 86 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_277:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_278:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_279:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_272:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_273:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_274:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_275:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - - Driver Comp: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_651:O2 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/dec_inst/SLICE_284:I3 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_347:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_351:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I4 -Signal trig_c_i[1] - Driver Comp: SLICE_745:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I5, - - Page 87 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_339:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I5, - genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_343:I5 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_346:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_338:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_350:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_342:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_345:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_337:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_341:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_349:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_336:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_344:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O4 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver - Comp: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_340:O3 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/SLICE_348:I4 -Signal genblk1[1].tdc_channel_fifo_out_inst/fb_0 - Driver Comp: - genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:O0 - Load Comps: genblk1[1].tdc_channel_fifo_out_inst/SLICE_326:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r29 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r28 - Driver - - Page 88 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r27 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I2 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r26 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_0 - - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I0 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r25 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:I4, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r24 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I2 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r23 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:I3 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r22 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I3 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_g2b_xor_cluster_1 - - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:I4, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r8 - Driver - - Page 89 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_645:O2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_669:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_705:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_644:O2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r21 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_668:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r20 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_r0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_667:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w29 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w28 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w27 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I2, - - Page 90 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I2 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w26 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I3, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_0 - - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I0 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w25 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:I4, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w24 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I2 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w23 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:I3 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w22 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I3 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_g2b_xor_cluster_1 - - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:I4, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I8, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_647:O2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_672:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w3 - Driver - - Page 91 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_704:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_646:O2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w21 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_671:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w20 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_w0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_670:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_9 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:I8 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_set - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_clr - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_689:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I5, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_9 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I2, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:I8 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_set - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_clr - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_690:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_in_data[9] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O3 - - Page 92 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI9, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI11, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI12, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI13, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI15, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI24, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI26, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DI27 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_0 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW0 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW2 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW3 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_4 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_5 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_6 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_7 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wptr_8 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADW8 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wren_i - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I14, - - Page 93 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CEW -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_0 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR6 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR8 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_4 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR9 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_5 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR10 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_6 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR11 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_7 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:O4 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rptr_8 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:O3 - Load Comps: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:ADR13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rden_i - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I14, - - Page 94 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I14, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:CER, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:OCER -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[18] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO0 - Load Comps: fifo_colector_inst/SLICE_139:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[19] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO1 - Load Comps: fifo_colector_inst/SLICE_139:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[20] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO2 - Load Comps: fifo_colector_inst/SLICE_140:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[21] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO3 - Load Comps: fifo_colector_inst/SLICE_140:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[22] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO4 - Load Comps: fifo_colector_inst/SLICE_141:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[23] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO5 - Load Comps: fifo_colector_inst/SLICE_141:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[0] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO18 - Load Comps: fifo_colector_inst/SLICE_126:I1, fifo_colector_inst/SLICE_126:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[1] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO19 - Load Comps: fifo_colector_inst/SLICE_127:I1, fifo_colector_inst/SLICE_127:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[2] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO20 - Load Comps: fifo_colector_inst/SLICE_128:I1, fifo_colector_inst/SLICE_128:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[3] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO21 - Load Comps: fifo_colector_inst/SLICE_129:I1, fifo_colector_inst/SLICE_129:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[4] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO22 - Load Comps: fifo_colector_inst/SLICE_130:I1, fifo_colector_inst/SLICE_130:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[5] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO23 - Load Comps: fifo_colector_inst/SLICE_131:I1, fifo_colector_inst/SLICE_131:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[6] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO24 - Load Comps: fifo_colector_inst/SLICE_132:I1, fifo_colector_inst/SLICE_132:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[7] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO25 - Load Comps: fifo_colector_inst/SLICE_133:I1, fifo_colector_inst/SLICE_133:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[8] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO26 - Load Comps: fifo_colector_inst/SLICE_134:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[9] - Driver Comp: - - Page 95 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO27 - Load Comps: fifo_colector_inst/SLICE_134:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[10] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO28 - Load Comps: fifo_colector_inst/SLICE_135:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[11] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO29 - Load Comps: fifo_colector_inst/SLICE_135:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[12] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO30 - Load Comps: fifo_colector_inst/SLICE_136:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[13] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO31 - Load Comps: fifo_colector_inst/SLICE_136:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[14] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO32 - Load Comps: fifo_colector_inst/SLICE_137:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[15] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO33 - Load Comps: fifo_colector_inst/SLICE_137:I7 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[16] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO34 - Load Comps: fifo_colector_inst/SLICE_138:I1 -Signal genblk1[0].un1_tdc_channel_fifo_out_inst[17] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0:DO35 - Load Comps: fifo_colector_inst/SLICE_138:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_241:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_3 - Driver - - Page 96 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_242:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_243:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_244:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/wcount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I0, - - Page 97 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_245:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/iwcount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_226:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_227:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_228:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_229:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gdata_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O0 - - Page 98 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_230:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_221:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_222:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I4 - - Page 99 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_223:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I1, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I6, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_224:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rcount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_225:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/ircount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_206:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_2 - Driver - - Page 100 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_207:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_208:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O1 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:I13 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_209:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gdata_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_210:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_231:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_236:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_232:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_237:I5 - - Page 101 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_233:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_238:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_234:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_239:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gcount_r9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_235:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_240:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w0 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_211:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_216:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w2 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w3 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_212:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_217:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w4 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w5 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_213:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_218:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w6 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w7 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_214:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_219:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w8 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gcount_w9 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_215:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_220:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I12 -Signal fifo_empty1_c - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:O3 - Load Comps: fifo_colector_inst/SLICE_125:I1, fifo_colector_inst/SLICE_680:I7, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I1, - fifo_empty1:I0 - - Page 102 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_ci - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_52:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_53:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_54:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_55:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_56:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_57:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_ci - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_58:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_59:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_60:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_61:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_1 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_62:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_63:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_64:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_65:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_66:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_67:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_2 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_68:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_d_c - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_69:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_70:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/cmp_ci_1 - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_71:O6 - - Page 103 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co0_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_72:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co1_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_73:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co2_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_74:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co3_3 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_75:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_d_c - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_76:O6 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_77:I17 -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo_wren - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I0 -Signal fifo_read[0] - Driver Comp: fifo_colector_inst/SLICE_189:O3 - Load Comps: fifo_colector_inst/SLICE_189:I0, - genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/SLICE_718:I0 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/N_352_i - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I12 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced7_rising_i - - Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I16 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/decoder_valid - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_205:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I0, - genblk1[0].tdc_channel_fifo_out_inst/SLICE_717:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][0] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[0] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I0 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][1] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[1] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_200:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][2] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[2] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I2, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][3] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:O4 - - Page 104 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[3] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_201:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I1, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I7 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][4] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[4] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I2, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I8 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][5] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[5] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_202:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I3, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I9 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][6] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[6] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I0, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:I6 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[1][7] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:I5, - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I0 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/in_synced[7] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_203:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_719:I1 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][1] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_196:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][2] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][3] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_197:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][4] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][5] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_198:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][6] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][7] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:O4 - - Page 105 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_199:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[0] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[1] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_192:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[2] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[3] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_193:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[4] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[5] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_194:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[6] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_out[7] - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_195:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/dec_inst/un1_out_internal35_1_0_0 - - Driver Comp: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_652:O2 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/dec_inst/SLICE_204:I3 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[3] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_267:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[3] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[7] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[7] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_271:I4 -Signal trig_c_i[0] - Driver Comp: SLICE_744:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_259:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I5, - genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_263:I5 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[2] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[2] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_258:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_266:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[6] - Driver - - Page 106 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_270:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[6] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_262:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[1] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[1] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_257:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_265:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[5] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_269:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[5] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_261:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[0] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_264:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[0] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_256:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/in_clk_synced[4] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O4 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/out_buffered1[4] - Driver - Comp: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_260:O3 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/SLICE_268:I4 -Signal genblk1[0].tdc_channel_fifo_out_inst/fb_0 - Driver Comp: - genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:O0 - Load Comps: genblk1[0].tdc_channel_fifo_out_inst/SLICE_246:I12 -Signal fifo_colector_inst/data_buffer_3[31] - Driver Comp: - fifo_colector_inst/SLICE_145:O1 - Load Comps: fifo_colector_inst/SLICE_145:I13 -Signal fifo_colector_inst/in_empty_pmux_i - Driver Comp: - fifo_colector_inst/SLICE_125:O2 - Load Comps: fifo_colector_inst/SLICE_125:I12, - fifo_colector_inst/SLICE_126:I14, fifo_colector_inst/SLICE_127:I14, - fifo_colector_inst/SLICE_128:I14, fifo_colector_inst/SLICE_129:I14, - fifo_colector_inst/SLICE_130:I14, fifo_colector_inst/SLICE_131:I14, - fifo_colector_inst/SLICE_132:I14, fifo_colector_inst/SLICE_133:I14, - fifo_colector_inst/SLICE_134:I14, fifo_colector_inst/SLICE_135:I14, - fifo_colector_inst/SLICE_136:I14, fifo_colector_inst/SLICE_137:I14, - fifo_colector_inst/SLICE_138:I14, fifo_colector_inst/SLICE_139:I14, - fifo_colector_inst/SLICE_140:I14, fifo_colector_inst/SLICE_141:I14, - fifo_colector_inst/SLICE_142:I14, fifo_colector_inst/SLICE_143:I14, - fifo_colector_inst/SLICE_144:I14, fifo_colector_inst/SLICE_145:I14, - fifo_colector_inst/SLICE_146:I14 -Signal fifo_colector_inst/iterator_RNI7U5I[1] - Driver Comp: - fifo_colector_inst/SLICE_722:O0 - Load Comps: fifo_colector_inst/SLICE_134:I16, - fifo_colector_inst/SLICE_135:I16, fifo_colector_inst/SLICE_136:I16, - fifo_colector_inst/SLICE_137:I16, fifo_colector_inst/SLICE_138:I16, - fifo_colector_inst/SLICE_139:I16, fifo_colector_inst/SLICE_140:I16, - fifo_colector_inst/SLICE_141:I16, fifo_colector_inst/SLICE_142:I16, - - Page 107 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/SLICE_143:I16, fifo_colector_inst/SLICE_144:I16, - fifo_colector_inst/SLICE_145:I16 -Signal fifo_colector_inst/data_buffer[31] - Driver Comp: - fifo_colector_inst/SLICE_145:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI31 -Signal fifo_colector_inst/data_buffer[0] - Driver Comp: - fifo_colector_inst/SLICE_126:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI0 -Signal fifo_colector_inst/data_buffer[1] - Driver Comp: - fifo_colector_inst/SLICE_127:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI1 -Signal fifo_colector_inst/data_buffer[2] - Driver Comp: - fifo_colector_inst/SLICE_128:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI2 -Signal fifo_colector_inst/data_buffer[3] - Driver Comp: - fifo_colector_inst/SLICE_129:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI3 -Signal fifo_colector_inst/data_buffer[4] - Driver Comp: - fifo_colector_inst/SLICE_130:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI4 -Signal fifo_colector_inst/data_buffer[5] - Driver Comp: - fifo_colector_inst/SLICE_131:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI5 -Signal fifo_colector_inst/data_buffer[6] - Driver Comp: - fifo_colector_inst/SLICE_132:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI6 -Signal fifo_colector_inst/data_buffer[7] - Driver Comp: - fifo_colector_inst/SLICE_133:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI7 -Signal fifo_colector_inst/data_buffer[8] - Driver Comp: - fifo_colector_inst/SLICE_134:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI8 -Signal fifo_colector_inst/data_buffer[9] - Driver Comp: - fifo_colector_inst/SLICE_134:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI9 -Signal fifo_colector_inst/data_buffer[10] - Driver Comp: - fifo_colector_inst/SLICE_135:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI10 -Signal fifo_colector_inst/data_buffer[11] - Driver Comp: - fifo_colector_inst/SLICE_135:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI11 -Signal fifo_colector_inst/data_buffer[12] - Driver Comp: - fifo_colector_inst/SLICE_136:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI12 -Signal fifo_colector_inst/data_buffer[13] - Driver Comp: - fifo_colector_inst/SLICE_136:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI13 -Signal fifo_colector_inst/data_buffer[14] - Driver Comp: - fifo_colector_inst/SLICE_137:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI14 -Signal fifo_colector_inst/data_buffer[15] - Driver Comp: - fifo_colector_inst/SLICE_137:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI15 -Signal fifo_colector_inst/data_buffer[16] - Driver Comp: - fifo_colector_inst/SLICE_138:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI16 - - Page 108 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal fifo_colector_inst/data_buffer[17] - Driver Comp: - fifo_colector_inst/SLICE_138:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI17 -Signal fifo_colector_inst/data_buffer[18] - Driver Comp: - fifo_colector_inst/SLICE_139:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI18 -Signal fifo_colector_inst/data_buffer[19] - Driver Comp: - fifo_colector_inst/SLICE_139:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI19 -Signal fifo_colector_inst/data_buffer[20] - Driver Comp: - fifo_colector_inst/SLICE_140:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI20 -Signal fifo_colector_inst/data_buffer[21] - Driver Comp: - fifo_colector_inst/SLICE_140:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI21 -Signal fifo_colector_inst/data_buffer[22] - Driver Comp: - fifo_colector_inst/SLICE_141:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI22 -Signal fifo_colector_inst/data_buffer[23] - Driver Comp: - fifo_colector_inst/SLICE_141:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI23 -Signal fifo_colector_inst/data_buffer[24] - Driver Comp: - fifo_colector_inst/SLICE_142:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI24 -Signal fifo_colector_inst/data_buffer[25] - Driver Comp: - fifo_colector_inst/SLICE_142:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI25 -Signal fifo_colector_inst/data_buffer[26] - Driver Comp: - fifo_colector_inst/SLICE_143:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI26 -Signal fifo_colector_inst/data_buffer[27] - Driver Comp: - fifo_colector_inst/SLICE_143:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI27 -Signal fifo_colector_inst/data_buffer[28] - Driver Comp: - fifo_colector_inst/SLICE_144:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI28 -Signal fifo_colector_inst/data_buffer[29] - Driver Comp: - fifo_colector_inst/SLICE_144:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI29 -Signal fifo_colector_inst/data_buffer[30] - Driver Comp: - fifo_colector_inst/SLICE_145:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI30 -Signal fifo_colector_inst/data_buffer[32] - Driver Comp: - fifo_colector_inst/SLICE_146:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI32 -Signal fifo_colector_inst/data_buffer[33] - Driver Comp: - fifo_colector_inst/SLICE_146:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DI33 -Signal fifo_colector_inst/fifo40_inst/wptr_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_182:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW0 -Signal fifo_colector_inst/fifo40_inst/wptr_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_182:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW1 -Signal fifo_colector_inst/fifo40_inst/wptr_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_183:O3 - - Page 109 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW2 -Signal fifo_colector_inst/fifo40_inst/wptr_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_183:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW3 -Signal fifo_colector_inst/fifo40_inst/wptr_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_184:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW4 -Signal fifo_colector_inst/fifo40_inst/wptr_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_184:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW5 -Signal fifo_colector_inst/fifo40_inst/wptr_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_185:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW6 -Signal fifo_colector_inst/fifo40_inst/wptr_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_185:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW7 -Signal fifo_colector_inst/fifo40_inst/wptr_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_186:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADW8 -Signal fifo_colector_inst/fifo40_inst/wren_i - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_721:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I14, - fifo_colector_inst/fifo40_inst/SLICE_80:I14, - fifo_colector_inst/fifo40_inst/SLICE_81:I14, - fifo_colector_inst/fifo40_inst/SLICE_82:I14, - fifo_colector_inst/fifo40_inst/SLICE_83:I14, - fifo_colector_inst/fifo40_inst/SLICE_97:I6, - fifo_colector_inst/fifo40_inst/SLICE_97:I7, - fifo_colector_inst/fifo40_inst/SLICE_167:I14, - fifo_colector_inst/fifo40_inst/SLICE_168:I14, - fifo_colector_inst/fifo40_inst/SLICE_169:I14, - fifo_colector_inst/fifo40_inst/SLICE_170:I14, - fifo_colector_inst/fifo40_inst/SLICE_171:I14, - fifo_colector_inst/fifo40_inst/SLICE_182:I14, - fifo_colector_inst/fifo40_inst/SLICE_183:I14, - fifo_colector_inst/fifo40_inst/SLICE_184:I14, - fifo_colector_inst/fifo40_inst/SLICE_185:I14, - fifo_colector_inst/fifo40_inst/SLICE_186:I14, - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CEW -Signal fifo_colector_inst/fifo40_inst/rptr_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_162:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR5 -Signal fifo_colector_inst/fifo40_inst/rptr_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_162:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR6 -Signal fifo_colector_inst/fifo40_inst/rptr_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_163:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR7 -Signal fifo_colector_inst/fifo40_inst/rptr_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_163:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR8 -Signal fifo_colector_inst/fifo40_inst/rptr_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_164:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR9 -Signal fifo_colector_inst/fifo40_inst/rptr_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_164:O4 - - Page 110 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR10 -Signal fifo_colector_inst/fifo40_inst/rptr_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_165:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR11 -Signal fifo_colector_inst/fifo40_inst/rptr_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_165:O4 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR12 -Signal fifo_colector_inst/fifo40_inst/rptr_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_166:O3 - Load Comps: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:ADR13 -Signal fifo_colector_inst/fifo40_inst/rden_i - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_720:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I14, - fifo_colector_inst/fifo40_inst/SLICE_86:I14, - fifo_colector_inst/fifo40_inst/SLICE_87:I14, - fifo_colector_inst/fifo40_inst/SLICE_88:I14, - fifo_colector_inst/fifo40_inst/SLICE_89:I14, - fifo_colector_inst/fifo40_inst/SLICE_90:I6, - fifo_colector_inst/fifo40_inst/SLICE_90:I7, - fifo_colector_inst/fifo40_inst/SLICE_147:I14, - fifo_colector_inst/fifo40_inst/SLICE_148:I14, - fifo_colector_inst/fifo40_inst/SLICE_149:I14, - fifo_colector_inst/fifo40_inst/SLICE_150:I14, - fifo_colector_inst/fifo40_inst/SLICE_151:I14, - fifo_colector_inst/fifo40_inst/SLICE_162:I14, - fifo_colector_inst/fifo40_inst/SLICE_163:I14, - fifo_colector_inst/fifo40_inst/SLICE_164:I14, - fifo_colector_inst/fifo40_inst/SLICE_165:I14, - fifo_colector_inst/fifo40_inst/SLICE_166:I14, - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CER, - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:OCER -Signal rd_clk_c - Driver Comp: rd_clk:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I15, - fifo_colector_inst/fifo40_inst/SLICE_86:I15, - fifo_colector_inst/fifo40_inst/SLICE_87:I15, - fifo_colector_inst/fifo40_inst/SLICE_88:I15, - fifo_colector_inst/fifo40_inst/SLICE_89:I15, - fifo_colector_inst/fifo40_inst/SLICE_96:I15, - trb_adapter_inst/SLICE_124:I15, - fifo_colector_inst/fifo40_inst/SLICE_147:I15, - fifo_colector_inst/fifo40_inst/SLICE_148:I15, - fifo_colector_inst/fifo40_inst/SLICE_149:I15, - fifo_colector_inst/fifo40_inst/SLICE_150:I15, - fifo_colector_inst/fifo40_inst/SLICE_151:I15, - fifo_colector_inst/fifo40_inst/SLICE_162:I15, - fifo_colector_inst/fifo40_inst/SLICE_163:I15, - fifo_colector_inst/fifo40_inst/SLICE_164:I15, - fifo_colector_inst/fifo40_inst/SLICE_165:I15, - fifo_colector_inst/fifo40_inst/SLICE_166:I15, - fifo_colector_inst/fifo40_inst/SLICE_172:I15, - fifo_colector_inst/fifo40_inst/SLICE_173:I15, - fifo_colector_inst/fifo40_inst/SLICE_174:I15, - fifo_colector_inst/fifo40_inst/SLICE_175:I15, - fifo_colector_inst/fifo40_inst/SLICE_176:I15, - fifo_colector_inst/fifo40_inst/SLICE_177:I15, - fifo_colector_inst/fifo40_inst/SLICE_178:I15, - - Page 111 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_179:I15, - fifo_colector_inst/fifo40_inst/SLICE_180:I15, - fifo_colector_inst/fifo40_inst/SLICE_181:I15, - trb_adapter_inst/SLICE_188:I15, trb_adapter_inst/SLICE_631:I15, - trb_adapter_inst/SLICE_632:I15, trb_adapter_inst/SLICE_633:I15, - trb_adapter_inst/SLICE_724:I15, FEE_TRG_RELEASE_OUT_MGIOL:I6, - FEE_DATAFINISHED_OUT_MGIOL:I6, FEE_DATA_WRITE_OUT_MGIOL:I6, - LVL1_INVALID_TRG_IN_MGIOL:I6, LVL1_TRG_DATA_VALID_IN_MGIOL:I6, - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:CLKR -Signal FEE_DATA_OUT_c[18] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO0 - Load Comps: FEE_DATA_OUT[18]:I0, fifo_data_out[18]:I0 -Signal FEE_DATA_OUT_c[19] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO1 - Load Comps: FEE_DATA_OUT[19]:I0, fifo_data_out[19]:I0 -Signal FEE_DATA_OUT_c[20] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO2 - Load Comps: FEE_DATA_OUT[20]:I0, fifo_data_out[20]:I0 -Signal FEE_DATA_OUT_c[21] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO3 - Load Comps: FEE_DATA_OUT[21]:I0, fifo_data_out[21]:I0 -Signal FEE_DATA_OUT_c[22] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO4 - Load Comps: FEE_DATA_OUT[22]:I0, fifo_data_out[22]:I0 -Signal FEE_DATA_OUT_c[23] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO5 - Load Comps: FEE_DATA_OUT[23]:I0, fifo_data_out[23]:I0 -Signal FEE_DATA_OUT_c[24] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO6 - Load Comps: FEE_DATA_OUT[24]:I0, fifo_data_out[24]:I0 -Signal FEE_DATA_OUT_c[25] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO7 - Load Comps: FEE_DATA_OUT[25]:I0, fifo_data_out[25]:I0 -Signal FEE_DATA_OUT_c[26] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO8 - Load Comps: FEE_DATA_OUT[26]:I0, fifo_data_out[26]:I0 -Signal FEE_DATA_OUT_c[27] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO9 - Load Comps: FEE_DATA_OUT[27]:I0, fifo_data_out[27]:I0 -Signal FEE_DATA_OUT_c[28] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO10 - Load Comps: FEE_DATA_OUT[28]:I0, fifo_data_out[28]:I0 -Signal FEE_DATA_OUT_c[29] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO11 - Load Comps: FEE_DATA_OUT[29]:I0, fifo_data_out[29]:I0 -Signal FEE_DATA_OUT_c[30] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO12 - Load Comps: FEE_DATA_OUT[30]:I0, fifo_data_out[30]:I0 -Signal FEE_DATA_OUT_c[31] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO13 - Load Comps: FEE_DATA_OUT[31]:I0, fifo_data_out[31]:I0 -Signal FEE_DATA_OUT_c[1] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO19 - Load Comps: FEE_DATA_OUT[1]:I0, fifo_data_out[1]:I0 -Signal FEE_DATA_OUT_c[2] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO20 - - Page 112 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: FEE_DATA_OUT[2]:I0, fifo_data_out[2]:I0 -Signal FEE_DATA_OUT_c[3] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO21 - Load Comps: FEE_DATA_OUT[3]:I0, fifo_data_out[3]:I0 -Signal FEE_DATA_OUT_c[4] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO22 - Load Comps: FEE_DATA_OUT[4]:I0, fifo_data_out[4]:I0 -Signal FEE_DATA_OUT_c[5] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO23 - Load Comps: FEE_DATA_OUT[5]:I0, fifo_data_out[5]:I0 -Signal FEE_DATA_OUT_c[6] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO24 - Load Comps: FEE_DATA_OUT[6]:I0, fifo_data_out[6]:I0 -Signal FEE_DATA_OUT_c[7] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO25 - Load Comps: FEE_DATA_OUT[7]:I0, fifo_data_out[7]:I0 -Signal FEE_DATA_OUT_c[8] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO26 - Load Comps: FEE_DATA_OUT[8]:I0, fifo_data_out[8]:I0 -Signal FEE_DATA_OUT_c[9] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO27 - Load Comps: FEE_DATA_OUT[9]:I0, fifo_data_out[9]:I0 -Signal FEE_DATA_OUT_c[10] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO28 - Load Comps: FEE_DATA_OUT[10]:I0, fifo_data_out[10]:I0 -Signal FEE_DATA_OUT_c[11] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO29 - Load Comps: FEE_DATA_OUT[11]:I0, fifo_data_out[11]:I0 -Signal FEE_DATA_OUT_c[12] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO30 - Load Comps: FEE_DATA_OUT[12]:I0, fifo_data_out[12]:I0 -Signal FEE_DATA_OUT_c[13] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO31 - Load Comps: FEE_DATA_OUT[13]:I0, fifo_data_out[13]:I0 -Signal FEE_DATA_OUT_c[14] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO32 - Load Comps: FEE_DATA_OUT[14]:I0, fifo_data_out[14]:I0 -Signal FEE_DATA_OUT_c[15] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO33 - Load Comps: FEE_DATA_OUT[15]:I0, fifo_data_out[15]:I0 -Signal FEE_DATA_OUT_c[16] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO34 - Load Comps: FEE_DATA_OUT[16]:I0, fifo_data_out[16]:I0 -Signal FEE_DATA_OUT_c[17] - Driver Comp: - fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1:DO35 - Load Comps: FEE_DATA_OUT[17]:I0, fifo_data_out[17]:I0 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w29 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_161:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I0, - fifo_colector_inst/fifo40_inst/SLICE_648:I6, - fifo_colector_inst/fifo40_inst/SLICE_649:I0, - fifo_colector_inst/fifo40_inst/SLICE_649:I6, - fifo_colector_inst/fifo40_inst/SLICE_677:I0, - fifo_colector_inst/fifo40_inst/SLICE_679:I0, - fifo_colector_inst/fifo40_inst/SLICE_691:I0, - fifo_colector_inst/fifo40_inst/SLICE_691:I6, - - Page 113 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_703:I6 -Signal fifo_colector_inst/fifo40_inst/wcount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_83:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I6, - fifo_colector_inst/fifo40_inst/SLICE_171:I1, - fifo_colector_inst/fifo40_inst/SLICE_171:I5, - fifo_colector_inst/fifo40_inst/SLICE_186:I5, - fifo_colector_inst/fifo40_inst/SLICE_691:I1, - fifo_colector_inst/fifo40_inst/SLICE_691:I7 -Signal fifo_colector_inst/fifo40_inst/wptr_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_186:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_691:I2, - fifo_colector_inst/fifo40_inst/SLICE_691:I8 -Signal fifo_colector_inst/fifo40_inst/full_cmp_clr - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_691:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I7 -Signal fifo_colector_inst/fifo40_inst/full_d - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_103:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I12 -Signal fifo_colector_inst/fifo40_inst/Full - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_103:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I1 -Signal fifo_colector_inst/fifo40_inst/empty_d - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_96:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I12 -Signal last_buf_empty_c - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_96:O3 - Load Comps: trb_adapter_inst/SLICE_188:I2, - fifo_colector_inst/fifo40_inst/SLICE_720:I1, last_buf_empty:I0 -Signal fifo_colector_inst/fifo40_inst/rcount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_89:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I6, - fifo_colector_inst/fifo40_inst/SLICE_151:I1, - fifo_colector_inst/fifo40_inst/SLICE_151:I5, - fifo_colector_inst/fifo40_inst/SLICE_166:I5, - fifo_colector_inst/fifo40_inst/SLICE_692:I1, - fifo_colector_inst/fifo40_inst/SLICE_692:I7 -Signal fifo_colector_inst/fifo40_inst/rptr_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_166:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_692:I2, - fifo_colector_inst/fifo40_inst/SLICE_692:I8 -Signal fifo_colector_inst/fifo40_inst/ircount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_85:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I12 -Signal fifo_colector_inst/fifo40_inst/rcount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_85:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I0, - fifo_colector_inst/fifo40_inst/SLICE_91:I0, - fifo_colector_inst/fifo40_inst/SLICE_147:I0, - fifo_colector_inst/fifo40_inst/SLICE_162:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r29 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_181:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I0, - fifo_colector_inst/fifo40_inst/SLICE_675:I0, - fifo_colector_inst/fifo40_inst/SLICE_676:I0, - fifo_colector_inst/fifo40_inst/SLICE_692:I0, - - Page 114 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_692:I6 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r28 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_181:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I1, - fifo_colector_inst/fifo40_inst/SLICE_675:I1, - fifo_colector_inst/fifo40_inst/SLICE_676:I1 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r27 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_180:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I2, - fifo_colector_inst/fifo40_inst/SLICE_675:I7, - fifo_colector_inst/fifo40_inst/SLICE_676:I2 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r26 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_180:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I3, - fifo_colector_inst/fifo40_inst/SLICE_675:I8, - fifo_colector_inst/fifo40_inst/SLICE_676:I7 -Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_673:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I1, - fifo_colector_inst/fifo40_inst/SLICE_673:I9, - fifo_colector_inst/fifo40_inst/SLICE_674:I8, - fifo_colector_inst/fifo40_inst/SLICE_702:I1, - fifo_colector_inst/fifo40_inst/SLICE_702:I6 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r25 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_179:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I0, - fifo_colector_inst/fifo40_inst/SLICE_675:I9, - fifo_colector_inst/fifo40_inst/SLICE_676:I8, - fifo_colector_inst/fifo40_inst/SLICE_702:I7 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r24 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_179:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I1, - fifo_colector_inst/fifo40_inst/SLICE_676:I9, - fifo_colector_inst/fifo40_inst/SLICE_702:I8 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r23 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_178:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I2, - fifo_colector_inst/fifo40_inst/SLICE_702:I9 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r22 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_178:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_674:I3 -Signal fifo_colector_inst/fifo40_inst/w_g2b_xor_cluster_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_674:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I8, - fifo_colector_inst/fifo40_inst/SLICE_674:I7, - fifo_colector_inst/fifo40_inst/SLICE_702:I0 -Signal fifo_colector_inst/fifo40_inst/wcount_r8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_675:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I1, - fifo_colector_inst/fifo40_inst/SLICE_675:I6 -Signal fifo_colector_inst/fifo40_inst/wcount_r7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_676:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I7, - fifo_colector_inst/fifo40_inst/SLICE_676:I6 -Signal fifo_colector_inst/fifo40_inst/wcount_r5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_675:O1 - - Page 115 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I7 -Signal fifo_colector_inst/fifo40_inst/wcount_r4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_676:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I1 -Signal fifo_colector_inst/fifo40_inst/wcount_r3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_702:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I7 -Signal fifo_colector_inst/fifo40_inst/wcount_r2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_702:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I1 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r21 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_177:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I6, - fifo_colector_inst/fifo40_inst/SLICE_674:I6 -Signal fifo_colector_inst/fifo40_inst/wcount_r1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_674:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I7 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r20 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_177:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_673:I7 -Signal fifo_colector_inst/fifo40_inst/wcount_r0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_673:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I1 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w28 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_161:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I1, - fifo_colector_inst/fifo40_inst/SLICE_648:I7, - fifo_colector_inst/fifo40_inst/SLICE_649:I1, - fifo_colector_inst/fifo40_inst/SLICE_649:I7, - fifo_colector_inst/fifo40_inst/SLICE_677:I1, - fifo_colector_inst/fifo40_inst/SLICE_679:I1, - fifo_colector_inst/fifo40_inst/SLICE_703:I7 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w27 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_160:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I2, - fifo_colector_inst/fifo40_inst/SLICE_648:I8, - fifo_colector_inst/fifo40_inst/SLICE_649:I2, - fifo_colector_inst/fifo40_inst/SLICE_649:I8, - fifo_colector_inst/fifo40_inst/SLICE_677:I2, - fifo_colector_inst/fifo40_inst/SLICE_679:I2 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w26 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_160:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I3, - fifo_colector_inst/fifo40_inst/SLICE_648:I9, - fifo_colector_inst/fifo40_inst/SLICE_649:I3, - fifo_colector_inst/fifo40_inst/SLICE_649:I9, - fifo_colector_inst/fifo40_inst/SLICE_677:I3, - fifo_colector_inst/fifo40_inst/SLICE_679:I7 -Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_677:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I1, - fifo_colector_inst/fifo40_inst/SLICE_677:I9, - fifo_colector_inst/fifo40_inst/SLICE_678:I8, - fifo_colector_inst/fifo40_inst/SLICE_703:I0 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w25 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_159:O4 - - Page 116 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_649:I4, - fifo_colector_inst/fifo40_inst/SLICE_678:I0, - fifo_colector_inst/fifo40_inst/SLICE_679:I8, - fifo_colector_inst/fifo40_inst/SLICE_703:I1 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w24 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_159:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I1, - fifo_colector_inst/fifo40_inst/SLICE_679:I9, - fifo_colector_inst/fifo40_inst/SLICE_703:I2 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w23 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_158:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I2, - fifo_colector_inst/fifo40_inst/SLICE_703:I3 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w22 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_158:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_678:I3 -Signal fifo_colector_inst/fifo40_inst/r_g2b_xor_cluster_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_678:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_648:I4, - fifo_colector_inst/fifo40_inst/SLICE_677:I8, - fifo_colector_inst/fifo40_inst/SLICE_678:I7 -Signal fifo_colector_inst/fifo40_inst/rcount_w8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_703:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I1 -Signal fifo_colector_inst/fifo40_inst/rcount_w7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_679:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I7, - fifo_colector_inst/fifo40_inst/SLICE_679:I6 -Signal fifo_colector_inst/fifo40_inst/rcount_w5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_649:O2 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I7 -Signal fifo_colector_inst/fifo40_inst/rcount_w4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_679:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I1 -Signal fifo_colector_inst/fifo40_inst/rcount_w3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_703:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I7 -Signal fifo_colector_inst/fifo40_inst/rcount_w2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_648:O2 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I1 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w21 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_157:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I6, - fifo_colector_inst/fifo40_inst/SLICE_678:I6 -Signal fifo_colector_inst/fifo40_inst/rcount_w1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_678:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I7 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w20 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_157:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_677:I7 -Signal fifo_colector_inst/fifo40_inst/rcount_w0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_677:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I1 -Signal fifo_colector_inst/fifo40_inst/empty_cmp_set - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_692:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I6 - - Page 117 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal fifo_colector_inst/fifo40_inst/empty_cmp_clr - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_692:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I7 -Signal fifo_colector_inst/fifo40_inst/full_cmp_set - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_691:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I6 -Signal fifo_colector_inst/fifo40_inst/iwcount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_79:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I12 -Signal fifo_colector_inst/fifo40_inst/wcount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_79:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I0, - fifo_colector_inst/fifo40_inst/SLICE_98:I0, - fifo_colector_inst/fifo40_inst/SLICE_167:I0, - fifo_colector_inst/fifo40_inst/SLICE_182:I4 -Signal fifo_colector_inst/fifo40_inst/iwcount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_79:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I13 -Signal fifo_colector_inst/fifo40_inst/wcount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_79:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I6, - fifo_colector_inst/fifo40_inst/SLICE_98:I6, - fifo_colector_inst/fifo40_inst/SLICE_167:I1, - fifo_colector_inst/fifo40_inst/SLICE_167:I6, - fifo_colector_inst/fifo40_inst/SLICE_182:I5 -Signal fifo_colector_inst/fifo40_inst/iwcount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_80:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I12 -Signal fifo_colector_inst/fifo40_inst/wcount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_80:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I0, - fifo_colector_inst/fifo40_inst/SLICE_99:I0, - fifo_colector_inst/fifo40_inst/SLICE_167:I7, - fifo_colector_inst/fifo40_inst/SLICE_168:I0, - fifo_colector_inst/fifo40_inst/SLICE_183:I4 -Signal fifo_colector_inst/fifo40_inst/iwcount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_80:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I13 -Signal fifo_colector_inst/fifo40_inst/wcount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_80:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I6, - fifo_colector_inst/fifo40_inst/SLICE_99:I6, - fifo_colector_inst/fifo40_inst/SLICE_168:I1, - fifo_colector_inst/fifo40_inst/SLICE_168:I6, - fifo_colector_inst/fifo40_inst/SLICE_183:I5 -Signal fifo_colector_inst/fifo40_inst/iwcount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_81:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I12 -Signal fifo_colector_inst/fifo40_inst/wcount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_81:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I0, - fifo_colector_inst/fifo40_inst/SLICE_100:I0, - fifo_colector_inst/fifo40_inst/SLICE_168:I7, - fifo_colector_inst/fifo40_inst/SLICE_169:I0, - fifo_colector_inst/fifo40_inst/SLICE_184:I4 -Signal fifo_colector_inst/fifo40_inst/iwcount_5 - Driver Comp: - - Page 118 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_81:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I13 -Signal fifo_colector_inst/fifo40_inst/wcount_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_81:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I6, - fifo_colector_inst/fifo40_inst/SLICE_100:I6, - fifo_colector_inst/fifo40_inst/SLICE_169:I1, - fifo_colector_inst/fifo40_inst/SLICE_169:I6, - fifo_colector_inst/fifo40_inst/SLICE_184:I5 -Signal fifo_colector_inst/fifo40_inst/iwcount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_82:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I12 -Signal fifo_colector_inst/fifo40_inst/wcount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_82:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I0, - fifo_colector_inst/fifo40_inst/SLICE_101:I0, - fifo_colector_inst/fifo40_inst/SLICE_169:I7, - fifo_colector_inst/fifo40_inst/SLICE_170:I0, - fifo_colector_inst/fifo40_inst/SLICE_185:I4 -Signal fifo_colector_inst/fifo40_inst/iwcount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_82:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I13 -Signal fifo_colector_inst/fifo40_inst/wcount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_82:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I6, - fifo_colector_inst/fifo40_inst/SLICE_101:I6, - fifo_colector_inst/fifo40_inst/SLICE_170:I1, - fifo_colector_inst/fifo40_inst/SLICE_170:I6, - fifo_colector_inst/fifo40_inst/SLICE_185:I5 -Signal fifo_colector_inst/fifo40_inst/iwcount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_83:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I12 -Signal fifo_colector_inst/fifo40_inst/wcount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_83:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I0, - fifo_colector_inst/fifo40_inst/SLICE_102:I0, - fifo_colector_inst/fifo40_inst/SLICE_170:I7, - fifo_colector_inst/fifo40_inst/SLICE_171:I0, - fifo_colector_inst/fifo40_inst/SLICE_186:I4 -Signal fifo_colector_inst/fifo40_inst/iwcount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_83:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I13 -Signal fifo_colector_inst/fifo40_inst/w_gdata_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_167:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I12 -Signal fifo_colector_inst/fifo40_inst/w_gcount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_167:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I4 -Signal fifo_colector_inst/fifo40_inst/w_gdata_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_167:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_167:I13 -Signal fifo_colector_inst/fifo40_inst/w_gcount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_167:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_172:I5 -Signal fifo_colector_inst/fifo40_inst/w_gdata_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_168:O0 - - Page 119 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I12 -Signal fifo_colector_inst/fifo40_inst/w_gcount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_168:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I4 -Signal fifo_colector_inst/fifo40_inst/w_gdata_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_168:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_168:I13 -Signal fifo_colector_inst/fifo40_inst/w_gcount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_168:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_173:I5 -Signal fifo_colector_inst/fifo40_inst/w_gdata_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_169:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I12 -Signal fifo_colector_inst/fifo40_inst/w_gcount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_169:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I4 -Signal fifo_colector_inst/fifo40_inst/w_gdata_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_169:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_169:I13 -Signal fifo_colector_inst/fifo40_inst/w_gcount_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_169:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_174:I5 -Signal fifo_colector_inst/fifo40_inst/w_gdata_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_170:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I12 -Signal fifo_colector_inst/fifo40_inst/w_gcount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_170:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I4 -Signal fifo_colector_inst/fifo40_inst/w_gdata_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_170:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_170:I13 -Signal fifo_colector_inst/fifo40_inst/w_gcount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_170:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_175:I5 -Signal fifo_colector_inst/fifo40_inst/w_gdata_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_171:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_171:I12 -Signal fifo_colector_inst/fifo40_inst/w_gcount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_171:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_171:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_176:I5 -Signal fifo_colector_inst/fifo40_inst/ircount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_85:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I13 -Signal fifo_colector_inst/fifo40_inst/rcount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_85:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I6, - fifo_colector_inst/fifo40_inst/SLICE_91:I6, - fifo_colector_inst/fifo40_inst/SLICE_147:I1, - fifo_colector_inst/fifo40_inst/SLICE_147:I6, - fifo_colector_inst/fifo40_inst/SLICE_162:I5 -Signal fifo_colector_inst/fifo40_inst/ircount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_86:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I12 - - Page 120 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal fifo_colector_inst/fifo40_inst/rcount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_86:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I0, - fifo_colector_inst/fifo40_inst/SLICE_92:I0, - fifo_colector_inst/fifo40_inst/SLICE_147:I7, - fifo_colector_inst/fifo40_inst/SLICE_148:I0, - fifo_colector_inst/fifo40_inst/SLICE_163:I4 -Signal fifo_colector_inst/fifo40_inst/ircount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_86:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I13 -Signal fifo_colector_inst/fifo40_inst/rcount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_86:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I6, - fifo_colector_inst/fifo40_inst/SLICE_92:I6, - fifo_colector_inst/fifo40_inst/SLICE_148:I1, - fifo_colector_inst/fifo40_inst/SLICE_148:I6, - fifo_colector_inst/fifo40_inst/SLICE_163:I5 -Signal fifo_colector_inst/fifo40_inst/ircount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_87:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I12 -Signal fifo_colector_inst/fifo40_inst/rcount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_87:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I0, - fifo_colector_inst/fifo40_inst/SLICE_93:I0, - fifo_colector_inst/fifo40_inst/SLICE_148:I7, - fifo_colector_inst/fifo40_inst/SLICE_149:I0, - fifo_colector_inst/fifo40_inst/SLICE_164:I4 -Signal fifo_colector_inst/fifo40_inst/ircount_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_87:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I13 -Signal fifo_colector_inst/fifo40_inst/rcount_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_87:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I6, - fifo_colector_inst/fifo40_inst/SLICE_93:I6, - fifo_colector_inst/fifo40_inst/SLICE_149:I1, - fifo_colector_inst/fifo40_inst/SLICE_149:I6, - fifo_colector_inst/fifo40_inst/SLICE_164:I5 -Signal fifo_colector_inst/fifo40_inst/ircount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_88:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I12 -Signal fifo_colector_inst/fifo40_inst/rcount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_88:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I0, - fifo_colector_inst/fifo40_inst/SLICE_94:I0, - fifo_colector_inst/fifo40_inst/SLICE_149:I7, - fifo_colector_inst/fifo40_inst/SLICE_150:I0, - fifo_colector_inst/fifo40_inst/SLICE_165:I4 -Signal fifo_colector_inst/fifo40_inst/ircount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_88:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I13 -Signal fifo_colector_inst/fifo40_inst/rcount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_88:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I6, - fifo_colector_inst/fifo40_inst/SLICE_94:I6, - fifo_colector_inst/fifo40_inst/SLICE_150:I1, - fifo_colector_inst/fifo40_inst/SLICE_150:I6, - - Page 121 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_165:I5 -Signal fifo_colector_inst/fifo40_inst/ircount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_89:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I12 -Signal fifo_colector_inst/fifo40_inst/rcount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_89:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I0, - fifo_colector_inst/fifo40_inst/SLICE_95:I0, - fifo_colector_inst/fifo40_inst/SLICE_150:I7, - fifo_colector_inst/fifo40_inst/SLICE_151:I0, - fifo_colector_inst/fifo40_inst/SLICE_166:I4 -Signal fifo_colector_inst/fifo40_inst/ircount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_89:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I13 -Signal fifo_colector_inst/fifo40_inst/r_gdata_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_147:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I12 -Signal fifo_colector_inst/fifo40_inst/r_gcount_0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_147:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I4 -Signal fifo_colector_inst/fifo40_inst/r_gdata_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_147:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_147:I13 -Signal fifo_colector_inst/fifo40_inst/r_gcount_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_147:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_152:I5 -Signal fifo_colector_inst/fifo40_inst/r_gdata_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_148:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I12 -Signal fifo_colector_inst/fifo40_inst/r_gcount_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_148:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I4 -Signal fifo_colector_inst/fifo40_inst/r_gdata_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_148:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_148:I13 -Signal fifo_colector_inst/fifo40_inst/r_gcount_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_148:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_153:I5 -Signal fifo_colector_inst/fifo40_inst/r_gdata_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_149:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I12 -Signal fifo_colector_inst/fifo40_inst/r_gcount_4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_149:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I4 -Signal fifo_colector_inst/fifo40_inst/r_gdata_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_149:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_149:I13 -Signal fifo_colector_inst/fifo40_inst/r_gcount_5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_149:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_154:I5 -Signal fifo_colector_inst/fifo40_inst/r_gdata_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_150:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I12 -Signal fifo_colector_inst/fifo40_inst/r_gcount_6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_150:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I4 - - Page 122 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal fifo_colector_inst/fifo40_inst/r_gdata_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_150:O1 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_150:I13 -Signal fifo_colector_inst/fifo40_inst/r_gcount_7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_150:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_155:I5 -Signal fifo_colector_inst/fifo40_inst/r_gdata_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_151:O0 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_151:I12 -Signal fifo_colector_inst/fifo40_inst/r_gcount_8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_151:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_151:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_156:I5 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_172:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_172:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_177:I5 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_173:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_173:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_178:I5 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_174:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_174:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_179:I5 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_175:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_175:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_180:I5 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_176:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I4 -Signal fifo_colector_inst/fifo40_inst/w_gcount_r9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_176:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_181:I5 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_152:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_152:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_157:I5 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_153:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_153:O4 - - Page 123 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_158:I5 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w4 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_154:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w5 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_154:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_159:I5 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w6 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_155:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w7 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_155:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_160:I5 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w8 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_156:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I4 -Signal fifo_colector_inst/fifo40_inst/r_gcount_w9 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_156:O4 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_161:I5 -Signal fifo_colector_inst/fifo40_inst/w_gctr_ci - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_78:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_79:I17 -Signal fifo_colector_inst/fifo40_inst/co0 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_79:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_80:I17 -Signal fifo_colector_inst/fifo40_inst/co1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_80:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_81:I17 -Signal fifo_colector_inst/fifo40_inst/co2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_81:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_82:I17 -Signal fifo_colector_inst/fifo40_inst/co3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_82:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_83:I17 -Signal fifo_colector_inst/fifo40_inst/r_gctr_ci - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_84:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_85:I17 -Signal fifo_colector_inst/fifo40_inst/co0_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_85:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_86:I17 -Signal fifo_colector_inst/fifo40_inst/co1_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_86:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_87:I17 -Signal fifo_colector_inst/fifo40_inst/co2_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_87:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_88:I17 -Signal fifo_colector_inst/fifo40_inst/co3_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_88:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_89:I17 -Signal fifo_colector_inst/fifo40_inst/cmp_ci - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_90:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_91:I17 -Signal fifo_colector_inst/fifo40_inst/co0_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_91:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_92:I17 -Signal fifo_colector_inst/fifo40_inst/co1_2 - Driver Comp: - - Page 124 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/fifo40_inst/SLICE_92:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_93:I17 -Signal fifo_colector_inst/fifo40_inst/co2_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_93:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_94:I17 -Signal fifo_colector_inst/fifo40_inst/co3_2 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_94:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_95:I17 -Signal fifo_colector_inst/fifo40_inst/empty_d_c - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_95:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_96:I17 -Signal fifo_colector_inst/fifo40_inst/cmp_ci_1 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_97:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_98:I17 -Signal fifo_colector_inst/fifo40_inst/co0_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_98:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_99:I17 -Signal fifo_colector_inst/fifo40_inst/co1_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_99:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_100:I17 -Signal fifo_colector_inst/fifo40_inst/co2_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_100:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_101:I17 -Signal fifo_colector_inst/fifo40_inst/co3_3 - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_101:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_102:I17 -Signal fifo_colector_inst/fifo40_inst/full_d_c - Driver Comp: - fifo_colector_inst/fifo40_inst/SLICE_102:O6 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_103:I17 -Signal fifo_rden_c - Driver Comp: trb_adapter_inst/SLICE_188:O3 - Load Comps: trb_adapter_inst/SLICE_188:I1, trb_adapter_inst/SLICE_632:I4, - fifo_colector_inst/fifo40_inst/SLICE_720:I0, - trb_adapter_inst/SLICE_724:I16, FEE_DATA_WRITE_OUT_MGIOL:I10, - fifo_rden:I0 -Signal fifo_colector_inst/buffer_wr_enable - Driver Comp: - fifo_colector_inst/SLICE_125:O3 - Load Comps: fifo_colector_inst/fifo40_inst/SLICE_721:I0 -Signal fifo_colector_inst/iterator[1] - Driver Comp: - fifo_colector_inst/SLICE_187:O4 - Load Comps: fifo_colector_inst/SLICE_125:I4, fifo_colector_inst/SLICE_126:I3, - fifo_colector_inst/SLICE_126:I9, fifo_colector_inst/SLICE_127:I3, - fifo_colector_inst/SLICE_127:I9, fifo_colector_inst/SLICE_128:I3, - fifo_colector_inst/SLICE_128:I9, fifo_colector_inst/SLICE_129:I3, - fifo_colector_inst/SLICE_129:I9, fifo_colector_inst/SLICE_130:I3, - fifo_colector_inst/SLICE_130:I9, fifo_colector_inst/SLICE_131:I3, - fifo_colector_inst/SLICE_131:I9, fifo_colector_inst/SLICE_132:I3, - fifo_colector_inst/SLICE_132:I9, fifo_colector_inst/SLICE_133:I3, - fifo_colector_inst/SLICE_133:I9, fifo_colector_inst/SLICE_146:I5, - fifo_colector_inst/SLICE_187:I1, fifo_colector_inst/SLICE_189:I1, - fifo_colector_inst/SLICE_190:I0, fifo_colector_inst/SLICE_680:I1, - fifo_colector_inst/SLICE_722:I0 -Signal fifo_colector_inst/iterator[0] - Driver Comp: - fifo_colector_inst/SLICE_187:O3 - Load Comps: fifo_colector_inst/SLICE_125:I0, fifo_colector_inst/SLICE_126:I0, - fifo_colector_inst/SLICE_126:I6, fifo_colector_inst/SLICE_127:I0, - fifo_colector_inst/SLICE_127:I6, fifo_colector_inst/SLICE_128:I0, - - Page 125 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/SLICE_128:I6, fifo_colector_inst/SLICE_129:I0, - fifo_colector_inst/SLICE_129:I6, fifo_colector_inst/SLICE_130:I0, - fifo_colector_inst/SLICE_130:I6, fifo_colector_inst/SLICE_131:I0, - fifo_colector_inst/SLICE_131:I6, fifo_colector_inst/SLICE_132:I0, - fifo_colector_inst/SLICE_132:I6, fifo_colector_inst/SLICE_133:I0, - fifo_colector_inst/SLICE_133:I6, fifo_colector_inst/SLICE_134:I0, - fifo_colector_inst/SLICE_134:I6, fifo_colector_inst/SLICE_135:I0, - fifo_colector_inst/SLICE_135:I6, fifo_colector_inst/SLICE_136:I0, - fifo_colector_inst/SLICE_136:I6, fifo_colector_inst/SLICE_137:I0, - fifo_colector_inst/SLICE_137:I6, fifo_colector_inst/SLICE_138:I0, - fifo_colector_inst/SLICE_138:I6, fifo_colector_inst/SLICE_139:I0, - fifo_colector_inst/SLICE_139:I6, fifo_colector_inst/SLICE_140:I0, - fifo_colector_inst/SLICE_140:I6, fifo_colector_inst/SLICE_141:I0, - fifo_colector_inst/SLICE_141:I6, fifo_colector_inst/SLICE_142:I0, - fifo_colector_inst/SLICE_142:I6, fifo_colector_inst/SLICE_143:I0, - fifo_colector_inst/SLICE_143:I6, fifo_colector_inst/SLICE_144:I0, - fifo_colector_inst/SLICE_144:I6, fifo_colector_inst/SLICE_145:I0, - fifo_colector_inst/SLICE_145:I6, fifo_colector_inst/SLICE_146:I4, - fifo_colector_inst/SLICE_187:I0, fifo_colector_inst/SLICE_187:I5, - fifo_colector_inst/SLICE_189:I2, fifo_colector_inst/SLICE_189:I6, - fifo_colector_inst/SLICE_680:I6 -Signal fifo_colector_inst/fb_0 - Driver Comp: fifo_colector_inst/SLICE_189:O0 - Load Comps: fifo_colector_inst/SLICE_189:I12 -Signal fifo_colector_inst/in_empty_pmux_0 - Driver Comp: - fifo_colector_inst/SLICE_680:O1 - Load Comps: fifo_colector_inst/SLICE_680:I0 -Signal fifo_colector_inst/fb_0_0 - Driver Comp: fifo_colector_inst/SLICE_190:O0 - Load Comps: fifo_colector_inst/SLICE_190:I12 -Signal fifo_colector_inst/fb_0_1 - Driver Comp: fifo_colector_inst/SLICE_189:O1 - Load Comps: fifo_colector_inst/SLICE_189:I13 -Signal fifo_colector_inst/un5_in_read_enable - Driver Comp: - fifo_colector_inst/SLICE_187:O0 - Load Comps: fifo_colector_inst/SLICE_187:I12 -Signal fifo_colector_inst/in_empty_pmux - Driver Comp: - fifo_colector_inst/SLICE_680:O0 - Load Comps: fifo_colector_inst/SLICE_189:I16, - fifo_colector_inst/SLICE_190:I16 -Signal fifo_colector_inst/data_buffer_3[0] - Driver Comp: - fifo_colector_inst/SLICE_126:O2 - Load Comps: fifo_colector_inst/SLICE_126:I12 -Signal fifo_colector_inst/data_buffer_3[1] - Driver Comp: - fifo_colector_inst/SLICE_127:O2 - Load Comps: fifo_colector_inst/SLICE_127:I12 -Signal fifo_colector_inst/data_buffer_3[2] - Driver Comp: - fifo_colector_inst/SLICE_128:O2 - Load Comps: fifo_colector_inst/SLICE_128:I12 -Signal fifo_colector_inst/data_buffer_3[3] - Driver Comp: - fifo_colector_inst/SLICE_129:O2 - Load Comps: fifo_colector_inst/SLICE_129:I12 -Signal fifo_colector_inst/data_buffer_3[4] - Driver Comp: - fifo_colector_inst/SLICE_130:O2 - Load Comps: fifo_colector_inst/SLICE_130:I12 -Signal fifo_colector_inst/data_buffer_3[5] - Driver Comp: - fifo_colector_inst/SLICE_131:O2 - Load Comps: fifo_colector_inst/SLICE_131:I12 -Signal fifo_colector_inst/data_buffer_3[6] - Driver Comp: - - Page 126 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - fifo_colector_inst/SLICE_132:O2 - Load Comps: fifo_colector_inst/SLICE_132:I12 -Signal fifo_colector_inst/data_buffer_3[7] - Driver Comp: - fifo_colector_inst/SLICE_133:O2 - Load Comps: fifo_colector_inst/SLICE_133:I12 -Signal fifo_colector_inst/data_buffer_3[8] - Driver Comp: - fifo_colector_inst/SLICE_134:O0 - Load Comps: fifo_colector_inst/SLICE_134:I12 -Signal fifo_colector_inst/data_buffer_3[9] - Driver Comp: - fifo_colector_inst/SLICE_134:O1 - Load Comps: fifo_colector_inst/SLICE_134:I13 -Signal fifo_colector_inst/data_buffer_3[10] - Driver Comp: - fifo_colector_inst/SLICE_135:O0 - Load Comps: fifo_colector_inst/SLICE_135:I12 -Signal fifo_colector_inst/data_buffer_3[11] - Driver Comp: - fifo_colector_inst/SLICE_135:O1 - Load Comps: fifo_colector_inst/SLICE_135:I13 -Signal fifo_colector_inst/data_buffer_3[12] - Driver Comp: - fifo_colector_inst/SLICE_136:O0 - Load Comps: fifo_colector_inst/SLICE_136:I12 -Signal fifo_colector_inst/data_buffer_3[13] - Driver Comp: - fifo_colector_inst/SLICE_136:O1 - Load Comps: fifo_colector_inst/SLICE_136:I13 -Signal fifo_colector_inst/data_buffer_3[14] - Driver Comp: - fifo_colector_inst/SLICE_137:O0 - Load Comps: fifo_colector_inst/SLICE_137:I12 -Signal fifo_colector_inst/data_buffer_3[15] - Driver Comp: - fifo_colector_inst/SLICE_137:O1 - Load Comps: fifo_colector_inst/SLICE_137:I13 -Signal fifo_colector_inst/data_buffer_3[16] - Driver Comp: - fifo_colector_inst/SLICE_138:O0 - Load Comps: fifo_colector_inst/SLICE_138:I12 -Signal fifo_colector_inst/data_buffer_3[17] - Driver Comp: - fifo_colector_inst/SLICE_138:O1 - Load Comps: fifo_colector_inst/SLICE_138:I13 -Signal fifo_colector_inst/data_buffer_3[18] - Driver Comp: - fifo_colector_inst/SLICE_139:O0 - Load Comps: fifo_colector_inst/SLICE_139:I12 -Signal fifo_colector_inst/data_buffer_3[19] - Driver Comp: - fifo_colector_inst/SLICE_139:O1 - Load Comps: fifo_colector_inst/SLICE_139:I13 -Signal fifo_colector_inst/data_buffer_3[20] - Driver Comp: - fifo_colector_inst/SLICE_140:O0 - Load Comps: fifo_colector_inst/SLICE_140:I12 -Signal fifo_colector_inst/data_buffer_3[21] - Driver Comp: - fifo_colector_inst/SLICE_140:O1 - Load Comps: fifo_colector_inst/SLICE_140:I13 -Signal fifo_colector_inst/data_buffer_3[22] - Driver Comp: - fifo_colector_inst/SLICE_141:O0 - Load Comps: fifo_colector_inst/SLICE_141:I12 -Signal fifo_colector_inst/data_buffer_3[23] - Driver Comp: - fifo_colector_inst/SLICE_141:O1 - Load Comps: fifo_colector_inst/SLICE_141:I13 -Signal fifo_colector_inst/data_buffer_3[24] - Driver Comp: - fifo_colector_inst/SLICE_142:O0 - Load Comps: fifo_colector_inst/SLICE_142:I12 - - Page 127 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal fifo_colector_inst/data_buffer_3[25] - Driver Comp: - fifo_colector_inst/SLICE_142:O1 - Load Comps: fifo_colector_inst/SLICE_142:I13 -Signal fifo_colector_inst/data_buffer_3[26] - Driver Comp: - fifo_colector_inst/SLICE_143:O0 - Load Comps: fifo_colector_inst/SLICE_143:I12 -Signal fifo_colector_inst/data_buffer_3[27] - Driver Comp: - fifo_colector_inst/SLICE_143:O1 - Load Comps: fifo_colector_inst/SLICE_143:I13 -Signal fifo_colector_inst/data_buffer_3[28] - Driver Comp: - fifo_colector_inst/SLICE_144:O0 - Load Comps: fifo_colector_inst/SLICE_144:I12 -Signal fifo_colector_inst/data_buffer_3[29] - Driver Comp: - fifo_colector_inst/SLICE_144:O1 - Load Comps: fifo_colector_inst/SLICE_144:I13 -Signal fifo_colector_inst/data_buffer_3[30] - Driver Comp: - fifo_colector_inst/SLICE_145:O0 - Load Comps: fifo_colector_inst/SLICE_145:I12 -Signal finished_c - Driver Comp: trb_adapter_inst/SLICE_724:O3 - Load Comps: trb_adapter_inst/SLICE_633:I4, trb_adapter_inst/SLICE_724:I0, - finished:I0, FEE_DATAFINISHED_OUT_MGIOL:I10 -Signal trb_adapter_inst/finished_prev - Driver Comp: - trb_adapter_inst/SLICE_633:O3 - Load Comps: trb_adapter_inst/SLICE_724:I1 -Signal trb_adapter_inst/buf_rden_prev - Driver Comp: - trb_adapter_inst/SLICE_632:O3 - Load Comps: trb_adapter_inst/SLICE_724:I4 -Signal trb_adapter_inst/buf_rden4 - Driver Comp: trb_adapter_inst/SLICE_188:O0 - Load Comps: trb_adapter_inst/SLICE_188:I12 -Signal trb_adapter_inst.LVL1_TRG_DATA_VALID_IN_dl[0] - Driver Comp: - LVL1_TRG_DATA_VALID_IN_MGIOL:O2 - Load Comps: trb_adapter_inst/SLICE_631:I4 -Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[1] - Driver Comp: - trb_adapter_inst/SLICE_631:O3 - Load Comps: trb_adapter_inst/SLICE_188:I8, trb_adapter_inst/SLICE_631:I5, - trb_adapter_inst/SLICE_723:I0 -Signal trb_adapter_inst/LVL1_TRG_DATA_VALID_IN_dl[2] - Driver Comp: - trb_adapter_inst/SLICE_631:O4 - Load Comps: trb_adapter_inst/SLICE_188:I7, trb_adapter_inst/SLICE_723:I1 -Signal trb_adapter_inst.LVL1_INVALID_TRG_IN_dl[0] - Driver Comp: - LVL1_INVALID_TRG_IN_MGIOL:O2 - Load Comps: trb_adapter_inst/SLICE_124:I4 -Signal discard_c - Driver Comp: trb_adapter_inst/SLICE_124:O3 - Load Comps: trb_adapter_inst/SLICE_188:I6, discard:I0 -Signal burst_c - Driver Comp: trb_adapter_inst/SLICE_188:O1 - Load Comps: trb_adapter_inst/SLICE_188:I0, burst:I0 -Signal LVL1_TRG_DATA_VALI_IN_rising_c - Driver Comp: - trb_adapter_inst/SLICE_723:O0 - Load Comps: LVL1_TRG_DATA_VALI_IN_rising:I0 -Signal release_out_c - Driver Comp: trb_adapter_inst/SLICE_724:O0 - Load Comps: release_out:I0, FEE_TRG_RELEASE_OUT_MGIOL:I10 -Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_cry - Driver Comp: - hades_tdc_bundle_inst/SLICE_120:O6 - Load Comps: hades_tdc_bundle_inst/SLICE_104:I17 -Signal hades_tdc_bundle_inst/hit_valid25 - Driver Comp: - hades_tdc_bundle_inst/SLICE_104:O0 - - Page 128 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: hades_tdc_bundle_inst/SLICE_456:I2, - hades_tdc_bundle_inst/SLICE_458:I1, hades_tdc_bundle_inst/SLICE_458:I7, - hades_tdc_bundle_inst/SLICE_710:I7 -Signal hades_tdc_bundle_inst/buf_finished5 - Driver Comp: - hades_tdc_bundle_inst/SLICE_432:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_432:I12 -Signal hades_buf_finished_c - Driver Comp: hades_tdc_bundle_inst/SLICE_432:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_433:I4, hades_buf_finished:I0 -Signal hades_dbg2_out_c[12] - Driver Comp: hades_tdc_bundle_inst/SLICE_443:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_449:I4, hades_dbg2_out[12]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_0_sqmuxa - Driver Comp: SLICE_740:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_445:I14, - hades_tdc_bundle_inst/SLICE_446:I14, - hades_tdc_bundle_inst/SLICE_447:I14, - hades_tdc_bundle_inst/SLICE_448:I14, - hades_tdc_bundle_inst/SLICE_449:I14, - hades_tdc_bundle_inst/SLICE_450:I14, - hades_tdc_bundle_inst/SLICE_451:I14, - hades_tdc_bundle_inst/SLICE_452:I14, - hades_tdc_bundle_inst/SLICE_453:I14, - hades_tdc_bundle_inst/SLICE_454:I14, hades_tdc_bundle_inst/SLICE_455:I14 - -Signal hades_drop_cmp_buf_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_449:O3 - - Load Comps: hades_tdc_bundle_inst/SLICE_120:I8, hades_drop_cmp_buf[8]:I0 -Signal hades_tdc_bundle_inst/hades_raw_out_valid - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I0, - hades_tdc_bundle_inst/SLICE_459:I6, hades_tdc_bundle_inst/SLICE_460:I6, - hades_tdc_bundle_inst/SLICE_628:I0, hades_tdc_bundle_inst/SLICE_628:I8, - hades_tdc_bundle_inst/SLICE_693:I1, hades_tdc_bundle_inst/SLICE_693:I8 -Signal hades_tdc_bundle_inst/hit_i[0] - Driver Comp: - hades_tdc_bundle_inst/SLICE_628:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I1, - hades_tdc_bundle_inst/SLICE_459:I7, hades_tdc_bundle_inst/SLICE_460:I7, - hades_tdc_bundle_inst/SLICE_628:I1, hades_tdc_bundle_inst/SLICE_628:I7, - hades_tdc_bundle_inst/SLICE_693:I2, hades_tdc_bundle_inst/SLICE_693:I7 -Signal hades_tdc_bundle_inst/hit_i[1] - Driver Comp: - hades_tdc_bundle_inst/SLICE_628:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I4, - hades_tdc_bundle_inst/SLICE_459:I4, hades_tdc_bundle_inst/SLICE_460:I4, - hades_tdc_bundle_inst/SLICE_628:I6, hades_tdc_bundle_inst/SLICE_693:I3, - hades_tdc_bundle_inst/SLICE_693:I6 -Signal un1_hit_i_2_0_a2 - Driver Comp: hades_tdc_bundle_inst/SLICE_693:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_439:I14, - hades_tdc_bundle_inst/SLICE_440:I14, - hades_tdc_bundle_inst/SLICE_441:I14, - hades_tdc_bundle_inst/SLICE_442:I14, - hades_tdc_bundle_inst/SLICE_443:I14, hades_dbg2_out[28]_MGIOL:I8, - hades_dbg2_out[27]_MGIOL:I8, hades_dbg2_out[26]_MGIOL:I8, - hades_dbg2_out[25]_MGIOL:I8, hades_dbg2_out[24]_MGIOL:I8, - hades_dbg2_out[23]_MGIOL:I8, hades_dbg2_out[22]_MGIOL:I8, - hades_dbg2_out[21]_MGIOL:I8, hades_dbg2_out[20]_MGIOL:I8, - hades_dbg2_out[18]_MGIOL:I8, hades_dbg2_out[17]_MGIOL:I8, - hades_dbg2_out[16]_MGIOL:I8, hades_dbg2_out[2]_MGIOL:I8, - hades_dbg2_out[1]_MGIOL:I8, hades_dbg2_out[0]_MGIOL:I8 - - Page 129 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out - _internal35_1_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_ - out_inst/dec_neg_inst/SLICE_573:O2 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_573:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed7_rising_i - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out - _inst/dec_neg_inst/SLICE_726:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec - _neg_inst/SLICE_572:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out - _inst/dec_neg_inst/SLICE_573:I16 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/valid_i - nternal - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst - /dec_neg_inst/SLICE_573:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_725:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid_neg - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i - nst/SLICE_725:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I2, hades - _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I - 1 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int - ernal[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins - t/dec_neg_inst/SLICE_571:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_576:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[0] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i - nst/SLICE_576:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I4 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_1 - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_571:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int - ernal[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins - t/dec_neg_inst/SLICE_571:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_576:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[1] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i - nst/SLICE_576:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I5 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1 - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_571:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I13 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/out_int - ernal[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_ins - - Page 130 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - t/dec_neg_inst/SLICE_572:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_577:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out_neg[2] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i - nst/SLICE_577:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I4 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/N_5 - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_i - nst/SLICE_572:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I12 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][0] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_563:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_567:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_567:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_573:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_728:I0 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][1] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_563:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_567:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_567:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_573:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_694:I6, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_728:I1 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][2] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_564:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_568:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_568:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_573:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_694:I0, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_694:I7, hades_tdc_bundle_inst/hades_tdc_c - hannel_raw_out_inst/dec_neg_inst/SLICE_729:I0 -Signal - - Page 131 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][3] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_564:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_568:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_568:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_694:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_694:I8, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_727:I0, hades_tdc_bundle_inst/hades_tdc_c - hannel_raw_out_inst/dec_neg_inst/SLICE_729:I1 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][4] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_565:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_569:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_569:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_694:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_694:I9, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_727:I1, hades_tdc_bundle_inst/hades_tdc_c - hannel_raw_out_inst/dec_neg_inst/SLICE_728:I2 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][5] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_565:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_569:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_569:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_572:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_694:I3, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_727:I2, hades_tdc_bundle_inst/hades_tdc_c - hannel_raw_out_inst/dec_neg_inst/SLICE_728:I3, hades_tdc_bundle_inst/had - es_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_729:I2 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][6] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_566:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_570:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_570:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_572:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - - Page 132 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - neg_inst/SLICE_727:I3 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[1][7] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_566:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_570:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_726:I0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/in_sync - ed[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/d - ec_neg_inst/SLICE_570:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_726:I1 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][0] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_559:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_563:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][1] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_559:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_563:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][2] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_560:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_564:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][3] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_560:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_564:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][4] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_561:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_565:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][5] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_561:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_565:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][6] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_562:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_566:I4 -Signal - - Page 133 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/dl[0][7] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_562:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_566:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[0] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_620:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_559:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[1] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_621:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_559:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[2] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_622:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_560:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[3] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_623:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_560:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[4] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_624:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_561:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[5] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_625:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_561:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[6] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_626:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_562:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out_neg[7] - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_i - nst/SLICE_627:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_562:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out - _internal35_1_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_neg_inst/SLICE_694:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_573:I3 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out - _internal35_1_0_0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_ra - w_out_inst/dec_neg_inst/SLICE_727:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_573:I4 - - Page 134 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_m3 - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_729:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I1 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/un1_out - _internal31_1_i_0_o5 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel - _raw_out_inst/dec_neg_inst/SLICE_572:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_571:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_neg_inst/SLICE_572:I0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m11_i_0 - - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg - _inst/SLICE_728:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I3 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive_ready - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I1, hades - _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLICE_725:I - 0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_11_i - Driver - Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/SLI - CE_725:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I14 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/m15_i_1 - _0 - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - neg_inst/SLICE_694:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst - /SLICE_571:I8 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int - ernal35_1_i - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O2 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_558:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced7_ - rising_i - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_730:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ins - t/SLICE_556:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/de - c_inst/SLICE_557:I16, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/dec_inst/SLICE_558:I16 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/valid_inter - - Page 135 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - nal - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_558:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_731:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_valid - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I2, hades - _tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:I0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_0 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna - l[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_574:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I4 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna - l[1] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_574:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_574:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I5 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_0 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_556:O2 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_556:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/out_interna - l[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_575:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/decoder_out[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_575:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I4 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int - ernal31_1_i_0_0 - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_557:O2 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_557:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][0] - - - Page 136 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_551:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_556:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_558:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_696:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_696:I6 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_547:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_551:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_551:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_558:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_695:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_696:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_696:I7 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_552:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_556:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_558:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_695:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_inst/SLICE_695:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_o - ut_inst/dec_inst/SLICE_696:I2, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/dec_inst/SLICE_696:I8 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][3] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_548:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_552:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_552:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_557:I6, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - - Page 137 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - inst/SLICE_695:I2, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_695:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_inst/SLICE_732:I0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][4] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_553:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_557:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_695:I3, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_695:I8, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_inst/SLICE_732:I1 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][5] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_549:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_553:I5 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_553:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_556:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_557:I7, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_695:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/dec_inst/SLICE_696:I9, hades_tdc_bundle_inst/hades_tdc_channel_raw_o - ut_inst/dec_inst/SLICE_732:I2 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][6] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_554:I4 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_556:I1, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_ - inst/SLICE_557:I4, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - dec_inst/SLICE_732:I3 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[1][7] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_550:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_554:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_730:I0 -Signal - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/in_synced[7] - - Page 138 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_554:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_730:I1 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][0] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_547:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_543:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_547:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_548:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][3] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_544:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_548:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][4] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_549:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][5] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_545:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_549:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][6] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_550:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/dl[0][7] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_546:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_550:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[0] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_612:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_543:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[1] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_613:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_543:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[2] - Driver - Comp: - - Page 139 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_614:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_544:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[3] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_615:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_544:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[4] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_616:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_545:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[5] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_617:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_545:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[6] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_618:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_546:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_out[7] - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_619:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_546:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_268 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_557:I8 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/N_269 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_555:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I0, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst - /SLICE_558:I3 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/un1_out_int - ernal35_1_0_0 - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_732:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_558:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m15_i_3 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_556:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_251_i - Driver - Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_731:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I14, - - Page 140 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I14 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_695:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I2 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/m11_i_1_0 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLICE_696:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/SLI - CE_555:I3 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_607:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_607:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[3] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_607:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_623:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_611:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_627:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[7] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_611:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_611:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_606:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_606:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[2] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_606:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_622:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_610:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_626:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[6] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_610:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_610:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_605:O3 - - Page 141 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_621:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[1] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_605:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_605:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_609:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_625:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[5] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_609:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_609:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_604:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_620:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[0] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_604:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_604:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/out_buf - fered1[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_608:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_624:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/in_clk_ - synced[4] - Driver Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_in - st/tdc_neg_inst/SLICE_608:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_608:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[3] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_591:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[3] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_591:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_615:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[7] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_619:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[7] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_595:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - - Page 142 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - CE_595:I4 -Signal hades_trig_c_i - Driver Comp: SLICE_747:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_588:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst - /SLICE_589:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ - inst/SLICE_590:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/ - tdc_inst/SLICE_591:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/tdc_inst/SLICE_592:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_o - ut_inst/tdc_inst/SLICE_593:I5, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/tdc_inst/SLICE_594:I5, hades_tdc_bundle_inst/hades_tdc_chann - el_raw_out_inst/tdc_inst/SLICE_595:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_614:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_590:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_590:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[6] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_594:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[6] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_594:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_618:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[1] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_589:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[1] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_589:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_613:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[5] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_617:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[5] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_593:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_593:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_588:I4 - - Page 143 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_588:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_612:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/in_clk_sync - ed[4] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_592:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/out_buffere - d1[4] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLICE_592:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/SLI - CE_616:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I0 -Signal hades_dbg2_coarse_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_435:I2, - hades_tdc_bundle_inst/SLICE_435:I7, hades_tdc_bundle_inst/SLICE_438:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I5, - hades_tdc_bundle_inst/SLICE_681:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I7, - hades_dbg2_coarse[2]:I0, hades_offset[5]_MGIOL:I10 -Signal hades_dbg2_coarse_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I9, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I9, - hades_tdc_bundle_inst/SLICE_434:I7, hades_tdc_bundle_inst/SLICE_435:I1, - hades_tdc_bundle_inst/SLICE_435:I8, hades_tdc_bundle_inst/SLICE_438:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:I4, - hades_tdc_bundle_inst/SLICE_681:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I2, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I8, - hades_dbg2_coarse[1]:I0, hades_offset[4]_MGIOL:I10 -Signal hades_dbg2_coarse_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_434:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I8, - hades_tdc_bundle_inst/SLICE_434:I0, hades_tdc_bundle_inst/SLICE_434:I6, - hades_tdc_bundle_inst/SLICE_435:I0, hades_tdc_bundle_inst/SLICE_435:I9, - hades_tdc_bundle_inst/SLICE_438:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:I5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:I5, - hades_tdc_bundle_inst/SLICE_681:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I3, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I9, - hades_dbg2_coarse[0]:I0, hades_offset[3]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_19 - - Page 144 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I0 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:I6 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N - _19 - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_697:O1 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I0 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_249_i - Driver - Comp: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I14, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I4 - -Signal hades_tdc_bundle_inst.hades_raw_out[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O3 - Load Comps: hades_dbg2_out[0]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_536:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:I5 - -Signal hades_tdc_bundle_inst.hades_raw_out[1] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_466:O4 - Load Comps: hades_dbg2_out[1]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I4 - -Signal hades_tdc_bundle_inst.hades_raw_out[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O3 - Load Comps: hades_dbg2_out[2]_MGIOL:I10 - - Page 145 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_537:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I4 -Signal hades_tdc_bundle_inst/hades_raw_out[3] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_439:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_538:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:I5 -Signal hades_tdc_bundle_inst/hades_raw_out[4] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_523:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_439:I5 -Signal hades_tdc_bundle_inst/hades_raw_out[5] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_440:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:I5 -Signal hades_tdc_bundle_inst/hades_raw_out[6] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_524:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_440:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[7] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I4, - hades_tdc_bundle_inst/SLICE_681:I3 -Signal hades_tdc_bundle_inst/hades_raw_out[7] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_441:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[8] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:I5 -Signal hades_tdc_bundle_inst/hades_raw_out[8] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_525:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_441:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[9] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I4 - -Signal hades_tdc_bundle_inst/hades_raw_out[9] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_442:I4 - - Page 146 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[10] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:I5 - -Signal hades_tdc_bundle_inst/hades_raw_out[10] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_526:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_442:I5 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_positive[11] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:I4 - -Signal hades_tdc_bundle_inst/hades_raw_out[11] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_527:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_443:I4 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:I5 - -Signal hades_tdc_bundle_inst.hades_raw_out[12] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_467:O4 - Load Comps: hades_dbg2_out[16]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_529:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I4 - -Signal hades_tdc_bundle_inst.hades_raw_out[13] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O3 - Load Comps: hades_dbg2_out[17]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:I5 - -Signal hades_tdc_bundle_inst.hades_raw_out[14] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_468:O4 - Load Comps: hades_dbg2_out[18]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_530:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I4 -Signal hades_tdc_bundle_inst.hades_raw_out[15] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O3 - Load Comps: hades_dbg2_out[20]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_531:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:I5 -Signal hades_tdc_bundle_inst.hades_raw_out[16] - Driver Comp: - - Page 147 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_469:O4 - Load Comps: hades_dbg2_out[21]_MGIOL:I10 -Signal hades_tdc_bundle_inst.hades_raw_out[17] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O3 - Load Comps: hades_dbg2_out[22]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:I5 -Signal hades_tdc_bundle_inst.hades_raw_out[18] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_470:O4 - Load Comps: hades_dbg2_out[23]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[7] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I4, - hades_tdc_bundle_inst/SLICE_698:I3 -Signal hades_tdc_bundle_inst.hades_raw_out[19] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O3 - Load Comps: hades_dbg2_out[24]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[8] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:I5 -Signal hades_tdc_bundle_inst.hades_raw_out[20] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_471:O4 - Load Comps: hades_dbg2_out[25]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[9] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I4 - -Signal hades_tdc_bundle_inst.hades_raw_out[21] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O3 - Load Comps: hades_dbg2_out[26]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[10] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O3 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:I5 - -Signal hades_tdc_bundle_inst.hades_raw_out[22] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_472:O4 - Load Comps: hades_dbg2_out[27]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative[11] - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:O4 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:I4 - -Signal hades_tdc_bundle_inst.hades_raw_out[23] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_473:O3 - Load Comps: hades_dbg2_out[28]_MGIOL:I10 - - Page 148 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_7 - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I12 -Signal hades_dbg2_coarse_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_435:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I3, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I3, - hades_tdc_bundle_inst/SLICE_435:I6, hades_tdc_bundle_inst/SLICE_436:I0, - hades_tdc_bundle_inst/SLICE_436:I6, hades_tdc_bundle_inst/SLICE_437:I0, - hades_tdc_bundle_inst/SLICE_438:I9, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I4, - hades_tdc_bundle_inst/SLICE_681:I0, hades_tdc_bundle_inst/SLICE_698:I0, - hades_tdc_bundle_inst/SLICE_698:I6, hades_dbg2_coarse[3]:I0, - hades_offset[6]_MGIOL:I10 -Signal hades_dbg2_coarse_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_436:I1, - hades_tdc_bundle_inst/SLICE_436:I7, hades_tdc_bundle_inst/SLICE_455:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_532:I5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_539:I5, - hades_tdc_bundle_inst/SLICE_681:I1, hades_tdc_bundle_inst/SLICE_698:I1, - hades_tdc_bundle_inst/SLICE_698:I7, hades_tdc_bundle_inst/SLICE_701:I6, - hades_dbg2_coarse[4]:I0, hades_offset[7]_MGIOL:I10 -Signal hades_dbg2_coarse_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_436:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I9, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I9, - hades_tdc_bundle_inst/SLICE_436:I8, hades_tdc_bundle_inst/SLICE_455:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I4, - hades_tdc_bundle_inst/SLICE_701:I7, hades_dbg2_coarse[5]:I0, - hades_offset[8]_MGIOL:I10 -Signal hades_dbg2_coarse_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I0, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I0, - hades_tdc_bundle_inst/SLICE_437:I1, hades_tdc_bundle_inst/SLICE_437:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_533:I5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_540:I5, - hades_tdc_bundle_inst/SLICE_701:I0, hades_dbg2_coarse[6]:I0 -Signal hades_dbg2_coarse_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_437:O4 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I1, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I1, - hades_tdc_bundle_inst/SLICE_437:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I4, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I4, - hades_tdc_bundle_inst/SLICE_701:I1, hades_dbg2_coarse[7]:I0 -Signal hades_dbg2_coarse_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_438:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I6, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I6, - hades_tdc_bundle_inst/SLICE_438:I0, hades_tdc_bundle_inst/SLICE_455:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_534:I5, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_541:I5, - - Page 149 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_dbg2_coarse[8]:I0 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready_4 - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I12 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/buf_negative_ready - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:O3 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_528:I0, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I0, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c3 - Driver Comp: - hades_tdc_bundle_inst/SLICE_681:O1 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I2, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I2, - hades_tdc_bundle_inst/SLICE_436:I2, hades_tdc_bundle_inst/SLICE_436:I9, - hades_tdc_bundle_inst/SLICE_437:I3, hades_tdc_bundle_inst/SLICE_681:I2, - hades_tdc_bundle_inst/SLICE_698:I2, hades_tdc_bundle_inst/SLICE_698:I8 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_N - _14 - Driver Comp: hades_tdc_bundle_inst/SLICE_681:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I6 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_N_14 - - Driver Comp: hades_tdc_bundle_inst/SLICE_698:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I6 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_i - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_542:I3 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_i - - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_535:I3 - -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_ - tmp[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_105:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I17 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c5 - Driver Comp: - hades_tdc_bundle_inst/SLICE_698:O1 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I8 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_data_ - tmp[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_106:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I17 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_9_0 - Driver Comp: - hades_tdc_bundle_inst/SLICE_701:O1 - - Page 150 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I2, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I8, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I2, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I8, - hades_tdc_bundle_inst/SLICE_437:I2, hades_tdc_bundle_inst/SLICE_437:I8, - hades_tdc_bundle_inst/SLICE_438:I1 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_c4 - Driver Comp: - hades_tdc_bundle_inst/SLICE_438:O1 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I3, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I9, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I3, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I9, - hades_tdc_bundle_inst/SLICE_437:I9, hades_tdc_bundle_inst/SLICE_438:I3, - hades_tdc_bundle_inst/SLICE_455:I4 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2_ac0_13_0 - Driver Comp: - hades_tdc_bundle_inst/SLICE_701:O0 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:I7, - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I7, - hades_tdc_bundle_inst/SLICE_438:I2, hades_tdc_bundle_inst/SLICE_455:I9 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_ - cry - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_107:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_108:I17 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d - ata_tmp[0] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_109:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:I17 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_d - ata_tmp[2] - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_110:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:I17 -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _27_cry - Driver Comp: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_111:O6 - Load Comps: - hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/SLICE_112:I17 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxadup - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I12, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I16 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I16 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I0, - - Page 151 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I6 -Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_1_sqmuxa_i_0 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I14, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I1, - hades_offset[8]_MGIOL:I8, hades_offset[7]_MGIOL:I8, - hades_offset[6]_MGIOL:I8, hades_offset[5]_MGIOL:I8, - hades_offset[4]_MGIOL:I8, hades_offset[3]_MGIOL:I8, - hades_offset[2]_MGIOL:I8, hades_offset[1]_MGIOL:I8, - hades_offset[0]_MGIOL:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/valid_fast - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I2 -Signal hades_discard_c - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_123:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I0, - hades_tdc_bundle_inst/SLICE_741:I0, hades_discard:I0 -Signal valid_fast_RNI999V - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_733:O0 - Load Comps: hades_offset[8]_MGIOL:I9, hades_offset[7]_MGIOL:I9, - hades_offset[6]_MGIOL:I9, hades_offset[5]_MGIOL:I9, - hades_offset[4]_MGIOL:I9, hades_offset[3]_MGIOL:I9, - hades_offset[2]_MGIOL:I9, hades_offset[1]_MGIOL:I9, - hades_offset[0]_MGIOL:I9 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35 - _1_i - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O2 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I12 -Signal - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced7_rising_i - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I16, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I16 - - Page 152 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/valid_internal - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/decoder_valid - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_490:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I4 -Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[0] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O3 - Load Comps: hades_offset[0]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:I5 -Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464:O4 - Load Comps: hades_offset[1]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:O2 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal31 - _1_i_0 - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O2 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/out_internal[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:I4 -Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.offset_5[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465:O3 - Load Comps: hades_offset[2]_MGIOL:I10 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][0] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O3 - Load Comps: - - Page 153 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I6 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][1] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_482:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I7 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][2] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][3] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_483:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][4] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O3 - - Page 154 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][5] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_484:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][6] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:I3 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[1][7] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced[7] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_485:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_734:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][0] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][1] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_478:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][2] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][3] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:O4 - - Page 155 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_479:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][4] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][5] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_480:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][6] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/dl[0][7] - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_481:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[0] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[3] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_475:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[4] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[5] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_476:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[6] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_out[7] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_477:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_290 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_488:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/N_291 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:O1 - - Page 156 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I3 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/un1_out_internal35 - _1_0_0 - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_489:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m15_i_3 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_487:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_699:O1 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/m11_i_1_0 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_700:O1 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_486:I3 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_4_0 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O1 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/G_25_0_a3_5_0 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2_0 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_510:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[3] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[7] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[7] - - - Page 157 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_514:I4 -Signal hades_lvl1_c_i - Driver Comp: SLICE_743:O0 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_502:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I5, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_506:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[2] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_501:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_509:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_513:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[6] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_505:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[1] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_500:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_508:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_512:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[5] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_504:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[0] - - Driver Comp: - - Page 158 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[0] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_499:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_507:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/out_buffered1[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O3 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_511:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/in_clk_synced[4] - - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:O4 - Load Comps: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/SLICE_503:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[0] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_2 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[0] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[3] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I3 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O4 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_516:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I2 -Signal hades_invalid_dl_c[3] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I1, - hades_invalid_dl[3]:I0 -Signal hades_invalid_dl_c[2] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O4 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_462:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_520:I0, - hades_invalid_dl[2]:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_0_sqmuxa - Driver - - Page 159 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I9, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I12 -Signal hades_tdc_bundle_inst/SUM1_0_0 - Driver Comp: - hades_tdc_bundle_inst/SLICE_628:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_628:I13 -Signal ANB3 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I7, - hades_tdc_bundle_inst/SLICE_122:I6, hades_tdc_bundle_inst/SLICE_123:I1, - hades_tdc_bundle_inst/SLICE_432:I2, hades_tdc_bundle_inst/SLICE_432:I7, - hades_tdc_bundle_inst/SLICE_653:I1, hades_tdc_bundle_inst/SLICE_654:I8, - hades_tdc_bundle_inst/SLICE_683:I7, hades_hit_out_i[3]:I0 -Signal ANB2 - Driver Comp: hades_tdc_bundle_inst/SLICE_123:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I9, - hades_tdc_bundle_inst/SLICE_122:I7, hades_tdc_bundle_inst/SLICE_123:I3, - hades_tdc_bundle_inst/SLICE_123:I7, hades_tdc_bundle_inst/SLICE_432:I0, - hades_tdc_bundle_inst/SLICE_653:I3, hades_tdc_bundle_inst/SLICE_654:I0, - hades_tdc_bundle_inst/SLICE_654:I7, hades_hit_out_i[2]:I0 -Signal ANB1 - Driver Comp: hades_tdc_bundle_inst/SLICE_122:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I6, - hades_tdc_bundle_inst/SLICE_122:I1, hades_tdc_bundle_inst/SLICE_122:I8, - hades_tdc_bundle_inst/SLICE_123:I2, hades_tdc_bundle_inst/SLICE_123:I6, - hades_tdc_bundle_inst/SLICE_432:I3, hades_tdc_bundle_inst/SLICE_432:I6, - hades_tdc_bundle_inst/SLICE_653:I2, hades_tdc_bundle_inst/SLICE_654:I6, - hades_tdc_bundle_inst/SLICE_683:I8, hades_hit_out_i[1]:I0 -Signal ANB0 - Driver Comp: hades_tdc_bundle_inst/SLICE_121:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I0, - hades_tdc_bundle_inst/SLICE_121:I8, hades_tdc_bundle_inst/SLICE_122:I0, - hades_tdc_bundle_inst/SLICE_122:I9, hades_tdc_bundle_inst/SLICE_123:I4, - hades_tdc_bundle_inst/SLICE_432:I1, hades_tdc_bundle_inst/SLICE_653:I0, - hades_tdc_bundle_inst/SLICE_683:I6, hades_tdc_bundle_inst/SLICE_710:I0, - hades_hit_out_i[0]:I0 -Signal hades_tdc_bundle_inst/N_50_i_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_122:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_122:I13 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_end5 - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I12 -Signal hades_window_end_c - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_741:I1, hades_window_end:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I4, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[3] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I13 - - Page 160 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[3] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:O4 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I7, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[4] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[4] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_739:I3 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[5] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I13 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[5] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:O4 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I1, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I7 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[6] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I12 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[6] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window_6[7] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I13 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/window[7] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:O4 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I3, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:I9 -Signal hades_tdc_bundle_inst.hades_LVL1_raw_out_inst.trig_dl[0] - Driver Comp: - hades_lvl1_MGIOL:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I4 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/trig_dl[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_515:I5 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_39_i - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:I12 -Signal hades_offset_valid_c - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_463:O3 - Load Comps: hades_offset_valid:I0, hades_raw_out_valid_MGIOL:I10 -Signal hades_invalid_dl_c[1] - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:O3 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_461:I5, - - Page 161 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_invalid_dl[1]:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard_en - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I14 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_1 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:O2 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_518:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_737:I1 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_97 - Driver Comp: - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_444:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_634:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I0 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_reset_0_a2_c - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I8, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I2, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S0 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S1 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_522:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_5_0_S0 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S1 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_521:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_3_0_S0 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I8 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S1 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O1 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_738:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_1_0_S0 - - Driver Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_519:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/discard4_0_a2_0_3 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_684:O0 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_629:I6, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_635:I0, - hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_682:I6 -Signal hades_tdc_bundle_inst/N_59_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_628:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_628:I12 -Signal hades_tdc_bundle_inst/N_46_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_122:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_122:I12 -Signal hades_tdc_bundle_inst/N_44 - Driver Comp: - hades_tdc_bundle_inst/SLICE_693:O1 - - Page 162 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: hades_tdc_bundle_inst/SLICE_458:I2 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_113:O6 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:I17 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_2 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_114:O6 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:I17 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_4 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_115:O6 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:I17 -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_6 - Driver - Comp: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_116:O6 - Load Comps: hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/SLICE_117:I17 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[3] - Driver Comp: - hades_tdc_bundle_inst/SLICE_435:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_435:I13, - hades_tdc_bundle_inst/SLICE_451:I5 -Signal hades_dbg2_out_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_445:I4, hades_dbg2_out[4]:I0 -Signal hades_dbg2_out_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_439:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_445:I5, hades_dbg2_out[5]:I0 -Signal hades_dbg2_out_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_446:I4, hades_dbg2_out[6]:I0 -Signal hades_dbg2_out_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_440:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_446:I5, hades_dbg2_out[7]:I0 -Signal hades_dbg2_out_c[8] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_447:I4, hades_dbg2_out[8]:I0 -Signal hades_dbg2_out_c[9] - Driver Comp: hades_tdc_bundle_inst/SLICE_441:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_447:I5, hades_dbg2_out[9]:I0 -Signal hades_dbg2_out_c[10] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_448:I4, hades_dbg2_out[10]:I0 -Signal hades_dbg2_out_c[11] - Driver Comp: hades_tdc_bundle_inst/SLICE_442:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_448:I5, hades_dbg2_out[11]:I0 -Signal hades_tdc_bundle_inst/N_246_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_457:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I12 -Signal hades_hit_valid_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_457:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I3, - hades_tdc_bundle_inst/SLICE_457:I7, hades_tdc_bundle_inst/SLICE_654:I3, - hades_hit_valid[0]:I0 -Signal hades_tdc_bundle_inst/N_243_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_458:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_458:I12 -Signal hades_hit_valid_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_458:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_456:I1, - hades_tdc_bundle_inst/SLICE_458:I4, hades_tdc_bundle_inst/SLICE_710:I1, - SLICE_740:I0, hades_hit_valid[1]:I0 -Signal hades_tdc_bundle_inst/N_245_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_459:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_459:I12 -Signal hades_hit_valid_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_459:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_459:I1, - hades_tdc_bundle_inst/SLICE_459:I9, hades_tdc_bundle_inst/SLICE_710:I2, - hades_hit_valid[2]:I0 -Signal hades_tdc_bundle_inst/N_244_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_460:O2 - - Page 163 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - Load Comps: hades_tdc_bundle_inst/SLICE_460:I12 -Signal hades_hit_valid_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_460:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_460:I1, - hades_tdc_bundle_inst/SLICE_460:I9, hades_tdc_bundle_inst/SLICE_683:I1, - hades_hit_valid[3]:I0 -Signal hades_tdc_bundle_inst/N_247_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_121:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I12 -Signal hades_tdc_bundle_inst/hit_out_i_6[2] - Driver Comp: - hades_tdc_bundle_inst/SLICE_123:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_123:I12 -Signal hades_tdc_bundle_inst/drop_cmp_buf_valid_4_iv_i - Driver Comp: - hades_tdc_bundle_inst/SLICE_456:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_456:I12 -Signal hades_drop_cmp_buf_valid_c - Driver Comp: - hades_tdc_bundle_inst/SLICE_456:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_456:I0, - hades_tdc_bundle_inst/SLICE_458:I0, hades_tdc_bundle_inst/SLICE_458:I6, - hades_tdc_bundle_inst/SLICE_710:I6, hades_drop_cmp_buf_valid:I0 -Signal hades_tdc_bundle_inst/hades_dbg2_coarse_c_i[0] - Driver Comp: - hades_tdc_bundle_inst/SLICE_434:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_434:I12, - hades_tdc_bundle_inst/SLICE_450:I4 -Signal hades_drop_cmp_buf_coarse_c[0] - Driver Comp: - hades_tdc_bundle_inst/SLICE_450:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_118:I8, - hades_drop_cmp_buf_coarse[0]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[1] - Driver Comp: - hades_tdc_bundle_inst/SLICE_434:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_434:I13, - hades_tdc_bundle_inst/SLICE_450:I5 -Signal hades_drop_cmp_buf_coarse_c[1] - Driver Comp: - hades_tdc_bundle_inst/SLICE_450:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_118:I6, - hades_drop_cmp_buf_coarse[1]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[2] - Driver Comp: - hades_tdc_bundle_inst/SLICE_435:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_435:I12, - hades_tdc_bundle_inst/SLICE_451:I4 -Signal hades_drop_cmp_buf_coarse_c[2] - Driver Comp: - hades_tdc_bundle_inst/SLICE_451:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_119:I2, - hades_drop_cmp_buf_coarse[2]:I0 -Signal hades_drop_cmp_buf_coarse_c[3] - Driver Comp: - hades_tdc_bundle_inst/SLICE_451:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_119:I0, - hades_drop_cmp_buf_coarse[3]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[4] - Driver Comp: - hades_tdc_bundle_inst/SLICE_436:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_436:I12, - hades_tdc_bundle_inst/SLICE_452:I4 -Signal hades_drop_cmp_buf_coarse_c[4] - Driver Comp: - hades_tdc_bundle_inst/SLICE_452:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_119:I8, - hades_drop_cmp_buf_coarse[4]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[5] - Driver Comp: - - Page 164 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - hades_tdc_bundle_inst/SLICE_436:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_436:I13, - hades_tdc_bundle_inst/SLICE_452:I5 -Signal hades_drop_cmp_buf_coarse_c[5] - Driver Comp: - hades_tdc_bundle_inst/SLICE_452:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_119:I6, - hades_drop_cmp_buf_coarse[5]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[6] - Driver Comp: - hades_tdc_bundle_inst/SLICE_437:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_437:I12, - hades_tdc_bundle_inst/SLICE_453:I4 -Signal hades_drop_cmp_buf_coarse_c[6] - Driver Comp: - hades_tdc_bundle_inst/SLICE_453:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_120:I2, - hades_drop_cmp_buf_coarse[6]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[7] - Driver Comp: - hades_tdc_bundle_inst/SLICE_437:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_437:I13, - hades_tdc_bundle_inst/SLICE_453:I5 -Signal hades_drop_cmp_buf_coarse_c[7] - Driver Comp: - hades_tdc_bundle_inst/SLICE_453:O4 - Load Comps: hades_tdc_bundle_inst/SLICE_120:I0, - hades_drop_cmp_buf_coarse[7]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[8] - Driver Comp: - hades_tdc_bundle_inst/SLICE_438:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_438:I12, - hades_tdc_bundle_inst/SLICE_454:I4 -Signal hades_drop_cmp_buf_coarse_c[8] - Driver Comp: - hades_tdc_bundle_inst/SLICE_454:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_120:I7, - hades_drop_cmp_buf_coarse[8]:I0 -Signal hades_tdc_bundle_inst/drop_cmp_buf_coarse_2[9] - Driver Comp: - hades_tdc_bundle_inst/SLICE_455:O2 - Load Comps: hades_tdc_bundle_inst/SLICE_455:I12 -Signal hades_drop_cmp_buf_coarse_c[9] - Driver Comp: - hades_tdc_bundle_inst/SLICE_455:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_120:I6, - hades_drop_cmp_buf_coarse[9]:I0 -Signal hades_drop_cmp_buf_c[0] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O3 - - Load Comps: hades_tdc_bundle_inst/SLICE_118:I9, hades_drop_cmp_buf[0]:I0 -Signal hades_drop_cmp_buf_c[1] - Driver Comp: hades_tdc_bundle_inst/SLICE_445:O4 - - Load Comps: hades_tdc_bundle_inst/SLICE_118:I7, hades_drop_cmp_buf[1]:I0 -Signal hades_drop_cmp_buf_c[2] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O3 - - Load Comps: hades_tdc_bundle_inst/SLICE_119:I3, hades_drop_cmp_buf[2]:I0 -Signal hades_drop_cmp_buf_c[3] - Driver Comp: hades_tdc_bundle_inst/SLICE_446:O4 - - Load Comps: hades_tdc_bundle_inst/SLICE_119:I1, hades_drop_cmp_buf[3]:I0 -Signal hades_drop_cmp_buf_c[4] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O3 - - Load Comps: hades_tdc_bundle_inst/SLICE_119:I9, hades_drop_cmp_buf[4]:I0 -Signal hades_drop_cmp_buf_c[5] - Driver Comp: hades_tdc_bundle_inst/SLICE_447:O4 - - Load Comps: hades_tdc_bundle_inst/SLICE_119:I7, hades_drop_cmp_buf[5]:I0 - - Page 165 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_drop_cmp_buf_c[6] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O3 - - Load Comps: hades_tdc_bundle_inst/SLICE_120:I3, hades_drop_cmp_buf[6]:I0 -Signal hades_drop_cmp_buf_c[7] - Driver Comp: hades_tdc_bundle_inst/SLICE_448:O4 - - Load Comps: hades_tdc_bundle_inst/SLICE_120:I1, hades_drop_cmp_buf[7]:I0 -Signal hades_buf_release_c - Driver Comp: hades_tdc_bundle_inst/SLICE_433:O3 - Load Comps: hades_tdc_bundle_inst/SLICE_457:I2, - hades_tdc_bundle_inst/SLICE_457:I6, hades_tdc_bundle_inst/SLICE_458:I3, - hades_tdc_bundle_inst/SLICE_458:I8, hades_tdc_bundle_inst/SLICE_459:I0, - hades_tdc_bundle_inst/SLICE_459:I8, hades_tdc_bundle_inst/SLICE_460:I0, - hades_tdc_bundle_inst/SLICE_460:I8, hades_buf_release:I0 -Signal hades_tdc_bundle_inst/N_90 - Driver Comp: - hades_tdc_bundle_inst/SLICE_683:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_683:I0 -Signal hades_tdc_bundle_inst/N_80 - Driver Comp: - hades_tdc_bundle_inst/SLICE_432:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_654:I2 -Signal hades_tdc_bundle_inst/hit_out_i_6_i_a2_0[0] - Driver Comp: - hades_tdc_bundle_inst/SLICE_741:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_121:I4 -Signal hades_tdc_bundle_inst/N_66 - Driver Comp: - hades_tdc_bundle_inst/SLICE_654:O1 - Load Comps: hades_tdc_bundle_inst/SLICE_654:I1 -Signal hades_tdc_bundle_inst/hit_valid_pmux_iv_0_0 - Driver Comp: - hades_tdc_bundle_inst/SLICE_654:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_683:I2 -Signal hades_tdc_bundle_inst/N_45 - Driver Comp: - hades_tdc_bundle_inst/SLICE_710:O0 - Load Comps: hades_tdc_bundle_inst/SLICE_654:I9 -Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[0] - Driver Comp: - hades_tdc_bundle_inst/SLICE_118:O6 - Load Comps: hades_tdc_bundle_inst/SLICE_119:I17 -Signal hades_tdc_bundle_inst/hit_valid25_0_data_tmp[2] - Driver Comp: - hades_tdc_bundle_inst/SLICE_119:O6 - Load Comps: hades_tdc_bundle_inst/SLICE_120:I17 -Signal pll0inst/GND - Driver Comp: pll0inst/SLICE_742:O0 - Load Comps: pll0inst/PLLInst_0:STDBY -Signal LVL1_TRG_DATA_VALID_IN_c - Driver Comp: LVL1_TRG_DATA_VALID_IN:O0 - Load Comps: LVL1_TRG_DATA_VALID_IN_MGIOL:I5 -Signal LVL1_INVALID_TRG_IN_c - Driver Comp: LVL1_INVALID_TRG_IN:O0 - Load Comps: LVL1_INVALID_TRG_IN_MGIOL:I5 -Signal reset_dc_c - Driver Comp: reset_dc:O0 - Load Comps: reset_dc_MGIOL:I5 -Signal hades_lvl1_c - Driver Comp: hades_lvl1:O0 - Load Comps: SLICE_743:I0, hades_lvl1_MGIOL:I5 -Signal FEE_TRG_RELEASE_OUT_c - Driver Comp: FEE_TRG_RELEASE_OUT_MGIOL:O0 - Load Comps: FEE_TRG_RELEASE_OUT:I1 -Signal FEE_DATA_WRITE_OUT_c - Driver Comp: FEE_DATA_WRITE_OUT_MGIOL:O0 - Load Comps: FEE_DATA_WRITE_OUT:I1 -Signal FEE_DATAFINISHED_OUT_c - Driver Comp: FEE_DATAFINISHED_OUT_MGIOL:O0 - Load Comps: FEE_DATAFINISHED_OUT:I1 -Signal hades_raw_out_valid_c - Driver Comp: hades_raw_out_valid_MGIOL:O0 - Load Comps: hades_raw_out_valid:I1 -Signal hades_dbg2_out_c[0] - Driver Comp: hades_dbg2_out[0]_MGIOL:O0 - Load Comps: hades_dbg2_out[0]:I1 - - Page 166 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ -Signal hades_dbg2_out_c[1] - Driver Comp: hades_dbg2_out[1]_MGIOL:O0 - Load Comps: hades_dbg2_out[1]:I1 -Signal hades_dbg2_out_c[2] - Driver Comp: hades_dbg2_out[2]_MGIOL:O0 - Load Comps: hades_dbg2_out[2]:I1 -Signal hades_dbg2_out_c[16] - Driver Comp: hades_dbg2_out[16]_MGIOL:O0 - Load Comps: hades_dbg2_out[16]:I1 -Signal hades_dbg2_out_c[17] - Driver Comp: hades_dbg2_out[17]_MGIOL:O0 - Load Comps: hades_dbg2_out[17]:I1 -Signal hades_dbg2_out_c[18] - Driver Comp: hades_dbg2_out[18]_MGIOL:O0 - Load Comps: hades_dbg2_out[18]:I1 -Signal hades_dbg2_out_c[20] - Driver Comp: hades_dbg2_out[20]_MGIOL:O0 - Load Comps: hades_dbg2_out[20]:I1 -Signal hades_dbg2_out_c[21] - Driver Comp: hades_dbg2_out[21]_MGIOL:O0 - Load Comps: hades_dbg2_out[21]:I1 -Signal hades_dbg2_out_c[22] - Driver Comp: hades_dbg2_out[22]_MGIOL:O0 - Load Comps: hades_dbg2_out[22]:I1 -Signal hades_dbg2_out_c[23] - Driver Comp: hades_dbg2_out[23]_MGIOL:O0 - Load Comps: hades_dbg2_out[23]:I1 -Signal hades_dbg2_out_c[24] - Driver Comp: hades_dbg2_out[24]_MGIOL:O0 - Load Comps: hades_dbg2_out[24]:I1 -Signal hades_dbg2_out_c[25] - Driver Comp: hades_dbg2_out[25]_MGIOL:O0 - Load Comps: hades_dbg2_out[25]:I1 -Signal hades_dbg2_out_c[26] - Driver Comp: hades_dbg2_out[26]_MGIOL:O0 - Load Comps: hades_dbg2_out[26]:I1 -Signal hades_dbg2_out_c[27] - Driver Comp: hades_dbg2_out[27]_MGIOL:O0 - Load Comps: hades_dbg2_out[27]:I1 -Signal hades_dbg2_out_c[28] - Driver Comp: hades_dbg2_out[28]_MGIOL:O0 - Load Comps: hades_dbg2_out[28]:I1 -Signal hades_offset_c[0] - Driver Comp: hades_offset[0]_MGIOL:O0 - Load Comps: hades_offset[0]:I1 -Signal hades_offset_c[1] - Driver Comp: hades_offset[1]_MGIOL:O0 - Load Comps: hades_offset[1]:I1 -Signal hades_offset_c[2] - Driver Comp: hades_offset[2]_MGIOL:O0 - Load Comps: hades_offset[2]:I1 -Signal hades_offset_c[3] - Driver Comp: hades_offset[3]_MGIOL:O0 - Load Comps: hades_offset[3]:I1 -Signal hades_offset_c[4] - Driver Comp: hades_offset[4]_MGIOL:O0 - Load Comps: hades_offset[4]:I1 -Signal hades_offset_c[5] - Driver Comp: hades_offset[5]_MGIOL:O0 - Load Comps: hades_offset[5]:I1 -Signal hades_offset_c[6] - Driver Comp: hades_offset[6]_MGIOL:O0 - Load Comps: hades_offset[6]:I1 -Signal hades_offset_c[7] - Driver Comp: hades_offset[7]_MGIOL:O0 - Load Comps: hades_offset[7]:I1 -Signal hades_offset_c[8] - Driver Comp: hades_offset[8]_MGIOL:O0 - Load Comps: hades_offset[8]:I1 -Signal hades_trig_c - Driver Comp: hades_trig:O0 - Load Comps: hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst - /SLICE_604:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_ - neg_inst/SLICE_605:I5, hades_tdc_bundle_inst/hades_tdc_channel_raw_out_i - nst/tdc_neg_inst/SLICE_606:I5, hades_tdc_bundle_inst/hades_tdc_channel_r - aw_out_inst/tdc_neg_inst/SLICE_607:I5, hades_tdc_bundle_inst/hades_tdc_c - hannel_raw_out_inst/tdc_neg_inst/SLICE_608:I5, hades_tdc_bundle_inst/had - es_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_609:I5, hades_tdc_bundle_ - inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_610:I5, hades_tdc - _bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/SLICE_611:I5, - - Page 167 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Signal Cross Reference (cont) ------------------------------ - SLICE_747:I0 -Signal trig_c[2] - Driver Comp: trig[2]:O0 - Load Comps: SLICE_746:I0 -Signal trig_c[1] - Driver Comp: trig[1]:O0 - Load Comps: SLICE_745:I0 -Signal trig_c[0] - Driver Comp: trig[0]:O0 - Load Comps: SLICE_744:I0 - - - - - - Number of warnings: 13 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(10): Semantic - error in "BLOCK NET "tdc_out*" ;": tdc_out* does not match any nets in the - design. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(48): Semantic - error in "LOCATE COMP "reset" SITE "D11" ;": COMP "reset" cannot be found - in design. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(59): Semantic - error in "UGROUP "trig_gate0" BBOX 1 1 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO - BLKNAME trig_pad_RNII4FF[0];": Block - "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1" of UGROUP - "trig_gate0" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst1/out_RNO" of UGROUP - "trig_gate0" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2" of UGROUP - "trig_gate0" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/trig_inv_inst2/out_RNO" of UGROUP - "trig_gate0" not found in design This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(60): Semantic - error in "LOCATE UGROUP "trig_gate0" SITE "R68C13D" ;": UGROUP "trig_gate0" - cannot be found for 'LOCATE UGROUP'. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(95): Semantic - error in "UGROUP "tdc_ch0" BBOX 1 6 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/de .... - _inst/dec_inst/out_internal[2] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/dec_inst/valid_internal;": - Block "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP - "tdc_ch0" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[1]" of UGROUP "tdc_ch0" - not found in designBlock - - Page 168 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Design Errors/Warnings (cont) ------------------------------ - "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out[2]" of UGROUP "tdc_ch0" - not found in designBlock "genblk1[0].tdc_cha .... out_internal[1]" of - UGROUP "tdc_ch0" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/dec_inst/out_internal[2]" of UGROUP - "tdc_ch0" not found in design This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(96): Semantic - error in "LOCATE UGROUP "tdc_ch0" SITE "R67C14D" ;": UGROUP "tdc_ch0" - cannot be found for 'LOCATE UGROUP'. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(141): Semantic - error in "UGROUP "tdc2" BBOX 1 6 - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_ .... - st/dec_inst/valid - BLKNAME genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal - BLKNAME - genblk1[1].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block - "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI7VDR[7]" of - UGROUP "tdc2" not found in designBlock - "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "tdc2" not - found in designBlock "genblk1[1].tdc_channel_fifo_out_inst/dec_inst/out[1]" - of UGROUP "tdc2" not found in designBlock "genblk1[1].td .... - ternal[2]" of UGROUP "tdc2" not found in designBlock "genblk1[1].tdc_channe - l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "tdc2" not - found in design This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(142): Semantic - error in "LOCATE UGROUP "tdc2" SITE "R65C41D" ;": UGROUP "tdc2" cannot be - found for 'LOCATE UGROUP'. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(264): Semantic - error in "UGROUP "dec3" BBOX 1 6 - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/dl[0][0] - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_ .... - st/dec_inst/valid - BLKNAME genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal - BLKNAME - genblk1[2].tdc_channel_fifo_out_inst/dec_inst/valid_internal_RNO;": Block - "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/in_synced_RNI9T6L[7]" of - UGROUP "dec3" not found in designBlock - "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[0]" of UGROUP "dec3" not - found in designBlock "genblk1[2].tdc_channel_fifo_out_inst/dec_inst/out[1]" - of UGROUP "dec3" not found in designBlock "genblk1[2].td .... - ternal[2]" of UGROUP "dec3" not found in designBlock "genblk1[2].tdc_channe - l_fifo_out_inst/dec_inst/out_internal_2_1_0_.m15_i_0" of UGROUP "dec3" not - found in design This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(265): Semantic - error in "LOCATE UGROUP "dec3" SITE "R65C49D" ;": UGROUP "dec3" cannot be - found for 'LOCATE UGROUP'. This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(289): Semantic - error in "UGROUP "tdc0_neg" BBOX 1 4 - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].in_cl - k_synced[0] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b - uffered1[0] - - Page 169 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Design Errors/Warnings (cont) ------------------------------ - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_ .... enblk1[0].tdc_c - hannel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_buffered[3] - BLKNAME genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[3].out_b - uffered[7];": Block "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genb - lk1[0].in_clk_synced[0]" of UGROUP "tdc0_neg" not found in designBlock "gen - blk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_buffered1[0]" - of UGROUP "tdc0_neg" not found in designBlock - "genblk1[0].tdc_channel_fifo_out_inst/tdc_neg_inst/genblk1[0].out_b .... - of UGROUP "tdc0_neg" not found in designBlock "genblk1[0].tdc_channel_fifo_ - out_inst/tdc_neg_inst/genblk1[3].out_buffered[7]" of UGROUP "tdc0_neg" not - found in design This preference has been disabled. -WARNING - map: /home/hadaq/mmichalek/lattice/simplified/s1.lpf(290): Semantic - error in "LOCATE UGROUP "tdc0_neg" SITE "R69C14D" ;": UGROUP "tdc0_neg" - cannot be found for 'LOCATE UGROUP'. This preference has been disabled. -WARNING - map: Semantic error in "PGROUP "lvl1_dec" BBOX 1 6 DEVSIZE - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_464" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_465" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_474" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_ins .... - inst/SLICE_734" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_735" - COMP "hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/SLICE_736";": - Group lvl1_dec is invalid because BBOX size is too small to accommodate all - the components. This preference has been disabled. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| hades_raw_valid_vect[0]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| clk | INPUT | LVDS | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_valid| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[11]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[10]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[9]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[8]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[7]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[6]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[5]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[4]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 170 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| hades_drop_cmp_buf_coarse[3]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[2]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[1]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf_coarse[0]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[11]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[10]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[9]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[8]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[7]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[6]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[5]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[4]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[3]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[2]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[1]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_drop_cmp_buf[0]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[8]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[7]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[6]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[5]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[4]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[3]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[2]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[1]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_coarse[0]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[31] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[30] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[29] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 171 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| hades_dbg2_out[28] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[27] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[26] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[25] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[24] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[23] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[22] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[21] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[20] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[19] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[18] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[17] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[16] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[15] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[14] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[13] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[12] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[11] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[10] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[9] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[8] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[7] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[6] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[5] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[4] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[2] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_dbg2_out[1] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ - - Page 172 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| hades_dbg2_out[0] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_buf_drop[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_buf_drop[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_buf_drop[1] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_buf_drop[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_invalid_dl[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_invalid_dl[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_invalid_dl[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_invalid_dl[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_discard | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_valid[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_valid[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_valid[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_valid[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_out_i[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_out_i[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_out_i[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_hit_out_i[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_buf_finished | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_buf_release | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_buf_out_valid | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_window_end | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_offset_valid | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_offset[8] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[7] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[6] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[5] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[4] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ - - Page 173 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| hades_offset[3] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[2] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[1] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_offset[0] | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_lvl1_invalid | INPUT | LVCMOS25 | IN | -+---------------------+-----------+-----------+------------+ -| hades_lvl1 | INPUT | LVCMOS25 | IN | -+---------------------+-----------+-----------+------------+ -| hades_raw_valid_vect[1]| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| hades_raw_out_valid | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| hades_trig | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| release_out | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| finished | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| last_buf_empty | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| discard | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| burst | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| LVL1_TRG_DATA_VALI_IN_rising| OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_TRG_RELEASE_OUT | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| FEE_DATAFINISHED_OUT| OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_WRITE_OUT | OUTPUT | LVCMOS25 | OUT | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[31] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[30] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[29] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[28] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[27] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[26] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[25] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[24] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[23] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[22] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 174 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| FEE_DATA_OUT[21] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[20] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[19] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[18] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[17] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[16] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[15] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[14] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[13] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[12] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[11] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[10] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[9] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[8] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[7] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[6] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[5] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[4] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| FEE_DATA_OUT[0] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| LVL1_INVALID_TRG_IN | INPUT | LVCMOS25 | IN | -+---------------------+-----------+-----------+------------+ -| LVL1_TRG_DATA_VALID_IN| INPUT | LVCMOS25 | IN | -+---------------------+-----------+-----------+------------+ -| fifo_empty1 | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_rden | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[31] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[30] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 175 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| fifo_data_out[29] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[28] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[27] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[26] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[25] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[24] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[23] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[22] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[21] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[20] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[19] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[18] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[17] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[16] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[15] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[14] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[13] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[12] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[11] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[10] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[9] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[8] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[7] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[6] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[5] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[4] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[3] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| fifo_data_out[2] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - - Page 176 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -IO (PIO) Attributes (cont) --------------------------- -| fifo_data_out[1] | OUTPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| trig[2] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| trig[1] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| trig[0] | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ -| reset_dc | INPUT | LVCMOS25 | IN | -+---------------------+-----------+-----------+------------+ -| rd_clk | INPUT | LVCMOS25 | | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block GSR_INST undriven or does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/VCC undriven or - does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/VCC undriven or - does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_inst/VCC undriven - or does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/tdc_neg_inst/VCC - undriven or does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_inst/VCC undriven - or does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/dec_neg_inst/VCC - undriven or does not drive anything - clipped. -Block trb_adapter_inst/VCC undriven or does not drive anything - clipped. -Block fifo_colector_inst/VCC undriven or does not drive anything - clipped. -Block genblk1[0].tdc_channel_fifo_out_inst/VCC undriven or does not drive - anything - clipped. -Block genblk1[0].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not - drive anything - clipped. -Block genblk1[0].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not - drive anything - clipped. -Block genblk1[1].tdc_channel_fifo_out_inst/VCC undriven or does not drive - anything - clipped. -Block genblk1[1].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not - drive anything - clipped. -Block genblk1[1].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not - drive anything - clipped. -Block genblk1[2].tdc_channel_fifo_out_inst/VCC undriven or does not drive - anything - clipped. -Block genblk1[2].tdc_channel_fifo_out_inst/tdc_inst/VCC undriven or does not - drive anything - clipped. -Block genblk1[2].tdc_channel_fifo_out_inst/dec_inst/VCC undriven or does not - drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_gate_neg was - merged into signal hades_trig_c -Signal reset_dl_i[2] was merged into signal reset_dl[2] -Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[0].out_buffered_4_. - CN was merged into signal pll_clks[0] -Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[1].out_buffered_5_. - CN was merged into signal pll_clks[1] - - Page 177 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- -Signal genblk1[0].tdc_channel_fifo_out_inst.tdc_inst.genblk1[2].out_buffered_6_. - CN was merged into signal pll_clks[2] -Signal genblk1[0].tdc_channel_fifo_out_inst.fifo_wren.CN was merged into signal - pll_clks[3] -Signal fifo_colector_inst/fifo40_inst/invout_0 was merged into signal - last_buf_empty_c -Signal fifo_colector_inst/fifo40_inst/invout_1 was merged into signal - fifo_colector_inst/fifo40_inst/Full -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged - into signal fifo_empty1_c -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged - into signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged - into signal fifo_empty[1] -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged - into signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_0 was merged - into signal fifo_empty[2] -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/invout_1 was merged - into signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Full -Signal GND undriven or does not drive anything - clipped. -Signal VCC undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/VCC undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC undriven or does not - drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC undriven or does - not drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/VCC undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/rRst undriven or does not drive anything - - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/rRst undriven or does - not drive anything - clipped. -Signal pll0inst/CLKINTFB undriven or does not drive anything - clipped. -Signal pll0inst/REFCLK undriven or does not drive anything - clipped. -Signal pll0inst/INTLOCK undriven or does not drive anything - clipped. -Signal pll0inst/LOCK undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S1 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_21_0_S0 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S1 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_9_0_S0 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S1 undriven or does not drive - - Page 178 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_1_0_S0 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/N_73 undriven or does not drive anything - clipped. - -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_S1 - undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_s_7_0_COUT - undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S1 - undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/un1_window_8_cry_0_0_S0 - undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/N_1 undriven or does not - drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _27_0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _27_0_COUT undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _21_0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _21_0_S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _9_0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _9_0_S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _1_0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_buf_positive_0_I - _1_0_S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_1 undriven or does - not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_ - 0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_27_ - 0_COUT undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_ - 0_S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_21_ - 0_S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0 - _S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_9_0 - _S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0 - _S1 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/un1_coarse_1_0_I_1_0 - _S0 undriven or does not drive anything - clipped. -Signal hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/N_2 undriven or does - not drive anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_S1 undriven or does not drive - anything - clipped. -Signal hades_tdc_bundle_inst/hit_valid25_0_I_27_0_COUT undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/a1_S1_2 undriven or does not drive - - Page 179 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/a1_COUT_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_4_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_3_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_2_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_1_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_0_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/full_cmp_ci_a_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/CIN undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/a0_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/a0_COUT_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_4_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_3_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_2_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_1_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_0_S0_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S1_2 undriven or does not - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/empty_cmp_ci_a_S0_2 undriven or does not - - Page 180 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - drive anything - clipped. -Signal fifo_colector_inst/fifo40_inst/CIN_0 undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/co4_1 undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/r_gctr_cia_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/CIN_1 undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/co4 undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S1_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/w_gctr_cia_S0_2 undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/CIN_2 undriven or does not drive anything - - clipped. -Signal fifo_colector_inst/fifo40_inst/Q_1[35] undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/Q_1[34] undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/Q_1[33] undriven or does not drive - anything - clipped. -Signal fifo_colector_inst/fifo40_inst/Q_1[32] undriven or does not drive - anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does - - Page 181 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0 undriven - or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does - not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14 - undriven or does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or - - Page 182 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or - does not drive anything - clipped. -Signal genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_0 undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_0 undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_0 undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_0 undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_0 - - Page 183 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does - not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_0 - undriven or does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or - - Page 184 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - does not drive anything - clipped. -Signal genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_S1_1 undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a1_COUT_1 undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_4_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_3_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_2_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_1_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_0_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/full_cmp_ci_a_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_S1_1 undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/a0_COUT_1 undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_4_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_3_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_2_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_1_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_0_S0_1 - - Page 185 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/empty_cmp_ci_a_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_0 undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4_1 undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/r_gctr_cia_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_1 undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/co4 undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S1_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/w_gctr_cia_S0_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/CIN_2 undriven or does - not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO17_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO16_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO15_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0_DO14_1 - undriven or does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[31] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[30] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[29] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[28] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[27] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[26] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[25] undriven or - does not drive anything - clipped. -Signal genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/Q_1[24] undriven or - does not drive anything - clipped. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/trig_inv_inst1/out_RN - O was optimized away. -Block reset_dl_RNISCAF[2] was optimized away. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[0].out_buff - ered1_4_.CN was optimized away. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[1].out_buff - ered1_5_.CN was optimized away. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/tdc_inst/genblk1[2].out_buff - ered1_6_.CN was optimized away. - - Page 186 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Removed logic (cont) --------------------- -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/dec_inst/in_synced_7_.CN was - optimized away. -Block fifo_colector_inst/fifo40_inst/INV_0 was optimized away. -Block fifo_colector_inst/fifo40_inst/INV_1 was optimized away. -Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized - away. -Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized - away. -Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized - away. -Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized - away. -Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_0 was optimized - away. -Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/INV_1 was optimized - away. -Block GND was optimized away. -Block VCC was optimized away. -Block hades_tdc_bundle_inst/VCC was optimized away. -Block hades_tdc_bundle_inst/hades_LVL1_raw_out_inst/VCC was optimized away. -Block hades_tdc_bundle_inst/hades_tdc_channel_raw_out_inst/VCC was optimized - away. -Block fifo_colector_inst/fifo40_inst/VCC was optimized away. -Block fifo_colector_inst/fifo40_inst/OR2_t18 was optimized away. -Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away. - -Block genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized - away. -Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away. - -Block genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized - away. -Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/VCC was optimized away. - -Block genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/OR2_t18 was optimized - away. - -Memory Usage ------------- - -/fifo_colector_inst/fifo40_inst: - EBRs: 1 - RAM SLICEs: 0 - Logic SLICEs: 81 - PFU Registers: 102 - -Contains EBR pdp_ram_0_0_1: TYPE= PDPW16KD, Width= 32, Depth_R= 512, - Depth_W= 512, REGMODE= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= - SYNC, GSR= DISABLED, MEM_LPC_FILE= fifo40_dc.lpc -/genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst: - EBRs: 1 - RAM SLICEs: 0 - Logic SLICEs: 81 - PFU Registers: 102 - -Contains EBR pdp_ram_0_0_0: TYPE= PDPW16KD, Width= 24, Depth_R= 512, - Depth_W= 512, REGMODE= NOREG, RESETMODE= SYNC, ASYNC_RESET_RELEASE= - SYNC, GSR= DISABLED, MEM_LPC_FILE= fifo32dc.lpc - - Page 187 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -Memory Usage (cont) -------------------- -/genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst: - EBRs: 1 - RAM SLICEs: 0 - Logic SLICEs: 81 - PFU Registers: 102 - -Contains EBR pdp_ram_0_0_0: TYPE= PDPW16KD, Width= 24, Depth_R= 512, - Depth_W= 512, REGMODE= NOREG, RESETMODE= SYNC, ASYNC_RESET_RELEASE= - SYNC, GSR= DISABLED, MEM_LPC_FILE= fifo32dc.lpc -/genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst: - EBRs: 1 - RAM SLICEs: 0 - Logic SLICEs: 81 - PFU Registers: 102 - -Contains EBR pdp_ram_0_0_0: TYPE= PDPW16KD, Width= 24, Depth_R= 512, - Depth_W= 512, REGMODE= NOREG, RESETMODE= SYNC, ASYNC_RESET_RELEASE= - SYNC, GSR= DISABLED, MEM_LPC_FILE= fifo32dc.lpc - - - -PLL/DLL Summary ---------------- - -PLL 1: Pin/Node Value - PLL Instance Name: pll0inst/PLLInst_0 - PLL Type: EHXPLLL - Input Clock: PIN clk_c - Input Clock2: NONE - Input Clock select: NONE - Output Clock(P): NODE pll_clks[0] - Output Clock(S): NODE pll_clks[1] - Output Clock(S2): NODE pll_clks[2] - Output Clock(S3): NODE pll_clks[3] - Feedback Signal: NODE pll_clks[0] - Reset Signal: NONE - Standby Signal: NODE pll0inst/GND - PLL LOCK signal: NONE - PLL Internal LOCK Signal: NONE - Input Clock Frequency (MHz): 100.0000 - Output Clock(P) Frequency (MHz): 300.0000 - Output Clock(S) Frequency (MHz): 300.0000 - Output Clock(S2) Frequency (MHz): 300.0000 - Output Clock(S3) Frequency (MHz): 300.0000 - CLKOP Post Divider A Input: DIVA - CLKOS Post Divider B Input: DIVB - CLKOS2 Post Divider C Input: DIVC - CLKOS3 Post Divider D Input: DIVD - Pre Divider A Input: NONE - Pre Divider B Input: NONE - Pre Divider C Input: NONE - Pre Divider D Input: NONE - FB_MODE: CLKOP - CLKI Divider: 1 - CLKFB Divider: 3 - CLKOP Divider: 2 - CLKOS Divider: 2 - CLKOS2 Divider: 2 - - Page 188 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -PLL/DLL Summary (cont) ----------------------- - CLKOS3 Divider: 2 - Fractional N Divider: NONE - CLKOP Desired Phase Shift(degree): 0 - CLKOP Trim Option Rising/Falling: FALLING - CLKOP Trim Option Delay: 0 - CLKOS Desired Phase Shift(degree): 45 - CLKOS Trim Option Rising/Falling: FALLING - CLKOS Trim Option Delay: 0 - CLKOS2 Desired Phase Shift(degree): 90 - CLKOS2 Trim Option Rising/Falling: NONE - CLKOS2 Trim Option Delay: NONE - CLKOS3 Desired Phase Shift(degree): 135 - CLKOS3 Trim Option Rising/Falling: NONE - CLKOS3 Trim Option Delay: NONE - -ASIC Components ---------------- - -Instance Name: genblk1[2].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 - Type: PDPW16KD -Instance Name: genblk1[1].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 - Type: PDPW16KD -Instance Name: genblk1[0].tdc_channel_fifo_out_inst/fifo32dc_inst/pdp_ram_0_0_0 - Type: PDPW16KD -Instance Name: fifo_colector_inst/fifo40_inst/pdp_ram_0_0_1 - Type: PDPW16KD -Instance Name: pll0inst/PLLInst_0 - Type: EHXPLLL - -PGROUP Utilization ------------------- - -PGROUP "tdc0": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) -PGROUP "tdc22": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) -PGROUP "tdc3": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) -PGROUP "lvl1_tdc": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) -PGROUP "hades_dec_pos": - Logic contained: 23 SLICEs, 6 PFUs - Bounded Area: 6 PFUs (DEVSIZE) (ANCHORED) -PGROUP "hades_dec_neg": - Logic contained: 23 SLICEs, 6 PFUs - Bounded Area: 6 PFUs (DEVSIZE) (ANCHORED) -PGROUP "hades_tdc_pos": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) -PGROUP "hades_tdc_neg": - Logic contained: 16 SLICEs, 4 PFUs - Bounded Area: 4 PFUs (DEVSIZE) (ANCHORED) - - Page 189 - - - - -Design: top_tf Date: 06/16/21 09:19:26 - -PGROUP Utilization (cont) -------------------------- -PGROUP "lvl1_pad": - Logic contained: 1 SLICEs, 1 PFUs - Bounded Area: 1 PFUs (DEVSIZE) (ANCHORED) -PGROUP "gate2": - Logic contained: 1 SLICEs, 1 PFUs - Bounded Area: 1 PFUs (DEVSIZE) (ANCHORED) -PGROUP "trig3": - Logic contained: 1 SLICEs, 1 PFUs - Bounded Area: 1 PFUs (DEVSIZE) (ANCHORED) - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 4 secs - Total REAL Time: 5 secs - Peak Memory Usage: 361 MB - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Page 190 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2019 Lattice Semiconductor Corporation, All rights - reserved. diff --git a/impl1/s1_impl1.mt b/impl1/s1_impl1.mt deleted file mode 100644 index ade4de5..0000000 --- a/impl1/s1_impl1.mt +++ /dev/null @@ -1,9 +0,0 @@ --v -1 - - --gt - --fullname --mapchkpnt 0 --sethld diff --git a/impl1/s1_impl1.ncd b/impl1/s1_impl1.ncd deleted file mode 100644 index eb6d8aae862a7e9b50dfe2c3969662b19f0737f2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1332184 zcmeEP2b@*K^}hSwTR;#&uwY+f12y{I_T5P0vIUVQELdWamjxCjBH)58g=`X&m>y#+ zv7~Cc>Am;fV|wrZ^xljAZ_eC%&&-**%iYJq%QN$SzYq4FIdkr`Z~DwV{P5rXuBr8H zkBN#=ao6@8)m@vTM}G3||1?ESJ4ZTpl*^YyD~1L;*01bX`oQ*%p{T!a$BOc&k#ucSB%PG1P$XU3 z6iL@MMN-=~B1yqMLPoNcvg|lVOi6OABPJuqIAV(X(TTO0^%f8JH>sLw9!s+pXrDx?guzxiu(*lOs|~oh$-&V95Kbc z*%4FROOBZ0?l7dC;;tED#GT%#OM_AIbWq$K-gHph9Zq&o+?_~vP~4qJc2L}%NOn+2 zoJe+1+?_~vP~4qJc2L}%YM_JSuA^hbolHB0yOZMXM6#3O?i7bkin~)BIw|f>apAU!{9E8yOVxh6nCdMbWz-$l!!FnC9Rv{ z?xa*V#obA%Zi>6p;85^%#mK?a?TxM%4JidfSBr*}LZNF#LrQ_rm7*b~Fz7nbkW%u? zDp9vIItvY5N_?GzhLn<1XP_aaxas_xnRaw2V6qOgq<)@ag#Mf8%0=W8%Ki7O4W7>nC>NT5ZWnVx|3i?$%5`97*YzD?jjgc z3YhL87*YzD?jRUa$_d>+Fr<_dx@qS~(92|j)YZOj3E6ndIse~vH}5n1$f1ur?F>vzcsUA@bKu4{M6 z2`YKAM0ZmLO9S1M6SC-ad+Q4lN=o!lMJ*Gohbl;!U_IXYqQ_fb^myxw9*Tran;vg{ z(G%Af&FKhiRo}|Nc+fY0^OnuqtD8o4ja0W^x$EM#N^kk$kb|N@Gs^f} zsjJ7U*;dV*(1X}Rb?R=}M)9g{+Uk#*9@^$rrhLn*Oc|F~nR0Hv4)ca9H&-`}ZQqd* zV#>IDs+4c}R4LmsRn1%@V&=*<-64u|ZPSKJS|{L7D;0*Ex)g+*x+X986b6%*d(t&| zxhGwdmwVDRdATQDlb3taHF@dLHFKDfELRTe9$>zli02-38TW+1k)CtP ztxdU{TbmLiw>IT;Zf(lz+}f1exwVPW6KR_{PQlKV<9hHkkzF&-^`L4&oR8?2R5xC} zql!+-#T9Q)SP!=*p-;`tB=jloC!tTdKM8$G$Vuo^37CXFm4Qj1-Thgj=&EYR_dVX^9-l$wm-WwH<$$O)0nY=eDER**} zWhR$5v*^&vauppt=bGyUW(m@BvXl2l1!?l$YAa8A&NtWF%*3N4&rCc+QxA)BX-+&s zHf>T0<+3?(@7}aIaWB!-oVd4PYEIlrnVJ*VW2WZB#n#lEIFIzy9?eZqA|0@6Y|AAV zwdB>gx6DjA=L{U-U>Jk0QM>k0KTAJc^Voc@(K&=TW3`okx+1b(W%$%oLaGWY!~r zEIURr>tR41MJm&I6p3(o6!T`BUY5>dF>l7{rHnil^Jbi0@W`@gWL$2_>8^d2MI#G! zuRf1r-YnD$DtRpC%|gBGlE-4+EYyoLc`WA5LcN5OWzopO+|8Npm1kKrvQT%&^C;%c zLcK(kWzmRC?iN?CBpso<^kXAeSM_xKRihhsU7U^{jX3Ewrb*~i)pxMAzkT!Oouj*W ze!&Rv#0|d@0KG<)VbIj0u2~K}O8XpoQ~~DDBl6_Xqq;ta9#JQU9+lq=z4@zmjE;@$ z+OqAEmj3PAHf`CpW&1X@lW=DL>Xj=8*Y+>#TR{tE2b{NT6?Ly@A+We{>t(i>(sbI` zrfT9cGx4AofDZSp#4T*?T0~Z6u`Zc67BkdZ92GpNXl9~Xb{QMpIy$m*RH|wI=t8E{ zHgDOsW#^@%o1`A);o(}(UISd%<^+;5(y!d=C{u3wl`D=iWvO4e>?l*d8p^y5=m|6N z-mmP2nKF8^OBvzM-cA|hxGZoo8$ovBS0T%@weqGdJ2#Gu$!yaLhVe9oSTJKp?Nn5HyKsiK zQ||TNt_*EA1u4ffwA-CFx}9+7fpvyuC*SqpIz!vZ zcfF|S*RDAEt_Rr}+D^W=O_1*uC*Sp8JHxh)C_2Arf_olkIv2!LRJ(db`<%3(HQX>(xfT zWhc+|a-(0_$#T8k=vQ`fTrW8KmECMH+i(#jGJX^Ysf+;yY+N~ zKgdpQ>+Oy42!euaEITfAvQV!(W~n=wsQ18UsXN)ICn2)bos865D6`a^tke?{S?W$^ z>P?qf>TVWM-e;-DnZ&ic?sR%{-^oxtOOa*T$x=O6adcc*oE6B0754?y#82SEeFwEt zM`galsVMYL(QFS+Nz=0#*&dv-ruUa-dvHpdp54gy;FLGLD>d7LQ{wb&N4AH!%yFsE zqYH1TaI!#8d}JGUN~oRy$@btB3%xNm+k+b|&4poKmUJW$e+PQ#kd(jXnBv%BVisu}6P#QRRZ9N1ncdoclJgGxl8!O!W={iD;*!L=*~7_-EIqB+Ly$^b3fOLTw>9Yy zvu<{mrxNEj>t;8QN&CgR+0|wx&Q;dcqjg_C#gzoBQkEX(QJge(Rc5Iko_SSej_R?QS5>xGdSK>Nby7gjzW5R|CM>6bo_z7C z%G_+D+&q9($2N^_v$>?lU$e+{^zt3MuC0)J%0nu;My|<#=uy^TE6!h0sjgeQR4=BU z-?w7fKy}$F`&D{~HJ?MZkwHJL+ZRh?x%Rat2DfXW*HS!neJPOoZQXw$5uSQ%LyryKKj*o%) z;vx&R9z1!i%CZ!1*z{R-!b;`RXEkZN({$GZCa&)z50t#BGB@=g$*U@J zQ?K57Rb_5w*Zs+4W|{)==1fnzI?azB7kL99GgfcP^s35?)$6!kRhhAR40Na`tg`9R zgCC!!%vL?>@oCCj)x#a1rp#15&hcr=Jk?XQRCX*i6_>4-b>Jg1kQ)Z|h z%J?*8e(FVCpQaN|;wdlxUa)rAxz)!S6$oTpwDtYT58Pg99E#D)#f0qG~$U z4z3vN8}=Ebv^?5vmeAT%$F}Umx}pdHwUW&nt{mIBOSn)MXS%u2lUAwOLkOo)(Ibe1 zwvO!FrFJ@3sj;=+qz4N#tfjz|#Ck+9D_%}i$DV{|>R-*&qde8i63&zn@dBn=HMbWq z`8Cu^#M2y})%9d5jXh9~OyEHliEhf8IG|gv+NwJoY>(1(o{ooduEy(UB0iKW@v#A8 zl|Gq{OS33@%+V_A3B6G7u_>zweZJJAC~FCQVH@@Lu4`t0)z#5$dMQ<9-@1#=8|`WBP&Jp*f;gTDUuZ^J=je>aEj=mtGP4rnyh#0F{8(l9wGW1vQk8k{(L^NQbdpJd_J$?0Mf8}+=OZ(?S!F~IaD1k+%1D+a zJy!8p(nAxULsp9DfrrmWR*LA6h0jM;isVeBhe8H64 z$m-s|&qr46t!MOoK5Q;?XzhGW`&yJ2PG3tjm#G!eTC&{EQkL7{XStoBEYAqN-pQ0k zm-X#Z$#OeySe}sz6ig=-L=%}>5iKOkGg3jckF1}O3ZivneY;SzJR=qK+_0N!qGe3W z0tLrO1>G#VVt+4P@11eqDO$ud?0VwXqn}X{M03b?GSWaahOD1a66m!~WJN=mS`qCa z%QH%XXa!k6qa=tnko7Z4f@lF*KZ6gV{Yy(ihI!HYrRGKB$MTG15KSNJXC#AY_*g$H zoEe2dw0dkOqcCKc5lvodMznY=&qxN*-m!j0GKkiW^)r$|v~{eXQ5r-`mzIVMb0xko#0+$2ZfbGBz;0j<2*a_?ct^}?Et_H3F zt_2|Te08a(32c8Bz9e4)tOyF6-vw`OT&joG( zo(J3rJRi6TxEVm4nr{VO0Ne)L4%`9U3A_+^5%6N*CBRF8mjOtZ=DUHH1FryH3A_q; zHSikXwZJ{V>wwn-Zvfs1ya{+S@D|{$z}tYg1MdLd3A_tc27Gw>JSufX4czXSgO{t5gG_&4w$;JzrD76DB_0Vo0`pc#O}wCTVM-~eDIFbg;k zm<=2R%mL;C2Ltnf`M@E-p}=9l;lKjm2;fNIDBx(|7~ojoIG_bM9(Vw70&pU55^yqb z3a}7Z1e^+-2AmE&5I6%k6DR`}pcQBX+JO$B6X*iEfgYe2co1+Fuo!qS@DSi^pbuCA z^aBIHATR_h1kZ+yUGPybyR1@M7R4z)OLb0e1m+11|?&0lX4;74T}{ zHNb0udw|yguLs@$yb*X4@MhpGz*~X00dEK10lX7<7w~T2J-~Z`_W|z*J^*|W_z>`6 z;3L3CfsX+n2R;FO68IGGY2Y)!XMxWFp9j7Gd=dB(@MYj$;48pafv*8y2fhJ(6ZjVJ zZQwh=cY*H#-v@pG{1EsN@MGX7z)yjn0sja59QXzBOW;?)uYunHzXg5={2urN@JHZJ zz@LG?0DlGk2K*iP2k=keU%JRt@04aXDcslt+260d%-L4L*_+A zpae7n%7hBR4B!A@CNK*)5SR@d1k3^E0tW;0fcd~7z@fllz~R6G;0WMI;3(i|;27Xo z;5eWKI39QaZ~|~5a1wAba0;*xSOlC3oCcf@JPrY)F{JmpY1nDUI0>_xV4WV3{f5M^ZSf%5S3&p5ZQN3|OXDndvlGd1 zuv5TruwQOC*a0;h?0}UN6|ACC7_mb!d-IiBxB5dqGj+1Pu-rDyay!^8w?oZxH_-MQ z3nTWM(&n&|w>iWc3J6u<4Zs_LH=zze{pB`?Du}u{ROLt&I#m``!ByoMRZxT~C_=Ru zp<0Yk6-B5Pqq6~2ixH~DNSQ^o7@=B>P%TEN79&)P(K6s%U^%b?SP85GRs-h&Yk;-D zFt83-51bEN09*)M1UwYD7b&A=tVrN9>8QNU%u zR^W1A8?YVN0bBu$0XuNyb5?V@EYK?z&*h0fY+l*dmr$A-~+%1fo}re0=^A= z2ly`VJ>dJm4}c#6KLUOX`~=1HAYcwK7dRMb2ReXGpbJ<63`DXyY#)b+e%u^NSsCsu zOPU8;N=-|TrAVS~OO*JnSW;3%5RI3R2q8B_iQiUBN{Wc4p-3Xc-Vh~z+bk(5dPMdc z62G=ZyE)|4Q8uYL6e2sdlIFpdD!+jHaq=Wt!n&r-0#Lzua)J!)`d(0ZW=g4vuaP`Ppd> z*@>GgJK!w0!_9I#*eth0&2l%;_8WC`$RSIc!*br{5OsHxs`Cy9763<}4q1xqa7Kry z=oxm>OO5iHsY5-MzbS;3Y zK0;L=p{kEi)kmo6BUJU#IDo1?dLn?TKDrJ-RUe_MkDdyks*h0BN2ux}RP_<6`Uq8h zgsMJ5RUbVUxB++`a3k=1;3nW^ME9-0+km$N?*QHjybE|Y@E+j30IKRHRMkx%08mvo zeF*q4@Dbpnz{h}(1D^ms3499pH1HYVv%u$o&jVioz6g8?_%d)W@D<>zz}JAU1K$A9 z6f~hJXhKuagr=YgO+gcyf~M~SXbPIp6f~hJX!`%oN^WQ8UGe-w&931|kU z0n>pQzyZKaU>0y7FdH}sm;=lO4hH4{^MONvLxIE4q#;d9NYfJ1w1hM*AxDME& z-;nsVE!xeY9cgL~g~(2=q-n9G)QY#z;uZrr{Vm-B5OOXfLI-tb!k+zOz^iBRK2 zsBt3HI1y@`2sKWG8Ye=H6QRb5eh2&>_yh1q;7`Dx0o0-qYS9R_XoOlcLMVL97HvW;+JsuP3AJbwYSAXtqD`npn^223p%!gI zE!u=yv}rDIFfb384;%uZ#%n??+H^Ru05}3T5;zJt8aM_x7B~)Q0geYA0Gt4v2%H3* z44eWi1Qr3O0?z`T4Lk?95qLgu6L2$d3xG63(4%I=r+EebptGCp*hfmZ;p1YQNa8h8z$?A-&r4tPEA2H=grn}9b1 zZvoy4ybX9e@DAXez`KBV1MdOe3%n0_KkxzIgTRLXG(i!Xpy;E($AFImpFl)U15O7X z2%G_&381(&RR9#+rZ%7*=m0u_E}$Fe0eXQ40cQb=fd>N*0nP^cfF(dbFaQh!L%>qt z9AFu6F0dRx0ynJ$RspMl^MEzLT3{Gh2doFq2QC0E1TF#|3S10440t&32%ri)5*PtC z02_f#z$ma8xCFQq*aAEXxD40|Tn=mlwgWqWD}XUzC$I~+61WPu8n_0y7I-x97~rwM zJQcVecpC6@;2FR((bOYPO30JaAAmmse**pt`~~K}I# zqzt7YVp-B`+EQxjdn`o~bz7puFUpo-krcaJQKuzJ{Gv=szbKkggc56r62Bx6;@=K#;+b?w!Sd{p6(~!CetVrfW8XDaMq3EU| zbrV=Cd9Ryb)JS?&hfexvRtaLD3M+NtH#4Oed4v~@IT%)ko#P?<)b z0zM7g3w#s!7VvH0JHU5=9{@iDegym&t6!*Ci>O$Os91}rSc|Awi>O$Os91}rSc|Aw zi>O$Os91}rSc^M=D}XUzC$I}Z#ag@yK*d@_#acwgT13TKM8#TsEP#r&h>Ep{inTZn zpkgheVlAR#Euu0lqB1R_GA*JqEuu0lqB1Q$3wSp09N@XY4Z!n&8-eEoHvu;Tw*a>S zF92=>ZU^oF?gU;4ya;$P@Dkvqz{`NUP~pA-cq4$cDt!j{EGpL`Fb$Xv90{BRoC=%< zoCPcfHULPo=n!?uEZu(E+EFc6msMN4sw(q7i3sZ7vGEa8W9>URPa3adf07i3@Gn9T zAq3IqfX@S80KN!(3HUNX{5s(E076|vsEcm`-VD42cq{NW;O)RWfOi7#0^SY02Qixk z90<$?4g%%?bAf|_dBA+&5a3YYFyL@t0dNF>R45$<91R=;919!=v;fBg4**U8P6Uuz zrIUeEfQ7&!0I63(>Xl9h9tfNPoCzSMN)@0LSO+{7cotH&0KjH5Y&OGYbjX$4D)D_! z)e0pu{)PP0@R~ z$R!lq5(;iJ{4~Q)GjyAw+l<23Tm>EpjNk>7-SHXN?&`*|Ymp7AK-@cyf9U6G=-i%2 zqiv5iz;Re-8}n2ars3FG)tSQX^JVp*1M$gm9Z2jvkqWwyu!38`NE36@d#2kpE`jr*X=^9lqILI?rRXZ>`s&28QhM7v{3)*ZKiW_b5sdiR3BiPsj zlodANGI!V5hU&C|Sw2N|x?ZLZ-~ZPP)^@JYdDH{p{~kzK8K3OC`CvM$4?a1%b; zRi0+}6mG(2#{@owoAB8=fluKke0ELXQ@G8uas{Qg+xF|Y_t@@M>I=V?oA5VZzPCb@ z<|K9%M5&l#Sh!gFwjG5}*R&`$u7W5Xwt3;(b`(Bc)1vse3Zj(Q=7n$DQTTLCi(=#| zh|*%47rt#r;nOuO3X7{CN{nq@__iH|PseoYp2}LQC^43K>DzV`KHYbV(&8$J5@VYe zzHLY0(={zhi>n|?jBQ@{wjG5}*R&`tu7W5rwt3;(b`(Bc)1tJv3Zlf==7n$DQTTLB zx9zE{wTTjAnU}t8#|eE-R8rbRNtu4(>b0%aUEOHpZXL%z^oxaEcwiw-mtZs_MP*AA zd+qcIJ1n8H*U{sOyg_NV^x~JaSwgbs2D!r<6xAo>sKxf&$aQ#v>d{h*>?Z}YGj!ELz zj!Yu8<3rx<$dJg6Nz8XoTuZ#SOhEi7F5kH}n-Z^c6Ss6*u%1H}u_Z=)2v}ce$bOazo$c zrhS(i`Yt#0U2f>R+|YN~p~qZG2PU%d1+bA#zVY>}Etm`#!MeB{KC^>p^$$=Jb?OdZ z6&xPx$F~-mq8W*%rFe)P8q5luv3UbDZW+fv^phGDN8@1Ih77xO7BP_aTlZ*R^lfHr z8cokjsp$$j!_;&eCQfb#?f~utFhkz-BH+cqOMsUGF9YrZ?glUw*o3LTCQJo3VJff* zQ-Mvd0bUE-17I4j3DbB@Zvfs1ya{+S@D@zSdOg>!$rhr9<8dNLICTxjciqO zn^yiDWV>5#&E#f@;wDX1a+}9>*~2+O-Ct1E91B$?-KlC(AyTy{i(;>;I&_4pLS&(` zNBwvq@&-lKRIC@jL{*(EBzta)&y6wo2MLQ;OC14j!(z8QNA~(p?kLMUGE$YYHBI?Hrkz0VMA1}1* z=qvMWZj`7WFFd-Tr+&PxMg4doaubpI@wOKAOFTM`>XCkPO@)gq z)a7N@8ERWgyfZ@gSQlXbJ$4`zun1f@8aM{P4urySKnrj@@Bje21qvquCjln|rvM9q zMZl>5b|4h61EKIh06P#0X97slg5ujz$u$Kyh@zG(^)lY*rV4eY3P+4n$b}-}h|eUO zy)K_3PI}rFRfIDXZHrloxJtpcs5);xi%_&JW+}Ewi>lM-vj|1oVwR$lj;gchvj|1o zVwR$lj;fRCvj|1oVwR$lj;eF&v*@H_mZFo6s#EK;=%k}iJTjv^%Ho*niPWJHit*x9 zPsEwVEIvIE6B@<%^h7?>xW=a^!zc12GkhYYQ#~0zk$&d5SJhZF?k(W20$RudYPtd% zp91Q|0-CA<8puK~@F3tUU@`Du;32@-Kp(IK=m!RXL0|}23Y-IAd|NmdSPrZJumPd; zNsN1;XO4Rdt>X~T&lvZ*Qevs2OH6a5#1=f{lB4Sh zFLXWOh13&XNIl_&)DvDvMR<)7qzJR&BEoIBh_D+jBK(Gnh=buG;$gUmxEL-XKHhP! zkrU3i*KkY5y@n|60;&#K`?xN9*0`62s{cjfULisg>3Z$-2~`Ke_DthmA@T-A^;=ob z827SJg|9>PWQ52Y6xEq!z1W^==vheiJVEvbrR;iD)rzoYzm+<)?mKDRYkQ<|uMpYE zq-@c+S7_OhCoMNhH0~81-O$sx*VdwOuMm~3XseN@8eXuHlGtHa5gxyG91U36n~1o_fFhp( zJ_~#f_&o3h;ETYQfG-300$%~X3VaRtI`9qPo4~h#Zv)=}z6*R0_&)Fh;D^AEfFA=t z0e*^cFKU-&jF+u(@2AHpC@dw0J5pk)BPFIeQc7<}N~!BeDJ>l-rJOCr=#pwPN9qYL zbUopP)DvDvJ>iAa6JAI?;e}L$*BC*HFdHr++=hz?yWt|jZ@7p!7%n0nhKq=c;UePW zANO)jxZ_@SOUJz|GRD1ywDiToE)+x-s{R*^dxfZMX~kYUeL~fNuszebSBO;KkVUaQ z)o*o#s`+Q33LlMog~%He)tP0z_$8`i%|f#039>gRb|R2hPw4EoDlJ;?wcknOURy-t zULmrRN!g-tuh6n1Pg-u2XxuA2x}m3WudPMnULmqmLXAAtxR;fb#16ZX*hNiA?2s#o z9dISFvqDMiU@M86<}~i*08wVyp;jUq_u5)C?iC_C;N;N`If?9`lgJJ`iR{3W$PRrn z*0W!lNZt3+xYrIajeA*?__YI=NZl~fxR<@FFw(e}MTuWKGKtiV4|%sELn1pSiC>$Z ziPX(GTJPlmkwrTuG2iWiNqTmuN#q8Z#=Z6nXxwXyXxuAAcEMNXY1}Kc?C6u0oj)Y9 zqeLP%^fd0Z&C|G7h}=Y^aj&gK<6a?hGmpl-Ldy+3jeCWb8+sb|+FCU36(TqEH14&v zXxuAAZs=*;E419u)3{e?xuK_VFKcCtdz;2lJ<`uN?qyeV+^c)63viGat0+aRq7-qA zv$z^K4_E`N1%`ojzrBgi_K9PRvXg0nn zv2DxFOGh{9y`sh)9EX^$>Yk2~RyxT4$?=%w(SfE0gzPd)xx}B5w;T@MxP4@7=cqa< z-aRnbNjYWsJ9^XD_8oLRxiS#zwpK^3*>KH9)#CFT4$zL$Kq6MPf}uT;UDc$sT_b>< zYtK86vfgk`?5jG$BUVH=#1p+%wb=aHi8NJ{!k_zyZTuT?eCmS5z}88=Zp;cj-3Ia3jAW z^DV!^&G9RWgymPbIetY!vHS|R*;}^h*d|xLaCKlh(Hs3vWRRWaZr{9l=V+3KbSTBB zVh%K2t;)xon7^0mC~QG3;t*BwwZJ{VdjTxr6|sa@`~dJl084m9Ea4Tggjf71@G$^O zctuRI7qNs_#1dZd(*P#;i=PEB!C(A5@CD$Dz?Xn819)TcE5KKQuK`~NFu`BM1b-0| z{6$Rg7rz5wg1`A>09$997Xpg_45^wiq-w^Hsu}HJGlo>rG>n<3cobhfPLWAuD%+(@ zC9WZx8Q)H&ixrgADe9yw(a%V#BaDwz(HcRn9fiTE6--tak4RpE1>+QH{Q6@t%! znC)@Uw`ceqM2e&_Z_SE%tBARA_|C`)V-un)6}cAcD!Z<(N={d*($bZxgmk4U6@?T_ z9yG+}5~jicsVHNy)DvFldcq5-C%lk)!V9S8!jRa zhKq=Y;UeNE0QaV=w;}E1T$QI#ac+gH*Spmu=+c98*PRYR0Q@ z6nFv~A}Q&SD7kYK)f|43XyE$LWiekPYp4IXz+7>CVJc?rEAJ1y}6>W=@bsj}AM-b0y z`4w%8L^F?~nC*yXwfu^sc+2o`{KV4m^4?d?NQU!zc12)sx{9DV^%c@QL)B z8IOM{9gJ>fDpySK$yIqa_h%2#PP#M3;#skePWftf5bsC~DY_f4PQ*fc zUTnWy-FXErTpZbSt$|2)5?4Yv5a7f-S^b@hrW-}_s3^VMYvdC~q3<>>2 zEVR=;E+q$d^-?(n(<7&FdgSz4kDT7?k&8}g`rfQQsh+Q4LuuDjAKPPxBh@VDw$V#Q z=u%vDhsU*Q)@EtfxqV14)|;K&O&cH4H=O2}CUk*hf3_nPvMfg`Gg*!z;cc@b^=(Iy z1-7He2is9(hV3YF#C8cfY)Ty^g(#cY zRiqJRQ{tLtlbYx8Ws|LFWs^DKfGGm}PRH&%tmc;50Zhb~Flk;wN4k_sMlzM>& z0cQb=fd>N*0nP?M;?feJ9~b}zfgxZia1O8xzzMk0a$p6p5?BSS2F?Spc3Z;QZ3%0) zrK^Cefom|Ca4c{f&;lF}oDW<8TnJ!2*W5)|Y8{7we#XGnm8x>(N>zb!rK%*kQdNXp zsVY0JR23Q_#qdz|qFt%VYFFwBFD!V%3#li(kb1%ksVBUUitrjkKoMrcMTFaM5n(r6 zMEDIC5eLIX#KUkAaWPy(d@@FpG;lSNexiY^q2>-;4abaE(ZJPEvu%i^oM7OZX+osA zci?Jxb_TA7+kxtKD6}WZd3&xW)}y3?izRTe1TL1q#S$h0OBVx}2rQ|RjETS!_EwZ0 z35)>PTT#N^iqa-v6xa-00$d7UFkgBUa2c=_xE$C9YzNTuD_sGM0XuXPPl0K#h36YIvQl3*z%x+A4@bfi>n9VwMrM@r?@ky2T8 zq*P9ADcDGybEKZ|Le~>sNIl_&)DvDvJ>iAa6JAI~cn!vhFdHr++=hz?yWt|jZ@7p! z7%n0nhKq=c;UeObL0(-?aE4^4X^yj+&2f=HwxdX+i7EiLf0X*nfNy@Qx?MHotZ2VW zq`JSRV9#z%!EWhK>w%{MPY0d>JQH{!@FL*Fz)OIa0xtvZ0`89XG>=w#EZ(Vq6VIdh z6vYgOo=3}2wC7eRr9H0}a}9bP&1cb>|Dm+@SQN7odLGSZ(V71tHhV0J`4v5n=CcSz zJJwVScq}^UNR@(L(YBbS=%gc6CLW7UI%X+4=}483$D)&tLh(R#CyvujFF9rN$-yi|KNCC_{Y>yE zI_XFS+^=Y-W0s4ozno6;G-s z;;egH9(y7ty8q?Tli?HfSo&TWK2bZRdNO>X&PnxT_(V;T>dEj4mZo|#e1dzao(!L0 zRH`S#CwP+T$?#G7ae+zoWcWmxPW5E?L`hBcWcWn+n}v@iVFwQ;&E#j3=xa*yD^xSo zmYFSjlI)XdT^UPNQW{%x=EhUvquVy=Evj(6H}x}A-t!4n#y~))bW20BuPU#+7$7z1N_oWg~>Blox9EG{67dtkp zcF)ib+=>;E=_}T+YuC497sla2zgXCV2Nq5v%}$TZ)-x=&kCQq4V_0M%Ta+?ok!6O( z%|44PWQ$U!EJ~S*%dM$F?N{ls%pE7_mG&|chNo^P(rQiZPoQPoe|$Xe_M%T>VG5FR ztyN9yuNzoOXXLm{AL>&_=!^n>m``P-)zZ-^+}Z{qXLy|Kn74F<;_zOqi9wO8sRHBJ z?Dh%mx9jZiy<8mQ(Tcuz(?=ip-CEK2YKpj1-qgFLP~6sIMBLF-5tl-7*GKGKMVvJ` z;w+05Ri?3!BhIo|vFuS)5toV-ai&G=TSZ(7DdJK{TPmfHZta&sak-}van|IBv&@J% z3pwH}Ga}AHt*9c-GOb7vXP(EtRm7!`A})pE(*dzfRkJ#pc7+mas{C;@RX81?DjO{1 zBw|?{c2zc5$VtSqSkZnrClM>oL4S4h@*TUb)nDbi5|(cn$3OHFj>;N49_#(KCO)pH zHm-`5lnFNLt4MPlCmS$Kb{Z}8oOsW9yRIiycA-s+AW_Hr=t8Uk4 zitZhUJN+^j8PG%+b9P6W6MJ}t>Re*49p)IT2yi|{q@FP`mtj%uh*K81Cy*7w%WZqd z_(Mqc6qgK()VD~^5FjGUsxjw~BHT|odLnjOnm&7zVsIDCac*U#j7n=n+1S6Ap%^Ej zp*T?z8ftq=LPPafYYRUg98)I;^cQM5KF4J1$`8rLm9E{@jD;$ZBnfO;tmtEqQe^fS zijL5yDQ@Z3q*RJrK^P_-p-)p>fW{`d4l_(TLS<44#o2OiPxf-VVra3lMjt{*c00M% z$c(;K1Nh7wby@i32hdH~SC5TisVr(5$3OIomBmr^L-ae+UAr+&jNyU#5>83$C2iyJ zJ0kNXteo`{u2amHa0#$pGU|N^D`&jK7@U}a3pye)Jby zXoyu=x=yabO)zpZ>`YL1m8~!won5a}3$QLtB0FeH+6ULjjRdoG=|fz**RNb_wFzld zxsXg05!Q+qtTvDA+@(^ar>Ez9tCF@u)ppK#Lli2bE}h^#hSq!?_T)Vs18cgFS%$() zR>O_ z#Zc$iRihhssX)u%9PU$;N{3MGOJ6ZiiRm$;Z?;G@r2pya;{fnw1+fUBB{*6K#maLX zc%MaRQF_AO(7eZF_C4V+L9RvN_E;^$3ga`n2zDa zLURvxX-{7+yFzmhcGaA*kq{GvS7`3Ru9~yXXIE(M!LFJ!&u3R??!m5_v(IN&XzszT zS~JLJS7`3RuBdS)$Ty+62fL!Go4~Hn+=E@gq6zE@%_BX0^HmOUoom)jPOXq>OT5!- zOXwVt5iUXNLtQn={47g?$UaL#CCieauFsNC$+9HK>a!$NvMdRD`YZ{REK7orK1)I+ z%aWj=&yrBdvLs07vm{iqED4(VED4n?OQHb#ED4pQ72j}4YjP`$qMj&qhr~skwWLOd z9Z}{yc7#TT9Z}*uc7#TT9Z}vqc7#TT9Z}jmc7#TT9Z}Xic7#TT9Z}Lec7#TT9Z}9a zc7#TT9Z||Wc7#S!AFC3UbZ^_lyXG0C5IPr2cdrfc9><1o_t|I_6~43~-MuyhqZ}K; zeW8x4+G(}n%59srj?$*+Dkgrh8m=$m*|Pm&eXySUjNUg3hBdISrElm zS`f}Y3!?Z*3&PoFK@>h|K{)#?h@vMg2xp%KQShV%;e1NI{*^to<9n?rtMawNIp1rA zC*NyD@s_U@&iP&|JjJh7yDw?VMU4wZKE$t0RHU=dg2)GHK{)#?h}4l5g!4)Mj81}F zt)Lq%y!c)!(nh{iIL8zEeA^pM9E-%8uS3R4GWq;gL<+f9go59Sh_Y)%DEO_2XuDQ~ zLY!>LHJK<;*3{|jxCYj@Xj)Ej8(?fua!X^}2BbPNJ-s$WYB@H9yVr(DE60X#_u3FC z<=7DJh7G;6=3%E{gLEcH54IuV>(~(P-f)QcIyQv6*M^9%V?(&dHWaOs#cyY^E4E?k zSY^!MeX_DHOQ^wnzJ!^_-!V(n8&rz=7tUgqSV~qnCaAJft6OkX*;sUlCs=q_z7zSm znp>=4`Hz#&yf4zR5GS9hW7&w~6}zkQDEdEhbP%+HbnMZN&V&c8_R^_>YYl`j;|4-h#daWsW37P@X52uCy4((gaI7^D z!c1J@(KeE#2PP}~xWY4atO{@OYw=^tX zepq6*dcoRd>-@2v=jvE5J}L9XY*f59jZG3)XK8G1`chL=k}xVrx3l9=sZ zx_bPJZk_NiTs{6pk4*R%t{(rQGbQ{BSC4hUi+ z4#K~1_4pS}hwv|4J^n=r6aIy(>t8N{*#4!f$G<3H!oP6!_!lKi_!q7o|DuEm|H9Sd zUz9N6U$}bwixMXM3s;YSQNo0O;p*`(N|^93Ts{6p2^0Q>tH-}6VZy&~rG|_SyvNO) z-2XMls(!`7g6mrpFWa|pbbX7$W&0M6u5VGaY~RAs^(_jP?OQmyzD2RJeG5m|wZs})oi3x`8wPj9|Q$?9aB?sPId zKCqYH9W5N`_894g2N{IJ{CZX>&h&@EcYTB#kU6v;p1RU>62P)N%W$+DW|M=yO+xg) z^`Ri;WcfJM-FGiH9vy6{INd9s1(B=Lf^ha&kbNj&K|1>^h?+!N5Y9deqBfBhgtO0r zs8OT^;q0>@Y87cgIQuM!nnhX=&OQsGc99l@v(JL4VWb7&?6V+h8EHW{`z(k;CoKqP zj|JJU5*DPh&w?m)(t>dISrCOzS`f}Y3!>0T3&PoFK@>V^K{)#?h(aeV2xp%KQRt)v z;q0>@3Z1kdoP8EVp_3Mbv(JJkbkc%w_MDLtoh@-jO1OIbixMaN3s;YSQQm}q;p*`( zN}KR6Ts{6pSrh(+tH-}6X~Ms7_4pU%O!ybB9{-}03ID>?<6o39;a|AUN~R6valh%x zK?+%0n9C0*vT_y4AnfN57@ATg^EjJAn zZ^q};aP_+V`_!i{8Qr#F>t*UT&ok5#-Ns8twrv~TinZ3w+i5CR&CZ>vp4wXBOi#lr zmh}(fLWcYBi|8R*+t%6N-q}Z@B3`k4zJYz6$d#nOSd-|jNhCvwWGI#tmkzJh#-=YXFR!dzf1!Sw*1uwT`q11znEpL&#qiqnp|pDF z!q{T-(1odZ8dTEIDxLUc%`5o@%`3~Peo3W}%9dhOM0|A!N*4^Qj{T`Wlh<6(mx`O! z-=@4(`y_cATZzTWN-Ujr!2rJ<4;(B!w5H+0LtFYV9dBb#>WO`+C-$bE*q?gWlJ!Gz zvf^FlL#z4FmOjwCtS9zG@3P$3U-Q6uYx`Cvuj=O6V%~5GTLMfhF|*VzdaaP%kP(rKmZY9!-m8L$gEAY_<#asMJQRDG;THq};1^b$} zs2^2fNqJl0=ZfNSD?hiY=UZ#$bzEnfyzY;A9YuF#u~5-*Uy`p6KTSUM*Hn>j29s}k z1CsB6K)$+=uZ_t@y^DJ8R}Zm&*ZvQ#K9rxA%wHTQ$y{`q|q< zxotb70o%620&n*VZ{_UmYHrJ@Z99*jscm~<&Aje*d7aGO>Jev{K+0M~MOSqJ)A{fQ zr1KGh&UK;l8m2GNc`ZK^onKTloqJq5hxy=qdm=#RqnOS|HXxmk4s@;yorjseMCWz< zOmu#6&2+{`$|y$3gfNDlVL~|nOwzH;=VKa>&&LHm*M-mPnZLy6^ZA+h{F2)FEH*(Y zKKqB!Q?m)`eljC`JoC7v0eSp@z~j2`_yXoF@%Tc1CLX`Eb{^ZCp4!XSlyD!f!{pk~ zTl026O4Wwm#(P4b#(trOoCtnd?M2_-azsVn--J!gOt7C!Jw3_nY){V=?X7KmGMyO6 zR2MScRXdsN4L?MteL4M_MW$qGvgC+ydg^y!AX8n)^vc@FWN$DbG9@FND7t}X$~}0yJ*Q}5@8Zr?;zQ47qgrm$W#|Hy{2|DiA@QL zOi34QU+e)6Jc!#IT}*G_DEivbav`-^qEm2S2SI#1x#jP2&Zj1SuTDND^PHcO-3lTe+!ws`Y zx}BTg9^!ME&&wK+&&va!>%wQu-X*fCl5wB!EuV_F% zuL^vw3!l$s{t}-to0ssL`24Ke`E2hXQhd&s6`q=lOY1f(%&R<8IV*e~^Lcdx@)`Hl zhdmQ@*fX(&`AdB6=V#*cvuo$Gy%~!5ye|jR_mf%SVdnAL2IMg=rVl)>1CKEqpR~io zV@y0I&&1>B)Xrmj?^Ao5(Jp5l6A5=flvg@83*pZ9K#l!C4LKM5+}ex2z43^OzP|~Z znvDus$JY7IyKoV4e0CQfObBGE1DS59nN02Wt{)7rR|l(YHr9>d0^@YQ`tGr%k~}xA)wRgxiVYcI2UfOm!jC zO|_Fr>@ZPeN=7*Mn~R7qZooGS!7lx7SRj4zZ4}$drsn0-5T12ls|Rrn->nj@rp2*6|gYc!bl~ z7ZGo4z?tGrfkFF)L2{<}Nn)n>&V*6r$zDXQ?6SWev#Z%LAY5!spq{U$u{+co07mpLf>IXM0}* z@p)fP^WV?-yq)>HtpWMGBk;K{e4fMnB|gvPXX5j&+WBm6)=+%zOtzBi_IYYM-v0%B zp2|xs#+c7nG$5aM20qt?&j&MqiO=)+nfQEV?R>U(pb($^1L>(b0bI9BEb?4c9_7AV z>PqJEt_I}sRe{HK;qiRtE%EpeekLAYRXdOE?KFzVZArTvW`%2-6}~!V>UI1z3#8G!q;-^c1;7eZjTPc-7mzIv%-tGHKW$;RDPz`?V6g2-Dz*h zAz~-9!ckPWF(UUVr*aPWvCO{5G$8vP7uZ)9_MOITBlexn&&0lKYiFOmhlkh~=5TY5 z6(7%h-razF9uIu33!fjz{3Sl0!Oz6!N7v40cLz~>GFA+8xO@Ciz!RCzPiR0sV<%d; zzGpvN-y?g+XEJ|@&t-llK0l^*KD(Qt+V|zKw{CN|c`g>uKZpBd=J9n6$m6F39@nK^ zt}t(j$F2NKJbrBLJht~fVWYe`hwDFc6)qz7T+{W`K#l!E4LNiBxY~=py-kRUe$s@6 zJ0K=;2gLQE=+~v_@2O!U`)J`UQ-v^N?89nTaLql1e zvT*&0^G%><1~S!!Oi!$tOkMU~3nCMbM{ZEJa`yJ)a+{X5gGG0a#fn~#eOI8dHwCGQM^y0sk{y}^;s<+azVt6h60soc7t>*+P>=!D?3Et~!FZyE7 zfhziT7cDtAHZ|u=vbtz|cWU^aPfVug1~S!!Oi!+zOk%-bktyk-*&BEQne=v^X6ktA zzo+TWCtocex5~{!7pC7dou+%FtP^*Nn^#s+o#vIEN$48_nd(BOr_@d+d)2*7kts|< z*YM?q=Y^tQm!kjF+Kaxu>aL1@SF#Z_YdjK`9zC`GjiKn*rRZN@d(pR7-KpsN$0Jj7 zR4{8i!c)d!JQ9ybo*&3m7cxDqb~4%P_(Y~;JQ78XeaY`l4LDPLb70VZVUV0D#&uU% zTWDUjblCvS6hD3Qmd)F%8@F#A-MDM}Sar*`ox9FdqV}@>dw9jN{=sUOy%nIXVr&Hn zS2xsjb;An+0rm?4#Qbn+eZB&3FV|Cn-HtgW{9GjNwzmloiMh{rKf99Qh0L@&8<1%)3QVgD)BeoNqW<7t_?eh?K|ZF5 zT?49rm`qUbi`{K?<1QcXoXYD|Uc%gcaRYMqrGdM3;qG6VtHj;E@iTGv!hGBn+aAE( z^kXgdO6}B4GyWHFcPg*Ty^Fc~vIgYt-GRGx;qKp=tHj-Z@H27uqI}#HyDSuU_vJA4 zesZnCE10t{Z$QqzGH|vooc$+rlsNk@ekRU7G#_WhW{wVgRhn0{m-FUz?b8A`@8wOS9$M`E!VMUgm}OARwTy1gqbPnyZ)aWkn7b5+z~uGcYl?`c5pzCLib z9^5S%A5l>~&XVzQ2IB6+^Kn<~eNo&Ev$MG`$9*Gn_YDom-8Tj9)`h#qhf|2Vhle}+?)nG5 zQ?s&iKbf6~8j@X%@h?9&+qUe5d8SeWV za3c5vfj0YvHsXqdXeLkm(nRnj`Di3INwis49QeCgVdB>_KKWoM_WPyS%ZcAh^A&Tk zpFkCJe>ZDtHskt@$XJ`iU=AOHApAWmI~ z^Qc_Jsg%W%x?)Z;^Sdv$j%PJFe2-!HNI~4>d?YZZF3hGZPVUL%j|S${g*jVuGDj@aE9Th4oWPtqEz^H2FsClexjZLx#5%oVPBPAE^ow#o z-hi{np9pl>FLaT!$Onj7@5il_?PdQ8K2u=qZqc6( zq%RWErw5Ij9XiV8w$q34fkFC^U~g}q`f}hB`g~yeAwl0A50n3-Af;mC-RORS$BNUduEx8xxjJNG^N9pUA~y8_nYa z%?LDOZeT`q09Hh2MF&Q+ql2P3(Og^zF)x}Q9TFWH9TpuPEr^bYj*O0qj*gCrj*X6s zTB75l2Sg`CCq^elCr7753!`(q(5f!9x`zo= z1Fh^007R=~;Ik-F-9y~K5UItTeMzhCa=9y}Rabc^(CWVXqLS(^t4mZq7id)%TD@+s zXk~9WAX+7>KT$Nn$Y>;tj3)k$=jQ_*>OzOt?-d>FZ3L~I{jKTu48zDsZyfk<*z^2_ zK(4xw>kWHDu8O_WfXKxoBXuw{LMKkGmF~+foG~)O7%6n&%r4v)1Fh;pt2gcyt?X?G zL@OQ{DO#zK(Y~gYF)}K5g^>}85s!?%6lhf!TD@tnXl3tFAXFQ+`6g+kU9N zlWsqBFY14|{rGwyQeBAj)7pq+ul_3{btgO4B6ACj>@oF}lOB^ALG}k%J zz)IL-uiX=SlA-k?><>%ULDYfFY5Q#BWp`_PMR&0*_Joa>Xm!37cvBbNyk){xr`2AT zC*CAu^F>%Y)C==^U*%NrW~Fz6mw8j}?%>k^9^Uk-12_MB^Ss{<+`m?(F{K2)={=pVCRfUP^mFi}(-j(H+i4MA<#{Uj|EGAAP^|{3| zgwb~!?Vu+WydusY#fzO646KeT%@Y2Mqt|>vUn-`*O?kYSO!9a^O?i#Q>d#m@?ScWm zwG9u($D1!0XywJ%3kKTKhv|4Tds0vAOFgkS^~C@1@-*<%E?BEdo_2}Q+7wYjnpZ7dHc-aCmF8RdSzQ;{jPKMY z?&`ZS%{wNhr@e?@sbD`RPr#{tG5Vqby*p;_598eKq37=YQ~OTqKXu{m0sKF3>cS;w z_bpnKG8B*fM9~USl(|{~SBbDZlec%&^-vY@|9(`!=TPzcUQAW|`9uE1(+>hw)lQy3 zRaAkIplXS!sHj@{4nNb)p7_QP3KLP8sCorIw<+rGoS3@yz5|?5O=tY{T!>=s)b&bz z4eOFqclXH_bs^}yyHB;WOX}IM{>a;~{y4BTur+B*1zTmq`a)(SHLUm$t;N={U1J-n zBb!Ec>>3@jPLH?RTNv8g`@2(SM$rbN1*FETx3_nAU~zd;olkUZdvWPP(gE!ozGzi{ zzCI`Q)bw|~(?6+s`)Qy?phgBY#N`Uj7kTdDi6(^VGjFr>e}Q{}dl}pl%~I)~+ze5( zbOt|DC-TGzxG8p9bYPL#oQqL2G3p@1RL#ZQZ8UYsTnxI5Y7(ZOregX}#k@>kG8eND zT#cRam)4*^KxZEI?Rkm@voP@-%~UY<=U&GCA}}^EHXmb~PiBS^W6$JgVr+2&#)@qn zU~ErdtY@Nz`m*sv%`d%-{Z(LWU~Eptp27?z#+Lb+7+acvvGx{~Hrzki&HZ0qWS^=t zyuLOT6ELcc)yo}ARKM41V`FD(ZD~P7HM@F_HTN>e)V8s|_A>T2fw6(HIT^c<8A^<; z@G~*Cc>>1T+hT~Zys0cOHf~zu#k#nS{jHa=zYB~FjLpedwc{*a{2<1*@-s1ZS~g?b z>TA&O%g|IiLtzePF+nHW}dLmz;0vz=w)crb0~NrY5FvDWz}|R?F5TlUQrwS^C0IA{mM$MV!;o$C>JWRXQzh zg@bEIhG<_OT$8PEFH@8#{2+cN3eVwZqVU`aC@i)~VL`|^#b!<~PtB%dFNNLSa(u>A zorsAWXzEC-2D*N&aMQGe!nj0U1w-{wW-x`P2MUK)IA<$-7E_ccyqKSf!Uyv+QFz`2 z6c+oY(2+K7(M>2kb+cDBP*_iHDVm=)P+tnqOelN+Q}{rp@T@@LK;fJeelSy%DEtt9 zCJN8zXQJ>S6Hr)eq*4?%H!JJ0u)5|!O+oMd1hkjJ6OV;KVRWRGPQ597P(tC^OyRjq z;W>fAfx2#LvV`J|X{^+OmraDsi$b`a2Foln13Lh0H94MTV!b40^qVQ6FCJGh>M{TnHT)n*UctA#)6KAm-JLg8bW!YxeU;{t^Pg>zE) z9HuByco{zvg^%H9qVTa3P+08FQmrtLg;g7@&IYOlrF}?YwdPAaRrey=TRU_|T3w)_ zoa($T{D6eQ$1{abWD1`UC>$u9lfvgRMTx@8`I#tu96u9CY(rCZZE4)ib^0R8$N=M}+tl0geZjEBX>JKv&tk z4zWQA^GlscV;V(|GnlmZld|at7rhfcdow5d5a!T>1BU{KGB_mWWJ|_v5yYYHob8#j zBdD!2+0@rKoatlEoER>zXU;4MoC%!C$rPK$IeW8-jUC39v);7s65PR^|6wNv8EdHFcg>27vN z?|^6=&a7t6tO}e7oXN?VHG(s1b8<%PH&A`E#+w6J!<;!Ua3*jjCufEQXV&H9jJprO zm}_pB!&$>jnzey6fiyWubD|*4NjXX5ZUjib)6_sG8rL&v)&xB~!Pfpi8j95sY*r_rh9}x%{2$?}hdEvyT?eS9a zGyJSh>=gga&+2qt@jp3RId><5^{ozl<;4HYaoCZBu#aTIZe+r42!suU%}LnLG9lHH zZSiybOoY9UpXoSkl#{Sx8${W<(n+6D!Z#V?1F`$2g{33wNefH2Ptfr`bsW}rF1FG; z)Ux-7V?AeLark#MA?zk5>?KUt&4I9iusI3)c_t(g_6z(>XJXYwF7XvlMA$+;!gh&0 z7>cmTI1*O?()}>eKJF6J`Spab_3aXGNeFu>6ZSGD?4tr<17UL#_KQqNBJ7v=nFwnf zdMCn`auQZ-00CjsL+xq|tFH^5x-PN*!UXnXB8FtCt6^2Cims)!<%P z^?tw1+@uYR&HPMUotBfEVxtM>m(tst8fQb}4(8DIz@fmQ3=YW)CmzV0Ar769lQUwU zi8=_}c!%f5m@`)d&IHcnC(HOj?CyO=XO17`wfa&o33IMbSw zGh&yC;tcOHX%x;}#hke^a3*jjCuiCOXWDaeMr<-sa}ABxH@k*8b9LZM;7m@=bO_FL z=H!gK$0YrjSL4h9JeoOkZQxAcOis@93C=9Z$r*Q>M+1&$9?P70OyEr5Ois@93(gGW ztIrI3ynZTKx zoLMS3b52gqi2VkNGsy;_#^KBpnKMraoC%!C$(dz>Gw0^yjMxW&?<5-YW({*V>pCXQ zlLBc1X>yWgx**MroTL#O0YI8`Cu##-IPnxF&65LZ0%>xR<^VyOnK?-#b^<8U@Q9{i zTAJ&bG*1nr38cwMnpuK02j(P=*b1OX!&?CwhBQxS(mXAYCXgm4X=V%3Fohpz_TBliaBu)q3kQ{J*ZcIs{X-Ne@ z9UgpMpk$zAPD(zMDX0$oG(Vi56(yU`pP-Etn-@BbFPUjls*~r_(LSoHBKH28h#So| z5?^ROr?Plq|7pfWOp1=X`!pX1;@ zC;YsTo6MWJ$-F7>Gw?HmpW;rY(m$AwbRf^TgNgX5+CJmPh~}njzV?WX6N;~9BbppK zSA3m51$^CN^0f@UmKQHn?34{<8F#lV9bVfzuxz+*$%?^&mi`sXSFXRX7yq^N530Xv zV4>M@y~W!~-WpgKSeU^=c`Wu{%ra^v3zv*;+pzVr%Eje}pRsGx#_GmPN49Mn-C8B` zZNGAt?!0aq-DveP29T%$Ue8I*w{h_m>F zWvkAY>_MB^TY-(Z9qSvuXjOm9%8Fvx%1X=1GW}8ZwP`7v(vBt#18?Ux?Y6+Cz@~g` zD!$leQ}HFWvB_R)?(FWb82il|kWF_oo9+l~3T(>Brk4sfy{tAi*=x|9o&A-Lq;nWW z4alY!F`Hf(*c8~5lTCLCHr-tto9xAD#U^8&tpVBe5@yqj1DgVya7th)W#-zX`9AP$tmD(=D~JN$iDCZBsIC;=^Clu}!vlN;bAX&9hOK_Oi!EPH@0P z{WWk}-y$475ywm>*gZSJR>1t*+0(6mI9T!~VrAS9PLG?sIS@1uG$%n{DG2)P+6ZcI zujuILZ#9Numm72{H)0%bBNV|)XYK5O=zToh3|&)ZtD z72P;C*;=+YPT<&NTZh?@scr81gw`}PW_y1^%bWyRo}AD++c=?B-|vFHEjgC;*0>!* zllBhoXuds=GLSNZl;T)c;pcWcR`>-!t7BP3<69l-yP(DPy&$o@Uqg|&-6XL-`>Zb_ z*jFU(I~x}fB=-{ZpFKr~D{+1j{ZKmKYd5#GQLVVtboNJ1*Wyw~6o?cFKVola(1O%hMlr9e4IoZJtz zm)9KBMB)!6B>o_i_#;f>4+jzl66YlGZ<(Y-;@|Nzk+_GSiNw9Nlel7UifPB^@Qjui zBSKsxRHPdare<>YNycnc(u1b%w0p)|k(keS4^1$$8=vgn18viz-JYJbIj#Fq=I_Uu zzaI8jnYxW*&Vi@F?&oCy#~&kJjx4kL;~BY9`0nYSSp~(Px=Q zp9wq)Jj%(V^@2y|?*)(SO*X1MGVbqh6drw^dGxu!qrjt_Ji0*e=)%3=k-Zm&<};Gz z!N&Qt-xrxjUkE%3Jj%(Viv*7zx)(fh_sSSo_B2X+^kwGJmjaIhk8<*8RPbo?Uhv4> zuJZrvod;ms#?^o!iIlVVo=Th{TW&&-)NIvSA|;!(hE2(qT_s*V`xk_mFA*rRVtj=n`45l5OF?LZtoCI&|+Xam-JeYpar zaP%F?(LKZwaiq!7<%px5^>dW1j+-!WT=zZ6(RYa>;z*ODD-cJsF*s7=8KD1Wu2YWd zjOknZ0}0ai2_ynZ6Qq6w(!*nbqy{wPdLS=G1~eE0(vKuaKO~R{Bu$VWfk0Xr10*$~ zfm0SbfK+*(h0D&|Z10*%10pb~CXt_Zk{X~NFV*-gl(gdl1Kq|%n z3B@$9Y)Jzx($6GFKP8X|Bu$Wp5JKbDa4wBw)1Z4U8?a+^bZQVfXIa1IW! z7}7F`TR6t7@p@y@j)N@mpudWb%t78CmiYGq;@?S#|0p5;13^p>YeM`}2`Pv8XL6fE ze6rl;5T6nQVl|e8Lo8zL{Sdcuj2EV!o&s@!71!g11oj8Se-aQsAR+#Xg!s<{F+r>e z@y{is9O7TdZ4U9Na+^bZTKy2`)Ib)tZrJ6A*eL+Q5N74L;zJx%0Hnw)adHZP{8jS% zcggSHh+pD2gkM|$$~96)pg> zN^-=xS{;KUHC~2uB;#dF355Q)*SXG`=3%jC*xl2zYNBlMDyB=;WY*ZwMZno=EsU)3HqwP5?{%xwYrr`w zH9ox2J!5)!qdW%M5sVjyaS7xRR{F(PqTaMKL&1 z!&MkZS@Xtq&=8CDj$`39Y2t{+b;9D;;OJt+(W7HxO)^Vc;WA~`ykI3kWTIog6a+FCzHd3R1bF;XfFS!F&yGH+aWnB?eC z;)poXXgUT*uH(n$h^Jf2ah)mY*3CyqkPau12qaCA&O{)!#Q@25j|z}jy0tV& z#(;E`1nEcui9pf>=_~}&*)c#;BN}+!0y#r62Bc#oNJkS$1d=95OA$!t!~jVRY2YBq zB_v}&I!=OgEP+HIX@Ybv0_nUMAgM78JV(R8InoIdq~i%B0!b63^ASkxS|IUhP$ipJ z!x*3fm8_k^auh{+Q<^6@#ZPaV3+Qh=*iq!^O_@I4(m2z%t}UvYabI5_1nu-MEsbq( z8ynkgPOwfN{AqJya@fnt_=cf!1-c$bH#BZOk#pzzS-f@JlL$dVP!GY>UsMEBf73#6 zZhBi~$LyZD3tbjFRTjH?3buivd8bM%b_yXx2Pga{!`gx-P>`oFpm>QcjpxD}EEIe)pb>bfZ4AebojXWG`;;7M4=+zF8U z(^o7_3=ED872BMQALc`d@Fdvqo(<=4y$J&oo5l)lJguj1)NbQBJ$<8@NY4Tfq-X8~ zRyeeIsif&_qKRnIr0HXbrcc&KlNvO&>%weYifF)JP&u zlN{a|NYnX}rt^pLAw)D0`9NKW zbXTwL=Z&%=8A5~*(M053^&wKdWZ!KRA~qpHh-f16Hi3wJ@dYd^X4_?3W@l%1R<`fh zzN@lp@0^n+Gd-i`%XFi4_|8J!XGIKLhtJEE!yM5=^n}oZs#-U{U9OPuZg}sgk0!JZ zpD*Nng?J65sY}w-Ni-2nnl!x=(c}%^=4YGGI(%0l*K2f)SdXNsn`k1MG-*OHV$EJc z&HQLWtM^@nd`3=&475#slBQmwiD=TK>AlD{y|2EJ9$NEf^CqJsE*~aodMMFEG-=Xw zH=^l{_0fbP1%Rfk(KJ0=($r5h5lxyjy$R9e#TU$Pq=(`QpdOXk^QM)OrbiG>M3W{> zD2uxJt@YU^6pFy+O-6em1|>}cL=(}ZNz>bqZSrao%*!_Qpr{2H>E(>3sVHeG5KTmr zCQYwIG`*@W+th;s9DpXtL^n9fQl3?bpKdYdDp-@cak?N`Ptt z`hEoH%j*MF4X^0z^#N*G24pOa5;BBL2r{UCNb@VS5Mhz$xh!hX(4z)UD%Shc~GPUjSxcTV9IeRvBMukh)x-8UTB zOvNqk15Hxg7Ak?&eF7S&z^@&*n%D61J!7sNgMI7dKyxiYNl=DBnUZ!Z(*#|H{w=pz z2z%3iNJ~7x%rY-U&J6HkTjD7J z@dgR;CJFIIf|wxIgSgp}kn&_Q-|(43{7Csehj>j4h}Gy62%7|sEmj$_#d0h$yLieS zP%jL`1r_4LeuQ|lfcQ}o;)^B37ZJn+u_na63{ehoi-eX#JR-L_#G~~?+^Yt~Kqi3< zijkI>&54nBJBTCVNRy+T zh@&fFaD-xIz`5^BJvGJ8uv2n$IdMcBX>#;9#L+b|I6~nnj3e{Lb+eMAD~KcFNRy+- zBaW_(!BIfOh)g#%#U5QLIod@W5l5OFU57ZjJ_bhtK^x|Av|DoYSmKB{(&T6#;^>CD zIm%^F+ysp4vgY|2<|IdZh$G@ilcO6EM>oabs4AWz*DE>N=ZhBN(YZ>1kl0w~<;yfC zK4^5F9qJ(B<0=W#UIK|g(gbNO0%=_gkg5V2{FN7t0qJoPq^k)e0!b63G6HEL21o%B z4bo$03`mccAYDTs5lEUKO(Kxi#{db1G-M#j%fO-CbrPg&2_ynZ6Qm6Yq^TGnRmU`B z4YWx6BuLj2NCc85NE;DIn__^3f*LZuLOK6~wF7Px8H+b?GHq4@= z!-*FF`I8E1)1T!w&v)KzxgY_(>AtClbU2u_nZS zk&v?Vs;0lnZ4U8rxy>Q&hyk%0&H>dw)Y<_}ycpNQ)($`gK=xP7A-6fi4~YRWiY2jO4P4Aim%(M4p_-lrRRdVl+_bu7lgn>eYBuxpL9Ubv#4T_AE);Gl@2$Erd2yuA}K+k|thOAS1UqZFUU0 zPxQ4 z;%G|@j!{e4*s%1;i0?q{-1%#L>1G9HGb-@G}_5(TgQVFCvbJBTbHG z5l6dXa8w;!V&J&$rIMqU5J$w3CP!ByjvgC>BQ?H*l{56MDw#5_d%5K3WyBG2q{-24 z#L=D@994%{|pO^~t(q+AS;)PM#Kk~B!hfb@C^((4E$0!b63 zJOZgR21r#A4MtWOxLbns1_Fsd(gdjsfz%xXBsHXgStQ%Qavg7yAia@5B9Jse>Omm& z#sH~0romSl)R>{&TO>$tCXfguO_2H!NDtKlX=0>Q7^>v5Y8XSV%U3c=b|Y?FM&X>V zzNknd9O!_ILfL>g)3>f|I3k$|ijWpY*7Pqejcst-5Zi4d6XntM8~fl-8@w7X4zZV& z@eM=eN@1w2M*HEna_(F|ONxCFR+r;#gdicPhhXXtDuSs8v=E$|-d5Q$yJzk~m&KgQ zVpo@uAw}~j!-x1>NUqlU>k?JhMbYk365&a(;XS)QBfJR%6Pv~gZKF1GGK|`7b@VIw zfTZdDL=(}ZNz*qGP50DClNv8CzXp&5*NgUCKsQskBjO+0$)gJQn~mPaY0;Y za`CbHxTuZ}$jO|AE9#kF%zG6k)>Pxuga{#`iO9F=L!^53-6Oqr>he-93ecq^n*5?QjLPQghj|)Vy7hk}#VzynjWp;LE zXJz}2?Yk5Isas2tBClPt&L53JLFB z=Xt#5M^p7We2+9Z2GaCpNz<2zCZb7`CX@out%$v;ikpDo^ z^nIdh$c;%-h*g*Z+$eOSO`Xw(O!uA zBu)1cO+=F>P47cAy}v%1P%H$SHyQ1P_=%+H$3zp+q)F2U5KSMfk0ulg0k)|}&?IZj zr>wNK#A>w;vJSQmu@1Ekvkte8u#U8jvW~Wnv5vKlvyQh;uuim2vQD;6u}-y4vrf0p zu+FsFth21Mt)G+thg^CT;eAe+kDt6y+WHS}Fg9eFlZ5!M65_uQ#00S>#K%iWIm9Q(Z4PloZgYq)sUPBQH7JHb z>;-K4ox9Ann{EKaw*)wM2fb;qsAns?iOQ*PL`zY)E=~;lD|K{~`JP zJMl~WhVa`WdF0dK6XiDNcZ=NS{BDiGs~UF0eOSWin$zCxUy`eT5?91k2v@jL!qt)^ z&eh{$aHIy@FphkMb4}^-_8-a7zlkH_NRy*$5J!)X!I2tj!#z3X*&|;sgZ~mo#E~XP z*CLLti@}i^WW${)Vr|lxaa~K3XOCK7C1#yFR&8GAPBNQ^#hzhzPYX0HvH0X`$(qa> z)}PVYYAuYc@ix+hA@6mov(D)pl^P%3=$yip!AQD(DDd5n9pG@k)FyVJY}q)dkrhF9E(9CC z-#t~#`rpZU8%yA7@*Y2d*X@hJks1q=x4|hXiz65^u4{n> zOy&Y%@d(Yt5!oZDDX$FC`JqAeC z5e<16(O?Wn$4ZcnA&>|pO^_}{AYB#%BsHXgO_6*p@QeZJcnQ*R1QLOy3DOP((qm$P zq{cKbkbLz$i~;FH3DOA!5`m-%(&Y%GoiRW{K@HvDY!E}c|Gl*1mXqC##g>yencR_a zs)Y0uf|MW)ffN@2X+@AOk=s1u>7jC)XDmJ}2E-_$f;l>b$MAoz07%Q}0^-vo#Aix~ z&mf2iVoit-l92K++=JydhqzyEbBG@v17Z};!7QHVixA_RMR`~3xKqoDdrw0 zKng3Nicj_WJ}ZhT*Y<}Os{lw#yX1GdaZgYN% zF?dA*GmKaB0?$@Rt~!V-vWp>h5hsdXAvxk)&BowJjhA7GqMjScoP>f4Bu5V+j))^o zj&>oAu8hGE3YTF;)y+$A%SetcB#ww9O^zOmINBY9BQ;tkpY_ed%&|vV$&pPQ5l5OF z?Li#P#o!19%YZ%doRa2nl$RXkh$G@ilcT+eqpM|(U7zHrmpCGhG&y=A z;^;{+I8uW)__$64ZJ5K+!z4!!C60(AO^$9w9NktoNBInjn_x*fB5uMQjvg*K>L-qf zBTbHOM;tvl21h8K0SbWRWjup1$!#koNRJ?p2qaCAh7d@@F+frS8geWz#z2q;B}fAV z5`m-%(kcYf>KGuQhz16d9N8ITk%|(e0)a#zX@XQjAU!e$NNPv}vq+r=TBKnK(hz|} zAZdcM27xpZ10)pFz(A5~vBp@W)e@vt1QLOy3DPJ6X-o?wUI(#~&!}MxIdCs{Hpt)K zxKZg%bH0kDYchR(t26!WgB=B)-jwO%8BLkKb!}0}OikG z_|xVzw_-0V;~R#`6{u<&Ri_k+la@GluAjwgEc8f1kPy^EF!gH{!PIZH5S*LdR@pJT zXYN9mMO$UD3(Q!rG-Iap<{Fh&Y=jUZg!B+<`nifw)3547NR1`}ggR~W5E_>VjS)hG zkS0R+A%uQfA3|y%5kttl&fhKTBtmNmAwozKq3!N7)J&EunuvRKIG*WTB2?G_amBqT^~(q5D}v(BUhRXq-jdhw1H?Mnlx$pF{0^b_0gn85;2-=qixeB zNz+E6iD=TK>HCPLAJs>b8cxJ*lhHJ7mNY$zXd;?4Y5F#z={xn&q{b8hP5E9q(%Y)e zn_&Ib?H9R@ExJZ`hx8U%gQrHB(e)eW(G${Z51C=@Aul3Mh?5Xbnj{yQCaAaii~6`w zLxlL4E%{trOk5Bbnq1sl9~V_I2c6mEbMa{6g1FG+;(PURQ58s#@0DrbNgYR3hzsIE zlZ$WE$3;MNfaKzedgd4NUWJJ@)wqNZAw)D0`DJ~GRIUDZW@HSS0f=lNLEZG}{$TmWR5Ya^BTbFH_p4n4j2{Bvu&Q9-~QSxGP z>Uz7KD`dS=Qp>sWBv^zE6?c9N(u#OgUgE@Y`V9yz2MCF z1i3H?bl-uA;C{sSu>#*KCBAzkzPkxu!dDaDmr6W2zAuv79N(wOZI18Lqw!S(DYBh_ zue83bfi0V9ra8cku)c2!w!TGfeLYwe>kAAQ7~R4+7gh?Vj?F6)E&5P;uYh?@!hE%a z`6_~$VAh2B#S&Hy^RwkPhxr+Do5TFfXqeUL4?dI@(SpnPFq+}ays#+%`XK9I>k#Wu z>oDtZ>j>*e>nQ7J>lo`;>p1Ip>jdjW>m=)B>lEu$>on_h>kR8mtIaygI@?-monxJA zooAhIwOh{#fEhfmFpw@TAM_8PF~S4R_*#<7i;6Ai{P!9G?c-c%)e!f`6SM?v2(;KQ z`y2@+hxQe6n?w7oXh_xgldN6H+G4@EYxU^h!vZX#BQ6-`!lAXXj|&59aF0!{@xFYU@Up9^5VaU@Xs z+bs;f06FWo5D)}J2oN}oc>rMHc_&DrF~ zS+;J3x9zz;)I@j*bBebQvNbPOq~BZh0w)~X-@*60FMJ^<^YOMxNJFB%0;=~zXvq_W zyX^_wM&U5XClQ@QX9%6h-IjW{YOYdWklW1NmilZky>8Y1yc%9&_ZG5QvA|`JyX`hP z)Vr0~A$CI8!S1%3BrDwAc5^f7@1 zNxPC*ciS@v2m&Gm2;^?Fj)?@Ivue#>29z5#33-+@7SAL$h>Z|7@Pz$pWGo&R&5F9_ z&x}QnffM#SB`bFjE5wQ>E7u@a9v{sLTJyId)4{+=$a5qs&n8xg6-`#IMXX#G%?euc zXRH`#SMHLmJeOD@Ry0|;9Vcet)qW2Ll>?UBOr$vQMIUKg~x~bmzKshM23k5#Gmoh z&gM0|chL(2d3+J^NIZt{h+T58lKk-)nyaGuLvaClNW+o*v4UefA&wU_YD84%v;F)z z)i8_8_YDeD$O1&6y3ydW4k(SnN@S`z*9~HDo;LEuflR)Hm?S1cn8Y^ng^0;F$Zc*T zcSbXc;t`-?t(St$N{%@ifYnG~Rx-Ygd{s50oJ&R}+NFkWKqYwF>&nI$b!MN;sy2qvJA>>hWJ7U8 z8LM7ORALZ)Wgw!jB18#MO+;UyBAWW4+~#IH(4{(lt7@CKsbo`;3*y zh-Y3E?EBPOgb+&)`pNJ9#fR4gj`m(p$PscO$YIm;9b}q5IX?uaXSOLdE4tKRm0sux zBu&(9K5$};^4PlF$Qozit}w&~bGD!;aDja^#(?jQa=>>tQAJegQDwbLrOJ9wOsdof z7#@Z%B48}bfR@5Hu!Bc)dsVxW3JE2VghjHXMw;ZZ1>acCAeP=H zS$Zq6L@a5tgfb;lH%V&zO^W5-NS4%y5MZfGEG`>mm)CW1*5 zrY9koZjA+#8soqWll0OV#L{~uOYb3;h$T&yZbK~H9*ZS4*nv%$jI>Mdmn^-HSR$4* zS$Z;J=_#>TQUfFyOVTdQsEe|YVd;k6X$0EUc7bPjtX-xpDv8n;V&}c&A$A`iU|_s3NK~ zsrm|{>Z>uSQo|jcSn zqKc@}r0Nrhs+egO-D(H~n^^glZ4JcgGZL#$6IO(kCRQl1)|zKxE%pNTplAq&l?)#@ z5UbBgtUgOv5muU5eFj;pkPf)c$gs8>ut$xHfH9z*mC>&TV)X@y)#nK-!b%gX&mpWn zA8%^aqlQR88BjYX*L4lV>Pr%+1j8zCG*(}cSbdqWBCIsA z`VhkE!!fZ!5f;o^8NC+#HHp<%2`j=%6RVFPtUekOD->b@b1Pp_FarmH-;h{+ov^!s_EOu|gphV68fZ%Ys#KXSHUVq0Ve;gSwpD?Tf;7dk(cjDd_fg=&ev#=C(TF zuf3A9?eM141Z7!=s6E!#2X!qbh9>*re@>;$VH-N3L{%b-sHPNB*CHU67fNG(%W@l{ ze3Ju=8x(z;SSFT3SVqkkta}m5z8Yn$0rLQUVgP+Agd!CzdOV8s@b+> z`xMUizQK-tMW@7jHNqi1ROS!vJiDme6A1Em2xJ0T6Xb6qkWndV>%B2SMzJN#NXseZ zUDep_8|Yx96&P%8dJt;iPKjD9~5=pPW!1hgj5-;esY3CKK$VEUu&kuE0sjN>LcE0Vg4byO8Iunb76>jpX?2py#~+Cg z;zN^c9jURi0G)@h9Sg_|W9z7cu#$iZ<}# zzl~@{|7SvlP|-x?UolasiYD+S=Nk}N{TD)oP|-x?FELT6juw!kE(1{cE1^QDXrl7_ zn5a~R0Qh<%8i2~*2o*v_6O~`h4;3d(r_)Bu`K+zA^Z}a^#`zDq-1v7whL8zC2Ic9b zP${I;JWC-7gwWc3Zy{&P0a;SrVE-geh?5Xb&@yA{6ZM%Ew7S^i%a&dS3;oSd9n5NA zWw3zq2fXS5)H*0at%Jek&c6j&7tGnkDkDJUFgO6-f~sJdzNO=1PED|of_tfVuX$Dx`WH81xE$EOiBsY7zwN3t*w8RYjb_@RvGtR8|ZVNBH%gl3peglnj z0gN*YqM@P~kjwCu#<}{f{brm~Dc3lsTBLDq^^9{WO)wM8Auwa({B;R0huPN)mK$eZ zO9*b9=h+fM7-w}+JZFP(_K&<_Lzux|KL7Izzt&+_ANm3 zr4EsBA53r)+?sHI6~XOmpU&a_hDpK@q0j&ZlbBi>1=CRyrXvX^f=Lsm>kv%W$ASq32|%2UFBHun%XEx{>1cw9 zVA6zXAA;$ISTLcyet^lBEij|bnKCeCa;HfdSOknaLz?Hr$eSav^}p1yL<|uVLJSVN zxiJVv1zQ(7RR-B zq8#&`KqL`Knk2mtk@TWCB<0jV6^KIfg3t^i>10XLNkkHnq)F0?5lJtJMG^`bfw5su z<|`Oulunf>okA!PN}4FW6ruF8SSYCh8d-*tTyHW4rPC!!rx8kok|s(oM<~4_7D^}% zqPx&zpiw$gl5_@v1%wizq>0k=5K7OFg;G^K zMK&YiW&IBKMisnxW{|@jO4by4F&lWnob7If3)mRwfC6;;)7_rojAD1YO}G-Snz+6m z;rg_?aGjpnrWCQrR|RkQ!raYkU!2NITbLub2rfOitZgb>)^uawQsX(;R87Vh8VFaH zgsYR_BDgf+nn7@FZwy>jAs$_Foy$PDdL&%k1Q)@j3D>0vuFDz&7YfJdF8HG34TP&t z!qrP~5nP&Z?LcrnrZI3;MQHdEA`OJ=VG^!~5?lnACS02lTo*M4E)=u@b1tKYg%6i- z^%GnKmnK{nBe)*j7`RXvM|Z)iYHe8tTCSB6u164D1eYdU6$IBM4S}n(DzL-X&(lD- z1|?hr1Q)@j3D*_`*Ve|sRTb*tE8=M&Ttx|2f#4#zG~t>+a7{J_E)@I$b1so=Y2>hQ zSi&_#a1mUZaIHshZDSz zyogt39jTpq`zbKkjp;~zSGB?3HwgH4fKA>vAi%bhM)TT0n%5D{M6)K%S4es}&3olG zr@7o1nyVsVyyRACoLT#6HUN*`g8F6EG-m|EY#a`i@Ag5HdG-=I&U>#4xCY+-GScNh ztS1O-!desS%O%Df>p8j2v0hU**0VF0Dp`A-Y8(!<)bPgLM!KywaQ1kkwe6f$ z1ehjZD-d80X&hi`Yz~`)84cJa60iyZMu2Gob^!wH!o~rn#^%xDXCnFQ=o0*nCD1nfKn*!hhEtSXYj>;$C8NWgXwU<8;ZVC@L7 zWeo$YyDE~y>>A8FC195mU<8;ZV9OC;9gPF5Dw4yO<;QXrS|D+NW%#kQf%sv@@2Czl zh9tfLNZ;!yDtUbaPEsG+3wc1SMYb;;2wrB?J?regbxxMhqNV%Iigdp#IMX)VtJIYe z?_Gp9;T?i^O5&VhjP=WH9tpWhZu8LNGv#)U9e-Bi@UMz9@yb)MBwq{ihFW-z!IFk# z8N4q5f5DbpafWgFXRp_gN$Cb53&uMO{p2+sCGy(VsFTfK#FcymjO+%Xi8wW zPy&y2mB54WpHu>SNC}V<2vGt!=l9_fa;^kc%WbX%mNpLhs@Ru+)S@)l{MLp*Uo*7` z;D-!;mRbb;zr0r>qkrl6*#6D`oeM;JFQH9nYoh%yi84pKD7QJUB~TeX-BUj*a)@|*l=3Wn1qYNHr^Px)My)k%a>Agg>P8v&Q1F! ziv5{-?G~Hv+VJs-GC%Ra#HO)A+h}HV{l>o0Oj|(p89wT4UgJ8;Qf$U-sUy+H5kW*y z2tjO)XIbg7Riz@Ij;^bl7@Xjz${%$6cI%s6k)S;c3srWO{*=Fd(@biY)`@Scv{x=>OhW-!<>PfI;!&)8$zm` zw4pMB!Q(lbkLT=p5A0x_VV|@^*AqcRPzXWT4!suHp}QMHlo|vBMEMdCOd;wNFKrA_YM2WU<#XSeLevu^ zQMV9LM3g2`&p|{zzcECqkt0Bq*##7yB;k4@!9{Rs!u5It*BcuHml~k~aCuRgMy8(L zCgHl3;3Bv*;d&K<>otvm3&lymSWwQc3~VO(WC_>p1Q)@j3D=7eTrX=3TqsTghJ{AM z^;8MhQwT1COB1f=A-G;pH(V&BqAP=}SFay1Q#={ZkW@XLs3NK~sd_r1>RFAW3YjgS zN*2>Hg{o&ss-8(y5mlO0-G-=oO5>>t$iZ%Bp_} zVMEx2V1v^aU)LB+sv-k@6^E0G$x8_n!bB63S2P9_6eR%}RI(OQQZacMVM3T_V)DYq zV1mLPAQV>4Xp)M_%Lx<0L=%(eHU<+E#{faCvQd!%RaRa>#1Ju>#Jr&~#Gn`jNMMrV zF9V2qB@si!XcF_v#t?(z4`3)}6fv(NVu%<`VqVf1Vo*Q-ToS?iG_2)=HiAZEt~o%1f*?^i@8{I@mhII@CJMI@~(KI?_7II@&tM zI@UVQI^H_LI?+1GI@vnKI@LPOI^83SSw}T$%yw<_PQ9=?3Ru*X+|c> zqBkYHtc-6MDpv|aL5(S)SJ7KUi}W}1bTb?7L+WiZ^X#oeAQ2csU`l41vBs3C@5^o0 zM=$jrxy|}0r|0B$j&1J^Cf3JWwcMR_G|GC_%4Q1a>+!D7T z+_p##Ik#Vu+nn2b?-}?LtqFEGKMAt*duRYxfSK zhNual26gL8Pf1D`HR+9^l%U1eLZ`1?SW*{X-$f)42_Yn))ams4&?g_QrNWb+{QR|d z)00n6zUGrZQP&J6ht^HI3prc3<=70S1?DhKeE!1x5%GNy53QcT6qoNSh`CEUo6Rii zXdhf&T-G+v$;W%DCm(zs(!9&7W_WL;;G4Q7LcDKSI!kHgev^ z61bZD5ZjWUVq5ZKY)gKQU2AatuzUC5TKBd;%6sy2>Ehb*z^J%X zK}xW7syyWV63czO(_^bjMLzlXygH0Z{ir^qsuopqzN))j)c|C~(+{(FHk}__J}}>B z|Go6=Tl{&aXTQ#8|I6svzvt4K*{wS-w>M`mzF=;8TV>m2TV`ixc2>6U*uG2p!Pr(V z3vc_qVmWnvG@mWxy|991U{9EboB6j}!LBsIru?!Rsdk3aAg76$6Y!4tUc(!%nPF}- z@mhR<9nbeO7rFDAe?Xjv?G?bniG5cQpW+tG`2y~Be3x6 z?;|ZhT7ZvY>a>7OXR2DD>7*E1Kwa+zhg{w>gQNw7;t*QJQwZ_3!23xHkQRug1x`a+ z;FK6zKwaz3LFTQOL`Yg-0kyyfNDGh_h@}OVAuVur3@xCplXEQ~y-YMCa3&E8Fc$bA zX#vs#v9!Q>NDG`Jw17Qtzd+vgWAZRKtDMgj^4{trQ#LGKrU^U(tvq5TzOOmZF941J z2$z9*d6B!B{jcE-cR%pxy%rx}$MgO0VfQuvfH)7^>-h!5hxk>*r^JT5j_)!|1@JE; z&gWi+@Aj_9zSaCa;~yd|Kw2P<7HB?9)dJ1w7+Szxst{TLyn|l)gfrw|{=p@#e{g}c z0Q1Xn*Bzq`Ty4JB@CGo)31@G(uf+$v{lKgHntwo?hc8@-a9Z&pc{WD5|6_c^cNwOb z_?Hpqb1%bpdsk%NYW`Z_!=wdB3&hd_2O}-8B!(7n7ixT3AR}i4&PbqzN6n@|6D*t- zU_1hHTnqSLGwz)IfTZ^tFysfZSK%9r|^~M6Oa)Chy`;?>UoZ ze?OdC?Dt;s!@cvc1LnI@_z}_qqy=JWffJAxI5LJ7P=m7AN}&>c;zV~j>x2uY1%OZB znz`aQh5py@hPxlQ^Cwr3H>fTHt7*1v2yZ3#c(@uu_=w`30P40n3dRAT8i21W(s+ zZBmaG_!wyc(gLxxz(0@{cp!!rP{ZcHJDBq#v}vV~4MW&4fz2=gb@>u@JA0X4;4kMp zBltLJ0n!4ow7_4H7Wi`vEr4PNGfGCS6OG=?y@QR(jSpNSaHjb%&UU>zO-_R580r4Tn72v-NquqCI@1?Wfod)KxR2LTnqe{Ck$-cwR2|M+%7j|pY6(Ll$?P)iWAHha$W^>Hu`6tz-As7 zz~TcIh5&v72_?Dk*5|3g68S%0TmXn<4)XrI0;sIqK z&>_|T8gO&>1Ag9XK#m{eGUtEIKOoKnqjovcPZsf?CgO?sSj7Jd5r4lJ=||=YPS2=m zf}LtOU>Ae~cFPa|XX&q*rwFoC!T2V>Qk^EaZ=hq}V8^~K#aQEyC3DqdNw11ap`+L_&@njQW!TRX zF+@xpV$yf1#H9Z(niw_e%FZEVn7_3NkZIH!%Sbgc;A3T$ht0JL%Y0?X!68#*#mU*2 zu!FzfQDpDS>f@GWTPb!zr^r+D8eS{>i=uw`7lQKhkb&pd5s0XDcJf3u|;gfV(V)vT+APkNzoXi`xcau>>RZGWaTSZJrHHHL^>fvw#%ZwPZJlzC<+M0!ZlI$u zXe{Vp#M%?8^DOSss5ut=j^OGZ;)=M6#nriptMdg{kuey7e!(s^5QCRPlXEPQ_PnrT zLB&;3*I4j-g01foTf|lzwwlu_Tg^wrU`vg*;A{nt1sjt<6k@ZuZ{70?f)V4qaVLB& zzu*r9SKlYDh^ts!wIZ$#kHM81X2H11O0L*gklC%q*{l$*xNA@u3u^lXe(I`TmOo|mKuM-N{wcv z&z+40nFphBY=w*k`FzS73(kwHUka}7C$5OASX})HarMs_T&b}aym+S^3yP%Th4l+^ zryxwJl(C?;U+~w0t6vdU#8oV={(`vrTm4*htFad_!SeT#4;i^}-vW;AlRImT+fPB61VO!K%g4p9Dt_5J$vO9FAJP zk2w07CP!)%1m{Rb7l|>RQ;?z&Q4k^CIdzPugr3)8=r4kyKNCa5P%MUifEfCzCPQkp zLr#r$aN_eCIiBkdt~SAKk&?N~QZ;Ih<^Cr4`77~5{KVqthlrnhHThAa8n_LT(L&B_ z$SI4oaM3~l4_^~f_~8RNov4O?2!{Sn3=u=I82S-n=srz`)CdN~P^W)B zAclUY$&ebEz!~z7=N#``<7`ooPXP=O4^B|VbK3sx2L(g_C5DKhSPcCVG4$&IhTMY6 zJ!<3uEVlZiyTv?+`Lmf{JAOswH35DERvXr-MGh~ZBCN0W1N7u!Wn-aJ2fTo4%eB{u z(lF{=li~J~I3kYXaFj+>Akr5^R$A^+Ll?4Lg{-fbUgHZrtPDU2swuO6kaB4V+}f<{ za>pPbrj>=12Id`ppbuYpXqEe;*h^PcG_P~_HLnwUhQ*#?cTdZziLz6(dC8j08hdp8 zMrW(FFtWzmNEe2@*R3NHWp5(|&F$PXriV9ryIbK9uNE{r#=Tg2R9+xGn(>ZL6$!;V`}e!&;QQSrK=x60H+$*sZJjF0tHXx;TCkDz zz87rdyp1JrHTfa7B|pWsm*>$R77b zbBkq_v%L_yAeW0o(5bWN+KA<%AU6Xr)DE^tF->e2@WvY2Xqct6z$!&pky(mkmQr6- zu}a+&jFlMSsZk5O0f2vI^Y5n7qsBL|N-18aC(9ZQ zBEos-!Bqe+fC_(kRz?cn#oNs=e?o1ubEx3r5aNQkh{HwG3YCkdhs59l#VvG0l~(^` z$f?unWJffj16m+y%=SRfP8hy1hn?bYVCIMI;r*QWF||oMT#$Ackw&D&BJBc1+J%C& z`PUQbQKK93d8mOWqZ>p$p~iW}14;9{zp+h&_Z*uh4ysMsk%F`%h%_QC4r$G(3r+JW zF-TM6A7BAWR-23*>%kb$8SGV$^_+Lu>_}&tzER_Z7|#i6R@4~VKi zMusx;A;*bShi1{wU zc#m5y7K7((A`=EnPAm=r4lFq9PV9AU4o?>xo<=ZYem>8akly zkXbjl0zhM%unepgLw1v;_1)2!32GpsYM zHtQ_wY-_1?j&-heo^`&}ZmkQlf`Adro^n_diBzK61jCKBrg7hOyVTSQyIm@HJDYeT z-s13<+O6`I3bA6YsBTmbGCOmz`c#8fP%4n<6PnZ)z1Th^UXqbqVfg?zp`Txns) zek@eUn@`Pa?AI%p>LI3xsW?nEwW~}uog?g29ZabK6;KBw-zCR>(nsM`!dRHGpW>rX z8hzCAQ9M*I)kjPbQ?Zyj12J_<HE;U#=Qk@ zcaVoy0|~7k9$`^;kOwX54#G)|?hew#GKk%7A*`ZC>Ni?IvZdl&c3KI!?Y2>51$43U zr7KH38|867BM48{2*iQ020AON(c$-t&>?h0pCq-hjt>>qSf{B)3l$WY-fgS#6J5DN zXGX^D2}&C0?+c`aB?oI!GC-8jh;LpaK1|711SOHnO=5(n20}n&p1)9&fa8B@gg00X zAeid{jqsr942|$~MtHwNBfLLq0U12PQ)4Q4pHjaMP)xv*F~TcWqeCM+cl1H%1fhd% z*B`V{sT$#_Q4(F95GCPXeR3#iTo>%X5#FHg2yciep%Gr35nl5L1tpQi)x`);4R-(^ zUaqSej{l_*-f%U5Fv43!BRm@6c@3LYM}#j*mN_DtzlTP6f7Jpqc!Y-{C%RDmX~%Xo zF1sVpcCntMTHcA()#%U&k4AVAy-3jrulWaBs8o&c)K~}@;n_+ogrLM3W5hXOji!;J&d4pbRU{;NFVD155vo_(qTVU5V>kqGm#Ulv|!Xge9*72HHps)q# z=@AgNz~bguMCt-ri-PW$Y7JpQSj54iIkRfs^YH)!^s390IvFv{eOa8PlCb zOZ1sSx8P|R1bT|K$3|7RdO`r9tg0!Sg*Pxv+J+En8$zw!Q0ak*O=AV^AnCP%xUM5y z30FN_tw*T1TBl1e=h@Gq3Rg8&06IJ^zQ;^E7_?js5+4*$$TY>GX@yK%D;oz6iX(uM zS=DyVv2u;5?vn|!b5KGU8oNNkf#{9KUhB=MCI}^(QN@{2S%Zy339b2O{C$=b6c=}NN#Uh?yT3DYHg~X6E1{HEL`r1iHjOh!8^%To1Ek>HC;pi5kRp3`ff~s z)EI|sFLXDmwl|F%v)vXjX5)QdS-dL@){+vJba6G9;G=jn`6$Roq3NTz5BVtGF+Wh< zq>P*zO2POHh(%|9L*{ai?{GgWh)!zKkYm9x%xm+10}d23tHW6 z6et}5ps*(8?E}mAaazFppjpT95<-RsfpG?bsc+VYOjSHYE+8Jgah+I}1t9~4?in`V z^WNt)3eyON*h0V%FtLES&mCUn)o=#Z0b)U8y!Qqnz^fw6uWCI`nu@g^yR{l8nCon# zxem>B^yWJ0*Q2@4p~3b@K&OU7fP*{RQ$193dKE2cz?|mHAn14yo>mmmbTu9{qoEm% z{){I5<|}vZ%=n||@@k|(SFg-0vaFMf5gSwp_R2mk=85X7ABQ$i?N`AnosBu{b zr&K@j`-)nR{H65B(<2|}k+)6~kG#6@4l3CWi2h2#Gk+O9^YqNedFIpa7tg%9dfo*+ z+wAIrcoLrZ9rVo8Gau`j|A2Vr)dg?%%=aeqnSTsD^YqNedgebUo_Vy0+~c2a1`WOk zv z@xk@OP;Y4M`jHVfY3v^x9~)XxESEM6_4llp7#W%>4@?gAPmGLDttgBPjIQk;A6v0{ z)5PRZd1#_E(LXlORvefd7+t@yZ|y*_IL=PR{zCbp4dtQXzVYGVw(%l+8@j-5C{D0f z?gt=4_i!uCjxIUI!R#`&s9h6uX3bIKPPVdP!-l zT!f$HZn4YCE%u&wktOa|a*rG>tu4tT*_L;t)AHT24qbXKe3^6Cmc~j&*2{W>bkt_p zc8Zq+o!&CHrLt=;zVouZn`J%S`LXS?9qY>GFD!Th>ng-0{0#3c2T{@yg_;wL|^v83}v#y=UBgtoll0@Bp>Bj}B}( z51ZbD4oO(-P{35n?52oWJO z?S&G|AD zmCNHjxm=q(xx5w0++Ely$WKS+nNuFHZgXHq-YPn!{SyzuF#dLSsQ$5){ zEqSteIg-t9f@Gu8((Usxn=YHDd$M^(@?`T0B%9v`$VPRL^>iLM*gVq{&9jmxnpYyx z{4PK=ijQo>Hh!#phbNFblP8c@A%XlpKp={9Y{d2|n3`(zpX~|cImr{qtC2wd5FilM zD`p!%Yk96Gkh_v6kk=rA{4qcviaQKcmRz$mGkW5AoIwX)k1qeiSfZ4_`e7(pM$cvLF5MNR*i}gzXIY1z)=gWAF^%74W zFHN32-hcr4OMpC7k5@Khx(RuiCyRjJ4=$lt5wq0S2Z{h`g2 z2aNMwdAv4x@_0Uy$3Lp&p-c*4$SZ1jnmS8|QKc)7*C$UNFdkR<_-C~|)Hz|+_(?hp zVqAILojiHG5Xs|T)$&lLgpJ|MWzmB-tY zCy$pRc|2Gx4|O`2H9jH*g4bMmyfb<70Ox_9k5VrhM~x%3Cl&Hq-@)A5@NbsAQ;D$%X^b2murw*nvqDtn}mrT-te~dDyK*kSdLdmr&mT9uwz% z_IlENonqhJyAu0;&IWw6=nPh^CGf@NS6JfyAm^|{CMU!Xadxn`eFwY0Ssd*BYG+5f zI5aY_$$ialm-D(6PU3x&R{qW1@6rmN@ZMPh8}b_;G%`L=9FuR3j&EQBaL#yG5yVrN zERD+p(uLuX0r!rzju(sNjc!@nR`^Zcy=*P{-dR$1et>h%LmbK3-bLKE-P3?v@RO-J zTXR|YESjk&KJ4jJhNKbs4^n?j|LRmB&$@~0yX3jf4!k5zMMQgaTC%LhhROCjnETWpKJ~wJ@FON z6DH^hCB6gJ-WD|*W&!*YU-k6F*OI3vZbo{-?cq4>`7!MXJ>i$l0i-9sPI|%wJ)y)K zjpTflh|QdLe8bZd-%OsKxCQBn!|-?_6Qw77vN?eC#J5OK7@#L?CH`&Dm+fqN_}jNV zg>g^v6b4j@R2&tDBZXn3@Hb!aGBefpcRXo)H+j-{B9g`t)zS!GuFm;na{#ID?~(d8 zL4Bj}x6VaPhFO5=;P*W}@q^^)38*2fXze4hp6HGm=J{lE0O^SzlAbU@PpIKxroFH@|ESAU$y(=?N3`gcANX+3g$Knm!-=v8OS9l01z8 zRnV1@#nD(}sNqIkzAysQTcEPY|!uVVAgaJKD6f#al z!cZsXw()9@yYHkX~0dNjsMdV%fFH*7HAuzFmgH)i!vD> z$z>OH#<2j4l>hdG@t@=g<2gteXH*FzB9_4?ngeL<;lH%@V8YsizvC=uiA5doFMyVK zP-ux(D|uQ18cQiE`%I)IA_LofqB(H1L~9di2?Ml*;=P2p_C=liG+s-zHhWs4C3#xn zE~F*ekd}xJYnP%qfV4!4v_x{X#MZsrE7QAoUAbAA2$s8iTEg&&U~Agb7p=+D7jsBo zoaN{XPb|tru-xUFZI~{WC7xIgN}gEuBC(u}#G)?G=6r6GMQ|uCfK5Hv6UHIQ6UJ3Y z7)z^!5jsDg^o!=spi;X~{VNK?wGDj?^FjmBY9u` z-Xf^(#;=mL9^r}O$mEIRN+gbRtHhxUaG)xjT!1iB97lQLI68Uacq|gfc~#<21~x#) zqPi3pfR1B4aU7dGaqLFoIKN69iWM0&zSVW>ah^DiPo6mTAaS%i;+WpCXWN$D)4be% z)7sLwwRX~9_{>Z-b%G~|6O$*1T}Tki96?;RW3Ix@II`ikZMv2^$&<#($&<$ANE*wr zG*lCAd_-pJDV{V=O`bG%B58DBX{Z+5-!{ukO?8?ljnk7SjVq8eR$yr;27JWMOAo)9 z(m2DD#+k{J#w?P?L!>mIheBnCYBwf*b8<6<(dG%`tmFyfQY4HEurL&}F}b)d)CHJn zob3r?Y4U_|84|{YSQv`cfbp$#SDA^%Ii57mO`bG%AZcW1X>|Fev02HV9?9kw)jhNT_A}>+BA+}_Y(k>wMxqF{or+*ywop+-YNu|! zNFx3j=<&@0ke~x}y&*-NWJHr|L>a+^Q@KpelMjRneC`Rk0bVie5!kMAa?L`UG*Ar>Kgk&fR{&9Ehso;iM`OuPW5KJ=w)wuwQ^t#Ungb zu`+q8;$oyK9;&E{sOH^%!5oOHVt`ad;#Gx`OgxfZTz~%psER>PRTPq^Djtng#lsX; z5!JujFPH;SRTN28BwkghQGnUSjmca9RWanLis9s`iV9K{{ferHXyHBS7tDdEDprxI zNW7{*F{+DO`FjCW#cEGgl#-_^E+`=HfC}zmAm-ef` z5`{{A{9h;pG`N1audlB#GBCQfe|)TMLwRVpZ+v*Ttu$6HvhbVI7#z_yT3TCjw)kGl zI^0V0Gw`cet&?T;wzHAuCxybItz#bItLwy4io5l)l!|W!*as9>8#K7RlP;rIxcE9s>X$%fv|FrSXl*&V^D&z1EtGdKb z2Y*>S6n~wWcZH<~;lCFzC8I|)LSt7f*%ZC2*)WjilT>~+Gdu3bMe!qjK~*!bAc ziekC6VW_`n#l*sDEN)d}@U-y(?C4nwT6a4^5ON`o{*^m>z^*&F%C!7!RJ_ z+nJUV$Y zfXR+x(}s6$*)vyR6%uByxN`0q9}VS2?k}+bG{7RMD~U^zCyBL46054K6PEM7(Y2W{ zfJfOC!Pex7U>u2H_13++_xLSB+59TDkVEVWU^;mM08go+jY=aMM(oODc~yl?>na-t zMoN{^SY`K)Jv(Ooqa2XSqK3CGfNp|{9IjlpCr>V;NG^{Y9vb3eDG!Yd4NMGGVAkR@ z6_cGg=>=E>J+%N6QK)g|isQ26iDLwbV@-fK!Y87B;T#~16L!#yG>NNm?6G8ud$=@K znpizltX30?I=@-~H31dITs3id^3()`7AV$qBuE}ndO}L)0MQdWNlzqMPgJJLrOE2S zgz;W&s3q)biP_|7iAN$WF)Fl#ltzS(@X6)?(Gj~yMa#ciG}Zcm;ppt`W4q8_En zLYa0?b}eq-k_C{(lRa5HC3&*wMzYwf%0iiTPj(q^E}rVi;%Ui~MGun2MXD^+X?Lgb zvUs{Di)SQH7Esn$(NPzxvQVepxlWnpXy!2LnVu}3l{{JWAz3_Hm4!0x9_j2gT^4tE zvbZyOvUn(xMMaf`I_y9xOH^4X({A9x^fB#oJz3n9JX!Q3 zS!_{dp-j66?M~BW@jOo!&rhB#9*$(ORh5M@?FKik=}Sp3@MQ7AW1r)7T6x0qy6zYUK?+fNO(-HMLPZY0Do+yTqC?2DT zLYZ%u?QYZOcyI7Tad+}Wu?mUeazzx%bQ?xcrkm|IdZKt!@~chuZMjsHi58uxRd#_F;eMW~zMV|Oy=i=$gacHi!?`;O$X+m6`X6?_{* z@l|fBx%j@5@ZHb&Zr`zems5YsDUs~dLk8<$`bhL$9{%r69{%Se{IBF<*gZWn>sOpT zou&)nJ)RKWn>-<$hlKE0E`;eVb6Z$(Mx6L-cbh&Tc%LVX_a{#ntwaX!J$RF}#@!{mj;vgi8IV1~pIn>|Bz)ZjDM?7JCGJy$YKAAjW9EyZ-H4=up zD4NYkcb=JQ>QkODKAk*a9EODPI3x^pSu|&Skl$xKVSF}u!Z;iW;~FFkbzwB?tD$cu z8K3in@%iKl;|L^-$0K1VOQVCvXRds~lf@U4CyOJIEUrbeP}W8vGv4$m-kEOom3FGU@6UH$}82gYgl=(Nb z5HWqq_YF@N-%Oq`jzz+_0SQBye?u0q>B9JyCyZ|=PZ-A`Vcdv>q0Ya}Pj|e>6UKLv zCye8fFm6J^Q0Lz{<3sho>j~p~$rHv2NEkOGVJP!&NO&~eGxdE>7(Ym!Fiu3mxCIFV z&A&6IPcwe#3FAk}6UIqM7*9aLQ0Cu2hUr7wdp%*?mpoydjD+z-Bn)K&4&~5HA5Hz( z6UI-HCyY~&FrI{jp-jLb8Q63+^;1t6KTDo4PDR4FRTT!#1~%P(|J;+sFOnyV(~vA~ zQ)QvdzabsibT01qWbw=7$>MY*i`!LMDAVteF5`<0{mPTYuahT>GmtEvtja=}eM3U9 z>Bjpvo-BTwJXxHHWbqVL7V6~NHa_?9cb+VMpFCN#Az3_Cm4!0*hLm8_?ZqEFS^P11 zvN#LL;%TZZ)TwvQc;ER0o-F>9JXxHLWbt%W7Rt;Ul7dYi)Bf3$#b1&qi={{w&roHd zOuQj0*mT?dS5FpyOP(ywL9%$}-0mHhZdP&V@&ykrVhY>ez5Di$%K79!%biYeqNj+2Y29XP5eKqp{hgODxJR-Ot&jyQeGLc3$oW)Spc03NKLHlnB6mX zA=}Dj;cdQk<@A-6-CM4xWZ3`l8*U8^mf8O*h6ou*qy$BRRKYl~~A?5;J% zHu0jbudgss94f$@m8t&B)=b7;v1+2+Uo1@w42}#HS4@?Pe0PTbXRjC?8m)}1EmVd} zBSZb-%UrPY%589-sZ77U0{+*|3^Uu+s2|9Jlmban!kMOJidLqeFd}CU~O-ZdK?JwtIxl zk2pTy95z2m3huOXmJ&Jt!CT>$=22&TR_*b=~5iY{cby#6h`;gL=h5d45o!RNQ-6vLn8d5Z!prkxJl+ z-1}X!ov$5ujC;FFw)3q6k8$sI$&UEa?#(XQ5#PtX*CpF|NCL0r-s+O=JR^a}xOci_ zJC8` z$O=igyas+}Aqf}Pz+;3YTv`K<5t7J;OCl>Ikqwsw|LGu!@L!%2l5k-T`ZhTsiCnlO zazYZha7pBZBythoM@S+UE{U9wLc(Ab1AeGhNk#;2@-IZF@@ zosJOLs4VnXcRE5~L$>f^93imrT=+3U2<3=tIXJMfQTTZT4&{hz2^`AdH@Q>bP!4}c zI|UA9=ROBX!g(l)rSM0zOW;tBI7Z-54u6ch1P1jmF+pvTcla7?%edK|3;$ArtE#{mJ32^WGZrc(H?>UBVXvxG~b z*8u^J2^T}J0|FcqE{9%6E5R}0g6MTffMX)Qvyeo@V7pgHB4V)JDGM`g5OqgL=Yi0Z-+C-7N-chVa^OY@`&13 zsd>|#xpm}KYTop0&6}RBdDF8sZ@M$17T+}Jrq}$j&U9LwBIu?&lj+DKYTk5bA{}{- znoqhjiH-t^9zk4IHE(*&i#U_t zsEasL-^e3sKIzW1H}V`cpLBQ58#Rn_=e&`J@H-MY7<1>mk!RsI-aAW>HLYnI+$nF= zW!x!m5syBk_U(7(yU}N=jI}<``nJpBkbJV_|$!F$5nD-@crfwNZqG)9El;P z=3Li(YRCN*a%%oS)_rQnYZh{9u7T@5wc~6HIW-5M?o&HHy5Lh!akou9r@op|6D7u} zx}o8xjuPWk-OTV)M~QK&Ze;kWqr^DH)o$JQI#P^v)5yQIqx?dikh*E)r*?E-$f@h5 zk)PU8eIci=n?`1XfrZgUyhq9`+UBtQ_!$pOv%S@UwFE z8huvB)7S8`a+n)_R?cz#XAPpESmH*n!6zN(=5B@WY27<(S3=`hH`|cG&z{o2Z#d2$ z{dt@$>XCYogfbtAqRS2g-4gDmWblktIr{>dP{KH_9tUFn|;>Lx^-jO!Eqlestr z*&P;fJHLlE5+`ScLjS3?qn}#N(>%@=2^4=e^iP&`PZoUFoK+J2v)PeEIV&pjI9nuA zP9Wnv&KAj(vr;pUvqeIc<511xY>`wsD?sx&n~PPjVVUPw%eo>BJ{jj-|C?naB+7z> z7^C&fVORq(82u{QBuyD%?(BwTljOQ7n*o&JEGzIPx;L7# zNrLW<6ZHa*7-f_A{P}`+$|j*~k|1g*n}kn(gKmuzE0cni$MB$dCt8Lb6UE>%&AM}nvhQawhd<9FyNd|sn$|iAY(Xg5(&OPI|Rot_n zP)xp#Bn}9=?UYTz%lmk@l(I=!IUVnIP&SEjJ1Cn(rG=ZBDD^_wBWRuMI-1EsMneVyhkxeq+ zQ%9vClsVU4#L9e69hHVq=K7%SQ%9vC{6Bl|9&c4uwU4iT$oqv%&AcUMhUSgCx7U=* zQ7PmgXlP0&MO2hT1tc>wLo+L1B~!C96}wp~`j)9F`TD9AWSN*yTA6_vnIYZGioJf% zGoCTlnrolUJ{SG`KHooBpO5arGshfrj4{W&t~uA4X#Gf^MYp8Gv$^TUU3pJsa^<96FC_oJbDN}FrTcW7I-^qX3KN$`jB(ah4tn(Nw;S9<~B*U!df<`hTA0F3hUKvlJ2Fo zY*5wPB;5+@)oqe)rS0!o1|^$xJ@#s=YqQV+ax&Ip5s~nw@KFD zCTVhPI<6$FzfH3KHc5-mB@eb26ujQj;tGtd`^dBIk0B4X^%i-w57O{vKv!vO^+X{2iN~?k|tfJCQR^7i)&$; z29amoZDRf3CRzWtNxJ;qF}>|w|F=oHyd<@5d;M*aG3);}N%PQH|F=ojeF;E=M_0?=~gJ4kgz*_olspQcdCXU86=cyi9YtCcq!QyaSbDrv< zwdOq4Q)>-N#`U*J8v90h#2nk|*sxx$1xLdo+hnZ2O;R~XyZ&#JRNSFubi_}yR=NH* zNyTC7ZDw^VDt^}ACTVb3w|%<)W@q@cS)Xp>b}%$+wCit^RGq&5Hc6!uTYsCR zS)*Bho22=T{q?s=nnjEL0%x%>YRXbw7d2(6E{oRncQ~r&;(KvCq1U%bdMmp(w@G>{ zyEnH{y45v=hT9~)72WC@Lc?v6-imH@4WZ#SNpD5Bx`xnjo20j*TV6xx zbF1m?ZIWJSZK7LMW5aEd-imHjjSaU+dMmnBH8$KP>8 z;x{5DB1B=_<*NiQV-zjK?UTc!JSo80VkdZj*E?tT(qwx);`>M!Vc5fwb3h zo21{Sr%pe0X6MwIGp0?QJ@Z`54QI`^ODMwziB4~h47OV$S^KDo{I7H3&|#x-X4P+w zWG^1oF{b^XIHfosh=UF~Xkz=M_G6fO$jC{@j~~7F=t*PRN8_KJlMfkm@}NP3_da6M z#6!l6oiuXPxb`u7PaZqQ;6e5b-utNbqdLb;7~OgJ*m3QLP+O>W%G7;loIUlR(UT?* zI%F{9O&*Lt27;d<_A_yiegsY=IC0W3`2VPOvX5#XZ2uo({~wC~^L#Fnc?1_f{MfaA zD1e`=*3VG=fO9~Gzwq(~S|pEb9LDOO8;+U4jcolRt7$3I@P@?BDB98=N6WPr(~QF| zYl1^-@rJ!Q9fda`Ji;z1=~OO0d_Q=QGj$BnLbExO6^6fI;eR}!Ig`yr$fU(zb0+Iw z$<%cjSL)>V1v-Z4?0s`dHnr#9)o5j%-xyf`w?4G_(KJlf-_97K5NhTf{fRx^Vpw-W z(_hXb&$>@fYSKxbb=QRElH^(UJsC|A$+PY|0qg(P$5{WfJgwHjliR6Pg5QntTzCUPwJX7 z+0@9G);(yAu&I$Tt$WlOVY`RMwC-U`hg16DZzHZVfJW#xCI1k&@id#z>Y(nJvFmo? z`r8@nuBr96Ga64I+Zt&7?Tq!eGuGeEC~sBR5K|obX;@h6%>Me@8U9yJ8irPRr`ziY zgU!XQ4!7!a2rW5m0B_0B?Gf6+HlDVW(d|jz^|v!B$4<4bZspSTw=*gZTYo#F;*Mdq zP-qoD>u+aN&%Jls53awR(crLd`}Fm)(*ku==%$MYp51 z7QZ2)+1x~b=CUP6x3ic1yPdu4Z#xhzOR-j4Ofs9QYSWk2EZPr<3&2gKbbmhG|Gs5N zY3BKEEAIfkj0+jfG&w+T<65$q?^~LDKy`NBv>@|-Ybo8kUw_@QwUqANe?a%{KcIR& zpqcyE-_B@O&;S45&e*-1*Zn=ciP0lDJ-BtzBRSeDT-U7=Yfe3qqfOcElJ9iISx4-& zT6^k|7`;YZhZyVfdL*XR@p|2o=#dz07Oq1ZYr8!X)9To~Za?%$Ov@wk*28uuriZs0 zdL*Wmi*1&Z#rb?3`+EOPU#vS1FUJ_GV|#m_gQA zC-~X0bWbl##5p4J?%Je_Kjoy^Cv~1Y=hRcDoqK{GTW&7FW;oqR@S~N@6y`A`D)F{% zlxTU_bL?PKqgxrR^{|;(w=#ybINdx}yL{csXmMT-{;;`Rw=!CtyTsR0d*strr!Da{ z)gH-cb;c53TkVmIRtJ{xHP#-O#!ep*@Q9p)LD#oo4UOqeELpx(A_8=E?HWQl^qtHU9z+q96M}a>XN0^XxL#R zQI{;OhQE%c!8xQwQ;WM--L3wc{nehVh86rEyInP5+_&?h3$aDM|F-F``$x_?hU$Qg3&{ao|Mu<(tiw1|Iyh#p4Y4n z(a#uV9nusX+6_24hv7=G+u@fh@k3Z&+1C4t^=P?t<9@ROaW85K!kAzdlAK@xB z!UtKIliJ7eK3CAZ;$`%hu@i%wbWHn%pvQG!Q@H&I{&U>8$s^y>&Z}$qmu`}^k2nA0 z-=Zd!6mN?;h#O;B)|TEB+sG@^?}laC%-edm-5uXOu18s)_68I();5QlaM&zn18^KZ zDo)!r3el`(BUg5vTqeo6Casgp2J?;GGHr?CO;491tpg7>ZFx3hv(AUwcT8Aki8dA* z&$_j;?qx&DnY3=5tV0pgx;3&cs@WJEDAen@Ns;FBqDbv}H(@iMZyZ5yWj5h5ue&g`hjp=;<2N^9-c;7b zY2M#p(lKL39ltIX^ZjN?Lt7W4)j&VA!6pp$hTYmtytl4er=xwGD@1xVFqK{r(2T*V zq?H5U zWwo*695Xtv-@h!Y?Knf2=)C^duVl6D=L!>@*Z=WAR@>jo%${0Jt@I9a4eO#k@7B{pYXxSl((dRf^Fj16$!SfrL5Bxph+dj+2UWqb$Kg1J{fsaU3PIS)n!-Z z{bXtz+92h9GL^TRu*)|~^n1JHU6#t*U06ll-dVQu^Jwc|Px7Kti7ia)XgK;u)X}nU zC43`?u0!~UJ{O%OKx`~*ANu~!moB7K0o7be&w$5MHx z3EQzf;X6OiJJ8w&Jf2`5&hx_-WwnFz1iL_dXT6kQ7v}lu6%B3cqj~<^v3b7s)r9XN z@l~*okuS@3d^q8|SlA9@6YS&6n`ISjp0J7?mpGQnyHvVV`iM`+_Z93i*ZG2^+)pZA z)~49y%-f*zrzEe!_i4vcAACmg>S;T_f>?uX|E;!F@fBjUeh$h_>+LG>RpiZ=pDWmB zrAr0FxX-pw=_jvuU4EGO;0vmcJ${{FUz869PED{cNxvP^yf>&_*5@XCUsf3vc{fVl z9-Rr_P2#JRakFF3C465OR%svKaQ#xgTZN6fI?4M@$F@x{^f#=J3g35yRpRs><*nFz zuVZQK-Y2Y5Z{L%=ioN%H{idnGfu*zv!4eG%}ZZcMO; z^7?1D&FiNfn_&N^yr&d8eoS z3+6m5WA@A>?_$T&{$+{eRrr1^zB#LsypOTJ!X#r>g8fACcjxg5_EYu673^{GRr=?j z3A-bm3p^pLGEOfQRvEXRR2dcQ=dANQzxmNbm!}vT4P)Li$y=1#v0Qm8@_r$#qTert zEf}4Yfi(onxIgWOo)KRK`<2SA#M-ZAM`axRjq|1P_pGqWT;;dID)v4ntTN{PPFQ75 zgYksper2w*((|Ts5X=|o)8*-y{CnwK@!t!=D)sh$^vmC9I{&K>`#GAev8 zN?yhHSTlX9hPq7izU0_5NqziT^N5PP)sk1q`?7SY^v`RAtw>|&FTz$nl$7yT=Q|?7 z{^q_)=S_bXUuE2SRc))%Z>$wIe&#$LAJjJRyt^iR8)n(T;7!|a4RdPD_39tr zDB;`K#;r=9Q`^M)x=Mdl!6}&!8v9{=eG;1_-}V%Y1^v3Ls;6^)ds4J zbnQ~xL%LM>_7wI&GJmPPQ&`%E)%KFSO1ZwqspQ>9e3g3JSMt*SsH}*l=1u#*8up*K-m36nuY`ORJ4Ohr)FswiTo0z>LJjLJ!_rto-^_YT z`|;XAvNv5b)ee>}72jhG#=PnJympxJ)zi63ZH)SZ3U;LU(s@n|8yW03D%eq3HV<=? zO208a%jO)|z=!QZ>=o40`Acm=mVNfvhCb|Q$-DUSq|IRej(IC(OmZxlztoPAyereb z6Kf;tQjv$v9LlTkO?E7q>(!2vysOea`*_K#VDGcM)w(=Edl{AbJ<DXO+zpzR?cdCpE_5m*=jhB-Y2kBb8cCzH9dl|K`oU}X_sfnj&uyIohe_XbEz6O%@BW;J(=1E-KSe8@p6`YRVibp%1Fof z+Sy)4G7qa^eaL;O6-OlU&Xv3hHcMDV-fYLxzIcwxsQC0el~M5@HvhPnR_P-?B&_25 z^MzIVoDa*VmHz$$l~L*IKBBx8z6*s_V&kLIIbCzsuzyeAr*o;=#~e%MX0?l@ONH;_ z!YXw+Pgtdl%hdKOeZ;5L1}oT=;;ZySSBtNL;Uxz5Uv~X*QkU0oepTI*sa-`ys^Bayzu}Xy^p=1?7V*`*cbEqD#ZRh7bn=4981f+LD-|) zCwyP#`VH?Oh9=mJd3_%Ib>4*uhV}jhh|7-K6YOTJ=U&OOC-+OR1;Uozm0(!=lJALR z{agEr^QGl}HP1J^w1Mwy@?zO(l`^oWK>yv7+KW8}V)v$YU{ArY)PHCjlvnYy z@7?cvT4KlT=D*rDsm^x@8<4EeYYQDq*3-2+^ZH{)Wwi?5U3q;P)*zL6)Boi8wp%w~ z-{#sN%T9kj(d9dewPWr}u)AePr9Qr!*LNP6W$FG)?H*z2-c9Y^yuRi2SvK&wMBaUQ zeXqN-Y~*zb_C3sHbV)N73#eT^&yqLTpZPVBX}eykJhk z_EEvGUqZf0oMOL(d=*`=U-H>)8{!oEB_=P8)5n}IZPPyyR*7fqmvFzc5*thNwZB{4 z5YNlx=Xq&eJ}tg^X@Bq==S#6?W!v<$F0p^W{$PCC&ar<$T~0{-hy4R$mDs?%k?~yV zOR#@HzK*m$Z2thU`$`f+zgHht=}%t}R_RawAgt1dtx{iC@zo#Y`wI4=wbg1L`zN)T zbWgDMlCX+xf0nN*`mGjL(eGu&X{B7etF-pfnb`Z6y#Dkv4fXq1m0R)i-z2Y6N7z5u z?dB}2l=}~1mGJ}bO*wv4^8Qn?c1EfT_8zE9CGWqa%k;G0_&45}Vy;-p`ybg>DPyhT zufkWCyb6X_6_l6eZNp1c`YPpXt4UskuT6ZZpWFILUIlwYUe7jbC}RVcm)O>}q4TBK zM)}$`nCn!^-B?&fzfF|4f^90kQAxknwwZKJ_qf|Omo62)Eo4W9Z%fHbW3sKkrDY6I-V=XVwzsyo%ia^mCfFY0OZ%p_y`|rTy%N4b;+xW*V8bLY zZL4huxV&V{Yx^(BOZ(HdL(~tY{e9cJ)OS|O#hjJvigbUs?X$iQaz&!cHQHlL_b1yh zC*=Gf9pl?DUn5qDXMbmt_SwbxhGg#3_G=v5n3CtOemW`lSz=kX+pGk8PJG{3lVB@^ z-S$#~JumE=s}t-6VapCouvNq`9xY0+7sa>svIKic*v}44u$P7X{NM!pi?CNx|NV^^ z=14P3zJBOSi0yt(f}!6aw(Fb(LmxrEEIlN_Hp9OET|6|BV5r9fhBsilO5XKT629H? z{M;8C_;wfH4aX;Z1BIR2Kf(4CcHU+QwwJKkTO`;%dH&wx8_L)(&u9I$0UMm>#~$5) z4bAHvAIa;xeaPZpRsNG?ywCsUMnm{ z+1$#NPa{3jC{6T|{^FBQt9%6pc}uQvKJ#emUyg2<{<|F0 z3(E`t2A?q1+q?~+^B|^?Pj+19cJS9QPp2IP2AaCkUg=!QAzxsOjjMLSmMV@6T=Ol- z+xf>lcBO4r{_=_RNF&C)-<+hhh2Aciz7YKYUmNh35A!lT(!$SA+>BR?h}Y%&kP9^Y zv<&S<$GIG{^hhiDmhUOP<#_#Kc@w?@gS_R~rlGv$W(Vk$FEGS7b$R4Xr7n-)_0%#9 zJ$4k#^;0@9OH;W~@p-hdu=n$5gS1yi%Op?fz%0!%(6pC)VOz>q zVB~|n#^<(G_!{i}8v4f2y7_lomjOOf%X@+5D#W1-94mz28PjW#EKL~m4u2Kf&(~tB8QZ1w!C|*>+gV%E2j`AidZd+k&p1it&U{H2 zWuNtu$~`MElsl7{rHPNR@#0f>?e|^GE$|wN<*r@~`Wd|nTw{Gsq(@qr_n)hAR1N)B z{Q_anLE*KqLq`!EvvgpVR?WNmfif@4WnR95Tx(-8XiHbQfiVtPN6+CkZq(6p2ZMf? z?1K$o_zmg-qz@m)R4^W2WtzN9WIu_}erBlCB9%;r4`64zXM|=fF zKIm+Gu5*RYv8W^ZS@S>Y%K04ah;niEF4+J0bGUl*v1 zwNbxmT{=en7zganBMu%xpS~7(*^ftFrK=wgEd0Fmrqa(#Z(5RKF4TB{qM4)Zgax0Q+5Ovc0BT?(vC+k4`8h6sHy5h z>C9WkOW46VVc5a>4fW%kCgNV{z$`85S8bvG?y}taWYCB|9bFZl(wUcOjzJD>V;Nyb zT1H@Om*iu+EU=_q21ehLk3KChs~h<~u!v{IL&PNgyk-i0#ozE1)8*#^qu(Ike2VyB ze^v3RW2}$2EoYm+tBI-NV?VIRuNlw$b5=A`+eW)XKgJVnqhG={rPF^UMqT&l zlpT9?N?vM5V9Y~%DKG3zPwNP&zP6bN%RF zlwrPid8y6=lQIt34171?DDib=-ceZnGw-OY9kX;`kXvA+w{^a4oA5bCJ6Hzwj54Sz z%b*=0PwBFwz`)1;o_x`-k&j~(WdugO7(>)K;)OPmPid|n`G}EkY^ig>7Z~{1ACNEF zekw08>cH5benlKuj7h)1tPg=5*1z}|mBx735$&9PO0;wKT`xb&yye)VbYPYyJB&u# zH@=e`Gda#Dto{ug)j1ZgW^cl_)Cp+AXh-#%E(d)#UkmZqF-wm$Va$6ZUhgmZd|n^F ztFT31N0|7Eg};tjdZbnJQs>A^olien zI-jn&quF#iFV~#R%Qa`@RXW#OCB|~O=A_(Mb8?L0nv-KxvA(o)m0Muoy94c=XGbc}i!WSYlB}oI{46IUi!VoDW4AN(W|Xr5%e92efyQ#{qr*z^k&O zz`QP5ew0BSSO)crGL$a;3JiR#5AucYQ@#QN--6NNTQIt-y@AnQ)*J1KdZSJELucB1 z|EtQYblDqN`bH)|}7vSd!s*1+g4!InQf3dM|-2r zl&7@PFYNCxf4bE9@)x9wuDgg&>EN?8$4H|;FurG+@HrNK;eKZHCEO#W9o+8>ot3Wr z)4-@J{X#p!FR2}YF^;*WWBkSXjsD}BPHAp0_*QsZSmAvv`Bokwz5)Z^N*{YxKIC~5 zz5=5>=0&+Hj_Ar4*dvTn^amEFdy20Tr;gEA+~1&1u|B8%+-G1Jv8SMP>Fk)zPdUfL z=Oyan-)d#poQ!i!&P$HE(J@O0hWSKbF+b(pCg!J1AHTEmj^EkyTDtNU82K>QV;M28 zlMc@3^FJ$ZSMeR?b6}MxK4JE50&~JFJLu_{BY}QFb0Z${*L_SE}4 z(*ak=Oh5cGXQW4(V_45#ySwQCGgZr5*7OH?>2U z>X&OA)^E)D5sNklrp__nRl4jcFw;S{soanwzQC+5F%DW?`kW!PP2;8Xr);Y?n|oJn zQ@LfG^F6S1wm!$^jOcTG?r43IrSm;;I-k4>@yzlgo~a+}i24=vVd=mujb0YbxF=u4 zz2rn%$;WvF`C`tH+8Y?-o@)rE#r%)uaUHW(!(LuixG|pL2USQOV z{-DnCi)>;)5NRwUbf!I_Gt*ff^G3Om9%;-=n*9LzqCX%XV<*zcN4+?|rp}sYgLWT9 z8u_RT&k9jSoX?>g+Qc#n+dMteA}`N4uq~>u1C3bWI+blz>(w$n(jqVGjd{ZdOsDP4 z8$O8iNQ=BTpr2$~v>B$eO)+n@tw@hF<~2Eg_cHKnnClQ}#LSnFXMXnfTk*4F%)`27 zxl!jVm;Q(}D+7G&L&#V3Ypy@}qJLpK;&}`9QE~o&eHiDq?89PRt912E1x7ya$78Kl z;q$(oWpEwJwixSBwpFeh*;ZqXsC2c}IH$#UdE#cplJrxoE!#)2#$P^+HKsGx0;5ma z_UO}SgK3NlQ$KF+v7uk=3sAq8vDTn|IwL3jx&Ba^%7uQIW1 z8R^iez#=c_#gUhDU*_f9QG2hNXX)&h ze32e$k(XJ<^DUuc(ve zr*_8Ae1)@v#k@VzsdLQbjb0_&G(VMXloM%D#;3NE?pNMI1T<{B66-A5#$Ur=2h$^s zSlC8?hi&vZZPN8*%bG=cq(xqqOWmVf>c#SCTa+8=k;c46-{^e!HO%Ei8Zqj6)y}em zzlJ4t1V%fk3-t_Ls4LTHNAN{@q){I7TE783y5;~~w4LenOYqSzloM&>Gdt0zn-8pS*O^}WDALFm{$pPo z{$pRf40Cw)#r)+H>5)c^dT}q1I%`i*Hif+f20rf7kx%<|;-k)#5g2vhoPl=7oPp_F z6EJVA4I(|#s7u(vw6KHe9AB6>#+gWuv@|cr=E%!&m$q|E4j)8%q%kk$a6Dxh8dpKP z4v`jo94E;a<0bjRR|N)noL7-A=2t0SV6^w2t5v7kt5UskKZmcn;eb&-6>A zF)wxIS?tL#V{dQ_5!uVVK-#N4!7`op24?!7BwgYReb^ppA&+~8l&8JJs=UBL7wQ@3 z!l^6MX-DuydZe)o($tH5pKAj?NRKp@!MvOkp88R=4}9K*57XHmnK#;H zq(@rtalTHzn75~81Qz5&%t zQ8x99GE)5t4EC~JkT2Q?`HC1v8XxMyHqE+}6is z$-H52q(>UdKwg{6bIup@anAcV7v-E#=L$3@WO}5fc{vx2yqxDS59e!t~5Qo%{R+#&WZBFt*_gb9P>?GH_lPpSl3{9{xIJ>A)1J+H6Aow9o`Hop3*4t@pz*mV9n zX6e8zE#ZTojZeOEInL)8%lO~^z#!w%FP3>9-ClVgm2IA`yn!+Ar@xMKDEK_f{GrNw z6V?S+;d-7v`{9_S^SlbvgfTDbw?6L!Mg7+2eGv48z~I~SE)<{Afmxbico&mp@7^8n zNby;xj=O|ia6GU41DnNP$1I)iQcH~W_LDvH`YS)fCqC{rzWOV_=4VELy~1C|EFGAo zm3&L@65mpl>vF_bV94{t-Qs&9%1GoD82FaLS1fm_`$c-WJYm)rpmV+<&c(aV`G#j& z8U9HV*{gK$S(-4~ix{#P_ZYG`MhxkbCW;|XSDboW73Fr|ec{sokvzsOeBhr*am>;c zyY2&(fwrp8rihR2>|U0Oc65)oU()wpD873y?8;YQN70Lt90oc?Gkxwdprx@|17KR3m>9iWBu3mJw2itkv>u@>FhcSb8 zL>Z60gZ;Fy$A%&g*!p;}_r*fo=(s32u(u6TD&Wc-JKTmDxIR9*U{j9U6D{o+tcgu5e zW_GINZF!NMSN2cuIA-biM1ZB0<>D-HeXsv6&Jx%6!dNi!I(_zIB+=Hp&R!vkdxPpKnrLrK^n8_q1*PpG*Db z!=8IEuhVCqlvn9I|6Gi#HebTH>Ysip%b*X;Mvb+~1I*<4e6k`hFvzAn^7)wTda2wP zr=!nadQ;IK*k|+HfArZ(=XuNmt9$!c`@0_%WB1zMJ!NCJe{#y~@bui%WLvZ? zw%KS~Y}515hp|o1yH0#cSDSXsYXy`>tg;W_>33Bu{+Shp??$S&lI_rlY@N zY)tpQiLo&q?^l#&W!SuQJmymR)Rkk&oOS$N!sye0{HHb&aBrCjF;4} zL+w0Qy2=fVWek5sWyJkjmccu`N;7%Z4{^P~b&9VCZN0rZSHRjO~bXft?U@qdq5j z%*%0_pY4e;S?QXC1Qz-+)}xLX@2n%Xg{UK?t1T25_*h5ei~30U0;7JMZ*VRWzUO#F z|MAm&;VY$UEDMZnls;g85caY^*n@KmOOw4(M^AsJEaT~iRE9p6CO)O(vt^bhjQXLi zns2?W+8hpT)%@q}($nR?z-R~i4cZa?Mrwy+Hb3Rw$Zj7l{G9KG*x{asKFMafcsejk za||^19>^Da50WFkh@tQS<3Ie&{RQgB_7VCiUF|5a$jfmg@^WlC1HR|@aYmGFMGo_Fof4=VDm{rM55 zvwv>R@_KsiX_6P^GM1uT#uI(TSPQ=>U9lEel*=*C^V)a>U)gx%ez7qR2wkW%X z^B4+U*5H%eQEzK7*3&QgT%XESIxtIf3^ePPeBslSFEHxD`k*camgwS`&706?ucZvX z3u@)z9;uZv3T+O10G^Itljp_$x5P-zd%rElqx* zUX(|jLtd(LV5Xmcb}(#Xe*t+G!-1K9VF&BC(Anz7eSfulKpo&K`B`;T^|LVf4f4#V z%IiLNpE^eUXa_%MS?HYT7e0u3V>=1oGuBw=jJ42N>5BUTBOi1&KG(0p7Z~{Hd-8=Y zDPQQq{+WFQ`><%|X&)9CeZ_v<`crR%Y2TFgV?6ac@rTmy#2UOlh1#}mgYUQQfqe4eg&am?Bb z_PwoKpQD>>%(KleKBx9{l^Yn#Mc%cn1J7&yWytX)1QaJcs_kxdu_iFy4d><8o2bO#|Gi&mGu}APBCQUznay0nVerd;qM8Etz$y<9_ z@Yx+Plb4?t@^BXGU*h}Op(P*Ayc^%5f0cZ{*jIc%Ke*&8^xL=Od;UoAy>dm#SJcOm z!Ix!wzMp*9hn^XHw#SWfnU?UKBEH?vX~K6($%i)NpFb`6iuxTCe6ZI(r-~RnB>3!% zzwG^+VfiClWVHuz&Ox6^6^6Zx+P!Phjx0^sVe`dzfPFeu7~`3IN;AxCx)h%(roGqW zKgEIV`Ffi2UT}ou=@YBMqFkjJW_fNjKV!e}c*ATAz<#2qm3&ivpmNXcU-Ds$GQKI; zSA{M{&$T$fdJ5xm=!dnWr{TRq)x^ z?PU*5;qam;4Q=0fbkNGq2 zfavqIRe4Gi_BHg4~n2-zV)pd4|#T{5qre?uqq$V zp*Hey9HtM>!kmP5Ig)YRreN?creH8Mr=iF6Z zqyH$cu|9}-y%l9}kF&8Z>F3ElH;cMt-e%=CV@uq}v1-$OoPS#8wi(G~+UKG!oa<8yn6WhevKg@x`Z zR_JNq@;smRAM#5lVj0dwP5V#iWC*Y$McEOvAvH<35pBjPr(3APvd!K_6 zHs%GLue}dz;@ZZ{8#I20C798`4oWbi^ZKvQCTs7qyd`aVR$aw7gVOvmW=Od5N{_>tqtQ5&pW=bSxt z#+jYdPa(GHkb?)0IC$u=gNF|~ciOCJvpY|jal#PJyf+z_)!Oj;UkIh!@TDvCvIC|Z zZR-P|8D5m&Fj#HCQ{yI0bcdh;Q%Y!|L(i1ZowoS`x0lejxo3fW zz88}szpMR;;i*~o2pc#(;k#G+MFU?*u>16`Y~&3I_C38rtdw!T_(pG+@Zmci+)J#K zu}Ih+D-yo=6H}8$M)cGII&juqd*Z*Ygqs@KHD(#;rKykN&bbt%w)3SyqXW`1??6$~t^i@8RZd zR6xaFl1WN!J65gf&g%<@wE1q_Jr5V2Y`fAo&&HPe7Jpmj>IA!n?#0H|j}z<$-`M(P zDee|Q)9)&r+4faM`MhUGMJ=>_!z*TWnem%~#^+^5ZwdpxIwmsq+YDO;-{MlY)S}k&h5H=FYCi(a#Sp<_NV8D|?+*Gbu3e?J+}q1E+gl~Z*ml0bF{7iq7B>4gW=DPY^MxHwM;G2z-e_A= zN%rXNqFWbVML)O0^n)Gh>bvsofhh^FB@3G=P_h? z5Leb47g)k~9%ctD*W}HMUR&5rpOjy2LhtDHTNfQYx%lSI5Z}C6C7gEscB9|;o;?88}h+YXKyo!3|Ii=$YN3lp8!S)Vi2w>u3x%$}}%Cm$t@c}~VL zR{27h>IU-m&T88~>U>7$^&buccAqfO@U!{5%C`bnA9nhsFwtIDUT+o5>n+M%jWYIe z{Y1kDc$Kv0UnNg8;>F^oTJCRe%W7NiB}{Z)XIcFpEOqJspmd42@^bTCQO`RrGCrsC z{CsR7?|7{+(Ru!}-vC3qWsC>?&Z~gom=&L(FJ4(&;tTp#lyTh~9dr8Y z@b{u~ga!Q-yu$eI--HEy#~oSiKF5NN_#$V>zV8dj`>gT?9kEF?u!v#W7WSeqs~veV zx$<1Jey^>U*tKPKad5y;G5Xb$;=M8+{&9e7BT*bcft}L7S z2VtV|m-Ie{_I9*k*0$JYZX1WKoi_;+o!5^6pXYTtufGLt_GE3fIgK%SQ}p|HDX-G= z`Zfm@Iy(&v?ffwBuS6^FNVP4uQ$E~g z@l0Vs$9Th7i@XOym+$^jd_fO;3&s?Szbp%S%-{0-SC@(}=osf1Yej#sHDc&<B2TI^=y%6+9%C5WH`*TJ^q*OFgnaKb;&czh{gvVqjW|VpkMOt`jX1@)KElWN z3fAsrByGP#uR@A8!~US-Lh(rlmGK_PWF1l7dk~|VI|vJ1emWah-hHePt^Q^7nc}Np zlMM5=oYyx+eH`?-FwuE^gPXE!sN^}F*SB~-Ua$MOB^q*7^63KI?awlCp)HeTiVcd$?K z>hFb##$E=>=e`8x#TUT_5JH11EqVs$_u8f{z>z<&k z&avkrKKTfJ_p+?E_jAHTtM7I{TR%SHW%=*m{}x~PdD6_Rw)3vSL_?P?i#fH^D*tV_ zi;sG}4M(vMf7o9!%*Up@{)3@e_MLvhMBCguyXRr$jXviWXeUQqCrosn{}k;n`dHEG zuR2zXFJc@=SF(#dHbkQxAs**FD?av_qbF&nZM6C|n^%oK(=qS=)VB(YKGrbo0@^V% z?~ASfZbv&m5dDVt+3M3BQ+wkY19rmRqxfsO*c@u)FVVjY#2$sl1)o<5^ZAwQul<+Q zj*iu?i~E53jYoJ>Kc6Ss8e_m$wKlc+X)S9*>HUwH+&Okq=je{{laA@c>y29N^pj4R zHmh^?DN{R7o^#eIGp2P;KWouqW7Y1?qg-;e%-%9^0zK38jZFJ?6MEBabOIIcD9ATpIiV&LK?R=u6Eb@)-95U>H&gq~w zxv#W{TlBE#&Y2yDA6KzyPuf&$?`LmNQQ}1&Y*pN;?nUOHSsq|noX^tpd^omkzxxGY zqFp6xzGc0`*&g0g!My3Ig@W|&{@gRK);wla`~LuF)0!7QI35Rw*SzS+MTJ!OjPqs; zMpIMMva-jQWe>seGQ1Jl{rm|d$BePg9{KtW1-gWPcf5c+DH|F*6*sgiZSy1%x1B<9|U3AxYR|SUD6&%9ZAMajb3#UafT=m)GA{7bY4Q zK2vn7uZctp`=-(v_IE}Bon~ltS+O)Gyo^j@2yf)sKJ@C}iPde+Y zX)`)coqp;}_5;=z@5g@)9fD-`%=^vlJZ=MqDtV!+VXiat z(jUw#zr42K#=0o0wJW%>?kO|ZS1V75n- zWs$c7{nqWP#22(x=RQp^n};HlJ&*C(+M|?b)%jKBHN8-tg^HJJ81ypC^$R%`J}%EN zlxLWiYk6U(<#l_F54swk>rCtx=s=9W@a}8sFZYLp+TjW*w4@rgW7%Kcyu53FxkdTL zK0<2uqN^%G>Z>JJgw&#vD?;kiC0B&hzyi{k8H(WdNhtIc`90`K*!%qAw!(roAAY)u zb&S9#EsqrzwE1;lmCy3--UQpCN!~?GFslpH3%gI`v3m5pA=@x7!*oC%tJ@^+LdZ7E z%dot#$@02wmKXXPpV{%+VqgT!so@F)$ILVap6J@GY+oF{D0-T~V+P9|SrG$wm0azv z=HikoV&J-xD`KF%>_grtp%#o!AO4oyF9=%+{pqF8;pUFWUtJ@^+LdZ7E z%dot#)AG8#mNy)3`t>a?hMe5_p_%7)PMtAl*6eBLc5>EOJ5u4X0amxHzfMH?*ka+8 zp|UvcJutFp!^Xv7`G#_WgDpI&d&@p$EL`Ex)kQ31(P*p)Bx4nS^Jm?OPSem^u5N-bdBQ zW9~jpd_kK_53J^8nm(w7gY!+qfe@dS1bx)E%MK!Fv&VJ;u#@ZQhM^Vl ziFC8q`6Asg<9lsB;NDqnoO}R36h25s`0zo$GKkRG^D%>;!0&fpun)mOPkM9N!v_7{ zU*-8%c2(Y>%^-N6PtazZVSO{MVVL3oT05#}PS%xi4EbR(OvRMt=GA3~$H5G3e8H{7 z%%kW72NqCfFFCC3h`lVw3OZy^sf z^GH+A%iajG&5Kq>U%cp}#Q~66D>vKP*ulfrTP7D9*x6P-#NXE?KE#=2$K&|qf(gpm*dL; z?s)li;d_diN*V%pJdflCkt0)-bpYB_~+_4UAx0x zV3hR4cjHgOen)l$-LWCo=8p;sn)WPuQdrO`j@WCk%|==r-eVBpzaj`;DZ@J~ySof; zjLCdx*&VOo_elKS>zLDAQQkjOSkR{V-OfjgK${hYy#_06Ae&fP5skFH4CO7osAHSf z&n@jp#(S~_N4a)Rcf1ppvHQdmG)HiKxZ0#yrH7w=X{M;l&(qY+1jYYoLA?{IYC+7!O#~15Xso#Vl!m z3x0{@705BbwR5`Tt%zJ?`{{o%b~*! zv1;o;RXvMp`-~I}deR=Kwx}Yfty&g}FKDYG!}?-~SBF`FH?q+kQe{@h30!E%L{ zR>uj*@hGf#*|l?;jp+_w;|6V2@L*}h1E8%s4C{jx=SFqR)ytmaWC&I~wdtCyF4?tg zSa@N_zg)8X%%az53us;uYHde|YuU__E1=6tF1%yqwV7ovm0TwZT7FL9r?&G1J)bP0 z11g(x8|vTm+Mp1hZ7U~ny1fLU@a_)mnx82wXrA183eM*f^w@J@-Z@>dWiM5+5g*F) z$EOJk`k%C}-ExW8M-!dQPQoiN$y7Db|om2gu_t36jn<%g8fIO=-guQSp@Bs#iFDL+6zjq2->Slt_a#!ORfmo3(H-F2*<68jM-M^5nKH& z*%9G5HVH?k5Bn0r@gngBZLYqsE4J*_DmDU#&mQ-%4cc6NrT8k?+$Naom+~#Ux+~wZ z3xt_$$gyg4c~PEWUM?}_v5-pgQnq1U2JNIx7G`c+*luCwKCm*NtCe9ozqat%ALi8F zr|{Vbs|bw&7GQF2B2{I%qY@F~00cwr+&pb)l3 ze)JdlJ?O*!7qRl9u%OLf(Or1D`Sq_=zTtmBtXv~3Xsf3ynqYIfV#_aYf_dy&{eZUm zNipOx%=21#kZm#GWrPlfxh|o<#f94uc3NDRy{|0>?1jw!M58|7n*fn5*-*e&|eKOJ-Wu*cA5`U?x%{FPU+BQcLy z`gvhNn-6^`h`hreL0sG{zM!p6u5W@}+!b3MG39bB7SeVL+F~HZkjF63Yvn<<#ekO) zIvD1OL8MVm|d@TiS)Mj9_-SR2dl!?689RQ%m$tXaEkvWF^u z`9wO;e-};8X{$B&Xz-0djXr*q@&-+hEnn3Yiy3I}9f&_y6lDZ$-gaF=4m}_8LI-Oi zu8ZZt49{u^zkOQOCCdog9(uoO2&dW0y3?qRa;_CGVyrs84R@bb zR!7hyFpGNpcz2)E=8C^}#bOo}dHF(N>00pxJ!WFrD+XHLakG7?g#Qzd~ok>xMNY-5W>x?%h^Www48v%Hi$Aq2s(qO{wyB^Jpvm8 zkNap5wE1+k_)=`yUxh`w`NjDx)R1mIFuvE;8Q4zO2jl}R016-6(>2uoU5vJ|6JiG6 z1B3DT)u;aE20K0cUohCGutA$a|4xhpZN?eaH$xhRn!%7>JE>?oZLGl2XuY==Lrt-A znN)UeG1Qc+4a>+*c#CoYvWYa8Jjlfv?ldkvQDkLIi7`yhEY@Hu}V#jL`~xU!?I6Olal6! z(eLI63z{2Hzq&|R(40;@`#-{hHVeHI3EHeR>@`?B6y>1j?$St;`SrG{$Cc%Nex)Ao zLNXd;Op}8i@-D>Vp0Xn7VK2b4$Atw=YgXPOENEIL>@`?s!_#S{Wn3~MMwjoI#%S19 zo_SAgTMqpX=CJN&q9(6*+ni>1tIO(H7PQ&pd4o3F4C{++<$ke^R;SB6&OoNA z4_bC;IRlBIsoa+>hNfD%RlAYwU>~&XPzb?($Fj{Gb9(d~3?&PN1#SJ(235X8@sX9K zzAq9q?fym0`Orski`M!e&l~CVi}?ED7awxWDbve3k0JcQvh8l;(Oh1Sh$)Fh$Ad_I z9v-+?8VAi@C)#e%R-?O!FKDY>!}?-HS-ZCEJ) zK+q#_-s^GS$OwAK4yd93YvUz z^ss^rtmgdyhQ1j5gP!sQ*x}I`^r;u&js69m*J+j!wiSHD?sq=dl|CqR_H^@0!nY85 z$>U{S>Tj6&sxPr~_Uv;zEplcka{75~BXZK$d{NuUy_A5GGv(fGGwk?=?X)vt)tS;Z zXnNs$UOPe4b8+}IXsey}(wj^-3{x~dL7Vj{hCGH@-adF_+6T{`eZE~o#^+U0Q0;?d zUqO>$TY9)@D;3w|y}CG&{1fExlT1M~j=u9#Gb9U|7R7t@plOM)*JR1m8RycHv$|T6 zoX`nNmKU8v^xbC3E3gE27vqFZ&{G~MPv`_~+Ao)NL7OFp^}&+4>bosY_bYq24OAU3 zuPJ*tLh#v|vJ0xs67+m|_%xuEYl`ly_Hhj_Yx);Z@uE3792_s2%M1s%F+9?bv@6SbFW`_I{ zhRlK?OQm4YW2d4GEq0}yHsyDBj7EVrLk#P&A-G4~dCEz%PdeeiDUh|%A<~{_YUZgL z>hp?Ov_Ytb`lH2Wc)$5s_EwDlTYPxT*pci8`4r$M01h53utYyYlnYKi1@C8xa)HgK zK)+0MxIm%zps>@&j2$(i5u6S1fJP8%jS980?UhPT*I^wGHmrS882`x27FUKXCAKAc zGqdj#33icV*rVgayjyeCNZSpiLL}hfj*p-(4`&6`$}CTZ4Sn zEy-pT4Z8MG?TRE#q6pNDM~)d8aT@zuTq85k4#r=Ni$J5{TU_pefm1+yB7Gn_?WoA0 zxA{w1kwH^NI4bCn+owKkE{$b7t$QdYixG`G0;QEa;uSQZ~n+LvG)VWv^O0 zudA^$yVmRuFg7~Tim@|Qb73so;+E&Tu{+2J)-2Px<@29gg#|tEkMP}T!h+rl1#R*L zVL^x7z8gCX0&8bXaX)c=#bHO!`QpjKGfB)@?K|Q*gIg@V0K>iq%r#vEPJ-WvRB-)cZfaG zhvSA9c>V5MR){p@nV^FY*bR)>3ZYt!4j$yLnx# zZPG%A&{}q1_ITZzwP>O|E}UAs#f5IIXNYtj%vj~qgP?cA<)r^$GlNgiv}_aae1qmM z<@ViLb}+c~T38#4o)^1zz6a3Sm=)UYA@b7NmtVy1!}#5Un)sv%!;jUi_h6Ae>R(y5 zqwmrOJscZ$Tf1dJ@Agg9Z7z91zvKAQ13{YyP*&eOaPG9T>;qsmeAJQ4zO8Xk3o}n1 z#9x`*tgq>`{L3$nZkI-OgNX;|*Gw-VM4dq|ln@TGaQ*u72TN!JhZ0#Rm3zA@ZZ4OQ z0hMoIYX~WdU-^?lR_$zMOvKmD5!Z@ICD*wsF@&#OkqWf8D4yNiDAuj*~i}k z!w@0I3**kg%O4ESCm7^dZ6xwmV$hdY#mBvN=B3^I<->AUOcEb|`LGPql$T7iRYElK3Hq>0%5sAa zU!;74|55S`hO*C}t%5t~G#T$B6tqzuqjhGBhJAD&yR4?kKCWM?4A z(2cLXtU8e0g8>uk!%@Zha3d)qUgQ~tJRcBd%A-TIO#)vZM*5x~!C#bKD!!mM-57I} zzY7a`+qa>>t%L==-H*#PW6)7npT;qBz+e&Q|2tNhA3lFjDe;mG4N8LO4m?toZFdiuZ-=q{d;kf67H8=S|@ zJ3K*i?HEg|phIrojU9>-F!XjYwtUTDLoSWQI<(r_ zk#5VWU4#X_+v%93UMei;kkNO;Y|Z%b(y$q-#UyZa*#`sF3 zDRqt;Hoy(@bpEM>HE$6X^uRx&W+8)5(7Vkp7t%q8+`b#jUI;t6MJ!(8ENFUw zW%b?H8nw8*MN@bHYs*nx)|O&MrgxM#T}&$ovVPmwmXSW}TGY2sR)QY5 z0QG&BtPOg%&!E27xCfjLxqY{meNOGtuGW_K#tLh(wj9-EZE4o-4r}*>wSSRz)T)1f zx0Zb%o=6`y1J=G>SkT-nh?j9e@Ai50Tic2+=#blYYi(`$iPGA$FgNB~|MHS$VJ+5{ zqsq0VkF{cE`3MN~=6tLU&`Vq0`r0zm4?yqx2!caT>wq_kay89o=$r!R*4y`vw zsaEyM3Nx0?=X8v24=_7Ssj32KeisxNCyW#6#WzS#{_-Klo4Bfs1jBe?n2#Hr)Gx+> zsp=4)VUS~3B5yf{0p{f|A5M^2o_sBg3m{@#42CYm7F`tH79YzX#xnTJhdQslOl9zw z56iIGjyb%)WqW*Byg3~`6k6t4zXsbW?j8BTuw|qhumKC3O2|DVOd}-dO^TM^EwK7Q@(~{O53W8prbtz4PE$ku=q?= z(B|9Yl{aYfvt!}YF~38Me^q=zAM{kYhz~m2rlBwm-Vj^po!=3_f5A*f+Vd7}R3~-~2;kI*QYw*~jwyxnr@> z`%-b;D3+NVw>STgmX=%CiVCb4TX)37Kv}3yna(xy4tog;dQ&V;wq7Jmbe{ilN$ep9 zjq@hp+sS+#bd<%s$wosrHrsKGP4LG)+K>(Z6*hkqHhY_~KUGfyc9_-NX6&!ps?V0u z(qji4FHsiR66stf?|?Y~pP)B=SJ;P7>KmQsFQV@Cf-ea-8Nq$n>YW5^jZA_vPKqSW%{<5x@-?oe1hKeWZ36z zMKtVu6EN#XgU<6mV|nKBCbN{3*-!`#F)I^ZW(W!8)nM?KT#H-9I} zB45vK9%AkJ>aI3l1)GOa7N1MpfOWKIOkvF?8_!)2v}cCKjxR|F|SuiN?5t z*ChLWj9Acl{(HpCJANokG;Cgw)U(l17WsN^^H8(-b6st|7B&y3EIyaAaboeXN%MNX z)@@!&UbZo^Miyd`4x13$8*fY`X#Dx83Fx;^5+)kANG4#-d7UuPY{Pl}7whYSj1nD<%lNgBhyv zx=B`3LBpgvY7Z+PGtX$u63&L&?-3?C&wqkjphp%R^rt1eUVan2Qlrs9|A*>$z=CFHyWyvWiN@`Q-<56LZyq=um-JkIhpXEq8MZ^UxQMEc)UwuUxiP%!|JGk1X2F1HCDNb;FBg9+CXYs zz(%+G8)4SP{zhHs#ufoVBVcjr`aiQ|ifD-5iK2yxj^c>**p%UBO1WcOn1bH4Jcbvh zBp=1xki~f0i{A7xVP*>G?a=$J{If98>_PMVHv@JTD<~VYn@^XWX=>h=Jox_Cm^D~}-tJ$R%)C{YX!W4m z-b5^D^`_fxFO0qEcH7e=7AH(}s6ed8=Iw8_S8l)-<}HAE+^)1I%)7Om?xyBpEVdfM z+MiF*Zvh?ViDr%Q%?P=I&hz^oheciRqOspM2a4dbcm5d%(cKC+N4lj6qJ4=U}dRS=sv1eiF+e8nwBP za-#G6-=8T*G|_qfcZ9N*UP03siVkB)M{&e@Zj2@=_|xx=#(eMpW9?hO?VPT)*V?J1 zArcxXan~GFLrEeu%~6*K4JFkaN0oGoh)7+6NR<}VP)U^t*_0fYL={y@R25B9x1+M7 zswknTlBg;@M31UN_WIv3g!T?F!*02uR{0R%nZSWU;7?*C(eiCsvi0T8DQ+?|LHfa3~);{u@Z z)*hgTAQv|R{4D{d7-SaLap=Y(1}QZNFb3*=3M3ll_#>EOEP0&9IUksAckJHNQ8hN8KSG08-xlAQQ~aU=S=i`b)o=e% z%x#w~W|S58Ls8_jp2SV-RsB>Zc#*EOIz6qe$fd+vyTqK&Bym2SV=PLXzZOv0#GgE^ z%s&&VbFk&By61YXj=9;wHwpyolsACtFx)@wJZ`Ob%vF)d7wLR#qVsg34SmFUs%P{U z@o3~9URE^o=}lGT+y9#UuwC@v9bi1@Xf^H3SZ&^RZr;kMc90<0wYu+G<+{%5bLovql3g-X)iTZn6KU6#SG1 z`W{4i7;5{Wp>P;@dSozg=cROmXuKvw4g)obw{eL%!^uGNiK=9v`Ni>Mp!p@zWT5#a z;l#=>3ETT?==_eG)4SxA(q>ly93mN=%`#iKIcyepUP?Fcd)Mv-X+Tpww(zwMnT`AxBbL+NIp zMZQ-dtJ$YyhHbwZM!|bi9!fUL>AZS-wpqmKbgHYy=aU&^(M4U+xl>&=9_dd&ZTA+? zu27laMY_R8T2ms2&6>p9Wt)}6`PDhDnoQ#S6UzL?z4dGU{m*2e`I`ml<$?uiGZ?2! zt>CKsTXmI<0~Gsd5}I0`!BdB;E>e-m7wLR#`X*vWUZSl-u6Lg5;cue7VoMX)Q_yC| zyLdkF_$c*-i=8K$k5YB^U9{QN8u|Fq^tbNxvZDF!t{&5h79Qp-d2cW9vXbAs+j(lw z`#b03R};*R0|)c59_I7dt-ds;LkUvC!L#J-b1> zIxGoyUP@P5SM1m%9?)pV`JJm|$N6`^lO5+@w@gNRW7-KwtVQWTK(gaYvhOYJcrw7f zxP~2H5_XKcfsb?pe|J4^B%&t0&?VaRyU6p^@ouc=4SE~)9zIYsKc$yG&=$1W)wT8Q z+7W~P&J)dJD)Qx`>9^lp;rT?fzE#4;cmbHqjsu(8GdqrU4HM)yn++Vs15V=^-Y(cN z*Pzt}*^awGCi(E59satq;h1`k(avdbJ1`PK_>nBy9p!PxFE+=A=*3R=?}H-dQily`KnB?5EdI z;@u3Mx_JkoH+921FQtEFf7nT^7)4u$45-h?cXVD4I}y$JQ@&iZ+G1(tGuwE?>l2S} zn`^9y-sBH?42b^pw(##Kds)$}kMRI6@%EpNe6~f5m^oT9MdRW%$>w;|$McdVdjkf)d?4xBVn|_3k{)hkC-`j5%&^8V0!krg?0g&ki+jvcg z9I=K;yknzn=XaiyZ4XVZwj$duB3~JD{_K6S?feF0vh5ABkH*@Bm-&FdV*o2p8(=XPA4ZIo7Q`wQ-VY4v_ine20D?FcQ+R!^8i`rm* zeKu9J+20n?2AvROHTw*im2UP~MR=rir8OmT_+FEEV54nMN$>V0+kPNFqLpnIUR8!% zn7dfTtLC!pB0i422?IX`K%WBmeH^^$7%_p_HtxKXZr~rN=kYt5`u3S<)9=lmuZ|Zs zruz8HiF&VCG>=Xzo)s;bSflD2^CkG+tGo@-%&)I`i8h-w{|Ov)T9Drq8#t71He2N5 zcrg2v%p9A*WIV&x1)Jrw>gt`@W)Z)cE{Y9bvf!jT+wk?QNXN2U8@`0b4PP(g-J*1* zb;V{);$5=MO5$R}R}vQ+zMHunl^eb?(83?n0{JW=f5$w1o3S{q_lW?-dFu_7cnSB| z12+5U88(YMFQxMxZ0!Mywhq~`KHu2?$-YuF{kMFjXqMG)+bJJ;E5f&lM?d<)B5y-9 z{ixP{qA9!fY?Y6%1?Yu6(af*7T(oc-UdX_GVKachrn+g{YD2OzpJWy$*8*$nf^82& z@#-%cZM)bjmZfyES8TTZ9t0SJF8Cou0VG00sASM0WKz1)niBcU)`|Q=pMQ;P+a$8> zpJB;Wd?!&`YAfGs438MWu6zWM8kU~=P$Fl&m4Lxnk9S^5S6Z_o`LkxzDOVUCX9KO^F%9uvoNgZ2cgdD zry5b@4?CuwU)?x)8;s|CVWclRTJNrop2wXR7fwu9TC*a1&zsD@Y?S$_G<~O@pOTk5 zuz6l4@>95DIaAm3;RILWZuuhpSUiW+Qd#uz=jCZmv}wc2HZgQH4hEy;>c3@V+_xBk zahP9bO#5%0EE7B{iVQ%JSSHxY8?&^nym9BHbftAo8z%GJjWXwj0=`CP?Jp=MlQ{HX zBE#1CKCyy(inRcf2u0@IM2>VmCf9pzqWP;5dM`~hH%@Ll$jgdWz0Jb4@iGK;R(EJb zn}gk?p-zHbgNtByIG!~s*flL6$TbZ`u&Z>XH7l}@7nAv(MwxTCn>3U^#jJBTCNk`r z??Au3kN2qcWS`Iw?!1(~`vuU@Z=5HZpES{LD2wJ+DL*jIOSI~37OrW?HVr?W(Q~sCiA_GGLOk~$v3_I zXP(Y;N#W7>aT|V1WyQ`Wv5EZ5(<&0YNaq9gr{T1DiRMEi{YaE(LSr4xLNjd)Me*uq z8j-c8#bMIMw9e<36|H~)kymU>Q9x50(;OP_#*1{NH7l}f!({$dqs&L<`9<1zzSH?- z#gPyXAAVV}Lx{(oeBMRo-9(P`(ReiWbWD??c~nBbvm)BGVP(58zu2bE&KcS1h&B+; zmt%u0My8#N4bO^nY%^(WaN6V8@G=ff=}POGHcaM4jWQQw<4kY=#z}c>#Qb6+V{C9U zM`MFx-8e}_LgYw4=5V~{{cGom9{X4PD*VmP6V1iQb&LRUiB`SM!nN_TCn~Idwh?VH zUZkN;#*4wlc;RM=#*1kIG zv#S)DcV0>#ivuc8$67@+$H=oYJfCPn^Rmr(G>0|}l~#Y<2(4HQ2-?_ed@*$zw5K5Y zj5VN*4QROYQu^4R16nN2L~{WkXD!;GS=lC_O*-9?*#h&vgp99zGmvS&Dg`peLQvBF zNauk}`&B4%C|-E^v!Sr5vz-fND-*m(=lsGnfSqv4u_v84=%~SCKfAWa)Jlm5xy0;Y zNqlVzW0J&Ar4t2}4PBtc_a;{QSjw3r!pBys-|$?kZ^}NtPat5YT#Mwxfb@^S1De%0 zsYvi5o$<}1;Z;N%dKdyP)x+;&=$E}kGvD$vJ)d~IYqLl+>(v27(JV`uc%?Ru!P{1U zcOD-kkY@gSj&q)9mR)?W^CYWjQ8Gt5d1XGzN}kKygl1)ow&uRS(HL({aa>aEW1Yuw z?YBY{96)UULILA37q1<6UP?EJ#%n_4Fh-MjuuIIjM#fnDHWyhO3i-FWk}>9AFok7$?uOO`^-PuoxUvfQud!f#T|z7{rimr6#EIg zx;!K(@LY+n!rqG)iF}bh`ZKV_^PDHz^xIaSj|T@IJi>XRS#SGG^*sKHrs@;TyABbG z=01)dh>Dh+tWomwz>R*iPP8d3WGQ(|_HtR2ZUz$h$YVNrWxnOWX*L^pg^7LT*t%fH zLm*G}!A3jYG5cBB@xh(@*=0LIycH1TlmgnpF7h(mc`4ms8?OnG!_S(;do$Raz&OC~N-B^hlF4HD~(oJ)3G>{OL@ydA*3xP~3W51Sp!A4j@@$2yRg%8c%n ze=1M(f5MK__lbfw+ZbJ6mIo0ZWN+XSZMN}7C%l-qm2c4BFb4X1KGA%c;jIsxC)y4e zzV1BHHU@-^jtQ8|j)jeO3|Y;NLuQi;GMLSVERxlDCUX-;A%AQ;S`TGA?uqv4XRgTp zm@EvfWek;G4De~f;&el32> z^XTZ-_eLbs#!`Tf0NV?He3Iu{c6W|vHwsYfr>jvfp8W_sb+hbl6^VS2&KU7wytBhg zv~|eS&Qm=+B>3Ro&J)cCl=8>o(YLBT(Q2QimCx+uz4|uz@o)Wbr)Z8N{cxvf8$XMp zENvFDnlVUb+APw&Z#|#dGy9BoCBOGB^L4>yhoX4(zZ-4#rtEuV0qq~*dlBCASy%gY zF0!eiJ)q&vOX*5$O62gpCh_MRZ8m@KHrecJ$%R&AvyUZK`tD@mdu6kQ@0HCi=`_aW zmvi}4t8@ab#1qD{Z@pOJ37@L9??_~VFixfOs*^#1>gZ~E=& zJke%%vDi>q9x&852SuB`OJ>?9WHtMg%(Tx~yztITa+xiLe3IXIUG=H96Z&wrPkj4< z8yM~Vvri=pTQcpV8hxr~MLKqGmv*?w+^1+Cr82>bbftC0K273(&-N*a^XG^wlK80X zQ{e{*V)5|2;F2+}&W8xU?ml(NBl!UL$>DkT%06|I0L6aV2K8c}cj>>JXZ~a_6^VS2 z&OIva5s0=9IjTM%4-PJhHNEQQA(96#@_eGr4p!Im_`5p~e%pDX`Er8V6)icLQ|*oU zG;I5DFDsgDEP2Fvl7&BCDt|1R-(uAFB}H@NO5eH^O}vYTM}0IDU^nAZA4IzA%JT`Q z*?ZuXT;#cYUGUKy&(+^Fj)8&MN6Vr{H~MHB0|NmAYFqkd0S#f1L5uK6>85hyH6e2N zXp{I0jbk8xq&kg(DfzIW#z6k4a8(9hgc@Q!l?tZs`HsjwI^tskzde9rr(IvWHrpBz zV*qzvN;mLR>UsR(jYTn$iRMnbeuP`J+0K~yvOFZH@4brNb8aMuE*qA8dBn#C{#qoz1n{xnOMuHT|9g=D zAL-wC9P|5&&J(TtF4!#NtLoB5n=ST$WdWV+0h`)x zg$3eZq4t0c8p0=o7GadqmDZfimIn)mB#~{e49lzKyQYvSZJ)I^hD=!F8~XwVHn*Oc z?&6tP69O9Uyp*oAW<_>wn9R!>Wgeckw~{uN=P9>1=DB=0M0#-zZ7dIwaW|18ouBO1 zvqaGb!}2vTbWe|QV4KZ*W)$3`7*RLfq`kIIrW?BeScOgFX~kEm1WO6ywB zo6L_k%A6;h>NtEI?^SedaVRQ|6`07FB>3|~nk2Sb%B(8lJ+E{g9Mr=;(fk>r$LD%J z(OdpFKgbrXdYgr7V`B)~sSayIo1JUYP$$mS;KI2M$9MhYTulpbs-~fEu1Z&0vm*Q0 zFqwbbD06Y1ScHd|7>bZBZKHHDhCC~ZU`3`e#2K3*8)s~P_MX#~)~v{`A(Q#B zMwyE-bgZ{uZbZghVj^P<@yA9rhA0*{A}KQOyp+E8_6VSCj;K^b?~eubgXk$8*`1m1jlIk3%GUeu&JS3uuEq&pR)rQ)K5gH~o3fo6L_l%6wjqsm4e9+vJ$4=z0G5 z%Rv*@5P2IF36Ue6ZwKiBhiHR={9Wq#JyE>6ZzGC}bNr;9U(gsoS8*bR-W!Zn5k2;2wb~8;aGq%HmFtwTXv1subxFUr{CPU#or+L+1gtK< z@LN6GjdSi>dCCgBo)aZ@K#Bi$nQ3=(-%=6hDV-lboO_z{MDv3$b9Qu|XbxHFSG4Nw zqJD>7OCrSA`2-ZIpAqW77PJ~+gA zq8T_zzoJ!d7x7wXzC7doCbk5y-}KDgdHjCccL^32A0!IAo)gK3VNvwIE;Ba@7Otlv z!Haah=d<)a=ZWThKH>phqIrHm?pd_z?IK?GcJmIxIEMN^#7R1 zcJ^=~HXOMV$2%{j^G%wiE1V~q_xTGlk2KFT%0G)XyjEYA#;=8(&t<%4x_`d$;H=;8 zxbrE;FZ9QY)9;N3qsKA*&I_BQU*Y&=#K1c*rE_2Vx;E#DKK6iG?HY^;UZPb;7jSTFL9M2%?;Ir0eKH>6FE-s6SL(5~O^VzM&plHsKI%^|Zb#zfj77xA9 zh;8qzBVj8Rn}z*7vo~ZFi3TzmIh7EUKO6M~s;N%{hSi zo6=FnF$fh@|I~=%-mD|xXnc9aaNG+VICE2nV{G8SotM&i-sN#r$4fM0Qf)YkHf&b5 zOFFXn<)w@bd$n8d2uX|i?Rb0)9*fa(`!?*)bD{)(nnm;5&i~1*D&jblzT-*2Hq&{c z2M*3#wW3u=7xiYb%AXst6?2)e6&s%=HjII-x6E^y$%PG1>yFs?RQisW0o$~|7W58B zX1$449bLp`ammXW8+W9zy;J;Re08E5*z(55PoC4aN^}m4_O$#76>%KgN@4mw7oZO~ zo8S`7xKi(miB=t5#5NSoR9|Vtme0#2Y{kQzh(Qb+)=J!rsKd5Au;I>2=_7ub&!LOn z=NIskw|hR(j4PiEKP1}lT76v_gBF9V$au%QE|*lZpFF{ZZ!gYFg`L{wOBHxVVNHzr zniu72-%CZDr*wYocWL++(bS*LGl^CmUDPG5rn<5bTaWBJg{?RXQ)24@Y@^q}HX^X$ z&P(b0VB9U;*LkApFSWrc+OS#KF6qtUl2sDJ~IBY+klY*w}jYFOArWb)K;8-LTHHURVX$?*_JFowp3J ziebZ@m(oYzaosO|=RDE$GfTH}o@mn_{1GqFhS%zA0`G*APd($TR_Lu#eJx?FAWCG^ zxcGy#RcCesZgcfVVi2qvw?_11%(E zD11QW9K2|-0x#DLPshkwPQ|zMPs2MvccjymEth#0znwn@-Exf=T(w;~saYuw=`4Zs z;0BUp7v1_M-gk~*O!Sx+@MABdiKbE!z0bM%XMIFdDR19cpKl8|X#epT{F;=}_;Hvg zRaP`a#gmg&+p%mt@15cGy#L!8U&Xt~c}}Aa=gPgh5h zhaL?1X{?Sza;Ynss|kZUe(FglxxM{0+gpD$2*0s%RJJ#=(Dur+8tu)q!s(63n`D%C zbwlnv(Yb$cwtFn>I?DcQ9KJ(s6mea#lJR#xFDSGGSpboPD%|DVm2?^tCL} zT-C3fC)#NqN;oO-#lp?9{OYz)?(Yv65%!Gq;Jt9bh*4~g7kIop zuhPM&^4si{KL2q<>!>lUBSs%O=094;j5@GdZ9>HHlWn2&W)?04S#@Y39GasLtG?E` zaH|egI>l{Dia~_+_bi24{B0pcw`k?rkC5WGN^e>UTaf%umLghw=b%Cg7}xRhp}emb zQiQ>=kKQ>5QoxYjDYj(ZK1yXMS*3FHKJXL>-RO;(#!F?C)?`20vg56cK+=|`1{ZG# zIx#il|6b{os|js#@tVwjRh9*Qmp#<}y`nb}U>WbyqBje(Z~vasAvu`z%``;{H zh_b9wh{qQxA@Z_bor|}OinH`4yK4O8K`zI;Sq`;%ZXrj{Xy*qXA;-B&Z(5GQF2_H! z9BT8!LJl6Bhw-;>RLD^n|FRDuM+N;=qa1GF?Hj6$^Jw4?&&X-ys*KW_GQ07Uhd74! zG6u<8n%o8UpHOrrI>vZs6rEYv{$i|6 zJiS>#Chyj29__;{huZv0AxH0M=bev`<1b2YT8=?3M=i?{Z7w;kkfV>cv*gsypV2b_)lmJPEgeeo<0&!kuUvQX_N!F#Y!Z45cjtMq0?!I0w=+_F)YBidZK zdm%?ZZ)fE`oy)NjJ8YC^H_8a_DORLXH@6?1xtor1CuKtL$4`Tvn{uS7n^H_rKL@FJaGAY2>Pm(wZ`L z&MT(V{uzVhEp2PFkf#&dGHkz8IwfmjUh(CdkGL(fDA8=4d2t1Y?(EFGj1Tkj^mP)Y z^~}>JoPrWP^7%4bePQpRI8u@pWLKqq0WHY*IASGMJp2rY7G$FNC|Td}7EO=2@+!*c z-jlQ~$c$$@7^hDdcU){>TIT*wWw1u9ck} zH(`A1q*JDxvFo9&Lx%3wIti7v#BU;D9aTNDQknYgTE}Gr(h}cT!@wHTxWxCYmC83a zsCCSY?W3t%GB2vJGA^sqm9~~Pon)PKO6!!fP8mPpxIJ4>pEPCCDHC1p_`Ms*-7>3E zx%{eH$ECM6%01vqW4_{IU{A=2sar$dpFzg$2{m{@o7}BsM=z@OrQIMTE}#Z zZC;|M{0sF(JS$pltt;kljyq}6aZuG66HY&69QQU_im%X0O*`eC_pf1Q#LnOHG5Pck zB3fRirJbOqjkA`xoLmkqc@fX2bUg9zxOklNL?5$Ht>c%!ah~X7K3S`+_vPRP%?-FQ ze{r5@-sd4w<|TUUY&@yy>pamDuuG^XHKHZw+V|e%<0hQmYMqDLd&Jw~80b}Y5OzzK z7cV|dgKxv`RY!iEFnOfnkXv-47p5S1aCo7MZeHi)@HDvdQaaBlK7N|>MDqhjuUzds z(ez;Y6#>zzmpN6I4?$E`G#?&(c&pbZnvS94KIe&cl;o|OlQ{0AqXvyVYBz5BwiKV; zJ*-l>pl7Y){I+a>>|ITcF+#bf|IV+WEZ=wX}1YC3k=ijL!&Qtp24{IG~uXdhj z4yI`lLyJ}&>xwBklfV_f+(Pe15b%B_E{-&MvI*&pQ+>$Nb0Ycc1+Jh^`X(Gk*obJ# zeKFQDyhNKroZvjs-W++&=xUJZs`x0cbTubG$daz^%@0IMUE#sSw6}l>aX&BX=X<>y z&c~gX(oa1Bx_Zueq9<=t>o^w+XI`RJ$GT$5x^i6cizTJ53S81vYkqzZfuZRNxTcOP za0PwRH=wIBV@>=*1qKv=pD>#he6>(lPbSJcj<${Bg(3gYy`Q3CnY` z_i7zyJmPY}H6p8uI8W*LI77$TIK0nG^w{46=U&bejYC4oCPk~>=5^&*cTF)?mB4^? z<}Mklbai6dif>_$+y)sR%kVA6QeoU*Lh?5p0>!)(v6UAIUZfL>=3&vw&z!2qX16I` zRjvLv#NEfDg_ignD811b)X35N zZnp3vypfsh*__MK{4P{B4Jv&v%Q~}NMVzPfV}4VN=AiLm>g2UVBWTK_IcQTe>TP~B zJJxvXooXg9j^^7E)}+(-@`@=&^UOZ!y9{+|zKsF_!Uq90XtU0N&J%4Au=&QTDr-b|D+HCx$rgYTnx4^#6VX`iI}AHJF_ z=c})RbvR~~1M_H(*n*41nY$nvYS!d*`RABbMO=QR&)OtUPNJ2cgJLZ{m)*E9KFTq~ zJNZ-}1%_mo7J(2`2HfhLn_U4ll2f)dPo|%wv7N*(L=Ik z(=z6!%YTUEn43&%hlG}K=cV)?4$t$IXyzC6l6RTPMmi16^Q{~7JeVE+ux!z?hF$Yu zp5=mHntitR-pp=xh3bbCst|)-)>rQ#-|ABc+o>#N0!m@ zVOWMd0`J)QigW6jC~n zVFf*LT#5~<5eQ6e%bqhPNY9B9ST#@lyvt9QF}2NyKkvMhJ`NM#F&4{IDx&cdDjjE_ z+jxm)$bae|ohMrLHm5reb&Kx<2KfZls@)`TE~>LoF|(4`sSm~6HQF4qd80-*c4wF5T=*2 z?u4m-)?JC|Wweahy$)0Vz=XR=7U|f`?3jWL7G9zmv`SB+4U?5^X59H~zfbn>*oLLo z{$Ag#C(d}7NXp%Wz~niR44Kc54P5$d?k0E-(Z-+M=1S=-^pt#(Zr@;TeQv75&noaoL1jj z>5e~pGI{D5zTMbkzpS($`lNQk*sL_n3H0Wrvkawi`a1zp4JWOMw>!XTnAGSby@>Oa z&WUWw1I`o8iA;k_wCY$(r3sA9W<82;7+g}R%)OB!HiBvNh@P`jnYYCnVBiT2On5}4 z{|KI6U_@VX3q0bT4p1~_wNoP!5p4jizID=;O>I5)&)T}QQdu~t9w27{Yz|L6FT27p zN6(28w`PFcO`3R~in!oP|1PGnV-ckB5{=&n?KtM!&J#VQqt-G0e&>l+z3Zq!o6~xX z%m8P)IhJ#`0A85=Vyt>-juWwK%3XWS-6qI|0T6dyO6N|#=5Eo-zm9_2B-P`9Ecj)v znNo22cuZ0!yx*y2DELA+FbPg)e8T%G;({yvyVy287S9TKi5`dG>X_S{Cz_itlkRYy zXw|!p0By$VabN~G3qB0qed0@bYzbg3YbG3p=R^s3_laA&Kqg2n0OHO|>E}KPFd?|; zalgzw(W+w|!Pr#QJ{F|Yvc*}1j=@ba_Q0JvuW#GRMY zIWH;R70r3++>Je-Xai$q*UIaq9fhf<4B}*!9y|{j+B&FpH~UHLmV**T+e$!OcIH{Mzy z;zVT!9f;=GsmC8b;q(c|4LZsr`7b3T)r(>hE+SkwLQX=ZTQ9uc3D2X%^+=8gm-7qV zx)*VomCi|4?pn0+uY;Kx4y^9SpLAjzga{m?8*vm-Euc}T(g~J0UIvbv>T%EsdXc~p z>EA_4lz!zs zwT|Pqcb@1=-iEI`-+7`{$GT#x*O6lz(}=Cm5#a(`siP7bbi`el5*z#6iv+evzvvBM z>+3wxms|;K*9W$siOuzP#_5wLwqlg{p{Nb8+{2QOKk?A=a~~96+czJlxgac~TXJF5 z3*ncsWIdr^eZNv!fM>@gOIDa?s_OK}Rj_6RsPl96KZxp!T|5yU z?mIZoEEJo6X3@Cwn!7)xlivYK?`qrm&S<&jBvMlE#$tT)yge-OK2CuF@>a9y}bEJu&esKEM)!}(?!gLw6 zPkc2mH^Z7IuFi2uI8e`t5<8&8CkfciV0?(%%6;$=Jd_9<~X zG3MF+l}fj^+UlqGsCDfA+=wq7JbKJvue4J6SFPjnezlH6t_NE@1lZFqs^?WJp6}2( zIbRjVX8E=&czfGNQaes~yx@(%Yhy=1!lw$}fu6692LUYK;YB`mTv=AbxoiWWfDNX@ zin5Fkxe->@_e5>=s&gGp}Wv+Ui%{!egdU z1#dvDqxaQo@OJdFqjxRx4fL{K9$4^pb>2~r7Cg9R)>p^dGwQp&$T!@}9(qUSRS+-Y zY-z_Wd)GR?IJed@>wjt;hi>P*Sszfx(tq$Q9r-M+zU;JPa@lDods(*=&*$l|2}{du z96Cp~)7ZwLww#VK+sU3fsn2AtR1Vu6YpADTJD7e?_zLrZeiSqu9KN`0cjHC6(#TWU zKD!}bY^?R!i*_mdWG>K=t~Byk5A(4N-i=qZA)b{%-EPO8udcpmchy6VV*%EGl4Swx zkoDN8k2aL9G}frHb3dQU&V}=4AJ{|@&R*$CV_DX7!eJUKb%<9z`D>$)n0o)9Dt5=QZ_`==BS@0}fX~s)sYb$fv+A5AijYlu*>9y6K z7WJWx3;KB*7xZgvLp+w5)?eecvA$_8v&nMA!5BYFF>W9Ae6KvsG3;aN=uyG5bnq3jJFmg9smel9V`+lW$#Fs{o zI2dn)AG+_Cn4>z#OPzKq*P4@#Bd^Eq!-woKeCXh=EW170I-)V!Dz>x~41BxuXzL|J zQ<$T*rDeh9x5Fpm&P(a@=NHjd(8}MnC7nNbIWps5RD(UL6N)9B0-a*-F``D#2|L2P zt|grX>+ieI_GMX4zX8$Z`1=i7MYQs-D~|eQx8pdf5l68NqCl+J-7axF4>_^hQ{v#V z+vXnJc`5ydZ3`Sh69@Bm4TnEeADeM-O$vRKTcsE{Ho-R9mFGkBKR~{9mOaTKOxL6vdlRJ!3}@Q&o!MUqXmCdW_dusk~R~xB;Rbx>XVQA%J6WRtD^R z$B6k3DFgOyk*_FQ#iWiOXFxEL>#OePK}}s?e}Lz!;~fVoq>L@-bW@y~j`x?ukW&sP`3Z|(WUj?8#lKIN0y(T^0o9lUH^!2TJZ z9P4;F%2G#v$7k^+6V^Z>vt~Gae@J zfe3yd!i$oBfV+zz{`0TV-eh+yo70s>p33$?zpE^RZU(;$x_RfNbfuBUdYDezRzAs~ zG%L&c4wD^|vqpVL9i;`V}mtWD`k zGhQmY3JXn@GoXen9ycbdN>=!i9zEqmCe-Z$P*#rbA&1 z`D{VKAfCZ_3fK*&;}DNBGdQQr3eHQJ6`WHB^H-o51g>_Us4Y{aGvH0ZR?y17u0dlx4nGk# zF5_TSa}~Vv_`LP2K<i^qjECevtik>Jp_thtdcdZ4QXVh|+mVcKrR8ts+|a*A+*7 z5brp~H{vMH;LM7Nq){J+V=Qp=smDP**xZ9VFQxM_dBPDiak$>PVpqFCib~6bjN<~# zMDzrOU4g|%F`aD1drlE@1z^*f}kN^9qEsK&;rYueQW4ZW-9`Wnb;B590TAUR}UGGI(XsJu1qU zJLl@Ra#1inR?X#3{13gePAKcU%=6Xl#6Rv6NZqdcQ$9)61?RGzYgaOQzZ8IzlbpVhHvKZ+`@N+=eD$)MSWZX*t4Pt_sjZx34m!G;q0+XU_A%GjYVj` z^N|=r2t)A==@f=4U1@A3mHiURTECzS$}&`ES%vI7N4nBj)@X#imJfI1g$znF9%Vt@ zCX3oA>SG!&$ujMljAI)1H;Kbs0q(q%t~Byi-R*s_;K5wh_SS*Jo>Ae>OX*4@kM%Ho zw}-`nqijQ=J-P|n|PFkO91yuSr#qN_g-GMPChRSY_*Qh9*%qu!K3{(@)=!Q{fDLC!H&@PK_fJV z9(Ip*od(amq2=qCcqu~lYvl*YL%8ry^72?Lc^YHX??i0({`q0qI&;si zfI94&im)7CI`KNliRHtqv3%IndA5Am)RzpEzdO&K0sP&U4~fTT0OWDsU-^v2k^#?G zs-Ls6nKn7=c_Am5MH!P5tdCqi3|ZIZ!*0We3?9Dw=hiLEs}EN#qH3Ag80Hnv02GEa zhTRtCy#)V-IZb=Dc31`Bw)x!%yOqx4b}7sYTKU&C?5UM2W|M<3;Kc^8pVay&v-o?!1)F(;^DHMJxZh;;7e$<2bPqNAV0mAzcKg;t(<4+iO$|)00YPIi*u~+ScCjS~T zSm#djZ_N!JhH6``^^RU2!+H;dGI!N#H|8HWYWbo?H?_8N(%IR>YD;g>w|InKo7X?* z5^GS-HP-8z{rCLQg;qNRQM+lo@oBk^F@K9ju*xw-X?zm-silm=q-PmWf9H#uAJ!kBm;t4 zsJ-ApR^x@t)*rx5p6v-CtMSlB#*4lpkNr!Y`dRJqXU)~FVS@bRT@*Nk(|CcG^|60h zpZBwze{+L?b6LxEJ_tTu41)X%X365u%rB^GT+B=_sHZ`&Vg3q%2Eq2pN?SAt-p_Su z5KPG|nRnkbdMcj?Rd9eF3{yS0Fz=uTd>>uh$McD{?tj0Y*B|D1$y?47Z7P{kpU=9w zZzHd5W+yz1TV9guQ#~<+!hA%tzIoewzB=B9&SQET>Y-|R=Vd&!XS`_F>OmRu<`rdG zxACG4=9>-da^0a(!9T=Qf@2(0RO)EVK{IqYb&aJfE&}b_Y(mPejR!&RG zOspB%vB)s`W-lVv!0e=CE44gR%T_K-b(Owm;RGMk$yVTN%vRuQ=I&%&QlYOQZGAYf z6P}GJ=u!D-Q$swT*%WB&>slkPZAK@&)9Txx51Z4|d7?M@7j)Lgd7`)caWVA;ZTh@0 z+MxZQZnKqWgK|*@<4G3q<^hx0N?;Rq<3%3`6M3@(o7yw`v38rYpTWnrerqy*nB%0W zQ}8KHe-Ub~n-NB^O*3#gv+qa&Xyr3Lx6UryL|8-HdfAzL-CrpAGI&7~{FSrnd35@-#yd|mJ4Ay^^$Z-G6(!mf@os(D9iPQS_PX;#TRwCF zFV)S?PHj-3NH>K>KFLa6l9~C?p5?Q4n^RQ$ko90p0+p6|NkdhvvHAOd^YSk{D}pF~ zDYZrF$d0^4m zzDs%H4wq=_v2f$cXQq9g=Tm()&9^yEG|Q@8)yJRr(=;R6H2Hy-RePqPXjkpoP>Oa{ z#?j2HBd zC*@zK7CqoPsOSjKC)&DaN+v_Es3rNQ@6zZfmX8_=Z>7nyf~cOC7shNhB>z~K zXhseu;j*-ph(M)1+XyL|gw%Y~;1Y&{DefU*xm?jUnjyy4F|Nl&-YgC8%UKdc< zTI-hNB{)0Mp%zx5z^8446yT;gv@n4H;e}BNetS_SAlkfMs9QY7l=7aU4d4de0iq3T z!MhUmnD?~$y3hd@SKOM_ILbZU+=q)-;43@X`NP_kIcCsDps2{X52H*Q?h9RJ(L3Nr z>Av&t&J*2#lUi*`41Uqw@k#NEdU!t3eLfE*oaa2zI8qtBF5tBp`KKAL6uwtBTcOR< zg3Q*myBD zQ=Dh-K%k)K#NdOWw_$4JCA$B2vs)3}`;*y5MH`w3>O>nd<8=XjOZ{Fdk1lzJHKo5Gr zSlKS<*E(Q+)-R!<1FkH_-;Qp%ZFwh4Ak$x}}`qxJN`+~03mkbopj7NNZ~xoKJqmqTzKg7%$n&Oy8A9j4c6H~+$g7R_LL z?rF{wZK~STd7@2i#%l&#Kr>_u6SA}!@KAPPhDpfT5At2*21IM&@iKfH9B%(pl zrj|e^+Eiq`CQ$IV7fnTH`U9#v90(s!eaa{Ixy$oL>Opv=rq% z*qaxt*qcAb>sqj5T068H>#T)arDaRIxb=d0u0Mcx{1-03`%wXb&@ch{KDIHK&GQPyPc znsHnF{c|^NEK!qjKaqESWy!^JRk4casC;ue{U-hrw+V$#IjvZKCH}upN1xZw^*1W?FS^1kc(KjXS+d$r}{BC~LAJ-Apg! zll;cBd|uyz?YykZ;=F~sI&Y!%OYj~Jo?+{nne7S8EqA(^^?;e78~R)gNX5RRY^v~% zVin#|HdT09v5E%_GP7OMW^ppJof4}OHsyjqARLZT@FSWF33o~OeJrDEwfAp;O+`OB zjRO&T)M|GOr)EV*A0mh(Px;I)#yQVv&$nO~^0EvJBHfMRn?pgHJ_mZfI-cRkZM=IK za2«)U^8}7c>;BDyn%nmUXn4Oip?Sp6T4D!+Kp*^!H^&feV%XlWAFnL+W=DdYF zId7r$OV@0Qkz30z8f~fwon%18qf4<0YmosJxx^}F?_&bZknE>4FAvSr>n7|^^aYI@ zky)RMp^Ml~72O^0@W@X&4c+Z7KPB4xYr&AHFX}P9n{LA{K$}itT2i|4Fwo5QtZvxl zZiS5+9Xc6W-$u6wV0#hnI_>$W@+{aMKy7(8nu zFd^M+%JOBL#*1)*^)0|wD(myU^7a-Eb>2e5)|{QKvGZr~>|Jhd>%sD9515GOznT}z zaI&1M%h^pOA?V0t1koNXuTfQ%^CUCz3O)c}zb{af_Z*Sx+yuFdP02WQ< zsh;(}41?R3JWNJGZ~CYvtx82SV<=5pq8%ekh71SeP6en9lPh?V54?r9JJ027PALk? zsn?cYCT&!=#ScQlS1p*FgK|hiQz;*0sq3%LQM1PI@VqZ4ZQPuviVYpDH-V-QF3i7y zJU2@|NbZ}xD z&q)KpA5f`qtyUWi4;`M|X?S!j41G^QH1cz>-{gIe@?q6}%{9*Zm(jl1nj5Ce#ob(* z8cl9a(SJ9AM@JI%dAjpFU)TD|b_MVCzTyKa^;L1oPJMM-9{Vs<^K|T0c)HrCqGOB( zxa0AF>UGcObac#Z1-RP+obj3ivc{CepuXi-X*k);0x1`aPg7FMLEdQT1djoS+}BKu)U<_jwpjKg($5zNLzTXX!D-u5zAvysMCpCbFcS_kUYsIAI!P&pM5K zBjGJ0ICeV9j`Vyk1A6ddo`Z+Afg%L&^$96j|7M<#mx#po&90l`ciw9Ulkw|$p@KHRHj z*)E{4b=u{Ne+77WKoqK4#LdmWdP&c%*vr|r(Hb@Ed&t{ z0RIfI8#7;~`9SNogPbSYI$&?-iFT>TQ{ApwZ=(yHVzI`OtXc*Zi0|tkZXrBm1hDYl z)GgYj^}I+v3uP9%%%XcWV02rVy-A$;(~ubdwZe;U(KO*gWlj{8sL?RXp`LheV_nsD2&$y6gCOomr-DT zu_4u(%@zxGYbwWib%U=JlHD`aP);WFpLeLq0?GQIxCp`jzm!&nQN>qpFVypD*Ip_oM^`_=mR@xCK?gT z4~yu+BQDS|UPW1XaL%SBgLAyaydp;4nR!LKn&T9rm)}$?uA4))yCX3w|X)@0o z?jjxXJOrE_2mpP%L^RCxN|^3h4$f(x;eARFjr>%lO$nlLr`n9y47gB{A^Y!yEG_)s zYgAE=uuJDM|2;^8m}UMwVL(Bze+E=!D?F$uXj74ezo8<~rXu4tkAn8xGRHx1Zr&c% zVh)?WU0N?23&t>ga+<-ao8hV36tE6U%Y?+*`w*Hguj-B-5zH8#SS@Ed>!Rn9mrATv zsrt%BUV#e&fw0QG=qt|SqsZydoHbue^fTaWInndZOJ&$^((!X7lnM1 z-*|?j8JjrujMH1qA|7^&pzDPe`E+H*R>>lg%3jTDaVd6nT8rxpj~7NI4*^wwMP~pC7U)46(vpWV#o~ zxplmdxol(ceO^|wdT%?=>Onent$ZdIWFT)z$Rb&dXEHZq6Uj?0&0cD_575OMB#THY zdmwGuB-V3zL0X)wT)Y7)!Naaa&pIm6^i01#+ugQzk86KRC^xU-|{|Ka#nUy+FB?g;`IU?+}V<|P~vW=EX+*wCV$T7szq~!?N2f* z718VjkCGiQX@YZJSHOkeTGj~e;_SBst_Xlja2EqyJHTBKfP>!T4*<8^d7`(vS367q z5VV0qAk0g&fivD(gTq_yt;dZ!W86{0#-gGgCp#hp<<)=pP3gB!PMh3hy@gL`ynR=i zSi9kr-BUd)l?~6{f7HIiOc<;<#r!^)g9fe1{UN#N9J^B9%gN<}m{;OnM{dNL&b=Cq zov{C?{o(*zW}X4&=e&4kLahBHR%HvO3Ki}j$G-!d_cA;e>00g2n`il) zRzG@uC9ex5*h)_r$^ptKsEC)6hu<{qcSG-*+h6 z;$_ZVd9fZISgSpAAroBq4QGS_;e-=;o{pvExwYCWFe37t#{KkK?ZaDxXLPOh#@Eoq zMCUoJddX`REXQ-pV~t>kr>QN0?G3ORr{&h_ay&$-4O#>22LZOX3+(9*?3Jm`Bgj{< zaq!01YPHv+1Dvkap2f;b9pJQsl|^w>(V}?Y@B`M@YzNSFwfru30A8RqZQt3b?M=`D zd$KKFrM6)md?548T}*JHdLtY+7XtG(ZCiS+_TF^VZ|+jGYj)c?o{yT{b`Cn==t`yk z4CgtmddX`REIo3|wO$g)nW4)U4>MlaOz zL?f{68#TKFfDNLPvn%YFhYH&9@9hnM>>Z|rRPP0{9h~RsKyxUN{hRZg1{$cpSIv1& zyBgC}1C{o?M)fjZvuN$q)sq?R=V2>X!zPC{s&QwcRn+2!tjxH72ZcW264Q|TbPKdt z&GAxtcjSBJW#>7K=kMUXfTb9F%4zff?BXqRN1|ce*mCG~ljn2Vd!P^YJDTqS`k|Jm z8hc>xMtu)v517kggFX0P^uXS@pNAgkMUG3g;W^O*Q9$V*e-K0Y3(SWfDG9p!_b_bV zb)M7g3An}>wob!V+M)Nbc&F7C%QkBR^eZiY$UQLJ7bJ_9%MpKwa+B(%{o*?XWb$je==%dW^vvMr#s(=f8H9Wjy;@!HZ^%eKg@t%7xR zW^IkSjzGa}GHaV)6?N_6tm3gqMXbEPUj4M^TD)GWtGZLLre)S=oK?tG9q22(g%ffv z3{0+z78eB>p8@0Yp*a^PakB2rEO>f`h6SK1y#_EoGc4zV5n1(FR11ILB6>|7G18_e z_F;rU^f}9}s8lxE2^Gf#&L;rv*LwTy*D^C`@Ro%tmTgh+P@Zxwv*-uXe4YZjRJ`*t z9_le|Sbff;>5|90@-4=^YCPPQmrMwgcV1j^vaI(kIWF_^p)TKY&Mx91 z*zvw~9^>xzZPdBsxqQ!H?qs{X^RhM|t9LIs5xw0DhhzOqUhd022%jIeK1Dr2voD0B zoBET^pef$--@pMg3S7?}-FWSzI5vjrXP_y8R1tF<2yx_~~4@m!q8LwD+SNtVPCm zt8baFzW>~=)CSxZ+JC&&^ND8PK6#h(M6>T*m$_efKE`!~{xI76#qD_wp6tHJr}3eF zehYG|KBr+{ocxBmp&iDFQmNfHoOz^7X z!G?LMZ0}Fztt!#hmf4Wk!>51NuJM|1_ot_I>GC|`4e)q$_TBXp9(>7$SeNb>b{I3h z@_Ot#`!YfZBY^|5O^lB_kFo3Q%RF9P{5$6{j$QmaMt!LKo!}Xb80g>geCKqn_WW=z z&pe;gYKy#PJHXbe&o*|zlKPm39e}lJ+Edb@LWa1rmw1Rf`v)!@M@#R%(E+hmWr#cb z2esO(XW@O?@t)7=TJ4YbqazkO&uJ{x&W4qK;5?_v!;H}`9_i?m2!pIsVwCpA+}(Vq z3`W_O=W?g~n`^pljok`%3f8atnHOVw76&RX?wbPi=}ZVsy%n7j>sL>w1>_EJ8a%86 zHhj~|It{D11y(V|c}`p|TvyI`TMFmgC9EYulp1jh*K-tOVNc zJ&U|%!P@%u`3x4q6Trg!jWml_2o~$tyjj}a1@XKnvj|Qw_L5AflLPFwkDZIgOYW6R9=@od(!VuxUBW^En-0PbRNfu=HRpFEoP99}i4mv8LT`P+HTPi;kW- z5qF%KD$(}o6KHpEi9MZm477i9p3~rUR4N~fLF=?5>(ht%nnh;o*B3Lg9bDKo*Dh2e z*01~J^=qNW#p|IEe08~Y>HS6^LzrwvYw3O<_MUJ@JP>;i+z~ftR({O$IqjP>+KlDq zOm}SLn0>s#e9fYz&uRHnBij7Luc?& zE7y0P)393nEj>Do;rlimvrYS=RWHjni`LeqFJ-hl`nq(+rj64y)}{M(x-OluDGFh# z@*@l(mF8)!OCx=gKh|njM6f3MlWt=51D|)fV$L z(*wt8T{^{k04~4f3PgffHLNPm?`{Vc@Jufjp`Qv?u?R(k!(1~qO$)RNrW!_47Zr=p z?VVNDg@Mgn#n=2QV&zX!RN=H(eOs|`#KRl1t{jwFtRlYS!g0ZCnFZ~z`gxCK)@E^P zCIhNMdKR30cg_U|Lsr=$yf<0p8W-Mxta7~!BjUoT=m{G#2;;ae-H+PBWxOAdH###b zh|j2VR{=I}M_{D99y}~er*Gkyrz=1wFBYcL;eo6ycry?oxHiZ`4}6|#@SfmZJl4bB zDeG&Cg=CurrKkt>T{+0>yOLoY(UTg*pa>Rs+_a52U)=zSh#QSXLatXiiRJOmFpWxgF%b2F_?mSi?8d$yxxx*Hn4lJQ7!vbAdcdnzZ><8g{ ze!CINWx&F9s9iH)U~r6EZk*1&=~=1i3j0WuzZYbeu6q3w@;?bI7dy{s#H-jr=)b~w zPNV9dvTEl!t>(yEd%X-XAMu?=ELQ?c+9(s2oz^(8=c|lfR|XcW8WNVbF^0ZhschcE zc}@f0{7R+o9nN#QR(s-yz;cuGoDO{GAJ%91b_#sPTWfqitn$w@nhWenx3>T2bZEYE zDdrf&wjIMWOJ-+z(exaYxj)1)8sWgDc;L6K^PKi6^}|KZoGhC7c_SqH)* zZ;rgRhT#%pfA+oJc}@qE7*hu8rhsC+wT5E9v(z*HUR2TwT;0CO)xnq1plc%< zT^)^1uI@t@(cB)E;eUGpu5Om|oW}V1FSzX;o#!;6uxjTyt>(yEYbf@Mvpv7js13|YP`V0zok*w#8x7JYhFsGe= z{VHkYzW^nkz*Z`=5H(`4TpQK-SV2#l`0;?>X&BQ@y6|q_~x)}95C)W#h zWXid}KzBbLnw*MJkHZK=>@>W?8OVRP^PEN+rknRyM?RxbAENS()=qc_I?vLvT5(AW zUTg5I>{|DX2k)o2lFOc%kDeLE>Uo{#yX?1A`K;VGV%?hirU$bk zUgd~FWMlmi{pB>=9408utxltFEh!{)boeRaH;%-9c`!)3Wtp3iu<2G7c_ zeLr|;bXsFS+|PbUvC;Qvf%W|$R?!b-Ga*$=%iF~9z=>{*;fzTcqcz+A@* z%$9C$ni4o>FB4L&BW91GPH)8g8)8mD)HJVsiz~7>73;R_O-sxezlJkraHoM8PqXAr zop#Jy+~!#7cvob6TVM;Hy}m`syDfNDcJ1}-!B#vT=vGW1za{1rZ6U~Ii(77*=XJ4m zUE{USu=n4h1a%uzz0R(9<%dsKEt zqn@86=ClC4kRt~VO7a&YD`MsEtzX0Xyw3O3W20qBx&ht5qs(;F=o#(WgBX8}&c%b*qMlgROm_1n; zFM-LQlhAn#(<*{b0}wO5)3w?IU&B(|9HD6J0DTEyUSgf1Yqj5D1@(H2Xs5CJfF|Dz zD{(qNTVNtOKpU?B{gJz`yVn1p>ZEvsb~lLA?PIAEDqA3mzyrYc;)Q0iP6O+aHGczE zS#d|eyY$ZvjmwC3sNc&3&(guOH1e7dxsVudnpb&{$9oB5*XzV{>8onBZADJ`RG$bUx1M zK>u8QK7MHBnLf^Q8e!pXQ0|YM=d{`?^Wl*KjOX#2$;)*2Yk=EA3yh|q`6yv=Ja!R} z_xVqGS6iW#a%!@HYY!7Hs|ox&vH(q=R36WaP8-0Kcl9 z$4~D)eWUZ7cH4e(f%9nFPcBfsWj@&C8L-c3~qwT94Z+erSHjQ+%S<45SV+8G)%|^SD%XlVV6GkCB=48;V zd$!{(ArthotY3ZufGiBHWg|Oxw9ERzj<<(OPt4GkVJ7!7&hvEeVB^cyoZZ)UZU{T3 z#4YiFgmx^6x5$oG66f!|R1j{lzlz@;NJg6%&DEWvryovXa+Ny(^u13U!a2#VPw;=R z*-scUd=0Y%zx)Xm@qC`{{`28;ok#!qF!nR7Lk_FY$5%L?KF@hhd)a4aE_53C;27kio%XV-Pi1%%<#BT; zu;ZY+e;syg@eKTN&}Kt62G-!+OIb3H`R8wwd8GM8VSOS(wArz(ri2N14F6?@&FzyP z<2E~vRhP+t_RMCZUCCuUldlP*kdNkyw%fz5=Qo0aeB- z*4)lRD#LD3I(YQa50Te|$YIBnxaHg&Ye?d&vyYaO7~TL!PeB$74Nu z$H!^ZXZ4o(V7q@tKAZ3|P1{&DmiaP|$6@q7k7%cPGJ34`YojXRd`H!NXo zqWxR6*Sz68ewUVX_kD0wN>{5H6e1?J0))UZlk?l zpWZ8}NaEL$`%U(qf7U1&caB^VD?9wE?0rP`+Zz!8z|b#T4{&&3ronD@iNS9}WQ6DQ z^Z@@_J&#{dc+e&?*qzZRdpF{MHqYmD*n3@l{)yBFhcREK&ECU*@)N2|H(taB;_>S? zzgp#GMQ?z$-_14Wi8h{p1CY&fm#N$O z*=Dy!oA5jB{c{{m7KTUrs5O1Gvf_RgrnnA=OYz!AsZ8)9U1?phSxVgUy==3RIDg2X zB8d-AQAGM|a{gJbWT3?d7YF*m*M<38yXjTgBeIX)I6$$VFdy?(dH*B=Xn=p_2nWwQ zFQs#BrT02Tn=U7NzLM8|xbsw&KUCuT8t{ifb5FtdH4qa7t@c@3`8K;U?`w$e_i4!9 z!`l$u4{^nOTZiHu&YCel{ zj`swXZW}b(@xbhRWfh~>^t}*^s)X|U;DO50H@#a7+US6WJ1?axtt)m+iCZpcwB!8U zie$%A()L8MG-WAWkUXob(7rc@kkIlZfwBzjo?mU2h$8fqG$GrFq?!1(4;HT8{ zx=%;UjJcYZXxg*K%)XaEnq^g=@@@7j*k{<7XxiG+6<(j{P5uS@G{22^hl4g7irAoz zce|HOynFLIvi9Y%iLg)FY506$GCK}zN;f->eAXW7Hk*w$B!lrxmM-{XJX)-D>y_=8 z{)NU_Y#@_Gf84NvtgN_09ZUc0U0~22QJLUHy3)F0$CS9```L~qaj}6ciHi+n?1oss z=1=w}qrET3%sYFo#l>=Pc(4X!f7~}fv7fF5(2D`y_LPwoI$k_LMIv9M+rGe~&J%4N z@?3pB?&mK0yYocTkKPq_BATD;OW!XHTJ5v6(v5eo*Qc`d!P-9-ZFY5EeY@Plm}~J2 z##zuDGjoPSeL?rbd@vt_YPS_+xc7TvC$hfIrV5a}!wu@_8TX)LPc)6o>uV0KX=o7YY{}=h6WWbaFpxAfwDVwKG3G{2_KTi$@k|RtLqoXp zQo7Qb8V4{c*AQjy)~8WJ`Bl-Rp;dVbFEz9QM8XuV&#GEat_ls|&P(b19EZOZi&GIn z^Rpe&nrMEkR&N-IR=v%_H4VZ2S6a@=Xm^5aw6b&Z7$OVP+~V6iA47}JLHcyS{f!|r zkGA-Bl?h&?n}(3qtjMk*%G_M7F}{}9z*t?aiE)qJ0_n+_fr(m7}`rX zVF4!Z#*1_Y^qNdWD}S>vtmipVw4B$7VrCv2>iIiAVrOZ!{FU` zk#0S2yyk|p_dI3pwsE7(GtxFi>iHY<*eH8`2E^l*|F1$k_WX^}^SJX;I>T0dz*)5Q zyya^ShV{H{E}oxJa6=F_Up%r(OVWl%R?3Pm{cM1#?!*uoF!)%C2IP;YaymtB{*jfu zl5OFBqEY7j(5j00ij%;yVV&AMKU%cW##v-~k7bzjy@CTP=!mF>bfunn9GGqQpHnSh1) z*MibgU}mH5=f~?7wxY=0h-R^h<3+I+!Yk3Jc;}^brFBgkwoSH4qs;m1BUOZ0d@+0B zdJW^iM4sT^HIT?V|0lDmNQk_|A?^4J{4fceFfY-{-z*ICK(^&@Q6q}{BWbDU+Zuhp z!8i>tup#Zgk`_JR7CnzUFQr@08?QNI@o``qJN+7E&Ywa_J--i0$=W(}uk^bpz(eqJOG~eX)pT$F&piLWAwmE2~4O=+R$jGqRwJ$RkF_6~3oy0(% z6-5vzCGT& zc&>_s$dSI|NmyhbVRinT|wCZRI+N9H6X}0*=EFr7l`8c1qOfSyLkcCGP(;EU0 zWyKwb4lnvTMF#yJ%&RiNvvj4A*TmQ;ByRbEOHAXD#5wFR79~C+KZnH}%}A*2#I)_7 zK6G+UK9o4XpD4|KI@@QTK)_DnS+bje^sCO}L#Ww!xX6c4v!9N9mhK0){C$7Xf&Pg4 zd_0Ia`x56l?fKfysptLeC$-w8+c?i@d_@?&dQ}hSIqeUyB#Y|i;l)e0XFfcf4Z1gm zzL)g}1f&_9w80}LEuzCr^Cojn_m0f@+RpKOE^`x_l`&!rRl4Vi18U zf>Y-K!;2PY@unXfFb;N}r-MgBHC_`UhcQy(mWy3tuD4~3ITA|}=SN8u8DsvnpJa@u zC6i68BA4v*`8=DI_Q}?70r;;tP_xhH!#-25A8}}9`W3Lx?V+OA2^M*2 zg9tFZjPpEQY2-B_a@eQsrCgHjQxX@4RwQw8Xywzc%b9rt9%m#e_Wxt;Tj0E^ zs{IFM3`vp9Cq7a$B(M2bAVf4%#7AmMhNkAVi2#8VQ63tZDH;J0nvWSJpUh;M4+gK| zBN<<4I%8_+mC?-5z-wMLKr^pbne+dy^6f*MU#s(8`tT z*_JfxHO?sV8ZN8ky}ciNb`5!?8B;IcmOP26mm^M6PV!uSxhe27%Rij{%-KGEumNwh z`f+M(JB%_%ahM;YT>Uty*KirN>oSX@G|nK8*h)Bs`?2ns>{#^UeR#itxbnS*Ig z4hhcI8=__!JB%`?%~Yl3UM9Q}BAXwJ#62%7`f+j?#U)M-qnIBz_R8;(_Hd`26miyB zv!a&!adOZ*IgB#rMt~o&&JO3i`oR;s| zUaAU)j~T80WIn-qyk6rxX&d$ArvE~$0p*W0p3y!TtL`I(rp z3&awahbVFoaL!H%G;BU7G*cDJ!4n@>UI~%Sk4561R~G#^zDAl$JT49bx*sP|)tz?d zNGqI`9P@TRo*OxC>c`k&;&-JRa~9 zS`JS$4+vWQSmRjKlLM$X-Oje8aZq(%Kj7yyd(C9gFnytir++G5b>v zqs+b<dkg*-v^Ks?^K9tklpmKi0kFhVWyTI5~{s5+{dIa3@B#%&vO3=(O>@ z`X1X+?B>34fO`)rdTDYPWorW^db%DheuCd~X;-n$Qj0NiC`JCfT-NGy-zCp!Rfy&g zQBMx_aW4V!(`c#J+?Q>gC$ZHJfRJX)TryhfInCJ0`;1Q0uUtOAo*Y#1{ROAxj_~D@ zwc*cc*=D>-aYP^TJ`Nr%AaIccPWm6`X^vVuJkYvxdWQDo^p2a0-v*x^us4_;G*Q zC*1@V7KTi56WFWb7v|t5FldCGIfr{2gKOnp)}2_c_eU0lAG^fKCa_DKYy$7aSl*Cq zvboa^h}?R6Zp+UZ6Z;wi*l_NU4RUJ(5B53JLw zkdrFw$vLQt-Y3s#IS1wQfYaWW)bx6CV_?ph%InGZ*{*^?4fV_r8*npRd0Ose!YiTWDSq%n?-_luD06&VrAI&OKY7Bq&O{M( zNJ8aCiho)~lG=vl-o)x@ITxUQlS7^`zPgveSY956-eMhy_B}5xq8Oep#B$A#tG*Cx zz~+J6Ot@-=i7YV28H{n{vD`#fUUxJvGS}{2lsUfYl50MB{x#M7fe__ZhQl>SwqkPSF^MdM!K^TNVbPUET7eZFxoXnq8= ztr;f8YCP53nC7+I%Y;`>WZoy$t^Y3-WgZv@{B~gf>CMAL^YUVU*?>t!mYatH({I?Z zoIdZH(Bkv52`!puy>c*A^P(<%5K-TkftR}IZm4MfpzwLu{OIaF--!83HWwOXHD%GJ zaWr8x+WLXz6q&qoB2)7sb8Y{k%tPaVpKCt3Ew+h?C+LPk}K)b!zoFS>CMt1WE{XUJ z4dglf+1qe4M|~a}=tc`Pxkg!NY7Ge`J%3$9_Hv8^x5oMn$ALk^o{SuLZQ4~t0Z**4 zp3vl1{=D4F%8JZ!ATrnPS(N#O7zb{R$s3FV6Zr**grQntjmZ?b8Nc%9<@!05Bgu1G zHLvx$F%EQ5dtIQAh3FEjKjJJ_4_})W&SH60{9={p%Wz#?9d7Gc{K}t~ds+81FEZEu zTT$j%i1)yll-1qr2V)#)1Oi*oVe$NxTVnAnV$FWgo2bNjxg6^A1+ddzzk4ur<+xW7 zMx5ixVLV!JAce6TM8+`W*&EOT<57cwU-|R$J#NC<{&e!3_WGq@(WTi}0ta@f z4I2$Ntm0$Vua(Px_$q4eC_WIq#0U>K@_bK9- z6+zc=^e@;*am<38LpH$C-*Dhp{=8hCJXm7boEE$Ip;)ICo3};9mG9tmpJjh%fmw zkw*Jh-#1UrpZz1zyBWiQ+BEG6pJ<0kt?ePmxSp@(s4Vu_3~h7ph_m%J~B} zAzm++smfpW>9p7Hrrk908C=AXEC3uwazEYtN)f*c9D_H&G1qY5SN^w)Ast=P0}w``=T#a9Cx<^+*=Y4SV)%qR+PE~eP5iQ-!-pC^#?m`y0Nm+yWr z{O<+woEBT%ATuidoEB`QQ|yQ@nr{p#VoM$Xq4}M zMT{+{n(SCF-|(|*N}SM!lrr2&?2@6V$O4HNt{fv zJpkFU6>t=b|hs zE?_~>biC;t;5G5vh!(%1%(7+KJkgsNPs_2nd_!_}OljbiyA&9oYD=YIzx{j+I*se; zb){anY&jSgs2x_s+ZwiXyvZ0$@wP%1WNugeLS!+yCL3NIM_vxR*CcqA2Hw+g7HJ9F zl16>8@3D40rTx0X>lR+kX$}ay*cp;7pha(oeRs8;pV=Gaon8~ao1(?zluvdWTV{I` z@>q^D9Izi>MCr6`7R~N94$V~#EaF%fc5@u_BkxQ$y%wzl4(t{!dMLp$-*C(~99qu% z_I_?lz6o}N!~1}YM!Ow3wE%*672XWf3+fBP^4svi2Z=40n@qQ5FD8<_hyw?Kn*~F%DePDR; zD}P@8MQri^>?rb_-uhX@zst#UTAn8Nyu@k0ZYjLuCY?QPM*UdyQhP{_wZ@*OZMZYv zViuMjR(Q3z#ViZDhC8uTL+Z%SB)*tErJMLDZ`Vr}B$NcK%Sj-(`rr zsOAC&q4)O5kDl~AoAb%Kcv-!EIUcj{dvT7oW-}8&1ihOpPZv~HnL=-eoq(nHvYykT z^)klPE+ zli7UTeU6g#g!kUg)P+7VD+dG{q#NIr23;q)sGl?+^7@kM;&!!j~*pN95Y#0EQg11 z$c#j|_L@XEoCjCl=GBF3HzC_M7lBJjp=*mHLJIHkr->9YCPcDde2NrU0kOQa6uJsH zGNkYxKS`vJw`G18hWcD0h2>Y;JNAWT1h;1*1)Zv`kGCPO_7S{6WNwss{w!_0tfU?> zXliP|5eQt`)YY()s0a$KX8eo2T%;{wO<7gtZhv&hvMcQ~C-tn|jQ1&?HOD+_j(FDp zt=reD%N-lyxhSd2At@1~&iNFVn`16FM;AdQR5fPuK+17k$l-maPPaSdn7e7>bV+oW zBTff7=jw<3O35*Za*PZ)yw4ve&i^I4#_ZH}66c@$W5@yLpL>D04(cMJ&YtIO$P)+u zS+6K_=a)8KR?6+hOdd=O-wF&SZ-vYCr#y2CE@ym^8v|Tju8jMSnRK>={BMUKd+?$S zJ0!{+V7xsxG^*G2a#36lC?e2N^`czJ0#22zfbLk{b+ zaoa?WJ=ss=7pu$BxUH9$mSYg*I5p((KCepTkQ4uZ$7;EeJ!m%5#7CBHC zInh-&dmHk$`Y{f!?G|Oi^)_Bs(x!un;d_C>R-t9wa+U4rF{4o%S+0_0mrd_dWf<&&DC;TVp_S~2v=|UZem)Eqh8m` z%Zf62-+G;b669EXbRvgrgb43D z)#X@xw3nBbV-V$-9CqhN8I!f#k)=23*u^* zRoqMYa4(j3NtF8Yri?oaEqd7(d9eu56&W@L+T)!X`6BK0d>voorqr6;m*dAQf|flx zeoTvdbV7^y+FutLgVqI^@^pJ)%DB;EZFj*A(aC+2R-_@=yb+rF*A>c9qDksC=!E#=g?6%Bj8}im2Y;BPftveVzl^}Ss z9Uwez2W*s2j2$nGx3wf12i*rUhip{WJP1*hkGJIXof0}##v*=jU8G)W#ZI{XN{-a7v)~u z^C~FfZe0BRqTJKJIqKUK15fXmJYUN?r~e2tjzE*?#xq*wR-RuHzfGw3HK`Z$XTOzo zPFl{kPQwX1&$SribYJVMtC-InedffmFx9kiQ_dQFCi{+!06 z-<=PiOP#xr_T>|D=5fR;a} zKQlJAjhvP!_4H)cb6TU6_3QQI8tbt3mOs*bqMdt-PIG^7ZL`#J+O;9Pt_6g#XCe@u zy6P^V=@-J_J zL3Ay7PJ8{X%AW@b!(g8Pk*FpDFM&iK1qK;G5}}qAW*OE*i(61E_nGkL^!95ZuMKdg zHK;9PJ*RnT;gzw0?snHEZ*p}TTo8AK+y* zFkMET(>M{yAYRs(jv7>7P#Cl_r+UX%(v7o*x|y-jm~LE0_D%? zep>^>!{j-ww(#*R6Ax&$i}JdLfn#IPY3QLgdC%)+*f1VYIX3#TlPY6_HFb+Q9~&a0 zj17@Xe&r9_&RYK2_hM`~?e)9rS78HUn8TSAuKP~*+p)j;m>KWFFdb@2Yfrv{!lpjl^dm{-n6^Ob6QQRyfP*otR_uf z7V9QWhMJqSIMmdn7rC#B_+yijwHN4q)t2>PvanO?wqzD+*zZH*TnC3C{}ky)f1$uHxW!;t`E9d zvgEYamwH{3KSn7r*rUy2J`q^*+er9wTiu;U%AECdzDP+{BxsC_G~yzf0|t$w0G;R9 zh;&-bV-sBk?{0ww6G`9#t)@zOXrnxB+co$MvP0B-_S(hNeBrsO4Kd%18%%y?z6`%R zpjamfGY9VLsl{&;>Af7!B*L91JwYC6U7^{CblR^W^}2>BOiEn#%yeqfnfc_G+waa| z;C&*0F-VODUWg?AFcZHrGBx)M8gBwMShziDw4~$t;>2h*qr%rWHEFr>aKm2yoK};j zJhV}sw(XiqXy*OY%=T77F>@ax8ox4fv@OAcna|xSM(HLZmDj{C0`GX7{ZSr9>A72Z z6XR()PKzyqj*cgfw4QG4Jp0e&;nX8&wAE_}uWOjX%*166Xp5Nz1S~cEgB(|G<_GfI z&^c>){wj@h=*YxejmHu(g)5Kf~JRzA8KvkE#rsU;5U_Hs|G0u zuXk=g*5kD)3;XDr+QMt7y5!+<_nMD$)#Z8`o=?}@7eoKzUmwFQMkX$zw4VD6FW)b` zeERSN!*Ii(yslw@>G$(_X)v{LJd@e3a-PbA%+P7jKnEogSNE)Ao%@{cAM!n)vOPb?UKK|ZDZ8s#uCg-sqRcTD~AF_B|RY?5NaIK_tn zI%gi8V1g|ali9?}@!U-3R2}R1u%FR*ZYEF7omNcRw#+zTUT5zR6FY6nlqH?@kgnp0 zSHj$eru$W49L!>KS-^(KPT%keI)U12Ai^+@Y^;yfPUoH1zKIkMGf8B9!U zl1I=TQxf(a(}qhZLys6Q37f}w#e}mns)n5nla}Ly=AT52C#~m<^MnoOj6oYFZCeHt zXK{N+me>g=FeS>4A06XKW;aYi zor@kvKn%>36J9BT*>HK|HSzm0z`RN!RS+y|6u&NSqI}@L0*uoKyoeEEkS@k<2&aN23LV@QOgz-}jxw7#6QbK+g(;pL>D8K}pv7habD>a5f2ya0$fUiLB5 zpkM&gXlB-8P24@+5}-6FP!Ne`0+7+n%Mpzq2N(nl0Z1D4?n6}5G3c~kqsw4)y6N?! z0CNn%q}GyXEz`|~g>fWc#9DIGs$#mi(3^-rUJd|X1(-JBIL*bdTSgYcVi}!oE|hv* zvW(6%y=DZMZ!&IG12d~IjwBWe7+DKcfSF}rW{E&izWMjv^=fKJN~-+G>Y){S5fmW+;AABn?^?=+j!sb6OVWOdeivLyafk(e zF#Yt?$4wbGcA(+7rHCU*2oSslN0s5CI8FnO8!K^)hpV%R;jnU*y?=rObia$>VKd2d zTCmAAx`&Nf+V29}VH`baT$2HXWGBUztfVIZo7`V@8_C=*aqIKi{BX#dk^yD&aBK>l$$(751wiZzw)P}FLTKg9z2<% zlc(21J-r@&*0L?c|E7yep0W3C$e>Aa^cA#d zg{of_q3K$Z#c2S=ul#wr1&)J|EXbZg;#a~#9#zG!SQEvF zp+3%K3KV~06XNjlz2JZDS5ABVuKHEwI46!ria3&SemI4yVh_c!62-Sbb{pp+mn5B< zI;ozc9IrtN97cQnuHvYSyS%ONSl}3rUSW@PdF-3jP*R)~!A$ns{Gwc}$+;YXCO-tYvySH>t^}C!GnA^AYP$0Xc(?g`!7n38?!ZQ@Ot8U zJbW@aPn>#wGs~{I46K{;`|>%fH9ud}^H|nu93MwkoONM-WTodAyViiX);O{n;ybB5 zXFv$t_Gz9O*K*c^xYk@YTpVAJsHM1YInafwAY0Tq-3R!M|LwFygQHJX@FJRjWo~|=o zev`Si*hkCF#-c} z_ItR`IpmRMy@n4e>#3@-j1w32wt79=`>o*Fu6%ku|Ab=&Zz`{+*TEjKMhI)mYa7q{ z5MJX{@*0!2jq{8*FS*`eYioF=Z39j|Ngs|)c#DrDZ?R(Qp8LqoL+$_2eR_e$dsnVm zjxNq9#=+aez8)Hv<)^iBUx`nT=B)UNW9~kC$F+NlA4V(G}#<}{1;^>|a$SL32kBUApt{6gYjG4)O zAbGctPkixF@7xD2&m%$Z1G~kw%m*5`%4^kp&hU#fqIdy9b?yU71Hbry`2}h4ME|?7 zE!!Yo`~t5+e4RYftk<|z72f4lcrz-mclB}TSC7=-i$Y3UzxT0T1@A`kRIVFQPy8a~ z-Df;&EA`}4-Rc+CuktQ8p2V=C+Y>~TyeqsSwTS8J>m2`cMdcQ*{$LLOQ87mEt$O6%STo*D{Jgg zTsZ8RPriKho0;uR{5}|FBMlY27*UqAsl~DsuXp92puRn+D$-Q_;thD0HDN|J9%)9= z+-!)b@|`wSZI49t$c{98SidYc)muGP{hp?J?W23Dm#%8pQ}wl=-!WAst3+3QlF|6^ zi0`ZWBMUk_CgURe#{!LXmR$nyODFY$(}B5Ol0}E>C1!a)t*uI!2my!05`eTRVLXAT62_YnY>Lw{xSN4f zUO6BeOmPDRPnHic4TA`l$rP8bnBwiWc_K3`hM1!cRyxEMy#dK#hI~GgWMwwZ(lVQ< zSuP(9i#drj&D=7K^_-^~F`l=*5Su5rU(I@?5#3IQ+gMa3jbVmpnI|$zTOTHi45yZ1 zCZF}e{>%c(D`NqhrDXAnkmjG1(}@N1eoK5dtLAWBL_ zhF)xDAf07bEREM@lg3)$N7xJS9A9bbuQ|!dn=MZ#uN&B8=B}#^Z0-aP=U>ChkwkG2ejeee#^d!8i<(m;bm@6HZGrnDim2|#?W8501zlX~4iCev8m zCV@s7S=_ZM-bBO^e1WHcph2K1BOFs;GG`J2hxVEH|r_3-iA$i zWw7Dpk&~yNHLZTiAeq(bK0|nty}XTKjP18Y@m8OF3QOMV<5O6${7F1E#zhXtMINHe zq%o$>MZi6hJkrG0a&RS2rw`)^-j;)j*Xyy|rWdVOMhB(=RY0$>uRw$EE&4FV-*9%{ z)Ligf)IdskT37J{Uq0pw-Z?r3P0rUsgt$rH3q&EB2x${-8t$|=jb zO>=O$b>ofvxpfbZ>BNGIno|4$-tBMXC!J-w0=}L?lO~Xs!^u;#!3AUpl2-3sp=sF9u)|A{TuKNw6X8CL)aih?__Y8z?bpqG*~ID4OOG1$iYQ!5NY)3KiNRvOP_5ll-TrYc=#<#ia(uu(^B>$;*oSkLt$y!PkF zYd2Yx_oneoW^Ma|wN<>`b7alQH=`p<^68GeN$du@*DeXSa@I59R_?V=hr2s#Rk*u5 za^mjp$VWv(chQ$4lHo-;lK!ZRZi3(M!A1XSJf+PoXOgGxGZXd1MN^kDUh6Z(daX+; zulLkxaQQa!NJH)7$}d;edj^T+lBwj8wt7buc}rJS;XQ5F6W3cpSIK1&-ZRECnMH=B zPtygKT3h9}=~gQ2CEyy;hTtn2e{`y5~~57}}gJ)eF%6oMkT{w0AB^DT zE)`)Z4}?k7bC+5kj^{4*M840J$Hoykt7c2;n1TT7nh0^E5h}#q_pu&n^PeZk^Lh`% zW0#ojNVA@Yp9rv+J`HI|(s_Rqql`7%q(cG9l z-B%($PV>br=pLJ3Uq!~cq*)il z&8TD8Y1^q0N<1PY^UipKIy$BzpJXCGtJ&NXrd^=L4`KK}7*A>NWRQ(6@;tD!O_n`_ zRpOFUS&ua26vKPoqUHE70vzS3J6Vr(mM#CezueVnwr#WP$#vRJb=)QkTft!-a9<$;~k|QVJi3RV);< zL`@$m;Z$G5UZhQXq)l12a#e>p$N(#^9JmdpxPg$OZmWDK z_7p(yhov9qQ(T_zTpt0{r?@1yaZQ|>r#q>OEd3bQeHYg~o~RYg^@iqp<7qi~V%k%S zJWo(~9efcA$%qdz($?0mhwDi4pmWlzNx!FBzuHF`E!ym(i`T7l|LBQmBuQKAyx8&k zCcUxkg?y&*8awhAY&8z^+Wv`ronB+P2+ z86HsMNzT+fNzH?CVs5)_z{a?UxRIHgw2fdht@Hl)7yrgK@>Qh`tgUG!0=7*xJtn+X zm{CW1cg;8iimux>%!mlA7|u&K=8vY&w7;9Hz&EN{7qY+|JzXPhYr4B=NL|z2g*r$E zo|;P@X}EG{q+F!w%I)v6o(ze03=eT-^15Mgoqe|pyk_v$KH;{G_QgD_^{^&rTl+vm z^I_c+C>`l6dl(v6(vLjS3~TPn64svl$dJ95AbZh}DX$yIbaLB1koka|kq5IHn=;xb z=1D{avKc_O0LW$ex;ySdDezW19sw(wvO)SsH=;o@Z&b-`iHBSnc<+{U|9 z5bUx)p;O87(1ENuH3K9)&clOn6;!DGzn2xgG%tVT8=NwtS8E{#IO*hfYF#r=2Exinq zybejeL=>cf>W46kITdN5XtRwGHPOpNL0%aX5ydccUHeahkj>G9d6#xYd`VncJ7-zP zW--&j^Oqn^X^r)AjkEe6E3T`5ud&v`_ylkMjM4nqJez?Yarx$(BTw8)n!6zQ#o?eA z|3Ti8OVMqA>%M>R7JlHJSzB#`wzy8mW|h3fPi5J2myky~%kF50&aWkpG(7Hdc+>gh zkwzcde`P)8N!EnEyzL#oMfU!&@svi}3*!zvX92rmA-Zx@<^MOZmhzaO`f8kZAeqzjmFcqCD8MO zYVs+wspF=huex0#E(qd!X#Ma=Iu2)dP1hGfH*2DJ4G}Ic^jzXk~}@iexxC3 zCQp&zw1RjkPcW1~a$XYQUXKVj41p7=L>l3Qg@0*;d&5{C=XU{XoYfH#?w?lcl$_Pm z?{G(^oU@Xp!sm#Sg5V<97xV}x(Y?dws1BW@P%gYvyfbU7ZIG_*f~7_ad8EC56`ozM zqMk)5%3y6RVmj}^lOsBk#*Q-fCLgoZmNewJ&6guyZoC&wX2F4!liE&r9~;kP(d%Fl zAj`RSYs+gJPnSVud?JrhyG4`|E5ai>4vZ+}R*X+o=T>|_<|#WJ$;PwFX3Kf@`yhPr$XUBM|bs z1H@w4?nNLsM=Wz7NkT1?7$U3!xf#DmdfILVOx8QdF$J0#&Q7>&**9Cp;9a?4cy0OkAS{TAlm0$DtfuFI+9 zk(QIt_|DF+$s;YZq~Iy?wphQx^}dYj&9mz%&9+%;4%ygnb0M|}XVx~1?o+Vhh)BuI4DWmW%tpw_I#MdAMI;^~guRW}`e*l_nr-+g1< zEW39cUf=Klg}Y`93_jPKz=Af*kzQaLeajPTrEz-ix-9$T8MY;jwz!5XiZpqB=5`0{ zKs2t~qX;%0@yWq%0kA&SD!@(#*fTZ&`>}zw2jf@{uzvwq+sYyhus;G=3}zXTqz&v{ z**ySkpaeAiOOas_doLnV1+otf z*&b5c%Yp12Aj3c5kp{A}fov*yqz&1J!YhkRPe1Jy$dE^>AC4-T>??vyqL==qBXkrR zVM1K>6)B-qeQOPw@mP)#dI(0Z<%*<%?3+M_NmJUAri1pi2}zt4uhQe>h{>xwT8S@p zUn!zJrD(@Ng4Q#oigII+iWKBFV~% z`$ilty~`hrA*_xe!5V6;yMwhqt~Cq|hXo7&tE}W&*wGMH+oagyaaP* zTnhnTSZ&t_Yn8Ef2^JRL+HgUze19SlRdOd>Yu&`CC6g{#tCj~#A~RU4p9z+Xe5o}m zSiaX0%F!_QXE^Kh5r?Z)MTh3};x4P6h7Pcoy~-zMrwS_z4jg1wtdIowOvnMo9&fJzirq#5tMBBD7_dg~^#-nxm=hbAYYwdKK+DU8Yu-l|dLts0f|Awx_0Fdax@)8_#M64kHO zQ(a;hjm2)!%jA(pTh&h$p6Qu(z;4kA$N)8sbQ(`CVyXT1rEE(YnczKG-)uu3X~?27 zk;m)c6$4ku2Vlq}4Q#3(^1R>0_agW;TRo+*SH2=}kY-!AM+ML9=GS}Rxh#9lCREb6 z9`@N^Jc@mg=JnhU((AeZrS)9*uG5F$AHGFFntE=VWZ0ndwn?;`^U~|Jn-8Tt_o1|p z=a=w$(#P{l*oVtPz42beN=t*}Uc^e^7d^WVrM%V8@OmlFeX^nt8(S`moSE@GDAI;^ zYJzvF;ZfK(O4S?sU)`Ox*Kb}Lv>7u3`w4`_HDGmN?mYX_&c2WH1bH}cEW48oH-FVXpaA`x=}Ann(cdS$^5M%%iUGMe-z~eBEhml8`x#AWYkjny- z=u$VN2yAM_IzVN_dhXDH)z))s5f)_~u=Ws2C&>EtHDr5`$8tkvDTg9M*uUY>m~Khi z3a78MEsIRobNdA{giA5Q>Nr-N`zO|OhgMzBtsaS$DE87;-5AKWKyDLsR2wCJsYWkb;;Wz5OC$$ z@pRqyHL}um-$BMo7E@p6{pfVvcd)UNbstnBmv7o7)_u;3SFO}M1G%tLSUfJ)SI_cV zDeF1bYDyMnu#7ZZ^ma59gMroBBUqA8fweZNB@^+^G7(2DiQrOeQm`aKfVFyLu*8YL zS{MsP9Y!Z}-FK*13xCS{w(!u@nKcJU5!xf@tiw|G-V4y%Tja@e{IVFNErKVDLE(7< zEcIjoraVhn<#>QB1_jUxn-7$S>nYE2I7yJ@^^GF`Vw)tTp75le^Q2yrnWV{*XW=b+ zn{5|qTmlVVYY*~Tdl)wGG#5o5YptI2Avmb;q~0X9U26*nxt_#VsyyoH7*w5;r(^H| zj6qd;!hURX9|%o;=dfDRkRpGZAU(*?E4wB^PGdJ7zc1 z)J2X%%Z+C`@V2t}`P&%wOPcjo+n$ftlY>rg%{Td!M%>sw+LDG&Rky6?JUK$*izw2p z=Zm}wp81RG<&K+hP|L89rhIN+%7qN_7adzN+6+B(AcpKCk6Y`N}TbD2G*L~9E zYk3KF`!(^B#(D>!oh3;?NOky$S zbDP~rQ>QLp+ONMjPWrulH2d{2llvNU;PQzML_YPo{_K}DcoIB~=en2IMSU`h^+?+c zYU5mIP>g*YCkL`#1@8gjC3A{=R_;?@+kWc6{bjA#yFQ;tJ#X0jM~97!lbrK-pTG0i z{3g67_Aj&_G&40a0o; zHflPLC6Ba=AiRyor$-EWf4_+Dr@%K*t|fntZ&b`=mM18_pBlckQrBtVLyoZNwd9e; zmyq`Wrpe@yM&^XE{jW9Tk>+}+6HDZ>hz{>*T`M0wPv7@zVY$xl|2M;bo-J>YwSJkoe70DI!jBh3w#Yy|7c zCSEqeMG)S`@@Hpjr!z4@<;>U#lWKD z%4y)cA$X(>pT&B`hxtx6Iy2>MJU;!{RPQlGe7^!dS)1zLe7Sf{%??-R=Zh=w{mL-e z+^AT84}91P>1RGmTI^R-v(=SyQK!Xz!6PmBq&wCl?IH+o+qxY2f=6@SR5&zS>sWzx4v#47tWzQ|ZAxk6NKYPRKQZ1I@IC>$ZLy_vxuH`UTc)Q+ zJInrhH+iJ>OYixeNqp%YH2(b|G*iJd&1g9^ zLrHl(wlQAUG{Yf3vZxt^?BRLHzDTrQQ?t{SG31@KXB^e+ZCVhY@hJXR86;SW#o{C7XFBlvk!Tsv+PwYEVr6S9%<}!>`+s)t&KX;;wO-5Pu8p8ZAqS%Z|Tw} zygiMlZ8zGF7(l*N)D|Xy;rRqGlh;lIq_bK=Tj>b%IRTo;W6B?)q3=LjyOKv5dCdQV zwnmXh8i!q>)veAak2E#2LrWE&#Zl4B4p+ORtf#yd<7wNC){K7FsQ2+j&0y*no=+W^ z&(^F$zt=}P=d309TRLibQyPsuKASvZJn^GPFv5NV#9ttfw2Ux(XM72Hq_gaw$fmaI zM;>W>FZs7<+e#j38Fi4#+E(zcXFV;y-lb1?ON^&&H(Fczm9*a9E@}%CQJl8BgxB72 zene_#-5ilR)t1jqizuPSqealxZHcy&rf+R?0PBfwZF2x()(mLN*4(6_t^3jTKGq{m zZS8n-6`rjvMO!;!8WmgbnDTBmp0?d+ZRs}`dygt=>pEy_KM_Oz5OJixoi+y{KNW34)L#xk0E#}t7^EFYS`QoA5nuOJ~wOHb@`nlyhVUFOfDsV4lj8-=x2nFtVQN% zLH0PT6!%=; z<{}7h;{h@wJ-G<*_X2RBTulBP;ER!^Vn)j?h;@~Mvb=#b0IrU_fpnIAcoX(PF;=B5 zX@LGNqS%Gxkp}4RAQD|h9%%#pB6$k>MFXw8jR(zS^OPd!M+9`9ZO)O^kEk}Rx(Pd1 zw|&GwKSG{@2JbFp8K1$XkN_l&WC?e3Ke2>|v@Evd(yT|?yA$5VgJCZC-6EJj2$(z> zbTEkpQ!vQ(6~H12L>d4-2QZV!BMmTz#0~*z17ns^FtCj3u8Wpo`gUp&%pV0zp1Ix0(@Qo4v~w=p94%XhSXZm8$g>E72u`-_;_Roq_NINPUYDFX#-=~ zfr7!TulnrTtUr(m(P>36FA11DBf_derk3OhCV%E%$I(j!Q^t z+o`OICV#=HyZ@!ga>HT8>)_okzsA#Y@U%>LB}7gnuKg3uAsTjx@5|4iC`)>OKT_>) zFz%%9TrwHkPm3_VmSV4qPptTt02L{2FDzLJr2jNjK(h`rpdej0+jv^eTQPn+N^XhB znLb7Teq}xJ<~Ex$NwZ$N+-*F&ePx46Pr7S-l_y?NMCc@ko|pqgkI?l6x+`N#^h;PcgEvm=5p4=$gSKz=jYFwSNLZuKp~*`Q{)109hSN3pJsoS6TH6@ z!+8>bo?0aeVPJY{73;N6tin5xHW2<7I!GkG4PIEPsYGIcD;2b3;Schdu%4J zCjsxVndXb@tPkLjC&mSb%dEb*&U`Vc*M2#GOLj(y;t_3*n{2{in_LaQf_<=_cy<&_ZG{8J>ZeIfi)#1o0*C}#e^ z!#NQwkD^}Nt2pENu?+@q5wY7=M*M_9gtcl-{#L-6Ee)vl3h+2~k%C{f#+w*;EeG#H ziJ8_`Y4AiL=Tz3a<9_(v0`f>RF22!Bp2WpBn%Q>Mnhn}M1b;uz+A7U@Z7YkscH6$B z{8=XF&7c2}^++QDK0C$_Y5H;Miyh~n5AkEeA$}}AD={^#*M2_hdB1|aZ6$e>uY^;$ zA4~FI7q@p2Yhxqd8APfKEATe`cRr}S6Noe{t%ac4IkUg+A7U@{^~B48}Eh6dQHf}{N;3{ zv6=E2%okg+9%(G@PR6o(5_zQI+h0b#{^XH1-?kh=jeH6E72h_z>f4jex08C3LrA?e zhiH4-cyCJ|B^V*Y`!fL*LH+&yTo@#LhBMIU#LFX^co*lsc}dCFmB?=j4PTR9WnYnvR1zxF*^0_ zy8#|{Ou?@<+pJdGcsb+j^Vd)z5@(;k#uValRe&q<+Q~Ow3rCG1dc2`(#Jd4rJd-ySofy3FBH1yafp79}VzWp5Q zsgZ4->M(5T+n571ZYTBHK19EwaqCywwv9HP%GV9w9s+sl;&?~y+sW75+*4M4O5A=J z=DQ5)zCVFxPSRni8q29Z@=AzozAX~hzFhR}2l8|E3IYmyDLxZhMJ~8rR zXUzzAci&zY`7t)CbR8uz-~oWg4oZb@Tc}^Xj`dhh@GteKe!pA0yX&(Q*ya z%zHhSOWwP(jo0%&cpdWEa7#<%^M3Du&-=TANL#%VSEIwVn}^9sn>QQ>$O=Q>a#P9r}C9>0FTGA+fx@uc53!V|Hy4t432m#ETlgx#uVc* ztD^i=ly4s}R*dmB#?x}}kWQ@_BfJtKo6m~GwXcNFy2QgG9=pWTBWFGa@ei9>ZB-mJ zdDeF|wb~wU2CI3WtX1bkJhu5*!9y|fhVT_0qY+P5o#Ramyq3cs{s+ToE_tL)A=4}C z$#a{3!I35LJJOi*5x@OG2GWSf$Y=9-tTg)7{@K>+NzUQ90cqCrw|3<`zHbwKvz{7$x;cg6Wx3nM`jvP*mHP931ylQr z&${r%vG(Jt})NTl80lV{uAx#NXtHO@+2nCAX|Uc~4v&4v;e4hAU9mn$|8d#yT; zwpn$a)zfkVZ+i)B1Ajg)@olAXbMP$i9%Nh6^gF+v^JKql#cr%en)TY>ufnsx^eUh$=xIliG7ldVPQ$!uCg)AswhWT@r_}H_PV#BT38OA#O>FGS3+d-W0AOa zW%#j6oNNrc#P3EH@lDff@_Jr(+T>l0Z&2)x4a8v}MdHPpMr;eDuozU+GB_0$(pPx6oSh4mdDm<|+231fSl9fp4DPA~dr zvRCZZuCiCG{<#dIz#o0DSfN>Z#C>5e$FKOOrc5P7KCgbfywy+NYF7Jvh>X5vY1+O` zq(Z_HjU8T0g;*7tVm+eD8HtuLU9b&#EC=sWxsLG4iOe^r>iwbdMVWVuWC)%m4>`5Q zr$GFWii*4=M8?jLi!9IXv|jH`Ok^#`iCrWakDWvwX>3sJi_HhS8A4hfZbqQDiJvr| zOKH{9aOL2tg$APU+W#z~9T1bZTj-eLEM!X?mhK>a+9%)$U8?egF9+0}MVWVrG4%H=JAW#& z{YzpDS@NyuFka-D^{4)a;+_8;sp?HkWG&CK*+|?U{~>v#vuynK7+3SjBb{YauqgG& zM>@-XJO~y(n)OJd5A92MUgb)EO`OA zTcfS|7;3*6(6E8-Zva^Z8zJ)C z4XiQWtYHz2<-9%fD2_wQJS4Yj9>wsKEsjMmkVl$Z-2P;^KJh)?ETq>f2Ujhmi}=3< z+BYz!v7AnC-w6v#yK1-ZSQTmMW>~H*p~$+De%0HM$8zuxGCE!rUOACzA>AsOT$DMv zf%o6+Kb@P*LMrmz5P8c=k!5ZYn2Rqlk+mFS<*SH>`;bSPJpa&)@b3H=Q4gEJK88pW zF0a=exVrK_y9hVAr{i#wpq|2g0C2b404^L<;aX5Q z>D?WYw81SKz$Z?jadiQFPM}37x(17$bRSGua!;+wJ{YT_{E^rPleZkm0ZFzY43>kZ zWx^|Ap+w@^Rg_qQvP+!ogSo`X0ZA<8^tB7KVrvWuoFsvZ?~JG6uuu@zy55mv+2*Yx z#irLan3{akOM>IN-rmHJYPq~;4;w}{L`fTZ+ic}^@Z2&EZTrDT(pX(S8xOOP=A7}K z9YB*gd6TVtbx>N-z1OaW;W%O5ZRnoB(7aei6vCH(h@nSr5eB z3-{x`k#&CFfXd*8?_Bc-_^~~YqJG@h{J5{x({h6MLy2qypOCnXCqQKuB@KHY03VZl z7(CMEV-Hl}EhI0$-f!Zj#uZ9qT-<}_U_NF&()8oEEF}~_ehWsV?5yXq$T+&nW`5FH zcJ*=aT?uxOk2JCQho!`iCW^O&qquMDZpzf~ zZDjc3u<0R8VTqVk4q>t?e0v1UoD9*9dT&D&upB&rUG@;B`L;-0`(NSPE^%@Q(6I&CMf*%6#M+JD+Vf!MD|qRlaWcvF_?k4?jK#{YxxQ4r>ZaVtJLrnyd;_j)o~Ml~ic3KHHet zv>ZH%AXux?y{mA8YJxU+ViH!<*9jy&XE_^chmBy9>=Q(5n_pW$%w@#K-l9FIL3f0CLs z`p~{A+g|<v2~8+a`zct60&HprQO1mE79^+>}%5zF72O&)1n??QQ4 zi9FKur?ngOarxij@4sX{(imsAA=kKwJksd*k$6`lY0B5Ufc2cW@ICmk%#_F#NVDH& z8v_+QU)Lh2z0`va;CR)y7m(+Ds2|%}yxH0+Z#U|XeRRXOb=Ua3@a?Z-9M!{C$w5zH z?F?3xgPyF4@`F*nJyjsXQ4V^tjq$V`JS`Jm36agWb#MM3;oB~8a?sNyP7Zn=MuD38 z6dif*csL4ok|biZ>>X*!O0rf@idb%Wxq=^t>mCZgwhk5BtcEYkRaQ?j@LJA$w|>x5 z?%lpL*Az0nvfje|W8Fv^{(2F3Hd&J9LC^ewsk7sODeu?o$pd>Yu4f;lu{-<_Hsnq- zp3;yRvbWecV>#LtodLFOnuUUxx}d$^XUJO?{#dX{)|#eW){F??oNO zb)ap?^R{e5oi)mt{>R!Qmq&Ze@ zJ=WS@ggoY0wrx4M3U5GVTlqGD?-i1U&m)iUy+YE&;qO{jgU$y}f}~>;Ki-8ructmc zz=0z-br%m2Gg-lzt+M2u&_BFB=CJ(w= z+*a_|2fyX`%6;&K$Uo&O3oYMfIeo(S!Nn)!MFFai_f1K99r)sJkiTC>9%;l>xmj;( zMAGO3vA1;u>p4$;{e}r?)@wN?>MfcFJ$yOVlBCUNZ49W-Vho6UP4g<-%AUK&ZPM%` z$16sDpZfNFa9)Qzzn=Q>G1QgIM@-}qTM0*T-yR0J>waAH?PPDk7QAcmWz`Q6EUxDvf|l_V zPc*vtGH*kk93p7JYLR8aD<^Vt-|YON%;Vw^!SmMtCXo=;nRtS391jsxh`fn6F_AB! z$l`E*=!Uexko#XHVd(AXfoNX)W)a0Xap=Z1-%$O)z~XawV4%g$6RCC^3`T>&fF)W0 zfo0`IrshTFx}OwfJ|hkcxaK#DX*kvV89Xphq4~{Bk}PKCdFHFMBx?W%qeWly5&8WdftSJ}(Q<+P8}+5}$X?SMhm;0iVAW zYf|@l6$?JEFwEy!ZXzqMoU_p9MdrGn7G+L+-ZfwJc@-Hxf6K=kXdXVVBAd^%98;pC zzxRl+`y~_->$h4r2+Cu<6N&^TN6vtPiWl`KBi^bTLetY{yL^O4Enlh9a|^ z!?fu`;dMvzB6Hn^MVaFh&o%$aqaA6oltdf(=!!fb;3CVJ97&esG>9h;EXNZmkKscY zDzei&<-vO8U}&@%0u;4tiYQ)=IPaQYUp>w@y$l%e`=(uSDL95|e!Xel*32yTGO1Ti zWcs|wTz64X=J*D6uKDCW78XU+uP`L!V1I??5q(tiAK>bM!E$K(zo7ZI$s>(=ePTI7 z+N_~%%Ry6X=*G;tKqfgk#=)XDVjOsyzD@OUu;>jmfnzOdr^sTBmThQ_mTiou<+KKQ zS<7+S>Aw+R?Zy&m zemKJqe94D1G9RSYSO-xsJ{CPhkyVqJ57dA*AFv!_<2$g1j7E$X z(tOU-4;0IDp7Kc?UPJ1YgQnKdh3*G|Y&qn_*jV~;j16Hyv#ono9~(CrVbjIW&x_b*g^e6ra`r35HVd*~gj8VbYuN1U7t4VS z_ww)TFlP?7)<+vC7H~8B@d1Nlkw(w ziznX|FUFgEIM>IU$~E8c`u?hx!90Qx$E|1`q6oO5NgXLK^>rmja`!S@6 zqxAAI;)_g$b-yU$NETy`qd5604#dEpAO=?8*vxR)-s z5_9aw-g+SGk>=SRkDYS1M`9)4svM`M>4h?M=>TU4vZ~%xS|3F zVxr=(n8|Dxt zdo#uxCNzC=Bw1D^IakY@OdVUqyI}*_UXYl`Cge$K*)kN#`;URmVj^j;FZD{;EpTXF z@~a|_cVlchj$%wy#6T^J@d_M>iHgH~jpbad-)iGh7VEbP-aaw5NE^1YF)^@dUUGS0 z!?HG#jxdS^$2EP4Y>>*3z3cVmZdvSAl0s@<vhXUnr~cD#F5y@ zaU{88l3%sJMv`w-;OJ{OJa^P`*kU;TwGans*zK{vMjCC!ZZ@_^8{V?{WY|sfjVlB1 zf8xrBiOHwJYp|&$MrcaTteD+c6UE;{i`$4p##YlLZ(=+x=ksWOmQS8XlQXHTFZH@* zH_bP$D&pvfvE?|Da|bC78G56E<2MP8sfJ^!@wA)|n)yBahjx(-FvFqsx`jh?i-y2~ zO!Ebdf^;1HnL7|mcaJ&B{Es!!VrKZCY&b04-J1{x%dtW6Px$IR_vMwP`i#f$Ow0_I>JZ;E$M!)tMz<-qn7 z&M6Hb4$`Q1ZLG0L8#Zm*Eo_=^TpieCV*t{oYwTC(V5u$5Cs`Bm9(kd!LuIUpEoC@T z_g>Dpv1Bh|len>DFZ$&FfsHiZxTc6BSx-BTqKy>CEXau*umT5cq&Un*Ea$wn#MWRk zZ!N+2l9=cFAfydjSsRU;boR6v_2SWW3j!B1HkpaiTP?yuK3MHm3#+1hIm&mY;w8b8 zTPalm9>*LHZ1S5%(y*)qc%eNxhn$ z?N8zgFXUxxt8MV?4B~p*pQM`8n43?Iv$Uik7+U7b>0e>}$05Npy5|v}&v{Pwy#Dmy8Qt^I|Mh2=YMgc(KxoJ5 zE+IHvNA45kQRnUy!YdKWPM?0}nH(m+j$v{vr=;|iWnjssc(qrSNsMma22GGv`1`*k zMzcuf^0lYn^He!BAVA-8_19ZFIj|>Mb{lM zA|KpCjCbo1BaV{pDVC=Za;S3u}5{`I(G1K5xA5Ty283Kr0^cENu(HRz5M1=q`(*#wRUJ8SV{_A z3*8h_SdTAln@F)goZ@RR-oGVM_{@*qU)mN@AZos3(OMj7#Q<+3`oYTlS&WuuI@}7& zYS_lhO6yTqK??(cOPjhHau7vO#nqI5otKxCLe?m`+c$?S2Vg(wiVfWUK;u=Bg>}6g zvh=9=zjXV0b-CY$cqU4P+M@<7UQOUU7UrmlaG^;5<5wSTz2 z{&vIlDaWlLhxJ+E{9i}fv1@hbm;S~1W!uo5Uot0gezp-EVcPr;IzP+EV;e6kt;@m0 z@Vmg^@}};8u*p-!E=us{<*=T_K0{*}QKe#|ZY*{I%+G zH1F%>rS&n0a@-Sgc%O?BIgme!11x+jk;5Xq=%E==UL3ahE|CLu@o(Y7-iADJ@*5CP zSVkV((8+Jm`vRqOIhYvk3k)W2g>NB86AVpNd`tQ8EtZRHCFHPmn685Aejl=Uzo~yA z)zZGI_?PmbE0&j(WsD9uj{S#2lp{HfwOyQ;_8Z2#G%>9WIhp#}F81=WqF~7B6#Q7o zVSTpOByt?Ze%d#$E=N0DO5|zR_o$aJkIXA7#}grk_xaOAj-#!gUwn!jKlSp``WQqx zo(eg<&rcFLj=`MJ4*h>Fk;8_Z>fsZ}u@m%>i5y&Nv|($3ZOD7--*IbXu9uO=Hh9cJ z%Y;`-mxGDn>A>LfroM$+Vk%D+-%>t&i{&Nd;F69b?%5Eu=XZ4SMOwdj@l>t!0~2aZ{7yoPEsUo$&AU3unOFA% z51A@?y74k)+~~2V^4s0EHz(I^#p?NPJUO2n)f1L%vcxCp^G%lB<5{6z6o8G<;$~dr z%f?e0kL>&nTNam+M;f=EF2WYZbL5d`!vEgxm2GwVL&hM0lXj`d(`EkdXe)a^+IFLS zbL_Y=^%KvUI&Gih>IV-QRIf|Rj_`)3v(A>OS?BaMaiC0C1GCO^cPShwv#MF=;@Yfp z+J`DvXUo=7*V~ZCa`3cFcwLiq;#u`mXPh-=+}NS@QzlNGc-DBzZJ!oGR^RjLtn;Qf zs>(fm%{NDVTe_4#ZkKnqY>TQtf;>A*6De?-ayyTg%sLlN4}7Gv&f9*UbxvBywxqMp zJJ)8NXY)19M&o+gm(=ST=5t4%IdLpZHErCKvqsC_MqTpKUN_SR`LL<^W0oD#nst7d zoT1a`4++GeAHYhza}?PjH%V1*LKG~|Iv@B(AS0c1E;}^qyy!~SBMshuS?8~tji+?h zxnd5qwVpiES+>=`Wu49MDbMIE+v0?*^G|;xk93ypa$MHAb^&>$v+Qd>3?At$JNV+P z^ZmcF9%8I5{f#~~mAK@^Fh_F-}$?gI|9^~>_n?@=oK*kxbo z-W%ihZ@9?GEt79l)dtLi?6`- zTF4`f=Mn#c0BHO7q#4-OFJnCkSnHR$CWW`LreeSvd*-PFPhgR8}j;#BgHPIkrD}q%rV+mUVugZfZ2z zBCt*PsOy;Wz-GAYLp-uiAs{etC%h84JQ5!iGb586tH~ig{#D8=!+HFxS?6!}$U3La zAdfWVJ@+8;G$%4abrkXv-BaQL$M@%Qzl1G|2r|B5# z8m6!nalIa4TR>pEOgletxvd69*v7OY{xrQIpn6WAjZyp^T!dj(O)$N|n;3j8=UjiT znNQ~ZbEP+^W_knbrMz=xuTXLfl%I?4HJ?&m*WlBngVm(TYm(ihcZQp~NpFmyW;oTP zcfzFCZ(!0JDc7_cDJ#pf&if$u^skUdnjvt~-Q-C)oOCzZZi3v$b3mnum)GkW&M-5v z+WTx}c6Kw*%(3=#n?8`=)yY{;#4CtWGtY!*r@+j|5dvwL^j~5|@<GmHTX2&5H+8@_%k)%1-a*{ zHl*X7W0YE=qUO5*=6i7i^X+W1?ri4Ma+vR1FrP&p(x|rybg<5Jq_pWn+jb38n3TBe zsrb~SS&l0=>7Dr`nX{JX2N!C%fTlmlJU;zYbv=Ka*n_HIit^B=epP4m%qu$lp`IKRpQQ}WT9 zI`C`x=uJPDs@{b1vpnm(`ZbgtPaf&4^Tr>NTWZ*D!^diR=H9b{%k1RoDB? ztV5F$#S(YXAVzoj8=?y=SYlyO5D^d+ENBo>(I{d8ja?)Lu|$oA*gK+PBZ}A%r6fUY zV2oX3?+O|V>dyOr=X~e9duM0!n>Cr=Z<)h)%RB9!bMJlky|G8|#mpiExQ+5_X48e) zd^Cez2rt93k;}&D1QFcxD`|{eER`mHNU=zp`Fx6}<%TU}JvHeu!<)j~+Q>KK-CSq>{df*Jd} z6q7XS!J4Rv#uJ)C zE{$Aw%;VVDI5jOEu$X*_`%P%_Cd63It)aaq5|gc=y(e-NcKBFgvI;wVET@o1&Lt+( z#UtmUKkZkr|3*%(V4{}@xSW5>g0stcL{&&Sv7A_>-2hv~avo7dIggORfauI}$oV>C z8%K;Z$^#3p+2fXg%?*u-VJD%d2JX#)7)0W!(idW;k0=PHxQR=_NWOoJd(FV-WS7SI1a z#Bez;Ax@Dd z|34y5O+Iw|*hy0+b33o?jbYoRh_2q1uoDz7u^C*9c_Rd!CGY?7f>@z+vs#wimpV!UgZM5 zTQ*u)6D=?q9Ogm`Bj`bOVzVEXLm1TC|9LV_8bV|CGupB-X%j}<{wQHIowU6S=jeeE8M0xZAqKNMqxyHZ5*% zQy$X5I;F*(|H*o!)8c*b_B|}+l16&M4osGwlxBDzwoKaoC`D*qYC9_^0+~|Q>n$nb znKG-gCU>Dr6oEYmRm3wCMs}u$-NqYDgZ3sSH<||Rje3_NSGf|EHes~wj}k_cRNHVu zFPEoPV;7Yek0dqW%wW|hpbzVXVk9YdQ3>c1&h#c^oaIbX2k6S$X(lNTh?1lvAhHi> z`=f->?9?_K^UGm4PlJOE?-|CM3v*7ejEybUOpCu80AWrhUOgW}rl3#Yyx=+K{`mtNkG=?PMwq467wyDU$YXq|a7yF9}T#L=_u3sKVA;3 z+Q%P#lpUC$9EDuD9MMWcL<3WCYO@)X$^n;`{WxD~2w#%g*u><}a_*pKa$t4ha{S0t zr1mJ4Lq|^`ALPIsRJa?yRhS71B+4Be!b2p-@U2k18oXQlQ~eJ1CMJiLQ;s1Q5R*Fr zLoPr)vB%&aZ;w*Hq8w|L%Ms$Z1_sD6Y-r1J^aL*-m&!40DCHP7)a1}|`c)+1?fwTsabIrXsNqj3G1*1G{nO%3JZz$YTGqtmoAo4S4j<->6O&9h z409B6ZWZ{FqQL0h z9L@PHps*%d>=6Q^x)B1Sx{=Pky&N;am%|*Lw5j#S&Cy#(RFtEAxg1fVLZ(rlE#C@L zIp&~vNJv!b=15d*Lib=fXS5#RWkxFjp7o{P|B`TZ{#RH#$RWcY+KdyfObKO7l?O)F zMDfEx4smY@jBG+VSe_Qo9u(|B8uhgPkC&s=uP8_7aycTu^2k>1S1QL`@bYNzE9DEC zP&v%6SPnVhe{K)bCdYr_SEX|30>98D$RW`l)2=w-3M4t9JmIn?w_ZHq>aa(`WfR&% zwq}N%oEC5X8^XlL#7JA1_@5Il$*He95QBPvdt#6 z5zDzYbva~hDsr&?|7s7)QC%)aWDlPYmfJ(+fIZ|kk=sMZKI|cK_~M7?f?~Pf*dmOM2?SRn9oJaV;F0q#q*FO+B6xC@u9g11s6EAdVVKz%F7 zI+51!oYkA7z)oS{u5uyyoXKi2be7aglA32iExh7Dpz2Wp!gEHSzg-GVBUCdo)cT!4 zQD5hfiB%tmTEEAGLQqo-O=qp9>7mxSJQyEC@*vjVN?ARReZ{rTClt$g0sBgGq5BI3 zDisLcB2W0l4KET1SBzx5n6=`*+%KZ;aTH!;jB5=P1Gw$*Jr92$64SSptV7#;u@12} z@sxeBK)n<>@lcNvOib8q;+qbb=|>NRDyBqmP^2qsTCG)*VA5^o0+o@q_TSWo&3^{4~E zTwduf&ACDS8kCI|B_@wYiLPi;$HbO`$+u(dPwJ&PVqy=uhK_c_u@An(HKZDJPa020Jeee2xhHFMnl8L2U|w$x+IHpUbV@o+zdAZeIx;954LKmA z^X&DC80;IY;B`q$y&$ji_v$Jk%nwn;a4urCrJZ?+-`HP_h!#fk2HKkeT4my zS6p}3H2sb{wnmd@w>Bff-9A^E z*Y$eN-{<+>s*yg>J==aw=h9)uewDSfZuL;8!scw+8`Ec z@-QssulPOd39rTP$zO(TLjIO)4ksPq^@Nss0V|Fsf5n63TC7JJIFd((jb?vExMGb3 zY|>IM!lM417wJ#<)1+lQfBtv;UuITFm|l;x+nT)4&0)v&@b^o@lupxsx5cZ}>WPs? zLYWDk*C$3A|Htbv*1SiIG_I+9me%{|GX#=dyf8koGVWiPw~dp86VXEg+JH z-PER~*Z68C-cE-}hy-HN!XE;}eZ)u$f1+<<-XCpWiam@v9cK|EjYk`cp+C~Fx%va^ zxon@^7-S<2-K$+nud(bs;Fds1^L3e@An}VF^194Vo}|31e?!c9dFmY`{p+khrKO(B z)pAOGOZNngK2t8+vGU6h1Z<5yjV_b#5EB%S`a%aF$UK5`}b*lLB9(dcog)N;1O z;7$lVY$cVwJWXGNxxYraV5IS?1HIj*WXC_JKGrbWpmZ#|}r$MMaiIGmz zzubrC^&cQc8jrOuNz)%z6C;gRj$RT3C5>z7wWMAJL7BIrCq2QSSfnLEcZZ-lmZjge z@{iZW_lC^`MIut|>~8h6JWU_pCr!WAmk~LQ_sx6(;mvtT%k#UiD6}irAT7TQ4MDFY zM%n~DU$6>-@>EsyIOSPlQF!??1G81cpA!{F_hDjQ^{2IsB!^DLxASvOoY|7*(vz8 zFf9UfX>S4`oT;E%F75{bt|vws0(=I4-;5Y(`H`E*DoRtRF72gW1)+E<%ATkbp|IXx zCHb%gp$>#ldX`oC&4LGoT7}bZE|g4mJ7JSRt#Y7LMxR;^m%~_ep-5v9upg{4pY=#H zKD(<)d~T2F9Q&1e6@=pHD0|LKgaR`nRL#h8OC18C8l+G8L_*1Gan&^t>INyWiz6bc zP=^p>IfOa@LhV6}G=#$cJ6=kRv^-A_YwK8X+WVDy6@=0|Np0;(D-jAa0~M-;@pA-( z>L-25CkqrZ*3jl*2xa3(G};+UTNUaEsqEzt>fkVbNT=yV$jrW6Bb}x8`SQl*&`u!CwDk#>K zD(Ep%*~=07kBvgV(rNnCUBGM#LK+su*z$--+Ju4hhUXN;A9~>!0#elSZ;*hiwN0lAr=8k&o@tp2#8uPLY9MmPmJXd z0snWOCoN+GA|RJZThbJvRr#i#(|~`6iJdIAPi@%>7l;VW=K-vYM!ybL(CMmYoD0Yr z%faGrF_gbDc9q7ftZ;6_EkoL-rqiTeB`a_u@O8NeEm#3F?g3>pZWTc`0LBF?s0deC zgo5L!Wwe}Q;X9kQ$XNJpC}!OMfMslvPMRXLw?wKl?)fH`&eki5#i_uzK`g}2=P-w8 zX@YjSh}C>9z{+TJUC1!PMwVeNr&uh<&knqmB;7U8ISsMi!`jcX6KPpHg$WL6iq)!Y zQqRf2cjaO|Up{886|u6}Ko+^6gXbaEtY%^%B56Lk*2L0sh=Q4OCYI80xDIH$1M87C z5j4V8vJ6vyI5V4I<4F=iOOfkl5h2U{nFvxDm;9u3%w(&fo5>o>A%d*(Z9Yv}94=%J z(k4P{vPV6WdUSx+MQCBn+%6(yS>2{DDlf*&%Fj#3OlL%JwZiQtf|lb&u^-DgAx0X} zYC=ZGnvG#S(r`FLJ)eA%Hc>U|RkD_*dQ5k7GIxyh` z?>X=^!@9U4QhmwN6_TE$jlRY^F&XT7scEw@L!d_3fh5wJyQh zB|}D;!J0I@mLYPt;@Xe^xxDFD%Af=K{7NPJ^CB*47bvkYlS&^=@s(k8(P(zb#P zdTXw47oDrc_KQT_H2gkdwkd+eW@Af9M(+8@uXy>Mh_2PvHwkQTuslugfuvtA6waK+ zTJ3=lp-EGMF1k-rNdn%MZWFx7C1_z=2dmA-Y_(}NP-(IGw{*i&2|8mAriQcCCd<=w zF6LHW-%ANdLxMXXfz10L6=}1>IYvJp9BITjtmL);~e8RMZyCzkw4qd&~oJGCYw_SQt-u0y#5W6H+?){%`_ z=D_qq^S4Ml23N$KwYttQx%x>a0b-BV({gZoEcBfcBW>KCBv>VVYyNK6F>oul6R?fm zQry7;u`x>$ZFoi2Mg3VJ?&!J+c~13h3q+Rlb(X%9B(Jml_Ez}*&G4ev*dJ*~1^an? zB2B3}wBVBxmh%wSoQ+}484XHFMClMT ztRico@GhQ+&LYNg5f$#c4>8g(YG1hToy15(ECf`a3X!H*txHavAVeoLU91+86V{=P z_1QW!77N)a9Z@P)mYpyIlgP+&@l}X*hKZ%L_$tIQKPL^bdO)o8S&y_?t2G&`4`&TO z4c58@dllG=Z)w(mwP|Bmo0?dxj7AR!v2%C?I2RUdjV&zLARCX zoy~}m=5D{QDCI7I-_Gc)8Lc&f$^5<$y+OhSd#NO4Dv#9=ESnr;OEL)b5(F#a8=Da# zm_`t61hSD~S`MFo4^ha5Flmevh%+GEce5nn+lFC<7zAhN^{#WOS(who^(5(+*&DQ5EjBq z8j^>Y0_u(`4@TRF6f(y36Xk%qqtNKfB&mH^N=%QKm#FMI%Do(sXAi`C__Wj`jr}d; zi8jiy)82>Ft7HrOM1vkfFKo(m3}&(d>k(r{c0h@r|_a!*4c<8<3Q!cBu?nuyYJMCt&@mi1oAe!@NI;#$EHQ zCz$jn)@W!;Ob)9`f7B{5Ih0xZDJ7}}KkAae8Zk8#DI2eguuToyl$i7<^`t+qCzwog zsM^rB`Z>0(elEf!^y3YTG)NS=mtS5S|zKJ?@jJAOsxR$pi4NPS$y{@dewwOqaH0#wJRf;{0d1-e| zO&GpPL*A>BWV4T1k2El~OKDr$uN0GO?Q9{OG_ULSa2?2oov4uJS`2HR zutRDVV_metkd4h~BHBiNR-Sq$^q)(O@J z^$K^E3s$=3Q69182^*poqg1e$AQ&cZC2Jmc#cDFga=B%gBpc?4k;cUEX}H}aVx-{# z7?Yij6Rb7X(KXLqK?v-S%R!QsHeayj345KHb)>Ewdo10|=!68Wl6NO_EQfW@4&#Y5 zEU{zQ*CY+W{vP%!7>K1#4lO2J4_`Ycn$sB*T>Btv<~pbHCfdB-3(A z;ZZ@Pkf^Zi?;$FXHYr-|WBqWE!aYF>>#Asj(`=^F!t+)k#*|2lh_BMxx{Bp^j_RFYAJTjluFV8WE6@M5nP5`r zbf`5$O4n6?2{yY0i?b^*##;z@SXV_S-qmJaSypr*;>n=ye2z(>>nbl#)7KI4)<2OP zlTOo@U&Q@`^@x#{(@+>^%ZQPN&Ax@EFd3C}LE5A}N3crL9_s6_%_%J|n7=$pHmQXP zCWQ6ZDDaBaZu|i2XoIF@ON?Y+Lh+-i`z6W7?}EYT@!S0g#eKnL<@uG`1!4W=(BiQE zx)g%_4Nn>!8LoI4VjXykpQ6Q9jX<@NLamvEqSa7>04Z0DA4JAHM7m!!F*KA!hrZ(V zmqb@A6Ji#?nfmSTojBbO6HuxYDqKMIM18M76`yKqr zNle6z)_P`-7;}5LUDxjruHm%XO0E%Ov{Aq|#DcA1XQ_pWh0z@j!2;(cVx;kq)72Od zT?BI)*W4P5JWM_WBMrU6R<(p0Rycgp!7Dz`xwrV$6Nb`=ig5Uw4%)h@I#6yF+%H^OKhN z>b7(mzNS7W{UwR(x6RqEQ}}_=?uVjNzlNSIu9uc}=C~el8v64G-d?9vFs>RGnd2Cfrfb0s<>GJO+ae_`9&HzN%5Ypoaaav!n2r$_bX8TNgI zJwhAZ^+v$*I}y7(vQd8LBzg4oBzMoJQ9Z091)KX}gdsv|y-5M9LcRN&;Fae@*uW&2 z_f<1&*Ce?Dk8PFIn~>z6T9c+{KN+<}R=pT+04%8oAG#kA8`FY4hBmsBBb>-*Btpfv zU%^4Q#&ABBSQn(1rZqk=46|}C6IAHpNvtQ|ibeG@OzO!sFwo??te#=c%f^oeUN&A1 zUci@5DU3fa_cG~EY4EJ|@U58j<7I-4+%idetN<@aO?46?@aeJx=&`~dzZJ7`F9Vi8 zVRf2LTN@65h1F_mh4(X5O_|~$}w#REMt2@~0p}clH+t#WM zyqs+_4E5^9vYzP2uTgg}>pAB96|sTh{1u_g>LIY>aq`W!EC;4##6$*QiJD#SVm0r{Owo3>TsRkT0NwTqF|%s+uKUHv<;ZI{T#PRyzS>m z)y0z}ILJ5KvK*L}2}ZwKe?I-H#oy{puq>*Fgrx!e(iZ9&Cj7}YmUKiPm$BXw>{|~MY+Ly@Ov{0388O$(=h%05y?l